From f0724f0704299b49d42a48099b97c4cf0a55b155 Mon Sep 17 00:00:00 2001 From: Paul Kirth Date: Fri, 5 Apr 2024 09:41:53 -0700 Subject: [PATCH 001/695] [llvm][NFC] Update URL in comment about Android ABI The previous URL was stale, and referenced 'master' instead of 'main', which will never be updated. Reviewers: topperc, enh-google Reviewed By: enh-google Pull Request: https://github.com/llvm/llvm-project/pull/87726 --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 8218960406ec..b81688c35713 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -26025,7 +26025,7 @@ static Value *UseTlsOffset(IRBuilderBase &IRB, unsigned Offset) { Value *AArch64TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const { // Android provides a fixed TLS slot for the stack cookie. See the definition // of TLS_SLOT_STACK_GUARD in - // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h + // https://android.googlesource.com/platform/bionic/+/main/libc/platform/bionic/tls_defines.h if (Subtarget->isTargetAndroid()) return UseTlsOffset(IRB, 0x28); -- GitLab From 345c4822e4db2aa734b9f8a0b106308288ddc702 Mon Sep 17 00:00:00 2001 From: Eric Li Date: Fri, 5 Apr 2024 13:00:01 -0400 Subject: [PATCH 002/695] [libTooling] Fix `getFileRangeForEdit` for inner nested template types (#87673) When there is `>>` in source from the right brackets of a nested template, the end location of the inner template points into a scratch space with a single `>` token. This prevents the lexer from seeing the `>>` token in the original source. However, this causes the range to appear to be partially in a macro, and is problematic if we are trying to avoid ranges with any macro expansions. This change detects these split tokens in token ranges, converting it to the corresponding character range without the expansion. --- clang/lib/Tooling/Transformer/SourceCode.cpp | 59 +++++++++++++++++-- clang/unittests/Tooling/SourceCodeTest.cpp | 60 ++++++++++++++++++++ 2 files changed, 114 insertions(+), 5 deletions(-) diff --git a/clang/lib/Tooling/Transformer/SourceCode.cpp b/clang/lib/Tooling/Transformer/SourceCode.cpp index 6aae834b0db5..ab7184c2c069 100644 --- a/clang/lib/Tooling/Transformer/SourceCode.cpp +++ b/clang/lib/Tooling/Transformer/SourceCode.cpp @@ -101,6 +101,54 @@ static bool spelledInMacroDefinition(SourceLocation Loc, return false; } +// Returns the expansion char-range of `Loc` if `Loc` is a split token. For +// example, `>>` in nested templates needs the first `>` to be split, otherwise +// the `SourceLocation` of the token would lex as `>>` instead of `>`. +static std::optional +getExpansionForSplitToken(SourceLocation Loc, const SourceManager &SM, + const LangOptions &LangOpts) { + if (Loc.isMacroID()) { + bool Invalid = false; + auto &SLoc = SM.getSLocEntry(SM.getFileID(Loc), &Invalid); + if (Invalid) + return std::nullopt; + if (auto &Expansion = SLoc.getExpansion(); + !Expansion.isExpansionTokenRange()) { + // A char-range expansion is only used where a token-range would be + // incorrect, and so identifies this as a split token (and importantly, + // not as a macro). + return Expansion.getExpansionLocRange(); + } + } + return std::nullopt; +} + +// If `Range` covers a split token, returns the expansion range, otherwise +// returns `Range`. +static CharSourceRange getRangeForSplitTokens(CharSourceRange Range, + const SourceManager &SM, + const LangOptions &LangOpts) { + if (Range.isTokenRange()) { + auto BeginToken = getExpansionForSplitToken(Range.getBegin(), SM, LangOpts); + auto EndToken = getExpansionForSplitToken(Range.getEnd(), SM, LangOpts); + if (EndToken) { + SourceLocation BeginLoc = + BeginToken ? BeginToken->getBegin() : Range.getBegin(); + // We can't use the expansion location with a token-range, because that + // will incorrectly lex the end token, so use a char-range that ends at + // the split. + return CharSourceRange::getCharRange(BeginLoc, EndToken->getEnd()); + } else if (BeginToken) { + // Since the end token is not split, the whole range covers the split, so + // the only adjustment we make is to use the expansion location of the + // begin token. + return CharSourceRange::getTokenRange(BeginToken->getBegin(), + Range.getEnd()); + } + } + return Range; +} + static CharSourceRange getRange(const CharSourceRange &EditRange, const SourceManager &SM, const LangOptions &LangOpts, @@ -109,13 +157,14 @@ static CharSourceRange getRange(const CharSourceRange &EditRange, if (IncludeMacroExpansion) { Range = Lexer::makeFileCharRange(EditRange, SM, LangOpts); } else { - if (spelledInMacroDefinition(EditRange.getBegin(), SM) || - spelledInMacroDefinition(EditRange.getEnd(), SM)) + auto AdjustedRange = getRangeForSplitTokens(EditRange, SM, LangOpts); + if (spelledInMacroDefinition(AdjustedRange.getBegin(), SM) || + spelledInMacroDefinition(AdjustedRange.getEnd(), SM)) return {}; - auto B = SM.getSpellingLoc(EditRange.getBegin()); - auto E = SM.getSpellingLoc(EditRange.getEnd()); - if (EditRange.isTokenRange()) + auto B = SM.getSpellingLoc(AdjustedRange.getBegin()); + auto E = SM.getSpellingLoc(AdjustedRange.getEnd()); + if (AdjustedRange.isTokenRange()) E = Lexer::getLocForEndOfToken(E, 0, SM, LangOpts); Range = CharSourceRange::getCharRange(B, E); } diff --git a/clang/unittests/Tooling/SourceCodeTest.cpp b/clang/unittests/Tooling/SourceCodeTest.cpp index 3641d2ee453f..3c24b6220a22 100644 --- a/clang/unittests/Tooling/SourceCodeTest.cpp +++ b/clang/unittests/Tooling/SourceCodeTest.cpp @@ -8,6 +8,7 @@ #include "clang/Tooling/Transformer/SourceCode.h" #include "TestVisitor.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/SourceLocation.h" #include "clang/Lex/Lexer.h" @@ -18,10 +19,12 @@ #include using namespace clang; +using namespace clang::ast_matchers; using llvm::Failed; using llvm::Succeeded; using llvm::ValueIs; +using testing::Optional; using tooling::getAssociatedRange; using tooling::getExtendedRange; using tooling::getExtendedText; @@ -50,6 +53,15 @@ struct CallsVisitor : TestVisitor { std::function OnCall; }; +struct TypeLocVisitor : TestVisitor { + bool VisitTypeLoc(TypeLoc TL) { + OnTypeLoc(TL, Context); + return true; + } + + std::function OnTypeLoc; +}; + // Equality matcher for `clang::CharSourceRange`, which lacks `operator==`. MATCHER_P(EqualsRange, R, "") { return arg.isTokenRange() == R.isTokenRange() && @@ -510,6 +522,54 @@ int c = M3(3); Visitor.runOver(Code.code()); } +TEST(SourceCodeTest, InnerNestedTemplate) { + llvm::Annotations Code(R"cpp( + template + struct A {}; + template + struct B {}; + template + struct C {}; + + void f(A$r[[>>]]); + )cpp"); + + TypeLocVisitor Visitor; + Visitor.OnTypeLoc = [&](TypeLoc TL, ASTContext *Context) { + if (TL.getSourceRange().isInvalid()) + return; + + // There are no macros, so every TypeLoc's range should be valid. + auto Range = CharSourceRange::getTokenRange(TL.getSourceRange()); + auto LastTokenRange = CharSourceRange::getTokenRange(TL.getEndLoc()); + EXPECT_TRUE(getFileRangeForEdit(Range, *Context, + /*IncludeMacroExpansion=*/false)) + << TL.getSourceRange().printToString(Context->getSourceManager()); + EXPECT_TRUE(getFileRangeForEdit(LastTokenRange, *Context, + /*IncludeMacroExpansion=*/false)) + << TL.getEndLoc().printToString(Context->getSourceManager()); + + if (auto matches = match( + templateSpecializationTypeLoc( + loc(templateSpecializationType( + hasDeclaration(cxxRecordDecl(hasName("A"))))), + hasTemplateArgumentLoc( + 0, templateArgumentLoc(hasTypeLoc(typeLoc().bind("b"))))), + TL, *Context); + !matches.empty()) { + // A range where the start token is split, but the end token is not. + auto OuterTL = TL; + auto MiddleTL = *matches[0].getNodeAs("b"); + EXPECT_THAT( + getFileRangeForEdit(CharSourceRange::getTokenRange( + MiddleTL.getEndLoc(), OuterTL.getEndLoc()), + *Context, /*IncludeMacroExpansion=*/false), + Optional(EqualsAnnotatedRange(Context, Code.range("r")))); + } + }; + Visitor.runOver(Code.code(), TypeLocVisitor::Lang_CXX11); +} + TEST_P(GetFileRangeForEditTest, EditPartialMacroExpansionShouldFail) { std::string Code = R"cpp( #define BAR 10+ -- GitLab From 68b939f9311aaacd4a4fb6e41f86d81857d5c86e Mon Sep 17 00:00:00 2001 From: Cassie Jones Date: Fri, 5 Apr 2024 13:01:09 -0400 Subject: [PATCH 003/695] [driver] Make --version show if assertions, etc. are enabled (#87585) It's useful to have some significant build options visible in the version when investigating problems with a specific compiler artifact. This makes it easy to see if assertions, expensive checks, sanitizers, etc. are enabled when checking a compiler version. Example config line output: Build configuration: +unoptimized, +assertions, +asan, +ubsan --- clang/lib/Driver/Driver.cpp | 6 +++ clang/test/Driver/version-build-config.test | 6 +++ llvm/CMakeLists.txt | 3 ++ llvm/include/llvm/Config/config.h.cmake | 3 ++ llvm/include/llvm/Support/CommandLine.h | 10 +++++ llvm/lib/Support/CommandLine.cpp | 46 +++++++++++++++++++++ 6 files changed, 74 insertions(+) create mode 100644 clang/test/Driver/version-build-config.test diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index e6c1767a0082..e7335a61b10c 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -2003,6 +2003,12 @@ void Driver::PrintVersion(const Compilation &C, raw_ostream &OS) const { // Print out the install directory. OS << "InstalledDir: " << Dir << '\n'; + // Print the build config if it's non-default. + // Intended to help LLVM developers understand the configs of compilers + // they're investigating. + if (!llvm::cl::getCompilerBuildConfig().empty()) + llvm::cl::printBuildConfig(OS); + // If configuration files were used, print their paths. for (auto ConfigFile : ConfigFiles) OS << "Configuration file: " << ConfigFile << '\n'; diff --git a/clang/test/Driver/version-build-config.test b/clang/test/Driver/version-build-config.test new file mode 100644 index 000000000000..4cedf1e63181 --- /dev/null +++ b/clang/test/Driver/version-build-config.test @@ -0,0 +1,6 @@ +# REQUIRES: asserts +# RUN: %clang --version 2>&1 | FileCheck %s + +# CHECK: clang version +# When assertions are enabled, we should have a build configuration line that reflects that +# CHECK: Build config: {{.*}}+assertions diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 6f5647d70d8b..88cf2d7ff099 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -799,6 +799,9 @@ option (LLVM_BUILD_EXTERNAL_COMPILER_RT option (LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO "Show target and host info when tools are invoked with --version." ON) +option(LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG + "Show the optional build config flags when tools are invoked with --version." ON) + # You can configure which libraries from LLVM you want to include in the # shared library by setting LLVM_DYLIB_COMPONENTS to a semi-colon delimited # list of LLVM components. All component names handled by llvm-config are valid. diff --git a/llvm/include/llvm/Config/config.h.cmake b/llvm/include/llvm/Config/config.h.cmake index fc1f9bf342f8..977c182e9d2b 100644 --- a/llvm/include/llvm/Config/config.h.cmake +++ b/llvm/include/llvm/Config/config.h.cmake @@ -290,6 +290,9 @@ /* Whether tools show host and target info when invoked with --version */ #cmakedefine01 LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO +/* Whether tools show optional build config flags when invoked with --version */ +#cmakedefine01 LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG + /* Define if libxml2 is supported on this platform. */ #cmakedefine LLVM_ENABLE_LIBXML2 ${LLVM_ENABLE_LIBXML2} diff --git a/llvm/include/llvm/Support/CommandLine.h b/llvm/include/llvm/Support/CommandLine.h index 99dc9aefbd7d..b035209406b6 100644 --- a/llvm/include/llvm/Support/CommandLine.h +++ b/llvm/include/llvm/Support/CommandLine.h @@ -2002,6 +2002,16 @@ void PrintVersionMessage(); /// \param Categorized if true print options in categories void PrintHelpMessage(bool Hidden = false, bool Categorized = false); +/// An array of optional enabled settings in the LLVM build configuration, +/// which may be of interest to compiler developers. For example, includes +/// "+assertions" if assertions are enabled. Used by printBuildConfig. +ArrayRef getCompilerBuildConfig(); + +/// Prints the compiler build configuration. +/// Designed for compiler developers, not compiler end-users. +/// Intended to be used in --version output when enabled. +void printBuildConfig(raw_ostream &OS); + //===----------------------------------------------------------------------===// // Public interface for accessing registered options. // diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index c076ae8b8431..056340bbab5a 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -2734,6 +2734,52 @@ void cl::PrintHelpMessage(bool Hidden, bool Categorized) { CommonOptions->CategorizedHiddenPrinter.printHelp(); } +ArrayRef cl::getCompilerBuildConfig() { + static const StringRef Config[] = { + // Placeholder to ensure the array always has elements, since it's an + // error to have a zero-sized array. Slice this off before returning. + "", + // Actual compiler build config feature list: +#if LLVM_IS_DEBUG_BUILD + "+unoptimized", +#endif +#ifndef NDEBUG + "+assertions", +#endif +#ifdef EXPENSIVE_CHECKS + "+expensive-checks", +#endif +#if __has_feature(address_sanitizer) + "+asan", +#endif +#if __has_feature(dataflow_sanitizer) + "+dfsan", +#endif +#if __has_feature(hwaddress_sanitizer) + "+hwasan", +#endif +#if __has_feature(memory_sanitizer) + "+msan", +#endif +#if __has_feature(thread_sanitizer) + "+tsan", +#endif +#if __has_feature(undefined_behavior_sanitizer) + "+ubsan", +#endif + }; + return ArrayRef(Config).drop_front(1); +} + +// Utility function for printing the build config. +void cl::printBuildConfig(raw_ostream &OS) { +#if LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG + OS << "Build config: "; + llvm::interleaveComma(cl::getCompilerBuildConfig(), OS); + OS << '\n'; +#endif +} + /// Utility function for printing version number. void cl::PrintVersionMessage() { CommonOptions->VersionPrinterInstance.print(CommonOptions->ExtraVersionPrinters); -- GitLab From b7593b2e925fc005fc6248cd8e1a3f019e124c6b Mon Sep 17 00:00:00 2001 From: Jakub Chlanda Date: Fri, 5 Apr 2024 19:05:19 +0200 Subject: [PATCH 004/695] [NFC][Doc] Fix typo in new pass manager snippet (#87765) Add missing closing parenthesis and re-flow the snippet to what clang format would generate. --- llvm/docs/NewPassManager.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/docs/NewPassManager.rst b/llvm/docs/NewPassManager.rst index 4554d8004375..b75ab918fda0 100644 --- a/llvm/docs/NewPassManager.rst +++ b/llvm/docs/NewPassManager.rst @@ -162,10 +162,10 @@ certain parts of the pipeline. For example, .. code-block:: c++ PassBuilder PB; - PB.registerPipelineStartEPCallback([&](ModulePassManager &MPM, - PassBuilder::OptimizationLevel Level) { - MPM.addPass(FooPass()); - }; + PB.registerPipelineStartEPCallback( + [&](ModulePassManager &MPM, PassBuilder::OptimizationLevel Level) { + MPM.addPass(FooPass()); + }); will add ``FooPass`` near the very beginning of the pipeline for pass managers created by that ``PassBuilder``. See the documentation for -- GitLab From 30f6eafaa978b4e0211368976fe60f15fa9f0067 Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Fri, 5 Apr 2024 10:06:44 -0700 Subject: [PATCH 005/695] [OpenACC][NFC] Add OpenACC Clause AST Nodes/infrastructure (#87675) As a first step in adding clause support for OpenACC to Semantic Analysis, this patch adds the 'base' AST nodes required for clauses. This patch has no functional effect at the moment, but followup patches will add the semantic analysis of clauses (plus individual clauses). --- clang/include/clang/AST/ASTNodeTraverser.h | 13 ++ clang/include/clang/AST/JSONNodeDumper.h | 1 + clang/include/clang/AST/OpenACCClause.h | 135 ++++++++++++++++++ clang/include/clang/AST/RecursiveASTVisitor.h | 13 +- clang/include/clang/AST/StmtOpenACC.h | 55 +++++-- clang/include/clang/AST/TextNodeDumper.h | 2 + .../clang/Serialization/ASTRecordReader.h | 7 + .../clang/Serialization/ASTRecordWriter.h | 7 + clang/lib/AST/CMakeLists.txt | 1 + clang/lib/AST/JSONNodeDumper.cpp | 2 + clang/lib/AST/OpenACCClause.cpp | 17 +++ clang/lib/AST/StmtOpenACC.cpp | 19 +-- clang/lib/AST/StmtPrinter.cpp | 8 +- clang/lib/AST/StmtProfile.cpp | 21 ++- clang/lib/AST/TextNodeDumper.cpp | 23 ++- clang/lib/Sema/SemaOpenACC.cpp | 2 + clang/lib/Serialization/ASTReader.cpp | 65 +++++++++ clang/lib/Serialization/ASTReaderStmt.cpp | 10 +- clang/lib/Serialization/ASTWriter.cpp | 62 ++++++++ clang/lib/Serialization/ASTWriterStmt.cpp | 3 +- 20 files changed, 439 insertions(+), 27 deletions(-) create mode 100644 clang/include/clang/AST/OpenACCClause.h create mode 100644 clang/lib/AST/OpenACCClause.cpp diff --git a/clang/include/clang/AST/ASTNodeTraverser.h b/clang/include/clang/AST/ASTNodeTraverser.h index 06d67e9cba95..94e7dd817809 100644 --- a/clang/include/clang/AST/ASTNodeTraverser.h +++ b/clang/include/clang/AST/ASTNodeTraverser.h @@ -53,6 +53,7 @@ struct { void Visit(TypeLoc); void Visit(const Decl *D); void Visit(const CXXCtorInitializer *Init); + void Visit(const OpenACCClause *C); void Visit(const OMPClause *C); void Visit(const BlockDecl::Capture &C); void Visit(const GenericSelectionExpr::ConstAssociation &A); @@ -239,6 +240,13 @@ public: }); } + void Visit(const OpenACCClause *C) { + getNodeDelegate().AddChild([=] { + getNodeDelegate().Visit(C); + // TODO OpenACC: Switch on clauses that have children, and add them. + }); + } + void Visit(const OMPClause *C) { getNodeDelegate().AddChild([=] { getNodeDelegate().Visit(C); @@ -799,6 +807,11 @@ public: Visit(C); } + void VisitOpenACCConstructStmt(const OpenACCConstructStmt *Node) { + for (const auto *C : Node->clauses()) + Visit(C); + } + void VisitInitListExpr(const InitListExpr *ILE) { if (auto *Filler = ILE->getArrayFiller()) { Visit(Filler, "array_filler"); diff --git a/clang/include/clang/AST/JSONNodeDumper.h b/clang/include/clang/AST/JSONNodeDumper.h index dde70dde2fa2..7a60f362650c 100644 --- a/clang/include/clang/AST/JSONNodeDumper.h +++ b/clang/include/clang/AST/JSONNodeDumper.h @@ -203,6 +203,7 @@ public: void Visit(const TemplateArgument &TA, SourceRange R = {}, const Decl *From = nullptr, StringRef Label = {}); void Visit(const CXXCtorInitializer *Init); + void Visit(const OpenACCClause *C); void Visit(const OMPClause *C); void Visit(const BlockDecl::Capture &C); void Visit(const GenericSelectionExpr::ConstAssociation &A); diff --git a/clang/include/clang/AST/OpenACCClause.h b/clang/include/clang/AST/OpenACCClause.h new file mode 100644 index 000000000000..06a0098bbda4 --- /dev/null +++ b/clang/include/clang/AST/OpenACCClause.h @@ -0,0 +1,135 @@ +//===- OpenACCClause.h - Classes for OpenACC clauses ------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// \file +// This file defines OpenACC AST classes for clauses. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_AST_OPENACCCLAUSE_H +#define LLVM_CLANG_AST_OPENACCCLAUSE_H +#include "clang/AST/ASTContext.h" +#include "clang/Basic/OpenACCKinds.h" + +namespace clang { +/// This is the base type for all OpenACC Clauses. +class OpenACCClause { + OpenACCClauseKind Kind; + SourceRange Location; + +protected: + OpenACCClause(OpenACCClauseKind K, SourceLocation BeginLoc, + SourceLocation EndLoc) + : Kind(K), Location(BeginLoc, EndLoc) {} + +public: + OpenACCClauseKind getClauseKind() const { return Kind; } + SourceLocation getBeginLoc() const { return Location.getBegin(); } + SourceLocation getEndLoc() const { return Location.getEnd(); } + + static bool classof(const OpenACCClause *) { return true; } + + virtual ~OpenACCClause() = default; +}; + +/// Represents a clause that has a list of parameters. +class OpenACCClauseWithParams : public OpenACCClause { + /// Location of the '('. + SourceLocation LParenLoc; + +protected: + OpenACCClauseWithParams(OpenACCClauseKind K, SourceLocation BeginLoc, + SourceLocation LParenLoc, SourceLocation EndLoc) + : OpenACCClause(K, BeginLoc, EndLoc), LParenLoc(LParenLoc) {} + +public: + SourceLocation getLParenLoc() const { return LParenLoc; } +}; + +template class OpenACCClauseVisitor { + Impl &getDerived() { return static_cast(*this); } + +public: + void VisitClauseList(ArrayRef List) { + for (const OpenACCClause *Clause : List) + Visit(Clause); + } + + void Visit(const OpenACCClause *C) { + if (!C) + return; + + switch (C->getClauseKind()) { + case OpenACCClauseKind::Default: + case OpenACCClauseKind::Finalize: + case OpenACCClauseKind::IfPresent: + case OpenACCClauseKind::Seq: + case OpenACCClauseKind::Independent: + case OpenACCClauseKind::Auto: + case OpenACCClauseKind::Worker: + case OpenACCClauseKind::Vector: + case OpenACCClauseKind::NoHost: + case OpenACCClauseKind::If: + case OpenACCClauseKind::Self: + case OpenACCClauseKind::Copy: + case OpenACCClauseKind::UseDevice: + case OpenACCClauseKind::Attach: + case OpenACCClauseKind::Delete: + case OpenACCClauseKind::Detach: + case OpenACCClauseKind::Device: + case OpenACCClauseKind::DevicePtr: + case OpenACCClauseKind::DeviceResident: + case OpenACCClauseKind::FirstPrivate: + case OpenACCClauseKind::Host: + case OpenACCClauseKind::Link: + case OpenACCClauseKind::NoCreate: + case OpenACCClauseKind::Present: + case OpenACCClauseKind::Private: + case OpenACCClauseKind::CopyOut: + case OpenACCClauseKind::CopyIn: + case OpenACCClauseKind::Create: + case OpenACCClauseKind::Reduction: + case OpenACCClauseKind::Collapse: + case OpenACCClauseKind::Bind: + case OpenACCClauseKind::VectorLength: + case OpenACCClauseKind::NumGangs: + case OpenACCClauseKind::NumWorkers: + case OpenACCClauseKind::DeviceNum: + case OpenACCClauseKind::DefaultAsync: + case OpenACCClauseKind::DeviceType: + case OpenACCClauseKind::DType: + case OpenACCClauseKind::Async: + case OpenACCClauseKind::Tile: + case OpenACCClauseKind::Gang: + case OpenACCClauseKind::Wait: + case OpenACCClauseKind::Invalid: + llvm_unreachable("Clause visitor not yet implemented"); + } + llvm_unreachable("Invalid Clause kind"); + } +}; + +class OpenACCClausePrinter final + : public OpenACCClauseVisitor { + raw_ostream &OS; + +public: + void VisitClauseList(ArrayRef List) { + for (const OpenACCClause *Clause : List) { + Visit(Clause); + + if (Clause != List.back()) + OS << ' '; + } + } + OpenACCClausePrinter(raw_ostream &OS) : OS(OS) {} +}; + +} // namespace clang + +#endif // LLVM_CLANG_AST_OPENACCCLAUSE_H diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h index 8630317795a9..7eb92e304a38 100644 --- a/clang/include/clang/AST/RecursiveASTVisitor.h +++ b/clang/include/clang/AST/RecursiveASTVisitor.h @@ -509,6 +509,7 @@ private: bool TraverseOpenACCConstructStmt(OpenACCConstructStmt *S); bool TraverseOpenACCAssociatedStmtConstruct(OpenACCAssociatedStmtConstruct *S); + bool VisitOpenACCClauseList(ArrayRef); }; template @@ -3936,8 +3937,8 @@ bool RecursiveASTVisitor::VisitOMPXBareClause(OMPXBareClause *C) { template bool RecursiveASTVisitor::TraverseOpenACCConstructStmt( - OpenACCConstructStmt *) { - // TODO OpenACC: When we implement clauses, ensure we traverse them here. + OpenACCConstructStmt *C) { + TRY_TO(VisitOpenACCClauseList(C->clauses())); return true; } @@ -3949,6 +3950,14 @@ bool RecursiveASTVisitor::TraverseOpenACCAssociatedStmtConstruct( return true; } +template +bool RecursiveASTVisitor::VisitOpenACCClauseList( + ArrayRef) { + // TODO OpenACC: When we have Clauses with expressions, we should visit them + // here. + return true; +} + DEF_TRAVERSE_STMT(OpenACCComputeConstruct, { TRY_TO(TraverseOpenACCAssociatedStmtConstruct(S)); }) diff --git a/clang/include/clang/AST/StmtOpenACC.h b/clang/include/clang/AST/StmtOpenACC.h index 19da66832c73..419cb6cada0b 100644 --- a/clang/include/clang/AST/StmtOpenACC.h +++ b/clang/include/clang/AST/StmtOpenACC.h @@ -13,9 +13,11 @@ #ifndef LLVM_CLANG_AST_STMTOPENACC_H #define LLVM_CLANG_AST_STMTOPENACC_H +#include "clang/AST/OpenACCClause.h" #include "clang/AST/Stmt.h" #include "clang/Basic/OpenACCKinds.h" #include "clang/Basic/SourceLocation.h" +#include namespace clang { /// This is the base class for an OpenACC statement-level construct, other @@ -30,13 +32,23 @@ class OpenACCConstructStmt : public Stmt { /// the directive. SourceRange Range; - // TODO OPENACC: Clauses should probably be collected in this class. + /// The list of clauses. This is stored here as an ArrayRef, as this is the + /// most convienient place to access the list, however the list itself should + /// be stored in leaf nodes, likely in trailing-storage. + MutableArrayRef Clauses; protected: OpenACCConstructStmt(StmtClass SC, OpenACCDirectiveKind K, SourceLocation Start, SourceLocation End) : Stmt(SC), Kind(K), Range(Start, End) {} + // Used only for initialization, the leaf class can initialize this to + // trailing storage. + void setClauseList(MutableArrayRef NewClauses) { + assert(Clauses.empty() && "Cannot change clause list"); + Clauses = NewClauses; + } + public: OpenACCDirectiveKind getDirectiveKind() const { return Kind; } @@ -47,6 +59,7 @@ public: SourceLocation getBeginLoc() const { return Range.getBegin(); } SourceLocation getEndLoc() const { return Range.getEnd(); } + ArrayRef clauses() const { return Clauses; } child_range children() { return child_range(child_iterator(), child_iterator()); @@ -101,17 +114,32 @@ public: /// those three, as they are semantically identical, and have only minor /// differences in the permitted list of clauses, which can be differentiated by /// the 'Kind'. -class OpenACCComputeConstruct : public OpenACCAssociatedStmtConstruct { +class OpenACCComputeConstruct final + : public OpenACCAssociatedStmtConstruct, + public llvm::TrailingObjects { friend class ASTStmtWriter; friend class ASTStmtReader; friend class ASTContext; - OpenACCComputeConstruct() - : OpenACCAssociatedStmtConstruct( - OpenACCComputeConstructClass, OpenACCDirectiveKind::Invalid, - SourceLocation{}, SourceLocation{}, /*AssociatedStmt=*/nullptr) {} + OpenACCComputeConstruct(unsigned NumClauses) + : OpenACCAssociatedStmtConstruct(OpenACCComputeConstructClass, + OpenACCDirectiveKind::Invalid, + SourceLocation{}, SourceLocation{}, + /*AssociatedStmt=*/nullptr) { + // We cannot send the TrailingObjects storage to the base class (which holds + // a reference to the data) until it is constructed, so we have to set it + // separately here. + std::uninitialized_value_construct( + getTrailingObjects(), + getTrailingObjects() + NumClauses); + setClauseList(MutableArrayRef(getTrailingObjects(), + NumClauses)); + } OpenACCComputeConstruct(OpenACCDirectiveKind K, SourceLocation Start, - SourceLocation End, Stmt *StructuredBlock) + SourceLocation End, + ArrayRef Clauses, + Stmt *StructuredBlock) : OpenACCAssociatedStmtConstruct(OpenACCComputeConstructClass, K, Start, End, StructuredBlock) { assert((K == OpenACCDirectiveKind::Parallel || @@ -119,6 +147,13 @@ class OpenACCComputeConstruct : public OpenACCAssociatedStmtConstruct { K == OpenACCDirectiveKind::Kernels) && "Only parallel, serial, and kernels constructs should be " "represented by this type"); + + // Initialize the trailing storage. + std::uninitialized_copy(Clauses.begin(), Clauses.end(), + getTrailingObjects()); + + setClauseList(MutableArrayRef(getTrailingObjects(), + Clauses.size())); } void setStructuredBlock(Stmt *S) { setAssociatedStmt(S); } @@ -128,10 +163,12 @@ public: return T->getStmtClass() == OpenACCComputeConstructClass; } - static OpenACCComputeConstruct *CreateEmpty(const ASTContext &C, EmptyShell); + static OpenACCComputeConstruct *CreateEmpty(const ASTContext &C, + unsigned NumClauses); static OpenACCComputeConstruct * Create(const ASTContext &C, OpenACCDirectiveKind K, SourceLocation BeginLoc, - SourceLocation EndLoc, Stmt *StructuredBlock); + SourceLocation EndLoc, ArrayRef Clauses, + Stmt *StructuredBlock); Stmt *getStructuredBlock() { return getAssociatedStmt(); } const Stmt *getStructuredBlock() const { diff --git a/clang/include/clang/AST/TextNodeDumper.h b/clang/include/clang/AST/TextNodeDumper.h index efb5bfe7f83d..1fede6e462e9 100644 --- a/clang/include/clang/AST/TextNodeDumper.h +++ b/clang/include/clang/AST/TextNodeDumper.h @@ -189,6 +189,8 @@ public: void Visit(const OMPClause *C); + void Visit(const OpenACCClause *C); + void Visit(const BlockDecl::Capture &C); void Visit(const GenericSelectionExpr::ConstAssociation &A); diff --git a/clang/include/clang/Serialization/ASTRecordReader.h b/clang/include/clang/Serialization/ASTRecordReader.h index 5d3e95cb5d63..7dd1140106e4 100644 --- a/clang/include/clang/Serialization/ASTRecordReader.h +++ b/clang/include/clang/Serialization/ASTRecordReader.h @@ -24,6 +24,7 @@ #include "llvm/ADT/APSInt.h" namespace clang { +class OpenACCClause; class OMPTraitInfo; class OMPChildren; @@ -278,6 +279,12 @@ public: /// Read an OpenMP children, advancing Idx. void readOMPChildren(OMPChildren *Data); + /// Read an OpenACC clause, advancing Idx. + OpenACCClause *readOpenACCClause(); + + /// Read a list of OpenACC clauses into the passed SmallVector. + void readOpenACCClauseList(MutableArrayRef Clauses); + /// Read a source location, advancing Idx. SourceLocation readSourceLocation(LocSeq *Seq = nullptr) { return Reader->ReadSourceLocation(*F, Record, Idx, Seq); diff --git a/clang/include/clang/Serialization/ASTRecordWriter.h b/clang/include/clang/Serialization/ASTRecordWriter.h index e007d4a70843..1feb8fcbacf7 100644 --- a/clang/include/clang/Serialization/ASTRecordWriter.h +++ b/clang/include/clang/Serialization/ASTRecordWriter.h @@ -21,6 +21,7 @@ namespace clang { +class OpenACCClause; class TypeLoc; /// An object for streaming information to a record. @@ -292,6 +293,12 @@ public: /// Writes data related to the OpenMP directives. void writeOMPChildren(OMPChildren *Data); + /// Writes out a single OpenACC Clause. + void writeOpenACCClause(const OpenACCClause *C); + + /// Writes out a list of OpenACC clauses. + void writeOpenACCClauseList(ArrayRef Clauses); + /// Emit a string. void AddString(StringRef Str) { return Writer->AddString(Str, *Record); diff --git a/clang/lib/AST/CMakeLists.txt b/clang/lib/AST/CMakeLists.txt index 3fba052d916c..3faefb54f599 100644 --- a/clang/lib/AST/CMakeLists.txt +++ b/clang/lib/AST/CMakeLists.txt @@ -98,6 +98,7 @@ add_clang_library(clangAST NSAPI.cpp ODRDiagsEmitter.cpp ODRHash.cpp + OpenACCClause.cpp OpenMPClause.cpp OSLog.cpp ParentMap.cpp diff --git a/clang/lib/AST/JSONNodeDumper.cpp b/clang/lib/AST/JSONNodeDumper.cpp index 5861d5a7ea0d..fb3494393f75 100644 --- a/clang/lib/AST/JSONNodeDumper.cpp +++ b/clang/lib/AST/JSONNodeDumper.cpp @@ -187,6 +187,8 @@ void JSONNodeDumper::Visit(const CXXCtorInitializer *Init) { llvm_unreachable("Unknown initializer type"); } +void JSONNodeDumper::Visit(const OpenACCClause *C) {} + void JSONNodeDumper::Visit(const OMPClause *C) {} void JSONNodeDumper::Visit(const BlockDecl::Capture &C) { diff --git a/clang/lib/AST/OpenACCClause.cpp b/clang/lib/AST/OpenACCClause.cpp new file mode 100644 index 000000000000..e1db872f25c3 --- /dev/null +++ b/clang/lib/AST/OpenACCClause.cpp @@ -0,0 +1,17 @@ +//===---- OpenACCClause.cpp - Classes for OpenACC Clauses ----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the subclasses of the OpenACCClause class declared in +// OpenACCClause.h +// +//===----------------------------------------------------------------------===// + +#include "clang/AST/OpenACCClause.h" +#include "clang/AST/ASTContext.h" + +using namespace clang; diff --git a/clang/lib/AST/StmtOpenACC.cpp b/clang/lib/AST/StmtOpenACC.cpp index e6191bc6db70..a381a8dd7b62 100644 --- a/clang/lib/AST/StmtOpenACC.cpp +++ b/clang/lib/AST/StmtOpenACC.cpp @@ -15,20 +15,23 @@ using namespace clang; OpenACCComputeConstruct * -OpenACCComputeConstruct::CreateEmpty(const ASTContext &C, EmptyShell) { - void *Mem = C.Allocate(sizeof(OpenACCComputeConstruct), - alignof(OpenACCComputeConstruct)); - auto *Inst = new (Mem) OpenACCComputeConstruct; +OpenACCComputeConstruct::CreateEmpty(const ASTContext &C, unsigned NumClauses) { + void *Mem = C.Allocate( + OpenACCComputeConstruct::totalSizeToAlloc( + NumClauses)); + auto *Inst = new (Mem) OpenACCComputeConstruct(NumClauses); return Inst; } OpenACCComputeConstruct * OpenACCComputeConstruct::Create(const ASTContext &C, OpenACCDirectiveKind K, SourceLocation BeginLoc, SourceLocation EndLoc, + ArrayRef Clauses, Stmt *StructuredBlock) { - void *Mem = C.Allocate(sizeof(OpenACCComputeConstruct), - alignof(OpenACCComputeConstruct)); - auto *Inst = - new (Mem) OpenACCComputeConstruct(K, BeginLoc, EndLoc, StructuredBlock); + void *Mem = C.Allocate( + OpenACCComputeConstruct::totalSizeToAlloc( + Clauses.size())); + auto *Inst = new (Mem) + OpenACCComputeConstruct(K, BeginLoc, EndLoc, Clauses, StructuredBlock); return Inst; } diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index d66c3ccce209..74b18e50bf1f 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -1142,7 +1142,13 @@ void StmtPrinter::VisitOMPTargetParallelGenericLoopDirective( //===----------------------------------------------------------------------===// void StmtPrinter::VisitOpenACCComputeConstruct(OpenACCComputeConstruct *S) { Indent() << "#pragma acc " << S->getDirectiveKind(); - // TODO OpenACC: Print Clauses. + + if (!S->clauses().empty()) { + OS << ' '; + OpenACCClausePrinter Printer(OS); + Printer.VisitClauseList(S->clauses()); + } + PrintStmt(S->getStructuredBlock()); } diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index b545ff472e5a..d68547f444c5 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -2441,11 +2441,30 @@ void StmtProfiler::VisitTemplateArgument(const TemplateArgument &Arg) { } } +namespace { +class OpenACCClauseProfiler + : public OpenACCClauseVisitor { + +public: + OpenACCClauseProfiler() = default; + + void VisitOpenACCClauseList(ArrayRef Clauses) { + for (const OpenACCClause *Clause : Clauses) { + // TODO OpenACC: When we have clauses with expressions, we should + // profile them too. + Visit(Clause); + } + } +}; +} // namespace + void StmtProfiler::VisitOpenACCComputeConstruct( const OpenACCComputeConstruct *S) { // VisitStmt handles children, so the AssociatedStmt is handled. VisitStmt(S); - // TODO OpenACC: Visit Clauses. + + OpenACCClauseProfiler P; + P.VisitOpenACCClauseList(S->clauses()); } void Stmt::Profile(llvm::FoldingSetNodeID &ID, const ASTContext &Context, diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index 413e452146bd..0ffbf47c9a2f 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -381,6 +381,28 @@ void TextNodeDumper::Visit(const OMPClause *C) { OS << " "; } +void TextNodeDumper::Visit(const OpenACCClause *C) { + if (!C) { + ColorScope Color(OS, ShowColors, NullColor); + OS << "<<>> OpenACCClause"; + return; + } + { + ColorScope Color(OS, ShowColors, AttrColor); + OS << C->getClauseKind(); + + // Handle clauses with parens for types that have no children, likely + // because there is no sub expression. + switch (C->getClauseKind()) { + default: + // Nothing to do here. + break; + } + } + dumpPointer(C); + dumpSourceRange(SourceRange(C->getBeginLoc(), C->getEndLoc())); +} + void TextNodeDumper::Visit(const GenericSelectionExpr::ConstAssociation &A) { const TypeSourceInfo *TSI = A.getTypeSourceInfo(); if (TSI) { @@ -2684,5 +2706,4 @@ void TextNodeDumper::VisitHLSLBufferDecl(const HLSLBufferDecl *D) { void TextNodeDumper::VisitOpenACCConstructStmt(const OpenACCConstructStmt *S) { OS << " " << S->getDirectiveKind(); - // TODO OpenACC: Dump clauses as well. } diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index 2ac994cac71e..86ffa5ad74c1 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -94,8 +94,10 @@ StmtResult SemaOpenACC::ActOnEndStmtDirective(OpenACCDirectiveKind K, case OpenACCDirectiveKind::Parallel: case OpenACCDirectiveKind::Serial: case OpenACCDirectiveKind::Kernels: + // TODO OpenACC: Add clauses to the construct here. return OpenACCComputeConstruct::Create( getASTContext(), K, StartLoc, EndLoc, + /*Clauses=*/std::nullopt, AssocStmt.isUsable() ? AssocStmt.get() : nullptr); } llvm_unreachable("Unhandled case in directive handling?"); diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 9a39e7d3826e..9c0364b3934b 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -32,6 +32,7 @@ #include "clang/AST/NestedNameSpecifier.h" #include "clang/AST/ODRDiagsEmitter.h" #include "clang/AST/ODRHash.h" +#include "clang/AST/OpenACCClause.h" #include "clang/AST/OpenMPClause.h" #include "clang/AST/RawCommentList.h" #include "clang/AST/TemplateBase.h" @@ -53,6 +54,7 @@ #include "clang/Basic/LangOptions.h" #include "clang/Basic/Module.h" #include "clang/Basic/ObjCRuntime.h" +#include "clang/Basic/OpenACCKinds.h" #include "clang/Basic/OpenMPKinds.h" #include "clang/Basic/OperatorKinds.h" #include "clang/Basic/PragmaKinds.h" @@ -11751,3 +11753,66 @@ void ASTRecordReader::readOMPChildren(OMPChildren *Data) { for (unsigned I = 0, E = Data->getNumChildren(); I < E; ++I) Data->getChildren()[I] = readStmt(); } + +OpenACCClause *ASTRecordReader::readOpenACCClause() { + OpenACCClauseKind ClauseKind = readEnum(); + // TODO OpenACC: We don't have these used anywhere, but eventually we should + // be constructing the Clauses with them, so these attributes can go away at + // that point. + [[maybe_unused]] SourceLocation BeginLoc = readSourceLocation(); + [[maybe_unused]] SourceLocation EndLoc = readSourceLocation(); + + switch (ClauseKind) { + case OpenACCClauseKind::Default: + case OpenACCClauseKind::Finalize: + case OpenACCClauseKind::IfPresent: + case OpenACCClauseKind::Seq: + case OpenACCClauseKind::Independent: + case OpenACCClauseKind::Auto: + case OpenACCClauseKind::Worker: + case OpenACCClauseKind::Vector: + case OpenACCClauseKind::NoHost: + case OpenACCClauseKind::If: + case OpenACCClauseKind::Self: + case OpenACCClauseKind::Copy: + case OpenACCClauseKind::UseDevice: + case OpenACCClauseKind::Attach: + case OpenACCClauseKind::Delete: + case OpenACCClauseKind::Detach: + case OpenACCClauseKind::Device: + case OpenACCClauseKind::DevicePtr: + case OpenACCClauseKind::DeviceResident: + case OpenACCClauseKind::FirstPrivate: + case OpenACCClauseKind::Host: + case OpenACCClauseKind::Link: + case OpenACCClauseKind::NoCreate: + case OpenACCClauseKind::Present: + case OpenACCClauseKind::Private: + case OpenACCClauseKind::CopyOut: + case OpenACCClauseKind::CopyIn: + case OpenACCClauseKind::Create: + case OpenACCClauseKind::Reduction: + case OpenACCClauseKind::Collapse: + case OpenACCClauseKind::Bind: + case OpenACCClauseKind::VectorLength: + case OpenACCClauseKind::NumGangs: + case OpenACCClauseKind::NumWorkers: + case OpenACCClauseKind::DeviceNum: + case OpenACCClauseKind::DefaultAsync: + case OpenACCClauseKind::DeviceType: + case OpenACCClauseKind::DType: + case OpenACCClauseKind::Async: + case OpenACCClauseKind::Tile: + case OpenACCClauseKind::Gang: + case OpenACCClauseKind::Wait: + case OpenACCClauseKind::Invalid: + llvm_unreachable("Clause serialization not yet implemented"); + } + llvm_unreachable("Invalid Clause Kind"); +} + +void ASTRecordReader::readOpenACCClauseList( + MutableArrayRef Clauses) { + for (unsigned I = 0; I < Clauses.size(); ++I) + Clauses[I] = readOpenACCClause(); +} diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp index bbeb6db01164..f0984c3e4696 100644 --- a/clang/lib/Serialization/ASTReaderStmt.cpp +++ b/clang/lib/Serialization/ASTReaderStmt.cpp @@ -2784,9 +2784,10 @@ void ASTStmtReader::VisitOMPTargetParallelGenericLoopDirective( // OpenACC Constructs/Directives. //===----------------------------------------------------------------------===// void ASTStmtReader::VisitOpenACCConstructStmt(OpenACCConstructStmt *S) { + (void)Record.readInt(); S->Kind = Record.readEnum(); S->Range = Record.readSourceRange(); - // TODO OpenACC: Deserialize Clauses. + Record.readOpenACCClauseList(S->Clauses); } void ASTStmtReader::VisitOpenACCAssociatedStmtConstruct( @@ -4218,10 +4219,11 @@ Stmt *ASTReader::ReadStmtFromStream(ModuleFile &F) { S = new (Context) ConceptSpecializationExpr(Empty); break; } - case STMT_OPENACC_COMPUTE_CONSTRUCT: - S = OpenACCComputeConstruct::CreateEmpty(Context, Empty); + case STMT_OPENACC_COMPUTE_CONSTRUCT: { + unsigned NumClauses = Record[ASTStmtReader::NumStmtFields]; + S = OpenACCComputeConstruct::CreateEmpty(Context, NumClauses); break; - + } case EXPR_REQUIRES: unsigned numLocalParameters = Record[ASTStmtReader::NumExprFields]; unsigned numRequirement = Record[ASTStmtReader::NumExprFields + 1]; diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index ba6a8a5e16e4..baf03f69d730 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -29,6 +29,7 @@ #include "clang/AST/ExprCXX.h" #include "clang/AST/LambdaCapture.h" #include "clang/AST/NestedNameSpecifier.h" +#include "clang/AST/OpenACCClause.h" #include "clang/AST/OpenMPClause.h" #include "clang/AST/RawCommentList.h" #include "clang/AST/TemplateName.h" @@ -44,6 +45,7 @@ #include "clang/Basic/LangOptions.h" #include "clang/Basic/Module.h" #include "clang/Basic/ObjCRuntime.h" +#include "clang/Basic/OpenACCKinds.h" #include "clang/Basic/OpenCLOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/SourceManager.h" @@ -7397,3 +7399,63 @@ void ASTRecordWriter::writeOMPChildren(OMPChildren *Data) { for (unsigned I = 0, E = Data->getNumChildren(); I < E; ++I) AddStmt(Data->getChildren()[I]); } + +void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { + writeEnum(C->getClauseKind()); + writeSourceLocation(C->getBeginLoc()); + writeSourceLocation(C->getEndLoc()); + + switch (C->getClauseKind()) { + case OpenACCClauseKind::Default: + case OpenACCClauseKind::Finalize: + case OpenACCClauseKind::IfPresent: + case OpenACCClauseKind::Seq: + case OpenACCClauseKind::Independent: + case OpenACCClauseKind::Auto: + case OpenACCClauseKind::Worker: + case OpenACCClauseKind::Vector: + case OpenACCClauseKind::NoHost: + case OpenACCClauseKind::If: + case OpenACCClauseKind::Self: + case OpenACCClauseKind::Copy: + case OpenACCClauseKind::UseDevice: + case OpenACCClauseKind::Attach: + case OpenACCClauseKind::Delete: + case OpenACCClauseKind::Detach: + case OpenACCClauseKind::Device: + case OpenACCClauseKind::DevicePtr: + case OpenACCClauseKind::DeviceResident: + case OpenACCClauseKind::FirstPrivate: + case OpenACCClauseKind::Host: + case OpenACCClauseKind::Link: + case OpenACCClauseKind::NoCreate: + case OpenACCClauseKind::Present: + case OpenACCClauseKind::Private: + case OpenACCClauseKind::CopyOut: + case OpenACCClauseKind::CopyIn: + case OpenACCClauseKind::Create: + case OpenACCClauseKind::Reduction: + case OpenACCClauseKind::Collapse: + case OpenACCClauseKind::Bind: + case OpenACCClauseKind::VectorLength: + case OpenACCClauseKind::NumGangs: + case OpenACCClauseKind::NumWorkers: + case OpenACCClauseKind::DeviceNum: + case OpenACCClauseKind::DefaultAsync: + case OpenACCClauseKind::DeviceType: + case OpenACCClauseKind::DType: + case OpenACCClauseKind::Async: + case OpenACCClauseKind::Tile: + case OpenACCClauseKind::Gang: + case OpenACCClauseKind::Wait: + case OpenACCClauseKind::Invalid: + llvm_unreachable("Clause serialization not yet implemented"); + } + llvm_unreachable("Invalid Clause Kind"); +} + +void ASTRecordWriter::writeOpenACCClauseList( + ArrayRef Clauses) { + for (const OpenACCClause *Clause : Clauses) + writeOpenACCClause(Clause); +} diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp index 22e190450d39..0651614e2ce5 100644 --- a/clang/lib/Serialization/ASTWriterStmt.cpp +++ b/clang/lib/Serialization/ASTWriterStmt.cpp @@ -2839,9 +2839,10 @@ void ASTStmtWriter::VisitOMPTargetParallelGenericLoopDirective( // OpenACC Constructs/Directives. //===----------------------------------------------------------------------===// void ASTStmtWriter::VisitOpenACCConstructStmt(OpenACCConstructStmt *S) { + Record.push_back(S->clauses().size()); Record.writeEnum(S->Kind); Record.AddSourceRange(S->Range); - // TODO OpenACC: Serialize Clauses. + Record.writeOpenACCClauseList(S->clauses()); } void ASTStmtWriter::VisitOpenACCAssociatedStmtConstruct( -- GitLab From 0cd0aa029647c8d1dba5c3d62f92325576796fa2 Mon Sep 17 00:00:00 2001 From: Ian Anderson Date: Fri, 5 Apr 2024 10:13:42 -0700 Subject: [PATCH 006/695] [clang][modules] Headers meant to be included multiple times can be completely invisible in clang module builds (#83660) Once a file has been `#import`'ed, it gets stamped as if it was `#pragma once` and will not be re-entered, even on #include. This means that any errant #import of a file designed to be included multiple times, such as , will incorrectly mark it as include-once and break the multiple include functionality. Normally this isn't a big problem, e.g. can't have its NDEBUG mode changed after the first #import, but it is still mostly functional. However, when clang modules are involved, this can cause the header to be hidden entirely. Objective-C code most often uses #import for everything, because it's required for most Objective-C headers to prevent double inclusion and redeclaration errors. (It's rare for Objective-C headers to use macro guards or `#pragma once`.) The problem arises when a submodule includes a multiple-include header. The "already included" state is global across all modules (which is necessary so that non-modular headers don't get compiled into multiple translation units and cause redeclaration errors). If another module or the main file #import's the same header, it becomes invisible from then on. If the original submodule is not imported, the include of the header will effectively do nothing and the header will be invisible. The only way to actually get the header's declarations is to somehow figure out which submodule consumed the header, and import that instead. That's basically impossible since it depends on exactly which modules were built in which order. #import is a poor indicator of whether a header is actually include-once, as the #import is external to the header it applies to, and requires that all inclusions correctly and consistently use #import vs #include. When modules are enabled, consider a header marked `textual` in its module as a stronger indicator of multiple-include than #import's indication of include-once. This will allow headers like to always be included when modules are enabled, even if #import is erroneously used somewhere. --- clang/include/clang/Lex/HeaderSearch.h | 26 ++- clang/lib/Lex/HeaderSearch.cpp | 183 +++++++++++++------ clang/lib/Serialization/ASTReader.cpp | 2 +- clang/test/Modules/builtin-import.mm | 2 + clang/test/Modules/import-textual-noguard.mm | 6 +- clang/test/Modules/import-textual.mm | 2 + clang/test/Modules/multiple-import.m | 43 +++++ 7 files changed, 201 insertions(+), 63 deletions(-) create mode 100644 clang/test/Modules/multiple-import.m diff --git a/clang/include/clang/Lex/HeaderSearch.h b/clang/include/clang/Lex/HeaderSearch.h index 705dcfa8aacc..855f81f775f8 100644 --- a/clang/include/clang/Lex/HeaderSearch.h +++ b/clang/include/clang/Lex/HeaderSearch.h @@ -78,11 +78,19 @@ struct HeaderFileInfo { LLVM_PREFERRED_TYPE(bool) unsigned External : 1; - /// Whether this header is part of a module. + /// Whether this header is part of and built with a module. i.e. it is listed + /// in a module map, and is not `excluded` or `textual`. (same meaning as + /// `ModuleMap::isModular()`). LLVM_PREFERRED_TYPE(bool) unsigned isModuleHeader : 1; - /// Whether this header is part of the module that we are building. + /// Whether this header is a `textual header` in a module. + LLVM_PREFERRED_TYPE(bool) + unsigned isTextualModuleHeader : 1; + + /// Whether this header is part of the module that we are building, even if it + /// doesn't build with the module. i.e. this will include `excluded` and + /// `textual` headers as well as normal headers. LLVM_PREFERRED_TYPE(bool) unsigned isCompilingModuleHeader : 1; @@ -128,13 +136,20 @@ struct HeaderFileInfo { HeaderFileInfo() : isImport(false), isPragmaOnce(false), DirInfo(SrcMgr::C_User), - External(false), isModuleHeader(false), isCompilingModuleHeader(false), - Resolved(false), IndexHeaderMapHeader(false), IsValid(false) {} + External(false), isModuleHeader(false), isTextualModuleHeader(false), + isCompilingModuleHeader(false), Resolved(false), + IndexHeaderMapHeader(false), IsValid(false) {} /// Retrieve the controlling macro for this header file, if /// any. const IdentifierInfo * getControllingMacro(ExternalPreprocessorSource *External); + + /// Update the module membership bits based on the header role. + /// + /// isModuleHeader will potentially be set, but not cleared. + /// isTextualModuleHeader will be set or cleared based on the role update. + void mergeModuleMembership(ModuleMap::ModuleHeaderRole Role); }; /// An external source of header file information, which may supply @@ -522,6 +537,9 @@ public: /// /// \return false if \#including the file will have no effect or true /// if we should include it. + /// + /// \param M The module to which `File` belongs (this should usually be the + /// SuggestedModule returned by LookupFile/LookupSubframeworkHeader) bool ShouldEnterIncludeFile(Preprocessor &PP, FileEntryRef File, bool isImport, bool ModulesEnabled, Module *M, bool &IsFirstIncludeOfFile); diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index fcc2b56df166..7dffcf0e941e 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -1307,6 +1307,23 @@ OptionalFileEntryRef HeaderSearch::LookupSubframeworkHeader( // File Info Management. //===----------------------------------------------------------------------===// +static void mergeHeaderFileInfoModuleBits(HeaderFileInfo &HFI, + bool isModuleHeader, + bool isTextualModuleHeader) { + assert((!isModuleHeader || !isTextualModuleHeader) && + "A header can't build with a module and be textual at the same time"); + HFI.isModuleHeader |= isModuleHeader; + if (HFI.isModuleHeader) + HFI.isTextualModuleHeader = false; + else + HFI.isTextualModuleHeader |= isTextualModuleHeader; +} + +void HeaderFileInfo::mergeModuleMembership(ModuleMap::ModuleHeaderRole Role) { + mergeHeaderFileInfoModuleBits(*this, ModuleMap::isModular(Role), + (Role & ModuleMap::TextualHeader)); +} + /// Merge the header file info provided by \p OtherHFI into the current /// header file info (\p HFI) static void mergeHeaderFileInfo(HeaderFileInfo &HFI, @@ -1315,7 +1332,8 @@ static void mergeHeaderFileInfo(HeaderFileInfo &HFI, HFI.isImport |= OtherHFI.isImport; HFI.isPragmaOnce |= OtherHFI.isPragmaOnce; - HFI.isModuleHeader |= OtherHFI.isModuleHeader; + mergeHeaderFileInfoModuleBits(HFI, OtherHFI.isModuleHeader, + OtherHFI.isTextualModuleHeader); if (!HFI.ControllingMacro && !HFI.ControllingMacroID) { HFI.ControllingMacro = OtherHFI.ControllingMacro; @@ -1403,11 +1421,9 @@ bool HeaderSearch::isFileMultipleIncludeGuarded(FileEntryRef File) const { void HeaderSearch::MarkFileModuleHeader(FileEntryRef FE, ModuleMap::ModuleHeaderRole Role, bool isCompilingModuleHeader) { - bool isModularHeader = ModuleMap::isModular(Role); - // Don't mark the file info as non-external if there's nothing to change. if (!isCompilingModuleHeader) { - if (!isModularHeader) + if ((Role & ModuleMap::ExcludedHeader)) return; auto *HFI = getExistingFileInfo(FE); if (HFI && HFI->isModuleHeader) @@ -1415,7 +1431,7 @@ void HeaderSearch::MarkFileModuleHeader(FileEntryRef FE, } auto &HFI = getFileInfo(FE); - HFI.isModuleHeader |= isModularHeader; + HFI.mergeModuleMembership(Role); HFI.isCompilingModuleHeader |= isCompilingModuleHeader; } @@ -1423,74 +1439,128 @@ bool HeaderSearch::ShouldEnterIncludeFile(Preprocessor &PP, FileEntryRef File, bool isImport, bool ModulesEnabled, Module *M, bool &IsFirstIncludeOfFile) { - ++NumIncluded; // Count # of attempted #includes. - + // An include file should be entered if either: + // 1. This is the first include of the file. + // 2. This file can be included multiple times, that is it's not an + // "include-once" file. + // + // Include-once is controlled by these preprocessor directives. + // + // #pragma once + // This directive is in the include file, and marks it as an include-once + // file. + // + // #import + // This directive is in the includer, and indicates that the include file + // should only be entered if this is the first include. + ++NumIncluded; IsFirstIncludeOfFile = false; - - // Get information about this file. HeaderFileInfo &FileInfo = getFileInfo(File); - // FIXME: this is a workaround for the lack of proper modules-aware support - // for #import / #pragma once - auto TryEnterImported = [&]() -> bool { - if (!ModulesEnabled) + auto MaybeReenterImportedFile = [&]() -> bool { + // Modules add a wrinkle though: what's included isn't necessarily visible. + // Consider this module. + // module Example { + // module A { header "a.h" export * } + // module B { header "b.h" export * } + // } + // b.h includes c.h. The main file includes a.h, which will trigger a module + // build of Example, and c.h will be included. However, c.h isn't visible to + // the main file. Normally this is fine, the main file can just include c.h + // if it needs it. If c.h is in a module, the include will translate into a + // module import, this function will be skipped, and everything will work as + // expected. However, if c.h is not in a module (or is `textual`), then this + // function will run. If c.h is include-once, it will not be entered from + // the main file and it will still not be visible. + + // If modules aren't enabled then there's no visibility issue. Always + // respect `#pragma once`. + if (!ModulesEnabled || FileInfo.isPragmaOnce) return false; + // Ensure FileInfo bits are up to date. ModMap.resolveHeaderDirectives(File); - // Modules with builtins are special; multiple modules use builtins as - // modular headers, example: - // - // module stddef { header "stddef.h" export * } - // - // After module map parsing, this expands to: - // - // module stddef { - // header "/path_to_builtin_dirs/stddef.h" - // textual "stddef.h" - // } + + // This brings up a subtlety of #import - it's not a very good indicator of + // include-once. Developers are often unaware of the difference between + // #include and #import, and tend to use one or the other indiscrimiately. + // In order to support #include on include-once headers that lack macro + // guards and `#pragma once` (which is the vast majority of Objective-C + // headers), if a file is ever included with #import, it's marked as + // isImport in the HeaderFileInfo and treated as include-once. This allows + // #include to work in Objective-C. + // #include + // #include + // Foundation.h has an #import of NSString.h, and so the second #include is + // skipped even though NSString.h has no `#pragma once` and no macro guard. // - // It's common that libc++ and system modules will both define such - // submodules. Make sure cached results for a builtin header won't - // prevent other builtin modules from potentially entering the builtin - // header. Note that builtins are header guarded and the decision to - // actually enter them is postponed to the controlling macros logic below. - bool TryEnterHdr = false; - if (FileInfo.isCompilingModuleHeader && FileInfo.isModuleHeader) - TryEnterHdr = ModMap.isBuiltinHeader(File); - - // Textual headers can be #imported from different modules. Since ObjC - // headers find in the wild might rely only on #import and do not contain - // controlling macros, be conservative and only try to enter textual headers - // if such macro is present. - if (!FileInfo.isModuleHeader && - FileInfo.getControllingMacro(ExternalLookup)) - TryEnterHdr = true; - return TryEnterHdr; + // However, this helpfulness causes problems with modules. If c.h is not an + // include-once file, but something included it with #import anyway (as is + // typical in Objective-C code), this include will be skipped and c.h will + // not be visible. Consider it not include-once if it is a `textual` header + // in a module. + if (FileInfo.isTextualModuleHeader) + return true; + + if (FileInfo.isCompilingModuleHeader) { + // It's safer to re-enter a file whose module is being built because its + // declarations will still be scoped to a single module. + if (FileInfo.isModuleHeader) { + // Headers marked as "builtin" are covered by the system module maps + // rather than the builtin ones. Some versions of the Darwin module fail + // to mark stdarg.h and stddef.h as textual. Attempt to re-enter these + // files while building their module to allow them to function properly. + if (ModMap.isBuiltinHeader(File)) + return true; + } else { + // Files that are excluded from their module can potentially be + // re-entered from their own module. This might cause redeclaration + // errors if another module saw this file first, but there's a + // reasonable chance that its module will build first. However if + // there's no controlling macro, then trust the #import and assume this + // really is an include-once file. + if (FileInfo.getControllingMacro(ExternalLookup)) + return true; + } + } + // If the include file has a macro guard, then it might still not be + // re-entered if the controlling macro is visibly defined. e.g. another + // header in the module being built included this file and local submodule + // visibility is not enabled. + + // It might be tempting to re-enter the include-once file if it's not + // visible in an attempt to make it visible. However this will still cause + // redeclaration errors against the known-but-not-visible declarations. The + // include file not being visible will most likely cause "undefined x" + // errors, but at least there's a slim chance of compilation succeeding. + return false; }; - // If this is a #import directive, check that we have not already imported - // this header. if (isImport) { - // If this has already been imported, don't import it again. + // As discussed above, record that this file was ever `#import`ed, and treat + // it as an include-once file from here out. FileInfo.isImport = true; - - // Has this already been #import'ed or #include'd? - if (PP.alreadyIncluded(File) && !TryEnterImported()) + if (PP.alreadyIncluded(File) && !MaybeReenterImportedFile()) return false; } else { - // Otherwise, if this is a #include of a file that was previously #import'd - // or if this is the second #include of a #pragma once file, ignore it. - if ((FileInfo.isPragmaOnce || FileInfo.isImport) && !TryEnterImported()) + // isPragmaOnce and isImport are only set after the file has been included + // at least once. If either are set then this is a repeat #include of an + // include-once file. + if (FileInfo.isPragmaOnce || + (FileInfo.isImport && !MaybeReenterImportedFile())) return false; } - // Next, check to see if the file is wrapped with #ifndef guards. If so, and - // if the macro that guards it is defined, we know the #include has no effect. - if (const IdentifierInfo *ControllingMacro - = FileInfo.getControllingMacro(ExternalLookup)) { + // As a final optimization, check for a macro guard and skip entering the file + // if the controlling macro is defined. The macro guard will effectively erase + // the file's contents, and the include would have no effect other than to + // waste time opening and reading a file. + if (const IdentifierInfo *ControllingMacro = + FileInfo.getControllingMacro(ExternalLookup)) { // If the header corresponds to a module, check whether the macro is already - // defined in that module rather than checking in the current set of visible - // modules. + // defined in that module rather than checking all visible modules. This is + // mainly to cover corner cases where the same controlling macro is used in + // different files in multiple modules. if (M ? PP.isMacroDefinedInLocalModule(ControllingMacro, M) : PP.isMacroDefined(ControllingMacro)) { ++NumMultiIncludeFileOptzn; @@ -1499,7 +1569,6 @@ bool HeaderSearch::ShouldEnterIncludeFile(Preprocessor &PP, } IsFirstIncludeOfFile = PP.markIncluded(File); - return true; } diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 9c0364b3934b..fa5bb9f2d543 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -2096,7 +2096,7 @@ HeaderFileInfoTrait::ReadData(internal_key_ref key, const unsigned char *d, Module::Header H = {std::string(key.Filename), "", *FE}; ModMap.addHeader(Mod, H, HeaderRole, /*Imported=*/true); } - HFI.isModuleHeader |= ModuleMap::isModular(HeaderRole); + HFI.mergeModuleMembership(HeaderRole); } // This HeaderFileInfo was externally loaded. diff --git a/clang/test/Modules/builtin-import.mm b/clang/test/Modules/builtin-import.mm index 8a27cb358484..52db9c15803c 100644 --- a/clang/test/Modules/builtin-import.mm +++ b/clang/test/Modules/builtin-import.mm @@ -1,4 +1,6 @@ // RUN: rm -rf %t +// RUN: %clang_cc1 -fsyntax-only -nobuiltininc -nostdinc++ -isysroot %S/Inputs/libc-libcxx/sysroot -isystem %S/Inputs/libc-libcxx/sysroot/usr/include/c++/v1 -isystem %S/Inputs/libc-libcxx/sysroot/usr/include -std=c++11 -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -x objective-c++ %s +// RUN: rm -rf %t // RUN: %clang_cc1 -fsyntax-only -nobuiltininc -nostdinc++ -isysroot %S/Inputs/libc-libcxx/sysroot -isystem %S/Inputs/libc-libcxx/sysroot/usr/include/c++/v1 -isystem %S/Inputs/libc-libcxx/sysroot/usr/include -std=c++11 -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -x objective-c++ -fmodules-local-submodule-visibility %s #include diff --git a/clang/test/Modules/import-textual-noguard.mm b/clang/test/Modules/import-textual-noguard.mm index dd124b6609d0..ffc506117f51 100644 --- a/clang/test/Modules/import-textual-noguard.mm +++ b/clang/test/Modules/import-textual-noguard.mm @@ -1,7 +1,11 @@ // RUN: rm -rf %t +// RUN: %clang_cc1 -fsyntax-only -std=c++11 -fmodules -fimplicit-module-maps -I%S/Inputs/import-textual/M2 -fmodules-cache-path=%t -x objective-c++ %s -verify +// RUN: rm -rf %t // RUN: %clang_cc1 -fsyntax-only -std=c++11 -fmodules -fimplicit-module-maps -I%S/Inputs/import-textual/M2 -fmodules-cache-path=%t -x objective-c++ -fmodules-local-submodule-visibility %s -verify -#include "A/A.h" // expected-error {{could not build module 'M'}} +// expected-no-diagnostics + +#include "A/A.h" #include "B/B.h" typedef aint xxx; diff --git a/clang/test/Modules/import-textual.mm b/clang/test/Modules/import-textual.mm index 6593239d7fd7..94a6aa448cdc 100644 --- a/clang/test/Modules/import-textual.mm +++ b/clang/test/Modules/import-textual.mm @@ -1,4 +1,6 @@ // RUN: rm -rf %t +// RUN: %clang_cc1 -fsyntax-only -std=c++11 -fmodules -fimplicit-module-maps -I%S/Inputs/import-textual/M -fmodules-cache-path=%t -x objective-c++ %s -verify +// RUN: rm -rf %t // RUN: %clang_cc1 -fsyntax-only -std=c++11 -fmodules -fimplicit-module-maps -I%S/Inputs/import-textual/M -fmodules-cache-path=%t -x objective-c++ -fmodules-local-submodule-visibility %s -verify // expected-no-diagnostics diff --git a/clang/test/Modules/multiple-import.m b/clang/test/Modules/multiple-import.m new file mode 100644 index 000000000000..95ca7dbcd438 --- /dev/null +++ b/clang/test/Modules/multiple-import.m @@ -0,0 +1,43 @@ +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: %clang_cc1 -std=c17 -fmodules-cache-path=%t/no-lsv -fmodules -fimplicit-module-maps -I%t %t/multiple-imports.m -verify +// RUN: %clang_cc1 -std=c17 -fmodules-cache-path=%t/lsv -fmodules -fimplicit-module-maps -fmodules-local-submodule-visibility -I%t %t/multiple-imports.m -verify + +//--- multiple-imports.m +// expected-no-diagnostics +#import +#import +void test(void) { + assert(0); +} + +//--- module.modulemap +module Submodules [system] { + module one { + header "one.h" + export * + } + module two { + header "two.h" + export * + } +} + +module libc [system] { + textual header "assert.h" +} + +//--- one.h +#ifndef one_h +#define one_h +#endif + +//--- two.h +#ifndef two_h +#define two_h +#include +#endif + +//--- assert.h +#undef assert +#define assert(expression) ((void)0) -- GitLab From c7eede5d4c1c8e0c20337f3f3c9003f59fe5ccd5 Mon Sep 17 00:00:00 2001 From: Argyrios Kyrtzidis Date: Fri, 5 Apr 2024 10:31:16 -0700 Subject: [PATCH 007/695] [clang][deps] Remove pgo profile flags from modules (#87724) These are not necessary when not performing codegen. --- clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp | 3 +++ .../test/ClangScanDeps/Inputs/removed-args/cdb.json.template | 2 +- clang/test/ClangScanDeps/removed-args.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp index eb5c50c35428..94ccbd3351b0 100644 --- a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp +++ b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp @@ -175,6 +175,9 @@ makeCommonInvocationForModuleBuild(CompilerInvocation CI) { CI.getCodeGenOpts().CoverageCompilationDir.clear(); CI.getCodeGenOpts().CoverageDataFile.clear(); CI.getCodeGenOpts().CoverageNotesFile.clear(); + CI.getCodeGenOpts().ProfileInstrumentUsePath.clear(); + CI.getCodeGenOpts().SampleProfileFile.clear(); + CI.getCodeGenOpts().ProfileRemappingFile.clear(); } // Map output paths that affect behaviour to "-" so their existence is in the diff --git a/clang/test/ClangScanDeps/Inputs/removed-args/cdb.json.template b/clang/test/ClangScanDeps/Inputs/removed-args/cdb.json.template index 7ae3c88aedd8..ca56799cd08e 100644 --- a/clang/test/ClangScanDeps/Inputs/removed-args/cdb.json.template +++ b/clang/test/ClangScanDeps/Inputs/removed-args/cdb.json.template @@ -1,7 +1,7 @@ [ { "directory": "DIR", - "command": "clang -fsyntax-only DIR/tu.c -fmodules -fimplicit-module-maps -fmodules-validate-once-per-build-session -fbuild-session-file=DIR/build-session -fmodules-prune-interval=123 -fmodules-prune-after=123 -fmodules-cache-path=DIR/cache -include DIR/header.h -grecord-command-line -fdebug-compilation-dir=DIR/debug -fcoverage-compilation-dir=DIR/coverage -ftest-coverage -o DIR/tu.o -serialize-diagnostics DIR/tu.diag -MT tu -MD -MF DIR/tu.d", + "command": "clang -fsyntax-only DIR/tu.c -fmodules -fimplicit-module-maps -fmodules-validate-once-per-build-session -fbuild-session-file=DIR/build-session -fmodules-prune-interval=123 -fmodules-prune-after=123 -fmodules-cache-path=DIR/cache -include DIR/header.h -grecord-command-line -fdebug-compilation-dir=DIR/debug -fcoverage-compilation-dir=DIR/coverage -ftest-coverage -fprofile-instr-use=DIR/tu.profdata -o DIR/tu.o -serialize-diagnostics DIR/tu.diag -MT tu -MD -MF DIR/tu.d", "file": "DIR/tu.c" } ] diff --git a/clang/test/ClangScanDeps/removed-args.c b/clang/test/ClangScanDeps/removed-args.c index 9a4ef25838e4..f49e4ead82f7 100644 --- a/clang/test/ClangScanDeps/removed-args.c +++ b/clang/test/ClangScanDeps/removed-args.c @@ -9,6 +9,8 @@ // RUN: rm -rf %t && mkdir %t // RUN: cp %S/Inputs/removed-args/* %t // RUN: touch %t/build-session +// RUN: touch %t/tu.proftext +// RUN: llvm-profdata merge %t/tu.proftext -o %t/tu.profdata // RUN: sed "s|DIR|%/t|g" %S/Inputs/removed-args/cdb.json.template > %t/cdb.json // RUN: clang-scan-deps -compilation-database %t/cdb.json -format experimental-full > %t/result.json @@ -25,6 +27,7 @@ // CHECK-NOT: "-fcoverage-compilation-dir=" // CHECK-NOT: "-coverage-notes-file // CHECK-NOT: "-coverage-data-file +// CHECK-NOT: "-fprofile-instrument-use-path // CHECK-NOT: "-dwarf-debug-flags" // CHECK-NOT: "-main-file-name" // CHECK-NOT: "-include" @@ -50,6 +53,7 @@ // CHECK-NOT: "-fcoverage-compilation-dir= // CHECK-NOT: "-coverage-notes-file // CHECK-NOT: "-coverage-data-file +// CHECK-NOT: "-fprofile-instrument-use-path // CHECK-NOT: "-dwarf-debug-flags" // CHECK-NOT: "-main-file-name" // CHECK-NOT: "-include" -- GitLab From 0e60cf7f4b66312c09df9412be3efd1e9c891e85 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Fri, 5 Apr 2024 17:37:01 +0000 Subject: [PATCH 008/695] [gn build] Manually port 68b939f9 --- llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn index e5fb529b455f..80a91507fcc6 100644 --- a/llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/include/llvm/Config/BUILD.gn @@ -122,6 +122,7 @@ write_cmake_config("config") { "HOST_LINK_VERSION=", "LIBPFM_HAS_FIELD_CYCLES=", "LLVM_TARGET_TRIPLE_ENV=", + "LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG=1", "LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO=1", "LLVM_WINDOWS_PREFER_FORWARD_SLASH=", "PACKAGE_BUGREPORT=https://github.com/llvm/llvm-project/issues/", -- GitLab From 666fd665e98df1e5c8e8d5be1eb08bf102c0691c Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Fri, 5 Apr 2024 17:37:44 +0000 Subject: [PATCH 009/695] [gn build] Port 30f6eafaa978 --- llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn index a405878fecb2..0cf99256c9bd 100644 --- a/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn @@ -127,6 +127,7 @@ static_library("AST") { "ODRDiagsEmitter.cpp", "ODRHash.cpp", "OSLog.cpp", + "OpenACCClause.cpp", "OpenMPClause.cpp", "ParentMap.cpp", "ParentMapContext.cpp", -- GitLab From 6411aaf99cbfddafdeecb73d9fd7388fcae32293 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Fri, 5 Apr 2024 17:37:45 +0000 Subject: [PATCH 010/695] [gn build] Port e84a757222aa --- llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn index 15c198c73f94..edf06df4f609 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn @@ -52,6 +52,7 @@ unittest("ADTTests") { "ImmutableMapTest.cpp", "ImmutableSetTest.cpp", "IntEqClassesTest.cpp", + "Interleave.cpp", "IntervalMapTest.cpp", "IntervalTreeTest.cpp", "IntrusiveRefCntPtrTest.cpp", -- GitLab From 965e053eb3ba336b6174e6753f138cabc0ea92c2 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Fri, 5 Apr 2024 17:37:46 +0000 Subject: [PATCH 011/695] [gn build] Port f5960c168dfe --- llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 78a6e6fda826..66e8084d5808 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -807,6 +807,7 @@ if (current_toolchain == default_toolchain) { "__type_traits/datasizeof.h", "__type_traits/decay.h", "__type_traits/dependent_type.h", + "__type_traits/desugars_to.h", "__type_traits/disjunction.h", "__type_traits/enable_if.h", "__type_traits/extent.h", @@ -891,7 +892,6 @@ if (current_toolchain == default_toolchain) { "__type_traits/nat.h", "__type_traits/negation.h", "__type_traits/noexcept_move_assign_container.h", - "__type_traits/operation_traits.h", "__type_traits/promote.h", "__type_traits/rank.h", "__type_traits/remove_all_extents.h", -- GitLab From 5772fc890f7ebda04029ba82af32c9072a1c44b6 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Fri, 5 Apr 2024 17:42:36 +0000 Subject: [PATCH 012/695] [gn build] Add missing dependency --- llvm/utils/gn/secondary/llvm/lib/TextAPI/BinaryReader/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/TextAPI/BinaryReader/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/TextAPI/BinaryReader/BUILD.gn index 3eeb32aae4e3..24130bc2e08f 100644 --- a/llvm/utils/gn/secondary/llvm/lib/TextAPI/BinaryReader/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/TextAPI/BinaryReader/BUILD.gn @@ -1,6 +1,7 @@ static_library("BinaryReader") { output_name = "LLVMTextAPIBinaryReader" deps = [ + "//llvm/lib/DebugInfo/DWARF", "//llvm/lib/Object", "//llvm/lib/Support", "//llvm/lib/TargetParser", -- GitLab From e915b7d8166a870834868bcf7de85cb5e96a08ec Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 5 Apr 2024 10:52:10 -0700 Subject: [PATCH 013/695] [ELF,test] Add test for R_AARCH64_* implicit addends to support certain static relocations in the REL format. See #87328 for the armasm need. Note: `R_AARCH64_{ABS64,PREL32,PREL64}` have been implemented by https://reviews.llvm.org/D120535 Pull Request: https://github.com/llvm/llvm-project/pull/87733 --- .../ELF/aarch64-reloc-implicit-addend.test | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 lld/test/ELF/aarch64-reloc-implicit-addend.test diff --git a/lld/test/ELF/aarch64-reloc-implicit-addend.test b/lld/test/ELF/aarch64-reloc-implicit-addend.test new file mode 100644 index 000000000000..15f42c4d87b5 --- /dev/null +++ b/lld/test/ELF/aarch64-reloc-implicit-addend.test @@ -0,0 +1,86 @@ +## Test certain REL relocation types generated by legacy armasm. +# RUN: yaml2obj %s -o %t.o +# RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s + +# CHECK-COUNT-17: internal linker error: cannot read addend + +--- +!ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_REL + Machine: EM_AARCH64 +Sections: + - Name: .abs + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + Content: fffffefffffffdfffffffffffffffcffffffffffffff + - Name: .rel.abs + Type: SHT_REL + Link: .symtab + Info: .abs + Relocations: + - {Offset: 0, Symbol: abs, Type: R_AARCH64_ABS16} + - {Offset: 2, Symbol: abs, Type: R_AARCH64_ABS32} + - {Offset: 6, Symbol: abs, Type: R_AARCH64_ABS64} + - {Offset: 14, Symbol: abs, Type: R_AARCH64_ADD_ABS_LO12_NC} + + - Name: .uabs + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + AddressAlign: 4 + Content: 00ffffff00ffffff00ffffff00ffffff00ffffff00ffffff + - Name: .rel.uabs + Type: SHT_REL + Link: .symtab + Info: .uabs + Relocations: + - {Offset: 0, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G0} + - {Offset: 4, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G0_NC} + - {Offset: 8, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G1} + - {Offset: 12, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G1_NC} + - {Offset: 16, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G2} + - {Offset: 20, Symbol: abs, Type: R_AARCH64_MOVW_UABS_G2_NC} + + - Name: .prel + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + AddressAlign: 4 + Content: 00ffffff00ffffff00ffffff00ffffff00ffffff00ffffff + - Name: .rel.prel + Type: SHT_REL + Link: .symtab + Info: .prel + Relocations: + - {Offset: 0, Symbol: .prel, Type: R_AARCH64_PREL64} + - {Offset: 4, Symbol: .prel, Type: R_AARCH64_PREL32} + - {Offset: 8, Symbol: .prel, Type: R_AARCH64_PREL16} + - {Offset: 12, Symbol: .prel, Type: R_AARCH64_LD_PREL_LO19} + - {Offset: 16, Symbol: .prel, Type: R_AARCH64_ADR_PREL_PG_HI21} + - {Offset: 20, Symbol: .prel, Type: R_AARCH64_ADR_PREL_PG_HI21_NC} + + - Name: .branch + Type: SHT_PROGBITS + Flags: [ SHF_ALLOC ] + AddressAlign: 4 + Content: f0fffffff0fffffff0fffffff0ffffff + - Name: .rel.branch + Type: SHT_REL + Link: .symtab + Info: .branch + Relocations: + - {Offset: 0, Symbol: .branch, Type: R_AARCH64_TSTBR14} + - {Offset: 4, Symbol: .branch, Type: R_AARCH64_CONDBR19} + - {Offset: 8, Symbol: .branch, Type: R_AARCH64_CALL26} + - {Offset: 12, Symbol: .branch, Type: R_AARCH64_JUMP26} + +Symbols: + - Name: .branch + Section: .branch + - Name: .prel + Section: .prel + - Name: abs + Index: SHN_ABS + Value: 42 + Binding: STB_GLOBAL -- GitLab From 2606c87788153bf33d854fa5c3a03e16d544c5d7 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Fri, 5 Apr 2024 14:04:29 -0400 Subject: [PATCH 014/695] [C99] Claim conformance to WG14 N717 (#87228) This was the paper that added Universal Character Names to C. --- clang/test/C/C99/n717.c | 75 +++++++++++++++++++++++++++++++++++++++++ clang/www/c_status.html | 2 +- 2 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 clang/test/C/C99/n717.c diff --git a/clang/test/C/C99/n717.c b/clang/test/C/C99/n717.c new file mode 100644 index 000000000000..25010b413706 --- /dev/null +++ b/clang/test/C/C99/n717.c @@ -0,0 +1,75 @@ +// RUN: %clang_cc1 -verify -std=c99 %s +// RUN: %clang_cc1 -verify -std=c99 -fno-dollars-in-identifiers %s + +/* WG14 N717: Clang 17 + * Extended identifiers + */ + +// Used as a sink for UCNs. +#define M(arg) + +// C99 6.4.3p1 specifies the grammar for UCNs. A \u must be followed by exactly +// four hex digits, and \U must be followed by exactly eight. +M(\u1) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\u12) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\u123) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\u1234) // Okay +M(\u12345)// Okay, two tokens (UCN followed by 5) + +M(\U1) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\U12) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\U123) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\U1234) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} \ + expected-note {{did you mean to use '\u'?}} +M(\U12345) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\U123456) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\U1234567) // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} +M(\U12345678) // Okay +M(\U123456789) // Okay-ish, two tokens (valid-per-spec-but-actually-invalid UCN followed by 9) + +// Now test the ones that should work. Note, these work in C17 and earlier but +// are part of the basic character set in C23 and thus should be diagnosed in +// that mode. They're valid in a character constant, but not valid in an +// identifier, except for U+0024 which is allowed if -fdollars-in-identifiers +// is enabled. +// FIXME: These three should be handled the same way, and should be accepted +// when dollar signs are allowed in identifiers, rather than rejected, see +// GH87106. +M(\u0024) // expected-error {{character '$' cannot be specified by a universal character name}} +M(\U00000024) // expected-error {{character '$' cannot be specified by a universal character name}} +M($) + +// These should always be rejected because they're not valid identifier +// characters. +// FIXME: the diagnostic could be improved to make it clear this is an issue +// with forming an identifier rather than a UCN. +M(\u0040) // expected-error {{character '@' cannot be specified by a universal character name}} +M(\u0060) // expected-error {{character '`' cannot be specified by a universal character name}} +M(\U00000040) // expected-error {{character '@' cannot be specified by a universal character name}} +M(\U00000060) // expected-error {{character '`' cannot be specified by a universal character name}} + +// UCNs outside of identifiers are handled in Phase 5 of translation, so we +// cannot use the macro expansion to test their behavior. + +// This is outside of the range of values specified by ISO 10646. +const char *c1 = "\U00110000"; // expected-error {{invalid universal character}} +// This does not fall outside of the range +const char *c2 = "\U0010FFFF"; + +// These should always be accepted because they're a valid in a character +// constant. +int c3 = '\u0024'; +int c4 = '\u0040'; +int c5 = '\u0060'; + +int c6 = '\U00000024'; +int c7 = '\U00000040'; +int c8 = '\U00000060'; + +// Valid lone surrogates. +M(\uD799) +const char *c9 = "\U0000E000"; + +// Invalid lone surrogates, which are excluded explicitly by 6.4.3p2. +M(\uD800) // expected-error {{invalid universal character}} +const char *c10 = "\U0000DFFF"; // expected-error {{invalid universal character}} diff --git a/clang/www/c_status.html b/clang/www/c_status.html index bc27b20ce648..7ee1d2b507e8 100644 --- a/clang/www/c_status.html +++ b/clang/www/c_status.html @@ -203,7 +203,7 @@ conformance.

extended identifiers N717 - Unknown + Clang 17 hexadecimal floating-point constants -- GitLab From 9264c85b47d3866c44f916cfff533c0d9d9d7a8d Mon Sep 17 00:00:00 2001 From: Haojian Wu Date: Fri, 5 Apr 2024 20:16:54 +0200 Subject: [PATCH 015/695] [Sema] Remove the duplicated `DeduceTemplateArguments` for partial specialization, NFC (#87782) We have two identical "DeduceTemplateArguments" implementations for class and variable partial template specializations, this patch removes the duplicated code. --- clang/lib/Sema/SemaTemplateDeduction.cpp | 85 +++++++----------------- 1 file changed, 24 insertions(+), 61 deletions(-) diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index 716660244537..0b6375001f53 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -3140,13 +3140,15 @@ static TemplateDeductionResult FinishTemplateArgumentDeduction( return TemplateDeductionResult::Success; } -/// Perform template argument deduction to determine whether -/// the given template arguments match the given class template -/// partial specialization per C++ [temp.class.spec.match]. -TemplateDeductionResult -Sema::DeduceTemplateArguments(ClassTemplatePartialSpecializationDecl *Partial, - ArrayRef TemplateArgs, - TemplateDeductionInfo &Info) { +/// Perform template argument deduction to determine whether the given template +/// arguments match the given class or variable template partial specialization +/// per C++ [temp.class.spec.match]. +template +static std::enable_if_t::value, + TemplateDeductionResult> +DeduceTemplateArguments(Sema &S, T *Partial, + ArrayRef TemplateArgs, + TemplateDeductionInfo &Info) { if (Partial->isInvalidDecl()) return TemplateDeductionResult::Invalid; @@ -3158,25 +3160,25 @@ Sema::DeduceTemplateArguments(ClassTemplatePartialSpecializationDecl *Partial, // Unevaluated SFINAE context. EnterExpressionEvaluationContext Unevaluated( - *this, Sema::ExpressionEvaluationContext::Unevaluated); - SFINAETrap Trap(*this); + S, Sema::ExpressionEvaluationContext::Unevaluated); + Sema::SFINAETrap Trap(S); // This deduction has no relation to any outer instantiation we might be // performing. - LocalInstantiationScope InstantiationScope(*this); + LocalInstantiationScope InstantiationScope(S); SmallVector Deduced; Deduced.resize(Partial->getTemplateParameters()->size()); if (TemplateDeductionResult Result = ::DeduceTemplateArguments( - *this, Partial->getTemplateParameters(), + S, Partial->getTemplateParameters(), Partial->getTemplateArgs().asArray(), TemplateArgs, Info, Deduced, /*NumberOfArgumentsMustMatch=*/false); Result != TemplateDeductionResult::Success) return Result; SmallVector DeducedArgs(Deduced.begin(), Deduced.end()); - InstantiatingTemplate Inst(*this, Info.getLocation(), Partial, DeducedArgs, - Info); + Sema::InstantiatingTemplate Inst(S, Info.getLocation(), Partial, DeducedArgs, + Info); if (Inst.isInvalid()) return TemplateDeductionResult::InstantiationDepth; @@ -3184,64 +3186,25 @@ Sema::DeduceTemplateArguments(ClassTemplatePartialSpecializationDecl *Partial, return TemplateDeductionResult::SubstitutionFailure; TemplateDeductionResult Result; - runWithSufficientStackSpace(Info.getLocation(), [&] { - Result = ::FinishTemplateArgumentDeduction(*this, Partial, + S.runWithSufficientStackSpace(Info.getLocation(), [&] { + Result = ::FinishTemplateArgumentDeduction(S, Partial, /*IsPartialOrdering=*/false, TemplateArgs, Deduced, Info); }); return Result; } -/// Perform template argument deduction to determine whether -/// the given template arguments match the given variable template -/// partial specialization per C++ [temp.class.spec.match]. +TemplateDeductionResult +Sema::DeduceTemplateArguments(ClassTemplatePartialSpecializationDecl *Partial, + ArrayRef TemplateArgs, + TemplateDeductionInfo &Info) { + return ::DeduceTemplateArguments(*this, Partial, TemplateArgs, Info); +} TemplateDeductionResult Sema::DeduceTemplateArguments(VarTemplatePartialSpecializationDecl *Partial, ArrayRef TemplateArgs, TemplateDeductionInfo &Info) { - if (Partial->isInvalidDecl()) - return TemplateDeductionResult::Invalid; - - // C++ [temp.class.spec.match]p2: - // A partial specialization matches a given actual template - // argument list if the template arguments of the partial - // specialization can be deduced from the actual template argument - // list (14.8.2). - - // Unevaluated SFINAE context. - EnterExpressionEvaluationContext Unevaluated( - *this, Sema::ExpressionEvaluationContext::Unevaluated); - SFINAETrap Trap(*this); - - // This deduction has no relation to any outer instantiation we might be - // performing. - LocalInstantiationScope InstantiationScope(*this); - - SmallVector Deduced; - Deduced.resize(Partial->getTemplateParameters()->size()); - if (TemplateDeductionResult Result = ::DeduceTemplateArguments( - *this, Partial->getTemplateParameters(), - Partial->getTemplateArgs().asArray(), TemplateArgs, Info, Deduced, - /*NumberOfArgumentsMustMatch=*/false); - Result != TemplateDeductionResult::Success) - return Result; - - SmallVector DeducedArgs(Deduced.begin(), Deduced.end()); - InstantiatingTemplate Inst(*this, Info.getLocation(), Partial, DeducedArgs, - Info); - if (Inst.isInvalid()) - return TemplateDeductionResult::InstantiationDepth; - - if (Trap.hasErrorOccurred()) - return TemplateDeductionResult::SubstitutionFailure; - - TemplateDeductionResult Result; - runWithSufficientStackSpace(Info.getLocation(), [&] { - Result = ::FinishTemplateArgumentDeduction(*this, Partial, - /*IsPartialOrdering=*/false, - TemplateArgs, Deduced, Info); - }); - return Result; + return ::DeduceTemplateArguments(*this, Partial, TemplateArgs, Info); } /// Determine whether the given type T is a simple-template-id type. -- GitLab From 66b528078e4852412769375e35d2a672bf36a0ec Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Fri, 5 Apr 2024 14:29:26 -0400 Subject: [PATCH 016/695] [SLP]Improve minbitwidth analysis for abs/smin/smax/umin/umax intrinsics. https://alive2.llvm.org/ce/z/ivPZ26 for the abs transformations. Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/86135 --- .../Transforms/Vectorize/SLPVectorizer.cpp | 102 +++++++++++++++--- .../X86/call-arg-reduced-by-minbitwidth.ll | 4 +- .../cmp-after-intrinsic-call-minbitwidth.ll | 12 ++- .../X86/store-abs-minbitwidth.ll | 9 +- 4 files changed, 100 insertions(+), 27 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 332877f35081..731d7b4edfa3 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -7056,19 +7056,16 @@ bool BoUpSLP::areAllUsersVectorized( static std::pair getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, - TargetTransformInfo *TTI, TargetLibraryInfo *TLI) { + TargetTransformInfo *TTI, TargetLibraryInfo *TLI, + ArrayRef ArgTys) { Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); // Calculate the cost of the scalar and vector calls. - SmallVector VecTys; - for (Use &Arg : CI->args()) - VecTys.push_back( - FixedVectorType::get(Arg->getType(), VecTy->getNumElements())); FastMathFlags FMF; if (auto *FPCI = dyn_cast(CI)) FMF = FPCI->getFastMathFlags(); SmallVector Arguments(CI->args()); - IntrinsicCostAttributes CostAttrs(ID, VecTy, Arguments, VecTys, FMF, + IntrinsicCostAttributes CostAttrs(ID, VecTy, Arguments, ArgTys, FMF, dyn_cast(CI)); auto IntrinsicCost = TTI->getIntrinsicInstrCost(CostAttrs, TTI::TCK_RecipThroughput); @@ -7081,8 +7078,8 @@ getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, if (!CI->isNoBuiltin() && VecFunc) { // Calculate the cost of the vector library call. // If the corresponding vector call is cheaper, return its cost. - LibCost = TTI->getCallInstrCost(nullptr, VecTy, VecTys, - TTI::TCK_RecipThroughput); + LibCost = + TTI->getCallInstrCost(nullptr, VecTy, ArgTys, TTI::TCK_RecipThroughput); } return {IntrinsicCost, LibCost}; } @@ -8508,6 +8505,30 @@ TTI::CastContextHint BoUpSLP::getCastContextHint(const TreeEntry &TE) const { return TTI::CastContextHint::None; } +/// Builds the arguments types vector for the given call instruction with the +/// given \p ID for the specified vector factor. +static SmallVector buildIntrinsicArgTypes(const CallInst *CI, + const Intrinsic::ID ID, + const unsigned VF, + unsigned MinBW) { + SmallVector ArgTys; + for (auto [Idx, Arg] : enumerate(CI->args())) { + if (ID != Intrinsic::not_intrinsic) { + if (isVectorIntrinsicWithScalarOpAtArg(ID, Idx)) { + ArgTys.push_back(Arg->getType()); + continue; + } + if (MinBW > 0) { + ArgTys.push_back(FixedVectorType::get( + IntegerType::get(CI->getContext(), MinBW), VF)); + continue; + } + } + ArgTys.push_back(FixedVectorType::get(Arg->getType(), VF)); + } + return ArgTys; +} + InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, SmallPtrSetImpl &CheckedExtracts) { @@ -9074,7 +9095,11 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, }; auto GetVectorCost = [=](InstructionCost CommonCost) { auto *CI = cast(VL0); - auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI); + Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); + SmallVector ArgTys = + buildIntrinsicArgTypes(CI, ID, VecTy->getNumElements(), + It != MinBWs.end() ? It->second.first : 0); + auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI, ArgTys); return std::min(VecCallCosts.first, VecCallCosts.second) + CommonCost; }; return GetCostDiff(GetScalarCost, GetVectorCost); @@ -12546,7 +12571,10 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); - auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI); + SmallVector ArgTys = + buildIntrinsicArgTypes(CI, ID, VecTy->getNumElements(), + It != MinBWs.end() ? It->second.first : 0); + auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI, ArgTys); bool UseIntrinsic = ID != Intrinsic::not_intrinsic && VecCallCosts.first <= VecCallCosts.second; @@ -12555,8 +12583,7 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { SmallVector TysForDecl; // Add return type if intrinsic is overloaded on it. if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1)) - TysForDecl.push_back( - FixedVectorType::get(CI->getType(), E->Scalars.size())); + TysForDecl.push_back(VecTy); auto *CEI = cast(VL0); for (unsigned I : seq(0, CI->arg_size())) { ValueList OpVL; @@ -12564,7 +12591,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { // vectorized. if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) { ScalarArg = CEI->getArgOperand(I); - OpVecs.push_back(CEI->getArgOperand(I)); + // if decided to reduce bitwidth of abs intrinsic, it second argument + // must be set false (do not return poison, if value issigned min). + if (ID == Intrinsic::abs && It != MinBWs.end() && + It->second.first < DL->getTypeSizeInBits(CEI->getType())) + ScalarArg = Builder.getFalse(); + OpVecs.push_back(ScalarArg); if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I)) TysForDecl.push_back(ScalarArg->getType()); continue; @@ -12577,10 +12609,13 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { } ScalarArg = CEI->getArgOperand(I); if (cast(OpVec->getType())->getElementType() != - ScalarArg->getType()) { + ScalarArg->getType() && + It == MinBWs.end()) { auto *CastTy = FixedVectorType::get(ScalarArg->getType(), VecTy->getNumElements()); OpVec = Builder.CreateIntCast(OpVec, CastTy, GetOperandSignedness(I)); + } else if (It != MinBWs.end()) { + OpVec = Builder.CreateIntCast(OpVec, VecTy, GetOperandSignedness(I)); } LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n"); OpVecs.push_back(OpVec); @@ -14324,6 +14359,45 @@ bool BoUpSLP::collectValuesToDemote( return TryProcessInstruction(I, *ITE, BitWidth, Ops); } + case Instruction::Call: { + auto *IC = dyn_cast(I); + if (!IC) + break; + Intrinsic::ID ID = getVectorIntrinsicIDForCall(IC, TLI); + if (ID != Intrinsic::abs && ID != Intrinsic::smin && + ID != Intrinsic::smax && ID != Intrinsic::umin && ID != Intrinsic::umax) + break; + SmallVector Operands(1, I->getOperand(0)); + End = 1; + if (ID != Intrinsic::abs) { + Operands.push_back(I->getOperand(1)); + End = 2; + } + InstructionCost BestCost = + std::numeric_limits::max(); + unsigned BestBitWidth = BitWidth; + unsigned VF = ITE->Scalars.size(); + // Choose the best bitwidth based on cost estimations. + auto Checker = [&](unsigned BitWidth, unsigned) { + unsigned MinBW = PowerOf2Ceil(BitWidth); + SmallVector ArgTys = buildIntrinsicArgTypes(IC, ID, VF, MinBW); + auto VecCallCosts = getVectorCallCosts( + IC, + FixedVectorType::get(IntegerType::get(IC->getContext(), MinBW), VF), + TTI, TLI, ArgTys); + InstructionCost Cost = std::min(VecCallCosts.first, VecCallCosts.second); + if (Cost < BestCost) { + BestCost = Cost; + BestBitWidth = BitWidth; + } + return false; + }; + [[maybe_unused]] bool NeedToExit; + (void)AttemptCheckBitwidth(Checker, NeedToExit); + BitWidth = BestBitWidth; + return TryProcessInstruction(I, *ITE, BitWidth, Operands); + } + // Otherwise, conservatively give up. default: break; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll index 27c9655f94d3..82966124d3ba 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll @@ -11,9 +11,7 @@ define void @test(ptr %0, i8 %1, i1 %cmp12.i) { ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <8 x i32> zeroinitializer ; CHECK-NEXT: br label [[PRE:%.*]] ; CHECK: pre: -; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i32> -; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[TMP6]], <8 x i32> ) -; CHECK-NEXT: [[TMP8:%.*]] = trunc <8 x i32> [[TMP7]] to <8 x i8> +; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP5]], <8 x i8> ) ; CHECK-NEXT: [[TMP9:%.*]] = add <8 x i8> [[TMP8]], ; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x i8> [[TMP9]], <8 x i8> [[TMP5]] ; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[TMP0]], align 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll index a05d4fdd6315..9fa88084aaa0 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll @@ -5,12 +5,14 @@ define void @test() { ; CHECK-LABEL: define void @test( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> zeroinitializer, <2 x i32> zeroinitializer) -; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[ADD:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1 +; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i2> @llvm.smin.v2i2(<2 x i2> zeroinitializer, <2 x i2> zeroinitializer) +; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i2> zeroinitializer, <2 x i2> [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i2> [[TMP1]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i2> [[TMP2]], i32 1 +; CHECK-NEXT: [[ADD:%.*]] = zext i2 [[TMP3]] to i32 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[ADD]], 0 -; CHECK-NEXT: [[ADD45:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i2> [[TMP2]], i32 0 +; CHECK-NEXT: [[ADD45:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[ADD152:%.*]] = or i32 [[ADD45]], [[ADD]] ; CHECK-NEXT: [[IDXPROM153:%.*]] = sext i32 [[ADD152]] to i64 ; CHECK-NEXT: [[ARRAYIDX154:%.*]] = getelementptr i8, ptr null, i64 [[IDXPROM153]] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll index e8b854b7cea6..df7312e3d2b5 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll @@ -13,14 +13,13 @@ define i32 @test(ptr noalias %in, ptr noalias %inn, ptr %out) { ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP3]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i8> [[TMP2]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i8> [[TMP5]], <4 x i8> [[TMP6]], <4 x i32> -; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i16> ; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> [[TMP10]], <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i32> -; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i32> [[TMP12]], [[TMP8]] -; CHECK-NEXT: [[TMP14:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP13]], i1 true) -; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16> +; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i16> +; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i16> [[TMP12]], [[TMP8]] +; CHECK-NEXT: [[TMP15:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP13]], i1 false) ; CHECK-NEXT: store <4 x i16> [[TMP15]], ptr [[OUT:%.*]], align 2 ; CHECK-NEXT: ret i32 undef ; -- GitLab From e4169f79ef0f54676c0072e1704c3d02f32925b3 Mon Sep 17 00:00:00 2001 From: David Green Date: Fri, 5 Apr 2024 19:33:22 +0100 Subject: [PATCH 017/695] [AArch64] Add extra zip and uzp shuffle cost tests. NFC --- .../CostModel/AArch64/shuffle-other.ll | 191 ++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll index 776c80c4bd1e..90ec92a35a1c 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll @@ -167,6 +167,197 @@ define void @insert_subvec() { ret void } +define void @zip() { +; CHECK-LABEL: 'zip' +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %zipv2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %zip1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %zip2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %zip1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %zip2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %zipv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %zipv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %zip1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %zip2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %zipv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zipv4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zip1v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zip2v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zipv8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zip1v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zip2v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zipv2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zip1v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zip2v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zipv4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zip1v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zip2v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zip1v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zip2v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %zipv16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %zip1v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> + %zip2v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> + %zipv2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> + %zip1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> + %zip2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> + %zipv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> + %zip1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> + %zip2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> + %zipv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> + %zip1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> + %zip2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> + %zipv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> + + %zip1v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> + %zip2v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> + %zipv2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> + %zip1v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> + %zip2v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> + %zipv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> + %zip1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> + %zip2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> + %zipv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> + %zip1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> + %zip2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> + %zipv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> + + %zip1v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> + %zip2v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> + %zipv2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> + %zip1v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> + %zip2v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> + %zipv4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> + %zip1v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> + %zip2v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> + %zipv8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> + %zip1v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> + %zip2v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> + %zipv16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> + + %zip1v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> + %zip2v2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <2 x i32> + %zipv2i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> + %zip1v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> + %zip2v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> + %zipv4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <8 x i32> + %zip1v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> + %zip2v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> + %zipv8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <16 x i32> + %zip1v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> + %zip2v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> + %zipv16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> + + ret void +} + +define void @uzp() { +; CHECK-LABEL: 'uzp' +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %uzp1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %uzp2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %uzp1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %uzp2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %uzpv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %uzpv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %uzp1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %uzp2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %uzpv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzpv4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzp1v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzp2v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzpv8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzp1v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzp2v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzp1v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzp2v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzpv4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzp1v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzp2v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzp1v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzp2v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %uzpv16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %uzp1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> + %uzp2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> + %uzpv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> + %uzp1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> + %uzp2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> + %uzpv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> + %uzp1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> + %uzp2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> + %uzpv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> + + %uzp1v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> + %uzp2v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> + %uzpv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> + %uzp1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> + %uzp2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> + %uzpv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> + %uzp1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> + %uzp2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> + %uzpv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> + + %uzp1v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> + %uzp2v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> + %uzpv4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> + %uzp1v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> + %uzp2v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> + %uzpv8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> + %uzp1v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> + %uzp2v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> + %uzpv16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> + + %uzp1v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> + %uzp2v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> + %uzpv4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <8 x i32> + %uzp1v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> + %uzp2v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> + %uzpv8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <16 x i32> + %uzp1v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> + %uzp2v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> + %uzpv16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> + + ret void +} + + define void @multipart() { ; CHECK-LABEL: 'multipart' ; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v16a = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -- GitLab From 225e14e5b6d64e1f63da39fa7fe31d2ebb08260d Mon Sep 17 00:00:00 2001 From: Dmitry Vasilyev Date: Fri, 5 Apr 2024 22:40:07 +0400 Subject: [PATCH 018/695] [Support][Windows] Use the original path if GetFinalPathNameByHandleW() failed (#87749) The commit f11b056c (#76304) breaks `clang` and other tools if they are used from a RAMDrive. `GetFinalPathNameByHandleW()` may return 0 and GetLastError 0x28. This patch fixes that issue. Note `real_path()` uses `openFileForRead()` but it reports the error only if failed to open a file. Getting `RealPath` is optional functionality. BTW, `sys::fs::real_path()` resolves not only symlinks, but also network drives and virtual drives created by the `subst` tool. It may break an automation. It is better to detect symlinks and resolve only symlinks. --- llvm/lib/Support/Windows/Path.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc index 854d531ab371..4f0336a85daa 100644 --- a/llvm/lib/Support/Windows/Path.inc +++ b/llvm/lib/Support/Windows/Path.inc @@ -157,7 +157,9 @@ std::string getMainExecutable(const char *argv0, void *MainExecAddr) { SmallString<256> RealPath; sys::fs::real_path(PathNameUTF8, RealPath); - return std::string(RealPath); + if (RealPath.size()) + return std::string(RealPath); + return std::string(PathNameUTF8.data()); } UniqueID file_status::getUniqueID() const { -- GitLab From 0a0fccfc6c0519402a2566e1f63440410e524d17 Mon Sep 17 00:00:00 2001 From: Chris B Date: Fri, 5 Apr 2024 13:46:14 -0500 Subject: [PATCH 019/695] [HLSL] Implement floating literal suffixes (#87270) This change implements the HLSL floating literal suffixes for half and double literals. The PR for the HLSL language specification for this behavior is https://github.com/microsoft/hlsl-specs/pull/175. The TL;DR is that the `h` suffix on floating literals means `half`, and the `l` suffix means `double`. The expected behavior and diagnostics are different if native half is supported. When native half is not enabled half is 32-bit so implicit conversions to float do not lose precision and do not warn. In all cases `half` and `float` are distinct types. Resolves #85712 --- clang/lib/Sema/SemaExpr.cpp | 5 +- clang/test/SemaHLSL/literal_suffixes.hlsl | 59 +++++++++++++++++++ .../SemaHLSL/literal_suffixes_no_16bit.hlsl | 59 +++++++++++++++++++ 3 files changed, 121 insertions(+), 2 deletions(-) create mode 100644 clang/test/SemaHLSL/literal_suffixes.hlsl create mode 100644 clang/test/SemaHLSL/literal_suffixes_no_16bit.hlsl diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 6b2eb245d582..ffe7e44e2387 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -4117,7 +4117,8 @@ ExprResult Sema::ActOnNumericConstant(const Token &Tok, Scope *UDLScope) { } else if (Literal.isFloatingLiteral()) { QualType Ty; if (Literal.isHalf){ - if (getOpenCLOptions().isAvailableOption("cl_khr_fp16", getLangOpts())) + if (getLangOpts().HLSL || + getOpenCLOptions().isAvailableOption("cl_khr_fp16", getLangOpts())) Ty = Context.HalfTy; else { Diag(Tok.getLocation(), diag::err_half_const_requires_fp16); @@ -4126,7 +4127,7 @@ ExprResult Sema::ActOnNumericConstant(const Token &Tok, Scope *UDLScope) { } else if (Literal.isFloat) Ty = Context.FloatTy; else if (Literal.isLong) - Ty = Context.LongDoubleTy; + Ty = !getLangOpts().HLSL ? Context.LongDoubleTy : Context.DoubleTy; else if (Literal.isFloat16) Ty = Context.Float16Ty; else if (Literal.isFloat128) diff --git a/clang/test/SemaHLSL/literal_suffixes.hlsl b/clang/test/SemaHLSL/literal_suffixes.hlsl new file mode 100644 index 000000000000..25a4d3b5103c --- /dev/null +++ b/clang/test/SemaHLSL/literal_suffixes.hlsl @@ -0,0 +1,59 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.2-library -fnative-half-type -Wconversion -verify %s + +void literal_assignments() { + half h; + + h = 2.0h; // No conversion, no diagnostic expected. + + // Literal conversions that don't lose precision also don't cause diagnostics. + // Conversion from double (no diagnostic expected) + h = 2.0l; + h = 2.0; + h = 2.0f; + + // Literal assignments with conversions that lose precision produce + // diagnostics under `-Wconversion`. + + // Lose precision on assignment. + h = 3.1415926535897932384626433h; // No diagnostic expected because this isn't a conversion. + + // Lose precision on assignment converting float to half. + h = 3.1415926535897932384626433f; // expected-warning {{implicit conversion loses floating-point precision: 'float' to 'half'}} + + // Lose precision on assignment converting float to half. + h = 3.1415926535897932384626433f * 2.0f; // expected-warning {{implicit conversion loses floating-point precision: 'float' to 'half'}} + + // Lose precision on assignment converting double to half. + h = 3.1415926535897932384626433l; // expected-warning {{implicit conversion loses floating-point precision: 'double' to 'half'}} + + // Lose precision on assignment converting double to half. + h = 3.1415926535897932384626433l * 2.0l; // expected-warning {{implicit conversion loses floating-point precision: 'double' to 'half'}} + + // Literal assinments of values out of the representable range produce + // warnings. + + h = 66000.h; // expected-warning {{magnitude of floating-point constant too large for type 'half'; maximum is 65504}} + h = -66000.h; // expected-warning {{magnitude of floating-point constant too large for type 'half'; maximum is 65504}} + + // The `h` suffix is invalid on integer literals. + h = 66000h; // expected-error {{invalid suffix 'h' on integer constant}} +} + +template +struct is_same { + static const bool value = false; +}; + +template +struct is_same { + static const bool value = true; +}; + +// The no-suffix behavior is currently wrong. The behavior in DXC is complicated +// and undocumented. We have a language change planned to address this, and an +// issue tracking: https://github.com/llvm/llvm-project/issues/85714. +_Static_assert(is_same::value, "1.0f literal is double (should be float)"); + +_Static_assert(is_same::value, "1.0h literal is half"); +_Static_assert(is_same::value, "1.0f literal is float"); +_Static_assert(is_same::value, "1.0l literal is double"); diff --git a/clang/test/SemaHLSL/literal_suffixes_no_16bit.hlsl b/clang/test/SemaHLSL/literal_suffixes_no_16bit.hlsl new file mode 100644 index 000000000000..73e57041329e --- /dev/null +++ b/clang/test/SemaHLSL/literal_suffixes_no_16bit.hlsl @@ -0,0 +1,59 @@ +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.2-library -Wconversion -verify %s + +void literal_assignments() { + half h; + + h = 2.0h; // No conversion, no diagnostic expected. + + // Literal conversions that don't lose precision also don't cause diagnostics. + // Conversion from double (no diagnostic expected) + h = 2.0l; + h = 2.0; + h = 2.0f; + + // Literal assignments with conversions that lose precision produce + // diagnostics under `-Wconversion`. + + // Lose precision on assignment. + h = 3.1415926535897932384626433h; // No diagnostic expected because this isn't a conversion. + + // Lose precision on assignment converting float to half. + h = 3.1415926535897932384626433f; // No diagnostic expected because half and float are the same size. + + // Lose precision on assignment converting float to half. + h = 3.1415926535897932384626433f * 2.0f; // No diagnostic expected because half and float are the same size. + + // Lose precision on assignment converting double to half. + h = 3.1415926535897932384626433l; // expected-warning {{implicit conversion loses floating-point precision: 'double' to 'half'}} + + // Lose precision on assignment converting double to half. + h = 3.1415926535897932384626433l * 2.0l; // expected-warning {{implicit conversion loses floating-point precision: 'double' to 'half'}} + + // Literal assinments of values out of the representable range produce + // warnings. + + h = 66000.h; // No diagnostic expected because half is 32-bit. + h = -66000.h; // No diagnostic expected because half is 32-bit. + + // The `h` suffix is invalid on integer literals. + h = 66000h; // expected-error {{invalid suffix 'h' on integer constant}} +} + +template +struct is_same { + static const bool value = false; +}; + +template +struct is_same { + static const bool value = true; +}; + +// The no-suffix behavior is currently wrong. The behavior in DXC is complicated +// and undocumented. We have a language change planned to address this, and an +// issue tracking: https://github.com/llvm/llvm-project/issues/85714. +_Static_assert(is_same::value, "1.0f literal is double (should be float)"); + +_Static_assert(is_same::value, "1.0h literal is half"); +_Static_assert(is_same::value, "1.0f literal is float"); +_Static_assert(is_same::value, "1.0l literal is double"); -- GitLab From 3989e2245746bbeaae26416a330753b9189cfaeb Mon Sep 17 00:00:00 2001 From: Daniil Kovalev Date: Fri, 5 Apr 2024 21:50:29 +0300 Subject: [PATCH 020/695] [test][lld][ELF] Enhance pack-dyn-relocs.s test (#87756) Use symbol `.data` (STT_SECTION) instead of `__ehdr_start` for some relocation entries. See discussion in [72714/#discussion_r1517127619](https://github.com/llvm/llvm-project/pull/72714/#discussion_r1517127619) --- lld/test/ELF/pack-dyn-relocs.s | 100 ++++++++++++++++----------------- 1 file changed, 50 insertions(+), 50 deletions(-) diff --git a/lld/test/ELF/pack-dyn-relocs.s b/lld/test/ELF/pack-dyn-relocs.s index 733ddd4ecad3..dd5d366ae234 100644 --- a/lld/test/ELF/pack-dyn-relocs.s +++ b/lld/test/ELF/pack-dyn-relocs.s @@ -198,24 +198,24 @@ // RUN: llvm-readobj -r %t2.a64 | FileCheck --check-prefix=UNPACKED64 %s // UNPACKED64: Section ({{.+}}) .rela.dyn { -// UNPACKED64-NEXT: 0x30690 R_AARCH64_RELATIVE - 0x0 -// UNPACKED64-NEXT: 0x30698 R_AARCH64_RELATIVE - 0x1 +// UNPACKED64-NEXT: 0x30690 R_AARCH64_RELATIVE - 0x30690 +// UNPACKED64-NEXT: 0x30698 R_AARCH64_RELATIVE - 0x30691 // UNPACKED64-NEXT: 0x306A0 R_AARCH64_RELATIVE - 0x2 // UNPACKED64-NEXT: 0x306A8 R_AARCH64_RELATIVE - 0xFFFFFFFFFFFFFFFF // UNPACKED64-NEXT: 0x306B0 R_AARCH64_RELATIVE - 0x80000000 // UNPACKED64-NEXT: 0x306B8 R_AARCH64_RELATIVE - 0x6 // UNPACKED64-NEXT: 0x306C0 R_AARCH64_RELATIVE - 0x7 -// UNPACKED64-NEXT: 0x306C8 R_AARCH64_RELATIVE - 0x8 +// UNPACKED64-NEXT: 0x306C8 R_AARCH64_RELATIVE - 0x30698 -// UNPACKED64-NEXT: 0x306D8 R_AARCH64_RELATIVE - 0x1 +// UNPACKED64-NEXT: 0x306D8 R_AARCH64_RELATIVE - 0x30691 // UNPACKED64-NEXT: 0x306E0 R_AARCH64_RELATIVE - 0x2 // UNPACKED64-NEXT: 0x306E8 R_AARCH64_RELATIVE - 0x3 // UNPACKED64-NEXT: 0x306F0 R_AARCH64_RELATIVE - 0x4 // UNPACKED64-NEXT: 0x306F8 R_AARCH64_RELATIVE - 0x5 // UNPACKED64-NEXT: 0x30700 R_AARCH64_RELATIVE - 0x6 -// UNPACKED64-NEXT: 0x30708 R_AARCH64_RELATIVE - 0x7 +// UNPACKED64-NEXT: 0x30708 R_AARCH64_RELATIVE - 0x30697 -// UNPACKED64-NEXT: 0x30720 R_AARCH64_RELATIVE - 0x1 +// UNPACKED64-NEXT: 0x30720 R_AARCH64_RELATIVE - 0x30691 // UNPACKED64-NEXT: 0x30728 R_AARCH64_RELATIVE - 0x2 // UNPACKED64-NEXT: 0x30730 R_AARCH64_RELATIVE - 0x3 // UNPACKED64-NEXT: 0x30738 R_AARCH64_RELATIVE - 0x4 @@ -223,9 +223,9 @@ // UNPACKED64-NEXT: 0x30748 R_AARCH64_RELATIVE - 0x6 // UNPACKED64-NEXT: 0x30750 R_AARCH64_RELATIVE - 0x7 // UNPACKED64-NEXT: 0x30758 R_AARCH64_RELATIVE - 0x8 -// UNPACKED64-NEXT: 0x30760 R_AARCH64_RELATIVE - 0x9 +// UNPACKED64-NEXT: 0x30760 R_AARCH64_RELATIVE - 0x30699 -// UNPACKED64-NEXT: 0x30769 R_AARCH64_RELATIVE - 0xA +// UNPACKED64-NEXT: 0x30769 R_AARCH64_RELATIVE - 0x3069A // UNPACKED64-NEXT: 0x306D0 R_AARCH64_ABS64 bar2 0x1 // UNPACKED64-NEXT: 0x30718 R_AARCH64_ABS64 bar2 0x0 @@ -247,7 +247,7 @@ // ANDROID64: (DEBUG) 0x0 // ANDROID64-NEXT: (ANDROID_RELA) 0x[[#ANDROID]] -// ANDROID64-NEXT: (ANDROID_RELASZ) 122 (bytes) +// ANDROID64-NEXT: (ANDROID_RELASZ) 136 (bytes) // ANDROID64-NEXT: (RELAENT) 24 (bytes) // ANDROID64-HEADERS: 0x0000000060000011 ANDROID_RELA [[ADDR]] @@ -255,39 +255,39 @@ // ANDROID64: Relocation section '.rela.dyn' at offset {{.*}} contains 33 entries: // ANDROID64-NEXT: Offset Info Type Symbol's Value Symbol's Name + Addend -// ANDROID64-NEXT: 00000000000303e8 0000000000000403 R_AARCH64_RELATIVE 0 -// ANDROID64-NEXT: 00000000000303f0 0000000000000403 R_AARCH64_RELATIVE 1 -// ANDROID64-NEXT: 00000000000303f8 0000000000000403 R_AARCH64_RELATIVE 2 -// ANDROID64-NEXT: 0000000000030400 0000000000000403 R_AARCH64_RELATIVE ffffffffffffffff -// ANDROID64-NEXT: 0000000000030408 0000000000000403 R_AARCH64_RELATIVE 80000000 -// ANDROID64-NEXT: 0000000000030410 0000000000000403 R_AARCH64_RELATIVE 6 -// ANDROID64-NEXT: 0000000000030418 0000000000000403 R_AARCH64_RELATIVE 7 -// ANDROID64-NEXT: 0000000000030420 0000000000000403 R_AARCH64_RELATIVE 8 -// ANDROID64-NEXT: 0000000000030478 0000000000000403 R_AARCH64_RELATIVE 1 -// ANDROID64-NEXT: 0000000000030480 0000000000000403 R_AARCH64_RELATIVE 2 -// ANDROID64-NEXT: 0000000000030488 0000000000000403 R_AARCH64_RELATIVE 3 -// ANDROID64-NEXT: 0000000000030490 0000000000000403 R_AARCH64_RELATIVE 4 -// ANDROID64-NEXT: 0000000000030498 0000000000000403 R_AARCH64_RELATIVE 5 -// ANDROID64-NEXT: 00000000000304a0 0000000000000403 R_AARCH64_RELATIVE 6 -// ANDROID64-NEXT: 00000000000304a8 0000000000000403 R_AARCH64_RELATIVE 7 -// ANDROID64-NEXT: 00000000000304b0 0000000000000403 R_AARCH64_RELATIVE 8 -// ANDROID64-NEXT: 00000000000304b8 0000000000000403 R_AARCH64_RELATIVE 9 -// ANDROID64-NEXT: 0000000000030430 0000000000000403 R_AARCH64_RELATIVE 1 -// ANDROID64-NEXT: 0000000000030438 0000000000000403 R_AARCH64_RELATIVE 2 -// ANDROID64-NEXT: 0000000000030440 0000000000000403 R_AARCH64_RELATIVE 3 -// ANDROID64-NEXT: 0000000000030448 0000000000000403 R_AARCH64_RELATIVE 4 -// ANDROID64-NEXT: 0000000000030450 0000000000000403 R_AARCH64_RELATIVE 5 -// ANDROID64-NEXT: 0000000000030458 0000000000000403 R_AARCH64_RELATIVE 6 -// ANDROID64-NEXT: 0000000000030460 0000000000000403 R_AARCH64_RELATIVE 7 -// ANDROID64-NEXT: 00000000000304c1 0000000000000403 R_AARCH64_RELATIVE a -// ANDROID64-NEXT: 0000000000030470 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 -// ANDROID64-NEXT: 00000000000304c9 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 +// ANDROID64-NEXT: 00000000000303f0 0000000000000403 R_AARCH64_RELATIVE 303f0 +// ANDROID64-NEXT: 00000000000303f8 0000000000000403 R_AARCH64_RELATIVE 303f1 +// ANDROID64-NEXT: 0000000000030400 0000000000000403 R_AARCH64_RELATIVE 2 +// ANDROID64-NEXT: 0000000000030408 0000000000000403 R_AARCH64_RELATIVE ffffffffffffffff +// ANDROID64-NEXT: 0000000000030410 0000000000000403 R_AARCH64_RELATIVE 80000000 +// ANDROID64-NEXT: 0000000000030418 0000000000000403 R_AARCH64_RELATIVE 6 +// ANDROID64-NEXT: 0000000000030420 0000000000000403 R_AARCH64_RELATIVE 7 +// ANDROID64-NEXT: 0000000000030428 0000000000000403 R_AARCH64_RELATIVE 303f8 +// ANDROID64-NEXT: 0000000000030480 0000000000000403 R_AARCH64_RELATIVE 303f1 +// ANDROID64-NEXT: 0000000000030488 0000000000000403 R_AARCH64_RELATIVE 2 +// ANDROID64-NEXT: 0000000000030490 0000000000000403 R_AARCH64_RELATIVE 3 +// ANDROID64-NEXT: 0000000000030498 0000000000000403 R_AARCH64_RELATIVE 4 +// ANDROID64-NEXT: 00000000000304a0 0000000000000403 R_AARCH64_RELATIVE 5 +// ANDROID64-NEXT: 00000000000304a8 0000000000000403 R_AARCH64_RELATIVE 6 +// ANDROID64-NEXT: 00000000000304b0 0000000000000403 R_AARCH64_RELATIVE 7 +// ANDROID64-NEXT: 00000000000304b8 0000000000000403 R_AARCH64_RELATIVE 8 +// ANDROID64-NEXT: 00000000000304c0 0000000000000403 R_AARCH64_RELATIVE 303f9 +// ANDROID64-NEXT: 0000000000030438 0000000000000403 R_AARCH64_RELATIVE 303f1 +// ANDROID64-NEXT: 0000000000030440 0000000000000403 R_AARCH64_RELATIVE 2 +// ANDROID64-NEXT: 0000000000030448 0000000000000403 R_AARCH64_RELATIVE 3 +// ANDROID64-NEXT: 0000000000030450 0000000000000403 R_AARCH64_RELATIVE 4 +// ANDROID64-NEXT: 0000000000030458 0000000000000403 R_AARCH64_RELATIVE 5 +// ANDROID64-NEXT: 0000000000030460 0000000000000403 R_AARCH64_RELATIVE 6 +// ANDROID64-NEXT: 0000000000030468 0000000000000403 R_AARCH64_RELATIVE 303f7 +// ANDROID64-NEXT: 00000000000304c9 0000000000000403 R_AARCH64_RELATIVE 303fa +// ANDROID64-NEXT: 0000000000030478 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 // ANDROID64-NEXT: 00000000000304d1 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 -// ANDROID64-NEXT: 00000000000304e9 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 -// ANDROID64-NEXT: 0000000000030428 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 1 -// ANDROID64-NEXT: 0000000000030468 0000000200000101 R_AARCH64_ABS64 0000000000000000 zed2 + 0 -// ANDROID64-NEXT: 00000000000304d9 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 1 +// ANDROID64-NEXT: 00000000000304d9 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 +// ANDROID64-NEXT: 00000000000304f1 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 +// ANDROID64-NEXT: 0000000000030430 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 1 +// ANDROID64-NEXT: 0000000000030470 0000000200000101 R_AARCH64_ABS64 0000000000000000 zed2 + 0 // ANDROID64-NEXT: 00000000000304e1 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 1 +// ANDROID64-NEXT: 00000000000304e9 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 1 // ANDROID64-EMPTY: // RUN: ld.lld -pie --pack-dyn-relocs=relr %t.a64.o %t.a64.so -o %t4.a64 @@ -317,7 +317,7 @@ /// Any relative relocations with odd offset stay in SHT_RELA. // RELR64: Relocation section '.rela.dyn' at offset {{.*}} contains 9 entries: // RELR64-NEXT: Offset Info Type Symbol's Value Symbol's Name + Addend -// RELR64-NEXT: 0000000000030569 0000000000000403 R_AARCH64_RELATIVE a +// RELR64-NEXT: 0000000000030569 0000000000000403 R_AARCH64_RELATIVE 3049a // RELR64-NEXT: 00000000000304d0 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 1 // RELR64-NEXT: 0000000000030518 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 // RELR64-NEXT: 0000000000030571 0000000100000101 R_AARCH64_ABS64 0000000000000000 bar2 + 0 @@ -355,33 +355,33 @@ // RELR64-NEXT: 0000000000030560 0000000000000403 R_AARCH64_RELATIVE // RELR64-EMPTY: // RELR64-NEXT: Hex dump of section '.data': -// RELR64-NEXT: 0x00030490 00000000 00000000 01000000 00000000 . +// RELR64-NEXT: 0x00030490 90040300 00000000 91040300 00000000 . // RELR64-NEXT: 0x000304a0 02000000 00000000 ffffffff ffffffff . // RELR64-NEXT: 0x000304b0 00000080 00000000 06000000 00000000 . .data .balign 2 -.dc.a __ehdr_start -.dc.a __ehdr_start + 1 +.dc.a .data +.dc.a .data + 1 .dc.a __ehdr_start + 2 .dc.a __ehdr_start - 1 .dc.a __ehdr_start + 0x80000000 .dc.a __ehdr_start + 6 .dc.a __ehdr_start + 7 -.dc.a __ehdr_start + 8 +.dc.a .data + 8 .dc.a bar2 + 1 -.dc.a __ehdr_start + 1 +.dc.a .data + 1 .dc.a __ehdr_start + 2 .dc.a __ehdr_start + 3 .dc.a __ehdr_start + 4 .dc.a __ehdr_start + 5 .dc.a __ehdr_start + 6 -.dc.a __ehdr_start + 7 +.dc.a .data + 7 .dc.a zed2 .dc.a bar2 -.dc.a __ehdr_start + 1 +.dc.a .data + 1 .dc.a __ehdr_start + 2 .dc.a __ehdr_start + 3 .dc.a __ehdr_start + 4 @@ -389,9 +389,9 @@ .dc.a __ehdr_start + 6 .dc.a __ehdr_start + 7 .dc.a __ehdr_start + 8 -.dc.a __ehdr_start + 9 +.dc.a .data + 9 .byte 00 -.dc.a __ehdr_start + 10 +.dc.a .data + 10 .dc.a bar2 .dc.a bar2 .dc.a bar2 + 1 -- GitLab From 3c37f926a153d38852d593c4a7f9062e72ee4b2f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 5 Apr 2024 11:19:33 -0700 Subject: [PATCH 021/695] [RISCV] Fix comment in compress-opt-branch.ll to match description. NFC Test description says constant does not fit in 12 bits, but the constant used was -2048 which does fit in 12 bits. Update to -2049. Also remove uses of -NOT in favor of positive checks. One of the -NOT should have been using RESBROPT instead of "c.beqz" so that it would check for the absense of the correct instruction based on the sed replacement on the RUN line. --- .../test/CodeGen/RISCV/compress-opt-branch.ll | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll index b6ae6419c4cd..354f180b45a9 100644 --- a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll +++ b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll @@ -270,9 +270,14 @@ if.end: ; constant is big and do not fit in 12 bit (imm), fit in i32 ; RV32IFDC-LABEL: : -; RV32IFDC-NOT: RESBROPT +; RV32IFDC: c.li [[REG:.*]], 0x1 +; RV32IFDC: c.slli [[REG]], 0xb +; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; nothing to check. +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG1:.*]], zero, 0x1 +; RV32IFD: slli [[REG2:.*]], [[REG1]], 0xb +; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] define i32 @f_big_ledge_pos(i32 %in0) minsize { %cmp = icmp CMPCOND i32 %in0, 2048 br i1 %cmp, label %if.then, label %if.else @@ -290,11 +295,16 @@ if.end: ; constant is big and do not fit in 12 bit (imm), fit in i32 ; RV32IFDC-LABEL: : -; RV32IFDC-NOT: c.beqz +; RV32IFDC: c.lui [[REG1:.*]], 0xfffff +; RV32IFDC: addi [[REG2:.*]], [[REG1]], 0x7ff +; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; nothing to check. +; RV32IFD-LABEL: : +; RV32IFD: lui [[REG1:.*]], 0xfffff +; RV32IFD: addi [[REG2:.*]], [[REG1]], 0x7ff +; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] define i32 @f_big_ledge_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -2048 + %cmp = icmp CMPCOND i32 %in0, -2049 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 -- GitLab From a834436099279e458112b8be653f4a597269747b Mon Sep 17 00:00:00 2001 From: Hristo Hristov Date: Fri, 5 Apr 2024 22:04:07 +0300 Subject: [PATCH 022/695] [libc++] P2872R3: Remove ``wstring_convert`` From C++26 (#87100) Implements: https://wg21.link/P2872R3 --- libcxx/docs/ReleaseNotes/19.rst | 4 ++++ libcxx/docs/Status/Cxx2cPapers.csv | 2 +- libcxx/docs/UsingLibcxx.rst | 8 ++++++-- libcxx/include/locale | 8 ++++++-- libcxx/modules/std/locale.inc | 5 +++++ .../fstreams/fstream.cons/wchar_pointer.pass.cpp | 2 +- .../fstreams/fstream.members/open_wchar_pointer.pass.cpp | 2 +- .../fstreams/ofstream.cons/wchar_pointer.pass.cpp | 2 +- .../fstreams/ofstream.members/open_wchar_pointer.pass.cpp | 2 +- .../conversions/conversions.string/ctor_move.pass.cpp | 2 +- .../conversions/conversions.buffer/ctor.pass.cpp | 2 +- .../conversions/conversions.buffer/overflow.pass.cpp | 2 +- .../conversions/conversions.buffer/pbackfail.pass.cpp | 2 +- .../conversions/conversions.buffer/rdbuf.pass.cpp | 2 +- .../conversions/conversions.buffer/seekoff.pass.cpp | 2 +- .../conversions/conversions.buffer/state.pass.cpp | 2 +- .../conversions/conversions.buffer/test.pass.cpp | 2 +- .../conversions/conversions.buffer/underflow.pass.cpp | 2 +- .../conversions/conversions.string/converted.pass.cpp | 2 +- .../conversions/conversions.string/ctor_codecvt.pass.cpp | 2 +- .../conversions.string/ctor_codecvt_state.pass.cpp | 2 +- .../conversions/conversions.string/ctor_copy.pass.cpp | 2 +- .../conversions.string/ctor_err_string.pass.cpp | 2 +- .../conversions/conversions.string/depr.verify.cpp | 2 ++ .../conversions/conversions.string/from_bytes.pass.cpp | 2 +- .../conversions/conversions.string/state.pass.cpp | 2 +- .../conversions/conversions.string/to_bytes.pass.cpp | 2 +- .../conversions/conversions.string/types.pass.cpp | 2 +- 28 files changed, 46 insertions(+), 27 deletions(-) diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 2da9df54a531..abf1570737df 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -43,6 +43,7 @@ Implemented Papers - P2819R2 - Add ``tuple`` protocol to ``complex`` - P2495R3 - Interfacing ``stringstream``\s with ``string_view`` - P2867R2 - Remove Deprecated ``strstream``\s From C++26 +- P2872R3 - Remove ``wstring_convert`` From C++26 - P2302R4 - ``std::ranges::contains`` - P1659R3 - ``std::ranges::starts_with`` and ``std::ranges::ends_with`` @@ -57,6 +58,9 @@ Improvements and New Features - The ``_LIBCPP_ENABLE_CXX26_REMOVED_STRSTREAM`` macro has been added to make the declarations in ```` available. +- The ``_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT`` macro has been added to make the declarations in ```` + available. + Deprecations and Removals ------------------------- diff --git a/libcxx/docs/Status/Cxx2cPapers.csv b/libcxx/docs/Status/Cxx2cPapers.csv index a34dad581680..af270150fda0 100644 --- a/libcxx/docs/Status/Cxx2cPapers.csv +++ b/libcxx/docs/Status/Cxx2cPapers.csv @@ -49,7 +49,7 @@ "`P2875R4 `__","LWG","Undeprecate ``polymorphic_allocator::destroy`` for C++26","Tokyo March 2024","|Complete|","15.0","" "`P2867R2 `__","LWG","Remove Deprecated ``strstreams`` From C++26","Tokyo March 2024","|Complete|","19.0","" "`P2869R4 `__","LWG","Remove Deprecated ``shared_ptr`` Atomic Access APIs from C++26","Tokyo March 2024","","","" -"`P2872R3 `__","LWG","Remove ``wstring_convert`` From C++26","Tokyo March 2024","","","" +"`P2872R3 `__","LWG","Remove ``wstring_convert`` From C++26","Tokyo March 2024","|Complete|","19.0","" "`P3107R5 `__","LWG","Permit an efficient implementation of ``std::print``","Tokyo March 2024","","","|format| |DR|" "`P3142R0 `__","LWG","Printing Blank Lines with ``println``","Tokyo March 2024","","","|format|" "`P2845R8 `__","LWG","Formatting of ``std::filesystem::path``","Tokyo March 2024","","","|format|" diff --git a/libcxx/docs/UsingLibcxx.rst b/libcxx/docs/UsingLibcxx.rst index 8a1c747a2541..bc7817d14d04 100644 --- a/libcxx/docs/UsingLibcxx.rst +++ b/libcxx/docs/UsingLibcxx.rst @@ -234,7 +234,7 @@ C++17 Specific Configuration Macros C++20 Specific Configuration Macros ----------------------------------- -**_LIBCPP_ENABLE_CXX20_REMOVED_SHARED_PTR_UNIQUE** +**_LIBCPP_ENABLE_CXX20_REMOVED_SHARED_PTR_UNIQUE**: This macro is used to re-enable the function ``std::shared_ptr<...>::unique()``. @@ -267,7 +267,7 @@ C++26 Specific Configuration Macros **_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT**: This macro is used to re-enable all named declarations in ````. -**_LIBCPP_ENABLE_CXX26_REMOVED_STRING_RESERVE** +**_LIBCPP_ENABLE_CXX26_REMOVED_STRING_RESERVE**: This macro is used to re-enable the function ``std::basic_string<...>::reserve()``. @@ -277,6 +277,10 @@ C++26 Specific Configuration Macros **_LIBCPP_ENABLE_CXX26_REMOVED_STRSTREAM**: This macro is used to re-enable all named declarations in ````. +**_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT**: + This macro is used to re-enable the ``wstring_convert`` and ``wbuffer_convert`` + in ````. + Libc++ Extensions ================= diff --git a/libcxx/include/locale b/libcxx/include/locale index e3c63e3abe13..748b276a8525 100644 --- a/libcxx/include/locale +++ b/libcxx/include/locale @@ -84,7 +84,7 @@ template charT tolower(charT c, const locale& loc); template, class Byte_alloc = allocator> -class wstring_convert +class wstring_convert // Removed in C++26 { public: typedef basic_string, Byte_alloc> byte_string; @@ -119,7 +119,7 @@ public: }; template > -class wbuffer_convert +class wbuffer_convert // Removed in C++26 : public basic_streambuf { public: @@ -3107,6 +3107,8 @@ extern template class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS messages_byname; extern template class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS messages_byname; #endif +#if _LIBCPP_STD_VER < 26 || defined(_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT) + template , @@ -3712,6 +3714,8 @@ wbuffer_convert<_Codecvt, _Elem, _Tr>* wbuffer_convert<_Codecvt, _Elem, _Tr>::__ _LIBCPP_SUPPRESS_DEPRECATED_POP +#endif // _LIBCPP_STD_VER < 26 || defined(_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT) + _LIBCPP_END_NAMESPACE_STD _LIBCPP_POP_MACROS diff --git a/libcxx/modules/std/locale.inc b/libcxx/modules/std/locale.inc index c34f56530e98..897545386422 100644 --- a/libcxx/modules/std/locale.inc +++ b/libcxx/modules/std/locale.inc @@ -67,10 +67,15 @@ export namespace std { using std::messages_base; using std::messages_byname; +# if _LIBCPP_STD_VER < 26 || defined(_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT) + // [depr.conversions.buffer] using std::wbuffer_convert; // [depr.conversions.string] using std::wstring_convert; + +# endif // _LIBCPP_STD_VER < 26 || defined(_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT) + #endif // _LIBCPP_HAS_NO_LOCALIZATION } // namespace std diff --git a/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.cons/wchar_pointer.pass.cpp b/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.cons/wchar_pointer.pass.cpp index c2b23bba421b..652783fc6513 100644 --- a/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.cons/wchar_pointer.pass.cpp +++ b/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.cons/wchar_pointer.pass.cpp @@ -18,7 +18,7 @@ // UNSUPPORTED: no-wide-characters // TODO: This should not be necessary -// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT #include #include diff --git a/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.members/open_wchar_pointer.pass.cpp b/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.members/open_wchar_pointer.pass.cpp index 9a5564fa9e11..b592492f8483 100644 --- a/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.members/open_wchar_pointer.pass.cpp +++ b/libcxx/test/libcxx/input.output/file.streams/fstreams/fstream.members/open_wchar_pointer.pass.cpp @@ -18,7 +18,7 @@ // UNSUPPORTED: no-wide-characters // TODO: This should not be necessary -// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT #include #include diff --git a/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.cons/wchar_pointer.pass.cpp b/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.cons/wchar_pointer.pass.cpp index 185ee9e5f96a..3730e73648d3 100644 --- a/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.cons/wchar_pointer.pass.cpp +++ b/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.cons/wchar_pointer.pass.cpp @@ -18,7 +18,7 @@ // UNSUPPORTED: no-wide-characters // TODO: This should not be necessary -// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT #include #include diff --git a/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.members/open_wchar_pointer.pass.cpp b/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.members/open_wchar_pointer.pass.cpp index 9403643ad6ab..bfbbd5322161 100644 --- a/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.members/open_wchar_pointer.pass.cpp +++ b/libcxx/test/libcxx/input.output/file.streams/fstreams/ofstream.members/open_wchar_pointer.pass.cpp @@ -18,7 +18,7 @@ // UNSUPPORTED: no-wide-characters // TODO: This should not be necessary -// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS:-D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT #include #include diff --git a/libcxx/test/libcxx/localization/locales/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp b/libcxx/test/libcxx/localization/locales/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp index 006bece21105..a536e6e9b04c 100644 --- a/libcxx/test/libcxx/localization/locales/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp +++ b/libcxx/test/libcxx/localization/locales/locale.convenience/conversions/conversions.string/ctor_move.pass.cpp @@ -10,7 +10,7 @@ // UNSUPPORTED: c++03 -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/ctor.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/ctor.pass.cpp index e99a85a87398..fbc0bb4ace3a 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/ctor.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/ctor.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/overflow.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/overflow.pass.cpp index 5a5a3f5a3462..91ebd9eb9b04 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/overflow.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/overflow.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/pbackfail.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/pbackfail.pass.cpp index 926f661a2d44..28e54cec366e 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/pbackfail.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/pbackfail.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/rdbuf.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/rdbuf.pass.cpp index cdbabafcdf5a..b53516b4df77 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/rdbuf.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/rdbuf.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/seekoff.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/seekoff.pass.cpp index 87d9061dd6df..1947e811c553 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/seekoff.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/seekoff.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/state.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/state.pass.cpp index fe77d9b3bcc8..6ae7c9d66d1e 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/state.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/state.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/test.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/test.pass.cpp index 01a112e03e8e..1a45036215c4 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/test.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/test.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/underflow.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/underflow.pass.cpp index 0e6f77fff9d1..65ec28cdd977 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/underflow.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.buffer/underflow.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wbuffer_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/converted.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/converted.pass.cpp index 9627d2ca3312..5585ec86d771 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/converted.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/converted.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt.pass.cpp index 76ccd1ac9f6d..90dd81885ac2 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt_state.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt_state.pass.cpp index 454576d8035d..e55b21169d54 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt_state.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_codecvt_state.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_copy.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_copy.pass.cpp index 3d7d8c601c1b..27f878463b97 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_copy.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_copy.pass.cpp @@ -12,7 +12,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_err_string.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_err_string.pass.cpp index e5da324196ff..937a276af04f 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_err_string.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/ctor_err_string.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/depr.verify.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/depr.verify.cpp index c520d34a2380..f8bd156bdd5f 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/depr.verify.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/depr.verify.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT + // UNSUPPORTED: c++03, c++11, c++14, c++26 // UNSUPPORTED: no-wide-characters diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/from_bytes.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/from_bytes.pass.cpp index f745cbc202d6..59939e1cf7c6 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/from_bytes.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/from_bytes.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/state.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/state.pass.cpp index d7e1989e6a17..f59730c5b29d 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/state.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/state.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/to_bytes.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/to_bytes.pass.cpp index 19ffdd57d2ec..8c5348477aee 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/to_bytes.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/to_bytes.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // wstring_convert diff --git a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/types.pass.cpp b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/types.pass.cpp index 1987a06a9048..bec4f7a1d802 100644 --- a/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/types.pass.cpp +++ b/libcxx/test/std/localization/locales/locale.convenience/conversions/conversions.string/types.pass.cpp @@ -8,7 +8,7 @@ // -// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS -D_LIBCPP_ENABLE_CXX26_REMOVED_CODECVT -D_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT // template, -- GitLab From 43ba568daac098b286e1c1207deadd1f59d56cd7 Mon Sep 17 00:00:00 2001 From: Daniel Paoliello Date: Fri, 5 Apr 2024 12:06:47 -0700 Subject: [PATCH 023/695] Prepend all library intrinsics with `#` when building for Arm64EC (#87542) While attempting to build some Rust code, I was getting linker errors due to missing functions that are implemented in `compiler-rt`. Turns out that when `compiler-rt` is built for Arm64EC, all its function names are mangled with the leading `#`. This change removes the hard-coded list of library-implemented intrinsics to mangle for Arm64EC, and instead assumes that they all must be mangled. --- .../Target/AArch64/AArch64ISelLowering.cpp | 42 ++++--------------- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 3 ++ 2 files changed, 11 insertions(+), 34 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b81688c35713..b10d8a80c8c9 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1716,40 +1716,14 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setMaxAtomicSizeInBitsSupported(128); if (Subtarget->isWindowsArm64EC()) { - // FIXME: are there other intrinsics we need to add here? - setLibcallName(RTLIB::MEMCPY, "#memcpy"); - setLibcallName(RTLIB::MEMSET, "#memset"); - setLibcallName(RTLIB::MEMMOVE, "#memmove"); - setLibcallName(RTLIB::REM_F32, "#fmodf"); - setLibcallName(RTLIB::REM_F64, "#fmod"); - setLibcallName(RTLIB::FMA_F32, "#fmaf"); - setLibcallName(RTLIB::FMA_F64, "#fma"); - setLibcallName(RTLIB::SQRT_F32, "#sqrtf"); - setLibcallName(RTLIB::SQRT_F64, "#sqrt"); - setLibcallName(RTLIB::CBRT_F32, "#cbrtf"); - setLibcallName(RTLIB::CBRT_F64, "#cbrt"); - setLibcallName(RTLIB::LOG_F32, "#logf"); - setLibcallName(RTLIB::LOG_F64, "#log"); - setLibcallName(RTLIB::LOG2_F32, "#log2f"); - setLibcallName(RTLIB::LOG2_F64, "#log2"); - setLibcallName(RTLIB::LOG10_F32, "#log10f"); - setLibcallName(RTLIB::LOG10_F64, "#log10"); - setLibcallName(RTLIB::EXP_F32, "#expf"); - setLibcallName(RTLIB::EXP_F64, "#exp"); - setLibcallName(RTLIB::EXP2_F32, "#exp2f"); - setLibcallName(RTLIB::EXP2_F64, "#exp2"); - setLibcallName(RTLIB::EXP10_F32, "#exp10f"); - setLibcallName(RTLIB::EXP10_F64, "#exp10"); - setLibcallName(RTLIB::SIN_F32, "#sinf"); - setLibcallName(RTLIB::SIN_F64, "#sin"); - setLibcallName(RTLIB::COS_F32, "#cosf"); - setLibcallName(RTLIB::COS_F64, "#cos"); - setLibcallName(RTLIB::POW_F32, "#powf"); - setLibcallName(RTLIB::POW_F64, "#pow"); - setLibcallName(RTLIB::LDEXP_F32, "#ldexpf"); - setLibcallName(RTLIB::LDEXP_F64, "#ldexp"); - setLibcallName(RTLIB::FREXP_F32, "#frexpf"); - setLibcallName(RTLIB::FREXP_F64, "#frexp"); + // FIXME: are there intrinsics we need to exclude from this? + for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { + auto code = static_cast(i); + auto libcallName = getLibcallName(code); + if ((libcallName != nullptr) && (libcallName[0] != '#')) { + setLibcallName(code, Saver.save(Twine("#") + libcallName).data()); + } + } } } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 3465f3be8875..18439dc7f010 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1003,6 +1003,9 @@ private: /// make the right decision when generating code for different targets. const AArch64Subtarget *Subtarget; + llvm::BumpPtrAllocator BumpAlloc; + llvm::StringSaver Saver{BumpAlloc}; + bool isExtFreeImpl(const Instruction *Ext) const override; void addTypeForNEON(MVT VT); -- GitLab From 5e77dfecd2e274117cc0a75de69c832d00130e6a Mon Sep 17 00:00:00 2001 From: Haojian Wu Date: Fri, 5 Apr 2024 21:07:14 +0200 Subject: [PATCH 024/695] [clang] CTAD: build aggregate deduction guides for alias templates. (#85904) Fixes https://github.com/llvm/llvm-project/issues/85767. The aggregate deduction guides are handled in a separate code path. We don't generate dedicated aggregate deduction guides for alias templates (we just reuse the ones from the underlying template decl by accident). The patch fixes this incorrect issue. Note: there is a small refactoring change in this PR, where we move the cache logic from `Sema::DeduceTemplateSpecializationFromInitializer` to `Sema::DeclareImplicitDeductionGuideFromInitList` --- clang/include/clang/Sema/Sema.h | 3 +- clang/lib/Sema/SemaInit.cpp | 28 +-- clang/lib/Sema/SemaTemplate.cpp | 209 +++++++++++++++----- clang/test/SemaTemplate/deduction-guide.cpp | 12 ++ 4 files changed, 182 insertions(+), 70 deletions(-) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 149b268311bc..f52816e12efe 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -9713,7 +9713,8 @@ public: /// not already done so. void DeclareImplicitDeductionGuides(TemplateDecl *Template, SourceLocation Loc); - FunctionTemplateDecl *DeclareImplicitDeductionGuideFromInitList( + + FunctionTemplateDecl *DeclareAggregateDeductionGuideFromInitList( TemplateDecl *Template, MutableArrayRef ParamTypes, SourceLocation Loc); diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index e2a1951f1062..a75e9925a431 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -10930,32 +10930,16 @@ QualType Sema::DeduceTemplateSpecializationFromInitializer( Context.getLValueReferenceType(ElementTypes[I].withConst()); } - llvm::FoldingSetNodeID ID; - ID.AddPointer(Template); - for (auto &T : ElementTypes) - T.getCanonicalType().Profile(ID); - unsigned Hash = ID.ComputeHash(); - if (AggregateDeductionCandidates.count(Hash) == 0) { - if (FunctionTemplateDecl *TD = - DeclareImplicitDeductionGuideFromInitList( - Template, ElementTypes, - TSInfo->getTypeLoc().getEndLoc())) { - auto *GD = cast(TD->getTemplatedDecl()); - GD->setDeductionCandidateKind(DeductionCandidate::Aggregate); - AggregateDeductionCandidates[Hash] = GD; - addDeductionCandidate(TD, GD, DeclAccessPair::make(TD, AS_public), - OnlyListConstructors, - /*AllowAggregateDeductionCandidate=*/true); - } - } else { - CXXDeductionGuideDecl *GD = AggregateDeductionCandidates[Hash]; - FunctionTemplateDecl *TD = GD->getDescribedFunctionTemplate(); - assert(TD && "aggregate deduction candidate is function template"); + if (FunctionTemplateDecl *TD = + DeclareAggregateDeductionGuideFromInitList( + LookupTemplateDecl, ElementTypes, + TSInfo->getTypeLoc().getEndLoc())) { + auto *GD = cast(TD->getTemplatedDecl()); addDeductionCandidate(TD, GD, DeclAccessPair::make(TD, AS_public), OnlyListConstructors, /*AllowAggregateDeductionCandidate=*/true); + HasAnyDeductionGuide = true; } - HasAnyDeductionGuide = true; } }; diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 0b75f4fb401e..73030cf4b722 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -2754,23 +2754,42 @@ bool hasDeclaredDeductionGuides(DeclarationName Name, DeclContext *DC) { return false; } -// Build deduction guides for a type alias template. -void DeclareImplicitDeductionGuidesForTypeAlias( - Sema &SemaRef, TypeAliasTemplateDecl *AliasTemplate, SourceLocation Loc) { - if (AliasTemplate->isInvalidDecl()) - return; - auto &Context = SemaRef.Context; - // FIXME: if there is an explicit deduction guide after the first use of the - // type alias usage, we will not cover this explicit deduction guide. fix this - // case. - if (hasDeclaredDeductionGuides( - Context.DeclarationNames.getCXXDeductionGuideName(AliasTemplate), - AliasTemplate->getDeclContext())) - return; +NamedDecl *transformTemplateParameter(Sema &SemaRef, DeclContext *DC, + NamedDecl *TemplateParam, + MultiLevelTemplateArgumentList &Args, + unsigned NewIndex) { + if (auto *TTP = dyn_cast(TemplateParam)) + return transformTemplateTypeParam(SemaRef, DC, TTP, Args, TTP->getDepth(), + NewIndex); + if (auto *TTP = dyn_cast(TemplateParam)) + return transformTemplateParam(SemaRef, DC, TTP, Args, NewIndex, + TTP->getDepth()); + if (auto *NTTP = dyn_cast(TemplateParam)) + return transformTemplateParam(SemaRef, DC, NTTP, Args, NewIndex, + NTTP->getDepth()); + llvm_unreachable("Unhandled template parameter types"); +} + +Expr *transformRequireClause(Sema &SemaRef, FunctionTemplateDecl *FTD, + llvm::ArrayRef TransformedArgs) { + Expr *RC = FTD->getTemplateParameters()->getRequiresClause(); + if (!RC) + return nullptr; + MultiLevelTemplateArgumentList Args; + Args.setKind(TemplateSubstitutionKind::Rewrite); + Args.addOuterTemplateArguments(TransformedArgs); + ExprResult E = SemaRef.SubstExpr(RC, Args); + if (E.isInvalid()) + return nullptr; + return E.getAs(); +} + +std::pair> +getRHSTemplateDeclAndArgs(Sema &SemaRef, TypeAliasTemplateDecl *AliasTemplate) { // Unwrap the sugared ElaboratedType. auto RhsType = AliasTemplate->getTemplatedDecl() ->getUnderlyingType() - .getSingleStepDesugaredType(Context); + .getSingleStepDesugaredType(SemaRef.Context); TemplateDecl *Template = nullptr; llvm::ArrayRef AliasRhsTemplateArgs; if (const auto *TST = RhsType->getAs()) { @@ -2791,6 +2810,24 @@ void DeclareImplicitDeductionGuidesForTypeAlias( } else { assert(false && "unhandled RHS type of the alias"); } + return {Template, AliasRhsTemplateArgs}; +} + +// Build deduction guides for a type alias template. +void DeclareImplicitDeductionGuidesForTypeAlias( + Sema &SemaRef, TypeAliasTemplateDecl *AliasTemplate, SourceLocation Loc) { + if (AliasTemplate->isInvalidDecl()) + return; + auto &Context = SemaRef.Context; + // FIXME: if there is an explicit deduction guide after the first use of the + // type alias usage, we will not cover this explicit deduction guide. fix this + // case. + if (hasDeclaredDeductionGuides( + Context.DeclarationNames.getCXXDeductionGuideName(AliasTemplate), + AliasTemplate->getDeclContext())) + return; + auto [Template, AliasRhsTemplateArgs] = + getRHSTemplateDeclAndArgs(SemaRef, AliasTemplate); if (!Template) return; DeclarationNameInfo NameInfo( @@ -2803,6 +2840,13 @@ void DeclareImplicitDeductionGuidesForTypeAlias( FunctionTemplateDecl *F = dyn_cast(G); if (!F) continue; + // The **aggregate** deduction guides are handled in a different code path + // (DeclareImplicitDeductionGuideFromInitList), which involves the tricky + // cache. + if (cast(F->getTemplatedDecl()) + ->getDeductionCandidateKind() == DeductionCandidate::Aggregate) + continue; + auto RType = F->getTemplatedDecl()->getReturnType(); // The (trailing) return type of the deduction guide. const TemplateSpecializationType *FReturnType = @@ -2885,21 +2929,6 @@ void DeclareImplicitDeductionGuidesForTypeAlias( // parameters, used for building `TemplateArgsForBuildingFPrime`. SmallVector TransformedDeducedAliasArgs( AliasTemplate->getTemplateParameters()->size()); - auto TransformTemplateParameter = - [&SemaRef](DeclContext *DC, NamedDecl *TemplateParam, - MultiLevelTemplateArgumentList &Args, - unsigned NewIndex) -> NamedDecl * { - if (auto *TTP = dyn_cast(TemplateParam)) - return transformTemplateTypeParam(SemaRef, DC, TTP, Args, - TTP->getDepth(), NewIndex); - if (auto *TTP = dyn_cast(TemplateParam)) - return transformTemplateParam(SemaRef, DC, TTP, Args, NewIndex, - TTP->getDepth()); - if (auto *NTTP = dyn_cast(TemplateParam)) - return transformTemplateParam(SemaRef, DC, NTTP, Args, NewIndex, - NTTP->getDepth()); - return nullptr; - }; for (unsigned AliasTemplateParamIdx : DeducedAliasTemplateParams) { auto *TP = AliasTemplate->getTemplateParameters()->getParam( @@ -2909,9 +2938,9 @@ void DeclareImplicitDeductionGuidesForTypeAlias( MultiLevelTemplateArgumentList Args; Args.setKind(TemplateSubstitutionKind::Rewrite); Args.addOuterTemplateArguments(TransformedDeducedAliasArgs); - NamedDecl *NewParam = - TransformTemplateParameter(AliasTemplate->getDeclContext(), TP, Args, - /*NewIndex*/ FPrimeTemplateParams.size()); + NamedDecl *NewParam = transformTemplateParameter( + SemaRef, AliasTemplate->getDeclContext(), TP, Args, + /*NewIndex*/ FPrimeTemplateParams.size()); FPrimeTemplateParams.push_back(NewParam); auto NewTemplateArgument = Context.getCanonicalTemplateArgument( @@ -2927,8 +2956,8 @@ void DeclareImplicitDeductionGuidesForTypeAlias( // We take a shortcut here, it is ok to reuse the // TemplateArgsForBuildingFPrime. Args.addOuterTemplateArguments(TemplateArgsForBuildingFPrime); - NamedDecl *NewParam = TransformTemplateParameter( - F->getDeclContext(), TP, Args, FPrimeTemplateParams.size()); + NamedDecl *NewParam = transformTemplateParameter( + SemaRef, F->getDeclContext(), TP, Args, FPrimeTemplateParams.size()); FPrimeTemplateParams.push_back(NewParam); assert(TemplateArgsForBuildingFPrime[FTemplateParamIdx].isNull() && @@ -2938,16 +2967,8 @@ void DeclareImplicitDeductionGuidesForTypeAlias( Context.getInjectedTemplateArg(NewParam)); } // Substitute new template parameters into requires-clause if present. - Expr *RequiresClause = nullptr; - if (Expr *InnerRC = F->getTemplateParameters()->getRequiresClause()) { - MultiLevelTemplateArgumentList Args; - Args.setKind(TemplateSubstitutionKind::Rewrite); - Args.addOuterTemplateArguments(TemplateArgsForBuildingFPrime); - ExprResult E = SemaRef.SubstExpr(InnerRC, Args); - if (E.isInvalid()) - return; - RequiresClause = E.getAs(); - } + Expr *RequiresClause = + transformRequireClause(SemaRef, F, TemplateArgsForBuildingFPrime); // FIXME: implement the is_deducible constraint per C++ // [over.match.class.deduct]p3.3: // ... and a constraint that is satisfied if and only if the arguments @@ -3013,11 +3034,102 @@ void DeclareImplicitDeductionGuidesForTypeAlias( } } +// Build an aggregate deduction guide for a type alias template. +FunctionTemplateDecl *DeclareAggregateDeductionGuideForTypeAlias( + Sema &SemaRef, TypeAliasTemplateDecl *AliasTemplate, + MutableArrayRef ParamTypes, SourceLocation Loc) { + TemplateDecl *RHSTemplate = + getRHSTemplateDeclAndArgs(SemaRef, AliasTemplate).first; + if (!RHSTemplate) + return nullptr; + auto *RHSDeductionGuide = SemaRef.DeclareAggregateDeductionGuideFromInitList( + RHSTemplate, ParamTypes, Loc); + if (!RHSDeductionGuide) + return nullptr; + + LocalInstantiationScope Scope(SemaRef); + + // Build a new template parameter list for the synthesized aggregate deduction + // guide by transforming the one from RHSDeductionGuide. + SmallVector TransformedTemplateParams; + // Template args that refer to the rebuilt template parameters. + // All template arguments must be initialized in advance. + SmallVector TransformedTemplateArgs( + RHSDeductionGuide->getTemplateParameters()->size()); + for (auto *TP : *RHSDeductionGuide->getTemplateParameters()) { + // Rebuild any internal references to earlier parameters and reindex as + // we go. + MultiLevelTemplateArgumentList Args; + Args.setKind(TemplateSubstitutionKind::Rewrite); + Args.addOuterTemplateArguments(TransformedTemplateArgs); + NamedDecl *NewParam = transformTemplateParameter( + SemaRef, AliasTemplate->getDeclContext(), TP, Args, + /*NewIndex=*/TransformedTemplateParams.size()); + + TransformedTemplateArgs[TransformedTemplateParams.size()] = + SemaRef.Context.getCanonicalTemplateArgument( + SemaRef.Context.getInjectedTemplateArg(NewParam)); + TransformedTemplateParams.push_back(NewParam); + } + // FIXME: implement the is_deducible constraint per C++ + // [over.match.class.deduct]p3.3. + Expr *TransformedRequiresClause = transformRequireClause( + SemaRef, RHSDeductionGuide, TransformedTemplateArgs); + auto *TransformedTemplateParameterList = TemplateParameterList::Create( + SemaRef.Context, AliasTemplate->getTemplateParameters()->getTemplateLoc(), + AliasTemplate->getTemplateParameters()->getLAngleLoc(), + TransformedTemplateParams, + AliasTemplate->getTemplateParameters()->getRAngleLoc(), + TransformedRequiresClause); + auto *TransformedTemplateArgList = TemplateArgumentList::CreateCopy( + SemaRef.Context, TransformedTemplateArgs); + + if (auto *TransformedDeductionGuide = SemaRef.InstantiateFunctionDeclaration( + RHSDeductionGuide, TransformedTemplateArgList, + AliasTemplate->getLocation(), + Sema::CodeSynthesisContext::BuildingDeductionGuides)) { + auto *GD = + llvm::dyn_cast(TransformedDeductionGuide); + FunctionTemplateDecl *Result = buildDeductionGuide( + SemaRef, AliasTemplate, TransformedTemplateParameterList, + GD->getCorrespondingConstructor(), GD->getExplicitSpecifier(), + GD->getTypeSourceInfo(), AliasTemplate->getBeginLoc(), + AliasTemplate->getLocation(), AliasTemplate->getEndLoc(), + GD->isImplicit()); + cast(Result->getTemplatedDecl()) + ->setDeductionCandidateKind(DeductionCandidate::Aggregate); + return Result; + } + return nullptr; +} + } // namespace -FunctionTemplateDecl *Sema::DeclareImplicitDeductionGuideFromInitList( +FunctionTemplateDecl *Sema::DeclareAggregateDeductionGuideFromInitList( TemplateDecl *Template, MutableArrayRef ParamTypes, SourceLocation Loc) { + llvm::FoldingSetNodeID ID; + ID.AddPointer(Template); + for (auto &T : ParamTypes) + T.getCanonicalType().Profile(ID); + unsigned Hash = ID.ComputeHash(); + + auto Found = AggregateDeductionCandidates.find(Hash); + if (Found != AggregateDeductionCandidates.end()) { + CXXDeductionGuideDecl *GD = Found->getSecond(); + return GD->getDescribedFunctionTemplate(); + } + + if (auto *AliasTemplate = llvm::dyn_cast(Template)) { + if (auto *FTD = DeclareAggregateDeductionGuideForTypeAlias( + *this, AliasTemplate, ParamTypes, Loc)) { + auto *GD = cast(FTD->getTemplatedDecl()); + GD->setDeductionCandidateKind(DeductionCandidate::Aggregate); + AggregateDeductionCandidates[Hash] = GD; + return FTD; + } + } + if (CXXRecordDecl *DefRecord = cast(Template->getTemplatedDecl())->getDefinition()) { if (TemplateDecl *DescribedTemplate = @@ -3050,10 +3162,13 @@ FunctionTemplateDecl *Sema::DeclareImplicitDeductionGuideFromInitList( Transform.NestedPattern ? Transform.NestedPattern : Transform.Template; ContextRAII SavedContext(*this, Pattern->getTemplatedDecl()); - auto *DG = cast( + auto *FTD = cast( Transform.buildSimpleDeductionGuide(ParamTypes)); SavedContext.pop(); - return DG; + auto *GD = cast(FTD->getTemplatedDecl()); + GD->setDeductionCandidateKind(DeductionCandidate::Aggregate); + AggregateDeductionCandidates[Hash] = GD; + return FTD; } void Sema::DeclareImplicitDeductionGuides(TemplateDecl *Template, diff --git a/clang/test/SemaTemplate/deduction-guide.cpp b/clang/test/SemaTemplate/deduction-guide.cpp index 0caef78fedbf..58f08aa1eed6 100644 --- a/clang/test/SemaTemplate/deduction-guide.cpp +++ b/clang/test/SemaTemplate/deduction-guide.cpp @@ -248,3 +248,15 @@ G g = {1}; // CHECK: FunctionTemplateDecl // CHECK: |-CXXDeductionGuideDecl {{.*}} implicit 'auto (T) -> G' aggregate // CHECK: `-CXXDeductionGuideDecl {{.*}} implicit used 'auto (int) -> G' implicit_instantiation aggregate + +template +using AG = G; +AG ag = {1}; +// Verify that the aggregate deduction guide for alias templates is built. +// CHECK-LABEL: Dumping +// CHECK: FunctionTemplateDecl +// CHECK: |-CXXDeductionGuideDecl {{.*}} 'auto (type-parameter-0-0) -> G' +// CHECK: `-CXXDeductionGuideDecl {{.*}} 'auto (int) -> G' implicit_instantiation +// CHECK: |-TemplateArgument type 'int' +// CHECK: | `-BuiltinType {{.*}} 'int' +// CHECK: `-ParmVarDecl {{.*}} 'int' -- GitLab From 9f0758405b71c23d1f260eb89d7d6daab280a425 Mon Sep 17 00:00:00 2001 From: Shourya Goel Date: Sat, 6 Apr 2024 00:41:44 +0530 Subject: [PATCH 025/695] reland: [libc] Added transitive bindings for OffsetType (#87680) Followup to issues addressed here: #87397 --- libc/config/gpu/api.td | 6 +++++- libc/config/linux/api.td | 12 ++++++++++-- libc/include/CMakeLists.txt | 10 ++++++---- libc/spec/posix.td | 7 +++++-- libc/src/stdio/fseeko.h | 1 - libc/src/stdio/ftello.h | 1 - 6 files changed, 26 insertions(+), 11 deletions(-) diff --git a/libc/config/gpu/api.td b/libc/config/gpu/api.td index adaf5bfd747a..523ad49ffa3f 100644 --- a/libc/config/gpu/api.td +++ b/libc/config/gpu/api.td @@ -64,7 +64,11 @@ def StdIOAPI : PublicAPI<"stdio.h"> { SimpleMacroDef<"_IOLBF", "1">, SimpleMacroDef<"_IONBF", "2">, ]; - let Types = ["size_t", "FILE"]; + let Types = [ + "FILE", + "off_t", + "size_t", + ]; } def IntTypesAPI : PublicAPI<"inttypes.h"> { diff --git a/libc/config/linux/api.td b/libc/config/linux/api.td index eb5ed8089850..9964971f191b 100644 --- a/libc/config/linux/api.td +++ b/libc/config/linux/api.td @@ -49,7 +49,10 @@ def CTypeAPI : PublicAPI<"ctype.h"> { } def FCntlAPI : PublicAPI<"fcntl.h"> { - let Types = ["mode_t"]; + let Types = [ + "mode_t", + "off_t", + ]; } def IntTypesAPI : PublicAPI<"inttypes.h"> { @@ -77,7 +80,12 @@ def StdIOAPI : PublicAPI<"stdio.h"> { SimpleMacroDef<"_IOLBF", "1">, SimpleMacroDef<"_IONBF", "2">, ]; - let Types = ["size_t", "FILE", "cookie_io_functions_t"]; + let Types = [ + "FILE", + "cookie_io_functions_t", + "off_t", + "size_t", + ]; } def StdlibAPI : PublicAPI<"stdlib.h"> { diff --git a/libc/include/CMakeLists.txt b/libc/include/CMakeLists.txt index 4203f0bc901b..02c7dc8fbc0b 100644 --- a/libc/include/CMakeLists.txt +++ b/libc/include/CMakeLists.txt @@ -41,9 +41,10 @@ add_gen_header( DEF_FILE fcntl.h.def GEN_HDR fcntl.h DEPENDS - .llvm_libc_common_h .llvm-libc-macros.fcntl_macros .llvm-libc-types.mode_t + .llvm-libc-types.off_t + .llvm_libc_common_h ) add_gen_header( @@ -264,13 +265,14 @@ add_gen_header( DEF_FILE stdio.h.def GEN_HDR stdio.h DEPENDS - .llvm_libc_common_h .llvm-libc-macros.file_seek_macros .llvm-libc-macros.stdio_macros - .llvm-libc-types.size_t - .llvm-libc-types.ssize_t .llvm-libc-types.FILE .llvm-libc-types.cookie_io_functions_t + .llvm-libc-types.off_t + .llvm-libc-types.size_t + .llvm-libc-types.ssize_t + .llvm_libc_common_h ) add_gen_header( diff --git a/libc/spec/posix.td b/libc/spec/posix.td index cfa8d3afedde..45f7ecfe84e9 100644 --- a/libc/spec/posix.td +++ b/libc/spec/posix.td @@ -210,7 +210,10 @@ def POSIX : StandardSpec<"POSIX"> { HeaderSpec FCntl = HeaderSpec< "fcntl.h", [], // Macros - [ModeTType], + [ + ModeTType, + OffTType, + ], [], // Enumerations [ FunctionSpec< @@ -1180,7 +1183,7 @@ def POSIX : StandardSpec<"POSIX"> { HeaderSpec StdIO = HeaderSpec< "stdio.h", [], // Macros - [], // Types + [OffTType], // Types [], // Enumerations [ FunctionSpec< diff --git a/libc/src/stdio/fseeko.h b/libc/src/stdio/fseeko.h index 3202ed2f97d0..77fb41215c31 100644 --- a/libc/src/stdio/fseeko.h +++ b/libc/src/stdio/fseeko.h @@ -10,7 +10,6 @@ #define LLVM_LIBC_SRC_STDIO_FSEEKO_H #include -#include namespace LIBC_NAMESPACE { diff --git a/libc/src/stdio/ftello.h b/libc/src/stdio/ftello.h index 0fdf13ab6bdb..5ab17f9244a5 100644 --- a/libc/src/stdio/ftello.h +++ b/libc/src/stdio/ftello.h @@ -10,7 +10,6 @@ #define LLVM_LIBC_SRC_STDIO_FTELLO_H #include -#include namespace LIBC_NAMESPACE { -- GitLab From 25ebbe3851c54f035875fd3d7d2569d79cacf803 Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Fri, 5 Apr 2024 12:14:55 -0700 Subject: [PATCH 026/695] [flang][doc] Added information about `REAL(16)` math intrinsics support. (#87710) --- flang/docs/GettingStarted.md | 10 +++++++++ flang/docs/Real16MathSupport.md | 38 +++++++++++++++++++++++++++++++++ flang/docs/index.md | 1 + 3 files changed, 49 insertions(+) create mode 100644 flang/docs/Real16MathSupport.md diff --git a/flang/docs/GettingStarted.md b/flang/docs/GettingStarted.md index 043804e5a122..1c85a6754b15 100644 --- a/flang/docs/GettingStarted.md +++ b/flang/docs/GettingStarted.md @@ -304,6 +304,16 @@ Clang-like device linking pipeline. The same set of CMake variables works for Flang in-tree build. +### Build options + +One may provide optional CMake variables to customize the build. Available options: + +* `-DFLANG_RUNTIME_F128_MATH_LIB=libquadmath`: enables build of + `FortranFloat128Math` library that provides `REAL(16)` math APIs + for intrinsics such as `SIN`, `COS`, etc. GCC `libquadmath`'s header file + `quadmath.h` must be available to the build compiler. + [More details](Real16MathSupport.md). + ## Supported C++ compilers Flang is written in C++17. diff --git a/flang/docs/Real16MathSupport.md b/flang/docs/Real16MathSupport.md new file mode 100644 index 000000000000..21482c7be21a --- /dev/null +++ b/flang/docs/Real16MathSupport.md @@ -0,0 +1,38 @@ + + +# Flang support for REAL(16) math intrinsics + +To support most `REAL(16)` (i.e. 128-bit float) math intrinsics Flang relies +on third-party libraries providing the implementation. + +`-DFLANG_RUNTIME_F128_MATH_LIB=libquadmath` CMake option can be used +to build `FortranFloat128Math` library that has unresolved references +to GCC `libquadmath` library. A Flang driver built with this option +will automatically link `FortranFloat128Math` and `libquadmath` libraries +to any Fortran program. This implies that `libquadmath` library +has to be available in the standard library paths, so that linker +can find it. The `libquadmath` library installation into Flang project +distribution is not automatic in CMake currently. + +Testing shows that `libquadmath` versions before GCC-9.3.0 have +accuracy issues, so it is recommended to distribute the Flang +package with later versions of `libquadmath`. + +Care must be taken by the distributors of a Flang package built +with `REAL(16)` support via `libquadmath` because of its licensing +under the GNU Library General Public License. Moreover, static linking +of `libquadmath` to the Flang users' programs may imply some +restrictions/requirements. This document is not intended to give +any legal advice on distributing such a Flang compiler. + +Flang compiler targeting systems with `LDBL_MANT_DIG == 113` +may provide `REAL(16)` math support without a `libquadmath` +dependency, using standard `libc` APIs for the `long double` +data type. It is not recommended to use the above CMake option +for building Flang compilers for such targets. diff --git a/flang/docs/index.md b/flang/docs/index.md index ed749f565ff1..4a0b145df10b 100644 --- a/flang/docs/index.md +++ b/flang/docs/index.md @@ -85,6 +85,7 @@ on how to get in touch with us and to learn more about the current status. Semantics f2018-grammar.md fstack-arrays + Real16MathSupport ``` # Indices and tables -- GitLab From e7e78274a66df59ce3f2fa2bfd8a554e637ee0b6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 5 Apr 2024 12:02:00 -0700 Subject: [PATCH 027/695] [RISCV] Remove uses of sed from compress-opt-branch.ll. NFC sed was being used to use the same test functions with eq/ne branch condition. This commit duplicates the test functions so that we have a version with each condition. This allows us to remove 2 RUN lines. I plan to add a Zca testing to this file which now requires 1 new RUN line instead of 2. --- .../test/CodeGen/RISCV/compress-opt-branch.ll | 456 ++++++++++++++---- 1 file changed, 362 insertions(+), 94 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll index 354f180b45a9..44eaf4bdc207 100644 --- a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll +++ b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll @@ -3,45 +3,50 @@ ; The optimization should appear only with +c, otherwise default isel should be ; choosen. ; -; RUN: cat %s | sed 's/CMPCOND/eq/g' | sed 's/RESBRNORMAL/bne/g' | \ -; RUN: sed 's/RESBROPT/c.bnez/g' > %t.compress_eq ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \ -; RUN: -disable-block-placement < %t.compress_eq \ +; RUN: -disable-block-placement < %s \ ; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ -; RUN: | FileCheck -check-prefix=RV32IFDC %t.compress_eq +; RUN: | FileCheck -check-prefix=RV32IFDC %s ; -; RUN: cat %s | sed -e 's/CMPCOND/eq/g' | sed -e 's/RESBRNORMAL/bne/g'\ -; RUN: | sed -e 's/RESBROPT/c.bnez/g' > %t.nocompr_eq ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \ -; RUN: -disable-block-placement < %t.nocompr_eq \ +; RUN: -disable-block-placement < %s \ ; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \ -; RUN: | FileCheck -check-prefix=RV32IFD %t.nocompr_eq -; -; RUN: cat %s | sed 's/CMPCOND/ne/g' | sed 's/RESBRNORMAL/beq/g' | \ -; RUN: sed 's/RESBROPT/c.beqz/g' > %t.compress_neq -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \ -; RUN: -disable-block-placement < %t.compress_neq \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ -; RUN: | FileCheck -check-prefix=RV32IFDC %t.compress_neq -; -; RUN: cat %s | sed -e 's/CMPCOND/ne/g' | sed -e 's/RESBRNORMAL/beq/g'\ -; RUN: | sed -e 's/RESBROPT/c.beqz/g' > %t.nocompr_neq -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \ -; RUN: -disable-block-placement < %t.nocompr_neq \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \ -; RUN: | FileCheck -check-prefix=RV32IFD %t.nocompr_neq +; RUN: | FileCheck -check-prefix=RV32IFD %s + + +; constant is small and fit in 6 bit (compress imm) +; RV32IFDC-LABEL: : +; RV32IFDC: c.li [[REG:.*]], 0x14 +; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, 0x14 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_pos_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, 20 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} ; constant is small and fit in 6 bit (compress imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: c.li [[REG:.*]], 0x14 -; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, 0x14 -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_small_pos(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, 20 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_pos_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, 20 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -56,15 +61,61 @@ if.end: } ; constant is small and fit in 6 bit (compress imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: c.li [[REG:.*]], -0x14 -; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, -0x14 -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_small_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -20 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_neg_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, -20 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is small and fit in 6 bit (compress imm) +; RV32IFDC-LABEL: : +; RV32IFDC: c.li [[REG:.*]], -0x14 +; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, -0x14 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_neg_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, -20 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is small and fit in 6 bit (compress imm) +; RV32IFDC-LABEL: : +; RV32IFDC: c.li [[REG:.*]], 0x1f +; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, 0x1f +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_edge_pos_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, 31 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -79,15 +130,38 @@ if.end: } ; constant is small and fit in 6 bit (compress imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: c.li [[REG:.*]], 0x1f -; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, 0x1f -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_small_edge_pos(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, 31 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_edge_pos_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, 31 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is small and fit in 6 bit (compress imm) +; RV32IFDC-LABEL: : +; RV32IFDC: c.li [[REG:.*]], -0x20 +; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, -0x20 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_edge_neg_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, -32 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -102,15 +176,15 @@ if.end: } ; constant is small and fit in 6 bit (compress imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: c.li [[REG:.*]], -0x20 -; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, -0x20 -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_small_edge_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -32 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_small_edge_neg_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, -32 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -126,15 +200,63 @@ if.end: ; constant is medium and not fit in 6 bit (compress imm), ; but fit in 12 bit (imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x20 -; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]] +; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, 0x20 -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_medium_ledge_pos(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, 32 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_ledge_pos_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, 32 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is medium and not fit in 6 bit (compress imm), +; but fit in 12 bit (imm) +; RV32IFDC-LABEL: : +; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x20 +; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, 0x20 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_ledge_pos_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, 32 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is medium and not fit in 6 bit (compress imm), +; but fit in 12 bit (imm) +; RV32IFDC-LABEL: : +; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21 +; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, -0x21 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_ledge_neg_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, -33 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -150,15 +272,15 @@ if.end: ; constant is medium and not fit in 6 bit (compress imm), ; but fit in 12 bit (imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x21 -; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]] +; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, -0x21 -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_medium_ledge_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -33 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_ledge_neg_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, -33 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -174,15 +296,15 @@ if.end: ; constant is medium and not fit in 6 bit (compress imm), ; but fit in 12 bit (imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f -; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]] +; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, 0x3f -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_medium_pos(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, 63 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_pos_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, 63 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -198,15 +320,39 @@ if.end: ; constant is medium and not fit in 6 bit (compress imm), ; but fit in 12 bit (imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : +; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x3f +; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, 0x3f +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_pos_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, 63 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is medium and not fit in 6 bit (compress imm), +; but fit in 12 bit (imm) +; RV32IFDC-LABEL: : ; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f -; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]] +; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, -0x3f -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_medium_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -63 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_neg_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, -63 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -222,15 +368,87 @@ if.end: ; constant is medium and not fit in 6 bit (compress imm), ; but fit in 12 bit (imm) -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : +; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x3f +; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, -0x3f +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_neg_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, -63 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is medium and not fit in 6 bit (compress imm), +; but fit in 12 bit (imm) +; RV32IFDC-LABEL: : ; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff -; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]] +; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, 0x7ff -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_medium_bedge_pos(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, 2047 +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_bedge_pos_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, 2047 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is medium and not fit in 6 bit (compress imm), +; but fit in 12 bit (imm) +; RV32IFDC-LABEL: : +; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], -0x7ff +; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, 0x7ff +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_bedge_pos_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, 2047 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is medium and not fit in 6 bit (compress imm), +; but fit in 12 bit (imm), negative value fit in 12 bit too. +; RV32IFDC-LABEL: : +; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff +; RV32IFDC: c.bnez [[MAYZEROREG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG:.*]], zero, -0x7ff +; RV32IFD: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_bedge_neg_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, -2047 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -246,15 +464,15 @@ if.end: ; constant is medium and not fit in 6 bit (compress imm), ; but fit in 12 bit (imm), negative value fit in 12 bit too. -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: addi [[MAYZEROREG:.*]], [[REG:.*]], 0x7ff -; RV32IFDC: RESBROPT [[MAYZEROREG]], [[PLACE:.*]] +; RV32IFDC: c.beqz [[MAYZEROREG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG:.*]], zero, -0x7ff -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] -define i32 @f_medium_bedge_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -2047 +; RV32IFD: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +define i32 @f_medium_bedge_neg_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, -2047 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -269,17 +487,67 @@ if.end: } ; constant is big and do not fit in 12 bit (imm), fit in i32 -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: c.li [[REG:.*]], 0x1 ; RV32IFDC: c.slli [[REG]], 0xb -; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: addi [[REG1:.*]], zero, 0x1 ; RV32IFD: slli [[REG2:.*]], [[REG1]], 0xb -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] -define i32 @f_big_ledge_pos(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, 2048 +; RV32IFD: bne [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] +define i32 @f_big_ledge_pos_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, 2048 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is big and do not fit in 12 bit (imm), fit in i32 +; RV32IFDC-LABEL: : +; RV32IFDC: c.li [[REG:.*]], 0x1 +; RV32IFDC: c.slli [[REG]], 0xb +; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: addi [[REG1:.*]], zero, 0x1 +; RV32IFD: slli [[REG2:.*]], [[REG1]], 0xb +; RV32IFD: beq [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] +define i32 @f_big_ledge_pos_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, 2048 + br i1 %cmp, label %if.then, label %if.else +if.then: + %call = shl i32 %in0, 1 + br label %if.end +if.else: + %call2 = add i32 %in0, 42 + br label %if.end + +if.end: + %toRet = phi i32 [ %call, %if.then ], [ %call2, %if.else ] + ret i32 %toRet +} + +; constant is big and do not fit in 12 bit (imm), fit in i32 +; RV32IFDC-LABEL: : +; RV32IFDC: c.lui [[REG1:.*]], 0xfffff +; RV32IFDC: addi [[REG2:.*]], [[REG1]], 0x7ff +; RV32IFDC: bne [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; --- no compress extension +; RV32IFD-LABEL: : +; RV32IFD: lui [[REG1:.*]], 0xfffff +; RV32IFD: addi [[REG2:.*]], [[REG1]], 0x7ff +; RV32IFD: bne [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] +define i32 @f_big_ledge_neg_eq(i32 %in0) minsize { + %cmp = icmp eq i32 %in0, -2049 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 @@ -294,17 +562,17 @@ if.end: } ; constant is big and do not fit in 12 bit (imm), fit in i32 -; RV32IFDC-LABEL: : +; RV32IFDC-LABEL: : ; RV32IFDC: c.lui [[REG1:.*]], 0xfffff ; RV32IFDC: addi [[REG2:.*]], [[REG1]], 0x7ff -; RV32IFDC: RESBRNORMAL [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] +; RV32IFDC: beq [[ANOTHER:.*]], [[REG]], [[PLACE:.*]] ; --- no compress extension -; RV32IFD-LABEL: : +; RV32IFD-LABEL: : ; RV32IFD: lui [[REG1:.*]], 0xfffff ; RV32IFD: addi [[REG2:.*]], [[REG1]], 0x7ff -; RV32IFD: RESBRNORMAL [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] -define i32 @f_big_ledge_neg(i32 %in0) minsize { - %cmp = icmp CMPCOND i32 %in0, -2049 +; RV32IFD: beq [[ANOTHER:.*]], [[REG2]], [[PLACE:.*]] +define i32 @f_big_ledge_neg_ne(i32 %in0) minsize { + %cmp = icmp ne i32 %in0, -2049 br i1 %cmp, label %if.then, label %if.else if.then: %call = shl i32 %in0, 1 -- GitLab From 0a6a40d62ed338eb3aa57bfee83d958521542fba Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 5 Apr 2024 12:39:37 -0700 Subject: [PATCH 028/695] [RISCV] Add Zca predicate to BrccCompressOpt patterns used for MinSize. Previously we only checked for C. --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +- llvm/test/CodeGen/RISCV/compress-opt-branch.ll | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index fd8777fdc121..2cfad7f7c061 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1419,7 +1419,7 @@ defm : BccPat; defm : BccPat; defm : BccPat; -let Predicates = [HasStdExtC, OptForMinSize] in { +let Predicates = [HasStdExtCOrZca, OptForMinSize] in { def : BrccCompressOpt; def : BrccCompressOpt; } diff --git a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll index 44eaf4bdc207..f740e7fc4e31 100644 --- a/llvm/test/CodeGen/RISCV/compress-opt-branch.ll +++ b/llvm/test/CodeGen/RISCV/compress-opt-branch.ll @@ -8,6 +8,11 @@ ; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zca,+f,+d -filetype=obj \ +; RUN: -disable-block-placement < %s \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zca,+f,+d -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s +; ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d -filetype=obj \ ; RUN: -disable-block-placement < %s \ ; RUN: | llvm-objdump -d --triple=riscv32 --mattr=-c,+f,+d -M no-aliases - \ -- GitLab From 4abb722ffa7fcf809faa4a479fdf2f78c685b351 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 3 Apr 2024 11:58:18 -0700 Subject: [PATCH 029/695] [RISCV] Add tests for opportunities to reassociate to form more shXadd instructions. NFC These tests consist of patterns like (sh3add Z, (add X, (slli Y, 6))) that can be reassociated to form (sh3add (sh3add Y, Z), X). --- llvm/test/CodeGen/RISCV/rv64zba.ll | 361 +++++++++++++++++++++++++++++ 1 file changed, 361 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index c81c6aeaab89..7e32253c8653 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -2036,3 +2036,364 @@ define i64 @pack_i64_disjoint_2(i32 signext %a, i64 %b) nounwind { %or = or disjoint i64 %b, %zexta ret i64 %or } + +define i8 @array_index_sh1_sh0(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh1_sh0: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh1_sh0: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh1add a0, a1, a0 +; RV64ZBA-NEXT: add a0, a0, a2 +; RV64ZBA-NEXT: lbu a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [2 x i8], ptr %p, i64 %idx1, i64 %idx2 + %b = load i8, ptr %a, align 1 + ret i8 %b +} + +define i16 @array_index_sh1_sh1(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh1_sh1: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lh a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh1_sh1: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: sh1add a0, a2, a0 +; RV64ZBA-NEXT: lh a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [2 x i16], ptr %p, i64 %idx1, i64 %idx2 + %b = load i16, ptr %a, align 2 + ret i16 %b +} + +define i32 @array_index_sh1_sh2(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh1_sh2: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 3 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 2 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh1_sh2: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: sh2add a0, a2, a0 +; RV64ZBA-NEXT: lw a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [2 x i32], ptr %p, i64 %idx1, i64 %idx2 + %b = load i32, ptr %a, align 4 + ret i32 %b +} + +define i64 @array_index_sh1_sh3(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh1_sh3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 3 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh1_sh3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 4 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [2 x i64], ptr %p, i64 %idx1, i64 %idx2 + %b = load i64, ptr %a, align 8 + ret i64 %b +} + +define i8 @array_index_sh2_sh0(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh2_sh0: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 2 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh2_sh0: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh2add a0, a1, a0 +; RV64ZBA-NEXT: add a0, a0, a2 +; RV64ZBA-NEXT: lbu a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [4 x i8], ptr %p, i64 %idx1, i64 %idx2 + %b = load i8, ptr %a, align 1 + ret i8 %b +} + +define i16 @array_index_sh2_sh1(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh2_sh1: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 3 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lh a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh2_sh1: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: sh1add a0, a2, a0 +; RV64ZBA-NEXT: lh a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [4 x i16], ptr %p, i64 %idx1, i64 %idx2 + %b = load i16, ptr %a, align 2 + ret i16 %b +} + +define i32 @array_index_sh2_sh2(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh2_sh2: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 2 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh2_sh2: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 4 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh2add a0, a2, a0 +; RV64ZBA-NEXT: lw a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [4 x i32], ptr %p, i64 %idx1, i64 %idx2 + %b = load i32, ptr %a, align 4 + ret i32 %b +} + +define i64 @array_index_sh2_sh3(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh2_sh3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 5 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 3 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh2_sh3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 5 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [4 x i64], ptr %p, i64 %idx1, i64 %idx2 + %b = load i64, ptr %a, align 8 + ret i64 %b +} + +define i8 @array_index_sh3_sh0(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh3_sh0: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 3 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: lbu a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh3_sh0: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh3add a0, a1, a0 +; RV64ZBA-NEXT: add a0, a0, a2 +; RV64ZBA-NEXT: lbu a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [8 x i8], ptr %p, i64 %idx1, i64 %idx2 + %b = load i8, ptr %a, align 1 + ret i8 %b +} + +define i16 @array_index_sh3_sh1(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh3_sh1: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 4 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lh a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh3_sh1: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 4 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh1add a0, a2, a0 +; RV64ZBA-NEXT: lh a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [8 x i16], ptr %p, i64 %idx1, i64 %idx2 + %b = load i16, ptr %a, align 2 + ret i16 %b +} + +define i32 @array_index_sh3_sh2(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh3_sh2: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 5 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 2 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh3_sh2: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 5 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh2add a0, a2, a0 +; RV64ZBA-NEXT: lw a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [8 x i32], ptr %p, i64 %idx1, i64 %idx2 + %b = load i32, ptr %a, align 4 + ret i32 %b +} + +define i64 @array_index_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh3_sh3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 6 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 3 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh3_sh3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 6 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [8 x i64], ptr %p, i64 %idx1, i64 %idx2 + %b = load i64, ptr %a, align 8 + ret i64 %b +} + +; Similar to above, but with a lshr on one of the indices. This requires +; special handling during isel to form a shift pair. +define i64 @array_index_lshr_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_lshr_sh3_sh3: +; RV64I: # %bb.0: +; RV64I-NEXT: srli a1, a1, 58 +; RV64I-NEXT: slli a1, a1, 6 +; RV64I-NEXT: slli a2, a2, 3 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_lshr_sh3_sh3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: srli a1, a1, 58 +; RV64ZBA-NEXT: slli a1, a1, 6 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: ret + %shr = lshr i64 %idx1, 58 + %a = getelementptr inbounds [8 x i64], ptr %p, i64 %shr, i64 %idx2 + %b = load i64, ptr %a, align 8 + ret i64 %b +} + +define i8 @array_index_sh4_sh0(ptr %p, i64 %idx1, i64 %idx2) { +; CHECK-LABEL: array_index_sh4_sh0: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a1, a1, 4 +; CHECK-NEXT: add a0, a0, a2 +; CHECK-NEXT: add a0, a0, a1 +; CHECK-NEXT: lbu a0, 0(a0) +; CHECK-NEXT: ret + %a = getelementptr inbounds [16 x i8], ptr %p, i64 %idx1, i64 %idx2 + %b = load i8, ptr %a, align 1 + ret i8 %b +} + +define i16 @array_index_sh4_sh1(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh4_sh1: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 5 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lh a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh4_sh1: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 5 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh1add a0, a2, a0 +; RV64ZBA-NEXT: lh a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [16 x i16], ptr %p, i64 %idx1, i64 %idx2 + %b = load i16, ptr %a, align 2 + ret i16 %b +} + +define i32 @array_index_sh4_sh2(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh4_sh2: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 6 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 2 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh4_sh2: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 6 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh2add a0, a2, a0 +; RV64ZBA-NEXT: lw a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [16 x i32], ptr %p, i64 %idx1, i64 %idx2 + %b = load i32, ptr %a, align 4 + ret i32 %b +} + +define i64 @array_index_sh4_sh3(ptr %p, i64 %idx1, i64 %idx2) { +; RV64I-LABEL: array_index_sh4_sh3: +; RV64I: # %bb.0: +; RV64I-NEXT: slli a1, a1, 7 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: slli a2, a2, 3 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: array_index_sh4_sh3: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: slli a1, a1, 7 +; RV64ZBA-NEXT: add a0, a0, a1 +; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: ld a0, 0(a0) +; RV64ZBA-NEXT: ret + %a = getelementptr inbounds [16 x i64], ptr %p, i64 %idx1, i64 %idx2 + %b = load i64, ptr %a, align 8 + ret i64 %b +} -- GitLab From 60fc4ac67a613e4e36cef019fb2d13d70a06cfe8 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 5 Apr 2024 10:49:19 -0700 Subject: [PATCH 030/695] [GlobalISel] Don't form anyextending atomic loads. Until we can reliably check the legality and improve our selection of these, don't form them at all. --- .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 4 +- .../Atomics/aarch64-atomic-load-rcpc_immo.ll | 55 +++++++++++++----- .../AArch64/GlobalISel/arm64-atomic.ll | 56 +++++++++---------- .../AArch64/GlobalISel/arm64-pcsections.ll | 28 +++++----- .../atomic-anyextending-load-crash.ll | 47 ++++++++++++++++ 5 files changed, 131 insertions(+), 59 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 719209e0edd5..0b58d95bc8b2 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -597,8 +597,8 @@ bool CombinerHelper::matchCombineExtendingLoads(MachineInstr &MI, UseMI.getOpcode() == TargetOpcode::G_ZEXT || (UseMI.getOpcode() == TargetOpcode::G_ANYEXT)) { const auto &MMO = LoadMI->getMMO(); - // For atomics, only form anyextending loads. - if (MMO.isAtomic() && UseMI.getOpcode() != TargetOpcode::G_ANYEXT) + // Don't do anything for atomics. + if (MMO.isAtomic()) continue; // Check for legality. if (!isPreLegalize()) { diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll index b0507e9d075f..9687ba683fb7 100644 --- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll +++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-rcpc_immo.ll @@ -35,16 +35,24 @@ define i8 @load_atomic_i8_aligned_monotonic_const(ptr readonly %ptr) { } define i8 @load_atomic_i8_aligned_acquire(ptr %ptr) { -; CHECK-LABEL: load_atomic_i8_aligned_acquire: -; CHECK: ldapurb w0, [x0, #4] +; GISEL-LABEL: load_atomic_i8_aligned_acquire: +; GISEL: add x8, x0, #4 +; GISEL: ldaprb w0, [x8] +; +; SDAG-LABEL: load_atomic_i8_aligned_acquire: +; SDAG: ldapurb w0, [x0, #4] %gep = getelementptr inbounds i8, ptr %ptr, i32 4 %r = load atomic i8, ptr %gep acquire, align 1 ret i8 %r } define i8 @load_atomic_i8_aligned_acquire_const(ptr readonly %ptr) { -; CHECK-LABEL: load_atomic_i8_aligned_acquire_const: -; CHECK: ldapurb w0, [x0, #4] +; GISEL-LABEL: load_atomic_i8_aligned_acquire_const: +; GISEL: add x8, x0, #4 +; GISEL: ldaprb w0, [x8] +; +; SDAG-LABEL: load_atomic_i8_aligned_acquire_const: +; SDAG: ldapurb w0, [x0, #4] %gep = getelementptr inbounds i8, ptr %ptr, i32 4 %r = load atomic i8, ptr %gep acquire, align 1 ret i8 %r @@ -101,16 +109,24 @@ define i16 @load_atomic_i16_aligned_monotonic_const(ptr readonly %ptr) { } define i16 @load_atomic_i16_aligned_acquire(ptr %ptr) { -; CHECK-LABEL: load_atomic_i16_aligned_acquire: -; CHECK: ldapurh w0, [x0, #8] +; GISEL-LABEL: load_atomic_i16_aligned_acquire: +; GISEL: add x8, x0, #8 +; GISEL: ldaprh w0, [x8] +; +; SDAG-LABEL: load_atomic_i16_aligned_acquire: +; SDAG: ldapurh w0, [x0, #8] %gep = getelementptr inbounds i16, ptr %ptr, i32 4 %r = load atomic i16, ptr %gep acquire, align 2 ret i16 %r } define i16 @load_atomic_i16_aligned_acquire_const(ptr readonly %ptr) { -; CHECK-LABEL: load_atomic_i16_aligned_acquire_const: -; CHECK: ldapurh w0, [x0, #8] +; GISEL-LABEL: load_atomic_i16_aligned_acquire_const: +; GISEL: add x8, x0, #8 +; GISEL: ldaprh w0, [x8] +; +; SDAG-LABEL: load_atomic_i16_aligned_acquire_const: +; SDAG: ldapurh w0, [x0, #8] %gep = getelementptr inbounds i16, ptr %ptr, i32 4 %r = load atomic i16, ptr %gep acquire, align 2 ret i16 %r @@ -367,16 +383,24 @@ define i8 @load_atomic_i8_unaligned_monotonic_const(ptr readonly %ptr) { } define i8 @load_atomic_i8_unaligned_acquire(ptr %ptr) { -; CHECK-LABEL: load_atomic_i8_unaligned_acquire: -; CHECK: ldapurb w0, [x0, #4] +; GISEL-LABEL: load_atomic_i8_unaligned_acquire: +; GISEL: add x8, x0, #4 +; GISEL: ldaprb w0, [x8] +; +; SDAG-LABEL: load_atomic_i8_unaligned_acquire: +; SDAG: ldapurb w0, [x0, #4] %gep = getelementptr inbounds i8, ptr %ptr, i32 4 %r = load atomic i8, ptr %gep acquire, align 1 ret i8 %r } define i8 @load_atomic_i8_unaligned_acquire_const(ptr readonly %ptr) { -; CHECK-LABEL: load_atomic_i8_unaligned_acquire_const: -; CHECK: ldapurb w0, [x0, #4] +; GISEL-LABEL: load_atomic_i8_unaligned_acquire_const: +; GISEL: add x8, x0, #4 +; GISEL: ldaprb w0, [x8] +; +; SDAG-LABEL: load_atomic_i8_unaligned_acquire_const: +; SDAG: ldapurb w0, [x0, #4] %gep = getelementptr inbounds i8, ptr %ptr, i32 4 %r = load atomic i8, ptr %gep acquire, align 1 ret i8 %r @@ -819,7 +843,8 @@ define i128 @load_atomic_i128_unaligned_seq_cst_const(ptr readonly %ptr) { define i8 @load_atomic_i8_from_gep() { ; GISEL-LABEL: load_atomic_i8_from_gep: ; GISEL: bl init -; GISEL: ldapurb w0, [x8, #1] +; GISEL: add x8, x8, #1 +; GISEL: ldaprb w0, [x8] ; ; SDAG-LABEL: load_atomic_i8_from_gep: ; SDAG: bl init @@ -834,7 +859,8 @@ define i8 @load_atomic_i8_from_gep() { define i16 @load_atomic_i16_from_gep() { ; GISEL-LABEL: load_atomic_i16_from_gep: ; GISEL: bl init -; GISEL: ldapurh w0, [x8, #2] +; GISEL: add x8, x8, #2 +; GISEL: ldaprh w0, [x8] ; ; SDAG-LABEL: load_atomic_i16_from_gep: ; SDAG: bl init @@ -884,7 +910,6 @@ define i128 @load_atomic_i128_from_gep() { ; ; SDAG-LABEL: load_atomic_i128_from_gep: ; SDAG: bl init -; SDAG: ldp x0, x1, [sp, #16] ; SDAG: dmb ishld %a = alloca [3 x i128] call void @init(ptr %a) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll index 7163da0dc024..b619aac709d9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll @@ -993,24 +993,24 @@ define i8 @atomic_load_relaxed_8(ptr %p, i32 %off32) #0 { ; CHECK-NOLSE-O1: ; %bb.0: ; CHECK-NOLSE-O1-NEXT: ldrb w8, [x0, #4095] ; CHECK-NOLSE-O1-NEXT: ldrb w9, [x0, w1, sxtw] -; CHECK-NOLSE-O1-NEXT: add x11, x0, #291, lsl #12 ; =1191936 ; CHECK-NOLSE-O1-NEXT: ldurb w10, [x0, #-256] -; CHECK-NOLSE-O1-NEXT: add w8, w8, w9 -; CHECK-NOLSE-O1-NEXT: ldrb w9, [x11] -; CHECK-NOLSE-O1-NEXT: add w8, w8, w10 -; CHECK-NOLSE-O1-NEXT: add w0, w8, w9 +; CHECK-NOLSE-O1-NEXT: add w8, w9, w8, uxtb +; CHECK-NOLSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 +; CHECK-NOLSE-O1-NEXT: ldrb w9, [x9] +; CHECK-NOLSE-O1-NEXT: add w8, w8, w10, uxtb +; CHECK-NOLSE-O1-NEXT: add w0, w8, w9, uxtb ; CHECK-NOLSE-O1-NEXT: ret ; ; CHECK-OUTLINE-O1-LABEL: atomic_load_relaxed_8: ; CHECK-OUTLINE-O1: ; %bb.0: ; CHECK-OUTLINE-O1-NEXT: ldrb w8, [x0, #4095] ; CHECK-OUTLINE-O1-NEXT: ldrb w9, [x0, w1, sxtw] -; CHECK-OUTLINE-O1-NEXT: add x11, x0, #291, lsl #12 ; =1191936 ; CHECK-OUTLINE-O1-NEXT: ldurb w10, [x0, #-256] -; CHECK-OUTLINE-O1-NEXT: add w8, w8, w9 -; CHECK-OUTLINE-O1-NEXT: ldrb w9, [x11] -; CHECK-OUTLINE-O1-NEXT: add w8, w8, w10 -; CHECK-OUTLINE-O1-NEXT: add w0, w8, w9 +; CHECK-OUTLINE-O1-NEXT: add w8, w9, w8, uxtb +; CHECK-OUTLINE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 +; CHECK-OUTLINE-O1-NEXT: ldrb w9, [x9] +; CHECK-OUTLINE-O1-NEXT: add w8, w8, w10, uxtb +; CHECK-OUTLINE-O1-NEXT: add w0, w8, w9, uxtb ; CHECK-OUTLINE-O1-NEXT: ret ; ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_8: @@ -1045,12 +1045,12 @@ define i8 @atomic_load_relaxed_8(ptr %p, i32 %off32) #0 { ; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1-NEXT: ldrb w8, [x0, #4095] ; CHECK-LSE-O1-NEXT: ldrb w9, [x0, w1, sxtw] -; CHECK-LSE-O1-NEXT: ldurb w10, [x0, #-256] -; CHECK-LSE-O1-NEXT: add w8, w8, w10 -; CHECK-LSE-O1-NEXT: add w8, w8, w9 +; CHECK-LSE-O1-NEXT: add w8, w9, w8, uxtb +; CHECK-LSE-O1-NEXT: ldurb w9, [x0, #-256] +; CHECK-LSE-O1-NEXT: add w8, w8, w9, uxtb ; CHECK-LSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O1-NEXT: ldrb w9, [x9] -; CHECK-LSE-O1-NEXT: add w0, w8, w9 +; CHECK-LSE-O1-NEXT: add w0, w8, w9, uxtb ; CHECK-LSE-O1-NEXT: ret ; ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_8: @@ -1089,24 +1089,24 @@ define i16 @atomic_load_relaxed_16(ptr %p, i32 %off32) #0 { ; CHECK-NOLSE-O1: ; %bb.0: ; CHECK-NOLSE-O1-NEXT: ldrh w8, [x0, #8190] ; CHECK-NOLSE-O1-NEXT: ldrh w9, [x0, w1, sxtw #1] -; CHECK-NOLSE-O1-NEXT: add x11, x0, #291, lsl #12 ; =1191936 ; CHECK-NOLSE-O1-NEXT: ldurh w10, [x0, #-256] -; CHECK-NOLSE-O1-NEXT: add w8, w8, w9 -; CHECK-NOLSE-O1-NEXT: ldrh w9, [x11] -; CHECK-NOLSE-O1-NEXT: add w8, w8, w10 -; CHECK-NOLSE-O1-NEXT: add w0, w8, w9 +; CHECK-NOLSE-O1-NEXT: add w8, w9, w8, uxth +; CHECK-NOLSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 +; CHECK-NOLSE-O1-NEXT: ldrh w9, [x9] +; CHECK-NOLSE-O1-NEXT: add w8, w8, w10, uxth +; CHECK-NOLSE-O1-NEXT: add w0, w8, w9, uxth ; CHECK-NOLSE-O1-NEXT: ret ; ; CHECK-OUTLINE-O1-LABEL: atomic_load_relaxed_16: ; CHECK-OUTLINE-O1: ; %bb.0: ; CHECK-OUTLINE-O1-NEXT: ldrh w8, [x0, #8190] ; CHECK-OUTLINE-O1-NEXT: ldrh w9, [x0, w1, sxtw #1] -; CHECK-OUTLINE-O1-NEXT: add x11, x0, #291, lsl #12 ; =1191936 ; CHECK-OUTLINE-O1-NEXT: ldurh w10, [x0, #-256] -; CHECK-OUTLINE-O1-NEXT: add w8, w8, w9 -; CHECK-OUTLINE-O1-NEXT: ldrh w9, [x11] -; CHECK-OUTLINE-O1-NEXT: add w8, w8, w10 -; CHECK-OUTLINE-O1-NEXT: add w0, w8, w9 +; CHECK-OUTLINE-O1-NEXT: add w8, w9, w8, uxth +; CHECK-OUTLINE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 +; CHECK-OUTLINE-O1-NEXT: ldrh w9, [x9] +; CHECK-OUTLINE-O1-NEXT: add w8, w8, w10, uxth +; CHECK-OUTLINE-O1-NEXT: add w0, w8, w9, uxth ; CHECK-OUTLINE-O1-NEXT: ret ; ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_16: @@ -1141,12 +1141,12 @@ define i16 @atomic_load_relaxed_16(ptr %p, i32 %off32) #0 { ; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1-NEXT: ldrh w8, [x0, #8190] ; CHECK-LSE-O1-NEXT: ldrh w9, [x0, w1, sxtw #1] -; CHECK-LSE-O1-NEXT: ldurh w10, [x0, #-256] -; CHECK-LSE-O1-NEXT: add w8, w8, w10 -; CHECK-LSE-O1-NEXT: add w8, w8, w9 +; CHECK-LSE-O1-NEXT: add w8, w9, w8, uxth +; CHECK-LSE-O1-NEXT: ldurh w9, [x0, #-256] +; CHECK-LSE-O1-NEXT: add w8, w8, w9, uxth ; CHECK-LSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O1-NEXT: ldrh w9, [x9] -; CHECK-LSE-O1-NEXT: add w0, w8, w9 +; CHECK-LSE-O1-NEXT: add w0, w8, w9, uxth ; CHECK-LSE-O1-NEXT: ret ; ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_16: diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll index c7f3bcf640e3..c8d313cf31af 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll @@ -377,13 +377,13 @@ define i8 @atomic_load_relaxed_8(ptr %p, i32 %off32) { ; CHECK-NEXT: liveins: $w1, $x0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: renamable $w8 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unsigned) - ; CHECK-NEXT: renamable $w9 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_regoff) - ; CHECK-NEXT: renamable $w10 = LDURBBi renamable $x0, -256, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unscaled) - ; CHECK-NEXT: renamable $x11 = ADDXri killed renamable $x0, 291, 12 - ; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0 - ; CHECK-NEXT: renamable $w9 = LDRBBui killed renamable $x11, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random) - ; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w10, 0, pcsections !0 - ; CHECK-NEXT: $w0 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0 + ; CHECK-NEXT: renamable $w9 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0 :: (load unordered (s8) from %ir.ptr_regoff) + ; CHECK-NEXT: renamable $w10 = LDURBBi renamable $x0, -256 :: (load monotonic (s8) from %ir.ptr_unscaled) + ; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w9, killed renamable $w8, 0, pcsections !0 + ; CHECK-NEXT: renamable $x9 = ADDXri killed renamable $x0, 291, 12 + ; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w8, killed renamable $w10, 0, pcsections !0 + ; CHECK-NEXT: renamable $w9 = LDRBBui killed renamable $x9, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random) + ; CHECK-NEXT: renamable $w0 = ADDWrx killed renamable $w8, killed renamable $w9, 0, pcsections !0 ; CHECK-NEXT: RET undef $lr, implicit $w0 %ptr_unsigned = getelementptr i8, ptr %p, i32 4095 %val_unsigned = load atomic i8, ptr %ptr_unsigned monotonic, align 1, !pcsections !0 @@ -409,13 +409,13 @@ define i16 @atomic_load_relaxed_16(ptr %p, i32 %off32) { ; CHECK-NEXT: liveins: $w1, $x0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: renamable $w8 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unsigned) - ; CHECK-NEXT: renamable $w9 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s16) from %ir.ptr_regoff) - ; CHECK-NEXT: renamable $w10 = LDURHHi renamable $x0, -256, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unscaled) - ; CHECK-NEXT: renamable $x11 = ADDXri killed renamable $x0, 291, 12 - ; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0 - ; CHECK-NEXT: renamable $w9 = LDRHHui killed renamable $x11, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random) - ; CHECK-NEXT: $w8 = ADDWrs killed renamable $w8, killed renamable $w10, 0, pcsections !0 - ; CHECK-NEXT: $w0 = ADDWrs killed renamable $w8, killed renamable $w9, 0, pcsections !0 + ; CHECK-NEXT: renamable $w9 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1 :: (load unordered (s16) from %ir.ptr_regoff) + ; CHECK-NEXT: renamable $w10 = LDURHHi renamable $x0, -256 :: (load monotonic (s16) from %ir.ptr_unscaled) + ; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w9, killed renamable $w8, 8, pcsections !0 + ; CHECK-NEXT: renamable $x9 = ADDXri killed renamable $x0, 291, 12 + ; CHECK-NEXT: renamable $w8 = ADDWrx killed renamable $w8, killed renamable $w10, 8, pcsections !0 + ; CHECK-NEXT: renamable $w9 = LDRHHui killed renamable $x9, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random) + ; CHECK-NEXT: renamable $w0 = ADDWrx killed renamable $w8, killed renamable $w9, 8, pcsections !0 ; CHECK-NEXT: RET undef $lr, implicit $w0 %ptr_unsigned = getelementptr i16, ptr %p, i32 4095 %val_unsigned = load atomic i16, ptr %ptr_unsigned monotonic, align 2, !pcsections !0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll b/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll new file mode 100644 index 000000000000..4bb4e4882410 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/atomic-anyextending-load-crash.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel -global-isel-abort=1 -O0 -o - %s | FileCheck %s +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64e-apple-macosx14.0.0" + +define void @test(ptr %0) { +; CHECK-LABEL: test: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: sub sp, sp, #144 +; CHECK-NEXT: stp x29, x30, [sp, #128] ; 16-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 144 +; CHECK-NEXT: .cfi_offset w30, -8 +; CHECK-NEXT: .cfi_offset w29, -16 +; CHECK-NEXT: ldar w8, [x0] +; CHECK-NEXT: str w8, [sp, #116] ; 4-byte Folded Spill +; CHECK-NEXT: mov x8, #0 ; =0x0 +; CHECK-NEXT: str x8, [sp, #120] ; 8-byte Folded Spill +; CHECK-NEXT: blr x8 +; CHECK-NEXT: ldr w11, [sp, #116] ; 4-byte Folded Reload +; CHECK-NEXT: ldr x8, [sp, #120] ; 8-byte Folded Reload +; CHECK-NEXT: mov x9, sp +; CHECK-NEXT: str xzr, [x9] +; CHECK-NEXT: str xzr, [x9, #8] +; CHECK-NEXT: str xzr, [x9, #16] +; CHECK-NEXT: str xzr, [x9, #24] +; CHECK-NEXT: str xzr, [x9, #32] +; CHECK-NEXT: str xzr, [x9, #40] +; CHECK-NEXT: ; implicit-def: $x10 +; CHECK-NEXT: mov x10, x11 +; CHECK-NEXT: str x10, [x9, #48] +; CHECK-NEXT: str xzr, [x9, #56] +; CHECK-NEXT: str xzr, [x9, #64] +; CHECK-NEXT: str xzr, [x9, #72] +; CHECK-NEXT: str xzr, [x9, #80] +; CHECK-NEXT: str xzr, [x9, #88] +; CHECK-NEXT: str xzr, [x9, #96] +; CHECK-NEXT: mov x0, x8 +; CHECK-NEXT: blr x8 +; CHECK-NEXT: ldp x29, x30, [sp, #128] ; 16-byte Folded Reload +; CHECK-NEXT: add sp, sp, #144 +; CHECK-NEXT: ret +entry: + %atomic-load = load atomic i32, ptr %0 seq_cst, align 4 + %call10 = call ptr null() + call void (ptr, ...) null(ptr null, ptr null, i32 0, ptr null, ptr null, i32 0, i32 0, i32 %atomic-load, i32 0, i32 0, i32 0, i32 0, i64 0, ptr null) + ret void +} -- GitLab From 0aa982fb326effa62277028375b5c346e0f6fcf5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Fri, 5 Apr 2024 13:40:38 -0700 Subject: [PATCH 031/695] [flang][cuda] Add restriction on implicit data transfer (#87720) In section 3.4.2, some example of illegal data transfer using expression are given. One of it is when multiple device objects are part of an expression in the rhs. Current implementation allow a single device object in such case. This patch adds a similar restriction. --- flang/include/flang/Evaluate/tools.h | 16 +++++++++++----- flang/lib/Semantics/check-cuda.cpp | 16 ++++++++++++++++ flang/lib/Semantics/check-cuda.h | 2 ++ flang/test/Semantics/cuf11.cuf | 12 ++++++++++++ 4 files changed, 41 insertions(+), 5 deletions(-) create mode 100644 flang/test/Semantics/cuf11.cuf diff --git a/flang/include/flang/Evaluate/tools.h b/flang/include/flang/Evaluate/tools.h index 29065c9f01ec..ca14c144af2d 100644 --- a/flang/include/flang/Evaluate/tools.h +++ b/flang/include/flang/Evaluate/tools.h @@ -1227,18 +1227,24 @@ bool CheckForCoindexedObject(parser::ContextualMessages &, const std::optional &, const std::string &procName, const std::string &argName); -/// Check if any of the symbols part of the expression has a cuda data -/// attribute. -inline bool HasCUDAAttrs(const Expr &expr) { +// Get the number of distinct symbols with CUDA attribute in the expression. +template inline int GetNbOfCUDASymbols(const A &expr) { + semantics::UnorderedSymbolSet symbols; for (const Symbol &sym : CollectSymbols(expr)) { if (const auto *details = sym.GetUltimate().detailsIf()) { if (details->cudaDataAttr()) { - return true; + symbols.insert(sym); } } } - return false; + return symbols.size(); +} + +// Check if any of the symbols part of the expression has a CUDA data +// attribute. +template inline bool HasCUDAAttrs(const A &expr) { + return GetNbOfCUDASymbols(expr) > 0; } /// Check if the expression is a mix of host and device variables that require diff --git a/flang/lib/Semantics/check-cuda.cpp b/flang/lib/Semantics/check-cuda.cpp index c0c6ff4c1a2b..39bfc47a8eb1 100644 --- a/flang/lib/Semantics/check-cuda.cpp +++ b/flang/lib/Semantics/check-cuda.cpp @@ -9,12 +9,14 @@ #include "check-cuda.h" #include "flang/Common/template.h" #include "flang/Evaluate/fold.h" +#include "flang/Evaluate/tools.h" #include "flang/Evaluate/traverse.h" #include "flang/Parser/parse-tree-visitor.h" #include "flang/Parser/parse-tree.h" #include "flang/Parser/tools.h" #include "flang/Semantics/expression.h" #include "flang/Semantics/symbol.h" +#include "flang/Semantics/tools.h" // Once labeled DO constructs have been canonicalized and their parse subtrees // transformed into parser::DoConstructs, scan the parser::Blocks of the program @@ -413,4 +415,18 @@ void CUDAChecker::Enter(const parser::CUFKernelDoConstruct &x) { } } +void CUDAChecker::Enter(const parser::AssignmentStmt &x) { + const evaluate::Assignment *assign{semantics::GetAssignment(x)}; + int nbLhs{evaluate::GetNbOfCUDASymbols(assign->lhs)}; + int nbRhs{evaluate::GetNbOfCUDASymbols(assign->rhs)}; + auto lhsLoc{std::get(x.t).GetSource()}; + + // device to host transfer with more than one device object on the rhs is not + // legal. + if (nbLhs == 0 && nbRhs > 1) { + context_.Say(lhsLoc, + "More than one reference to a CUDA object on the right hand side of the assigment"_err_en_US); + } +} + } // namespace Fortran::semantics diff --git a/flang/lib/Semantics/check-cuda.h b/flang/lib/Semantics/check-cuda.h index d863795f16a7..aa0cb46360be 100644 --- a/flang/lib/Semantics/check-cuda.h +++ b/flang/lib/Semantics/check-cuda.h @@ -17,6 +17,7 @@ struct Program; class Messages; struct Name; class CharBlock; +struct AssignmentStmt; struct ExecutionPartConstruct; struct ExecutableConstruct; struct ActionStmt; @@ -38,6 +39,7 @@ public: void Enter(const parser::FunctionSubprogram &); void Enter(const parser::SeparateModuleSubprogram &); void Enter(const parser::CUFKernelDoConstruct &); + void Enter(const parser::AssignmentStmt &); private: SemanticsContext &context_; diff --git a/flang/test/Semantics/cuf11.cuf b/flang/test/Semantics/cuf11.cuf new file mode 100644 index 000000000000..96108e2b2455 --- /dev/null +++ b/flang/test/Semantics/cuf11.cuf @@ -0,0 +1,12 @@ +! RUN: %python %S/test_errors.py %s %flang_fc1 + +subroutine sub1() + real, device :: adev(10), bdev(10) + real :: ahost(10) + +!ERROR: More than one reference to a CUDA object on the right hand side of the assigment + ahost = adev + bdev + + ahost = adev + adev + +end subroutine -- GitLab From 8ee6ab7f69ca9c34eed56faad3971d075dc47121 Mon Sep 17 00:00:00 2001 From: aniplcc Date: Sat, 6 Apr 2024 02:22:57 +0530 Subject: [PATCH 032/695] [libc][c23][fenv] implement fesetexcept (#87603) Closes #87564 --- libc/config/baremetal/arm/entrypoints.txt | 1 + libc/config/baremetal/riscv/entrypoints.txt | 1 + libc/config/darwin/arm/entrypoints.txt | 1 + libc/config/darwin/x86_64/entrypoints.txt | 1 + libc/config/linux/aarch64/entrypoints.txt | 1 + libc/config/linux/arm/entrypoints.txt | 1 + libc/config/linux/riscv/entrypoints.txt | 1 + libc/config/linux/x86_64/entrypoints.txt | 1 + libc/config/windows/entrypoints.txt | 1 + libc/docs/c23.rst | 2 +- libc/spec/stdc.td | 5 +++ libc/src/fenv/CMakeLists.txt | 13 +++++++ libc/src/fenv/fesetexcept.cpp | 19 +++++++++++ libc/src/fenv/fesetexcept.h | 18 ++++++++++ libc/test/src/fenv/CMakeLists.txt | 1 + libc/test/src/fenv/exception_status_test.cpp | 34 ++++++++++++++++++- .../llvm-project-overlay/libc/BUILD.bazel | 10 ++++++ .../libc/test/src/fenv/BUILD.bazel | 1 + 18 files changed, 110 insertions(+), 2 deletions(-) create mode 100644 libc/src/fenv/fesetexcept.cpp create mode 100644 libc/src/fenv/fesetexcept.h diff --git a/libc/config/baremetal/arm/entrypoints.txt b/libc/config/baremetal/arm/entrypoints.txt index 9e21f5c20d92..f33f9430c792 100644 --- a/libc/config/baremetal/arm/entrypoints.txt +++ b/libc/config/baremetal/arm/entrypoints.txt @@ -196,6 +196,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/baremetal/riscv/entrypoints.txt b/libc/config/baremetal/riscv/entrypoints.txt index 7664937da0f6..dad187fa0496 100644 --- a/libc/config/baremetal/riscv/entrypoints.txt +++ b/libc/config/baremetal/riscv/entrypoints.txt @@ -196,6 +196,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/darwin/arm/entrypoints.txt b/libc/config/darwin/arm/entrypoints.txt index 6b89ce55d72b..aea2f6d5771e 100644 --- a/libc/config/darwin/arm/entrypoints.txt +++ b/libc/config/darwin/arm/entrypoints.txt @@ -107,6 +107,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/darwin/x86_64/entrypoints.txt b/libc/config/darwin/x86_64/entrypoints.txt index 5a1a6a15ef30..09fe3d7b4768 100644 --- a/libc/config/darwin/x86_64/entrypoints.txt +++ b/libc/config/darwin/x86_64/entrypoints.txt @@ -101,6 +101,7 @@ set(TARGET_LIBM_ENTRYPOINTS # libc.src.fenv.fegetround # libc.src.fenv.feholdexcept # libc.src.fenv.fesetenv + # libc.src.fenv.fesetexcept # libc.src.fenv.fesetexceptflag # libc.src.fenv.fesetround # libc.src.fenv.feraiseexcept diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index 8bf99459f789..f5f5c437685a 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -319,6 +319,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/linux/arm/entrypoints.txt b/libc/config/linux/arm/entrypoints.txt index 04baa4c1cf93..fca50735d320 100644 --- a/libc/config/linux/arm/entrypoints.txt +++ b/libc/config/linux/arm/entrypoints.txt @@ -187,6 +187,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index 4dc5e9d33f0f..71289789158f 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -327,6 +327,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index b522e7f03015..6bb53cb76220 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -337,6 +337,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/config/windows/entrypoints.txt b/libc/config/windows/entrypoints.txt index c38125a64622..c46c947bf313 100644 --- a/libc/config/windows/entrypoints.txt +++ b/libc/config/windows/entrypoints.txt @@ -105,6 +105,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.fenv.fegetround libc.src.fenv.feholdexcept libc.src.fenv.fesetenv + libc.src.fenv.fesetexcept libc.src.fenv.fesetexceptflag libc.src.fenv.fesetround libc.src.fenv.feraiseexcept diff --git a/libc/docs/c23.rst b/libc/docs/c23.rst index 152178eaf751..4138c9d7104f 100644 --- a/libc/docs/c23.rst +++ b/libc/docs/c23.rst @@ -20,7 +20,7 @@ Additions: * fenv.h - * fesetexcept + * fesetexcept |check| * fetestexceptflag * fegetmode * fesetmode diff --git a/libc/spec/stdc.td b/libc/spec/stdc.td index bd62870b07c8..63d044986711 100644 --- a/libc/spec/stdc.td +++ b/libc/spec/stdc.td @@ -179,6 +179,11 @@ def StdC : StandardSpec<"stdc"> { RetValSpec, [ArgSpec, ArgSpec] >, + FunctionSpec< + "fesetexcept", + RetValSpec, + [ArgSpec] + >, FunctionSpec< "fesetexceptflag", RetValSpec, diff --git a/libc/src/fenv/CMakeLists.txt b/libc/src/fenv/CMakeLists.txt index 0da539d187bf..d2f90d3d007a 100644 --- a/libc/src/fenv/CMakeLists.txt +++ b/libc/src/fenv/CMakeLists.txt @@ -102,6 +102,19 @@ add_entrypoint_object( -O2 ) +add_entrypoint_object( + fesetexcept + SRCS + fesetexcept.cpp + HDRS + fesetexcept.h + DEPENDS + libc.include.fenv + libc.src.__support.FPUtil.fenv_impl + COMPILE_OPTIONS + -O2 +) + add_entrypoint_object( fesetexceptflag SRCS diff --git a/libc/src/fenv/fesetexcept.cpp b/libc/src/fenv/fesetexcept.cpp new file mode 100644 index 000000000000..9afa7b73b4fb --- /dev/null +++ b/libc/src/fenv/fesetexcept.cpp @@ -0,0 +1,19 @@ +//===-- Implementation of fesetexcept function ----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/fenv/fesetexcept.h" +#include "src/__support/FPUtil/FEnvImpl.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(int, fesetexcept, (int excepts)) { + return fputil::set_except(excepts); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/fenv/fesetexcept.h b/libc/src/fenv/fesetexcept.h new file mode 100644 index 000000000000..40a7303efcb0 --- /dev/null +++ b/libc/src/fenv/fesetexcept.h @@ -0,0 +1,18 @@ +//===-- Implementation header for fesetexcept -------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_FENV_FESETEXCEPT_H +#define LLVM_LIBC_SRC_FENV_FESETEXCEPT_H + +namespace LIBC_NAMESPACE { + +int fesetexcept(int excepts); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_FENV_FESETEXCEPT_H diff --git a/libc/test/src/fenv/CMakeLists.txt b/libc/test/src/fenv/CMakeLists.txt index ba338bb6c731..7e456b9a922f 100644 --- a/libc/test/src/fenv/CMakeLists.txt +++ b/libc/test/src/fenv/CMakeLists.txt @@ -20,6 +20,7 @@ add_libc_unittest( DEPENDS libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept + libc.src.fenv.fesetexcept libc.src.fenv.fetestexcept libc.src.__support.FPUtil.fenv_impl ) diff --git a/libc/test/src/fenv/exception_status_test.cpp b/libc/test/src/fenv/exception_status_test.cpp index e4e2240fc374..cf0fd1fe1af3 100644 --- a/libc/test/src/fenv/exception_status_test.cpp +++ b/libc/test/src/fenv/exception_status_test.cpp @@ -1,4 +1,5 @@ -//===-- Unittests for feclearexcept, feraiseexcept and fetestexpect -------===// +//===-- Unittests for feclearexcept, feraiseexcept, fetestexpect ----------===// +//===-- and fesetexcept ---------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,6 +9,7 @@ #include "src/fenv/feclearexcept.h" #include "src/fenv/feraiseexcept.h" +#include "src/fenv/fesetexcept.h" #include "src/fenv/fetestexcept.h" #include "src/__support/FPUtil/FEnvImpl.h" @@ -38,6 +40,11 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(r, 0); s = LIBC_NAMESPACE::fetestexcept(e); ASSERT_EQ(s, 0); + + r = LIBC_NAMESPACE::fesetexcept(e); + ASSERT_EQ(r, 0); + s = LIBC_NAMESPACE::fetestexcept(e); + ASSERT_EQ(s, e); } for (int e1 : excepts) { @@ -52,6 +59,11 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(r, 0); s = LIBC_NAMESPACE::fetestexcept(e); ASSERT_EQ(s, 0); + + r = LIBC_NAMESPACE::fesetexcept(e); + ASSERT_EQ(r, 0); + s = LIBC_NAMESPACE::fetestexcept(e); + ASSERT_EQ(s, e); } } @@ -68,6 +80,11 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(r, 0); s = LIBC_NAMESPACE::fetestexcept(e); ASSERT_EQ(s, 0); + + r = LIBC_NAMESPACE::fesetexcept(e); + ASSERT_EQ(r, 0); + s = LIBC_NAMESPACE::fetestexcept(e); + ASSERT_EQ(s, e); } } } @@ -86,6 +103,11 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(r, 0); s = LIBC_NAMESPACE::fetestexcept(e); ASSERT_EQ(s, 0); + + r = LIBC_NAMESPACE::fesetexcept(e); + ASSERT_EQ(r, 0); + s = LIBC_NAMESPACE::fetestexcept(e); + ASSERT_EQ(s, e); } } } @@ -106,6 +128,11 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(r, 0); s = LIBC_NAMESPACE::fetestexcept(e); ASSERT_EQ(s, 0); + + r = LIBC_NAMESPACE::fesetexcept(e); + ASSERT_EQ(r, 0); + s = LIBC_NAMESPACE::fetestexcept(e); + ASSERT_EQ(s, e); } } } @@ -116,4 +143,9 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(r, 0); int s = LIBC_NAMESPACE::fetestexcept(ALL_EXCEPTS); ASSERT_EQ(s, ALL_EXCEPTS); + + r = LIBC_NAMESPACE::fesetexcept(ALL_EXCEPTS); + ASSERT_EQ(r, 0); + s = LIBC_NAMESPACE::fetestexcept(ALL_EXCEPTS); + ASSERT_EQ(s, ALL_EXCEPTS); } diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 42af5cbe8f35..13b290c4bd2b 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -1194,6 +1194,16 @@ libc_function( ], ) +libc_function( + name = "fesetexcept", + srcs = ["src/fenv/fesetexcept.cpp"], + hdrs = ["src/fenv/fesetexcept.h"], + deps = [ + ":__support_common", + ":__support_fputil_fenv_impl", + ], +) + libc_function( name = "fegetexceptflag", srcs = ["src/fenv/fegetexceptflag.cpp"], diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel index f64f78c113c0..2a268ae227fb 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel @@ -16,6 +16,7 @@ libc_test( libc_function_deps = [ "//libc:feclearexcept", "//libc:feraiseexcept", + "//libc:fesetexcept", "//libc:fetestexcept", ], deps = [ -- GitLab From 27b2d7d4bb790ec1e7430bf18b1bc2f6e0800d0d Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Fri, 5 Apr 2024 13:58:24 -0700 Subject: [PATCH 033/695] [InstallAPI] Capture & compare load commands that may differ per arch slice (#87674) * Capture reexported libraries, allowable clients, rpaths, shared cache eligibility. * Add support for select Xarch options. * Add diagnostics related to capturing these options. * Add support for verifying these attributes against what is encoded in the dylib. --- .../clang/Basic/DiagnosticDriverKinds.td | 1 + .../clang/Basic/DiagnosticInstallAPIKinds.td | 21 + clang/include/clang/InstallAPI/Context.h | 17 + .../include/clang/InstallAPI/DylibVerifier.h | 29 +- clang/include/clang/InstallAPI/MachO.h | 2 + clang/lib/InstallAPI/CMakeLists.txt | 1 + .../InstallAPI/DiagnosticBuilderWrappers.cpp | 109 +++ .../InstallAPI/DiagnosticBuilderWrappers.h | 49 ++ clang/lib/InstallAPI/DylibVerifier.cpp | 196 ++++++ clang/lib/InstallAPI/Frontend.cpp | 54 ++ clang/test/InstallAPI/binary-attributes.test | 76 ++ .../InstallAPI/driver-invalid-options.test | 6 + .../InstallAPI/reexported-frameworks.test | 638 +++++++++++++++++ clang/test/InstallAPI/rpath.test | 663 ++++++++++++++++++ clang/tools/clang-installapi/CMakeLists.txt | 1 + .../clang-installapi/ClangInstallAPI.cpp | 27 +- .../tools/clang-installapi/InstallAPIOpts.td | 40 +- clang/tools/clang-installapi/Options.cpp | 277 +++++++- clang/tools/clang-installapi/Options.h | 43 +- 19 files changed, 2234 insertions(+), 16 deletions(-) create mode 100644 clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp create mode 100644 clang/lib/InstallAPI/DiagnosticBuilderWrappers.h create mode 100644 clang/test/InstallAPI/binary-attributes.test create mode 100644 clang/test/InstallAPI/reexported-frameworks.test create mode 100644 clang/test/InstallAPI/rpath.test diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 6186a88e1c80..ed3fd9b1c4a5 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -666,6 +666,7 @@ def warn_drv_darwin_sdk_invalid_settings : Warning< "SDK settings were ignored as 'SDKSettings.json' could not be parsed">, InGroup>; +def err_missing_sysroot : Error<"no such sysroot directory: '%0'">; def err_drv_darwin_sdk_missing_arclite : Error< "SDK does not contain 'libarclite' at the path '%0'; try increasing the minimum deployment target">; diff --git a/clang/include/clang/Basic/DiagnosticInstallAPIKinds.td b/clang/include/clang/Basic/DiagnosticInstallAPIKinds.td index e3263fe9ccb9..0a477da7186b 100644 --- a/clang/include/clang/Basic/DiagnosticInstallAPIKinds.td +++ b/clang/include/clang/Basic/DiagnosticInstallAPIKinds.td @@ -19,9 +19,11 @@ def err_no_such_header_file : Error<"no such %select{public|private|project}1 he def warn_no_such_excluded_header_file : Warning<"no such excluded %select{public|private}0 header file: '%1'">, InGroup; def warn_glob_did_not_match: Warning<"glob '%0' did not match any header file">, InGroup; def err_no_such_umbrella_header_file : Error<"%select{public|private|project}1 umbrella header file not found in input: '%0'">; +def err_cannot_find_reexport : Error<"cannot find re-exported %select{framework|library}0: '%1'">; } // end of command line category. let CategoryName = "Verification" in { +// Diagnostics about symbols. def warn_target: Warning<"violations found for %0">, InGroup; def err_library_missing_symbol : Error<"declaration has external linkage, but dynamic library doesn't have symbol '%0'">; def warn_library_missing_symbol : Warning<"declaration has external linkage, but dynamic library doesn't have symbol '%0'">, InGroup; @@ -43,6 +45,25 @@ def err_dylib_symbol_flags_mismatch : Error<"dynamic library symbol '%0' is " "%select{weak defined|thread local}1, but its declaration is not">; def err_header_symbol_flags_mismatch : Error<"declaration '%0' is " "%select{weak defined|thread local}1, but symbol is not in dynamic library">; + +// Diagnostics about load commands. +def err_architecture_mismatch : Error<"architectures do not match: '%0' (provided) vs '%1' (found)">; +def warn_platform_mismatch : Warning<"platform does not match: '%0' (provided) vs '%1' (found)">, InGroup; +def err_platform_mismatch : Error<"platform does not match: '%0' (provided) vs '%1' (found)">; +def err_install_name_mismatch : Error<"install_name does not match: '%0' (provided) vs '%1' (found)">; +def err_current_version_mismatch : Error<"current_version does not match: '%0' (provided) vs '%1' (found)">; +def err_compatibility_version_mismatch : Error<"compatibility_version does not match: '%0' (provided) vs '%1' (found)">; +def err_appextension_safe_mismatch : Error<"ApplicationExtensionSafe flag does not match: '%0' (provided) vs '%1' (found)">; +def err_shared_cache_eligiblity_mismatch : Error<"NotForDyldSharedCache flag does not match: '%0' (provided) vs '%1' (found)">; +def err_no_twolevel_namespace : Error<"flat namespace libraries are not supported">; +def err_parent_umbrella_missing: Error<"parent umbrella missing from %0: '%1'">; +def err_parent_umbrella_mismatch : Error<"parent umbrella does not match: '%0' (provided) vs '%1' (found)">; +def err_reexported_libraries_missing : Error<"re-exported library missing from %0: '%1'">; +def err_reexported_libraries_mismatch : Error<"re-exported libraries do not match: '%0' (provided) vs '%1' (found)">; +def err_allowable_clients_missing : Error<"allowable client missing from %0: '%1'">; +def err_allowable_clients_mismatch : Error<"allowable clients do not match: '%0' (provided) vs '%1' (found)">; +def warn_rpaths_missing : Warning<"runpath search paths missing from %0: '%1'">, InGroup; +def warn_rpaths_mismatch : Warning<"runpath search paths do not match: '%0' (provided) vs '%1' (found)">, InGroup; } // end of Verification category. } // end of InstallAPI component diff --git a/clang/include/clang/InstallAPI/Context.h b/clang/include/clang/InstallAPI/Context.h index 54e517544b8e..8f88331a2803 100644 --- a/clang/include/clang/InstallAPI/Context.h +++ b/clang/include/clang/InstallAPI/Context.h @@ -28,6 +28,9 @@ struct InstallAPIContext { /// Library attributes that are typically passed as linker inputs. BinaryAttrs BA; + /// Install names of reexported libraries of a library. + LibAttrs Reexports; + /// All headers that represent a library. HeaderSeq InputHeaders; @@ -80,6 +83,20 @@ private: llvm::DenseMap KnownIncludes; }; +/// Lookup the dylib or TextAPI file location for a system library or framework. +/// The search paths provided are searched in order. +/// @rpath based libraries are not supported. +/// +/// \param InstallName The install name for the library. +/// \param FrameworkSearchPaths Search paths to look up frameworks with. +/// \param LibrarySearchPaths Search paths to look up dylibs with. +/// \param SearchPaths Fallback search paths if library was not found in earlier +/// paths. +/// \return The full path of the library. +std::string findLibrary(StringRef InstallName, FileManager &FM, + ArrayRef FrameworkSearchPaths, + ArrayRef LibrarySearchPaths, + ArrayRef SearchPaths); } // namespace installapi } // namespace clang diff --git a/clang/include/clang/InstallAPI/DylibVerifier.h b/clang/include/clang/InstallAPI/DylibVerifier.h index 22cdc234486c..07dbd3bf5f2b 100644 --- a/clang/include/clang/InstallAPI/DylibVerifier.h +++ b/clang/include/clang/InstallAPI/DylibVerifier.h @@ -24,6 +24,9 @@ enum class VerificationMode { Pedantic, }; +using LibAttrs = llvm::StringMap; +using ReexportedInterfaces = llvm::SmallVector; + /// Service responsible to tracking state of verification across the /// lifetime of InstallAPI. /// As declarations are collected during AST traversal, they are @@ -63,11 +66,12 @@ public: DylibVerifier() = default; - DylibVerifier(llvm::MachO::Records &&Dylib, DiagnosticsEngine *Diag, - VerificationMode Mode, bool Demangle, StringRef DSYMPath) - : Dylib(std::move(Dylib)), Mode(Mode), Demangle(Demangle), - DSYMPath(DSYMPath), Exports(std::make_unique()), - Ctx(VerifierContext{Diag}) {} + DylibVerifier(llvm::MachO::Records &&Dylib, ReexportedInterfaces &&Reexports, + DiagnosticsEngine *Diag, VerificationMode Mode, bool Demangle, + StringRef DSYMPath) + : Dylib(std::move(Dylib)), Reexports(std::move(Reexports)), Mode(Mode), + Demangle(Demangle), DSYMPath(DSYMPath), + Exports(std::make_unique()), Ctx(VerifierContext{Diag}) {} Result verify(GlobalRecord *R, const FrontendAttrs *FA); Result verify(ObjCInterfaceRecord *R, const FrontendAttrs *FA); @@ -77,6 +81,14 @@ public: // Scan through dylib slices and report any remaining missing exports. Result verifyRemainingSymbols(); + /// Compare and report the attributes represented as + /// load commands in the dylib to the attributes provided via options. + bool verifyBinaryAttrs(const ArrayRef ProvidedTargets, + const BinaryAttrs &ProvidedBA, + const LibAttrs &ProvidedReexports, + const LibAttrs &ProvidedClients, + const LibAttrs &ProvidedRPaths, const FileType &FT); + /// Initialize target for verification. void setTarget(const Target &T); @@ -105,6 +117,10 @@ private: bool shouldIgnoreObsolete(const Record *R, SymbolContext &SymCtx, const Record *DR); + /// Check if declaration is exported from a reexported library. These + /// symbols should be omitted from the text-api file. + bool shouldIgnoreReexport(const Record *R, SymbolContext &SymCtx) const; + /// Compare the visibility declarations to the linkage of symbol found in /// dylib. Result compareVisibility(const Record *R, SymbolContext &SymCtx, @@ -154,6 +170,9 @@ private: // Symbols in dylib. llvm::MachO::Records Dylib; + // Reexported interfaces apart of the library. + ReexportedInterfaces Reexports; + // Controls what class of violations to report. VerificationMode Mode = VerificationMode::Invalid; diff --git a/clang/include/clang/InstallAPI/MachO.h b/clang/include/clang/InstallAPI/MachO.h index 827220dbf39f..854399f54ba6 100644 --- a/clang/include/clang/InstallAPI/MachO.h +++ b/clang/include/clang/InstallAPI/MachO.h @@ -23,6 +23,8 @@ #include "llvm/TextAPI/TextAPIWriter.h" #include "llvm/TextAPI/Utils.h" +using Architecture = llvm::MachO::Architecture; +using ArchitectureSet = llvm::MachO::ArchitectureSet; using SymbolFlags = llvm::MachO::SymbolFlags; using RecordLinkage = llvm::MachO::RecordLinkage; using Record = llvm::MachO::Record; diff --git a/clang/lib/InstallAPI/CMakeLists.txt b/clang/lib/InstallAPI/CMakeLists.txt index e0bc8d969ecb..b36493942300 100644 --- a/clang/lib/InstallAPI/CMakeLists.txt +++ b/clang/lib/InstallAPI/CMakeLists.txt @@ -7,6 +7,7 @@ set(LLVM_LINK_COMPONENTS ) add_clang_library(clangInstallAPI + DiagnosticBuilderWrappers.cpp DylibVerifier.cpp FileList.cpp Frontend.cpp diff --git a/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp b/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp new file mode 100644 index 000000000000..1fa988f93bdd --- /dev/null +++ b/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp @@ -0,0 +1,109 @@ +//===- DiagnosticBuilderWrappers.cpp ----------------------------*- C++-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "DiagnosticBuilderWrappers.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/TextAPI/Platform.h" + +using clang::DiagnosticBuilder; + +namespace llvm { +namespace MachO { +const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, + const Architecture &Arch) { + DB.AddString(getArchitectureName(Arch)); + return DB; +} + +const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, + const ArchitectureSet &ArchSet) { + DB.AddString(std::string(ArchSet)); + return DB; +} + +const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, + const PlatformType &Platform) { + DB.AddString(getPlatformName(Platform)); + return DB; +} + +const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, + const PlatformVersionSet &Platforms) { + std::string PlatformAsString; + raw_string_ostream Stream(PlatformAsString); + + Stream << "[ "; + llvm::interleaveComma( + Platforms, Stream, + [&Stream](const std::pair &PV) { + Stream << getPlatformName(PV.first); + if (!PV.second.empty()) + Stream << PV.second.getAsString(); + }); + Stream << " ]"; + DB.AddString(Stream.str()); + return DB; +} + +const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, + const FileType &Type) { + switch (Type) { + case FileType::MachO_Bundle: + DB.AddString("mach-o bundle"); + return DB; + case FileType::MachO_DynamicLibrary: + DB.AddString("mach-o dynamic library"); + return DB; + case FileType::MachO_DynamicLibrary_Stub: + DB.AddString("mach-o dynamic library stub"); + return DB; + case FileType::TBD_V1: + DB.AddString("tbd-v1"); + return DB; + case FileType::TBD_V2: + DB.AddString("tbd-v2"); + return DB; + case FileType::TBD_V3: + DB.AddString("tbd-v3"); + return DB; + case FileType::TBD_V4: + DB.AddString("tbd-v4"); + return DB; + case FileType::TBD_V5: + DB.AddString("tbd-v5"); + return DB; + case FileType::Invalid: + case FileType::All: + llvm_unreachable("Unexpected file type for diagnostics."); + } +} + +const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, + const PackedVersion &Version) { + std::string VersionString; + raw_string_ostream OS(VersionString); + OS << Version; + DB.AddString(OS.str()); + return DB; +} + +const clang::DiagnosticBuilder & +operator<<(const clang::DiagnosticBuilder &DB, + const StringMapEntry &LibAttr) { + std::string IFAsString; + raw_string_ostream OS(IFAsString); + + OS << LibAttr.getKey() << " [ " << LibAttr.getValue() << " ]"; + DB.AddString(OS.str()); + return DB; +} + +} // namespace MachO +} // namespace llvm diff --git a/clang/lib/InstallAPI/DiagnosticBuilderWrappers.h b/clang/lib/InstallAPI/DiagnosticBuilderWrappers.h new file mode 100644 index 000000000000..48cfefbf65e6 --- /dev/null +++ b/clang/lib/InstallAPI/DiagnosticBuilderWrappers.h @@ -0,0 +1,49 @@ +//===- DiagnosticBuilderWrappers.h -----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +/// Diagnostic wrappers for TextAPI types for error reporting. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_INSTALLAPI_DIAGNOSTICBUILDER_WRAPPER_H +#define LLVM_CLANG_INSTALLAPI_DIAGNOSTICBUILDER_WRAPPER_H + +#include "clang/Basic/Diagnostic.h" +#include "llvm/TextAPI/Architecture.h" +#include "llvm/TextAPI/ArchitectureSet.h" +#include "llvm/TextAPI/InterfaceFile.h" +#include "llvm/TextAPI/Platform.h" + +namespace llvm { +namespace MachO { + +const clang::DiagnosticBuilder &operator<<(const clang::DiagnosticBuilder &DB, + const PlatformType &Platform); + +const clang::DiagnosticBuilder &operator<<(const clang::DiagnosticBuilder &DB, + const PlatformVersionSet &Platforms); + +const clang::DiagnosticBuilder &operator<<(const clang::DiagnosticBuilder &DB, + const Architecture &Arch); + +const clang::DiagnosticBuilder &operator<<(const clang::DiagnosticBuilder &DB, + const ArchitectureSet &ArchSet); + +const clang::DiagnosticBuilder &operator<<(const clang::DiagnosticBuilder &DB, + const FileType &Type); + +const clang::DiagnosticBuilder &operator<<(const clang::DiagnosticBuilder &DB, + const PackedVersion &Version); + +const clang::DiagnosticBuilder & +operator<<(const clang::DiagnosticBuilder &DB, + const StringMapEntry &LibAttr); + +} // namespace MachO +} // namespace llvm +#endif // LLVM_CLANG_INSTALLAPI_DIAGNOSTICBUILDER_WRAPPER_H diff --git a/clang/lib/InstallAPI/DylibVerifier.cpp b/clang/lib/InstallAPI/DylibVerifier.cpp index c0eda1d81b9b..2387ee0e78ad 100644 --- a/clang/lib/InstallAPI/DylibVerifier.cpp +++ b/clang/lib/InstallAPI/DylibVerifier.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "clang/InstallAPI/DylibVerifier.h" +#include "DiagnosticBuilderWrappers.h" #include "clang/InstallAPI/FrontendRecords.h" #include "clang/InstallAPI/InstallAPIDiagnostic.h" #include "llvm/Demangle/Demangle.h" @@ -178,6 +179,22 @@ bool DylibVerifier::shouldIgnoreObsolete(const Record *R, SymbolContext &SymCtx, return SymCtx.FA->Avail.isObsoleted(); } +bool DylibVerifier::shouldIgnoreReexport(const Record *R, + SymbolContext &SymCtx) const { + if (Reexports.empty()) + return false; + + for (const InterfaceFile &Lib : Reexports) { + if (!Lib.hasTarget(Ctx.Target)) + continue; + if (auto Sym = + Lib.getSymbol(SymCtx.Kind, SymCtx.SymbolName, SymCtx.ObjCIFKind)) + if ((*Sym)->hasTarget(Ctx.Target)) + return true; + } + return false; +} + bool DylibVerifier::compareObjCInterfaceSymbols(const Record *R, SymbolContext &SymCtx, const ObjCInterfaceRecord *DR) { @@ -383,6 +400,11 @@ DylibVerifier::Result DylibVerifier::verifyImpl(Record *R, return Ctx.FrontendState; } + if (shouldIgnoreReexport(R, SymCtx)) { + updateState(Result::Ignore); + return Ctx.FrontendState; + } + Record *DR = findRecordFromSlice(Ctx.DylibSlice, SymCtx.SymbolName, SymCtx.Kind); if (DR) @@ -702,5 +724,179 @@ DylibVerifier::Result DylibVerifier::verifyRemainingSymbols() { return getState(); } +bool DylibVerifier::verifyBinaryAttrs(const ArrayRef ProvidedTargets, + const BinaryAttrs &ProvidedBA, + const LibAttrs &ProvidedReexports, + const LibAttrs &ProvidedClients, + const LibAttrs &ProvidedRPaths, + const FileType &FT) { + assert(!Dylib.empty() && "Need dylib to verify."); + + // Pickup any load commands that can differ per slice to compare. + TargetList DylibTargets; + LibAttrs DylibReexports; + LibAttrs DylibClients; + LibAttrs DylibRPaths; + for (const std::shared_ptr &RS : Dylib) { + DylibTargets.push_back(RS->getTarget()); + const BinaryAttrs &BinInfo = RS->getBinaryAttrs(); + for (const StringRef LibName : BinInfo.RexportedLibraries) + DylibReexports[LibName].set(DylibTargets.back().Arch); + for (const StringRef LibName : BinInfo.AllowableClients) + DylibClients[LibName].set(DylibTargets.back().Arch); + // Compare attributes that are only representable in >= TBD_V5. + if (FT >= FileType::TBD_V5) + for (const StringRef Name : BinInfo.RPaths) + DylibRPaths[Name].set(DylibTargets.back().Arch); + } + + // Check targets first. + ArchitectureSet ProvidedArchs = mapToArchitectureSet(ProvidedTargets); + ArchitectureSet DylibArchs = mapToArchitectureSet(DylibTargets); + if (ProvidedArchs != DylibArchs) { + Ctx.Diag->Report(diag::err_architecture_mismatch) + << ProvidedArchs << DylibArchs; + return false; + } + auto ProvidedPlatforms = mapToPlatformVersionSet(ProvidedTargets); + auto DylibPlatforms = mapToPlatformVersionSet(DylibTargets); + if (ProvidedPlatforms != DylibPlatforms) { + const bool DiffMinOS = + mapToPlatformSet(ProvidedTargets) == mapToPlatformSet(DylibTargets); + if (DiffMinOS) + Ctx.Diag->Report(diag::warn_platform_mismatch) + << ProvidedPlatforms << DylibPlatforms; + else { + Ctx.Diag->Report(diag::err_platform_mismatch) + << ProvidedPlatforms << DylibPlatforms; + return false; + } + } + + // Because InstallAPI requires certain attributes to match across architecture + // slices, take the first one to compare those with. + const BinaryAttrs &DylibBA = (*Dylib.begin())->getBinaryAttrs(); + + if (ProvidedBA.InstallName != DylibBA.InstallName) { + Ctx.Diag->Report(diag::err_install_name_mismatch) + << ProvidedBA.InstallName << DylibBA.InstallName; + return false; + } + + if (ProvidedBA.CurrentVersion != DylibBA.CurrentVersion) { + Ctx.Diag->Report(diag::err_current_version_mismatch) + << ProvidedBA.CurrentVersion << DylibBA.CurrentVersion; + return false; + } + + if (ProvidedBA.CompatVersion != DylibBA.CompatVersion) { + Ctx.Diag->Report(diag::err_compatibility_version_mismatch) + << ProvidedBA.CompatVersion << DylibBA.CompatVersion; + return false; + } + + if (ProvidedBA.AppExtensionSafe != DylibBA.AppExtensionSafe) { + Ctx.Diag->Report(diag::err_appextension_safe_mismatch) + << (ProvidedBA.AppExtensionSafe ? "true" : "false") + << (DylibBA.AppExtensionSafe ? "true" : "false"); + return false; + } + + if (!DylibBA.TwoLevelNamespace) { + Ctx.Diag->Report(diag::err_no_twolevel_namespace); + return false; + } + + if (ProvidedBA.OSLibNotForSharedCache != DylibBA.OSLibNotForSharedCache) { + Ctx.Diag->Report(diag::err_shared_cache_eligiblity_mismatch) + << (ProvidedBA.OSLibNotForSharedCache ? "true" : "false") + << (DylibBA.OSLibNotForSharedCache ? "true" : "false"); + return false; + } + + if (ProvidedBA.ParentUmbrella.empty() && !DylibBA.ParentUmbrella.empty()) { + Ctx.Diag->Report(diag::err_parent_umbrella_missing) + << "installAPI option" << DylibBA.ParentUmbrella; + return false; + } + + if (!ProvidedBA.ParentUmbrella.empty() && DylibBA.ParentUmbrella.empty()) { + Ctx.Diag->Report(diag::err_parent_umbrella_missing) + << "binary file" << ProvidedBA.ParentUmbrella; + return false; + } + + if ((!ProvidedBA.ParentUmbrella.empty()) && + (ProvidedBA.ParentUmbrella != DylibBA.ParentUmbrella)) { + Ctx.Diag->Report(diag::err_parent_umbrella_mismatch) + << ProvidedBA.ParentUmbrella << DylibBA.ParentUmbrella; + return false; + } + + auto CompareLibraries = [&](const LibAttrs &Provided, const LibAttrs &Dylib, + unsigned DiagID_missing, unsigned DiagID_mismatch, + bool Fatal = true) { + if (Provided == Dylib) + return true; + + for (const llvm::StringMapEntry &PAttr : Provided) { + const auto DAttrIt = Dylib.find(PAttr.getKey()); + if (DAttrIt == Dylib.end()) { + Ctx.Diag->Report(DiagID_missing) << "binary file" << PAttr; + if (Fatal) + return false; + } + + if (PAttr.getValue() != DAttrIt->getValue()) { + Ctx.Diag->Report(DiagID_mismatch) << PAttr << *DAttrIt; + if (Fatal) + return false; + } + } + + for (const llvm::StringMapEntry &DAttr : Dylib) { + const auto PAttrIt = Provided.find(DAttr.getKey()); + if (PAttrIt == Provided.end()) { + Ctx.Diag->Report(DiagID_missing) << "installAPI option" << DAttr; + if (!Fatal) + continue; + return false; + } + + if (PAttrIt->getValue() != DAttr.getValue()) { + if (Fatal) + llvm_unreachable("this case was already covered above."); + } + } + return true; + }; + + if (!CompareLibraries(ProvidedReexports, DylibReexports, + diag::err_reexported_libraries_missing, + diag::err_reexported_libraries_mismatch)) + return false; + + if (!CompareLibraries(ProvidedClients, DylibClients, + diag::err_allowable_clients_missing, + diag::err_allowable_clients_mismatch)) + return false; + + if (FT >= FileType::TBD_V5) { + // Ignore rpath differences if building an asan variant, since the + // compiler injects additional paths. + // FIXME: Building with sanitizers does not always change the install + // name, so this is not a foolproof solution. + if (!ProvidedBA.InstallName.ends_with("_asan")) { + if (!CompareLibraries(ProvidedRPaths, DylibRPaths, + diag::warn_rpaths_missing, + diag::warn_rpaths_mismatch, + /*Fatal=*/false)) + return true; + } + } + + return true; +} + } // namespace installapi } // namespace clang diff --git a/clang/lib/InstallAPI/Frontend.cpp b/clang/lib/InstallAPI/Frontend.cpp index e07ccb14e0b8..bd7589c13e04 100644 --- a/clang/lib/InstallAPI/Frontend.cpp +++ b/clang/lib/InstallAPI/Frontend.cpp @@ -162,4 +162,58 @@ std::unique_ptr createInputBuffer(InstallAPIContext &Ctx) { return llvm::MemoryBuffer::getMemBufferCopy(Contents, BufferName); } +std::string findLibrary(StringRef InstallName, FileManager &FM, + ArrayRef FrameworkSearchPaths, + ArrayRef LibrarySearchPaths, + ArrayRef SearchPaths) { + auto getLibrary = + [&](const StringRef FullPath) -> std::optional { + // Prefer TextAPI files when possible. + SmallString TextAPIFilePath = FullPath; + replace_extension(TextAPIFilePath, ".tbd"); + + if (FM.getOptionalFileRef(TextAPIFilePath)) + return std::string(TextAPIFilePath); + + if (FM.getOptionalFileRef(FullPath)) + return std::string(FullPath); + + return std::nullopt; + }; + + const StringRef Filename = sys::path::filename(InstallName); + const bool IsFramework = sys::path::parent_path(InstallName) + .ends_with((Filename + ".framework").str()); + if (IsFramework) { + for (const StringRef Path : FrameworkSearchPaths) { + SmallString FullPath(Path); + sys::path::append(FullPath, Filename + StringRef(".framework"), Filename); + if (auto LibOrNull = getLibrary(FullPath)) + return *LibOrNull; + } + } else { + // Copy Apple's linker behavior: If this is a .dylib inside a framework, do + // not search -L paths. + bool IsEmbeddedDylib = (sys::path::extension(InstallName) == ".dylib") && + InstallName.contains(".framework/"); + if (!IsEmbeddedDylib) { + for (const StringRef Path : LibrarySearchPaths) { + SmallString FullPath(Path); + sys::path::append(FullPath, Filename); + if (auto LibOrNull = getLibrary(FullPath)) + return *LibOrNull; + } + } + } + + for (const StringRef Path : SearchPaths) { + SmallString FullPath(Path); + sys::path::append(FullPath, InstallName); + if (auto LibOrNull = getLibrary(FullPath)) + return *LibOrNull; + } + + return {}; +} + } // namespace clang::installapi diff --git a/clang/test/InstallAPI/binary-attributes.test b/clang/test/InstallAPI/binary-attributes.test new file mode 100644 index 000000000000..d97c7a14a98d --- /dev/null +++ b/clang/test/InstallAPI/binary-attributes.test @@ -0,0 +1,76 @@ +; RUN: rm -rf %t +; RUN: split-file %s %t +; RUN: mkdir -p %t/System/Library/Frameworks +; RUN: cp -r %S/Inputs/Simple/Simple.framework %t/System/Library/Frameworks/ +; RUN: yaml2obj %S/Inputs/Simple/Simple.yaml -o %t/Simple + +; RUN: not clang-installapi -target x86_64h-apple-macos10.12 \ +; RUN: -install_name Simple -current_version 3 -compatibility_version 2 \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=ARCHITECTURE %s +; ARCHITECTURE: error: architectures do not match: 'x86_64h' (provided) vs 'x86_64' (found) + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name Simple -current_version 3 -compatibility_version 2 \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=INSTALL_NAME %s +; INSTALL_NAME: error: install_name does not match: 'Simple' (provided) vs '/System/Library/Frameworks/Simple.framework/Versions/A/Simple' (found) + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 3 -compatibility_version 2 \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=CURRENT_VERSION %s +; CURRENT_VERSION: error: current_version does not match: '3' (provided) vs '1.2.3' (found) + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 1.2.3 -compatibility_version 2 \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=COMPATIBILITY_VERSION %s +; COMPATIBILITY_VERSION: error: compatibility_version does not match: '2' (provided) vs '1' (found) + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 1.2.3 -compatibility_version 1 -fapplication-extension \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=APPEXTSAFE %s +; APPEXTSAFE: error: ApplicationExtensionSafe flag does not match: 'true' (provided) vs 'false' (found) + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 1.2.3 -compatibility_version 1 -not_for_dyld_shared_cache \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=SHARED_CACHE %s +; SHARED_CACHE: error: NotForDyldSharedCache flag does not match: 'true' (provided) vs 'false' (found) + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 1.2.3 -compatibility_version 1 \ +; RUN: -allowable_client Foo -allowable_client Bar \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=ALLOWABLE %s +; ALLOWABLE: error: allowable client missing from binary file: 'Foo [ x86_64 ]' + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 1.2.3 -compatibility_version 1 -reexport_library %t/Foo.tbd \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=REEXPORT %s +; REEXPORT: error: re-exported library missing from binary file: 'Foo [ x86_64 ]' + +; RUN: not clang-installapi -target x86_64-apple-macos10.12 \ +; RUN: -install_name /System/Library/Frameworks/Simple.framework/Versions/A/Simple \ +; RUN: -current_version 1.2.3 -compatibility_version 1 -umbrella Bogus \ +; RUN: -o tmp.tbd --verify-against=%t/Simple 2>&1 | FileCheck -check-prefix=UMBRELLA %s +; UMBRELLA: error: parent umbrella missing from binary file: 'Bogus' + +;--- Foo.tbd +{ + "main_library": { + "install_names": [ + { + "name": "Foo" + } + ], + "target_info": [ + { + "min_deployment": "13.0", + "target": "arm64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} diff --git a/clang/test/InstallAPI/driver-invalid-options.test b/clang/test/InstallAPI/driver-invalid-options.test index 0c630eacd183..2b2c551fca20 100644 --- a/clang/test/InstallAPI/driver-invalid-options.test +++ b/clang/test/InstallAPI/driver-invalid-options.test @@ -13,3 +13,9 @@ // RUN: --verify-mode=Invalid -o tmp.tbd 2> %t // RUN: FileCheck --check-prefix INVALID_VERIFY_MODE -input-file %t %s // INVALID_VERIFY_MODE: error: invalid value 'Invalid' in '--verify-mode=Invalid' + +/// Check that invalid sysroot is fatal. +// RUN: not clang-installapi -install_name Foo -target arm64-apple-ios13 \ +// RUN: -isysroot /no/such/path -o tmp.tbd 2> %t +// RUN: FileCheck --check-prefix INVALID_ISYSROOT -input-file %t %s +// INVALID_ISYSROOT: error: no such sysroot directory: {{.*}}no/such/path' diff --git a/clang/test/InstallAPI/reexported-frameworks.test b/clang/test/InstallAPI/reexported-frameworks.test new file mode 100644 index 000000000000..41c4f539c0b1 --- /dev/null +++ b/clang/test/InstallAPI/reexported-frameworks.test @@ -0,0 +1,638 @@ +; RUN: rm -rf %t +; RUN: split-file %s %t +; RUN: sed -e "s|DSTROOT|%/t|g" %t/inputs.json.in > %t/inputs.json + +; RUN: yaml2obj %t/Umbrella.yaml -o %t/Umbrella +; RUN: mkdir -p %t/System/Library/Frameworks/Bar.framework +; RUN: yaml2obj %t/Bar.yaml -o %t/System/Library/Frameworks/Bar.framework/Bar + +; RUN: clang-installapi -target x86_64-apple-macosx13 -install_name \ +; RUN: /System/Library/Frameworks/Umbrella3.framework/Versions/A/Umbrella3 \ +; RUN: -current_version 1 -compatibility_version 1 \ +; RUN: --verify-against=%t/Umbrella \ +; RUN: -F %t/System/Library/Frameworks -L %t/usr/lib \ +; RUN: %t/inputs.json --verify-mode=Pedantic \ +; RUN: -reexport_framework Foo -reexport_framework Bar -reexport-lBaz \ +; RUN: -o %t/Umbrella.tbd 2>&1 | FileCheck -allow-empty %s +; RUN: llvm-readtapi -compare %t/Umbrella.tbd %t/expected.tbd 2>&1 | FileCheck -allow-empty %s + +// Checks that one of the reexported frameworks found earlier doesn't resolve +// a missing export from a declaration. +; RUN: not clang-installapi -target x86_64-apple-macosx13 -install_name \ +; RUN: /System/Library/Frameworks/Umbrella3.framework/Versions/A/Umbrella3 \ +; RUN: -current_version 1 -compatibility_version 1 \ +; RUN: --verify-against=%t/Umbrella \ +; RUN: %t/inputs.json -F %t/BadFoo \ +; RUN: -F %t/System/Library/Frameworks -L %t/usr/lib \ +; RUN: --verify-mode=ErrorsOnly \ +; RUN: -reexport_framework Foo -reexport_framework Bar -reexport-lBaz \ +; RUN: -o %t/Umbrella.tbd 2>&1 | FileCheck %s --check-prefix MISSING_SYMBOL + +; MISSING_SYMBOL: error: declaration has external linkage, but dynamic library doesn't have symbol 'foo' +; MISSING_SYMBOL-NEXT: extern int foo(); + + +; CHECK-NOT: error +; CHECK-NOT: warning + +;--- System/Library/Frameworks/Umbrella.framework/Headers/Bar.h +extern int bar(); + +;--- System/Library/Frameworks/Umbrella.framework/Headers/Baz.h +extern int baz(); + +;--- System/Library/Frameworks/Umbrella.framework/Headers/Foo.h +extern int foo(); + +;--- System/Library/Frameworks/Umbrella.framework/Headers/Umbrella.h +#import +#import +#import + +;--- inputs.json.in +{ + "headers": [ { + "path" : "DSTROOT/System/Library/Frameworks/Umbrella.framework/Headers/Bar.h", + "type" : "public" + }, + { + "path" : "DSTROOT/System/Library/Frameworks/Umbrella.framework/Headers/Baz.h", + "type" : "public" + }, + { + "path" : "DSTROOT/System/Library/Frameworks/Umbrella.framework/Headers/Umbrella.h", + "type" : "public" + }, + { + "path" : "DSTROOT/System/Library/Frameworks/Umbrella.framework/Headers/Foo.h", + "type" : "public" + } + ], + "version": "3" +} + +;--- Umbrella.yaml +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x1000007 + cpusubtype: 0x3 + filetype: 0x6 + ncmds: 18 + sizeofcmds: 1184 + flags: 0x85 + reserved: 0x0 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __TEXT + vmaddr: 0 + vmsize: 12288 + fileoff: 0 + filesize: 12288 + maxprot: 5 + initprot: 5 + nsects: 1 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x24C0 + size: 0 + offset: 0x24C0 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x80000000 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '' + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA_CONST + vmaddr: 12288 + vmsize: 4096 + fileoff: 12288 + filesize: 4096 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 16 + Sections: + - sectname: __objc_imageinfo + segname: __DATA_CONST + addr: 0x3000 + size: 8 + offset: 0x3000 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '0000000040000000' + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 16384 + vmsize: 48 + fileoff: 16384 + filesize: 48 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 0 + export_size: 0 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 16392 + nsyms: 1 + stroff: 16408 + strsize: 24 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 0 + iundefsym: 0 + nundefsym: 1 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_ID_DYLIB + cmdsize: 96 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '/System/Library/Frameworks/Umbrella3.framework/Versions/A/Umbrella3' + ZeroPadBytes: 5 + - cmd: LC_UUID + cmdsize: 24 + uuid: 4C4C44AE-5555-3144-A1D3-33A5C6F7B36A + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 851968 + sdk: 983040 + ntools: 1 + Tools: + - tool: 4 + version: 1245184 + - cmd: LC_LOAD_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '/System/Library/Frameworks/Foo.framework/Versions/A/Foo' + ZeroPadBytes: 1 + - cmd: LC_REEXPORT_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 0 + compatibility_version: 0 + Content: '/System/Library/Frameworks/Foo.framework/Versions/A/Foo' + ZeroPadBytes: 1 + - cmd: LC_LOAD_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '/System/Library/Frameworks/Bar.framework/Versions/A/Bar' + ZeroPadBytes: 1 + - cmd: LC_REEXPORT_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 0 + compatibility_version: 0 + Content: '/System/Library/Frameworks/Bar.framework/Versions/A/Bar' + ZeroPadBytes: 1 + - cmd: LC_LOAD_DYLIB + cmdsize: 48 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '/usr/lib/libBaz.1.dylib' + ZeroPadBytes: 1 + - cmd: LC_REEXPORT_DYLIB + cmdsize: 48 + dylib: + name: 24 + timestamp: 0 + current_version: 0 + compatibility_version: 0 + Content: '/usr/lib/libBaz.1.dylib' + ZeroPadBytes: 1 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 0 + current_version: 88539136 + compatibility_version: 65536 + Content: '/usr/lib/libSystem.B.dylib' + ZeroPadBytes: 6 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 16384 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 16392 + datasize: 0 +LinkEditData: + NameList: + - n_strx: 2 + n_type: 0x1 + n_sect: 0 + n_desc: 1024 + n_value: 0 + StringTable: + - ' ' + - dyld_stub_binder + - '' + - '' + - '' + - '' + - '' +... + +;--- System/Library/Frameworks/Foo.framework/Foo.tbd +{ + "main_library": { + "exported_symbols": [ + { + "text": { + "global": [ + "_foo" + ] + } + } + ], + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "/System/Library/Frameworks/Foo.framework/Versions/A/Foo" + } + ], + "target_info": [ + { + "min_deployment": "13", + "target": "x86_64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} + +;--- Bar.yaml +--- !mach-o +FileHeader: + magic: 0xFEEDFACF + cputype: 0x1000007 + cpusubtype: 0x3 + filetype: 0x6 + ncmds: 12 + sizeofcmds: 912 + flags: 0x100085 + reserved: 0x0 +LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 312 + segname: __TEXT + vmaddr: 0 + vmsize: 8192 + fileoff: 0 + filesize: 8192 + maxprot: 5 + initprot: 5 + nsects: 3 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0xBB0 + size: 8 + offset: 0xBB0 + align: 4 + reloff: 0x0 + nreloc: 0 + flags: 0x80000400 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: 554889E531C05DC3 + - sectname: __unwind_info + segname: __TEXT + addr: 0xBB8 + size: 4152 + offset: 0xBB8 + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: 010000001C000000010000002000000000000000200000000200000000000001B00B00003800000038000000B80B00000000000038000000030000000C000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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+ - sectname: __eh_frame + segname: __TEXT + addr: 0x1BF0 + size: 24 + offset: 0x1BF0 + align: 3 + reloff: 0x0 + nreloc: 0 + flags: 0x6000000B + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: 1400000000000000017A520001781001100C070890010000 + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA_CONST + vmaddr: 8192 + vmsize: 4096 + fileoff: 8192 + filesize: 4096 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 16 + Sections: + - sectname: __objc_imageinfo + segname: __DATA_CONST + addr: 0x2000 + size: 8 + offset: 0x2000 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '0000000040000000' + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 12288 + vmsize: 80 + fileoff: 12288 + filesize: 80 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 12288 + export_size: 16 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 12312 + nsyms: 2 + stroff: 12344 + strsize: 24 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 1 + iundefsym: 1 + nundefsym: 1 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_ID_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '/System/Library/Frameworks/Bar.framework/Versions/A/Bar' + ZeroPadBytes: 1 + - cmd: LC_UUID + cmdsize: 24 + uuid: 4C4C4415-5555-3144-A11E-3C68D85CC061 + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 851968 + sdk: 983040 + ntools: 1 + Tools: + - tool: 4 + version: 1245184 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 0 + current_version: 88539136 + compatibility_version: 65536 + Content: '/usr/lib/libSystem.B.dylib' + ZeroPadBytes: 6 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 12304 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 12312 + datasize: 0 +LinkEditData: + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0 + Address: 0x0 + Other: 0x0 + ImportName: '' + Children: + - TerminalSize: 3 + NodeOffset: 8 + Name: _bar + Flags: 0x0 + Address: 0xBB0 + Other: 0x0 + ImportName: '' + NameList: + - n_strx: 2 + n_type: 0xF + n_sect: 1 + n_desc: 0 + n_value: 2992 + - n_strx: 7 + n_type: 0x1 + n_sect: 0 + n_desc: 256 + n_value: 0 + StringTable: + - ' ' + - _bar + - dyld_stub_binder + FunctionStarts: [ 0xBB0 ] +... + +;--- usr/lib/libBaz.tbd +{ + "main_library": { + "exported_symbols": [ + { + "text": { + "global": [ + "_baz" + ] + } + } + ], + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "/usr/lib/libBaz.1.dylib" + } + ], + "target_info": [ + { + "min_deployment": "13", + "target": "x86_64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} + +;--- BadFoo/Foo.framework/Foo.tbd +{ + "main_library": { + "exported_symbols": [ + { + "text": { + "global": [ + "_not_so_foo" + ] + } + } + ], + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "/System/Library/Frameworks/Foo.framework/Versions/A/Foo" + } + ], + "target_info": [ + { + "min_deployment": "13", + "target": "x86_64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} + +;--- expected.tbd +{ + "main_library": { + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "/System/Library/Frameworks/Umbrella3.framework/Versions/A/Umbrella3" + } + ], + "reexported_libraries": [ + { + "names": [ + "/System/Library/Frameworks/Bar.framework/Versions/A/Bar", + "/System/Library/Frameworks/Foo.framework/Versions/A/Foo", + "/usr/lib/libBaz.1.dylib" + ] + } + ], + "target_info": [ + { + "min_deployment": "13", + "target": "x86_64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} diff --git a/clang/test/InstallAPI/rpath.test b/clang/test/InstallAPI/rpath.test new file mode 100644 index 000000000000..083a15419aba --- /dev/null +++ b/clang/test/InstallAPI/rpath.test @@ -0,0 +1,663 @@ +; RUN: rm -rf %t +; RUN: split-file %s %t +; RUN: yaml2obj %t/RPath.yaml -o %t/RPath + +; RUN: clang-installapi --filetype=tbd-v5 \ +; RUN: -target arm64-apple-macos13.0 -target x86_64-apple-macos13.0 \ +; RUN: -install_name @rpath/Frameworks/RPath.framework/Versions/A/RPath \ +; RUN: -current_version 1 -compatibility_version 1 \ +; RUN: --extra-public-header=%t/public.h \ +; RUN: -o %t/RPath_warnings.tbd \ +; RUN: --verify-against=%t/RPath \ +; RUN: --verify-mode=Pedantic 2>&1 | FileCheck %s --check-prefix=MISSING +; RUN: llvm-readtapi --compare %t/RPath_warnings.tbd %t/expected_no_rpaths.tbd + +; MISSING: warning: runpath search paths missing from installAPI option: '@loader_path/../../../SharedFrameworks/ [ x86_64 arm64 ]' +; MISSING: warning: runpath search paths missing from installAPI option: '@loader_path/../../PrivateFrameworks/ [ x86_64 arm64 ]' + +; RUN: clang-installapi --filetype=tbd-v5 \ +; RUN: -target arm64-apple-macos13.0 -target x86_64-apple-macos13.0 \ +; RUN: -install_name @rpath/Frameworks/RPath.framework/Versions/A/RPath \ +; RUN: -current_version 1 -compatibility_version 1 \ +; RUN: --extra-public-header=%t/public.h \ +; RUN: -Xarch_arm64 -rpath @loader_path/../../../SharedFrameworks/ \ +; RUN: -o %t/RPath_Xarch.tbd \ +; RUN: --verify-against=%t/RPath \ +; RUN: --verify-mode=Pedantic 2>&1 | FileCheck %s --check-prefix=XARCH +; RUN: llvm-readtapi --compare %t/RPath_Xarch.tbd %t/expected_xarch_rpaths.tbd + +; XARCH: warning: runpath search paths do not match: '@loader_path/../../../SharedFrameworks/ [ arm64 ]' (provided) vs '@loader_path/../../../SharedFrameworks/ [ x86_64 arm64 ]' +; XARCH: warning: runpath search paths missing from installAPI option: '@loader_path/../../PrivateFrameworks/ [ x86_64 arm64 ]' + +; RUN: clang-installapi --filetype=tbd-v5 \ +; RUN: -target arm64-apple-macos13.0 -target x86_64-apple-macos13.0 \ +; RUN: -install_name @rpath/Frameworks/RPath.framework/Versions/A/RPath \ +; RUN: -current_version 1 -compatibility_version 1 \ +; RUN: --extra-public-header=%t/public.h \ +; RUN: -rpath @loader_path/../../../SharedFrameworks/ \ +; RUN: -rpath @loader_path/../../PrivateFrameworks/ \ +; RUN: --verify-against=%t/RPath --verify-mode=Pedantic \ +; RUN: -o %t/RPath.tbd 2>&1 | FileCheck -allow-empty %s +; RUN: llvm-readtapi --compare %t/RPath.tbd %t/expected.tbd + +CHECK-NOT: error +CHECK-NOT: warning + +;--- public.h +extern int publicGlobalVariable; + +;--- expected.tbd +{ + "main_library": { + "exported_symbols": [ + { + "data": { + "global": [ + "_publicGlobalVariable" + ] + } + } + ], + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "@rpath/Frameworks/RPath.framework/Versions/A/RPath" + } + ], + "rpaths": [ + { + "paths": [ + "@loader_path/../../../SharedFrameworks/", + "@loader_path/../../PrivateFrameworks/" + ] + } + ], + "target_info": [ + { + "min_deployment": "13.0", + "target": "x86_64-macos" + }, + { + "min_deployment": "13.0", + "target": "arm64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} + +;--- expected_no_rpaths.tbd +{ + "main_library": { + "exported_symbols": [ + { + "data": { + "global": [ + "_publicGlobalVariable" + ] + } + } + ], + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "@rpath/Frameworks/RPath.framework/Versions/A/RPath" + } + ], + "target_info": [ + { + "min_deployment": "13.0", + "target": "x86_64-macos" + }, + { + "min_deployment": "13.0", + "target": "arm64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} + +;--- expected_xarch_rpaths.tbd +{ + "main_library": { + "exported_symbols": [ + { + "data": { + "global": [ + "_publicGlobalVariable" + ] + } + } + ], + "flags": [ + { + "attributes": [ + "not_app_extension_safe" + ] + } + ], + "install_names": [ + { + "name": "@rpath/Frameworks/RPath.framework/Versions/A/RPath" + } + ], + "rpaths": [ + { + "paths": [ + "@loader_path/../../../SharedFrameworks/" + ], + "targets": [ + "arm64-macos" + ] + } + ], + "target_info": [ + { + "min_deployment": "13.0", + "target": "x86_64-macos" + }, + { + "min_deployment": "13.0", + "target": "arm64-macos" + } + ] + }, + "tapi_tbd_version": 5 +} + +;--- RPath.yaml +--- !fat-mach-o +FatHeader: + magic: 0xCAFEBABE + nfat_arch: 2 +FatArchs: + - cputype: 0x1000007 + cpusubtype: 0x3 + offset: 0x1000 + size: 12408 + align: 12 + - cputype: 0x100000C + cpusubtype: 0x0 + offset: 0x8000 + size: 33312 + align: 14 +Slices: + - !mach-o + FileHeader: + magic: 0xFEEDFACF + cputype: 0x1000007 + cpusubtype: 0x3 + filetype: 0x6 + ncmds: 16 + sizeofcmds: 1072 + flags: 0x100085 + reserved: 0x0 + LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __TEXT + vmaddr: 0 + vmsize: 8192 + fileoff: 0 + filesize: 8192 + maxprot: 5 + initprot: 5 + nsects: 1 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x1050 + size: 0 + offset: 0x1050 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x80000000 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '' + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA_CONST + vmaddr: 8192 + vmsize: 4096 + fileoff: 8192 + filesize: 4096 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 16 + Sections: + - sectname: __objc_imageinfo + segname: __DATA_CONST + addr: 0x2000 + size: 8 + offset: 0x2000 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '0000000040000000' + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA + vmaddr: 12288 + vmsize: 4096 + fileoff: 12288 + filesize: 0 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 0 + Sections: + - sectname: __common + segname: __DATA + addr: 0x3000 + size: 4 + offset: 0x0 + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x1 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 16384 + vmsize: 120 + fileoff: 12288 + filesize: 120 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 12288 + export_size: 32 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 12328 + nsyms: 2 + stroff: 12360 + strsize: 48 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 1 + iundefsym: 1 + nundefsym: 1 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_RPATH + cmdsize: 56 + path: 12 + Content: '@loader_path/../../../SharedFrameworks/' + ZeroPadBytes: 5 + - cmd: LC_RPATH + cmdsize: 56 + path: 12 + Content: '@loader_path/../../PrivateFrameworks/' + ZeroPadBytes: 7 + - cmd: LC_ID_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '@rpath/Frameworks/RPath.framework/Versions/A/RPath' + ZeroPadBytes: 6 + - cmd: LC_UUID + cmdsize: 24 + uuid: 4C4C4489-5555-3144-A1D1-28C8EA66FB24 + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 851968 + sdk: 983040 + ntools: 1 + Tools: + - tool: 4 + version: 1245184 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 0 + current_version: 14942208 + compatibility_version: 65536 + Content: '/usr/lib/libobjc.A.dylib' + ZeroPadBytes: 8 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 0 + current_version: 88539136 + compatibility_version: 65536 + Content: '/usr/lib/libSystem.B.dylib' + ZeroPadBytes: 6 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 12320 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 12328 + datasize: 0 + LinkEditData: + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0 + Address: 0x0 + Other: 0x0 + ImportName: '' + Children: + - TerminalSize: 3 + NodeOffset: 25 + Name: _publicGlobalVariable + Flags: 0x0 + Address: 0x3000 + Other: 0x0 + ImportName: '' + NameList: + - n_strx: 2 + n_type: 0xF + n_sect: 3 + n_desc: 0 + n_value: 12288 + - n_strx: 24 + n_type: 0x1 + n_sect: 0 + n_desc: 512 + n_value: 0 + StringTable: + - ' ' + - _publicGlobalVariable + - dyld_stub_binder + - '' + - '' + - '' + - '' + - '' + - '' + - '' + - !mach-o + FileHeader: + magic: 0xFEEDFACF + cputype: 0x100000C + cpusubtype: 0x0 + filetype: 0x6 + ncmds: 17 + sizeofcmds: 1088 + flags: 0x100085 + reserved: 0x0 + LoadCommands: + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __TEXT + vmaddr: 0 + vmsize: 16384 + fileoff: 0 + filesize: 16384 + maxprot: 5 + initprot: 5 + nsects: 1 + flags: 0 + Sections: + - sectname: __text + segname: __TEXT + addr: 0x1060 + size: 0 + offset: 0x1060 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x80000000 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '' + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA_CONST + vmaddr: 16384 + vmsize: 16384 + fileoff: 16384 + filesize: 16384 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 16 + Sections: + - sectname: __objc_imageinfo + segname: __DATA_CONST + addr: 0x4000 + size: 8 + offset: 0x4000 + align: 0 + reloff: 0x0 + nreloc: 0 + flags: 0x0 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + content: '0000000040000000' + - cmd: LC_SEGMENT_64 + cmdsize: 152 + segname: __DATA + vmaddr: 32768 + vmsize: 16384 + fileoff: 32768 + filesize: 0 + maxprot: 3 + initprot: 3 + nsects: 1 + flags: 0 + Sections: + - sectname: __common + segname: __DATA + addr: 0x8000 + size: 4 + offset: 0x0 + align: 2 + reloff: 0x0 + nreloc: 0 + flags: 0x1 + reserved1: 0x0 + reserved2: 0x0 + reserved3: 0x0 + - cmd: LC_SEGMENT_64 + cmdsize: 72 + segname: __LINKEDIT + vmaddr: 49152 + vmsize: 544 + fileoff: 32768 + filesize: 544 + maxprot: 1 + initprot: 1 + nsects: 0 + flags: 0 + - cmd: LC_DYLD_INFO_ONLY + cmdsize: 48 + rebase_off: 0 + rebase_size: 0 + bind_off: 0 + bind_size: 0 + weak_bind_off: 0 + weak_bind_size: 0 + lazy_bind_off: 0 + lazy_bind_size: 0 + export_off: 32768 + export_size: 32 + - cmd: LC_SYMTAB + cmdsize: 24 + symoff: 32808 + nsyms: 2 + stroff: 32840 + strsize: 48 + - cmd: LC_DYSYMTAB + cmdsize: 80 + ilocalsym: 0 + nlocalsym: 0 + iextdefsym: 0 + nextdefsym: 1 + iundefsym: 1 + nundefsym: 1 + tocoff: 0 + ntoc: 0 + modtaboff: 0 + nmodtab: 0 + extrefsymoff: 0 + nextrefsyms: 0 + indirectsymoff: 0 + nindirectsyms: 0 + extreloff: 0 + nextrel: 0 + locreloff: 0 + nlocrel: 0 + - cmd: LC_RPATH + cmdsize: 56 + path: 12 + Content: '@loader_path/../../../SharedFrameworks/' + ZeroPadBytes: 5 + - cmd: LC_RPATH + cmdsize: 56 + path: 12 + Content: '@loader_path/../../PrivateFrameworks/' + ZeroPadBytes: 7 + - cmd: LC_ID_DYLIB + cmdsize: 80 + dylib: + name: 24 + timestamp: 0 + current_version: 65536 + compatibility_version: 65536 + Content: '@rpath/Frameworks/RPath.framework/Versions/A/RPath' + ZeroPadBytes: 6 + - cmd: LC_UUID + cmdsize: 24 + uuid: 4C4C440D-5555-3144-A18B-DB67A0A12202 + - cmd: LC_BUILD_VERSION + cmdsize: 32 + platform: 1 + minos: 851968 + sdk: 983040 + ntools: 1 + Tools: + - tool: 4 + version: 1245184 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 0 + current_version: 14942208 + compatibility_version: 65536 + Content: '/usr/lib/libobjc.A.dylib' + ZeroPadBytes: 8 + - cmd: LC_LOAD_DYLIB + cmdsize: 56 + dylib: + name: 24 + timestamp: 0 + current_version: 88539136 + compatibility_version: 65536 + Content: '/usr/lib/libSystem.B.dylib' + ZeroPadBytes: 6 + - cmd: LC_FUNCTION_STARTS + cmdsize: 16 + dataoff: 32800 + datasize: 8 + - cmd: LC_DATA_IN_CODE + cmdsize: 16 + dataoff: 32808 + datasize: 0 + - cmd: LC_CODE_SIGNATURE + cmdsize: 16 + dataoff: 32896 + datasize: 416 + LinkEditData: + ExportTrie: + TerminalSize: 0 + NodeOffset: 0 + Name: '' + Flags: 0x0 + Address: 0x0 + Other: 0x0 + ImportName: '' + Children: + - TerminalSize: 4 + NodeOffset: 25 + Name: _publicGlobalVariable + Flags: 0x0 + Address: 0x8000 + Other: 0x0 + ImportName: '' + NameList: + - n_strx: 2 + n_type: 0xF + n_sect: 3 + n_desc: 0 + n_value: 32768 + - n_strx: 24 + n_type: 0x1 + n_sect: 0 + n_desc: 512 + n_value: 0 + StringTable: + - ' ' + - _publicGlobalVariable + - dyld_stub_binder + - '' + - '' + - '' + - '' + - '' + - '' + - '' + FunctionStarts: [ 0x1060 ] +... diff --git a/clang/tools/clang-installapi/CMakeLists.txt b/clang/tools/clang-installapi/CMakeLists.txt index b90ffc847b15..9c0d9dff7dc7 100644 --- a/clang/tools/clang-installapi/CMakeLists.txt +++ b/clang/tools/clang-installapi/CMakeLists.txt @@ -1,4 +1,5 @@ set(LLVM_LINK_COMPONENTS + BinaryFormat Support TargetParser TextAPI diff --git a/clang/tools/clang-installapi/ClangInstallAPI.cpp b/clang/tools/clang-installapi/ClangInstallAPI.cpp index 13061cfa36ee..0c1980ba5d62 100644 --- a/clang/tools/clang-installapi/ClangInstallAPI.cpp +++ b/clang/tools/clang-installapi/ClangInstallAPI.cpp @@ -101,6 +101,16 @@ static bool run(ArrayRef Args, const char *ProgName) { if (Diag->hasErrorOccurred()) return EXIT_FAILURE; + if (!Opts.DriverOpts.DylibToVerify.empty()) { + TargetList Targets; + llvm::for_each(Opts.DriverOpts.Targets, + [&](const auto &T) { Targets.push_back(T.first); }); + if (!Ctx.Verifier->verifyBinaryAttrs(Targets, Ctx.BA, Ctx.Reexports, + Opts.LinkerOpts.AllowableClients, + Opts.LinkerOpts.RPaths, Ctx.FT)) + return EXIT_FAILURE; + }; + // Set up compilation. std::unique_ptr CI(new CompilerInstance()); CI->setFileManager(FM.get()); @@ -108,7 +118,7 @@ static bool run(ArrayRef Args, const char *ProgName) { if (!CI->hasDiagnostics()) return EXIT_FAILURE; - // Execute and gather AST results. + // Execute, verify and gather AST results. // An invocation is ran for each unique target triple and for each header // access level. for (const auto &[Targ, Trip] : Opts.DriverOpts.Targets) { @@ -136,10 +146,25 @@ static bool run(ArrayRef Args, const char *ProgName) { // Assign attributes for serialization. InterfaceFile IF(Ctx.Verifier->getExports()); + // Assign attributes that are the same per slice first. for (const auto &TargetInfo : Opts.DriverOpts.Targets) { IF.addTarget(TargetInfo.first); IF.setFromBinaryAttrs(Ctx.BA, TargetInfo.first); } + // Then assign potentially different attributes per slice after. + auto assignLibAttrs = + [&IF]( + const auto &Attrs, + std::function Add) { + for (const auto &Lib : Attrs) + for (const auto &T : IF.targets(Lib.getValue())) + Add(&IF, Lib.getKey(), T); + }; + + assignLibAttrs(Opts.LinkerOpts.AllowableClients, + &InterfaceFile::addAllowableClient); + assignLibAttrs(Opts.LinkerOpts.RPaths, &InterfaceFile::addRPath); + assignLibAttrs(Ctx.Reexports, &InterfaceFile::addReexportedLibrary); // Write output file and perform CI cleanup. if (auto Err = TextAPIWriter::writeToStream(*Out, IF, Ctx.FT)) { diff --git a/clang/tools/clang-installapi/InstallAPIOpts.td b/clang/tools/clang-installapi/InstallAPIOpts.td index 010f2507a1d1..8b1998c280dd 100644 --- a/clang/tools/clang-installapi/InstallAPIOpts.td +++ b/clang/tools/clang-installapi/InstallAPIOpts.td @@ -17,11 +17,23 @@ include "llvm/Option/OptParser.td" ///////// // Options -// TextAPI options. +// +/// TextAPI options. +// def filetype : Joined<["--"], "filetype=">, HelpText<"Specify the output file type (tbd-v4 or tbd-v5)">; +def not_for_dyld_shared_cache : Joined<["-"], "not_for_dyld_shared_cache">, + HelpText<"Mark library as shared cache ineligible">; + +// +/// Debugging or logging options. +// +def t: Flag<["-"], "t">, + HelpText<"Logs each dylib loaded for InstallAPI. Useful for debugging problems with search paths where the wrong library is loaded.">; -// Verification options. +// +/// Verification options. +// def verify_against : Separate<["-"], "verify-against">, HelpText<"Verify the specified dynamic library/framework against the headers">; def verify_against_EQ : Joined<["--"], "verify-against=">, Alias; @@ -32,7 +44,9 @@ def demangle : Flag<["--", "-"], "demangle">, def dsym: Joined<["--"], "dsym=">, MetaVarName<"">, HelpText<"Specify dSYM path for enriched diagnostics.">; -// Additional input options. +// +/// Additional input options. +// def extra_project_header : Separate<["-"], "extra-project-header">, MetaVarName<"">, HelpText<"Add additional project header location for parsing">; @@ -75,3 +89,23 @@ def project_umbrella_header : Separate<["-"], "project-umbrella-header">, MetaVarName<"">, HelpText<"Specify the project umbrella header location">; def project_umbrella_header_EQ : Joined<["--"], "project-umbrella-header=">, Alias; + +// +/// Overidden clang options for different behavior. +// + +// Clang's Xarch does not support options that require arguments. +// But is supported for InstallAPI generation. +def Xarch__ : Joined<["-"], "Xarch_">; +def allowable_client : Separate<["-"], "allowable_client">, + HelpText<"Restricts what can link against the dynamic library being created">; +def rpath: Separate<["-"], "rpath">, + HelpText<"Add path to the runpath search path list for the dynamic library being created.">; +def reexport_l : Joined<["-"], "reexport-l">, + HelpText<"Re-export the specified library">; +def reexport_library : Separate<["-"], "reexport_library">, MetaVarName<"">, + HelpText<"Re-export the specified library">; +def reexport_framework : Separate<["-"], "reexport_framework">, + HelpText<"Re-export the specified framework">; + + diff --git a/clang/tools/clang-installapi/Options.cpp b/clang/tools/clang-installapi/Options.cpp index 04d5e3cbb9d6..d1f911812800 100644 --- a/clang/tools/clang-installapi/Options.cpp +++ b/clang/tools/clang-installapi/Options.cpp @@ -7,14 +7,17 @@ //===----------------------------------------------------------------------===// #include "Options.h" +#include "clang/Basic/DiagnosticIDs.h" #include "clang/Driver/Driver.h" -#include "clang/Frontend/FrontendDiagnostic.h" #include "clang/InstallAPI/FileList.h" #include "clang/InstallAPI/HeaderFile.h" #include "clang/InstallAPI/InstallAPIDiagnostic.h" +#include "llvm/BinaryFormat/Magic.h" #include "llvm/Support/Program.h" #include "llvm/TargetParser/Host.h" #include "llvm/TextAPI/DylibReader.h" +#include "llvm/TextAPI/TextAPIError.h" +#include "llvm/TextAPI/TextAPIReader.h" #include "llvm/TextAPI/TextAPIWriter.h" using namespace llvm; @@ -137,6 +140,56 @@ bool Options::processDriverOptions(InputArgList &Args) { return true; } +bool Options::processInstallAPIXOptions(InputArgList &Args) { + for (arg_iterator It = Args.begin(), End = Args.end(); It != End; ++It) { + if ((*It)->getOption().matches(OPT_Xarch__)) { + if (!processXarchOption(Args, It)) + return false; + } + } + // TODO: Add support for the all of the X* options installapi supports. + + return true; +} + +bool Options::processXarchOption(InputArgList &Args, arg_iterator Curr) { + Arg *CurrArg = *Curr; + Architecture Arch = getArchitectureFromName(CurrArg->getValue(0)); + if (Arch == AK_unknown) { + Diags->Report(diag::err_drv_invalid_arch_name) + << CurrArg->getAsString(Args); + return false; + } + + auto NextIt = std::next(Curr); + if (NextIt == Args.end()) { + Diags->Report(diag::err_drv_missing_argument) + << CurrArg->getAsString(Args) << 1; + return false; + } + + // InstallAPI has a limited understanding of supported Xarch options. + // Currently this is restricted to linker inputs. + const Arg *NextArg = *NextIt; + switch (NextArg->getOption().getID()) { + case OPT_allowable_client: + case OPT_reexport_l: + case OPT_reexport_framework: + case OPT_reexport_library: + case OPT_rpath: + break; + default: + Diags->Report(diag::err_drv_invalid_argument_to_option) + << NextArg->getAsString(Args) << CurrArg->getAsString(Args); + return false; + } + + ArgToArchMap[NextArg] = Arch; + CurrArg->claim(); + + return true; +} + bool Options::processLinkerOptions(InputArgList &Args) { // Handle required arguments. if (const Arg *A = Args.getLastArg(drv::OPT_install__name)) @@ -153,6 +206,12 @@ bool Options::processLinkerOptions(InputArgList &Args) { if (auto *Arg = Args.getLastArg(drv::OPT_compatibility__version)) LinkerOpts.CompatVersion.parse64(Arg->getValue()); + if (auto *Arg = Args.getLastArg(drv::OPT_compatibility__version)) + LinkerOpts.CompatVersion.parse64(Arg->getValue()); + + if (auto *Arg = Args.getLastArg(drv::OPT_umbrella)) + LinkerOpts.ParentUmbrella = Arg->getValue(); + LinkerOpts.IsDylib = Args.hasArg(drv::OPT_dynamiclib); LinkerOpts.AppExtensionSafe = Args.hasFlag( @@ -164,12 +223,24 @@ bool Options::processLinkerOptions(InputArgList &Args) { if (::getenv("LD_APPLICATION_EXTENSION_SAFE") != nullptr) LinkerOpts.AppExtensionSafe = true; + + // Capture library paths. + PathSeq LibraryPaths; + for (const Arg *A : Args.filtered(drv::OPT_L)) { + LibraryPaths.emplace_back(A->getValue()); + A->claim(); + } + + if (!LibraryPaths.empty()) + LinkerOpts.LibPaths = std::move(LibraryPaths); + return true; } +// NOTE: Do not claim any arguments, as they will be passed along for CC1 +// invocations. bool Options::processFrontendOptions(InputArgList &Args) { - // Do not claim any arguments, as they will be passed along for CC1 - // invocations. + // Capture language mode. if (auto *A = Args.getLastArgNoClaim(drv::OPT_x)) { FEOpts.LangMode = llvm::StringSwitch(A->getValue()) .Case("c", clang::Language::C) @@ -191,6 +262,54 @@ bool Options::processFrontendOptions(InputArgList &Args) { FEOpts.LangMode = clang::Language::ObjCXX; } + // Capture Sysroot. + if (const Arg *A = Args.getLastArgNoClaim(drv::OPT_isysroot)) { + SmallString Path(A->getValue()); + FM->makeAbsolutePath(Path); + if (!FM->getOptionalDirectoryRef(Path)) { + Diags->Report(diag::err_missing_sysroot) << Path; + return false; + } + FEOpts.ISysroot = std::string(Path); + } else if (FEOpts.ISysroot.empty()) { + // Mirror CLANG and obtain the isysroot from the SDKROOT environment + // variable, if it wasn't defined by the command line. + if (auto *Env = ::getenv("SDKROOT")) { + if (StringRef(Env) != "/" && llvm::sys::path::is_absolute(Env) && + FM->getOptionalFileRef(Env)) + FEOpts.ISysroot = Env; + } + } + + // Capture system frameworks. + // TODO: Support passing framework paths per platform. + for (const Arg *A : Args.filtered(drv::OPT_iframework)) + FEOpts.SystemFwkPaths.emplace_back(A->getValue()); + + // Capture framework paths. + PathSeq FrameworkPaths; + for (const Arg *A : Args.filtered(drv::OPT_F)) + FrameworkPaths.emplace_back(A->getValue()); + + if (!FrameworkPaths.empty()) + FEOpts.FwkPaths = std::move(FrameworkPaths); + + // Add default framework/library paths. + PathSeq DefaultLibraryPaths = {"/usr/lib", "/usr/local/lib"}; + PathSeq DefaultFrameworkPaths = {"/Library/Frameworks", + "/System/Library/Frameworks"}; + + for (const StringRef LibPath : DefaultLibraryPaths) { + SmallString Path(FEOpts.ISysroot); + sys::path::append(Path, LibPath); + LinkerOpts.LibPaths.emplace_back(Path.str()); + } + for (const StringRef FwkPath : DefaultFrameworkPaths) { + SmallString Path(FEOpts.ISysroot); + sys::path::append(Path, FwkPath); + FEOpts.SystemFwkPaths.emplace_back(Path.str()); + } + return true; } @@ -224,6 +343,9 @@ Options::processAndFilterOutInstallAPIOptions(ArrayRef Args) { MissingArgCount, Visibility()); // Capture InstallAPI only driver options. + if (!processInstallAPIXOptions(ParsedArgs)) + return {}; + DriverOpts.Demangle = ParsedArgs.hasArg(OPT_demangle); if (auto *A = ParsedArgs.getLastArg(OPT_filetype)) { @@ -256,6 +378,42 @@ Options::processAndFilterOutInstallAPIOptions(ArrayRef Args) { if (const Arg *A = ParsedArgs.getLastArg(OPT_dsym)) DriverOpts.DSYMPath = A->getValue(); + DriverOpts.TraceLibraryLocation = ParsedArgs.hasArg(OPT_t); + + // Linker options not handled by clang driver. + LinkerOpts.OSLibNotForSharedCache = + ParsedArgs.hasArg(OPT_not_for_dyld_shared_cache); + + for (const Arg *A : ParsedArgs.filtered(OPT_allowable_client)) { + LinkerOpts.AllowableClients[A->getValue()] = + ArgToArchMap.count(A) ? ArgToArchMap[A] : ArchitectureSet(); + A->claim(); + } + + for (const Arg *A : ParsedArgs.filtered(OPT_reexport_l)) { + LinkerOpts.ReexportedLibraries[A->getValue()] = + ArgToArchMap.count(A) ? ArgToArchMap[A] : ArchitectureSet(); + A->claim(); + } + + for (const Arg *A : ParsedArgs.filtered(OPT_reexport_library)) { + LinkerOpts.ReexportedLibraryPaths[A->getValue()] = + ArgToArchMap.count(A) ? ArgToArchMap[A] : ArchitectureSet(); + A->claim(); + } + + for (const Arg *A : ParsedArgs.filtered(OPT_reexport_framework)) { + LinkerOpts.ReexportedFrameworks[A->getValue()] = + ArgToArchMap.count(A) ? ArgToArchMap[A] : ArchitectureSet(); + A->claim(); + } + + for (const Arg *A : ParsedArgs.filtered(OPT_rpath)) { + LinkerOpts.RPaths[A->getValue()] = + ArgToArchMap.count(A) ? ArgToArchMap[A] : ArchitectureSet(); + A->claim(); + } + // Handle exclude & extra header directories or files. auto handleAdditionalInputArgs = [&](PathSeq &Headers, clang::installapi::ID OptID) { @@ -336,6 +494,22 @@ Options::Options(DiagnosticsEngine &Diag, FileManager *FM, if (!processFrontendOptions(ArgList)) return; + // After all InstallAPI necessary arguments have been collected. Go back and + // assign values that were unknown before the clang driver opt table was used. + ArchitectureSet AllArchs; + llvm::for_each(DriverOpts.Targets, + [&AllArchs](const auto &T) { AllArchs.set(T.first.Arch); }); + auto assignDefaultLibAttrs = [&AllArchs](LibAttrs &Attrs) { + for (StringMapEntry &Entry : Attrs) + if (Entry.getValue().empty()) + Entry.setValue(AllArchs); + }; + assignDefaultLibAttrs(LinkerOpts.AllowableClients); + assignDefaultLibAttrs(LinkerOpts.ReexportedFrameworks); + assignDefaultLibAttrs(LinkerOpts.ReexportedLibraries); + assignDefaultLibAttrs(LinkerOpts.ReexportedLibraryPaths); + assignDefaultLibAttrs(LinkerOpts.RPaths); + /// Force cc1 options that should always be on. FrontendArgs = {"-fsyntax-only", "-Wprivate-extern"}; @@ -357,6 +531,89 @@ static StringRef getFrameworkNameFromInstallName(StringRef InstallName) { return Match.back(); } +static Expected> +getInterfaceFile(const StringRef Filename) { + ErrorOr> BufferOrErr = + MemoryBuffer::getFile(Filename); + if (auto Err = BufferOrErr.getError()) + return errorCodeToError(std::move(Err)); + + auto Buffer = std::move(*BufferOrErr); + std::unique_ptr IF; + switch (identify_magic(Buffer->getBuffer())) { + case file_magic::macho_dynamically_linked_shared_lib: + LLVM_FALLTHROUGH; + case file_magic::macho_dynamically_linked_shared_lib_stub: + LLVM_FALLTHROUGH; + case file_magic::macho_universal_binary: + return DylibReader::get(Buffer->getMemBufferRef()); + break; + case file_magic::tapi_file: + return TextAPIReader::get(Buffer->getMemBufferRef()); + default: + return make_error(TextAPIErrorCode::InvalidInputFormat, + "unsupported library file format"); + } + llvm_unreachable("unexpected failure in getInterface"); +} + +std::pair Options::getReexportedLibraries() { + LibAttrs Reexports; + ReexportedInterfaces ReexportIFs; + auto AccumulateReexports = [&](StringRef Path, const ArchitectureSet &Archs) { + auto ReexportIFOrErr = getInterfaceFile(Path); + if (!ReexportIFOrErr) + return false; + std::unique_ptr Reexport = std::move(*ReexportIFOrErr); + StringRef InstallName = Reexport->getInstallName(); + assert(!InstallName.empty() && "Parse error for install name"); + Reexports.insert({InstallName, Archs}); + ReexportIFs.emplace_back(std::move(*Reexport)); + return true; + }; + + // Populate search paths by looking at user paths before system ones. + PathSeq FwkSearchPaths(FEOpts.FwkPaths.begin(), FEOpts.FwkPaths.end()); + // FIXME: System framework paths need to reset if installapi is invoked with + // different platforms. + FwkSearchPaths.insert(FwkSearchPaths.end(), FEOpts.SystemFwkPaths.begin(), + FEOpts.SystemFwkPaths.end()); + + for (const StringMapEntry &Lib : + LinkerOpts.ReexportedLibraries) { + std::string Name = "lib" + Lib.getKey().str() + ".dylib"; + std::string Path = findLibrary(Name, *FM, {}, LinkerOpts.LibPaths, {}); + if (Path.empty()) { + Diags->Report(diag::err_cannot_find_reexport) << true << Lib.getKey(); + return {}; + } + if (DriverOpts.TraceLibraryLocation) + errs() << Path << "\n"; + + AccumulateReexports(Path, Lib.getValue()); + } + + for (const StringMapEntry &Lib : + LinkerOpts.ReexportedLibraryPaths) + AccumulateReexports(Lib.getKey(), Lib.getValue()); + + for (const StringMapEntry &Lib : + LinkerOpts.ReexportedFrameworks) { + std::string Name = (Lib.getKey() + ".framework/" + Lib.getKey()).str(); + std::string Path = findLibrary(Name, *FM, FwkSearchPaths, {}, {}); + if (Path.empty()) { + Diags->Report(diag::err_cannot_find_reexport) << false << Lib.getKey(); + return {}; + } + if (DriverOpts.TraceLibraryLocation) + errs() << Path << "\n"; + + AccumulateReexports(Path, Lib.getValue()); + } + + return {std::move(Reexports), std::move(ReexportIFs)}; +} + InstallAPIContext Options::createContext() { InstallAPIContext Ctx; Ctx.FM = FM; @@ -369,10 +626,17 @@ InstallAPIContext Options::createContext() { Ctx.BA.CurrentVersion = LinkerOpts.CurrentVersion; Ctx.BA.CompatVersion = LinkerOpts.CompatVersion; Ctx.BA.AppExtensionSafe = LinkerOpts.AppExtensionSafe; + Ctx.BA.ParentUmbrella = LinkerOpts.ParentUmbrella; + Ctx.BA.OSLibNotForSharedCache = LinkerOpts.OSLibNotForSharedCache; Ctx.FT = DriverOpts.OutFT; Ctx.OutputLoc = DriverOpts.OutputPath; Ctx.LangMode = FEOpts.LangMode; + auto [Reexports, ReexportedIFs] = getReexportedLibraries(); + if (Diags->hasErrorOccurred()) + return Ctx; + Ctx.Reexports = Reexports; + // Attempt to find umbrella headers by capturing framework name. StringRef FrameworkName; if (!LinkerOpts.IsDylib) @@ -532,13 +796,14 @@ InstallAPIContext Options::createContext() { Expected Slices = DylibReader::readFile((*Buffer)->getMemBufferRef(), PO); if (auto Err = Slices.takeError()) { - Diags->Report(diag::err_cannot_open_file) << DriverOpts.DylibToVerify; + Diags->Report(diag::err_cannot_open_file) + << DriverOpts.DylibToVerify << std::move(Err); return Ctx; } Ctx.Verifier = std::make_unique( - std::move(*Slices), Diags, DriverOpts.VerifyMode, DriverOpts.Demangle, - DriverOpts.DSYMPath); + std::move(*Slices), std::move(ReexportedIFs), Diags, + DriverOpts.VerifyMode, DriverOpts.Demangle, DriverOpts.DSYMPath); return Ctx; } diff --git a/clang/tools/clang-installapi/Options.h b/clang/tools/clang-installapi/Options.h index cd74722c92c8..6da1469de2c8 100644 --- a/clang/tools/clang-installapi/Options.h +++ b/clang/tools/clang-installapi/Options.h @@ -20,7 +20,6 @@ #include "llvm/Option/Option.h" #include "llvm/Support/Program.h" #include "llvm/TargetParser/Triple.h" -#include #include #include @@ -81,9 +80,30 @@ struct DriverOptions { /// \brief Print verbose output. bool Verbose = false; + + /// \brief Log libraries loaded. + bool TraceLibraryLocation = false; }; struct LinkerOptions { + /// \brief List of allowable clients to use for the dynamic library. + LibAttrs AllowableClients; + + /// \brief List of reexported libraries to use for the dynamic library. + LibAttrs ReexportedLibraries; + + /// \brief List of reexported libraries to use for the dynamic library. + LibAttrs ReexportedLibraryPaths; + + /// \brief List of reexported frameworks to use for the dynamic library. + LibAttrs ReexportedFrameworks; + + /// \brief List of rpaths to use for the dynamic library. + LibAttrs RPaths; + + /// \brief Additional library search paths. + PathSeq LibPaths; + /// \brief The install name to use for the dynamic library. std::string InstallName; @@ -93,18 +113,34 @@ struct LinkerOptions { /// \brief The compatibility version to use for the dynamic library. PackedVersion CompatVersion; + /// \brief Name of the umbrella library. + std::string ParentUmbrella; + /// \brief Is application extension safe. bool AppExtensionSafe = false; /// \brief Set if we should scan for a dynamic library and not a framework. bool IsDylib = false; + + /// \brief Is an OS library that is not shared cache eligible. + bool OSLibNotForSharedCache = false; }; struct FrontendOptions { /// \brief The language mode to parse headers in. Language LangMode = Language::ObjC; + + /// \brief The sysroot to search for SDK headers or libraries. + std::string ISysroot; + + /// \brief Additional framework search paths. + PathSeq FwkPaths; + + /// \brief Additional SYSTEM framework search paths. + PathSeq SystemFwkPaths; }; +using arg_iterator = llvm::opt::arg_iterator; class Options { private: bool processDriverOptions(llvm::opt::InputArgList &Args); @@ -112,6 +148,8 @@ private: bool processFrontendOptions(llvm::opt::InputArgList &Args); std::vector processAndFilterOutInstallAPIOptions(ArrayRef Args); + bool processInstallAPIXOptions(llvm::opt::InputArgList &Args); + bool processXarchOption(llvm::opt::InputArgList &Args, arg_iterator Curr); public: /// The various options grouped together. @@ -136,9 +174,12 @@ private: bool addFilePaths(llvm::opt::InputArgList &Args, PathSeq &Headers, llvm::opt::OptSpecifier ID); + std::pair getReexportedLibraries(); + DiagnosticsEngine *Diags; FileManager *FM; std::vector FrontendArgs; + llvm::DenseMap ArgToArchMap; }; enum ID { -- GitLab From 0a39f1a7e5c7fd00b37231964ec81dae938948e7 Mon Sep 17 00:00:00 2001 From: Christopher Ferris Date: Fri, 5 Apr 2024 14:25:39 -0700 Subject: [PATCH 034/695] [scudo] Add errno description to mmap failure. (#87713) Added unit tests for all of the linux report error functions. --- .../lib/scudo/standalone/report_linux.cpp | 8 +++--- .../scudo/standalone/tests/report_test.cpp | 25 +++++++++++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/report_linux.cpp b/compiler-rt/lib/scudo/standalone/report_linux.cpp index dfddef3324bd..432f6a016964 100644 --- a/compiler-rt/lib/scudo/standalone/report_linux.cpp +++ b/compiler-rt/lib/scudo/standalone/report_linux.cpp @@ -25,10 +25,10 @@ namespace scudo { // Fatal internal map() error (potentially OOM related). void NORETURN reportMapError(uptr SizeIfOOM) { ScopedString Error; - Error.append("Scudo ERROR: internal map failure"); - if (SizeIfOOM) { - Error.append(" (NO MEMORY) requesting %zuKB", SizeIfOOM >> 10); - } + Error.append("Scudo ERROR: internal map failure (error desc=%s)", + strerror(errno)); + if (SizeIfOOM) + Error.append(" requesting %zuKB", SizeIfOOM >> 10); Error.append("\n"); reportRawError(Error.data()); } diff --git a/compiler-rt/lib/scudo/standalone/tests/report_test.cpp b/compiler-rt/lib/scudo/standalone/tests/report_test.cpp index 92f1ee813036..2c790247a2f6 100644 --- a/compiler-rt/lib/scudo/standalone/tests/report_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/report_test.cpp @@ -53,3 +53,28 @@ TEST(ScudoReportDeathTest, CSpecific) { EXPECT_DEATH(scudo::reportInvalidAlignedAllocAlignment(123, 456), "Scudo ERROR.*123.*456"); } + +#if SCUDO_LINUX || SCUDO_TRUSTY || SCUDO_ANDROID +#include "report_linux.h" + +#include +#include + +TEST(ScudoReportDeathTest, Linux) { + errno = ENOMEM; + EXPECT_DEATH(scudo::reportMapError(), + "Scudo ERROR:.*internal map failure \\(error desc=.*\\)\\s*$"); + errno = ENOMEM; + EXPECT_DEATH(scudo::reportMapError(1024U), + "Scudo ERROR:.*internal map failure \\(error desc=.*\\) " + "requesting 1KB\\s*$"); + errno = ENOMEM; + EXPECT_DEATH(scudo::reportUnmapError(0x1000U, 100U), + "Scudo ERROR:.*internal unmap failure \\(error desc=.*\\) Addr " + "0x1000 Size 100\\s*$"); + errno = ENOMEM; + EXPECT_DEATH(scudo::reportProtectError(0x1000U, 100U, PROT_READ), + "Scudo ERROR:.*internal protect failure \\(error desc=.*\\) " + "Addr 0x1000 Size 100 Prot 1\\s*$"); +} +#endif -- GitLab From 2744a243bb132ef0bbb37c888cee661488609ea5 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Fri, 5 Apr 2024 14:29:23 -0700 Subject: [PATCH 035/695] [libc][support][bit] use new type generic builtins (#86746) These are new in clang-19+, gcc-14+. --- libc/src/__support/CPP/bit.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/libc/src/__support/CPP/bit.h b/libc/src/__support/CPP/bit.h index 80f50fd221ef..8a8951a18bfa 100644 --- a/libc/src/__support/CPP/bit.h +++ b/libc/src/__support/CPP/bit.h @@ -72,6 +72,14 @@ has_single_bit(T value) { /// Only unsigned integral types are allowed. /// /// Returns cpp::numeric_limits::digits on an input of 0. +// clang-19+, gcc-14+ +#if __has_builtin(__builtin_ctzg) +template +[[nodiscard]] LIBC_INLINE constexpr cpp::enable_if_t, int> +countr_zero(T value) { + return __builtin_ctzg(value, cpp::numeric_limits::digits); +} +#else template [[nodiscard]] LIBC_INLINE constexpr cpp::enable_if_t, int> countr_zero(T value) { @@ -99,6 +107,7 @@ ADD_SPECIALIZATION(countr_zero, unsigned short, __builtin_ctzs) ADD_SPECIALIZATION(countr_zero, unsigned int, __builtin_ctz) ADD_SPECIALIZATION(countr_zero, unsigned long, __builtin_ctzl) ADD_SPECIALIZATION(countr_zero, unsigned long long, __builtin_ctzll) +#endif // __has_builtin(__builtin_ctzg) /// Count number of 0's from the most significant bit to the least /// stopping at the first 1. @@ -106,6 +115,14 @@ ADD_SPECIALIZATION(countr_zero, unsigned long long, __builtin_ctzll) /// Only unsigned integral types are allowed. /// /// Returns cpp::numeric_limits::digits on an input of 0. +// clang-19+, gcc-14+ +#if __has_builtin(__builtin_clzg) +template +[[nodiscard]] LIBC_INLINE constexpr cpp::enable_if_t, int> +countl_zero(T value) { + return __builtin_clzg(value, cpp::numeric_limits::digits); +} +#else template [[nodiscard]] LIBC_INLINE constexpr cpp::enable_if_t, int> countl_zero(T value) { @@ -129,6 +146,7 @@ ADD_SPECIALIZATION(countl_zero, unsigned short, __builtin_clzs) ADD_SPECIALIZATION(countl_zero, unsigned int, __builtin_clz) ADD_SPECIALIZATION(countl_zero, unsigned long, __builtin_clzl) ADD_SPECIALIZATION(countl_zero, unsigned long long, __builtin_clzll) +#endif // __has_builtin(__builtin_clzg) #undef ADD_SPECIALIZATION -- GitLab From 25cf27910c3a58e71e37c3d5391235730aa7c488 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Fri, 5 Apr 2024 14:41:20 -0700 Subject: [PATCH 036/695] [cmake] Build executables with -no_exported_symbols when building Apple toolchain (#87684) Building the Apple way turns off plugin support, meaning we don't need to export unloadable symbols from all executables. While deadstripping effects aren't expected to change, enabling this across all tools prevents the creation of export tries. This saves us ~3.5 MB in just the universal build of `clang`. --- clang/cmake/caches/Apple-stage2.cmake | 1 + lldb/cmake/caches/Apple-lldb-base.cmake | 1 + llvm/CMakeLists.txt | 3 +++ llvm/cmake/modules/AddLLVM.cmake | 35 +++++++++++++++++++------ llvm/docs/CMake.rst | 5 ++++ 5 files changed, 37 insertions(+), 8 deletions(-) diff --git a/clang/cmake/caches/Apple-stage2.cmake b/clang/cmake/caches/Apple-stage2.cmake index 72cdedd611bc..ede256a2da6b 100644 --- a/clang/cmake/caches/Apple-stage2.cmake +++ b/clang/cmake/caches/Apple-stage2.cmake @@ -15,6 +15,7 @@ set(LLVM_ENABLE_ZLIB ON CACHE BOOL "") set(LLVM_ENABLE_BACKTRACES OFF CACHE BOOL "") set(LLVM_ENABLE_MODULES ON CACHE BOOL "") set(LLVM_EXTERNALIZE_DEBUGINFO ON CACHE BOOL "") +set(LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES OFF CACHE BOOL "") set(CLANG_PLUGIN_SUPPORT OFF CACHE BOOL "") set(CLANG_SPAWN_CC1 ON CACHE BOOL "") set(BUG_REPORT_URL "http://developer.apple.com/bugreporter/" CACHE STRING "") diff --git a/lldb/cmake/caches/Apple-lldb-base.cmake b/lldb/cmake/caches/Apple-lldb-base.cmake index 4d4f02bfae95..6c3fa4346d7e 100644 --- a/lldb/cmake/caches/Apple-lldb-base.cmake +++ b/lldb/cmake/caches/Apple-lldb-base.cmake @@ -3,6 +3,7 @@ set(CMAKE_EXPORT_COMPILE_COMMANDS ON CACHE BOOL "") set(LLVM_TARGETS_TO_BUILD X86;ARM;AArch64 CACHE STRING "") set(LLVM_ENABLE_ASSERTIONS ON CACHE BOOL "") +set(LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES OFF CACHE BOOL "") set(LIBCXX_ENABLE_SHARED OFF CACHE BOOL "") set(LIBCXX_ENABLE_STATIC OFF CACHE BOOL "") diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 88cf2d7ff099..d511376e18ba 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -673,6 +673,9 @@ option(LLVM_USE_OPROFILE option(LLVM_EXTERNALIZE_DEBUGINFO "Generate dSYM files and strip executables and libraries (Darwin Only)" OFF) +option(LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES + "Preserve exported symbols in executables" ON) + set(LLVM_CODESIGNING_IDENTITY "" CACHE STRING "Sign executables and dylibs with the given identity or skip if empty (Darwin Only)") diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index 745935f14051..f8a17f645e25 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -258,15 +258,24 @@ if (NOT DEFINED LLVM_LINKER_DETECTED AND NOT WIN32) endif() endif() - # Apple's linker complains about duplicate libraries, which CMake likes to do - # to support ELF platforms. To silence that warning, we can use - # -no_warn_duplicate_libraries, but only in versions of the linker that - # support that flag. - if(NOT LLVM_USE_LINKER AND ${CMAKE_SYSTEM_NAME} MATCHES "Darwin") + if(${CMAKE_SYSTEM_NAME} MATCHES "Darwin") include(CheckLinkerFlag) - check_linker_flag(C "-Wl,-no_warn_duplicate_libraries" LLVM_LINKER_SUPPORTS_NO_WARN_DUPLICATE_LIBRARIES) - else() - set(LLVM_LINKER_SUPPORTS_NO_WARN_DUPLICATE_LIBRARIES OFF CACHE INTERNAL "") + # Linkers that support Darwin allow a setting to internalize all symbol exports, + # aiding in reducing binary size and often is applicable for executables. + check_linker_flag(C "-Wl,-no_exported_symbols" LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS) + + if (NOT LLVM_USE_LINKER) + # Apple's linker complains about duplicate libraries, which CMake likes to do + # to support ELF platforms. To silence that warning, we can use + # -no_warn_duplicate_libraries, but only in versions of the linker that + # support that flag. + check_linker_flag(C "-Wl,-no_warn_duplicate_libraries" LLVM_LINKER_SUPPORTS_NO_WARN_DUPLICATE_LIBRARIES) + else() + set(LLVM_LINKER_SUPPORTS_NO_WARN_DUPLICATE_LIBRARIES OFF CACHE INTERNAL "") + endif() + + else() + set(LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS OFF CACHE INTERNAL "") endif() endif() @@ -1029,6 +1038,16 @@ macro(add_llvm_executable name) add_llvm_symbol_exports( ${name} ${LLVM_EXPORTED_SYMBOL_FILE} ) endif(LLVM_EXPORTED_SYMBOL_FILE) + if (NOT LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES) + if(LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS) + set_property(TARGET ${name} APPEND_STRING PROPERTY + LINK_FLAGS " -Wl,-no_exported_symbols") + else() + message(FATAL_ERROR + "LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES cannot be disabled when linker does not support \"-no_exported_symbols\"") + endif() + endif() + if (LLVM_LINK_LLVM_DYLIB AND NOT ARG_DISABLE_LLVM_LINK_LLVM_DYLIB) set(USE_SHARED USE_SHARED) endif() diff --git a/llvm/docs/CMake.rst b/llvm/docs/CMake.rst index d2f66d71d39a..7a809d44d3d8 100644 --- a/llvm/docs/CMake.rst +++ b/llvm/docs/CMake.rst @@ -654,6 +654,11 @@ enabled sub-projects. Nearly all of these variable names begin with Generate dSYM files and strip executables and libraries (Darwin Only). Defaults to OFF. +**LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES**:BOOL + When building executables, preserve symbol exports. Defaults to ON. + You can use this option to disable exported symbols from all + executables (Darwin Only). + **LLVM_FORCE_USE_OLD_TOOLCHAIN**:BOOL If enabled, the compiler and standard library versions won't be checked. LLVM may not compile at all, or might fail at runtime due to known bugs in these -- GitLab From b329da896c4959f6c56cf5e515d3412322f4b3c5 Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Fri, 5 Apr 2024 14:46:24 -0700 Subject: [PATCH 037/695] [flang][runtime] Support for offload build of FortranDecimal. (#87653) --- .../modules/AddFlangOffloadRuntime.cmake | 132 ++++++++++++++++++ flang/lib/Decimal/CMakeLists.txt | 10 +- flang/lib/Decimal/big-radix-floating-point.h | 69 +++++---- flang/lib/Decimal/binary-to-decimal.cpp | 6 +- flang/lib/Decimal/decimal-to-binary.cpp | 22 +-- flang/runtime/CMakeLists.txt | 129 +---------------- 6 files changed, 199 insertions(+), 169 deletions(-) create mode 100644 flang/cmake/modules/AddFlangOffloadRuntime.cmake diff --git a/flang/cmake/modules/AddFlangOffloadRuntime.cmake b/flang/cmake/modules/AddFlangOffloadRuntime.cmake new file mode 100644 index 000000000000..6fb6213e90fc --- /dev/null +++ b/flang/cmake/modules/AddFlangOffloadRuntime.cmake @@ -0,0 +1,132 @@ +option(FLANG_EXPERIMENTAL_CUDA_RUNTIME + "Compile Fortran runtime as CUDA sources (experimental)" OFF + ) + +set(FLANG_LIBCUDACXX_PATH "" CACHE PATH "Path to libcu++ package installation") + +set(FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD "off" CACHE STRING + "Compile Fortran runtime as OpenMP target offload sources (experimental). Valid options are 'off', 'host_device', 'nohost'") + +set(FLANG_OMP_DEVICE_ARCHITECTURES "all" CACHE STRING + "List of OpenMP device architectures to be used to compile the Fortran runtime (e.g. 'gfx1103;sm_90')") + +macro(enable_cuda_compilation files) + if (FLANG_EXPERIMENTAL_CUDA_RUNTIME) + if (BUILD_SHARED_LIBS) + message(FATAL_ERROR + "BUILD_SHARED_LIBS is not supported for CUDA build of Fortran runtime" + ) + endif() + + enable_language(CUDA) + + # TODO: figure out how to make target property CUDA_SEPARABLE_COMPILATION + # work, and avoid setting CMAKE_CUDA_SEPARABLE_COMPILATION. + set(CMAKE_CUDA_SEPARABLE_COMPILATION ON) + + # Treat all supported sources as CUDA files. + set_source_files_properties(${files} PROPERTIES LANGUAGE CUDA) + set(CUDA_COMPILE_OPTIONS) + if ("${CMAKE_CUDA_COMPILER_ID}" MATCHES "Clang") + # Allow varargs. + set(CUDA_COMPILE_OPTIONS + -Xclang -fcuda-allow-variadic-functions + ) + endif() + if ("${CMAKE_CUDA_COMPILER_ID}" MATCHES "NVIDIA") + set(CUDA_COMPILE_OPTIONS + --expt-relaxed-constexpr + # Disable these warnings: + # 'long double' is treated as 'double' in device code + -Xcudafe --diag_suppress=20208 + -Xcudafe --display_error_number + ) + endif() + set_source_files_properties(${files} PROPERTIES COMPILE_OPTIONS + "${CUDA_COMPILE_OPTIONS}" + ) + + if (EXISTS "${FLANG_LIBCUDACXX_PATH}/include") + # When using libcudacxx headers files, we have to use them + # for all files of F18 runtime. + include_directories(AFTER ${FLANG_LIBCUDACXX_PATH}/include) + add_compile_definitions(RT_USE_LIBCUDACXX=1) + endif() + endif() +endmacro() + +macro(enable_omp_offload_compilation files) + if (NOT FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD STREQUAL "off") + # 'host_device' build only works with Clang compiler currently. + # The build is done with the CMAKE_C/CXX_COMPILER, i.e. it does not use + # the in-tree built Clang. We may have a mode that would use the in-tree + # built Clang. + # + # 'nohost' is supposed to produce an LLVM Bitcode library, + # and it has to be done with a C/C++ compiler producing LLVM Bitcode + # compatible with the LLVM toolchain version distributed with the Flang + # compiler. + # In general, the in-tree built Clang should be used for 'nohost' build. + # Note that 'nohost' build does not produce the host version of Flang + # runtime library, so there will be two separate distributable objects. + # 'nohost' build is a TODO. + + if (NOT FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD STREQUAL "host_device") + message(FATAL_ERROR "Unsupported OpenMP offload build of Flang runtime") + endif() + if (BUILD_SHARED_LIBS) + message(FATAL_ERROR + "BUILD_SHARED_LIBS is not supported for OpenMP offload build of Fortran runtime" + ) + endif() + + if ("${CMAKE_CXX_COMPILER_ID}" MATCHES "Clang" AND + "${CMAKE_C_COMPILER_ID}" MATCHES "Clang") + + set(all_amdgpu_architectures + "gfx700;gfx701;gfx801;gfx803;gfx900;gfx902;gfx906" + "gfx908;gfx90a;gfx90c;gfx940;gfx1010;gfx1030" + "gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036" + "gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151" + ) + set(all_nvptx_architectures + "sm_35;sm_37;sm_50;sm_52;sm_53;sm_60;sm_61;sm_62" + "sm_70;sm_72;sm_75;sm_80;sm_86;sm_89;sm_90" + ) + set(all_gpu_architectures + "${all_amdgpu_architectures};${all_nvptx_architectures}" + ) + # TODO: support auto detection on the build system. + if (FLANG_OMP_DEVICE_ARCHITECTURES STREQUAL "all") + set(FLANG_OMP_DEVICE_ARCHITECTURES ${all_gpu_architectures}) + endif() + list(REMOVE_DUPLICATES FLANG_OMP_DEVICE_ARCHITECTURES) + + string(REPLACE ";" "," compile_for_architectures + "${FLANG_OMP_DEVICE_ARCHITECTURES}" + ) + + set(OMP_COMPILE_OPTIONS + -fopenmp + -fvisibility=hidden + -fopenmp-cuda-mode + --offload-arch=${compile_for_architectures} + # Force LTO for the device part. + -foffload-lto + ) + set_source_files_properties(${files} PROPERTIES COMPILE_OPTIONS + "${OMP_COMPILE_OPTIONS}" + ) + + # Enable "declare target" in the source code. + set_source_files_properties(${files} + PROPERTIES COMPILE_DEFINITIONS OMP_OFFLOAD_BUILD + ) + else() + message(FATAL_ERROR + "Flang runtime build is not supported for these compilers:\n" + "CMAKE_CXX_COMPILER_ID: ${CMAKE_CXX_COMPILER_ID}\n" + "CMAKE_C_COMPILER_ID: ${CMAKE_C_COMPILER_ID}") + endif() + endif() +endmacro() diff --git a/flang/lib/Decimal/CMakeLists.txt b/flang/lib/Decimal/CMakeLists.txt index 2f6caa22e156..3d562b8e3ce1 100644 --- a/flang/lib/Decimal/CMakeLists.txt +++ b/flang/lib/Decimal/CMakeLists.txt @@ -49,11 +49,17 @@ endif() # avoid an unwanted dependency on libstdc++.so. add_definitions(-U_GLIBCXX_ASSERTIONS) -add_flang_library(FortranDecimal INSTALL_WITH_TOOLCHAIN +set(sources binary-to-decimal.cpp decimal-to-binary.cpp ) +include(AddFlangOffloadRuntime) +enable_cuda_compilation("${sources}") +enable_omp_offload_compilation("${sources}") + +add_flang_library(FortranDecimal INSTALL_WITH_TOOLCHAIN ${sources}) + if (DEFINED MSVC) set(CMAKE_MSVC_RUNTIME_LIBRARY MultiThreaded) add_flang_library(FortranDecimal.static INSTALL_WITH_TOOLCHAIN @@ -77,4 +83,4 @@ if (DEFINED MSVC) ) add_dependencies(FortranDecimal FortranDecimal.static FortranDecimal.dynamic FortranDecimal.static_dbg FortranDecimal.dynamic_dbg) -endif() \ No newline at end of file +endif() diff --git a/flang/lib/Decimal/big-radix-floating-point.h b/flang/lib/Decimal/big-radix-floating-point.h index 2143d1d9b3f7..6ce8ae7925c1 100644 --- a/flang/lib/Decimal/big-radix-floating-point.h +++ b/flang/lib/Decimal/big-radix-floating-point.h @@ -30,6 +30,10 @@ #include #include +// Some environments, viz. glibc 2.17, allow the macro HUGE +// to leak out of . +#undef HUGE + namespace Fortran::decimal { static constexpr std::uint64_t TenToThe(int power) { @@ -64,15 +68,15 @@ private: static constexpr int maxDigits{3 - minLog2AnyBit / log10Radix}; public: - explicit BigRadixFloatingPointNumber( + explicit RT_API_ATTRS BigRadixFloatingPointNumber( enum FortranRounding rounding = RoundNearest) : rounding_{rounding} {} // Converts a binary floating point value. - explicit BigRadixFloatingPointNumber( + explicit RT_API_ATTRS BigRadixFloatingPointNumber( Real, enum FortranRounding = RoundNearest); - BigRadixFloatingPointNumber &SetToZero() { + RT_API_ATTRS BigRadixFloatingPointNumber &SetToZero() { isNegative_ = false; digits_ = 0; exponent_ = 0; @@ -80,14 +84,14 @@ public: } // Converts decimal floating-point to binary. - ConversionToBinaryResult ConvertToBinary(); + RT_API_ATTRS ConversionToBinaryResult ConvertToBinary(); // Parses and converts to binary. Handles leading spaces, // "NaN", & optionally-signed "Inf". Does not skip internal // spaces. // The argument is a reference to a pointer that is left // pointing to the first character that wasn't parsed. - ConversionToBinaryResult ConvertToBinary( + RT_API_ATTRS ConversionToBinaryResult ConvertToBinary( const char *&, const char *end = nullptr); // Formats a decimal floating-point number to a user buffer. @@ -96,7 +100,7 @@ public: // after the last digit; the effective decimal exponent is // returned as part of the result structure so that it can be // formatted by the client. - ConversionToDecimalResult ConvertToDecimal( + RT_API_ATTRS ConversionToDecimalResult ConvertToDecimal( char *, std::size_t, enum DecimalConversionFlags, int digits) const; // Discard decimal digits not needed to distinguish this value @@ -108,13 +112,14 @@ public: // This minimization necessarily assumes that the value will be // emitted and read back into the same (or less precise) format // with default rounding to the nearest value. - void Minimize( + RT_API_ATTRS void Minimize( BigRadixFloatingPointNumber &&less, BigRadixFloatingPointNumber &&more); template STREAM &Dump(STREAM &) const; private: - BigRadixFloatingPointNumber(const BigRadixFloatingPointNumber &that) + RT_API_ATTRS BigRadixFloatingPointNumber( + const BigRadixFloatingPointNumber &that) : digits_{that.digits_}, exponent_{that.exponent_}, isNegative_{that.isNegative_}, rounding_{that.rounding_} { for (int j{0}; j < digits_; ++j) { @@ -122,7 +127,7 @@ private: } } - bool IsZero() const { + RT_API_ATTRS bool IsZero() const { // Don't assume normalization. for (int j{0}; j < digits_; ++j) { if (digit_[j] != 0) { @@ -136,13 +141,13 @@ private: // (When this happens during decimal-to-binary conversion, // there are more digits in the input string than can be // represented precisely.) - bool IsFull() const { + RT_API_ATTRS bool IsFull() const { return digits_ == digitLimit_ && digit_[digits_ - 1] >= radix / 10; } // Sets *this to an unsigned integer value. // Returns any remainder. - template UINT SetTo(UINT n) { + template RT_API_ATTRS UINT SetTo(UINT n) { static_assert( std::is_same_v || std::is_unsigned_v); SetToZero(); @@ -169,7 +174,7 @@ private: } } - int RemoveLeastOrderZeroDigits() { + RT_API_ATTRS int RemoveLeastOrderZeroDigits() { int remove{0}; if (digits_ > 0 && digit_[0] == 0) { while (remove < digits_ && digit_[remove] == 0) { @@ -193,25 +198,25 @@ private: return remove; } - void RemoveLeadingZeroDigits() { + RT_API_ATTRS void RemoveLeadingZeroDigits() { while (digits_ > 0 && digit_[digits_ - 1] == 0) { --digits_; } } - void Normalize() { + RT_API_ATTRS void Normalize() { RemoveLeadingZeroDigits(); exponent_ += RemoveLeastOrderZeroDigits() * log10Radix; } // This limited divisibility test only works for even divisors of the radix, // which is fine since it's only ever used with 2 and 5. - template bool IsDivisibleBy() const { + template RT_API_ATTRS bool IsDivisibleBy() const { static_assert(N > 1 && radix % N == 0, "bad modulus"); return digits_ == 0 || (digit_[0] % N) == 0; } - template int DivideBy() { + template RT_API_ATTRS int DivideBy() { Digit remainder{0}; for (int j{digits_ - 1}; j >= 0; --j) { Digit q{digit_[j] / DIVISOR}; @@ -222,7 +227,7 @@ private: return remainder; } - void DivideByPowerOfTwo(int twoPow) { // twoPow <= log10Radix + RT_API_ATTRS void DivideByPowerOfTwo(int twoPow) { // twoPow <= log10Radix Digit remainder{0}; auto mask{(Digit{1} << twoPow) - 1}; auto coeff{radix >> twoPow}; @@ -234,7 +239,7 @@ private: } // Returns true on overflow - bool DivideByPowerOfTwoInPlace(int twoPow) { + RT_API_ATTRS bool DivideByPowerOfTwoInPlace(int twoPow) { if (digits_ > 0) { while (twoPow > 0) { int chunk{twoPow > log10Radix ? log10Radix : twoPow}; @@ -264,7 +269,7 @@ private: return false; // no overflow } - int AddCarry(int position = 0, int carry = 1) { + RT_API_ATTRS int AddCarry(int position = 0, int carry = 1) { for (; position < digits_; ++position) { Digit v{digit_[position] + carry}; if (v < radix) { @@ -286,13 +291,13 @@ private: return carry; } - void Decrement() { + RT_API_ATTRS void Decrement() { for (int j{0}; digit_[j]-- == 0; ++j) { digit_[j] = radix - 1; } } - template int MultiplyByHelper(int carry = 0) { + template RT_API_ATTRS int MultiplyByHelper(int carry = 0) { for (int j{0}; j < digits_; ++j) { auto v{N * digit_[j] + carry}; carry = v / radix; @@ -301,7 +306,7 @@ private: return carry; } - template int MultiplyBy(int carry = 0) { + template RT_API_ATTRS int MultiplyBy(int carry = 0) { if (int newCarry{MultiplyByHelper(carry)}) { return AddCarry(digits_, newCarry); } else { @@ -309,7 +314,7 @@ private: } } - template int MultiplyWithoutNormalization() { + template RT_API_ATTRS int MultiplyWithoutNormalization() { if (int carry{MultiplyByHelper(0)}) { if (digits_ < digitLimit_) { digit_[digits_++] = carry; @@ -322,9 +327,9 @@ private: } } - void LoseLeastSignificantDigit(); // with rounding + RT_API_ATTRS void LoseLeastSignificantDigit(); // with rounding - void PushCarry(int carry) { + RT_API_ATTRS void PushCarry(int carry) { if (digits_ == maxDigits && RemoveLeastOrderZeroDigits() == 0) { LoseLeastSignificantDigit(); digit_[digits_ - 1] += carry; @@ -336,18 +341,20 @@ private: // Adds another number and then divides by two. // Assumes same exponent and sign. // Returns true when the result has effectively been rounded down. - bool Mean(const BigRadixFloatingPointNumber &); + RT_API_ATTRS bool Mean(const BigRadixFloatingPointNumber &); // Parses a floating-point number; leaves the pointer reference // argument pointing at the next character after what was recognized. // The "end" argument can be left null if the caller is sure that the // string is properly terminated with an addressable character that // can't be in a valid floating-point character. - bool ParseNumber(const char *&, bool &inexact, const char *end); + RT_API_ATTRS bool ParseNumber(const char *&, bool &inexact, const char *end); using Raw = typename Real::RawType; - constexpr Raw SignBit() const { return Raw{isNegative_} << (Real::bits - 1); } - constexpr Raw Infinity() const { + constexpr RT_API_ATTRS Raw SignBit() const { + return Raw{isNegative_} << (Real::bits - 1); + } + constexpr RT_API_ATTRS Raw Infinity() const { Raw result{static_cast(Real::maxExponent)}; result <<= Real::significandBits; result |= SignBit(); @@ -356,7 +363,7 @@ private: } return result; } - constexpr Raw NaN(bool isQuiet = true) { + constexpr RT_API_ATTRS Raw NaN(bool isQuiet = true) { Raw result{Real::maxExponent}; result <<= Real::significandBits; result |= SignBit(); @@ -369,7 +376,7 @@ private: } return result; } - constexpr Raw HUGE() const { + constexpr RT_API_ATTRS Raw HUGE() const { Raw result{static_cast(Real::maxExponent)}; result <<= Real::significandBits; result |= SignBit(); diff --git a/flang/lib/Decimal/binary-to-decimal.cpp b/flang/lib/Decimal/binary-to-decimal.cpp index 55fc548a6979..b64865e95df2 100644 --- a/flang/lib/Decimal/binary-to-decimal.cpp +++ b/flang/lib/Decimal/binary-to-decimal.cpp @@ -336,6 +336,8 @@ template ConversionToDecimalResult ConvertToDecimal<113>(char *, std::size_t, BinaryFloatingPointNumber<113>); extern "C" { +RT_EXT_API_GROUP_BEGIN + ConversionToDecimalResult ConvertFloatToDecimal(char *buffer, std::size_t size, enum DecimalConversionFlags flags, int digits, enum FortranRounding rounding, float x) { @@ -365,7 +367,9 @@ ConversionToDecimalResult ConvertLongDoubleToDecimal(char *buffer, rounding, Fortran::decimal::BinaryFloatingPointNumber<113>(x)); } #endif -} + +RT_EXT_API_GROUP_END +} // extern "C" template template diff --git a/flang/lib/Decimal/decimal-to-binary.cpp b/flang/lib/Decimal/decimal-to-binary.cpp index c5cdb72e355f..dc4aa82ac6fe 100644 --- a/flang/lib/Decimal/decimal-to-binary.cpp +++ b/flang/lib/Decimal/decimal-to-binary.cpp @@ -191,12 +191,12 @@ public: static constexpr IntType topBit{IntType{1} << (precision - 1)}; static constexpr IntType mask{topBit + (topBit - 1)}; - IntermediateFloat() {} + RT_API_ATTRS IntermediateFloat() {} IntermediateFloat(const IntermediateFloat &) = default; // Assumes that exponent_ is valid on entry, and may increment it. // Returns the number of guard_ bits that have been determined. - template bool SetTo(UINT n) { + template RT_API_ATTRS bool SetTo(UINT n) { static constexpr int nBits{CHAR_BIT * sizeof n}; if constexpr (precision >= nBits) { value_ = n; @@ -218,14 +218,14 @@ public: } } - void ShiftIn(int bit = 0) { value_ = value_ + value_ + bit; } - bool IsFull() const { return value_ >= topBit; } - void AdjustExponent(int by) { exponent_ += by; } - void SetGuard(int g) { + RT_API_ATTRS void ShiftIn(int bit = 0) { value_ = value_ + value_ + bit; } + RT_API_ATTRS bool IsFull() const { return value_ >= topBit; } + RT_API_ATTRS void AdjustExponent(int by) { exponent_ += by; } + RT_API_ATTRS void SetGuard(int g) { guard_ |= (static_cast(g & 6) << (guardBits - 3)) | (g & 1); } - ConversionToBinaryResult ToBinary( + RT_API_ATTRS ConversionToBinaryResult ToBinary( bool isNegative, FortranRounding) const; private: @@ -241,7 +241,7 @@ private: // The standard says that these overflow cases round to "representable" // numbers, and some popular compilers interpret that to mean +/-HUGE() // rather than +/-Inf. -static inline constexpr bool RoundOverflowToHuge( +static inline RT_API_ATTRS constexpr bool RoundOverflowToHuge( enum FortranRounding rounding, bool isNegative) { return rounding == RoundToZero || (!isNegative && rounding == RoundDown) || (isNegative && rounding == RoundUp); @@ -531,6 +531,8 @@ template ConversionToBinaryResult<113> ConvertToBinary<113>( const char *&, enum FortranRounding, const char *end); extern "C" { +RT_EXT_API_GROUP_BEGIN + enum ConversionResultFlags ConvertDecimalToFloat( const char **p, float *f, enum FortranRounding rounding) { auto result{Fortran::decimal::ConvertToBinary<24>(*p, rounding)}; @@ -552,5 +554,7 @@ enum ConversionResultFlags ConvertDecimalToLongDouble( reinterpret_cast(&result.binary), sizeof *ld); return result.flags; } -} + +RT_EXT_API_GROUP_END +} // extern "C" } // namespace Fortran::decimal diff --git a/flang/runtime/CMakeLists.txt b/flang/runtime/CMakeLists.txt index c0e4cff698e3..2a65a22ab674 100644 --- a/flang/runtime/CMakeLists.txt +++ b/flang/runtime/CMakeLists.txt @@ -171,10 +171,7 @@ set(sources utf.cpp ) -option(FLANG_EXPERIMENTAL_CUDA_RUNTIME - "Compile Fortran runtime as CUDA sources (experimental)" OFF - ) -set(FLANG_LIBCUDACXX_PATH "" CACHE PATH "Path to libcu++ package installation") +include(AddFlangOffloadRuntime) # List of files that are buildable for all devices. set(supported_files @@ -227,128 +224,8 @@ set(supported_files utf.cpp ) -if (FLANG_EXPERIMENTAL_CUDA_RUNTIME) - if (BUILD_SHARED_LIBS) - message(FATAL_ERROR - "BUILD_SHARED_LIBS is not supported for CUDA build of Fortran runtime" - ) - endif() - - enable_language(CUDA) - - # TODO: figure out how to make target property CUDA_SEPARABLE_COMPILATION - # work, and avoid setting CMAKE_CUDA_SEPARABLE_COMPILATION. - set(CMAKE_CUDA_SEPARABLE_COMPILATION ON) - - # Treat all supported sources as CUDA files. - set_source_files_properties(${supported_files} PROPERTIES LANGUAGE CUDA) - set(CUDA_COMPILE_OPTIONS) - if ("${CMAKE_CUDA_COMPILER_ID}" MATCHES "Clang") - # Allow varargs. - set(CUDA_COMPILE_OPTIONS - -Xclang -fcuda-allow-variadic-functions - ) - endif() - if ("${CMAKE_CUDA_COMPILER_ID}" MATCHES "NVIDIA") - set(CUDA_COMPILE_OPTIONS - --expt-relaxed-constexpr - # Disable these warnings: - # 'long double' is treated as 'double' in device code - -Xcudafe --diag_suppress=20208 - -Xcudafe --display_error_number - ) - endif() - set_source_files_properties(${supported_files} PROPERTIES COMPILE_OPTIONS - "${CUDA_COMPILE_OPTIONS}" - ) - - if (EXISTS "${FLANG_LIBCUDACXX_PATH}/include") - # When using libcudacxx headers files, we have to use them - # for all files of F18 runtime. - include_directories(AFTER ${FLANG_LIBCUDACXX_PATH}/include) - add_compile_definitions(RT_USE_LIBCUDACXX=1) - endif() -endif() - -set(FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD "off" CACHE STRING - "Compile Fortran runtime as OpenMP target offload sources (experimental). Valid options are 'off', 'host_device', 'nohost'") - -set(FLANG_OMP_DEVICE_ARCHITECTURES "all" CACHE STRING - "List of OpenMP device architectures to be used to compile the Fortran runtime (e.g. 'gfx1103;sm_90')") - -if (NOT FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD STREQUAL "off") - # 'host_device' build only works with Clang compiler currently. - # The build is done with the CMAKE_C/CXX_COMPILER, i.e. it does not use - # the in-tree built Clang. We may have a mode that would use the in-tree - # built Clang. - # - # 'nohost' is supposed to produce an LLVM Bitcode library, - # and it has to be done with a C/C++ compiler producing LLVM Bitcode - # compatible with the LLVM toolchain version distributed with the Flang - # compiler. - # In general, the in-tree built Clang should be used for 'nohost' build. - # Note that 'nohost' build does not produce the host version of Flang - # runtime library, so there will be two separate distributable objects. - # 'nohost' build is a TODO. - - if (NOT FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD STREQUAL "host_device") - message(FATAL_ERROR "Unsupported OpenMP offload build of Flang runtime") - endif() - if (BUILD_SHARED_LIBS) - message(FATAL_ERROR - "BUILD_SHARED_LIBS is not supported for OpenMP offload build of Fortran runtime" - ) - endif() - - if ("${CMAKE_CXX_COMPILER_ID}" MATCHES "Clang" AND - "${CMAKE_C_COMPILER_ID}" MATCHES "Clang") - - set(all_amdgpu_architectures - "gfx700;gfx701;gfx801;gfx803;gfx900;gfx902;gfx906" - "gfx908;gfx90a;gfx90c;gfx940;gfx1010;gfx1030" - "gfx1031;gfx1032;gfx1033;gfx1034;gfx1035;gfx1036" - "gfx1100;gfx1101;gfx1102;gfx1103;gfx1150;gfx1151" - ) - set(all_nvptx_architectures - "sm_35;sm_37;sm_50;sm_52;sm_53;sm_60;sm_61;sm_62" - "sm_70;sm_72;sm_75;sm_80;sm_86;sm_89;sm_90" - ) - set(all_gpu_architectures - "${all_amdgpu_architectures};${all_nvptx_architectures}" - ) - # TODO: support auto detection on the build system. - if (FLANG_OMP_DEVICE_ARCHITECTURES STREQUAL "all") - set(FLANG_OMP_DEVICE_ARCHITECTURES ${all_gpu_architectures}) - endif() - list(REMOVE_DUPLICATES FLANG_OMP_DEVICE_ARCHITECTURES) - - string(REPLACE ";" "," compile_for_architectures - "${FLANG_OMP_DEVICE_ARCHITECTURES}" - ) - - set(OMP_COMPILE_OPTIONS - -fopenmp - -fvisibility=hidden - -fopenmp-cuda-mode - --offload-arch=${compile_for_architectures} - # Force LTO for the device part. - -foffload-lto - ) - set_source_files_properties(${supported_files} PROPERTIES COMPILE_OPTIONS - "${OMP_COMPILE_OPTIONS}" - ) - - # Enable "declare target" in the source code. - set_source_files_properties(${supported_files} - PROPERTIES COMPILE_DEFINITIONS OMP_OFFLOAD_BUILD - ) - else() - message(FATAL_ERROR - "Flang runtime build is not supported for these compilers:\n" - "CMAKE_CXX_COMPILER_ID: ${CMAKE_CXX_COMPILER_ID}\n" - "CMAKE_C_COMPILER_ID: ${CMAKE_C_COMPILER_ID}") - endif() -endif() +enable_cuda_compilation("${supported_files}") +enable_omp_offload_compilation("${supported_files}") if (NOT TARGET FortranFloat128Math) # If FortranFloat128Math is not defined, then we are not building -- GitLab From 65e5391657147d1bda3a4d9b26c9b3db0ca54fd7 Mon Sep 17 00:00:00 2001 From: Usama Hameed Date: Fri, 5 Apr 2024 14:48:16 -0700 Subject: [PATCH 038/695] Pass the linker version to libfuzzer tests on darwin (#87719) The HOST_LINK_VERSION is a hardcoded string in Darwin clang that detects the linker version at configure time. The driver uses this information to build the correct set of arguments for the linker. This patch detects the linker version again during compiler-rt configuration and passes it to the libfuzzer tests. This allows a clang built on a machine with a new linker to run compiler-rt tests on a machine with an old linker. rdar://125932376 --- compiler-rt/test/fuzzer/lit.cfg.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/compiler-rt/test/fuzzer/lit.cfg.py b/compiler-rt/test/fuzzer/lit.cfg.py index 4e203236b167..9084254b3b15 100644 --- a/compiler-rt/test/fuzzer/lit.cfg.py +++ b/compiler-rt/test/fuzzer/lit.cfg.py @@ -98,6 +98,11 @@ def generate_compiler_cmd(is_cpp=True, fuzzer_enabled=True, msan_enabled=False): if "windows" in config.available_features: extra_cmd = extra_cmd + " -D_DISABLE_VECTOR_ANNOTATION -D_DISABLE_STRING_ANNOTATION" + if "darwin" in config.available_features and getattr( + config, "darwin_linker_version", None + ): + extra_cmd = extra_cmd + " -mlinker-version=" + config.darwin_linker_version + return " ".join( [ compiler_cmd, -- GitLab From 80deb8269f2252b65c8af09da100e5b4949d589d Mon Sep 17 00:00:00 2001 From: Robin Caloudis Date: Fri, 5 Apr 2024 23:49:46 +0200 Subject: [PATCH 039/695] [libc][fenv] Add compile time check (#87826) Take care of a TODO. This check makes sure that the fexcept_t value fits in an int value. TODO introduced in: https://github.com/llvm/llvm-project/commit/9550f8ba9a3a697f28a7920c8aeb5cba1e8003a6 --- libc/src/fenv/fegetexceptflag.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/libc/src/fenv/fegetexceptflag.cpp b/libc/src/fenv/fegetexceptflag.cpp index 71b87ce7315d..c6160da7afbd 100644 --- a/libc/src/fenv/fegetexceptflag.cpp +++ b/libc/src/fenv/fegetexceptflag.cpp @@ -15,7 +15,8 @@ namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, fegetexceptflag, (fexcept_t * flagp, int excepts)) { - // TODO: Add a compile time check to see if the excepts actually fit in flagp. + static_assert(sizeof(int) >= sizeof(fexcept_t), + "fexcept_t value cannot fit in an int value."); *flagp = static_cast(fputil::test_except(FE_ALL_EXCEPT) & excepts); return 0; } -- GitLab From fe45029dbdee6b3df2dbeaed17c9dd598ec511f2 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Fri, 5 Apr 2024 14:49:02 -0700 Subject: [PATCH 040/695] [cmake] Back out of making unsupported `-no_exported_symbols` linker a fatal error for now Appeases build bots while being investigated. --- llvm/cmake/modules/AddLLVM.cmake | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index f8a17f645e25..81398ddb5c92 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -1038,14 +1038,9 @@ macro(add_llvm_executable name) add_llvm_symbol_exports( ${name} ${LLVM_EXPORTED_SYMBOL_FILE} ) endif(LLVM_EXPORTED_SYMBOL_FILE) - if (NOT LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES) - if(LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS) + if (NOT LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES AND LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS) set_property(TARGET ${name} APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-no_exported_symbols") - else() - message(FATAL_ERROR - "LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES cannot be disabled when linker does not support \"-no_exported_symbols\"") - endif() endif() if (LLVM_LINK_LLVM_DYLIB AND NOT ARG_DISABLE_LLVM_LINK_LLVM_DYLIB) -- GitLab From af34a5d382bc7cd93c620efa00dce449de252a0a Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Fri, 5 Apr 2024 14:50:45 -0700 Subject: [PATCH 041/695] [libc][docs] Introduce docgen (#87682) This script+config should help us generate more consistent documentation wrt. what we currently support or not. As an example usage: $ ./libc/utils/docgen/docgen.py fenv.h Will spit out an RST formatted table that can be copy+pasted into our docs. The config is not filled out entirely, but doing so and then updating our docs would be great beginner bugs for new contributors. Having python+json generate things like docs, or headers (as imagined in https://github.com/nickdesaulniers/llvm-project/tree/hdr-gen2) is perhaps easier to work with than tablegen, and doesn't introduce a dependency on a host tool that needs to be compiled from llvm sources before building the rest of the libc. This can probably be merged with whatever we end up doing to replace libc-hdrgen. Please use https://llvm.org/docs/CodingStandards.html#python-version-and-source-code-formatting for keeping this file formatted. --- libc/docs/fenv.rst | 64 +++++++++++++++++++++++++++++ libc/docs/index.rst | 1 + libc/utils/docgen/ctype.json | 7 ++++ libc/utils/docgen/docgen.py | 80 ++++++++++++++++++++++++++++++++++++ libc/utils/docgen/fenv.json | 58 ++++++++++++++++++++++++++ 5 files changed, 210 insertions(+) create mode 100644 libc/docs/fenv.rst create mode 100644 libc/utils/docgen/ctype.json create mode 100755 libc/utils/docgen/docgen.py create mode 100644 libc/utils/docgen/fenv.json diff --git a/libc/docs/fenv.rst b/libc/docs/fenv.rst new file mode 100644 index 000000000000..6574fb7246dd --- /dev/null +++ b/libc/docs/fenv.rst @@ -0,0 +1,64 @@ +.. include:: check.rst + +fenv.h Functions +================ + +.. list-table:: + :widths: auto + :align: center + :header-rows: 1 + + * - Function + - Implemented + - Standard + * - fe_dec_getround + - + - 7.6.5.3 + * - fe_dec_setround + - + - 7.6.5.6 + * - feclearexcept + - |check| + - 7.6.4.1 + * - fegetenv + - |check| + - 7.6.6.1 + * - fegetexceptflag + - |check| + - 7.6.4.2 + * - fegetmode + - + - 7.6.5.1 + * - fegetround + - |check| + - 7.6.5.2 + * - feholdexcept + - |check| + - 7.6.6.2 + * - feraiseexcept + - |check| + - 7.6.4.3 + * - fesetenv + - |check| + - 7.6.6.3 + * - fesetexcept + - + - 7.6.4.4 + * - fesetexceptflag + - |check| + - 7.6.4.5 + * - fesetmode + - + - 7.6.5.4 + * - fesetround + - |check| + - 7.6.5.5 + * - fetestexcept + - |check| + - 7.6.4.7 + * - fetestexceptflag + - + - 7.6.4.6 + * - feupdateenv + - |check| + - 7.6.6.4 diff --git a/libc/docs/index.rst b/libc/docs/index.rst index 370fcd843974..65ccb91e92ff 100644 --- a/libc/docs/index.rst +++ b/libc/docs/index.rst @@ -66,6 +66,7 @@ stages there is no ABI stability in any form. strings stdio stdbit + fenv libc_search c23 diff --git a/libc/utils/docgen/ctype.json b/libc/utils/docgen/ctype.json new file mode 100644 index 000000000000..4102c2dd1109 --- /dev/null +++ b/libc/utils/docgen/ctype.json @@ -0,0 +1,7 @@ +{ + "functions": { + "isalnum": null, + "isalpha": null, + "isblank": null + } +} diff --git a/libc/utils/docgen/docgen.py b/libc/utils/docgen/docgen.py new file mode 100755 index 000000000000..7411b4506f08 --- /dev/null +++ b/libc/utils/docgen/docgen.py @@ -0,0 +1,80 @@ +#!/usr/bin/env python +# +# ====- Generate documentation for libc functions ------------*- python -*--==# +# +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +# +# ==-------------------------------------------------------------------------==# +from argparse import ArgumentParser, Namespace +from pathlib import Path +from typing import Dict +import sys +import json + + +def load_api(hname: str) -> Dict: + p = Path(__file__).parent / Path(hname).with_suffix(".json") + api = p.read_text(encoding="utf-8") + return json.loads(api) + + +# TODO: we may need to get more sophisticated for less generic implementations. +# Does libc/src/{hname minus .h suffix}/{fname}.cpp exist? +def is_implemented(hname: str, fname: str) -> bool: + return Path( + Path(__file__).parent.parent.parent, + "src", + hname.rstrip(".h"), + fname + ".cpp", + ).exists() + + +def print_functions(header: str, functions: Dict): + for key in sorted(functions.keys()): + print(f" * - {key}") + + if is_implemented(header, key): + print(" - |check|") + else: + print(" -") + + # defined is optional. Having any content is optional. + if functions[key] is not None and "defined" in functions[key]: + print(f' - {functions[key]["defined"]}') + else: + print(" -") + + +def print_header(header: str, api: Dict): + fns = f"{header} Functions" + print(fns) + print("=" * (len(fns))) + print( + f""" +.. list-table:: + :widths: auto + :align: center + :header-rows: 1 + + * - Function + - Implemented + - Standard""" + ) + # TODO: how do we want to signal implementation of macros? + print_functions(header, api["functions"]) + + +def parse_args() -> Namespace: + parser = ArgumentParser() + choices = [p.with_suffix(".h").name for p in Path(__file__).parent.glob("*.json")] + parser.add_argument("header_name", choices=choices) + return parser.parse_args() + + +if __name__ == "__main__": + args = parse_args() + api = load_api(args.header_name) + + print_header(args.header_name, api) diff --git a/libc/utils/docgen/fenv.json b/libc/utils/docgen/fenv.json new file mode 100644 index 000000000000..0af38b16b2d9 --- /dev/null +++ b/libc/utils/docgen/fenv.json @@ -0,0 +1,58 @@ +{ + "macros": [ + "__STDC_VERSION_FENV_H__" + ], + "functions": { + "feclearexcept": { + "defined": "7.6.4.1" + }, + "fegetexceptflag": { + "defined": "7.6.4.2" + }, + "feraiseexcept": { + "defined": "7.6.4.3" + }, + "fesetexcept": { + "defined": "7.6.4.4" + }, + "fesetexceptflag": { + "defined": "7.6.4.5" + }, + "fetestexceptflag": { + "defined": "7.6.4.6" + }, + "fetestexcept": { + "defined": "7.6.4.7" + }, + "fegetmode": { + "defined": "7.6.5.1" + }, + "fegetround": { + "defined": "7.6.5.2" + }, + "fe_dec_getround": { + "defined": "7.6.5.3" + }, + "fesetmode": { + "defined": "7.6.5.4" + }, + "fesetround": { + "defined": "7.6.5.5" + }, + "fe_dec_setround": { + "defined": "7.6.5.6" + }, + "fegetenv": { + "defined": "7.6.6.1" + }, + "feholdexcept": { + "defined": "7.6.6.2" + }, + "fesetenv": { + "defined": "7.6.6.3" + }, + "feupdateenv": { + "defined": "7.6.6.4" + } + } +} -- GitLab From 920298456037b9ed3ab14cb646ef6d3bf95d2c2b Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Fri, 5 Apr 2024 14:52:35 -0700 Subject: [PATCH 042/695] [flang][build] Fixed paths discrovery for the out-of-tree build. (#87822) When building flang out-of-tree with relative paths in LLVM_DIR, CLANG_DIR and MLIR_DIR, we need to compute the absolute paths based on the CMake build directory (i.e. where the cmake is invoked from). --- flang/CMakeLists.txt | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/flang/CMakeLists.txt b/flang/CMakeLists.txt index 71141e5efac4..c8e75024823f 100644 --- a/flang/CMakeLists.txt +++ b/flang/CMakeLists.txt @@ -81,12 +81,13 @@ if (FLANG_STANDALONE_BUILD) mark_as_advanced(LLVM_ENABLE_ASSERTIONS) endif() - # We need a pre-built/installed version of LLVM. - find_package(LLVM REQUIRED HINTS "${LLVM_CMAKE_DIR}") # If the user specifies a relative path to LLVM_DIR, the calls to include # LLVM modules fail. Append the absolute path to LLVM_DIR instead. - get_filename_component(LLVM_DIR_ABSOLUTE ${LLVM_DIR} REALPATH) + get_filename_component(LLVM_DIR_ABSOLUTE ${LLVM_DIR} + REALPATH BASE_DIR ${CMAKE_CURRENT_BINARY_DIR}) list(APPEND CMAKE_MODULE_PATH ${LLVM_DIR_ABSOLUTE}) + # We need a pre-built/installed version of LLVM. + find_package(LLVM REQUIRED HINTS "${LLVM_DIR_ABSOLUTE}") # Users might specify a path to CLANG_DIR that's: # * a full path, or @@ -97,7 +98,7 @@ if (FLANG_STANDALONE_BUILD) CLANG_DIR_ABSOLUTE ${CLANG_DIR} REALPATH - ${CMAKE_CURRENT_SOURCE_DIR}) + BASE_DIR ${CMAKE_CURRENT_BINARY_DIR}) list(APPEND CMAKE_MODULE_PATH ${CLANG_DIR_ABSOLUTE}) # TODO: Remove when libclangDriver is lifted out of Clang @@ -124,13 +125,14 @@ if (FLANG_STANDALONE_BUILD) include(AddClang) include(TableGen) - find_package(MLIR REQUIRED CONFIG) - # Use SYSTEM for the same reasons as for LLVM includes - include_directories(SYSTEM ${MLIR_INCLUDE_DIRS}) # If the user specifies a relative path to MLIR_DIR, the calls to include # MLIR modules fail. Append the absolute path to MLIR_DIR instead. - get_filename_component(MLIR_DIR_ABSOLUTE ${MLIR_DIR} REALPATH) + get_filename_component(MLIR_DIR_ABSOLUTE ${MLIR_DIR} + REALPATH BASE_DIR ${CMAKE_CURRENT_BINARY_DIR}) list(APPEND CMAKE_MODULE_PATH ${MLIR_DIR_ABSOLUTE}) + find_package(MLIR REQUIRED CONFIG HINTS ${MLIR_DIR_ABSOLUTE}) + # Use SYSTEM for the same reasons as for LLVM includes + include_directories(SYSTEM ${MLIR_INCLUDE_DIRS}) include(AddMLIR) find_program(MLIR_TABLEGEN_EXE "mlir-tblgen" ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH) -- GitLab From 42a6ad7bad85a0e35ff5ae6b9b370617509e363a Mon Sep 17 00:00:00 2001 From: Diego Caballero Date: Fri, 5 Apr 2024 15:01:20 -0700 Subject: [PATCH 043/695] [mlir][Vector] Fix n-D vector.extract/insert lowering to LLVM (#87591) The lowering of n-D vector.extract/insert ops to LLVM is not supported but if one of these accidentally reaches the vector-to-llvm conversion patterns, we end up with a kind of puzzling crash. This PR fixes that crash and gracefully bails out in those cases. --- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 20 +++------------ .../VectorToLLVM/vector-to-llvm.mlir | 25 +++++++++++++++++++ 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index 337f8bb6ab99..85d10f326e26 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -1082,14 +1082,8 @@ public: if (!llvmResultType) return failure(); - SmallVector positionVec; - for (auto [idx, pos] : llvm::enumerate(extractOp.getMixedPosition())) { - if (pos.is()) - // Make sure we use the value that has been already converted to LLVM. - positionVec.push_back(adaptor.getDynamicPosition()[idx]); - else - positionVec.push_back(pos); - } + SmallVector positionVec = getMixedValues( + adaptor.getStaticPosition(), adaptor.getDynamicPosition(), rewriter); // Extract entire vector. Should be handled by folder, but just to be safe. ArrayRef position(positionVec); @@ -1209,14 +1203,8 @@ public: if (!llvmResultType) return failure(); - SmallVector positionVec; - for (auto [idx, pos] : llvm::enumerate(insertOp.getMixedPosition())) { - if (pos.is()) - // Make sure we use the value that has been already converted to LLVM. - positionVec.push_back(adaptor.getDynamicPosition()[idx]); - else - positionVec.push_back(pos); - } + SmallVector positionVec = getMixedValues( + adaptor.getStaticPosition(), adaptor.getDynamicPosition(), rewriter); // Overwrite entire vector with value. Should be handled by folder, but // just to be safe. diff --git a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir index e94e51d49a98..1712d3d745b7 100644 --- a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir +++ b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir @@ -738,6 +738,18 @@ func.func @extract_element_with_value_1d(%arg0: vector<16xf32>, %arg1: index) -> // ----- +func.func @extract_element_with_value_2d(%arg0: vector<1x16xf32>, %arg1: index) -> f32 { + %0 = vector.extract %arg0[0, %arg1]: f32 from vector<1x16xf32> + return %0 : f32 +} + +// Multi-dim vectors are not supported but this test shouldn't crash. + +// CHECK-LABEL: @extract_element_with_value_2d( +// CHECK: vector.extract + +// ----- + // CHECK-LABEL: @insert_element_0d // CHECK-SAME: %[[A:.*]]: f32, func.func @insert_element_0d(%a: f32, %b: vector) -> vector { @@ -853,6 +865,19 @@ func.func @insert_element_with_value_1d(%arg0: vector<16xf32>, %arg1: f32, %arg2 // ----- +func.func @insert_element_with_value_2d(%base: vector<1x16xf32>, %value: f32, %idx: index) + -> vector<1x16xf32> { + %0 = vector.insert %value, %base[0, %idx]: f32 into vector<1x16xf32> + return %0 : vector<1x16xf32> +} + +// Multi-dim vectors are not supported but this test shouldn't crash. + +// CHECK-LABEL: @insert_element_with_value_2d( +// CHECK: vector.insert + +// ----- + func.func @vector_type_cast(%arg0: memref<8x8x8xf32>) -> memref> { %0 = vector.type_cast %arg0: memref<8x8x8xf32> to memref> return %0 : memref> -- GitLab From 3b337242ee165554f0017b00671381ec5b1ba855 Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Fri, 5 Apr 2024 15:10:04 -0700 Subject: [PATCH 044/695] [NFC][flang][runtime] Moved freestanding-tools.h to use it in FortranDecimal. (#87827) I will add `toupper` implementation into it in the next PR. --- flang/{runtime => include/flang/Runtime}/freestanding-tools.h | 2 +- flang/runtime/buffer.h | 2 +- flang/runtime/descriptor-io.cpp | 2 +- flang/runtime/edit-input.cpp | 2 +- flang/runtime/format.h | 2 +- flang/runtime/internal-unit.cpp | 2 +- flang/runtime/memory.cpp | 2 +- flang/runtime/tools.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) rename flang/{runtime => include/flang/Runtime}/freestanding-tools.h (98%) diff --git a/flang/runtime/freestanding-tools.h b/flang/include/flang/Runtime/freestanding-tools.h similarity index 98% rename from flang/runtime/freestanding-tools.h rename to flang/include/flang/Runtime/freestanding-tools.h index 9089dc6bcf53..7f8d37d87e0e 100644 --- a/flang/runtime/freestanding-tools.h +++ b/flang/include/flang/Runtime/freestanding-tools.h @@ -1,4 +1,4 @@ -//===-- runtime/freestanding-tools.h ----------------------------*- C++ -*-===// +//===-- include/flang/Runtime/freestanding-tools.h --------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/flang/runtime/buffer.h b/flang/runtime/buffer.h index ca1baea12efa..41a1abb1b2d9 100644 --- a/flang/runtime/buffer.h +++ b/flang/runtime/buffer.h @@ -11,8 +11,8 @@ #ifndef FORTRAN_RUNTIME_BUFFER_H_ #define FORTRAN_RUNTIME_BUFFER_H_ -#include "freestanding-tools.h" #include "io-error.h" +#include "flang/Runtime/freestanding-tools.h" #include "flang/Runtime/memory.h" #include #include diff --git a/flang/runtime/descriptor-io.cpp b/flang/runtime/descriptor-io.cpp index 93df51cf22d3..380ad425d925 100644 --- a/flang/runtime/descriptor-io.cpp +++ b/flang/runtime/descriptor-io.cpp @@ -7,8 +7,8 @@ //===----------------------------------------------------------------------===// #include "descriptor-io.h" -#include "freestanding-tools.h" #include "flang/Common/restorer.h" +#include "flang/Runtime/freestanding-tools.h" namespace Fortran::runtime::io::descr { RT_OFFLOAD_API_GROUP_BEGIN diff --git a/flang/runtime/edit-input.cpp b/flang/runtime/edit-input.cpp index 935b7c299b25..37989bbcee0a 100644 --- a/flang/runtime/edit-input.cpp +++ b/flang/runtime/edit-input.cpp @@ -7,12 +7,12 @@ //===----------------------------------------------------------------------===// #include "edit-input.h" -#include "freestanding-tools.h" #include "namelist.h" #include "utf.h" #include "flang/Common/optional.h" #include "flang/Common/real.h" #include "flang/Common/uint128.h" +#include "flang/Runtime/freestanding-tools.h" #include #include diff --git a/flang/runtime/format.h b/flang/runtime/format.h index f57cf9204487..5329f2482d3e 100644 --- a/flang/runtime/format.h +++ b/flang/runtime/format.h @@ -12,11 +12,11 @@ #define FORTRAN_RUNTIME_FORMAT_H_ #include "environment.h" -#include "freestanding-tools.h" #include "io-error.h" #include "flang/Common/Fortran.h" #include "flang/Common/optional.h" #include "flang/Decimal/decimal.h" +#include "flang/Runtime/freestanding-tools.h" #include namespace Fortran::runtime { diff --git a/flang/runtime/internal-unit.cpp b/flang/runtime/internal-unit.cpp index 35766306ccef..4097ea659edd 100644 --- a/flang/runtime/internal-unit.cpp +++ b/flang/runtime/internal-unit.cpp @@ -7,9 +7,9 @@ //===----------------------------------------------------------------------===// #include "internal-unit.h" -#include "freestanding-tools.h" #include "io-error.h" #include "flang/Runtime/descriptor.h" +#include "flang/Runtime/freestanding-tools.h" #include #include diff --git a/flang/runtime/memory.cpp b/flang/runtime/memory.cpp index de6c4c72fdac..c7068ad6479a 100644 --- a/flang/runtime/memory.cpp +++ b/flang/runtime/memory.cpp @@ -7,9 +7,9 @@ //===----------------------------------------------------------------------===// #include "flang/Runtime/memory.h" -#include "freestanding-tools.h" #include "terminator.h" #include "tools.h" +#include "flang/Runtime/freestanding-tools.h" #include namespace Fortran::runtime { diff --git a/flang/runtime/tools.h b/flang/runtime/tools.h index 5d7d99c08179..52049c511f13 100644 --- a/flang/runtime/tools.h +++ b/flang/runtime/tools.h @@ -9,12 +9,12 @@ #ifndef FORTRAN_RUNTIME_TOOLS_H_ #define FORTRAN_RUNTIME_TOOLS_H_ -#include "freestanding-tools.h" #include "stat.h" #include "terminator.h" #include "flang/Common/optional.h" #include "flang/Runtime/cpp-type.h" #include "flang/Runtime/descriptor.h" +#include "flang/Runtime/freestanding-tools.h" #include "flang/Runtime/memory.h" #include #include -- GitLab From 5748ad84e5e8e5621f221199cc290666f00e2a30 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Fri, 5 Apr 2024 18:21:16 -0400 Subject: [PATCH 045/695] [libc] Add proxy header math_macros.h. (#87598) Context: https://github.com/llvm/llvm-project/pull/87017 - Add proxy header `libc/hdr/math_macros.h` that will: - include `` in overlay mode, - include `"include/llvm-libc-macros/math-macros.h"` in full build mode. - Its corresponding CMake target `libc.hdr.math_macros` will only depend on `libc.include.math` and `libc.include.llvm-libc-macros.math_macros` in full build mode. - Replace all `#include "include/llvm-libc-macros/math-macros.h"` with `#include "hdr/math_macros.h"`. - Add dependency to `libc.hdr.math_macros` CMake target when using `add_fp_unittest`. - Update the remaining dependency. - Update bazel overlay: add `libc:hdr_math_macros` target, and replacing all dependency on `libc:llvm_libc_macros_math_macros` with `libc:hdr_math_macros`. --- libc/CMakeLists.txt | 1 + libc/fuzzing/math/CMakeLists.txt | 1 + libc/fuzzing/math/RemQuoDiff.h | 2 +- libc/fuzzing/stdlib/CMakeLists.txt | 1 + libc/fuzzing/stdlib/strtofloat_fuzz.cpp | 2 +- libc/hdr/CMakeLists.txt | 33 ++++++ libc/hdr/math_macros.h | 22 ++++ libc/include/llvm-libc-macros/math-macros.h | 12 +- libc/src/__support/FPUtil/CMakeLists.txt | 7 +- libc/src/__support/FPUtil/FEnvImpl.h | 2 +- .../__support/FPUtil/ManipulationFunctions.h | 2 +- .../FPUtil/NearestIntegerOperations.h | 2 +- libc/src/math/generic/CMakeLists.txt | 17 +-- libc/src/math/generic/math_utils.h | 2 +- libc/test/CMakeLists.txt | 6 +- libc/test/UnitTest/FPMatcher.h | 2 +- libc/test/src/CMakeLists.txt | 8 +- libc/test/src/__support/uint_test.cpp | 2 +- libc/test/src/math/CMakeLists.txt | 100 ---------------- libc/test/src/math/CeilTest.h | 2 +- libc/test/src/math/CopySignTest.h | 2 +- libc/test/src/math/FAbsTest.h | 2 +- libc/test/src/math/FDimTest.h | 2 +- libc/test/src/math/FMaxTest.h | 2 +- libc/test/src/math/FMinTest.h | 2 +- libc/test/src/math/FModTest.h | 2 +- libc/test/src/math/FloorTest.h | 2 +- libc/test/src/math/FrexpTest.h | 2 +- libc/test/src/math/HypotTest.h | 2 +- libc/test/src/math/ILogbTest.h | 2 +- libc/test/src/math/LdExpTest.h | 2 +- libc/test/src/math/LogbTest.h | 2 +- libc/test/src/math/ModfTest.h | 2 +- libc/test/src/math/NextAfterTest.h | 2 +- libc/test/src/math/RIntTest.h | 2 +- libc/test/src/math/RemQuoTest.h | 2 +- libc/test/src/math/RoundEvenTest.h | 2 +- libc/test/src/math/RoundTest.h | 2 +- libc/test/src/math/RoundToIntegerTest.h | 2 +- libc/test/src/math/SqrtTest.h | 2 +- libc/test/src/math/TruncTest.h | 2 +- libc/test/src/math/acosf_test.cpp | 2 +- libc/test/src/math/acoshf_test.cpp | 2 +- libc/test/src/math/asinf_test.cpp | 2 +- libc/test/src/math/asinhf_test.cpp | 2 +- libc/test/src/math/atan2f_test.cpp | 2 +- libc/test/src/math/atanf_test.cpp | 2 +- libc/test/src/math/atanhf_test.cpp | 2 +- libc/test/src/math/cos_test.cpp | 2 +- libc/test/src/math/cosf_test.cpp | 2 +- libc/test/src/math/coshf_test.cpp | 2 +- libc/test/src/math/erff_test.cpp | 2 +- libc/test/src/math/exhaustive/CMakeLists.txt | 24 ---- libc/test/src/math/exp10_test.cpp | 2 +- libc/test/src/math/exp10f_test.cpp | 2 +- libc/test/src/math/exp2_test.cpp | 2 +- libc/test/src/math/exp2f_test.cpp | 2 +- libc/test/src/math/exp2m1f_test.cpp | 2 +- libc/test/src/math/exp_test.cpp | 2 +- libc/test/src/math/expf_test.cpp | 2 +- libc/test/src/math/explogxf_test.cpp | 2 +- libc/test/src/math/expm1_test.cpp | 2 +- libc/test/src/math/expm1f_test.cpp | 2 +- libc/test/src/math/fdim_test.cpp | 2 +- libc/test/src/math/fdimf_test.cpp | 2 +- libc/test/src/math/fdiml_test.cpp | 2 +- libc/test/src/math/generic/CMakeLists.txt | 3 - libc/test/src/math/ilogb_test.cpp | 2 +- libc/test/src/math/ilogbf_test.cpp | 2 +- libc/test/src/math/ilogbl_test.cpp | 2 +- libc/test/src/math/log10_test.cpp | 2 +- libc/test/src/math/log10f_test.cpp | 2 +- libc/test/src/math/log1p_test.cpp | 2 +- libc/test/src/math/log1pf_test.cpp | 2 +- libc/test/src/math/log2_test.cpp | 2 +- libc/test/src/math/log2f_test.cpp | 2 +- libc/test/src/math/log_test.cpp | 2 +- libc/test/src/math/logf_test.cpp | 2 +- libc/test/src/math/powf_test.cpp | 2 +- libc/test/src/math/sin_test.cpp | 2 +- libc/test/src/math/sincosf_test.cpp | 2 +- libc/test/src/math/sinf_test.cpp | 2 +- libc/test/src/math/sinhf_test.cpp | 2 +- libc/test/src/math/smoke/CMakeLists.txt | 111 ------------------ libc/test/src/math/smoke/CanonicalizeTest.h | 2 +- libc/test/src/math/smoke/CeilTest.h | 2 +- libc/test/src/math/smoke/CopySignTest.h | 2 +- libc/test/src/math/smoke/FAbsTest.h | 2 +- libc/test/src/math/smoke/FModTest.h | 2 +- libc/test/src/math/smoke/FloorTest.h | 2 +- libc/test/src/math/smoke/HypotTest.h | 2 +- libc/test/src/math/smoke/ModfTest.h | 2 +- libc/test/src/math/smoke/NextAfterTest.h | 2 +- libc/test/src/math/smoke/NextTowardTest.h | 2 +- libc/test/src/math/smoke/RIntTest.h | 2 +- libc/test/src/math/smoke/RemQuoTest.h | 2 +- libc/test/src/math/smoke/RoundEvenTest.h | 2 +- libc/test/src/math/smoke/RoundTest.h | 2 +- libc/test/src/math/smoke/RoundToIntegerTest.h | 2 +- libc/test/src/math/smoke/SqrtTest.h | 2 +- libc/test/src/math/smoke/TruncTest.h | 2 +- libc/test/src/math/smoke/acosf_test.cpp | 2 +- libc/test/src/math/smoke/acoshf_test.cpp | 2 +- libc/test/src/math/smoke/asinf_test.cpp | 2 +- libc/test/src/math/smoke/asinhf_test.cpp | 2 +- libc/test/src/math/smoke/atan2f_test.cpp | 2 +- libc/test/src/math/smoke/atanf_test.cpp | 2 +- libc/test/src/math/smoke/atanhf_test.cpp | 2 +- libc/test/src/math/smoke/cosf_test.cpp | 2 +- libc/test/src/math/smoke/coshf_test.cpp | 2 +- libc/test/src/math/smoke/erff_test.cpp | 2 +- libc/test/src/math/smoke/exp10_test.cpp | 2 +- libc/test/src/math/smoke/exp10f_test.cpp | 2 +- libc/test/src/math/smoke/exp2_test.cpp | 2 +- libc/test/src/math/smoke/exp2f_test.cpp | 2 +- libc/test/src/math/smoke/exp_test.cpp | 2 +- libc/test/src/math/smoke/expf_test.cpp | 2 +- libc/test/src/math/smoke/expm1_test.cpp | 2 +- libc/test/src/math/smoke/expm1f_test.cpp | 2 +- libc/test/src/math/smoke/log10_test.cpp | 2 +- libc/test/src/math/smoke/log10f_test.cpp | 2 +- libc/test/src/math/smoke/log1p_test.cpp | 2 +- libc/test/src/math/smoke/log1pf_test.cpp | 2 +- libc/test/src/math/smoke/log2_test.cpp | 2 +- libc/test/src/math/smoke/log2f_test.cpp | 2 +- libc/test/src/math/smoke/log_test.cpp | 2 +- libc/test/src/math/smoke/logf_test.cpp | 2 +- libc/test/src/math/smoke/powf_test.cpp | 2 +- libc/test/src/math/smoke/sincosf_test.cpp | 2 +- libc/test/src/math/smoke/sinf_test.cpp | 2 +- libc/test/src/math/smoke/sinhf_test.cpp | 2 +- libc/test/src/math/smoke/tanf_test.cpp | 2 +- libc/test/src/math/smoke/tanhf_test.cpp | 2 +- libc/test/src/math/tan_test.cpp | 2 +- libc/test/src/math/tanf_test.cpp | 2 +- libc/test/src/math/tanhf_test.cpp | 2 +- libc/test/src/sys/random/linux/CMakeLists.txt | 1 - libc/test/utils/FPUtil/CMakeLists.txt | 2 +- .../utils/FPUtil/x86_long_double_test.cpp | 2 +- libc/utils/MPFRWrapper/MPFRUtils.cpp | 2 +- .../llvm-project-overlay/libc/BUILD.bazel | 16 ++- .../libc/test/UnitTest/BUILD.bazel | 2 +- .../libc/test/src/__support/BUILD.bazel | 2 +- .../libc/test/src/math/BUILD.bazel | 14 +-- .../test/src/math/libc_math_test_rules.bzl | 2 +- .../libc/test/src/math/smoke/BUILD.bazel | 4 +- .../libc/utils/MPFRWrapper/BUILD.bazel | 2 +- 147 files changed, 222 insertions(+), 417 deletions(-) create mode 100644 libc/hdr/CMakeLists.txt create mode 100644 libc/hdr/math_macros.h diff --git a/libc/CMakeLists.txt b/libc/CMakeLists.txt index a0d79858a896..175efd89d67e 100644 --- a/libc/CMakeLists.txt +++ b/libc/CMakeLists.txt @@ -381,6 +381,7 @@ endforeach() add_subdirectory(include) add_subdirectory(config) +add_subdirectory(hdr) add_subdirectory(src) add_subdirectory(utils) diff --git a/libc/fuzzing/math/CMakeLists.txt b/libc/fuzzing/math/CMakeLists.txt index 86c864083d20..6990a04922a5 100644 --- a/libc/fuzzing/math/CMakeLists.txt +++ b/libc/fuzzing/math/CMakeLists.txt @@ -8,6 +8,7 @@ add_libc_fuzzer( SingleInputSingleOutputDiff.h TwoInputSingleOutputDiff.h DEPENDS + libc.hdr.math_macros libc.src.math.ceil libc.src.math.ceilf libc.src.math.ceill diff --git a/libc/fuzzing/math/RemQuoDiff.h b/libc/fuzzing/math/RemQuoDiff.h index 95a9866f29db..84a6a24ce527 100644 --- a/libc/fuzzing/math/RemQuoDiff.h +++ b/libc/fuzzing/math/RemQuoDiff.h @@ -11,7 +11,7 @@ #include "src/__support/FPUtil/FPBits.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include #include diff --git a/libc/fuzzing/stdlib/CMakeLists.txt b/libc/fuzzing/stdlib/CMakeLists.txt index 711b0fd9820f..204bc619318d 100644 --- a/libc/fuzzing/stdlib/CMakeLists.txt +++ b/libc/fuzzing/stdlib/CMakeLists.txt @@ -22,6 +22,7 @@ add_libc_fuzzer( SRCS strtofloat_fuzz.cpp DEPENDS + libc.hdr.math_macros libc.src.stdlib.atof libc.src.stdlib.strtof libc.src.stdlib.strtod diff --git a/libc/fuzzing/stdlib/strtofloat_fuzz.cpp b/libc/fuzzing/stdlib/strtofloat_fuzz.cpp index b000321854d1..c158162ba623 100644 --- a/libc/fuzzing/stdlib/strtofloat_fuzz.cpp +++ b/libc/fuzzing/stdlib/strtofloat_fuzz.cpp @@ -16,7 +16,7 @@ #include "src/__support/FPUtil/FPBits.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include #include diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt new file mode 100644 index 000000000000..1d3eb9d5240a --- /dev/null +++ b/libc/hdr/CMakeLists.txt @@ -0,0 +1,33 @@ +function(add_proxy_header_library target_name) + cmake_parse_arguments( + "ADD_PROXY_HEADER" + "" # Optional arguments + "" # Single value arguments + "DEPENDS;FULL_BUILD_DEPENDS" # Multi-value arguments + ${ARGN} + ) + + set(deps "") + if(ADD_PROXY_HEADER_DEPENDS) + list(APPEND deps ${ADD_PROXY_HEADER_DEPENDS}) + endif() + + if(LLVM_LIBC_FULL_BUILD AND ADD_PROXY_HEADER_FULL_BUILD_DEPENDS) + list(APPEND deps ${ADD_PROXY_HEADER_FULL_BUILD_DEPENDS}) + endif() + + add_header_library( + ${target_name} + ${ADD_PROXY_HEADER_UNPARSED_ARGUMENTS} + DEPENDS ${deps} + ) +endfunction() + +add_proxy_header_library( + math_macros + HDRS + math_macros.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-macros.math_macros + libc.include.math +) diff --git a/libc/hdr/math_macros.h b/libc/hdr/math_macros.h new file mode 100644 index 000000000000..864afd0e50e3 --- /dev/null +++ b/libc/hdr/math_macros.h @@ -0,0 +1,22 @@ +//===-- Definition of macros from math.h ----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_MATH_MACROS_H +#define LLVM_LIBC_HDR_MATH_MACROS_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-macros/math-macros.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_MATH_MACROS_H diff --git a/libc/include/llvm-libc-macros/math-macros.h b/libc/include/llvm-libc-macros/math-macros.h index 6046ea98cb8a..1cbd1665d0cd 100644 --- a/libc/include/llvm-libc-macros/math-macros.h +++ b/libc/include/llvm-libc-macros/math-macros.h @@ -9,11 +9,6 @@ #ifndef LLVM_LIBC_MACROS_MATH_MACROS_H #define LLVM_LIBC_MACROS_MATH_MACROS_H -// TODO: Remove this. This is a temporary fix for a downstream problem. -// This cannot be left permanently since it would require downstream users to -// define this macro. -#ifdef LIBC_FULL_BUILD - #include "limits-macros.h" #define FP_NAN 0 @@ -62,6 +57,7 @@ // the identifier, even in places with parentheses where a function-like macro // will be expanded (such as a function declaration in a C++ namespace). +// TODO: Move generic functional math macros to a separate header file. #ifdef __cplusplus template inline constexpr bool isfinite(T x) { @@ -84,10 +80,4 @@ template inline constexpr bool isnan(T x) { #endif -#else // LIBC_FULL_BUILD - -#include - -#endif // LIBC_FULL_BUILD - #endif // LLVM_LIBC_MACROS_MATH_MACROS_H diff --git a/libc/src/__support/FPUtil/CMakeLists.txt b/libc/src/__support/FPUtil/CMakeLists.txt index ff155a19758d..1af236ed9d6b 100644 --- a/libc/src/__support/FPUtil/CMakeLists.txt +++ b/libc/src/__support/FPUtil/CMakeLists.txt @@ -4,7 +4,7 @@ add_header_library( FEnvImpl.h DEPENDS libc.include.fenv - libc.include.math + libc.hdr.math_macros libc.src.__support.macros.attributes libc.src.errno.errno ) @@ -15,7 +15,6 @@ add_header_library( rounding_mode.h DEPENDS libc.include.fenv - libc.include.math libc.src.__support.macros.attributes libc.src.__support.macros.properties.architectures libc.src.__support.macros.sanitizer @@ -59,9 +58,9 @@ add_header_library( .fp_bits .fenv_impl .rounding_mode + libc.hdr.math_macros libc.src.__support.CPP.type_traits libc.src.__support.common - libc.include.math libc.src.errno.errno ) @@ -216,12 +215,12 @@ add_header_library( .dyadic_float .nearest_integer_operations .normal_float + libc.hdr.math_macros libc.src.__support.CPP.bit libc.src.__support.CPP.limits libc.src.__support.CPP.type_traits libc.src.__support.common libc.src.__support.macros.optimization - libc.include.math libc.src.errno.errno ) diff --git a/libc/src/__support/FPUtil/FEnvImpl.h b/libc/src/__support/FPUtil/FEnvImpl.h index 6086d5d3de2d..4be1a57f0f4b 100644 --- a/libc/src/__support/FPUtil/FEnvImpl.h +++ b/libc/src/__support/FPUtil/FEnvImpl.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_FENVIMPL_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_FENVIMPL_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE #include "src/__support/macros/properties/architectures.h" #include "src/errno/libc_errno.h" diff --git a/libc/src/__support/FPUtil/ManipulationFunctions.h b/libc/src/__support/FPUtil/ManipulationFunctions.h index 2c90b4888c2e..a289c2ef7046 100644 --- a/libc/src/__support/FPUtil/ManipulationFunctions.h +++ b/libc/src/__support/FPUtil/ManipulationFunctions.h @@ -15,7 +15,7 @@ #include "dyadic_float.h" #include "rounding_mode.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/limits.h" // INT_MAX, INT_MIN #include "src/__support/CPP/type_traits.h" diff --git a/libc/src/__support/FPUtil/NearestIntegerOperations.h b/libc/src/__support/FPUtil/NearestIntegerOperations.h index 6b28e7ffb387..4645ab0b5350 100644 --- a/libc/src/__support/FPUtil/NearestIntegerOperations.h +++ b/libc/src/__support/FPUtil/NearestIntegerOperations.h @@ -13,7 +13,7 @@ #include "FPBits.h" #include "rounding_mode.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/common.h" diff --git a/libc/src/math/generic/CMakeLists.txt b/libc/src/math/generic/CMakeLists.txt index 5bc9066c6263..afbcdea3cf7a 100644 --- a/libc/src/math/generic/CMakeLists.txt +++ b/libc/src/math/generic/CMakeLists.txt @@ -102,8 +102,8 @@ add_object_library( HDRS math_utils.h DEPENDS + libc.hdr.math_macros libc.include.errno - libc.include.math libc.src.errno.errno ) @@ -139,7 +139,6 @@ add_entrypoint_object( ../cosf.h DEPENDS .sincosf_utils - libc.include.math libc.src.errno.errno libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fenv_impl @@ -162,7 +161,6 @@ add_entrypoint_object( DEPENDS .range_reduction .sincosf_utils - libc.include.math libc.src.errno.errno libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fenv_impl @@ -185,7 +183,6 @@ add_entrypoint_object( DEPENDS .range_reduction .sincosf_utils - libc.include.math libc.src.errno.errno libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -207,7 +204,6 @@ add_entrypoint_object( DEPENDS .range_reduction .sincosf_utils - libc.include.math libc.src.errno.errno libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fenv_impl @@ -770,7 +766,6 @@ add_entrypoint_object( libc.src.__support.FPUtil.multiply_add libc.src.__support.FPUtil.polyeval libc.src.__support.macros.optimization - libc.include.math COMPILE_OPTIONS -O3 ) @@ -785,7 +780,6 @@ add_entrypoint_object( .common_constants .explogxf libc.include.errno - libc.include.math libc.src.__support.CPP.bit libc.src.__support.CPP.optional libc.src.__support.FPUtil.dyadic_float @@ -821,7 +815,6 @@ add_entrypoint_object( libc.src.__support.macros.optimization libc.include.errno libc.src.errno.errno - libc.include.math COMPILE_OPTIONS -O3 ) @@ -836,7 +829,6 @@ add_entrypoint_object( .common_constants .explogxf libc.include.errno - libc.include.math libc.src.__support.CPP.bit libc.src.__support.CPP.optional libc.src.__support.FPUtil.dyadic_float @@ -871,7 +863,6 @@ add_header_library( libc.src.__support.common libc.include.errno libc.src.errno.errno - libc.include.math ) add_entrypoint_object( @@ -917,7 +908,6 @@ add_entrypoint_object( .common_constants .explogxf libc.include.errno - libc.include.math libc.src.__support.CPP.bit libc.src.__support.CPP.optional libc.src.__support.FPUtil.dyadic_float @@ -951,7 +941,6 @@ add_header_library( libc.src.__support.common libc.include.errno libc.src.errno.errno - libc.include.math COMPILE_OPTIONS -O3 ) @@ -978,7 +967,6 @@ add_entrypoint_object( .common_constants .explogxf libc.include.errno - libc.include.math libc.src.__support.CPP.bit libc.src.__support.CPP.optional libc.src.__support.FPUtil.dyadic_float @@ -1014,7 +1002,6 @@ add_entrypoint_object( libc.src.__support.macros.optimization libc.include.errno libc.src.errno.errno - libc.include.math COMPILE_OPTIONS -O3 ) @@ -1031,7 +1018,6 @@ add_entrypoint_object( .exp2f_impl .explogxf libc.include.errno - libc.include.math libc.src.__support.CPP.bit libc.src.__support.CPP.optional libc.src.__support.FPUtil.fenv_impl @@ -2755,7 +2741,6 @@ add_object_library( libc.src.__support.common libc.include.errno libc.src.errno.errno - libc.include.math COMPILE_OPTIONS -O3 ) diff --git a/libc/src/math/generic/math_utils.h b/libc/src/math/generic/math_utils.h index cced761fc8c8..3ddfeccfd648 100644 --- a/libc/src/math/generic/math_utils.h +++ b/libc/src/math/generic/math_utils.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_MATH_GENERIC_MATH_UTILS_H #define LLVM_LIBC_SRC_MATH_GENERIC_MATH_UTILS_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/common.h" diff --git a/libc/test/CMakeLists.txt b/libc/test/CMakeLists.txt index 745a9a04b4af..5e26a1000633 100644 --- a/libc/test/CMakeLists.txt +++ b/libc/test/CMakeLists.txt @@ -18,10 +18,6 @@ add_subdirectory(include) add_subdirectory(src) add_subdirectory(utils) -if(LLVM_LIBC_FULL_BUILD AND NOT LIBC_TARGET_OS_IS_BAREMETAL) - add_subdirectory(IntegrationTest) -endif() - if(NOT LLVM_LIBC_FULL_BUILD) return() endif() @@ -31,4 +27,6 @@ if(NOT ${LIBC_TARGET_OS} STREQUAL "linux" AND # Integration tests are currently only available for linux and the GPU. return() endif() + +add_subdirectory(IntegrationTest) add_subdirectory(integration) diff --git a/libc/test/UnitTest/FPMatcher.h b/libc/test/UnitTest/FPMatcher.h index f4553eac5c8a..a76e0b8ef6f6 100644 --- a/libc/test/UnitTest/FPMatcher.h +++ b/libc/test/UnitTest/FPMatcher.h @@ -18,7 +18,7 @@ #include "test/UnitTest/StringUtils.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace LIBC_NAMESPACE { namespace testing { diff --git a/libc/test/src/CMakeLists.txt b/libc/test/src/CMakeLists.txt index f70ffda3f700..95f1768c96aa 100644 --- a/libc/test/src/CMakeLists.txt +++ b/libc/test/src/CMakeLists.txt @@ -3,7 +3,7 @@ function(add_fp_unittest name) "MATH_UNITTEST" "NEED_MPFR;UNIT_TEST_ONLY;HERMETIC_TEST_ONLY" # Optional arguments "" # Single value arguments - "LINK_LIBRARIES" # Multi-value arguments + "LINK_LIBRARIES;DEPENDS" # Multi-value arguments ${ARGN} ) @@ -28,11 +28,17 @@ function(add_fp_unittest name) endif() list(APPEND MATH_UNITTEST_LINK_LIBRARIES LibcFPTestHelpers) + set(deps libc.hdr.math_macros) + if(MATH_UNITTEST_DEPENDS) + list(APPEND deps ${MATH_UNITTEST_DEPENDS}) + endif() + add_libc_test( ${name} ${test_type} LINK_LIBRARIES "${MATH_UNITTEST_LINK_LIBRARIES}" "${MATH_UNITTEST_UNPARSED_ARGUMENTS}" + DEPENDS "${deps}" ) endfunction(add_fp_unittest) diff --git a/libc/test/src/__support/uint_test.cpp b/libc/test/src/__support/uint_test.cpp index 5696e54c73f3..7f278619b8c9 100644 --- a/libc/test/src/__support/uint_test.cpp +++ b/libc/test/src/__support/uint_test.cpp @@ -11,7 +11,7 @@ #include "src/__support/integer_literals.h" // parse_unsigned_bigint #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 -#include "include/llvm-libc-macros/math-macros.h" // HUGE_VALF, HUGE_VALF +#include "hdr/math_macros.h" // HUGE_VALF, HUGE_VALF #include "test/UnitTest/Test.h" namespace LIBC_NAMESPACE { diff --git a/libc/test/src/math/CMakeLists.txt b/libc/test/src/math/CMakeLists.txt index d928cb5c6475..01416eefc15e 100644 --- a/libc/test/src/math/CMakeLists.txt +++ b/libc/test/src/math/CMakeLists.txt @@ -108,7 +108,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabs libc.src.__support.FPUtil.fp_bits ) @@ -123,7 +122,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabsf libc.src.__support.FPUtil.fp_bits ) @@ -138,7 +136,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabsl libc.src.__support.FPUtil.fp_bits ) @@ -153,7 +150,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.trunc libc.src.__support.FPUtil.fp_bits ) @@ -168,7 +164,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.truncf libc.src.__support.FPUtil.fp_bits ) @@ -183,7 +178,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.truncl libc.src.__support.FPUtil.fp_bits ) @@ -198,7 +192,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceil libc.src.__support.FPUtil.fp_bits ) @@ -213,7 +206,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceilf libc.src.__support.FPUtil.fp_bits ) @@ -228,7 +220,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceill libc.src.__support.FPUtil.fp_bits ) @@ -243,7 +234,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floor libc.src.__support.FPUtil.fp_bits ) @@ -258,7 +248,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floorf libc.src.__support.FPUtil.fp_bits ) @@ -273,7 +262,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floorl libc.src.__support.FPUtil.fp_bits ) @@ -288,7 +276,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.round libc.src.__support.FPUtil.fp_bits ) @@ -303,7 +290,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.roundf libc.src.__support.FPUtil.fp_bits ) @@ -318,7 +304,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.roundl libc.src.__support.FPUtil.fp_bits ) @@ -333,7 +318,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundeven libc.src.__support.FPUtil.fp_bits ) @@ -348,7 +332,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundevenf libc.src.__support.FPUtil.fp_bits ) @@ -363,7 +346,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundevenl libc.src.__support.FPUtil.fp_bits ) @@ -378,7 +360,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -397,7 +378,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -416,7 +396,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -435,7 +414,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -454,7 +432,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -473,7 +450,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -492,7 +468,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rint libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -508,7 +483,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rintf libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -524,7 +498,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rintl libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -540,7 +513,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrint libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -556,7 +528,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrintf libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -572,7 +543,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrintl libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -588,7 +558,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrint libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -604,7 +573,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrintf libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -620,7 +588,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrintl libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -635,7 +602,6 @@ add_fp_unittest( expf_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.expf libc.src.__support.FPUtil.fp_bits ) @@ -649,7 +615,6 @@ add_fp_unittest( exp_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp libc.src.__support.FPUtil.fp_bits ) @@ -663,7 +628,6 @@ add_fp_unittest( exp2f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp2f libc.src.__support.FPUtil.fp_bits ) @@ -677,7 +641,6 @@ add_fp_unittest( exp2_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp2 libc.src.__support.FPUtil.fp_bits ) @@ -690,7 +653,6 @@ add_fp_unittest( SRCS exp2m1f_test.cpp DEPENDS - libc.include.llvm-libc-macros.math_macros libc.src.errno.errno libc.src.math.exp2m1f libc.src.__support.CPP.array @@ -706,7 +668,6 @@ add_fp_unittest( exp10f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp10f libc.src.__support.FPUtil.fp_bits ) @@ -720,7 +681,6 @@ add_fp_unittest( exp10_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp10 libc.src.__support.FPUtil.fp_bits ) @@ -734,7 +694,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysign libc.src.__support.FPUtil.fp_bits # FIXME: Currently fails on the GPU build. @@ -750,7 +709,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysignf libc.src.__support.FPUtil.fp_bits # FIXME: Currently fails on the GPU build. @@ -766,7 +724,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysignl libc.src.__support.FPUtil.fp_bits # FIXME: Currently fails on the GPU build. @@ -783,7 +740,6 @@ add_fp_unittest( HDRS FrexpTest.h DEPENDS - libc.include.math libc.src.math.frexp libc.src.__support.FPUtil.basic_operations ) @@ -798,7 +754,6 @@ add_fp_unittest( HDRS FrexpTest.h DEPENDS - libc.include.math libc.src.math.frexpf libc.src.__support.FPUtil.basic_operations ) @@ -813,7 +768,6 @@ add_fp_unittest( HDRS FrexpTest.h DEPENDS - libc.include.math libc.src.math.frexpl libc.src.__support.FPUtil.basic_operations ) @@ -827,7 +781,6 @@ add_fp_unittest( HDRS ILogbTest.h DEPENDS - libc.include.math libc.src.math.ilogb libc.src.__support.CPP.limits libc.src.__support.FPUtil.fp_bits @@ -843,7 +796,6 @@ add_fp_unittest( HDRS ILogbTest.h DEPENDS - libc.include.math libc.src.math.ilogbf libc.src.__support.CPP.limits libc.src.__support.FPUtil.fp_bits @@ -859,7 +811,6 @@ add_fp_unittest( HDRS ILogbTest.h DEPENDS - libc.include.math libc.src.math.ilogbl libc.src.__support.CPP.limits libc.src.__support.FPUtil.fp_bits @@ -875,7 +826,6 @@ add_fp_unittest( HDRS LdExpTest.h DEPENDS - libc.include.math libc.src.math.ldexp libc.src.__support.CPP.limits libc.src.__support.FPUtil.fp_bits @@ -891,7 +841,6 @@ add_fp_unittest( HDRS LdExpTest.h DEPENDS - libc.include.math libc.src.math.ldexpf libc.src.__support.CPP.limits libc.src.__support.FPUtil.fp_bits @@ -907,7 +856,6 @@ add_fp_unittest( HDRS LdExpTest.h DEPENDS - libc.include.math libc.src.math.ldexpl libc.src.__support.CPP.limits libc.src.__support.FPUtil.fp_bits @@ -921,7 +869,6 @@ add_fp_unittest( SRCS logb_test.cpp DEPENDS - libc.include.math libc.src.math.logb libc.src.__support.FPUtil.manipulation_functions ) @@ -933,7 +880,6 @@ add_fp_unittest( SRCS logbf_test.cpp DEPENDS - libc.include.math libc.src.math.logbf libc.src.__support.FPUtil.manipulation_functions ) @@ -947,7 +893,6 @@ add_fp_unittest( HDRS LogbTest.h DEPENDS - libc.include.math libc.src.math.logbl libc.src.__support.FPUtil.manipulation_functions ) @@ -961,7 +906,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modf libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -978,7 +922,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modff libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -995,7 +938,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modfl libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -1010,7 +952,6 @@ add_fp_unittest( HDRS FDimTest.h DEPENDS - libc.include.math libc.src.math.fdimf libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1025,7 +966,6 @@ add_fp_unittest( HDRS FDimTest.h DEPENDS - libc.include.math libc.src.math.fdim libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1040,7 +980,6 @@ add_fp_unittest( HDRS FDimTest.h DEPENDS - libc.include.math libc.src.math.fdiml libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1055,7 +994,6 @@ add_fp_unittest( HDRS FMinTest.h DEPENDS - libc.include.math libc.src.math.fminf libc.src.__support.FPUtil.fp_bits ) @@ -1069,7 +1007,6 @@ add_fp_unittest( HDRS FMinTest.h DEPENDS - libc.include.math libc.src.math.fmin libc.src.__support.FPUtil.fp_bits ) @@ -1083,7 +1020,6 @@ add_fp_unittest( HDRS FMinTest.h DEPENDS - libc.include.math libc.src.math.fminl libc.src.__support.FPUtil.fp_bits ) @@ -1097,7 +1033,6 @@ add_fp_unittest( HDRS FMaxTest.h DEPENDS - libc.include.math libc.src.math.fmaxf libc.src.__support.FPUtil.fp_bits ) @@ -1111,7 +1046,6 @@ add_fp_unittest( HDRS FMaxTest.h DEPENDS - libc.include.math libc.src.math.fmax libc.src.__support.FPUtil.fp_bits ) @@ -1125,7 +1059,6 @@ add_fp_unittest( HDRS FMaxTest.h DEPENDS - libc.include.math libc.src.math.fmaxl libc.src.__support.FPUtil.fp_bits ) @@ -1138,7 +1071,6 @@ add_fp_unittest( SRCS sqrtf_test.cpp DEPENDS - libc.include.math libc.src.math.sqrtf libc.src.__support.FPUtil.fp_bits ) @@ -1151,7 +1083,6 @@ add_fp_unittest( SRCS sqrt_test.cpp DEPENDS - libc.include.math libc.src.math.sqrt libc.src.__support.FPUtil.fp_bits ) @@ -1164,7 +1095,6 @@ add_fp_unittest( SRCS sqrtl_test.cpp DEPENDS - libc.include.math libc.src.math.sqrtl libc.src.__support.FPUtil.fp_bits ) @@ -1224,7 +1154,6 @@ add_fp_unittest( HDRS RemQuoTest.h DEPENDS - libc.include.math libc.src.math.remquof libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1240,7 +1169,6 @@ add_fp_unittest( HDRS RemQuoTest.h DEPENDS - libc.include.math libc.src.math.remquo libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1256,7 +1184,6 @@ add_fp_unittest( HDRS RemQuoTest.h DEPENDS - libc.include.math libc.src.math.remquol libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1270,7 +1197,6 @@ add_fp_unittest( SRCS hypotf_test.cpp DEPENDS - libc.include.math libc.src.math.hypotf libc.src.__support.FPUtil.fp_bits ) @@ -1283,7 +1209,6 @@ add_fp_unittest( SRCS hypot_test.cpp DEPENDS - libc.include.math libc.src.math.hypot libc.src.__support.FPUtil.fp_bits ) @@ -1297,7 +1222,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafter libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1312,7 +1236,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafterf libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1327,7 +1250,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafterl libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1342,7 +1264,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafterf128 libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -1358,7 +1279,6 @@ add_fp_unittest( SRCS fmaf_test.cpp DEPENDS - libc.include.math libc.src.math.fmaf libc.src.__support.FPUtil.fp_bits FLAGS @@ -1373,7 +1293,6 @@ add_fp_unittest( SRCS fma_test.cpp DEPENDS - libc.include.math libc.src.math.fma libc.src.__support.FPUtil.fp_bits ) @@ -1399,7 +1318,6 @@ add_fp_unittest( expm1f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.expm1f libc.src.__support.FPUtil.fp_bits ) @@ -1413,7 +1331,6 @@ add_fp_unittest( expm1_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.expm1 libc.src.__support.FPUtil.fp_bits ) @@ -1427,7 +1344,6 @@ add_fp_unittest( log_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log libc.src.__support.FPUtil.fp_bits ) @@ -1441,7 +1357,6 @@ add_fp_unittest( logf_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.logf libc.src.__support.FPUtil.fp_bits ) @@ -1455,7 +1370,6 @@ log2_test log2_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log2 libc.src.__support.FPUtil.fp_bits ) @@ -1469,7 +1383,6 @@ add_fp_unittest( log2f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log2f libc.src.__support.FPUtil.fp_bits ) @@ -1483,7 +1396,6 @@ add_fp_unittest( log10_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log10 libc.src.__support.FPUtil.fp_bits ) @@ -1497,7 +1409,6 @@ add_fp_unittest( log10f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log10f libc.src.__support.FPUtil.fp_bits ) @@ -1511,7 +1422,6 @@ log1p_test log1p_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log1p libc.src.__support.FPUtil.fp_bits ) @@ -1525,7 +1435,6 @@ add_fp_unittest( log1pf_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log1pf libc.src.__support.FPUtil.fp_bits ) @@ -1539,7 +1448,6 @@ add_fp_unittest( HDRS FModTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.math.fmodf libc.src.__support.FPUtil.basic_operations @@ -1557,7 +1465,6 @@ add_fp_unittest( HDRS FModTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.math.fmod libc.src.__support.FPUtil.basic_operations @@ -1576,7 +1483,6 @@ add_fp_unittest( SRCS explogxf_test.cpp DEPENDS - libc.include.math libc.src.math.generic.explogxf libc.src.math.fabs libc.src.math.fabsf @@ -1715,7 +1621,6 @@ add_fp_unittest( HDRS ScalbnTest.h DEPENDS - libc.include.math libc.src.math.scalbn libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.normal_float @@ -1731,7 +1636,6 @@ add_fp_unittest( HDRS ScalbnTest.h DEPENDS - libc.include.math libc.src.math.scalbnf libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.normal_float @@ -1747,7 +1651,6 @@ add_fp_unittest( HDRS ScalbnTest.h DEPENDS - libc.include.math libc.src.math.scalbnl libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.normal_float @@ -1761,7 +1664,6 @@ add_fp_unittest( SRCS erff_test.cpp DEPENDS - libc.include.math libc.src.math.erff libc.src.__support.FPUtil.fp_bits ) @@ -1774,7 +1676,6 @@ add_fp_unittest( SRCS powf_test.cpp DEPENDS - libc.include.math libc.src.math.powf libc.src.__support.FPUtil.fp_bits ) @@ -1787,7 +1688,6 @@ add_fp_unittest( SRCS atan2f_test.cpp DEPENDS - libc.include.math libc.src.math.atan2f libc.src.__support.FPUtil.fp_bits ) diff --git a/libc/test/src/math/CeilTest.h b/libc/test/src/math/CeilTest.h index 74cc90614dfc..da3f3c0e8f5a 100644 --- a/libc/test/src/math/CeilTest.h +++ b/libc/test/src/math/CeilTest.h @@ -10,7 +10,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/CopySignTest.h b/libc/test/src/math/CopySignTest.h index 206626d66f58..052ff0333438 100644 --- a/libc/test/src/math/CopySignTest.h +++ b/libc/test/src/math/CopySignTest.h @@ -10,7 +10,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/FAbsTest.h b/libc/test/src/math/FAbsTest.h index 942991f23be1..23ad8a26c481 100644 --- a/libc/test/src/math/FAbsTest.h +++ b/libc/test/src/math/FAbsTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/FDimTest.h b/libc/test/src/math/FDimTest.h index df8de91b4298..44aba9caf646 100644 --- a/libc/test/src/math/FDimTest.h +++ b/libc/test/src/math/FDimTest.h @@ -6,7 +6,7 @@ // //===---------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/FMaxTest.h b/libc/test/src/math/FMaxTest.h index 2c7dc3dc13ec..e9857f332e65 100644 --- a/libc/test/src/math/FMaxTest.h +++ b/libc/test/src/math/FMaxTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/FMinTest.h b/libc/test/src/math/FMinTest.h index a986d5240d0d..c6b9f4439b79 100644 --- a/libc/test/src/math/FMinTest.h +++ b/libc/test/src/math/FMinTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/FModTest.h b/libc/test/src/math/FModTest.h index 96ad299258a1..bc909987a161 100644 --- a/libc/test/src/math/FModTest.h +++ b/libc/test/src/math/FModTest.h @@ -14,7 +14,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #define TEST_SPECIAL(x, y, expected, dom_err, expected_exception) \ EXPECT_FP_EQ(expected, f(x, y)); \ diff --git a/libc/test/src/math/FloorTest.h b/libc/test/src/math/FloorTest.h index 21ae291e61bc..679dc26e1248 100644 --- a/libc/test/src/math/FloorTest.h +++ b/libc/test/src/math/FloorTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/FrexpTest.h b/libc/test/src/math/FrexpTest.h index f971b45628f0..5f993f604999 100644 --- a/libc/test/src/math/FrexpTest.h +++ b/libc/test/src/math/FrexpTest.h @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/HypotTest.h b/libc/test/src/math/HypotTest.h index df69965d5dbc..0c15f02fe371 100644 --- a/libc/test/src/math/HypotTest.h +++ b/libc/test/src/math/HypotTest.h @@ -14,7 +14,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/ILogbTest.h b/libc/test/src/math/ILogbTest.h index ad47b9bb3961..3d1f047a4806 100644 --- a/libc/test/src/math/ILogbTest.h +++ b/libc/test/src/math/ILogbTest.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_ILOGBTEST_H #define LLVM_LIBC_TEST_SRC_MATH_ILOGBTEST_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/limits.h" // INT_MAX #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" diff --git a/libc/test/src/math/LdExpTest.h b/libc/test/src/math/LdExpTest.h index 8bfd022973b4..2a406feed52f 100644 --- a/libc/test/src/math/LdExpTest.h +++ b/libc/test/src/math/LdExpTest.h @@ -15,7 +15,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include template diff --git a/libc/test/src/math/LogbTest.h b/libc/test/src/math/LogbTest.h index 3859b56582e5..f066d5f9de02 100644 --- a/libc/test/src/math/LogbTest.h +++ b/libc/test/src/math/LogbTest.h @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/ModfTest.h b/libc/test/src/math/ModfTest.h index 84e26db49695..49b0328753b3 100644 --- a/libc/test/src/math/ModfTest.h +++ b/libc/test/src/math/ModfTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/NextAfterTest.h b/libc/test/src/math/NextAfterTest.h index 05803fb45ee2..a7248dd7042d 100644 --- a/libc/test/src/math/NextAfterTest.h +++ b/libc/test/src/math/NextAfterTest.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_NEXTAFTERTEST_H #define LLVM_LIBC_TEST_SRC_MATH_NEXTAFTERTEST_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/BasicOperations.h" diff --git a/libc/test/src/math/RIntTest.h b/libc/test/src/math/RIntTest.h index 301655c64ed3..5be34bece54b 100644 --- a/libc/test/src/math/RIntTest.h +++ b/libc/test/src/math/RIntTest.h @@ -15,7 +15,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include #include diff --git a/libc/test/src/math/RemQuoTest.h b/libc/test/src/math/RemQuoTest.h index 1cb8cdbe81a2..677772dd9fcc 100644 --- a/libc/test/src/math/RemQuoTest.h +++ b/libc/test/src/math/RemQuoTest.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_REMQUOTEST_H #define LLVM_LIBC_TEST_SRC_MATH_REMQUOTEST_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/RoundEvenTest.h b/libc/test/src/math/RoundEvenTest.h index db7263a39c0f..68b8b9ae1d96 100644 --- a/libc/test/src/math/RoundEvenTest.h +++ b/libc/test/src/math/RoundEvenTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/RoundTest.h b/libc/test/src/math/RoundTest.h index 17da00f869d3..eecf95982729 100644 --- a/libc/test/src/math/RoundTest.h +++ b/libc/test/src/math/RoundTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/RoundToIntegerTest.h b/libc/test/src/math/RoundToIntegerTest.h index d2fabd0b4c9c..7c93451235f2 100644 --- a/libc/test/src/math/RoundToIntegerTest.h +++ b/libc/test/src/math/RoundToIntegerTest.h @@ -15,7 +15,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/SqrtTest.h b/libc/test/src/math/SqrtTest.h index 9811b2767ee3..799b7862a372 100644 --- a/libc/test/src/math/SqrtTest.h +++ b/libc/test/src/math/SqrtTest.h @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/TruncTest.h b/libc/test/src/math/TruncTest.h index c3a89dbb837b..57c953fad874 100644 --- a/libc/test/src/math/TruncTest.h +++ b/libc/test/src/math/TruncTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/acosf_test.cpp b/libc/test/src/math/acosf_test.cpp index 6f8321bd7182..0d25a808e0bf 100644 --- a/libc/test/src/math/acosf_test.cpp +++ b/libc/test/src/math/acosf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/acosf.h" diff --git a/libc/test/src/math/acoshf_test.cpp b/libc/test/src/math/acoshf_test.cpp index 41d1166fb430..32761e25b5ce 100644 --- a/libc/test/src/math/acoshf_test.cpp +++ b/libc/test/src/math/acoshf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/acoshf.h" diff --git a/libc/test/src/math/asinf_test.cpp b/libc/test/src/math/asinf_test.cpp index 4e36f03f4895..91e61085e91b 100644 --- a/libc/test/src/math/asinf_test.cpp +++ b/libc/test/src/math/asinf_test.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/asinf.h" diff --git a/libc/test/src/math/asinhf_test.cpp b/libc/test/src/math/asinhf_test.cpp index 9a3bfbed1068..b19e26efd07b 100644 --- a/libc/test/src/math/asinhf_test.cpp +++ b/libc/test/src/math/asinhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/asinhf.h" diff --git a/libc/test/src/math/atan2f_test.cpp b/libc/test/src/math/atan2f_test.cpp index 343e7601b039..1242b7e66528 100644 --- a/libc/test/src/math/atan2f_test.cpp +++ b/libc/test/src/math/atan2f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/atan2f.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/atanf_test.cpp b/libc/test/src/math/atanf_test.cpp index 58b0eadd63f8..4fa7badaf736 100644 --- a/libc/test/src/math/atanf_test.cpp +++ b/libc/test/src/math/atanf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/atanf.h" diff --git a/libc/test/src/math/atanhf_test.cpp b/libc/test/src/math/atanhf_test.cpp index c659f17d13b0..7fc8c70d1386 100644 --- a/libc/test/src/math/atanhf_test.cpp +++ b/libc/test/src/math/atanhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/atanhf.h" diff --git a/libc/test/src/math/cos_test.cpp b/libc/test/src/math/cos_test.cpp index 6a1122997c51..9a39616ed16f 100644 --- a/libc/test/src/math/cos_test.cpp +++ b/libc/test/src/math/cos_test.cpp @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" using LlvmLibcCosTest = LIBC_NAMESPACE::testing::FPTest; diff --git a/libc/test/src/math/cosf_test.cpp b/libc/test/src/math/cosf_test.cpp index 8a5eb17fdcea..dab35fa1a9fe 100644 --- a/libc/test/src/math/cosf_test.cpp +++ b/libc/test/src/math/cosf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/cosf.h" diff --git a/libc/test/src/math/coshf_test.cpp b/libc/test/src/math/coshf_test.cpp index 8792f56b0346..7c5d6630e109 100644 --- a/libc/test/src/math/coshf_test.cpp +++ b/libc/test/src/math/coshf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/array.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/erff_test.cpp b/libc/test/src/math/erff_test.cpp index 1e43c206aef0..5c848d7d5bf7 100644 --- a/libc/test/src/math/erff_test.cpp +++ b/libc/test/src/math/erff_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/erff.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/exhaustive/CMakeLists.txt b/libc/test/src/math/exhaustive/CMakeLists.txt index 6b2f3dddcadd..938e519aff08 100644 --- a/libc/test/src/math/exhaustive/CMakeLists.txt +++ b/libc/test/src/math/exhaustive/CMakeLists.txt @@ -16,7 +16,6 @@ add_fp_unittest( sqrtf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.sqrtf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -33,7 +32,6 @@ add_fp_unittest( sinf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.sinf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -50,7 +48,6 @@ add_fp_unittest( cosf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.cosf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -67,7 +64,6 @@ add_fp_unittest( sincosf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.sincosf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -84,7 +80,6 @@ add_fp_unittest( tanf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.tanf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -101,7 +96,6 @@ add_fp_unittest( erff_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.erff libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -118,7 +112,6 @@ add_fp_unittest( expf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.expf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -135,7 +128,6 @@ add_fp_unittest( exp2f_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.exp2f libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -167,7 +159,6 @@ add_fp_unittest( exp10f_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.exp10f libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -184,7 +175,6 @@ add_fp_unittest( expm1f_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.expm1f libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -201,7 +191,6 @@ add_fp_unittest( logf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.logf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -218,7 +207,6 @@ add_fp_unittest( log10f_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.log10f libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -235,7 +223,6 @@ add_fp_unittest( log1pf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.log1pf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -252,7 +239,6 @@ add_fp_unittest( log2f_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.log2f libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -271,7 +257,6 @@ add_fp_unittest( -O3 DEPENDS .exhaustive_test - libc.include.math libc.src.math.hypotf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -302,7 +287,6 @@ add_fp_unittest( coshf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.coshf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -319,7 +303,6 @@ add_fp_unittest( sinhf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.sinhf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -336,7 +319,6 @@ add_fp_unittest( tanhf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.tanhf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -353,7 +335,6 @@ add_fp_unittest( acoshf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.acoshf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -370,7 +351,6 @@ add_fp_unittest( asinhf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.asinhf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -387,7 +367,6 @@ add_fp_unittest( atanhf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.atanhf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -404,7 +383,6 @@ add_fp_unittest( atanf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.atanf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -421,7 +399,6 @@ add_fp_unittest( asinf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.asinf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES @@ -438,7 +415,6 @@ add_fp_unittest( acosf_test.cpp DEPENDS .exhaustive_test - libc.include.math libc.src.math.acosf libc.src.__support.FPUtil.fp_bits LINK_LIBRARIES diff --git a/libc/test/src/math/exp10_test.cpp b/libc/test/src/math/exp10_test.cpp index 778189626a61..4cbdd169d803 100644 --- a/libc/test/src/math/exp10_test.cpp +++ b/libc/test/src/math/exp10_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp10.h" diff --git a/libc/test/src/math/exp10f_test.cpp b/libc/test/src/math/exp10f_test.cpp index 9d44e8f65dec..e9b278668104 100644 --- a/libc/test/src/math/exp10f_test.cpp +++ b/libc/test/src/math/exp10f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp10f.h" diff --git a/libc/test/src/math/exp2_test.cpp b/libc/test/src/math/exp2_test.cpp index 845fda5451d4..73232ed36077 100644 --- a/libc/test/src/math/exp2_test.cpp +++ b/libc/test/src/math/exp2_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp2.h" diff --git a/libc/test/src/math/exp2f_test.cpp b/libc/test/src/math/exp2f_test.cpp index f63f091eab9a..8ff0ce6a6e72 100644 --- a/libc/test/src/math/exp2f_test.cpp +++ b/libc/test/src/math/exp2f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/exp2m1f_test.cpp b/libc/test/src/math/exp2m1f_test.cpp index a0f0da868117..cb948289b617 100644 --- a/libc/test/src/math/exp2m1f_test.cpp +++ b/libc/test/src/math/exp2m1f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/array.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/exp_test.cpp b/libc/test/src/math/exp_test.cpp index 42018e608ae4..64d8198e64f2 100644 --- a/libc/test/src/math/exp_test.cpp +++ b/libc/test/src/math/exp_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp.h" diff --git a/libc/test/src/math/expf_test.cpp b/libc/test/src/math/expf_test.cpp index 634958bdc43e..1dce381918eb 100644 --- a/libc/test/src/math/expf_test.cpp +++ b/libc/test/src/math/expf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/expf.h" diff --git a/libc/test/src/math/explogxf_test.cpp b/libc/test/src/math/explogxf_test.cpp index a536a9f3ab8d..bcca87f590d7 100644 --- a/libc/test/src/math/explogxf_test.cpp +++ b/libc/test/src/math/explogxf_test.cpp @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// +#include "hdr/math_macros.h" #include "in_float_range_test_helper.h" -#include "include/llvm-libc-macros/math-macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/fabs.h" #include "src/math/fabsf.h" diff --git a/libc/test/src/math/expm1_test.cpp b/libc/test/src/math/expm1_test.cpp index 198e6d5cdd8a..1bf07f19f3a7 100644 --- a/libc/test/src/math/expm1_test.cpp +++ b/libc/test/src/math/expm1_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/expm1.h" diff --git a/libc/test/src/math/expm1f_test.cpp b/libc/test/src/math/expm1f_test.cpp index c72815887ba8..515f988b6264 100644 --- a/libc/test/src/math/expm1f_test.cpp +++ b/libc/test/src/math/expm1f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/expm1f.h" diff --git a/libc/test/src/math/fdim_test.cpp b/libc/test/src/math/fdim_test.cpp index 6c0c3e204c5f..1e8adf036dde 100644 --- a/libc/test/src/math/fdim_test.cpp +++ b/libc/test/src/math/fdim_test.cpp @@ -8,7 +8,7 @@ #include "FDimTest.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/fdim.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/fdimf_test.cpp b/libc/test/src/math/fdimf_test.cpp index a74011b5a224..13e61d9082da 100644 --- a/libc/test/src/math/fdimf_test.cpp +++ b/libc/test/src/math/fdimf_test.cpp @@ -8,7 +8,7 @@ #include "FDimTest.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/fdimf.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/fdiml_test.cpp b/libc/test/src/math/fdiml_test.cpp index d3f2e68a7c1d..2d99d2134c1c 100644 --- a/libc/test/src/math/fdiml_test.cpp +++ b/libc/test/src/math/fdiml_test.cpp @@ -8,7 +8,7 @@ #include "FDimTest.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/fdiml.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/generic/CMakeLists.txt b/libc/test/src/math/generic/CMakeLists.txt index bc2b5cea89d1..1fe7801941d5 100644 --- a/libc/test/src/math/generic/CMakeLists.txt +++ b/libc/test/src/math/generic/CMakeLists.txt @@ -6,7 +6,6 @@ add_fp_unittest( SRCS ../ceil_test.cpp DEPENDS - libc.include.math libc.src.math.generic.ceil ) @@ -18,7 +17,6 @@ add_fp_unittest( SRCS ../ceilf_test.cpp DEPENDS - libc.include.math libc.src.math.generic.ceilf ) @@ -30,7 +28,6 @@ add_fp_unittest( SRCS ../ceill_test.cpp DEPENDS - libc.include.math libc.src.math.generic.ceill ) diff --git a/libc/test/src/math/ilogb_test.cpp b/libc/test/src/math/ilogb_test.cpp index 45756ffa3d9a..c8daf2e0adaf 100644 --- a/libc/test/src/math/ilogb_test.cpp +++ b/libc/test/src/math/ilogb_test.cpp @@ -8,7 +8,7 @@ #include "ILogbTest.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" #include "src/math/ilogb.h" diff --git a/libc/test/src/math/ilogbf_test.cpp b/libc/test/src/math/ilogbf_test.cpp index ff19dd145a19..87a2789f6c11 100644 --- a/libc/test/src/math/ilogbf_test.cpp +++ b/libc/test/src/math/ilogbf_test.cpp @@ -8,7 +8,7 @@ #include "ILogbTest.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" #include "src/math/ilogbf.h" diff --git a/libc/test/src/math/ilogbl_test.cpp b/libc/test/src/math/ilogbl_test.cpp index b2c524666994..042a803b024a 100644 --- a/libc/test/src/math/ilogbl_test.cpp +++ b/libc/test/src/math/ilogbl_test.cpp @@ -8,7 +8,7 @@ #include "ILogbTest.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" #include "src/math/ilogbl.h" diff --git a/libc/test/src/math/log10_test.cpp b/libc/test/src/math/log10_test.cpp index dc4ac895546c..fd9a615ca87f 100644 --- a/libc/test/src/math/log10_test.cpp +++ b/libc/test/src/math/log10_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log10.h" diff --git a/libc/test/src/math/log10f_test.cpp b/libc/test/src/math/log10f_test.cpp index f8a137e44c35..4ba118455df4 100644 --- a/libc/test/src/math/log10f_test.cpp +++ b/libc/test/src/math/log10f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/log10f.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/log1p_test.cpp b/libc/test/src/math/log1p_test.cpp index 975fb8e05c35..5e461c91518b 100644 --- a/libc/test/src/math/log1p_test.cpp +++ b/libc/test/src/math/log1p_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log1p.h" diff --git a/libc/test/src/math/log1pf_test.cpp b/libc/test/src/math/log1pf_test.cpp index a1108fee4819..db0772d3c8b8 100644 --- a/libc/test/src/math/log1pf_test.cpp +++ b/libc/test/src/math/log1pf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log1pf.h" diff --git a/libc/test/src/math/log2_test.cpp b/libc/test/src/math/log2_test.cpp index 876527900579..9992c1340e99 100644 --- a/libc/test/src/math/log2_test.cpp +++ b/libc/test/src/math/log2_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log2.h" diff --git a/libc/test/src/math/log2f_test.cpp b/libc/test/src/math/log2f_test.cpp index c05b6b93cff7..24b51adac94d 100644 --- a/libc/test/src/math/log2f_test.cpp +++ b/libc/test/src/math/log2f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log2f.h" diff --git a/libc/test/src/math/log_test.cpp b/libc/test/src/math/log_test.cpp index 06a0dc574be5..de1e59579419 100644 --- a/libc/test/src/math/log_test.cpp +++ b/libc/test/src/math/log_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log.h" diff --git a/libc/test/src/math/logf_test.cpp b/libc/test/src/math/logf_test.cpp index 1ab480744ba5..28a171d54066 100644 --- a/libc/test/src/math/logf_test.cpp +++ b/libc/test/src/math/logf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/logf.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/powf_test.cpp b/libc/test/src/math/powf_test.cpp index cf674ecf8f99..69135593cd32 100644 --- a/libc/test/src/math/powf_test.cpp +++ b/libc/test/src/math/powf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/powf.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/sin_test.cpp b/libc/test/src/math/sin_test.cpp index fa1c5370c30f..0171b79810d4 100644 --- a/libc/test/src/math/sin_test.cpp +++ b/libc/test/src/math/sin_test.cpp @@ -12,7 +12,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" using LlvmLibcSinTest = LIBC_NAMESPACE::testing::FPTest; diff --git a/libc/test/src/math/sincosf_test.cpp b/libc/test/src/math/sincosf_test.cpp index a7372fd53b31..7c359b345f4c 100644 --- a/libc/test/src/math/sincosf_test.cpp +++ b/libc/test/src/math/sincosf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/sincosf.h" diff --git a/libc/test/src/math/sinf_test.cpp b/libc/test/src/math/sinf_test.cpp index a3c5384e3e62..6a8f8f4ee428 100644 --- a/libc/test/src/math/sinf_test.cpp +++ b/libc/test/src/math/sinf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/sinf.h" diff --git a/libc/test/src/math/sinhf_test.cpp b/libc/test/src/math/sinhf_test.cpp index bea976055dbd..cc0552f72894 100644 --- a/libc/test/src/math/sinhf_test.cpp +++ b/libc/test/src/math/sinhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/array.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/smoke/CMakeLists.txt b/libc/test/src/math/smoke/CMakeLists.txt index e9ff35577b95..22c59c97f6c7 100644 --- a/libc/test/src/math/smoke/CMakeLists.txt +++ b/libc/test/src/math/smoke/CMakeLists.txt @@ -62,7 +62,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabs libc.src.__support.FPUtil.fp_bits ) @@ -76,7 +75,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabsf libc.src.__support.FPUtil.fp_bits ) @@ -90,7 +88,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabsl libc.src.__support.FPUtil.fp_bits ) @@ -104,7 +101,6 @@ add_fp_unittest( HDRS FAbsTest.h DEPENDS - libc.include.math libc.src.math.fabsf128 libc.src.__support.FPUtil.fp_bits ) @@ -118,7 +114,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.trunc libc.src.__support.FPUtil.fp_bits ) @@ -132,7 +127,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.truncf libc.src.__support.FPUtil.fp_bits ) @@ -146,7 +140,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.truncl libc.src.__support.FPUtil.fp_bits ) @@ -160,7 +153,6 @@ add_fp_unittest( HDRS TruncTest.h DEPENDS - libc.include.math libc.src.math.truncf128 libc.src.__support.FPUtil.fp_bits ) @@ -174,7 +166,6 @@ add_fp_unittest( HDRS CanonicalizeTest.h DEPENDS - libc.include.math libc.src.math.canonicalize libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.fenv_impl @@ -190,7 +181,6 @@ add_fp_unittest( HDRS CanonicalizeTest.h DEPENDS - libc.include.math libc.src.math.canonicalizef libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.fenv_impl @@ -206,7 +196,6 @@ add_fp_unittest( HDRS CanonicalizeTest.h DEPENDS - libc.include.math libc.src.math.canonicalizef128 libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.fenv_impl @@ -222,7 +211,6 @@ add_fp_unittest( HDRS CanonicalizeTest.h DEPENDS - libc.include.math libc.src.math.canonicalizel libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.fenv_impl @@ -238,7 +226,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceil libc.src.__support.FPUtil.fp_bits ) @@ -252,7 +239,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceilf libc.src.__support.FPUtil.fp_bits ) @@ -266,7 +252,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceill libc.src.__support.FPUtil.fp_bits ) @@ -280,7 +265,6 @@ add_fp_unittest( HDRS CeilTest.h DEPENDS - libc.include.math libc.src.math.ceilf128 libc.src.__support.FPUtil.fp_bits ) @@ -294,7 +278,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floor libc.src.__support.FPUtil.fp_bits ) @@ -308,7 +291,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floorf libc.src.__support.FPUtil.fp_bits ) @@ -322,7 +304,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floorl libc.src.__support.FPUtil.fp_bits ) @@ -336,7 +317,6 @@ add_fp_unittest( HDRS FloorTest.h DEPENDS - libc.include.math libc.src.math.floorf128 libc.src.__support.FPUtil.fp_bits ) @@ -350,7 +330,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.round libc.src.__support.FPUtil.fp_bits ) @@ -364,7 +343,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.roundf libc.src.__support.FPUtil.fp_bits ) @@ -378,7 +356,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.roundl libc.src.__support.FPUtil.fp_bits ) @@ -392,7 +369,6 @@ add_fp_unittest( HDRS RoundTest.h DEPENDS - libc.include.math libc.src.math.roundf128 libc.src.__support.FPUtil.fp_bits ) @@ -406,7 +382,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundeven libc.src.__support.FPUtil.fp_bits ) @@ -420,7 +395,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundevenf libc.src.__support.FPUtil.fp_bits ) @@ -434,7 +408,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundevenl libc.src.__support.FPUtil.fp_bits ) @@ -448,7 +421,6 @@ add_fp_unittest( HDRS RoundEvenTest.h DEPENDS - libc.include.math libc.src.math.roundevenf128 libc.src.__support.FPUtil.fp_bits ) @@ -462,7 +434,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -480,7 +451,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -498,7 +468,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -516,7 +485,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -534,7 +502,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -552,7 +519,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -570,7 +536,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -588,7 +553,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.fenv.feclearexcept libc.src.fenv.feraiseexcept @@ -606,7 +570,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rint libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -621,7 +584,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rintf libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -636,7 +598,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rintl libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -651,7 +612,6 @@ add_fp_unittest( HDRS RIntTest.h DEPENDS - libc.include.math libc.src.math.rintf128 libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -666,7 +626,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrint libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -681,7 +640,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrintf libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -696,7 +654,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrintl libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -711,7 +668,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.lrintf128 libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -726,7 +682,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrint libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -741,7 +696,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrintf libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -756,7 +710,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrintl libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -771,7 +724,6 @@ add_fp_unittest( HDRS RoundToIntegerTest.h DEPENDS - libc.include.math libc.src.math.llrintf128 libc.src.__support.FPUtil.fenv_impl libc.src.__support.FPUtil.fp_bits @@ -785,7 +737,6 @@ add_fp_unittest( expf_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.expf libc.src.__support.FPUtil.fp_bits ) @@ -798,7 +749,6 @@ add_fp_unittest( exp_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp libc.src.__support.FPUtil.fp_bits ) @@ -811,7 +761,6 @@ add_fp_unittest( exp2f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp2f libc.src.__support.FPUtil.fp_bits ) @@ -824,7 +773,6 @@ add_fp_unittest( exp2_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp2 libc.src.__support.FPUtil.fp_bits ) @@ -848,7 +796,6 @@ add_fp_unittest( exp10f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp10f libc.src.__support.FPUtil.fp_bits ) @@ -861,7 +808,6 @@ add_fp_unittest( exp10_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.exp10 libc.src.__support.FPUtil.fp_bits ) @@ -875,7 +821,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysign libc.src.__support.FPUtil.fp_bits ) @@ -889,7 +834,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysignf libc.src.__support.FPUtil.fp_bits ) @@ -903,7 +847,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysignl libc.src.__support.FPUtil.fp_bits ) @@ -917,7 +860,6 @@ add_fp_unittest( HDRS CopySignTest.h DEPENDS - libc.include.math libc.src.math.copysignf128 libc.src.__support.FPUtil.fp_bits ) @@ -1397,7 +1339,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modf libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -1412,7 +1353,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modff libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -1427,7 +1367,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modfl libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -1442,7 +1381,6 @@ add_fp_unittest( HDRS ModfTest.h DEPENDS - libc.include.math libc.src.math.modff128 libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.nearest_integer_operations @@ -2033,7 +1971,6 @@ add_fp_unittest( SRCS sqrtf_test.cpp DEPENDS - libc.include.math libc.src.math.sqrtf libc.src.__support.FPUtil.fp_bits ) @@ -2045,7 +1982,6 @@ add_fp_unittest( SRCS sqrt_test.cpp DEPENDS - libc.include.math libc.src.math.sqrt libc.src.__support.FPUtil.fp_bits ) @@ -2057,7 +1993,6 @@ add_fp_unittest( SRCS sqrtl_test.cpp DEPENDS - libc.include.math libc.src.math.sqrtl libc.src.__support.FPUtil.fp_bits ) @@ -2069,7 +2004,6 @@ add_fp_unittest( SRCS sqrtf128_test.cpp DEPENDS - libc.include.math libc.src.math.sqrtf128 libc.src.__support.FPUtil.fp_bits ) @@ -2139,7 +2073,6 @@ add_fp_unittest( HDRS RemQuoTest.h DEPENDS - libc.include.math libc.src.math.remquof libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2154,7 +2087,6 @@ add_fp_unittest( HDRS RemQuoTest.h DEPENDS - libc.include.math libc.src.math.remquo libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2169,7 +2101,6 @@ add_fp_unittest( HDRS RemQuoTest.h DEPENDS - libc.include.math libc.src.math.remquol libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2182,7 +2113,6 @@ add_fp_unittest( SRCS hypotf_test.cpp DEPENDS - libc.include.math libc.src.math.hypotf libc.src.__support.FPUtil.fp_bits ) @@ -2194,7 +2124,6 @@ add_fp_unittest( SRCS hypot_test.cpp DEPENDS - libc.include.math libc.src.math.hypot libc.src.__support.FPUtil.fp_bits ) @@ -2206,7 +2135,6 @@ add_fp_unittest( SRCS nanf_test.cpp DEPENDS - libc.include.math libc.include.signal libc.src.math.nanf libc.src.__support.FPUtil.fp_bits @@ -2222,7 +2150,6 @@ add_fp_unittest( SRCS nan_test.cpp DEPENDS - libc.include.math libc.include.signal libc.src.math.nan libc.src.__support.FPUtil.fp_bits @@ -2238,7 +2165,6 @@ add_fp_unittest( SRCS nanl_test.cpp DEPENDS - libc.include.math libc.include.signal libc.src.math.nanl libc.src.__support.FPUtil.fp_bits @@ -2254,7 +2180,6 @@ add_fp_unittest( SRCS nanf128_test.cpp DEPENDS - libc.include.math libc.include.signal libc.src.math.nanf128 libc.src.__support.FPUtil.fp_bits @@ -2272,7 +2197,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafter libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2287,7 +2211,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafterf libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2302,7 +2225,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafterl libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2317,7 +2239,6 @@ add_fp_unittest( HDRS NextAfterTest.h DEPENDS - libc.include.math libc.src.math.nextafterf128 libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2334,7 +2255,6 @@ if(NOT LIBC_TARGET_OS_IS_GPU) HDRS NextTowardTest.h DEPENDS - libc.include.math libc.src.math.nexttoward libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2349,7 +2269,6 @@ if(NOT LIBC_TARGET_OS_IS_GPU) HDRS NextTowardTest.h DEPENDS - libc.include.math libc.src.math.nexttowardf libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2365,7 +2284,6 @@ add_fp_unittest( HDRS NextTowardTest.h DEPENDS - libc.include.math libc.src.math.nexttowardl libc.src.__support.FPUtil.basic_operations libc.src.__support.FPUtil.fp_bits @@ -2380,7 +2298,6 @@ add_fp_unittest( HDRS NextDownTest.h DEPENDS - libc.include.math libc.src.math.nextdown libc.src.__support.FPUtil.manipulation_functions ) @@ -2394,7 +2311,6 @@ add_fp_unittest( HDRS NextDownTest.h DEPENDS - libc.include.math libc.src.math.nextdownf libc.src.__support.FPUtil.manipulation_functions ) @@ -2408,7 +2324,6 @@ add_fp_unittest( HDRS NextDownTest.h DEPENDS - libc.include.math libc.src.math.nextdownl libc.src.__support.FPUtil.manipulation_functions ) @@ -2422,7 +2337,6 @@ add_fp_unittest( HDRS NextDownTest.h DEPENDS - libc.include.math libc.src.math.nextdownf128 libc.src.__support.FPUtil.manipulation_functions ) @@ -2436,7 +2350,6 @@ add_fp_unittest( HDRS NextUpTest.h DEPENDS - libc.include.math libc.src.math.nextup libc.src.__support.FPUtil.manipulation_functions ) @@ -2450,7 +2363,6 @@ add_fp_unittest( HDRS NextUpTest.h DEPENDS - libc.include.math libc.src.math.nextupf libc.src.__support.FPUtil.manipulation_functions ) @@ -2464,7 +2376,6 @@ add_fp_unittest( HDRS NextUpTest.h DEPENDS - libc.include.math libc.src.math.nextupl libc.src.__support.FPUtil.manipulation_functions ) @@ -2478,7 +2389,6 @@ add_fp_unittest( HDRS NextUpTest.h DEPENDS - libc.include.math libc.src.math.nextupf128 libc.src.__support.FPUtil.manipulation_functions ) @@ -2492,7 +2402,6 @@ add_fp_unittest( SRCS fmaf_test.cpp DEPENDS - libc.include.math libc.src.math.fmaf libc.src.__support.FPUtil.fp_bits FLAGS @@ -2506,7 +2415,6 @@ add_fp_unittest( SRCS fma_test.cpp DEPENDS - libc.include.math libc.src.math.fma libc.src.__support.FPUtil.fp_bits ) @@ -2519,7 +2427,6 @@ add_fp_unittest( expm1f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.expm1f libc.src.__support.FPUtil.fp_bits ) @@ -2532,7 +2439,6 @@ add_fp_unittest( expm1_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.expm1 libc.src.__support.FPUtil.fp_bits ) @@ -2545,7 +2451,6 @@ add_fp_unittest( log_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log libc.src.__support.FPUtil.fp_bits ) @@ -2558,7 +2463,6 @@ add_fp_unittest( logf_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.logf libc.src.__support.FPUtil.fp_bits ) @@ -2571,7 +2475,6 @@ add_fp_unittest( log2_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log2 libc.src.__support.FPUtil.fp_bits ) @@ -2584,7 +2487,6 @@ add_fp_unittest( log2f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log2f libc.src.__support.FPUtil.fp_bits ) @@ -2597,7 +2499,6 @@ add_fp_unittest( log10_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log10 libc.src.__support.FPUtil.fp_bits ) @@ -2610,7 +2511,6 @@ add_fp_unittest( log10f_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log10f libc.src.__support.FPUtil.fp_bits ) @@ -2623,7 +2523,6 @@ add_fp_unittest( log1p_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log1p libc.src.__support.FPUtil.fp_bits ) @@ -2636,7 +2535,6 @@ add_fp_unittest( log1pf_test.cpp DEPENDS libc.src.errno.errno - libc.include.math libc.src.math.log1pf libc.src.__support.FPUtil.fp_bits ) @@ -2650,7 +2548,6 @@ add_fp_unittest( HDRS FModTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.math.fmodf libc.src.__support.FPUtil.basic_operations @@ -2668,7 +2565,6 @@ add_fp_unittest( HDRS FModTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.math.fmod libc.src.__support.FPUtil.basic_operations @@ -2686,7 +2582,6 @@ add_fp_unittest( HDRS FModTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.math.fmodl libc.src.__support.FPUtil.basic_operations @@ -2704,7 +2599,6 @@ add_fp_unittest( HDRS FModTest.h DEPENDS - libc.include.math libc.src.errno.errno libc.src.math.fmodf128 libc.src.__support.FPUtil.basic_operations @@ -2843,7 +2737,6 @@ add_fp_unittest( HDRS ScalbnTest.h DEPENDS - libc.include.math libc.src.math.scalbn libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.normal_float @@ -2858,7 +2751,6 @@ add_fp_unittest( HDRS ScalbnTest.h DEPENDS - libc.include.math libc.src.math.scalbnf libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.normal_float @@ -2873,7 +2765,6 @@ add_fp_unittest( HDRS ScalbnTest.h DEPENDS - libc.include.math libc.src.math.scalbnl libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.normal_float @@ -2886,7 +2777,6 @@ add_fp_unittest( SRCS erff_test.cpp DEPENDS - libc.include.math libc.src.math.erff libc.src.__support.FPUtil.fp_bits ) @@ -2898,7 +2788,6 @@ add_fp_unittest( SRCS powf_test.cpp DEPENDS - libc.include.math libc.src.math.powf libc.src.__support.FPUtil.fp_bits ) diff --git a/libc/test/src/math/smoke/CanonicalizeTest.h b/libc/test/src/math/smoke/CanonicalizeTest.h index 4361f7d8ac7a..ab45e0eb8e94 100644 --- a/libc/test/src/math/smoke/CanonicalizeTest.h +++ b/libc/test/src/math/smoke/CanonicalizeTest.h @@ -14,7 +14,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #define TEST_SPECIAL(x, y, expected, expected_exception) \ EXPECT_EQ(expected, f(&x, &y)); \ diff --git a/libc/test/src/math/smoke/CeilTest.h b/libc/test/src/math/smoke/CeilTest.h index ec70258fddec..70e441a849cb 100644 --- a/libc/test/src/math/smoke/CeilTest.h +++ b/libc/test/src/math/smoke/CeilTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class CeilTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/CopySignTest.h b/libc/test/src/math/smoke/CopySignTest.h index 70a6a419e0a0..fa9da91920f8 100644 --- a/libc/test/src/math/smoke/CopySignTest.h +++ b/libc/test/src/math/smoke/CopySignTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class CopySignTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/FAbsTest.h b/libc/test/src/math/smoke/FAbsTest.h index 9309c2ada4a1..0c8ca95ba0f7 100644 --- a/libc/test/src/math/smoke/FAbsTest.h +++ b/libc/test/src/math/smoke/FAbsTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class FAbsTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/FModTest.h b/libc/test/src/math/smoke/FModTest.h index 96ad299258a1..bc909987a161 100644 --- a/libc/test/src/math/smoke/FModTest.h +++ b/libc/test/src/math/smoke/FModTest.h @@ -14,7 +14,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #define TEST_SPECIAL(x, y, expected, dom_err, expected_exception) \ EXPECT_FP_EQ(expected, f(x, y)); \ diff --git a/libc/test/src/math/smoke/FloorTest.h b/libc/test/src/math/smoke/FloorTest.h index 8886e8e75183..12944aa77562 100644 --- a/libc/test/src/math/smoke/FloorTest.h +++ b/libc/test/src/math/smoke/FloorTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class FloorTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/HypotTest.h b/libc/test/src/math/smoke/HypotTest.h index 80816033f28f..a1b8f8a7fafa 100644 --- a/libc/test/src/math/smoke/HypotTest.h +++ b/libc/test/src/math/smoke/HypotTest.h @@ -13,7 +13,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class HypotTestTemplate : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/ModfTest.h b/libc/test/src/math/smoke/ModfTest.h index 107963665b83..65d61855c9f2 100644 --- a/libc/test/src/math/smoke/ModfTest.h +++ b/libc/test/src/math/smoke/ModfTest.h @@ -11,7 +11,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class ModfTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/NextAfterTest.h b/libc/test/src/math/smoke/NextAfterTest.h index 403ea6bd8df6..d9c50c8109d8 100644 --- a/libc/test/src/math/smoke/NextAfterTest.h +++ b/libc/test/src/math/smoke/NextAfterTest.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_NEXTAFTERTEST_H #define LLVM_LIBC_TEST_SRC_MATH_NEXTAFTERTEST_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/BasicOperations.h" diff --git a/libc/test/src/math/smoke/NextTowardTest.h b/libc/test/src/math/smoke/NextTowardTest.h index 0c2abf815c23..d97aea96d837 100644 --- a/libc/test/src/math/smoke/NextTowardTest.h +++ b/libc/test/src/math/smoke/NextTowardTest.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_NEXTTOWARDTEST_H #define LLVM_LIBC_TEST_SRC_MATH_NEXTTOWARDTEST_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/BasicOperations.h" diff --git a/libc/test/src/math/smoke/RIntTest.h b/libc/test/src/math/smoke/RIntTest.h index 5a283a8bc0b5..73c3428047e9 100644 --- a/libc/test/src/math/smoke/RIntTest.h +++ b/libc/test/src/math/smoke/RIntTest.h @@ -14,7 +14,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include #include diff --git a/libc/test/src/math/smoke/RemQuoTest.h b/libc/test/src/math/smoke/RemQuoTest.h index cf56b1d6460f..7df537d8b206 100644 --- a/libc/test/src/math/smoke/RemQuoTest.h +++ b/libc/test/src/math/smoke/RemQuoTest.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_REMQUOTEST_H #define LLVM_LIBC_TEST_SRC_MATH_REMQUOTEST_H -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/smoke/RoundEvenTest.h b/libc/test/src/math/smoke/RoundEvenTest.h index 107052fa0e28..e168d57bdbf3 100644 --- a/libc/test/src/math/smoke/RoundEvenTest.h +++ b/libc/test/src/math/smoke/RoundEvenTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class RoundEvenTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/RoundTest.h b/libc/test/src/math/smoke/RoundTest.h index 8cf96f456903..49b2a1bf7dfb 100644 --- a/libc/test/src/math/smoke/RoundTest.h +++ b/libc/test/src/math/smoke/RoundTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class RoundTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/RoundToIntegerTest.h b/libc/test/src/math/smoke/RoundToIntegerTest.h index 44b3f8996df5..863cf75f05ff 100644 --- a/libc/test/src/math/smoke/RoundToIntegerTest.h +++ b/libc/test/src/math/smoke/RoundToIntegerTest.h @@ -14,7 +14,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include static constexpr int ROUNDING_MODES[4] = {FE_UPWARD, FE_DOWNWARD, FE_TOWARDZERO, diff --git a/libc/test/src/math/smoke/SqrtTest.h b/libc/test/src/math/smoke/SqrtTest.h index eea5dc1534e0..46382ed58e14 100644 --- a/libc/test/src/math/smoke/SqrtTest.h +++ b/libc/test/src/math/smoke/SqrtTest.h @@ -10,7 +10,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class SqrtTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/TruncTest.h b/libc/test/src/math/smoke/TruncTest.h index 5612d27fef21..c0fc87f9313b 100644 --- a/libc/test/src/math/smoke/TruncTest.h +++ b/libc/test/src/math/smoke/TruncTest.h @@ -12,7 +12,7 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" template class TruncTest : public LIBC_NAMESPACE::testing::Test { diff --git a/libc/test/src/math/smoke/acosf_test.cpp b/libc/test/src/math/smoke/acosf_test.cpp index 573a2c39492f..732c29548c60 100644 --- a/libc/test/src/math/smoke/acosf_test.cpp +++ b/libc/test/src/math/smoke/acosf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/acosf.h" diff --git a/libc/test/src/math/smoke/acoshf_test.cpp b/libc/test/src/math/smoke/acoshf_test.cpp index f561f23eb99a..2e94216ede36 100644 --- a/libc/test/src/math/smoke/acoshf_test.cpp +++ b/libc/test/src/math/smoke/acoshf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/acoshf.h" diff --git a/libc/test/src/math/smoke/asinf_test.cpp b/libc/test/src/math/smoke/asinf_test.cpp index 39d25e72c143..c67d07711cd1 100644 --- a/libc/test/src/math/smoke/asinf_test.cpp +++ b/libc/test/src/math/smoke/asinf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/asinf.h" diff --git a/libc/test/src/math/smoke/asinhf_test.cpp b/libc/test/src/math/smoke/asinhf_test.cpp index 9637bfa53948..f95184676303 100644 --- a/libc/test/src/math/smoke/asinhf_test.cpp +++ b/libc/test/src/math/smoke/asinhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/asinhf.h" diff --git a/libc/test/src/math/smoke/atan2f_test.cpp b/libc/test/src/math/smoke/atan2f_test.cpp index ecac36b3a8c0..f81d140fefc5 100644 --- a/libc/test/src/math/smoke/atan2f_test.cpp +++ b/libc/test/src/math/smoke/atan2f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/atan2f.h" diff --git a/libc/test/src/math/smoke/atanf_test.cpp b/libc/test/src/math/smoke/atanf_test.cpp index abd9835d38a0..3800c2334b92 100644 --- a/libc/test/src/math/smoke/atanf_test.cpp +++ b/libc/test/src/math/smoke/atanf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/atanf.h" diff --git a/libc/test/src/math/smoke/atanhf_test.cpp b/libc/test/src/math/smoke/atanhf_test.cpp index 590a7ab60f04..fc3e2dd9bc54 100644 --- a/libc/test/src/math/smoke/atanhf_test.cpp +++ b/libc/test/src/math/smoke/atanhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/atanhf.h" diff --git a/libc/test/src/math/smoke/cosf_test.cpp b/libc/test/src/math/smoke/cosf_test.cpp index 62132990ed54..7000fe2f2b07 100644 --- a/libc/test/src/math/smoke/cosf_test.cpp +++ b/libc/test/src/math/smoke/cosf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/cosf.h" diff --git a/libc/test/src/math/smoke/coshf_test.cpp b/libc/test/src/math/smoke/coshf_test.cpp index 9d7ef505ae74..4d915b12dee1 100644 --- a/libc/test/src/math/smoke/coshf_test.cpp +++ b/libc/test/src/math/smoke/coshf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/array.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/smoke/erff_test.cpp b/libc/test/src/math/smoke/erff_test.cpp index 24778f8d653a..102126ee4e23 100644 --- a/libc/test/src/math/smoke/erff_test.cpp +++ b/libc/test/src/math/smoke/erff_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/erff.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/smoke/exp10_test.cpp b/libc/test/src/math/smoke/exp10_test.cpp index fffffeb4c78a..7154cb176038 100644 --- a/libc/test/src/math/smoke/exp10_test.cpp +++ b/libc/test/src/math/smoke/exp10_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp10.h" diff --git a/libc/test/src/math/smoke/exp10f_test.cpp b/libc/test/src/math/smoke/exp10f_test.cpp index c0dcc1250332..9fb15ae75348 100644 --- a/libc/test/src/math/smoke/exp10f_test.cpp +++ b/libc/test/src/math/smoke/exp10f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp10f.h" diff --git a/libc/test/src/math/smoke/exp2_test.cpp b/libc/test/src/math/smoke/exp2_test.cpp index d362d32f678b..a8ef6cfa7f6a 100644 --- a/libc/test/src/math/smoke/exp2_test.cpp +++ b/libc/test/src/math/smoke/exp2_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp2.h" diff --git a/libc/test/src/math/smoke/exp2f_test.cpp b/libc/test/src/math/smoke/exp2f_test.cpp index e2989a6ec4d8..3ef1a4ece4cf 100644 --- a/libc/test/src/math/smoke/exp2f_test.cpp +++ b/libc/test/src/math/smoke/exp2f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/smoke/exp_test.cpp b/libc/test/src/math/smoke/exp_test.cpp index a2becc74f526..2abaa7230831 100644 --- a/libc/test/src/math/smoke/exp_test.cpp +++ b/libc/test/src/math/smoke/exp_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/exp.h" diff --git a/libc/test/src/math/smoke/expf_test.cpp b/libc/test/src/math/smoke/expf_test.cpp index 42710c5fa404..b954125afd7b 100644 --- a/libc/test/src/math/smoke/expf_test.cpp +++ b/libc/test/src/math/smoke/expf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/expf.h" diff --git a/libc/test/src/math/smoke/expm1_test.cpp b/libc/test/src/math/smoke/expm1_test.cpp index 07963ec2d34c..d5f166d53a50 100644 --- a/libc/test/src/math/smoke/expm1_test.cpp +++ b/libc/test/src/math/smoke/expm1_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/expm1.h" diff --git a/libc/test/src/math/smoke/expm1f_test.cpp b/libc/test/src/math/smoke/expm1f_test.cpp index 82e0b1546350..03b6e47b7c3b 100644 --- a/libc/test/src/math/smoke/expm1f_test.cpp +++ b/libc/test/src/math/smoke/expm1f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/expm1f.h" diff --git a/libc/test/src/math/smoke/log10_test.cpp b/libc/test/src/math/smoke/log10_test.cpp index 36d753419764..37baf89128f2 100644 --- a/libc/test/src/math/smoke/log10_test.cpp +++ b/libc/test/src/math/smoke/log10_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log10.h" diff --git a/libc/test/src/math/smoke/log10f_test.cpp b/libc/test/src/math/smoke/log10f_test.cpp index 53e699417fb7..721045d355da 100644 --- a/libc/test/src/math/smoke/log10f_test.cpp +++ b/libc/test/src/math/smoke/log10f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/log10f.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/smoke/log1p_test.cpp b/libc/test/src/math/smoke/log1p_test.cpp index 5fe9c60f90ab..993dbf8001df 100644 --- a/libc/test/src/math/smoke/log1p_test.cpp +++ b/libc/test/src/math/smoke/log1p_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log1p.h" diff --git a/libc/test/src/math/smoke/log1pf_test.cpp b/libc/test/src/math/smoke/log1pf_test.cpp index e2fb2f057d2e..6127cc89a742 100644 --- a/libc/test/src/math/smoke/log1pf_test.cpp +++ b/libc/test/src/math/smoke/log1pf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log1pf.h" diff --git a/libc/test/src/math/smoke/log2_test.cpp b/libc/test/src/math/smoke/log2_test.cpp index fbeba9527bcb..b59767e668eb 100644 --- a/libc/test/src/math/smoke/log2_test.cpp +++ b/libc/test/src/math/smoke/log2_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log2.h" diff --git a/libc/test/src/math/smoke/log2f_test.cpp b/libc/test/src/math/smoke/log2f_test.cpp index 46906e78dcaf..00bfb7c4abad 100644 --- a/libc/test/src/math/smoke/log2f_test.cpp +++ b/libc/test/src/math/smoke/log2f_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log2f.h" diff --git a/libc/test/src/math/smoke/log_test.cpp b/libc/test/src/math/smoke/log_test.cpp index b1e390599480..fd527dee5084 100644 --- a/libc/test/src/math/smoke/log_test.cpp +++ b/libc/test/src/math/smoke/log_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/log.h" diff --git a/libc/test/src/math/smoke/logf_test.cpp b/libc/test/src/math/smoke/logf_test.cpp index 97b6bdde307b..a27206027614 100644 --- a/libc/test/src/math/smoke/logf_test.cpp +++ b/libc/test/src/math/smoke/logf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/logf.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/smoke/powf_test.cpp b/libc/test/src/math/smoke/powf_test.cpp index e9de1554ec61..98a532f3468c 100644 --- a/libc/test/src/math/smoke/powf_test.cpp +++ b/libc/test/src/math/smoke/powf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/math/powf.h" #include "test/UnitTest/FPMatcher.h" diff --git a/libc/test/src/math/smoke/sincosf_test.cpp b/libc/test/src/math/smoke/sincosf_test.cpp index 5952b20fc5bf..8c35953240d8 100644 --- a/libc/test/src/math/smoke/sincosf_test.cpp +++ b/libc/test/src/math/smoke/sincosf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/sincosf.h" diff --git a/libc/test/src/math/smoke/sinf_test.cpp b/libc/test/src/math/smoke/sinf_test.cpp index 945089504187..9fc208dd545b 100644 --- a/libc/test/src/math/smoke/sinf_test.cpp +++ b/libc/test/src/math/smoke/sinf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/sinf.h" diff --git a/libc/test/src/math/smoke/sinhf_test.cpp b/libc/test/src/math/smoke/sinhf_test.cpp index 0f005f752e69..1e052988eb28 100644 --- a/libc/test/src/math/smoke/sinhf_test.cpp +++ b/libc/test/src/math/smoke/sinhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/CPP/array.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" diff --git a/libc/test/src/math/smoke/tanf_test.cpp b/libc/test/src/math/smoke/tanf_test.cpp index 68bf493f7e82..ab3f7c1aeb7e 100644 --- a/libc/test/src/math/smoke/tanf_test.cpp +++ b/libc/test/src/math/smoke/tanf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/tanf.h" diff --git a/libc/test/src/math/smoke/tanhf_test.cpp b/libc/test/src/math/smoke/tanhf_test.cpp index f1ce8b40d43a..ddae021d2bc4 100644 --- a/libc/test/src/math/smoke/tanhf_test.cpp +++ b/libc/test/src/math/smoke/tanhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/tanhf.h" diff --git a/libc/test/src/math/tan_test.cpp b/libc/test/src/math/tan_test.cpp index 85174db9364e..d813dccc3836 100644 --- a/libc/test/src/math/tan_test.cpp +++ b/libc/test/src/math/tan_test.cpp @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" using LlvmLibcTanTest = LIBC_NAMESPACE::testing::FPTest; diff --git a/libc/test/src/math/tanf_test.cpp b/libc/test/src/math/tanf_test.cpp index d40bc44d6442..e624d30f1e00 100644 --- a/libc/test/src/math/tanf_test.cpp +++ b/libc/test/src/math/tanf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/tanf.h" diff --git a/libc/test/src/math/tanhf_test.cpp b/libc/test/src/math/tanhf_test.cpp index ef272b17d68c..c34efe8d733b 100644 --- a/libc/test/src/math/tanhf_test.cpp +++ b/libc/test/src/math/tanhf_test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/errno/libc_errno.h" #include "src/math/tanhf.h" diff --git a/libc/test/src/sys/random/linux/CMakeLists.txt b/libc/test/src/sys/random/linux/CMakeLists.txt index 47d363c2c174..737326cb158c 100644 --- a/libc/test/src/sys/random/linux/CMakeLists.txt +++ b/libc/test/src/sys/random/linux/CMakeLists.txt @@ -7,7 +7,6 @@ add_libc_unittest( SRCS getrandom_test.cpp DEPENDS - libc.include.math libc.include.sys_random libc.src.errno.errno libc.src.math.fabs diff --git a/libc/test/utils/FPUtil/CMakeLists.txt b/libc/test/utils/FPUtil/CMakeLists.txt index 06b7042e20db..7b6c294506b1 100644 --- a/libc/test/utils/FPUtil/CMakeLists.txt +++ b/libc/test/utils/FPUtil/CMakeLists.txt @@ -4,7 +4,7 @@ if((${LIBC_TARGET_OS} STREQUAL "linux") AND (${LIBC_TARGET_ARCHITECTURE_IS_X86}) SRCS x86_long_double_test.cpp DEPENDS - libc.include.math + libc.hdr.math_macros libc.src.__support.FPUtil.fp_bits ) endif() diff --git a/libc/test/utils/FPUtil/x86_long_double_test.cpp b/libc/test/utils/FPUtil/x86_long_double_test.cpp index 3b140c6c0266..87796b5c9f5b 100644 --- a/libc/test/utils/FPUtil/x86_long_double_test.cpp +++ b/libc/test/utils/FPUtil/x86_long_double_test.cpp @@ -9,7 +9,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/Test.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/utils/MPFRWrapper/MPFRUtils.cpp b/libc/utils/MPFRWrapper/MPFRUtils.cpp index 938e2c3c0edf..91a623ddfa12 100644 --- a/libc/utils/MPFRWrapper/MPFRUtils.cpp +++ b/libc/utils/MPFRWrapper/MPFRUtils.cpp @@ -14,7 +14,7 @@ #include "src/__support/FPUtil/fpbits_str.h" #include "test/UnitTest/FPMatcher.h" -#include "include/llvm-libc-macros/math-macros.h" +#include "hdr/math_macros.h" #include #include #include diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 13b290c4bd2b..1fb93cac42b9 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -106,6 +106,14 @@ libc_support_library( hdrs = ["include/llvm-libc-macros/linux/fcntl-macros.h"], ) +############################ Proxy Header Files ################################ + +libc_support_library( + name = "hdr_math_macros", + hdrs = ["hdr/math_macros.h"], +) + + ############################### Support libraries ############################## libc_support_library( @@ -736,7 +744,7 @@ libc_support_library( ":__support_macros_properties_architectures", ":__support_macros_sanitizer", ":errno", - ":llvm_libc_macros_math_macros", + ":hdr_math_macros", ], ) @@ -810,7 +818,7 @@ libc_support_library( ":__support_fputil_normal_float", ":__support_macros_optimization", ":__support_uint128", - ":llvm_libc_macros_math_macros", + ":hdr_math_macros", ], ) @@ -824,7 +832,7 @@ libc_support_library( ":__support_fputil_fp_bits", ":__support_fputil_rounding_mode", ":__support_macros_attributes", - ":llvm_libc_macros_math_macros", + ":hdr_math_macros", ], ) @@ -1245,7 +1253,7 @@ libc_support_library( "__support_cpp_type_traits", ":__support_common", ":errno", - ":llvm_libc_macros_math_macros", + ":hdr_math_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel index d2087a3d528f..7d77b6114464 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel @@ -85,7 +85,7 @@ libc_support_library( "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_fpbits_str", "//libc:__support_fputil_rounding_mode", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel index c0d402a89ea3..9e1b25e10d6c 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel @@ -90,7 +90,7 @@ libc_test( "//libc:__support_integer_literals", "//libc:__support_macros_properties_types", "//libc:__support_uint", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel index 15e367f0aca2..3c43c604316f 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel @@ -178,7 +178,7 @@ libc_support_library( deps = [ "//libc:__support_fputil_basic_operations", "//libc:__support_fputil_fp_bits", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", "//libc/utils/MPFRWrapper:mpfr_wrapper", @@ -297,7 +297,7 @@ libc_support_library( "//libc:__support_cpp_limits", "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_manipulation_functions", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", ], ) @@ -324,7 +324,7 @@ libc_support_library( "//libc:__support_fputil_basic_operations", "//libc:__support_fputil_fenv_impl", "//libc:__support_fputil_fp_bits", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", ], @@ -352,7 +352,7 @@ libc_support_library( "//libc:__support_cpp_limits", "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_normal_float", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", ], @@ -379,7 +379,7 @@ libc_support_library( deps = [ "//libc:__support_fputil_fenv_impl", "//libc:__support_fputil_fp_bits", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", "//libc/utils/MPFRWrapper:mpfr_wrapper", @@ -416,7 +416,7 @@ libc_support_library( deps = [ "//libc:__support_fputil_fenv_impl", "//libc:__support_fputil_fp_bits", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", "//libc/utils/MPFRWrapper:mpfr_wrapper", @@ -528,7 +528,7 @@ libc_support_library( "//libc:__support_cpp_type_traits", "//libc:__support_fputil_basic_operations", "//libc:__support_fputil_fp_bits", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", ], diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl b/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl index 1a5868d242e8..da4964bd8982 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/libc_math_test_rules.bzl @@ -34,7 +34,7 @@ def math_test(name, hdrs = [], deps = [], **kwargs): "//libc:__support_math_extras", "//libc:__support_uint128", "//libc/test/UnitTest:fp_test_helpers", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", ] + deps, **kwargs ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel index 0d69a480cb28..f16bce32fe98 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel @@ -90,7 +90,7 @@ libc_support_library( "//libc:__support_cpp_limits", "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_normal_float", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", ], @@ -135,7 +135,7 @@ libc_support_library( "//libc:__support_cpp_type_traits", "//libc:__support_fputil_basic_operations", "//libc:__support_fputil_fp_bits", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", ], diff --git a/utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel index 5f59d70ecc16..53a8c9b9476f 100644 --- a/utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel @@ -46,7 +46,7 @@ libc_support_library( "//libc:__support_cpp_type_traits", "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_fpbits_str", - "//libc:llvm_libc_macros_math_macros", + "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", "//libc/utils/MPFRWrapper:mpfr_impl", -- GitLab From 2d3c827c053c112491dc1102ff31fc7d703adc36 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Fri, 5 Apr 2024 16:08:59 -0700 Subject: [PATCH 046/695] [BOLT] Use BAT for YAML profile call target information Provide a mechanism to resolve call target information for calls from non-BAT functions to BAT functions (`YAMLProfileWriter::convert`). Make it generic for future use in BAT-to-BAT calls. Test Plan: Updated bolt/test/X86/bolt-address-translation-yaml.test Reviewers: ayermolo, maksfb, rafaelauler, dcci Reviewed By: maksfb Pull Request: https://github.com/llvm/llvm-project/pull/86219 --- .../bolt/Profile/BoltAddressTranslation.h | 12 +++++ bolt/include/bolt/Profile/YAMLProfileWriter.h | 13 +++++- bolt/lib/Profile/BoltAddressTranslation.cpp | 44 +++++++++++++++++++ bolt/lib/Profile/DataAggregator.cpp | 2 +- bolt/lib/Profile/YAMLProfileWriter.cpp | 23 ++++++---- .../X86/bolt-address-translation-yaml.test | 7 ++- 6 files changed, 88 insertions(+), 13 deletions(-) diff --git a/bolt/include/bolt/Profile/BoltAddressTranslation.h b/bolt/include/bolt/Profile/BoltAddressTranslation.h index caf907cc43da..6a0a477f2758 100644 --- a/bolt/include/bolt/Profile/BoltAddressTranslation.h +++ b/bolt/include/bolt/Profile/BoltAddressTranslation.h @@ -19,6 +19,7 @@ #include namespace llvm { +class MCSymbol; class raw_ostream; namespace object { @@ -123,6 +124,13 @@ public: std::unordered_map> getBFBranches(uint64_t FuncOutputAddress) const; + /// For a given \p Symbol in the output binary and known \p InputOffset + /// return a corresponding pair of parent BinaryFunction and secondary entry + /// point in it. + std::pair + translateSymbol(const BinaryContext &BC, const MCSymbol &Symbol, + uint32_t InputOffset) const; + private: /// Helper to update \p Map by inserting one or more BAT entries reflecting /// \p BB for function located at \p FuncAddress. At least one entry will be @@ -158,6 +166,10 @@ private: /// Map a function to its secondary entry points vector std::unordered_map> SecondaryEntryPointsMap; + /// Return a secondary entry point ID for a function located at \p Address and + /// \p Offset within that function. + unsigned getSecondaryEntryPointId(uint64_t Address, uint32_t Offset) const; + /// Links outlined cold bocks to their original function std::map ColdPartSource; diff --git a/bolt/include/bolt/Profile/YAMLProfileWriter.h b/bolt/include/bolt/Profile/YAMLProfileWriter.h index 882748627e7f..4a9355dfceac 100644 --- a/bolt/include/bolt/Profile/YAMLProfileWriter.h +++ b/bolt/include/bolt/Profile/YAMLProfileWriter.h @@ -15,6 +15,7 @@ namespace llvm { namespace bolt { +class BoltAddressTranslation; class RewriteInstance; class YAMLProfileWriter { @@ -31,8 +32,16 @@ public: /// Save execution profile for that instance. std::error_code writeProfile(const RewriteInstance &RI); - static yaml::bolt::BinaryFunctionProfile convert(const BinaryFunction &BF, - bool UseDFS); + static yaml::bolt::BinaryFunctionProfile + convert(const BinaryFunction &BF, bool UseDFS, + const BoltAddressTranslation *BAT = nullptr); + + /// Set CallSiteInfo destination fields from \p Symbol and return a target + /// BinaryFunction for that symbol. + static const BinaryFunction * + setCSIDestination(const BinaryContext &BC, yaml::bolt::CallSiteInfo &CSI, + const MCSymbol *Symbol, const BoltAddressTranslation *BAT, + uint32_t Offset = 0); }; } // namespace bolt diff --git a/bolt/lib/Profile/BoltAddressTranslation.cpp b/bolt/lib/Profile/BoltAddressTranslation.cpp index bcd4a457ce3b..6b808257e9ab 100644 --- a/bolt/lib/Profile/BoltAddressTranslation.cpp +++ b/bolt/lib/Profile/BoltAddressTranslation.cpp @@ -597,5 +597,49 @@ BoltAddressTranslation::getBFBranches(uint64_t OutputAddress) const { return Branches; } +unsigned +BoltAddressTranslation::getSecondaryEntryPointId(uint64_t Address, + uint32_t Offset) const { + auto FunctionIt = SecondaryEntryPointsMap.find(Address); + if (FunctionIt == SecondaryEntryPointsMap.end()) + return 0; + const std::vector &Offsets = FunctionIt->second; + auto OffsetIt = std::find(Offsets.begin(), Offsets.end(), Offset); + if (OffsetIt == Offsets.end()) + return 0; + // Adding one here because main entry point is not stored in BAT, and + // enumeration for secondary entry points starts with 1. + return OffsetIt - Offsets.begin() + 1; +} + +std::pair +BoltAddressTranslation::translateSymbol(const BinaryContext &BC, + const MCSymbol &Symbol, + uint32_t Offset) const { + // The symbol could be a secondary entry in a cold fragment. + uint64_t SymbolValue = cantFail(errorOrToExpected(BC.getSymbolValue(Symbol))); + + const BinaryFunction *Callee = BC.getFunctionForSymbol(&Symbol); + assert(Callee); + + // Containing function, not necessarily the same as symbol value. + const uint64_t CalleeAddress = Callee->getAddress(); + const uint32_t OutputOffset = SymbolValue - CalleeAddress; + + const uint64_t ParentAddress = fetchParentAddress(CalleeAddress); + const uint64_t HotAddress = ParentAddress ? ParentAddress : CalleeAddress; + + const BinaryFunction *ParentBF = BC.getBinaryFunctionAtAddress(HotAddress); + + const uint32_t InputOffset = + translate(CalleeAddress, OutputOffset, /*IsBranchSrc*/ false) + Offset; + + unsigned SecondaryEntryId{0}; + if (InputOffset) + SecondaryEntryId = getSecondaryEntryPointId(HotAddress, InputOffset); + + return std::pair(ParentBF, SecondaryEntryId); +} + } // namespace bolt } // namespace llvm diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp index 05099aa25ce2..71824e2cc0e9 100644 --- a/bolt/lib/Profile/DataAggregator.cpp +++ b/bolt/lib/Profile/DataAggregator.cpp @@ -2333,7 +2333,7 @@ std::error_code DataAggregator::writeBATYAML(BinaryContext &BC, if (BAT->isBATFunction(Function.getAddress())) continue; BP.Functions.emplace_back( - YAMLProfileWriter::convert(Function, /*UseDFS=*/false)); + YAMLProfileWriter::convert(Function, /*UseDFS=*/false, BAT)); } for (const auto &KV : NamesToBranches) { diff --git a/bolt/lib/Profile/YAMLProfileWriter.cpp b/bolt/lib/Profile/YAMLProfileWriter.cpp index 0f082086c1fc..ef04ba0d21ad 100644 --- a/bolt/lib/Profile/YAMLProfileWriter.cpp +++ b/bolt/lib/Profile/YAMLProfileWriter.cpp @@ -9,6 +9,7 @@ #include "bolt/Profile/YAMLProfileWriter.h" #include "bolt/Core/BinaryBasicBlock.h" #include "bolt/Core/BinaryFunction.h" +#include "bolt/Profile/BoltAddressTranslation.h" #include "bolt/Profile/ProfileReaderBase.h" #include "bolt/Rewrite/RewriteInstance.h" #include "llvm/Support/CommandLine.h" @@ -25,17 +26,19 @@ extern llvm::cl::opt ProfileUseDFS; namespace llvm { namespace bolt { -/// Set CallSiteInfo destination fields from \p Symbol and return a target -/// BinaryFunction for that symbol. -static const BinaryFunction *setCSIDestination(const BinaryContext &BC, - yaml::bolt::CallSiteInfo &CSI, - const MCSymbol *Symbol) { +const BinaryFunction *YAMLProfileWriter::setCSIDestination( + const BinaryContext &BC, yaml::bolt::CallSiteInfo &CSI, + const MCSymbol *Symbol, const BoltAddressTranslation *BAT, + uint32_t Offset) { CSI.DestId = 0; // designated for unknown functions CSI.EntryDiscriminator = 0; + if (Symbol) { uint64_t EntryID = 0; - if (const BinaryFunction *const Callee = + if (const BinaryFunction *Callee = BC.getFunctionForSymbol(Symbol, &EntryID)) { + if (BAT && BAT->isBATFunction(Callee->getAddress())) + std::tie(Callee, EntryID) = BAT->translateSymbol(BC, *Symbol, Offset); CSI.DestId = Callee->getFunctionNumber(); CSI.EntryDiscriminator = EntryID; return Callee; @@ -45,7 +48,8 @@ static const BinaryFunction *setCSIDestination(const BinaryContext &BC, } yaml::bolt::BinaryFunctionProfile -YAMLProfileWriter::convert(const BinaryFunction &BF, bool UseDFS) { +YAMLProfileWriter::convert(const BinaryFunction &BF, bool UseDFS, + const BoltAddressTranslation *BAT) { yaml::bolt::BinaryFunctionProfile YamlBF; const BinaryContext &BC = BF.getBinaryContext(); @@ -98,7 +102,8 @@ YAMLProfileWriter::convert(const BinaryFunction &BF, bool UseDFS) { continue; for (const IndirectCallProfile &CSP : ICSP.get()) { StringRef TargetName = ""; - const BinaryFunction *Callee = setCSIDestination(BC, CSI, CSP.Symbol); + const BinaryFunction *Callee = + setCSIDestination(BC, CSI, CSP.Symbol, BAT); if (Callee) TargetName = Callee->getOneName(); CSI.Count = CSP.Count; @@ -109,7 +114,7 @@ YAMLProfileWriter::convert(const BinaryFunction &BF, bool UseDFS) { StringRef TargetName = ""; const MCSymbol *CalleeSymbol = BC.MIB->getTargetSymbol(Instr); const BinaryFunction *const Callee = - setCSIDestination(BC, CSI, CalleeSymbol); + setCSIDestination(BC, CSI, CalleeSymbol, BAT); if (Callee) TargetName = Callee->getOneName(); diff --git a/bolt/test/X86/bolt-address-translation-yaml.test b/bolt/test/X86/bolt-address-translation-yaml.test index 7fdf7709a8b9..af24c3d84a0f 100644 --- a/bolt/test/X86/bolt-address-translation-yaml.test +++ b/bolt/test/X86/bolt-address-translation-yaml.test @@ -36,9 +36,14 @@ YAML-BAT-CHECK-NEXT: - bid: 0 YAML-BAT-CHECK-NEXT: insns: 26 YAML-BAT-CHECK-NEXT: hash: 0xA900AE79CFD40000 YAML-BAT-CHECK-NEXT: succ: [ { bid: 3, cnt: 0 }, { bid: 1, cnt: 0 } ] +# Calls from no-BAT to BAT function +YAML-BAT-CHECK: - bid: 28 +YAML-BAT-CHECK-NEXT: insns: 13 +YAML-BAT-CHECK-NEXT: hash: 0xB2F04C1F25F00400 +YAML-BAT-CHECK-NEXT: calls: [ { off: 0x21, fid: [[#SOLVECUBIC:]], cnt: 25 }, { off: 0x2D, fid: [[#]], cnt: 9 } ] # Function covered by BAT with calls YAML-BAT-CHECK: - name: SolveCubic -YAML-BAT-CHECK-NEXT: fid: [[#]] +YAML-BAT-CHECK-NEXT: fid: [[#SOLVECUBIC]] YAML-BAT-CHECK-NEXT: hash: 0x6AF7E61EA3966722 YAML-BAT-CHECK-NEXT: exec: 25 YAML-BAT-CHECK-NEXT: nblocks: 15 -- GitLab From 3f2f700633bbcc0cb5ada17f5736b43f9c1e426e Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Sat, 6 Apr 2024 07:31:53 +0800 Subject: [PATCH 047/695] [flang] Fix -Wunused-but-set-variable in Bridge.cpp (NFC) llvm-project/flang/lib/Lower/Bridge.cpp:3775:14: error: variable 'nbDeviceResidentObject' set but not used [-Werror,-Wunused-but-set-variable] unsigned nbDeviceResidentObject = 0; ^ 1 error generated. --- flang/lib/Lower/Bridge.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index 478c8f4c17ec..47bd6ace4e4b 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -3772,7 +3772,7 @@ private: localSymbols.pushScope(); auto transferKindAttr = fir::CUDADataTransferKindAttr::get( builder.getContext(), fir::CUDADataTransferKind::DeviceHost); - unsigned nbDeviceResidentObject = 0; + [[maybe_unused]] unsigned nbDeviceResidentObject = 0; for (const Fortran::semantics::Symbol &sym : Fortran::evaluate::CollectSymbols(assign.rhs)) { if (const auto *details = -- GitLab From 8bd391457fbd5108610557efdb26c2397aa0bd24 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 5 Apr 2024 17:02:03 -0700 Subject: [PATCH 048/695] [RISCV] Rename OP-P to OP-VE. (#87546) This has been updated in the isa-manual https://github.com/riscv/riscv-isa-manual/pull/1311 --- llvm/lib/Target/RISCV/RISCVInstrFormats.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index 52c794446af0..a5c8524d05cb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -155,7 +155,7 @@ def OPC_BRANCH : RISCVOpcode<"BRANCH", 0b1100011>; def OPC_JALR : RISCVOpcode<"JALR", 0b1100111>; def OPC_JAL : RISCVOpcode<"JAL", 0b1101111>; def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>; -def OPC_OP_P : RISCVOpcode<"OP_P", 0b1110111>; +def OPC_OP_VE : RISCVOpcode<"OP_VE", 0b1110111>; def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>; class RVInstCommon funct6> // op vd, vs2, vs1 class PALUVVNoVm funct6, RISCVVFormat opv, string opcodestr> : VALUVVNoVm { - let Inst{6-0} = OPC_OP_P.Value; + let Inst{6-0} = OPC_OP_VE.Value; } // op vd, vs2, vs1 @@ -74,13 +74,13 @@ class PALUVVNoVmTernary funct6, RISCVVFormat opv, string opcodestr> opcodestr, "$vd, $vs2, $vs1"> { let Constraints = "$vd = $vd_wb"; let vm = 1; - let Inst{6-0} = OPC_OP_P.Value; + let Inst{6-0} = OPC_OP_VE.Value; } // op vd, vs2, imm class PALUVINoVm funct6, string opcodestr, Operand optype> : VALUVINoVm { - let Inst{6-0} = OPC_OP_P.Value; + let Inst{6-0} = OPC_OP_VE.Value; let Inst{14-12} = OPMVV.Value; } @@ -91,7 +91,7 @@ class PALUVINoVmBinary funct6, string opcodestr, Operand optype> opcodestr, "$vd, $vs2, $imm"> { let Constraints = "$vd = $vd_wb"; let vm = 1; - let Inst{6-0} = OPC_OP_P.Value; + let Inst{6-0} = OPC_OP_VE.Value; let Inst{14-12} = OPMVV.Value; } @@ -103,7 +103,7 @@ class PALUVs2NoVmBinary funct6, bits<5> vs1, RISCVVFormat opv, opcodestr, "$vd, $vs2"> { let Constraints = "$vd = $vd_wb"; let vm = 1; - let Inst{6-0} = OPC_OP_P.Value; + let Inst{6-0} = OPC_OP_VE.Value; } multiclass VAES_MV_V_S funct6_vv, bits<6> funct6_vs, bits<5> vs1, -- GitLab From 0227623915bf0b4794bdbc64974f6cbd6fcc1611 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Fri, 5 Apr 2024 17:50:50 -0700 Subject: [PATCH 049/695] [BOLT][BAT] Support multi-way split functions BAT writeMaps encoded the assumption that functions are only split into two fragments (hot and cold). However, BOLT supports splitting into arbitrary number of fragments. Relax that assumption and look up primary (hot) fragment explicitly. Depends on: https://github.com/llvm/llvm-project/pull/86219 Test Plan: Updated bolt/test/X86/yaml-secondary-entry-discriminator.s Reviewers: ayermolo, rafaelauler, maksfb, dcci Reviewed By: maksfb, dcci Pull Request: https://github.com/llvm/llvm-project/pull/87123 --- bolt/lib/Profile/BoltAddressTranslation.cpp | 7 ++++--- .../X86/yaml-secondary-entry-discriminator.s | 19 ++++++++++++++++--- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/bolt/lib/Profile/BoltAddressTranslation.cpp b/bolt/lib/Profile/BoltAddressTranslation.cpp index 6b808257e9ab..90c62c13dcaa 100644 --- a/bolt/lib/Profile/BoltAddressTranslation.cpp +++ b/bolt/lib/Profile/BoltAddressTranslation.cpp @@ -100,7 +100,7 @@ void BoltAddressTranslation::write(const BinaryContext &BC, raw_ostream &OS) { LLVM_DEBUG(dbgs() << "Function name: " << Function.getPrintName() << "\n"); LLVM_DEBUG(dbgs() << " Address reference: 0x" << Twine::utohexstr(Function.getOutputAddress()) << "\n"); - LLVM_DEBUG(dbgs() << formatv(" Hash: {0:x}\n", getBFHash(OutputAddress))); + LLVM_DEBUG(dbgs() << formatv(" Hash: {0:x}\n", getBFHash(InputAddress))); LLVM_DEBUG(dbgs() << " Secondary Entry Points: " << NumSecondaryEntryPoints << '\n'); @@ -197,8 +197,9 @@ void BoltAddressTranslation::writeMaps(std::map &Maps, ? SecondaryEntryPointsMap[Address].size() : 0; if (Cold) { - size_t HotIndex = - std::distance(ColdPartSource.begin(), ColdPartSource.find(Address)); + auto HotEntryIt = Maps.find(ColdPartSource[Address]); + assert(HotEntryIt != Maps.end()); + size_t HotIndex = std::distance(Maps.begin(), HotEntryIt); encodeULEB128(HotIndex - PrevIndex, OS); PrevIndex = HotIndex; } else { diff --git a/bolt/test/X86/yaml-secondary-entry-discriminator.s b/bolt/test/X86/yaml-secondary-entry-discriminator.s index 43c2e2a7f055..78e7e55aa98e 100644 --- a/bolt/test/X86/yaml-secondary-entry-discriminator.s +++ b/bolt/test/X86/yaml-secondary-entry-discriminator.s @@ -11,17 +11,17 @@ # RUN: FileCheck %s -input-file %t.yaml # CHECK: - name: main # CHECK-NEXT: fid: 2 -# CHECK-NEXT: hash: 0xADF270D550151185 +# CHECK-NEXT: hash: {{.*}} # CHECK-NEXT: exec: 0 # CHECK-NEXT: nblocks: 4 # CHECK-NEXT: blocks: # CHECK: - bid: 1 # CHECK-NEXT: insns: 1 -# CHECK-NEXT: hash: 0x36A303CBA4360014 +# CHECK-NEXT: hash: {{.*}} # CHECK-NEXT: calls: [ { off: 0x0, fid: 1, disc: 1, cnt: 1 } ] # CHECK: - bid: 2 # CHECK-NEXT: insns: 5 -# CHECK-NEXT: hash: 0x8B2F5747CD0019 +# CHECK-NEXT: hash: {{.*}} # CHECK-NEXT: calls: [ { off: 0x0, fid: 1, disc: 1, cnt: 1, mis: 1 } ] # Make sure that the profile is attached correctly @@ -33,6 +33,11 @@ # CHECK-CFG: callq *%rax # Offset: [[#]] # CallProfile: 1 (1 misses) : # CHECK-CFG-NEXT: { secondary_entry: 1 (1 misses) } +# YAML BAT test of calling BAT secondary entry from non-BAT function +# Now force-split func and skip main (making it call secondary entries) +# RUN: llvm-bolt %t.exe -o %t.bat --data %t.fdata --funcs=func \ +# RUN: --split-functions --split-strategy=all --split-all-cold --enable-bat + .globl func .type func, @function func: @@ -40,8 +45,16 @@ func: .cfi_startproc pushq %rbp movq %rsp, %rbp + # Placeholder code to make splitting profitable +.rept 5 + testq %rax, %rax +.endr .globl secondary_entry secondary_entry: + # Placeholder code to make splitting profitable +.rept 5 + testq %rax, %rax +.endr popq %rbp retq nopl (%rax) -- GitLab From e64eede0dcf08e9b2d4bec0b47818b26862ec2c7 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Fri, 5 Apr 2024 17:54:07 -0700 Subject: [PATCH 050/695] [BOLT][BAT] Fix encoded NumBasicBlocks Emit the recorded number of blocks, not the number of basic block hashes. There might be differences in corner cases (openssl BN_BLINDING_convert_ex function). Test Plan: Updated openssl.test in https://github.com/rafaelauler/bolt-tests/pull/31 Reviewers: rafaelauler, ayermolo, maksfb, dcci Reviewed By: ayermolo Pull Request: https://github.com/llvm/llvm-project/pull/87830 --- bolt/lib/Profile/BoltAddressTranslation.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/bolt/lib/Profile/BoltAddressTranslation.cpp b/bolt/lib/Profile/BoltAddressTranslation.cpp index 90c62c13dcaa..59d499f97be7 100644 --- a/bolt/lib/Profile/BoltAddressTranslation.cpp +++ b/bolt/lib/Profile/BoltAddressTranslation.cpp @@ -208,7 +208,7 @@ void BoltAddressTranslation::writeMaps(std::map &Maps, LLVM_DEBUG(dbgs() << "Hash: " << formatv("{0:x}\n", BFHash)); OS.write(reinterpret_cast(&BFHash), 8); // Number of basic blocks - size_t NumBasicBlocks = getBBHashMap(HotInputAddress).getNumBasicBlocks(); + size_t NumBasicBlocks = NumBasicBlocksMap[HotInputAddress]; LLVM_DEBUG(dbgs() << "Basic blocks: " << NumBasicBlocks << '\n'); encodeULEB128(NumBasicBlocks, OS); // Secondary entry points @@ -426,8 +426,9 @@ void BoltAddressTranslation::dump(raw_ostream &OS) { for (const auto &MapEntry : Maps) { const uint64_t Address = MapEntry.first; const uint64_t HotAddress = fetchParentAddress(Address); + const bool IsHotFunction = HotAddress == 0; OS << "Function Address: 0x" << Twine::utohexstr(Address); - if (HotAddress == 0) + if (IsHotFunction) OS << formatv(", hash: {0:x}", getBFHash(Address)); OS << "\n"; OS << "BB mappings:\n"; @@ -444,6 +445,8 @@ void BoltAddressTranslation::dump(raw_ostream &OS) { OS << formatv(" hash: {0:x}", BBHashMap.getBBHash(Val)); OS << "\n"; } + if (IsHotFunction) + OS << "NumBlocks: " << NumBasicBlocksMap[Address] << '\n'; if (SecondaryEntryPointsMap.count(Address)) { const std::vector &SecondaryEntryPoints = SecondaryEntryPointsMap[Address]; @@ -575,6 +578,7 @@ void BoltAddressTranslation::saveMetadata(BinaryContext &BC) { // Set BF/BB metadata for (const BinaryBasicBlock &BB : BF) BBHashMap.addEntry(BB.getInputOffset(), BB.getIndex(), BB.getHash()); + NumBasicBlocksMap.emplace(BF.getAddress(), BF.size()); } } -- GitLab From ed4e505c219fe6c7464ea5a056e90d8cd94c7332 Mon Sep 17 00:00:00 2001 From: Mike Date: Sat, 6 Apr 2024 04:38:08 +0300 Subject: [PATCH 051/695] [clang-tidy] Fix readability-duplicate-include for includes with macro (#87433) Completely skip include directives that form the filename using macros. fixes #87303 --- .../readability/DuplicateIncludeCheck.cpp | 4 ++++ clang-tools-extra/docs/ReleaseNotes.rst | 4 ++++ .../checkers/readability/duplicate-include.cpp | 15 +++++++++++++++ 3 files changed, 23 insertions(+) diff --git a/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp b/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp index 67147164946a..229e5583846b 100644 --- a/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp @@ -79,6 +79,10 @@ void DuplicateIncludeCallbacks::InclusionDirective( bool IsAngled, CharSourceRange FilenameRange, OptionalFileEntryRef File, StringRef SearchPath, StringRef RelativePath, const Module *SuggestedModule, bool ModuleImported, SrcMgr::CharacteristicKind FileType) { + // Skip includes behind macros + if (FilenameRange.getBegin().isMacroID() || + FilenameRange.getEnd().isMacroID()) + return; if (llvm::is_contained(Files.back(), FileName)) { // We want to delete the entire line, so make sure that [Start,End] covers // everything. diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 456e09204fa2..34bad7e62463 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -255,6 +255,10 @@ Changes in existing checks analyzed, se the check now handles the common patterns `const auto e = (*vector_ptr)[i]` and `const auto e = vector_ptr->at(i);`. +- Improved :doc:`readability-duplicate-include + ` check by excluding include + directives that form the filename using macro. + - Improved :doc:`readability-identifier-naming ` check in `GetConfigPerFile` mode by resolving symbolic links to header files. Fixed handling of Hungarian diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/duplicate-include.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/duplicate-include.cpp index dd954c705514..2119602ba454 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/duplicate-include.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/duplicate-include.cpp @@ -70,3 +70,18 @@ int r; // CHECK-FIXES: {{^int q;$}} // CHECK-FIXES-NEXT: {{^#include $}} // CHECK-FIXES-NEXT: {{^int r;$}} + +namespace Issue_87303 { +#define RESET_INCLUDE_CACHE +// Expect no warnings + +#define MACRO_FILENAME "duplicate-include.h" +#include MACRO_FILENAME +#include "duplicate-include.h" + +#define MACRO_FILENAME_2 +#include +#include MACRO_FILENAME_2 + +#undef RESET_INCLUDE_CACHE +} // Issue_87303 -- GitLab From 0f52f4ddd909eb38f2a691ffed8469263fe5f635 Mon Sep 17 00:00:00 2001 From: Jeff Niu Date: Sat, 6 Apr 2024 05:01:37 +0300 Subject: [PATCH 052/695] [mlir][ods] Emit "trivial" ODS getter/setters inline (#87741) Emitting trivial getters that amount to `(*this)->getOperand(1)` out-of-line or `getProperties().foo` is a pretty significant performance hit on these basic MLIR APIs for manipulating ops (3-4x). Emit them inline (without adding additional dependencies to header files). --- mlir/include/mlir/TableGen/Class.h | 2 +- mlir/test/mlir-tblgen/op-attribute.td | 80 ++++++++-------- mlir/test/mlir-tblgen/op-decl-and-defs.td | 40 ++++---- mlir/test/mlir-tblgen/op-operand.td | 9 +- mlir/test/mlir-tblgen/op-properties.td | 6 +- mlir/test/mlir-tblgen/op-result.td | 9 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 101 ++++++++++++-------- 7 files changed, 135 insertions(+), 112 deletions(-) diff --git a/mlir/include/mlir/TableGen/Class.h b/mlir/include/mlir/TableGen/Class.h index 81cdf7dbef5f..92fec6a3b11d 100644 --- a/mlir/include/mlir/TableGen/Class.h +++ b/mlir/include/mlir/TableGen/Class.h @@ -681,7 +681,7 @@ public: Method *addMethod(RetTypeT &&retType, NameT &&name, Method::Properties properties, ArrayRef parameters) { - // If the class has template parameters, the has to defined inline. + // If the class has template parameters, then it has to be defined inline. if (!templateParams.empty()) properties |= Method::Inline; return addMethodAndPrune(Method(std::forward(retType), diff --git a/mlir/test/mlir-tblgen/op-attribute.td b/mlir/test/mlir-tblgen/op-attribute.td index b5b8619e7c9b..6f2d430fb6db 100644 --- a/mlir/test/mlir-tblgen/op-attribute.td +++ b/mlir/test/mlir-tblgen/op-attribute.td @@ -98,26 +98,26 @@ def AOp : NS_Op<"a_op", []> { // Test getter methods // --- -// DEF: some-attr-kind AOp::getAAttrAttr() -// DEF-NEXT: ::llvm::cast(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 0, (*this)->getAttrs().end() - 0, getAAttrAttrName())) +// DECL: some-attr-kind getAAttrAttr() +// DECL-NEXT: ::llvm::cast(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 0, (*this)->getAttrs().end() - 0, getAAttrAttrName())) // DEF: some-return-type AOp::getAAttr() { // DEF-NEXT: auto attr = getAAttrAttr() // DEF-NEXT: return attr.some-convert-from-storage(); -// DEF: some-attr-kind AOp::getBAttrAttr() -// DEF-NEXT: ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 1, (*this)->getAttrs().end() - 0, getBAttrAttrName())) +// DECL: some-attr-kind getBAttrAttr() +// DECL-NEXT: ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 1, (*this)->getAttrs().end() - 0, getBAttrAttrName())) // DEF: some-return-type AOp::getBAttr() { // DEF-NEXT: auto attr = getBAttrAttr(); // DEF-NEXT: return attr.some-convert-from-storage(); -// DEF: some-attr-kind AOp::getCAttrAttr() -// DEF-NEXT: ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 1, (*this)->getAttrs().end() - 0, getCAttrAttrName())) +// DECL: some-attr-kind getCAttrAttr() +// DECL-NEXT: ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 1, (*this)->getAttrs().end() - 0, getCAttrAttrName())) // DEF: ::std::optional AOp::getCAttr() { // DEF-NEXT: auto attr = getCAttrAttr() // DEF-NEXT: return attr ? ::std::optional(attr.some-convert-from-storage()) : (::std::nullopt); -// DEF: some-attr-kind AOp::getDAttrAttr() -// DEF-NEXT: ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 1, (*this)->getAttrs().end() - 0, getDAttrAttrName())) +// DECL: some-attr-kind getDAttrAttr() +// DECL-NEXT: ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange((*this)->getAttrs().begin() + 1, (*this)->getAttrs().end() - 0, getDAttrAttrName())) // DEF: some-return-type AOp::getDAttr() { // DEF-NEXT: auto attr = getDAttrAttr(); // DEF-NEXT: if (!attr) @@ -127,16 +127,16 @@ def AOp : NS_Op<"a_op", []> { // Test setter methods // --- -// DEF: void AOp::setAAttrAttr(some-attr-kind attr) { -// DEF-NEXT: (*this)->setAttr(getAAttrAttrName(), attr); +// DECL: void setAAttrAttr(some-attr-kind attr) { +// DECL-NEXT: (*this)->setAttr(getAAttrAttrName(), attr); // DEF: void AOp::setAAttr(some-return-type attrValue) { // DEF-NEXT: (*this)->setAttr(getAAttrAttrName(), some-const-builder-call(::mlir::Builder((*this)->getContext()), attrValue)); -// DEF: void AOp::setBAttrAttr(some-attr-kind attr) { -// DEF-NEXT: (*this)->setAttr(getBAttrAttrName(), attr); +// DECL: void setBAttrAttr(some-attr-kind attr) { +// DECL-NEXT: (*this)->setAttr(getBAttrAttrName(), attr); // DEF: void AOp::setBAttr(some-return-type attrValue) { // DEF-NEXT: (*this)->setAttr(getBAttrAttrName(), some-const-builder-call(::mlir::Builder((*this)->getContext()), attrValue)); -// DEF: void AOp::setCAttrAttr(some-attr-kind attr) { -// DEF-NEXT: (*this)->setAttr(getCAttrAttrName(), attr); +// DECL: void setCAttrAttr(some-attr-kind attr) { +// DECL-NEXT: (*this)->setAttr(getCAttrAttrName(), attr); // DEF: void AOp::setCAttr(::std::optional attrValue) { // DEF-NEXT: if (attrValue) // DEF-NEXT: return (*this)->setAttr(getCAttrAttrName(), some-const-builder-call(::mlir::Builder((*this)->getContext()), *attrValue)); @@ -145,8 +145,8 @@ def AOp : NS_Op<"a_op", []> { // Test remove methods // --- -// DEF: ::mlir::Attribute AOp::removeCAttrAttr() { -// DEF-NEXT: return (*this)->removeAttr(getCAttrAttrName()); +// DECL: ::mlir::Attribute removeCAttrAttr() { +// DECL-NEXT: return (*this)->removeAttr(getCAttrAttrName()); // Test build methods // --- @@ -236,22 +236,22 @@ def AgetOp : Op { // Test getter methods // --- -// DEF: some-attr-kind AgetOp::getAAttrAttr() -// DEF-NEXT: ::llvm::cast(::mlir::impl::getAttrFromSortedRange({{.*}})) +// DECL: some-attr-kind getAAttrAttr() +// DECL-NEXT: ::llvm::cast(::mlir::impl::getAttrFromSortedRange({{.*}})) // DEF: some-return-type AgetOp::getAAttr() { // DEF-NEXT: auto attr = getAAttrAttr() // DEF-NEXT: return attr.some-convert-from-storage(); -// DEF: some-attr-kind AgetOp::getBAttrAttr() -// DEF-NEXT: return ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange({{.*}})) +// DECL: some-attr-kind getBAttrAttr() +// DECL-NEXT: return ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange({{.*}})) // DEF: some-return-type AgetOp::getBAttr() { // DEF-NEXT: auto attr = getBAttrAttr(); // DEF-NEXT: if (!attr) // DEF-NEXT: return some-const-builder-call(::mlir::Builder((*this)->getContext()), 4.2).some-convert-from-storage(); // DEF-NEXT: return attr.some-convert-from-storage(); -// DEF: some-attr-kind AgetOp::getCAttrAttr() -// DEF-NEXT: return ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange({{.*}})) +// DECL: some-attr-kind getCAttrAttr() +// DECL-NEXT: return ::llvm::dyn_cast_or_null(::mlir::impl::getAttrFromSortedRange({{.*}})) // DEF: ::std::optional AgetOp::getCAttr() { // DEF-NEXT: auto attr = getCAttrAttr() // DEF-NEXT: return attr ? ::std::optional(attr.some-convert-from-storage()) : (::std::nullopt); @@ -259,18 +259,18 @@ def AgetOp : Op { // Test setter methods // --- -// DEF: void AgetOp::setAAttrAttr(some-attr-kind attr) { -// DEF-NEXT: (*this)->setAttr(getAAttrAttrName(), attr); -// DEF: void AgetOp::setBAttrAttr(some-attr-kind attr) { -// DEF-NEXT: (*this)->setAttr(getBAttrAttrName(), attr); -// DEF: void AgetOp::setCAttrAttr(some-attr-kind attr) { -// DEF-NEXT: (*this)->setAttr(getCAttrAttrName(), attr); +// DECL: void setAAttrAttr(some-attr-kind attr) { +// DECL-NEXT: (*this)->setAttr(getAAttrAttrName(), attr); +// DECL: void setBAttrAttr(some-attr-kind attr) { +// DECL-NEXT: (*this)->setAttr(getBAttrAttrName(), attr); +// DECL: void setCAttrAttr(some-attr-kind attr) { +// DECL-NEXT: (*this)->setAttr(getCAttrAttrName(), attr); // Test remove methods // --- -// DEF: ::mlir::Attribute AgetOp::removeCAttrAttr() { -// DEF-NEXT: return (*this)->removeAttr(getCAttrAttrName()); +// DECL: ::mlir::Attribute removeCAttrAttr() { +// DECL-NEXT: return (*this)->removeAttr(getCAttrAttrName()); // Test build methods // --- @@ -476,9 +476,6 @@ def NamespaceOp : NS_Op<"namespace_op", []> { SomeAttrDef:$AttrDef ); } -// DECL: NamespaceOp -// DECL: foobar::SomeAttrAttr getAttrDef() - // Test mixing operands and attributes in arbitrary order // --- @@ -487,6 +484,14 @@ def MixOperandsAndAttrs : NS_Op<"mix_operands_and_attrs", []> { let arguments = (ins F32Attr:$attr, F32:$operand, F32Attr:$otherAttr, F32:$otherArg); } +// DECL-LABEL: MixOperandsAndAttrs declarations +// DECL-DAG: ::mlir::TypedValue<::mlir::FloatType> getOperand() +// DECL-DAG: ::mlir::TypedValue<::mlir::FloatType> getOtherArg() + +// DECL-LABEL: NamespaceOp declarations +// DECL: foobar::SomeAttrAttr getAttrDef() + + def OpWithDefaultAndRegion : NS_Op<"default_with_region", []> { let arguments = (ins DefaultValuedAttr:$dv_bool_attr @@ -509,11 +514,9 @@ def OpWithDefaultAndSuccessor : NS_Op<"default_with_succ", []> { // We should not have a default attribute in this case. // DECL-LABEL: OpWithDefaultAndSuccessor declarations -// DECL: static void build({{.*}}, bool dv_bool_attr, ::mlir::BlockRange succ) +// DECL-DAG: static void build({{.*}}, bool dv_bool_attr, ::mlir::BlockRange succ) // DEF-LABEL: MixOperandsAndAttrs definitions -// DEF-DAG: ::mlir::TypedValue<::mlir::FloatType> MixOperandsAndAttrs::getOperand() -// DEF-DAG: ::mlir::TypedValue<::mlir::FloatType> MixOperandsAndAttrs::getOtherArg() // DEF-DAG: void MixOperandsAndAttrs::build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::FloatAttr attr, ::mlir::Value operand, ::mlir::FloatAttr otherAttr, ::mlir::Value otherArg) // DEF-DAG: ::llvm::APFloat MixOperandsAndAttrs::getAttr() // DEF-DAG: ::llvm::APFloat MixOperandsAndAttrs::getOtherAttr() @@ -529,14 +532,13 @@ def UnitAttrOp : NS_Op<"unit_attr_op", []> { // DEF: bool UnitAttrOp::getAttr() { // DEF: return {{.*}} != nullptr -// DEF: ::mlir::Attribute UnitAttrOp::removeAttrAttr() { -// DEF-NEXT: (*this)->removeAttr(getAttrAttrName()); // DEF: build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, /*optional*/::mlir::UnitAttr attr) // DEF: build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, /*optional*/bool attr) // DECL-LABEL: UnitAttrOp declarations -// DECL-NOT: declarations +// DECL: ::mlir::Attribute removeAttrAttr() { +// DECL-NEXT: (*this)->removeAttr(getAttrAttrName()); // DECL: build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, /*optional*/bool attr = false) diff --git a/mlir/test/mlir-tblgen/op-decl-and-defs.td b/mlir/test/mlir-tblgen/op-decl-and-defs.td index ca133fafdcb5..4fa2f308978a 100644 --- a/mlir/test/mlir-tblgen/op-decl-and-defs.td +++ b/mlir/test/mlir-tblgen/op-decl-and-defs.td @@ -59,12 +59,12 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove, IsolatedFromAbove]> { // CHECK: class AOpGenericAdaptorBase { // CHECK: public: // CHECK: AOpGenericAdaptorBase(AOp{{[[:space:]]}} -// CHECK: ::mlir::IntegerAttr getAttr1Attr(); +// CHECK: ::mlir::IntegerAttr getAttr1Attr() { // CHECK: uint32_t getAttr1(); -// CHECK: ::mlir::FloatAttr getSomeAttr2Attr(); +// CHECK: ::mlir::FloatAttr getSomeAttr2Attr() { // CHECK: ::std::optional< ::llvm::APFloat > getSomeAttr2(); -// CHECK: ::mlir::Region &getSomeRegion(); -// CHECK: ::mlir::RegionRange getSomeRegions(); +// CHECK: ::mlir::Region &getSomeRegion() { +// CHECK: ::mlir::RegionRange getSomeRegions() { // CHECK: }; // CHECK: } @@ -94,20 +94,20 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove, IsolatedFromAbove]> { // CHECK: static constexpr ::llvm::StringLiteral getOperationName() { // CHECK: return ::llvm::StringLiteral("test.a_op"); // CHECK: } -// CHECK: ::mlir::Operation::operand_range getODSOperands(unsigned index); -// CHECK: ::mlir::TypedValue<::mlir::IntegerType> getA(); -// CHECK: ::mlir::Operation::operand_range getB(); -// CHECK: ::mlir::OpOperand &getAMutable(); +// CHECK: ::mlir::Operation::operand_range getODSOperands(unsigned index) { +// CHECK: ::mlir::TypedValue<::mlir::IntegerType> getA() { +// CHECK: ::mlir::Operation::operand_range getB() { +// CHECK: ::mlir::OpOperand &getAMutable() { // CHECK: ::mlir::MutableOperandRange getBMutable(); -// CHECK: ::mlir::Operation::result_range getODSResults(unsigned index); -// CHECK: ::mlir::TypedValue<::mlir::IntegerType> getR(); -// CHECK: ::mlir::Region &getSomeRegion(); -// CHECK: ::mlir::MutableArrayRef<::mlir::Region> getSomeRegions(); -// CHECK: ::mlir::IntegerAttr getAttr1Attr() +// CHECK: ::mlir::Operation::result_range getODSResults(unsigned index) { +// CHECK: ::mlir::TypedValue<::mlir::IntegerType> getR() { +// CHECK: ::mlir::Region &getSomeRegion() { +// CHECK: ::mlir::MutableArrayRef<::mlir::Region> getSomeRegions() { +// CHECK: ::mlir::IntegerAttr getAttr1Attr() { // CHECK: uint32_t getAttr1(); -// CHECK: ::mlir::FloatAttr getSomeAttr2Attr() +// CHECK: ::mlir::FloatAttr getSomeAttr2Attr() { // CHECK: ::std::optional< ::llvm::APFloat > getSomeAttr2(); -// CHECK: ::mlir::Attribute removeSomeAttr2Attr(); +// CHECK: ::mlir::Attribute removeSomeAttr2Attr() { // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, Value val); // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, int integer = 0); // CHECK{LITERAL}: [[deprecated("the deprecation message")]] @@ -137,9 +137,9 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove, IsolatedFromAbove]> { // DEFS-SAME: p.getProperties() // DEFS-SAME: op->getRegions() -// DEFS: ::mlir::RegionRange AOpGenericAdaptorBase::getSomeRegions() -// DEFS-NEXT: return odsRegions.drop_front(1); -// DEFS: ::mlir::RegionRange AOpGenericAdaptorBase::getRegions() +// DECLS: ::mlir::RegionRange AOpGenericAdaptorBase::getSomeRegions() +// DECLS-NEXT: return odsRegions.drop_front(1); +// DECLS: ::mlir::RegionRange AOpGenericAdaptorBase::getRegions() // Check AttrSizedOperandSegments // --- @@ -196,9 +196,9 @@ def NS_EOp : NS_Op<"op_with_optionals", []> { } // CHECK-LABEL: NS::EOp declarations -// CHECK: ::mlir::TypedValue<::mlir::IntegerType> getA(); +// CHECK: ::mlir::TypedValue<::mlir::IntegerType> getA() { // CHECK: ::mlir::MutableOperandRange getAMutable(); -// CHECK: ::mlir::TypedValue<::mlir::FloatType> getB(); +// CHECK: ::mlir::TypedValue<::mlir::FloatType> getB() { // CHECK: static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, /*optional*/::mlir::Type b, /*optional*/::mlir::Value a) // Check that all types match constraint results in generating builder. diff --git a/mlir/test/mlir-tblgen/op-operand.td b/mlir/test/mlir-tblgen/op-operand.td index 68a9def83c2e..a74970824479 100644 --- a/mlir/test/mlir-tblgen/op-operand.td +++ b/mlir/test/mlir-tblgen/op-operand.td @@ -1,4 +1,5 @@ // RUN: mlir-tblgen -gen-op-defs -I %S/../../include %s | FileCheck %s +// RUN: mlir-tblgen -gen-op-decls -I %S/../../include %s | FileCheck %s --check-prefix=DECL include "mlir/IR/OpBase.td" @@ -39,11 +40,11 @@ def OpD : NS_Op<"mix_variadic_and_normal_inputs_op", [SameVariadicOperandSize]> let arguments = (ins Variadic:$input1, AnyTensor:$input2, Variadic:$input3); } -// CHECK-LABEL: ::mlir::Operation::operand_range OpD::getInput1 -// CHECK-NEXT: return getODSOperands(0); +// DECL-LABEL: ::mlir::Operation::operand_range getInput1 +// DECL-NEXT: return getODSOperands(0); -// CHECK-LABEL: ::mlir::TypedValue<::mlir::TensorType> OpD::getInput2 -// CHECK-NEXT: return ::llvm::cast<::mlir::TypedValue<::mlir::TensorType>>(*getODSOperands(1).begin()); +// DECL-LABEL: ::mlir::TypedValue<::mlir::TensorType> getInput2 +// DECL-NEXT: return ::llvm::cast<::mlir::TypedValue<::mlir::TensorType>>(*getODSOperands(1).begin()); // CHECK-LABEL: OpD::build // CHECK-NEXT: odsState.addOperands(input1); diff --git a/mlir/test/mlir-tblgen/op-properties.td b/mlir/test/mlir-tblgen/op-properties.td index a484f68fc4a1..7b0ee6b2a1bd 100644 --- a/mlir/test/mlir-tblgen/op-properties.td +++ b/mlir/test/mlir-tblgen/op-properties.td @@ -1,4 +1,4 @@ -// RUN: mlir-tblgen -gen-op-defs -I %S/../../include %s | FileCheck %s +// RUN: mlir-tblgen -gen-op-decls -I %S/../../include %s | FileCheck %s include "mlir/IR/AttrTypeBase.td" include "mlir/IR/EnumAttr.td" @@ -15,7 +15,7 @@ def OpWithAttr : NS_Op<"op_with_attr">{ let arguments = (ins AnyAttr:$attr, OptionalAttr:$optional); } -// CHECK: void OpWithAttr::setAttrAttr(::mlir::Attribute attr) +// CHECK: void setAttrAttr(::mlir::Attribute attr) // CHECK-NEXT: getProperties().attr = attr -// CHECK: void OpWithAttr::setOptionalAttr(::mlir::Attribute attr) +// CHECK: void setOptionalAttr(::mlir::Attribute attr) // CHECK-NEXT: getProperties().optional = attr diff --git a/mlir/test/mlir-tblgen/op-result.td b/mlir/test/mlir-tblgen/op-result.td index a4a3764aae2b..0ca570cf8caf 100644 --- a/mlir/test/mlir-tblgen/op-result.td +++ b/mlir/test/mlir-tblgen/op-result.td @@ -1,4 +1,5 @@ // RUN: mlir-tblgen -gen-op-defs -I %S/../../include %s | FileCheck %s +// RUN: mlir-tblgen -gen-op-decls -I %S/../../include %s | FileCheck %s --check-prefix=DECL include "mlir/IR/OpBase.td" include "mlir/Interfaces/InferTypeOpInterface.td" @@ -97,11 +98,11 @@ def OpI : NS_Op<"mix_variadic_and_normal_results_op", [SameVariadicResultSize]> let results = (outs Variadic:$output1, AnyTensor:$output2, Variadic:$output3); } -// CHECK-LABEL: ::mlir::Operation::result_range OpI::getOutput1 -// CHECK-NEXT: return getODSResults(0); +// DECL-LABEL: ::mlir::Operation::result_range getOutput1 +// DECL-NEXT: return getODSResults(0); -// CHECK-LABEL: ::mlir::TypedValue<::mlir::TensorType> OpI::getOutput2 -// CHECK-NEXT: return ::llvm::cast<::mlir::TypedValue<::mlir::TensorType>>(*getODSResults(1).begin()); +// DECL-LABEL: ::mlir::TypedValue<::mlir::TensorType> getOutput2 +// DECL-NEXT: return ::llvm::cast<::mlir::TypedValue<::mlir::TensorType>>(*getODSResults(1).begin()); // CHECK-LABEL: OpI::build // CHECK-NEXT: odsState.addTypes(output1); diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp index 843760d57c99..5739c7e1124f 100644 --- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp +++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp @@ -1712,7 +1712,9 @@ void OpEmitter::genAttrGetters() { // having to use the string interface for better compile time verification. auto emitAttrWithStorageType = [&](StringRef name, StringRef attrName, Attribute attr) { - auto *method = opClass.addMethod(attr.getStorageType(), name + "Attr"); + // The method body for this getter is trivial. Emit it inline. + auto *method = + opClass.addInlineMethod(attr.getStorageType(), name + "Attr"); if (!method) return; method->body() << formatv( @@ -1823,9 +1825,10 @@ void OpEmitter::genAttrSetters() { // for better compile time verification. auto emitAttrWithStorageType = [&](StringRef setterName, StringRef getterName, StringRef attrName, Attribute attr) { + // This method body is trivial, so emit it inline. auto *method = - opClass.addMethod("void", setterName + "Attr", - MethodParameter(attr.getStorageType(), "attr")); + opClass.addInlineMethod("void", setterName + "Attr", + MethodParameter(attr.getStorageType(), "attr")); if (method) emitSetAttr(method, getterName, attrName, "attr"); }; @@ -1912,8 +1915,8 @@ void OpEmitter::genOptionalAttrRemovers() { // use the string interface. Enables better compile time verification. auto emitRemoveAttr = [&](StringRef name, bool useProperties) { auto upperInitial = name.take_front().upper(); - auto *method = opClass.addMethod("::mlir::Attribute", - op.getRemoverName(name) + "Attr"); + auto *method = opClass.addInlineMethod("::mlir::Attribute", + op.getRemoverName(name) + "Attr"); if (!method) return; if (useProperties) { @@ -1952,7 +1955,11 @@ static void generateValueRangeStartAndEnd( rangeSizeCall = "odsOperandsSize"; } + // The method is trivial if the operation does not have any variadic operands. + // In that case, make sure to generate it in-line. auto *method = opClass.addMethod("std::pair", methodName, + numVariadic == 0 ? Method::Properties::Inline + : Method::Properties::None, parameters); if (!method) return; @@ -2054,17 +2061,19 @@ generateNamedOperandGetters(const Operator &op, Class &opClass, // Generate trampoline for calling 'getODSOperandIndexAndLength' with just // the index. This just calls the implementation in the base class but // passes the operand size as parameter. - Method *method = opClass.addMethod("std::pair", - "getODSOperandIndexAndLength", - MethodParameter("unsigned", "index")); + Method *method = opClass.addInlineMethod( + "std::pair", "getODSOperandIndexAndLength", + MethodParameter("unsigned", "index")); ERROR_IF_PRUNED(method, "getODSOperandIndexAndLength", op); MethodBody &body = method->body(); body.indent() << formatv( "return Base::getODSOperandIndexAndLength(index, {0});", rangeSizeCall); } - auto *m = opClass.addMethod(rangeType, "getODSOperands", - MethodParameter("unsigned", "index")); + // The implementation of this method is trivial and it is very load-bearing. + // Generate it inline. + auto *m = opClass.addInlineMethod(rangeType, "getODSOperands", + MethodParameter("unsigned", "index")); ERROR_IF_PRUNED(m, "getODSOperands", op); auto &body = m->body(); body << formatv(valueRangeReturnCode, rangeBeginCall, @@ -2078,10 +2087,10 @@ generateNamedOperandGetters(const Operator &op, Class &opClass, continue; std::string name = op.getGetterName(operand.name); if (operand.isOptional()) { - m = opClass.addMethod(isGenericAdaptorBase - ? rangeElementType - : generateTypeForGetter(operand), - name); + m = opClass.addInlineMethod(isGenericAdaptorBase + ? rangeElementType + : generateTypeForGetter(operand), + name); ERROR_IF_PRUNED(m, name, op); m->body().indent() << formatv("auto operands = getODSOperands({0});\n" "return operands.empty() ? {1}{{} : ", @@ -2100,19 +2109,19 @@ generateNamedOperandGetters(const Operator &op, Class &opClass, continue; } - m = opClass.addMethod("::mlir::OperandRangeRange", name); + m = opClass.addInlineMethod("::mlir::OperandRangeRange", name); ERROR_IF_PRUNED(m, name, op); m->body() << " return getODSOperands(" << i << ").split(" << segmentAttr << "Attr());"; } else if (operand.isVariadic()) { - m = opClass.addMethod(rangeType, name); + m = opClass.addInlineMethod(rangeType, name); ERROR_IF_PRUNED(m, name, op); m->body() << " return getODSOperands(" << i << ");"; } else { - m = opClass.addMethod(isGenericAdaptorBase - ? rangeElementType - : generateTypeForGetter(operand), - name); + m = opClass.addInlineMethod(isGenericAdaptorBase + ? rangeElementType + : generateTypeForGetter(operand), + name); ERROR_IF_PRUNED(m, name, op); m->body().indent() << "return "; if (!isGenericAdaptorBase) @@ -2164,12 +2173,16 @@ void OpEmitter::genNamedOperandSetters() { } else { returnType = "::mlir::OpOperand &"; } - auto *m = opClass.addMethod(returnType, name + "Mutable"); + bool isVariadicOperand = + operand.isVariadicOfVariadic() || operand.isVariableLength(); + auto *m = opClass.addMethod(returnType, name + "Mutable", + isVariadicOperand ? Method::Properties::None + : Method::Properties::Inline); ERROR_IF_PRUNED(m, name, op); auto &body = m->body(); body << " auto range = getODSOperandIndexAndLength(" << i << ");\n"; - if (!operand.isVariadicOfVariadic() && !operand.isVariableLength()) { + if (!isVariadicOperand) { // In case of a single operand, return a single OpOperand. body << " return getOperation()->getOpOperand(range.first);\n"; continue; @@ -2254,9 +2267,11 @@ void OpEmitter::genNamedResultGetters() { numVariadicResults, numNormalResults, "getOperation()->getNumResults()", attrSizedResults, attrSizeInitCode, op.getResults()); - auto *m = - opClass.addMethod("::mlir::Operation::result_range", "getODSResults", - MethodParameter("unsigned", "index")); + // The implementation of this method is trivial and it is very load-bearing. + // Generate it inline. + auto *m = opClass.addInlineMethod("::mlir::Operation::result_range", + "getODSResults", + MethodParameter("unsigned", "index")); ERROR_IF_PRUNED(m, "getODSResults", op); m->body() << formatv(valueRangeReturnCode, "getOperation()->result_begin()", "getODSResultIndexAndLength(index)"); @@ -2267,7 +2282,7 @@ void OpEmitter::genNamedResultGetters() { continue; std::string name = op.getGetterName(result.name); if (result.isOptional()) { - m = opClass.addMethod(generateTypeForGetter(result), name); + m = opClass.addInlineMethod(generateTypeForGetter(result), name); ERROR_IF_PRUNED(m, name, op); m->body() << " auto results = getODSResults(" << i << ");\n" << llvm::formatv(" return results.empty()" @@ -2275,11 +2290,11 @@ void OpEmitter::genNamedResultGetters() { " : ::llvm::cast<{0}>(*results.begin());", m->getReturnType()); } else if (result.isVariadic()) { - m = opClass.addMethod("::mlir::Operation::result_range", name); + m = opClass.addInlineMethod("::mlir::Operation::result_range", name); ERROR_IF_PRUNED(m, name, op); m->body() << " return getODSResults(" << i << ");"; } else { - m = opClass.addMethod(generateTypeForGetter(result), name); + m = opClass.addInlineMethod(generateTypeForGetter(result), name); ERROR_IF_PRUNED(m, name, op); m->body() << llvm::formatv( " return ::llvm::cast<{0}>(*getODSResults({1}).begin());", @@ -2298,15 +2313,15 @@ void OpEmitter::genNamedRegionGetters() { // Generate the accessors for a variadic region. if (region.isVariadic()) { - auto *m = - opClass.addMethod("::mlir::MutableArrayRef<::mlir::Region>", name); + auto *m = opClass.addInlineMethod( + "::mlir::MutableArrayRef<::mlir::Region>", name); ERROR_IF_PRUNED(m, name, op); m->body() << formatv(" return (*this)->getRegions().drop_front({0});", i); continue; } - auto *m = opClass.addMethod("::mlir::Region &", name); + auto *m = opClass.addInlineMethod("::mlir::Region &", name); ERROR_IF_PRUNED(m, name, op); m->body() << formatv(" return (*this)->getRegion({0});", i); } @@ -2321,7 +2336,7 @@ void OpEmitter::genNamedSuccessorGetters() { std::string name = op.getGetterName(successor.name); // Generate the accessors for a variadic successor list. if (successor.isVariadic()) { - auto *m = opClass.addMethod("::mlir::SuccessorRange", name); + auto *m = opClass.addInlineMethod("::mlir::SuccessorRange", name); ERROR_IF_PRUNED(m, name, op); m->body() << formatv( " return {std::next((*this)->successor_begin(), {0}), " @@ -2330,7 +2345,7 @@ void OpEmitter::genNamedSuccessorGetters() { continue; } - auto *m = opClass.addMethod("::mlir::Block *", name); + auto *m = opClass.addInlineMethod("::mlir::Block *", name); ERROR_IF_PRUNED(m, name, op); m->body() << formatv(" return (*this)->getSuccessor({0});", i); } @@ -4148,8 +4163,12 @@ OpOperandAdaptorEmitter::OpOperandAdaptorEmitter( // Generate named accessor with Attribute return type. auto emitAttrWithStorageType = [&](StringRef name, StringRef emitName, Attribute attr) { - auto *method = - genericAdaptorBase.addMethod(attr.getStorageType(), emitName + "Attr"); + // The method body is trivial if the attribute does not have a default + // value, in which case the default value may be arbitrary code. + auto *method = genericAdaptorBase.addMethod( + attr.getStorageType(), emitName + "Attr", + attr.hasDefaultValue() ? Method::Properties::None + : Method::Properties::Inline); ERROR_IF_PRUNED(method, "Adaptor::" + emitName + "Attr", op); auto &body = method->body().indent(); if (!useProperties) @@ -4179,8 +4198,8 @@ OpOperandAdaptorEmitter::OpOperandAdaptorEmitter( m->body() << " return properties;"; } { - auto *m = - genericAdaptorBase.addMethod("::mlir::DictionaryAttr", "getAttributes"); + auto *m = genericAdaptorBase.addInlineMethod("::mlir::DictionaryAttr", + "getAttributes"); ERROR_IF_PRUNED(m, "Adaptor::getAttributes", op); m->body() << " return odsAttrs;"; } @@ -4203,21 +4222,21 @@ OpOperandAdaptorEmitter::OpOperandAdaptorEmitter( // Generate the accessors for a variadic region. std::string name = op.getGetterName(region.name); if (region.isVariadic()) { - auto *m = genericAdaptorBase.addMethod("::mlir::RegionRange", name); + auto *m = genericAdaptorBase.addInlineMethod("::mlir::RegionRange", name); ERROR_IF_PRUNED(m, "Adaptor::" + name, op); m->body() << formatv(" return odsRegions.drop_front({0});", i); continue; } - auto *m = genericAdaptorBase.addMethod("::mlir::Region &", name); + auto *m = genericAdaptorBase.addInlineMethod("::mlir::Region &", name); ERROR_IF_PRUNED(m, "Adaptor::" + name, op); m->body() << formatv(" return *odsRegions[{0}];", i); } if (numRegions > 0) { // Any invalid overlap for `getRegions` will have been diagnosed before // here already. - if (auto *m = - genericAdaptorBase.addMethod("::mlir::RegionRange", "getRegions")) + if (auto *m = genericAdaptorBase.addInlineMethod("::mlir::RegionRange", + "getRegions")) m->body() << " return odsRegions;"; } -- GitLab From c8f3d211fc428dd6075440ac22f48641436545d0 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Fri, 5 Apr 2024 22:40:18 -0400 Subject: [PATCH 053/695] [ADT] Allow reverse to find free rbegin/rend functions (#87840) Lift the requirement that rbegin/rend must be member functions. Also allow the rbegin/rend to be found through Argument Dependent Lookup (ADL) and add `adl_rbegin`/`adl_rend` to STLExtras. --- llvm/include/llvm/ADT/ADL.h | 32 ++++++++++++++++++++++++ llvm/include/llvm/ADT/STLExtras.h | 33 +++++++++---------------- llvm/unittests/ADT/IteratorTest.cpp | 15 +++++++++++ llvm/unittests/ADT/RangeAdapterTest.cpp | 4 --- llvm/unittests/ADT/STLExtrasTest.cpp | 10 ++++++++ 5 files changed, 69 insertions(+), 25 deletions(-) diff --git a/llvm/include/llvm/ADT/ADL.h b/llvm/include/llvm/ADT/ADL.h index ab1f28ff6b9c..812d9a4b52d8 100644 --- a/llvm/include/llvm/ADT/ADL.h +++ b/llvm/include/llvm/ADT/ADL.h @@ -37,6 +37,22 @@ constexpr auto end_impl(RangeT &&range) return end(std::forward(range)); } +using std::rbegin; + +template +constexpr auto rbegin_impl(RangeT &&range) + -> decltype(rbegin(std::forward(range))) { + return rbegin(std::forward(range)); +} + +using std::rend; + +template +constexpr auto rend_impl(RangeT &&range) + -> decltype(rend(std::forward(range))) { + return rend(std::forward(range)); +} + using std::swap; template @@ -72,6 +88,22 @@ constexpr auto adl_end(RangeT &&range) return adl_detail::end_impl(std::forward(range)); } +/// Returns the reverse-begin iterator to \p range using `std::rbegin` and +/// function found through Argument-Dependent Lookup (ADL). +template +constexpr auto adl_rbegin(RangeT &&range) + -> decltype(adl_detail::rbegin_impl(std::forward(range))) { + return adl_detail::rbegin_impl(std::forward(range)); +} + +/// Returns the reverse-end iterator to \p range using `std::rend` and +/// functions found through Argument-Dependent Lookup (ADL). +template +constexpr auto adl_rend(RangeT &&range) + -> decltype(adl_detail::rend_impl(std::forward(range))) { + return adl_detail::rend_impl(std::forward(range)); +} + /// Swaps \p lhs with \p rhs using `std::swap` and functions found through /// Argument-Dependent Lookup (ADL). template diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index b5eb319ccf34..08a708e5c587 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -405,32 +405,23 @@ public: } }; -/// Helper to determine if type T has a member called rbegin(). -template class has_rbegin_impl { - using yes = char[1]; - using no = char[2]; - - template - static yes& test(Inner *I, decltype(I->rbegin()) * = nullptr); - - template - static no& test(...); - -public: - static const bool value = sizeof(test(nullptr)) == sizeof(yes); -}; +namespace detail { +template +using check_has_free_function_rbegin = + decltype(adl_rbegin(std::declval())); -/// Metafunction to determine if T& or T has a member called rbegin(). -template -struct has_rbegin : has_rbegin_impl> {}; +template +static constexpr bool HasFreeFunctionRBegin = + is_detected::value; +} // namespace detail // Returns an iterator_range over the given container which iterates in reverse. template auto reverse(ContainerTy &&C) { - if constexpr (has_rbegin::value) - return make_range(C.rbegin(), C.rend()); + if constexpr (detail::HasFreeFunctionRBegin) + return make_range(adl_rbegin(C), adl_rend(C)); else - return make_range(std::make_reverse_iterator(std::end(C)), - std::make_reverse_iterator(std::begin(C))); + return make_range(std::make_reverse_iterator(adl_end(C)), + std::make_reverse_iterator(adl_begin(C))); } /// An iterator adaptor that filters the elements of given inner iterators. diff --git a/llvm/unittests/ADT/IteratorTest.cpp b/llvm/unittests/ADT/IteratorTest.cpp index 3a4a5b02b104..a0d3c9b564d8 100644 --- a/llvm/unittests/ADT/IteratorTest.cpp +++ b/llvm/unittests/ADT/IteratorTest.cpp @@ -395,6 +395,21 @@ TEST(PointerIterator, Range) { EXPECT_EQ(A + I++, P); } +namespace rbegin_detail { +struct WithFreeRBegin { + int data[3] = {42, 43, 44}; +}; + +auto rbegin(const WithFreeRBegin &X) { return std::rbegin(X.data); } +auto rend(const WithFreeRBegin &X) { return std::rend(X.data); } +} // namespace rbegin_detail + +TEST(ReverseTest, ADL) { + // Check that we can find the rbegin/rend functions via ADL. + rbegin_detail::WithFreeRBegin Foo; + EXPECT_THAT(reverse(Foo), ElementsAre(44, 43, 42)); +} + TEST(ZipIteratorTest, Basic) { using namespace std; const SmallVector pi{3, 1, 4, 1, 5, 9}; diff --git a/llvm/unittests/ADT/RangeAdapterTest.cpp b/llvm/unittests/ADT/RangeAdapterTest.cpp index eb75ac301805..c1a8a984f233 100644 --- a/llvm/unittests/ADT/RangeAdapterTest.cpp +++ b/llvm/unittests/ADT/RangeAdapterTest.cpp @@ -150,10 +150,6 @@ TYPED_TEST(RangeAdapterRValueTest, TrivialOperation) { TestRev(reverse(TypeParam({0, 1, 2, 3}))); } -TYPED_TEST(RangeAdapterRValueTest, HasRbegin) { - static_assert(has_rbegin::value, "rbegin() should be defined"); -} - TYPED_TEST(RangeAdapterRValueTest, RangeType) { static_assert( std::is_same_v()).begin()), diff --git a/llvm/unittests/ADT/STLExtrasTest.cpp b/llvm/unittests/ADT/STLExtrasTest.cpp index b73891b59f02..3927bc59c031 100644 --- a/llvm/unittests/ADT/STLExtrasTest.cpp +++ b/llvm/unittests/ADT/STLExtrasTest.cpp @@ -405,6 +405,14 @@ std::vector::const_iterator end(const some_struct &s) { return s.data.end(); } +std::vector::const_reverse_iterator rbegin(const some_struct &s) { + return s.data.rbegin(); +} + +std::vector::const_reverse_iterator rend(const some_struct &s) { + return s.data.rend(); +} + void swap(some_struct &lhs, some_struct &rhs) { // make swap visible as non-adl swap would even seem to // work with std::swap which defaults to moving @@ -573,6 +581,8 @@ TEST(STLExtrasTest, ADLTest) { EXPECT_EQ(*adl_begin(s), 1); EXPECT_EQ(*(adl_end(s) - 1), 5); + EXPECT_EQ(*adl_rbegin(s), 5); + EXPECT_EQ(*(adl_rend(s) - 1), 1); adl_swap(s, s2); EXPECT_EQ(s.swap_val, "lhs"); -- GitLab From 08200fa3f50ba9dc094467d6e1d31197dfcb7134 Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sat, 6 Apr 2024 12:43:26 +0900 Subject: [PATCH 054/695] [mlir][Arith] Specify evaluation order of `getExpr` (#87859) The C++ standard does not specify an evaluation order for addition/... operands. E.g., in `a() + b()`, the compiler is free to evaluate `a` or `b` first. This lead to different `mlir-opt` outputs in #85895. (FileCheck passed when compiled with LLVM but failed when compiled with gcc.) --- .../Arith/IR/ValueBoundsOpInterfaceImpl.cpp | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp index 9c6b50e767ea..90895e381c74 100644 --- a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp @@ -24,8 +24,15 @@ struct AddIOpInterface auto addIOp = cast(op); assert(value == addIOp.getResult() && "invalid value"); - cstr.bound(value) == - cstr.getExpr(addIOp.getLhs()) + cstr.getExpr(addIOp.getRhs()); + // Note: `getExpr` has a side effect: it may add a new column to the + // constraint system. The evaluation order of addition operands is + // unspecified in C++. To make sure that all compilers produce the exact + // same results (that can be FileCheck'd), it is important that `getExpr` + // is called first and assigned to temporary variables, and the addition + // is performed afterwards. + AffineExpr lhs = cstr.getExpr(addIOp.getLhs()); + AffineExpr rhs = cstr.getExpr(addIOp.getRhs()); + cstr.bound(value) == lhs + rhs; } }; @@ -49,8 +56,9 @@ struct SubIOpInterface auto subIOp = cast(op); assert(value == subIOp.getResult() && "invalid value"); - cstr.bound(value) == - cstr.getExpr(subIOp.getLhs()) - cstr.getExpr(subIOp.getRhs()); + AffineExpr lhs = cstr.getExpr(subIOp.getLhs()); + AffineExpr rhs = cstr.getExpr(subIOp.getRhs()); + cstr.bound(value) == lhs - rhs; } }; @@ -61,8 +69,9 @@ struct MulIOpInterface auto mulIOp = cast(op); assert(value == mulIOp.getResult() && "invalid value"); - cstr.bound(value) == - cstr.getExpr(mulIOp.getLhs()) * cstr.getExpr(mulIOp.getRhs()); + AffineExpr lhs = cstr.getExpr(mulIOp.getLhs()); + AffineExpr rhs = cstr.getExpr(mulIOp.getRhs()); + cstr.bound(value) == lhs *rhs; } }; -- GitLab From 76435f2dca97621dfd7e7299bb93e2f38dcf403d Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sat, 6 Apr 2024 13:04:49 +0900 Subject: [PATCH 055/695] [mlir][SCF] `ValueBoundsConstraintSet`: Support `scf.if` (branches) (#87860) This commit adds support for `scf.if` to `ValueBoundsConstraintSet`. Example: ``` %0 = scf.if ... -> index { scf.yield %a : index } else { scf.yield %b : index } ``` The following constraints hold for %0: * %0 >= min(%a, %b) * %0 <= max(%a, %b) Such constraints cannot be added to the constraint set; min/max is not supported by `IntegerRelation`. However, if we know which one of %a and %b is larger, we can add constraints for %0. E.g., if %a <= %b: * %0 >= %a * %0 <= %b This commit required a few minor changes to the `ValueBoundsConstraintSet` infrastructure, so that values can be compared while we are still in the process of traversing the IR/adding constraints. Note: This is a re-upload of #85895, which was reverted. The bug that caused the failure was fixed in #87859. --- .../mlir/Interfaces/ValueBoundsOpInterface.h | 43 ++++-- .../SCF/IR/ValueBoundsOpInterfaceImpl.cpp | 61 ++++++++ .../IR/ScalableValueBoundsConstraintSet.cpp | 14 +- .../lib/Interfaces/ValueBoundsOpInterface.cpp | 143 ++++++++++++++---- .../SCF/value-bounds-op-interface-impl.mlir | 119 ++++++++++++++- 5 files changed, 334 insertions(+), 46 deletions(-) diff --git a/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h b/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h index 83107a3f5f94..3543ab52407a 100644 --- a/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h +++ b/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h @@ -203,6 +203,26 @@ public: std::optional dim1 = std::nullopt, std::optional dim2 = std::nullopt); + /// Traverse the IR starting from the given value/dim and populate constraints + /// as long as the stop condition holds. Also process all values/dims that are + /// already on the worklist. + void populateConstraints(Value value, std::optional dim); + + /// Comparison operator for `ValueBoundsConstraintSet::compare`. + enum ComparisonOperator { LT, LE, EQ, GT, GE }; + + /// Try to prove that, based on the current state of this constraint set + /// (i.e., without analyzing additional IR or adding new constraints), the + /// "lhs" value/dim is LE/LT/EQ/GT/GE than the "rhs" value/dim. + /// + /// Return "true" if the specified relation between the two values/dims was + /// proven to hold. Return "false" if the specified relation could not be + /// proven. This could be because the specified relation does in fact not hold + /// or because there is not enough information in the constraint set. In other + /// words, if we do not know for sure, this function returns "false". + bool compare(Value lhs, std::optional lhsDim, ComparisonOperator cmp, + Value rhs, std::optional rhsDim); + /// Compute whether the given values/dimensions are equal. Return "failure" if /// equality could not be determined. /// @@ -274,13 +294,13 @@ protected: ValueBoundsConstraintSet(MLIRContext *ctx, StopConditionFn stopCondition); - /// Populates the constraint set for a value/map without actually computing - /// the bound. Returns the position for the value/map (via the return value - /// and `posOut` output parameter). - int64_t populateConstraintsSet(Value value, - std::optional dim = std::nullopt); - int64_t populateConstraintsSet(AffineMap map, ValueDimList mapOperands, - int64_t *posOut = nullptr); + /// Given an affine map with a single result (and map operands), add a new + /// column to the constraint set that represents the result of the map. + /// Traverse additional IR starting from the map operands as needed (as long + /// as the stop condition is not satisfied). Also process all values/dims that + /// are already on the worklist. Return the position of the newly added + /// column. + int64_t populateConstraints(AffineMap map, ValueDimList mapOperands); /// Iteratively process all elements on the worklist until an index-typed /// value or shaped value meets `stopCondition`. Such values are not processed @@ -295,14 +315,19 @@ protected: /// value/dimension exists in the constraint set. int64_t getPos(Value value, std::optional dim = std::nullopt) const; + /// Return an affine expression that represents column `pos` in the constraint + /// set. + AffineExpr getPosExpr(int64_t pos); + /// Insert a value/dimension into the constraint set. If `isSymbol` is set to /// "false", a dimension is added. The value/dimension is added to the - /// worklist. + /// worklist if `addToWorklist` is set. /// /// Note: There are certain affine restrictions wrt. dimensions. E.g., they /// cannot be multiplied. Furthermore, bounds can only be queried for /// dimensions but not for symbols. - int64_t insert(Value value, std::optional dim, bool isSymbol = true); + int64_t insert(Value value, std::optional dim, bool isSymbol = true, + bool addToWorklist = true); /// Insert an anonymous column into the constraint set. The column is not /// bound to any value/dimension. If `isSymbol` is set to "false", a dimension diff --git a/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp b/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp index 1e13e60068ee..8e9d1021f93e 100644 --- a/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp @@ -111,6 +111,66 @@ struct ForOpInterface } }; +struct IfOpInterface + : public ValueBoundsOpInterface::ExternalModel { + + static void populateBounds(scf::IfOp ifOp, Value value, + std::optional dim, + ValueBoundsConstraintSet &cstr) { + unsigned int resultNum = cast(value).getResultNumber(); + Value thenValue = ifOp.thenYield().getResults()[resultNum]; + Value elseValue = ifOp.elseYield().getResults()[resultNum]; + + // Populate constraints for the yielded value (and all values on the + // backward slice, as long as the current stop condition is not satisfied). + cstr.populateConstraints(thenValue, dim); + cstr.populateConstraints(elseValue, dim); + auto boundsBuilder = cstr.bound(value); + if (dim) + boundsBuilder[*dim]; + + // Compare yielded values. + // If thenValue <= elseValue: + // * result <= elseValue + // * result >= thenValue + if (cstr.compare(thenValue, dim, + ValueBoundsConstraintSet::ComparisonOperator::LE, + elseValue, dim)) { + if (dim) { + cstr.bound(value)[*dim] >= cstr.getExpr(thenValue, dim); + cstr.bound(value)[*dim] <= cstr.getExpr(elseValue, dim); + } else { + cstr.bound(value) >= thenValue; + cstr.bound(value) <= elseValue; + } + } + // If elseValue <= thenValue: + // * result <= thenValue + // * result >= elseValue + if (cstr.compare(elseValue, dim, + ValueBoundsConstraintSet::ComparisonOperator::LE, + thenValue, dim)) { + if (dim) { + cstr.bound(value)[*dim] >= cstr.getExpr(elseValue, dim); + cstr.bound(value)[*dim] <= cstr.getExpr(thenValue, dim); + } else { + cstr.bound(value) >= elseValue; + cstr.bound(value) <= thenValue; + } + } + } + + void populateBoundsForIndexValue(Operation *op, Value value, + ValueBoundsConstraintSet &cstr) const { + populateBounds(cast(op), value, /*dim=*/std::nullopt, cstr); + } + + void populateBoundsForShapedValueDim(Operation *op, Value value, int64_t dim, + ValueBoundsConstraintSet &cstr) const { + populateBounds(cast(op), value, dim, cstr); + } +}; + } // namespace } // namespace scf } // namespace mlir @@ -119,5 +179,6 @@ void mlir::scf::registerValueBoundsOpInterfaceExternalModels( DialectRegistry ®istry) { registry.addExtension(+[](MLIRContext *ctx, scf::SCFDialect *dialect) { scf::ForOp::attachInterface(*ctx); + scf::IfOp::attachInterface(*ctx); }); } diff --git a/mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp b/mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp index 52359fa8a510..f8df34843a36 100644 --- a/mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp +++ b/mlir/lib/Dialect/Vector/IR/ScalableValueBoundsConstraintSet.cpp @@ -59,12 +59,16 @@ ScalableValueBoundsConstraintSet::computeScalableBound( ScalableValueBoundsConstraintSet scalableCstr( value.getContext(), stopCondition ? stopCondition : defaultStopCondition, vscaleMin, vscaleMax); - int64_t pos = scalableCstr.populateConstraintsSet(value, dim); + int64_t pos = scalableCstr.insert(value, dim, /*isSymbol=*/false); + scalableCstr.processWorklist(); - // Project out all variables apart from vscale. - // This should result in constraints in terms of vscale only. + // Project out all columns apart from vscale and the starting point + // (value/dim). This should result in constraints in terms of vscale only. auto projectOutFn = [&](ValueDim p) { - return p.first != scalableCstr.getVscaleValue(); + bool isStartingPoint = + p.first == value && + p.second == dim.value_or(ValueBoundsConstraintSet::kIndexValue); + return p.first != scalableCstr.getVscaleValue() && !isStartingPoint; }; scalableCstr.projectOut(projectOutFn); @@ -72,7 +76,7 @@ ScalableValueBoundsConstraintSet::computeScalableBound( scalableCstr.positionToValueDim.size() && "inconsistent mapping state"); - // Check that the only symbols left are vscale. + // Check that the only columns left are vscale and the starting point. for (int64_t i = 0; i < scalableCstr.cstr.getNumDimAndSymbolVars(); ++i) { if (i == pos) continue; diff --git a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp index 0d362c7efa0a..6e3d6dd3c757 100644 --- a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp +++ b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp @@ -110,25 +110,47 @@ AffineExpr ValueBoundsConstraintSet::getExpr(Value value, assertValidValueDim(value, dim); #endif // NDEBUG + // Check if the value/dim is statically known. In that case, an affine + // constant expression should be returned. This allows us to support + // multiplications with constants. (Multiplications of two columns in the + // constraint set is not supported.) + std::optional constSize = std::nullopt; auto shapedType = dyn_cast(value.getType()); if (shapedType) { - // Static dimension: return constant directly. if (shapedType.hasRank() && !shapedType.isDynamicDim(*dim)) - return builder.getAffineConstantExpr(shapedType.getDimSize(*dim)); - } else { - // Constant index value: return directly. - if (auto constInt = ::getConstantIntValue(value)) - return builder.getAffineConstantExpr(*constInt); + constSize = shapedType.getDimSize(*dim); + } else if (auto constInt = ::getConstantIntValue(value)) { + constSize = *constInt; } - // Dynamic value: add to constraint set. + // If the value/dim is already mapped, return the corresponding expression + // directly. ValueDim valueDim = std::make_pair(value, dim.value_or(kIndexValue)); - if (!valueDimToPosition.contains(valueDim)) - (void)insert(value, dim); - int64_t pos = getPos(value, dim); - return pos < cstr.getNumDimVars() - ? builder.getAffineDimExpr(pos) - : builder.getAffineSymbolExpr(pos - cstr.getNumDimVars()); + if (valueDimToPosition.contains(valueDim)) { + // If it is a constant, return an affine constant expression. Otherwise, + // return an affine expression that represents the respective column in the + // constraint set. + if (constSize) + return builder.getAffineConstantExpr(*constSize); + return getPosExpr(getPos(value, dim)); + } + + if (constSize) { + // Constant index value/dim: add column to the constraint set, add EQ bound + // and return an affine constant expression without pushing the newly added + // column to the worklist. + (void)insert(value, dim, /*isSymbol=*/true, /*addToWorklist=*/false); + if (shapedType) + bound(value)[*dim] == *constSize; + else + bound(value) == *constSize; + return builder.getAffineConstantExpr(*constSize); + } + + // Dynamic value/dim: insert column to the constraint set and put it on the + // worklist. Return an affine expression that represents the newly inserted + // column in the constraint set. + return getPosExpr(insert(value, dim, /*isSymbol=*/true)); } AffineExpr ValueBoundsConstraintSet::getExpr(OpFoldResult ofr) { @@ -145,7 +167,7 @@ AffineExpr ValueBoundsConstraintSet::getExpr(int64_t constant) { int64_t ValueBoundsConstraintSet::insert(Value value, std::optional dim, - bool isSymbol) { + bool isSymbol, bool addToWorklist) { #ifndef NDEBUG assertValidValueDim(value, dim); #endif // NDEBUG @@ -160,7 +182,12 @@ int64_t ValueBoundsConstraintSet::insert(Value value, if (positionToValueDim[i].has_value()) valueDimToPosition[*positionToValueDim[i]] = i; - worklist.push(pos); + if (addToWorklist) { + LLVM_DEBUG(llvm::dbgs() << "Push to worklist: " << value + << " (dim: " << dim.value_or(kIndexValue) << ")\n"); + worklist.push(pos); + } + return pos; } @@ -190,6 +217,13 @@ int64_t ValueBoundsConstraintSet::getPos(Value value, return it->second; } +AffineExpr ValueBoundsConstraintSet::getPosExpr(int64_t pos) { + assert(pos >= 0 && pos < cstr.getNumDimAndSymbolVars() && "invalid position"); + return pos < cstr.getNumDimVars() + ? builder.getAffineDimExpr(pos) + : builder.getAffineSymbolExpr(pos - cstr.getNumDimVars()); +} + static Operation *getOwnerOfValue(Value value) { if (auto bbArg = dyn_cast(value)) return bbArg.getOwner()->getParentOp(); @@ -492,7 +526,7 @@ FailureOr ValueBoundsConstraintSet::computeConstantBound( // Default stop condition if none was specified: Keep adding constraints until // a bound could be computed. - int64_t pos; + int64_t pos = 0; auto defaultStopCondition = [&](Value v, std::optional dim, ValueBoundsConstraintSet &cstr) { return cstr.cstr.getConstantBound64(type, pos).has_value(); @@ -500,7 +534,8 @@ FailureOr ValueBoundsConstraintSet::computeConstantBound( ValueBoundsConstraintSet cstr( map.getContext(), stopCondition ? stopCondition : defaultStopCondition); - cstr.populateConstraintsSet(map, operands, &pos); + pos = cstr.populateConstraints(map, operands); + assert(pos == 0 && "expected `map` is the first column"); // Compute constant bound for `valueDim`. int64_t ubAdjustment = closedUB ? 0 : 1; @@ -509,29 +544,28 @@ FailureOr ValueBoundsConstraintSet::computeConstantBound( return failure(); } -int64_t -ValueBoundsConstraintSet::populateConstraintsSet(Value value, - std::optional dim) { +void ValueBoundsConstraintSet::populateConstraints(Value value, + std::optional dim) { #ifndef NDEBUG assertValidValueDim(value, dim); #endif // NDEBUG - AffineMap map = - AffineMap::get(/*dimCount=*/1, /*symbolCount=*/0, - Builder(value.getContext()).getAffineDimExpr(0)); - return populateConstraintsSet(map, {{value, dim}}); + // `getExpr` pushes the value/dim onto the worklist (unless it was already + // analyzed). + (void)getExpr(value, dim); + // Process all values/dims on the worklist. This may traverse and analyze + // additional IR, depending the current stop function. + processWorklist(); } -int64_t ValueBoundsConstraintSet::populateConstraintsSet(AffineMap map, - ValueDimList operands, - int64_t *posOut) { +int64_t ValueBoundsConstraintSet::populateConstraints(AffineMap map, + ValueDimList operands) { assert(map.getNumResults() == 1 && "expected affine map with one result"); int64_t pos = insert(/*isSymbol=*/false); - if (posOut) - *posOut = pos; // Add map and operands to the constraint set. Dimensions are converted to - // symbols. All operands are added to the worklist. + // symbols. All operands are added to the worklist (unless they were already + // processed). auto mapper = [&](std::pair> v) { return getExpr(v.first, v.second); }; @@ -566,6 +600,55 @@ ValueBoundsConstraintSet::computeConstantDelta(Value value1, Value value2, {{value1, dim1}, {value2, dim2}}); } +bool ValueBoundsConstraintSet::compare(Value lhs, std::optional lhsDim, + ComparisonOperator cmp, Value rhs, + std::optional rhsDim) { + // This function returns "true" if "lhs CMP rhs" is proven to hold. + // + // Example for ComparisonOperator::LE and index-typed values: We would like to + // prove that lhs <= rhs. Proof by contradiction: add the inverse + // relation (lhs > rhs) to the constraint set and check if the resulting + // constraint set is "empty" (i.e. has no solution). In that case, + // lhs > rhs must be incorrect and we can deduce that lhs <= rhs holds. + + // We cannot prove anything if the constraint set is already empty. + if (cstr.isEmpty()) { + LLVM_DEBUG( + llvm::dbgs() + << "cannot compare value/dims: constraint system is already empty"); + return false; + } + + // EQ can be expressed as LE and GE. + if (cmp == EQ) + return compare(lhs, lhsDim, ComparisonOperator::LE, rhs, rhsDim) && + compare(lhs, lhsDim, ComparisonOperator::GE, rhs, rhsDim); + + // Construct inequality. For the above example: lhs > rhs. + // `IntegerRelation` inequalities are expressed in the "flattened" form and + // with ">= 0". I.e., lhs - rhs - 1 >= 0. + SmallVector eq(cstr.getNumDimAndSymbolVars() + 1, 0); + if (cmp == LT || cmp == LE) { + ++eq[getPos(lhs, lhsDim)]; + --eq[getPos(rhs, rhsDim)]; + } else if (cmp == GT || cmp == GE) { + --eq[getPos(lhs, lhsDim)]; + ++eq[getPos(rhs, rhsDim)]; + } else { + llvm_unreachable("unsupported comparison operator"); + } + if (cmp == LE || cmp == GE) + eq[cstr.getNumDimAndSymbolVars()] -= 1; + + // Add inequality to the constraint set and check if it made the constraint + // set empty. + int64_t ineqPos = cstr.getNumInequalities(); + cstr.addInequality(eq); + bool isEmpty = cstr.isEmpty(); + cstr.removeInequality(ineqPos); + return isEmpty; +} + FailureOr ValueBoundsConstraintSet::areEqual(Value value1, Value value2, std::optional dim1, diff --git a/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir b/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir index e4d714159249..0ea06737886d 100644 --- a/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir +++ b/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir @@ -1,5 +1,5 @@ -// RUN: mlir-opt %s -test-affine-reify-value-bounds -verify-diagnostics \ -// RUN: -split-input-file | FileCheck %s +// RUN: mlir-opt %s -test-affine-reify-value-bounds="reify-to-func-args" \ +// RUN: -verify-diagnostics -split-input-file | FileCheck %s // CHECK-LABEL: func @scf_for( // CHECK-SAME: %[[a:.*]]: index, %[[b:.*]]: index, %[[c:.*]]: index @@ -104,3 +104,118 @@ func.func @scf_for_swapping_yield(%t1: tensor, %t2: tensor, %a: in "test.some_use"(%reify1) : (index) -> () return } + +// ----- + +// CHECK-LABEL: func @scf_if_constant( +func.func @scf_if_constant(%c : i1) { + // CHECK: arith.constant 4 : index + // CHECK: arith.constant 9 : index + %c4 = arith.constant 4 : index + %c9 = arith.constant 9 : index + %r = scf.if %c -> index { + scf.yield %c4 : index + } else { + scf.yield %c9 : index + } + + // CHECK: %[[c4:.*]] = arith.constant 4 : index + // CHECK: %[[c10:.*]] = arith.constant 10 : index + %reify1 = "test.reify_bound"(%r) {type = "LB"} : (index) -> (index) + %reify2 = "test.reify_bound"(%r) {type = "UB"} : (index) -> (index) + // CHECK: "test.some_use"(%[[c4]], %[[c10]]) + "test.some_use"(%reify1, %reify2) : (index, index) -> () + return +} + +// ----- + +// CHECK: #[[$map:.*]] = affine_map<()[s0, s1] -> (s0 + s1)> +// CHECK: #[[$map1:.*]] = affine_map<()[s0, s1] -> (s0 + s1 + 5)> +// CHECK-LABEL: func @scf_if_dynamic( +// CHECK-SAME: %[[a:.*]]: index, %[[b:.*]]: index, %{{.*}}: i1) +func.func @scf_if_dynamic(%a: index, %b: index, %c : i1) { + %c4 = arith.constant 4 : index + %r = scf.if %c -> index { + %add1 = arith.addi %a, %b : index + scf.yield %add1 : index + } else { + %add2 = arith.addi %b, %c4 : index + %add3 = arith.addi %add2, %a : index + scf.yield %add3 : index + } + + // CHECK: %[[lb:.*]] = affine.apply #[[$map]]()[%[[a]], %[[b]]] + // CHECK: %[[ub:.*]] = affine.apply #[[$map1]]()[%[[a]], %[[b]]] + %reify1 = "test.reify_bound"(%r) {type = "LB"} : (index) -> (index) + %reify2 = "test.reify_bound"(%r) {type = "UB"} : (index) -> (index) + // CHECK: "test.some_use"(%[[lb]], %[[ub]]) + "test.some_use"(%reify1, %reify2) : (index, index) -> () + return +} + +// ----- + +func.func @scf_if_no_affine_bound(%a: index, %b: index, %c : i1) { + %r = scf.if %c -> index { + scf.yield %a : index + } else { + scf.yield %b : index + } + // The reified bound would be min(%a, %b). min/max expressions are not + // supported in reified bounds. + // expected-error @below{{could not reify bound}} + %reify1 = "test.reify_bound"(%r) {type = "LB"} : (index) -> (index) + "test.some_use"(%reify1) : (index) -> () + return +} + +// ----- + +// CHECK-LABEL: func @scf_if_tensor_dim( +func.func @scf_if_tensor_dim(%c : i1) { + // CHECK: arith.constant 4 : index + // CHECK: arith.constant 9 : index + %c4 = arith.constant 4 : index + %c9 = arith.constant 9 : index + %t1 = tensor.empty(%c4) : tensor + %t2 = tensor.empty(%c9) : tensor + %r = scf.if %c -> tensor { + scf.yield %t1 : tensor + } else { + scf.yield %t2 : tensor + } + + // CHECK: %[[c4:.*]] = arith.constant 4 : index + // CHECK: %[[c10:.*]] = arith.constant 10 : index + %reify1 = "test.reify_bound"(%r) {type = "LB", dim = 0} + : (tensor) -> (index) + %reify2 = "test.reify_bound"(%r) {type = "UB", dim = 0} + : (tensor) -> (index) + // CHECK: "test.some_use"(%[[c4]], %[[c10]]) + "test.some_use"(%reify1, %reify2) : (index, index) -> () + return +} + +// ----- + +// CHECK: #[[$map:.*]] = affine_map<()[s0, s1] -> (s0 + s1)> +// CHECK-LABEL: func @scf_if_eq( +// CHECK-SAME: %[[a:.*]]: index, %[[b:.*]]: index, %{{.*}}: i1) +func.func @scf_if_eq(%a: index, %b: index, %c : i1) { + %c0 = arith.constant 0 : index + %r = scf.if %c -> index { + %add1 = arith.addi %a, %b : index + scf.yield %add1 : index + } else { + %add2 = arith.addi %b, %c0 : index + %add3 = arith.addi %add2, %a : index + scf.yield %add3 : index + } + + // CHECK: %[[eq:.*]] = affine.apply #[[$map]]()[%[[a]], %[[b]]] + %reify1 = "test.reify_bound"(%r) {type = "EQ"} : (index) -> (index) + // CHECK: "test.some_use"(%[[eq]]) + "test.some_use"(%reify1) : (index) -> () + return +} -- GitLab From 813f68caf42260452ad7a5cc224ef199a2ad0067 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Sat, 6 Apr 2024 08:09:54 +0400 Subject: [PATCH 056/695] [clang] Reject VLAs in `__is_layout_compatible()` (#87737) This is a follow-up to #81506. Since `__is_layout_compatible()` is a C++ intrinsic (https://github.com/llvm/llvm-project/blob/ff1e72d68d1224271801ff5192a8c14fbd3be83b/clang/include/clang/Basic/TokenKinds.def#L523), I don't think we should define how it interacts with VLA extension unless we have a compelling reason to. Since #81506 was merged after 18 cut-off, we don't have to follow any kind of deprecation process. --- clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 +- clang/lib/Sema/SemaExprCXX.cpp | 3 +++ clang/test/SemaCXX/type-traits.cpp | 10 ++++++---- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index df57f5e6ce11..a1dda2d2461c 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -165,7 +165,7 @@ def ext_vla_folded_to_constant : ExtWarn< "variable length array folded to constant array as an extension">, InGroup; def err_vla_unsupported : Error< - "variable length arrays are not supported for %select{the current target|'%1'}0">; + "variable length arrays are not supported %select{for the current target|in '%1'}0">; def err_vla_in_coroutine_unsupported : Error< "variable length arrays in a coroutine are not supported">; def note_vla_unsupported : Note< diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 76bb78aa8b54..db84f1810122 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -6026,6 +6026,9 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, QualType LhsT, return false; } case BTT_IsLayoutCompatible: { + if (LhsT->isVariableArrayType() || RhsT->isVariableArrayType()) + Self.Diag(KeyLoc, diag::err_vla_unsupported) + << 1 << tok::kw___is_layout_compatible; return Self.IsLayoutCompatible(LhsT, RhsT); } default: llvm_unreachable("not a BTT"); diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index 14ec17989ec7..e99ad11666e5 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -740,7 +740,7 @@ void is_bounded_array(int n) { static_assert(!__is_bounded_array(cvoid *)); int t32[n]; - (void)__is_bounded_array(decltype(t32)); // expected-error{{variable length arrays are not supported for '__is_bounded_array'}} + (void)__is_bounded_array(decltype(t32)); // expected-error{{variable length arrays are not supported in '__is_bounded_array'}} } void is_unbounded_array(int n) { @@ -772,7 +772,7 @@ void is_unbounded_array(int n) { static_assert(!__is_unbounded_array(cvoid *)); int t32[n]; - (void)__is_unbounded_array(decltype(t32)); // expected-error{{variable length arrays are not supported for '__is_unbounded_array'}} + (void)__is_unbounded_array(decltype(t32)); // expected-error{{variable length arrays are not supported in '__is_unbounded_array'}} } void is_referenceable() { @@ -1741,8 +1741,10 @@ void is_layout_compatible(int n) static_assert(!__is_layout_compatible(unsigned char, signed char)); static_assert(__is_layout_compatible(int[], int[])); static_assert(__is_layout_compatible(int[2], int[2])); - static_assert(!__is_layout_compatible(int[n], int[2])); // FIXME: VLAs should be rejected - static_assert(!__is_layout_compatible(int[n], int[n])); // FIXME: VLAs should be rejected + static_assert(!__is_layout_compatible(int[n], int[2])); + // expected-error@-1 {{variable length arrays are not supported in '__is_layout_compatible'}} + static_assert(!__is_layout_compatible(int[n], int[n])); + // expected-error@-1 {{variable length arrays are not supported in '__is_layout_compatible'}} static_assert(__is_layout_compatible(int&, int&)); static_assert(!__is_layout_compatible(int&, char&)); static_assert(__is_layout_compatible(void(int), void(int))); -- GitLab From cd0f5b2e58fad3973f2f50936b0467b2de3b3e12 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Sat, 6 Apr 2024 08:10:53 +0400 Subject: [PATCH 057/695] [clang] Add test for CWG392 (#87744) [CWG392](https://cplusplus.github.io/CWG/issues/392.html) "Use of full expression lvalue before temporary destruction". We're testing that `operator bool()` is called before destructor of `C`. I'm also marking CWG388 as requiring libc++abi test instead of codegen test, as we need to test matching between exception object and exception handlers. --- clang/test/CXX/drs/dr392.cpp | 40 ++++++++++++++++++++++++++++++++++++ clang/test/CXX/drs/dr3xx.cpp | 4 ++-- clang/www/cxx_dr_status.html | 2 +- 3 files changed, 43 insertions(+), 3 deletions(-) create mode 100644 clang/test/CXX/drs/dr392.cpp diff --git a/clang/test/CXX/drs/dr392.cpp b/clang/test/CXX/drs/dr392.cpp new file mode 100644 index 000000000000..26e6259f7196 --- /dev/null +++ b/clang/test/CXX/drs/dr392.cpp @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +#if __cplusplus == 199711L +#define NOTHROW throw() +#else +#define NOTHROW noexcept(true) +#endif + +namespace dr392 { // dr392: 2.8 + +struct A { + operator bool() NOTHROW; +}; + +class C { +public: + C() NOTHROW; + ~C() NOTHROW; + A& get() NOTHROW { return p; } +private: + A p; +}; + +void f() +{ + if (C().get()) {} +} + +} // namespace dr392 + +// CHECK-LABEL: define {{.*}} void @dr392::f()() +// CHECK: call {{.*}} i1 @dr392::A::operator bool() +// CHECK: call void @dr392::C::~C() +// CHECK-LABEL: } diff --git a/clang/test/CXX/drs/dr3xx.cpp b/clang/test/CXX/drs/dr3xx.cpp index 4584801f9f97..483ebf7a08aa 100644 --- a/clang/test/CXX/drs/dr3xx.cpp +++ b/clang/test/CXX/drs/dr3xx.cpp @@ -1401,7 +1401,7 @@ namespace dr387 { // dr387: 2.8 } } -// FIXME: dr388 needs codegen test +// FIXME: dr388 needs libc++abi test namespace dr389 { // dr389: no struct S { @@ -1567,7 +1567,7 @@ namespace dr391 { // dr391: 2.8 c++11 const C &c = fc(); } -// dr392 FIXME write codegen test +// dr392 is in dr392.cpp // dr394: na namespace dr395 { // dr395: 3.0 diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 5e1e03dec1d4..588c5b3e939d 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -2392,7 +2392,7 @@ of class templates 392 CD1 Use of full expression lvalue before temporary destruction - Unknown + Clang 2.8 393 -- GitLab From 0b021c4b603b4e076f9e54572a4eef3e43ab57c0 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Sat, 6 Apr 2024 08:11:58 +0400 Subject: [PATCH 058/695] [clang] Claim conformance for CWG466 (#87748) [CWG466](https://cplusplus.github.io/CWG/issues/466.html) "cv-qualifiers on pseudo-destructor type". Richard claimed that we don't implement this DR because of one ill-formed example being accepted: `a->CI::~VI();`. This example is testing the behavior of calling a pseudo-destructor via a qualified name, where components of qualified name denote the same `int` type, but with different cv-qualifications. Initially, the following wording from [expr.pseudo] quoted in CWG466 was left intact: > Furthermore, the two type-names in a pseudo-destructor-name of the form > > `:: (opt) nested-name-specifier (opt) type-name ::~ type-name` > >shall designate the same scalar type. According to this wording, the example is indeed ill-formed. [P1131R2](https://wg21.link/p1131r2) merged wording for pseudo-destructors into regular destructor wording. Among other things, [expr.pseudo] was removed, and [expr.prim.id.qual]/2 was changed to read: > Where `type-name ::~ type-name` is used, the two type-names shall refer to the same type (ignoring cv-qualifications); I believe P1131R2 made the example well-formed. However, this wording didn't survive [P1787R6](https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p1787r6.html) "Declarations and where to find them". In that paper I don't see the intent to make the example ill-formed again, so I assume it confirmed status-quo via other wording. My _guess_ the new wording is http://eel.is/c++draft/basic.lookup#qual.general-4.6: > If a qualified name Q follows a ~: > - <...> > - The [type-name](http://eel.is/c++draft/dcl.type.simple#nt:type-name) that is or contains Q shall refer to its (original) lookup context (ignoring cv-qualification) under the interpretation established by at least one (successful) lookup performed[.](http://eel.is/c++draft/basic.lookup#qual.general-4.6.sentence-1) --- clang/test/CXX/drs/dr4xx.cpp | 4 ++-- clang/www/cxx_dr_status.html | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/CXX/drs/dr4xx.cpp b/clang/test/CXX/drs/dr4xx.cpp index 343c4ee6f334..34dd638c1d9b 100644 --- a/clang/test/CXX/drs/dr4xx.cpp +++ b/clang/test/CXX/drs/dr4xx.cpp @@ -948,7 +948,7 @@ namespace dr460 { // dr460: yes // dr464: na // dr465: na -namespace dr466 { // dr466: no +namespace dr466 { // dr466: 2.8 typedef int I; typedef const int CI; typedef volatile int VI; @@ -960,7 +960,7 @@ namespace dr466 { // dr466: no a->CI::~CI(); a->VI::~VI(); - a->CI::~VI(); // FIXME: This is invalid; CI and VI are not the same scalar type. + a->CI::~VI(); // allowed by changes to [expr.id.prim.qual]/2 introduced in P1131R2 b->~I(); b->~CI(); diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 588c5b3e939d..a4c133c13c49 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -2836,7 +2836,7 @@ of class templates 466 CD1 cv-qualifiers on pseudo-destructor type - No + Clang 2.8 467 -- GitLab From 770202343ebce1f2bc0745c78e298e251f204bee Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Fri, 5 Apr 2024 22:10:56 -0700 Subject: [PATCH 059/695] [clang-format][NFC] Rename `kind` to `Kind` --- clang/lib/Format/UnwrappedLineParser.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 55c627d87f08..57d8dbcf3b4c 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -365,11 +365,11 @@ bool UnwrappedLineParser::parseLevel(const FormatToken *OpeningBrace, nextToken(); continue; } - tok::TokenKind kind = FormatTok->Tok.getKind(); + tok::TokenKind Kind = FormatTok->Tok.getKind(); if (FormatTok->getType() == TT_MacroBlockBegin) - kind = tok::l_brace; + Kind = tok::l_brace; else if (FormatTok->getType() == TT_MacroBlockEnd) - kind = tok::r_brace; + Kind = tok::r_brace; auto ParseDefault = [this, OpeningBrace, IfKind, &IfLBrace, &HasDoWhile, &HasLabel, &StatementCount] { @@ -380,7 +380,7 @@ bool UnwrappedLineParser::parseLevel(const FormatToken *OpeningBrace, assert(StatementCount > 0 && "StatementCount overflow!"); }; - switch (kind) { + switch (Kind) { case tok::comment: nextToken(); addUnwrappedLine(); @@ -3280,8 +3280,8 @@ void UnwrappedLineParser::parseSwitch() { } // Operators that can follow a C variable. -static bool isCOperatorFollowingVar(tok::TokenKind kind) { - switch (kind) { +static bool isCOperatorFollowingVar(tok::TokenKind Kind) { + switch (Kind) { case tok::ampamp: case tok::ampequal: case tok::arrow: -- GitLab From 0ba3e96be114dcbe0ac6813a1d0e2940d2a88229 Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sat, 6 Apr 2024 15:30:26 +0900 Subject: [PATCH 060/695] [mlir][SCF][NFC] `ValueBoundsConstraintSet`: Simplify `scf.for` implementation (#87862) This commit simplifies the implementation of the `ValueBoundsOpInterface` for `scf.for` based on the newly added `ValueBoundsConstraintSet::compare` API and adds additional documentation. Previously, the interface implementation created a new constraint set just to check if the yielded value and iter_arg are equal. This was inefficient because constraints were added multiple times (to two different constraint sets) for ops that are inside the loop. Note: This is a re-upload of #86239. --- .../SCF/IR/ValueBoundsOpInterfaceImpl.cpp | 80 +++++++++---------- 1 file changed, 36 insertions(+), 44 deletions(-) diff --git a/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp b/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp index 8e9d1021f93e..72c5aaa23067 100644 --- a/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp @@ -12,7 +12,6 @@ #include "mlir/Interfaces/ValueBoundsOpInterface.h" using namespace mlir; -using presburger::BoundType; namespace mlir { namespace scf { @@ -21,7 +20,28 @@ namespace { struct ForOpInterface : public ValueBoundsOpInterface::ExternalModel { - /// Populate bounds of values/dimensions for iter_args/OpResults. + /// Populate bounds of values/dimensions for iter_args/OpResults. If the + /// value/dimension size does not change in an iteration, we can deduce that + /// it the same as the initial value/dimension. + /// + /// Example 1: + /// %0 = scf.for ... iter_args(%arg0 = %t) -> tensor { + /// ... + /// %1 = tensor.insert %f into %arg0[...] : tensor + /// scf.yield %1 : tensor + /// } + /// --> bound(%0)[0] == bound(%t)[0] + /// --> bound(%arg0)[0] == bound(%t)[0] + /// + /// Example 2: + /// %0 = scf.for ... iter_args(%arg0 = %t) -> tensor { + /// %sz = tensor.dim %arg0 : tensor + /// %incr = arith.addi %sz, %c1 : index + /// %1 = tensor.empty(%incr) : tensor + /// scf.yield %1 : tensor + /// } + /// --> The yielded tensor dimension size changes with each iteration. Such + /// loops are not supported and no constraints are added. static void populateIterArgBounds(scf::ForOp forOp, Value value, std::optional dim, ValueBoundsConstraintSet &cstr) { @@ -33,59 +53,31 @@ struct ForOpInterface iterArgIdx = llvm::cast(value).getResultNumber(); } - // An EQ constraint can be added if the yielded value (dimension size) - // equals the corresponding block argument (dimension size). Value yieldedValue = cast(forOp.getBody()->getTerminator()) .getOperand(iterArgIdx); Value iterArg = forOp.getRegionIterArg(iterArgIdx); Value initArg = forOp.getInitArgs()[iterArgIdx]; - auto addEqBound = [&]() { + // Populate constraints for the yielded value. + cstr.populateConstraints(yieldedValue, dim); + // Populate constraints for the iter_arg. This is just to ensure that the + // iter_arg is mapped in the constraint set, which is a prerequisite for + // `compare`. It may lead to a recursive call to this function in case the + // iter_arg was not visited when the constraints for the yielded value were + // populated, but no additional work is done. + cstr.populateConstraints(iterArg, dim); + + // An EQ constraint can be added if the yielded value (dimension size) + // equals the corresponding block argument (dimension size). + if (cstr.compare(yieldedValue, dim, + ValueBoundsConstraintSet::ComparisonOperator::EQ, iterArg, + dim)) { if (dim.has_value()) { cstr.bound(value)[*dim] == cstr.getExpr(initArg, dim); } else { cstr.bound(value) == initArg; } - }; - - if (yieldedValue == iterArg) { - addEqBound(); - return; - } - - // Compute EQ bound for yielded value. - AffineMap bound; - ValueDimList boundOperands; - LogicalResult status = ValueBoundsConstraintSet::computeBound( - bound, boundOperands, BoundType::EQ, yieldedValue, dim, - [&](Value v, std::optional d, ValueBoundsConstraintSet &cstr) { - // Stop when reaching a block argument of the loop body. - if (auto bbArg = llvm::dyn_cast(v)) - return bbArg.getOwner()->getParentOp() == forOp; - // Stop when reaching a value that is defined outside of the loop. It - // is impossible to reach an iter_arg from there. - Operation *op = v.getDefiningOp(); - return forOp.getRegion().findAncestorOpInRegion(*op) == nullptr; - }); - if (failed(status)) - return; - if (bound.getNumResults() != 1) - return; - - // Check if computed bound equals the corresponding iter_arg. - Value singleValue = nullptr; - std::optional singleDim; - if (auto dimExpr = dyn_cast(bound.getResult(0))) { - int64_t idx = dimExpr.getPosition(); - singleValue = boundOperands[idx].first; - singleDim = boundOperands[idx].second; - } else if (auto symExpr = dyn_cast(bound.getResult(0))) { - int64_t idx = symExpr.getPosition() + bound.getNumDims(); - singleValue = boundOperands[idx].first; - singleDim = boundOperands[idx].second; } - if (singleValue == iterArg && singleDim == dim) - addEqBound(); } void populateBoundsForIndexValue(Operation *op, Value value, -- GitLab From a522dbbd62d0cda4cd10b1b477f238938446294a Mon Sep 17 00:00:00 2001 From: Kai Sasaki Date: Sat, 6 Apr 2024 15:35:10 +0900 Subject: [PATCH 061/695] [mlir][complex] Support fast math flag for complex.sign op (#87148) We are going to support the fast math flag given in `complex.sign` op in the conversion to standard dialect. See: https://discourse.llvm.org/t/rfc-fastmath-flags-support-in-complex-dialect/71981 --- .../ComplexToStandard/ComplexToStandard.cpp | 7 +-- .../convert-to-standard.mlir | 43 +++++++++++++++++++ 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 17f64f1b65b7..e18b27702e4e 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -918,6 +918,7 @@ struct SignOpConversion : public OpConversionPattern { auto type = cast(adaptor.getComplex().getType()); auto elementType = cast(type.getElementType()); mlir::ImplicitLocOpBuilder b(op.getLoc(), rewriter); + arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); Value real = b.create(elementType, adaptor.getComplex()); Value imag = b.create(elementType, adaptor.getComplex()); @@ -928,9 +929,9 @@ struct SignOpConversion : public OpConversionPattern { Value imagIsZero = b.create(arith::CmpFPredicate::OEQ, imag, zero); Value isZero = b.create(realIsZero, imagIsZero); - auto abs = b.create(elementType, adaptor.getComplex()); - Value realSign = b.create(real, abs); - Value imagSign = b.create(imag, abs); + auto abs = b.create(elementType, adaptor.getComplex(), fmf); + Value realSign = b.create(real, abs, fmf); + Value imagSign = b.create(imag, abs, fmf); Value sign = b.create(type, realSign, imagSign); rewriter.replaceOpWithNewOp(op, isZero, adaptor.getComplex(), sign); diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index bac94aae6b74..112918b20d33 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -1880,3 +1880,46 @@ func.func @complex_sin_with_fmf(%arg: complex) -> complex { // CHECK-DAG: %[[RESULT_IMAG:.*]] = arith.mulf %[[EXP_DIFF]], %[[COS]] fastmath // CHECK-DAG: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] + +// ----- + +// CHECK-LABEL: func @complex_sign_with_fmf +// CHECK-SAME: %[[ARG:.*]]: complex +func.func @complex_sign_with_fmf(%arg: complex) -> complex { + %sign = complex.sign %arg fastmath : complex + return %sign : complex +} + +// CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex +// CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex +// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[REAL_IS_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 +// CHECK: %[[IMAG_IS_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 +// CHECK: %[[IS_ZERO:.*]] = arith.andi %[[REAL_IS_ZERO]], %[[IMAG_IS_ZERO]] : i1 +// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[REAL2:.*]] = complex.re %[[ARG]] : complex +// CHECK: %[[IMAG2:.*]] = complex.im %[[ARG]] : complex +// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL2]], %[[ZERO]] : f32 +// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG2]], %[[ZERO]] : f32 +// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG2]], %[[REAL2]] fastmath : f32 +// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] fastmath : f32 +// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL2]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] fastmath : f32 +// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL2]], %[[IMAG2]] fastmath : f32 +// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] fastmath : f32 +// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG2]] fastmath : f32 +// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] fastmath : f32 +// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL2]], %[[IMAG2]] : f32 +// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 +// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 +// CHECK: %[[NORM:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 +// CHECK: %[[REAL_SIGN:.*]] = arith.divf %[[REAL]], %[[NORM]] fastmath : f32 +// CHECK: %[[IMAG_SIGN:.*]] = arith.divf %[[IMAG]], %[[NORM]] fastmath : f32 +// CHECK: %[[SIGN:.*]] = complex.create %[[REAL_SIGN]], %[[IMAG_SIGN]] : complex +// CHECK: %[[RESULT:.*]] = arith.select %[[IS_ZERO]], %[[ARG]], %[[SIGN]] : complex +// CHECK: return %[[RESULT]] : complex -- GitLab From 09efe848cf2877ea7528411eaa0fe99224059256 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Sat, 6 Apr 2024 10:39:55 +0200 Subject: [PATCH 062/695] [libc][NFC] Rename `UInt.h` to `big_int.h` and `UInt128.h` to `uint128.h` for consistency (#87808) --- libc/fuzzing/__support/CMakeLists.txt | 2 +- libc/fuzzing/__support/uint_fuzz.cpp | 2 +- libc/src/__support/CMakeLists.txt | 10 +++++----- libc/src/__support/FPUtil/BasicOperations.h | 2 +- libc/src/__support/FPUtil/CMakeLists.txt | 2 +- libc/src/__support/FPUtil/FPBits.h | 2 +- libc/src/__support/FPUtil/Hypot.h | 2 +- libc/src/__support/FPUtil/dyadic_float.h | 2 +- libc/src/__support/FPUtil/generic/FMA.h | 2 +- libc/src/__support/FPUtil/generic/sqrt.h | 2 +- .../FPUtil/generic/sqrt_80_bit_long_double.h | 2 +- libc/src/__support/{UInt.h => big_int.h} | 0 libc/src/__support/float_to_string.h | 2 +- libc/src/__support/hash.h | 2 +- libc/src/__support/integer_literals.h | 2 +- libc/src/__support/integer_to_string.h | 2 +- libc/src/__support/str_to_float.h | 2 +- libc/src/__support/str_to_integer.h | 2 +- libc/src/__support/{UInt128.h => uint128.h} | 2 +- libc/src/math/generic/log_range_reduction.h | 2 +- libc/src/stdio/printf_core/CMakeLists.txt | 12 ++++++------ .../src/stdio/printf_core/float_dec_converter.h | 2 +- libc/test/UnitTest/CMakeLists.txt | 4 ++-- libc/test/UnitTest/LibcTest.cpp | 2 +- libc/test/UnitTest/StringUtils.h | 2 +- libc/test/UnitTest/TestLogger.cpp | 6 +++--- libc/test/src/__support/CMakeLists.txt | 4 ++-- libc/test/src/__support/CPP/CMakeLists.txt | 4 ++-- libc/test/src/__support/CPP/bit_test.cpp | 2 +- libc/test/src/__support/CPP/limits_test.cpp | 2 +- .../src/__support/FPUtil/dyadic_float_test.cpp | 2 +- .../__support/high_precision_decimal_test.cpp | 2 +- .../src/__support/integer_to_string_test.cpp | 4 ++-- libc/test/src/__support/math_extras_test.cpp | 2 +- libc/test/src/__support/str_to_fp_test.h | 2 +- libc/test/src/__support/uint_test.cpp | 2 +- libc/test/src/math/smoke/nanf128_test.cpp | 2 +- libc/test/src/stdlib/strtold_test.cpp | 2 +- .../bazel/llvm-project-overlay/libc/BUILD.bazel | 17 ++++++++--------- .../libc/test/UnitTest/BUILD.bazel | 4 ++-- .../libc/test/src/__support/BUILD.bazel | 5 +++-- .../libc/test/src/__support/CPP/BUILD.bazel | 4 ++-- .../libc/test/src/__support/FPUtil/BUILD.bazel | 2 +- 43 files changed, 68 insertions(+), 68 deletions(-) rename libc/src/__support/{UInt.h => big_int.h} (100%) rename libc/src/__support/{UInt128.h => uint128.h} (97%) diff --git a/libc/fuzzing/__support/CMakeLists.txt b/libc/fuzzing/__support/CMakeLists.txt index 278e914e3fbe..d4f6db71fdd8 100644 --- a/libc/fuzzing/__support/CMakeLists.txt +++ b/libc/fuzzing/__support/CMakeLists.txt @@ -3,5 +3,5 @@ add_libc_fuzzer( SRCS uint_fuzz.cpp DEPENDS - libc.src.__support.uint + libc.src.__support.big_int ) diff --git a/libc/fuzzing/__support/uint_fuzz.cpp b/libc/fuzzing/__support/uint_fuzz.cpp index f48f00d3b4ba..07149f511b83 100644 --- a/libc/fuzzing/__support/uint_fuzz.cpp +++ b/libc/fuzzing/__support/uint_fuzz.cpp @@ -1,5 +1,5 @@ #include "src/__support/CPP/bit.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "src/string/memory_utils/inline_memcpy.h" using namespace LIBC_NAMESPACE; diff --git a/libc/src/__support/CMakeLists.txt b/libc/src/__support/CMakeLists.txt index 7b1820d9bf35..dcae55e050bf 100644 --- a/libc/src/__support/CMakeLists.txt +++ b/libc/src/__support/CMakeLists.txt @@ -104,7 +104,7 @@ add_header_library( HDRS integer_to_string.h DEPENDS - .uint + .big_int libc.src.__support.common libc.src.__support.CPP.algorithm libc.src.__support.CPP.limits @@ -204,9 +204,9 @@ add_header_library( ) add_header_library( - uint + big_int HDRS - UInt.h + big_int.h DEPENDS .math_extras .number_pair @@ -220,9 +220,9 @@ add_header_library( add_header_library( uint128 HDRS - UInt128.h + uint128.h DEPENDS - .uint + .big_int libc.src.__support.macros.properties.types ) diff --git a/libc/src/__support/FPUtil/BasicOperations.h b/libc/src/__support/FPUtil/BasicOperations.h index 6e4156497618..e5ac101fedc0 100644 --- a/libc/src/__support/FPUtil/BasicOperations.h +++ b/libc/src/__support/FPUtil/BasicOperations.h @@ -14,9 +14,9 @@ #include "FEnvImpl.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY +#include "src/__support/uint128.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/__support/FPUtil/CMakeLists.txt b/libc/src/__support/FPUtil/CMakeLists.txt index 1af236ed9d6b..c75a7cd7e097 100644 --- a/libc/src/__support/FPUtil/CMakeLists.txt +++ b/libc/src/__support/FPUtil/CMakeLists.txt @@ -200,8 +200,8 @@ add_header_library( DEPENDS .fp_bits .multiply_add + libc.src.__support.big_int libc.src.__support.common - libc.src.__support.uint libc.src.__support.macros.optimization ) diff --git a/libc/src/__support/FPUtil/FPBits.h b/libc/src/__support/FPUtil/FPBits.h index 155bff2f5581..ab050360c353 100644 --- a/libc/src/__support/FPUtil/FPBits.h +++ b/libc/src/__support/FPUtil/FPBits.h @@ -11,13 +11,13 @@ #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" #include "src/__support/libc_assert.h" // LIBC_ASSERT #include "src/__support/macros/attributes.h" // LIBC_INLINE, LIBC_INLINE_VAR #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_FLOAT128 #include "src/__support/math_extras.h" // mask_trailing_ones #include "src/__support/sign.h" // Sign +#include "src/__support/uint128.h" #include diff --git a/libc/src/__support/FPUtil/Hypot.h b/libc/src/__support/FPUtil/Hypot.h index 2e6996573464..76b1f0797621 100644 --- a/libc/src/__support/FPUtil/Hypot.h +++ b/libc/src/__support/FPUtil/Hypot.h @@ -15,8 +15,8 @@ #include "rounding_mode.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" +#include "src/__support/uint128.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/__support/FPUtil/dyadic_float.h b/libc/src/__support/FPUtil/dyadic_float.h index e0c205f52383..49fb11971104 100644 --- a/libc/src/__support/FPUtil/dyadic_float.h +++ b/libc/src/__support/FPUtil/dyadic_float.h @@ -12,7 +12,7 @@ #include "FPBits.h" #include "multiply_add.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY #include diff --git a/libc/src/__support/FPUtil/generic/FMA.h b/libc/src/__support/FPUtil/generic/FMA.h index f03af9246337..f403aa7333b3 100644 --- a/libc/src/__support/FPUtil/generic/FMA.h +++ b/libc/src/__support/FPUtil/generic/FMA.h @@ -14,9 +14,9 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/rounding_mode.h" -#include "src/__support/UInt128.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY +#include "src/__support/uint128.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/__support/FPUtil/generic/sqrt.h b/libc/src/__support/FPUtil/generic/sqrt.h index b6b4aaecb2cc..7e7600ba6502 100644 --- a/libc/src/__support/FPUtil/generic/sqrt.h +++ b/libc/src/__support/FPUtil/generic/sqrt.h @@ -15,8 +15,8 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/rounding_mode.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" +#include "src/__support/uint128.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h index 656ade4f7735..6308ffe95493 100644 --- a/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h +++ b/libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h @@ -13,8 +13,8 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/rounding_mode.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" +#include "src/__support/uint128.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/__support/UInt.h b/libc/src/__support/big_int.h similarity index 100% rename from libc/src/__support/UInt.h rename to libc/src/__support/big_int.h diff --git a/libc/src/__support/float_to_string.h b/libc/src/__support/float_to_string.h index 4c59cfd99c2e..09b13324f25b 100644 --- a/libc/src/__support/float_to_string.h +++ b/libc/src/__support/float_to_string.h @@ -15,7 +15,7 @@ #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/dyadic_float.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "src/__support/common.h" #include "src/__support/libc_assert.h" #include "src/__support/macros/attributes.h" diff --git a/libc/src/__support/hash.h b/libc/src/__support/hash.h index 6b362ba83189..d1218fdc2592 100644 --- a/libc/src/__support/hash.h +++ b/libc/src/__support/hash.h @@ -11,8 +11,8 @@ #include "src/__support/CPP/bit.h" // rotl #include "src/__support/CPP/limits.h" // numeric_limits -#include "src/__support/UInt128.h" // UInt128 #include "src/__support/macros/attributes.h" // LIBC_INLINE +#include "src/__support/uint128.h" // UInt128 #include // For uint64_t namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/integer_literals.h b/libc/src/__support/integer_literals.h index e99799c3512e..5fb67464090c 100644 --- a/libc/src/__support/integer_literals.h +++ b/libc/src/__support/integer_literals.h @@ -14,8 +14,8 @@ #define LLVM_LIBC_SRC___SUPPORT_INTEGER_LITERALS_H #include "src/__support/CPP/limits.h" // CHAR_BIT -#include "src/__support/UInt128.h" // UInt128 #include "src/__support/macros/attributes.h" // LIBC_INLINE +#include "src/__support/uint128.h" // UInt128 #include // size_t #include // uintxx_t diff --git a/libc/src/__support/integer_to_string.h b/libc/src/__support/integer_to_string.h index f72d00d1a745..375f0e82960e 100644 --- a/libc/src/__support/integer_to_string.h +++ b/libc/src/__support/integer_to_string.h @@ -67,7 +67,7 @@ #include "src/__support/CPP/span.h" #include "src/__support/CPP/string_view.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt.h" // make_integral_or_big_int_unsigned_t +#include "src/__support/big_int.h" // make_integral_or_big_int_unsigned_t #include "src/__support/common.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/str_to_float.h b/libc/src/__support/str_to_float.h index f622b7edaa8a..cd0c07629f87 100644 --- a/libc/src/__support/str_to_float.h +++ b/libc/src/__support/str_to_float.h @@ -17,13 +17,13 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/dyadic_float.h" #include "src/__support/FPUtil/rounding_mode.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" #include "src/__support/ctype_utils.h" #include "src/__support/detailed_powers_of_ten.h" #include "src/__support/high_precision_decimal.h" #include "src/__support/str_to_integer.h" #include "src/__support/str_to_num_result.h" +#include "src/__support/uint128.h" #include "src/errno/libc_errno.h" // For ERANGE namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/str_to_integer.h b/libc/src/__support/str_to_integer.h index 02c71d40a1c0..6db851ab0e65 100644 --- a/libc/src/__support/str_to_integer.h +++ b/libc/src/__support/str_to_integer.h @@ -11,10 +11,10 @@ #include "src/__support/CPP/limits.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt128.h" #include "src/__support/common.h" #include "src/__support/ctype_utils.h" #include "src/__support/str_to_num_result.h" +#include "src/__support/uint128.h" #include "src/errno/libc_errno.h" // For ERANGE namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/UInt128.h b/libc/src/__support/uint128.h similarity index 97% rename from libc/src/__support/UInt128.h rename to libc/src/__support/uint128.h index b6ef9ca18eb0..722e79d0802e 100644 --- a/libc/src/__support/UInt128.h +++ b/libc/src/__support/uint128.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_UINT128_H #define LLVM_LIBC_SRC___SUPPORT_UINT128_H -#include "UInt.h" +#include "big_int.h" #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 #ifdef LIBC_TYPES_HAS_INT128 diff --git a/libc/src/math/generic/log_range_reduction.h b/libc/src/math/generic/log_range_reduction.h index 64c0fc3aa4f5..d12da47a2cfa 100644 --- a/libc/src/math/generic/log_range_reduction.h +++ b/libc/src/math/generic/log_range_reduction.h @@ -11,7 +11,7 @@ #include "common_constants.h" #include "src/__support/FPUtil/dyadic_float.h" -#include "src/__support/UInt128.h" +#include "src/__support/uint128.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/stdio/printf_core/CMakeLists.txt b/libc/src/stdio/printf_core/CMakeLists.txt index 7db79c54beb0..21ff0d43ab72 100644 --- a/libc/src/stdio/printf_core/CMakeLists.txt +++ b/libc/src/stdio/printf_core/CMakeLists.txt @@ -82,21 +82,21 @@ add_object_library( float_dec_converter.h fixed_converter.h #TODO: Check if this should be disabled when fixed unavail DEPENDS - .writer .core_structs .printf_config + .writer + libc.src.__support.big_int + libc.src.__support.common libc.src.__support.CPP.limits libc.src.__support.CPP.span libc.src.__support.CPP.string_view - libc.src.__support.FPUtil.fp_bits + libc.src.__support.float_to_string libc.src.__support.FPUtil.fenv_impl + libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.rounding_mode - libc.src.__support.common + libc.src.__support.integer_to_string libc.src.__support.libc_assert - libc.src.__support.uint libc.src.__support.uint128 - libc.src.__support.integer_to_string - libc.src.__support.float_to_string ) diff --git a/libc/src/stdio/printf_core/float_dec_converter.h b/libc/src/stdio/printf_core/float_dec_converter.h index c4e8aaa2f0e2..666e4c9fa75e 100644 --- a/libc/src/stdio/printf_core/float_dec_converter.h +++ b/libc/src/stdio/printf_core/float_dec_converter.h @@ -12,7 +12,7 @@ #include "src/__support/CPP/string_view.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/rounding_mode.h" -#include "src/__support/UInt.h" // is_big_int_v +#include "src/__support/big_int.h" // is_big_int_v #include "src/__support/float_to_string.h" #include "src/__support/integer_to_string.h" #include "src/__support/libc_assert.h" diff --git a/libc/test/UnitTest/CMakeLists.txt b/libc/test/UnitTest/CMakeLists.txt index d830d22bb540..4411170502ed 100644 --- a/libc/test/UnitTest/CMakeLists.txt +++ b/libc/test/UnitTest/CMakeLists.txt @@ -68,6 +68,7 @@ add_unittest_framework_library( Test.h TestLogger.h DEPENDS + libc.src.__support.big_int libc.src.__support.c_string libc.src.__support.CPP.string libc.src.__support.CPP.string_view @@ -75,7 +76,6 @@ add_unittest_framework_library( libc.src.__support.fixed_point.fx_rep libc.src.__support.macros.properties.types libc.src.__support.OSUtil.osutil - libc.src.__support.uint libc.src.__support.uint128 ) @@ -103,9 +103,9 @@ add_header_library( HDRS StringUtils.h DEPENDS + libc.src.__support.big_int libc.src.__support.CPP.string libc.src.__support.CPP.type_traits - libc.src.__support.uint ) add_unittest_framework_library( diff --git a/libc/test/UnitTest/LibcTest.cpp b/libc/test/UnitTest/LibcTest.cpp index 03cd25191ecd..846ad331e523 100644 --- a/libc/test/UnitTest/LibcTest.cpp +++ b/libc/test/UnitTest/LibcTest.cpp @@ -11,9 +11,9 @@ #include "include/llvm-libc-macros/stdfix-macros.h" #include "src/__support/CPP/string.h" #include "src/__support/CPP/string_view.h" -#include "src/__support/UInt128.h" #include "src/__support/fixed_point/fx_rep.h" #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 +#include "src/__support/uint128.h" #include "test/UnitTest/TestLogger.h" #if __STDC_HOSTED__ diff --git a/libc/test/UnitTest/StringUtils.h b/libc/test/UnitTest/StringUtils.h index cab0b58f9690..61d74b49d4c9 100644 --- a/libc/test/UnitTest/StringUtils.h +++ b/libc/test/UnitTest/StringUtils.h @@ -11,7 +11,7 @@ #include "src/__support/CPP/string.h" #include "src/__support/CPP/type_traits.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" namespace LIBC_NAMESPACE { diff --git a/libc/test/UnitTest/TestLogger.cpp b/libc/test/UnitTest/TestLogger.cpp index 4756188b46cb..feba4b5ddd39 100644 --- a/libc/test/UnitTest/TestLogger.cpp +++ b/libc/test/UnitTest/TestLogger.cpp @@ -1,10 +1,10 @@ #include "test/UnitTest/TestLogger.h" #include "src/__support/CPP/string.h" #include "src/__support/CPP/string_view.h" -#include "src/__support/OSUtil/io.h" // write_to_stderr -#include "src/__support/UInt.h" // is_big_int -#include "src/__support/UInt128.h" +#include "src/__support/OSUtil/io.h" // write_to_stderr +#include "src/__support/big_int.h" // is_big_int #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 +#include "src/__support/uint128.h" #include diff --git a/libc/test/src/__support/CMakeLists.txt b/libc/test/src/__support/CMakeLists.txt index 51b897f8b595..02ee91d0dc99 100644 --- a/libc/test/src/__support/CMakeLists.txt +++ b/libc/test/src/__support/CMakeLists.txt @@ -78,11 +78,11 @@ add_libc_test( SRCS integer_to_string_test.cpp DEPENDS + libc.src.__support.big_int libc.src.__support.CPP.limits libc.src.__support.CPP.string_view libc.src.__support.integer_literals libc.src.__support.integer_to_string - libc.src.__support.uint libc.src.__support.uint128 ) @@ -107,9 +107,9 @@ if(NOT LIBC_TARGET_ARCHITECTURE_IS_NVPTX) SRCS uint_test.cpp DEPENDS + libc.src.__support.big_int libc.src.__support.CPP.optional libc.src.__support.macros.properties.types - libc.src.__support.uint ) endif() diff --git a/libc/test/src/__support/CPP/CMakeLists.txt b/libc/test/src/__support/CPP/CMakeLists.txt index 74aa0c705ec4..708548f812c6 100644 --- a/libc/test/src/__support/CPP/CMakeLists.txt +++ b/libc/test/src/__support/CPP/CMakeLists.txt @@ -17,9 +17,9 @@ add_libc_test( SRCS bit_test.cpp DEPENDS + libc.src.__support.big_int libc.src.__support.CPP.bit libc.src.__support.macros.properties.types - libc.src.__support.uint ) add_libc_test( @@ -59,9 +59,9 @@ add_libc_test( SRCS limits_test.cpp DEPENDS + libc.src.__support.big_int libc.src.__support.CPP.limits libc.src.__support.macros.properties.types - libc.src.__support.uint ) add_libc_test( diff --git a/libc/test/src/__support/CPP/bit_test.cpp b/libc/test/src/__support/CPP/bit_test.cpp index 875b47e6a198..299623d2ca24 100644 --- a/libc/test/src/__support/CPP/bit_test.cpp +++ b/libc/test/src/__support/CPP/bit_test.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/CPP/bit.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 #include "test/UnitTest/Test.h" diff --git a/libc/test/src/__support/CPP/limits_test.cpp b/libc/test/src/__support/CPP/limits_test.cpp index efcd6839d073..bcf7d5ed6a6e 100644 --- a/libc/test/src/__support/CPP/limits_test.cpp +++ b/libc/test/src/__support/CPP/limits_test.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/CPP/limits.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 #include "test/UnitTest/Test.h" diff --git a/libc/test/src/__support/FPUtil/dyadic_float_test.cpp b/libc/test/src/__support/FPUtil/dyadic_float_test.cpp index 5ee9aaad5638..809381ed47b5 100644 --- a/libc/test/src/__support/FPUtil/dyadic_float_test.cpp +++ b/libc/test/src/__support/FPUtil/dyadic_float_test.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/dyadic_float.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" diff --git a/libc/test/src/__support/high_precision_decimal_test.cpp b/libc/test/src/__support/high_precision_decimal_test.cpp index 2bb28bcdab02..7a3c323b06d5 100644 --- a/libc/test/src/__support/high_precision_decimal_test.cpp +++ b/libc/test/src/__support/high_precision_decimal_test.cpp @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#include "src/__support/UInt128.h" #include "src/__support/high_precision_decimal.h" +#include "src/__support/uint128.h" #include "test/UnitTest/Test.h" diff --git a/libc/test/src/__support/integer_to_string_test.cpp b/libc/test/src/__support/integer_to_string_test.cpp index 270fddd828b6..e644751b56c9 100644 --- a/libc/test/src/__support/integer_to_string_test.cpp +++ b/libc/test/src/__support/integer_to_string_test.cpp @@ -9,10 +9,10 @@ #include "src/__support/CPP/limits.h" #include "src/__support/CPP/span.h" #include "src/__support/CPP/string_view.h" -#include "src/__support/UInt.h" -#include "src/__support/UInt128.h" +#include "src/__support/big_int.h" #include "src/__support/integer_literals.h" #include "src/__support/integer_to_string.h" +#include "src/__support/uint128.h" #include "test/UnitTest/Test.h" diff --git a/libc/test/src/__support/math_extras_test.cpp b/libc/test/src/__support/math_extras_test.cpp index 401e631ea4ba..004788896517 100644 --- a/libc/test/src/__support/math_extras_test.cpp +++ b/libc/test/src/__support/math_extras_test.cpp @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// -#include "src/__support/UInt128.h" // UInt<128> #include "src/__support/integer_literals.h" #include "src/__support/math_extras.h" +#include "src/__support/uint128.h" // UInt<128> #include "test/UnitTest/Test.h" namespace LIBC_NAMESPACE { diff --git a/libc/test/src/__support/str_to_fp_test.h b/libc/test/src/__support/str_to_fp_test.h index bddff035fdd1..8d6181cda884 100644 --- a/libc/test/src/__support/str_to_fp_test.h +++ b/libc/test/src/__support/str_to_fp_test.h @@ -7,8 +7,8 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/FPBits.h" -#include "src/__support/UInt128.h" #include "src/__support/str_to_float.h" +#include "src/__support/uint128.h" #include "src/errno/libc_errno.h" #include "test/UnitTest/Test.h" diff --git a/libc/test/src/__support/uint_test.cpp b/libc/test/src/__support/uint_test.cpp index 7f278619b8c9..fadec0cc313b 100644 --- a/libc/test/src/__support/uint_test.cpp +++ b/libc/test/src/__support/uint_test.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/CPP/optional.h" -#include "src/__support/UInt.h" +#include "src/__support/big_int.h" #include "src/__support/integer_literals.h" // parse_unsigned_bigint #include "src/__support/macros/properties/types.h" // LIBC_TYPES_HAS_INT128 diff --git a/libc/test/src/math/smoke/nanf128_test.cpp b/libc/test/src/math/smoke/nanf128_test.cpp index 2a9f57de5b43..652e35ccb53d 100644 --- a/libc/test/src/math/smoke/nanf128_test.cpp +++ b/libc/test/src/math/smoke/nanf128_test.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/FPBits.h" -#include "src/__support/UInt128.h" +#include "src/__support/uint128.h" #include "src/math/nanf128.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" diff --git a/libc/test/src/stdlib/strtold_test.cpp b/libc/test/src/stdlib/strtold_test.cpp index 2066e9635aba..2c9f542930bf 100644 --- a/libc/test/src/stdlib/strtold_test.cpp +++ b/libc/test/src/stdlib/strtold_test.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/FPBits.h" -#include "src/__support/UInt128.h" +#include "src/__support/uint128.h" #include "src/errno/libc_errno.h" #include "src/stdlib/strtold.h" diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 1fb93cac42b9..fd5309e688c3 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -113,7 +113,6 @@ libc_support_library( hdrs = ["hdr/math_macros.h"], ) - ############################### Support libraries ############################## libc_support_library( @@ -484,12 +483,12 @@ libc_support_library( "src/__support/ryu_long_double_constants.h", ], deps = [ + ":__support_big_int", ":__support_common", ":__support_cpp_type_traits", ":__support_fputil_dyadic_float", ":__support_fputil_fp_bits", ":__support_libc_assert", - ":__support_uint", ], ) @@ -502,8 +501,8 @@ libc_support_library( ) libc_support_library( - name = "__support_uint", - hdrs = ["src/__support/UInt.h"], + name = "__support_big_int", + hdrs = ["src/__support/big_int.h"], deps = [ ":__support_cpp_array", ":__support_cpp_bit", @@ -528,11 +527,11 @@ libc_support_library( libc_support_library( name = "__support_uint128", - hdrs = ["src/__support/UInt128.h"], + hdrs = ["src/__support/uint128.h"], deps = [ + ":__support_big_int", ":__support_macros_attributes", ":__support_macros_properties_types", - ":__support_uint", ], ) @@ -561,6 +560,7 @@ libc_support_library( name = "__support_integer_to_string", hdrs = ["src/__support/integer_to_string.h"], deps = [ + ":__support_big_int", ":__support_common", ":__support_cpp_algorithm", ":__support_cpp_bit", @@ -569,7 +569,6 @@ libc_support_library( ":__support_cpp_span", ":__support_cpp_string_view", ":__support_cpp_type_traits", - ":__support_uint", ], ) @@ -973,11 +972,11 @@ libc_support_library( name = "__support_fputil_dyadic_float", hdrs = ["src/__support/FPUtil/dyadic_float.h"], deps = [ + ":__support_big_int", ":__support_common", ":__support_fputil_fp_bits", ":__support_fputil_multiply_add", ":__support_macros_optimization", - ":__support_uint", ], ) @@ -3223,6 +3222,7 @@ libc_support_library( ], defines = PRINTF_COPTS, deps = [ + ":__support_big_int", ":__support_common", ":__support_cpp_limits", ":__support_cpp_span", @@ -3233,7 +3233,6 @@ libc_support_library( ":__support_fputil_rounding_mode", ":__support_integer_to_string", ":__support_libc_assert", - ":__support_uint", ":__support_uint128", ":printf_config", ":printf_core_structs", diff --git a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel index 7d77b6114464..2fc7e36aebb4 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel @@ -15,11 +15,11 @@ libc_support_library( srcs = ["TestLogger.cpp"], hdrs = ["TestLogger.h"], deps = [ + "//libc:__support_big_int", "//libc:__support_cpp_string", "//libc:__support_cpp_string_view", "//libc:__support_macros_properties_types", "//libc:__support_osutil_io", - "//libc:__support_uint", "//libc:__support_uint128", ], ) @@ -128,8 +128,8 @@ libc_support_library( "StringUtils.h", ], deps = [ + "//libc:__support_big_int", "//libc:__support_cpp_string", "//libc:__support_cpp_type_traits", - "//libc:__support_uint", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel index 9e1b25e10d6c..0ed5951904a0 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel @@ -64,12 +64,12 @@ libc_test( name = "integer_to_string_test", srcs = ["integer_to_string_test.cpp"], deps = [ + "//libc:__support_big_int", "//libc:__support_cpp_limits", "//libc:__support_cpp_span", "//libc:__support_cpp_string_view", "//libc:__support_integer_literals", "//libc:__support_integer_to_string", - "//libc:__support_uint", "//libc:__support_uint128", ], ) @@ -86,11 +86,12 @@ libc_test( name = "uint_test", srcs = ["uint_test.cpp"], deps = [ + "//libc:__support_big_int", "//libc:__support_cpp_optional", "//libc:__support_integer_literals", "//libc:__support_macros_properties_types", - "//libc:__support_uint", "//libc:hdr_math_macros", + "//libc:llvm_libc_macros_math_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/CPP/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/CPP/BUILD.bazel index dad1c7708e44..96dafbc6da48 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/CPP/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/CPP/BUILD.bazel @@ -26,9 +26,9 @@ libc_test( name = "bit_test", srcs = ["bit_test.cpp"], deps = [ + "//libc:__support_big_int", "//libc:__support_cpp_bit", "//libc:__support_macros_properties_types", - "//libc:__support_uint", ], ) @@ -48,9 +48,9 @@ libc_test( name = "limits_test", srcs = ["limits_test.cpp"], deps = [ + "//libc:__support_big_int", "//libc:__support_cpp_limits", "//libc:__support_macros_properties_types", - "//libc:__support_uint", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel index 18683e42724a..132c146b507b 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel @@ -26,8 +26,8 @@ libc_test( srcs = ["dyadic_float_test.cpp"], copts = ["-frounding-math"], deps = [ + "//libc:__support_big_int", "//libc:__support_fputil_dyadic_float", - "//libc:__support_uint", "//libc:__support_uint128", "//libc/test/UnitTest:fp_test_helpers", "//libc/utils/MPFRWrapper:mpfr_wrapper", -- GitLab From 684f27d37a6f1faf546a71bcb784b48c7fc8b7e0 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Sat, 6 Apr 2024 01:50:42 -0700 Subject: [PATCH 063/695] [clang-format][NFC] Use `is` instead of `getType() ==` --- clang/lib/Format/FormatTokenLexer.cpp | 2 +- clang/lib/Format/TokenAnnotator.cpp | 10 ++++------ clang/lib/Format/UnwrappedLineParser.cpp | 15 +++++++-------- clang/lib/Format/WhitespaceManager.cpp | 3 +-- 4 files changed, 13 insertions(+), 17 deletions(-) diff --git a/clang/lib/Format/FormatTokenLexer.cpp b/clang/lib/Format/FormatTokenLexer.cpp index 036f7e6a4efc..f430d3764bab 100644 --- a/clang/lib/Format/FormatTokenLexer.cpp +++ b/clang/lib/Format/FormatTokenLexer.cpp @@ -404,7 +404,7 @@ bool FormatTokenLexer::tryMergeNullishCoalescingEqual() { return false; auto &NullishCoalescing = *(Tokens.end() - 2); auto &Equal = *(Tokens.end() - 1); - if (NullishCoalescing->getType() != TT_NullCoalescingOperator || + if (NullishCoalescing->isNot(TT_NullCoalescingOperator) || Equal->isNot(tok::equal)) { return false; } diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 3e9988d50945..9abd4282103b 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -825,8 +825,7 @@ private: Parent->overwriteFixedType(TT_BinaryOperator); } // An arrow after an ObjC method expression is not a lambda arrow. - if (CurrentToken->getType() == TT_ObjCMethodExpr && - CurrentToken->Next && + if (CurrentToken->is(TT_ObjCMethodExpr) && CurrentToken->Next && CurrentToken->Next->is(TT_TrailingReturnArrow)) { CurrentToken->Next->overwriteFixedType(TT_Unknown); } @@ -1563,7 +1562,7 @@ private: case tok::l_brace: if (Style.Language == FormatStyle::LK_TextProto) { FormatToken *Previous = Tok->getPreviousNonComment(); - if (Previous && Previous->getType() != TT_DictLiteral) + if (Previous && Previous->isNot(TT_DictLiteral)) Previous->setType(TT_SelectorName); } Scopes.push_back(getScopeType(*Tok)); @@ -1583,7 +1582,7 @@ private: Tok->Previous->isOneOf(TT_SelectorName, TT_DictLiteral))) { Tok->setType(TT_DictLiteral); FormatToken *Previous = Tok->getPreviousNonComment(); - if (Previous && Previous->getType() != TT_DictLiteral) + if (Previous && Previous->isNot(TT_DictLiteral)) Previous->setType(TT_SelectorName); } if (Style.isTableGen()) @@ -4754,8 +4753,7 @@ bool TokenAnnotator::spaceRequiredBetween(const AnnotatedLine &Line, // Objective-C dictionary literal -> no space before closing brace. return false; } - if (Right.getType() == TT_TrailingAnnotation && - Right.isOneOf(tok::amp, tok::ampamp) && + if (Right.is(TT_TrailingAnnotation) && Right.isOneOf(tok::amp, tok::ampamp) && Left.isOneOf(tok::kw_const, tok::kw_volatile) && (!Right.Next || Right.Next->is(tok::semi))) { // Match const and volatile ref-qualifiers without any additional diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 57d8dbcf3b4c..6df7cc1c3955 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -366,9 +366,9 @@ bool UnwrappedLineParser::parseLevel(const FormatToken *OpeningBrace, continue; } tok::TokenKind Kind = FormatTok->Tok.getKind(); - if (FormatTok->getType() == TT_MacroBlockBegin) + if (FormatTok->is(TT_MacroBlockBegin)) Kind = tok::l_brace; - else if (FormatTok->getType() == TT_MacroBlockEnd) + else if (FormatTok->is(TT_MacroBlockEnd)) Kind = tok::r_brace; auto ParseDefault = [this, OpeningBrace, IfKind, &IfLBrace, &HasDoWhile, @@ -4709,14 +4709,13 @@ void UnwrappedLineParser::readToken(int LevelDifference) { do { FormatTok = Tokens->getNextToken(); assert(FormatTok); - while (FormatTok->getType() == TT_ConflictStart || - FormatTok->getType() == TT_ConflictEnd || - FormatTok->getType() == TT_ConflictAlternative) { - if (FormatTok->getType() == TT_ConflictStart) + while (FormatTok->isOneOf(TT_ConflictStart, TT_ConflictEnd, + TT_ConflictAlternative)) { + if (FormatTok->is(TT_ConflictStart)) conditionalCompilationStart(/*Unreachable=*/false); - else if (FormatTok->getType() == TT_ConflictAlternative) + else if (FormatTok->is(TT_ConflictAlternative)) conditionalCompilationAlternative(); - else if (FormatTok->getType() == TT_ConflictEnd) + else if (FormatTok->is(TT_ConflictEnd)) conditionalCompilationEnd(); FormatTok = Tokens->getNextToken(); FormatTok->MustBreakBefore = true; diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index d06c42d5f4c5..4f822807dd98 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -473,8 +473,7 @@ AlignTokenSequence(const FormatStyle &Style, unsigned Start, unsigned End, Style.ReferenceAlignment != FormatStyle::RAS_Right && Style.ReferenceAlignment != FormatStyle::RAS_Pointer; for (int Previous = i - 1; - Previous >= 0 && - Changes[Previous].Tok->getType() == TT_PointerOrReference; + Previous >= 0 && Changes[Previous].Tok->is(TT_PointerOrReference); --Previous) { assert(Changes[Previous].Tok->isPointerOrReference()); if (Changes[Previous].Tok->isNot(tok::star)) { -- GitLab From f5d7e755b8e9623f24812dcab8f4e09e888b2527 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 6 Apr 2024 11:45:16 +0200 Subject: [PATCH 064/695] [bazel] Fix the build after 27b2d7d4bb790ec1e7430bf18b1bc2f6e0800d0d --- utils/bazel/llvm-project-overlay/clang/BUILD.bazel | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index 54cecfaeb20c..a69894ea7a40 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -2042,6 +2042,7 @@ cc_library( name = "install_api", srcs = glob([ "lib/InstallAPI/*.cpp", + "lib/InstallAPI/*.h", ]), hdrs = glob([ "include/clang/InstallAPI/*.h", -- GitLab From d2884444472e92a8282f4d215a27128ac83a26b9 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Sat, 6 Apr 2024 15:10:48 +0400 Subject: [PATCH 065/695] [clang][NFC] Introduce `SemaBase` (#87634) This is a follow-up to #84184. Multiple reviewers there pointed out to me that we should have a common base class for `Sema` and `SemaOpenACC` to avoid code duplication for common helpers like `getLangOpts()`. On top of that, `Diag()` function was requested for `SemaOpenACC`. This patch delivers both. The intent is to keep `SemaBase` as small as possible, as things there are globally available across `Sema` and its parts without any additional effort from usage side. Overused, this can undermine the whole endeavor of splitting `Sema` apart. Apart of shuffling code around, this patch introduces a helper private function `SemaDiagnosticBuilder::getDeviceDeferredDiags()`, the sole purpose of which is to encapsulate member access into (incomplete) `Sema` for function templates defined in the header, where `Sema` can't be complete. --- clang/include/clang/Sema/Sema.h | 204 +--------------------- clang/include/clang/Sema/SemaBase.h | 224 +++++++++++++++++++++++++ clang/include/clang/Sema/SemaOpenACC.h | 14 +- clang/lib/Sema/CMakeLists.txt | 1 + clang/lib/Sema/Sema.cpp | 45 +---- clang/lib/Sema/SemaBase.cpp | 85 ++++++++++ clang/lib/Sema/SemaOpenACC.cpp | 16 +- 7 files changed, 329 insertions(+), 260 deletions(-) create mode 100644 clang/include/clang/Sema/SemaBase.h create mode 100644 clang/lib/Sema/SemaBase.cpp diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index f52816e12efe..f49bc724c96c 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -55,6 +55,7 @@ #include "clang/Sema/ObjCMethodList.h" #include "clang/Sema/Ownership.h" #include "clang/Sema/Scope.h" +#include "clang/Sema/SemaBase.h" #include "clang/Sema/SemaConcept.h" #include "clang/Sema/TypoCorrection.h" #include "clang/Sema/Weak.h" @@ -422,7 +423,7 @@ enum class TemplateDeductionResult { /// Sema - This implements semantic analysis and AST building for C. /// \nosubgrouping -class Sema final { +class Sema final : public SemaBase { // Table of Contents // ----------------- // 1. Semantic Analysis (Sema.cpp) @@ -512,195 +513,6 @@ public: /// void addExternalSource(ExternalSemaSource *E); - /// Helper class that creates diagnostics with optional - /// template instantiation stacks. - /// - /// This class provides a wrapper around the basic DiagnosticBuilder - /// class that emits diagnostics. ImmediateDiagBuilder is - /// responsible for emitting the diagnostic (as DiagnosticBuilder - /// does) and, if the diagnostic comes from inside a template - /// instantiation, printing the template instantiation stack as - /// well. - class ImmediateDiagBuilder : public DiagnosticBuilder { - Sema &SemaRef; - unsigned DiagID; - - public: - ImmediateDiagBuilder(DiagnosticBuilder &DB, Sema &SemaRef, unsigned DiagID) - : DiagnosticBuilder(DB), SemaRef(SemaRef), DiagID(DiagID) {} - ImmediateDiagBuilder(DiagnosticBuilder &&DB, Sema &SemaRef, unsigned DiagID) - : DiagnosticBuilder(DB), SemaRef(SemaRef), DiagID(DiagID) {} - - // This is a cunning lie. DiagnosticBuilder actually performs move - // construction in its copy constructor (but due to varied uses, it's not - // possible to conveniently express this as actual move construction). So - // the default copy ctor here is fine, because the base class disables the - // source anyway, so the user-defined ~ImmediateDiagBuilder is a safe no-op - // in that case anwyay. - ImmediateDiagBuilder(const ImmediateDiagBuilder &) = default; - - ~ImmediateDiagBuilder() { - // If we aren't active, there is nothing to do. - if (!isActive()) - return; - - // Otherwise, we need to emit the diagnostic. First clear the diagnostic - // builder itself so it won't emit the diagnostic in its own destructor. - // - // This seems wasteful, in that as written the DiagnosticBuilder dtor will - // do its own needless checks to see if the diagnostic needs to be - // emitted. However, because we take care to ensure that the builder - // objects never escape, a sufficiently smart compiler will be able to - // eliminate that code. - Clear(); - - // Dispatch to Sema to emit the diagnostic. - SemaRef.EmitCurrentDiagnostic(DiagID); - } - - /// Teach operator<< to produce an object of the correct type. - template - friend const ImmediateDiagBuilder & - operator<<(const ImmediateDiagBuilder &Diag, const T &Value) { - const DiagnosticBuilder &BaseDiag = Diag; - BaseDiag << Value; - return Diag; - } - - // It is necessary to limit this to rvalue reference to avoid calling this - // function with a bitfield lvalue argument since non-const reference to - // bitfield is not allowed. - template ::value>> - const ImmediateDiagBuilder &operator<<(T &&V) const { - const DiagnosticBuilder &BaseDiag = *this; - BaseDiag << std::move(V); - return *this; - } - }; - - /// A generic diagnostic builder for errors which may or may not be deferred. - /// - /// In CUDA, there exist constructs (e.g. variable-length arrays, try/catch) - /// which are not allowed to appear inside __device__ functions and are - /// allowed to appear in __host__ __device__ functions only if the host+device - /// function is never codegen'ed. - /// - /// To handle this, we use the notion of "deferred diagnostics", where we - /// attach a diagnostic to a FunctionDecl that's emitted iff it's codegen'ed. - /// - /// This class lets you emit either a regular diagnostic, a deferred - /// diagnostic, or no diagnostic at all, according to an argument you pass to - /// its constructor, thus simplifying the process of creating these "maybe - /// deferred" diagnostics. - class SemaDiagnosticBuilder { - public: - enum Kind { - /// Emit no diagnostics. - K_Nop, - /// Emit the diagnostic immediately (i.e., behave like Sema::Diag()). - K_Immediate, - /// Emit the diagnostic immediately, and, if it's a warning or error, also - /// emit a call stack showing how this function can be reached by an a - /// priori known-emitted function. - K_ImmediateWithCallStack, - /// Create a deferred diagnostic, which is emitted only if the function - /// it's attached to is codegen'ed. Also emit a call stack as with - /// K_ImmediateWithCallStack. - K_Deferred - }; - - SemaDiagnosticBuilder(Kind K, SourceLocation Loc, unsigned DiagID, - const FunctionDecl *Fn, Sema &S); - SemaDiagnosticBuilder(SemaDiagnosticBuilder &&D); - SemaDiagnosticBuilder(const SemaDiagnosticBuilder &) = default; - - // The copy and move assignment operator is defined as deleted pending - // further motivation. - SemaDiagnosticBuilder &operator=(const SemaDiagnosticBuilder &) = delete; - SemaDiagnosticBuilder &operator=(SemaDiagnosticBuilder &&) = delete; - - ~SemaDiagnosticBuilder(); - - bool isImmediate() const { return ImmediateDiag.has_value(); } - - /// Convertible to bool: True if we immediately emitted an error, false if - /// we didn't emit an error or we created a deferred error. - /// - /// Example usage: - /// - /// if (SemaDiagnosticBuilder(...) << foo << bar) - /// return ExprError(); - /// - /// But see CUDADiagIfDeviceCode() and CUDADiagIfHostCode() -- you probably - /// want to use these instead of creating a SemaDiagnosticBuilder yourself. - operator bool() const { return isImmediate(); } - - template - friend const SemaDiagnosticBuilder & - operator<<(const SemaDiagnosticBuilder &Diag, const T &Value) { - if (Diag.ImmediateDiag) - *Diag.ImmediateDiag << Value; - else if (Diag.PartialDiagId) - Diag.S.DeviceDeferredDiags[Diag.Fn][*Diag.PartialDiagId].second - << Value; - return Diag; - } - - // It is necessary to limit this to rvalue reference to avoid calling this - // function with a bitfield lvalue argument since non-const reference to - // bitfield is not allowed. - template ::value>> - const SemaDiagnosticBuilder &operator<<(T &&V) const { - if (ImmediateDiag) - *ImmediateDiag << std::move(V); - else if (PartialDiagId) - S.DeviceDeferredDiags[Fn][*PartialDiagId].second << std::move(V); - return *this; - } - - friend const SemaDiagnosticBuilder & - operator<<(const SemaDiagnosticBuilder &Diag, const PartialDiagnostic &PD) { - if (Diag.ImmediateDiag) - PD.Emit(*Diag.ImmediateDiag); - else if (Diag.PartialDiagId) - Diag.S.DeviceDeferredDiags[Diag.Fn][*Diag.PartialDiagId].second = PD; - return Diag; - } - - void AddFixItHint(const FixItHint &Hint) const { - if (ImmediateDiag) - ImmediateDiag->AddFixItHint(Hint); - else if (PartialDiagId) - S.DeviceDeferredDiags[Fn][*PartialDiagId].second.AddFixItHint(Hint); - } - - friend ExprResult ExprError(const SemaDiagnosticBuilder &) { - return ExprError(); - } - friend StmtResult StmtError(const SemaDiagnosticBuilder &) { - return StmtError(); - } - operator ExprResult() const { return ExprError(); } - operator StmtResult() const { return StmtError(); } - operator TypeResult() const { return TypeError(); } - operator DeclResult() const { return DeclResult(true); } - operator MemInitResult() const { return MemInitResult(true); } - - private: - Sema &S; - SourceLocation Loc; - unsigned DiagID; - const FunctionDecl *Fn; - bool ShowCallStack; - - // Invariant: At most one of these Optionals has a value. - // FIXME: Switch these to a Variant once that exists. - std::optional ImmediateDiag; - std::optional PartialDiagId; - }; - void PrintStats() const; /// Warn that the stack is nearly exhausted. @@ -742,14 +554,6 @@ public: void addImplicitTypedef(StringRef Name, QualType T); - /// Emit a diagnostic. - SemaDiagnosticBuilder Diag(SourceLocation Loc, unsigned DiagID, - bool DeferHint = false); - - /// Emit a partial diagnostic. - SemaDiagnosticBuilder Diag(SourceLocation Loc, const PartialDiagnostic &PD, - bool DeferHint = false); - /// Whether uncompilable error has occurred. This includes error happens /// in deferred diagnostics. bool hasUncompilableErrorOccurred() const; @@ -13115,9 +12919,7 @@ public: /// Diagnostics that are emitted only if we discover that the given function /// must be codegen'ed. Because handling these correctly adds overhead to /// compilation, this is currently only enabled for CUDA compilations. - llvm::DenseMap, - std::vector> - DeviceDeferredDiags; + SemaDiagnosticBuilder::DeferredDiagnosticsType DeviceDeferredDiags; /// A pair of a canonical FunctionDecl and a SourceLocation. When used as the /// key in a hashtable, both the FD and location are hashed. diff --git a/clang/include/clang/Sema/SemaBase.h b/clang/include/clang/Sema/SemaBase.h new file mode 100644 index 000000000000..ff718022fca0 --- /dev/null +++ b/clang/include/clang/Sema/SemaBase.h @@ -0,0 +1,224 @@ +//===--- SemaBase.h - Common utilities for semantic analysis-----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the SemaBase class, which provides utilities for Sema +// and its parts like SemaOpenACC. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_SEMA_SEMABASE_H +#define LLVM_CLANG_SEMA_SEMABASE_H + +#include "clang/AST/Decl.h" +#include "clang/AST/Redeclarable.h" +#include "clang/Basic/Diagnostic.h" +#include "clang/Basic/PartialDiagnostic.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Sema/Ownership.h" +#include "llvm/ADT/DenseMap.h" +#include +#include +#include +#include + +namespace clang { + +class ASTContext; +class DiagnosticsEngine; +class LangOptions; +class Sema; + +class SemaBase { +public: + SemaBase(Sema &S); + + Sema &SemaRef; + + ASTContext &getASTContext() const; + DiagnosticsEngine &getDiagnostics() const; + const LangOptions &getLangOpts() const; + + /// Helper class that creates diagnostics with optional + /// template instantiation stacks. + /// + /// This class provides a wrapper around the basic DiagnosticBuilder + /// class that emits diagnostics. ImmediateDiagBuilder is + /// responsible for emitting the diagnostic (as DiagnosticBuilder + /// does) and, if the diagnostic comes from inside a template + /// instantiation, printing the template instantiation stack as + /// well. + class ImmediateDiagBuilder : public DiagnosticBuilder { + Sema &SemaRef; + unsigned DiagID; + + public: + ImmediateDiagBuilder(DiagnosticBuilder &DB, Sema &SemaRef, unsigned DiagID) + : DiagnosticBuilder(DB), SemaRef(SemaRef), DiagID(DiagID) {} + ImmediateDiagBuilder(DiagnosticBuilder &&DB, Sema &SemaRef, unsigned DiagID) + : DiagnosticBuilder(DB), SemaRef(SemaRef), DiagID(DiagID) {} + + // This is a cunning lie. DiagnosticBuilder actually performs move + // construction in its copy constructor (but due to varied uses, it's not + // possible to conveniently express this as actual move construction). So + // the default copy ctor here is fine, because the base class disables the + // source anyway, so the user-defined ~ImmediateDiagBuilder is a safe no-op + // in that case anwyay. + ImmediateDiagBuilder(const ImmediateDiagBuilder &) = default; + + ~ImmediateDiagBuilder(); + + /// Teach operator<< to produce an object of the correct type. + template + friend const ImmediateDiagBuilder & + operator<<(const ImmediateDiagBuilder &Diag, const T &Value) { + const DiagnosticBuilder &BaseDiag = Diag; + BaseDiag << Value; + return Diag; + } + + // It is necessary to limit this to rvalue reference to avoid calling this + // function with a bitfield lvalue argument since non-const reference to + // bitfield is not allowed. + template ::value>> + const ImmediateDiagBuilder &operator<<(T &&V) const { + const DiagnosticBuilder &BaseDiag = *this; + BaseDiag << std::move(V); + return *this; + } + }; + + /// A generic diagnostic builder for errors which may or may not be deferred. + /// + /// In CUDA, there exist constructs (e.g. variable-length arrays, try/catch) + /// which are not allowed to appear inside __device__ functions and are + /// allowed to appear in __host__ __device__ functions only if the host+device + /// function is never codegen'ed. + /// + /// To handle this, we use the notion of "deferred diagnostics", where we + /// attach a diagnostic to a FunctionDecl that's emitted iff it's codegen'ed. + /// + /// This class lets you emit either a regular diagnostic, a deferred + /// diagnostic, or no diagnostic at all, according to an argument you pass to + /// its constructor, thus simplifying the process of creating these "maybe + /// deferred" diagnostics. + class SemaDiagnosticBuilder { + public: + enum Kind { + /// Emit no diagnostics. + K_Nop, + /// Emit the diagnostic immediately (i.e., behave like Sema::Diag()). + K_Immediate, + /// Emit the diagnostic immediately, and, if it's a warning or error, also + /// emit a call stack showing how this function can be reached by an a + /// priori known-emitted function. + K_ImmediateWithCallStack, + /// Create a deferred diagnostic, which is emitted only if the function + /// it's attached to is codegen'ed. Also emit a call stack as with + /// K_ImmediateWithCallStack. + K_Deferred + }; + + SemaDiagnosticBuilder(Kind K, SourceLocation Loc, unsigned DiagID, + const FunctionDecl *Fn, Sema &S); + SemaDiagnosticBuilder(SemaDiagnosticBuilder &&D); + SemaDiagnosticBuilder(const SemaDiagnosticBuilder &) = default; + + // The copy and move assignment operator is defined as deleted pending + // further motivation. + SemaDiagnosticBuilder &operator=(const SemaDiagnosticBuilder &) = delete; + SemaDiagnosticBuilder &operator=(SemaDiagnosticBuilder &&) = delete; + + ~SemaDiagnosticBuilder(); + + bool isImmediate() const { return ImmediateDiag.has_value(); } + + /// Convertible to bool: True if we immediately emitted an error, false if + /// we didn't emit an error or we created a deferred error. + /// + /// Example usage: + /// + /// if (SemaDiagnosticBuilder(...) << foo << bar) + /// return ExprError(); + /// + /// But see CUDADiagIfDeviceCode() and CUDADiagIfHostCode() -- you probably + /// want to use these instead of creating a SemaDiagnosticBuilder yourself. + operator bool() const { return isImmediate(); } + + template + friend const SemaDiagnosticBuilder & + operator<<(const SemaDiagnosticBuilder &Diag, const T &Value) { + if (Diag.ImmediateDiag) + *Diag.ImmediateDiag << Value; + else if (Diag.PartialDiagId) + Diag.getDeviceDeferredDiags()[Diag.Fn][*Diag.PartialDiagId].second + << Value; + return Diag; + } + + // It is necessary to limit this to rvalue reference to avoid calling this + // function with a bitfield lvalue argument since non-const reference to + // bitfield is not allowed. + template ::value>> + const SemaDiagnosticBuilder &operator<<(T &&V) const { + if (ImmediateDiag) + *ImmediateDiag << std::move(V); + else if (PartialDiagId) + getDeviceDeferredDiags()[Fn][*PartialDiagId].second << std::move(V); + return *this; + } + + friend const SemaDiagnosticBuilder & + operator<<(const SemaDiagnosticBuilder &Diag, const PartialDiagnostic &PD); + + void AddFixItHint(const FixItHint &Hint) const; + + friend ExprResult ExprError(const SemaDiagnosticBuilder &) { + return ExprError(); + } + friend StmtResult StmtError(const SemaDiagnosticBuilder &) { + return StmtError(); + } + operator ExprResult() const { return ExprError(); } + operator StmtResult() const { return StmtError(); } + operator TypeResult() const { return TypeError(); } + operator DeclResult() const { return DeclResult(true); } + operator MemInitResult() const { return MemInitResult(true); } + + using DeferredDiagnosticsType = + llvm::DenseMap, + std::vector>; + + private: + Sema &S; + SourceLocation Loc; + unsigned DiagID; + const FunctionDecl *Fn; + bool ShowCallStack; + + // Invariant: At most one of these Optionals has a value. + // FIXME: Switch these to a Variant once that exists. + std::optional ImmediateDiag; + std::optional PartialDiagId; + + DeferredDiagnosticsType &getDeviceDeferredDiags() const; + }; + + /// Emit a diagnostic. + SemaDiagnosticBuilder Diag(SourceLocation Loc, unsigned DiagID, + bool DeferHint = false); + + /// Emit a partial diagnostic. + SemaDiagnosticBuilder Diag(SourceLocation Loc, const PartialDiagnostic &PD, + bool DeferHint = false); +}; + +} // namespace clang + +#endif diff --git a/clang/include/clang/Sema/SemaOpenACC.h b/clang/include/clang/Sema/SemaOpenACC.h index 7f50d7889ad7..ad4cff04ec9c 100644 --- a/clang/include/clang/Sema/SemaOpenACC.h +++ b/clang/include/clang/Sema/SemaOpenACC.h @@ -18,24 +18,14 @@ #include "clang/Basic/OpenACCKinds.h" #include "clang/Basic/SourceLocation.h" #include "clang/Sema/Ownership.h" +#include "clang/Sema/SemaBase.h" namespace clang { -class ASTContext; -class DiagnosticEngine; -class LangOptions; -class Sema; - -class SemaOpenACC { +class SemaOpenACC : public SemaBase { public: SemaOpenACC(Sema &S); - ASTContext &getASTContext() const; - DiagnosticsEngine &getDiagnostics() const; - const LangOptions &getLangOpts() const; - - Sema &SemaRef; - /// Called after parsing an OpenACC Clause so that it can be checked. bool ActOnClause(OpenACCClauseKind ClauseKind, SourceLocation StartLoc); diff --git a/clang/lib/Sema/CMakeLists.txt b/clang/lib/Sema/CMakeLists.txt index e8bff07ced0c..ab3b813a9ccd 100644 --- a/clang/lib/Sema/CMakeLists.txt +++ b/clang/lib/Sema/CMakeLists.txt @@ -29,6 +29,7 @@ add_clang_library(clangSema SemaAttr.cpp SemaAPINotes.cpp SemaAvailability.cpp + SemaBase.cpp SemaCXXScopeSpec.cpp SemaCast.cpp SemaChecking.cpp diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index b7e4fc0ac9b5..6b8e88e88500 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -190,14 +190,15 @@ const uint64_t Sema::MaximumAlignment; Sema::Sema(Preprocessor &pp, ASTContext &ctxt, ASTConsumer &consumer, TranslationUnitKind TUKind, CodeCompleteConsumer *CodeCompleter) - : CollectStats(false), TUKind(TUKind), CurFPFeatures(pp.getLangOpts()), - LangOpts(pp.getLangOpts()), PP(pp), Context(ctxt), Consumer(consumer), - Diags(PP.getDiagnostics()), SourceMgr(PP.getSourceManager()), - APINotes(SourceMgr, LangOpts), AnalysisWarnings(*this), - ThreadSafetyDeclCache(nullptr), LateTemplateParser(nullptr), - LateTemplateParserCleanup(nullptr), OpaqueParser(nullptr), - CurContext(nullptr), ExternalSource(nullptr), CurScope(nullptr), - Ident_super(nullptr), OpenACCPtr(std::make_unique(*this)), + : SemaBase(*this), CollectStats(false), TUKind(TUKind), + CurFPFeatures(pp.getLangOpts()), LangOpts(pp.getLangOpts()), PP(pp), + Context(ctxt), Consumer(consumer), Diags(PP.getDiagnostics()), + SourceMgr(PP.getSourceManager()), APINotes(SourceMgr, LangOpts), + AnalysisWarnings(*this), ThreadSafetyDeclCache(nullptr), + LateTemplateParser(nullptr), LateTemplateParserCleanup(nullptr), + OpaqueParser(nullptr), CurContext(nullptr), ExternalSource(nullptr), + CurScope(nullptr), Ident_super(nullptr), + OpenACCPtr(std::make_unique(*this)), MSPointerToMemberRepresentationMethod( LangOpts.getMSPointerToMemberRepresentationMethod()), MSStructPragmaOn(false), VtorDispStack(LangOpts.getVtorDispMode()), @@ -1612,11 +1613,6 @@ void Sema::EmitCurrentDiagnostic(unsigned DiagID) { PrintContextStack(); } -Sema::SemaDiagnosticBuilder -Sema::Diag(SourceLocation Loc, const PartialDiagnostic &PD, bool DeferHint) { - return Diag(Loc, PD.getDiagID(), DeferHint) << PD; -} - bool Sema::hasUncompilableErrorOccurred() const { if (getDiagnostics().hasUncompilableErrorOccurred()) return true; @@ -1911,29 +1907,6 @@ Sema::targetDiag(SourceLocation Loc, unsigned DiagID, const FunctionDecl *FD) { FD, *this); } -Sema::SemaDiagnosticBuilder Sema::Diag(SourceLocation Loc, unsigned DiagID, - bool DeferHint) { - bool IsError = Diags.getDiagnosticIDs()->isDefaultMappingAsError(DiagID); - bool ShouldDefer = getLangOpts().CUDA && LangOpts.GPUDeferDiag && - DiagnosticIDs::isDeferrable(DiagID) && - (DeferHint || DeferDiags || !IsError); - auto SetIsLastErrorImmediate = [&](bool Flag) { - if (IsError) - IsLastErrorImmediate = Flag; - }; - if (!ShouldDefer) { - SetIsLastErrorImmediate(true); - return SemaDiagnosticBuilder(SemaDiagnosticBuilder::K_Immediate, Loc, - DiagID, getCurFunctionDecl(), *this); - } - - SemaDiagnosticBuilder DB = getLangOpts().CUDAIsDevice - ? CUDADiagIfDeviceCode(Loc, DiagID) - : CUDADiagIfHostCode(Loc, DiagID); - SetIsLastErrorImmediate(DB.isImmediate()); - return DB; -} - void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { if (isUnevaluatedContext() || Ty.isNull()) return; diff --git a/clang/lib/Sema/SemaBase.cpp b/clang/lib/Sema/SemaBase.cpp new file mode 100644 index 000000000000..95c0cfbe283b --- /dev/null +++ b/clang/lib/Sema/SemaBase.cpp @@ -0,0 +1,85 @@ +#include "clang/Sema/SemaBase.h" +#include "clang/Sema/Sema.h" + +namespace clang { + +SemaBase::SemaBase(Sema &S) : SemaRef(S) {} + +ASTContext &SemaBase::getASTContext() const { return SemaRef.Context; } +DiagnosticsEngine &SemaBase::getDiagnostics() const { return SemaRef.Diags; } +const LangOptions &SemaBase::getLangOpts() const { return SemaRef.LangOpts; } + +SemaBase::ImmediateDiagBuilder::~ImmediateDiagBuilder() { + // If we aren't active, there is nothing to do. + if (!isActive()) + return; + + // Otherwise, we need to emit the diagnostic. First clear the diagnostic + // builder itself so it won't emit the diagnostic in its own destructor. + // + // This seems wasteful, in that as written the DiagnosticBuilder dtor will + // do its own needless checks to see if the diagnostic needs to be + // emitted. However, because we take care to ensure that the builder + // objects never escape, a sufficiently smart compiler will be able to + // eliminate that code. + Clear(); + + // Dispatch to Sema to emit the diagnostic. + SemaRef.EmitCurrentDiagnostic(DiagID); +} + +const SemaBase::SemaDiagnosticBuilder & +operator<<(const SemaBase::SemaDiagnosticBuilder &Diag, + const PartialDiagnostic &PD) { + if (Diag.ImmediateDiag) + PD.Emit(*Diag.ImmediateDiag); + else if (Diag.PartialDiagId) + Diag.S.DeviceDeferredDiags[Diag.Fn][*Diag.PartialDiagId].second = PD; + return Diag; +} + +void SemaBase::SemaDiagnosticBuilder::AddFixItHint( + const FixItHint &Hint) const { + if (ImmediateDiag) + ImmediateDiag->AddFixItHint(Hint); + else if (PartialDiagId) + S.DeviceDeferredDiags[Fn][*PartialDiagId].second.AddFixItHint(Hint); +} + +llvm::DenseMap, + std::vector> & +SemaBase::SemaDiagnosticBuilder::getDeviceDeferredDiags() const { + return S.DeviceDeferredDiags; +} + +Sema::SemaDiagnosticBuilder SemaBase::Diag(SourceLocation Loc, unsigned DiagID, + bool DeferHint) { + bool IsError = + getDiagnostics().getDiagnosticIDs()->isDefaultMappingAsError(DiagID); + bool ShouldDefer = getLangOpts().CUDA && getLangOpts().GPUDeferDiag && + DiagnosticIDs::isDeferrable(DiagID) && + (DeferHint || SemaRef.DeferDiags || !IsError); + auto SetIsLastErrorImmediate = [&](bool Flag) { + if (IsError) + SemaRef.IsLastErrorImmediate = Flag; + }; + if (!ShouldDefer) { + SetIsLastErrorImmediate(true); + return SemaDiagnosticBuilder(SemaDiagnosticBuilder::K_Immediate, Loc, + DiagID, SemaRef.getCurFunctionDecl(), SemaRef); + } + + SemaDiagnosticBuilder DB = getLangOpts().CUDAIsDevice + ? SemaRef.CUDADiagIfDeviceCode(Loc, DiagID) + : SemaRef.CUDADiagIfHostCode(Loc, DiagID); + SetIsLastErrorImmediate(DB.isImmediate()); + return DB; +} + +Sema::SemaDiagnosticBuilder SemaBase::Diag(SourceLocation Loc, + const PartialDiagnostic &PD, + bool DeferHint) { + return Diag(Loc, PD.getDiagID(), DeferHint) << PD; +} + +} // namespace clang diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index 86ffa5ad74c1..f66cc1a69ce4 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -11,8 +11,8 @@ /// //===----------------------------------------------------------------------===// -#include "clang/AST/StmtOpenACC.h" #include "clang/Sema/SemaOpenACC.h" +#include "clang/AST/StmtOpenACC.h" #include "clang/Basic/DiagnosticSema.h" #include "clang/Sema/Sema.h" @@ -31,19 +31,14 @@ bool diagnoseConstructAppertainment(SemaOpenACC &S, OpenACCDirectiveKind K, case OpenACCDirectiveKind::Serial: case OpenACCDirectiveKind::Kernels: if (!IsStmt) - return S.SemaRef.Diag(StartLoc, diag::err_acc_construct_appertainment) - << K; + return S.Diag(StartLoc, diag::err_acc_construct_appertainment) << K; break; } return false; } } // namespace -SemaOpenACC::SemaOpenACC(Sema &S) : SemaRef(S) {} - -ASTContext &SemaOpenACC::getASTContext() const { return SemaRef.Context; } -DiagnosticsEngine &SemaOpenACC::getDiagnostics() const { return SemaRef.Diags; } -const LangOptions &SemaOpenACC::getLangOpts() const { return SemaRef.LangOpts; } +SemaOpenACC::SemaOpenACC(Sema &S) : SemaBase(S) {} bool SemaOpenACC::ActOnClause(OpenACCClauseKind ClauseKind, SourceLocation StartLoc) { @@ -53,8 +48,7 @@ bool SemaOpenACC::ActOnClause(OpenACCClauseKind ClauseKind, // whatever it can do. This function will eventually need to start returning // some sort of Clause AST type, but for now just return true/false based on // success. - return SemaRef.Diag(StartLoc, diag::warn_acc_clause_unimplemented) - << ClauseKind; + return Diag(StartLoc, diag::warn_acc_clause_unimplemented) << ClauseKind; } void SemaOpenACC::ActOnConstruct(OpenACCDirectiveKind K, SourceLocation StartLoc) { @@ -72,7 +66,7 @@ void SemaOpenACC::ActOnConstruct(OpenACCDirectiveKind K, // here as these constructs do not take any arguments. break; default: - SemaRef.Diag(StartLoc, diag::warn_acc_construct_unimplemented) << K; + Diag(StartLoc, diag::warn_acc_construct_unimplemented) << K; break; } } -- GitLab From 0e8b61f8e0bd37e99f3de06e4e8885844f904eba Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Sat, 6 Apr 2024 12:22:24 +0100 Subject: [PATCH 066/695] llvm-objdump/ELF: fix crash when reading dyn str table (#87519) When reading the dynamic string table, llvm-objdump used to crash if the ELF was malformed, due to an erroneous consumption of error status. Instead, propogate the error status to the caller, fixing the crash, and printing a warning. --- .../llvm-objdump/ELF/dynamic-malformed.test | 28 +++++++++++++++++-- llvm/tools/llvm-objdump/ELFDump.cpp | 11 ++++---- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test b/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test index b10e4f5e44f1..b1e3ca17b504 100644 --- a/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test +++ b/llvm/test/tools/llvm-objdump/ELF/dynamic-malformed.test @@ -12,7 +12,6 @@ FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC - Machine: EM_X86_64 Sections: - Name: .dynamic Type: SHT_DYNAMIC @@ -29,10 +28,35 @@ FileHeader: Class: ELFCLASS64 Data: ELFDATA2LSB Type: ET_EXEC - Machine: EM_X86_64 Sections: - Name: .dynamic Type: SHT_DYNAMIC Entries: - Tag: DT_SONAME Value: 1 + +# RUN: yaml2obj %s --docnum=3 -o %t.invalidaddr +# RUN: llvm-objdump -p %t.invalidaddr 2>&1 | \ +# RUN: FileCheck %s -DFILE=%t.invalidaddr --implicit-check-not=warning: --check-prefix=ADDR + +# ADDR: Dynamic Section: +# ADDR-NEXT: warning: '[[FILE]]': virtual address is not in any segment: 0x474 +# ADDR-NEXT: NEEDED 0xffffffffbe5a0b5f +# ADDR-NEXT: STRTAB 0x0000000000000474 + +--- +!ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_DYN +Sections: + - Name: .dynamic + Type: SHT_DYNAMIC + Entries: + - Tag: DT_NEEDED + Value: 0xFFFFFFFFBE5A0B5F + - Tag: DT_STRTAB + Value: 0x474 + - Tag: DT_NULL + Value: 0x0 diff --git a/llvm/tools/llvm-objdump/ELFDump.cpp b/llvm/tools/llvm-objdump/ELFDump.cpp index fda99bd6d33e..8c184fc1fbb6 100644 --- a/llvm/tools/llvm-objdump/ELFDump.cpp +++ b/llvm/tools/llvm-objdump/ELFDump.cpp @@ -68,7 +68,7 @@ static Expected getDynamicStrTab(const ELFFile &Elf) { if (Dyn.d_tag == ELF::DT_STRTAB) { auto MappedAddrOrError = Elf.toMappedAddr(Dyn.getPtr()); if (!MappedAddrOrError) - consumeError(MappedAddrOrError.takeError()); + return MappedAddrOrError.takeError(); return StringRef(reinterpret_cast(*MappedAddrOrError)); } } @@ -223,7 +223,6 @@ template void ELFDumper::printDynamicSection() { continue; std::string Str = Elf.getDynamicTagAsString(Dyn.d_tag); - outs() << format(TagFmt.c_str(), Str.c_str()); const char *Fmt = ELFT::Is64Bits ? "0x%016" PRIx64 "\n" : "0x%08" PRIx64 "\n"; @@ -232,14 +231,16 @@ template void ELFDumper::printDynamicSection() { Dyn.d_tag == ELF::DT_AUXILIARY || Dyn.d_tag == ELF::DT_FILTER) { Expected StrTabOrErr = getDynamicStrTab(Elf); if (StrTabOrErr) { - const char *Data = StrTabOrErr.get().data(); - outs() << (Data + Dyn.d_un.d_val) << "\n"; + const char *Data = StrTabOrErr->data(); + outs() << format(TagFmt.c_str(), Str.c_str()) << Data + Dyn.getVal() + << "\n"; continue; } reportWarning(toString(StrTabOrErr.takeError()), Obj.getFileName()); consumeError(StrTabOrErr.takeError()); } - outs() << format(Fmt, (uint64_t)Dyn.d_un.d_val); + outs() << format(TagFmt.c_str(), Str.c_str()) + << format(Fmt, (uint64_t)Dyn.getVal()); } } -- GitLab From 233c030dcb18880d5f0a749573f11f96f35e76b8 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 6 Apr 2024 12:35:51 +0100 Subject: [PATCH 067/695] [LV] Add extra tests for induction cost modeling. --- .../LoopVectorize/AArch64/induction-costs.ll | 299 ++++++++++++++++++ .../LoopVectorize/X86/induction-costs.ll | 231 ++++++++++++++ 2 files changed, 530 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll create mode 100644 llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll new file mode 100644 index 000000000000..931ab4f77618 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll @@ -0,0 +1,299 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -mtriple=arm64-apple-macosx -S %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +define i32 @multi_exit_iv_uniform(i32 %a, i64 %N, ptr %dst) { +; CHECK-LABEL: define i32 @multi_exit_iv_uniform( +; CHECK-SAME: i32 [[A:%.*]], i64 [[N:%.*]], ptr [[DST:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 2147483648) +; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[UMIN]], 1 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 4 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4 +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 4, i64 [[N_MOD_VF]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP2]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[BROADCAST_SPLAT]] to <2 x i64> +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP5]], i32 0 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP5]], i32 2 +; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP8]], align 8 +; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP9]], align 8 +; CHECK-NEXT: [[TMP10]] = add <2 x i32> [[VEC_PHI]], +; CHECK-NEXT: [[TMP11]] = add <2 x i32> [[VEC_PHI1]], +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[TMP11]], [[TMP10]] +; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]]) +; CHECK-NEXT: br label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP13]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] +; CHECK: loop.header: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[C_1:%.*]] = icmp eq i64 [[IV]], [[N]] +; CHECK-NEXT: br i1 [[C_1]], label [[EXIT_1:%.*]], label [[LOOP_LATCH]] +; CHECK: loop.latch: +; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV]] +; CHECK-NEXT: [[CONV7:%.*]] = zext i32 [[A]] to i64 +; CHECK-NEXT: store i64 [[CONV7]], ptr [[ARRAYIDX_I]], align 8 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], -1 +; CHECK-NEXT: [[C_2:%.*]] = icmp eq i64 [[IV]], 2147483648 +; CHECK-NEXT: br i1 [[C_2]], label [[EXIT_2:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: exit.1: +; CHECK-NEXT: ret i32 10 +; CHECK: exit.2: +; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_2_NEXT]], [[LOOP_LATCH]] ] +; CHECK-NEXT: ret i32 [[IV_2_NEXT_LCSSA]] +; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] + %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop.latch ] + %c.1 = icmp eq i64 %iv, %N + br i1 %c.1, label %exit.1, label %loop.latch + +loop.latch: + %arrayidx.i = getelementptr i64, ptr %dst, i64 %iv + %conv7 = zext i32 %a to i64 + store i64 %conv7, ptr %arrayidx.i, align 8 + %iv.next = add i64 %iv, 1 + %iv.2.next = add i32 %iv.2, -1 + %c.2 = icmp eq i64 %iv, 2147483648 + br i1 %c.2, label %exit.2, label %loop.header + +exit.1: + ret i32 10 + +exit.2: + ret i32 %iv.2.next +} + +define i64 @pointer_induction_only(ptr %start, ptr %end) { +; CHECK-LABEL: define i64 @pointer_induction_only( +; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64 +; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]] +; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 +; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] +; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 +; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <2 x i64> [ , [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 8 +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]] +; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 2 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 1 +; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x i32>, ptr [[TMP7]], align 1 +; CHECK-NEXT: [[TMP8:%.*]] = zext <2 x i32> [[WIDE_LOAD]] to <2 x i64> +; CHECK-NEXT: [[TMP9]] = zext <2 x i32> [[WIDE_LOAD4]] to <2 x i64> +; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[VECTOR_RECUR]], <2 x i64> [[TMP8]], <2 x i32> +; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <2 x i64> [[TMP8]], <2 x i64> [[TMP9]], <2 x i32> +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1 +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0 +; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[RECUR_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[IV]], align 1 +; CHECK-NEXT: [[RECUR_NEXT]] = zext i32 [[L]] to i64 +; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds i8, ptr [[IV]], i64 4 +; CHECK-NEXT: [[C:%.*]] = icmp eq ptr [[IV]], [[END]] +; CHECK-NEXT: br i1 [[C]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: [[RECUR_LCSSA:%.*]] = phi i64 [ [[SCALAR_RECUR]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: ret i64 [[RECUR_LCSSA]] +; +entry: + br label %loop + +loop: + %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] + %recur = phi i64 [ 0, %entry ], [ %recur.next, %loop ] + %l = load i32, ptr %iv, align 1 + %recur.next = zext i32 %l to i64 + %iv.next = getelementptr inbounds i8, ptr %iv, i64 4 + %c = icmp eq ptr %iv, %end + br i1 %c, label %exit, label %loop + +exit: + ret i64 %recur +} + + +define i64 @int_and_pointer_iv(ptr %start, i32 %N) { +; CHECK-LABEL: define i64 @int_and_pointer_iv( +; CHECK-SAME: ptr [[START:%.*]], i32 [[N:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 4000 +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[TMP5:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 16 +; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP0]] +; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 4 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 +; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i32> [[WIDE_LOAD]] to <4 x i64> +; CHECK-NEXT: [[TMP5]] = zext <4 x i32> [[WIDE_LOAD3]] to <4 x i64> +; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP4]], <4 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> [[TMP5]], <4 x i32> +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 +; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP5]], i32 3 +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP5]], i32 2 +; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[RECUR_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4 +; CHECK-NEXT: [[RECUR_NEXT]] = zext i32 [[L]] to i64 +; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4 +; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[IV_NEXT]], 1000 +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: [[RECUR_LCSSA:%.*]] = phi i64 [ [[SCALAR_RECUR]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ] +; CHECK-NEXT: ret i64 [[RECUR_LCSSA]] +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ] + %recur = phi i64 [ 0, %entry ], [ %recur.next, %loop ] + %l = load i32, ptr %ptr.iv, align 4 + %recur.next = zext i32 %l to i64 + %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 + %iv.next = add i32 %iv, 1 + %tobool.not = icmp eq i32 %iv.next, 1000 + br i1 %tobool.not, label %exit, label %loop + +exit: + ret i64 %recur +} + +define void @wide_truncated_iv(ptr %dst) { +; CHECK-LABEL: define void @wide_truncated_iv( +; CHECK-SAME: ptr [[DST:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i8> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i8> [[VEC_IND]], +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 8 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[TMP2]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP2]], i32 8 +; CHECK-NEXT: store <8 x i8> [[VEC_IND]], ptr [[TMP4]], align 1 +; CHECK-NEXT: store <8 x i8> [[STEP_ADD]], ptr [[TMP5]], align 1 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i8> [[STEP_ADD]], +; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 192 +; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 192, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i8 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; CHECK-NEXT: store i8 [[TRUNC_IV]], ptr [[GEP]], align 1 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[IV]], 200 +; CHECK-NEXT: br i1 [[C]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %trunc.iv = trunc i64 %iv to i8 + %gep = getelementptr i8, ptr %dst, i64 %iv + store i8 %trunc.iv, ptr %gep, align 1 + %iv.next = add i64 %iv, 1 + %c = icmp eq i64 %iv, 200 + br i1 %c, label %exit, label %loop + +exit: + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} +; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} +; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} +; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} +; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]} +;. diff --git a/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll new file mode 100644 index 000000000000..8ce87d0ef171 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/X86/induction-costs.ll @@ -0,0 +1,231 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -mtriple=x86_64-apple-macosx -S %s | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + +define i32 @iv_used_widened_and_truncated(ptr %dst, i64 %N) #0 { +; CHECK-LABEL: define i32 @iv_used_widened_and_truncated( +; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 32 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND4:%.*]] = phi <8 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT9:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i64> [[VEC_IND]], +; CHECK-NEXT: [[STEP_ADD1:%.*]] = add <8 x i64> [[STEP_ADD]], +; CHECK-NEXT: [[STEP_ADD2:%.*]] = add <8 x i64> [[STEP_ADD1]], +; CHECK-NEXT: [[STEP_ADD5:%.*]] = add <8 x i32> [[VEC_IND4]], +; CHECK-NEXT: [[STEP_ADD6:%.*]] = add <8 x i32> [[STEP_ADD5]], +; CHECK-NEXT: [[STEP_ADD7:%.*]] = add <8 x i32> [[STEP_ADD6]], +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr { i32, [8 x i32] }, ptr [[DST]], <8 x i64> [[VEC_IND]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr { i32, [8 x i32] }, ptr [[DST]], <8 x i64> [[STEP_ADD]] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr { i32, [8 x i32] }, ptr [[DST]], <8 x i64> [[STEP_ADD1]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr { i32, [8 x i32] }, ptr [[DST]], <8 x i64> [[STEP_ADD2]] +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VEC_IND4]], <8 x ptr> [[TMP1]], i32 8, <8 x i1> ) +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[STEP_ADD5]], <8 x ptr> [[TMP2]], i32 8, <8 x i1> ) +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[STEP_ADD6]], <8 x ptr> [[TMP3]], i32 8, <8 x i1> ) +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[STEP_ADD7]], <8 x ptr> [[TMP4]], i32 8, <8 x i1> ) +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[STEP_ADD2]], +; CHECK-NEXT: [[VEC_IND_NEXT9]] = add <8 x i32> [[STEP_ADD7]], +; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr { i32, [8 x i32] }, ptr [[DST]], i64 [[IV]] +; CHECK-NEXT: [[T:%.*]] = trunc i64 [[IV]] to i32 +; CHECK-NEXT: store i32 [[T]], ptr [[GEP]], align 8 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[IV]], [[N]] +; CHECK-NEXT: br i1 [[C]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret i32 0 +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr { i32, [ 8 x i32 ]}, ptr %dst, i64 %iv + %t = trunc i64 %iv to i32 + store i32 %t, ptr %gep, align 8 + %iv.next = add i64 %iv, 1 + %c = icmp eq i64 %iv, %N + br i1 %c, label %exit, label %loop + +exit: + ret i32 0 +} + +define void @multiple_truncated_ivs_with_wide_uses(i1 %c, ptr %A, ptr %B) { +; CHECK-LABEL: define void @multiple_truncated_ivs_with_wide_uses( +; CHECK-SAME: i1 [[C:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; CHECK: vector.memcheck: +; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A]], i64 130 +; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[B]], i64 260 +; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[A]], [[SCEVGEP1]] +; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[B]], [[SCEVGEP]] +; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND3:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT6:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i16> [[VEC_IND]], +; CHECK-NEXT: [[STEP_ADD4:%.*]] = add <4 x i32> [[VEC_IND3]], +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[C]], <4 x i16> [[VEC_IND]], <4 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = select i1 [[C]], <4 x i16> [[STEP_ADD]], <4 x i16> +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i16, ptr [[A]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i16, ptr [[A]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i16, ptr [[TMP4]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i16, ptr [[TMP4]], i32 4 +; CHECK-NEXT: store <4 x i16> [[TMP2]], ptr [[TMP6]], align 2, !alias.scope [[META4:![0-9]+]], !noalias [[META7:![0-9]+]] +; CHECK-NEXT: store <4 x i16> [[TMP3]], ptr [[TMP7]], align 2, !alias.scope [[META4]], !noalias [[META7]] +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[B]], i64 [[TMP0]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[B]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP8]], i32 0 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP8]], i32 4 +; CHECK-NEXT: store <4 x i32> [[VEC_IND3]], ptr [[TMP10]], align 4, !alias.scope [[META7]] +; CHECK-NEXT: store <4 x i32> [[STEP_ADD4]], ptr [[TMP11]], align 4, !alias.scope [[META7]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], +; CHECK-NEXT: [[VEC_IND_NEXT6]] = add <4 x i32> [[STEP_ADD4]], +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 +; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 64, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[IV_16:%.*]] = trunc i64 [[IV]] to i16 +; CHECK-NEXT: [[IV_32:%.*]] = trunc i64 [[IV]] to i32 +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i16 [[IV_16]], i16 10 +; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i16, ptr [[A]], i64 [[IV]] +; CHECK-NEXT: store i16 [[SEL]], ptr [[GEP_A]], align 2 +; CHECK-NEXT: [[GEP_B:%.*]] = getelementptr i32, ptr [[B]], i64 [[IV]] +; CHECK-NEXT: store i32 [[IV_32]], ptr [[GEP_B]], align 4 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 64 +; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.16 = trunc i64 %iv to i16 + %iv.32 = trunc i64 %iv to i32 + %sel = select i1 %c, i16 %iv.16, i16 10 + %gep.A = getelementptr i16, ptr %A, i64 %iv + store i16 %sel, ptr %gep.A + %gep.B = getelementptr i32, ptr %B, i64 %iv + store i32 %iv.32, ptr %gep.B + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, 64 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +define void @truncated_ivs_with_wide_and_scalar_uses(i1 %c, ptr %dst) { +; CHECK-LABEL: define void @truncated_ivs_with_wide_and_scalar_uses( +; CHECK-SAME: i1 [[C:%.*]], ptr [[DST:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i16> [[VEC_IND]], +; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[INDEX]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP0]], 8 +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr [[DST]], i32 [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i16, ptr [[DST]], i32 [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[C]], <8 x i16> [[VEC_IND]], <8 x i16> +; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C]], <8 x i16> [[STEP_ADD]], <8 x i16> +; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i16, ptr [[TMP3]], i32 0 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[TMP3]], i32 8 +; CHECK-NEXT: store <8 x i16> [[TMP5]], ptr [[TMP7]], align 2 +; CHECK-NEXT: store <8 x i16> [[TMP6]], ptr [[TMP8]], align 2 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i16> [[STEP_ADD]], +; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 64 +; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 64, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[IV_16:%.*]] = trunc i64 [[IV]] to i16 +; CHECK-NEXT: [[IV_32:%.*]] = trunc i64 [[IV]] to i32 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr [[DST]], i32 [[IV_32]] +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i16 [[IV_16]], i16 10 +; CHECK-NEXT: store i16 [[SEL]], ptr [[GEP]], align 2 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 64 +; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP12:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.16 = trunc i64 %iv to i16 + %iv.32 = trunc i64 %iv to i32 + %gep = getelementptr i16, ptr %dst, i32 %iv.32 + %sel = select i1 %c, i16 %iv.16, i16 10 + store i16 %sel, ptr %gep + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, 64 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +attributes #0 = { "min-legal-vector-width"="0" "target-cpu"="skylake-avx512" } +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; CHECK: [[META4]] = !{[[META5:![0-9]+]]} +; CHECK: [[META5]] = distinct !{[[META5]], [[META6:![0-9]+]]} +; CHECK: [[META6]] = distinct !{[[META6]], !"LVerDomain"} +; CHECK: [[META7]] = !{[[META8:![0-9]+]]} +; CHECK: [[META8]] = distinct !{[[META8]], [[META6]]} +; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} +; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]} +; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]} +; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META2]], [[META1]]} +;. -- GitLab From 4761e74a276ee1f38596f4849daa9d633929f2ae Mon Sep 17 00:00:00 2001 From: yronglin Date: Sat, 6 Apr 2024 20:33:41 +0800 Subject: [PATCH 068/695] [libc++] Implement LWG3430 disallow implicit conversion of the source arguments to `std::filesystem::path` when constructing `std::basic_*fstream` (#85079) Implement [LWG3430](https://wg21.link/LWG3430). --------- Signed-off-by: yronglin --- libcxx/docs/ReleaseNotes/19.rst | 5 +++ libcxx/docs/Status/Cxx23Issues.csv | 2 +- libcxx/include/fstream | 23 +++++++----- .../fstreams/fstream.cons/path.pass.cpp | 37 ++++++++++++++++++- .../fstreams/ifstream.cons/path.pass.cpp | 35 +++++++++++++++++- .../fstreams/ofstream.cons/path.pass.cpp | 34 ++++++++++++++++- libcxx/test/support/test_macros.h | 4 ++ 7 files changed, 125 insertions(+), 15 deletions(-) diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index abf1570737df..2746d1937164 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -92,6 +92,11 @@ Deprecations and Removals libatomic is not available. If you are one such user, please reach out to the libc++ developers so we can collaborate on a path for supporting atomics properly on freestanding platforms. +- LWG3430 disallow implicit conversion of the source arguments to ``std::filesystem::path`` when + constructing ``std::basic_*fstream``. This effectively removes the possibility to directly construct + a ``std::basic_*fstream`` from a ``std::basic_string_view``, a input-iterator or a C-string, instead + you can construct a temporary ``std::basic_string``. This change has been applied to C++17 and later. + Upcoming Deprecations and Removals ---------------------------------- diff --git a/libcxx/docs/Status/Cxx23Issues.csv b/libcxx/docs/Status/Cxx23Issues.csv index 02297715cc2e..a212d56685c0 100644 --- a/libcxx/docs/Status/Cxx23Issues.csv +++ b/libcxx/docs/Status/Cxx23Issues.csv @@ -64,7 +64,7 @@ `2818 `__,"``::std::`` everywhere rule needs tweaking","June 2021","|Nothing To Do|","" `2997 `__,"LWG 491 and the specification of ``{forward_,}list::unique``","June 2021","","" `3410 `__,"``lexicographical_compare_three_way`` is overspecified","June 2021","|Complete|","17.0","|spaceship|" -`3430 `__,"``std::fstream`` & co. should be constructible from string_view","June 2021","","" +`3430 `__,"``std::fstream`` & co. should be constructible from string_view","June 2021","|Complete|","19.0","" `3462 `__,"§[formatter.requirements]: Formatter requirements forbid use of ``fc.arg()``","June 2021","|Nothing To Do|","","|format|" `3481 `__,"``viewable_range`` mishandles lvalue move-only views","June 2021","Superseded by `P2415R2 `__","","|ranges|" `3506 `__,"Missing allocator-extended constructors for ``priority_queue``","June 2021","|Complete|","14.0" diff --git a/libcxx/include/fstream b/libcxx/include/fstream index 7a084d114b18..7128f72e1611 100644 --- a/libcxx/include/fstream +++ b/libcxx/include/fstream @@ -78,8 +78,8 @@ public: basic_ifstream(); explicit basic_ifstream(const char* s, ios_base::openmode mode = ios_base::in); explicit basic_ifstream(const string& s, ios_base::openmode mode = ios_base::in); - explicit basic_ifstream(const filesystem::path& p, - ios_base::openmode mode = ios_base::in); // C++17 + template + explicit basic_ifstream(const T& s, ios_base::openmode mode = ios_base::in); // Since C++17 basic_ifstream(basic_ifstream&& rhs); basic_ifstream& operator=(basic_ifstream&& rhs); @@ -117,8 +117,8 @@ public: basic_ofstream(); explicit basic_ofstream(const char* s, ios_base::openmode mode = ios_base::out); explicit basic_ofstream(const string& s, ios_base::openmode mode = ios_base::out); - explicit basic_ofstream(const filesystem::path& p, - ios_base::openmode mode = ios_base::out); // C++17 + template + explicit basic_ofstream(const T& s, ios_base::openmode mode = ios_base::out); // Since C++17 basic_ofstream(basic_ofstream&& rhs); basic_ofstream& operator=(basic_ofstream&& rhs); @@ -158,8 +158,8 @@ public: basic_fstream(); explicit basic_fstream(const char* s, ios_base::openmode mode = ios_base::in|ios_base::out); explicit basic_fstream(const string& s, ios_base::openmode mode = ios_base::in|ios_base::out); - explicit basic_fstream(const filesystem::path& p, - ios_base::openmode mode = ios_base::in|ios_base::out); C++17 + template + explicit basic_fstream(const T& s, ios_base::openmode mode = ios_base::in | ios_base::out); // Since C++17 basic_fstream(basic_fstream&& rhs); basic_fstream& operator=(basic_fstream&& rhs); @@ -192,6 +192,8 @@ typedef basic_fstream wfstream; #include <__config> #include <__fwd/fstream.h> #include <__locale> +#include <__type_traits/enable_if.h> +#include <__type_traits/is_same.h> #include <__utility/move.h> #include <__utility/swap.h> #include <__utility/unreachable.h> @@ -1101,8 +1103,9 @@ public: # endif _LIBCPP_HIDE_FROM_ABI explicit basic_ifstream(const string& __s, ios_base::openmode __mode = ios_base::in); # if _LIBCPP_STD_VER >= 17 + template >> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY _LIBCPP_HIDE_FROM_ABI explicit basic_ifstream( - const filesystem::path& __p, ios_base::openmode __mode = ios_base::in) + const _Tp& __p, ios_base::openmode __mode = ios_base::in) : basic_ifstream(__p.c_str(), __mode) {} # endif // _LIBCPP_STD_VER >= 17 _LIBCPP_HIDE_FROM_ABI basic_ifstream(basic_ifstream&& __rhs); @@ -1255,8 +1258,9 @@ public: _LIBCPP_HIDE_FROM_ABI explicit basic_ofstream(const string& __s, ios_base::openmode __mode = ios_base::out); # if _LIBCPP_STD_VER >= 17 + template >> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY _LIBCPP_HIDE_FROM_ABI explicit basic_ofstream( - const filesystem::path& __p, ios_base::openmode __mode = ios_base::out) + const _Tp& __p, ios_base::openmode __mode = ios_base::out) : basic_ofstream(__p.c_str(), __mode) {} # endif // _LIBCPP_STD_VER >= 17 @@ -1414,8 +1418,9 @@ public: ios_base::openmode __mode = ios_base::in | ios_base::out); # if _LIBCPP_STD_VER >= 17 + template >> _LIBCPP_AVAILABILITY_FILESYSTEM_LIBRARY _LIBCPP_HIDE_FROM_ABI explicit basic_fstream( - const filesystem::path& __p, ios_base::openmode __mode = ios_base::in | ios_base::out) + const _Tp& __p, ios_base::openmode __mode = ios_base::in | ios_base::out) : basic_fstream(__p.c_str(), __mode) {} # endif // _LIBCPP_STD_VER >= 17 diff --git a/libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/path.pass.cpp b/libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/path.pass.cpp index bc75d04740da..5edf22eaacf3 100644 --- a/libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/path.pass.cpp +++ b/libcxx/test/std/input.output/file.streams/fstreams/fstream.cons/path.pass.cpp @@ -15,17 +15,50 @@ // plate > // class basic_fstream -// explicit basic_fstream(const filesystem::path& s, -// ios_base::openmode mode = ios_base::in|ios_base::out); +// template +// explicit basic_fstream(const T& s, ios_base::openmode mode = ios_base::in); // Since C++17 +// Constraints: is_same_v is true #include #include #include +#include + #include "test_macros.h" +#include "test_iterators.h" #include "platform_support.h" namespace fs = std::filesystem; +template +constexpr bool test_non_convert_to_path() { + // String types + static_assert(!std::is_constructible_v>); + static_assert(!std::is_constructible_v>); + + // Char* pointers + if constexpr (!std::is_same_v) + static_assert(!std::is_constructible_v); + + // Iterators + static_assert(!std::is_convertible_v>); + + return true; +} + +static_assert(test_non_convert_to_path()); + +#if !defined(TEST_HAS_NO_WIDE_CHARACTERS) && !defined(TEST_HAS_OPEN_WITH_WCHAR) +static_assert(test_non_convert_to_path()); +#endif // !TEST_HAS_NO_WIDE_CHARACTERS && !TEST_HAS_OPEN_WITH_WCHAR + +#ifndef TEST_HAS_NO_CHAR8_T +static_assert(test_non_convert_to_path()); +#endif // TEST_HAS_NO_CHAR8_T + +static_assert(test_non_convert_to_path()); +static_assert(test_non_convert_to_path()); + int main(int, char**) { fs::path p = get_temp_file_name(); { diff --git a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/path.pass.cpp b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/path.pass.cpp index cfbb8419fe1c..2f27fd8e6e93 100644 --- a/libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/path.pass.cpp +++ b/libcxx/test/std/input.output/file.streams/fstreams/ifstream.cons/path.pass.cpp @@ -17,8 +17,9 @@ // template > // class basic_ifstream -// explicit basic_ifstream(const filesystem::path& s, -// ios_base::openmode mode = ios_base::in); +// template +// explicit basic_ifstream(const T& s, ios_base::openmode mode = ios_base::in); // Since C++17 +// Constraints: is_same_v is true #include #include @@ -26,9 +27,39 @@ #include #include "test_macros.h" +#include "test_iterators.h" namespace fs = std::filesystem; +template +constexpr bool test_non_convert_to_path() { + // String types + static_assert(!std::is_constructible_v>); + static_assert(!std::is_constructible_v>); + + // Char* pointers + if constexpr (!std::is_same_v) + static_assert(!std::is_constructible_v); + + // Iterators + static_assert(!std::is_convertible_v>); + + return true; +} + +static_assert(test_non_convert_to_path()); + +#if !defined(TEST_HAS_NO_WIDE_CHARACTERS) && !defined(TEST_HAS_OPEN_WITH_WCHAR) +static_assert(test_non_convert_to_path()); +#endif // !TEST_HAS_NO_WIDE_CHARACTERS && !TEST_HAS_OPEN_WITH_WCHAR + +#ifndef TEST_HAS_NO_CHAR8_T +static_assert(test_non_convert_to_path()); +#endif // TEST_HAS_NO_CHAR8_T + +static_assert(test_non_convert_to_path()); +static_assert(test_non_convert_to_path()); + int main(int, char**) { { fs::path p; diff --git a/libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/path.pass.cpp b/libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/path.pass.cpp index 316ed776a48b..e55adfd83fc3 100644 --- a/libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/path.pass.cpp +++ b/libcxx/test/std/input.output/file.streams/fstreams/ofstream.cons/path.pass.cpp @@ -15,7 +15,9 @@ // plate > // class basic_ofstream -// explicit basic_ofstream(const filesystem::path& s, ios_base::openmode mode = ios_base::out); +// template +// explicit basic_ifstream(const T& s, ios_base::openmode mode = ios_base::in); // Since C++17 +// Constraints: is_same_v is true #include #include @@ -24,9 +26,39 @@ #include "platform_support.h" #include "test_macros.h" +#include "test_iterators.h" namespace fs = std::filesystem; +template +constexpr bool test_non_convert_to_path() { + // String types + static_assert(!std::is_constructible_v>); + static_assert(!std::is_constructible_v>); + + // Char* pointers + if constexpr (!std::is_same_v) + static_assert(!std::is_constructible_v); + + // Iterators + static_assert(!std::is_convertible_v>); + + return true; +} + +static_assert(test_non_convert_to_path()); + +#if !defined(TEST_HAS_NO_WIDE_CHARACTERS) && !defined(TEST_HAS_OPEN_WITH_WCHAR) +static_assert(test_non_convert_to_path()); +#endif // !TEST_HAS_NO_WIDE_CHARACTERS && !TEST_HAS_OPEN_WITH_WCHAR + +#ifndef TEST_HAS_NO_CHAR8_T +static_assert(test_non_convert_to_path()); +#endif // TEST_HAS_NO_CHAR8_T + +static_assert(test_non_convert_to_path()); +static_assert(test_non_convert_to_path()); + int main(int, char**) { fs::path p = get_temp_file_name(); { diff --git a/libcxx/test/support/test_macros.h b/libcxx/test/support/test_macros.h index 24f69c758f36..7b2dcbb52d0c 100644 --- a/libcxx/test/support/test_macros.h +++ b/libcxx/test/support/test_macros.h @@ -385,6 +385,10 @@ inline Tp const& DoNotOptimize(Tp const& value) { # define TEST_HAS_NO_UNICODE #endif +#if defined(_LIBCPP_HAS_OPEN_WITH_WCHAR) +# define TEST_HAS_OPEN_WITH_WCHAR +#endif + #if defined(_LIBCPP_HAS_NO_INT128) || defined(_MSVC_STL_VERSION) # define TEST_HAS_NO_INT128 #endif -- GitLab From fa8a7266724f26d27820f8876b504d7a4f166948 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 6 Apr 2024 14:46:09 +0100 Subject: [PATCH 069/695] [LV] Make global_alias.ll test independent of O1 pipeline. Update global_alias.ll with the IR after the O1 pipeline. Depending on the O1 makes the tests more fragile and also makes it more difficult to reason about the behavior of the tests, as it doesn't show the IR before LoopVectorize. --- .../Transforms/LoopVectorize/global_alias.ll | 1068 ++++++----------- 1 file changed, 346 insertions(+), 722 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/global_alias.ll b/llvm/test/Transforms/LoopVectorize/global_alias.ll index 01affc1a689f..336e462a4cf6 100644 --- a/llvm/test/Transforms/LoopVectorize/global_alias.ll +++ b/llvm/test/Transforms/LoopVectorize/global_alias.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -passes='default,loop-vectorize,dce,instcombine' -force-vector-interleave=1 -force-vector-width=4 -S | FileCheck %s +; RUN: opt -passes='loop-vectorize,dce,instcombine' -force-vector-interleave=1 -force-vector-width=4 -S %s | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" @@ -28,39 +28,23 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 define i32 @noAlias01(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %arrayidx1 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %4 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %i.05 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %arrayidx1 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %i.05 store i32 %add, ptr %arrayidx1, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx2, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx2, align 4 + ret i32 %1 } ; /// Different objects, positive induction with widening slide @@ -76,40 +60,24 @@ for.end: ; preds = %for.cond define i32 @noAlias02(i32 %a) { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 90 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %add = add nsw i32 %1, 10 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %add - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add1 = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %4 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %add = add nuw nsw i32 %i.05, 10 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %add + %0 = load i32, ptr %arrayidx, align 4 + %add1 = add nsw i32 %0, %a + %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %i.05 store i32 %add1, ptr %arrayidx2, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx3, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 90 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx3, align 4 + ret i32 %1 } ; /// Different objects, positive induction with shortening slide @@ -125,40 +93,24 @@ for.end: ; preds = %for.cond define i32 @noAlias03(i32 %a) { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %add1 = add nsw i32 %4, 10 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %i.05 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %add1 = add nuw nsw i32 %i.05, 10 %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %add1 store i32 %add, ptr %arrayidx2, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx3, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx3, align 4 + ret i32 %1 } ; /// Pointer access, positive stride, run-time check added @@ -177,42 +129,26 @@ for.end: ; preds = %for.cond define i32 @noAlias04(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load ptr, ptr @PB, align 4 - %2 = load i32, ptr %i, align 4 - %add.ptr = getelementptr inbounds i32, ptr %1, i32 %2 - %3 = load i32, ptr %add.ptr, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %3, %4 - %5 = load ptr, ptr @PA, align 4 - %6 = load i32, ptr %i, align 4 - %add.ptr1 = getelementptr inbounds i32, ptr %5, i32 %6 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = load ptr, ptr @PB, align 4 + %add.ptr = getelementptr inbounds i32, ptr %0, i32 %i.05 + %1 = load i32, ptr %add.ptr, align 4 + %add = add nsw i32 %1, %a + %2 = load ptr, ptr @PA, align 4 + %add.ptr1 = getelementptr inbounds i32, ptr %2, i32 %i.05 store i32 %add, ptr %add.ptr1, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load ptr, ptr @PA, align 4 - %9 = load i32, ptr %a.addr, align 4 - %add.ptr2 = getelementptr inbounds i32, ptr %8, i32 %9 - %10 = load i32, ptr %add.ptr2, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %3 = load ptr, ptr @PA, align 4 + %add.ptr2 = getelementptr inbounds i32, ptr %3, i32 %a + %4 = load i32, ptr %add.ptr2, align 4 + ret i32 %4 } ; /// Different objects, positive induction, multi-array @@ -228,47 +164,23 @@ for.end: ; preds = %for.cond define i32 @noAlias05(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - %N = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 10, ptr %N, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %2 = load i32, ptr %N, align 4 - %arrayidx = getelementptr inbounds [100 x [100 x i32]], ptr getelementptr inbounds (%struct.anon.0, ptr @Bar, i32 0, i32 2), i32 0, i32 %2 - %arrayidx1 = getelementptr inbounds [100 x i32], ptr %arrayidx, i32 0, i32 %1 - %3 = load i32, ptr %arrayidx1, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %3, %4 - %5 = load i32, ptr %i, align 4 - %6 = load i32, ptr %N, align 4 - %arrayidx2 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %6 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr %arrayidx2, i32 0, i32 %5 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.07 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx1 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 2, i32 10, i32 %i.07 + %0 = load i32, ptr %arrayidx1, align 4 + %add = add nsw i32 %0, %a + %arrayidx3 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %i.07 store i32 %add, ptr %arrayidx3, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load i32, ptr %a.addr, align 4 - %9 = load i32, ptr %N, align 4 - %arrayidx4 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %9 - %arrayidx5 = getelementptr inbounds [100 x i32], ptr %arrayidx4, i32 0, i32 %8 - %10 = load i32, ptr %arrayidx5, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.07, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx5 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %a + %1 = load i32, ptr %arrayidx5, align 4 + ret i32 %1 } ; /// Same objects, positive induction, multi-array, different sub-elements @@ -284,48 +196,23 @@ for.end: ; preds = %for.cond define i32 @noAlias06(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - %N = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 10, ptr %N, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %2 = load i32, ptr %N, align 4 - %add = add nsw i32 %2, 1 - %arrayidx = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %add - %arrayidx1 = getelementptr inbounds [100 x i32], ptr %arrayidx, i32 0, i32 %1 - %3 = load i32, ptr %arrayidx1, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add2 = add nsw i32 %3, %4 - %5 = load i32, ptr %i, align 4 - %6 = load i32, ptr %N, align 4 - %arrayidx3 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %6 - %arrayidx4 = getelementptr inbounds [100 x i32], ptr %arrayidx3, i32 0, i32 %5 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.07 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx1 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 11, i32 %i.07 + %0 = load i32, ptr %arrayidx1, align 4 + %add2 = add nsw i32 %0, %a + %arrayidx4 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %i.07 store i32 %add2, ptr %arrayidx4, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load i32, ptr %a.addr, align 4 - %9 = load i32, ptr %N, align 4 - %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %9 - %arrayidx6 = getelementptr inbounds [100 x i32], ptr %arrayidx5, i32 0, i32 %8 - %10 = load i32, ptr %arrayidx6, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.07, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx6 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %a + %1 = load i32, ptr %arrayidx6, align 4 + ret i32 %1 } ; /// Different objects, negative induction, constant distance @@ -340,43 +227,24 @@ for.end: ; preds = %for.cond ; CHECK: ret define i32 @noAlias07(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 1 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %sub2 = sub nsw i32 100, %4 - %sub3 = sub nsw i32 %sub2, 1 - %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub3 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 99, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub1 store i32 %add, ptr %arrayidx4, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx5, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx5, align 4 + ret i32 %1 } ; /// Different objects, negative induction, shortening slide @@ -392,43 +260,25 @@ for.end: ; preds = %for.cond define i32 @noAlias08(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 90 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 10 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %sub2 = sub nsw i32 100, %4 - %sub3 = sub nsw i32 %sub2, 1 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 90, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %sub3 = sub nuw nsw i32 99, %i.05 %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub3 store i32 %add, ptr %arrayidx4, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx5, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 90 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx5, align 4 + ret i32 %1 } ; /// Different objects, negative induction, widening slide @@ -444,43 +294,25 @@ for.end: ; preds = %for.cond define i32 @noAlias09(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 1 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %sub2 = sub nsw i32 100, %4 - %sub3 = sub nsw i32 %sub2, 10 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 99, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %sub3 = sub nsw i32 90, %i.05 %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub3 store i32 %add, ptr %arrayidx4, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx5, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx5, align 4 + ret i32 %1 } ; /// Pointer access, negative stride, run-time check added @@ -499,48 +331,31 @@ for.end: ; preds = %for.cond define i32 @noAlias10(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load ptr, ptr @PB, align 4 - %add.ptr = getelementptr inbounds i32, ptr %1, i32 100 - %2 = load i32, ptr %i, align 4 - %idx.neg = sub i32 0, %2 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = load ptr, ptr @PB, align 4 + %add.ptr = getelementptr inbounds i8, ptr %0, i32 400 + %idx.neg = sub nsw i32 0, %i.05 %add.ptr1 = getelementptr inbounds i32, ptr %add.ptr, i32 %idx.neg - %add.ptr2 = getelementptr inbounds i32, ptr %add.ptr1, i32 -1 - %3 = load i32, ptr %add.ptr2, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %3, %4 - %5 = load ptr, ptr @PA, align 4 - %add.ptr3 = getelementptr inbounds i32, ptr %5, i32 100 - %6 = load i32, ptr %i, align 4 - %idx.neg4 = sub i32 0, %6 - %add.ptr5 = getelementptr inbounds i32, ptr %add.ptr3, i32 %idx.neg4 - %add.ptr6 = getelementptr inbounds i32, ptr %add.ptr5, i32 -1 + %add.ptr2 = getelementptr inbounds i8, ptr %add.ptr1, i32 -4 + %1 = load i32, ptr %add.ptr2, align 4 + %add = add nsw i32 %1, %a + %2 = load ptr, ptr @PA, align 4 + %add.ptr3 = getelementptr inbounds i8, ptr %2, i32 400 + %add.ptr5 = getelementptr inbounds i32, ptr %add.ptr3, i32 %idx.neg + %add.ptr6 = getelementptr inbounds i8, ptr %add.ptr5, i32 -4 store i32 %add, ptr %add.ptr6, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load ptr, ptr @PA, align 4 - %9 = load i32, ptr %a.addr, align 4 - %add.ptr7 = getelementptr inbounds i32, ptr %8, i32 %9 - %10 = load i32, ptr %add.ptr7, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %3 = load ptr, ptr @PA, align 4 + %add.ptr7 = getelementptr inbounds i32, ptr %3, i32 %a + %4 = load i32, ptr %add.ptr7, align 4 + ret i32 %4 } ; /// Different objects, negative induction, multi-array @@ -556,51 +371,24 @@ for.end: ; preds = %for.cond define i32 @noAlias11(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - %N = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 10, ptr %N, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 1 - %2 = load i32, ptr %N, align 4 - %arrayidx = getelementptr inbounds [100 x [100 x i32]], ptr getelementptr inbounds (%struct.anon.0, ptr @Bar, i32 0, i32 2), i32 0, i32 %2 - %arrayidx2 = getelementptr inbounds [100 x i32], ptr %arrayidx, i32 0, i32 %sub1 - %3 = load i32, ptr %arrayidx2, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %3, %4 - %5 = load i32, ptr %i, align 4 - %sub3 = sub nsw i32 100, %5 - %sub4 = sub nsw i32 %sub3, 1 - %6 = load i32, ptr %N, align 4 - %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %6 - %arrayidx6 = getelementptr inbounds [100 x i32], ptr %arrayidx5, i32 0, i32 %sub4 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.07 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 99, %i.07 + %arrayidx2 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 2, i32 10, i32 %sub1 + %0 = load i32, ptr %arrayidx2, align 4 + %add = add nsw i32 %0, %a + %arrayidx6 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %sub1 store i32 %add, ptr %arrayidx6, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load i32, ptr %a.addr, align 4 - %9 = load i32, ptr %N, align 4 - %arrayidx7 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %9 - %arrayidx8 = getelementptr inbounds [100 x i32], ptr %arrayidx7, i32 0, i32 %8 - %10 = load i32, ptr %arrayidx8, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.07, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx8 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %a + %1 = load i32, ptr %arrayidx8, align 4 + ret i32 %1 } ; /// Same objects, negative induction, multi-array, different sub-elements @@ -616,52 +404,24 @@ for.end: ; preds = %for.cond define i32 @noAlias12(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - %N = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 10, ptr %N, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 1 - %2 = load i32, ptr %N, align 4 - %add = add nsw i32 %2, 1 - %arrayidx = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %add - %arrayidx2 = getelementptr inbounds [100 x i32], ptr %arrayidx, i32 0, i32 %sub1 - %3 = load i32, ptr %arrayidx2, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add3 = add nsw i32 %3, %4 - %5 = load i32, ptr %i, align 4 - %sub4 = sub nsw i32 100, %5 - %sub5 = sub nsw i32 %sub4, 1 - %6 = load i32, ptr %N, align 4 - %arrayidx6 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %6 - %arrayidx7 = getelementptr inbounds [100 x i32], ptr %arrayidx6, i32 0, i32 %sub5 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.07 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 99, %i.07 + %arrayidx2 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 11, i32 %sub1 + %0 = load i32, ptr %arrayidx2, align 4 + %add3 = add nsw i32 %0, %a + %arrayidx7 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %sub1 store i32 %add3, ptr %arrayidx7, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load i32, ptr %a.addr, align 4 - %9 = load i32, ptr %N, align 4 - %arrayidx8 = getelementptr inbounds [100 x [100 x i32]], ptr @Bar, i32 0, i32 %9 - %arrayidx9 = getelementptr inbounds [100 x i32], ptr %arrayidx8, i32 0, i32 %8 - %10 = load i32, ptr %arrayidx9, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.07, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx9 = getelementptr inbounds %struct.anon.0, ptr @Bar, i32 0, i32 0, i32 10, i32 %a + %1 = load i32, ptr %arrayidx9, align 4 + ret i32 %1 } ; /// Same objects, positive induction, constant distance, just enough for vector size @@ -677,40 +437,24 @@ for.end: ; preds = %for.cond define i32 @noAlias13(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %add = add nsw i32 %1, 4 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %add = add nuw nsw i32 %i.05, 4 %arrayidx = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %add - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add1 = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %4 + %0 = load i32, ptr %arrayidx, align 4 + %add1 = add nsw i32 %0, %a + %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %i.05 store i32 %add1, ptr %arrayidx2, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx3, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx3, align 4 + ret i32 %1 } ; /// Same objects, negative induction, constant distance, just enough for vector size @@ -726,43 +470,25 @@ for.end: ; preds = %for.cond define i32 @noAlias14(i32 %a) #0 { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 5 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nsw i32 95, %i.05 %arrayidx = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %sub2 = sub nsw i32 100, %4 - %sub3 = sub nsw i32 %sub2, 1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %sub3 = sub nuw nsw i32 99, %i.05 %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub3 store i32 %add, ptr %arrayidx4, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx5, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx5 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx5, align 4 + ret i32 %1 } @@ -782,41 +508,24 @@ for.end: ; preds = %for.cond define i32 @mayAlias01(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 1 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %4 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 99, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %i.05 store i32 %add, ptr %arrayidx2, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx3, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx3, align 4 + ret i32 %1 } ; /// Different objects, swapped induction, alias at the beginning @@ -832,41 +541,24 @@ for.end: ; preds = %for.cond define i32 @mayAlias02(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %4 - %sub1 = sub nsw i32 %sub, 1 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %i.05 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %sub1 = sub nuw nsw i32 99, %i.05 %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %sub1 store i32 %add, ptr %arrayidx2, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx3, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx3, align 4 + ret i32 %1 } ; /// Pointer access, run-time check added @@ -882,48 +574,31 @@ for.end: ; preds = %for.cond define i32 @mayAlias03(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load ptr, ptr @PB, align 4 - %add.ptr = getelementptr inbounds i32, ptr %1, i32 100 - %2 = load i32, ptr %i, align 4 - %idx.neg = sub i32 0, %2 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %0 = load ptr, ptr @PB, align 4 + %add.ptr = getelementptr inbounds i8, ptr %0, i32 400 + %idx.neg = sub nsw i32 0, %i.05 %add.ptr1 = getelementptr inbounds i32, ptr %add.ptr, i32 %idx.neg - %add.ptr2 = getelementptr inbounds i32, ptr %add.ptr1, i32 -1 - %3 = load i32, ptr %add.ptr2, align 4 - %4 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %3, %4 - %5 = load ptr, ptr @PA, align 4 - %6 = load i32, ptr %i, align 4 - %add.ptr3 = getelementptr inbounds i32, ptr %5, i32 %6 + %add.ptr2 = getelementptr inbounds i8, ptr %add.ptr1, i32 -4 + %1 = load i32, ptr %add.ptr2, align 4 + %add = add nsw i32 %1, %a + %2 = load ptr, ptr @PA, align 4 + %add.ptr3 = getelementptr inbounds i32, ptr %2, i32 %i.05 store i32 %add, ptr %add.ptr3, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %7 = load i32, ptr %i, align 4 - %inc = add nsw i32 %7, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %8 = load ptr, ptr @PA, align 4 - %9 = load i32, ptr %a.addr, align 4 - %add.ptr4 = getelementptr inbounds i32, ptr %8, i32 %9 - %10 = load i32, ptr %add.ptr4, align 4 - ret i32 %10 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %3 = load ptr, ptr @PA, align 4 + %add.ptr4 = getelementptr inbounds i32, ptr %3, i32 %a + %4 = load i32, ptr %add.ptr4, align 4 + ret i32 %4 } - ;; === Finally, the tests that should only vectorize with care (or if we ignore undefined behaviour at all) === @@ -939,42 +614,25 @@ for.end: ; preds = %for.cond define i32 @mustAlias01(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 1 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %add2 = add nsw i32 %4, 10 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nuw nsw i32 99, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %add2 = add nuw nsw i32 %i.05, 10 %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %add2 store i32 %add, ptr %arrayidx3, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx4, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx4, align 4 + ret i32 %1 } ; int mustAlias02 (int a) { @@ -989,41 +647,24 @@ for.end: ; preds = %for.cond define i32 @mustAlias02(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 10 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %4 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nsw i32 90, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %arrayidx2 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %i.05 store i32 %add, ptr %arrayidx2, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx3, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx3, align 4 + ret i32 %1 } ; int mustAlias03 (int a) { @@ -1038,40 +679,23 @@ for.end: ; preds = %for.cond define i32 @mustAlias03(i32 %a) nounwind { entry: - %a.addr = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 %a, ptr %a.addr, align 4 - store i32 0, ptr %i, align 4 - br label %for.cond - -for.cond: ; preds = %for.inc, %entry - %0 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %0, 100 - br i1 %cmp, label %for.body, label %for.end - -for.body: ; preds = %for.cond - %1 = load i32, ptr %i, align 4 - %sub = sub nsw i32 100, %1 - %sub1 = sub nsw i32 %sub, 10 - %arrayidx = getelementptr inbounds [100 x i32], ptr getelementptr inbounds (%struct.anon, ptr @Foo, i32 0, i32 2), i32 0, i32 %sub1 - %2 = load i32, ptr %arrayidx, align 4 - %3 = load i32, ptr %a.addr, align 4 - %add = add nsw i32 %2, %3 - %4 = load i32, ptr %i, align 4 - %add2 = add nsw i32 %4, 10 + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.05 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %sub1 = sub nsw i32 90, %i.05 + %arrayidx = getelementptr inbounds %struct.anon, ptr @Foo, i32 0, i32 2, i32 %sub1 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %a + %add2 = add nuw nsw i32 %i.05, 10 %arrayidx3 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %add2 store i32 %add, ptr %arrayidx3, align 4 - br label %for.inc - -for.inc: ; preds = %for.body - %5 = load i32, ptr %i, align 4 - %inc = add nsw i32 %5, 1 - store i32 %inc, ptr %i, align 4 - br label %for.cond - -for.end: ; preds = %for.cond - %6 = load i32, ptr %a.addr, align 4 - %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %6 - %7 = load i32, ptr %arrayidx4, align 4 - ret i32 %7 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, 100 + br i1 %exitcond.not, label %for.end, label %for.body + +for.end: ; preds = %for.body + %arrayidx4 = getelementptr inbounds [100 x i32], ptr @Foo, i32 0, i32 %a + %1 = load i32, ptr %arrayidx4, align 4 + ret i32 %1 } -- GitLab From 1803d675004bb512051d2df7e1ae3ea95692fc67 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 6 Apr 2024 14:56:18 +0100 Subject: [PATCH 070/695] [Driver] Add missing include of std::set. 4ddd4ed7fe15a added a use of std::set without including it. With some recent libc++, std::set isn't included transitively causing build failures. Add explicit include. --- clang/lib/Driver/ToolChains/AIX.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index 7a62b0f9aec4..3f10888596a2 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -17,6 +17,8 @@ #include "llvm/ProfileData/InstrProf.h" #include "llvm/Support/Path.h" +#include + using AIX = clang::driver::toolchains::AIX; using namespace clang::driver; using namespace clang::driver::tools; -- GitLab From 935e699173636921b118c3c21da6b18659c09a16 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Sat, 6 Apr 2024 17:22:07 +0200 Subject: [PATCH 071/695] [libc++] Optimize ranges::minmax (#87335) This allows Clang to vectorize the loop. ``` --------------------------------------------------------------------- Benchmark old new --------------------------------------------------------------------- BM_std_minmax/1 0.659 ns 1.41 ns BM_std_minmax/2 1.08 ns 2.16 ns BM_std_minmax/3 2.16 ns 2.96 ns BM_std_minmax/4 2.82 ns 3.81 ns BM_std_minmax/5 3.43 ns 4.69 ns BM_std_minmax/6 4.08 ns 5.63 ns BM_std_minmax/7 4.75 ns 6.51 ns BM_std_minmax/8 5.42 ns 7.41 ns BM_std_minmax/9 6.05 ns 8.34 ns BM_std_minmax/10 6.68 ns 9.29 ns BM_std_minmax/11 7.47 ns 10.6 ns BM_std_minmax/12 7.95 ns 11.4 ns BM_std_minmax/13 8.64 ns 12.4 ns BM_std_minmax/14 9.35 ns 13.4 ns BM_std_minmax/15 10.1 ns 14.4 ns BM_std_minmax/16 10.6 ns 2.25 ns BM_std_minmax/17 11.3 ns 2.82 ns BM_std_minmax/18 11.8 ns 3.71 ns BM_std_minmax/19 12.6 ns 4.52 ns BM_std_minmax/20 13.2 ns 5.47 ns BM_std_minmax/21 14.1 ns 6.67 ns BM_std_minmax/22 14.5 ns 7.78 ns BM_std_minmax/23 15.1 ns 8.67 ns BM_std_minmax/24 15.7 ns 9.68 ns BM_std_minmax/25 16.4 ns 10.7 ns BM_std_minmax/26 17.1 ns 11.7 ns BM_std_minmax/27 17.8 ns 12.8 ns BM_std_minmax/28 18.4 ns 14.1 ns BM_std_minmax/29 19.0 ns 15.0 ns BM_std_minmax/30 19.6 ns 16.0 ns BM_std_minmax/31 20.2 ns 17.0 ns BM_std_minmax/32 20.8 ns 2.46 ns BM_std_minmax/64 41.5 ns 2.97 ns BM_std_minmax/512 340 ns 6.05 ns BM_std_minmax/1024 667 ns 8.83 ns BM_std_minmax/4000 2571 ns 28.6 ns BM_std_minmax/4096 2632 ns 25.8 ns BM_std_minmax/5500 3554 ns 51.1 ns BM_std_minmax/64000 41175 ns 480 ns BM_std_minmax/65536 42039 ns 490 ns BM_std_minmax/70000 44931 ns 528 ns BM_std_minmax/1 0.708 ns 1.20 ns BM_std_minmax/2 1.18 ns 1.78 ns BM_std_minmax/3 1.98 ns 2.42 ns BM_std_minmax/4 2.47 ns 3.05 ns BM_std_minmax/5 3.09 ns 3.72 ns BM_std_minmax/6 3.49 ns 4.37 ns BM_std_minmax/7 4.24 ns 5.03 ns BM_std_minmax/8 4.65 ns 2.12 ns BM_std_minmax/9 5.34 ns 2.51 ns BM_std_minmax/10 5.82 ns 3.18 ns BM_std_minmax/11 6.36 ns 3.97 ns BM_std_minmax/12 6.73 ns 4.68 ns BM_std_minmax/13 7.59 ns 5.49 ns BM_std_minmax/14 7.77 ns 6.45 ns BM_std_minmax/15 8.54 ns 7.55 ns BM_std_minmax/16 8.74 ns 2.38 ns BM_std_minmax/17 9.59 ns 2.76 ns BM_std_minmax/18 9.88 ns 3.37 ns BM_std_minmax/19 10.7 ns 4.17 ns BM_std_minmax/20 10.9 ns 4.88 ns BM_std_minmax/21 12.1 ns 5.70 ns BM_std_minmax/22 12.6 ns 6.64 ns BM_std_minmax/23 13.5 ns 7.72 ns BM_std_minmax/24 13.2 ns 2.87 ns BM_std_minmax/25 14.2 ns 3.10 ns BM_std_minmax/26 14.2 ns 3.59 ns BM_std_minmax/27 15.4 ns 4.35 ns BM_std_minmax/28 15.3 ns 5.10 ns BM_std_minmax/29 16.2 ns 5.87 ns BM_std_minmax/30 16.2 ns 6.88 ns BM_std_minmax/31 17.0 ns 7.78 ns BM_std_minmax/32 17.2 ns 3.45 ns BM_std_minmax/64 34.1 ns 3.35 ns BM_std_minmax/512 279 ns 8.37 ns BM_std_minmax/1024 549 ns 14.2 ns BM_std_minmax/4000 2111 ns 50.1 ns BM_std_minmax/4096 2167 ns 47.9 ns BM_std_minmax/5500 2895 ns 69.7 ns BM_std_minmax/64000 33454 ns 953 ns BM_std_minmax/65536 34474 ns 970 ns BM_std_minmax/70000 36691 ns 1037 ns BM_std_minmax/1 0.664 ns 1.17 ns BM_std_minmax/2 1.11 ns 1.69 ns BM_std_minmax/3 2.36 ns 2.29 ns BM_std_minmax/4 2.53 ns 2.91 ns BM_std_minmax/5 3.23 ns 3.56 ns BM_std_minmax/6 3.56 ns 4.23 ns BM_std_minmax/7 4.28 ns 4.91 ns BM_std_minmax/8 4.60 ns 5.60 ns BM_std_minmax/9 5.38 ns 6.31 ns BM_std_minmax/10 5.69 ns 7.03 ns BM_std_minmax/11 6.41 ns 7.70 ns BM_std_minmax/12 6.73 ns 8.39 ns BM_std_minmax/13 7.38 ns 9.07 ns BM_std_minmax/14 7.74 ns 9.79 ns BM_std_minmax/15 8.53 ns 10.5 ns BM_std_minmax/16 8.79 ns 11.2 ns BM_std_minmax/17 9.63 ns 12.0 ns BM_std_minmax/18 9.84 ns 12.7 ns BM_std_minmax/19 10.6 ns 13.5 ns BM_std_minmax/20 11.0 ns 14.3 ns BM_std_minmax/21 11.7 ns 15.0 ns BM_std_minmax/22 12.0 ns 15.7 ns BM_std_minmax/23 13.1 ns 16.5 ns BM_std_minmax/24 13.0 ns 17.3 ns BM_std_minmax/25 13.7 ns 17.9 ns BM_std_minmax/26 14.0 ns 18.6 ns BM_std_minmax/27 14.8 ns 19.4 ns BM_std_minmax/28 15.1 ns 20.3 ns BM_std_minmax/29 15.8 ns 20.9 ns BM_std_minmax/30 16.1 ns 21.7 ns BM_std_minmax/31 16.9 ns 22.5 ns BM_std_minmax/32 17.2 ns 3.40 ns BM_std_minmax/64 33.9 ns 4.04 ns BM_std_minmax/512 275 ns 14.6 ns BM_std_minmax/1024 541 ns 27.5 ns BM_std_minmax/4000 2093 ns 96.3 ns BM_std_minmax/4096 2146 ns 98.3 ns BM_std_minmax/5500 2866 ns 157 ns BM_std_minmax/64000 33619 ns 1954 ns BM_std_minmax/65536 34252 ns 2009 ns BM_std_minmax/70000 36618 ns 2125 ns BM_std_minmax/1 0.709 ns 1.19 ns BM_std_minmax/2 1.01 ns 1.65 ns BM_std_minmax/3 2.14 ns 2.21 ns BM_std_minmax/4 2.45 ns 2.83 ns BM_std_minmax/5 3.09 ns 3.47 ns BM_std_minmax/6 3.44 ns 4.11 ns BM_std_minmax/7 4.16 ns 4.79 ns BM_std_minmax/8 4.54 ns 5.47 ns BM_std_minmax/9 5.37 ns 6.20 ns BM_std_minmax/10 5.71 ns 6.93 ns BM_std_minmax/11 6.00 ns 7.60 ns BM_std_minmax/12 6.43 ns 8.27 ns BM_std_minmax/13 7.01 ns 8.94 ns BM_std_minmax/14 7.45 ns 9.65 ns BM_std_minmax/15 8.16 ns 10.4 ns BM_std_minmax/16 8.46 ns 5.22 ns BM_std_minmax/17 9.16 ns 5.22 ns BM_std_minmax/18 9.53 ns 5.52 ns BM_std_minmax/19 10.2 ns 6.02 ns BM_std_minmax/20 10.5 ns 6.89 ns BM_std_minmax/21 11.3 ns 7.83 ns BM_std_minmax/22 11.6 ns 8.59 ns BM_std_minmax/23 12.3 ns 9.91 ns BM_std_minmax/24 12.6 ns 10.1 ns BM_std_minmax/25 13.2 ns 12.0 ns BM_std_minmax/26 13.6 ns 13.5 ns BM_std_minmax/27 14.2 ns 14.8 ns BM_std_minmax/28 14.7 ns 15.9 ns BM_std_minmax/29 15.3 ns 16.6 ns BM_std_minmax/30 15.8 ns 17.3 ns BM_std_minmax/31 16.3 ns 18.2 ns BM_std_minmax/32 16.7 ns 7.18 ns BM_std_minmax/64 33.1 ns 11.5 ns BM_std_minmax/512 268 ns 71.0 ns BM_std_minmax/1024 532 ns 138 ns BM_std_minmax/4000 2056 ns 533 ns BM_std_minmax/4096 2112 ns 539 ns BM_std_minmax/5500 2823 ns 749 ns BM_std_minmax/64000 32956 ns 8590 ns BM_std_minmax/65536 33795 ns 8791 ns BM_std_minmax/70000 36084 ns 9442 ns BM_std_minmax/1 0.714 ns 1.41 ns BM_std_minmax/2 0.955 ns 1.96 ns BM_std_minmax/3 1.90 ns 2.63 ns BM_std_minmax/4 2.40 ns 3.34 ns BM_std_minmax/5 2.87 ns 4.10 ns BM_std_minmax/6 3.47 ns 4.88 ns BM_std_minmax/7 4.04 ns 5.66 ns BM_std_minmax/8 4.65 ns 6.45 ns BM_std_minmax/9 5.18 ns 7.24 ns BM_std_minmax/10 5.80 ns 8.05 ns BM_std_minmax/11 6.24 ns 8.86 ns BM_std_minmax/12 6.78 ns 9.70 ns BM_std_minmax/13 7.30 ns 10.6 ns BM_std_minmax/14 7.86 ns 11.4 ns BM_std_minmax/15 8.46 ns 12.3 ns BM_std_minmax/16 9.00 ns 2.12 ns BM_std_minmax/17 9.58 ns 2.83 ns BM_std_minmax/18 10.1 ns 3.37 ns BM_std_minmax/19 10.7 ns 4.11 ns BM_std_minmax/20 11.2 ns 4.85 ns BM_std_minmax/21 11.9 ns 5.69 ns BM_std_minmax/22 12.3 ns 6.77 ns BM_std_minmax/23 13.1 ns 7.56 ns BM_std_minmax/24 13.5 ns 8.40 ns BM_std_minmax/25 14.2 ns 9.30 ns BM_std_minmax/26 14.4 ns 10.1 ns BM_std_minmax/27 15.0 ns 11.1 ns BM_std_minmax/28 15.3 ns 11.9 ns BM_std_minmax/29 16.2 ns 12.9 ns BM_std_minmax/30 16.5 ns 13.9 ns BM_std_minmax/31 17.2 ns 14.8 ns BM_std_minmax/32 17.6 ns 2.36 ns BM_std_minmax/64 35.6 ns 3.21 ns BM_std_minmax/512 288 ns 6.00 ns BM_std_minmax/1024 573 ns 8.80 ns BM_std_minmax/4000 2222 ns 28.6 ns BM_std_minmax/4096 2265 ns 25.9 ns BM_std_minmax/5500 3047 ns 48.8 ns BM_std_minmax/64000 35059 ns 480 ns BM_std_minmax/65536 35941 ns 491 ns BM_std_minmax/70000 38922 ns 525 ns BM_std_minmax/1 0.711 ns 1.18 ns BM_std_minmax/2 0.957 ns 1.65 ns BM_std_minmax/3 2.13 ns 2.21 ns BM_std_minmax/4 2.14 ns 2.78 ns BM_std_minmax/5 3.06 ns 3.29 ns BM_std_minmax/6 2.89 ns 3.87 ns BM_std_minmax/7 3.80 ns 4.55 ns BM_std_minmax/8 3.68 ns 2.02 ns BM_std_minmax/9 4.53 ns 2.40 ns BM_std_minmax/10 4.60 ns 2.94 ns BM_std_minmax/11 5.67 ns 3.67 ns BM_std_minmax/12 5.39 ns 4.22 ns BM_std_minmax/13 6.58 ns 4.78 ns BM_std_minmax/14 6.33 ns 5.54 ns BM_std_minmax/15 7.34 ns 6.30 ns BM_std_minmax/16 7.17 ns 2.25 ns BM_std_minmax/17 8.19 ns 2.61 ns BM_std_minmax/18 8.02 ns 3.19 ns BM_std_minmax/19 9.03 ns 3.72 ns BM_std_minmax/20 8.89 ns 4.36 ns BM_std_minmax/21 9.77 ns 5.10 ns BM_std_minmax/22 9.70 ns 5.55 ns BM_std_minmax/23 10.8 ns 6.29 ns BM_std_minmax/24 10.6 ns 2.41 ns BM_std_minmax/25 11.6 ns 2.75 ns BM_std_minmax/26 11.4 ns 3.26 ns BM_std_minmax/27 12.4 ns 3.86 ns BM_std_minmax/28 12.3 ns 4.45 ns BM_std_minmax/29 13.2 ns 5.07 ns BM_std_minmax/30 13.1 ns 5.77 ns BM_std_minmax/31 13.9 ns 6.65 ns BM_std_minmax/32 13.9 ns 2.72 ns BM_std_minmax/64 27.8 ns 3.25 ns BM_std_minmax/512 220 ns 8.30 ns BM_std_minmax/1024 435 ns 14.1 ns BM_std_minmax/4000 1703 ns 49.8 ns BM_std_minmax/4096 1746 ns 47.9 ns BM_std_minmax/5500 2350 ns 69.9 ns BM_std_minmax/64000 27388 ns 953 ns BM_std_minmax/65536 28040 ns 975 ns BM_std_minmax/70000 29967 ns 1040 ns BM_std_minmax/1 0.712 ns 1.18 ns BM_std_minmax/2 0.965 ns 1.65 ns BM_std_minmax/3 2.13 ns 2.14 ns BM_std_minmax/4 2.09 ns 2.64 ns BM_std_minmax/5 3.02 ns 3.21 ns BM_std_minmax/6 2.94 ns 3.81 ns BM_std_minmax/7 3.91 ns 4.38 ns BM_std_minmax/8 3.75 ns 4.93 ns BM_std_minmax/9 4.71 ns 5.60 ns BM_std_minmax/10 4.59 ns 6.26 ns BM_std_minmax/11 5.57 ns 6.80 ns BM_std_minmax/12 5.43 ns 7.47 ns BM_std_minmax/13 6.45 ns 8.10 ns BM_std_minmax/14 6.32 ns 8.69 ns BM_std_minmax/15 7.29 ns 9.37 ns BM_std_minmax/16 7.12 ns 9.99 ns BM_std_minmax/17 8.24 ns 10.6 ns BM_std_minmax/18 8.00 ns 11.2 ns BM_std_minmax/19 8.94 ns 12.0 ns BM_std_minmax/20 8.91 ns 12.6 ns BM_std_minmax/21 9.73 ns 17.2 ns BM_std_minmax/22 9.75 ns 13.8 ns BM_std_minmax/23 10.6 ns 14.5 ns BM_std_minmax/24 10.6 ns 15.1 ns BM_std_minmax/25 11.5 ns 15.7 ns BM_std_minmax/26 11.4 ns 16.3 ns BM_std_minmax/27 12.3 ns 17.0 ns BM_std_minmax/28 12.3 ns 17.6 ns BM_std_minmax/29 13.2 ns 18.3 ns BM_std_minmax/30 13.2 ns 19.0 ns BM_std_minmax/31 14.0 ns 19.6 ns BM_std_minmax/32 14.0 ns 3.39 ns BM_std_minmax/64 27.6 ns 4.05 ns BM_std_minmax/512 221 ns 14.2 ns BM_std_minmax/1024 439 ns 25.5 ns BM_std_minmax/4000 1720 ns 96.3 ns BM_std_minmax/4096 1762 ns 97.8 ns BM_std_minmax/5500 2364 ns 146 ns BM_std_minmax/64000 27874 ns 1905 ns BM_std_minmax/65536 28012 ns 1961 ns BM_std_minmax/70000 29899 ns 2087 ns BM_std_minmax/1 0.707 ns 1.18 ns BM_std_minmax/2 0.909 ns 1.65 ns BM_std_minmax/3 1.65 ns 2.70 ns BM_std_minmax/4 1.93 ns 2.69 ns BM_std_minmax/5 2.45 ns 3.34 ns BM_std_minmax/6 2.78 ns 3.81 ns BM_std_minmax/7 3.28 ns 4.43 ns BM_std_minmax/8 3.70 ns 4.92 ns BM_std_minmax/9 4.12 ns 5.64 ns BM_std_minmax/10 4.44 ns 6.15 ns BM_std_minmax/11 4.91 ns 6.81 ns BM_std_minmax/12 5.31 ns 7.41 ns BM_std_minmax/13 5.72 ns 7.96 ns BM_std_minmax/14 6.05 ns 8.66 ns BM_std_minmax/15 6.55 ns 9.37 ns BM_std_minmax/16 6.89 ns 7.98 ns BM_std_minmax/17 7.34 ns 8.13 ns BM_std_minmax/18 7.73 ns 8.42 ns BM_std_minmax/19 8.26 ns 8.63 ns BM_std_minmax/20 8.54 ns 8.96 ns BM_std_minmax/21 9.14 ns 9.37 ns BM_std_minmax/22 9.39 ns 9.67 ns BM_std_minmax/23 10.1 ns 10.1 ns BM_std_minmax/24 10.4 ns 10.6 ns BM_std_minmax/25 11.0 ns 11.3 ns BM_std_minmax/26 11.3 ns 12.1 ns BM_std_minmax/27 11.8 ns 14.2 ns BM_std_minmax/28 12.1 ns 15.8 ns BM_std_minmax/29 12.6 ns 17.4 ns BM_std_minmax/30 13.1 ns 18.1 ns BM_std_minmax/31 13.4 ns 18.8 ns BM_std_minmax/32 13.8 ns 10.4 ns BM_std_minmax/64 27.3 ns 15.5 ns BM_std_minmax/512 222 ns 80.6 ns BM_std_minmax/1024 443 ns 156 ns BM_std_minmax/4000 1731 ns 591 ns BM_std_minmax/4096 1752 ns 609 ns BM_std_minmax/5500 2340 ns 819 ns BM_std_minmax/64000 27166 ns 9652 ns BM_std_minmax/65536 27869 ns 9876 ns BM_std_minmax/70000 29920 ns 10680 ns ``` --- libcxx/benchmarks/CMakeLists.txt | 1 + libcxx/benchmarks/algorithms/minmax.bench.cpp | 68 +++++++++++++++++++ libcxx/docs/ReleaseNotes/19.rst | 2 + libcxx/include/__algorithm/comp.h | 3 + libcxx/include/__algorithm/ranges_minmax.h | 17 ++++- libcxx/include/__functional/operations.h | 6 ++ .../include/__functional/ranges_operations.h | 3 + libcxx/include/__type_traits/desugars_to.h | 1 + 8 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 libcxx/benchmarks/algorithms/minmax.bench.cpp diff --git a/libcxx/benchmarks/CMakeLists.txt b/libcxx/benchmarks/CMakeLists.txt index 387e013afeb6..928238c1ac69 100644 --- a/libcxx/benchmarks/CMakeLists.txt +++ b/libcxx/benchmarks/CMakeLists.txt @@ -182,6 +182,7 @@ set(BENCHMARK_TESTS algorithms/make_heap.bench.cpp algorithms/make_heap_then_sort_heap.bench.cpp algorithms/min.bench.cpp + algorithms/minmax.bench.cpp algorithms/min_max_element.bench.cpp algorithms/mismatch.bench.cpp algorithms/pop_heap.bench.cpp diff --git a/libcxx/benchmarks/algorithms/minmax.bench.cpp b/libcxx/benchmarks/algorithms/minmax.bench.cpp new file mode 100644 index 000000000000..b0ff7f91c199 --- /dev/null +++ b/libcxx/benchmarks/algorithms/minmax.bench.cpp @@ -0,0 +1,68 @@ +#include +#include + +#include + +void run_sizes(auto benchmark) { + benchmark->Arg(1) + ->Arg(2) + ->Arg(3) + ->Arg(4) + ->Arg(5) + ->Arg(6) + ->Arg(7) + ->Arg(8) + ->Arg(9) + ->Arg(10) + ->Arg(11) + ->Arg(12) + ->Arg(13) + ->Arg(14) + ->Arg(15) + ->Arg(16) + ->Arg(17) + ->Arg(18) + ->Arg(19) + ->Arg(20) + ->Arg(21) + ->Arg(22) + ->Arg(23) + ->Arg(24) + ->Arg(25) + ->Arg(26) + ->Arg(27) + ->Arg(28) + ->Arg(29) + ->Arg(30) + ->Arg(31) + ->Arg(32) + ->Arg(64) + ->Arg(512) + ->Arg(1024) + ->Arg(4000) + ->Arg(4096) + ->Arg(5500) + ->Arg(64000) + ->Arg(65536) + ->Arg(70000); +} + +template +static void BM_std_minmax(benchmark::State& state) { + std::vector vec(state.range(), 3); + + for (auto _ : state) { + benchmark::DoNotOptimize(vec); + benchmark::DoNotOptimize(std::ranges::minmax(vec)); + } +} +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); +BENCHMARK(BM_std_minmax)->Apply(run_sizes); + +BENCHMARK_MAIN(); diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 2746d1937164..633fba08eec2 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -55,6 +55,8 @@ Improvements and New Features resulting in a performance increase of up to 1400x. - The ``std::mismatch`` algorithm has been optimized for integral types, which can lead up to 40x performance improvements. +- The ``std::ranges::minmax`` algorithm has been optimized for integral types, resulting in a performance increase of + up to 100x. - The ``_LIBCPP_ENABLE_CXX26_REMOVED_STRSTREAM`` macro has been added to make the declarations in ```` available. diff --git a/libcxx/include/__algorithm/comp.h b/libcxx/include/__algorithm/comp.h index a089375e3da1..a0fa88d6d2ac 100644 --- a/libcxx/include/__algorithm/comp.h +++ b/libcxx/include/__algorithm/comp.h @@ -41,6 +41,9 @@ struct __less { } }; +template +inline const bool __desugars_to_v<__less_tag, __less<>, _Tp, _Tp> = true; + _LIBCPP_END_NAMESPACE_STD #endif // _LIBCPP___ALGORITHM_COMP_H diff --git a/libcxx/include/__algorithm/ranges_minmax.h b/libcxx/include/__algorithm/ranges_minmax.h index 22a62b620c93..ca5722523336 100644 --- a/libcxx/include/__algorithm/ranges_minmax.h +++ b/libcxx/include/__algorithm/ranges_minmax.h @@ -23,7 +23,9 @@ #include <__iterator/projected.h> #include <__ranges/access.h> #include <__ranges/concepts.h> +#include <__type_traits/desugars_to.h> #include <__type_traits/is_reference.h> +#include <__type_traits/is_trivially_copyable.h> #include <__type_traits/remove_cvref.h> #include <__utility/forward.h> #include <__utility/move.h> @@ -83,7 +85,20 @@ struct __fn { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(__first != __last, "range has to contain at least one element"); - if constexpr (forward_range<_Range>) { + // This optimiation is not in minmax_element because clang doesn't see through the pointers and as a result doesn't + // vectorize the code. + if constexpr (contiguous_range<_Range> && is_integral_v<_ValueT> && + __is_cheap_to_copy<_ValueT> & __is_identity<_Proj>::value && + __desugars_to_v<__less_tag, _Comp, _ValueT, _ValueT>) { + minmax_result<_ValueT> __result = {__r[0], __r[0]}; + for (auto __e : __r) { + if (__e < __result.min) + __result.min = __e; + if (__result.max < __e) + __result.max = __e; + } + return __result; + } else if constexpr (forward_range<_Range>) { // Special-case the one element case. Avoid repeatedly initializing objects from the result of an iterator // dereference when doing so might not be idempotent. The `if constexpr` avoids the extra branch in cases where // it's not needed. diff --git a/libcxx/include/__functional/operations.h b/libcxx/include/__functional/operations.h index 9aa28e492506..240f127e5425 100644 --- a/libcxx/include/__functional/operations.h +++ b/libcxx/include/__functional/operations.h @@ -359,6 +359,9 @@ struct _LIBCPP_TEMPLATE_VIS less : __binary_function<_Tp, _Tp, bool> { }; _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(less); +template +inline const bool __desugars_to_v<__less_tag, less<_Tp>, _Tp, _Tp> = true; + #if _LIBCPP_STD_VER >= 14 template <> struct _LIBCPP_TEMPLATE_VIS less { @@ -370,6 +373,9 @@ struct _LIBCPP_TEMPLATE_VIS less { } typedef void is_transparent; }; + +template +inline const bool __desugars_to_v<__less_tag, less<>, _Tp, _Tp> = true; #endif #if _LIBCPP_STD_VER >= 14 diff --git a/libcxx/include/__functional/ranges_operations.h b/libcxx/include/__functional/ranges_operations.h index a9dffaf69625..27f06eadd0eb 100644 --- a/libcxx/include/__functional/ranges_operations.h +++ b/libcxx/include/__functional/ranges_operations.h @@ -99,6 +99,9 @@ struct greater_equal { template inline const bool __desugars_to_v<__equal_tag, ranges::equal_to, _Tp, _Up> = true; +template +inline const bool __desugars_to_v<__less_tag, ranges::less, _Tp, _Up> = true; + #endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__type_traits/desugars_to.h b/libcxx/include/__type_traits/desugars_to.h index a8f69c28dfc5..97a2ee5448f2 100644 --- a/libcxx/include/__type_traits/desugars_to.h +++ b/libcxx/include/__type_traits/desugars_to.h @@ -20,6 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD // Tags to represent the canonical operations struct __equal_tag {}; struct __plus_tag {}; +struct __less_tag {}; // This class template is used to determine whether an operation "desugars" // (or boils down) to a given canonical operation. -- GitLab From fc7087b7b7fa410e00f7abce5ea379a459af066b Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Sat, 6 Apr 2024 19:10:25 +0200 Subject: [PATCH 072/695] [libc][NFC] Rename `uint_test` into `big_int_test` for consistency (#87875) --- libc/test/src/__support/CMakeLists.txt | 4 ++-- libc/test/src/__support/{uint_test.cpp => big_int_test.cpp} | 0 .../llvm-project-overlay/libc/test/src/__support/BUILD.bazel | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) rename libc/test/src/__support/{uint_test.cpp => big_int_test.cpp} (100%) diff --git a/libc/test/src/__support/CMakeLists.txt b/libc/test/src/__support/CMakeLists.txt index 02ee91d0dc99..5d1230f5f3a7 100644 --- a/libc/test/src/__support/CMakeLists.txt +++ b/libc/test/src/__support/CMakeLists.txt @@ -101,11 +101,11 @@ endif() if(NOT LIBC_TARGET_ARCHITECTURE_IS_NVPTX) add_libc_test( - uint_test + big_int_test SUITE libc-support-tests SRCS - uint_test.cpp + big_int_test.cpp DEPENDS libc.src.__support.big_int libc.src.__support.CPP.optional diff --git a/libc/test/src/__support/uint_test.cpp b/libc/test/src/__support/big_int_test.cpp similarity index 100% rename from libc/test/src/__support/uint_test.cpp rename to libc/test/src/__support/big_int_test.cpp diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel index 0ed5951904a0..3980ef60c197 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/BUILD.bazel @@ -83,8 +83,8 @@ libc_test( ) libc_test( - name = "uint_test", - srcs = ["uint_test.cpp"], + name = "big_int_test", + srcs = ["big_int_test.cpp"], deps = [ "//libc:__support_big_int", "//libc:__support_cpp_optional", -- GitLab From b88a1dd6c75754ace4abe18c8ea16a019f7b5529 Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Sat, 6 Apr 2024 19:30:16 +0200 Subject: [PATCH 073/695] [libc] Make `BigInt` bitwise shift consistent with regular integral semantics. (#87874) This patch removes the test for cases where the shift operand is greater or equal to the bit width of the number. This is done for two reasons, first it makes `BigInt` consistent with regular integral bitwise shift semantics, and second it makes the shift operation faster. The shift operation is on the critical path for `exp` and `log` operations, see https://github.com/llvm/llvm-project/pull/86137#issuecomment-2034133868. --- libc/src/__support/FPUtil/dyadic_float.h | 6 ++++-- libc/src/__support/big_int.h | 10 ++++------ libc/test/src/__support/big_int_test.cpp | 10 +--------- 3 files changed, 9 insertions(+), 17 deletions(-) diff --git a/libc/src/__support/FPUtil/dyadic_float.h b/libc/src/__support/FPUtil/dyadic_float.h index 49fb11971104..12a69228d36c 100644 --- a/libc/src/__support/FPUtil/dyadic_float.h +++ b/libc/src/__support/FPUtil/dyadic_float.h @@ -122,7 +122,8 @@ template struct DyadicFloat { int exp_lo = exp_hi - static_cast(PRECISION) - 1; - MantissaType m_hi(mantissa >> shift); + MantissaType m_hi = + shift >= MantissaType::BITS ? MantissaType(0) : mantissa >> shift; T d_hi = FPBits::create_value( sign, exp_hi, @@ -130,7 +131,8 @@ template struct DyadicFloat { IMPLICIT_MASK) .get_val(); - MantissaType round_mask = MantissaType(1) << (shift - 1); + MantissaType round_mask = + shift > MantissaType::BITS ? 0 : MantissaType(1) << (shift - 1); MantissaType sticky_mask = round_mask - MantissaType(1); bool round_bit = !(mantissa & round_mask).is_zero(); diff --git a/libc/src/__support/big_int.h b/libc/src/__support/big_int.h index c1e55ceef211..f722a81d357d 100644 --- a/libc/src/__support/big_int.h +++ b/libc/src/__support/big_int.h @@ -249,18 +249,14 @@ LIBC_INLINE constexpr bool is_negative(cpp::array &array) { enum Direction { LEFT, RIGHT }; // A bitwise shift on an array of elements. -// TODO: Make the result UB when 'offset' is greater or equal to the number of -// bits in 'array'. This will allow for better code performance. +// 'offset' must be less than TOTAL_BITS (i.e., sizeof(word) * CHAR_BIT * N) +// otherwise the behavior is undefined. template LIBC_INLINE constexpr cpp::array shift(cpp::array array, size_t offset) { static_assert(direction == LEFT || direction == RIGHT); constexpr size_t WORD_BITS = cpp::numeric_limits::digits; constexpr size_t TOTAL_BITS = N * WORD_BITS; - if (LIBC_UNLIKELY(offset == 0)) - return array; - if (LIBC_UNLIKELY(offset >= TOTAL_BITS)) - return {}; #ifdef LIBC_TYPES_HAS_INT128 if constexpr (TOTAL_BITS == 128) { using type = cpp::conditional_t; @@ -272,6 +268,8 @@ LIBC_INLINE constexpr cpp::array shift(cpp::array array, return cpp::bit_cast>(tmp); } #endif + if (LIBC_UNLIKELY(offset == 0)) + return array; const bool is_neg = is_signed && is_negative(array); constexpr auto at = [](size_t index) -> int { // reverse iteration when direction == LEFT. diff --git a/libc/test/src/__support/big_int_test.cpp b/libc/test/src/__support/big_int_test.cpp index fadec0cc313b..1c4f0ac29171 100644 --- a/libc/test/src/__support/big_int_test.cpp +++ b/libc/test/src/__support/big_int_test.cpp @@ -192,7 +192,7 @@ TYPED_TEST(LlvmLibcUIntClassTest, Masks, Types) { TYPED_TEST(LlvmLibcUIntClassTest, CountBits, Types) { if constexpr (!T::SIGNED) { - for (size_t i = 0; i <= T::BITS; ++i) { + for (size_t i = 0; i < T::BITS; ++i) { const auto l_one = T::all_ones() << i; // 0b111...000 const auto r_one = T::all_ones() >> i; // 0b000...111 const int zeros = i; @@ -559,10 +559,6 @@ TEST(LlvmLibcUIntClassTest, ShiftLeftTests) { LL_UInt128 result5({0, 0x2468ace000000000}); EXPECT_EQ((val2 << 100), result5); - LL_UInt128 result6({0, 0}); - EXPECT_EQ((val2 << 128), result6); - EXPECT_EQ((val2 << 256), result6); - LL_UInt192 val3({1, 0, 0}); LL_UInt192 result7({0, 1, 0}); EXPECT_EQ((val3 << 64), result7); @@ -589,10 +585,6 @@ TEST(LlvmLibcUIntClassTest, ShiftRightTests) { LL_UInt128 result5({0x0000000001234567, 0}); EXPECT_EQ((val2 >> 100), result5); - LL_UInt128 result6({0, 0}); - EXPECT_EQ((val2 >> 128), result6); - EXPECT_EQ((val2 >> 256), result6); - LL_UInt128 v1({0x1111222233334444, 0xaaaabbbbccccdddd}); LL_UInt128 r1({0xaaaabbbbccccdddd, 0}); EXPECT_EQ((v1 >> 64), r1); -- GitLab From 7f9f82e3de94040ca6124a43f2d737201bd4a595 Mon Sep 17 00:00:00 2001 From: Hristo Hristov Date: Sat, 6 Apr 2024 21:52:52 +0300 Subject: [PATCH 074/695] [libc++][format] P3142R0: Printing Blank Lines with `println` (#87277) Implements https://wg21.link/P3142R0 Applied retroactively as DR, same as stdlibc++ and MS STL: https://github.com/orgs/microsoft/projects/1143?pane=issue&itemId=57457187 --- libcxx/docs/ReleaseNotes/19.rst | 1 + libcxx/docs/Status/Cxx2cPapers.csv | 2 +- libcxx/include/ostream | 4 ++ libcxx/include/print | 8 ++++ .../locale-specific_form.pass.cpp | 43 +++++++++++++++-- .../ostream.formatted.print/println.pass.cpp | 13 +++++ .../print.fun/no_file_description.pass.cpp | 17 +++++++ .../print.fun/println.blank_line.sh.cpp | 48 +++++++++++++++++++ .../print.fun/println.file.pass.cpp | 24 ++++++++++ 9 files changed, 156 insertions(+), 4 deletions(-) create mode 100644 libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 633fba08eec2..eaba5c8d0456 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -44,6 +44,7 @@ Implemented Papers - P2495R3 - Interfacing ``stringstream``\s with ``string_view`` - P2867R2 - Remove Deprecated ``strstream``\s From C++26 - P2872R3 - Remove ``wstring_convert`` From C++26 +- P3142R0 - Printing Blank Lines with ``println`` (as DR against C++23) - P2302R4 - ``std::ranges::contains`` - P1659R3 - ``std::ranges::starts_with`` and ``std::ranges::ends_with`` diff --git a/libcxx/docs/Status/Cxx2cPapers.csv b/libcxx/docs/Status/Cxx2cPapers.csv index af270150fda0..fa11da62bc08 100644 --- a/libcxx/docs/Status/Cxx2cPapers.csv +++ b/libcxx/docs/Status/Cxx2cPapers.csv @@ -51,7 +51,7 @@ "`P2869R4 `__","LWG","Remove Deprecated ``shared_ptr`` Atomic Access APIs from C++26","Tokyo March 2024","","","" "`P2872R3 `__","LWG","Remove ``wstring_convert`` From C++26","Tokyo March 2024","|Complete|","19.0","" "`P3107R5 `__","LWG","Permit an efficient implementation of ``std::print``","Tokyo March 2024","","","|format| |DR|" -"`P3142R0 `__","LWG","Printing Blank Lines with ``println``","Tokyo March 2024","","","|format|" +"`P3142R0 `__","LWG","Printing Blank Lines with ``println``","Tokyo March 2024","|Complete|","19.0","|format|" "`P2845R8 `__","LWG","Formatting of ``std::filesystem::path``","Tokyo March 2024","","","|format|" "`P0493R5 `__","LWG","Atomic minimum/maximum","Tokyo March 2024","","","" "`P2542R8 `__","LWG","``views::concat``","Tokyo March 2024","","","|ranges|" diff --git a/libcxx/include/ostream b/libcxx/include/ostream index 42819ceb252c..d4fc1c58b8a9 100644 --- a/libcxx/include/ostream +++ b/libcxx/include/ostream @@ -164,6 +164,7 @@ template void print(ostream& os, format_string fmt, Args&&... args); template // since C++23 void println(ostream& os, format_string fmt, Args&&... args); +void println(ostream& os); // since C++26 void vprint_unicode(ostream& os, string_view fmt, format_args args); // since C++23 void vprint_nonunicode(ostream& os, string_view fmt, format_args args); // since C++23 @@ -1163,6 +1164,9 @@ _LIBCPP_HIDE_FROM_ABI void println(ostream& __os, format_string<_Args...> __fmt, # endif // _LIBCPP_HAS_NO_UNICODE } +template // TODO PRINT template or availability markup fires too eagerly (http://llvm.org/PR61563). +_LIBCPP_HIDE_FROM_ABI inline void println(ostream& __os) { std::print(__os, "\n"); } + #endif // _LIBCPP_STD_VER >= 23 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/print b/libcxx/include/print index a9f10433a7dc..e0bcf214ea23 100644 --- a/libcxx/include/print +++ b/libcxx/include/print @@ -15,8 +15,10 @@ namespace std { // [print.fun], print functions template void print(format_string fmt, Args&&... args); + void println(); // Since C++26 template void print(FILE* stream, format_string fmt, Args&&... args); + void println(FILE* stream); // Since C++26 template void println(format_string fmt, Args&&... args); @@ -356,6 +358,12 @@ _LIBCPP_HIDE_FROM_ABI void println(FILE* __stream, format_string<_Args...> __fmt # endif // _LIBCPP_HAS_NO_UNICODE } +template // TODO PRINT template or availability markup fires too eagerly (http://llvm.org/PR61563). +_LIBCPP_HIDE_FROM_ABI inline void println(FILE* __stream) { std::print(__stream, "\n"); } + +template // TODO PRINT template or availability markup fires too eagerly (http://llvm.org/PR61563). +_LIBCPP_HIDE_FROM_ABI inline void println() { println(stdout); } + template _LIBCPP_HIDE_FROM_ABI void println(format_string<_Args...> __fmt, _Args&&... __args) { std::println(stdout, __fmt, std::forward<_Args>(__args)...); diff --git a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp index 6b62e2f1754d..2e19e38e2ed0 100644 --- a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp @@ -26,6 +26,7 @@ // void print(ostream& os, format_string fmt, Args&&... args); // template // void println(ostream& os, format_string fmt, Args&&... args); +// void println(ostream& os); // since C++26 // // void vprint_unicode(ostream& os, string_view fmt, format_args args); // void vprint_nonunicode(ostream& os, string_view fmt, format_args args); @@ -67,7 +68,7 @@ test(std::stringstream& stream, std::string expected, test_format_string(args)...); std::string out = stream.str(); TEST_REQUIRE(out == expected, @@ -111,6 +112,7 @@ static void test(std::string expected, std::locale loc, test_format_string { string_type do_truename() const override { return "gültig"; } string_type do_falsename() const override { return "ungültig"; } @@ -2188,12 +2190,47 @@ static void test_floating_point() { test_floating_point_default_precision(); } +static void test_println_blank_line(std::stringstream& stream) { + std::string expected{'\n'}; + stream.str(""); + + std::println(stream); + std::string out = stream.str(); + TEST_REQUIRE(out == expected, + TEST_WRITE_CONCATENATED("\nExpected output (blank line) ", expected, "\nActual output ", out, '\n')); +} + +static void test_println_blank_line(std::locale loc) { + std::stringstream stream; + stream.imbue(loc); + test_println_blank_line(stream); +} + +static void test_println_blank_line() { + std::locale::global(std::locale(LOCALE_en_US_UTF_8)); + assert(std::locale().name() == LOCALE_en_US_UTF_8); + std::stringstream stream; + test_println_blank_line(stream); + + std::locale loc = std::locale(std::locale(), new numpunct()); + std::locale::global(loc); + test_println_blank_line(std::locale(LOCALE_en_US_UTF_8)); + +#ifndef TEST_HAS_NO_UNICODE + + std::locale loc_unicode = std::locale(std::locale(), new numpunct_unicode()); + test_println_blank_line(loc_unicode); + +#endif // TEST_HAS_NO_UNICODE +} + int main(int, char**) { test_bool(); test_integer(); test_floating_point(); test_floating_point(); test_floating_point(); + test_println_blank_line(); return 0; } diff --git a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/println.pass.cpp b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/println.pass.cpp index 479a3de0a93c..19a02638a9da 100644 --- a/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/println.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/println.pass.cpp @@ -17,6 +17,7 @@ // template // void println(ostream& os, format_string fmt, Args&&... args); +// void println(ostream& os); // since C++26 // [ostream.formatted.print]/3 // If the function is vprint_unicode and os is a stream that refers to @@ -55,8 +56,20 @@ auto test_exception = [](std::string_view, std::string_view, Args // The exceptions are tested by other functions that don't use the basic-format-string as fmt argument. }; +void test_println_blank_line() { + std::string expected{'\n'}; + + std::stringstream sstr; + std::println(sstr); + + std::string out = sstr.str(); + TEST_REQUIRE(out == expected, + TEST_WRITE_CONCATENATED("\nExpected output (blank line) ", expected, "\nActual output ", out, '\n')); +}; + int main(int, char**) { print_tests(test_file, test_exception); + test_println_blank_line(); return 0; } diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp index f502616b677b..ffa48c5e745d 100644 --- a/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/print.fun/no_file_description.pass.cpp @@ -25,8 +25,10 @@ // template // void print(FILE* stream, format_string fmt, Args&&... args); +// void println(); // Since C++26 // template // void println(FILE* stream, format_string fmt, Args&&... args); +// void println(FILE* stream); // Since C++26 // void vprint_unicode(FILE* stream, string_view fmt, format_args args); // void vprint_nonunicode(FILE* stream, string_view fmt, format_args args); @@ -63,6 +65,20 @@ static void test_println() { assert(std::string_view(buffer.data(), pos) == "hello world!\n"); } +static void test_println_blank_line() { + std::array buffer{0}; + + FILE* file = fmemopen(buffer.data(), buffer.size(), "wb"); + assert(file); + + std::println(file); + long pos = std::ftell(file); + std::fclose(file); + + assert(pos > 0); + assert(std::string_view(buffer.data(), pos) == "\n"); +} + static void test_vprint_unicode() { std::array buffer{0}; @@ -96,6 +112,7 @@ static void test_vprint_nonunicode() { int main(int, char**) { test_print(); test_println(); + test_println_blank_line(); test_vprint_unicode(); test_vprint_nonunicode(); diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp new file mode 100644 index 000000000000..93c3563d501b --- /dev/null +++ b/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp @@ -0,0 +1,48 @@ +//===----------------------------------------------------------------------===// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 +// UNSUPPORTED: no-filesystem +// UNSUPPORTED: executor-has-no-bash +// UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME + +// FIXME PRINT How to test println on Windows? +// XFAIL: msvc, target={{.+}}-windows-gnu + +// XFAIL: availability-fp_to_chars-missing + +// + +// void println(); + +// Testing this properly is quite hard; the function unconditionally +// writes to stdout. When stdout is redirected to a file it is no longer +// considered a terminal. The function is a small wrapper around +// +// template +// void println(FILE* stream, format_string fmt, Args&&... args); +// +// So do minimal tests for this function and rely on the FILE* overload +// to do more testing. +// +// The testing is based on the testing for std::cout. + +// TODO PRINT Use lit builtin echo + +// FILE_DEPENDENCIES: echo.sh +// RUN: %{build} +// RUN: %{exec} bash echo.sh -ne "\n" > %t.expected +// RUN: %{exec} "%t.exe" > %t.actual +// RUN: diff -u %t.actual %t.expected + +#include + +int main(int, char**) { + std::println(); + + return 0; +} diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/println.file.pass.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/println.file.pass.cpp index 07272ebb57e5..2f088e7a7db5 100644 --- a/libcxx/test/std/input.output/iostream.format/print.fun/println.file.pass.cpp +++ b/libcxx/test/std/input.output/iostream.format/print.fun/println.file.pass.cpp @@ -129,6 +129,29 @@ static void test_new_line() { } } +static void test_println_blank_line() { + // Text does newline translation. + { + FILE* file = fopen(filename.c_str(), "w"); + assert(file); + + std::println(file); +#ifndef _WIN32 + assert(std::ftell(file) == 1); +#else + assert(std::ftell(file) == 2); +#endif + } + // Binary no newline translation. + { + FILE* file = fopen(filename.c_str(), "wb"); + assert(file); + + std::println(file); + assert(std::ftell(file) == 1); + } +} + int main(int, char**) { print_tests(test_file, test_exception); @@ -137,6 +160,7 @@ int main(int, char**) { #endif test_read_only(); test_new_line(); + test_println_blank_line(); return 0; } -- GitLab From bd589f5c7a079d8829fcf994b746634eaaea24ff Mon Sep 17 00:00:00 2001 From: Guillaume Chatelet Date: Sat, 6 Apr 2024 20:58:22 +0200 Subject: [PATCH 075/695] [libc] Move statement inside #ifdef/#endif to prevent unused variable warning This is a fix forward for arm32 `/llvm/libc_worker/worker/libc-arm32-debian/libc-arm32-debian-dbg/llvm-project/libc/src/__support/big_int.h:259:20: error: unused variable 'TOTAL_BITS' [-Werror,-Wunused-variable]` https://lab.llvm.org/buildbot/#/builders/229/builds/24791 --- libc/src/__support/big_int.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libc/src/__support/big_int.h b/libc/src/__support/big_int.h index f722a81d357d..e2061c430070 100644 --- a/libc/src/__support/big_int.h +++ b/libc/src/__support/big_int.h @@ -256,8 +256,8 @@ LIBC_INLINE constexpr cpp::array shift(cpp::array array, size_t offset) { static_assert(direction == LEFT || direction == RIGHT); constexpr size_t WORD_BITS = cpp::numeric_limits::digits; - constexpr size_t TOTAL_BITS = N * WORD_BITS; #ifdef LIBC_TYPES_HAS_INT128 + constexpr size_t TOTAL_BITS = N * WORD_BITS; if constexpr (TOTAL_BITS == 128) { using type = cpp::conditional_t; auto tmp = cpp::bit_cast(array); -- GitLab From 4cb110a84f587d3c65b85d79ab6fc8aa5489fb86 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 6 Apr 2024 15:27:45 -0400 Subject: [PATCH 076/695] [RFC] IR: Support atomicrmw FP ops with vector types (#86796) Allow using atomicrmw fadd, fsub, fmin, and fmax with vectors of floating-point type. AMDGPU supports atomic fadd for <2 x half> and <2 x bfloat> on some targets and address spaces. Note this only supports the proper floating-point operations; float vector typed xchg is still not supported. cmpxchg still only supports integers, so this inserts bitcasts for the loop expansion. I have support for fp vector typed xchg, and vector of int/ptr separately implemented but I don't have an immediate need for those beyond feature consistency. --- llvm/docs/LangRef.rst | 11 +- llvm/lib/AsmParser/LLParser.cpp | 4 +- llvm/lib/CodeGen/AtomicExpandPass.cpp | 6 +- llvm/lib/IR/Verifier.cpp | 5 +- llvm/test/Assembler/atomic.ll | 16 + .../Assembler/invalid-atomicrmw-scalable.ll | 41 + .../invalid-atomicrmw-xchg-fp-vector.ll | 7 + .../AArch64/atomicrmw-fadd-fp-vector.ll | 115 ++ .../CodeGen/X86/atomicrmw-fadd-fp-vector.ll | 84 ++ .../AMDGPU/expand-atomicrmw-fp-vector.ll | 1204 +++++++++++++++++ llvm/unittests/IR/VerifierTest.cpp | 28 + 11 files changed, 1510 insertions(+), 11 deletions(-) create mode 100644 llvm/test/Assembler/invalid-atomicrmw-scalable.ll create mode 100644 llvm/test/Assembler/invalid-atomicrmw-xchg-fp-vector.ll create mode 100644 llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll create mode 100644 llvm/test/CodeGen/X86/atomicrmw-fadd-fp-vector.ll create mode 100644 llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 774729c5f083..b3f41eb2ea09 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -11112,11 +11112,12 @@ For most of these operations, the type of '' must be an integer type whose bit width is a power of two greater than or equal to eight and less than or equal to a target-specific size limit. For xchg, this may also be a floating point or a pointer type with the same size constraints -as integers. For fadd/fsub/fmax/fmin, this must be a floating point type. The -type of the '````' operand must be a pointer to that type. If -the ``atomicrmw`` is marked as ``volatile``, then the optimizer is not -allowed to modify the number or order of execution of this -``atomicrmw`` with other :ref:`volatile operations `. +as integers. For fadd/fsub/fmax/fmin, this must be a floating-point +or fixed vector of floating-point type. The type of the '````' +operand must be a pointer to that type. If the ``atomicrmw`` is marked +as ``volatile``, then the optimizer is not allowed to modify the +number or order of execution of this ``atomicrmw`` with other +:ref:`volatile operations `. Note: if the alignment is not greater or equal to the size of the `` type, the atomic operation is likely to require a lock and have poor diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 67ec4a7c2dd0..8609f3d6276c 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -8240,6 +8240,8 @@ int LLParser::parseAtomicRMW(Instruction *&Inst, PerFunctionState &PFS) { return tokError("atomicrmw cannot be unordered"); if (!Ptr->getType()->isPointerTy()) return error(PtrLoc, "atomicrmw operand must be a pointer"); + if (Val->getType()->isScalableTy()) + return error(ValLoc, "atomicrmw operand may not be scalable"); if (Operation == AtomicRMWInst::Xchg) { if (!Val->getType()->isIntegerTy() && @@ -8251,7 +8253,7 @@ int LLParser::parseAtomicRMW(Instruction *&Inst, PerFunctionState &PFS) { " operand must be an integer, floating point, or pointer type"); } } else if (IsFP) { - if (!Val->getType()->isFloatingPointTy()) { + if (!Val->getType()->isFPOrFPVectorTy()) { return error(ValLoc, "atomicrmw " + AtomicRMWInst::getOperationName(Operation) + " operand must be a floating point type"); diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp index d5db79df6862..0aa89ea94335 100644 --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -562,9 +562,9 @@ static void createCmpXchgInstFun(IRBuilderBase &Builder, Value *Addr, Value *&Success, Value *&NewLoaded) { Type *OrigTy = NewVal->getType(); - // This code can go away when cmpxchg supports FP types. + // This code can go away when cmpxchg supports FP and vector types. assert(!OrigTy->isPointerTy()); - bool NeedBitcast = OrigTy->isFloatingPointTy(); + bool NeedBitcast = OrigTy->isFloatingPointTy() || OrigTy->isVectorTy(); if (NeedBitcast) { IntegerType *IntTy = Builder.getIntNTy(OrigTy->getPrimitiveSizeInBits()); NewVal = Builder.CreateBitCast(NewVal, IntTy); @@ -731,7 +731,7 @@ static PartwordMaskValues createMaskInstrs(IRBuilderBase &Builder, unsigned ValueSize = DL.getTypeStoreSize(ValueType); PMV.ValueType = PMV.IntValueType = ValueType; - if (PMV.ValueType->isFloatingPointTy()) + if (PMV.ValueType->isFloatingPointTy() || PMV.ValueType->isVectorTy()) PMV.IntValueType = Type::getIntNTy(Ctx, ValueType->getPrimitiveSizeInBits()); diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 64c59914cf2f..e63efe98a2e2 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -4268,9 +4268,10 @@ void Verifier::visitAtomicRMWInst(AtomicRMWInst &RMWI) { " operand must have integer or floating point type!", &RMWI, ElTy); } else if (AtomicRMWInst::isFPOperation(Op)) { - Check(ElTy->isFloatingPointTy(), + Check(ElTy->isFPOrFPVectorTy() && !isa(ElTy), "atomicrmw " + AtomicRMWInst::getOperationName(Op) + - " operand must have floating point type!", + " operand must have floating-point or fixed vector of floating-point " + "type!", &RMWI, ElTy); } else { Check(ElTy->isIntegerTy(), diff --git a/llvm/test/Assembler/atomic.ll b/llvm/test/Assembler/atomic.ll index e967407af14b..32fe82ef2268 100644 --- a/llvm/test/Assembler/atomic.ll +++ b/llvm/test/Assembler/atomic.ll @@ -72,3 +72,19 @@ define void @fp_atomics(ptr %x) { ret void } + +define void @fp_vector_atomicrmw(ptr %x, <2 x half> %val) { + ; CHECK: %atomic.fadd = atomicrmw fadd ptr %x, <2 x half> %val seq_cst + %atomic.fadd = atomicrmw fadd ptr %x, <2 x half> %val seq_cst + + ; CHECK: %atomic.fsub = atomicrmw fsub ptr %x, <2 x half> %val seq_cst + %atomic.fsub = atomicrmw fsub ptr %x, <2 x half> %val seq_cst + + ; CHECK: %atomic.fmax = atomicrmw fmax ptr %x, <2 x half> %val seq_cst + %atomic.fmax = atomicrmw fmax ptr %x, <2 x half> %val seq_cst + + ; CHECK: %atomic.fmin = atomicrmw fmin ptr %x, <2 x half> %val seq_cst + %atomic.fmin = atomicrmw fmin ptr %x, <2 x half> %val seq_cst + + ret void +} diff --git a/llvm/test/Assembler/invalid-atomicrmw-scalable.ll b/llvm/test/Assembler/invalid-atomicrmw-scalable.ll new file mode 100644 index 000000000000..e47413471570 --- /dev/null +++ b/llvm/test/Assembler/invalid-atomicrmw-scalable.ll @@ -0,0 +1,41 @@ +; RUN: split-file %s %t --leading-lines +; RUN: not llvm-as < %t/scalable_fp_vector_atomicrmw_xchg.ll 2>&1 | FileCheck -check-prefix=ERR0 %s +; RUN: not llvm-as < %t/scalable_int_vector_atomicrmw_xchg.ll 2>&1 | FileCheck -check-prefix=ERR1 %s +; RUN: not llvm-as < %t/scalable_ptr_vector_atomicrmw_xchg.ll 2>&1 | FileCheck -check-prefix=ERR2 %s +; RUN: not llvm-as < %t/scalable_fp_vector_atomicrmw_fadd.ll 2>&1 | FileCheck -check-prefix=ERR3 %s +; RUN: not llvm-as < %t/scalable_int_vector_atomicrmw_add.ll 2>&1 | FileCheck -check-prefix=ERR4 %s + +;--- scalable_fp_vector_atomicrmw_xchg.ll +define @scalable_fp_vector_atomicrmw_xchg(ptr %x, %val) { +; ERR0: :41: error: atomicrmw operand may not be scalable + %atomic.xchg = atomicrmw xchg ptr %x, %val seq_cst + ret %atomic.xchg +} + +;--- scalable_int_vector_atomicrmw_xchg.ll +define @scalable_int_vector_atomicrmw_xchg(ptr %x, %val) { +; ERR1: :41: error: atomicrmw operand may not be scalable + %atomic.xchg = atomicrmw xchg ptr %x, %val seq_cst + ret %atomic.xchg +} + +;--- scalable_ptr_vector_atomicrmw_xchg.ll +define @scalable_ptr_vector_atomicrmw_xchg(ptr %x, %val) { +; ERR2: :41: error: atomicrmw operand may not be scalable + %atomic.xchg = atomicrmw xchg ptr %x, %val seq_cst + ret %atomic.xchg +} + +;--- scalable_fp_vector_atomicrmw_fadd.ll +define @scalable_fp_vector_atomicrmw_fadd(ptr %x, %val) { +; ERR3: :41: error: atomicrmw operand may not be scalable + %atomic.fadd = atomicrmw fadd ptr %x, %val seq_cst + ret %atomic.fadd +} + +;--- scalable_int_vector_atomicrmw_add.ll +define @scalable_int_vector_atomicrmw_add(ptr %x, %val) { +; ERR4: :39: error: atomicrmw operand may not be scalable + %atomic.add = atomicrmw add ptr %x, %val seq_cst + ret %atomic.add +} diff --git a/llvm/test/Assembler/invalid-atomicrmw-xchg-fp-vector.ll b/llvm/test/Assembler/invalid-atomicrmw-xchg-fp-vector.ll new file mode 100644 index 000000000000..ea523255ee77 --- /dev/null +++ b/llvm/test/Assembler/invalid-atomicrmw-xchg-fp-vector.ll @@ -0,0 +1,7 @@ +; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s + +; CHECK: error: atomicrmw xchg operand must be an integer, floating point, or pointer type +define <2 x half> @fp_vector_atomicrmw(ptr %x, <2 x half> %val) { + %atomic.xchg = atomicrmw xchg ptr %x, <2 x half> %val seq_cst + ret <2 x half> %atomic.xchg +} diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll new file mode 100644 index 000000000000..a7539ac3cce8 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/atomicrmw-fadd-fp-vector.ll @@ -0,0 +1,115 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=aarch64-- -O1 -fast-isel=0 -global-isel=false %s -o - | FileCheck -check-prefixes=CHECK,NOLSE %s +; RUN: llc -mtriple=aarch64-- -mattr=+lse -O1 -fast-isel=0 -global-isel=false %s -o - | FileCheck -check-prefixes=CHECK,LSE %s + +define <2 x half> @test_atomicrmw_fadd_v2f16_align4(ptr addrspace(1) %ptr, <2 x half> %value) #0 { +; NOLSE-LABEL: test_atomicrmw_fadd_v2f16_align4: +; NOLSE: // %bb.0: +; NOLSE-NEXT: fcvtl v1.4s, v0.4h +; NOLSE-NEXT: ldr s0, [x0] +; NOLSE-NEXT: b .LBB0_2 +; NOLSE-NEXT: .LBB0_1: // %atomicrmw.start +; NOLSE-NEXT: // in Loop: Header=BB0_2 Depth=1 +; NOLSE-NEXT: fmov s0, w10 +; NOLSE-NEXT: cmp w10, w9 +; NOLSE-NEXT: b.eq .LBB0_5 +; NOLSE-NEXT: .LBB0_2: // %atomicrmw.start +; NOLSE-NEXT: // =>This Loop Header: Depth=1 +; NOLSE-NEXT: // Child Loop BB0_3 Depth 2 +; NOLSE-NEXT: fcvtl v2.4s, v0.4h +; NOLSE-NEXT: fmov w9, s0 +; NOLSE-NEXT: fadd v2.4s, v2.4s, v1.4s +; NOLSE-NEXT: fcvtn v2.4h, v2.4s +; NOLSE-NEXT: fmov w8, s2 +; NOLSE-NEXT: .LBB0_3: // %atomicrmw.start +; NOLSE-NEXT: // Parent Loop BB0_2 Depth=1 +; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 +; NOLSE-NEXT: ldaxr w10, [x0] +; NOLSE-NEXT: cmp w10, w9 +; NOLSE-NEXT: b.ne .LBB0_1 +; NOLSE-NEXT: // %bb.4: // %atomicrmw.start +; NOLSE-NEXT: // in Loop: Header=BB0_3 Depth=2 +; NOLSE-NEXT: stlxr wzr, w8, [x0] +; NOLSE-NEXT: cbnz wzr, .LBB0_3 +; NOLSE-NEXT: b .LBB0_1 +; NOLSE-NEXT: .LBB0_5: // %atomicrmw.end +; NOLSE-NEXT: // kill: def $d0 killed $d0 killed $q0 +; NOLSE-NEXT: ret +; +; LSE-LABEL: test_atomicrmw_fadd_v2f16_align4: +; LSE: // %bb.0: +; LSE-NEXT: fcvtl v1.4s, v0.4h +; LSE-NEXT: ldr s0, [x0] +; LSE-NEXT: .LBB0_1: // %atomicrmw.start +; LSE-NEXT: // =>This Inner Loop Header: Depth=1 +; LSE-NEXT: fcvtl v2.4s, v0.4h +; LSE-NEXT: fmov w8, s0 +; LSE-NEXT: mov w10, w8 +; LSE-NEXT: fadd v2.4s, v2.4s, v1.4s +; LSE-NEXT: fcvtn v2.4h, v2.4s +; LSE-NEXT: fmov w9, s2 +; LSE-NEXT: casal w10, w9, [x0] +; LSE-NEXT: fmov s0, w10 +; LSE-NEXT: cmp w10, w8 +; LSE-NEXT: b.ne .LBB0_1 +; LSE-NEXT: // %bb.2: // %atomicrmw.end +; LSE-NEXT: // kill: def $d0 killed $d0 killed $q0 +; LSE-NEXT: ret + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x half> %value seq_cst, align 4 + ret <2 x half> %res +} + +define <2 x float> @test_atomicrmw_fadd_v2f32_align8(ptr addrspace(1) %ptr, <2 x float> %value) #0 { +; NOLSE-LABEL: test_atomicrmw_fadd_v2f32_align8: +; NOLSE: // %bb.0: +; NOLSE-NEXT: ldr d1, [x0] +; NOLSE-NEXT: b .LBB1_2 +; NOLSE-NEXT: .LBB1_1: // %atomicrmw.start +; NOLSE-NEXT: // in Loop: Header=BB1_2 Depth=1 +; NOLSE-NEXT: fmov d1, x10 +; NOLSE-NEXT: cmp x10, x9 +; NOLSE-NEXT: b.eq .LBB1_5 +; NOLSE-NEXT: .LBB1_2: // %atomicrmw.start +; NOLSE-NEXT: // =>This Loop Header: Depth=1 +; NOLSE-NEXT: // Child Loop BB1_3 Depth 2 +; NOLSE-NEXT: fadd v2.2s, v1.2s, v0.2s +; NOLSE-NEXT: fmov x9, d1 +; NOLSE-NEXT: fmov x8, d2 +; NOLSE-NEXT: .LBB1_3: // %atomicrmw.start +; NOLSE-NEXT: // Parent Loop BB1_2 Depth=1 +; NOLSE-NEXT: // => This Inner Loop Header: Depth=2 +; NOLSE-NEXT: ldaxr x10, [x0] +; NOLSE-NEXT: cmp x10, x9 +; NOLSE-NEXT: b.ne .LBB1_1 +; NOLSE-NEXT: // %bb.4: // %atomicrmw.start +; NOLSE-NEXT: // in Loop: Header=BB1_3 Depth=2 +; NOLSE-NEXT: stlxr wzr, x8, [x0] +; NOLSE-NEXT: cbnz wzr, .LBB1_3 +; NOLSE-NEXT: b .LBB1_1 +; NOLSE-NEXT: .LBB1_5: // %atomicrmw.end +; NOLSE-NEXT: fmov d0, d1 +; NOLSE-NEXT: ret +; +; LSE-LABEL: test_atomicrmw_fadd_v2f32_align8: +; LSE: // %bb.0: +; LSE-NEXT: ldr d1, [x0] +; LSE-NEXT: .LBB1_1: // %atomicrmw.start +; LSE-NEXT: // =>This Inner Loop Header: Depth=1 +; LSE-NEXT: fadd v2.2s, v1.2s, v0.2s +; LSE-NEXT: fmov x8, d1 +; LSE-NEXT: mov x10, x8 +; LSE-NEXT: fmov x9, d2 +; LSE-NEXT: casal x10, x9, [x0] +; LSE-NEXT: fmov d1, x10 +; LSE-NEXT: cmp x10, x8 +; LSE-NEXT: b.ne .LBB1_1 +; LSE-NEXT: // %bb.2: // %atomicrmw.end +; LSE-NEXT: fmov d0, d1 +; LSE-NEXT: ret + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x float> %value seq_cst, align 8 + ret <2 x float> %res +} + +attributes #0 = { nounwind } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK: {{.*}} diff --git a/llvm/test/CodeGen/X86/atomicrmw-fadd-fp-vector.ll b/llvm/test/CodeGen/X86/atomicrmw-fadd-fp-vector.ll new file mode 100644 index 000000000000..4f8cd5a52ed4 --- /dev/null +++ b/llvm/test/CodeGen/X86/atomicrmw-fadd-fp-vector.ll @@ -0,0 +1,84 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple x86_64-pc-linux < %s | FileCheck %s + +define <2 x half> @test_atomicrmw_fadd_v2f16_align4(ptr addrspace(1) %ptr, <2 x half> %value) #0 { +; CHECK-LABEL: test_atomicrmw_fadd_v2f16_align4: +; CHECK: # %bb.0: +; CHECK-NEXT: pushq %rbp +; CHECK-NEXT: pushq %rbx +; CHECK-NEXT: subq $88, %rsp +; CHECK-NEXT: movq %rdi, %rbx +; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; CHECK-NEXT: psrld $16, %xmm0 +; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; CHECK-NEXT: pinsrw $0, 2(%rdi), %xmm1 +; CHECK-NEXT: pinsrw $0, (%rdi), %xmm0 +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB0_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; CHECK-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; CHECK-NEXT: callq __extendhfsf2@PLT +; CHECK-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; CHECK-NEXT: callq __extendhfsf2@PLT +; CHECK-NEXT: addss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload +; CHECK-NEXT: callq __truncsfhf2@PLT +; CHECK-NEXT: pextrw $0, %xmm0, %eax +; CHECK-NEXT: movzwl %ax, %ebp +; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; CHECK-NEXT: callq __extendhfsf2@PLT +; CHECK-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill +; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; CHECK-NEXT: callq __extendhfsf2@PLT +; CHECK-NEXT: addss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload +; CHECK-NEXT: callq __truncsfhf2@PLT +; CHECK-NEXT: pextrw $0, %xmm0, %ecx +; CHECK-NEXT: shll $16, %ecx +; CHECK-NEXT: orl %ebp, %ecx +; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; CHECK-NEXT: pextrw $0, %xmm0, %edx +; CHECK-NEXT: shll $16, %edx +; CHECK-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload +; CHECK-NEXT: pextrw $0, %xmm0, %eax +; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: orl %edx, %eax +; CHECK-NEXT: lock cmpxchgl %ecx, (%rbx) +; CHECK-NEXT: setne %cl +; CHECK-NEXT: pinsrw $0, %eax, %xmm0 +; CHECK-NEXT: shrl $16, %eax +; CHECK-NEXT: pinsrw $0, %eax, %xmm1 +; CHECK-NEXT: testb %cl, %cl +; CHECK-NEXT: jne .LBB0_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; CHECK-NEXT: addq $88, %rsp +; CHECK-NEXT: popq %rbx +; CHECK-NEXT: popq %rbp +; CHECK-NEXT: retq + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x half> %value seq_cst, align 4 + ret <2 x half> %res +} + +define <2 x float> @test_atomicrmw_fadd_v2f32_align8(ptr addrspace(1) %ptr, <2 x float> %value) #0 { +; CHECK-LABEL: test_atomicrmw_fadd_v2f32_align8: +; CHECK: # %bb.0: +; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero +; CHECK-NEXT: .p2align 4, 0x90 +; CHECK-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: movq %xmm1, %rax +; CHECK-NEXT: addps %xmm0, %xmm1 +; CHECK-NEXT: movq %xmm1, %rcx +; CHECK-NEXT: lock cmpxchgq %rcx, (%rdi) +; CHECK-NEXT: movq %rax, %xmm1 +; CHECK-NEXT: jne .LBB1_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: movdqa %xmm1, %xmm0 +; CHECK-NEXT: retq + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x float> %value seq_cst, align 8 + ret <2 x float> %res +} + +attributes #0 = { nounwind } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll new file mode 100644 index 000000000000..1411890e01dc --- /dev/null +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomicrmw-fp-vector.ll @@ -0,0 +1,1204 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=atomic-expand -mcpu=gfx900 %s | FileCheck %s +; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=atomic-expand -mcpu=gfx90a %s | FileCheck %s +; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -passes=atomic-expand -mcpu=gfx940 %s | FileCheck %s + +;--------------------------------------------------------------------- +; atomicrmw fadd +;--------------------------------------------------------------------- + +define <2 x half> @test_atomicrmw_fadd_v2f16_global_agent_align2(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fadd_v2f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <2 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x half> [[NEW]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <2 x half>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <2 x half>, i1 } poison, <2 x half> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x half>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x half>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x half>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[NEWLOADED]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 2 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fadd_v2bf16_global_agent_align2(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fadd_v2bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <2 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x bfloat> [[NEW]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <2 x bfloat>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <2 x bfloat>, i1 } poison, <2 x bfloat> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x bfloat>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x bfloat>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x bfloat>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <2 x bfloat> %res +} + +define <2 x half> @test_atomicrmw_fadd_v2f16_global_agent_align4(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fadd_v2f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <2 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x half> [[NEW]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x half> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP3]], i32 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i32 [[NEWLOADED]] to <2 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[TMP5]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 4 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fadd_v2bf16_global_agent_align4(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fadd_v2bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <2 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x bfloat> [[NEW]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x bfloat> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP3]], i32 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i32 [[NEWLOADED]] to <2 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[TMP5]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <2 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fadd_v4f16_global_agent_align2(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fadd_v4f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <4 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 2 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fadd_v4bf16_global_agent_align2(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fadd_v4bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <4 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fadd_v4f16_global_agent_align4(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fadd_v4f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <4 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 4 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fadd_v4bf16_global_agent_align4(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fadd_v4bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <4 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fadd_v4f16_global_agent_align8(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fadd_v4f16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <4 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[NEW]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP3]], i64 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i64 [[NEWLOADED]] to <4 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[TMP5]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 8 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fadd_v4bf16_global_agent_align8(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fadd_v4bf16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <4 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x bfloat> [[NEW]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x bfloat> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP3]], i64 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i64 [[NEWLOADED]] to <4 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[TMP5]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 8 + ret <4 x bfloat> %res +} + +define <2 x float> @test_atomicrmw_fadd_v2f32_global_agent_align8(ptr addrspace(1) %ptr, <2 x float> %value) { +; CHECK-LABEL: define <2 x float> @test_atomicrmw_fadd_v2f32_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x float> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x float> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fadd <2 x float> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[NEW]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP3]], i64 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i64 [[NEWLOADED]] to <2 x float> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x float> [[TMP5]] +; + %res = atomicrmw fadd ptr addrspace(1) %ptr, <2 x float> %value syncscope("agent") seq_cst, align 8 + ret <2 x float> %res +} + +;--------------------------------------------------------------------- +; atomicrmw fsub +;--------------------------------------------------------------------- + +define <2 x half> @test_atomicrmw_fsub_v2f16_global_agent_align2(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fsub_v2f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <2 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x half> [[NEW]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <2 x half>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <2 x half>, i1 } poison, <2 x half> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x half>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x half>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x half>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[NEWLOADED]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 2 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fsub_v2bf16_global_agent_align2(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fsub_v2bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <2 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x bfloat> [[NEW]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <2 x bfloat>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <2 x bfloat>, i1 } poison, <2 x bfloat> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x bfloat>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x bfloat>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x bfloat>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <2 x bfloat> %res +} + +define <2 x half> @test_atomicrmw_fsub_v2f16_global_agent_align4(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fsub_v2f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <2 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x half> [[NEW]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x half> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP3]], i32 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i32 [[NEWLOADED]] to <2 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[TMP5]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 4 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fsub_v2bf16_global_agent_align4(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fsub_v2bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <2 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x bfloat> [[NEW]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x bfloat> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP3]], i32 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i32 [[NEWLOADED]] to <2 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[TMP5]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <2 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fsub_v4f16_global_agent_align2(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fsub_v4f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <4 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 2 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fsub_v4bf16_global_agent_align2(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fsub_v4bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <4 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fsub_v4f16_global_agent_align4(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fsub_v4f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <4 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 4 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fsub_v4bf16_global_agent_align4(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fsub_v4bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <4 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[NEW]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP4]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP6:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP6]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP7]], i1 [[TMP5]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP8]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fsub_v4f16_global_agent_align8(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fsub_v4f16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <4 x half> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[NEW]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP3]], i64 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i64 [[NEWLOADED]] to <4 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[TMP5]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 8 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fsub_v4bf16_global_agent_align8(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fsub_v4bf16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <4 x bfloat> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x bfloat> [[NEW]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x bfloat> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP3]], i64 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i64 [[NEWLOADED]] to <4 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[TMP5]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 8 + ret <4 x bfloat> %res +} + +define <2 x float> @test_atomicrmw_fsub_v2f32_global_agent_align8(ptr addrspace(1) %ptr, <2 x float> %value) { +; CHECK-LABEL: define <2 x float> @test_atomicrmw_fsub_v2f32_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x float> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x float> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP5:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[NEW:%.*]] = fsub <2 x float> [[LOADED]], [[VALUE]] +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[NEW]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP3]], i64 [[TMP2]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 +; CHECK-NEXT: [[TMP5]] = bitcast i64 [[NEWLOADED]] to <2 x float> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x float> [[TMP5]] +; + %res = atomicrmw fsub ptr addrspace(1) %ptr, <2 x float> %value syncscope("agent") seq_cst, align 8 + ret <2 x float> %res +} + +;--------------------------------------------------------------------- +; atomicrmw fmin +;--------------------------------------------------------------------- + +define <2 x half> @test_atomicrmw_fmin_v2f16_global_agent_align2(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fmin_v2f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <2 x half> @llvm.minnum.v2f16(<2 x half> [[LOADED]], <2 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x half> [[TMP4]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <2 x half>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x half>, i1 } poison, <2 x half> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <2 x half>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x half>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x half>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[NEWLOADED]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 2 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_global_agent_align2(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <2 x bfloat> @llvm.minnum.v2bf16(<2 x bfloat> [[LOADED]], <2 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x bfloat> [[TMP4]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <2 x bfloat>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x bfloat>, i1 } poison, <2 x bfloat> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <2 x bfloat>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x bfloat>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x bfloat>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <2 x bfloat> %res +} + +define <2 x half> @test_atomicrmw_fmin_v2f16_global_agent_align4(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fmin_v2f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <2 x half> @llvm.minnum.v2f16(<2 x half> [[LOADED]], <2 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x half> [[TMP2]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x half> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to <2 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[TMP6]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 4 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_global_agent_align4(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fmin_v2bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <2 x bfloat> @llvm.minnum.v2bf16(<2 x bfloat> [[LOADED]], <2 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x bfloat> [[TMP2]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x bfloat> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to <2 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[TMP6]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <2 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fmin_v4f16_global_agent_align2(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fmin_v4f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x half> @llvm.minnum.v4f16(<4 x half> [[LOADED]], <4 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x half>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 2 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fmin_v4bf16_global_agent_align2(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fmin_v4bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x bfloat> @llvm.minnum.v4bf16(<4 x bfloat> [[LOADED]], <4 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fmin_v4f16_global_agent_align4(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fmin_v4f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x half> @llvm.minnum.v4f16(<4 x half> [[LOADED]], <4 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x half>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 4 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fmin_v4bf16_global_agent_align4(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fmin_v4bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x bfloat> @llvm.minnum.v4bf16(<4 x bfloat> [[LOADED]], <4 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fmin_v4f16_global_agent_align8(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fmin_v4f16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <4 x half> @llvm.minnum.v4f16(<4 x half> [[LOADED]], <4 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x half> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to <4 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[TMP6]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 8 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fmin_v4bf16_global_agent_align8(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fmin_v4bf16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <4 x bfloat> @llvm.minnum.v4bf16(<4 x bfloat> [[LOADED]], <4 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x bfloat> [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x bfloat> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to <4 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[TMP6]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 8 + ret <4 x bfloat> %res +} + +define <2 x float> @test_atomicrmw_fmin_v2f32_global_agent_align8(ptr addrspace(1) %ptr, <2 x float> %value) { +; CHECK-LABEL: define <2 x float> @test_atomicrmw_fmin_v2f32_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x float> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x float> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.minnum.v2f32(<2 x float> [[LOADED]], <2 x float> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x float> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to <2 x float> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x float> [[TMP6]] +; + %res = atomicrmw fmin ptr addrspace(1) %ptr, <2 x float> %value syncscope("agent") seq_cst, align 8 + ret <2 x float> %res +} + +;--------------------------------------------------------------------- +; atomicrmw fmax +;--------------------------------------------------------------------- + +define <2 x half> @test_atomicrmw_fmax_v2f16_global_agent_align2(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fmax_v2f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x half>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <2 x half> @llvm.maxnum.v2f16(<2 x half> [[LOADED]], <2 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x half> [[TMP4]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <2 x half>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x half>, i1 } poison, <2 x half> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <2 x half>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x half>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x half>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[NEWLOADED]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 2 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_global_agent_align2(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <2 x bfloat>, align 4, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <2 x bfloat> @llvm.maxnum.v2bf16(<2 x bfloat> [[LOADED]], <2 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <2 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <2 x bfloat> [[TMP4]], ptr addrspace(5) [[TMP2]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 4, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <2 x bfloat>, ptr addrspace(5) [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <2 x bfloat>, i1 } poison, <2 x bfloat> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <2 x bfloat>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <2 x bfloat>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <2 x bfloat>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <2 x bfloat> %res +} + +define <2 x half> @test_atomicrmw_fmax_v2f16_global_agent_align4(ptr addrspace(1) %ptr, <2 x half> %value) { +; CHECK-LABEL: define <2 x half> @test_atomicrmw_fmax_v2f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <2 x half> @llvm.maxnum.v2f16(<2 x half> [[LOADED]], <2 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x half> [[TMP2]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x half> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to <2 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x half> [[TMP6]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <2 x half> %value syncscope("agent") seq_cst, align 4 + ret <2 x half> %res +} + +define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_global_agent_align4(ptr addrspace(1) %ptr, <2 x bfloat> %value) { +; CHECK-LABEL: define <2 x bfloat> @test_atomicrmw_fmax_v2bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <2 x bfloat> @llvm.maxnum.v2bf16(<2 x bfloat> [[LOADED]], <2 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x bfloat> [[TMP2]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x bfloat> [[LOADED]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 4 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to <2 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x bfloat> [[TMP6]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <2 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <2 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fmax_v4f16_global_agent_align2(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fmax_v4f16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x half> @llvm.maxnum.v4f16(<4 x half> [[LOADED]], <4 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x half>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 2 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fmax_v4bf16_global_agent_align2(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fmax_v4bf16_global_agent_align2( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 2 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x bfloat> @llvm.maxnum.v4bf16(<4 x bfloat> [[LOADED]], <4 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 2 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fmax_v4f16_global_agent_align4(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fmax_v4f16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x half>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x half> @llvm.maxnum.v4f16(<4 x half> [[LOADED]], <4 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x half> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x half> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x half>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x half>, i1 } poison, <4 x half> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x half>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x half>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x half>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[NEWLOADED]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 4 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fmax_v4bf16_global_agent_align4(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fmax_v4bf16_global_agent_align4( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP2:%.*]] = alloca <4 x bfloat>, align 8, addrspace(5) +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 4 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP4:%.*]] = call <4 x bfloat> @llvm.maxnum.v4bf16(<4 x bfloat> [[LOADED]], <4 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: store <4 x bfloat> [[LOADED]], ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: store <4 x bfloat> [[TMP4]], ptr addrspace(5) [[TMP2]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 8, ptr [[TMP5]], ptr addrspace(5) [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5, i32 5) +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP2]]) +; CHECK-NEXT: [[TMP7:%.*]] = load <4 x bfloat>, ptr addrspace(5) [[TMP1]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p5(i64 8, ptr addrspace(5) [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { <4 x bfloat>, i1 } poison, <4 x bfloat> [[TMP7]], 0 +; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { <4 x bfloat>, i1 } [[TMP8]], i1 [[TMP6]], 1 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 1 +; CHECK-NEXT: [[NEWLOADED]] = extractvalue { <4 x bfloat>, i1 } [[TMP9]], 0 +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[NEWLOADED]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 4 + ret <4 x bfloat> %res +} + +define <4 x half> @test_atomicrmw_fmax_v4f16_global_agent_align8(ptr addrspace(1) %ptr, <4 x half> %value) { +; CHECK-LABEL: define <4 x half> @test_atomicrmw_fmax_v4f16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x half> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x half>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x half> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <4 x half> @llvm.maxnum.v4f16(<4 x half> [[LOADED]], <4 x half> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x half> [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x half> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to <4 x half> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x half> [[TMP6]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <4 x half> %value syncscope("agent") seq_cst, align 8 + ret <4 x half> %res +} + +define <4 x bfloat> @test_atomicrmw_fmax_v4bf16_global_agent_align8(ptr addrspace(1) %ptr, <4 x bfloat> %value) { +; CHECK-LABEL: define <4 x bfloat> @test_atomicrmw_fmax_v4bf16_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <4 x bfloat> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x bfloat>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <4 x bfloat> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <4 x bfloat> @llvm.maxnum.v4bf16(<4 x bfloat> [[LOADED]], <4 x bfloat> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x bfloat> [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x bfloat> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to <4 x bfloat> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <4 x bfloat> [[TMP6]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <4 x bfloat> %value syncscope("agent") seq_cst, align 8 + ret <4 x bfloat> %res +} + +define <2 x float> @test_atomicrmw_fmax_v2f32_global_agent_align8(ptr addrspace(1) %ptr, <2 x float> %value) { +; CHECK-LABEL: define <2 x float> @test_atomicrmw_fmax_v2f32_global_agent_align8( +; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], <2 x float> [[VALUE:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr addrspace(1) [[PTR]], align 8 +; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] +; CHECK: atomicrmw.start: +; CHECK-NEXT: [[LOADED:%.*]] = phi <2 x float> [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] +; CHECK-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.maxnum.v2f32(<2 x float> [[LOADED]], <2 x float> [[VALUE]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x float> [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x float> [[LOADED]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("agent") seq_cst seq_cst, align 8 +; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 +; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 +; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to <2 x float> +; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; CHECK: atomicrmw.end: +; CHECK-NEXT: ret <2 x float> [[TMP6]] +; + %res = atomicrmw fmax ptr addrspace(1) %ptr, <2 x float> %value syncscope("agent") seq_cst, align 8 + ret <2 x float> %res +} diff --git a/llvm/unittests/IR/VerifierTest.cpp b/llvm/unittests/IR/VerifierTest.cpp index b2cd71e6a385..c8db7fb7ab84 100644 --- a/llvm/unittests/IR/VerifierTest.cpp +++ b/llvm/unittests/IR/VerifierTest.cpp @@ -367,5 +367,33 @@ TEST(VerifierTest, CrossFunctionRef) { Store->eraseFromParent(); } +TEST(VerifierTest, AtomicRMW) { + LLVMContext C; + Module M("M", C); + FunctionType *FTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg=*/false); + Function *F = Function::Create(FTy, Function::ExternalLinkage, "foo", M); + BasicBlock *Entry = BasicBlock::Create(C, "entry", F); + Value *Ptr = PoisonValue::get(PointerType::get(C, 0)); + + Type *FPTy = Type::getFloatTy(C); + Constant *CF = ConstantFP::getZero(FPTy); + + // Invalid scalable type : atomicrmw () + Constant *CV = ConstantVector::getSplat(ElementCount::getScalable(2), CF); + new AtomicRMWInst(AtomicRMWInst::FAdd, Ptr, CV, Align(8), + AtomicOrdering::SequentiallyConsistent, SyncScope::System, + Entry); + ReturnInst::Create(C, Entry); + + std::string Error; + raw_string_ostream ErrorOS(Error); + EXPECT_TRUE(verifyFunction(*F, &ErrorOS)); + EXPECT_TRUE( + StringRef(ErrorOS.str()) + .starts_with("atomicrmw fadd operand must have floating-point or " + "fixed vector of floating-point type!")) + << ErrorOS.str(); +} + } // end anonymous namespace } // end namespace llvm -- GitLab From d38bff460acb4fe3156d90ec739da49344db14ca Mon Sep 17 00:00:00 2001 From: Sizov Nikita Date: Sat, 6 Apr 2024 23:41:24 +0300 Subject: [PATCH 077/695] [AArch64] SimplifyDemandedBitsForTargetNode - add AArch64ISD::BICi handling (#76644) Fold BICi if all destination bits are already known to be zeroes ```llvm define <8 x i16> @haddu_known(<8 x i8> %a0, <8 x i8> %a1) { %x0 = zext <8 x i8> %a0 to <8 x i16> %x1 = zext <8 x i8> %a1 to <8 x i16> %hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1) %res = and <8 x i16> %hadd, ret <8 x i16> %res } declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>) ``` ``` haddu_known: // @haddu_known ushll v0.8h, v0.8b, #0 ushll v1.8h, v1.8b, #0 uhadd v0.8h, v0.8h, v1.8h bic v0.8h, #254, lsl #8 <-- this one will be removed as we know high bits are zero extended ret ``` Fixes #53881 Fixes #53622 --- .../Target/AArch64/AArch64ISelLowering.cpp | 30 +++++++++++++++++++ .../AArch64/aarch64-known-bits-hadd.ll | 4 --- 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b10d8a80c8c9..819e8ccd5c33 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -24555,6 +24555,18 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, if (auto R = foldOverflowCheck(N, DAG, /* IsAdd */ false)) return R; return performFlagSettingCombine(N, DCI, AArch64ISD::SBC); + case AArch64ISD::BICi: { + APInt DemandedBits = + APInt::getAllOnes(N->getValueType(0).getScalarSizeInBits()); + APInt DemandedElts = + APInt::getAllOnes(N->getValueType(0).getVectorNumElements()); + + if (DAG.getTargetLoweringInfo().SimplifyDemandedBits( + SDValue(N, 0), DemandedBits, DemandedElts, DCI)) + return SDValue(); + + break; + } case ISD::XOR: return performXorCombine(N, DAG, DCI, Subtarget); case ISD::MUL: @@ -27595,6 +27607,24 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode( // used - simplify to just Val. return TLO.CombineTo(Op, ShiftR->getOperand(0)); } + case AArch64ISD::BICi: { + // Fold BICi if all destination bits already known to be zeroed + SDValue Op0 = Op.getOperand(0); + KnownBits KnownOp0 = + TLO.DAG.computeKnownBits(Op0, OriginalDemandedElts, Depth + 1); + // Op0 &= ~(ConstantOperandVal(1) << ConstantOperandVal(2)) + uint64_t BitsToClear = Op->getConstantOperandVal(1) + << Op->getConstantOperandVal(2); + APInt AlreadyZeroedBitsToClear = BitsToClear & KnownOp0.Zero; + if (APInt(Known.getBitWidth(), BitsToClear) + .isSubsetOf(AlreadyZeroedBitsToClear)) + return TLO.CombineTo(Op, Op0); + + Known = KnownOp0 & + KnownBits::makeConstant(APInt(Known.getBitWidth(), ~BitsToClear)); + + return false; + } case ISD::INTRINSIC_WO_CHAIN: { if (auto ElementSize = IsSVECntIntrinsic(Op)) { unsigned MaxSVEVectorSizeInBits = Subtarget->getMaxSVEVectorSizeInBits(); diff --git a/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll b/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll index 017f38277489..f36b8440fe4b 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll @@ -12,7 +12,6 @@ define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) { ; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0 ; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h -; CHECK-NEXT: bic v0.8h, #254, lsl #8 ; CHECK-NEXT: ret %x0 = zext <8 x i8> %a0 to <8 x i16> %x1 = zext <8 x i8> %a1 to <8 x i16> @@ -27,7 +26,6 @@ define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) { ; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0 ; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h -; CHECK-NEXT: bic v0.8h, #254, lsl #8 ; CHECK-NEXT: ret %x0 = zext <8 x i8> %a0 to <8 x i16> %x1 = zext <8 x i8> %a1 to <8 x i16> @@ -42,7 +40,6 @@ define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) { ; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0 ; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h -; CHECK-NEXT: bic v0.8h, #254, lsl #8 ; CHECK-NEXT: ret %x0 = zext <8 x i8> %a0 to <8 x i16> %x1 = zext <8 x i8> %a1 to <8 x i16> @@ -57,7 +54,6 @@ define <8 x i16> @shaddu_zext(<8 x i8> %a0, <8 x i8> %a1) { ; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: ushll v1.8h, v1.8b, #0 ; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h -; CHECK-NEXT: bic v0.8h, #254, lsl #8 ; CHECK-NEXT: ret %x0 = zext <8 x i8> %a0 to <8 x i16> %x1 = zext <8 x i8> %a1 to <8 x i16> -- GitLab From bd9486b4ec7dc24f73f32474fa38b522a7cce085 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Storsj=C3=B6?= Date: Sat, 6 Apr 2024 18:17:39 +0300 Subject: [PATCH 078/695] Revert "[SLP]Improve minbitwidth analysis for abs/smin/smax/umin/umax intrinsics." This reverts commit 66b528078e4852412769375e35d2a672bf36a0ec. This commit caused miscompilations, breaking tests in the libyuv testsuite - see https://github.com/llvm/llvm-project/pull/86135#issuecomment-2041049709 for more details. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 102 +++--------------- .../X86/call-arg-reduced-by-minbitwidth.ll | 4 +- .../cmp-after-intrinsic-call-minbitwidth.ll | 12 +-- .../X86/store-abs-minbitwidth.ll | 9 +- 4 files changed, 27 insertions(+), 100 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 731d7b4edfa3..332877f35081 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -7056,16 +7056,19 @@ bool BoUpSLP::areAllUsersVectorized( static std::pair getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, - TargetTransformInfo *TTI, TargetLibraryInfo *TLI, - ArrayRef ArgTys) { + TargetTransformInfo *TTI, TargetLibraryInfo *TLI) { Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); // Calculate the cost of the scalar and vector calls. + SmallVector VecTys; + for (Use &Arg : CI->args()) + VecTys.push_back( + FixedVectorType::get(Arg->getType(), VecTy->getNumElements())); FastMathFlags FMF; if (auto *FPCI = dyn_cast(CI)) FMF = FPCI->getFastMathFlags(); SmallVector Arguments(CI->args()); - IntrinsicCostAttributes CostAttrs(ID, VecTy, Arguments, ArgTys, FMF, + IntrinsicCostAttributes CostAttrs(ID, VecTy, Arguments, VecTys, FMF, dyn_cast(CI)); auto IntrinsicCost = TTI->getIntrinsicInstrCost(CostAttrs, TTI::TCK_RecipThroughput); @@ -7078,8 +7081,8 @@ getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, if (!CI->isNoBuiltin() && VecFunc) { // Calculate the cost of the vector library call. // If the corresponding vector call is cheaper, return its cost. - LibCost = - TTI->getCallInstrCost(nullptr, VecTy, ArgTys, TTI::TCK_RecipThroughput); + LibCost = TTI->getCallInstrCost(nullptr, VecTy, VecTys, + TTI::TCK_RecipThroughput); } return {IntrinsicCost, LibCost}; } @@ -8505,30 +8508,6 @@ TTI::CastContextHint BoUpSLP::getCastContextHint(const TreeEntry &TE) const { return TTI::CastContextHint::None; } -/// Builds the arguments types vector for the given call instruction with the -/// given \p ID for the specified vector factor. -static SmallVector buildIntrinsicArgTypes(const CallInst *CI, - const Intrinsic::ID ID, - const unsigned VF, - unsigned MinBW) { - SmallVector ArgTys; - for (auto [Idx, Arg] : enumerate(CI->args())) { - if (ID != Intrinsic::not_intrinsic) { - if (isVectorIntrinsicWithScalarOpAtArg(ID, Idx)) { - ArgTys.push_back(Arg->getType()); - continue; - } - if (MinBW > 0) { - ArgTys.push_back(FixedVectorType::get( - IntegerType::get(CI->getContext(), MinBW), VF)); - continue; - } - } - ArgTys.push_back(FixedVectorType::get(Arg->getType(), VF)); - } - return ArgTys; -} - InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, SmallPtrSetImpl &CheckedExtracts) { @@ -9095,11 +9074,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, }; auto GetVectorCost = [=](InstructionCost CommonCost) { auto *CI = cast(VL0); - Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); - SmallVector ArgTys = - buildIntrinsicArgTypes(CI, ID, VecTy->getNumElements(), - It != MinBWs.end() ? It->second.first : 0); - auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI, ArgTys); + auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI); return std::min(VecCallCosts.first, VecCallCosts.second) + CommonCost; }; return GetCostDiff(GetScalarCost, GetVectorCost); @@ -12571,10 +12546,7 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); - SmallVector ArgTys = - buildIntrinsicArgTypes(CI, ID, VecTy->getNumElements(), - It != MinBWs.end() ? It->second.first : 0); - auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI, ArgTys); + auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI); bool UseIntrinsic = ID != Intrinsic::not_intrinsic && VecCallCosts.first <= VecCallCosts.second; @@ -12583,7 +12555,8 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { SmallVector TysForDecl; // Add return type if intrinsic is overloaded on it. if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1)) - TysForDecl.push_back(VecTy); + TysForDecl.push_back( + FixedVectorType::get(CI->getType(), E->Scalars.size())); auto *CEI = cast(VL0); for (unsigned I : seq(0, CI->arg_size())) { ValueList OpVL; @@ -12591,12 +12564,7 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { // vectorized. if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) { ScalarArg = CEI->getArgOperand(I); - // if decided to reduce bitwidth of abs intrinsic, it second argument - // must be set false (do not return poison, if value issigned min). - if (ID == Intrinsic::abs && It != MinBWs.end() && - It->second.first < DL->getTypeSizeInBits(CEI->getType())) - ScalarArg = Builder.getFalse(); - OpVecs.push_back(ScalarArg); + OpVecs.push_back(CEI->getArgOperand(I)); if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I)) TysForDecl.push_back(ScalarArg->getType()); continue; @@ -12609,13 +12577,10 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { } ScalarArg = CEI->getArgOperand(I); if (cast(OpVec->getType())->getElementType() != - ScalarArg->getType() && - It == MinBWs.end()) { + ScalarArg->getType()) { auto *CastTy = FixedVectorType::get(ScalarArg->getType(), VecTy->getNumElements()); OpVec = Builder.CreateIntCast(OpVec, CastTy, GetOperandSignedness(I)); - } else if (It != MinBWs.end()) { - OpVec = Builder.CreateIntCast(OpVec, VecTy, GetOperandSignedness(I)); } LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n"); OpVecs.push_back(OpVec); @@ -14359,45 +14324,6 @@ bool BoUpSLP::collectValuesToDemote( return TryProcessInstruction(I, *ITE, BitWidth, Ops); } - case Instruction::Call: { - auto *IC = dyn_cast(I); - if (!IC) - break; - Intrinsic::ID ID = getVectorIntrinsicIDForCall(IC, TLI); - if (ID != Intrinsic::abs && ID != Intrinsic::smin && - ID != Intrinsic::smax && ID != Intrinsic::umin && ID != Intrinsic::umax) - break; - SmallVector Operands(1, I->getOperand(0)); - End = 1; - if (ID != Intrinsic::abs) { - Operands.push_back(I->getOperand(1)); - End = 2; - } - InstructionCost BestCost = - std::numeric_limits::max(); - unsigned BestBitWidth = BitWidth; - unsigned VF = ITE->Scalars.size(); - // Choose the best bitwidth based on cost estimations. - auto Checker = [&](unsigned BitWidth, unsigned) { - unsigned MinBW = PowerOf2Ceil(BitWidth); - SmallVector ArgTys = buildIntrinsicArgTypes(IC, ID, VF, MinBW); - auto VecCallCosts = getVectorCallCosts( - IC, - FixedVectorType::get(IntegerType::get(IC->getContext(), MinBW), VF), - TTI, TLI, ArgTys); - InstructionCost Cost = std::min(VecCallCosts.first, VecCallCosts.second); - if (Cost < BestCost) { - BestCost = Cost; - BestBitWidth = BitWidth; - } - return false; - }; - [[maybe_unused]] bool NeedToExit; - (void)AttemptCheckBitwidth(Checker, NeedToExit); - BitWidth = BestBitWidth; - return TryProcessInstruction(I, *ITE, BitWidth, Operands); - } - // Otherwise, conservatively give up. default: break; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll index 82966124d3ba..27c9655f94d3 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll @@ -11,7 +11,9 @@ define void @test(ptr %0, i8 %1, i1 %cmp12.i) { ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <8 x i32> zeroinitializer ; CHECK-NEXT: br label [[PRE:%.*]] ; CHECK: pre: -; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP5]], <8 x i8> ) +; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[TMP6]], <8 x i32> ) +; CHECK-NEXT: [[TMP8:%.*]] = trunc <8 x i32> [[TMP7]] to <8 x i8> ; CHECK-NEXT: [[TMP9:%.*]] = add <8 x i8> [[TMP8]], ; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x i8> [[TMP9]], <8 x i8> [[TMP5]] ; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[TMP0]], align 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll index 9fa88084aaa0..a05d4fdd6315 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll @@ -5,14 +5,12 @@ define void @test() { ; CHECK-LABEL: define void @test( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i2> @llvm.smin.v2i2(<2 x i2> zeroinitializer, <2 x i2> zeroinitializer) -; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i2> zeroinitializer, <2 x i2> [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i2> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i2> [[TMP2]], i32 1 -; CHECK-NEXT: [[ADD:%.*]] = zext i2 [[TMP3]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> zeroinitializer, <2 x i32> zeroinitializer) +; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], zeroinitializer +; CHECK-NEXT: [[ADD:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[ADD]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i2> [[TMP2]], i32 0 -; CHECK-NEXT: [[ADD45:%.*]] = zext i2 [[TMP5]] to i32 +; CHECK-NEXT: [[ADD45:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0 ; CHECK-NEXT: [[ADD152:%.*]] = or i32 [[ADD45]], [[ADD]] ; CHECK-NEXT: [[IDXPROM153:%.*]] = sext i32 [[ADD152]] to i64 ; CHECK-NEXT: [[ARRAYIDX154:%.*]] = getelementptr i8, ptr null, i64 [[IDXPROM153]] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll index df7312e3d2b5..e8b854b7cea6 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll @@ -13,13 +13,14 @@ define i32 @test(ptr noalias %in, ptr noalias %inn, ptr %out) { ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP3]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i8> [[TMP2]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i8> [[TMP5]], <4 x i8> [[TMP6]], <4 x i32> -; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i16> +; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i32> ; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> [[TMP10]], <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i16> -; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i16> [[TMP12]], [[TMP8]] -; CHECK-NEXT: [[TMP15:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP13]], i1 false) +; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i32> +; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i32> [[TMP12]], [[TMP8]] +; CHECK-NEXT: [[TMP14:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP13]], i1 true) +; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16> ; CHECK-NEXT: store <4 x i16> [[TMP15]], ptr [[OUT:%.*]], align 2 ; CHECK-NEXT: ret i32 undef ; -- GitLab From 5f7b133e320b4d856463c87da3167f70477ada63 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Sat, 6 Apr 2024 17:38:20 -0400 Subject: [PATCH 079/695] [libc][math] Update error bound for log1p to compensate for directional rounding. (#87893) --- libc/src/math/generic/log1p.cpp | 5 +++-- libc/test/src/math/log1p_test.cpp | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/libc/src/math/generic/log1p.cpp b/libc/src/math/generic/log1p.cpp index 83bd753cde5d..2b187080a057 100644 --- a/libc/src/math/generic/log1p.cpp +++ b/libc/src/math/generic/log1p.cpp @@ -28,8 +28,9 @@ using LIBC_NAMESPACE::operator""_u128; namespace { -// Extra errors from P is from using x^2 to reduce evaluation latency. -constexpr double P_ERR = 0x1.0p-50; +// Extra errors from P is from using x^2 to reduce evaluation latency and +// directional rounding. +constexpr double P_ERR = 0x1.0p-49; // log(2) with 128-bit precision generated by SageMath with: // def format_hex(value): diff --git a/libc/test/src/math/log1p_test.cpp b/libc/test/src/math/log1p_test.cpp index 5e461c91518b..47dfa406ec25 100644 --- a/libc/test/src/math/log1p_test.cpp +++ b/libc/test/src/math/log1p_test.cpp @@ -34,7 +34,7 @@ TEST_F(LlvmLibcLog1pTest, SpecialNumbers) { } TEST_F(LlvmLibcLog1pTest, TrickyInputs) { - constexpr int N = 41; + constexpr int N = 42; constexpr uint64_t INPUTS[N] = { 0x3ff0000000000000, // x = 1.0 0x4024000000000000, // x = 10.0 @@ -65,6 +65,7 @@ TEST_F(LlvmLibcLog1pTest, TrickyInputs) { 0x3c90c40cef04efb5, 0x449d2ccad399848e, 0x4aa12ccdffd9d2ec, 0x5656f070b92d36ce, 0x6db06dcb74f76bcc, 0x7f1954e72ffd4596, 0x5671e2f1628093e4, 0x73dac56e2bf1a951, 0x8001bc6879ea14c5, + 0x45ca5f497ec291df, // x = 0x1.a5f497ec291dfp+93 }; for (int i = 0; i < N; ++i) { double x = FPBits(INPUTS[i]).get_val(); -- GitLab From 7248c9feb9023335ae45265f59a8752da42fb4c4 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Sat, 6 Apr 2024 17:38:47 -0400 Subject: [PATCH 080/695] [libc] Adding FP_INT_* macro constants if missing in overlay mode. (#87880) --- libc/hdr/math_macros.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/libc/hdr/math_macros.h b/libc/hdr/math_macros.h index 864afd0e50e3..d13c5ff7647a 100644 --- a/libc/hdr/math_macros.h +++ b/libc/hdr/math_macros.h @@ -17,6 +17,27 @@ #include +// Some older math.h header does not have FP_INT_* constants yet. +#ifndef FP_INT_UPWARD +#define FP_INT_UPWARD 0 +#endif // FP_INT_UPWARD + +#ifndef FP_INT_DOWNWARD +#define FP_INT_DOWNWARD 1 +#endif // FP_INT_DOWNWARD + +#ifndef FP_INT_TOWARDZERO +#define FP_INT_TOWARDZERO 2 +#endif // FP_INT_TOWARDZERO + +#ifndef FP_INT_TONEARESTFROMZERO +#define FP_INT_TONEARESTFROMZERO 3 +#endif // FP_INT_TONEARESTFROMZERO + +#ifndef FP_INT_TONEAREST +#define FP_INT_TONEAREST 4 +#endif // FP_INT_TONEAREST + #endif // LLVM_LIBC_FULL_BUILD #endif // LLVM_LIBC_HDR_MATH_MACROS_H -- GitLab From 8e98435ae9eb34f04c4b1b97975f152c4ba63ba3 Mon Sep 17 00:00:00 2001 From: darkbuck Date: Sat, 6 Apr 2024 18:33:01 -0400 Subject: [PATCH 081/695] [GISel][Combine] Enhance combining on G_BUILD_VECTOR Reviewers: aemerson, arsenm Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/87831 --- .../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 6 ++-- .../GlobalISel/combine-extract-vec-elt.mir | 31 +++++++++++++++++++ 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 0b58d95bc8b2..40c5119ee7fb 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -2925,8 +2925,10 @@ bool CombinerHelper::matchCombineInsertVecElts( } return true; } - // If we didn't end in a G_IMPLICIT_DEF, bail out. - return TmpInst->getOpcode() == TargetOpcode::G_IMPLICIT_DEF; + // If we didn't end in a G_IMPLICIT_DEF and the source is not fully + // overwritten, bail out. + return TmpInst->getOpcode() == TargetOpcode::G_IMPLICIT_DEF || + all_of(MatchInfo, [](Register Reg) { return !!Reg; }); } void CombinerHelper::applyCombineInsertVecElts( diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir index c2a38e26676c..a65b43d33e49 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir @@ -220,6 +220,37 @@ body: | $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 +... +--- +# This test checks that this combine runs after the insertvec->build_vector +name: extract_from_insert2 +tracksRegLiveness: true +liveins: + - { reg: '$x0' } + - { reg: '$x1' } +frameInfo: + maxAlignment: 1 +body: | + bb.1: + liveins: $q0, $x0, $x1 + ; CHECK-LABEL: name: extract_from_insert2 + ; CHECK: liveins: $q0, $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 + ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 + ; CHECK-NEXT: %ins2:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) + ; CHECK-NEXT: $q0 = COPY %ins2(<2 x s64>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 + %arg0:_(<2 x s64>) = COPY $q0 + %arg1:_(s64) = COPY $x0 + %arg2:_(s64) = COPY $x1 + %zero:_(s32) = G_CONSTANT i32 0 + %one:_(s32) = G_CONSTANT i32 1 + %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %arg0, %arg1(s64), %zero(s32) + %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s32) + $q0 = COPY %ins2(<2 x s64>) + RET_ReallyLR implicit $q0 + ... --- name: extract_from_idx_negative -- GitLab From d5b48ceb74e3ef83487f7220c6e2130195c07cc6 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:32:47 -0500 Subject: [PATCH 082/695] [ValueTracking] Add tests for non-constant idx for fpclass of `insertelement`; NFC --- llvm/test/Transforms/Attributor/nofpclass.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll index 4df647cf3bb5..501c6d5de9d2 100644 --- a/llvm/test/Transforms/Attributor/nofpclass.ll +++ b/llvm/test/Transforms/Attributor/nofpclass.ll @@ -1513,6 +1513,25 @@ define <4 x float> @insertelement_constant_chain() { ret <4 x float> %ins.3 } +define <4 x float> @insertelement_non_constant_chain(i32 %idx) { +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK-LABEL: define <4 x float> @insertelement_non_constant_chain +; CHECK-SAME: (i32 [[IDX:%.*]]) #[[ATTR3]] { +; CHECK-NEXT: [[INS_0:%.*]] = insertelement <4 x float> poison, float 1.000000e+00, i32 0 +; CHECK-NEXT: [[INS_1:%.*]] = insertelement <4 x float> [[INS_0]], float 0.000000e+00, i32 1 +; CHECK-NEXT: [[INS_2:%.*]] = insertelement <4 x float> [[INS_1]], float -9.000000e+00, i32 2 +; CHECK-NEXT: [[INS_4:%.*]] = insertelement <4 x float> [[INS_2]], float 3.000000e+00, i32 3 +; CHECK-NEXT: [[INS_3:%.*]] = insertelement <4 x float> [[INS_2]], float 4.000000e+00, i32 [[IDX]] +; CHECK-NEXT: ret <4 x float> [[INS_3]] +; + %ins.0 = insertelement <4 x float> poison, float 1.0, i32 0 + %ins.1 = insertelement <4 x float> %ins.0, float 0.0, i32 1 + %ins.2 = insertelement <4 x float> %ins.1, float -9.0, i32 2 + %ins.3 = insertelement <4 x float> %ins.2, float 3.0, i32 3 + %ins.4 = insertelement <4 x float> %ins.2, float 4.0, i32 %idx + ret <4 x float> %ins.4 +} + define @insertelement_scalable_constant_chain() { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define @insertelement_scalable_constant_chain -- GitLab From e4db938a4ed017432af95bef84a388e2a8a2c232 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:26:58 -0500 Subject: [PATCH 083/695] [ValueTracking] Support non-constant idx for `computeKnownFPClass` of `insertelement` Its same logic as before, we just need to intersect what we know about the new Elt and the entire pre-existing Vec. Closes #87708 --- llvm/lib/Analysis/ValueTracking.cpp | 19 ++++++++++--------- llvm/test/Transforms/Attributor/nofpclass.ll | 4 ++-- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 5ad4da43bca7..0b0e2653f8df 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -5355,14 +5355,17 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, const Value *Vec = Op->getOperand(0); const Value *Elt = Op->getOperand(1); auto *CIdx = dyn_cast(Op->getOperand(2)); - // Early out if the index is non-constant or out-of-range. unsigned NumElts = DemandedElts.getBitWidth(); - if (!CIdx || CIdx->getValue().uge(NumElts)) - return; + APInt DemandedVecElts = DemandedElts; + bool NeedsElt = true; + // If we know the index we are inserting to, clear it from Vec check. + if (CIdx && CIdx->getValue().ult(NumElts)) { + DemandedVecElts.clearBit(CIdx->getZExtValue()); + NeedsElt = DemandedElts[CIdx->getZExtValue()]; + } - unsigned EltIdx = CIdx->getZExtValue(); // Do we demand the inserted element? - if (DemandedElts[EltIdx]) { + if (NeedsElt) { computeKnownFPClass(Elt, Known, InterestedClasses, Depth + 1, Q); // If we don't know any bits, early out. if (Known.isUnknown()) @@ -5371,10 +5374,8 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, Known.KnownFPClasses = fcNone; } - // We don't need the base vector element that has been inserted. - APInt DemandedVecElts = DemandedElts; - DemandedVecElts.clearBit(EltIdx); - if (!!DemandedVecElts) { + // Do we need anymore elements from Vec? + if (!DemandedVecElts.isZero()) { KnownFPClass Known2; computeKnownFPClass(Vec, DemandedVecElts, InterestedClasses, Known2, Depth + 1, Q); diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll index 501c6d5de9d2..4370cea3c285 100644 --- a/llvm/test/Transforms/Attributor/nofpclass.ll +++ b/llvm/test/Transforms/Attributor/nofpclass.ll @@ -1515,7 +1515,7 @@ define <4 x float> @insertelement_constant_chain() { define <4 x float> @insertelement_non_constant_chain(i32 %idx) { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) -; CHECK-LABEL: define <4 x float> @insertelement_non_constant_chain +; CHECK-LABEL: define nofpclass(nan inf nzero sub) <4 x float> @insertelement_non_constant_chain ; CHECK-SAME: (i32 [[IDX:%.*]]) #[[ATTR3]] { ; CHECK-NEXT: [[INS_0:%.*]] = insertelement <4 x float> poison, float 1.000000e+00, i32 0 ; CHECK-NEXT: [[INS_1:%.*]] = insertelement <4 x float> [[INS_0]], float 0.000000e+00, i32 1 @@ -1601,7 +1601,7 @@ define float @insertelement_extractelement_unknown(<4 x float> nofpclass(zero) % define <4 x float> @insertelement_index_oob_chain() { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) -; CHECK-LABEL: define <4 x float> @insertelement_index_oob_chain +; CHECK-LABEL: define nofpclass(nan ninf nzero sub norm) <4 x float> @insertelement_index_oob_chain ; CHECK-SAME: () #[[ATTR3]] { ; CHECK-NEXT: [[INSERT:%.*]] = insertelement <4 x float> zeroinitializer, float 0x7FF0000000000000, i32 4 ; CHECK-NEXT: ret <4 x float> [[INSERT]] -- GitLab From c459a366d3e07ae220b96fb1aa4f69375d4b72ba Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Sun, 7 Apr 2024 09:36:28 +0900 Subject: [PATCH 084/695] [mlir][Arith] `ValueBoundsOpInterface`: Support `arith.select` (#87870) This commit adds a `ValueBoundsOpInterface` implementation for `arith.select`. The implementation is almost identical to `scf.if` (#85895), but there is one special case: if the condition is a shaped value, the selection is applied element-wise and the result shape can be inferred from either operand. Note: This is a re-upload of #86383. --- .../Arith/IR/ValueBoundsOpInterfaceImpl.cpp | 70 +++++++++++++++++++ .../Arith/value-bounds-op-interface-impl.mlir | 31 ++++++++ 2 files changed, 101 insertions(+) diff --git a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp index 90895e381c74..f0d43808bc45 100644 --- a/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/Arith/IR/ValueBoundsOpInterfaceImpl.cpp @@ -75,6 +75,75 @@ struct MulIOpInterface } }; +struct SelectOpInterface + : public ValueBoundsOpInterface::ExternalModel { + + static void populateBounds(SelectOp selectOp, std::optional dim, + ValueBoundsConstraintSet &cstr) { + Value value = selectOp.getResult(); + Value condition = selectOp.getCondition(); + Value trueValue = selectOp.getTrueValue(); + Value falseValue = selectOp.getFalseValue(); + + if (isa(condition.getType())) { + // If the condition is a shaped type, the condition is applied + // element-wise. All three operands must have the same shape. + cstr.bound(value)[*dim] == cstr.getExpr(trueValue, dim); + cstr.bound(value)[*dim] == cstr.getExpr(falseValue, dim); + cstr.bound(value)[*dim] == cstr.getExpr(condition, dim); + return; + } + + // Populate constraints for the true/false values (and all values on the + // backward slice, as long as the current stop condition is not satisfied). + cstr.populateConstraints(trueValue, dim); + cstr.populateConstraints(falseValue, dim); + auto boundsBuilder = cstr.bound(value); + if (dim) + boundsBuilder[*dim]; + + // Compare yielded values. + // If trueValue <= falseValue: + // * result <= falseValue + // * result >= trueValue + if (cstr.compare(trueValue, dim, + ValueBoundsConstraintSet::ComparisonOperator::LE, + falseValue, dim)) { + if (dim) { + cstr.bound(value)[*dim] >= cstr.getExpr(trueValue, dim); + cstr.bound(value)[*dim] <= cstr.getExpr(falseValue, dim); + } else { + cstr.bound(value) >= trueValue; + cstr.bound(value) <= falseValue; + } + } + // If falseValue <= trueValue: + // * result <= trueValue + // * result >= falseValue + if (cstr.compare(falseValue, dim, + ValueBoundsConstraintSet::ComparisonOperator::LE, + trueValue, dim)) { + if (dim) { + cstr.bound(value)[*dim] >= cstr.getExpr(falseValue, dim); + cstr.bound(value)[*dim] <= cstr.getExpr(trueValue, dim); + } else { + cstr.bound(value) >= falseValue; + cstr.bound(value) <= trueValue; + } + } + } + + void populateBoundsForIndexValue(Operation *op, Value value, + ValueBoundsConstraintSet &cstr) const { + populateBounds(cast(op), /*dim=*/std::nullopt, cstr); + } + + void populateBoundsForShapedValueDim(Operation *op, Value value, int64_t dim, + ValueBoundsConstraintSet &cstr) const { + populateBounds(cast(op), dim, cstr); + } +}; } // namespace } // namespace arith } // namespace mlir @@ -86,5 +155,6 @@ void mlir::arith::registerValueBoundsOpInterfaceExternalModels( arith::ConstantOp::attachInterface(*ctx); arith::SubIOp::attachInterface(*ctx); arith::MulIOp::attachInterface(*ctx); + arith::SelectOp::attachInterface(*ctx); }); } diff --git a/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir b/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir index 83d5f1c9c9e8..8fb3ba1a1ecc 100644 --- a/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir +++ b/mlir/test/Dialect/Arith/value-bounds-op-interface-impl.mlir @@ -74,3 +74,34 @@ func.func @arith_const() -> index { %0 = "test.reify_bound"(%c5) : (index) -> (index) return %0 : index } + +// ----- + +// CHECK-LABEL: func @arith_select( +func.func @arith_select(%c: i1) -> (index, index) { + // CHECK: arith.constant 5 : index + %c5 = arith.constant 5 : index + // CHECK: arith.constant 9 : index + %c9 = arith.constant 9 : index + %r = arith.select %c, %c5, %c9 : index + // CHECK: %[[c5:.*]] = arith.constant 5 : index + // CHECK: %[[c10:.*]] = arith.constant 10 : index + %0 = "test.reify_bound"(%r) {type = "LB"} : (index) -> (index) + %1 = "test.reify_bound"(%r) {type = "UB"} : (index) -> (index) + // CHECK: return %[[c5]], %[[c10]] + return %0, %1 : index, index +} + +// ----- + +// CHECK-LABEL: func @arith_select_elementwise( +// CHECK-SAME: %[[a:.*]]: tensor, %[[b:.*]]: tensor, %[[c:.*]]: tensor) +func.func @arith_select_elementwise(%a: tensor, %b: tensor, %c: tensor) -> index { + %r = arith.select %c, %a, %b : tensor, tensor + // CHECK: %[[c0:.*]] = arith.constant 0 : index + // CHECK: %[[dim:.*]] = tensor.dim %[[a]], %[[c0]] + %0 = "test.reify_bound"(%r) {type = "EQ", dim = 0} + : (tensor) -> (index) + // CHECK: return %[[dim]] + return %0 : index +} -- GitLab From 8389b3bf60ef3fbd04c6efc5ff4d4605d10e7fc5 Mon Sep 17 00:00:00 2001 From: AtariDreams Date: Sat, 6 Apr 2024 20:43:13 -0400 Subject: [PATCH 085/695] [X86] Fix typo: QWORD alignment is greater than or equal to 8, not greater than 8 (#87819) Align(8) is QWORD aligned, but this was checking to see if alignment was greater than that, when it should have been checking for being greater than OR EQUAL to Align(8). This bug was introduced in https://github.com/llvm/llvm-project/commit/6a6af30d433d7 during the transition to the Align type. --- llvm/lib/Target/X86/X86SelectionDAGInfo.cpp | 4 ++-- llvm/test/CodeGen/X86/memset-minsize.ll | 13 +++++++++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp index 7c630a2b0da0..0bff1884933d 100644 --- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp +++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp @@ -80,13 +80,13 @@ SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset( uint64_t Val = ValC->getZExtValue() & 255; // If the value is a constant, then we can potentially use larger sets. - if (Alignment > Align(2)) { + if (Alignment >= Align(4)) { // DWORD aligned AVT = MVT::i32; ValReg = X86::EAX; Val = (Val << 8) | Val; Val = (Val << 16) | Val; - if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned + if (Subtarget.is64Bit() && Alignment >= Align(8)) { // QWORD aligned AVT = MVT::i64; ValReg = X86::RAX; Val = (Val << 32) | Val; diff --git a/llvm/test/CodeGen/X86/memset-minsize.ll b/llvm/test/CodeGen/X86/memset-minsize.ll index 76d2928db3a9..cc0f2156262b 100644 --- a/llvm/test/CodeGen/X86/memset-minsize.ll +++ b/llvm/test/CodeGen/X86/memset-minsize.ll @@ -136,4 +136,17 @@ entry: ret void } +define void @small_memset_to_rep_stos_64(ptr %ptr) minsize nounwind { +; CHECK-LABEL: small_memset_to_rep_stos_64: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushq $16 +; CHECK-NEXT: popq %rcx +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: rep;stosq %rax, %es:(%rdi) +; CHECK-NEXT: retq +entry: + call void @llvm.memset.p0.i64(ptr align 8 %ptr, i8 0, i64 128, i1 false) + ret void +} + declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) -- GitLab From d08a76d1ac1ba6b376faa908ccbaaabc999dfbc5 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Sun, 7 Apr 2024 09:25:47 +0900 Subject: [PATCH 086/695] Fix warnings discovered by #87348 [-Wunused-but-set-variable] --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 1 + clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp | 1 + clang/lib/Sema/SemaOverload.cpp | 1 + llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 2 +- 4 files changed, 4 insertions(+), 1 deletion(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 46182809810b..50e86d947364 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -2511,6 +2511,7 @@ unsigned ByteCodeExprGen::allocateLocalPrimitive(DeclTy &&Src, dyn_cast_if_present(Src.dyn_cast())) { assert(!P.getGlobal(VD)); assert(!Locals.contains(VD)); + (void)VD; } // FIXME: There are cases where Src.is() is wrong, e.g. diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 70ac0764476f..1bfa7ebcfd50 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -850,6 +850,7 @@ void Environment::setValue(const Expr &E, Value &Val) { if (auto *RecordVal = dyn_cast(&Val)) { assert(isOriginalRecordConstructor(CanonE) || &RecordVal->getLoc() == &getResultObjectLocation(CanonE)); + (void)RecordVal; } assert(CanonE.isPRValue()); diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 0c913bc700f4..3808af37ff54 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -6354,6 +6354,7 @@ Sema::EvaluateConvertedConstantExpression(Expr *E, QualType T, APValue &Value, // by this point. assert(CE->getResultStorageKind() != ConstantResultStorageKind::None && "ConstantExpr has no value associated with it"); + (void)CE; } else { E = ConstantExpr::Create(Context, Result.get(), Value); } diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index 915cd81661f0..5396038d8b92 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -784,7 +784,7 @@ BasicBlock *llvm::SplitEdge(BasicBlock *BB, BasicBlock *Succ, DominatorTree *DT, // If the successor only has a single pred, split the top of the successor // block. assert(SP == BB && "CFG broken"); - SP = nullptr; + (void)SP; return SplitBlock(Succ, &Succ->front(), DT, LI, MSSAU, BBName, /*Before=*/true); } -- GitLab From ba5dad35fbefec456eb9da0f7c5a0ad983a268b2 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Sun, 7 Apr 2024 10:56:41 +0900 Subject: [PATCH 087/695] [Bazel] Enable LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG (for #87585) --- .../llvm-project-overlay/llvm/include/llvm/Config/config.h | 3 +++ utils/bazel/llvm_configs/config.h.cmake | 3 +++ 2 files changed, 6 insertions(+) diff --git a/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h b/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h index b4fb2373d571..e9385f45c5e5 100644 --- a/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h +++ b/utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h @@ -306,6 +306,9 @@ /* Whether tools show host and target info when invoked with --version */ #define LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO 1 +/* Whether tools show optional build config flags when invoked with --version */ +#define LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG 1 + /* Define if libxml2 is supported on this platform. */ /* #undef LLVM_ENABLE_LIBXML2 */ diff --git a/utils/bazel/llvm_configs/config.h.cmake b/utils/bazel/llvm_configs/config.h.cmake index fc1f9bf342f8..977c182e9d2b 100644 --- a/utils/bazel/llvm_configs/config.h.cmake +++ b/utils/bazel/llvm_configs/config.h.cmake @@ -290,6 +290,9 @@ /* Whether tools show host and target info when invoked with --version */ #cmakedefine01 LLVM_VERSION_PRINTER_SHOW_HOST_TARGET_INFO +/* Whether tools show optional build config flags when invoked with --version */ +#cmakedefine01 LLVM_VERSION_PRINTER_SHOW_BUILD_CONFIG + /* Define if libxml2 is supported on this platform. */ #cmakedefine LLVM_ENABLE_LIBXML2 ${LLVM_ENABLE_LIBXML2} -- GitLab From bc8726b16bacc1790cee9a27302f556f5ca7ba39 Mon Sep 17 00:00:00 2001 From: Jianjian Guan Date: Sun, 7 Apr 2024 10:41:47 +0800 Subject: [PATCH 088/695] [RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318) vfmv, vfmerge should support bfloat vector when we have both Zvfbfmin and Zfbfmin, this patch tries to support vfmv first. --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 5 + .../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 5 +- .../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 5 + llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll | 124 +++++++++++++++++- 4 files changed, 135 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index af20b11514ca..cf9a31c23a06 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -761,6 +761,11 @@ class GetVTypePredicates { true : [HasVInstructions]); } +class GetVTypeScalarPredicates { + list Predicates = !cond(!eq(vti.Scalar, bf16) : [HasStdExtZfbfmin], + true : []); +} + class VPseudoUSLoadNoMask : Pseudo<(outs RetClass:$rd), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td index b4c6ba7e9723..da761ae85670 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -1454,8 +1454,9 @@ foreach fvtiToFWti = AllWidenableFloatVectors in { // Vector Splats //===----------------------------------------------------------------------===// -foreach fvti = AllFloatVectors in { - let Predicates = GetVTypePredicates.Predicates in +foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in { + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypeScalarPredicates.Predicates) in def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl undef, fvti.ScalarRegClass:$rs1, srcvalue)), (!cast("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) (fvti.Vector (IMPLICIT_DEF)), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 73d52d5ecafb..b721dcd98988 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -2599,7 +2599,12 @@ foreach fvti = AllFloatVectors in { fvti.RegClass:$merge, fvti.RegClass:$rs2, (fvti.Scalar fvti.ScalarRegClass:$rs1), (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; + } +} +foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in { + let Predicates = !listconcat(GetVTypePredicates.Predicates, + GetVTypeScalarPredicates.Predicates) in { // 13.16. Vector Floating-Point Move Instruction // If we're splatting fpimm0, use vmv.v.x vd, x0. def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll index 237ef11d154b..c00433eba548 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmv.v.f.nxv1f16( @@ -528,3 +528,123 @@ entry: ret %a } + +declare @llvm.riscv.vfmv.v.f.nxv1bf16( + , + bfloat, + iXLen); + +define @intrinsic_vfmv.v.f_f_nxv1bf16(bfloat %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1bf16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vfmv.v.f.nxv1bf16( + undef, + bfloat %0, + iXLen %1) + + ret %a +} + +declare @llvm.riscv.vfmv.v.f.nxv2bf16( + , + bfloat, + iXLen); + +define @intrinsic_vfmv.v.f_f_nxv2bf16(bfloat %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2bf16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vfmv.v.f.nxv2bf16( + undef, + bfloat %0, + iXLen %1) + + ret %a +} + +declare @llvm.riscv.vfmv.v.f.nxv4bf16( + , + bfloat, + iXLen); + +define @intrinsic_vfmv.v.f_f_nxv4bf16(bfloat %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4bf16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vfmv.v.f.nxv4bf16( + undef, + bfloat %0, + iXLen %1) + + ret %a +} + +declare @llvm.riscv.vfmv.v.f.nxv8bf16( + , + bfloat, + iXLen); + +define @intrinsic_vfmv.v.f_f_nxv8bf16(bfloat %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8bf16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vfmv.v.f.nxv8bf16( + undef, + bfloat %0, + iXLen %1) + + ret %a +} + +declare @llvm.riscv.vfmv.v.f.nxv16bf16( + , + bfloat, + iXLen); + +define @intrinsic_vfmv.v.f_f_nxv16bf16(bfloat %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16bf16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vfmv.v.f.nxv16bf16( + undef, + bfloat %0, + iXLen %1) + + ret %a +} + +declare @llvm.riscv.vfmv.v.f.nxv32bf16( + , + bfloat, + iXLen); + +define @intrinsic_vfmv.v.f_f_nxv32bf16(bfloat %0, iXLen %1) nounwind { +; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32bf16: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma +; CHECK-NEXT: vfmv.v.f v8, fa0 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vfmv.v.f.nxv32bf16( + undef, + bfloat %0, + iXLen %1) + + ret %a +} -- GitLab From ccc02563f4d620d4d29a1cbd2c463871cc54745b Mon Sep 17 00:00:00 2001 From: Aviad Cohen Date: Sun, 7 Apr 2024 08:23:16 +0300 Subject: [PATCH 089/695] [mlir][linalg]: Fixed possible memory leak in cloneToCollapsedOp (#87595) * Direct call to `clone` function leads to memory leak. Instead, we should use `RewriterBase` clone function instead. --- mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp | 5 +++-- mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp | 6 ++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp b/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp index 9453502a253f..373e9cfc3ce7 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp @@ -1497,9 +1497,10 @@ LinalgOp cloneToCollapsedOp(RewriterBase &rewriter, LinalgOp origOp, SmallVector resultTypes; collapseOperandsAndResults(origOp, collapsingInfo, rewriter, inputOperands, outputOperands, resultTypes); - return cast(clone( + + return clone( rewriter, origOp, resultTypes, - llvm::to_vector(llvm::concat(inputOperands, outputOperands)))); + llvm::to_vector(llvm::concat(inputOperands, outputOperands))); } /// Collapse a `GenericOp` diff --git a/mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp b/mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp index 383ef1cea53f..adde8a66d835 100644 --- a/mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp +++ b/mlir/lib/Dialect/Utils/StructuredOpsUtils.cpp @@ -199,8 +199,10 @@ Operation *mlir::clone(OpBuilder &b, Operation *op, TypeRange newResultTypes, IRMapping bvm; OperationState state(op->getLoc(), op->getName(), newOperands, newResultTypes, op->getAttrs()); - for (Region &r : op->getRegions()) - r.cloneInto(state.addRegion(), bvm); + for (Region &r : op->getRegions()) { + Region *newRegion = state.addRegion(); + b.cloneRegionBefore(r, *newRegion, newRegion->begin(), bvm); + } return b.create(state); } -- GitLab From a2c4b7c8e2740a83f141dcf06cf50359588190b9 Mon Sep 17 00:00:00 2001 From: Fabian Mora Date: Sun, 7 Apr 2024 02:46:21 -0400 Subject: [PATCH 090/695] [mlir] Add `convertInstruction` and `getSupportedInstructions` to `LLVMImportInterface` (#86799) This patch adds the `convertInstruction` and `getSupportedInstructions` to `LLVMImportInterface`, allowing any non-LLVM dialect to specify how to import LLVM IR instructions and overriding the default import of LLVM instructions. --- .../mlir/Target/LLVMIR/LLVMImportInterface.h | 69 ++++++++++- mlir/lib/Target/LLVMIR/ModuleImport.cpp | 10 +- mlir/test/Target/LLVMIR/Import/test.ll | 11 ++ mlir/test/lib/Dialect/Test/CMakeLists.txt | 18 +++ .../Test/TestFromLLVMIRTranslation.cpp | 111 ++++++++++++++++++ mlir/tools/mlir-translate/mlir-translate.cpp | 2 + 6 files changed, 213 insertions(+), 8 deletions(-) create mode 100644 mlir/test/Target/LLVMIR/Import/test.ll create mode 100644 mlir/test/lib/Dialect/Test/TestFromLLVMIRTranslation.cpp diff --git a/mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h b/mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h index 9f8da83ae9c2..86bcd580c1b4 100644 --- a/mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h +++ b/mlir/include/mlir/Target/LLVMIR/LLVMImportInterface.h @@ -52,6 +52,15 @@ public: return failure(); } + /// Hook for derived dialect interfaces to implement the import of + /// instructions into MLIR. + virtual LogicalResult + convertInstruction(OpBuilder &builder, llvm::Instruction *inst, + ArrayRef llvmOperands, + LLVM::ModuleImport &moduleImport) const { + return failure(); + } + /// Hook for derived dialect interfaces to implement the import of metadata /// into MLIR. Attaches the converted metadata kind and node to the provided /// operation. @@ -66,6 +75,14 @@ public: /// returns the list of supported intrinsic identifiers. virtual ArrayRef getSupportedIntrinsics() const { return {}; } + /// Hook for derived dialect interfaces to publish the supported instructions. + /// As every LLVM IR instruction has a unique integer identifier, the function + /// returns the list of supported instruction identifiers. These identifiers + /// will then be used to match LLVM instructions to the appropriate import + /// interface and `convertInstruction` method. It is an error to have multiple + /// interfaces overriding the same instruction. + virtual ArrayRef getSupportedInstructions() const { return {}; } + /// Hook for derived dialect interfaces to publish the supported metadata /// kinds. As every metadata kind has a unique integer identifier, the /// function returns the list of supported metadata identifiers. @@ -88,21 +105,40 @@ public: LogicalResult initializeImport() { for (const LLVMImportDialectInterface &iface : *this) { // Verify the supported intrinsics have not been mapped before. - const auto *it = + const auto *intrinsicIt = llvm::find_if(iface.getSupportedIntrinsics(), [&](unsigned id) { return intrinsicToDialect.count(id); }); - if (it != iface.getSupportedIntrinsics().end()) { + if (intrinsicIt != iface.getSupportedIntrinsics().end()) { + return emitError( + UnknownLoc::get(iface.getContext()), + llvm::formatv( + "expected unique conversion for intrinsic ({0}), but " + "got conflicting {1} and {2} conversions", + *intrinsicIt, iface.getDialect()->getNamespace(), + intrinsicToDialect.lookup(*intrinsicIt)->getNamespace())); + } + const auto *instructionIt = + llvm::find_if(iface.getSupportedInstructions(), [&](unsigned id) { + return instructionToDialect.count(id); + }); + if (instructionIt != iface.getSupportedInstructions().end()) { return emitError( UnknownLoc::get(iface.getContext()), - llvm::formatv("expected unique conversion for intrinsic ({0}), but " - "got conflicting {1} and {2} conversions", - *it, iface.getDialect()->getNamespace(), - intrinsicToDialect.lookup(*it)->getNamespace())); + llvm::formatv( + "expected unique conversion for instruction ({0}), but " + "got conflicting {1} and {2} conversions", + *intrinsicIt, iface.getDialect()->getNamespace(), + instructionToDialect.lookup(*intrinsicIt) + ->getDialect() + ->getNamespace())); } // Add a mapping for all supported intrinsic identifiers. for (unsigned id : iface.getSupportedIntrinsics()) intrinsicToDialect[id] = iface.getDialect(); + // Add a mapping for all supported instruction identifiers. + for (unsigned id : iface.getSupportedInstructions()) + instructionToDialect[id] = &iface; // Add a mapping for all supported metadata kinds. for (unsigned kind : iface.getSupportedMetadata()) metadataToDialect[kind].push_back(iface.getDialect()); @@ -132,6 +168,26 @@ public: return intrinsicToDialect.count(id); } + /// Converts the LLVM instruction to an MLIR operation if a conversion exists. + /// Returns failure otherwise. + LogicalResult convertInstruction(OpBuilder &builder, llvm::Instruction *inst, + ArrayRef llvmOperands, + LLVM::ModuleImport &moduleImport) const { + // Lookup the dialect interface for the given instruction. + const LLVMImportDialectInterface *iface = + instructionToDialect.lookup(inst->getOpcode()); + if (!iface) + return failure(); + + return iface->convertInstruction(builder, inst, llvmOperands, moduleImport); + } + + /// Returns true if the given LLVM IR instruction is convertible to an MLIR + /// operation. + bool isConvertibleInstruction(unsigned id) { + return instructionToDialect.count(id); + } + /// Attaches the given LLVM metadata to the imported operation if a conversion /// to one or more MLIR dialect attributes exists and succeeds. Returns /// success if at least one of the conversions is successful and failure if @@ -166,6 +222,7 @@ public: private: DenseMap intrinsicToDialect; + DenseMap instructionToDialect; DenseMap> metadataToDialect; }; diff --git a/mlir/lib/Target/LLVMIR/ModuleImport.cpp b/mlir/lib/Target/LLVMIR/ModuleImport.cpp index 6e70d52fa760..af998b99d511 100644 --- a/mlir/lib/Target/LLVMIR/ModuleImport.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleImport.cpp @@ -123,12 +123,18 @@ static SmallVector getPositionFromIndices(ArrayRef indices) { /// access to the private module import methods. static LogicalResult convertInstructionImpl(OpBuilder &odsBuilder, llvm::Instruction *inst, - ModuleImport &moduleImport) { + ModuleImport &moduleImport, + LLVMImportInterface &iface) { // Copy the operands to an LLVM operands array reference for conversion. SmallVector operands(inst->operands()); ArrayRef llvmOperands(operands); // Convert all instructions that provide an MLIR builder. + if (iface.isConvertibleInstruction(inst->getOpcode())) + return iface.convertInstruction(odsBuilder, inst, llvmOperands, + moduleImport); + // TODO: Implement the `convertInstruction` hooks in the + // `LLVMDialectLLVMIRImportInterface` and move the following include there. #include "mlir/Dialect/LLVMIR/LLVMOpFromLLVMIRConversions.inc" return failure(); } @@ -1596,7 +1602,7 @@ LogicalResult ModuleImport::convertInstruction(llvm::Instruction *inst) { } // Convert all instructions that have an mlirBuilder. - if (succeeded(convertInstructionImpl(builder, inst, *this))) + if (succeeded(convertInstructionImpl(builder, inst, *this, iface))) return success(); return emitError(loc) << "unhandled instruction: " << diag(*inst); diff --git a/mlir/test/Target/LLVMIR/Import/test.ll b/mlir/test/Target/LLVMIR/Import/test.ll new file mode 100644 index 000000000000..a3165d602010 --- /dev/null +++ b/mlir/test/Target/LLVMIR/Import/test.ll @@ -0,0 +1,11 @@ +; RUN: mlir-translate -test-import-llvmir %s | FileCheck %s + +; CHECK-LABEL: @custom_load +; CHECK-SAME: %[[PTR:[[:alnum:]]+]] +define double @custom_load(ptr %ptr) { + ; CHECK: %[[LOAD:[0-9]+]] = llvm.load %[[PTR]] : !llvm.ptr -> f64 + ; CHECK: %[[TEST:[0-9]+]] = "test.same_operand_element_type"(%[[LOAD]], %[[LOAD]]) : (f64, f64) -> f64 + %1 = load double, ptr %ptr + ; CHECK: llvm.return %[[TEST]] : f64 + ret double %1 +} diff --git a/mlir/test/lib/Dialect/Test/CMakeLists.txt b/mlir/test/lib/Dialect/Test/CMakeLists.txt index b82b1631eead..47ddcf652474 100644 --- a/mlir/test/lib/Dialect/Test/CMakeLists.txt +++ b/mlir/test/lib/Dialect/Test/CMakeLists.txt @@ -2,6 +2,7 @@ set(LLVM_OPTIONAL_SOURCES TestDialect.cpp TestPatterns.cpp TestTraits.cpp + TestFromLLVMIRTranslation.cpp TestToLLVMIRTranslation.cpp ) @@ -86,6 +87,23 @@ add_mlir_library(MLIRTestDialect MLIRTransforms ) +add_mlir_translation_library(MLIRTestFromLLVMIRTranslation + TestFromLLVMIRTranslation.cpp + + EXCLUDE_FROM_LIBMLIR + + LINK_COMPONENTS + Core + + LINK_LIBS PUBLIC + MLIRIR + MLIRLLVMDialect + MLIRTestDialect + MLIRSupport + MLIRTargetLLVMIRImport + MLIRLLVMIRToLLVMTranslation +) + add_mlir_translation_library(MLIRTestToLLVMIRTranslation TestToLLVMIRTranslation.cpp diff --git a/mlir/test/lib/Dialect/Test/TestFromLLVMIRTranslation.cpp b/mlir/test/lib/Dialect/Test/TestFromLLVMIRTranslation.cpp new file mode 100644 index 000000000000..3673d62bea2c --- /dev/null +++ b/mlir/test/lib/Dialect/Test/TestFromLLVMIRTranslation.cpp @@ -0,0 +1,111 @@ +//===- TestFromLLVMIRTranslation.cpp - Import Test dialect from LLVM IR ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements a translation between LLVM IR and the MLIR Test dialect. +// +//===----------------------------------------------------------------------===// + +#include "TestDialect.h" +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/IR/Builders.h" +#include "mlir/IR/BuiltinAttributes.h" +#include "mlir/IR/BuiltinOps.h" +#include "mlir/Support/LLVM.h" +#include "mlir/Target/LLVMIR/Dialect/LLVMIR/LLVMIRToLLVMTranslation.h" +#include "mlir/Target/LLVMIR/Import.h" +#include "mlir/Target/LLVMIR/ModuleImport.h" +#include "mlir/Tools/mlir-translate/Translation.h" + +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Verifier.h" +#include "llvm/IRReader/IRReader.h" +#include "llvm/Support/SourceMgr.h" + +using namespace mlir; +using namespace test; + +static ArrayRef getSupportedInstructionsImpl() { + static unsigned instructions[] = {llvm::Instruction::Load}; + return instructions; +} + +static LogicalResult convertLoad(OpBuilder &builder, llvm::Instruction *inst, + ArrayRef llvmOperands, + LLVM::ModuleImport &moduleImport) { + FailureOr addr = moduleImport.convertValue(llvmOperands[0]); + if (failed(addr)) + return failure(); + // Create the LoadOp + Value loadOp = builder.create( + moduleImport.translateLoc(inst->getDebugLoc()), + moduleImport.convertType(inst->getType()), *addr); + moduleImport.mapValue(inst) = builder.create( + loadOp.getLoc(), loadOp.getType(), loadOp, loadOp); + return success(); +} + +namespace { +class TestDialectLLVMImportDialectInterface + : public LLVMImportDialectInterface { +public: + using LLVMImportDialectInterface::LLVMImportDialectInterface; + + LogicalResult + convertInstruction(OpBuilder &builder, llvm::Instruction *inst, + ArrayRef llvmOperands, + LLVM::ModuleImport &moduleImport) const override { + switch (inst->getOpcode()) { + case llvm::Instruction::Load: + return convertLoad(builder, inst, llvmOperands, moduleImport); + default: + break; + } + return failure(); + } + + ArrayRef getSupportedInstructions() const override { + return getSupportedInstructionsImpl(); + } +}; +} // namespace + +namespace mlir { +void registerTestFromLLVMIR() { + TranslateToMLIRRegistration registration( + "test-import-llvmir", "test dialect from LLVM IR", + [](llvm::SourceMgr &sourceMgr, + MLIRContext *context) -> OwningOpRef { + llvm::SMDiagnostic err; + llvm::LLVMContext llvmContext; + std::unique_ptr llvmModule = + llvm::parseIR(*sourceMgr.getMemoryBuffer(sourceMgr.getMainFileID()), + err, llvmContext); + if (!llvmModule) { + std::string errStr; + llvm::raw_string_ostream errStream(errStr); + err.print(/*ProgName=*/"", errStream); + emitError(UnknownLoc::get(context)) << errStream.str(); + return {}; + } + if (llvm::verifyModule(*llvmModule, &llvm::errs())) + return nullptr; + + return translateLLVMIRToModule(std::move(llvmModule), context, false); + }, + [](DialectRegistry ®istry) { + registry.insert(); + registry.insert(); + registerLLVMDialectImport(registry); + registry.addExtension( + +[](MLIRContext *ctx, test::TestDialect *dialect) { + dialect->addInterfaces(); + }); + }); +} +} // namespace mlir diff --git a/mlir/tools/mlir-translate/mlir-translate.cpp b/mlir/tools/mlir-translate/mlir-translate.cpp index 4f9661c058c2..309def888a07 100644 --- a/mlir/tools/mlir-translate/mlir-translate.cpp +++ b/mlir/tools/mlir-translate/mlir-translate.cpp @@ -23,6 +23,7 @@ void registerTestRoundtripSPIRV(); void registerTestRoundtripDebugSPIRV(); #ifdef MLIR_INCLUDE_TESTS void registerTestToLLVMIR(); +void registerTestFromLLVMIR(); #endif } // namespace mlir @@ -31,6 +32,7 @@ static void registerTestTranslations() { registerTestRoundtripDebugSPIRV(); #ifdef MLIR_INCLUDE_TESTS registerTestToLLVMIR(); + registerTestFromLLVMIR(); #endif } -- GitLab From 869797daca38941e0af3bcd8ae5300bcebf7b1a9 Mon Sep 17 00:00:00 2001 From: David Green Date: Sun, 7 Apr 2024 07:54:22 +0100 Subject: [PATCH 091/695] [VectorCombine] Add a debug message for foldShuffleOfCastop. NFC This optimization, much like the existing foldShuffleOfBinops can cause a lot of regressions. Add a quick debug message to make the costs are more obvious. --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 3738220b4f81..61e3f0ff55f7 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1485,6 +1485,10 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { TargetTransformInfo::SK_PermuteTwoSrc, CastSrcTy, Mask, CostKind); NewCost += TTI.getCastInstrCost(Opcode, ShuffleDstTy, NewShuffleDstTy, TTI::CastContextHint::None, CostKind); + + LLVM_DEBUG(dbgs() << "Found a shuffle feeding two casts: " << I + << "\n OldCost: " << OldCost << " vs NewCost: " << NewCost + << "\n"); if (NewCost > OldCost) return false; -- GitLab From da5a86b53e7d6e7ff7407b16c2c869894493ee99 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 7 Apr 2024 00:54:10 -0700 Subject: [PATCH 092/695] [IR] Fix typo in trunc nuw semantics; NFC (#87285) --- llvm/docs/LangRef.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index b3f41eb2ea09..a3722ecdf0c5 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -11448,7 +11448,7 @@ and converts the remaining bits to ``ty2``. Since the source size must be larger than the destination size, ``trunc`` cannot be a *no-op cast*. It will always truncate bits. -If the ``nuw`` keyword is present, and any of the truncated bits are zero, +If the ``nuw`` keyword is present, and any of the truncated bits are non-zero, the result is a :ref:`poison value `. If the ``nsw`` keyword is present, and any of the truncated bits are not the same as the top bit of the truncation result, the result is a :ref:`poison value `. -- GitLab From 8f01d3ff44779105966404d17e2d1b7b487ddb2e Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Thu, 4 Apr 2024 21:19:17 +0200 Subject: [PATCH 093/695] [libc++][doc] Updates format status page. --- libcxx/docs/Status/FormatIssues.csv | 4 ++++ libcxx/docs/Status/FormatPaper.csv | 27 ++++----------------------- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/libcxx/docs/Status/FormatIssues.csv b/libcxx/docs/Status/FormatIssues.csv index b7acc76b8c11..7da77def92da 100644 --- a/libcxx/docs/Status/FormatIssues.csv +++ b/libcxx/docs/Status/FormatIssues.csv @@ -20,6 +20,10 @@ Number,Name,Standard,Assignee,Status,First released version "`P2905R2 `__","Runtime format strings","C++26 DR","Mark de Wever","|Complete|",18.0 "`P2918R2 `__","Runtime format strings II","C++26","Mark de Wever","|Complete|",18.0 "`P2909R4 `__","Fix formatting of code units as integers (Dude, where’s my ``char``?)","C++26 DR","Mark de Wever","|Complete|",18.0 +"`P3107R5 `__","Permit an efficient implementation of ``std::print``","C++26 DR","Mark de Wever","|In Progress|","" +"`P3142R0 `__","Printing Blank Lines with ``println``","C++26 DR","Hristo Hristov","|Complete|",19.0 +"`P2845R8 `__","Formatting of ``std::filesystem::path``","C++26","Mark de Wever","","" + `P1361 `_,"Integration of chrono with text formatting","C++20",Mark de Wever,|In Progress|, `P2372 `__,"Fixing locale handling in chrono formatters","C++20",Mark de Wever,|In Progress|, "`P2419R2 `__","Clarify handling of encodings in localized formatting of chrono types","C++23", diff --git a/libcxx/docs/Status/FormatPaper.csv b/libcxx/docs/Status/FormatPaper.csv index 82da54284c73..e9d407e79e25 100644 --- a/libcxx/docs/Status/FormatPaper.csv +++ b/libcxx/docs/Status/FormatPaper.csv @@ -2,12 +2,12 @@ Section,Description,Dependencies,Assignee,Status,First released version `P1361 `__ `P2372 `__,"Formatting chrono" `[time.syn] `_,"Formatter ``chrono::duration``",,Mark de Wever,|Complete|,16.0 `[time.syn] `_,"Formatter ``chrono::sys_time``",,Mark de Wever,|Complete|,17.0 -`[time.syn] `_,"Formatter ``chrono::utc_time``",A ```` implementation,Not assigned,,, -`[time.syn] `_,"Formatter ``chrono::tai_time``",A ```` implementation,Not assigned,,, -`[time.syn] `_,"Formatter ``chrono::gps_time``",A ```` implementation,Not assigned,,, +`[time.syn] `_,"Formatter ``chrono::utc_time``",A ```` implementation,Mark de Wever,,, +`[time.syn] `_,"Formatter ``chrono::tai_time``",A ```` implementation,Mark de Wever,,, +`[time.syn] `_,"Formatter ``chrono::gps_time``",A ```` implementation,Mark de Wever,,, `[time.syn] `_,"Formatter ``chrono::file_time``",,Mark de Wever,|Complete|,17.0 `[time.syn] `_,"Formatter ``chrono::local_time``",,Mark de Wever,|Complete|,17.0 -`[time.syn] `_,"Formatter ``chrono::local-time-format-t``",A ```` implementation,Not assigned,,, +`[time.syn] `_,"Formatter ``chrono::local-time-format-t``",A ```` implementation,Mark de Wever,,, `[time.syn] `_,"Formatter ``chrono::day``",,Mark de Wever,|Complete|,16.0 `[time.syn] `_,"Formatter ``chrono::month``",,Mark de Wever,|Complete|,16.0 `[time.syn] `_,"Formatter ``chrono::year``",,Mark de Wever,|Complete|,16.0 @@ -28,25 +28,6 @@ Section,Description,Dependencies,Assignee,Status,First released version `[time.syn] `_,"Formatter ``chrono::local_info``",A ```` implementation,Mark de Wever,, `[time.syn] `_,"Formatter ``chrono::zoned_time``",A ```` implementation,Mark de Wever,, -`P2286R8 `__,"Formatting ranges" -`[format.syn] `_,"Concept ``formattable``",,Mark de Wever,|Complete|,16.0 -`[format.string.std] `_,"std-format-spec ``type`` debug",,Mark de Wever,|Complete|,16.0 -`[format.range] `_,"Formatting for ranges: sequences",,Mark de Wever,|Complete|,16.0 -`[format.range.fmtmap] `_,"Formatting for ranges: map",,Mark de Wever,|Complete|,16.0 -`[format.range.fmtset] `_,"Formatting for ranges: set",,Mark de Wever,|Complete|,16.0 -`[format.range] `_,"Formatting for ranges: container adaptors",,Mark de Wever,|Complete|,16.0 -`[format.range] `_,"Formatting for ranges: ``pair`` and ``tuple``",,Mark de Wever,|Complete|,16.0 -`[format.range] `_,"Formatting for ranges: ``vector``",,Mark de Wever,|Complete|,16.0 - -"`P2585R0 `__","Improving default container formatting" -`[format.range.fmtstr] `_,"Formatting for ranges: strings",,Mark de Wever,|Complete|,17.0 -`[format.range.fmtstr] `_,"Formatting for ranges: debug_strings",,Mark de Wever,|Complete|,17.0 - "`P2693R1 `__","Formatting ``thread::id`` and ``stacktrace``" `[thread.thread.id] `_,"Formatting ``thread::id``",,Mark de Wever,|Complete|,17.0 `[stacktrace.format] `_,"Formatting ``stacktrace``",A ```` implementation,Mark de Wever,, - -"`P2093R14 `__","Formatted output" -`[print.fun] `__,"Output to ``stdout``",,Mark de Wever,|Complete|, 17.0 -`[print.fun] `__,"Output to ``FILE*``",,Mark de Wever,|Complete|, 17.0 -`[ostream.formatted.print] `__,"Output to ``ostream``",,Mark de Wever,|Complete|, 18.0 -- GitLab From 7a4e89761a13bfad27a2614ecea5e8698f50336c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Sun, 7 Apr 2024 13:28:29 +0200 Subject: [PATCH 094/695] [clang-tidy] Add fix-its to `readability-avoid-return-with-void-value` check (#81420) --- .../AvoidReturnWithVoidValueCheck.cpp | 44 +++-- .../BracesAroundStatementsCheck.cpp | 157 +++------------- .../readability/BracesAroundStatementsCheck.h | 2 +- .../utils/BracesAroundStatement.cpp | 168 ++++++++++++++++++ .../clang-tidy/utils/BracesAroundStatement.h | 75 ++++++++ .../clang-tidy/utils/CMakeLists.txt | 1 + clang-tools-extra/docs/ReleaseNotes.rst | 4 + .../avoid-return-with-void-value.cpp | 51 +++++- 8 files changed, 353 insertions(+), 149 deletions(-) create mode 100644 clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp create mode 100644 clang-tools-extra/clang-tidy/utils/BracesAroundStatement.h diff --git a/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp b/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp index e3400f614fa5..48bca41f4a3b 100644 --- a/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp @@ -7,19 +7,18 @@ //===----------------------------------------------------------------------===// #include "AvoidReturnWithVoidValueCheck.h" -#include "clang/AST/Stmt.h" -#include "clang/ASTMatchers/ASTMatchFinder.h" -#include "clang/ASTMatchers/ASTMatchers.h" +#include "../utils/BracesAroundStatement.h" +#include "../utils/LexerUtils.h" using namespace clang::ast_matchers; namespace clang::tidy::readability { -static constexpr auto IgnoreMacrosName = "IgnoreMacros"; -static constexpr auto IgnoreMacrosDefault = true; +static constexpr char IgnoreMacrosName[] = "IgnoreMacros"; +static const bool IgnoreMacrosDefault = true; -static constexpr auto StrictModeName = "StrictMode"; -static constexpr auto StrictModeDefault = true; +static constexpr char StrictModeName[] = "StrictMode"; +static const bool StrictModeDefault = true; AvoidReturnWithVoidValueCheck::AvoidReturnWithVoidValueCheck( StringRef Name, ClangTidyContext *Context) @@ -32,7 +31,10 @@ void AvoidReturnWithVoidValueCheck::registerMatchers(MatchFinder *Finder) { Finder->addMatcher( returnStmt( hasReturnValue(allOf(hasType(voidType()), unless(initListExpr()))), - optionally(hasParent(compoundStmt().bind("compound_parent")))) + optionally(hasParent( + compoundStmt( + optionally(hasParent(functionDecl().bind("function_parent")))) + .bind("compound_parent")))) .bind("void_return"), this); } @@ -42,10 +44,30 @@ void AvoidReturnWithVoidValueCheck::check( const auto *VoidReturn = Result.Nodes.getNodeAs("void_return"); if (IgnoreMacros && VoidReturn->getBeginLoc().isMacroID()) return; - if (!StrictMode && !Result.Nodes.getNodeAs("compound_parent")) + const auto *SurroundingBlock = + Result.Nodes.getNodeAs("compound_parent"); + if (!StrictMode && !SurroundingBlock) return; - diag(VoidReturn->getBeginLoc(), "return statement within a void function " - "should not have a specified return value"); + DiagnosticBuilder Diag = diag(VoidReturn->getBeginLoc(), + "return statement within a void function " + "should not have a specified return value"); + const SourceLocation SemicolonPos = utils::lexer::findNextTerminator( + VoidReturn->getEndLoc(), *Result.SourceManager, getLangOpts()); + if (SemicolonPos.isInvalid()) + return; + if (!SurroundingBlock) { + const auto BraceInsertionHints = utils::getBraceInsertionsHints( + VoidReturn, getLangOpts(), *Result.SourceManager, + VoidReturn->getBeginLoc()); + if (BraceInsertionHints) + Diag << BraceInsertionHints.openingBraceFixIt() + << BraceInsertionHints.closingBraceFixIt(); + } + Diag << FixItHint::CreateRemoval(VoidReturn->getReturnLoc()); + if (!Result.Nodes.getNodeAs("function_parent") || + SurroundingBlock->body_back() != VoidReturn) + Diag << FixItHint::CreateInsertion(SemicolonPos.getLocWithOffset(1), + " return;", true); } void AvoidReturnWithVoidValueCheck::storeOptions( diff --git a/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp b/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp index 81ca33cbbdfb..85bd9c1e4f9a 100644 --- a/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "BracesAroundStatementsCheck.h" +#include "../utils/BracesAroundStatement.h" #include "../utils/LexerUtils.h" #include "clang/AST/ASTContext.h" #include "clang/ASTMatchers/ASTMatchers.h" @@ -17,12 +18,10 @@ using namespace clang::ast_matchers; namespace clang::tidy::readability { static tok::TokenKind getTokenKind(SourceLocation Loc, const SourceManager &SM, - const ASTContext *Context) { + const LangOptions &LangOpts) { Token Tok; - SourceLocation Beginning = - Lexer::GetBeginningOfToken(Loc, SM, Context->getLangOpts()); - const bool Invalid = - Lexer::getRawToken(Beginning, Tok, SM, Context->getLangOpts()); + SourceLocation Beginning = Lexer::GetBeginningOfToken(Loc, SM, LangOpts); + const bool Invalid = Lexer::getRawToken(Beginning, Tok, SM, LangOpts); assert(!Invalid && "Expected a valid token."); if (Invalid) @@ -33,64 +32,21 @@ static tok::TokenKind getTokenKind(SourceLocation Loc, const SourceManager &SM, static SourceLocation forwardSkipWhitespaceAndComments(SourceLocation Loc, const SourceManager &SM, - const ASTContext *Context) { + const LangOptions &LangOpts) { assert(Loc.isValid()); for (;;) { while (isWhitespace(*SM.getCharacterData(Loc))) Loc = Loc.getLocWithOffset(1); - tok::TokenKind TokKind = getTokenKind(Loc, SM, Context); + tok::TokenKind TokKind = getTokenKind(Loc, SM, LangOpts); if (TokKind != tok::comment) return Loc; // Fast-forward current token. - Loc = Lexer::getLocForEndOfToken(Loc, 0, SM, Context->getLangOpts()); + Loc = Lexer::getLocForEndOfToken(Loc, 0, SM, LangOpts); } } -static SourceLocation findEndLocation(const Stmt &S, const SourceManager &SM, - const ASTContext *Context) { - SourceLocation Loc = - utils::lexer::getUnifiedEndLoc(S, SM, Context->getLangOpts()); - if (!Loc.isValid()) - return Loc; - - // Start searching right after S. - Loc = Loc.getLocWithOffset(1); - - for (;;) { - assert(Loc.isValid()); - while (isHorizontalWhitespace(*SM.getCharacterData(Loc))) { - Loc = Loc.getLocWithOffset(1); - } - - if (isVerticalWhitespace(*SM.getCharacterData(Loc))) { - // EOL, insert brace before. - break; - } - tok::TokenKind TokKind = getTokenKind(Loc, SM, Context); - if (TokKind != tok::comment) { - // Non-comment token, insert brace before. - break; - } - - SourceLocation TokEndLoc = - Lexer::getLocForEndOfToken(Loc, 0, SM, Context->getLangOpts()); - SourceRange TokRange(Loc, TokEndLoc); - StringRef Comment = Lexer::getSourceText( - CharSourceRange::getTokenRange(TokRange), SM, Context->getLangOpts()); - if (Comment.starts_with("/*") && Comment.contains('\n')) { - // Multi-line block comment, insert brace before. - break; - } - // else: Trailing comment, insert brace after the newline. - - // Fast-forward current token. - Loc = TokEndLoc; - } - return Loc; -} - BracesAroundStatementsCheck::BracesAroundStatementsCheck( StringRef Name, ClangTidyContext *Context) : ClangTidyCheck(Name, Context), @@ -124,7 +80,7 @@ void BracesAroundStatementsCheck::check( } else if (const auto *S = Result.Nodes.getNodeAs("do")) { checkStmt(Result, S->getBody(), S->getDoLoc(), S->getWhileLoc()); } else if (const auto *S = Result.Nodes.getNodeAs("while")) { - SourceLocation StartLoc = findRParenLoc(S, SM, Context); + SourceLocation StartLoc = findRParenLoc(S, SM, Context->getLangOpts()); if (StartLoc.isInvalid()) return; checkStmt(Result, S->getBody(), StartLoc); @@ -133,7 +89,7 @@ void BracesAroundStatementsCheck::check( if (S->isConsteval()) return; - SourceLocation StartLoc = findRParenLoc(S, SM, Context); + SourceLocation StartLoc = findRParenLoc(S, SM, Context->getLangOpts()); if (StartLoc.isInvalid()) return; if (ForceBracesStmts.erase(S)) @@ -156,7 +112,7 @@ template SourceLocation BracesAroundStatementsCheck::findRParenLoc(const IfOrWhileStmt *S, const SourceManager &SM, - const ASTContext *Context) { + const LangOptions &LangOpts) { // Skip macros. if (S->getBeginLoc().isMacroID()) return {}; @@ -170,14 +126,14 @@ BracesAroundStatementsCheck::findRParenLoc(const IfOrWhileStmt *S, } SourceLocation PastCondEndLoc = - Lexer::getLocForEndOfToken(CondEndLoc, 0, SM, Context->getLangOpts()); + Lexer::getLocForEndOfToken(CondEndLoc, 0, SM, LangOpts); if (PastCondEndLoc.isInvalid()) return {}; SourceLocation RParenLoc = - forwardSkipWhitespaceAndComments(PastCondEndLoc, SM, Context); + forwardSkipWhitespaceAndComments(PastCondEndLoc, SM, LangOpts); if (RParenLoc.isInvalid()) return {}; - tok::TokenKind TokKind = getTokenKind(RParenLoc, SM, Context); + tok::TokenKind TokKind = getTokenKind(RParenLoc, SM, LangOpts); if (TokKind != tok::r_paren) return {}; return RParenLoc; @@ -188,86 +144,23 @@ BracesAroundStatementsCheck::findRParenLoc(const IfOrWhileStmt *S, bool BracesAroundStatementsCheck::checkStmt( const MatchFinder::MatchResult &Result, const Stmt *S, SourceLocation StartLoc, SourceLocation EndLocHint) { - while (const auto *AS = dyn_cast(S)) S = AS->getSubStmt(); - const SourceManager &SM = *Result.SourceManager; - const ASTContext *Context = Result.Context; - - // 1) If there's a corresponding "else" or "while", the check inserts "} " - // right before that token. - // 2) If there's a multi-line block comment starting on the same line after - // the location we're inserting the closing brace at, or there's a non-comment - // token, the check inserts "\n}" right before that token. - // 3) Otherwise the check finds the end of line (possibly after some block or - // line comments) and inserts "\n}" right before that EOL. - if (!S || isa(S)) { - // Already inside braces. - return false; - } - - // When TreeTransform, Stmt in constexpr IfStmt will be transform to NullStmt. - // This NullStmt can be detected according to beginning token. - const SourceLocation StmtBeginLoc = S->getBeginLoc(); - if (isa(S) && StmtBeginLoc.isValid() && - getTokenKind(StmtBeginLoc, SM, Context) == tok::l_brace) - return false; - - if (StartLoc.isInvalid()) - return false; - - // Convert StartLoc to file location, if it's on the same macro expansion - // level as the start of the statement. We also need file locations for - // Lexer::getLocForEndOfToken working properly. - StartLoc = Lexer::makeFileCharRange( - CharSourceRange::getCharRange(StartLoc, S->getBeginLoc()), SM, - Context->getLangOpts()) - .getBegin(); - if (StartLoc.isInvalid()) - return false; - StartLoc = - Lexer::getLocForEndOfToken(StartLoc, 0, SM, Context->getLangOpts()); - - // StartLoc points at the location of the opening brace to be inserted. - SourceLocation EndLoc; - std::string ClosingInsertion; - if (EndLocHint.isValid()) { - EndLoc = EndLocHint; - ClosingInsertion = "} "; - } else { - EndLoc = findEndLocation(*S, SM, Context); - ClosingInsertion = "\n}"; - } - - assert(StartLoc.isValid()); - - // Don't require braces for statements spanning less than certain number of - // lines. - if (ShortStatementLines && !ForceBracesStmts.erase(S)) { - unsigned StartLine = SM.getSpellingLineNumber(StartLoc); - unsigned EndLine = SM.getSpellingLineNumber(EndLoc); - if (EndLine - StartLine < ShortStatementLines) + const auto BraceInsertionHints = utils::getBraceInsertionsHints( + S, Result.Context->getLangOpts(), *Result.SourceManager, StartLoc, + EndLocHint); + if (BraceInsertionHints) { + if (ShortStatementLines && !ForceBracesStmts.erase(S) && + BraceInsertionHints.resultingCompoundLineExtent(*Result.SourceManager) < + ShortStatementLines) return false; + auto Diag = diag(BraceInsertionHints.DiagnosticPos, + "statement should be inside braces"); + if (BraceInsertionHints.offersFixIts()) + Diag << BraceInsertionHints.openingBraceFixIt() + << BraceInsertionHints.closingBraceFixIt(); } - - auto Diag = diag(StartLoc, "statement should be inside braces"); - - // Change only if StartLoc and EndLoc are on the same macro expansion level. - // This will also catch invalid EndLoc. - // Example: LLVM_DEBUG( for(...) do_something() ); - // In this case fix-it cannot be provided as the semicolon which is not - // visible here is part of the macro. Adding braces here would require adding - // another semicolon. - if (Lexer::makeFileCharRange( - CharSourceRange::getTokenRange(SourceRange( - SM.getSpellingLoc(StartLoc), SM.getSpellingLoc(EndLoc))), - SM, Context->getLangOpts()) - .isInvalid()) - return false; - - Diag << FixItHint::CreateInsertion(StartLoc, " {") - << FixItHint::CreateInsertion(EndLoc, ClosingInsertion); return true; } diff --git a/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.h b/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.h index 249aa1aaaa91..4cd37a7b2dd6 100644 --- a/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.h +++ b/clang-tools-extra/clang-tidy/readability/BracesAroundStatementsCheck.h @@ -52,7 +52,7 @@ private: SourceLocation EndLocHint = SourceLocation()); template SourceLocation findRParenLoc(const IfOrWhileStmt *S, const SourceManager &SM, - const ASTContext *Context); + const LangOptions &LangOpts); std::optional getCheckTraversalKind() const override { return TK_IgnoreUnlessSpelledInSource; } diff --git a/clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp b/clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp new file mode 100644 index 000000000000..2a3b7bed08c1 --- /dev/null +++ b/clang-tools-extra/clang-tidy/utils/BracesAroundStatement.cpp @@ -0,0 +1,168 @@ +//===--- BracesAroundStatement.cpp - clang-tidy -------- ------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file provides utilities to put braces around a statement. +/// +//===----------------------------------------------------------------------===// + +#include "BracesAroundStatement.h" +#include "../utils/LexerUtils.h" +#include "LexerUtils.h" +#include "clang/AST/ASTContext.h" +#include "clang/Basic/CharInfo.h" +#include "clang/Basic/LangOptions.h" +#include "clang/Lex/Lexer.h" + +namespace clang::tidy::utils { + +BraceInsertionHints::operator bool() const { return DiagnosticPos.isValid(); } + +bool BraceInsertionHints::offersFixIts() const { + return OpeningBracePos.isValid() && ClosingBracePos.isValid(); +} + +unsigned BraceInsertionHints::resultingCompoundLineExtent( + const SourceManager &SourceMgr) const { + return SourceMgr.getSpellingLineNumber(ClosingBracePos) - + SourceMgr.getSpellingLineNumber(OpeningBracePos); +} + +FixItHint BraceInsertionHints::openingBraceFixIt() const { + return OpeningBracePos.isValid() + ? FixItHint::CreateInsertion(OpeningBracePos, " {") + : FixItHint(); +} + +FixItHint BraceInsertionHints::closingBraceFixIt() const { + return ClosingBracePos.isValid() + ? FixItHint::CreateInsertion(ClosingBracePos, ClosingBrace) + : FixItHint(); +} + +static tok::TokenKind getTokenKind(SourceLocation Loc, const SourceManager &SM, + const LangOptions &LangOpts) { + Token Tok; + SourceLocation Beginning = Lexer::GetBeginningOfToken(Loc, SM, LangOpts); + const bool Invalid = Lexer::getRawToken(Beginning, Tok, SM, LangOpts); + assert(!Invalid && "Expected a valid token."); + + if (Invalid) + return tok::NUM_TOKENS; + + return Tok.getKind(); +} + +static SourceLocation findEndLocation(const Stmt &S, const SourceManager &SM, + const LangOptions &LangOpts) { + SourceLocation Loc = lexer::getUnifiedEndLoc(S, SM, LangOpts); + if (!Loc.isValid()) + return Loc; + + // Start searching right after S. + Loc = Loc.getLocWithOffset(1); + + for (;;) { + assert(Loc.isValid()); + while (isHorizontalWhitespace(*SM.getCharacterData(Loc))) { + Loc = Loc.getLocWithOffset(1); + } + + if (isVerticalWhitespace(*SM.getCharacterData(Loc))) { + // EOL, insert brace before. + break; + } + tok::TokenKind TokKind = getTokenKind(Loc, SM, LangOpts); + if (TokKind != tok::comment) { + // Non-comment token, insert brace before. + break; + } + + SourceLocation TokEndLoc = Lexer::getLocForEndOfToken(Loc, 0, SM, LangOpts); + SourceRange TokRange(Loc, TokEndLoc); + StringRef Comment = Lexer::getSourceText( + CharSourceRange::getTokenRange(TokRange), SM, LangOpts); + if (Comment.starts_with("/*") && Comment.contains('\n')) { + // Multi-line block comment, insert brace before. + break; + } + // else: Trailing comment, insert brace after the newline. + + // Fast-forward current token. + Loc = TokEndLoc; + } + return Loc; +} + +BraceInsertionHints getBraceInsertionsHints(const Stmt *const S, + const LangOptions &LangOpts, + const SourceManager &SM, + SourceLocation StartLoc, + SourceLocation EndLocHint) { + // 1) If there's a corresponding "else" or "while", the check inserts "} " + // right before that token. + // 2) If there's a multi-line block comment starting on the same line after + // the location we're inserting the closing brace at, or there's a non-comment + // token, the check inserts "\n}" right before that token. + // 3) Otherwise the check finds the end of line (possibly after some block or + // line comments) and inserts "\n}" right before that EOL. + if (!S || isa(S)) { + // Already inside braces. + return {}; + } + + // When TreeTransform, Stmt in constexpr IfStmt will be transform to NullStmt. + // This NullStmt can be detected according to beginning token. + const SourceLocation StmtBeginLoc = S->getBeginLoc(); + if (isa(S) && StmtBeginLoc.isValid() && + getTokenKind(StmtBeginLoc, SM, LangOpts) == tok::l_brace) + return {}; + + if (StartLoc.isInvalid()) + return {}; + + // Convert StartLoc to file location, if it's on the same macro expansion + // level as the start of the statement. We also need file locations for + // Lexer::getLocForEndOfToken working properly. + StartLoc = Lexer::makeFileCharRange( + CharSourceRange::getCharRange(StartLoc, S->getBeginLoc()), SM, + LangOpts) + .getBegin(); + if (StartLoc.isInvalid()) + return {}; + StartLoc = Lexer::getLocForEndOfToken(StartLoc, 0, SM, LangOpts); + + // StartLoc points at the location of the opening brace to be inserted. + SourceLocation EndLoc; + std::string ClosingInsertion; + if (EndLocHint.isValid()) { + EndLoc = EndLocHint; + ClosingInsertion = "} "; + } else { + EndLoc = findEndLocation(*S, SM, LangOpts); + ClosingInsertion = "\n}"; + } + + assert(StartLoc.isValid()); + + // Change only if StartLoc and EndLoc are on the same macro expansion level. + // This will also catch invalid EndLoc. + // Example: LLVM_DEBUG( for(...) do_something() ); + // In this case fix-it cannot be provided as the semicolon which is not + // visible here is part of the macro. Adding braces here would require adding + // another semicolon. + if (Lexer::makeFileCharRange( + CharSourceRange::getTokenRange(SourceRange( + SM.getSpellingLoc(StartLoc), SM.getSpellingLoc(EndLoc))), + SM, LangOpts) + .isInvalid()) + return {StartLoc}; + return {StartLoc, EndLoc, ClosingInsertion}; +} + +} // namespace clang::tidy::utils diff --git a/clang-tools-extra/clang-tidy/utils/BracesAroundStatement.h b/clang-tools-extra/clang-tidy/utils/BracesAroundStatement.h new file mode 100644 index 000000000000..cb1c06c7aa1a --- /dev/null +++ b/clang-tools-extra/clang-tidy/utils/BracesAroundStatement.h @@ -0,0 +1,75 @@ +//===--- BracesAroundStatement.h - clang-tidy ------- -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file provides utilities to put braces around a statement. +/// +//===----------------------------------------------------------------------===// + +#include "clang/AST/Stmt.h" +#include "clang/Basic/Diagnostic.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Basic/SourceManager.h" + +namespace clang::tidy::utils { + +/// A provider of fix-it hints to insert opening and closing braces. An instance +/// of this type is the result of calling `getBraceInsertionsHints` below. +struct BraceInsertionHints { + /// The position of a potential diagnostic. It coincides with the position of + /// the opening brace to insert, but can also just be the place to show a + /// diagnostic in case braces cannot be inserted automatically. + SourceLocation DiagnosticPos; + + /// Constructor for a no-hint. + BraceInsertionHints() = default; + + /// Constructor for a valid hint that cannot insert braces automatically. + BraceInsertionHints(SourceLocation DiagnosticPos) + : DiagnosticPos(DiagnosticPos) {} + + /// Constructor for a hint offering fix-its for brace insertion. Both + /// positions must be valid. + BraceInsertionHints(SourceLocation OpeningBracePos, + SourceLocation ClosingBracePos, std::string ClosingBrace) + : DiagnosticPos(OpeningBracePos), OpeningBracePos(OpeningBracePos), + ClosingBracePos(ClosingBracePos), ClosingBrace(ClosingBrace) { + assert(offersFixIts()); + } + + /// Indicates whether the hint provides at least the position of a diagnostic. + operator bool() const; + + /// Indicates whether the hint provides fix-its to insert braces. + bool offersFixIts() const; + + /// The number of lines between the inserted opening brace and its closing + /// counterpart. + unsigned resultingCompoundLineExtent(const SourceManager &SourceMgr) const; + + /// Fix-it to insert an opening brace. + FixItHint openingBraceFixIt() const; + + /// Fix-it to insert a closing brace. + FixItHint closingBraceFixIt() const; + +private: + SourceLocation OpeningBracePos; + SourceLocation ClosingBracePos; + std::string ClosingBrace; +}; + +/// Create fix-it hints for braces that wrap the given statement when applied. +/// The algorithm computing them respects comment before and after the statement +/// and adds line breaks before the braces accordingly. +BraceInsertionHints +getBraceInsertionsHints(const Stmt *const S, const LangOptions &LangOpts, + const SourceManager &SM, SourceLocation StartLoc, + SourceLocation EndLocHint = SourceLocation()); + +} // namespace clang::tidy::utils diff --git a/clang-tools-extra/clang-tidy/utils/CMakeLists.txt b/clang-tools-extra/clang-tidy/utils/CMakeLists.txt index f0160fa9df74..9cff7d475425 100644 --- a/clang-tools-extra/clang-tidy/utils/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/utils/CMakeLists.txt @@ -6,6 +6,7 @@ set(LLVM_LINK_COMPONENTS add_clang_library(clangTidyUtils Aliasing.cpp ASTUtils.cpp + BracesAroundStatement.cpp DeclRefExprUtils.cpp DesignatedInitializers.cpp ExceptionAnalyzer.cpp diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 34bad7e62463..2babb1406b97 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -255,6 +255,10 @@ Changes in existing checks analyzed, se the check now handles the common patterns `const auto e = (*vector_ptr)[i]` and `const auto e = vector_ptr->at(i);`. +- Improved :doc:`readability-avoid-return-with-void-value + ` check by adding + fix-its. + - Improved :doc:`readability-duplicate-include ` check by excluding include directives that form the filename using macro. diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-return-with-void-value.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-return-with-void-value.cpp index f00407c99ce5..7c948dba3e8f 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-return-with-void-value.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/avoid-return-with-void-value.cpp @@ -12,23 +12,30 @@ void f2() { return f1(); // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: f1(); } void f3(bool b) { if (b) return f1(); // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: if (b) { f1(); return; + // CHECK-NEXT: } return f2(); // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: f2(); + // CHECK-FIXES-LENIENT: f2(); } template T f4() {} void f5() { - return f4(); - // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] - // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + { return f4(); } + // CHECK-MESSAGES: :[[@LINE-1]]:7: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:7: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: { f4(); return; } + // CHECK-FIXES-LENIENT: { f4(); return; } } void f6() { return; } @@ -41,6 +48,8 @@ void f9() { return (void)f7(); // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: (void)f7(); + // CHECK-FIXES-LENIENT: (void)f7(); } #define RETURN_VOID return (void)1 @@ -50,12 +59,12 @@ void f10() { // CHECK-MESSAGES-INCLUDE-MACROS: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] } -template +template struct C { C(A) {} }; -template +template C f11() { return {}; } using VOID = void; @@ -66,4 +75,36 @@ VOID f13() { return f12(); // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: f12(); return; + // CHECK-FIXES-LENIENT: f12(); return; + (void)1; +} + +void f14() { + return /* comment */ f1() /* comment */ ; + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: /* comment */ f1() /* comment */ ; return; + // CHECK-FIXES-LENIENT: /* comment */ f1() /* comment */ ; return; + (void)1; +} + +void f15() { + return/*comment*/f1()/*comment*/;//comment + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-MESSAGES-LENIENT: :[[@LINE-2]]:5: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: /*comment*/f1()/*comment*/; return;//comment + // CHECK-FIXES-LENIENT: /*comment*/f1()/*comment*/; return;//comment + (void)1; +} + +void f16(bool b) { + if (b) return f1(); + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: if (b) { f1(); return; + // CHECK-NEXT: } + else return f2(); + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: return statement within a void function should not have a specified return value [readability-avoid-return-with-void-value] + // CHECK-FIXES: else { f2(); return; + // CHECK-NEXT: } } -- GitLab From 298f8f73e1d861f8b839477c6edc941ca994922d Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Sun, 7 Apr 2024 17:37:56 +0400 Subject: [PATCH 095/695] [clang][NFC] Remove "Sema" prefix from Sema-related functions (#87914) @AaronBallman once noted that this prefix is a historical accident, and shouldn't be there. I agree. --- clang/include/clang/Sema/Sema.h | 109 ++-- clang/lib/Sema/SemaChecking.cpp | 832 ++++++++++++++-------------- clang/lib/Sema/SemaExpr.cpp | 2 +- clang/lib/Sema/SemaExprCXX.cpp | 5 +- clang/lib/Sema/TreeTransform.h | 5 +- clang/utils/TableGen/MveEmitter.cpp | 7 +- 6 files changed, 473 insertions(+), 487 deletions(-) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index f49bc724c96c..56d66a4486e0 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -1831,10 +1831,10 @@ public: bool IsVariadic, FormatStringInfo *FSI); // Used by C++ template instantiation. - ExprResult SemaBuiltinShuffleVector(CallExpr *TheCall); - ExprResult SemaConvertVectorExpr(Expr *E, TypeSourceInfo *TInfo, - SourceLocation BuiltinLoc, - SourceLocation RParenLoc); + ExprResult BuiltinShuffleVector(CallExpr *TheCall); + ExprResult ConvertVectorExpr(Expr *E, TypeSourceInfo *TInfo, + SourceLocation BuiltinLoc, + SourceLocation RParenLoc); enum FormatStringType { FST_Scanf, @@ -2056,62 +2056,59 @@ private: bool CheckNVPTXBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, CallExpr *TheCall); - bool SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall); - bool SemaBuiltinVAStartARMMicrosoft(CallExpr *Call); - bool SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID); - bool SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, - unsigned BuiltinID); - bool SemaBuiltinComplex(CallExpr *TheCall); - bool SemaBuiltinVSX(CallExpr *TheCall); - bool SemaBuiltinOSLogFormat(CallExpr *TheCall); - bool SemaValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum); - - bool SemaBuiltinPrefetch(CallExpr *TheCall); - bool SemaBuiltinAllocaWithAlign(CallExpr *TheCall); - bool SemaBuiltinArithmeticFence(CallExpr *TheCall); - bool SemaBuiltinAssume(CallExpr *TheCall); - bool SemaBuiltinAssumeAligned(CallExpr *TheCall); - bool SemaBuiltinLongjmp(CallExpr *TheCall); - bool SemaBuiltinSetjmp(CallExpr *TheCall); - ExprResult SemaBuiltinAtomicOverloaded(ExprResult TheCallResult); - ExprResult SemaBuiltinNontemporalOverloaded(ExprResult TheCallResult); - ExprResult SemaAtomicOpsOverloaded(ExprResult TheCallResult, - AtomicExpr::AtomicOp Op); - bool SemaBuiltinConstantArg(CallExpr *TheCall, int ArgNum, - llvm::APSInt &Result); - bool SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, int Low, - int High, bool RangeIsError = true); - bool SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum, - unsigned Multiple); - bool SemaBuiltinConstantArgPower2(CallExpr *TheCall, int ArgNum); - bool SemaBuiltinConstantArgShiftedByte(CallExpr *TheCall, int ArgNum, - unsigned ArgBits); - bool SemaBuiltinConstantArgShiftedByteOrXXFF(CallExpr *TheCall, int ArgNum, - unsigned ArgBits); - bool SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, - int ArgNum, unsigned ExpectedFieldNum, - bool AllowName); - bool SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall); - bool SemaBuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID, - const char *TypeDesc); + bool BuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall); + bool BuiltinVAStartARMMicrosoft(CallExpr *Call); + bool BuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID); + bool BuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, + unsigned BuiltinID); + bool BuiltinComplex(CallExpr *TheCall); + bool BuiltinVSX(CallExpr *TheCall); + bool BuiltinOSLogFormat(CallExpr *TheCall); + bool ValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum); + + bool BuiltinPrefetch(CallExpr *TheCall); + bool BuiltinAllocaWithAlign(CallExpr *TheCall); + bool BuiltinArithmeticFence(CallExpr *TheCall); + bool BuiltinAssume(CallExpr *TheCall); + bool BuiltinAssumeAligned(CallExpr *TheCall); + bool BuiltinLongjmp(CallExpr *TheCall); + bool BuiltinSetjmp(CallExpr *TheCall); + ExprResult BuiltinAtomicOverloaded(ExprResult TheCallResult); + ExprResult BuiltinNontemporalOverloaded(ExprResult TheCallResult); + ExprResult AtomicOpsOverloaded(ExprResult TheCallResult, + AtomicExpr::AtomicOp Op); + bool BuiltinConstantArg(CallExpr *TheCall, int ArgNum, llvm::APSInt &Result); + bool BuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, int Low, int High, + bool RangeIsError = true); + bool BuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum, + unsigned Multiple); + bool BuiltinConstantArgPower2(CallExpr *TheCall, int ArgNum); + bool BuiltinConstantArgShiftedByte(CallExpr *TheCall, int ArgNum, + unsigned ArgBits); + bool BuiltinConstantArgShiftedByteOrXXFF(CallExpr *TheCall, int ArgNum, + unsigned ArgBits); + bool BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, int ArgNum, + unsigned ExpectedFieldNum, bool AllowName); + bool BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall); + bool BuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID, + const char *TypeDesc); bool CheckPPCMMAType(QualType Type, SourceLocation TypeLoc); - bool SemaBuiltinElementwiseMath(CallExpr *TheCall); - bool SemaBuiltinElementwiseTernaryMath(CallExpr *TheCall, - bool CheckForFloatArgs = true); + bool BuiltinElementwiseMath(CallExpr *TheCall); + bool BuiltinElementwiseTernaryMath(CallExpr *TheCall, + bool CheckForFloatArgs = true); bool PrepareBuiltinElementwiseMathOneArgCall(CallExpr *TheCall); bool PrepareBuiltinReduceMathOneArgCall(CallExpr *TheCall); - bool SemaBuiltinNonDeterministicValue(CallExpr *TheCall); + bool BuiltinNonDeterministicValue(CallExpr *TheCall); // Matrix builtin handling. - ExprResult SemaBuiltinMatrixTranspose(CallExpr *TheCall, - ExprResult CallResult); - ExprResult SemaBuiltinMatrixColumnMajorLoad(CallExpr *TheCall, - ExprResult CallResult); - ExprResult SemaBuiltinMatrixColumnMajorStore(CallExpr *TheCall, - ExprResult CallResult); + ExprResult BuiltinMatrixTranspose(CallExpr *TheCall, ExprResult CallResult); + ExprResult BuiltinMatrixColumnMajorLoad(CallExpr *TheCall, + ExprResult CallResult); + ExprResult BuiltinMatrixColumnMajorStore(CallExpr *TheCall, + ExprResult CallResult); // WebAssembly builtin handling. bool BuiltinWasmRefNullExtern(CallExpr *TheCall); @@ -6986,8 +6983,8 @@ public: SourceLocation ClosingBraceLoc); private: - ExprResult SemaBuiltinOperatorNewDeleteOverloaded(ExprResult TheCallResult, - bool IsDelete); + ExprResult BuiltinOperatorNewDeleteOverloaded(ExprResult TheCallResult, + bool IsDelete); void AnalyzeDeleteExprMismatch(const CXXDeleteExpr *DE); void AnalyzeDeleteExprMismatch(FieldDecl *Field, SourceLocation DeleteLoc, @@ -13160,8 +13157,8 @@ public: bool CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); - bool SemaBuiltinVectorMath(CallExpr *TheCall, QualType &Res); - bool SemaBuiltinVectorToScalarMath(CallExpr *TheCall); + bool BuiltinVectorMath(CallExpr *TheCall, QualType &Res); + bool BuiltinVectorToScalarMath(CallExpr *TheCall); ///@} diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 4c30cc3160de..f4746647b965 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -188,7 +188,7 @@ static bool convertArgumentToType(Sema &S, Expr *&Value, QualType Ty) { /// Check that the first argument to __builtin_annotation is an integer /// and the second argument is a non-wide string literal. -static bool SemaBuiltinAnnotation(Sema &S, CallExpr *TheCall) { +static bool BuiltinAnnotation(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 2)) return true; @@ -214,7 +214,7 @@ static bool SemaBuiltinAnnotation(Sema &S, CallExpr *TheCall) { return false; } -static bool SemaBuiltinMSVCAnnotation(Sema &S, CallExpr *TheCall) { +static bool BuiltinMSVCAnnotation(Sema &S, CallExpr *TheCall) { // We need at least one argument. if (TheCall->getNumArgs() < 1) { S.Diag(TheCall->getEndLoc(), diag::err_typecheck_call_too_few_args_at_least) @@ -238,7 +238,7 @@ static bool SemaBuiltinMSVCAnnotation(Sema &S, CallExpr *TheCall) { /// Check that the argument to __builtin_addressof is a glvalue, and set the /// result type to the corresponding pointer type. -static bool SemaBuiltinAddressof(Sema &S, CallExpr *TheCall) { +static bool BuiltinAddressof(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 1)) return true; @@ -253,7 +253,7 @@ static bool SemaBuiltinAddressof(Sema &S, CallExpr *TheCall) { } /// Check that the argument to __builtin_function_start is a function. -static bool SemaBuiltinFunctionStart(Sema &S, CallExpr *TheCall) { +static bool BuiltinFunctionStart(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 1)) return true; @@ -277,7 +277,7 @@ static bool SemaBuiltinFunctionStart(Sema &S, CallExpr *TheCall) { /// Check the number of arguments and set the result type to /// the argument type. -static bool SemaBuiltinPreserveAI(Sema &S, CallExpr *TheCall) { +static bool BuiltinPreserveAI(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 1)) return true; @@ -288,7 +288,7 @@ static bool SemaBuiltinPreserveAI(Sema &S, CallExpr *TheCall) { /// Check that the value argument for __builtin_is_aligned(value, alignment) and /// __builtin_aligned_{up,down}(value, alignment) is an integer or a pointer /// type (but not a function pointer) and that the alignment is a power-of-two. -static bool SemaBuiltinAlignment(Sema &S, CallExpr *TheCall, unsigned ID) { +static bool BuiltinAlignment(Sema &S, CallExpr *TheCall, unsigned ID) { if (checkArgCount(S, TheCall, 2)) return true; @@ -366,8 +366,7 @@ static bool SemaBuiltinAlignment(Sema &S, CallExpr *TheCall, unsigned ID) { return false; } -static bool SemaBuiltinOverflow(Sema &S, CallExpr *TheCall, - unsigned BuiltinID) { +static bool BuiltinOverflow(Sema &S, CallExpr *TheCall, unsigned BuiltinID) { if (checkArgCount(S, TheCall, 3)) return true; @@ -695,7 +694,7 @@ struct BuiltinDumpStructGenerator { }; } // namespace -static ExprResult SemaBuiltinDumpStruct(Sema &S, CallExpr *TheCall) { +static ExprResult BuiltinDumpStruct(Sema &S, CallExpr *TheCall) { if (checkArgCountAtLeast(S, TheCall, 2)) return ExprError(); @@ -761,7 +760,7 @@ static ExprResult SemaBuiltinDumpStruct(Sema &S, CallExpr *TheCall) { return Generator.buildWrapper(); } -static bool SemaBuiltinCallWithStaticChain(Sema &S, CallExpr *BuiltinCall) { +static bool BuiltinCallWithStaticChain(Sema &S, CallExpr *BuiltinCall) { if (checkArgCount(S, BuiltinCall, 2)) return true; @@ -1427,9 +1426,9 @@ void Sema::checkFortifiedBuiltinMemoryFunction(FunctionDecl *FD, << FunctionName << DestinationStr << SourceStr); } -static bool SemaBuiltinSEHScopeCheck(Sema &SemaRef, CallExpr *TheCall, - Scope::ScopeFlags NeededScopeFlags, - unsigned DiagID) { +static bool BuiltinSEHScopeCheck(Sema &SemaRef, CallExpr *TheCall, + Scope::ScopeFlags NeededScopeFlags, + unsigned DiagID) { // Scopes aren't available during instantiation. Fortunately, builtin // functions cannot be template args so they cannot be formed through template // instantiation. Therefore checking once during the parse is sufficient. @@ -1503,7 +1502,7 @@ static bool checkOpenCLSubgroupExt(Sema &S, CallExpr *Call) { return false; } -static bool SemaOpenCLBuiltinNDRangeAndBlock(Sema &S, CallExpr *TheCall) { +static bool OpenCLBuiltinNDRangeAndBlock(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 2)) return true; @@ -1530,7 +1529,7 @@ static bool SemaOpenCLBuiltinNDRangeAndBlock(Sema &S, CallExpr *TheCall) { /// OpenCL C v2.0, s6.13.17.6 - Check the argument to the /// get_kernel_work_group_size /// and get_kernel_preferred_work_group_size_multiple builtin functions. -static bool SemaOpenCLBuiltinKernelWorkGroupSize(Sema &S, CallExpr *TheCall) { +static bool OpenCLBuiltinKernelWorkGroupSize(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 1)) return true; @@ -1606,7 +1605,7 @@ static bool checkOpenCLEnqueueVariadicArgs(Sema &S, CallExpr *TheCall, /// clk_event_t *event_ret, /// void (^block)(local void*, ...), /// uint size0, ...) -static bool SemaOpenCLBuiltinEnqueueKernel(Sema &S, CallExpr *TheCall) { +static bool OpenCLBuiltinEnqueueKernel(Sema &S, CallExpr *TheCall) { unsigned NumArgs = TheCall->getNumArgs(); if (NumArgs < 4) { @@ -1805,7 +1804,7 @@ static bool checkOpenCLPipePacketType(Sema &S, CallExpr *Call, unsigned Idx) { // \param S Reference to the semantic analyzer. // \param Call A pointer to the builtin call. // \return True if a semantic error has been found, false otherwise. -static bool SemaBuiltinRWPipe(Sema &S, CallExpr *Call) { +static bool BuiltinRWPipe(Sema &S, CallExpr *Call) { // OpenCL v2.0 s6.13.16.2 - The built-in read/write // functions have two forms. switch (Call->getNumArgs()) { @@ -1860,7 +1859,7 @@ static bool SemaBuiltinRWPipe(Sema &S, CallExpr *Call) { // \param S Reference to the semantic analyzer. // \param Call The call to the builtin function to be analyzed. // \return True if a semantic error was found, false otherwise. -static bool SemaBuiltinReserveRWPipe(Sema &S, CallExpr *Call) { +static bool BuiltinReserveRWPipe(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 2)) return true; @@ -1889,7 +1888,7 @@ static bool SemaBuiltinReserveRWPipe(Sema &S, CallExpr *Call) { // \param S Reference to the semantic analyzer. // \param Call The call to the builtin function to be analyzed. // \return True if a semantic error was found, false otherwise. -static bool SemaBuiltinCommitRWPipe(Sema &S, CallExpr *Call) { +static bool BuiltinCommitRWPipe(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 2)) return true; @@ -1912,7 +1911,7 @@ static bool SemaBuiltinCommitRWPipe(Sema &S, CallExpr *Call) { // \param S Reference to the semantic analyzer. // \param Call The call to the builtin function to be analyzed. // \return True if a semantic error was found, false otherwise. -static bool SemaBuiltinPipePackets(Sema &S, CallExpr *Call) { +static bool BuiltinPipePackets(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 1)) return true; @@ -1931,8 +1930,7 @@ static bool SemaBuiltinPipePackets(Sema &S, CallExpr *Call) { // \param BuiltinID ID of the builtin function. // \param Call A pointer to the builtin call. // \return True if a semantic error has been found, false otherwise. -static bool SemaOpenCLBuiltinToAddr(Sema &S, unsigned BuiltinID, - CallExpr *Call) { +static bool OpenCLBuiltinToAddr(Sema &S, unsigned BuiltinID, CallExpr *Call) { if (checkArgCount(S, Call, 1)) return true; @@ -2087,7 +2085,7 @@ static bool checkPointerAuthValue(Sema &S, Expr *&Arg, return false; } -static ExprResult SemaPointerAuthStrip(Sema &S, CallExpr *Call) { +static ExprResult PointerAuthStrip(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 2)) return ExprError(); if (checkPointerAuthEnabled(S, Call)) @@ -2100,7 +2098,7 @@ static ExprResult SemaPointerAuthStrip(Sema &S, CallExpr *Call) { return Call; } -static ExprResult SemaPointerAuthBlendDiscriminator(Sema &S, CallExpr *Call) { +static ExprResult PointerAuthBlendDiscriminator(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 2)) return ExprError(); if (checkPointerAuthEnabled(S, Call)) @@ -2113,7 +2111,7 @@ static ExprResult SemaPointerAuthBlendDiscriminator(Sema &S, CallExpr *Call) { return Call; } -static ExprResult SemaPointerAuthSignGenericData(Sema &S, CallExpr *Call) { +static ExprResult PointerAuthSignGenericData(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 2)) return ExprError(); if (checkPointerAuthEnabled(S, Call)) @@ -2126,8 +2124,8 @@ static ExprResult SemaPointerAuthSignGenericData(Sema &S, CallExpr *Call) { return Call; } -static ExprResult SemaPointerAuthSignOrAuth(Sema &S, CallExpr *Call, - PointerAuthOpKind OpKind) { +static ExprResult PointerAuthSignOrAuth(Sema &S, CallExpr *Call, + PointerAuthOpKind OpKind) { if (checkArgCount(S, Call, 3)) return ExprError(); if (checkPointerAuthEnabled(S, Call)) @@ -2141,7 +2139,7 @@ static ExprResult SemaPointerAuthSignOrAuth(Sema &S, CallExpr *Call, return Call; } -static ExprResult SemaPointerAuthAuthAndResign(Sema &S, CallExpr *Call) { +static ExprResult PointerAuthAuthAndResign(Sema &S, CallExpr *Call) { if (checkArgCount(S, Call, 5)) return ExprError(); if (checkPointerAuthEnabled(S, Call)) @@ -2157,7 +2155,7 @@ static ExprResult SemaPointerAuthAuthAndResign(Sema &S, CallExpr *Call) { return Call; } -static ExprResult SemaBuiltinLaunder(Sema &S, CallExpr *TheCall) { +static ExprResult BuiltinLaunder(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 1)) return ExprError(); @@ -2330,11 +2328,11 @@ static bool checkFPMathBuiltinElementType(Sema &S, SourceLocation Loc, return false; } -/// SemaBuiltinCpu{Supports|Is} - Handle __builtin_cpu_{supports|is}(char *). +/// BuiltinCpu{Supports|Is} - Handle __builtin_cpu_{supports|is}(char *). /// This checks that the target supports the builtin and that the string /// argument is constant and valid. -static bool SemaBuiltinCpu(Sema &S, const TargetInfo &TI, CallExpr *TheCall, - const TargetInfo *AuxTI, unsigned BuiltinID) { +static bool BuiltinCpu(Sema &S, const TargetInfo &TI, CallExpr *TheCall, + const TargetInfo *AuxTI, unsigned BuiltinID) { assert((BuiltinID == Builtin::BI__builtin_cpu_supports || BuiltinID == Builtin::BI__builtin_cpu_is) && "Expecting __builtin_cpu_..."); @@ -2379,7 +2377,7 @@ static bool SemaBuiltinCpu(Sema &S, const TargetInfo &TI, CallExpr *TheCall, /// Checks that __builtin_popcountg was called with a single argument, which is /// an unsigned integer. -static bool SemaBuiltinPopcountg(Sema &S, CallExpr *TheCall) { +static bool BuiltinPopcountg(Sema &S, CallExpr *TheCall) { if (checkArgCount(S, TheCall, 1)) return true; @@ -2403,7 +2401,7 @@ static bool SemaBuiltinPopcountg(Sema &S, CallExpr *TheCall) { /// Checks that __builtin_{clzg,ctzg} was called with a first argument, which is /// an unsigned integer, and an optional second argument, which is promoted to /// an 'int'. -static bool SemaBuiltinCountZeroBitsGeneric(Sema &S, CallExpr *TheCall) { +static bool BuiltinCountZeroBitsGeneric(Sema &S, CallExpr *TheCall) { if (checkArgCountRange(S, TheCall, 1, 2)) return true; @@ -2463,7 +2461,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, // If we don't have enough arguments, continue so we can issue better // diagnostic in checkArgCount(...) if (ArgNo < TheCall->getNumArgs() && - SemaBuiltinConstantArg(TheCall, ArgNo, Result)) + BuiltinConstantArg(TheCall, ArgNo, Result)) return true; ICEArguments &= ~(1 << ArgNo); } @@ -2472,8 +2470,8 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, switch (BuiltinID) { case Builtin::BI__builtin_cpu_supports: case Builtin::BI__builtin_cpu_is: - if (SemaBuiltinCpu(*this, Context.getTargetInfo(), TheCall, - Context.getAuxTargetInfo(), BuiltinID)) + if (BuiltinCpu(*this, Context.getTargetInfo(), TheCall, + Context.getAuxTargetInfo(), BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_cpu_init: @@ -2498,7 +2496,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__builtin_ms_va_start: case Builtin::BI__builtin_stdarg_start: case Builtin::BI__builtin_va_start: - if (SemaBuiltinVAStart(BuiltinID, TheCall)) + if (BuiltinVAStart(BuiltinID, TheCall)) return ExprError(); break; case Builtin::BI__va_start: { @@ -2506,11 +2504,11 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case llvm::Triple::aarch64: case llvm::Triple::arm: case llvm::Triple::thumb: - if (SemaBuiltinVAStartARMMicrosoft(TheCall)) + if (BuiltinVAStartARMMicrosoft(TheCall)) return ExprError(); break; default: - if (SemaBuiltinVAStart(BuiltinID, TheCall)) + if (BuiltinVAStart(BuiltinID, TheCall)) return ExprError(); break; } @@ -2558,15 +2556,15 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__builtin_islessequal: case Builtin::BI__builtin_islessgreater: case Builtin::BI__builtin_isunordered: - if (SemaBuiltinUnorderedCompare(TheCall, BuiltinID)) + if (BuiltinUnorderedCompare(TheCall, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_fpclassify: - if (SemaBuiltinFPClassification(TheCall, 6, BuiltinID)) + if (BuiltinFPClassification(TheCall, 6, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_isfpclass: - if (SemaBuiltinFPClassification(TheCall, 2, BuiltinID)) + if (BuiltinFPClassification(TheCall, 2, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_isfinite: @@ -2580,20 +2578,20 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__builtin_signbit: case Builtin::BI__builtin_signbitf: case Builtin::BI__builtin_signbitl: - if (SemaBuiltinFPClassification(TheCall, 1, BuiltinID)) + if (BuiltinFPClassification(TheCall, 1, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_shufflevector: - return SemaBuiltinShuffleVector(TheCall); + return BuiltinShuffleVector(TheCall); // TheCall will be freed by the smart pointer here, but that's fine, since - // SemaBuiltinShuffleVector guts it, but then doesn't release it. + // BuiltinShuffleVector guts it, but then doesn't release it. case Builtin::BI__builtin_prefetch: - if (SemaBuiltinPrefetch(TheCall)) + if (BuiltinPrefetch(TheCall)) return ExprError(); break; case Builtin::BI__builtin_alloca_with_align: case Builtin::BI__builtin_alloca_with_align_uninitialized: - if (SemaBuiltinAllocaWithAlign(TheCall)) + if (BuiltinAllocaWithAlign(TheCall)) return ExprError(); [[fallthrough]]; case Builtin::BI__builtin_alloca: @@ -2602,29 +2600,29 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, << TheCall->getDirectCallee(); break; case Builtin::BI__arithmetic_fence: - if (SemaBuiltinArithmeticFence(TheCall)) + if (BuiltinArithmeticFence(TheCall)) return ExprError(); break; case Builtin::BI__assume: case Builtin::BI__builtin_assume: - if (SemaBuiltinAssume(TheCall)) + if (BuiltinAssume(TheCall)) return ExprError(); break; case Builtin::BI__builtin_assume_aligned: - if (SemaBuiltinAssumeAligned(TheCall)) + if (BuiltinAssumeAligned(TheCall)) return ExprError(); break; case Builtin::BI__builtin_dynamic_object_size: case Builtin::BI__builtin_object_size: - if (SemaBuiltinConstantArgRange(TheCall, 1, 0, 3)) + if (BuiltinConstantArgRange(TheCall, 1, 0, 3)) return ExprError(); break; case Builtin::BI__builtin_longjmp: - if (SemaBuiltinLongjmp(TheCall)) + if (BuiltinLongjmp(TheCall)) return ExprError(); break; case Builtin::BI__builtin_setjmp: - if (SemaBuiltinSetjmp(TheCall)) + if (BuiltinSetjmp(TheCall)) return ExprError(); break; case Builtin::BI__builtin_classify_type: @@ -2632,7 +2630,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, TheCall->setType(Context.IntTy); break; case Builtin::BI__builtin_complex: - if (SemaBuiltinComplex(TheCall)) + if (BuiltinComplex(TheCall)) return ExprError(); break; case Builtin::BI__builtin_constant_p: { @@ -2644,7 +2642,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, break; } case Builtin::BI__builtin_launder: - return SemaBuiltinLaunder(*this, TheCall); + return BuiltinLaunder(*this, TheCall); case Builtin::BI__sync_fetch_and_add: case Builtin::BI__sync_fetch_and_add_1: case Builtin::BI__sync_fetch_and_add_2: @@ -2747,14 +2745,14 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__sync_swap_4: case Builtin::BI__sync_swap_8: case Builtin::BI__sync_swap_16: - return SemaBuiltinAtomicOverloaded(TheCallResult); + return BuiltinAtomicOverloaded(TheCallResult); case Builtin::BI__sync_synchronize: Diag(TheCall->getBeginLoc(), diag::warn_atomic_implicit_seq_cst) << TheCall->getCallee()->getSourceRange(); break; case Builtin::BI__builtin_nontemporal_load: case Builtin::BI__builtin_nontemporal_store: - return SemaBuiltinNontemporalOverloaded(TheCallResult); + return BuiltinNontemporalOverloaded(TheCallResult); case Builtin::BI__builtin_memcpy_inline: { clang::Expr *SizeOp = TheCall->getArg(2); // We warn about copying to or from `nullptr` pointers when `size` is @@ -2780,49 +2778,49 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, break; } #define BUILTIN(ID, TYPE, ATTRS) -#define ATOMIC_BUILTIN(ID, TYPE, ATTRS) \ - case Builtin::BI##ID: \ - return SemaAtomicOpsOverloaded(TheCallResult, AtomicExpr::AO##ID); +#define ATOMIC_BUILTIN(ID, TYPE, ATTRS) \ + case Builtin::BI##ID: \ + return AtomicOpsOverloaded(TheCallResult, AtomicExpr::AO##ID); #include "clang/Basic/Builtins.inc" case Builtin::BI__annotation: - if (SemaBuiltinMSVCAnnotation(*this, TheCall)) + if (BuiltinMSVCAnnotation(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_annotation: - if (SemaBuiltinAnnotation(*this, TheCall)) + if (BuiltinAnnotation(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_addressof: - if (SemaBuiltinAddressof(*this, TheCall)) + if (BuiltinAddressof(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_function_start: - if (SemaBuiltinFunctionStart(*this, TheCall)) + if (BuiltinFunctionStart(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_is_aligned: case Builtin::BI__builtin_align_up: case Builtin::BI__builtin_align_down: - if (SemaBuiltinAlignment(*this, TheCall, BuiltinID)) + if (BuiltinAlignment(*this, TheCall, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_add_overflow: case Builtin::BI__builtin_sub_overflow: case Builtin::BI__builtin_mul_overflow: - if (SemaBuiltinOverflow(*this, TheCall, BuiltinID)) + if (BuiltinOverflow(*this, TheCall, BuiltinID)) return ExprError(); break; case Builtin::BI__builtin_operator_new: case Builtin::BI__builtin_operator_delete: { bool IsDelete = BuiltinID == Builtin::BI__builtin_operator_delete; ExprResult Res = - SemaBuiltinOperatorNewDeleteOverloaded(TheCallResult, IsDelete); + BuiltinOperatorNewDeleteOverloaded(TheCallResult, IsDelete); if (Res.isInvalid()) CorrectDelayedTyposInExpr(TheCallResult.get()); return Res; } case Builtin::BI__builtin_dump_struct: - return SemaBuiltinDumpStruct(*this, TheCall); + return BuiltinDumpStruct(*this, TheCall); case Builtin::BI__builtin_expect_with_probability: { // We first want to ensure we are called with 3 arguments if (checkArgCount(*this, TheCall, 3)) @@ -2853,23 +2851,23 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, break; } case Builtin::BI__builtin_preserve_access_index: - if (SemaBuiltinPreserveAI(*this, TheCall)) + if (BuiltinPreserveAI(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_call_with_static_chain: - if (SemaBuiltinCallWithStaticChain(*this, TheCall)) + if (BuiltinCallWithStaticChain(*this, TheCall)) return ExprError(); break; case Builtin::BI__exception_code: case Builtin::BI_exception_code: - if (SemaBuiltinSEHScopeCheck(*this, TheCall, Scope::SEHExceptScope, - diag::err_seh___except_block)) + if (BuiltinSEHScopeCheck(*this, TheCall, Scope::SEHExceptScope, + diag::err_seh___except_block)) return ExprError(); break; case Builtin::BI__exception_info: case Builtin::BI_exception_info: - if (SemaBuiltinSEHScopeCheck(*this, TheCall, Scope::SEHFilterScope, - diag::err_seh___except_filter)) + if (BuiltinSEHScopeCheck(*this, TheCall, Scope::SEHFilterScope, + diag::err_seh___except_filter)) return ExprError(); break; case Builtin::BI__GetExceptionInfo: @@ -2912,87 +2910,87 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, break; } case Builtin::BI__builtin_ptrauth_strip: - return SemaPointerAuthStrip(*this, TheCall); + return PointerAuthStrip(*this, TheCall); case Builtin::BI__builtin_ptrauth_blend_discriminator: - return SemaPointerAuthBlendDiscriminator(*this, TheCall); + return PointerAuthBlendDiscriminator(*this, TheCall); case Builtin::BI__builtin_ptrauth_sign_unauthenticated: - return SemaPointerAuthSignOrAuth(*this, TheCall, PAO_Sign); + return PointerAuthSignOrAuth(*this, TheCall, PAO_Sign); case Builtin::BI__builtin_ptrauth_auth: - return SemaPointerAuthSignOrAuth(*this, TheCall, PAO_Auth); + return PointerAuthSignOrAuth(*this, TheCall, PAO_Auth); case Builtin::BI__builtin_ptrauth_sign_generic_data: - return SemaPointerAuthSignGenericData(*this, TheCall); + return PointerAuthSignGenericData(*this, TheCall); case Builtin::BI__builtin_ptrauth_auth_and_resign: - return SemaPointerAuthAuthAndResign(*this, TheCall); + return PointerAuthAuthAndResign(*this, TheCall); // OpenCL v2.0, s6.13.16 - Pipe functions case Builtin::BIread_pipe: case Builtin::BIwrite_pipe: // Since those two functions are declared with var args, we need a semantic // check for the argument. - if (SemaBuiltinRWPipe(*this, TheCall)) + if (BuiltinRWPipe(*this, TheCall)) return ExprError(); break; case Builtin::BIreserve_read_pipe: case Builtin::BIreserve_write_pipe: case Builtin::BIwork_group_reserve_read_pipe: case Builtin::BIwork_group_reserve_write_pipe: - if (SemaBuiltinReserveRWPipe(*this, TheCall)) + if (BuiltinReserveRWPipe(*this, TheCall)) return ExprError(); break; case Builtin::BIsub_group_reserve_read_pipe: case Builtin::BIsub_group_reserve_write_pipe: if (checkOpenCLSubgroupExt(*this, TheCall) || - SemaBuiltinReserveRWPipe(*this, TheCall)) + BuiltinReserveRWPipe(*this, TheCall)) return ExprError(); break; case Builtin::BIcommit_read_pipe: case Builtin::BIcommit_write_pipe: case Builtin::BIwork_group_commit_read_pipe: case Builtin::BIwork_group_commit_write_pipe: - if (SemaBuiltinCommitRWPipe(*this, TheCall)) + if (BuiltinCommitRWPipe(*this, TheCall)) return ExprError(); break; case Builtin::BIsub_group_commit_read_pipe: case Builtin::BIsub_group_commit_write_pipe: if (checkOpenCLSubgroupExt(*this, TheCall) || - SemaBuiltinCommitRWPipe(*this, TheCall)) + BuiltinCommitRWPipe(*this, TheCall)) return ExprError(); break; case Builtin::BIget_pipe_num_packets: case Builtin::BIget_pipe_max_packets: - if (SemaBuiltinPipePackets(*this, TheCall)) + if (BuiltinPipePackets(*this, TheCall)) return ExprError(); break; case Builtin::BIto_global: case Builtin::BIto_local: case Builtin::BIto_private: - if (SemaOpenCLBuiltinToAddr(*this, BuiltinID, TheCall)) + if (OpenCLBuiltinToAddr(*this, BuiltinID, TheCall)) return ExprError(); break; // OpenCL v2.0, s6.13.17 - Enqueue kernel functions. case Builtin::BIenqueue_kernel: - if (SemaOpenCLBuiltinEnqueueKernel(*this, TheCall)) + if (OpenCLBuiltinEnqueueKernel(*this, TheCall)) return ExprError(); break; case Builtin::BIget_kernel_work_group_size: case Builtin::BIget_kernel_preferred_work_group_size_multiple: - if (SemaOpenCLBuiltinKernelWorkGroupSize(*this, TheCall)) + if (OpenCLBuiltinKernelWorkGroupSize(*this, TheCall)) return ExprError(); break; case Builtin::BIget_kernel_max_sub_group_size_for_ndrange: case Builtin::BIget_kernel_sub_group_count_for_ndrange: - if (SemaOpenCLBuiltinNDRangeAndBlock(*this, TheCall)) + if (OpenCLBuiltinNDRangeAndBlock(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_os_log_format: Cleanup.setExprNeedsCleanups(true); [[fallthrough]]; case Builtin::BI__builtin_os_log_format_buffer_size: - if (SemaBuiltinOSLogFormat(TheCall)) + if (BuiltinOSLogFormat(TheCall)) return ExprError(); break; case Builtin::BI__builtin_frame_address: case Builtin::BI__builtin_return_address: { - if (SemaBuiltinConstantArgRange(TheCall, 0, 0, 0xFFFF)) + if (BuiltinConstantArgRange(TheCall, 0, 0, 0xFFFF)) return ExprError(); // -Wframe-address warning if non-zero passed to builtin @@ -3010,7 +3008,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, } case Builtin::BI__builtin_nondeterministic_value: { - if (SemaBuiltinNonDeterministicValue(TheCall)) + if (BuiltinNonDeterministicValue(TheCall)) return ExprError(); break; } @@ -3063,7 +3061,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, break; } case Builtin::BI__builtin_elementwise_fma: { - if (SemaBuiltinElementwiseTernaryMath(TheCall)) + if (BuiltinElementwiseTernaryMath(TheCall)) return ExprError(); break; } @@ -3071,7 +3069,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, // These builtins restrict the element type to floating point // types only, and take in two arguments. case Builtin::BI__builtin_elementwise_pow: { - if (SemaBuiltinElementwiseMath(TheCall)) + if (BuiltinElementwiseMath(TheCall)) return ExprError(); QualType ArgTy = TheCall->getArg(0)->getType(); @@ -3087,7 +3085,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, // types only. case Builtin::BI__builtin_elementwise_add_sat: case Builtin::BI__builtin_elementwise_sub_sat: { - if (SemaBuiltinElementwiseMath(TheCall)) + if (BuiltinElementwiseMath(TheCall)) return ExprError(); const Expr *Arg = TheCall->getArg(0); @@ -3107,7 +3105,7 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, case Builtin::BI__builtin_elementwise_min: case Builtin::BI__builtin_elementwise_max: - if (SemaBuiltinElementwiseMath(TheCall)) + if (BuiltinElementwiseMath(TheCall)) return ExprError(); break; @@ -3198,13 +3196,13 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, } case Builtin::BI__builtin_matrix_transpose: - return SemaBuiltinMatrixTranspose(TheCall, TheCallResult); + return BuiltinMatrixTranspose(TheCall, TheCallResult); case Builtin::BI__builtin_matrix_column_major_load: - return SemaBuiltinMatrixColumnMajorLoad(TheCall, TheCallResult); + return BuiltinMatrixColumnMajorLoad(TheCall, TheCallResult); case Builtin::BI__builtin_matrix_column_major_store: - return SemaBuiltinMatrixColumnMajorStore(TheCall, TheCallResult); + return BuiltinMatrixColumnMajorStore(TheCall, TheCallResult); case Builtin::BI__builtin_get_device_side_mangled_name: { auto Check = [](CallExpr *TheCall) { @@ -3227,12 +3225,12 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, break; } case Builtin::BI__builtin_popcountg: - if (SemaBuiltinPopcountg(*this, TheCall)) + if (BuiltinPopcountg(*this, TheCall)) return ExprError(); break; case Builtin::BI__builtin_clzg: case Builtin::BI__builtin_ctzg: - if (SemaBuiltinCountZeroBitsGeneric(*this, TheCall)) + if (BuiltinCountZeroBitsGeneric(*this, TheCall)) return ExprError(); break; } @@ -3378,7 +3376,7 @@ bool Sema::ParseSVEImmChecks( // Check constant-ness first. llvm::APSInt Imm; - if (SemaBuiltinConstantArg(TheCall, ArgNum, Imm)) + if (BuiltinConstantArg(TheCall, ArgNum, Imm)) return true; if (!CheckImm(Imm.getSExtValue())) @@ -3388,65 +3386,63 @@ bool Sema::ParseSVEImmChecks( switch ((SVETypeFlags::ImmCheckType)CheckTy) { case SVETypeFlags::ImmCheck0_31: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 31)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 31)) HasError = true; break; case SVETypeFlags::ImmCheck0_13: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 13)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 13)) HasError = true; break; case SVETypeFlags::ImmCheck1_16: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 16)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 1, 16)) HasError = true; break; case SVETypeFlags::ImmCheck0_7: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 7)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 7)) HasError = true; break; case SVETypeFlags::ImmCheck1_1: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 1, 1)) HasError = true; break; case SVETypeFlags::ImmCheck1_3: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 3)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 1, 3)) HasError = true; break; case SVETypeFlags::ImmCheck1_7: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, 7)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 1, 7)) HasError = true; break; case SVETypeFlags::ImmCheckExtract: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, - (2048 / ElementSizeInBits) - 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, + (2048 / ElementSizeInBits) - 1)) HasError = true; break; case SVETypeFlags::ImmCheckShiftRight: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, ElementSizeInBits)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 1, ElementSizeInBits)) HasError = true; break; case SVETypeFlags::ImmCheckShiftRightNarrow: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 1, - ElementSizeInBits / 2)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 1, ElementSizeInBits / 2)) HasError = true; break; case SVETypeFlags::ImmCheckShiftLeft: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, - ElementSizeInBits - 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, ElementSizeInBits - 1)) HasError = true; break; case SVETypeFlags::ImmCheckLaneIndex: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, - (128 / (1 * ElementSizeInBits)) - 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, + (128 / (1 * ElementSizeInBits)) - 1)) HasError = true; break; case SVETypeFlags::ImmCheckLaneIndexCompRotate: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, - (128 / (2 * ElementSizeInBits)) - 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, + (128 / (2 * ElementSizeInBits)) - 1)) HasError = true; break; case SVETypeFlags::ImmCheckLaneIndexDot: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, - (128 / (4 * ElementSizeInBits)) - 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, + (128 / (4 * ElementSizeInBits)) - 1)) HasError = true; break; case SVETypeFlags::ImmCheckComplexRot90_270: @@ -3463,32 +3459,32 @@ bool Sema::ParseSVEImmChecks( HasError = true; break; case SVETypeFlags::ImmCheck0_1: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 1)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 1)) HasError = true; break; case SVETypeFlags::ImmCheck0_2: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 2)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 2)) HasError = true; break; case SVETypeFlags::ImmCheck0_3: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 3)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 3)) HasError = true; break; case SVETypeFlags::ImmCheck0_0: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 0)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 0)) HasError = true; break; case SVETypeFlags::ImmCheck0_15: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 15)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 15)) HasError = true; break; case SVETypeFlags::ImmCheck0_255: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, 255)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 0, 255)) HasError = true; break; case SVETypeFlags::ImmCheck2_4_Mul2: - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, 2, 4) || - SemaBuiltinConstantArgMultiple(TheCall, ArgNum, 2)) + if (BuiltinConstantArgRange(TheCall, ArgNum, 2, 4) || + BuiltinConstantArgMultiple(TheCall, ArgNum, 2)) HasError = true; break; } @@ -3664,7 +3660,7 @@ bool Sema::CheckNeonBuiltinFunctionCall(const TargetInfo &TI, // the immediate which specifies which variant to emit. unsigned ImmArg = TheCall->getNumArgs()-1; if (mask) { - if (SemaBuiltinConstantArg(TheCall, ImmArg, Result)) + if (BuiltinConstantArg(TheCall, ImmArg, Result)) return true; TV = Result.getLimitedValue(64); @@ -3712,7 +3708,7 @@ bool Sema::CheckNeonBuiltinFunctionCall(const TargetInfo &TI, #undef GET_NEON_IMMEDIATE_CHECK } - return SemaBuiltinConstantArgRange(TheCall, i, l, u + l); + return BuiltinConstantArgRange(TheCall, i, l, u + l); } bool Sema::CheckMVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { @@ -3886,19 +3882,19 @@ bool Sema::CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, } if (BuiltinID == ARM::BI__builtin_arm_prefetch) { - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1) || + BuiltinConstantArgRange(TheCall, 2, 0, 1); } if (BuiltinID == ARM::BI__builtin_arm_rsr64 || BuiltinID == ARM::BI__builtin_arm_wsr64) - return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 3, false); + return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 3, false); if (BuiltinID == ARM::BI__builtin_arm_rsr || BuiltinID == ARM::BI__builtin_arm_rsrp || BuiltinID == ARM::BI__builtin_arm_wsr || BuiltinID == ARM::BI__builtin_arm_wsrp) - return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); + return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall)) return true; @@ -3913,21 +3909,21 @@ bool Sema::CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, switch (BuiltinID) { default: return false; case ARM::BI__builtin_arm_ssat: - return SemaBuiltinConstantArgRange(TheCall, 1, 1, 32); + return BuiltinConstantArgRange(TheCall, 1, 1, 32); case ARM::BI__builtin_arm_usat: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + return BuiltinConstantArgRange(TheCall, 1, 0, 31); case ARM::BI__builtin_arm_ssat16: - return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); + return BuiltinConstantArgRange(TheCall, 1, 1, 16); case ARM::BI__builtin_arm_usat16: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15); case ARM::BI__builtin_arm_vcvtr_f: case ARM::BI__builtin_arm_vcvtr_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1); case ARM::BI__builtin_arm_dmb: case ARM::BI__builtin_arm_dsb: case ARM::BI__builtin_arm_isb: case ARM::BI__builtin_arm_dbg: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 15); + return BuiltinConstantArgRange(TheCall, 0, 0, 15); case ARM::BI__builtin_arm_cdp: case ARM::BI__builtin_arm_cdp2: case ARM::BI__builtin_arm_mcr: @@ -3946,7 +3942,7 @@ bool Sema::CheckARMBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, case ARM::BI__builtin_arm_stcl: case ARM::BI__builtin_arm_stc2: case ARM::BI__builtin_arm_stc2l: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 15) || + return BuiltinConstantArgRange(TheCall, 0, 0, 15) || CheckARMCoprocessorImmediate(TI, TheCall->getArg(0), /*WantCDE*/ false); } @@ -3963,17 +3959,17 @@ bool Sema::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, } if (BuiltinID == AArch64::BI__builtin_arm_prefetch) { - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 1) || - SemaBuiltinConstantArgRange(TheCall, 4, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1) || + BuiltinConstantArgRange(TheCall, 2, 0, 3) || + BuiltinConstantArgRange(TheCall, 3, 0, 1) || + BuiltinConstantArgRange(TheCall, 4, 0, 1); } if (BuiltinID == AArch64::BI__builtin_arm_rsr64 || BuiltinID == AArch64::BI__builtin_arm_wsr64 || BuiltinID == AArch64::BI__builtin_arm_rsr128 || BuiltinID == AArch64::BI__builtin_arm_wsr128) - return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); + return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); // Memory Tagging Extensions (MTE) Intrinsics if (BuiltinID == AArch64::BI__builtin_arm_irg || @@ -3982,27 +3978,27 @@ bool Sema::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, BuiltinID == AArch64::BI__builtin_arm_ldg || BuiltinID == AArch64::BI__builtin_arm_stg || BuiltinID == AArch64::BI__builtin_arm_subp) { - return SemaBuiltinARMMemoryTaggingCall(BuiltinID, TheCall); + return BuiltinARMMemoryTaggingCall(BuiltinID, TheCall); } if (BuiltinID == AArch64::BI__builtin_arm_rsr || BuiltinID == AArch64::BI__builtin_arm_rsrp || BuiltinID == AArch64::BI__builtin_arm_wsr || BuiltinID == AArch64::BI__builtin_arm_wsrp) - return SemaBuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); + return BuiltinARMSpecialReg(BuiltinID, TheCall, 0, 5, true); // Only check the valid encoding range. Any constant in this range would be // converted to a register of the form S1_2_C3_C4_5. Let the hardware throw // an exception for incorrect registers. This matches MSVC behavior. if (BuiltinID == AArch64::BI_ReadStatusReg || BuiltinID == AArch64::BI_WriteStatusReg) - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0x7fff); + return BuiltinConstantArgRange(TheCall, 0, 0, 0x7fff); if (BuiltinID == AArch64::BI__getReg) - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31); + return BuiltinConstantArgRange(TheCall, 0, 0, 31); if (BuiltinID == AArch64::BI__break) - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 0xffff); + return BuiltinConstantArgRange(TheCall, 0, 0, 0xffff); if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall)) return true; @@ -4024,7 +4020,7 @@ bool Sema::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, case AArch64::BI__builtin_arm_tcancel: l = 0; u = 65535; break; } - return SemaBuiltinConstantArgRange(TheCall, i, l, u + l); + return BuiltinConstantArgRange(TheCall, i, l, u + l); } static bool isValidBPFPreserveFieldInfoArg(Expr *Arg) { @@ -4423,13 +4419,13 @@ bool Sema::CheckHexagonBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { int32_t Min = A.IsSigned ? -(1 << (A.BitWidth - 1)) : 0; int32_t Max = (1 << (A.IsSigned ? A.BitWidth - 1 : A.BitWidth)) - 1; if (!A.Align) { - Error |= SemaBuiltinConstantArgRange(TheCall, A.OpNum, Min, Max); + Error |= BuiltinConstantArgRange(TheCall, A.OpNum, Min, Max); } else { unsigned M = 1 << A.Align; Min *= M; Max *= M; - Error |= SemaBuiltinConstantArgRange(TheCall, A.OpNum, Min, Max); - Error |= SemaBuiltinConstantArgMultiple(TheCall, A.OpNum, M); + Error |= BuiltinConstantArgRange(TheCall, A.OpNum, Min, Max); + Error |= BuiltinConstantArgMultiple(TheCall, A.OpNum, M); } } return Error; @@ -4449,9 +4445,8 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, // Basic intrinsics. case LoongArch::BI__builtin_loongarch_cacop_d: case LoongArch::BI__builtin_loongarch_cacop_w: { - SemaBuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(5)); - SemaBuiltinConstantArgRange(TheCall, 2, llvm::minIntN(12), - llvm::maxIntN(12)); + BuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(5)); + BuiltinConstantArgRange(TheCall, 2, llvm::minIntN(12), llvm::maxIntN(12)); break; } case LoongArch::BI__builtin_loongarch_break: @@ -4459,22 +4454,22 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_loongarch_ibar: case LoongArch::BI__builtin_loongarch_syscall: // Check if immediate is in [0, 32767]. - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767); + return BuiltinConstantArgRange(TheCall, 0, 0, 32767); case LoongArch::BI__builtin_loongarch_csrrd_w: case LoongArch::BI__builtin_loongarch_csrrd_d: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 16383); + return BuiltinConstantArgRange(TheCall, 0, 0, 16383); case LoongArch::BI__builtin_loongarch_csrwr_w: case LoongArch::BI__builtin_loongarch_csrwr_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 16383); + return BuiltinConstantArgRange(TheCall, 1, 0, 16383); case LoongArch::BI__builtin_loongarch_csrxchg_w: case LoongArch::BI__builtin_loongarch_csrxchg_d: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 16383); + return BuiltinConstantArgRange(TheCall, 2, 0, 16383); case LoongArch::BI__builtin_loongarch_lddir_d: case LoongArch::BI__builtin_loongarch_ldpte_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + return BuiltinConstantArgRange(TheCall, 1, 0, 31); case LoongArch::BI__builtin_loongarch_movfcsr2gr: case LoongArch::BI__builtin_loongarch_movgr2fcsr: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(2)); + return BuiltinConstantArgRange(TheCall, 0, 0, llvm::maxUIntN(2)); // LSX intrinsics. case LoongArch::BI__builtin_lsx_vbitclri_b: @@ -4490,7 +4485,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vsllwil_hu_bu: case LoongArch::BI__builtin_lsx_vrotri_b: case LoongArch::BI__builtin_lsx_vsrlri_b: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7); + return BuiltinConstantArgRange(TheCall, 1, 0, 7); case LoongArch::BI__builtin_lsx_vbitclri_h: case LoongArch::BI__builtin_lsx_vbitrevi_h: case LoongArch::BI__builtin_lsx_vbitseti_h: @@ -4504,7 +4499,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vsllwil_wu_hu: case LoongArch::BI__builtin_lsx_vrotri_h: case LoongArch::BI__builtin_lsx_vsrlri_h: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15); case LoongArch::BI__builtin_lsx_vssrarni_b_h: case LoongArch::BI__builtin_lsx_vssrarni_bu_h: case LoongArch::BI__builtin_lsx_vssrani_b_h: @@ -4517,7 +4512,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vssrlrni_b_h: case LoongArch::BI__builtin_lsx_vssrlrni_bu_h: case LoongArch::BI__builtin_lsx_vsrani_b_h: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); + return BuiltinConstantArgRange(TheCall, 2, 0, 15); case LoongArch::BI__builtin_lsx_vslei_bu: case LoongArch::BI__builtin_lsx_vslei_hu: case LoongArch::BI__builtin_lsx_vslei_wu: @@ -4557,7 +4552,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vbsll_v: case LoongArch::BI__builtin_lsx_vsubi_wu: case LoongArch::BI__builtin_lsx_vsubi_du: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + return BuiltinConstantArgRange(TheCall, 1, 0, 31); case LoongArch::BI__builtin_lsx_vssrarni_h_w: case LoongArch::BI__builtin_lsx_vssrarni_hu_w: case LoongArch::BI__builtin_lsx_vssrani_h_w: @@ -4572,7 +4567,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vssrlni_hu_w: case LoongArch::BI__builtin_lsx_vssrlrni_h_w: case LoongArch::BI__builtin_lsx_vssrlrni_hu_w: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); + return BuiltinConstantArgRange(TheCall, 2, 0, 31); case LoongArch::BI__builtin_lsx_vbitclri_d: case LoongArch::BI__builtin_lsx_vbitrevi_d: case LoongArch::BI__builtin_lsx_vbitseti_d: @@ -4584,7 +4579,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vsrari_d: case LoongArch::BI__builtin_lsx_vrotri_d: case LoongArch::BI__builtin_lsx_vsrlri_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); + return BuiltinConstantArgRange(TheCall, 1, 0, 63); case LoongArch::BI__builtin_lsx_vssrarni_w_d: case LoongArch::BI__builtin_lsx_vssrarni_wu_d: case LoongArch::BI__builtin_lsx_vssrani_w_d: @@ -4597,7 +4592,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vssrlrni_w_d: case LoongArch::BI__builtin_lsx_vssrlrni_wu_d: case LoongArch::BI__builtin_lsx_vsrani_w_d: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 63); + return BuiltinConstantArgRange(TheCall, 2, 0, 63); case LoongArch::BI__builtin_lsx_vssrarni_d_q: case LoongArch::BI__builtin_lsx_vssrarni_du_q: case LoongArch::BI__builtin_lsx_vssrani_d_q: @@ -4610,7 +4605,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vsrani_d_q: case LoongArch::BI__builtin_lsx_vsrlrni_d_q: case LoongArch::BI__builtin_lsx_vsrlni_d_q: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 127); + return BuiltinConstantArgRange(TheCall, 2, 0, 127); case LoongArch::BI__builtin_lsx_vseqi_b: case LoongArch::BI__builtin_lsx_vseqi_h: case LoongArch::BI__builtin_lsx_vseqi_w: @@ -4631,7 +4626,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vmini_h: case LoongArch::BI__builtin_lsx_vmini_w: case LoongArch::BI__builtin_lsx_vmini_d: - return SemaBuiltinConstantArgRange(TheCall, 1, -16, 15); + return BuiltinConstantArgRange(TheCall, 1, -16, 15); case LoongArch::BI__builtin_lsx_vandi_b: case LoongArch::BI__builtin_lsx_vnori_b: case LoongArch::BI__builtin_lsx_vori_b: @@ -4639,7 +4634,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vshuf4i_h: case LoongArch::BI__builtin_lsx_vshuf4i_w: case LoongArch::BI__builtin_lsx_vxori_b: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 255); + return BuiltinConstantArgRange(TheCall, 1, 0, 255); case LoongArch::BI__builtin_lsx_vbitseli_b: case LoongArch::BI__builtin_lsx_vshuf4i_d: case LoongArch::BI__builtin_lsx_vextrins_b: @@ -4647,61 +4642,61 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lsx_vextrins_w: case LoongArch::BI__builtin_lsx_vextrins_d: case LoongArch::BI__builtin_lsx_vpermi_w: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 255); + return BuiltinConstantArgRange(TheCall, 2, 0, 255); case LoongArch::BI__builtin_lsx_vpickve2gr_b: case LoongArch::BI__builtin_lsx_vpickve2gr_bu: case LoongArch::BI__builtin_lsx_vreplvei_b: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15); case LoongArch::BI__builtin_lsx_vinsgr2vr_b: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); + return BuiltinConstantArgRange(TheCall, 2, 0, 15); case LoongArch::BI__builtin_lsx_vpickve2gr_h: case LoongArch::BI__builtin_lsx_vpickve2gr_hu: case LoongArch::BI__builtin_lsx_vreplvei_h: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7); + return BuiltinConstantArgRange(TheCall, 1, 0, 7); case LoongArch::BI__builtin_lsx_vinsgr2vr_h: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7); + return BuiltinConstantArgRange(TheCall, 2, 0, 7); case LoongArch::BI__builtin_lsx_vpickve2gr_w: case LoongArch::BI__builtin_lsx_vpickve2gr_wu: case LoongArch::BI__builtin_lsx_vreplvei_w: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3); + return BuiltinConstantArgRange(TheCall, 1, 0, 3); case LoongArch::BI__builtin_lsx_vinsgr2vr_w: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 3); case LoongArch::BI__builtin_lsx_vpickve2gr_d: case LoongArch::BI__builtin_lsx_vpickve2gr_du: case LoongArch::BI__builtin_lsx_vreplvei_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1); case LoongArch::BI__builtin_lsx_vinsgr2vr_d: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 1); + return BuiltinConstantArgRange(TheCall, 2, 0, 1); case LoongArch::BI__builtin_lsx_vstelm_b: - return SemaBuiltinConstantArgRange(TheCall, 2, -128, 127) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 15); + return BuiltinConstantArgRange(TheCall, 2, -128, 127) || + BuiltinConstantArgRange(TheCall, 3, 0, 15); case LoongArch::BI__builtin_lsx_vstelm_h: - return SemaBuiltinConstantArgRange(TheCall, 2, -256, 254) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 7); + return BuiltinConstantArgRange(TheCall, 2, -256, 254) || + BuiltinConstantArgRange(TheCall, 3, 0, 7); case LoongArch::BI__builtin_lsx_vstelm_w: - return SemaBuiltinConstantArgRange(TheCall, 2, -512, 508) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, -512, 508) || + BuiltinConstantArgRange(TheCall, 3, 0, 3); case LoongArch::BI__builtin_lsx_vstelm_d: - return SemaBuiltinConstantArgRange(TheCall, 2, -1024, 1016) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 1); + return BuiltinConstantArgRange(TheCall, 2, -1024, 1016) || + BuiltinConstantArgRange(TheCall, 3, 0, 1); case LoongArch::BI__builtin_lsx_vldrepl_b: case LoongArch::BI__builtin_lsx_vld: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2047); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2047); case LoongArch::BI__builtin_lsx_vldrepl_h: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2046); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2046); case LoongArch::BI__builtin_lsx_vldrepl_w: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2044); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2044); case LoongArch::BI__builtin_lsx_vldrepl_d: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2040); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2040); case LoongArch::BI__builtin_lsx_vst: - return SemaBuiltinConstantArgRange(TheCall, 2, -2048, 2047); + return BuiltinConstantArgRange(TheCall, 2, -2048, 2047); case LoongArch::BI__builtin_lsx_vldi: - return SemaBuiltinConstantArgRange(TheCall, 0, -4096, 4095); + return BuiltinConstantArgRange(TheCall, 0, -4096, 4095); case LoongArch::BI__builtin_lsx_vrepli_b: case LoongArch::BI__builtin_lsx_vrepli_h: case LoongArch::BI__builtin_lsx_vrepli_w: case LoongArch::BI__builtin_lsx_vrepli_d: - return SemaBuiltinConstantArgRange(TheCall, 0, -512, 511); + return BuiltinConstantArgRange(TheCall, 0, -512, 511); // LASX intrinsics. case LoongArch::BI__builtin_lasx_xvbitclri_b: @@ -4717,7 +4712,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvsllwil_hu_bu: case LoongArch::BI__builtin_lasx_xvrotri_b: case LoongArch::BI__builtin_lasx_xvsrlri_b: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7); + return BuiltinConstantArgRange(TheCall, 1, 0, 7); case LoongArch::BI__builtin_lasx_xvbitclri_h: case LoongArch::BI__builtin_lasx_xvbitrevi_h: case LoongArch::BI__builtin_lasx_xvbitseti_h: @@ -4731,7 +4726,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvsllwil_wu_hu: case LoongArch::BI__builtin_lasx_xvrotri_h: case LoongArch::BI__builtin_lasx_xvsrlri_h: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15); case LoongArch::BI__builtin_lasx_xvssrarni_b_h: case LoongArch::BI__builtin_lasx_xvssrarni_bu_h: case LoongArch::BI__builtin_lasx_xvssrani_b_h: @@ -4744,7 +4739,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvssrlrni_b_h: case LoongArch::BI__builtin_lasx_xvssrlrni_bu_h: case LoongArch::BI__builtin_lasx_xvsrani_b_h: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); + return BuiltinConstantArgRange(TheCall, 2, 0, 15); case LoongArch::BI__builtin_lasx_xvslei_bu: case LoongArch::BI__builtin_lasx_xvslei_hu: case LoongArch::BI__builtin_lasx_xvslei_wu: @@ -4784,7 +4779,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvsubi_du: case LoongArch::BI__builtin_lasx_xvbsrl_v: case LoongArch::BI__builtin_lasx_xvbsll_v: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + return BuiltinConstantArgRange(TheCall, 1, 0, 31); case LoongArch::BI__builtin_lasx_xvssrarni_h_w: case LoongArch::BI__builtin_lasx_xvssrarni_hu_w: case LoongArch::BI__builtin_lasx_xvssrani_h_w: @@ -4799,7 +4794,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvssrlni_hu_w: case LoongArch::BI__builtin_lasx_xvssrlrni_h_w: case LoongArch::BI__builtin_lasx_xvssrlrni_hu_w: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); + return BuiltinConstantArgRange(TheCall, 2, 0, 31); case LoongArch::BI__builtin_lasx_xvbitclri_d: case LoongArch::BI__builtin_lasx_xvbitrevi_d: case LoongArch::BI__builtin_lasx_xvbitseti_d: @@ -4811,7 +4806,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvsrari_d: case LoongArch::BI__builtin_lasx_xvrotri_d: case LoongArch::BI__builtin_lasx_xvsrlri_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 63); + return BuiltinConstantArgRange(TheCall, 1, 0, 63); case LoongArch::BI__builtin_lasx_xvssrarni_w_d: case LoongArch::BI__builtin_lasx_xvssrarni_wu_d: case LoongArch::BI__builtin_lasx_xvssrani_w_d: @@ -4824,7 +4819,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvssrlrni_w_d: case LoongArch::BI__builtin_lasx_xvssrlrni_wu_d: case LoongArch::BI__builtin_lasx_xvsrani_w_d: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 63); + return BuiltinConstantArgRange(TheCall, 2, 0, 63); case LoongArch::BI__builtin_lasx_xvssrarni_d_q: case LoongArch::BI__builtin_lasx_xvssrarni_du_q: case LoongArch::BI__builtin_lasx_xvssrani_d_q: @@ -4837,7 +4832,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvsrani_d_q: case LoongArch::BI__builtin_lasx_xvsrlni_d_q: case LoongArch::BI__builtin_lasx_xvsrlrni_d_q: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 127); + return BuiltinConstantArgRange(TheCall, 2, 0, 127); case LoongArch::BI__builtin_lasx_xvseqi_b: case LoongArch::BI__builtin_lasx_xvseqi_h: case LoongArch::BI__builtin_lasx_xvseqi_w: @@ -4858,7 +4853,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvmini_h: case LoongArch::BI__builtin_lasx_xvmini_w: case LoongArch::BI__builtin_lasx_xvmini_d: - return SemaBuiltinConstantArgRange(TheCall, 1, -16, 15); + return BuiltinConstantArgRange(TheCall, 1, -16, 15); case LoongArch::BI__builtin_lasx_xvandi_b: case LoongArch::BI__builtin_lasx_xvnori_b: case LoongArch::BI__builtin_lasx_xvori_b: @@ -4867,7 +4862,7 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvshuf4i_w: case LoongArch::BI__builtin_lasx_xvxori_b: case LoongArch::BI__builtin_lasx_xvpermi_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 255); + return BuiltinConstantArgRange(TheCall, 1, 0, 255); case LoongArch::BI__builtin_lasx_xvbitseli_b: case LoongArch::BI__builtin_lasx_xvshuf4i_d: case LoongArch::BI__builtin_lasx_xvextrins_b: @@ -4876,59 +4871,59 @@ bool Sema::CheckLoongArchBuiltinFunctionCall(const TargetInfo &TI, case LoongArch::BI__builtin_lasx_xvextrins_d: case LoongArch::BI__builtin_lasx_xvpermi_q: case LoongArch::BI__builtin_lasx_xvpermi_w: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 255); + return BuiltinConstantArgRange(TheCall, 2, 0, 255); case LoongArch::BI__builtin_lasx_xvrepl128vei_b: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15); case LoongArch::BI__builtin_lasx_xvrepl128vei_h: case LoongArch::BI__builtin_lasx_xvpickve2gr_w: case LoongArch::BI__builtin_lasx_xvpickve2gr_wu: case LoongArch::BI__builtin_lasx_xvpickve_w_f: case LoongArch::BI__builtin_lasx_xvpickve_w: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 7); + return BuiltinConstantArgRange(TheCall, 1, 0, 7); case LoongArch::BI__builtin_lasx_xvinsgr2vr_w: case LoongArch::BI__builtin_lasx_xvinsve0_w: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7); + return BuiltinConstantArgRange(TheCall, 2, 0, 7); case LoongArch::BI__builtin_lasx_xvrepl128vei_w: case LoongArch::BI__builtin_lasx_xvpickve2gr_d: case LoongArch::BI__builtin_lasx_xvpickve2gr_du: case LoongArch::BI__builtin_lasx_xvpickve_d_f: case LoongArch::BI__builtin_lasx_xvpickve_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3); + return BuiltinConstantArgRange(TheCall, 1, 0, 3); case LoongArch::BI__builtin_lasx_xvinsve0_d: case LoongArch::BI__builtin_lasx_xvinsgr2vr_d: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 3); case LoongArch::BI__builtin_lasx_xvstelm_b: - return SemaBuiltinConstantArgRange(TheCall, 2, -128, 127) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 31); + return BuiltinConstantArgRange(TheCall, 2, -128, 127) || + BuiltinConstantArgRange(TheCall, 3, 0, 31); case LoongArch::BI__builtin_lasx_xvstelm_h: - return SemaBuiltinConstantArgRange(TheCall, 2, -256, 254) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 15); + return BuiltinConstantArgRange(TheCall, 2, -256, 254) || + BuiltinConstantArgRange(TheCall, 3, 0, 15); case LoongArch::BI__builtin_lasx_xvstelm_w: - return SemaBuiltinConstantArgRange(TheCall, 2, -512, 508) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 7); + return BuiltinConstantArgRange(TheCall, 2, -512, 508) || + BuiltinConstantArgRange(TheCall, 3, 0, 7); case LoongArch::BI__builtin_lasx_xvstelm_d: - return SemaBuiltinConstantArgRange(TheCall, 2, -1024, 1016) || - SemaBuiltinConstantArgRange(TheCall, 3, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, -1024, 1016) || + BuiltinConstantArgRange(TheCall, 3, 0, 3); case LoongArch::BI__builtin_lasx_xvrepl128vei_d: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1); case LoongArch::BI__builtin_lasx_xvldrepl_b: case LoongArch::BI__builtin_lasx_xvld: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2047); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2047); case LoongArch::BI__builtin_lasx_xvldrepl_h: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2046); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2046); case LoongArch::BI__builtin_lasx_xvldrepl_w: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2044); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2044); case LoongArch::BI__builtin_lasx_xvldrepl_d: - return SemaBuiltinConstantArgRange(TheCall, 1, -2048, 2040); + return BuiltinConstantArgRange(TheCall, 1, -2048, 2040); case LoongArch::BI__builtin_lasx_xvst: - return SemaBuiltinConstantArgRange(TheCall, 2, -2048, 2047); + return BuiltinConstantArgRange(TheCall, 2, -2048, 2047); case LoongArch::BI__builtin_lasx_xvldi: - return SemaBuiltinConstantArgRange(TheCall, 0, -4096, 4095); + return BuiltinConstantArgRange(TheCall, 0, -4096, 4095); case LoongArch::BI__builtin_lasx_xvrepli_b: case LoongArch::BI__builtin_lasx_xvrepli_h: case LoongArch::BI__builtin_lasx_xvrepli_w: case LoongArch::BI__builtin_lasx_xvrepli_d: - return SemaBuiltinConstantArgRange(TheCall, 0, -512, 511); + return BuiltinConstantArgRange(TheCall, 0, -512, 511); } return false; } @@ -5144,10 +5139,10 @@ bool Sema::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) { } if (!m) - return SemaBuiltinConstantArgRange(TheCall, i, l, u); + return BuiltinConstantArgRange(TheCall, i, l, u); - return SemaBuiltinConstantArgRange(TheCall, i, l, u) || - SemaBuiltinConstantArgMultiple(TheCall, i, m); + return BuiltinConstantArgRange(TheCall, i, l, u) || + BuiltinConstantArgMultiple(TheCall, i, m); } /// DecodePPCMMATypeFromStr - This decodes one PPC MMA type descriptor from Str, @@ -5247,7 +5242,7 @@ static bool isPPC_64Builtin(unsigned BuiltinID) { /// number of 0s on either side. The 1s are allowed to wrap from LSB to MSB, so /// 0x000FFF0, 0x0000FFFF, 0xFF0000FF, 0x0 are all runs. 0x0F0F0000 is not, /// since all 1s are not contiguous. -bool Sema::SemaValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum) { +bool Sema::ValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum) { llvm::APSInt Result; // We can't check the value of a dependent argument. Expr *Arg = TheCall->getArg(ArgNum); @@ -5255,7 +5250,7 @@ bool Sema::SemaValueIsRunOfOnes(CallExpr *TheCall, unsigned ArgNum) { return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; // Check contiguous run of 1s, 0xFF0000FF is also a run of 1s. @@ -5281,27 +5276,27 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, default: return false; case PPC::BI__builtin_altivec_crypto_vshasigmaw: case PPC::BI__builtin_altivec_crypto_vshasigmad: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 1) || + BuiltinConstantArgRange(TheCall, 2, 0, 15); case PPC::BI__builtin_altivec_dss: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3); + return BuiltinConstantArgRange(TheCall, 0, 0, 3); case PPC::BI__builtin_tbegin: case PPC::BI__builtin_tend: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); + return BuiltinConstantArgRange(TheCall, 0, 0, 1); case PPC::BI__builtin_tsr: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7); + return BuiltinConstantArgRange(TheCall, 0, 0, 7); case PPC::BI__builtin_tabortwc: case PPC::BI__builtin_tabortdc: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31); + return BuiltinConstantArgRange(TheCall, 0, 0, 31); case PPC::BI__builtin_tabortwci: case PPC::BI__builtin_tabortdci: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); + return BuiltinConstantArgRange(TheCall, 0, 0, 31) || + BuiltinConstantArgRange(TheCall, 2, 0, 31); // According to GCC 'Basic PowerPC Built-in Functions Available on ISA 2.05', // __builtin_(un)pack_longdouble are available only if long double uses IBM // extended double representation. case PPC::BI__builtin_unpack_longdouble: - if (SemaBuiltinConstantArgRange(TheCall, 1, 0, 1)) + if (BuiltinConstantArgRange(TheCall, 1, 0, 1)) return true; [[fallthrough]]; case PPC::BI__builtin_pack_longdouble: @@ -5313,39 +5308,39 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, case PPC::BI__builtin_altivec_dstt: case PPC::BI__builtin_altivec_dstst: case PPC::BI__builtin_altivec_dststt: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 3); case PPC::BI__builtin_vsx_xxpermdi: case PPC::BI__builtin_vsx_xxsldwi: - return SemaBuiltinVSX(TheCall); + return BuiltinVSX(TheCall); case PPC::BI__builtin_unpack_vector_int128: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1); case PPC::BI__builtin_altivec_vgnb: - return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7); + return BuiltinConstantArgRange(TheCall, 1, 2, 7); case PPC::BI__builtin_vsx_xxeval: - return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255); + return BuiltinConstantArgRange(TheCall, 3, 0, 255); case PPC::BI__builtin_altivec_vsldbi: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7); + return BuiltinConstantArgRange(TheCall, 2, 0, 7); case PPC::BI__builtin_altivec_vsrdbi: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7); + return BuiltinConstantArgRange(TheCall, 2, 0, 7); case PPC::BI__builtin_vsx_xxpermx: - return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7); + return BuiltinConstantArgRange(TheCall, 3, 0, 7); case PPC::BI__builtin_ppc_tw: case PPC::BI__builtin_ppc_tdw: - return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31); + return BuiltinConstantArgRange(TheCall, 2, 1, 31); case PPC::BI__builtin_ppc_cmprb: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); + return BuiltinConstantArgRange(TheCall, 0, 0, 1); // For __rlwnm, __rlwimi and __rldimi, the last parameter mask must // be a constant that represents a contiguous bit field. case PPC::BI__builtin_ppc_rlwnm: - return SemaValueIsRunOfOnes(TheCall, 2); + return ValueIsRunOfOnes(TheCall, 2); case PPC::BI__builtin_ppc_rlwimi: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) || - SemaValueIsRunOfOnes(TheCall, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 31) || + ValueIsRunOfOnes(TheCall, 3); case PPC::BI__builtin_ppc_rldimi: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 63) || - SemaValueIsRunOfOnes(TheCall, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 63) || + ValueIsRunOfOnes(TheCall, 3); case PPC::BI__builtin_ppc_addex: { - if (SemaBuiltinConstantArgRange(TheCall, 2, 0, 3)) + if (BuiltinConstantArgRange(TheCall, 2, 0, 3)) return true; // Output warning for reserved values 1 to 3. int ArgValue = @@ -5357,29 +5352,29 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, } case PPC::BI__builtin_ppc_mtfsb0: case PPC::BI__builtin_ppc_mtfsb1: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31); + return BuiltinConstantArgRange(TheCall, 0, 0, 31); case PPC::BI__builtin_ppc_mtfsf: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 255); + return BuiltinConstantArgRange(TheCall, 0, 0, 255); case PPC::BI__builtin_ppc_mtfsfi: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 7) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 0, 0, 7) || + BuiltinConstantArgRange(TheCall, 1, 0, 15); case PPC::BI__builtin_ppc_alignx: - return SemaBuiltinConstantArgPower2(TheCall, 0); + return BuiltinConstantArgPower2(TheCall, 0); case PPC::BI__builtin_ppc_rdlam: - return SemaValueIsRunOfOnes(TheCall, 2); + return ValueIsRunOfOnes(TheCall, 2); case PPC::BI__builtin_vsx_ldrmb: case PPC::BI__builtin_vsx_strmb: - return SemaBuiltinConstantArgRange(TheCall, 1, 1, 16); + return BuiltinConstantArgRange(TheCall, 1, 1, 16); case PPC::BI__builtin_altivec_vcntmbb: case PPC::BI__builtin_altivec_vcntmbh: case PPC::BI__builtin_altivec_vcntmbw: case PPC::BI__builtin_altivec_vcntmbd: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1); + return BuiltinConstantArgRange(TheCall, 1, 0, 1); case PPC::BI__builtin_vsx_xxgenpcvbm: case PPC::BI__builtin_vsx_xxgenpcvhm: case PPC::BI__builtin_vsx_xxgenpcvwm: case PPC::BI__builtin_vsx_xxgenpcvdm: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3); + return BuiltinConstantArgRange(TheCall, 1, 0, 3); case PPC::BI__builtin_ppc_test_data_class: { // Check if the first argument of the __builtin_ppc_test_data_class call is // valid. The argument must be 'float' or 'double' or '__float128'. @@ -5389,7 +5384,7 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, ArgType != QualType(Context.Float128Ty)) return Diag(TheCall->getBeginLoc(), diag::err_ppc_invalid_test_data_class_type); - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 127); + return BuiltinConstantArgRange(TheCall, 1, 0, 127); } case PPC::BI__builtin_ppc_maxfe: case PPC::BI__builtin_ppc_minfe: @@ -5418,12 +5413,12 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, << TheCall->getArg(I)->getType() << ArgType << 1 << 0 << 0; return false; } -#define CUSTOM_BUILTIN(Name, Intr, Types, Acc, Feature) \ +#define CUSTOM_BUILTIN(Name, Intr, Types, Acc, Feature) \ case PPC::BI__builtin_##Name: \ - return SemaBuiltinPPCMMACall(TheCall, BuiltinID, Types); + return BuiltinPPCMMACall(TheCall, BuiltinID, Types); #include "clang/Basic/BuiltinsPPC.def" } - return SemaBuiltinConstantArgRange(TheCall, i, l, u); + return BuiltinConstantArgRange(TheCall, i, l, u); } // Check if the given type is a non-pointer PPC MMA type. This function is used @@ -5574,7 +5569,7 @@ bool Sema::CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; if (CheckVectorElementCallArgs(this, TheCall)) return true; - if (SemaBuiltinElementwiseTernaryMath( + if (BuiltinElementwiseTernaryMath( TheCall, /*CheckForFloatArgs*/ TheCall->getArg(0)->getType()->hasFloatingRepresentation())) return true; @@ -5585,7 +5580,7 @@ bool Sema::CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; if (CheckVectorElementCallArgs(this, TheCall)) return true; - if (SemaBuiltinVectorToScalarMath(TheCall)) + if (BuiltinVectorToScalarMath(TheCall)) return true; if (CheckNoDoubleVectors(this, TheCall)) return true; @@ -5619,7 +5614,7 @@ bool Sema::CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; if (CheckVectorElementCallArgs(this, TheCall)) return true; - if (SemaBuiltinElementwiseTernaryMath(TheCall)) + if (BuiltinElementwiseTernaryMath(TheCall)) return true; if (CheckFloatOrHalfRepresentations(this, TheCall)) return true; @@ -5630,7 +5625,7 @@ bool Sema::CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { return true; if (CheckVectorElementCallArgs(this, TheCall)) return true; - if (SemaBuiltinElementwiseTernaryMath( + if (BuiltinElementwiseTernaryMath( TheCall, /*CheckForFloatArgs*/ TheCall->getArg(0)->getType()->hasFloatingRepresentation())) return true; @@ -5737,7 +5732,7 @@ bool Sema::CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum) { return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; int64_t Val = Result.getSExtValue(); @@ -5847,10 +5842,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, switch (BuiltinID) { case RISCVVector::BI__builtin_rvv_vsetvli: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 3) || + return BuiltinConstantArgRange(TheCall, 1, 0, 3) || CheckRISCVLMUL(TheCall, 2); case RISCVVector::BI__builtin_rvv_vsetvlimax: - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || CheckRISCVLMUL(TheCall, 1); case RISCVVector::BI__builtin_rvv_vget_v: { ASTContext::BuiltinVectorTypeInfo ResVecInfo = @@ -5865,7 +5860,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, else // vget for non-tuple type MaxIndex = (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors) / (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors); - return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1); + return BuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1); } case RISCVVector::BI__builtin_rvv_vset_v: { ASTContext::BuiltinVectorTypeInfo ResVecInfo = @@ -5880,7 +5875,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, else // vset fo non-tuple type MaxIndex = (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors) / (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors); - return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1); + return BuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1); } // Vector Crypto case RISCVVector::BI__builtin_rvv_vaeskf1_vi_tu: @@ -5891,19 +5886,19 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, QualType Op2Type = TheCall->getArg(1)->getType(); return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, 128) || CheckInvalidVLENandLMUL(TI, TheCall, *this, Op2Type, 128) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); + BuiltinConstantArgRange(TheCall, 2, 0, 31); } case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu: case RISCVVector::BI__builtin_rvv_vsm3c_vi: { QualType Op1Type = TheCall->getArg(0)->getType(); return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, 256) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31); + BuiltinConstantArgRange(TheCall, 2, 0, 31); } case RISCVVector::BI__builtin_rvv_vaeskf1_vi: case RISCVVector::BI__builtin_rvv_vsm4k_vi: { QualType Op1Type = TheCall->getArg(0)->getType(); return CheckInvalidVLENandLMUL(TI, TheCall, *this, Op1Type, 128) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + BuiltinConstantArgRange(TheCall, 1, 0, 31); } case RISCVVector::BI__builtin_rvv_vaesdf_vv: case RISCVVector::BI__builtin_rvv_vaesdf_vs: @@ -5956,27 +5951,27 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_sf_vc_i_se: // bit_27_26, bit_24_20, bit_11_7, simm5, sew, log2lmul - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 3, -16, 15) || + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 1, 0, 31) || + BuiltinConstantArgRange(TheCall, 2, 0, 31) || + BuiltinConstantArgRange(TheCall, 3, -16, 15) || CheckRISCVLMUL(TheCall, 5); case RISCVVector::BI__builtin_rvv_sf_vc_iv_se: // bit_27_26, bit_11_7, vs2, simm5 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 3, -16, 15); + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 1, 0, 31) || + BuiltinConstantArgRange(TheCall, 3, -16, 15); case RISCVVector::BI__builtin_rvv_sf_vc_v_i: case RISCVVector::BI__builtin_rvv_sf_vc_v_i_se: // bit_27_26, bit_24_20, simm5 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 2, -16, 15); + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 1, 0, 31) || + BuiltinConstantArgRange(TheCall, 2, -16, 15); case RISCVVector::BI__builtin_rvv_sf_vc_v_iv: case RISCVVector::BI__builtin_rvv_sf_vc_v_iv_se: // bit_27_26, vs2, simm5 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 2, -16, 15); + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 2, -16, 15); case RISCVVector::BI__builtin_rvv_sf_vc_ivv_se: case RISCVVector::BI__builtin_rvv_sf_vc_ivw_se: case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv: @@ -5984,13 +5979,13 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_sf_vc_v_ivv_se: case RISCVVector::BI__builtin_rvv_sf_vc_v_ivw_se: // bit_27_26, vd, vs2, simm5 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 3, -16, 15); + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 3, -16, 15); case RISCVVector::BI__builtin_rvv_sf_vc_x_se: // bit_27_26, bit_24_20, bit_11_7, xs1, sew, log2lmul - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 31) || + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 1, 0, 31) || + BuiltinConstantArgRange(TheCall, 2, 0, 31) || CheckRISCVLMUL(TheCall, 5); case RISCVVector::BI__builtin_rvv_sf_vc_xv_se: case RISCVVector::BI__builtin_rvv_sf_vc_vv_se: @@ -5998,8 +5993,8 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_sf_vc_v_x: case RISCVVector::BI__builtin_rvv_sf_vc_v_x_se: // bit_27_26, bit_24-20, xs1 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + return BuiltinConstantArgRange(TheCall, 0, 0, 3) || + BuiltinConstantArgRange(TheCall, 1, 0, 31); case RISCVVector::BI__builtin_rvv_sf_vc_vvv_se: case RISCVVector::BI__builtin_rvv_sf_vc_xvv_se: case RISCVVector::BI__builtin_rvv_sf_vc_vvw_se: @@ -6019,11 +6014,11 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_sf_vc_v_xvw_se: case RISCVVector::BI__builtin_rvv_sf_vc_v_vvw_se: // bit_27_26, vd, vs2, xs1/vs1 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 3); + return BuiltinConstantArgRange(TheCall, 0, 0, 3); case RISCVVector::BI__builtin_rvv_sf_vc_fv_se: // bit_26, bit_11_7, vs2, fs1 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1) || - SemaBuiltinConstantArgRange(TheCall, 1, 0, 31); + return BuiltinConstantArgRange(TheCall, 0, 0, 1) || + BuiltinConstantArgRange(TheCall, 1, 0, 31); case RISCVVector::BI__builtin_rvv_sf_vc_fvv_se: case RISCVVector::BI__builtin_rvv_sf_vc_fvw_se: case RISCVVector::BI__builtin_rvv_sf_vc_v_fvv: @@ -6034,7 +6029,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_sf_vc_v_fv: case RISCVVector::BI__builtin_rvv_sf_vc_v_fv_se: // bit_26, vs2, fs1 - return SemaBuiltinConstantArgRange(TheCall, 0, 0, 1); + return BuiltinConstantArgRange(TheCall, 0, 0, 1); // Check if byteselect is in [0, 3] case RISCV::BI__builtin_riscv_aes32dsi: case RISCV::BI__builtin_riscv_aes32dsmi: @@ -6042,10 +6037,10 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCV::BI__builtin_riscv_aes32esmi: case RISCV::BI__builtin_riscv_sm4ks: case RISCV::BI__builtin_riscv_sm4ed: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 3); // Check if rnum is in [0, 10] case RISCV::BI__builtin_riscv_aes64ks1i: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 10); + return BuiltinConstantArgRange(TheCall, 1, 0, 10); // Check if value range for vxrm is in [0, 3] case RISCVVector::BI__builtin_rvv_vaaddu_vv: case RISCVVector::BI__builtin_rvv_vaaddu_vx: @@ -6065,7 +6060,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vnclip_wx: case RISCVVector::BI__builtin_rvv_vnclipu_wv: case RISCVVector::BI__builtin_rvv_vnclipu_wx: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 3); + return BuiltinConstantArgRange(TheCall, 2, 0, 3); case RISCVVector::BI__builtin_rvv_vaaddu_vv_tu: case RISCVVector::BI__builtin_rvv_vaaddu_vx_tu: case RISCVVector::BI__builtin_rvv_vaadd_vv_tu: @@ -6102,7 +6097,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vnclip_wx_m: case RISCVVector::BI__builtin_rvv_vnclipu_wv_m: case RISCVVector::BI__builtin_rvv_vnclipu_wx_m: - return SemaBuiltinConstantArgRange(TheCall, 3, 0, 3); + return BuiltinConstantArgRange(TheCall, 3, 0, 3); case RISCVVector::BI__builtin_rvv_vaaddu_vv_tum: case RISCVVector::BI__builtin_rvv_vaaddu_vv_tumu: case RISCVVector::BI__builtin_rvv_vaaddu_vv_mu: @@ -6157,7 +6152,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vnclip_wx_tumu: case RISCVVector::BI__builtin_rvv_vnclipu_wv_tumu: case RISCVVector::BI__builtin_rvv_vnclipu_wx_tumu: - return SemaBuiltinConstantArgRange(TheCall, 4, 0, 3); + return BuiltinConstantArgRange(TheCall, 4, 0, 3); case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm: case RISCVVector::BI__builtin_rvv_vfrec7_v_rm: case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm: @@ -6171,7 +6166,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm: case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 4); + return BuiltinConstantArgRange(TheCall, 1, 0, 4); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm: @@ -6222,7 +6217,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m: case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m: - return SemaBuiltinConstantArgRange(TheCall, 2, 0, 4); + return BuiltinConstantArgRange(TheCall, 2, 0, 4); case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tu: @@ -6358,7 +6353,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu: case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu: case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu: - return SemaBuiltinConstantArgRange(TheCall, 3, 0, 4); + return BuiltinConstantArgRange(TheCall, 3, 0, 4); case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m: case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m: case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_m: @@ -6519,7 +6514,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu: - return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4); + return BuiltinConstantArgRange(TheCall, 4, 0, 4); case RISCV::BI__builtin_riscv_ntl_load: case RISCV::BI__builtin_riscv_ntl_store: DeclRefExpr *DRE = @@ -6539,7 +6534,7 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI, // Domain value should be compile-time constant. // 2 <= domain <= 5 if (TheCall->getNumArgs() == NumArgs && - SemaBuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5)) + BuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5)) return true; Expr *PointerArg = TheCall->getArg(0); @@ -6623,8 +6618,8 @@ bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, case SystemZ::BI__builtin_s390_vfaezfs: i = 2; l = 0; u = 15; break; case SystemZ::BI__builtin_s390_vfisb: case SystemZ::BI__builtin_s390_vfidb: - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15) || - SemaBuiltinConstantArgRange(TheCall, 2, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15) || + BuiltinConstantArgRange(TheCall, 2, 0, 15); case SystemZ::BI__builtin_s390_vftcisb: case SystemZ::BI__builtin_s390_vftcidb: i = 1; l = 0; u = 4095; break; case SystemZ::BI__builtin_s390_vlbb: i = 1; l = 0; u = 15; break; @@ -6655,7 +6650,7 @@ bool Sema::CheckSystemZBuiltinFunctionCall(unsigned BuiltinID, case SystemZ::BI__builtin_s390_vcnf: i = 1; l = 0; u = 15; break; case SystemZ::BI__builtin_s390_vcrnfs: i = 2; l = 0; u = 15; break; } - return SemaBuiltinConstantArgRange(TheCall, i, l, u); + return BuiltinConstantArgRange(TheCall, i, l, u); } bool Sema::CheckWebAssemblyBuiltinFunctionCall(const TargetInfo &TI, @@ -7008,7 +7003,7 @@ bool Sema::CheckX86BuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) { return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; // Make sure rounding mode is either ROUND_CUR_DIRECTION or ROUND_NO_EXC bit @@ -7118,7 +7113,7 @@ bool Sema::CheckX86BuiltinGatherScatterScale(unsigned BuiltinID, return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; if (Result == 1 || Result == 2 || Result == 4 || Result == 8) @@ -7133,7 +7128,7 @@ enum { TileRegLow = 0, TileRegHigh = 7 }; bool Sema::CheckX86BuiltinTileArgumentsRange(CallExpr *TheCall, ArrayRef ArgNums) { for (int ArgNum : ArgNums) { - if (SemaBuiltinConstantArgRange(TheCall, ArgNum, TileRegLow, TileRegHigh)) + if (BuiltinConstantArgRange(TheCall, ArgNum, TileRegLow, TileRegHigh)) return true; } return false; @@ -7150,7 +7145,7 @@ bool Sema::CheckX86BuiltinTileDuplicate(CallExpr *TheCall, continue; llvm::APSInt Result; - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; int ArgExtValue = Result.getExtValue(); assert((ArgExtValue >= TileRegLow && ArgExtValue <= TileRegHigh) && @@ -7576,7 +7571,7 @@ bool Sema::CheckX86BuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID, // template-generated or macro-generated dead code to potentially have out-of- // range values. These need to code generate, but don't need to necessarily // make any sense. We use a warning that defaults to an error. - return SemaBuiltinConstantArgRange(TheCall, i, l, u, /*RangeIsError*/ false); + return BuiltinConstantArgRange(TheCall, i, l, u, /*RangeIsError*/ false); } /// Given a FunctionDecl's FormatAttr, attempts to populate the FomatStringInfo @@ -8237,8 +8232,8 @@ static bool isValidOrderingForOp(int64_t Ordering, AtomicExpr::AtomicOp Op) { } } -ExprResult Sema::SemaAtomicOpsOverloaded(ExprResult TheCallResult, - AtomicExpr::AtomicOp Op) { +ExprResult Sema::AtomicOpsOverloaded(ExprResult TheCallResult, + AtomicExpr::AtomicOp Op) { CallExpr *TheCall = cast(TheCallResult.get()); DeclRefExpr *DRE =cast(TheCall->getCallee()->IgnoreParenCasts()); MultiExprArg Args{TheCall->getArgs(), TheCall->getNumArgs()}; @@ -8867,8 +8862,7 @@ bool Sema::BuiltinWasmRefNullFunc(CallExpr *TheCall) { /// /// This function goes through and does final semantic checking for these /// builtins, as well as generating any warnings. -ExprResult -Sema::SemaBuiltinAtomicOverloaded(ExprResult TheCallResult) { +ExprResult Sema::BuiltinAtomicOverloaded(ExprResult TheCallResult) { CallExpr *TheCall = static_cast(TheCallResult.get()); Expr *Callee = TheCall->getCallee(); DeclRefExpr *DRE = cast(Callee->IgnoreParenCasts()); @@ -9239,13 +9233,13 @@ Sema::SemaBuiltinAtomicOverloaded(ExprResult TheCallResult) { return TheCallResult; } -/// SemaBuiltinNontemporalOverloaded - We have a call to +/// BuiltinNontemporalOverloaded - We have a call to /// __builtin_nontemporal_store or __builtin_nontemporal_load, which is an /// overloaded function based on the pointer type of its last argument. /// /// This function goes through and does final semantic checking for these /// builtins. -ExprResult Sema::SemaBuiltinNontemporalOverloaded(ExprResult TheCallResult) { +ExprResult Sema::BuiltinNontemporalOverloaded(ExprResult TheCallResult) { CallExpr *TheCall = (CallExpr *)TheCallResult.get(); DeclRefExpr *DRE = cast(TheCall->getCallee()->IgnoreParenCasts()); @@ -9446,7 +9440,7 @@ static bool checkVAStartIsInVariadicFunction(Sema &S, Expr *Fn, /// Check the arguments to '__builtin_va_start' or '__builtin_ms_va_start' /// for validity. Emit an error and return true on failure; return false /// on success. -bool Sema::SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall) { +bool Sema::BuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall) { Expr *Fn = TheCall->getCallee(); if (checkVAStartABI(*this, BuiltinID, Fn)) @@ -9520,7 +9514,7 @@ bool Sema::SemaBuiltinVAStart(unsigned BuiltinID, CallExpr *TheCall) { return false; } -bool Sema::SemaBuiltinVAStartARMMicrosoft(CallExpr *Call) { +bool Sema::BuiltinVAStartARMMicrosoft(CallExpr *Call) { auto IsSuitablyTypedFormatArgument = [this](const Expr *Arg) -> bool { const LangOptions &LO = getLangOpts(); @@ -9583,9 +9577,9 @@ bool Sema::SemaBuiltinVAStartARMMicrosoft(CallExpr *Call) { return false; } -/// SemaBuiltinUnorderedCompare - Handle functions like __builtin_isgreater and +/// BuiltinUnorderedCompare - Handle functions like __builtin_isgreater and /// friends. This is declared to take (...), so we have to check everything. -bool Sema::SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID) { +bool Sema::BuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID) { if (checkArgCount(*this, TheCall, 2)) return true; @@ -9625,11 +9619,11 @@ bool Sema::SemaBuiltinUnorderedCompare(CallExpr *TheCall, unsigned BuiltinID) { return false; } -/// SemaBuiltinSemaBuiltinFPClassification - Handle functions like +/// BuiltinSemaBuiltinFPClassification - Handle functions like /// __builtin_isnan and friends. This is declared to take (...), so we have /// to check everything. -bool Sema::SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, - unsigned BuiltinID) { +bool Sema::BuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, + unsigned BuiltinID) { if (checkArgCount(*this, TheCall, NumArgs)) return true; @@ -9697,7 +9691,7 @@ bool Sema::SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, // __builtin_isfpclass has integer parameter that specify test mask. It is // passed in (...), so it should be analyzed completely here. if (IsFPClass) - if (SemaBuiltinConstantArgRange(TheCall, 1, 0, llvm::fcAllFlags)) + if (BuiltinConstantArgRange(TheCall, 1, 0, llvm::fcAllFlags)) return true; // TODO: enable this code to all classification functions. @@ -9714,7 +9708,7 @@ bool Sema::SemaBuiltinFPClassification(CallExpr *TheCall, unsigned NumArgs, } /// Perform semantic analysis for a call to __builtin_complex. -bool Sema::SemaBuiltinComplex(CallExpr *TheCall) { +bool Sema::BuiltinComplex(CallExpr *TheCall) { if (checkArgCount(*this, TheCall, 2)) return true; @@ -9775,7 +9769,7 @@ bool Sema::SemaBuiltinComplex(CallExpr *TheCall) { // Example builtins are : // vector double vec_xxpermdi(vector double, vector double, int); // vector short vec_xxsldwi(vector short, vector short, int); -bool Sema::SemaBuiltinVSX(CallExpr *TheCall) { +bool Sema::BuiltinVSX(CallExpr *TheCall) { unsigned ExpectedNumArgs = 3; if (checkArgCount(*this, TheCall, ExpectedNumArgs)) return true; @@ -9817,9 +9811,9 @@ bool Sema::SemaBuiltinVSX(CallExpr *TheCall) { return false; } -/// SemaBuiltinShuffleVector - Handle __builtin_shufflevector. +/// BuiltinShuffleVector - Handle __builtin_shufflevector. // This is declared to take (...), so we have to check everything. -ExprResult Sema::SemaBuiltinShuffleVector(CallExpr *TheCall) { +ExprResult Sema::BuiltinShuffleVector(CallExpr *TheCall) { if (TheCall->getNumArgs() < 2) return ExprError(Diag(TheCall->getEndLoc(), diag::err_typecheck_call_too_few_args_at_least) @@ -9907,10 +9901,10 @@ ExprResult Sema::SemaBuiltinShuffleVector(CallExpr *TheCall) { TheCall->getRParenLoc()); } -/// SemaConvertVectorExpr - Handle __builtin_convertvector -ExprResult Sema::SemaConvertVectorExpr(Expr *E, TypeSourceInfo *TInfo, - SourceLocation BuiltinLoc, - SourceLocation RParenLoc) { +/// ConvertVectorExpr - Handle __builtin_convertvector +ExprResult Sema::ConvertVectorExpr(Expr *E, TypeSourceInfo *TInfo, + SourceLocation BuiltinLoc, + SourceLocation RParenLoc) { ExprValueKind VK = VK_PRValue; ExprObjectKind OK = OK_Ordinary; QualType DstTy = TInfo->getType(); @@ -9934,14 +9928,14 @@ ExprResult Sema::SemaConvertVectorExpr(Expr *E, TypeSourceInfo *TInfo, << E->getSourceRange()); } - return new (Context) - ConvertVectorExpr(E, TInfo, DstTy, VK, OK, BuiltinLoc, RParenLoc); + return new (Context) class ConvertVectorExpr(E, TInfo, DstTy, VK, OK, + BuiltinLoc, RParenLoc); } -/// SemaBuiltinPrefetch - Handle __builtin_prefetch. +/// BuiltinPrefetch - Handle __builtin_prefetch. // This is declared to take (const void*, ...) and can take two // optional constant int args. -bool Sema::SemaBuiltinPrefetch(CallExpr *TheCall) { +bool Sema::BuiltinPrefetch(CallExpr *TheCall) { unsigned NumArgs = TheCall->getNumArgs(); if (NumArgs > 3) @@ -9953,14 +9947,14 @@ bool Sema::SemaBuiltinPrefetch(CallExpr *TheCall) { // Argument 0 is checked for us and the remaining arguments must be // constant integers. for (unsigned i = 1; i != NumArgs; ++i) - if (SemaBuiltinConstantArgRange(TheCall, i, 0, i == 1 ? 1 : 3)) + if (BuiltinConstantArgRange(TheCall, i, 0, i == 1 ? 1 : 3)) return true; return false; } -/// SemaBuiltinArithmeticFence - Handle __arithmetic_fence. -bool Sema::SemaBuiltinArithmeticFence(CallExpr *TheCall) { +/// BuiltinArithmeticFence - Handle __arithmetic_fence. +bool Sema::BuiltinArithmeticFence(CallExpr *TheCall) { if (!Context.getTargetInfo().checkArithmeticFenceSupported()) return Diag(TheCall->getBeginLoc(), diag::err_builtin_target_unsupported) << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc()); @@ -9982,10 +9976,10 @@ bool Sema::SemaBuiltinArithmeticFence(CallExpr *TheCall) { return false; } -/// SemaBuiltinAssume - Handle __assume (MS Extension). +/// BuiltinAssume - Handle __assume (MS Extension). // __assume does not evaluate its arguments, and should warn if its argument // has side effects. -bool Sema::SemaBuiltinAssume(CallExpr *TheCall) { +bool Sema::BuiltinAssume(CallExpr *TheCall) { Expr *Arg = TheCall->getArg(0); if (Arg->isInstantiationDependent()) return false; @@ -10000,7 +9994,7 @@ bool Sema::SemaBuiltinAssume(CallExpr *TheCall) { /// Handle __builtin_alloca_with_align. This is declared /// as (size_t, size_t) where the second size_t must be a power of 2 greater /// than 8. -bool Sema::SemaBuiltinAllocaWithAlign(CallExpr *TheCall) { +bool Sema::BuiltinAllocaWithAlign(CallExpr *TheCall) { // The alignment must be a constant integer. Expr *Arg = TheCall->getArg(1); @@ -10033,7 +10027,7 @@ bool Sema::SemaBuiltinAllocaWithAlign(CallExpr *TheCall) { /// Handle __builtin_assume_aligned. This is declared /// as (const void*, size_t, ...) and can take one optional constant int arg. -bool Sema::SemaBuiltinAssumeAligned(CallExpr *TheCall) { +bool Sema::BuiltinAssumeAligned(CallExpr *TheCall) { if (checkArgCountRange(*this, TheCall, 2, 3)) return true; @@ -10055,7 +10049,7 @@ bool Sema::SemaBuiltinAssumeAligned(CallExpr *TheCall) { // We can't check the value of a dependent argument. if (!SecondArg->isValueDependent()) { llvm::APSInt Result; - if (SemaBuiltinConstantArg(TheCall, 1, Result)) + if (BuiltinConstantArg(TheCall, 1, Result)) return true; if (!Result.isPowerOf2()) @@ -10077,7 +10071,7 @@ bool Sema::SemaBuiltinAssumeAligned(CallExpr *TheCall) { return false; } -bool Sema::SemaBuiltinOSLogFormat(CallExpr *TheCall) { +bool Sema::BuiltinOSLogFormat(CallExpr *TheCall) { unsigned BuiltinID = cast(TheCall->getCalleeDecl())->getBuiltinID(); bool IsSizeCall = BuiltinID == Builtin::BI__builtin_os_log_format_buffer_size; @@ -10157,10 +10151,10 @@ bool Sema::SemaBuiltinOSLogFormat(CallExpr *TheCall) { return false; } -/// SemaBuiltinConstantArg - Handle a check if argument ArgNum of CallExpr +/// BuiltinConstantArg - Handle a check if argument ArgNum of CallExpr /// TheCall is a constant expression. -bool Sema::SemaBuiltinConstantArg(CallExpr *TheCall, int ArgNum, - llvm::APSInt &Result) { +bool Sema::BuiltinConstantArg(CallExpr *TheCall, int ArgNum, + llvm::APSInt &Result) { Expr *Arg = TheCall->getArg(ArgNum); DeclRefExpr *DRE =cast(TheCall->getCallee()->IgnoreParenCasts()); FunctionDecl *FDecl = cast(DRE->getDecl()); @@ -10175,10 +10169,10 @@ bool Sema::SemaBuiltinConstantArg(CallExpr *TheCall, int ArgNum, return false; } -/// SemaBuiltinConstantArgRange - Handle a check if argument ArgNum of CallExpr +/// BuiltinConstantArgRange - Handle a check if argument ArgNum of CallExpr /// TheCall is a constant expression in the range [Low, High]. -bool Sema::SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, - int Low, int High, bool RangeIsError) { +bool Sema::BuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, int Low, + int High, bool RangeIsError) { if (isConstantEvaluatedContext()) return false; llvm::APSInt Result; @@ -10189,7 +10183,7 @@ bool Sema::SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; if (Result.getSExtValue() < Low || Result.getSExtValue() > High) { @@ -10208,10 +10202,10 @@ bool Sema::SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum, return false; } -/// SemaBuiltinConstantArgMultiple - Handle a check if argument ArgNum of CallExpr +/// BuiltinConstantArgMultiple - Handle a check if argument ArgNum of CallExpr /// TheCall is a constant expression is a multiple of Num.. -bool Sema::SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum, - unsigned Num) { +bool Sema::BuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum, + unsigned Num) { llvm::APSInt Result; // We can't check the value of a dependent argument. @@ -10220,7 +10214,7 @@ bool Sema::SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum, return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; if (Result.getSExtValue() % Num != 0) @@ -10230,9 +10224,9 @@ bool Sema::SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum, return false; } -/// SemaBuiltinConstantArgPower2 - Check if argument ArgNum of TheCall is a +/// BuiltinConstantArgPower2 - Check if argument ArgNum of TheCall is a /// constant expression representing a power of 2. -bool Sema::SemaBuiltinConstantArgPower2(CallExpr *TheCall, int ArgNum) { +bool Sema::BuiltinConstantArgPower2(CallExpr *TheCall, int ArgNum) { llvm::APSInt Result; // We can't check the value of a dependent argument. @@ -10241,7 +10235,7 @@ bool Sema::SemaBuiltinConstantArgPower2(CallExpr *TheCall, int ArgNum) { return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; // Bit-twiddling to test for a power of 2: for x > 0, x & (x-1) is zero if @@ -10275,11 +10269,11 @@ static bool IsShiftedByte(llvm::APSInt Value) { } } -/// SemaBuiltinConstantArgShiftedByte - Check if argument ArgNum of TheCall is +/// BuiltinConstantArgShiftedByte - Check if argument ArgNum of TheCall is /// a constant expression representing an arbitrary byte value shifted left by /// a multiple of 8 bits. -bool Sema::SemaBuiltinConstantArgShiftedByte(CallExpr *TheCall, int ArgNum, - unsigned ArgBits) { +bool Sema::BuiltinConstantArgShiftedByte(CallExpr *TheCall, int ArgNum, + unsigned ArgBits) { llvm::APSInt Result; // We can't check the value of a dependent argument. @@ -10288,7 +10282,7 @@ bool Sema::SemaBuiltinConstantArgShiftedByte(CallExpr *TheCall, int ArgNum, return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; // Truncate to the given size. @@ -10302,14 +10296,13 @@ bool Sema::SemaBuiltinConstantArgShiftedByte(CallExpr *TheCall, int ArgNum, << Arg->getSourceRange(); } -/// SemaBuiltinConstantArgShiftedByteOr0xFF - Check if argument ArgNum of +/// BuiltinConstantArgShiftedByteOr0xFF - Check if argument ArgNum of /// TheCall is a constant expression representing either a shifted byte value, /// or a value of the form 0x??FF (i.e. a member of the arithmetic progression /// 0x00FF, 0x01FF, ..., 0xFFFF). This strange range check is needed for some /// Arm MVE intrinsics. -bool Sema::SemaBuiltinConstantArgShiftedByteOrXXFF(CallExpr *TheCall, - int ArgNum, - unsigned ArgBits) { +bool Sema::BuiltinConstantArgShiftedByteOrXXFF(CallExpr *TheCall, int ArgNum, + unsigned ArgBits) { llvm::APSInt Result; // We can't check the value of a dependent argument. @@ -10318,7 +10311,7 @@ bool Sema::SemaBuiltinConstantArgShiftedByteOrXXFF(CallExpr *TheCall, return false; // Check constant-ness first. - if (SemaBuiltinConstantArg(TheCall, ArgNum, Result)) + if (BuiltinConstantArg(TheCall, ArgNum, Result)) return true; // Truncate to the given size. @@ -10335,8 +10328,8 @@ bool Sema::SemaBuiltinConstantArgShiftedByteOrXXFF(CallExpr *TheCall, << Arg->getSourceRange(); } -/// SemaBuiltinARMMemoryTaggingCall - Handle calls of memory tagging extensions -bool Sema::SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall) { +/// BuiltinARMMemoryTaggingCall - Handle calls of memory tagging extensions +bool Sema::BuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall) { if (BuiltinID == AArch64::BI__builtin_arm_irg) { if (checkArgCount(*this, TheCall, 2)) return true; @@ -10383,7 +10376,7 @@ bool Sema::SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall TheCall->setType(FirstArgType); // Second arg must be an constant in range [0,15] - return SemaBuiltinConstantArgRange(TheCall, 1, 0, 15); + return BuiltinConstantArgRange(TheCall, 1, 0, 15); } if (BuiltinID == AArch64::BI__builtin_arm_gmi) { @@ -10489,11 +10482,11 @@ bool Sema::SemaBuiltinARMMemoryTaggingCall(unsigned BuiltinID, CallExpr *TheCall return true; } -/// SemaBuiltinARMSpecialReg - Handle a check if argument ArgNum of CallExpr +/// BuiltinARMSpecialReg - Handle a check if argument ArgNum of CallExpr /// TheCall is an ARM/AArch64 special register string literal. -bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, - int ArgNum, unsigned ExpectedFieldNum, - bool AllowName) { +bool Sema::BuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, + int ArgNum, unsigned ExpectedFieldNum, + bool AllowName) { bool IsARMBuiltin = BuiltinID == ARM::BI__builtin_arm_rsr64 || BuiltinID == ARM::BI__builtin_arm_wsr64 || BuiltinID == ARM::BI__builtin_arm_rsr || @@ -10615,18 +10608,18 @@ bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall, // If a programmer wants to codegen the MSR (register) form of `msr tco, // xN`, they can still do so by specifying the register using five // colon-separated numbers in a string. - return SemaBuiltinConstantArgRange(TheCall, 1, 0, *MaxLimit); + return BuiltinConstantArgRange(TheCall, 1, 0, *MaxLimit); } return false; } -/// SemaBuiltinPPCMMACall - Check the call to a PPC MMA builtin for validity. +/// BuiltinPPCMMACall - Check the call to a PPC MMA builtin for validity. /// Emit an error and return true on failure; return false on success. /// TypeStr is a string containing the type descriptor of the value returned by /// the builtin and the descriptors of the expected type of the arguments. -bool Sema::SemaBuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID, - const char *TypeStr) { +bool Sema::BuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID, + const char *TypeStr) { assert((TypeStr[0] != '\0') && "Invalid types in PPC MMA builtin declaration"); @@ -10669,8 +10662,7 @@ bool Sema::SemaBuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID, // If the value of the Mask is not 0, we have a constraint in the size of // the integer argument so here we ensure the argument is a constant that // is in the valid range. - if (Mask != 0 && - SemaBuiltinConstantArgRange(TheCall, ArgNum, 0, Mask, true)) + if (Mask != 0 && BuiltinConstantArgRange(TheCall, ArgNum, 0, Mask, true)) return true; ArgNum++; @@ -10690,10 +10682,10 @@ bool Sema::SemaBuiltinPPCMMACall(CallExpr *TheCall, unsigned BuiltinID, return false; } -/// SemaBuiltinLongjmp - Handle __builtin_longjmp(void *env[5], int val). +/// BuiltinLongjmp - Handle __builtin_longjmp(void *env[5], int val). /// This checks that the target supports __builtin_longjmp and /// that val is a constant 1. -bool Sema::SemaBuiltinLongjmp(CallExpr *TheCall) { +bool Sema::BuiltinLongjmp(CallExpr *TheCall) { if (!Context.getTargetInfo().hasSjLjLowering()) return Diag(TheCall->getBeginLoc(), diag::err_builtin_longjmp_unsupported) << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc()); @@ -10702,7 +10694,7 @@ bool Sema::SemaBuiltinLongjmp(CallExpr *TheCall) { llvm::APSInt Result; // TODO: This is less than ideal. Overload this to take a value. - if (SemaBuiltinConstantArg(TheCall, 1, Result)) + if (BuiltinConstantArg(TheCall, 1, Result)) return true; if (Result != 1) @@ -10712,9 +10704,9 @@ bool Sema::SemaBuiltinLongjmp(CallExpr *TheCall) { return false; } -/// SemaBuiltinSetjmp - Handle __builtin_setjmp(void *env[5]). +/// BuiltinSetjmp - Handle __builtin_setjmp(void *env[5]). /// This checks that the target supports __builtin_setjmp. -bool Sema::SemaBuiltinSetjmp(CallExpr *TheCall) { +bool Sema::BuiltinSetjmp(CallExpr *TheCall) { if (!Context.getTargetInfo().hasSjLjLowering()) return Diag(TheCall->getBeginLoc(), diag::err_builtin_setjmp_unsupported) << SourceRange(TheCall->getBeginLoc(), TheCall->getEndLoc()); @@ -20134,17 +20126,17 @@ bool Sema::PrepareBuiltinElementwiseMathOneArgCall(CallExpr *TheCall) { return false; } -bool Sema::SemaBuiltinElementwiseMath(CallExpr *TheCall) { +bool Sema::BuiltinElementwiseMath(CallExpr *TheCall) { QualType Res; - if (SemaBuiltinVectorMath(TheCall, Res)) + if (BuiltinVectorMath(TheCall, Res)) return true; TheCall->setType(Res); return false; } -bool Sema::SemaBuiltinVectorToScalarMath(CallExpr *TheCall) { +bool Sema::BuiltinVectorToScalarMath(CallExpr *TheCall) { QualType Res; - if (SemaBuiltinVectorMath(TheCall, Res)) + if (BuiltinVectorMath(TheCall, Res)) return true; if (auto *VecTy0 = Res->getAs()) @@ -20155,7 +20147,7 @@ bool Sema::SemaBuiltinVectorToScalarMath(CallExpr *TheCall) { return false; } -bool Sema::SemaBuiltinVectorMath(CallExpr *TheCall, QualType &Res) { +bool Sema::BuiltinVectorMath(CallExpr *TheCall, QualType &Res) { if (checkArgCount(*this, TheCall, 2)) return true; @@ -20183,8 +20175,8 @@ bool Sema::SemaBuiltinVectorMath(CallExpr *TheCall, QualType &Res) { return false; } -bool Sema::SemaBuiltinElementwiseTernaryMath(CallExpr *TheCall, - bool CheckForFloatArgs) { +bool Sema::BuiltinElementwiseTernaryMath(CallExpr *TheCall, + bool CheckForFloatArgs) { if (checkArgCount(*this, TheCall, 3)) return true; @@ -20239,7 +20231,7 @@ bool Sema::PrepareBuiltinReduceMathOneArgCall(CallExpr *TheCall) { return false; } -bool Sema::SemaBuiltinNonDeterministicValue(CallExpr *TheCall) { +bool Sema::BuiltinNonDeterministicValue(CallExpr *TheCall) { if (checkArgCount(*this, TheCall, 1)) return true; @@ -20254,8 +20246,8 @@ bool Sema::SemaBuiltinNonDeterministicValue(CallExpr *TheCall) { return false; } -ExprResult Sema::SemaBuiltinMatrixTranspose(CallExpr *TheCall, - ExprResult CallResult) { +ExprResult Sema::BuiltinMatrixTranspose(CallExpr *TheCall, + ExprResult CallResult) { if (checkArgCount(*this, TheCall, 1)) return ExprError(); @@ -20304,8 +20296,8 @@ getAndVerifyMatrixDimension(Expr *Expr, StringRef Name, Sema &S) { return Dim; } -ExprResult Sema::SemaBuiltinMatrixColumnMajorLoad(CallExpr *TheCall, - ExprResult CallResult) { +ExprResult Sema::BuiltinMatrixColumnMajorLoad(CallExpr *TheCall, + ExprResult CallResult) { if (!getLangOpts().MatrixTypes) { Diag(TheCall->getBeginLoc(), diag::err_builtin_matrix_disabled); return ExprError(); @@ -20420,8 +20412,8 @@ ExprResult Sema::SemaBuiltinMatrixColumnMajorLoad(CallExpr *TheCall, return CallResult; } -ExprResult Sema::SemaBuiltinMatrixColumnMajorStore(CallExpr *TheCall, - ExprResult CallResult) { +ExprResult Sema::BuiltinMatrixColumnMajorStore(CallExpr *TheCall, + ExprResult CallResult) { if (checkArgCount(*this, TheCall, 3)) return ExprError(); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index ffe7e44e2387..8db4fffeecfe 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -7479,7 +7479,7 @@ ExprResult Sema::ActOnConvertVectorExpr(Expr *E, ParsedType ParsedDestTy, SourceLocation RParenLoc) { TypeSourceInfo *TInfo; GetTypeFromParser(ParsedDestTy, &TInfo); - return SemaConvertVectorExpr(E, TInfo, BuiltinLoc, RParenLoc); + return ConvertVectorExpr(E, TInfo, BuiltinLoc, RParenLoc); } /// BuildResolvedCallExpr - Build a call to a resolved expression, diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index db84f1810122..cfb5c6b6f283 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -3938,9 +3938,8 @@ static bool resolveBuiltinNewDeleteOverload(Sema &S, CallExpr *TheCall, llvm_unreachable("Unreachable, bad result from BestViableFunction"); } -ExprResult -Sema::SemaBuiltinOperatorNewDeleteOverloaded(ExprResult TheCallResult, - bool IsDelete) { +ExprResult Sema::BuiltinOperatorNewDeleteOverloaded(ExprResult TheCallResult, + bool IsDelete) { CallExpr *TheCall = cast(TheCallResult.get()); if (!getLangOpts().CPlusPlus) { Diag(TheCall->getExprLoc(), diag::err_builtin_requires_language) diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 7df352c24e86..66c2c7dd6be8 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -3890,15 +3890,14 @@ public: FPOptionsOverride()); // Type-check the __builtin_shufflevector expression. - return SemaRef.SemaBuiltinShuffleVector(cast(TheCall.get())); + return SemaRef.BuiltinShuffleVector(cast(TheCall.get())); } /// Build a new convert vector expression. ExprResult RebuildConvertVectorExpr(SourceLocation BuiltinLoc, Expr *SrcExpr, TypeSourceInfo *DstTInfo, SourceLocation RParenLoc) { - return SemaRef.SemaConvertVectorExpr(SrcExpr, DstTInfo, - BuiltinLoc, RParenLoc); + return SemaRef.ConvertVectorExpr(SrcExpr, DstTInfo, BuiltinLoc, RParenLoc); } /// Build a new template argument pack expansion. diff --git a/clang/utils/TableGen/MveEmitter.cpp b/clang/utils/TableGen/MveEmitter.cpp index aa20c758d84a..88e7b6e85465 100644 --- a/clang/utils/TableGen/MveEmitter.cpp +++ b/clang/utils/TableGen/MveEmitter.cpp @@ -927,7 +927,7 @@ public: llvm::APInt ArgTypeRange = llvm::APInt::getMaxValue(ArgTypeBits).zext(128); llvm::APInt ActualRange = (hi-lo).trunc(64).sext(128); if (ActualRange.ult(ArgTypeRange)) - SemaChecks.push_back("SemaBuiltinConstantArgRange(TheCall, " + Index + + SemaChecks.push_back("BuiltinConstantArgRange(TheCall, " + Index + ", " + signedHexLiteral(lo) + ", " + signedHexLiteral(hi) + ")"); @@ -942,9 +942,8 @@ public: } Suffix = (Twine(", ") + Arg).str(); } - SemaChecks.push_back((Twine("SemaBuiltinConstantArg") + - IA.ExtraCheckType + "(TheCall, " + Index + - Suffix + ")") + SemaChecks.push_back((Twine("BuiltinConstantArg") + IA.ExtraCheckType + + "(TheCall, " + Index + Suffix + ")") .str()); } -- GitLab From a61252419779a6d4a5ebf71e7e2fc4adc75cfddd Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Sun, 7 Apr 2024 09:51:47 -0400 Subject: [PATCH 096/695] [SLP]Fix the cost of the reduction result to the final type. Need to fix the way the cost is calculated, otherwise wrong cast opcode can be selected and lead to the over-optimistic vector cost. Plus, need to take into account reduction type size. Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/87528 --- .../Transforms/Vectorize/SLPVectorizer.cpp | 8 +++--- .../SLPVectorizer/RISCV/reductions.ll | 18 ++++++++++--- .../X86/minbitwidth-drop-wrapping-flags.ll | 25 +++++++++++-------- .../X86/minbitwidth-transformed-operand.ll | 2 +- 4 files changed, 35 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 332877f35081..6a662b2791bd 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -9824,11 +9824,13 @@ InstructionCost BoUpSLP::getTreeCost(ArrayRef VectorizedVals) { if (BWIt != MinBWs.end()) { Type *DstTy = Root.Scalars.front()->getType(); unsigned OriginalSz = DL->getTypeSizeInBits(DstTy); - if (OriginalSz != BWIt->second.first) { + unsigned SrcSz = + ReductionBitWidth == 0 ? BWIt->second.first : ReductionBitWidth; + if (OriginalSz != SrcSz) { unsigned Opcode = Instruction::Trunc; - if (OriginalSz < BWIt->second.first) + if (OriginalSz > SrcSz) Opcode = BWIt->second.second ? Instruction::SExt : Instruction::ZExt; - Type *SrcTy = IntegerType::get(DstTy->getContext(), BWIt->second.first); + Type *SrcTy = IntegerType::get(DstTy->getContext(), SrcSz); Cost += TTI->getCastInstrCost(Opcode, DstTy, SrcTy, TTI::CastContextHint::None, TTI::TCK_RecipThroughput); diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll index 500f10659f04..1e7eb4a41672 100644 --- a/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll @@ -801,10 +801,20 @@ entry: define i64 @red_zext_ld_4xi64(ptr %ptr) { ; CHECK-LABEL: @red_zext_ld_4xi64( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[PTR:%.*]], align 1 -; CHECK-NEXT: [[TMP1:%.*]] = zext <4 x i8> [[TMP0]] to <4 x i16> -; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> [[TMP1]]) -; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i64 +; CHECK-NEXT: [[LD0:%.*]] = load i8, ptr [[PTR:%.*]], align 1 +; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[LD0]] to i64 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 1 +; CHECK-NEXT: [[LD1:%.*]] = load i8, ptr [[GEP]], align 1 +; CHECK-NEXT: [[ZEXT_1:%.*]] = zext i8 [[LD1]] to i64 +; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i64 [[ZEXT]], [[ZEXT_1]] +; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 2 +; CHECK-NEXT: [[LD2:%.*]] = load i8, ptr [[GEP_1]], align 1 +; CHECK-NEXT: [[ZEXT_2:%.*]] = zext i8 [[LD2]] to i64 +; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i64 [[ADD_1]], [[ZEXT_2]] +; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 3 +; CHECK-NEXT: [[LD3:%.*]] = load i8, ptr [[GEP_2]], align 1 +; CHECK-NEXT: [[ZEXT_3:%.*]] = zext i8 [[LD3]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[ADD_2]], [[ZEXT_3]] ; CHECK-NEXT: ret i64 [[TMP3]] ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll index 44738aa1a674..a8d481a3e28a 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-drop-wrapping-flags.ll @@ -5,17 +5,22 @@ define i32 @test() { ; CHECK-LABEL: define i32 @test() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[A_PROMOTED:%.*]] = load i8, ptr null, align 1 -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[A_PROMOTED]], i32 0 -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i8> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP2]], <4 x i8> [[TMP3]], <4 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i16> -; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i16> [[TMP5]], -; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP6]]) -; CHECK-NEXT: [[TMP8:%.*]] = zext i16 [[TMP7]] to i32 +; CHECK-NEXT: [[DEC_4:%.*]] = add i8 [[A_PROMOTED]], 0 +; CHECK-NEXT: [[CONV_I_4:%.*]] = zext i8 [[DEC_4]] to i32 +; CHECK-NEXT: [[SUB_I_4:%.*]] = add nuw nsw i32 [[CONV_I_4]], 0 +; CHECK-NEXT: [[DEC_5:%.*]] = add i8 [[A_PROMOTED]], 0 +; CHECK-NEXT: [[CONV_I_5:%.*]] = zext i8 [[DEC_5]] to i32 +; CHECK-NEXT: [[SUB_I_5:%.*]] = add nuw nsw i32 [[CONV_I_5]], 65535 +; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[SUB_I_4]], [[SUB_I_5]] +; CHECK-NEXT: [[DEC_6:%.*]] = or i8 [[A_PROMOTED]], 0 +; CHECK-NEXT: [[CONV_I_6:%.*]] = zext i8 [[DEC_6]] to i32 +; CHECK-NEXT: [[SUB_I_6:%.*]] = add nuw nsw i32 [[CONV_I_6]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], [[SUB_I_6]] +; CHECK-NEXT: [[TMP10:%.*]] = or i8 [[A_PROMOTED]], 0 +; CHECK-NEXT: [[CONV_I_7:%.*]] = zext i8 [[TMP10]] to i32 +; CHECK-NEXT: [[SUB_I_7:%.*]] = add nuw nsw i32 [[CONV_I_7]], 0 +; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP1]], [[SUB_I_7]] ; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 65535 -; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i8> [[TMP4]], i32 3 ; CHECK-NEXT: store i8 [[TMP10]], ptr null, align 1 ; CHECK-NEXT: [[CALL3:%.*]] = tail call i32 (ptr, ...) null(ptr null, i32 [[TMP9]]) ; CHECK-NEXT: ret i32 0 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll index 4acd63078b82..4af69dff179e 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-transformed-operand.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-6 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s +; RUN: opt -passes=slp-vectorizer -S -slp-threshold=-7 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s define void @test(i64 %d.promoted.i) { ; CHECK-LABEL: define void @test( -- GitLab From c91254db1dcace869f4d3f1ac659bdd7700a1459 Mon Sep 17 00:00:00 2001 From: Alexander Richardson Date: Sun, 7 Apr 2024 09:50:06 -0700 Subject: [PATCH 097/695] [compiler-rt] Allow running tests without installing first Currently, the testsuite uses the default runtimes path to find the runtimes libraries which may or may not match the just-built runtimes. This change uses the `-resource-dir` flag for clang whenever `COMPILER_RT_TEST_STANDALONE_BUILD_LIBS` is set to ensure that we are actually testing the currently built libraries rather than the ones bundled with `${COMPILER_RT_TEST_COMPILER}`. The existing logic works fine when clang and compiler-rt share the same build directory ``-DLLVM_ENABLE_PROJECTS=clang;compiler-rt`, but when building compiler-rt separately we need to tell the compiler used for the tests where it can find the just-built libraries. This reduces the fixes check-all failures to one in my configuration: ``` cmake -DCMAKE_BUILD_TYPE=RelWithDebInfo -G Ninja -DCMAKE_C_COMPILER=$HOME/output/upstream-llvm/bin/clang -DCMAKE_CXX_COMPILER=$HOME/output/upstream-llvm/bin/clang++ -DCOMPILER_RT_INCLUDE_TESTS=ON -DLLVM_EXTERNAL_LIT=$HOME/build/upstream-llvm-project-build/bin/llvm-lit -DLLVM_CMAKE_DIR=$HOME/output/upstream-llvm -DCOMPILER_RT_DEBUG=OFF -S $HOME/src/upstream-llvm-project/compiler-rt -B $HOME/src/upstream-llvm-project/compiler-rt/cmake-build-all-sanitizers ``` Reviewed By: vitalybuka, delcypher, MaskRay Pull Request: https://github.com/llvm/llvm-project/pull/83088 --- compiler-rt/CMakeLists.txt | 21 +++++ compiler-rt/cmake/Modules/AddCompilerRT.cmake | 1 + compiler-rt/test/CMakeLists.txt | 8 -- compiler-rt/test/fuzzer/lit.cfg.py | 1 + compiler-rt/test/lit.common.cfg.py | 86 ++++++++++++++----- compiler-rt/test/lit.common.configured.in | 1 + compiler-rt/test/safestack/lit.cfg.py | 10 ++- 7 files changed, 96 insertions(+), 32 deletions(-) diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt index f4e92f14db85..af374edb76a8 100644 --- a/compiler-rt/CMakeLists.txt +++ b/compiler-rt/CMakeLists.txt @@ -584,6 +584,27 @@ string(APPEND COMPILER_RT_TEST_COMPILER_CFLAGS " ${stdlib_flag}") string(REPLACE " " ";" COMPILER_RT_UNITTEST_CFLAGS "${COMPILER_RT_TEST_COMPILER_CFLAGS}") set(COMPILER_RT_UNITTEST_LINK_FLAGS ${COMPILER_RT_UNITTEST_CFLAGS}) +option(COMPILER_RT_TEST_STANDALONE_BUILD_LIBS + "When set to ON and testing in a standalone build, test the runtime \ + libraries built by this standalone build rather than the runtime libraries \ + shipped with the compiler (used for testing). When set to OFF and testing \ + in a standalone build, test the runtime libraries shipped with the compiler \ + (used for testing). This option has no effect if the compiler and this \ + build are configured to use the same runtime library path." + ON) +if (COMPILER_RT_TEST_STANDALONE_BUILD_LIBS) + # Ensure that the unit tests can find the sanitizer headers prior to installation. + list(APPEND COMPILER_RT_UNITTEST_CFLAGS "-I${CMAKE_CURRENT_LIST_DIR}/include") + # Ensure that unit tests link against the just-built runtime libraries instead + # of the ones bundled with the compiler by overriding the resource directory. + # + if ("${COMPILER_RT_TEST_COMPILER_ID}" MATCHES "Clang") + list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-resource-dir=${COMPILER_RT_OUTPUT_DIR}") + endif() + get_compiler_rt_output_dir(${COMPILER_RT_DEFAULT_TARGET_ARCH} rtlib_dir) + list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-Wl,-rpath,${rtlib_dir}") +endif() + if(COMPILER_RT_USE_LLVM_UNWINDER) # We're linking directly against the libunwind that we're building so don't # try to link in the toolchain's default libunwind which may be missing. diff --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake b/compiler-rt/cmake/Modules/AddCompilerRT.cmake index e0400a8ea952..567b123b7abc 100644 --- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake +++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake @@ -768,6 +768,7 @@ function(configure_compiler_rt_lit_site_cfg input output) get_compiler_rt_output_dir(${COMPILER_RT_DEFAULT_TARGET_ARCH} output_dir) string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} COMPILER_RT_RESOLVED_TEST_COMPILER ${COMPILER_RT_TEST_COMPILER}) + string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} COMPILER_RT_RESOLVED_OUTPUT_DIR ${COMPILER_RT_OUTPUT_DIR}) string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR ${output_dir}) configure_lit_site_cfg(${input} ${output}) diff --git a/compiler-rt/test/CMakeLists.txt b/compiler-rt/test/CMakeLists.txt index c186be1e44fd..edc007aaf477 100644 --- a/compiler-rt/test/CMakeLists.txt +++ b/compiler-rt/test/CMakeLists.txt @@ -1,14 +1,6 @@ # Needed for lit support in standalone builds. include(AddLLVM) -option(COMPILER_RT_TEST_STANDALONE_BUILD_LIBS - "When set to ON and testing in a standalone build, test the runtime \ - libraries built by this standalone build rather than the runtime libraries \ - shipped with the compiler (used for testing). When set to OFF and testing \ - in a standalone build, test the runtime libraries shipped with the compiler \ - (used for testing). This option has no effect if the compiler and this \ - build are configured to use the same runtime library path." - ON) pythonize_bool(COMPILER_RT_TEST_STANDALONE_BUILD_LIBS) pythonize_bool(LLVM_ENABLE_EXPENSIVE_CHECKS) diff --git a/compiler-rt/test/fuzzer/lit.cfg.py b/compiler-rt/test/fuzzer/lit.cfg.py index 9084254b3b15..0c0550ac729d 100644 --- a/compiler-rt/test/fuzzer/lit.cfg.py +++ b/compiler-rt/test/fuzzer/lit.cfg.py @@ -106,6 +106,7 @@ def generate_compiler_cmd(is_cpp=True, fuzzer_enabled=True, msan_enabled=False): return " ".join( [ compiler_cmd, + config.target_cflags, std_cmd, "-O2 -gline-tables-only", sanitizers_cmd, diff --git a/compiler-rt/test/lit.common.cfg.py b/compiler-rt/test/lit.common.cfg.py index 0ac20a9831d9..ca9ce130dd51 100644 --- a/compiler-rt/test/lit.common.cfg.py +++ b/compiler-rt/test/lit.common.cfg.py @@ -14,6 +14,27 @@ import lit.formats import lit.util +def get_path_from_clang(args, allow_failure): + clang_cmd = [ + config.clang.strip(), + f"--target={config.target_triple}", + *args, + ] + path = None + try: + result = subprocess.run( + clang_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=True + ) + path = result.stdout.decode().strip() + except subprocess.CalledProcessError as e: + msg = f"Failed to run {clang_cmd}\nrc:{e.returncode}\nstdout:{e.stdout}\ne.stderr{e.stderr}" + if allow_failure: + lit_config.warning(msg) + else: + lit_config.fatal(msg) + return path, clang_cmd + + def find_compiler_libdir(): """ Returns the path to library resource directory used @@ -26,26 +47,6 @@ def find_compiler_libdir(): # TODO: Support other compilers. return None - def get_path_from_clang(args, allow_failure): - clang_cmd = [ - config.clang.strip(), - f"--target={config.target_triple}", - ] - clang_cmd.extend(args) - path = None - try: - result = subprocess.run( - clang_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=True - ) - path = result.stdout.decode().strip() - except subprocess.CalledProcessError as e: - msg = f"Failed to run {clang_cmd}\nrc:{e.returncode}\nstdout:{e.stdout}\ne.stderr{e.stderr}" - if allow_failure: - lit_config.warning(msg) - else: - lit_config.fatal(msg) - return path, clang_cmd - # Try using `-print-runtime-dir`. This is only supported by very new versions of Clang. # so allow failure here. runtime_dir, clang_cmd = get_path_from_clang( @@ -168,10 +169,51 @@ if config.enable_per_target_runtime_dir: r"/i386(?=-[^/]+$)", "/x86_64", config.compiler_rt_libdir ) + +# Check if the test compiler resource dir matches the local build directory +# (which happens with -DLLVM_ENABLE_PROJECTS=clang;compiler-rt) or if we are +# using an installed clang to test compiler-rt standalone. In the latter case +# we may need to override the resource dir to match the path of the just-built +# compiler-rt libraries. +test_cc_resource_dir, _ = get_path_from_clang( + shlex.split(config.target_cflags) + ["-print-resource-dir"], allow_failure=True +) +# Normalize the path for comparison +if test_cc_resource_dir is not None: + test_cc_resource_dir = os.path.realpath(test_cc_resource_dir) +if lit_config.debug: + lit_config.note(f"Resource dir for {config.clang} is {test_cc_resource_dir}") +local_build_resource_dir = os.path.realpath(config.compiler_rt_output_dir) +if test_cc_resource_dir != local_build_resource_dir and config.test_standalone_build_libs: + if config.compiler_id == "Clang": + if lit_config.debug: + lit_config.note( + f"Overriding test compiler resource dir to use " + f'libraries in "{config.compiler_rt_libdir}"' + ) + # Ensure that we use the just-built static libraries when linking by + # overriding the Clang resource directory. Additionally, we want to use + # the builtin headers shipped with clang (e.g. stdint.h), so we + # explicitly add this as an include path (since the headers are not + # going to be in the current compiler-rt build directory). + # We also tell the linker to add an RPATH entry for the local library + # directory so that the just-built shared libraries are used. + config.target_cflags += f" -nobuiltininc" + config.target_cflags += f" -I{config.compiler_rt_src_root}/include" + config.target_cflags += f" -idirafter {test_cc_resource_dir}/include" + config.target_cflags += f" -resource-dir={config.compiler_rt_output_dir}" + config.target_cflags += f" -Wl,-rpath,{config.compiler_rt_libdir}" + else: + lit_config.warning( + f"Cannot override compiler-rt library directory with non-Clang " + f"compiler: {config.compiler_id}" + ) + + # Ask the compiler for the path to libraries it is going to use. If this # doesn't match config.compiler_rt_libdir then it means we might be testing the # compiler's own runtime libraries rather than the ones we just built. -# Warn about about this and handle appropriately. +# Warn about this and handle appropriately. compiler_libdir = find_compiler_libdir() if compiler_libdir: compiler_rt_libdir_real = os.path.realpath(config.compiler_rt_libdir) @@ -182,7 +224,7 @@ if compiler_libdir: f'compiler-rt libdir: "{compiler_rt_libdir_real}"' ) if config.test_standalone_build_libs: - # Use just built runtime libraries, i.e. the the libraries this built just built. + # Use just built runtime libraries, i.e. the libraries this build just built. if not config.test_suite_supports_overriding_runtime_lib_path: # Test suite doesn't support this configuration. # TODO(dliew): This should be an error but it seems several bots are diff --git a/compiler-rt/test/lit.common.configured.in b/compiler-rt/test/lit.common.configured.in index fff5dc6cc750..8889b816b149 100644 --- a/compiler-rt/test/lit.common.configured.in +++ b/compiler-rt/test/lit.common.configured.in @@ -27,6 +27,7 @@ set_default("compiler_id", "@COMPILER_RT_TEST_COMPILER_ID@") set_default("python_executable", "@Python3_EXECUTABLE@") set_default("compiler_rt_debug", @COMPILER_RT_DEBUG_PYBOOL@) set_default("compiler_rt_intercept_libdispatch", @COMPILER_RT_INTERCEPT_LIBDISPATCH_PYBOOL@) +set_default("compiler_rt_output_dir", "@COMPILER_RT_RESOLVED_OUTPUT_DIR@") set_default("compiler_rt_libdir", "@COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR@") set_default("emulator", "@COMPILER_RT_EMULATOR@") set_default("asan_shadow_scale", "@COMPILER_RT_ASAN_SHADOW_SCALE@") diff --git a/compiler-rt/test/safestack/lit.cfg.py b/compiler-rt/test/safestack/lit.cfg.py index adf27a0d7e5e..aadb8bf0d5c7 100644 --- a/compiler-rt/test/safestack/lit.cfg.py +++ b/compiler-rt/test/safestack/lit.cfg.py @@ -13,10 +13,16 @@ config.suffixes = [".c", ".cpp", ".m", ".mm", ".ll", ".test"] # Add clang substitutions. config.substitutions.append( - ("%clang_nosafestack ", config.clang + " -O0 -fno-sanitize=safe-stack ") + ( + "%clang_nosafestack ", + config.clang + config.target_cflags + " -O0 -fno-sanitize=safe-stack ", + ) ) config.substitutions.append( - ("%clang_safestack ", config.clang + " -O0 -fsanitize=safe-stack ") + ( + "%clang_safestack ", + config.clang + config.target_cflags + " -O0 -fsanitize=safe-stack ", + ) ) if config.lto_supported: -- GitLab From d57d09477996e50237e2fc949bd5b747259b0012 Mon Sep 17 00:00:00 2001 From: David Green Date: Sun, 7 Apr 2024 18:18:32 +0100 Subject: [PATCH 098/695] [AArch64] Add test for LD2/LD3/LD4 shuffle cost models. NFC --- .../CostModel/AArch64/shuffle-store.ll | 231 ++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll new file mode 100644 index 000000000000..fc8e1dd052bb --- /dev/null +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll @@ -0,0 +1,231 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt < %s -mtriple=aarch64--linux-gnu -passes="print" 2>&1 -disable-output | FileCheck %s + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + +define void @vst2(ptr %p) { +; CHECK-LABEL: 'vst2' +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i8> %v4i8, ptr %p, align 4 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> %v16i8, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %v4i16, ptr %p, align 8 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> %v8i16, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %v4i32, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i64> %v4i64, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i64> %v16i64, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i64> %v32i64, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> + store <4 x i8> %v4i8, ptr %p + %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> + store <8 x i8> %v8i8, ptr %p + %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> + store <16 x i8> %v16i8, ptr %p + %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> + store <32 x i8> %v32i8, ptr %p + + %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> + store <4 x i16> %v4i16, ptr %p + %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> + store <8 x i16> %v8i16, ptr %p + %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> + store <16 x i16> %v16i16, ptr %p + %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> + store <32 x i16> %v32i16, ptr %p + + %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> + store <4 x i32> %v4i32, ptr %p + %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> + store <8 x i32> %v8i32, ptr %p + %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <16 x i32> + store <16 x i32> %v16i32, ptr %p + %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <32 x i32> + store <32 x i32> %v32i32, ptr %p + + %v4i64 = shufflevector <2 x i64> undef, <2 x i64> undef, <4 x i32> + store <4 x i64> %v4i64, ptr %p + %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <8 x i32> + store <8 x i64> %v8i64, ptr %p + %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <16 x i32> + store <16 x i64> %v16i64, ptr %p + %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <32 x i32> + store <32 x i64> %v32i64, ptr %p + + ret void +} + + +define void @vst3(ptr %p) { +; CHECK-LABEL: 'vst3' +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <6 x i8> %v8i8, ptr %p, align 8 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <12 x i8> %v16i8, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <24 x i8> %v32i8, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %v64i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <48 x i8> %v64i8, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <6 x i16> %v8i16, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <12 x i16> %v16i16, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <24 x i16> %v32i16, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v64i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <48 x i16> %v64i16, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <6 x i32> %v8i32, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <12 x i32> %v16i32, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <24 x i32> %v32i32, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v64i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <48 x i32> %v64i32, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <6 x i64> %v8i64, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <12 x i64> %v16i64, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <24 x i64> %v32i64, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v64i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <48 x i64> %v64i64, ptr %p, align 512 +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <6 x i32> + store <6 x i8> %v8i8, ptr %p + %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <12 x i32> + store <12 x i8> %v16i8, ptr %p + %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <24 x i32> + store <24 x i8> %v32i8, ptr %p + %v64i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <48 x i32> + store <48 x i8> %v64i8, ptr %p + + %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <6 x i32> + store <6 x i16> %v8i16, ptr %p + %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <12 x i32> + store <12 x i16> %v16i16, ptr %p + %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <24 x i32> + store <24 x i16> %v32i16, ptr %p + %v64i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <48 x i32> + store <48 x i16> %v64i16, ptr %p + + %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <6 x i32> + store <6 x i32> %v8i32, ptr %p + %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <12 x i32> + store <12 x i32> %v16i32, ptr %p + %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <24 x i32> + store <24 x i32> %v32i32, ptr %p + %v64i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <48 x i32> + store <48 x i32> %v64i32, ptr %p + + %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <6 x i32> + store <6 x i64> %v8i64, ptr %p + %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <12 x i32> + store <12 x i64> %v16i64, ptr %p + %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <24 x i32> + store <24 x i64> %v32i64, ptr %p + %v64i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <48 x i32> + store <48 x i64> %v64i64, ptr %p + + ret void +} + + +define void @vst4(ptr %p) { +; CHECK-LABEL: 'vst4' +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> %v16i8, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <64 x i8> %v64i8, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> %v8i16, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <64 x i16> %v64i16, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <64 x i32> %v64i32, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i64> %v16i64, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i64> %v32i64, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <64 x i64> %v64i64, ptr %p, align 512 +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> + store <8 x i8> %v8i8, ptr %p + %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> + store <16 x i8> %v16i8, ptr %p + %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> + store <32 x i8> %v32i8, ptr %p + %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> + store <64 x i8> %v64i8, ptr %p + + %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> + store <8 x i16> %v8i16, ptr %p + %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> + store <16 x i16> %v16i16, ptr %p + %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> + store <32 x i16> %v32i16, ptr %p + %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> + store <64 x i16> %v64i16, ptr %p + + %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> + store <8 x i32> %v8i32, ptr %p + %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> + store <16 x i32> %v16i32, ptr %p + %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> + store <32 x i32> %v32i32, ptr %p + %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> + store <64 x i32> %v64i32, ptr %p + + %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> + store <8 x i64> %v8i64, ptr %p + %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> + store <16 x i64> %v16i64, ptr %p + %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> + store <32 x i64> %v32i64, ptr %p + %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> + store <64 x i64> %v64i64, ptr %p + + ret void +} -- GitLab From 10b1864dff816174cd83fb2d3bc622e25fcf0f8a Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Sun, 7 Apr 2024 10:21:51 -0700 Subject: [PATCH 099/695] [compiler-rt] Do not add -rpath to linker args on Windows This is not supported. Should hopefully fix Windows CI after commit c91254db1dcace869f4d3f1ac659bdd7700a1459. --- compiler-rt/CMakeLists.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt index af374edb76a8..8649507ce1c7 100644 --- a/compiler-rt/CMakeLists.txt +++ b/compiler-rt/CMakeLists.txt @@ -602,7 +602,9 @@ if (COMPILER_RT_TEST_STANDALONE_BUILD_LIBS) list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-resource-dir=${COMPILER_RT_OUTPUT_DIR}") endif() get_compiler_rt_output_dir(${COMPILER_RT_DEFAULT_TARGET_ARCH} rtlib_dir) - list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-Wl,-rpath,${rtlib_dir}") + if (NOT WIN32) + list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-Wl,-rpath,${rtlib_dir}") + endif() endif() if(COMPILER_RT_USE_LLVM_UNWINDER) -- GitLab From a3bb9c2b06666e2f4eb005179ca7eef3313b6be5 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Sun, 7 Apr 2024 10:22:34 -0700 Subject: [PATCH 100/695] [cmake] Prevent implicitly passing `-no_exported_symbols` (#87846) * It is possible to setup llvm-project builds without going through `llvm/CMakeList.txt` so the fatal error handling should be smarter. * Disable option on Apple style lldb-linux builds. --- lldb/cmake/caches/Apple-lldb-Linux.cmake | 1 + llvm/cmake/modules/AddLLVM.cmake | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/lldb/cmake/caches/Apple-lldb-Linux.cmake b/lldb/cmake/caches/Apple-lldb-Linux.cmake index b2d3cf595fe1..9258f01e2ec2 100644 --- a/lldb/cmake/caches/Apple-lldb-Linux.cmake +++ b/lldb/cmake/caches/Apple-lldb-Linux.cmake @@ -1,4 +1,5 @@ include(${CMAKE_CURRENT_LIST_DIR}/Apple-lldb-base.cmake) +set(LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES ON CACHE BOOL "") set(LLVM_DISTRIBUTION_COMPONENTS lldb diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index 81398ddb5c92..693fd5669f63 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -1038,9 +1038,15 @@ macro(add_llvm_executable name) add_llvm_symbol_exports( ${name} ${LLVM_EXPORTED_SYMBOL_FILE} ) endif(LLVM_EXPORTED_SYMBOL_FILE) - if (NOT LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES AND LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS) + if (DEFINED LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES AND + NOT LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES) + if(LLVM_LINKER_SUPPORTS_NO_EXPORTED_SYMBOLS) set_property(TARGET ${name} APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-no_exported_symbols") + else() + message(FATAL_ERROR + "LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES cannot be disabled when linker does not support \"-no_exported_symbols\"") + endif() endif() if (LLVM_LINK_LLVM_DYLIB AND NOT ARG_DISABLE_LLVM_LINK_LLVM_DYLIB) -- GitLab From 3f16ff4e68552951cf39b2f1c707df64d7c8ec59 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 7 Apr 2024 11:38:15 -0700 Subject: [PATCH 101/695] [memprof] Use static instead of anonymous namespaces (#87889) This patch replaces anonymous namespaces with static as per LLVM Coding Standards. --- llvm/lib/ProfileData/MemProf.cpp | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/llvm/lib/ProfileData/MemProf.cpp b/llvm/lib/ProfileData/MemProf.cpp index ac0a8702c3f9..96aeedf2e691 100644 --- a/llvm/lib/ProfileData/MemProf.cpp +++ b/llvm/lib/ProfileData/MemProf.cpp @@ -10,8 +10,7 @@ namespace llvm { namespace memprof { -namespace { -size_t serializedSizeV0(const IndexedAllocationInfo &IAI) { +static size_t serializedSizeV0(const IndexedAllocationInfo &IAI) { size_t Size = 0; // The number of frames to serialize. Size += sizeof(uint64_t); @@ -22,7 +21,7 @@ size_t serializedSizeV0(const IndexedAllocationInfo &IAI) { return Size; } -size_t serializedSizeV2(const IndexedAllocationInfo &IAI) { +static size_t serializedSizeV2(const IndexedAllocationInfo &IAI) { size_t Size = 0; // The CallStackId Size += sizeof(CallStackId); @@ -30,7 +29,6 @@ size_t serializedSizeV2(const IndexedAllocationInfo &IAI) { Size += PortableMemInfoBlock::serializedSize(); return Size; } -} // namespace size_t IndexedAllocationInfo::serializedSize(IndexedVersion Version) const { switch (Version) { @@ -43,8 +41,7 @@ size_t IndexedAllocationInfo::serializedSize(IndexedVersion Version) const { llvm_unreachable("unsupported MemProf version"); } -namespace { -size_t serializedSizeV0(const IndexedMemProfRecord &Record) { +static size_t serializedSizeV0(const IndexedMemProfRecord &Record) { size_t Result = sizeof(GlobalValue::GUID); for (const IndexedAllocationInfo &N : Record.AllocSites) Result += N.serializedSize(Version0); @@ -59,7 +56,7 @@ size_t serializedSizeV0(const IndexedMemProfRecord &Record) { return Result; } -size_t serializedSizeV2(const IndexedMemProfRecord &Record) { +static size_t serializedSizeV2(const IndexedMemProfRecord &Record) { size_t Result = sizeof(GlobalValue::GUID); for (const IndexedAllocationInfo &N : Record.AllocSites) Result += N.serializedSize(Version2); @@ -70,7 +67,6 @@ size_t serializedSizeV2(const IndexedMemProfRecord &Record) { Result += Record.CallSiteIds.size() * sizeof(CallStackId); return Result; } -} // namespace size_t IndexedMemProfRecord::serializedSize(IndexedVersion Version) const { switch (Version) { @@ -83,9 +79,8 @@ size_t IndexedMemProfRecord::serializedSize(IndexedVersion Version) const { llvm_unreachable("unsupported MemProf version"); } -namespace { -void serializeV0(const IndexedMemProfRecord &Record, - const MemProfSchema &Schema, raw_ostream &OS) { +static void serializeV0(const IndexedMemProfRecord &Record, + const MemProfSchema &Schema, raw_ostream &OS) { using namespace support; endian::Writer LE(OS, llvm::endianness::little); @@ -107,8 +102,8 @@ void serializeV0(const IndexedMemProfRecord &Record, } } -void serializeV2(const IndexedMemProfRecord &Record, - const MemProfSchema &Schema, raw_ostream &OS) { +static void serializeV2(const IndexedMemProfRecord &Record, + const MemProfSchema &Schema, raw_ostream &OS) { using namespace support; endian::Writer LE(OS, llvm::endianness::little); @@ -124,7 +119,6 @@ void serializeV2(const IndexedMemProfRecord &Record, for (const auto &CSId : Record.CallSiteIds) LE.write(CSId); } -} // namespace void IndexedMemProfRecord::serialize(const MemProfSchema &Schema, raw_ostream &OS, IndexedVersion Version) { @@ -140,9 +134,8 @@ void IndexedMemProfRecord::serialize(const MemProfSchema &Schema, llvm_unreachable("unsupported MemProf version"); } -namespace { -IndexedMemProfRecord deserializeV0(const MemProfSchema &Schema, - const unsigned char *Ptr) { +static IndexedMemProfRecord deserializeV0(const MemProfSchema &Schema, + const unsigned char *Ptr) { using namespace support; IndexedMemProfRecord Record; @@ -185,8 +178,8 @@ IndexedMemProfRecord deserializeV0(const MemProfSchema &Schema, return Record; } -IndexedMemProfRecord deserializeV2(const MemProfSchema &Schema, - const unsigned char *Ptr) { +static IndexedMemProfRecord deserializeV2(const MemProfSchema &Schema, + const unsigned char *Ptr) { using namespace support; IndexedMemProfRecord Record; @@ -214,7 +207,6 @@ IndexedMemProfRecord deserializeV2(const MemProfSchema &Schema, return Record; } -} // namespace IndexedMemProfRecord IndexedMemProfRecord::deserialize(const MemProfSchema &Schema, -- GitLab From 15d11a4de9f62fd8fc6bdb888e32c9e4b86d0cdd Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sun, 7 Apr 2024 20:32:53 +0100 Subject: [PATCH 102/695] [VPlan] Track IsOrdered in VPReductionRecipe, remove use of ILV (NFCI). Instead of using ILV.useOrderedReductions during ::execute, instead store the information at recipe construction. Another step towards making recipe'::execute independent of legacy ILV. --- .../Transforms/Vectorize/LoopVectorize.cpp | 65 +------------------ llvm/lib/Transforms/Vectorize/VPlan.h | 8 ++- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 51 +++++++++++++++ .../Transforms/Vectorize/VPlanTest.cpp | 4 +- 4 files changed, 61 insertions(+), 67 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 49bacb5ae6cc..9e22dce38477 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -573,10 +573,6 @@ public: /// Fix the non-induction PHIs in \p Plan. void fixNonInductionPHIs(VPlan &Plan, VPTransformState &State); - /// Returns true if the reordering of FP operations is not allowed, but we are - /// able to vectorize with strict in-order reductions for the given RdxDesc. - bool useOrderedReductions(const RecurrenceDescriptor &RdxDesc); - /// Create a new phi node for the induction variable \p OrigPhi to resume /// iteration count in the scalar epilogue, from where the vectorized loop /// left off. \p Step is the SCEV-expanded induction step to use. In cases @@ -3714,11 +3710,6 @@ void InnerLoopVectorizer::fixNonInductionPHIs(VPlan &Plan, } } -bool InnerLoopVectorizer::useOrderedReductions( - const RecurrenceDescriptor &RdxDesc) { - return Cost->useOrderedReductions(RdxDesc); -} - void LoopVectorizationCostModel::collectLoopScalars(ElementCount VF) { // We should not collect Scalars more than once per VF. Right now, this // function is called from collectUniformsAndScalars(), which already does @@ -9056,8 +9047,9 @@ void LoopVectorizationPlanner::adjustRecipesForReductions( if (CM.blockNeedsPredicationForAnyReason(BB)) CondOp = RecipeBuilder.getBlockInMask(BB); - VPReductionRecipe *RedRecipe = new VPReductionRecipe( - RdxDesc, CurrentLinkI, PreviousLink, VecOp, CondOp); + VPReductionRecipe *RedRecipe = + new VPReductionRecipe(RdxDesc, CurrentLinkI, PreviousLink, VecOp, + CondOp, CM.useOrderedReductions(RdxDesc)); // Append the recipe to the end of the VPBasicBlock because we need to // ensure that it comes after all of it's inputs, including CondOp. // Note that this transformation may leave over dead recipes (including @@ -9307,57 +9299,6 @@ void VPInterleaveRecipe::execute(VPTransformState &State) { NeedsMaskForGaps); } -void VPReductionRecipe::execute(VPTransformState &State) { - assert(!State.Instance && "Reduction being replicated."); - Value *PrevInChain = State.get(getChainOp(), 0, /*IsScalar*/ true); - RecurKind Kind = RdxDesc.getRecurrenceKind(); - bool IsOrdered = State.ILV->useOrderedReductions(RdxDesc); - // Propagate the fast-math flags carried by the underlying instruction. - IRBuilderBase::FastMathFlagGuard FMFGuard(State.Builder); - State.Builder.setFastMathFlags(RdxDesc.getFastMathFlags()); - for (unsigned Part = 0; Part < State.UF; ++Part) { - Value *NewVecOp = State.get(getVecOp(), Part); - if (VPValue *Cond = getCondOp()) { - Value *NewCond = State.get(Cond, Part, State.VF.isScalar()); - VectorType *VecTy = dyn_cast(NewVecOp->getType()); - Type *ElementTy = VecTy ? VecTy->getElementType() : NewVecOp->getType(); - Value *Iden = RdxDesc.getRecurrenceIdentity(Kind, ElementTy, - RdxDesc.getFastMathFlags()); - if (State.VF.isVector()) { - Iden = - State.Builder.CreateVectorSplat(VecTy->getElementCount(), Iden); - } - - Value *Select = State.Builder.CreateSelect(NewCond, NewVecOp, Iden); - NewVecOp = Select; - } - Value *NewRed; - Value *NextInChain; - if (IsOrdered) { - if (State.VF.isVector()) - NewRed = createOrderedReduction(State.Builder, RdxDesc, NewVecOp, - PrevInChain); - else - NewRed = State.Builder.CreateBinOp( - (Instruction::BinaryOps)RdxDesc.getOpcode(Kind), PrevInChain, - NewVecOp); - PrevInChain = NewRed; - } else { - PrevInChain = State.get(getChainOp(), Part, /*IsScalar*/ true); - NewRed = createTargetReduction(State.Builder, RdxDesc, NewVecOp); - } - if (RecurrenceDescriptor::isMinMaxRecurrenceKind(Kind)) { - NextInChain = createMinMaxOp(State.Builder, RdxDesc.getRecurrenceKind(), - NewRed, PrevInChain); - } else if (IsOrdered) - NextInChain = NewRed; - else - NextInChain = State.Builder.CreateBinOp( - (Instruction::BinaryOps)RdxDesc.getOpcode(Kind), NewRed, PrevInChain); - State.set(this, NextInChain, Part, /*IsScalar*/ true); - } -} - void VPReplicateRecipe::execute(VPTransformState &State) { Instruction *UI = getUnderlyingInstr(); if (State.Instance) { // Generate a single instance. diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 77577b516ae2..5f6334b974cf 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -2075,13 +2075,15 @@ public: class VPReductionRecipe : public VPSingleDefRecipe { /// The recurrence decriptor for the reduction in question. const RecurrenceDescriptor &RdxDesc; + bool IsOrdered; public: VPReductionRecipe(const RecurrenceDescriptor &R, Instruction *I, - VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp) + VPValue *ChainOp, VPValue *VecOp, VPValue *CondOp, + bool IsOrdered) : VPSingleDefRecipe(VPDef::VPReductionSC, ArrayRef({ChainOp, VecOp}), I), - RdxDesc(R) { + RdxDesc(R), IsOrdered(IsOrdered) { if (CondOp) addOperand(CondOp); } @@ -2090,7 +2092,7 @@ public: VPRecipeBase *clone() override { return new VPReductionRecipe(RdxDesc, getUnderlyingInstr(), getChainOp(), - getVecOp(), getCondOp()); + getVecOp(), getCondOp(), IsOrdered); } VP_CLASSOF_IMPL(VPDef::VPReductionSC) diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index fc8323480d9a..2438e4dae3eb 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -1518,7 +1518,58 @@ void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent, } } } +#endif + +void VPReductionRecipe::execute(VPTransformState &State) { + assert(!State.Instance && "Reduction being replicated."); + Value *PrevInChain = State.get(getChainOp(), 0, /*IsScalar*/ true); + RecurKind Kind = RdxDesc.getRecurrenceKind(); + // Propagate the fast-math flags carried by the underlying instruction. + IRBuilderBase::FastMathFlagGuard FMFGuard(State.Builder); + State.Builder.setFastMathFlags(RdxDesc.getFastMathFlags()); + for (unsigned Part = 0; Part < State.UF; ++Part) { + Value *NewVecOp = State.get(getVecOp(), Part); + if (VPValue *Cond = getCondOp()) { + Value *NewCond = State.get(Cond, Part, State.VF.isScalar()); + VectorType *VecTy = dyn_cast(NewVecOp->getType()); + Type *ElementTy = VecTy ? VecTy->getElementType() : NewVecOp->getType(); + Value *Iden = RdxDesc.getRecurrenceIdentity(Kind, ElementTy, + RdxDesc.getFastMathFlags()); + if (State.VF.isVector()) { + Iden = State.Builder.CreateVectorSplat(VecTy->getElementCount(), Iden); + } + + Value *Select = State.Builder.CreateSelect(NewCond, NewVecOp, Iden); + NewVecOp = Select; + } + Value *NewRed; + Value *NextInChain; + if (IsOrdered) { + if (State.VF.isVector()) + NewRed = createOrderedReduction(State.Builder, RdxDesc, NewVecOp, + PrevInChain); + else + NewRed = State.Builder.CreateBinOp( + (Instruction::BinaryOps)RdxDesc.getOpcode(Kind), PrevInChain, + NewVecOp); + PrevInChain = NewRed; + } else { + PrevInChain = State.get(getChainOp(), Part, /*IsScalar*/ true); + NewRed = createTargetReduction(State.Builder, RdxDesc, NewVecOp); + } + if (RecurrenceDescriptor::isMinMaxRecurrenceKind(Kind)) { + NextInChain = createMinMaxOp(State.Builder, RdxDesc.getRecurrenceKind(), + NewRed, PrevInChain); + } else if (IsOrdered) + NextInChain = NewRed; + else + NextInChain = State.Builder.CreateBinOp( + (Instruction::BinaryOps)RdxDesc.getOpcode(Kind), NewRed, PrevInChain); + State.set(this, NextInChain, Part, /*IsScalar*/ true); + } +} +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) void VPReductionRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { O << Indent << "REDUCE "; diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp index 02e7ca341fe2..78d809296d4c 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp @@ -1119,7 +1119,7 @@ TEST(VPRecipeTest, MayHaveSideEffectsAndMayReadWriteMemory) { VPValue VecOp; VPValue CondOp; VPReductionRecipe Recipe(RecurrenceDescriptor(), nullptr, &ChainOp, &CondOp, - &VecOp); + &VecOp, false); EXPECT_FALSE(Recipe.mayHaveSideEffects()); EXPECT_FALSE(Recipe.mayReadFromMemory()); EXPECT_FALSE(Recipe.mayWriteToMemory()); @@ -1287,7 +1287,7 @@ TEST(VPRecipeTest, CastVPReductionRecipeToVPUser) { VPValue VecOp; VPValue CondOp; VPReductionRecipe Recipe(RecurrenceDescriptor(), nullptr, &ChainOp, &CondOp, - &VecOp); + &VecOp, false); EXPECT_TRUE(isa(&Recipe)); VPRecipeBase *BaseR = &Recipe; EXPECT_TRUE(isa(BaseR)); -- GitLab From 943db678dadd6088629d08ec3e582bea0595f2d2 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Sun, 7 Apr 2024 13:58:49 -0700 Subject: [PATCH 103/695] [clang-format][NFC] Add getNextNonComment() to FormatTokenSource (#87868) --- clang/lib/Format/FormatTokenSource.h | 9 +++++++++ clang/lib/Format/UnwrappedLineParser.cpp | 11 ++--------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/clang/lib/Format/FormatTokenSource.h b/clang/lib/Format/FormatTokenSource.h index cce19f527a92..2b93f302d360 100644 --- a/clang/lib/Format/FormatTokenSource.h +++ b/clang/lib/Format/FormatTokenSource.h @@ -72,6 +72,15 @@ public: // getNextToken() -> a1 // getNextToken() -> a2 virtual FormatToken *insertTokens(ArrayRef Tokens) = 0; + + [[nodiscard]] FormatToken *getNextNonComment() { + FormatToken *Tok; + do { + Tok = getNextToken(); + assert(Tok); + } while (Tok->is(tok::comment)); + return Tok; + } }; class IndexedTokenSource : public FormatTokenSource { diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 6df7cc1c3955..af57b1420c6e 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -427,11 +427,7 @@ bool UnwrappedLineParser::parseLevel(const FormatToken *OpeningBrace, break; case tok::kw_default: { unsigned StoredPosition = Tokens->getPosition(); - FormatToken *Next; - do { - Next = Tokens->getNextToken(); - assert(Next); - } while (Next->is(tok::comment)); + auto *Next = Tokens->getNextNonComment(); FormatTok = Tokens->setPosition(StoredPosition); if (Next->isNot(tok::colon)) { // default not followed by ':' is not a case label; treat it like @@ -497,10 +493,7 @@ void UnwrappedLineParser::calculateBraceTypes(bool ExpectClassBody) { assert(Tok->is(tok::l_brace)); do { - FormatToken *NextTok; - do { - NextTok = Tokens->getNextToken(); - } while (NextTok->is(tok::comment)); + auto *NextTok = Tokens->getNextNonComment(); if (!Line->InMacroBody && !Style.isTableGen()) { // Skip PPDirective lines and comments. -- GitLab From 649523f6f7b67604034a8af5d8ca6830fcd64aab Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Sun, 7 Apr 2024 13:06:49 -0600 Subject: [PATCH 104/695] [ORC] Add an ExecutionSession state verifier. Add an ExecutionSession state verifier, enabled under EXPENSIVE_CHECKS, that can be used to identify inconsistent session state to assist in tracking down bugs. This initial version was motivated by investigation of the EDU-update bug that was fixed in a671ceec334. rdar://125376708 --- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 7 + llvm/lib/ExecutionEngine/Orc/Core.cpp | 213 ++++++++++++++++++- 2 files changed, 218 insertions(+), 2 deletions(-) diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h index 45bf9adcf2a4..286112a0b46a 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h @@ -1237,6 +1237,8 @@ private: // * Pending queries holds any not-yet-completed queries that include this // symbol. struct MaterializingInfo { + friend class ExecutionSession; + std::shared_ptr DefiningEDU; DenseSet DependantEDUs; @@ -1746,6 +1748,11 @@ public: /// Dump the state of all the JITDylibs in this session. void dump(raw_ostream &OS); + /// Check the internal consistency of ExecutionSession data structures. +#ifdef EXPENSIVE_CHECKS + bool verifySessionState(Twine Phase); +#endif + private: static void logErrorsToStdErr(Error Err) { logAllUnhandledErrors(std::move(Err), errs(), "JIT session error: "); diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp index 60265c4f72ff..8bb68b45951d 100644 --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -1392,7 +1392,6 @@ void JITDylib::transferTracker(ResourceTracker &DstRT, ResourceTracker &SrcRT) { } Error JITDylib::defineImpl(MaterializationUnit &MU) { - LLVM_DEBUG({ dbgs() << " " << MU.getSymbols() << "\n"; }); SymbolNameSet Duplicates; @@ -1605,6 +1604,11 @@ Error ExecutionSession::endSession() { LLVM_DEBUG(dbgs() << "Ending ExecutionSession " << this << "\n"); auto JDsToRemove = runSessionLocked([&] { + +#ifdef EXPENSIVE_CHECKS + verifySessionState("Entering ExecutionSession::endSession"); +#endif + SessionOpen = false; return JDs; }); @@ -1662,7 +1666,6 @@ Expected ExecutionSession::createJITDylib(std::string Name) { } Error ExecutionSession::removeJITDylibs(std::vector JDsToRemove) { - // Set JD to 'Closing' state and remove JD from the ExecutionSession. runSessionLocked([&] { for (auto &JD : JDsToRemove) { @@ -1951,6 +1954,196 @@ void ExecutionSession::dump(raw_ostream &OS) { }); } +#ifdef EXPENSIVE_CHECKS +bool ExecutionSession::verifySessionState(Twine Phase) { + return runSessionLocked([&]() { + bool AllOk = true; + + // We'll collect these and verify them later to avoid redundant checks. + DenseSet EDUsToCheck; + + for (auto &JD : JDs) { + + auto LogFailure = [&]() -> raw_fd_ostream & { + auto &Stream = errs(); + if (AllOk) + Stream << "ERROR: Bad ExecutionSession state detected " << Phase + << "\n"; + Stream << " In JITDylib " << JD->getName() << ", "; + AllOk = false; + return Stream; + }; + + if (JD->State != JITDylib::Open) { + LogFailure() + << "state is not Open, but JD is in ExecutionSession list."; + } + + // Check symbol table. + // 1. If the entry state isn't resolved then check that no address has + // been set. + // 2. Check that if the hasMaterializerAttached flag is set then there is + // an UnmaterializedInfo entry, and vice-versa. + for (auto &[Sym, Entry] : JD->Symbols) { + // Check that unresolved symbols have null addresses. + if (Entry.getState() < SymbolState::Resolved) { + if (Entry.getAddress()) { + LogFailure() << "symbol " << Sym << " has state " + << Entry.getState() + << " (not-yet-resolved) but non-null address " + << Entry.getAddress() << ".\n"; + } + } + + // Check that the hasMaterializerAttached flag is correct. + auto UMIItr = JD->UnmaterializedInfos.find(Sym); + if (Entry.hasMaterializerAttached()) { + if (UMIItr == JD->UnmaterializedInfos.end()) { + LogFailure() << "symbol " << Sym + << " entry claims materializer attached, but " + "UnmaterializedInfos has no corresponding entry.\n"; + } + } else if (UMIItr != JD->UnmaterializedInfos.end()) { + LogFailure() + << "symbol " << Sym + << " entry claims no materializer attached, but " + "UnmaterializedInfos has an unexpected entry for it.\n"; + } + } + + // Check that every UnmaterializedInfo entry has a corresponding entry + // in the Symbols table. + for (auto &[Sym, UMI] : JD->UnmaterializedInfos) { + auto SymItr = JD->Symbols.find(Sym); + if (SymItr == JD->Symbols.end()) { + LogFailure() + << "symbol " << Sym + << " has UnmaterializedInfos entry, but no Symbols entry.\n"; + } + } + + // Check consistency of the MaterializingInfos table. + for (auto &[Sym, MII] : JD->MaterializingInfos) { + + auto SymItr = JD->Symbols.find(Sym); + if (SymItr == JD->Symbols.end()) { + // If there's no Symbols entry for this MaterializingInfos entry then + // report that. + LogFailure() + << "symbol " << Sym + << " has MaterializingInfos entry, but no Symbols entry.\n"; + } else { + // Otherwise check consistency between Symbols and MaterializingInfos. + + // Ready symbols should not have MaterializingInfos. + if (SymItr->second.getState() == SymbolState::Ready) { + LogFailure() + << "symbol " << Sym + << " is in Ready state, should not have MaterializingInfo.\n"; + } + + // Pending queries should be for subsequent states. + auto CurState = static_cast( + static_cast>( + SymItr->second.getState()) + 1); + for (auto &Q : MII.PendingQueries) { + if (Q->getRequiredState() != CurState) { + if (Q->getRequiredState() > CurState) + CurState = Q->getRequiredState(); + else + LogFailure() << "symbol " << Sym + << " has stale or misordered queries.\n"; + } + } + + // If there's a DefiningEDU then check that... + // 1. The JD matches. + // 2. The symbol is in the EDU's Symbols map. + // 3. The symbol table entry is in the Emitted state. + if (MII.DefiningEDU) { + + EDUsToCheck.insert(MII.DefiningEDU.get()); + + if (MII.DefiningEDU->JD != JD.get()) { + LogFailure() << "symbol " << Sym + << " has DefiningEDU with incorrect JD" + << (llvm::is_contained(JDs, MII.DefiningEDU->JD) + ? " (JD not currently in ExecutionSession" + : "") + << "\n"; + } + + if (SymItr->second.getState() != SymbolState::Emitted) { + LogFailure() + << "symbol " << Sym + << " has DefiningEDU, but is not in Emitted state.\n"; + } + } + + // Check that JDs for any DependantEDUs are also in the session -- + // that guarantees that we'll also visit them during this loop. + for (auto &DepEDU : MII.DependantEDUs) { + if (!llvm::is_contained(JDs, DepEDU->JD)) { + LogFailure() << "symbol " << Sym << " has DependantEDU " + << (void *)DepEDU << " with JD (" << DepEDU->JD + << ") that isn't in ExecutionSession.\n"; + } + } + } + } + } + + // Check EDUs. + for (auto *EDU : EDUsToCheck) { + assert(EDU->JD->State == JITDylib::Open && "EDU->JD is not Open"); + + auto LogFailure = [&]() -> raw_fd_ostream & { + AllOk = false; + auto &Stream = errs(); + Stream << "In EDU defining " << EDU->JD->getName() << ": { "; + for (auto &[Sym, Flags] : EDU->Symbols) + Stream << Sym << " "; + Stream << "}, "; + return Stream; + }; + + if (EDU->Symbols.empty()) + LogFailure() << "no symbols defined.\n"; + else { + for (auto &[Sym, Flags] : EDU->Symbols) { + if (!Sym) + LogFailure() << "null symbol defined.\n"; + else { + if (!EDU->JD->Symbols.count(SymbolStringPtr(Sym))) { + LogFailure() << "symbol " << Sym + << " isn't present in JD's symbol table.\n"; + } + } + } + } + + for (auto &[DepJD, Symbols] : EDU->Dependencies) { + if (!llvm::is_contained(JDs, DepJD)) { + LogFailure() << "dependant symbols listed for JD that isn't in " + "ExecutionSession.\n"; + } else { + for (auto &DepSym : Symbols) { + if (!DepJD->Symbols.count(SymbolStringPtr(DepSym))) { + LogFailure() + << "dependant symbol " << DepSym + << " does not appear in symbol table for dependant JD " + << DepJD->getName() << ".\n"; + } + } + } + } + } + + return AllOk; + }); +} +#endif // EXPENSIVE_CHECKS + void ExecutionSession::dispatchOutstandingMUs() { LLVM_DEBUG(dbgs() << "Dispatching MaterializationUnits...\n"); while (true) { @@ -3060,6 +3253,9 @@ ExecutionSession::IL_emit(MaterializationResponsibility &MR, return make_error("JITDylib " + TargetJD.getName() + " is defunct", inconvertibleErrorCode()); +#ifdef EXPENSIVE_CHECKS + verifySessionState("entering ExecutionSession::IL_emit"); +#endif // Walk all EDUs: // 1. Verifying that dependencies are available (not removed or in the error @@ -3217,6 +3413,10 @@ ExecutionSession::IL_emit(MaterializationResponsibility &MR, IL_makeEDUEmitted(std::move(EDUInfo.EDU), CompletedQueries); } +#ifdef EXPENSIVE_CHECKS + verifySessionState("exiting ExecutionSession::IL_emit"); +#endif + return std::move(CompletedQueries); } @@ -3305,6 +3505,11 @@ std::pair> ExecutionSession::IL_failSymbols(JITDylib &JD, const SymbolNameVector &SymbolsToFail) { + +#ifdef EXPENSIVE_CHECKS + verifySessionState("entering ExecutionSession::IL_failSymbols"); +#endif + JITDylib::AsynchronousSymbolQuerySet FailedQueries; auto FailedSymbolsMap = std::make_shared(); auto ExtractFailedQueries = [&](JITDylib::MaterializingInfo &MI) { @@ -3440,6 +3645,10 @@ ExecutionSession::IL_failSymbols(JITDylib &JD, JD.MaterializingInfos.erase(Name); } +#ifdef EXPENSIVE_CHECKS + verifySessionState("exiting ExecutionSession::IL_failSymbols"); +#endif + return std::make_pair(std::move(FailedQueries), std::move(FailedSymbolsMap)); } -- GitLab From 4d1bb7699bfa62ca113dcfabe6da8eae74fe7372 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 7 Apr 2024 15:06:13 -0700 Subject: [PATCH 105/695] [memprof] Fix a typo in writeMemProfV1 (#87890) This patch borrows memprof-merge.test to test --memprof-version. --- llvm/lib/ProfileData/InstrProfWriter.cpp | 2 +- .../tools/llvm-profdata/memprof-merge-v0.test | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 llvm/test/tools/llvm-profdata/memprof-merge-v0.test diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp index 72d77d5580a5..1e0159dd1e6f 100644 --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -493,7 +493,7 @@ static Error writeMemProfV1( llvm::MapVector &MemProfRecordData, llvm::MapVector &MemProfFrameData) { - OS.write(memprof::Version0); + OS.write(memprof::Version1); uint64_t HeaderUpdatePos = OS.tell(); OS.write(0ULL); // Reserve space for the memprof record table offset. OS.write(0ULL); // Reserve space for the memprof frame payload offset. diff --git a/llvm/test/tools/llvm-profdata/memprof-merge-v0.test b/llvm/test/tools/llvm-profdata/memprof-merge-v0.test new file mode 100644 index 000000000000..68132961eb78 --- /dev/null +++ b/llvm/test/tools/llvm-profdata/memprof-merge-v0.test @@ -0,0 +1,22 @@ +REQUIRES: x86_64-linux + +RUN: echo ":ir" > %t.proftext +RUN: echo "main" >> %t.proftext +RUN: echo "742261418966908927" >> %t.proftext +RUN: echo "1" >> %t.proftext +RUN: echo "1" >> %t.proftext + +To update the inputs used below run Inputs/update_memprof_inputs.sh /path/to/updated/clang +RUN: llvm-profdata merge %t.proftext %p/Inputs/basic.memprofraw --memprof-version=0 --profiled-binary %p/Inputs/basic.memprofexe -o %t.prof.v0 +RUN: llvm-profdata show %t.prof.v0 | FileCheck %s + +RUN: llvm-profdata merge %t.proftext %p/Inputs/basic.memprofraw --memprof-version=1 --profiled-binary %p/Inputs/basic.memprofexe -o %t.prof.v1 +RUN: llvm-profdata show %t.prof.v1 | FileCheck %s + +For now we only check the validity of the instrumented profile since we don't +have a way to display the contents of the memprof indexed format yet. + +CHECK: Instrumentation level: IR entry_first = 0 +CHECK: Total functions: 1 +CHECK: Maximum function count: 1 +CHECK: Maximum internal block count: 0 -- GitLab From da675b922cca3dc9a76642d792e882979a3d8c82 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Sun, 7 Apr 2024 14:25:02 -0700 Subject: [PATCH 106/695] [RISCV] Expand test coverage of stack offsets between 2^11 and 2^15 Adds two sets of tests. First, one for prolog/epilogue insertions where the second stack adjustment can be done with shNadd for zba. Second, a set of tests with offsets off SP in the same ranges, but also adding varying alignments. --- llvm/test/CodeGen/RISCV/prolog-epilogue.ll | 307 +++++++++++++++++++++ llvm/test/CodeGen/RISCV/stack-offset.ll | 259 +++++++++++++++++ 2 files changed, 566 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/prolog-epilogue.ll create mode 100644 llvm/test/CodeGen/RISCV/stack-offset.ll diff --git a/llvm/test/CodeGen/RISCV/prolog-epilogue.ll b/llvm/test/CodeGen/RISCV/prolog-epilogue.ll new file mode 100644 index 000000000000..700481d9e130 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/prolog-epilogue.ll @@ -0,0 +1,307 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32,RV32I +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+zba < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32,RV32ZBA +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64,RV64I +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+zba < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBA + +declare void @callee(ptr) + +define void @frame_16b() { +; RV32-LABEL: frame_16b: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: li a0, 0 +; RV32-NEXT: call callee +; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_16b: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -16 +; RV64-NEXT: .cfi_def_cfa_offset 16 +; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: li a0, 0 +; RV64-NEXT: call callee +; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: ret + call void @callee(ptr null) + ret void +} + +define void @frame_1024b() { +; RV32-LABEL: frame_1024b: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -1024 +; RV32-NEXT: .cfi_def_cfa_offset 1024 +; RV32-NEXT: sw ra, 1020(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lw ra, 1020(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 1024 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_1024b: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -1024 +; RV64-NEXT: .cfi_def_cfa_offset 1024 +; RV64-NEXT: sd ra, 1016(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: ld ra, 1016(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 1024 +; RV64-NEXT: ret + %a = alloca [1008 x i8] + call void @callee(ptr %a) + ret void +} + +define void @frame_2048b() { +; RV32-LABEL: frame_2048b: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 2048 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_2048b: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -16 +; RV64-NEXT: .cfi_def_cfa_offset 2048 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [2032 x i8] + call void @callee(ptr %a) + ret void +} + +define void @frame_4096b() { +; RV32-LABEL: frame_4096b: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -2048 +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 4096 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: addi sp, sp, 32 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_4096b: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -2048 +; RV64-NEXT: addi sp, sp, -16 +; RV64-NEXT: .cfi_def_cfa_offset 4096 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: addi sp, sp, 32 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [4080 x i8] + call void @callee(ptr %a) + ret void +} + +;; 2^12-16+2032 +define void @frame_4kb() { +; RV32-LABEL: frame_4kb: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 1 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 6128 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 1 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_4kb: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 1 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 6128 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 1 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [6112 x i8] + call void @callee(ptr %a) + ret void +} + +;; 2^13-16+2032 +define void @frame_8kb() { +; RV32-LABEL: frame_8kb: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 2 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 10224 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 2 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_8kb: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 2 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 10224 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 2 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [10208 x i8] + call void @callee(ptr %a) + ret void +} + +;; 2^14-16+2032 +define void @frame_16kb() { +; RV32-LABEL: frame_16kb: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 4 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 18416 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 4 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_16kb: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 4 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 18416 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 4 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [18400 x i8] + call void @callee(ptr %a) + ret void +} + +;; 2^15-16+2032 +define void @frame_32kb() { +; RV32-LABEL: frame_32kb: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 8 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 34800 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 8 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_32kb: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 8 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 34800 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 8 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [34784 x i8] + call void @callee(ptr %a) + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; RV32I: {{.*}} +; RV32ZBA: {{.*}} +; RV64I: {{.*}} +; RV64ZBA: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/stack-offset.ll b/llvm/test/CodeGen/RISCV/stack-offset.ll new file mode 100644 index 000000000000..6a24e5dcdbc3 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/stack-offset.ll @@ -0,0 +1,259 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32,RV32I +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+zba < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32,RV32ZBA +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64,RV64I +; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+zba < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64,RV64ZBA + +declare void @inspect(...) + +define void @test() { +; RV32-LABEL: test: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -2048 +; RV32-NEXT: addi sp, sp, -1120 +; RV32-NEXT: .cfi_def_cfa_offset 5200 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: addi a1, sp, 2047 +; RV32-NEXT: addi a1, a1, 13 +; RV32-NEXT: lui a2, 1 +; RV32-NEXT: addi a2, a2, 12 +; RV32-NEXT: add a2, sp, a2 +; RV32-NEXT: lui a3, 1 +; RV32-NEXT: addi a3, a3, 1036 +; RV32-NEXT: add a3, sp, a3 +; RV32-NEXT: call inspect +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: addi sp, sp, 1136 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: test: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -2048 +; RV64-NEXT: addi sp, sp, -1120 +; RV64-NEXT: .cfi_def_cfa_offset 5200 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: addi a1, sp, 2047 +; RV64-NEXT: addi a1, a1, 9 +; RV64-NEXT: lui a2, 1 +; RV64-NEXT: addiw a2, a2, 8 +; RV64-NEXT: add a2, sp, a2 +; RV64-NEXT: lui a3, 1 +; RV64-NEXT: addiw a3, a3, 1032 +; RV64-NEXT: add a3, sp, a3 +; RV64-NEXT: call inspect +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: addi sp, sp, 1136 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %p4 = alloca [64 x i8], align 1 + %p3 = alloca [1024 x i8], align 1 + %p2 = alloca [2048 x i8], align 1 + %p1 = alloca [2048 x i8], align 1 + call void (...) @inspect(ptr %p1, ptr %p2, ptr %p3, ptr %p4) + ret void +} + +define void @align_8() { +; RV32-LABEL: align_8: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -2048 +; RV32-NEXT: addi sp, sp, -32 +; RV32-NEXT: .cfi_def_cfa_offset 4112 +; RV32-NEXT: addi a0, sp, 7 +; RV32-NEXT: lui a1, 1 +; RV32-NEXT: addi a1, a1, 8 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: call inspect +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: addi sp, sp, 48 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: align_8: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -2048 +; RV64-NEXT: addi sp, sp, -48 +; RV64-NEXT: .cfi_def_cfa_offset 4128 +; RV64-NEXT: addi a0, sp, 15 +; RV64-NEXT: lui a1, 1 +; RV64-NEXT: addiw a1, a1, 16 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: call inspect +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: addi sp, sp, 64 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %p2 = alloca i8, align 8 + %p1 = alloca [4097 x i8], align 1 + call void (...) @inspect(ptr %p1, ptr %p2) + ret void +} + +define void @align_4() { +; RV32-LABEL: align_4: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -2048 +; RV32-NEXT: addi sp, sp, -32 +; RV32-NEXT: .cfi_def_cfa_offset 4112 +; RV32-NEXT: addi a0, sp, 7 +; RV32-NEXT: lui a1, 1 +; RV32-NEXT: addi a1, a1, 8 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: call inspect +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: addi sp, sp, 48 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: align_4: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -2048 +; RV64-NEXT: addi sp, sp, -48 +; RV64-NEXT: .cfi_def_cfa_offset 4128 +; RV64-NEXT: addi a0, sp, 19 +; RV64-NEXT: lui a1, 1 +; RV64-NEXT: addiw a1, a1, 20 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: call inspect +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: addi sp, sp, 64 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %p2 = alloca i8, align 4 + %p1 = alloca [4097 x i8], align 1 + call void (...) @inspect(ptr %p1, ptr %p2) + ret void +} + +define void @align_2() { +; RV32-LABEL: align_2: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -2048 +; RV32-NEXT: addi sp, sp, -32 +; RV32-NEXT: .cfi_def_cfa_offset 4112 +; RV32-NEXT: addi a0, sp, 9 +; RV32-NEXT: lui a1, 1 +; RV32-NEXT: addi a1, a1, 10 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: call inspect +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: addi sp, sp, 48 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: align_2: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -2048 +; RV64-NEXT: addi sp, sp, -48 +; RV64-NEXT: .cfi_def_cfa_offset 4128 +; RV64-NEXT: addi a0, sp, 21 +; RV64-NEXT: lui a1, 1 +; RV64-NEXT: addiw a1, a1, 22 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: call inspect +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: addi sp, sp, 64 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %p2 = alloca i8, align 2 + %p1 = alloca [4097 x i8], align 1 + call void (...) @inspect(ptr %p1, ptr %p2) + ret void +} + + +define void @align_1() { +; RV32-LABEL: align_1: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: addi sp, sp, -2048 +; RV32-NEXT: addi sp, sp, -32 +; RV32-NEXT: .cfi_def_cfa_offset 4112 +; RV32-NEXT: addi a0, sp, 10 +; RV32-NEXT: lui a1, 1 +; RV32-NEXT: addi a1, a1, 11 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: call inspect +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: addi sp, sp, 48 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: align_1: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: addi sp, sp, -2048 +; RV64-NEXT: addi sp, sp, -48 +; RV64-NEXT: .cfi_def_cfa_offset 4128 +; RV64-NEXT: addi a0, sp, 22 +; RV64-NEXT: lui a1, 1 +; RV64-NEXT: addiw a1, a1, 23 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: call inspect +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: addi sp, sp, 64 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %p2 = alloca i8, align 1 + %p1 = alloca [4097 x i8], align 1 + call void (...) @inspect(ptr %p1, ptr %p2) + ret void +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; RV32I: {{.*}} +; RV32ZBA: {{.*}} +; RV64I: {{.*}} +; RV64ZBA: {{.*}} -- GitLab From cebf77fb936a7270c7e3fa5c4a7e76216321d385 Mon Sep 17 00:00:00 2001 From: Haohai Wen Date: Mon, 8 Apr 2024 09:44:34 +0800 Subject: [PATCH 107/695] [CodeGen][DebugInfo] Add missing DebugLoc for SplitCriticalEdge (#72192) In SplitCriticalEdge, DebugLoc of the branch instruction in new created MBB was set to empty. It should be set and we can find proper DebugLoc for it in most cases. This patch set it to non empty merged DebugLoc of current MBB branches. --- llvm/lib/CodeGen/MachineBasicBlock.cpp | 10 +++++++++- llvm/test/CodeGen/X86/fsafdo_test1.ll | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp index 4410fb7ecd23..b2114c250ac0 100644 --- a/llvm/lib/CodeGen/MachineBasicBlock.cpp +++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp @@ -1137,7 +1137,6 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge( MachineFunction *MF = getParent(); MachineBasicBlock *PrevFallthrough = getNextNode(); - DebugLoc DL; // FIXME: this is nowhere MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock(); NMBB->setCallFrameSize(Succ->getCallFrameSize()); @@ -1218,6 +1217,15 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge( SlotIndexUpdateDelegate SlotUpdater(*MF, Indexes); SmallVector Cond; const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); + + // In original 'this' BB, there must be a branch instruction targeting at + // Succ. We can not find it out since currently getBranchDestBlock was not + // implemented for all targets. However, if the merged DL has column or line + // number, the scope and non-zero column and line number is same with that + // branch instruction so we can safely use it. + DebugLoc DL, MergedDL = findBranchDebugLoc(); + if (MergedDL && (MergedDL.getLine() || MergedDL.getCol())) + DL = MergedDL; TII->insertBranch(*NMBB, Succ, nullptr, Cond, DL); } diff --git a/llvm/test/CodeGen/X86/fsafdo_test1.ll b/llvm/test/CodeGen/X86/fsafdo_test1.ll index b5ae3915294c..61c0f59aba6f 100644 --- a/llvm/test/CodeGen/X86/fsafdo_test1.ll +++ b/llvm/test/CodeGen/X86/fsafdo_test1.ll @@ -6,7 +6,7 @@ ; V01: .loc 1 9 5 is_stmt 1 discriminator 2 # foo.c:9:5 ; V0: .loc 1 9 5 is_stmt 0 discriminator 11266 # foo.c:9:5 ; V0: .loc 1 7 3 is_stmt 1 discriminator 11266 # foo.c:7:3 -; V1: .loc 1 9 5 is_stmt 0 discriminator 258 # foo.c:9:5 +; V1: .loc 1 9 5 is_stmt 0 discriminator 514 # foo.c:9:5 ; V1: .loc 1 7 3 is_stmt 1 discriminator 258 # foo.c:7:3 ; Check that variable __llvm_fs_discriminator__ is generated. ; V01: .type __llvm_fs_discriminator__,@object # @__llvm_fs_discriminator__ -- GitLab From 739fa1c84b92b8af7dceedf2e5ad808a64e85a57 Mon Sep 17 00:00:00 2001 From: Carlos Alberto Enciso Date: Mon, 8 Apr 2024 05:31:56 +0100 Subject: [PATCH 108/695] [indvars] Missing variables at Og: (#69920) https://bugs.llvm.org/show_bug.cgi?id=51735 https://github.com/llvm/llvm-project/issues/51077 In the given test case: ``` 4 ... 5 void bar() { 6 int End = 777; 7 int Index = 27; 8 char Var = 1; 9 for (; Index < End; ++Index) 10 ; 11 nop(Index); 12 } 13 ... ``` Missing local variable `Index` after loop `Induction Variable Elimination`. When adding a breakpoint at line `11`, LLDB does not have information on the variable. But it has info on `Var` and `End`. --- llvm/include/llvm/Support/GenericLoopInfo.h | 24 ++++ .../include/llvm/Transforms/Utils/LoopUtils.h | 6 + llvm/lib/Transforms/Utils/LoopUtils.cpp | 65 +++++++++ .../Transforms/IndVarSimplify/pr51735-1.ll | 129 +++++++++++++++++ .../Transforms/IndVarSimplify/pr51735-2.ll | 128 +++++++++++++++++ .../Transforms/IndVarSimplify/pr51735-3.ll | 131 ++++++++++++++++++ .../test/Transforms/IndVarSimplify/pr51735.ll | 104 ++++++++++++++ 7 files changed, 587 insertions(+) create mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735-1.ll create mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735-2.ll create mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735-3.ll create mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735.ll diff --git a/llvm/include/llvm/Support/GenericLoopInfo.h b/llvm/include/llvm/Support/GenericLoopInfo.h index d560ca648132..f4b50367bf93 100644 --- a/llvm/include/llvm/Support/GenericLoopInfo.h +++ b/llvm/include/llvm/Support/GenericLoopInfo.h @@ -44,6 +44,8 @@ #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetOperations.h" +#include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/ValueHandle.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/GenericDomTree.h" @@ -75,6 +77,13 @@ template class LoopBase { const LoopBase & operator=(const LoopBase &) = delete; + // Induction variable exit value and its debug users, preserved by the + // 'indvars' pass, when it detects that the loop can be deleted and the + // there are no PHIs to be rewritten. + // For now, we only preserve single induction variables. + Value *IndVarFinalValue = nullptr; + SmallVector IndVarDebugUsers; + public: /// Return the nesting level of this loop. An outer-most loop has depth 1, /// for consistency with loop depth values used for basic blocks, where depth @@ -251,6 +260,21 @@ public: [&](BlockT *Pred) { return contains(Pred); }); } + /// Preserve the induction variable exit value and its debug users by the + /// 'indvars' pass if the loop can deleted. Those debug users will be used + /// by the 'loop-delete' pass. + void preserveDebugInductionVariableInfo( + Value *FinalValue, SmallVector DbgUsers) { + IndVarFinalValue = FinalValue; + for (DbgVariableIntrinsic *DebugUser : DbgUsers) + IndVarDebugUsers.push_back(DebugUser); + } + + Value *getDebugInductionVariableFinalValue() { return IndVarFinalValue; } + SmallVector &getDebugInductionVariableDebugUsers() { + return IndVarDebugUsers; + } + //===--------------------------------------------------------------------===// // APIs for simple analysis of the loop. // diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h index 345e09dce0b2..15b230ba92dd 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h +++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h @@ -468,6 +468,12 @@ int rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, ReplaceExitVal ReplaceExitValue, SmallVector &DeadInsts); +/// Assign exit values to variables that use this loop variable during the loop. +void addDebugValuesToIncomingValue(BasicBlock *Successor, Value *IndVar, + PHINode *PN); +void addDebugValuesToLoopVariable(BasicBlock *Successor, Value *ExitValue, + PHINode *PN); + /// Set weights for \p UnrolledLoop and \p RemainderLoop based on weights for /// \p OrigLoop and the following distribution of \p OrigLoop iteration among \p /// UnrolledLoop and \p RemainderLoop. \p UnrolledLoop receives weights that diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp index 9d816c522053..4187bd38cf29 100644 --- a/llvm/lib/Transforms/Utils/LoopUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp @@ -31,6 +31,7 @@ #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/IR/DIBuilder.h" +#include "llvm/IR/DebugInfo.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" @@ -608,6 +609,17 @@ void llvm::deleteDeadLoop(Loop *L, DominatorTree *DT, ScalarEvolution *SE, llvm::SmallVector DeadDbgVariableRecords; if (ExitBlock) { + if (ExitBlock->phis().empty()) { + // As the loop is deleted, replace the debug users with the preserved + // induction variable final value recorded by the 'indvar' pass. + Value *FinalValue = L->getDebugInductionVariableFinalValue(); + SmallVector &DbgUsers = L->getDebugInductionVariableDebugUsers(); + for (WeakVH &DebugUser : DbgUsers) + if (DebugUser) + cast(DebugUser)->replaceVariableLocationOp( + 0u, FinalValue); + } + // Given LCSSA form is satisfied, we should not have users of instructions // within the dead loop outside of the loop. However, LCSSA doesn't take // unreachable uses into account. We handle them here. @@ -1401,6 +1413,36 @@ static bool checkIsIndPhi(PHINode *Phi, Loop *L, ScalarEvolution *SE, return InductionDescriptor::isInductionPHI(Phi, L, SE, ID); } +void llvm::addDebugValuesToIncomingValue(BasicBlock *Successor, Value *IndVar, + PHINode *PN) { + SmallVector DbgUsers; + findDbgUsers(DbgUsers, IndVar); + for (auto *DebugUser : DbgUsers) { + // Skip debug-users with variadic variable locations; they will not, + // get updated, which is fine as that is the existing behaviour. + if (DebugUser->hasArgList()) + continue; + auto *Cloned = cast(DebugUser->clone()); + Cloned->replaceVariableLocationOp(0u, PN); + Cloned->insertBefore(*Successor, Successor->getFirstNonPHIIt()); + } +} + +void llvm::addDebugValuesToLoopVariable(BasicBlock *Successor, Value *ExitValue, + PHINode *PN) { + SmallVector DbgUsers; + findDbgUsers(DbgUsers, PN); + for (auto *DebugUser : DbgUsers) { + // Skip debug-users with variadic variable locations; they will not, + // get updated, which is fine as that is the existing behaviour. + if (DebugUser->hasArgList()) + continue; + auto *Cloned = cast(DebugUser->clone()); + Cloned->replaceVariableLocationOp(0u, ExitValue); + Cloned->insertBefore(*Successor, Successor->getFirstNonPHIIt()); + } +} + int llvm::rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, ScalarEvolution *SE, const TargetTransformInfo *TTI, @@ -1542,6 +1584,10 @@ int llvm::rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, (isa(Inst) || isa(Inst)) ? &*Inst->getParent()->getFirstInsertionPt() : Inst; RewritePhiSet.emplace_back(PN, i, ExitValue, InsertPt, HighCost); + + // Add debug values for the candidate PHINode incoming value. + if (BasicBlock *Successor = ExitBB->getSingleSuccessor()) + addDebugValuesToIncomingValue(Successor, PN->getIncomingValue(i), PN); } } } @@ -1600,11 +1646,30 @@ int llvm::rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, // Replace PN with ExitVal if that is legal and does not break LCSSA. if (PN->getNumIncomingValues() == 1 && LI->replacementPreservesLCSSAForm(PN, ExitVal)) { + addDebugValuesToLoopVariable(PN->getParent(), ExitVal, PN); PN->replaceAllUsesWith(ExitVal); PN->eraseFromParent(); } } + // If the loop can be deleted and there are no PHIs to be rewritten (there + // are no loop live-out values), record debug variables corresponding to the + // induction variable with their constant exit-values. Those values will be + // inserted by the 'deletion loop' logic. + if (LoopCanBeDel && RewritePhiSet.empty()) { + if (auto *IndVar = L->getInductionVariable(*SE)) { + const SCEV *PNSCEV = SE->getSCEVAtScope(IndVar, L->getParentLoop()); + if (auto *Const = dyn_cast(PNSCEV)) { + Value *FinalIVValue = Const->getValue(); + if (L->getUniqueExitBlock()) { + SmallVector DbgUsers; + findDbgUsers(DbgUsers, IndVar); + L->preserveDebugInductionVariableInfo(FinalIVValue, DbgUsers); + } + } + } + } + // The insertion point instruction may have been deleted; clear it out // so that the rewriter doesn't trip over it later. Rewriter.clearInsertPoint(); diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735-1.ll b/llvm/test/Transforms/IndVarSimplify/pr51735-1.ll new file mode 100644 index 000000000000..356217985fed --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/pr51735-1.ll @@ -0,0 +1,129 @@ +; RUN: opt -passes="loop(indvars)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --check-prefix=CHECK %s +; RUN: opt -passes="loop(indvars,loop-deletion)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --check-prefix=CHECK %s + +; Make sure that when we delete the loop, that the variable Index has +; the 777 value. + +; As this test case does fire the 'indvars' transformation, the debug values +; are added to the 'for.end' exit block. No debug values are preserved by the +; pass to be used by the 'loop-deletion' pass. + +; CHECK: for.cond: +; CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_INDEX_0:.+]], metadata ![[DBG:[0-9]+]], {{.*}} + +; CHECK: for.extra: +; CHECK: %[[SSA_CALL_0:.+]] = call noundef i32 @"?nop@@YAHH@Z"(i32 noundef %[[SSA_INDEX_0]]), {{.*}} +; CHECK: br i1 %[[SSA_CMP_0:.+]], label %for.cond, label %if.else, {{.*}} + +; CHECK: if.then: +; CHECK: call void @llvm.dbg.value(metadata i32 777, metadata ![[DBG]], {{.*}} +; CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_1:.+]], metadata ![[VAR:[0-9]+]], {{.*}} +; CHECK: br label %for.end, {{.*}} + +; CHECK: if.else: +; CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_2:.+]], metadata ![[VAR:[0-9]+]], {{.*}} +; CHECK: br label %for.end, {{.*}} + +; CHECK: for.end: +; CHECK: call void @llvm.dbg.value(metadata i32 777, metadata ![[DBG]], {{.*}} + +; CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Index"{{.*}}) +; CHECK-DAG: ![[VAR]] = !DILocalVariable(name: "Var"{{.*}}) + +define dso_local noundef i32 @"?nop@@YAHH@Z"(i32 noundef %Param) !dbg !11 { +entry: + %Param.addr = alloca i32, align 4 + store i32 %Param, ptr %Param.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %Param.addr, metadata !32, metadata !DIExpression()), !dbg !35 + ret i32 0, !dbg !36 +} + +define dso_local void @_Z3barv() local_unnamed_addr #1 !dbg !12 { +entry: + call void @llvm.dbg.value(metadata i32 777, metadata !16, metadata !DIExpression()), !dbg !17 + call void @llvm.dbg.value(metadata i32 27, metadata !18, metadata !DIExpression()), !dbg !17 + call void @llvm.dbg.value(metadata i32 1, metadata !19, metadata !DIExpression()), !dbg !17 + call void @llvm.dbg.value(metadata i32 1, metadata !30, metadata !DIExpression()), !dbg !17 + br label %for.cond, !dbg !20 + +for.cond: ; preds = %for.cond, %entry + %Index.0 = phi i32 [ 27, %entry ], [ %inc, %for.extra ], !dbg !17 + call void @llvm.dbg.value(metadata i32 %Index.0, metadata !18, metadata !DIExpression()), !dbg !17 + %cmp = icmp ult i32 %Index.0, 777, !dbg !21 + %inc = add nuw nsw i32 %Index.0, 1, !dbg !24 + call void @llvm.dbg.value(metadata i32 %inc, metadata !18, metadata !DIExpression()), !dbg !17 + br i1 %cmp, label %for.extra, label %if.then, !dbg !25, !llvm.loop !26 + +for.extra: + %call.0 = call noundef i32 @"?nop@@YAHH@Z"(i32 noundef %Index.0), !dbg !21 + %cmp.0 = icmp ult i32 %Index.0, %call.0, !dbg !21 + br i1 %cmp.0, label %for.cond, label %if.else, !dbg !25, !llvm.loop !26 + +if.then: ; preds = %for.cond + %Var.1 = add nsw i32 %Index.0, 1, !dbg !20 + call void @llvm.dbg.value(metadata i32 %Var.1, metadata !19, metadata !DIExpression()), !dbg !20 + br label %for.end, !dbg !20 + +if.else: + %Var.2 = add nsw i32 %Index.0, 2, !dbg !20 + call void @llvm.dbg.value(metadata i32 %Var.2, metadata !19, metadata !DIExpression()), !dbg !20 + br label %for.end, !dbg !20 + +for.end: ; preds = %if.else, %if.then + %Zeta.0 = phi i32 [ %Var.1, %if.then ], [ %Var.2, %if.else ], !dbg !20 + call void @llvm.dbg.value(metadata i32 %Zeta.0, metadata !30, metadata !DIExpression()), !dbg !20 + %Var.3 = add nsw i32 %Index.0, 1, !dbg !20 + call void @llvm.dbg.value(metadata i32 %Var.3, metadata !19, metadata !DIExpression()), !dbg !20 + %call = call noundef i32 @"?nop@@YAHH@Z"(i32 noundef %Index.0), !dbg !37 + ret void, !dbg !29 +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{!"clang version 18.0.0"} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = distinct !DISubprogram(name: "nop", linkageName: "?nop@@YAHH@Z", scope: !1, file: !1, line: 1, type: !33, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !31) +!12 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !13, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !15) +!13 = !DISubroutineType(types: !14) +!14 = !{null} +!15 = !{} +!16 = !DILocalVariable(name: "End", scope: !12, file: !1, line: 6, type: !10) +!17 = !DILocation(line: 0, scope: !12) +!18 = !DILocalVariable(name: "Index", scope: !12, file: !1, line: 7, type: !10) +!19 = !DILocalVariable(name: "Var", scope: !12, file: !1, line: 8, type: !10) +!20 = !DILocation(line: 9, column: 3, scope: !12) +!21 = !DILocation(line: 9, column: 16, scope: !22) +!22 = distinct !DILexicalBlock(scope: !23, file: !1, line: 9, column: 3) +!23 = distinct !DILexicalBlock(scope: !12, file: !1, line: 9, column: 3) +!24 = !DILocation(line: 9, column: 23, scope: !22) +!25 = !DILocation(line: 9, column: 3, scope: !23) +!26 = distinct !{!26, !25, !27, !28} +!27 = !DILocation(line: 10, column: 5, scope: !23) +!28 = !{!"llvm.loop.mustprogress"} +!29 = !DILocation(line: 12, column: 1, scope: !12) +!30 = !DILocalVariable(name: "Zeta", scope: !12, file: !1, line: 8, type: !10) +!31 = !{!32} +!32 = !DILocalVariable(name: "Param", arg: 1, scope: !11, file: !1, line: 1, type: !10) +!33 = !DISubroutineType(types: !34) +!34 = !{!10, !10} +!35 = !DILocation(line: 1, scope: !11) +!36 = !DILocation(line: 2, scope: !11) +!37 = !DILocation(line: 20, scope: !12) diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735-2.ll b/llvm/test/Transforms/IndVarSimplify/pr51735-2.ll new file mode 100644 index 000000000000..58cc9932e04c --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/pr51735-2.ll @@ -0,0 +1,128 @@ +; RUN: opt -passes="loop(indvars)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ +; RUN: --check-prefix=ALL-CHECK --check-prefix=PRE-CHECK %s +; RUN: opt -passes="loop(indvars,loop-deletion)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ +; RUN: --check-prefix=ALL-CHECK --check-prefix=POST-CHECK %s + +; Check what happens to a modified but otherwise unused variable in a loop +; that gets deleted. The assignment in the loop is 'forgotten' by LLVM and +; doesn't appear in the debugging information. This behaviour is suboptimal, +; but we want to know if it changes + +; For all cases, LLDB shows +; Var = + +; 1 __attribute__((optnone)) int nop() { +; 2 return 0; +; 3 } +; 4 +; 5 void bar() { +; 6 int End = 777; +; 7 int Index = 27; +; 8 char Var = 1; +; 9 for (; Index < End; ++Index) { +; 10 if (Index == 666) { +; 11 ++Var; +; 12 } +; 13 } +; 14 nop(); +; 15 } + +; ALL-CHECK: entry: +; ALL-CHECK: call void @llvm.dbg.value(metadata i32 1, metadata ![[DBG:[0-9]+]], {{.*}} + +; Only the 'indvars' pass is executed. +; PRE-CHECK: for.cond: +; PRE-CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_0:.+]], metadata ![[DBG]], {{.*}} +; PRE-CHECK: call void @llvm.dbg.value(metadata !DIArgList{{.*}} + +; PRE-CHECK: for.body: +; PRE-CHECK: {{.*}} = icmp eq i32 %[[SSA_INDEX_0:.+]], 666 +; PRE-CHECK: {{.*}} = add nsw i32 %[[SSA_VAR_0]], 1 +; PRE-CHECK: {{.*}} = select i1 {{.*}}, i32 {{.*}}, i32 %[[SSA_VAR_0]] +; PRE-CHECK: call void @llvm.dbg.value(metadata i32 {{.*}}, metadata ![[DBG]], {{.*}} +; PRE-CHECK: br label %for.cond + +; PRE-CHECK: for.end: +; PRE-CHECK: ret void +; PRE-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) + +; The 'indvars' and 'loop-deletion' passes are executed. +; POST-CHECK: for.end: +; POST-CHECK: call void @llvm.dbg.value(metadata i32 undef, metadata ![[DBG:[0-9]+]], {{.*}} +; POST-CHECK: ret void +; POST-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) + +define dso_local void @_Z3barv() local_unnamed_addr !dbg !18 { +entry: + call void @llvm.dbg.value(metadata i32 1, metadata !24, metadata !DIExpression()), !dbg !22 + br label %for.cond, !dbg !25 + +for.cond: ; preds = %for.cond, %entry + %Index.0 = phi i32 [ 27, %entry ], [ %inc2, %for.body ], !dbg !22 + %Var.0 = phi i32 [ 1, %entry ], [ %spec.select, %for.body ], !dbg !22 + call void @llvm.dbg.value(metadata i32 %Var.0, metadata !24, metadata !DIExpression()), !dbg !22 + %cmp = icmp ult i32 %Index.0, 777, !dbg !26 + call void @llvm.dbg.value(metadata !DIArgList(i32 poison, i32 %Index.0), metadata !24, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 666, DW_OP_eq, DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_plus, DW_OP_stack_value)), !dbg !22 + %inc2 = add nuw nsw i32 %Index.0, 1, !dbg !29 + br i1 %cmp, label %for.body, label %for.end, !dbg !30, !llvm.loop !31 + +for.body: ; preds = %for.cond + %cmp1 = icmp eq i32 %Index.0, 666, !dbg !30 + %inc = add nsw i32 %Var.0, 1 + %spec.select = select i1 %cmp1, i32 %inc, i32 %Var.0, !dbg !32 + call void @llvm.dbg.value(metadata i32 %spec.select, metadata !24, metadata !DIExpression()), !dbg !22 + br label %for.cond, !dbg !34, !llvm.loop !35 + +for.end: ; preds = %for.cond + ret void, !dbg !35 +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test-b.cpp", directory: "") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{!"clang version 19.0.0"} +!10 = distinct !DISubprogram(name: "nop", linkageName: "_Z3nopi", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) +!11 = !DISubroutineType(types: !12) +!12 = !{!13, !13} +!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!14 = !{} +!15 = !DILocalVariable(name: "Param", arg: 1, scope: !10, file: !1, line: 1, type: !13) +!16 = !DILocation(line: 1, column: 38, scope: !10) +!17 = !DILocation(line: 2, column: 3, scope: !10) +!18 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !19, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) +!19 = !DISubroutineType(types: !20) +!20 = !{null} +!22 = !DILocation(line: 0, scope: !18) +!24 = !DILocalVariable(name: "Var", scope: !18, file: !1, line: 8, type: !13) +!25 = !DILocation(line: 9, column: 3, scope: !18) +!26 = !DILocation(line: 9, column: 16, scope: !27) +!27 = distinct !DILexicalBlock(scope: !28, file: !1, line: 9, column: 3) +!28 = distinct !DILexicalBlock(scope: !18, file: !1, line: 9, column: 3) +!29 = !DILocation(line: 9, column: 23, scope: !27) +!30 = !DILocation(line: 9, column: 3, scope: !28) +!31 = distinct !{!31, !30, !32, !33} +!32 = !DILocation(line: 11, column: 9, scope: !28) +!33 = !{!"llvm.loop.mustprogress"} +!34 = !DILocation(line: 12, column: 3, scope: !18) +!35 = !DILocation(line: 13, column: 1, scope: !18) +!36 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 15, type: !37, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!37 = !DISubroutineType(types: !38) +!38 = !{!13} +!39 = !DILocation(line: 16, column: 3, scope: !36) +!40 = !DILocation(line: 17, column: 1, scope: !36) diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735-3.ll b/llvm/test/Transforms/IndVarSimplify/pr51735-3.ll new file mode 100644 index 000000000000..ac9964743e0f --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/pr51735-3.ll @@ -0,0 +1,131 @@ +; RUN: opt -passes="loop(indvars)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ +; RUN: --check-prefix=ALL-CHECK --check-prefix=PRE-CHECK %s +; RUN: opt -passes="loop(indvars,loop-deletion)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ +; RUN: --check-prefix=ALL-CHECK --check-prefix=POST-CHECK %s + +; Check what happens to a modified but otherwise unused variable in a loop +; that gets deleted. The assignment in the loop is 'forgotten' by LLVM and +; doesn't appear in the debugging information. This behaviour is suboptimal, +; but we want to know if it changes + +; For all cases, LLDB shows +; Var = + +; 1 __attribute__((optnone)) int nop() { +; 2 return 0; +; 3 } +; 4 +; 5 void bar() { +; 6 int End = 777; +; 7 int Index = 27; +; 8 char Var = 1; +; 9 for (; Index < End; ++Index) { +; 10 if (Index == 666) { +; 11 Var = 555; +; 12 } +; 13 } +; 14 nop(); +; 15 } + +; ALL-CHECK: entry: +; ALL-CHECK: call void @llvm.dbg.value(metadata i32 1, metadata ![[DBG:[0-9]+]], {{.*}} + +; Only the 'indvars' pass is executed. +; PRE-CHECK: if.then: +; PRE-CHECK: call void @llvm.dbg.value(metadata i32 555, metadata ![[DBG]], {{.*}} + +; PRE-CHECK: for.inc: +; PRE-CHECK: %[[SSA_VAR_0:.+]] = phi i32 [ 1, %for.body ], [ 555, %if.then ] +; PRE-CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_0]], metadata ![[DBG]], {{.*}} +; PRE-CHECK: {{.*}} = add nuw nsw i32 %[[SSA_INDEX_0:.+]], 1 +; PRE-CHECK: br label %for.cond + +; PRE-CHECK: for.end: +; PRE-CHECK: ret void +; PRE-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) + +; The 'indvars' and 'loop-deletion' passes are executed. +; POST-CHECK: for.end: +; POST-CHECK: call void @llvm.dbg.value(metadata i32 555, metadata ![[DBG]], {{.*}} +; POST-CHECK: ret void +; POST-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) + +define dso_local void @_Z3barv() local_unnamed_addr !dbg !18 { +entry: + call void @llvm.dbg.value(metadata i32 1, metadata !24, metadata !DIExpression()), !dbg !22 + br label %for.cond, !dbg !25 + +for.cond: ; preds = %for.inc, %entry + %Index.0 = phi i32 [ 27, %entry ], [ %inc, %for.inc ], !dbg !22 + %cmp = icmp ult i32 %Index.0, 777, !dbg !26 + br i1 %cmp, label %for.body, label %for.end, !dbg !30, !llvm.loop !29 + +for.body: ; preds = %for.cond + %cmp1 = icmp eq i32 %Index.0, 666, !dbg !30 + br i1 %cmp1, label %if.then, label %for.inc, !dbg !32 + +if.then: ; preds = %for.body + call void @llvm.dbg.value(metadata i32 555, metadata !24, metadata !DIExpression()), !dbg !22 + br label %for.inc, !dbg !34, !llvm.loop !32 + +for.inc: ; preds = %for.body, %if.then + %Var.0 = phi i32 [ 1, %for.body ], [ 555, %if.then ], !dbg !22 + call void @llvm.dbg.value(metadata i32 %Var.0, metadata !24, metadata !DIExpression()), !dbg !22 + %inc = add nuw nsw i32 %Index.0, 1, !dbg !29 + br label %for.cond, !dbg !34, !llvm.loop !35 + +for.end: ; preds = %for.cond + ret void, !dbg !35 +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test-c.cpp", directory: "") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{!"clang version 19.0.0"} +!10 = distinct !DISubprogram(name: "nop", linkageName: "_Z3nopi", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) +!11 = !DISubroutineType(types: !12) +!12 = !{!13, !13} +!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!14 = !{} +!15 = !DILocalVariable(name: "Param", arg: 1, scope: !10, file: !1, line: 1, type: !13) +!16 = !DILocation(line: 1, column: 38, scope: !10) +!17 = !DILocation(line: 2, column: 3, scope: !10) +!18 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !19, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) +!19 = !DISubroutineType(types: !20) +!20 = !{null} +!21 = !DILocalVariable(name: "End", scope: !18, file: !1, line: 6, type: !13) +!22 = !DILocation(line: 0, scope: !18) +!23 = !DILocalVariable(name: "Index", scope: !18, file: !1, line: 7, type: !13) +!24 = !DILocalVariable(name: "Var", scope: !18, file: !1, line: 8, type: !13) +!25 = !DILocation(line: 9, column: 3, scope: !18) +!26 = !DILocation(line: 9, column: 16, scope: !27) +!27 = distinct !DILexicalBlock(scope: !28, file: !1, line: 9, column: 3) +!28 = distinct !DILexicalBlock(scope: !18, file: !1, line: 9, column: 3) +!29 = !DILocation(line: 9, column: 23, scope: !27) +!30 = !DILocation(line: 9, column: 3, scope: !28) +!31 = distinct !{!31, !30, !32, !33} +!32 = !DILocation(line: 11, column: 13, scope: !28) +!33 = !{!"llvm.loop.mustprogress"} +!34 = !DILocation(line: 12, column: 3, scope: !18) +!35 = !DILocation(line: 13, column: 1, scope: !18) +!36 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 15, type: !37, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) +!37 = !DISubroutineType(types: !38) +!38 = !{!13} +!39 = !DILocation(line: 16, column: 3, scope: !36) +!40 = !DILocation(line: 17, column: 1, scope: !36) diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735.ll b/llvm/test/Transforms/IndVarSimplify/pr51735.ll new file mode 100644 index 000000000000..3014b3467852 --- /dev/null +++ b/llvm/test/Transforms/IndVarSimplify/pr51735.ll @@ -0,0 +1,104 @@ +; RUN: opt -passes="loop(indvars)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --check-prefix=PRE-CHECK %s +; RUN: opt -passes="loop(indvars,loop-deletion)" \ +; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ +; RUN: FileCheck --check-prefix=POST-CHECK %s + +; Make sure that when we delete the loop in the code below, that the variable +; Index has the 777 value. + +; 1 __attribute__((optnone)) int nop() { +; 2 return 0; +; 3 } +; 4 +; 5 void bar() { +; 6 int End = 777; +; 7 int Index = 27; +; 8 char Var = 1; +; 9 for (; Index < End; ++Index) +; 10 ; +; 11 nop(); +; 12 } +; 13 +; 14 int main () { +; 15 bar(); +; 16 } + +; Only the 'indvars' pass is executed. +; As this test case does not fire the 'indvars' transformation, no debug values +; are preserved and or added. + +; PRE-CHECK: for.cond: +; PRE-CHECK: call void @llvm.dbg.value(metadata i32 poison, metadata ![[DBG_1:[0-9]+]], {{.*}} +; PRE-CHECK: call void @llvm.dbg.value(metadata i32 poison, metadata ![[DBG_1]], {{.*}} +; PRE-CHECK: br i1 false, label %for.cond, label %for.end + +; PRE-CHECK: for.end: +; PRE-CHECK-NOT: call void @llvm.dbg.value +; PRE-CHECK: ret void +; PRE-CHECK-DAG: ![[DBG_1]] = !DILocalVariable(name: "Index"{{.*}}) + +; The 'indvars' and 'loop-deletion' passes are executed. +; The loop is deleted and the debug values collected by 'indvars' are used by +; 'loop-deletion' to add the induction variable debug value. + +; POST-CHECK: for.end: +; POST-CHECK: call void @llvm.dbg.value(metadata i32 777, metadata ![[DBG_2:[0-9]+]], {{.*}} +; POST-CHECK: ret void +; POST-CHECK-DAG: ![[DBG_2]] = !DILocalVariable(name: "Index"{{.*}}) + +define dso_local void @_Z3barv() local_unnamed_addr #1 !dbg !15 { +entry: + call void @llvm.dbg.value(metadata i32 777, metadata !19, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata i32 27, metadata !21, metadata !DIExpression()), !dbg !20 + call void @llvm.dbg.value(metadata i32 1, metadata !22, metadata !DIExpression()), !dbg !20 + br label %for.cond, !dbg !23 + +for.cond: ; preds = %for.cond, %entry + %Index.0 = phi i32 [ 27, %entry ], [ %inc, %for.cond ], !dbg !20 + call void @llvm.dbg.value(metadata i32 %Index.0, metadata !21, metadata !DIExpression()), !dbg !20 + %cmp = icmp ult i32 %Index.0, 777, !dbg !24 + %inc = add nuw nsw i32 %Index.0, 1, !dbg !27 + call void @llvm.dbg.value(metadata i32 %inc, metadata !21, metadata !DIExpression()), !dbg !20 + br i1 %cmp, label %for.cond, label %for.end, !dbg !28, !llvm.loop !29 + +for.end: ; preds = %for.cond + ret void, !dbg !33 +} + +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} +!llvm.ident = !{!9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{i32 7, !"frame-pointer", i32 2} +!9 = !{!"clang version 18.0.0"} +!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!15 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !16, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !18) +!16 = !DISubroutineType(types: !17) +!17 = !{null} +!18 = !{} +!19 = !DILocalVariable(name: "End", scope: !15, file: !1, line: 6, type: !13) +!20 = !DILocation(line: 0, scope: !15) +!21 = !DILocalVariable(name: "Index", scope: !15, file: !1, line: 7, type: !13) +!22 = !DILocalVariable(name: "Var", scope: !15, file: !1, line: 8, type: !13) +!23 = !DILocation(line: 9, column: 3, scope: !15) +!24 = !DILocation(line: 9, column: 16, scope: !25) +!25 = distinct !DILexicalBlock(scope: !26, file: !1, line: 9, column: 3) +!26 = distinct !DILexicalBlock(scope: !15, file: !1, line: 9, column: 3) +!27 = !DILocation(line: 9, column: 23, scope: !25) +!28 = !DILocation(line: 9, column: 3, scope: !26) +!29 = distinct !{!29, !28, !30, !31} +!30 = !DILocation(line: 10, column: 5, scope: !26) +!31 = !{!"llvm.loop.mustprogress"} +!33 = !DILocation(line: 12, column: 1, scope: !15) -- GitLab From f3b55973645d551d67af7662b815a5f415874ff7 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Mon, 8 Apr 2024 13:24:57 +0800 Subject: [PATCH 109/695] [RISCV] Use larger copies when register tuples are aligned When the encoding of register tuples are aligned, we can use a copy with larger LMUL to reduce copies. Reviewers: preames, topperc, lukel97 Reviewed By: topperc, lukel97 Pull Request: https://github.com/llvm/llvm-project/pull/84455 --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 182 ++++++++++--------- llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir | 30 +-- llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir | 149 +++++++-------- 3 files changed, 169 insertions(+), 192 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 5582de51b17d..a1befaf40d09 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -302,95 +302,108 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned VVOpc, VIOpc; - switch (LMul) { - default: - llvm_unreachable("Impossible LMUL for vector register copy."); - case RISCVII::LMUL_1: - Opc = RISCV::VMV1R_V; - SubRegIdx = RISCV::sub_vrm1_0; - VVOpc = RISCV::PseudoVMV_V_V_M1; - VIOpc = RISCV::PseudoVMV_V_I_M1; - break; - case RISCVII::LMUL_2: - Opc = RISCV::VMV2R_V; - SubRegIdx = RISCV::sub_vrm2_0; - VVOpc = RISCV::PseudoVMV_V_V_M2; - VIOpc = RISCV::PseudoVMV_V_I_M2; - break; - case RISCVII::LMUL_4: - Opc = RISCV::VMV4R_V; - SubRegIdx = RISCV::sub_vrm4_0; - VVOpc = RISCV::PseudoVMV_V_V_M4; - VIOpc = RISCV::PseudoVMV_V_I_M4; - break; - case RISCVII::LMUL_8: - assert(NF == 1); - Opc = RISCV::VMV8R_V; - SubRegIdx = RISCV::sub_vrm1_0; // There is no sub_vrm8_0. - VVOpc = RISCV::PseudoVMV_V_V_M8; - VIOpc = RISCV::PseudoVMV_V_I_M8; - break; - } - - bool UseVMV_V_V = false; - bool UseVMV_V_I = false; - MachineBasicBlock::const_iterator DefMBBI; - if (isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { - UseVMV_V_V = true; - Opc = VVOpc; - - if (DefMBBI->getOpcode() == VIOpc) { - UseVMV_V_I = true; - Opc = VIOpc; + uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg); + uint16_t DstEncoding = TRI->getEncodingValue(DstReg); + auto [LMulVal, Fractional] = RISCVVType::decodeVLMUL(LMul); + assert(!Fractional && "It is impossible be fractional lmul here."); + unsigned NumRegs = NF * LMulVal; + bool ReversedCopy = + forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NumRegs); + if (ReversedCopy) { + // If the src and dest overlap when copying a tuple, we need to copy the + // registers in reverse. + SrcEncoding += NumRegs - 1; + DstEncoding += NumRegs - 1; + } + + unsigned I = 0; + auto GetCopyInfo = [&](uint16_t SrcEncoding, uint16_t DstEncoding) + -> std::tuple { + if (ReversedCopy) { + // For reversed copying, if there are enough aligned registers(8/4/2), we + // can do a larger copy(LMUL8/4/2). + // Besides, we have already known that DstEncoding is larger than + // SrcEncoding in forwardCopyWillClobberTuple, so the difference between + // DstEncoding and SrcEncoding should be >= LMUL value we try to use to + // avoid clobbering. + uint16_t Diff = DstEncoding - SrcEncoding; + if (I + 8 <= NumRegs && Diff >= 8 && SrcEncoding % 8 == 7 && + DstEncoding % 8 == 7) + return {RISCVII::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V, + RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8}; + if (I + 4 <= NumRegs && Diff >= 4 && SrcEncoding % 4 == 3 && + DstEncoding % 4 == 3) + return {RISCVII::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V, + RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4}; + if (I + 2 <= NumRegs && Diff >= 2 && SrcEncoding % 2 == 1 && + DstEncoding % 2 == 1) + return {RISCVII::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V, + RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2}; + // Or we should do LMUL1 copying. + return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V, + RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1}; } - } - if (NF == 1) { - auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), DstReg); - if (UseVMV_V_V) - MIB.addReg(DstReg, RegState::Undef); - if (UseVMV_V_I) - MIB = MIB.add(DefMBBI->getOperand(2)); - else - MIB = MIB.addReg(SrcReg, getKillRegState(KillSrc)); - if (UseVMV_V_V) { - const MCInstrDesc &Desc = DefMBBI->getDesc(); - MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL - MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW - MIB.addImm(0); // tu, mu - MIB.addReg(RISCV::VL, RegState::Implicit); - MIB.addReg(RISCV::VTYPE, RegState::Implicit); + // For forward copying, if source register encoding and destination register + // encoding are aligned to 8/4/2, we can do a LMUL8/4/2 copying. + if (I + 8 <= NumRegs && SrcEncoding % 8 == 0 && DstEncoding % 8 == 0) + return {RISCVII::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V, + RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8}; + if (I + 4 <= NumRegs && SrcEncoding % 4 == 0 && DstEncoding % 4 == 0) + return {RISCVII::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V, + RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4}; + if (I + 2 <= NumRegs && SrcEncoding % 2 == 0 && DstEncoding % 2 == 0) + return {RISCVII::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V, + RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2}; + // Or we should do LMUL1 copying. + return {RISCVII::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V, + RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1}; + }; + auto FindRegWithEncoding = [&TRI](const TargetRegisterClass &RegClass, + uint16_t Encoding) { + ArrayRef Regs = RegClass.getRegisters(); + const auto *FoundReg = llvm::find_if(Regs, [&](MCPhysReg Reg) { + return TRI->getEncodingValue(Reg) == Encoding; + }); + // We should be always able to find one valid register. + assert(FoundReg != Regs.end()); + return *FoundReg; + }; + while (I != NumRegs) { + // For non-segment copying, we only do this once as the registers are always + // aligned. + // For segment copying, we may do this several times. If the registers are + // aligned to larger LMUL, we can eliminate some copyings. + auto [LMulCopied, RegClass, Opc, VVOpc, VIOpc] = + GetCopyInfo(SrcEncoding, DstEncoding); + auto [NumCopied, _] = RISCVVType::decodeVLMUL(LMulCopied); + + MachineBasicBlock::const_iterator DefMBBI; + if (LMul == LMulCopied && + isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) { + Opc = VVOpc; + if (DefMBBI->getOpcode() == VIOpc) + Opc = VIOpc; } - return; - } - int I = 0, End = NF, Incr = 1; - unsigned SrcEncoding = TRI->getEncodingValue(SrcReg); - unsigned DstEncoding = TRI->getEncodingValue(DstReg); - unsigned LMulVal; - bool Fractional; - std::tie(LMulVal, Fractional) = RISCVVType::decodeVLMUL(LMul); - assert(!Fractional && "It is impossible be fractional lmul here."); - if (forwardCopyWillClobberTuple(DstEncoding, SrcEncoding, NF * LMulVal)) { - I = NF - 1; - End = -1; - Incr = -1; - } - - for (; I != End; I += Incr) { - auto MIB = - BuildMI(MBB, MBBI, DL, get(Opc), TRI->getSubReg(DstReg, SubRegIdx + I)); - if (UseVMV_V_V) - MIB.addReg(TRI->getSubReg(DstReg, SubRegIdx + I), RegState::Undef); + // Emit actual copying. + // For reversed copying, the encoding should be decreased. + MCRegister ActualSrcReg = FindRegWithEncoding( + RegClass, ReversedCopy ? (SrcEncoding - NumCopied + 1) : SrcEncoding); + MCRegister ActualDstReg = FindRegWithEncoding( + RegClass, ReversedCopy ? (DstEncoding - NumCopied + 1) : DstEncoding); + + auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), ActualDstReg); + bool UseVMV_V_I = RISCV::getRVVMCOpcode(Opc) == RISCV::VMV_V_I; + bool UseVMV = UseVMV_V_I || RISCV::getRVVMCOpcode(Opc) == RISCV::VMV_V_V; + if (UseVMV) + MIB.addReg(ActualDstReg, RegState::Undef); if (UseVMV_V_I) MIB = MIB.add(DefMBBI->getOperand(2)); else - MIB = MIB.addReg(TRI->getSubReg(SrcReg, SubRegIdx + I), - getKillRegState(KillSrc)); - if (UseVMV_V_V) { + MIB = MIB.addReg(ActualSrcReg, getKillRegState(KillSrc)); + if (UseVMV) { const MCInstrDesc &Desc = DefMBBI->getDesc(); MIB.add(DefMBBI->getOperand(RISCVII::getVLOpNum(Desc))); // AVL MIB.add(DefMBBI->getOperand(RISCVII::getSEWOpNum(Desc))); // SEW @@ -398,6 +411,11 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, MIB.addReg(RISCV::VL, RegState::Implicit); MIB.addReg(RISCV::VTYPE, RegState::Implicit); } + + // If we are copying reversely, we should decrease the encoding. + SrcEncoding += (ReversedCopy ? -NumCopied : NumCopied); + DstEncoding += (ReversedCopy ? -NumCopied : NumCopied); + I += NumCopied; } } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir b/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir index 4fa29e174602..5bb6ce250e8d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir @@ -8,7 +8,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 82 = e32,m4 ; CHECK-LABEL: name: copy_different_lmul ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -25,7 +24,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 82 = e32,m4 ; CHECK-LABEL: name: copy_convert_to_vmv_v_v ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -42,7 +40,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14 - ; 82 = e32,m4 ; CHECK-LABEL: name: copy_convert_to_vmv_v_i ; CHECK: liveins: $x14 ; CHECK-NEXT: {{ $}} @@ -59,7 +56,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 82 = e32,m4 ; CHECK-LABEL: name: copy_from_whole_load_store ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -76,7 +72,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 82 = e32,m4 ; CHECK-LABEL: name: copy_with_vleff ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -95,8 +90,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16, $x17, $x18 - ; 82 = e32,m4 - ; 73 = e16,m2 ; CHECK-LABEL: name: copy_with_vsetvl_x0_x0_1 ; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK-NEXT: {{ $}} @@ -121,8 +114,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16, $x17, $x18 - ; 82 = e32,m4 - ; 73 = e16,m2 ; CHECK-LABEL: name: copy_with_vsetvl_x0_x0_2 ; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK-NEXT: {{ $}} @@ -147,8 +138,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16, $x17, $x18 - ; 82 = e32,m4 - ; 73 = e16,m2 ; CHECK-LABEL: name: copy_with_vsetvl_x0_x0_3 ; CHECK: liveins: $x14, $x16, $x17, $x18 ; CHECK-NEXT: {{ $}} @@ -169,7 +158,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x16, $x17 - ; 73 = e16,m2 ; CHECK-LABEL: name: copy_subregister ; CHECK: liveins: $x16, $x17 ; CHECK-NEXT: {{ $}} @@ -191,8 +179,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 82 = e32,m4 - ; 74 = e16,m4 ; CHECK-LABEL: name: copy_with_different_vlmax ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -231,7 +217,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 80 = e32,m1 ; CHECK-LABEL: name: copy_zvlsseg_reg ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -248,14 +233,12 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 80 = e32,m1 ; CHECK-LABEL: name: copy_zvlsseg_reg_2 ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v10 = PseudoVMV_V_V_M1 undef $v10, $v8, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: $v11 = PseudoVMV_V_V_M1 undef $v11, $v9, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: $v10m2 = VMV2R_V $v8m2 $x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype $v10_v11 = COPY $v8_v9 @@ -266,7 +249,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x14, $x16 - ; 87 = e32,mf2 ; CHECK-LABEL: name: copy_fractional_lmul ; CHECK: liveins: $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -283,7 +265,6 @@ tracksRegLiveness: true body: | bb.0: liveins: $x12, $x14, $x16 - ; 80 = e32,m1 ; CHECK-LABEL: name: copy_implicit_def ; CHECK: liveins: $x12, $x14, $x16 ; CHECK-NEXT: {{ $}} @@ -291,14 +272,7 @@ body: | ; CHECK-NEXT: $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x0 = PseudoVSETIVLI 10, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $v15 = PseudoVLE32_V_M1 undef $v15, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit killed $v8_v9_v10_v11_v12_v13_v14_v15, implicit-def $v8_v9_v10_v11_v12_v13_v14_v15 - ; CHECK-NEXT: $v24 = VMV1R_V killed $v8 - ; CHECK-NEXT: $v25 = VMV1R_V killed $v9 - ; CHECK-NEXT: $v26 = VMV1R_V killed $v10 - ; CHECK-NEXT: $v27 = VMV1R_V killed $v11 - ; CHECK-NEXT: $v28 = VMV1R_V killed $v12 - ; CHECK-NEXT: $v29 = VMV1R_V killed $v13 - ; CHECK-NEXT: $v30 = VMV1R_V killed $v14 - ; CHECK-NEXT: $v31 = VMV1R_V killed $v15 + ; CHECK-NEXT: $v24m8 = VMV8R_V killed $v8m8 $x0 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5, 0, implicit $vl, implicit $vtype $x0 = PseudoVSETIVLI 10, 80, implicit-def $vl, implicit-def $vtype diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir index 85bb54471ed3..a44a93449332 100644 --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir @@ -7,30 +7,24 @@ name: copy_zvlsseg_N2 body: | bb.0: ; CHECK-LABEL: name: copy_zvlsseg_N2 - ; CHECK: $v2 = VMV1R_V $v4 - ; CHECK-NEXT: $v3 = VMV1R_V $v5 + ; CHECK: $v2m2 = VMV2R_V $v4m2 ; CHECK-NEXT: $v3 = VMV1R_V $v4 ; CHECK-NEXT: $v4 = VMV1R_V $v5 ; CHECK-NEXT: $v6 = VMV1R_V $v5 ; CHECK-NEXT: $v5 = VMV1R_V $v4 - ; CHECK-NEXT: $v6 = VMV1R_V $v4 - ; CHECK-NEXT: $v7 = VMV1R_V $v5 - ; CHECK-NEXT: $v0m2 = VMV2R_V $v4m2 - ; CHECK-NEXT: $v2m2 = VMV2R_V $v6m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m2 + ; CHECK-NEXT: $v0m4 = VMV4R_V $v4m4 ; CHECK-NEXT: $v2m2 = VMV2R_V $v4m2 ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m2 - ; CHECK-NEXT: $v8m2 = VMV2R_V $v4m2 - ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2 - ; CHECK-NEXT: $v0m4 = VMV4R_V $v8m4 - ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v4m4 + ; CHECK-NEXT: $v0m8 = VMV8R_V $v8m8 ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m4 ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4 ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m4 - ; CHECK-NEXT: $v16m4 = VMV4R_V $v8m4 - ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v16m8 = VMV8R_V $v8m8 $v2_v3 = COPY $v4_v5 $v3_v4 = COPY $v4_v5 $v5_v6 = COPY $v4_v5 @@ -55,25 +49,20 @@ body: | ; CHECK-NEXT: $v3 = VMV1R_V $v6 ; CHECK-NEXT: $v4 = VMV1R_V $v7 ; CHECK-NEXT: $v3 = VMV1R_V $v5 - ; CHECK-NEXT: $v4 = VMV1R_V $v6 - ; CHECK-NEXT: $v5 = VMV1R_V $v7 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v4 = VMV1R_V $v5 ; CHECK-NEXT: $v5 = VMV1R_V $v6 ; CHECK-NEXT: $v6 = VMV1R_V $v7 - ; CHECK-NEXT: $v9 = VMV1R_V $v7 - ; CHECK-NEXT: $v8 = VMV1R_V $v6 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v7 = VMV1R_V $v5 ; CHECK-NEXT: $v9 = VMV1R_V $v5 - ; CHECK-NEXT: $v10 = VMV1R_V $v6 - ; CHECK-NEXT: $v11 = VMV1R_V $v7 + ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v0m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v2m2 = VMV2R_V $v8m2 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v2m2 = VMV2R_V $v6m2 - ; CHECK-NEXT: $v4m2 = VMV2R_V $v8m2 - ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2 - ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 - ; CHECK-NEXT: $v12m2 = VMV2R_V $v8m2 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m4 + ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m4 ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v12m2 = VMV2R_V $v6m2 ; CHECK-NEXT: $v14m2 = VMV2R_V $v8m2 @@ -94,10 +83,8 @@ name: copy_zvlsseg_N4 body: | bb.0: ; CHECK-LABEL: name: copy_zvlsseg_N4 - ; CHECK: $v6 = VMV1R_V $v10 - ; CHECK-NEXT: $v7 = VMV1R_V $v11 - ; CHECK-NEXT: $v8 = VMV1R_V $v12 - ; CHECK-NEXT: $v9 = VMV1R_V $v13 + ; CHECK: $v6m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2 ; CHECK-NEXT: $v7 = VMV1R_V $v10 ; CHECK-NEXT: $v8 = VMV1R_V $v11 ; CHECK-NEXT: $v9 = VMV1R_V $v12 @@ -106,13 +93,10 @@ body: | ; CHECK-NEXT: $v15 = VMV1R_V $v12 ; CHECK-NEXT: $v14 = VMV1R_V $v11 ; CHECK-NEXT: $v13 = VMV1R_V $v10 - ; CHECK-NEXT: $v14 = VMV1R_V $v10 - ; CHECK-NEXT: $v15 = VMV1R_V $v11 - ; CHECK-NEXT: $v16 = VMV1R_V $v12 - ; CHECK-NEXT: $v17 = VMV1R_V $v13 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v12m2 ; CHECK-NEXT: $v2m2 = VMV2R_V $v10m2 - ; CHECK-NEXT: $v4m2 = VMV2R_V $v12m2 - ; CHECK-NEXT: $v6m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4 ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 @@ -123,8 +107,7 @@ body: | ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2 - ; CHECK-NEXT: $v20m2 = VMV2R_V $v12m2 - ; CHECK-NEXT: $v22m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4 ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2 $v6_v7_v8_v9 = COPY $v10_v11_v12_v13 $v7_v8_v9_v10 = COPY $v10_v11_v12_v13 @@ -146,57 +129,59 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v12 ; CHECK-NEXT: $v8 = VMV1R_V $v13 ; CHECK-NEXT: $v9 = VMV1R_V $v14 - ; CHECK-NEXT: $v6 = VMV1R_V $v10 - ; CHECK-NEXT: $v7 = VMV1R_V $v11 - ; CHECK-NEXT: $v8 = VMV1R_V $v12 - ; CHECK-NEXT: $v9 = VMV1R_V $v13 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2 ; CHECK-NEXT: $v10 = VMV1R_V $v14 ; CHECK-NEXT: $v18 = VMV1R_V $v14 - ; CHECK-NEXT: $v17 = VMV1R_V $v13 - ; CHECK-NEXT: $v16 = VMV1R_V $v12 - ; CHECK-NEXT: $v15 = VMV1R_V $v11 - ; CHECK-NEXT: $v14 = VMV1R_V $v10 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v15 = VMV1R_V $v10 ; CHECK-NEXT: $v16 = VMV1R_V $v11 ; CHECK-NEXT: $v17 = VMV1R_V $v12 ; CHECK-NEXT: $v18 = VMV1R_V $v13 ; CHECK-NEXT: $v19 = VMV1R_V $v14 + ; CHECK-NEXT: $v7 = VMV1R_V $v11 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v15 = VMV1R_V $v11 $v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14 $v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14 $v14_v15_v16_v17_v18 = COPY $v10_v11_v12_v13_v14 $v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14 + $v7_v8_v9_v10_v11 = COPY $v11_v12_v13_v14_v15 + $v15_v16_v17_v18_v19 = COPY $v11_v12_v13_v14_v15 ... --- name: copy_zvlsseg_N6 body: | bb.0: ; CHECK-LABEL: name: copy_zvlsseg_N6 - ; CHECK: $v4 = VMV1R_V $v10 - ; CHECK-NEXT: $v5 = VMV1R_V $v11 - ; CHECK-NEXT: $v6 = VMV1R_V $v12 - ; CHECK-NEXT: $v7 = VMV1R_V $v13 - ; CHECK-NEXT: $v8 = VMV1R_V $v14 - ; CHECK-NEXT: $v9 = VMV1R_V $v15 + ; CHECK: $v4m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 ; CHECK-NEXT: $v5 = VMV1R_V $v10 ; CHECK-NEXT: $v6 = VMV1R_V $v11 ; CHECK-NEXT: $v7 = VMV1R_V $v12 ; CHECK-NEXT: $v8 = VMV1R_V $v13 ; CHECK-NEXT: $v9 = VMV1R_V $v14 ; CHECK-NEXT: $v10 = VMV1R_V $v15 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v20 = VMV1R_V $v15 ; CHECK-NEXT: $v19 = VMV1R_V $v14 ; CHECK-NEXT: $v18 = VMV1R_V $v13 ; CHECK-NEXT: $v17 = VMV1R_V $v12 ; CHECK-NEXT: $v16 = VMV1R_V $v11 ; CHECK-NEXT: $v15 = VMV1R_V $v10 - ; CHECK-NEXT: $v16 = VMV1R_V $v10 - ; CHECK-NEXT: $v17 = VMV1R_V $v11 - ; CHECK-NEXT: $v18 = VMV1R_V $v12 - ; CHECK-NEXT: $v19 = VMV1R_V $v13 - ; CHECK-NEXT: $v20 = VMV1R_V $v14 - ; CHECK-NEXT: $v21 = VMV1R_V $v15 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2 $v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15 $v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15 + $v6_v7_v8_v9_v10_v11 = COPY $v10_v11_v12_v13_v14_v15 + $v14_v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14_v15 $v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15 $v16_v17_v18_v19_v20_v21 = COPY $v10_v11_v12_v13_v14_v15 ... @@ -212,20 +197,17 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 - ; CHECK-NEXT: $v4 = VMV1R_V $v10 - ; CHECK-NEXT: $v5 = VMV1R_V $v11 - ; CHECK-NEXT: $v6 = VMV1R_V $v12 - ; CHECK-NEXT: $v7 = VMV1R_V $v13 - ; CHECK-NEXT: $v8 = VMV1R_V $v14 - ; CHECK-NEXT: $v9 = VMV1R_V $v15 + ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2 ; CHECK-NEXT: $v10 = VMV1R_V $v16 + ; CHECK-NEXT: $v20 = VMV1R_V $v16 + ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v22 = VMV1R_V $v16 - ; CHECK-NEXT: $v21 = VMV1R_V $v15 - ; CHECK-NEXT: $v20 = VMV1R_V $v14 - ; CHECK-NEXT: $v19 = VMV1R_V $v13 - ; CHECK-NEXT: $v18 = VMV1R_V $v12 - ; CHECK-NEXT: $v17 = VMV1R_V $v11 - ; CHECK-NEXT: $v16 = VMV1R_V $v10 + ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2 + ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2 ; CHECK-NEXT: $v17 = VMV1R_V $v10 ; CHECK-NEXT: $v18 = VMV1R_V $v11 ; CHECK-NEXT: $v19 = VMV1R_V $v12 @@ -233,24 +215,28 @@ body: | ; CHECK-NEXT: $v21 = VMV1R_V $v14 ; CHECK-NEXT: $v22 = VMV1R_V $v15 ; CHECK-NEXT: $v23 = VMV1R_V $v16 + ; CHECK-NEXT: $v22 = VMV1R_V $v21 + ; CHECK-NEXT: $v21 = VMV1R_V $v20 + ; CHECK-NEXT: $v20 = VMV1R_V $v19 + ; CHECK-NEXT: $v19 = VMV1R_V $v18 + ; CHECK-NEXT: $v18 = VMV1R_V $v17 + ; CHECK-NEXT: $v17 = VMV1R_V $v16 + ; CHECK-NEXT: $v16 = VMV1R_V $v15 $v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16 $v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v14_v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15_v16 $v16_v17_v18_v19_v20_v21_v22 = COPY $v10_v11_v12_v13_v14_v15_v16 $v17_v18_v19_v20_v21_v22_v23 = COPY $v10_v11_v12_v13_v14_v15_v16 + $v16_v17_v18_v19_v20_v21_v22 = COPY $v15_v16_v17_v18_v19_v20_v21 ... --- name: copy_zvlsseg_N8 body: | bb.0: ; CHECK-LABEL: name: copy_zvlsseg_N8 - ; CHECK: $v2 = VMV1R_V $v10 - ; CHECK-NEXT: $v3 = VMV1R_V $v11 - ; CHECK-NEXT: $v4 = VMV1R_V $v12 - ; CHECK-NEXT: $v5 = VMV1R_V $v13 - ; CHECK-NEXT: $v6 = VMV1R_V $v14 - ; CHECK-NEXT: $v7 = VMV1R_V $v15 - ; CHECK-NEXT: $v8 = VMV1R_V $v16 - ; CHECK-NEXT: $v9 = VMV1R_V $v17 + ; CHECK: $v2m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2 ; CHECK-NEXT: $v3 = VMV1R_V $v10 ; CHECK-NEXT: $v4 = VMV1R_V $v11 ; CHECK-NEXT: $v5 = VMV1R_V $v12 @@ -267,16 +253,15 @@ body: | ; CHECK-NEXT: $v19 = VMV1R_V $v12 ; CHECK-NEXT: $v18 = VMV1R_V $v11 ; CHECK-NEXT: $v17 = VMV1R_V $v10 - ; CHECK-NEXT: $v18 = VMV1R_V $v10 - ; CHECK-NEXT: $v19 = VMV1R_V $v11 - ; CHECK-NEXT: $v20 = VMV1R_V $v12 - ; CHECK-NEXT: $v21 = VMV1R_V $v13 - ; CHECK-NEXT: $v22 = VMV1R_V $v14 - ; CHECK-NEXT: $v23 = VMV1R_V $v15 - ; CHECK-NEXT: $v24 = VMV1R_V $v16 - ; CHECK-NEXT: $v25 = VMV1R_V $v17 + ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2 + ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4 + ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2 + ; CHECK-NEXT: $v8m8 = VMV8R_V $v0m8 + ; CHECK-NEXT: $v0m8 = VMV8R_V $v8m8 $v2_v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 $v3_v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 $v17_v18_v19_v20_v21_v22_v23_v24 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 $v18_v19_v20_v21_v22_v23_v24_v25 = COPY $v10_v11_v12_v13_v14_v15_v16_v17 + $v8_v9_v10_v11_v12_v13_v14_v15 = COPY $v0_v1_v2_v3_v4_v5_v6_v7 + $v0_v1_v2_v3_v4_v5_v6_v7 = COPY $v8_v9_v10_v11_v12_v13_v14_v15 ... -- GitLab From 006aaf32258fc27656c936f6aad729e4c77e3847 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Sun, 7 Apr 2024 23:02:19 -0600 Subject: [PATCH 110/695] [ORC] Replace some KV loop variables with structured bindings. This allows us to remove a lot of boilerplate .first and .second references and improve readability. Coding my way home: 1.58814S, 91.93889W --- llvm/lib/ExecutionEngine/Orc/Core.cpp | 315 +++++++++++++------------- 1 file changed, 153 insertions(+), 162 deletions(-) diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp index 8bb68b45951d..43be471fc3c5 100644 --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -87,13 +87,13 @@ FailedToMaterialize::FailedToMaterialize( // FIXME: Use a new dep-map type for FailedToMaterialize errors so that we // don't have to manually retain/release. - for (auto &KV : *this->Symbols) - KV.first->Retain(); + for (auto &[JD, Syms] : *this->Symbols) + JD->Retain(); } FailedToMaterialize::~FailedToMaterialize() { - for (auto &KV : *Symbols) - KV.first->Release(); + for (auto &[JD, Syms] : *Symbols) + JD->Release(); } std::error_code FailedToMaterialize::convertToErrorCode() const { @@ -187,8 +187,8 @@ AsynchronousSymbolQuery::AsynchronousSymbolQuery( OutstandingSymbolsCount = Symbols.size(); - for (auto &KV : Symbols) - ResolvedSymbols[KV.first] = ExecutorSymbolDef(); + for (auto &[Name, Flags] : Symbols) + ResolvedSymbols[Name] = ExecutorSymbolDef(); } void AsynchronousSymbolQuery::notifySymbolMetRequiredState( @@ -271,8 +271,8 @@ void AsynchronousSymbolQuery::dropSymbol(const SymbolStringPtr &Name) { void AsynchronousSymbolQuery::detach() { ResolvedSymbols.clear(); OutstandingSymbolsCount = 0; - for (auto &KV : QueryRegistrations) - KV.first->detachQueryHelper(*this, KV.second); + for (auto &[JD, Syms] : QueryRegistrations) + JD->detachQueryHelper(*this, Syms); QueryRegistrations.clear(); } @@ -312,8 +312,8 @@ void AbsoluteSymbolsMaterializationUnit::discard(const JITDylib &JD, MaterializationUnit::Interface AbsoluteSymbolsMaterializationUnit::extractFlags(const SymbolMap &Symbols) { SymbolFlagsMap Flags; - for (const auto &KV : Symbols) - Flags[KV.first] = KV.second.getFlags(); + for (const auto &[Sym, Def] : Symbols) + Flags[Sym] = Def.getFlags(); return MaterializationUnit::Interface(std::move(Flags), nullptr); } @@ -397,23 +397,23 @@ void ReExportsMaterializationUnit::materialize( SymbolAliasMap QueryAliases; // Collect as many aliases as we can without including a chain. - for (auto &KV : RequestedAliases) { + for (auto &[Alias, Entry] : RequestedAliases) { // Chain detected. Skip this symbol for this round. - if (&SrcJD == &TgtJD && (QueryAliases.count(KV.second.Aliasee) || - RequestedAliases.count(KV.second.Aliasee))) + if (&SrcJD == &TgtJD && (QueryAliases.count(Entry.Aliasee) || + RequestedAliases.count(Entry.Aliasee))) continue; - ResponsibilitySymbols.insert(KV.first); - QuerySymbols.add(KV.second.Aliasee, - KV.second.AliasFlags.hasMaterializationSideEffectsOnly() + ResponsibilitySymbols.insert(Alias); + QuerySymbols.add(Entry.Aliasee, + Entry.AliasFlags.hasMaterializationSideEffectsOnly() ? SymbolLookupFlags::WeaklyReferencedSymbol : SymbolLookupFlags::RequiredSymbol); - QueryAliases[KV.first] = std::move(KV.second); + QueryAliases[Alias] = std::move(Entry); } // Remove the aliases collected this round from the RequestedAliases map. - for (auto &KV : QueryAliases) - RequestedAliases.erase(KV.first); + for (auto &[Alias, Entry] : QueryAliases) + RequestedAliases.erase(Alias); assert(!QuerySymbols.empty() && "Alias cycle detected!"); @@ -458,16 +458,16 @@ void ReExportsMaterializationUnit::materialize( auto &ES = QueryInfo->R->getTargetJITDylib().getExecutionSession(); if (Result) { SymbolMap ResolutionMap; - for (auto &KV : QueryInfo->Aliases) { - assert((KV.second.AliasFlags.hasMaterializationSideEffectsOnly() || - Result->count(KV.second.Aliasee)) && + for (auto &[Alias, Entry] : QueryInfo->Aliases) { + assert((Entry.AliasFlags.hasMaterializationSideEffectsOnly() || + Result->count(Entry.Aliasee)) && "Result map missing entry?"); // Don't try to resolve materialization-side-effects-only symbols. - if (KV.second.AliasFlags.hasMaterializationSideEffectsOnly()) + if (Entry.AliasFlags.hasMaterializationSideEffectsOnly()) continue; - ResolutionMap[KV.first] = {(*Result)[KV.second.Aliasee].getAddress(), - KV.second.AliasFlags}; + ResolutionMap[Alias] = {(*Result)[Entry.Aliasee].getAddress(), + Entry.AliasFlags}; } if (auto Err = QueryInfo->R->notifyResolved(ResolutionMap)) { ES.reportError(std::move(Err)); @@ -502,8 +502,8 @@ void ReExportsMaterializationUnit::discard(const JITDylib &JD, MaterializationUnit::Interface ReExportsMaterializationUnit::extractFlags(const SymbolAliasMap &Aliases) { SymbolFlagsMap SymbolFlags; - for (auto &KV : Aliases) - SymbolFlags[KV.first] = KV.second.AliasFlags; + for (auto &[Alias, Entry] : Aliases) + SymbolFlags[Alias] = Entry.AliasFlags; return MaterializationUnit::Interface(std::move(SymbolFlags), nullptr); } @@ -628,9 +628,9 @@ Error ReexportsGenerator::tryToGenerate(LookupState &LS, LookupKind K, // Create an alias map. orc::SymbolAliasMap AliasMap; - for (auto &KV : *Flags) - if (!Allow || Allow(KV.first)) - AliasMap[KV.first] = SymbolAliasMapEntry(KV.first, KV.second); + for (auto &[Name, Flags] : *Flags) + if (!Allow || Allow(Name)) + AliasMap[Name] = SymbolAliasMapEntry(Name, Flags); if (AliasMap.empty()) return Error::success(); @@ -677,8 +677,8 @@ Error JITDylib::clear() { std::vector TrackersToRemove; ES.runSessionLocked([&]() { assert(State != Closed && "JD is defunct"); - for (auto &KV : TrackerSymbols) - TrackersToRemove.push_back(KV.first); + for (auto &[RT, Syms] : TrackerSymbols) + TrackersToRemove.push_back(RT); TrackersToRemove.push_back(getDefaultResourceTracker()); }); @@ -783,28 +783,27 @@ Error JITDylib::replace(MaterializationResponsibility &FromMR, auto Err = ES.runSessionLocked([&, this]() -> Error { + // If the tracker is defunct we need to bail out immediately. if (FromMR.RT->isDefunct()) return make_error(std::move(FromMR.RT)); #ifndef NDEBUG - for (auto &KV : MU->getSymbols()) { - auto SymI = Symbols.find(KV.first); + for (auto &[Name, Flags] : MU->getSymbols()) { + auto SymI = Symbols.find(Name); assert(SymI != Symbols.end() && "Replacing unknown symbol"); assert(SymI->second.getState() == SymbolState::Materializing && "Can not replace a symbol that ha is not materializing"); assert(!SymI->second.hasMaterializerAttached() && "Symbol should not have materializer attached already"); - assert(UnmaterializedInfos.count(KV.first) == 0 && + assert(UnmaterializedInfos.count(Name) == 0 && "Symbol being replaced should have no UnmaterializedInfo"); } #endif // NDEBUG - // If the tracker is defunct we need to bail out immediately. - // If any symbol has pending queries against it then we need to // materialize MU immediately. - for (auto &KV : MU->getSymbols()) { - auto MII = MaterializingInfos.find(KV.first); + for (auto &[Name, Flags] : MU->getSymbols()) { + auto MII = MaterializingInfos.find(Name); if (MII != MaterializingInfos.end()) { if (MII->second.hasQueriesPending()) { MustRunMR = ES.createMaterializationResponsibility( @@ -819,18 +818,18 @@ Error JITDylib::replace(MaterializationResponsibility &FromMR, // Otherwise, make MU responsible for all the symbols. auto UMI = std::make_shared(std::move(MU), FromMR.RT.get()); - for (auto &KV : UMI->MU->getSymbols()) { - auto SymI = Symbols.find(KV.first); + for (auto &[Name, Flags] : UMI->MU->getSymbols()) { + auto SymI = Symbols.find(Name); assert(SymI->second.getState() == SymbolState::Materializing && "Can not replace a symbol that is not materializing"); assert(!SymI->second.hasMaterializerAttached() && "Can not replace a symbol that has a materializer attached"); - assert(UnmaterializedInfos.count(KV.first) == 0 && + assert(UnmaterializedInfos.count(Name) == 0 && "Unexpected materializer entry in map"); SymI->second.setAddress(SymI->second.getAddress()); SymI->second.setMaterializerAttached(true); - auto &UMIEntry = UnmaterializedInfos[KV.first]; + auto &UMIEntry = UnmaterializedInfos[Name]; assert((!UMIEntry || !UMIEntry->MU) && "Replacing symbol with materializer still attached"); UMIEntry = UMI; @@ -872,19 +871,19 @@ JITDylib::getRequestedSymbols(const SymbolFlagsMap &SymbolFlags) const { return ES.runSessionLocked([&]() { SymbolNameSet RequestedSymbols; - for (auto &KV : SymbolFlags) { - assert(Symbols.count(KV.first) && "JITDylib does not cover this symbol?"); - assert(Symbols.find(KV.first)->second.getState() != + for (auto &[Name, Flags] : SymbolFlags) { + assert(Symbols.count(Name) && "JITDylib does not cover this symbol?"); + assert(Symbols.find(Name)->second.getState() != SymbolState::NeverSearched && - Symbols.find(KV.first)->second.getState() != SymbolState::Ready && + Symbols.find(Name)->second.getState() != SymbolState::Ready && "getRequestedSymbols can only be called for symbols that have " "started materializing"); - auto I = MaterializingInfos.find(KV.first); + auto I = MaterializingInfos.find(Name); if (I == MaterializingInfos.end()) continue; if (I->second.hasQueriesPending()) - RequestedSymbols.insert(KV.first); + RequestedSymbols.insert(Name); } return RequestedSymbols; @@ -914,12 +913,12 @@ Error JITDylib::resolve(MaterializationResponsibility &MR, Worklist.reserve(Resolved.size()); // Build worklist and check for any symbols in the error state. - for (const auto &KV : Resolved) { + for (const auto &[Name, Def] : Resolved) { - assert(!KV.second.getFlags().hasError() && + assert(!Def.getFlags().hasError() && "Resolution result can not have error flag set"); - auto SymI = Symbols.find(KV.first); + auto SymI = Symbols.find(Name); assert(SymI != Symbols.end() && "Symbol not found"); assert(!SymI->second.hasMaterializerAttached() && @@ -930,15 +929,15 @@ Error JITDylib::resolve(MaterializationResponsibility &MR, "Symbol has already been resolved"); if (SymI->second.getFlags().hasError()) - SymbolsInErrorState.insert(KV.first); + SymbolsInErrorState.insert(Name); else { - auto Flags = KV.second.getFlags(); + auto Flags = Def.getFlags(); Flags &= ~JITSymbolFlags::Common; assert(Flags == (SymI->second.getFlags() & ~JITSymbolFlags::Common) && "Resolved flags should match the declared flags"); - Worklist.push_back({SymI, {KV.second.getAddress(), Flags}}); + Worklist.push_back({SymI, {Def.getAddress(), Flags}}); } } @@ -1019,12 +1018,12 @@ void JITDylib::setLinkOrder(JITDylibSearchOrder NewLinkOrder, void JITDylib::addToLinkOrder(const JITDylibSearchOrder &NewLinks) { ES.runSessionLocked([&]() { - for (auto &KV : NewLinks) { + for (auto &Elem : NewLinks) { // Skip elements of NewLinks that are already in the link order. - if (llvm::is_contained(LinkOrder, KV)) + if (llvm::is_contained(LinkOrder, Elem)) continue; - LinkOrder.push_back(std::move(KV)); + LinkOrder.push_back(std::move(Elem)); } }); } @@ -1140,23 +1139,23 @@ void JITDylib::dump(raw_ostream &OS) { // Sort symbols so we get a deterministic order and can check them in tests. std::vector> SymbolsSorted; - for (auto &KV : Symbols) - SymbolsSorted.emplace_back(KV.first, &KV.second); + for (auto &[Name, Entry] : Symbols) + SymbolsSorted.emplace_back(Name, &Entry); std::sort(SymbolsSorted.begin(), SymbolsSorted.end(), [](const auto &L, const auto &R) { return *L.first < *R.first; }); - for (auto &KV : SymbolsSorted) { - OS << " \"" << *KV.first << "\": "; - if (auto Addr = KV.second->getAddress()) + for (auto &[Name, Entry] : SymbolsSorted) { + OS << " \"" << Name << "\": "; + if (auto Addr = Entry->getAddress()) OS << Addr; else OS << " "; - OS << " " << KV.second->getFlags() << " " << KV.second->getState(); + OS << " " << Entry->getFlags() << " " << Entry->getState(); - if (KV.second->hasMaterializerAttached()) { + if (Entry->hasMaterializerAttached()) { OS << " (Materializer "; - auto I = UnmaterializedInfos.find(KV.first); + auto I = UnmaterializedInfos.find(Name); assert(I != UnmaterializedInfos.end() && "Lazy symbol should have UnmaterializedInfo"); OS << I->second->MU.get() << ", " << I->second->MU->getName() << ")\n"; @@ -1166,21 +1165,20 @@ void JITDylib::dump(raw_ostream &OS) { if (!MaterializingInfos.empty()) OS << " MaterializingInfos entries:\n"; - for (auto &KV : MaterializingInfos) { - OS << " \"" << *KV.first << "\":\n" - << " " << KV.second.pendingQueries().size() - << " pending queries: { "; - for (const auto &Q : KV.second.pendingQueries()) + for (auto &[Name, Entry] : MaterializingInfos) { + OS << " \"" << Name << "\":\n" + << " " << Entry.pendingQueries().size() << " pending queries: { "; + for (const auto &Q : Entry.pendingQueries()) OS << Q.get() << " (" << Q->getRequiredState() << ") "; OS << "}\n Defining EDU: "; - if (KV.second.DefiningEDU) { - OS << KV.second.DefiningEDU.get() << " { "; - for (auto &[Name, Flags] : KV.second.DefiningEDU->Symbols) + if (Entry.DefiningEDU) { + OS << Entry.DefiningEDU.get() << " { "; + for (auto &[Name, Flags] : Entry.DefiningEDU->Symbols) OS << Name << " "; OS << "}\n"; OS << " Dependencies:\n"; - if (!KV.second.DefiningEDU->Dependencies.empty()) { - for (auto &[DepJD, Deps] : KV.second.DefiningEDU->Dependencies) { + if (!Entry.DefiningEDU->Dependencies.empty()) { + for (auto &[DepJD, Deps] : Entry.DefiningEDU->Dependencies) { OS << " " << DepJD->getName() << ": [ "; for (auto &Dep : Deps) OS << Dep << " "; @@ -1191,8 +1189,8 @@ void JITDylib::dump(raw_ostream &OS) { } else OS << "none\n"; OS << " Dependant EDUs:\n"; - if (!KV.second.DependantEDUs.empty()) { - for (auto &DependantEDU : KV.second.DependantEDUs) { + if (!Entry.DependantEDUs.empty()) { + for (auto &DependantEDU : Entry.DependantEDUs) { OS << " " << DependantEDU << ": " << DependantEDU->JD->getName() << " { "; for (auto &[Name, Flags] : DependantEDU->Symbols) @@ -1201,9 +1199,9 @@ void JITDylib::dump(raw_ostream &OS) { } } else OS << " none\n"; - assert((Symbols[KV.first].getState() != SymbolState::Ready || - (KV.second.pendingQueries().empty() && !KV.second.DefiningEDU && - !KV.second.DependantEDUs.empty())) && + assert((Symbols[Name].getState() != SymbolState::Ready || + (Entry.pendingQueries().empty() && !Entry.DefiningEDU && + !Entry.DependantEDUs.empty())) && "Stale materializing info entry"); } }); @@ -1262,14 +1260,13 @@ JITDylib::removeTracker(ResourceTracker &RT) { if (&RT == DefaultTracker.get()) { SymbolNameSet TrackedSymbols; - for (auto &KV : TrackerSymbols) - for (auto &Sym : KV.second) + for (auto &[RT, Syms] : TrackerSymbols) + for (auto &Sym : Syms) TrackedSymbols.insert(Sym); - for (auto &KV : Symbols) { - auto &Sym = KV.first; - if (!TrackedSymbols.count(Sym)) - SymbolsToRemove.push_back(Sym); + for (auto &[Name, Entry] : Symbols) { + if (!TrackedSymbols.count(Name)) + SymbolsToRemove.push_back(Name); } DefaultTracker.reset(); @@ -1323,9 +1320,9 @@ void JITDylib::transferTracker(ResourceTracker &DstRT, ResourceTracker &SrcRT) { assert(&SrcRT.getJITDylib() == this && "SrcRT is not for this JITDylib"); // Update trackers for any not-yet materialized units. - for (auto &KV : UnmaterializedInfos) { - if (KV.second->RT == &SrcRT) - KV.second->RT = &DstRT; + for (auto &[Name, Entry] : UnmaterializedInfos) { + if (Entry->RT == &SrcRT) + Entry->RT = &DstRT; } // Update trackers for any active materialization responsibilities. @@ -1363,14 +1360,13 @@ void JITDylib::transferTracker(ResourceTracker &DstRT, ResourceTracker &SrcRT) { SymbolNameVector SymbolsToTrack; SymbolNameSet CurrentlyTrackedSymbols; - for (auto &KV : TrackerSymbols) - for (auto &Sym : KV.second) + for (auto &[Name, Syms] : TrackerSymbols) + for (auto &Sym : Syms) CurrentlyTrackedSymbols.insert(Sym); - for (auto &KV : Symbols) { - auto &Sym = KV.first; - if (!CurrentlyTrackedSymbols.count(Sym)) - SymbolsToTrack.push_back(Sym); + for (auto &[Name, Entry] : Symbols) { + if (!CurrentlyTrackedSymbols.count(Name)) + SymbolsToTrack.push_back(Name); } TrackerSymbols[&DstRT] = std::move(SymbolsToTrack); @@ -1398,22 +1394,22 @@ Error JITDylib::defineImpl(MaterializationUnit &MU) { std::vector ExistingDefsOverridden; std::vector MUDefsOverridden; - for (const auto &KV : MU.getSymbols()) { - auto I = Symbols.find(KV.first); + for (const auto &[Name, Flags] : MU.getSymbols()) { + auto I = Symbols.find(Name); if (I != Symbols.end()) { - if (KV.second.isStrong()) { + if (Flags.isStrong()) { if (I->second.getFlags().isStrong() || I->second.getState() > SymbolState::NeverSearched) - Duplicates.insert(KV.first); + Duplicates.insert(Name); else { assert(I->second.getState() == SymbolState::NeverSearched && "Overridden existing def should be in the never-searched " "state"); - ExistingDefsOverridden.push_back(KV.first); + ExistingDefsOverridden.push_back(Name); } } else - MUDefsOverridden.push_back(KV.first); + MUDefsOverridden.push_back(Name); } } @@ -1447,9 +1443,9 @@ Error JITDylib::defineImpl(MaterializationUnit &MU) { } // Finally, add the defs from this MU. - for (auto &KV : MU.getSymbols()) { - auto &SymEntry = Symbols[KV.first]; - SymEntry.setFlags(KV.second); + for (auto &[Name, Flags] : MU.getSymbols()) { + auto &SymEntry = Symbols[Name]; + SymEntry.setFlags(Flags); SymEntry.setState(SymbolState::NeverSearched); SymEntry.setMaterializerAttached(true); } @@ -1464,13 +1460,13 @@ void JITDylib::installMaterializationUnit( if (&RT != DefaultTracker.get()) { auto &TS = TrackerSymbols[&RT]; TS.reserve(TS.size() + MU->getSymbols().size()); - for (auto &KV : MU->getSymbols()) - TS.push_back(KV.first); + for (auto &[Name, Flags] : MU->getSymbols()) + TS.push_back(Name); } auto UMI = std::make_shared(std::move(MU), &RT); - for (auto &KV : UMI->MU->getSymbols()) - UnmaterializedInfos[KV.first] = UMI; + for (auto &[Name, Flags] : UMI->MU->getSymbols()) + UnmaterializedInfos[Name] = UMI; } void JITDylib::detachQueryHelper(AsynchronousSymbolQuery &Q, @@ -1497,18 +1493,18 @@ Expected> Platform::lookupInitSymbols( LLVM_DEBUG({ dbgs() << "Issuing init-symbol lookup:\n"; - for (auto &KV : InitSyms) - dbgs() << " " << KV.first->getName() << ": " << KV.second << "\n"; + for (auto &[JD, Syms] : InitSyms) + dbgs() << " " << JD->getName() << ": " << Syms << "\n"; }); for (auto &KV : InitSyms) { auto *JD = KV.first; - auto Names = std::move(KV.second); + auto &Names = KV.second; ES.lookup( LookupKind::Static, JITDylibSearchOrder({{JD, JITDylibLookupFlags::MatchAllSymbols}}), std::move(Names), SymbolState::Ready, - [&, JD](Expected Result) { + [&](Expected Result) { { std::lock_guard Lock(LookupMutex); --Count; @@ -1557,15 +1553,13 @@ void Platform::lookupInitSymbolsAsync( LLVM_DEBUG({ dbgs() << "Issuing init-symbol lookup:\n"; - for (auto &KV : InitSyms) - dbgs() << " " << KV.first->getName() << ": " << KV.second << "\n"; + for (auto &[JD, Syms] : InitSyms) + dbgs() << " " << JD->getName() << ": " << Syms << "\n"; }); auto TOC = std::make_shared(std::move(OnComplete)); - for (auto &KV : InitSyms) { - auto *JD = KV.first; - auto Names = std::move(KV.second); + for (auto &[JD, Names] : InitSyms) { ES.lookup( LookupKind::Static, JITDylibSearchOrder({{JD, JITDylibLookupFlags::MatchAllSymbols}}), @@ -1732,11 +1726,10 @@ JITDylib::getDFSLinkOrder(ArrayRef JDs) { Result.push_back(std::move(WorkStack.back())); WorkStack.pop_back(); - for (auto &KV : llvm::reverse(Result.back()->LinkOrder)) { - auto &JD = *KV.first; - if (!Visited.insert(&JD).second) + for (auto &[JD, Flags] : llvm::reverse(Result.back()->LinkOrder)) { + if (!Visited.insert(JD).second) continue; - WorkStack.push_back(&JD); + WorkStack.push_back(JD); } } } @@ -1906,21 +1899,21 @@ Error ExecutionSession::registerJITDispatchHandlers( // Associate tag addresses with implementations. std::lock_guard Lock(JITDispatchHandlersMutex); - for (auto &KV : *TagAddrs) { - auto TagAddr = KV.second.getAddress(); + for (auto &[Name, Def] : *TagAddrs) { + auto TagAddr = Def.getAddress(); if (JITDispatchHandlers.count(TagAddr)) return make_error("Tag " + formatv("{0:x16}", TagAddr) + - " (for " + *KV.first + + " (for " + *Name + ") already registered", inconvertibleErrorCode()); - auto I = WFs.find(KV.first); + auto I = WFs.find(Name); assert(I != WFs.end() && I->second && "JITDispatchHandler implementation missing"); - JITDispatchHandlers[KV.second.getAddress()] = + JITDispatchHandlers[Def.getAddress()] = std::make_shared(std::move(I->second)); LLVM_DEBUG({ - dbgs() << "Associated function tag \"" << *KV.first << "\" (" - << formatv("{0:x}", KV.second.getAddress()) << ") with handler\n"; + dbgs() << "Associated function tag \"" << *Name << "\" (" + << formatv("{0:x}", Def.getAddress()) << ") with handler\n"; }); } return Error::success(); @@ -2353,11 +2346,11 @@ void ExecutionSession::OL_applyQueryPhase1( // Get the next JITDylib and lookup flags. auto &KV = IPLS->SearchOrder[IPLS->CurSearchOrderIndex]; - auto &JD = *KV.first; + auto *JD = KV.first; auto JDLookupFlags = KV.second; LLVM_DEBUG({ - dbgs() << "Visiting \"" << JD.getName() << "\" (" << JDLookupFlags + dbgs() << "Visiting \"" << JD->getName() << "\" (" << JDLookupFlags << ") with lookup set " << IPLS->LookupSet << ":\n"; }); @@ -2371,14 +2364,14 @@ void ExecutionSession::OL_applyQueryPhase1( IPLS->DefGeneratorCandidates.append(std::move(Tmp)); LLVM_DEBUG({ - dbgs() << " First time visiting " << JD.getName() + dbgs() << " First time visiting " << JD->getName() << ", resetting candidate sets and building generator stack\n"; }); // Build the definition generator stack for this JITDylib. runSessionLocked([&] { - IPLS->CurDefGeneratorStack.reserve(JD.DefGenerators.size()); - for (auto &DG : reverse(JD.DefGenerators)) + IPLS->CurDefGeneratorStack.reserve(JD->DefGenerators.size()); + for (auto &DG : reverse(JD->DefGenerators)) IPLS->CurDefGeneratorStack.push_back(DG); }); @@ -2393,9 +2386,9 @@ void ExecutionSession::OL_applyQueryPhase1( // generation. LLVM_DEBUG(dbgs() << " Updating candidate set...\n"); Err = IL_updateCandidatesFor( - JD, JDLookupFlags, IPLS->DefGeneratorCandidates, - JD.DefGenerators.empty() ? nullptr - : &IPLS->DefGeneratorNonCandidates); + *JD, JDLookupFlags, IPLS->DefGeneratorCandidates, + JD->DefGenerators.empty() ? nullptr + : &IPLS->DefGeneratorNonCandidates); LLVM_DEBUG({ dbgs() << " Remaining candidates = " << IPLS->DefGeneratorCandidates << "\n"; @@ -2462,7 +2455,7 @@ void ExecutionSession::OL_applyQueryPhase1( { LLVM_DEBUG(dbgs() << " Attempting to generate " << LookupSet << "\n"); LookupState LS(std::move(IPLS)); - Err = DG->tryToGenerate(LS, K, JD, JDLookupFlags, LookupSet); + Err = DG->tryToGenerate(LS, K, *JD, JDLookupFlags, LookupSet); IPLS = std::move(LS.IPLS); } @@ -2492,9 +2485,9 @@ void ExecutionSession::OL_applyQueryPhase1( runSessionLocked([&] { LLVM_DEBUG(dbgs() << " Updating candidate set post-generation\n"); Err = IL_updateCandidatesFor( - JD, JDLookupFlags, IPLS->DefGeneratorCandidates, - JD.DefGenerators.empty() ? nullptr - : &IPLS->DefGeneratorNonCandidates); + *JD, JDLookupFlags, IPLS->DefGeneratorCandidates, + JD->DefGenerators.empty() ? nullptr + : &IPLS->DefGeneratorNonCandidates); }); // If updating candidates failed then fail the query. @@ -2649,13 +2642,13 @@ void ExecutionSession::OL_completeLookup( // Move all symbols associated with this MaterializationUnit into // materializing state. - for (auto &KV : UMI->MU->getSymbols()) { - auto SymK = JD.Symbols.find(KV.first); + for (auto &[MUSymName, MUSymFlags] : UMI->MU->getSymbols()) { + auto SymK = JD.Symbols.find(MUSymName); assert(SymK != JD.Symbols.end() && "No entry for symbol covered by MaterializationUnit"); SymK->second.setMaterializerAttached(false); SymK->second.setState(SymbolState::Materializing); - JD.UnmaterializedInfos.erase(KV.first); + JD.UnmaterializedInfos.erase(MUSymName); } // Add MU to the list of MaterializationUnits to be materialized. @@ -2686,20 +2679,19 @@ void ExecutionSession::OL_completeLookup( Q->detach(); // Replace the MUs. - for (auto &KV : CollectedUMIs) { - auto &JD = *KV.first; - for (auto &UMI : KV.second) - for (auto &KV2 : UMI->MU->getSymbols()) { - assert(!JD.UnmaterializedInfos.count(KV2.first) && + for (auto &[JD, UMIs] : CollectedUMIs) { + for (auto &UMI : UMIs) + for (auto &[Name, Flags] : UMI->MU->getSymbols()) { + assert(!JD->UnmaterializedInfos.count(Name) && "Unexpected materializer in map"); - auto SymI = JD.Symbols.find(KV2.first); - assert(SymI != JD.Symbols.end() && "Missing symbol entry"); + auto SymI = JD->Symbols.find(Name); + assert(SymI != JD->Symbols.end() && "Missing symbol entry"); assert(SymI->second.getState() == SymbolState::Materializing && "Can not replace symbol that is not materializing"); assert(!SymI->second.hasMaterializerAttached() && "MaterializerAttached flag should not be set"); SymI->second.setMaterializerAttached(true); - JD.UnmaterializedInfos[KV2.first] = UMI; + JD->UnmaterializedInfos[Name] = UMI; } } @@ -2736,13 +2728,12 @@ void ExecutionSession::OL_completeLookup( std::lock_guard Lock(OutstandingMUsMutex); LLVM_DEBUG(dbgs() << "Adding MUs to dispatch:\n"); - for (auto &KV : CollectedUMIs) { + for (auto &[JD, UMIs] : CollectedUMIs) { LLVM_DEBUG({ - auto &JD = *KV.first; - dbgs() << " For " << JD.getName() << ": Adding " << KV.second.size() + dbgs() << " For " << JD->getName() << ": Adding " << UMIs.size() << " MUs.\n"; }); - for (auto &UMI : KV.second) { + for (auto &UMI : UMIs) { auto MR = createMaterializationResponsibility( *UMI->RT, std::move(UMI->MU->SymbolFlags), std::move(UMI->MU->InitSymbol)); @@ -2877,13 +2868,13 @@ Error ExecutionSession::OL_notifyResolved(MaterializationResponsibility &MR, dbgs() << "In " << MR.JD.getName() << " resolving " << Symbols << "\n"; }); #ifndef NDEBUG - for (auto &KV : Symbols) { - auto I = MR.SymbolFlags.find(KV.first); + for (auto &[Name, Def] : Symbols) { + auto I = MR.SymbolFlags.find(Name); assert(I != MR.SymbolFlags.end() && "Resolving symbol outside this responsibility set"); assert(!I->second.hasMaterializationSideEffectsOnly() && "Can't resolve materialization-side-effects-only symbol"); - assert((KV.second.getFlags() & ~JITSymbolFlags::Common) == + assert((Def.getFlags() & ~JITSymbolFlags::Common) == (I->second & ~JITSymbolFlags::Common) && "Resolving symbol with incorrect flags"); } @@ -3685,10 +3676,10 @@ void ExecutionSession::OL_notifyFailed(MaterializationResponsibility &MR) { Error ExecutionSession::OL_replace(MaterializationResponsibility &MR, std::unique_ptr MU) { - for (auto &KV : MU->getSymbols()) { - assert(MR.SymbolFlags.count(KV.first) && + for (auto &[Name, Flags] : MU->getSymbols()) { + assert(MR.SymbolFlags.count(Name) && "Replacing definition outside this responsibility set"); - MR.SymbolFlags.erase(KV.first); + MR.SymbolFlags.erase(Name); } if (MU->getInitializerSymbol() == MR.InitSymbol) -- GitLab From 91189afef5fb887699da88e0ed46bdf3421d4bce Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 8 Apr 2024 14:30:23 +0900 Subject: [PATCH 111/695] Revert "[indvars] Missing variables at Og: (#69920)" This reverts commit 739fa1c84b92b8af7dceedf2e5ad808a64e85a57. This introduces a layering violation by using IR in Support headers. --- llvm/include/llvm/Support/GenericLoopInfo.h | 24 ---- .../include/llvm/Transforms/Utils/LoopUtils.h | 6 - llvm/lib/Transforms/Utils/LoopUtils.cpp | 65 --------- .../Transforms/IndVarSimplify/pr51735-1.ll | 129 ----------------- .../Transforms/IndVarSimplify/pr51735-2.ll | 128 ----------------- .../Transforms/IndVarSimplify/pr51735-3.ll | 131 ------------------ .../test/Transforms/IndVarSimplify/pr51735.ll | 104 -------------- 7 files changed, 587 deletions(-) delete mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735-1.ll delete mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735-2.ll delete mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735-3.ll delete mode 100644 llvm/test/Transforms/IndVarSimplify/pr51735.ll diff --git a/llvm/include/llvm/Support/GenericLoopInfo.h b/llvm/include/llvm/Support/GenericLoopInfo.h index f4b50367bf93..d560ca648132 100644 --- a/llvm/include/llvm/Support/GenericLoopInfo.h +++ b/llvm/include/llvm/Support/GenericLoopInfo.h @@ -44,8 +44,6 @@ #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetOperations.h" -#include "llvm/IR/IntrinsicInst.h" -#include "llvm/IR/ValueHandle.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/GenericDomTree.h" @@ -77,13 +75,6 @@ template class LoopBase { const LoopBase & operator=(const LoopBase &) = delete; - // Induction variable exit value and its debug users, preserved by the - // 'indvars' pass, when it detects that the loop can be deleted and the - // there are no PHIs to be rewritten. - // For now, we only preserve single induction variables. - Value *IndVarFinalValue = nullptr; - SmallVector IndVarDebugUsers; - public: /// Return the nesting level of this loop. An outer-most loop has depth 1, /// for consistency with loop depth values used for basic blocks, where depth @@ -260,21 +251,6 @@ public: [&](BlockT *Pred) { return contains(Pred); }); } - /// Preserve the induction variable exit value and its debug users by the - /// 'indvars' pass if the loop can deleted. Those debug users will be used - /// by the 'loop-delete' pass. - void preserveDebugInductionVariableInfo( - Value *FinalValue, SmallVector DbgUsers) { - IndVarFinalValue = FinalValue; - for (DbgVariableIntrinsic *DebugUser : DbgUsers) - IndVarDebugUsers.push_back(DebugUser); - } - - Value *getDebugInductionVariableFinalValue() { return IndVarFinalValue; } - SmallVector &getDebugInductionVariableDebugUsers() { - return IndVarDebugUsers; - } - //===--------------------------------------------------------------------===// // APIs for simple analysis of the loop. // diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h index 15b230ba92dd..345e09dce0b2 100644 --- a/llvm/include/llvm/Transforms/Utils/LoopUtils.h +++ b/llvm/include/llvm/Transforms/Utils/LoopUtils.h @@ -468,12 +468,6 @@ int rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, ReplaceExitVal ReplaceExitValue, SmallVector &DeadInsts); -/// Assign exit values to variables that use this loop variable during the loop. -void addDebugValuesToIncomingValue(BasicBlock *Successor, Value *IndVar, - PHINode *PN); -void addDebugValuesToLoopVariable(BasicBlock *Successor, Value *ExitValue, - PHINode *PN); - /// Set weights for \p UnrolledLoop and \p RemainderLoop based on weights for /// \p OrigLoop and the following distribution of \p OrigLoop iteration among \p /// UnrolledLoop and \p RemainderLoop. \p UnrolledLoop receives weights that diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp index 4187bd38cf29..9d816c522053 100644 --- a/llvm/lib/Transforms/Utils/LoopUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp @@ -31,7 +31,6 @@ #include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/IR/DIBuilder.h" -#include "llvm/IR/DebugInfo.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" @@ -609,17 +608,6 @@ void llvm::deleteDeadLoop(Loop *L, DominatorTree *DT, ScalarEvolution *SE, llvm::SmallVector DeadDbgVariableRecords; if (ExitBlock) { - if (ExitBlock->phis().empty()) { - // As the loop is deleted, replace the debug users with the preserved - // induction variable final value recorded by the 'indvar' pass. - Value *FinalValue = L->getDebugInductionVariableFinalValue(); - SmallVector &DbgUsers = L->getDebugInductionVariableDebugUsers(); - for (WeakVH &DebugUser : DbgUsers) - if (DebugUser) - cast(DebugUser)->replaceVariableLocationOp( - 0u, FinalValue); - } - // Given LCSSA form is satisfied, we should not have users of instructions // within the dead loop outside of the loop. However, LCSSA doesn't take // unreachable uses into account. We handle them here. @@ -1413,36 +1401,6 @@ static bool checkIsIndPhi(PHINode *Phi, Loop *L, ScalarEvolution *SE, return InductionDescriptor::isInductionPHI(Phi, L, SE, ID); } -void llvm::addDebugValuesToIncomingValue(BasicBlock *Successor, Value *IndVar, - PHINode *PN) { - SmallVector DbgUsers; - findDbgUsers(DbgUsers, IndVar); - for (auto *DebugUser : DbgUsers) { - // Skip debug-users with variadic variable locations; they will not, - // get updated, which is fine as that is the existing behaviour. - if (DebugUser->hasArgList()) - continue; - auto *Cloned = cast(DebugUser->clone()); - Cloned->replaceVariableLocationOp(0u, PN); - Cloned->insertBefore(*Successor, Successor->getFirstNonPHIIt()); - } -} - -void llvm::addDebugValuesToLoopVariable(BasicBlock *Successor, Value *ExitValue, - PHINode *PN) { - SmallVector DbgUsers; - findDbgUsers(DbgUsers, PN); - for (auto *DebugUser : DbgUsers) { - // Skip debug-users with variadic variable locations; they will not, - // get updated, which is fine as that is the existing behaviour. - if (DebugUser->hasArgList()) - continue; - auto *Cloned = cast(DebugUser->clone()); - Cloned->replaceVariableLocationOp(0u, ExitValue); - Cloned->insertBefore(*Successor, Successor->getFirstNonPHIIt()); - } -} - int llvm::rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, ScalarEvolution *SE, const TargetTransformInfo *TTI, @@ -1584,10 +1542,6 @@ int llvm::rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, (isa(Inst) || isa(Inst)) ? &*Inst->getParent()->getFirstInsertionPt() : Inst; RewritePhiSet.emplace_back(PN, i, ExitValue, InsertPt, HighCost); - - // Add debug values for the candidate PHINode incoming value. - if (BasicBlock *Successor = ExitBB->getSingleSuccessor()) - addDebugValuesToIncomingValue(Successor, PN->getIncomingValue(i), PN); } } } @@ -1646,30 +1600,11 @@ int llvm::rewriteLoopExitValues(Loop *L, LoopInfo *LI, TargetLibraryInfo *TLI, // Replace PN with ExitVal if that is legal and does not break LCSSA. if (PN->getNumIncomingValues() == 1 && LI->replacementPreservesLCSSAForm(PN, ExitVal)) { - addDebugValuesToLoopVariable(PN->getParent(), ExitVal, PN); PN->replaceAllUsesWith(ExitVal); PN->eraseFromParent(); } } - // If the loop can be deleted and there are no PHIs to be rewritten (there - // are no loop live-out values), record debug variables corresponding to the - // induction variable with their constant exit-values. Those values will be - // inserted by the 'deletion loop' logic. - if (LoopCanBeDel && RewritePhiSet.empty()) { - if (auto *IndVar = L->getInductionVariable(*SE)) { - const SCEV *PNSCEV = SE->getSCEVAtScope(IndVar, L->getParentLoop()); - if (auto *Const = dyn_cast(PNSCEV)) { - Value *FinalIVValue = Const->getValue(); - if (L->getUniqueExitBlock()) { - SmallVector DbgUsers; - findDbgUsers(DbgUsers, IndVar); - L->preserveDebugInductionVariableInfo(FinalIVValue, DbgUsers); - } - } - } - } - // The insertion point instruction may have been deleted; clear it out // so that the rewriter doesn't trip over it later. Rewriter.clearInsertPoint(); diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735-1.ll b/llvm/test/Transforms/IndVarSimplify/pr51735-1.ll deleted file mode 100644 index 356217985fed..000000000000 --- a/llvm/test/Transforms/IndVarSimplify/pr51735-1.ll +++ /dev/null @@ -1,129 +0,0 @@ -; RUN: opt -passes="loop(indvars)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --check-prefix=CHECK %s -; RUN: opt -passes="loop(indvars,loop-deletion)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --check-prefix=CHECK %s - -; Make sure that when we delete the loop, that the variable Index has -; the 777 value. - -; As this test case does fire the 'indvars' transformation, the debug values -; are added to the 'for.end' exit block. No debug values are preserved by the -; pass to be used by the 'loop-deletion' pass. - -; CHECK: for.cond: -; CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_INDEX_0:.+]], metadata ![[DBG:[0-9]+]], {{.*}} - -; CHECK: for.extra: -; CHECK: %[[SSA_CALL_0:.+]] = call noundef i32 @"?nop@@YAHH@Z"(i32 noundef %[[SSA_INDEX_0]]), {{.*}} -; CHECK: br i1 %[[SSA_CMP_0:.+]], label %for.cond, label %if.else, {{.*}} - -; CHECK: if.then: -; CHECK: call void @llvm.dbg.value(metadata i32 777, metadata ![[DBG]], {{.*}} -; CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_1:.+]], metadata ![[VAR:[0-9]+]], {{.*}} -; CHECK: br label %for.end, {{.*}} - -; CHECK: if.else: -; CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_2:.+]], metadata ![[VAR:[0-9]+]], {{.*}} -; CHECK: br label %for.end, {{.*}} - -; CHECK: for.end: -; CHECK: call void @llvm.dbg.value(metadata i32 777, metadata ![[DBG]], {{.*}} - -; CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Index"{{.*}}) -; CHECK-DAG: ![[VAR]] = !DILocalVariable(name: "Var"{{.*}}) - -define dso_local noundef i32 @"?nop@@YAHH@Z"(i32 noundef %Param) !dbg !11 { -entry: - %Param.addr = alloca i32, align 4 - store i32 %Param, ptr %Param.addr, align 4 - call void @llvm.dbg.declare(metadata ptr %Param.addr, metadata !32, metadata !DIExpression()), !dbg !35 - ret i32 0, !dbg !36 -} - -define dso_local void @_Z3barv() local_unnamed_addr #1 !dbg !12 { -entry: - call void @llvm.dbg.value(metadata i32 777, metadata !16, metadata !DIExpression()), !dbg !17 - call void @llvm.dbg.value(metadata i32 27, metadata !18, metadata !DIExpression()), !dbg !17 - call void @llvm.dbg.value(metadata i32 1, metadata !19, metadata !DIExpression()), !dbg !17 - call void @llvm.dbg.value(metadata i32 1, metadata !30, metadata !DIExpression()), !dbg !17 - br label %for.cond, !dbg !20 - -for.cond: ; preds = %for.cond, %entry - %Index.0 = phi i32 [ 27, %entry ], [ %inc, %for.extra ], !dbg !17 - call void @llvm.dbg.value(metadata i32 %Index.0, metadata !18, metadata !DIExpression()), !dbg !17 - %cmp = icmp ult i32 %Index.0, 777, !dbg !21 - %inc = add nuw nsw i32 %Index.0, 1, !dbg !24 - call void @llvm.dbg.value(metadata i32 %inc, metadata !18, metadata !DIExpression()), !dbg !17 - br i1 %cmp, label %for.extra, label %if.then, !dbg !25, !llvm.loop !26 - -for.extra: - %call.0 = call noundef i32 @"?nop@@YAHH@Z"(i32 noundef %Index.0), !dbg !21 - %cmp.0 = icmp ult i32 %Index.0, %call.0, !dbg !21 - br i1 %cmp.0, label %for.cond, label %if.else, !dbg !25, !llvm.loop !26 - -if.then: ; preds = %for.cond - %Var.1 = add nsw i32 %Index.0, 1, !dbg !20 - call void @llvm.dbg.value(metadata i32 %Var.1, metadata !19, metadata !DIExpression()), !dbg !20 - br label %for.end, !dbg !20 - -if.else: - %Var.2 = add nsw i32 %Index.0, 2, !dbg !20 - call void @llvm.dbg.value(metadata i32 %Var.2, metadata !19, metadata !DIExpression()), !dbg !20 - br label %for.end, !dbg !20 - -for.end: ; preds = %if.else, %if.then - %Zeta.0 = phi i32 [ %Var.1, %if.then ], [ %Var.2, %if.else ], !dbg !20 - call void @llvm.dbg.value(metadata i32 %Zeta.0, metadata !30, metadata !DIExpression()), !dbg !20 - %Var.3 = add nsw i32 %Index.0, 1, !dbg !20 - call void @llvm.dbg.value(metadata i32 %Var.3, metadata !19, metadata !DIExpression()), !dbg !20 - %call = call noundef i32 @"?nop@@YAHH@Z"(i32 noundef %Index.0), !dbg !37 - ret void, !dbg !29 -} - -declare void @llvm.dbg.value(metadata, metadata, metadata) -declare void @llvm.dbg.declare(metadata, metadata, metadata) - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} -!llvm.ident = !{!9} - -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "test.cpp", directory: "") -!2 = !{i32 7, !"Dwarf Version", i32 5} -!3 = !{i32 2, !"Debug Info Version", i32 3} -!4 = !{i32 1, !"wchar_size", i32 4} -!5 = !{i32 8, !"PIC Level", i32 2} -!6 = !{i32 7, !"PIE Level", i32 2} -!7 = !{i32 7, !"uwtable", i32 2} -!8 = !{i32 7, !"frame-pointer", i32 2} -!9 = !{!"clang version 18.0.0"} -!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!11 = distinct !DISubprogram(name: "nop", linkageName: "?nop@@YAHH@Z", scope: !1, file: !1, line: 1, type: !33, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !31) -!12 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !13, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !15) -!13 = !DISubroutineType(types: !14) -!14 = !{null} -!15 = !{} -!16 = !DILocalVariable(name: "End", scope: !12, file: !1, line: 6, type: !10) -!17 = !DILocation(line: 0, scope: !12) -!18 = !DILocalVariable(name: "Index", scope: !12, file: !1, line: 7, type: !10) -!19 = !DILocalVariable(name: "Var", scope: !12, file: !1, line: 8, type: !10) -!20 = !DILocation(line: 9, column: 3, scope: !12) -!21 = !DILocation(line: 9, column: 16, scope: !22) -!22 = distinct !DILexicalBlock(scope: !23, file: !1, line: 9, column: 3) -!23 = distinct !DILexicalBlock(scope: !12, file: !1, line: 9, column: 3) -!24 = !DILocation(line: 9, column: 23, scope: !22) -!25 = !DILocation(line: 9, column: 3, scope: !23) -!26 = distinct !{!26, !25, !27, !28} -!27 = !DILocation(line: 10, column: 5, scope: !23) -!28 = !{!"llvm.loop.mustprogress"} -!29 = !DILocation(line: 12, column: 1, scope: !12) -!30 = !DILocalVariable(name: "Zeta", scope: !12, file: !1, line: 8, type: !10) -!31 = !{!32} -!32 = !DILocalVariable(name: "Param", arg: 1, scope: !11, file: !1, line: 1, type: !10) -!33 = !DISubroutineType(types: !34) -!34 = !{!10, !10} -!35 = !DILocation(line: 1, scope: !11) -!36 = !DILocation(line: 2, scope: !11) -!37 = !DILocation(line: 20, scope: !12) diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735-2.ll b/llvm/test/Transforms/IndVarSimplify/pr51735-2.ll deleted file mode 100644 index 58cc9932e04c..000000000000 --- a/llvm/test/Transforms/IndVarSimplify/pr51735-2.ll +++ /dev/null @@ -1,128 +0,0 @@ -; RUN: opt -passes="loop(indvars)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ -; RUN: --check-prefix=ALL-CHECK --check-prefix=PRE-CHECK %s -; RUN: opt -passes="loop(indvars,loop-deletion)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ -; RUN: --check-prefix=ALL-CHECK --check-prefix=POST-CHECK %s - -; Check what happens to a modified but otherwise unused variable in a loop -; that gets deleted. The assignment in the loop is 'forgotten' by LLVM and -; doesn't appear in the debugging information. This behaviour is suboptimal, -; but we want to know if it changes - -; For all cases, LLDB shows -; Var = - -; 1 __attribute__((optnone)) int nop() { -; 2 return 0; -; 3 } -; 4 -; 5 void bar() { -; 6 int End = 777; -; 7 int Index = 27; -; 8 char Var = 1; -; 9 for (; Index < End; ++Index) { -; 10 if (Index == 666) { -; 11 ++Var; -; 12 } -; 13 } -; 14 nop(); -; 15 } - -; ALL-CHECK: entry: -; ALL-CHECK: call void @llvm.dbg.value(metadata i32 1, metadata ![[DBG:[0-9]+]], {{.*}} - -; Only the 'indvars' pass is executed. -; PRE-CHECK: for.cond: -; PRE-CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_0:.+]], metadata ![[DBG]], {{.*}} -; PRE-CHECK: call void @llvm.dbg.value(metadata !DIArgList{{.*}} - -; PRE-CHECK: for.body: -; PRE-CHECK: {{.*}} = icmp eq i32 %[[SSA_INDEX_0:.+]], 666 -; PRE-CHECK: {{.*}} = add nsw i32 %[[SSA_VAR_0]], 1 -; PRE-CHECK: {{.*}} = select i1 {{.*}}, i32 {{.*}}, i32 %[[SSA_VAR_0]] -; PRE-CHECK: call void @llvm.dbg.value(metadata i32 {{.*}}, metadata ![[DBG]], {{.*}} -; PRE-CHECK: br label %for.cond - -; PRE-CHECK: for.end: -; PRE-CHECK: ret void -; PRE-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) - -; The 'indvars' and 'loop-deletion' passes are executed. -; POST-CHECK: for.end: -; POST-CHECK: call void @llvm.dbg.value(metadata i32 undef, metadata ![[DBG:[0-9]+]], {{.*}} -; POST-CHECK: ret void -; POST-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) - -define dso_local void @_Z3barv() local_unnamed_addr !dbg !18 { -entry: - call void @llvm.dbg.value(metadata i32 1, metadata !24, metadata !DIExpression()), !dbg !22 - br label %for.cond, !dbg !25 - -for.cond: ; preds = %for.cond, %entry - %Index.0 = phi i32 [ 27, %entry ], [ %inc2, %for.body ], !dbg !22 - %Var.0 = phi i32 [ 1, %entry ], [ %spec.select, %for.body ], !dbg !22 - call void @llvm.dbg.value(metadata i32 %Var.0, metadata !24, metadata !DIExpression()), !dbg !22 - %cmp = icmp ult i32 %Index.0, 777, !dbg !26 - call void @llvm.dbg.value(metadata !DIArgList(i32 poison, i32 %Index.0), metadata !24, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 666, DW_OP_eq, DW_OP_LLVM_convert, 1, DW_ATE_unsigned, DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_plus, DW_OP_stack_value)), !dbg !22 - %inc2 = add nuw nsw i32 %Index.0, 1, !dbg !29 - br i1 %cmp, label %for.body, label %for.end, !dbg !30, !llvm.loop !31 - -for.body: ; preds = %for.cond - %cmp1 = icmp eq i32 %Index.0, 666, !dbg !30 - %inc = add nsw i32 %Var.0, 1 - %spec.select = select i1 %cmp1, i32 %inc, i32 %Var.0, !dbg !32 - call void @llvm.dbg.value(metadata i32 %spec.select, metadata !24, metadata !DIExpression()), !dbg !22 - br label %for.cond, !dbg !34, !llvm.loop !35 - -for.end: ; preds = %for.cond - ret void, !dbg !35 -} - -declare void @llvm.dbg.value(metadata, metadata, metadata) - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} -!llvm.ident = !{!9} - -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "test-b.cpp", directory: "") -!2 = !{i32 7, !"Dwarf Version", i32 5} -!3 = !{i32 2, !"Debug Info Version", i32 3} -!4 = !{i32 1, !"wchar_size", i32 4} -!5 = !{i32 8, !"PIC Level", i32 2} -!6 = !{i32 7, !"PIE Level", i32 2} -!7 = !{i32 7, !"uwtable", i32 2} -!8 = !{i32 7, !"frame-pointer", i32 2} -!9 = !{!"clang version 19.0.0"} -!10 = distinct !DISubprogram(name: "nop", linkageName: "_Z3nopi", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) -!11 = !DISubroutineType(types: !12) -!12 = !{!13, !13} -!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!14 = !{} -!15 = !DILocalVariable(name: "Param", arg: 1, scope: !10, file: !1, line: 1, type: !13) -!16 = !DILocation(line: 1, column: 38, scope: !10) -!17 = !DILocation(line: 2, column: 3, scope: !10) -!18 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !19, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) -!19 = !DISubroutineType(types: !20) -!20 = !{null} -!22 = !DILocation(line: 0, scope: !18) -!24 = !DILocalVariable(name: "Var", scope: !18, file: !1, line: 8, type: !13) -!25 = !DILocation(line: 9, column: 3, scope: !18) -!26 = !DILocation(line: 9, column: 16, scope: !27) -!27 = distinct !DILexicalBlock(scope: !28, file: !1, line: 9, column: 3) -!28 = distinct !DILexicalBlock(scope: !18, file: !1, line: 9, column: 3) -!29 = !DILocation(line: 9, column: 23, scope: !27) -!30 = !DILocation(line: 9, column: 3, scope: !28) -!31 = distinct !{!31, !30, !32, !33} -!32 = !DILocation(line: 11, column: 9, scope: !28) -!33 = !{!"llvm.loop.mustprogress"} -!34 = !DILocation(line: 12, column: 3, scope: !18) -!35 = !DILocation(line: 13, column: 1, scope: !18) -!36 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 15, type: !37, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) -!37 = !DISubroutineType(types: !38) -!38 = !{!13} -!39 = !DILocation(line: 16, column: 3, scope: !36) -!40 = !DILocation(line: 17, column: 1, scope: !36) diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735-3.ll b/llvm/test/Transforms/IndVarSimplify/pr51735-3.ll deleted file mode 100644 index ac9964743e0f..000000000000 --- a/llvm/test/Transforms/IndVarSimplify/pr51735-3.ll +++ /dev/null @@ -1,131 +0,0 @@ -; RUN: opt -passes="loop(indvars)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ -; RUN: --check-prefix=ALL-CHECK --check-prefix=PRE-CHECK %s -; RUN: opt -passes="loop(indvars,loop-deletion)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --implicit-check-not="call void @llvm.dbg" \ -; RUN: --check-prefix=ALL-CHECK --check-prefix=POST-CHECK %s - -; Check what happens to a modified but otherwise unused variable in a loop -; that gets deleted. The assignment in the loop is 'forgotten' by LLVM and -; doesn't appear in the debugging information. This behaviour is suboptimal, -; but we want to know if it changes - -; For all cases, LLDB shows -; Var = - -; 1 __attribute__((optnone)) int nop() { -; 2 return 0; -; 3 } -; 4 -; 5 void bar() { -; 6 int End = 777; -; 7 int Index = 27; -; 8 char Var = 1; -; 9 for (; Index < End; ++Index) { -; 10 if (Index == 666) { -; 11 Var = 555; -; 12 } -; 13 } -; 14 nop(); -; 15 } - -; ALL-CHECK: entry: -; ALL-CHECK: call void @llvm.dbg.value(metadata i32 1, metadata ![[DBG:[0-9]+]], {{.*}} - -; Only the 'indvars' pass is executed. -; PRE-CHECK: if.then: -; PRE-CHECK: call void @llvm.dbg.value(metadata i32 555, metadata ![[DBG]], {{.*}} - -; PRE-CHECK: for.inc: -; PRE-CHECK: %[[SSA_VAR_0:.+]] = phi i32 [ 1, %for.body ], [ 555, %if.then ] -; PRE-CHECK: call void @llvm.dbg.value(metadata i32 %[[SSA_VAR_0]], metadata ![[DBG]], {{.*}} -; PRE-CHECK: {{.*}} = add nuw nsw i32 %[[SSA_INDEX_0:.+]], 1 -; PRE-CHECK: br label %for.cond - -; PRE-CHECK: for.end: -; PRE-CHECK: ret void -; PRE-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) - -; The 'indvars' and 'loop-deletion' passes are executed. -; POST-CHECK: for.end: -; POST-CHECK: call void @llvm.dbg.value(metadata i32 555, metadata ![[DBG]], {{.*}} -; POST-CHECK: ret void -; POST-CHECK-DAG: ![[DBG]] = !DILocalVariable(name: "Var"{{.*}}) - -define dso_local void @_Z3barv() local_unnamed_addr !dbg !18 { -entry: - call void @llvm.dbg.value(metadata i32 1, metadata !24, metadata !DIExpression()), !dbg !22 - br label %for.cond, !dbg !25 - -for.cond: ; preds = %for.inc, %entry - %Index.0 = phi i32 [ 27, %entry ], [ %inc, %for.inc ], !dbg !22 - %cmp = icmp ult i32 %Index.0, 777, !dbg !26 - br i1 %cmp, label %for.body, label %for.end, !dbg !30, !llvm.loop !29 - -for.body: ; preds = %for.cond - %cmp1 = icmp eq i32 %Index.0, 666, !dbg !30 - br i1 %cmp1, label %if.then, label %for.inc, !dbg !32 - -if.then: ; preds = %for.body - call void @llvm.dbg.value(metadata i32 555, metadata !24, metadata !DIExpression()), !dbg !22 - br label %for.inc, !dbg !34, !llvm.loop !32 - -for.inc: ; preds = %for.body, %if.then - %Var.0 = phi i32 [ 1, %for.body ], [ 555, %if.then ], !dbg !22 - call void @llvm.dbg.value(metadata i32 %Var.0, metadata !24, metadata !DIExpression()), !dbg !22 - %inc = add nuw nsw i32 %Index.0, 1, !dbg !29 - br label %for.cond, !dbg !34, !llvm.loop !35 - -for.end: ; preds = %for.cond - ret void, !dbg !35 -} - -declare void @llvm.dbg.value(metadata, metadata, metadata) - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} -!llvm.ident = !{!9} - -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "test-c.cpp", directory: "") -!2 = !{i32 7, !"Dwarf Version", i32 5} -!3 = !{i32 2, !"Debug Info Version", i32 3} -!4 = !{i32 1, !"wchar_size", i32 4} -!5 = !{i32 8, !"PIC Level", i32 2} -!6 = !{i32 7, !"PIE Level", i32 2} -!7 = !{i32 7, !"uwtable", i32 2} -!8 = !{i32 7, !"frame-pointer", i32 2} -!9 = !{!"clang version 19.0.0"} -!10 = distinct !DISubprogram(name: "nop", linkageName: "_Z3nopi", scope: !1, file: !1, line: 1, type: !11, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) -!11 = !DISubroutineType(types: !12) -!12 = !{!13, !13} -!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!14 = !{} -!15 = !DILocalVariable(name: "Param", arg: 1, scope: !10, file: !1, line: 1, type: !13) -!16 = !DILocation(line: 1, column: 38, scope: !10) -!17 = !DILocation(line: 2, column: 3, scope: !10) -!18 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !19, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !14) -!19 = !DISubroutineType(types: !20) -!20 = !{null} -!21 = !DILocalVariable(name: "End", scope: !18, file: !1, line: 6, type: !13) -!22 = !DILocation(line: 0, scope: !18) -!23 = !DILocalVariable(name: "Index", scope: !18, file: !1, line: 7, type: !13) -!24 = !DILocalVariable(name: "Var", scope: !18, file: !1, line: 8, type: !13) -!25 = !DILocation(line: 9, column: 3, scope: !18) -!26 = !DILocation(line: 9, column: 16, scope: !27) -!27 = distinct !DILexicalBlock(scope: !28, file: !1, line: 9, column: 3) -!28 = distinct !DILexicalBlock(scope: !18, file: !1, line: 9, column: 3) -!29 = !DILocation(line: 9, column: 23, scope: !27) -!30 = !DILocation(line: 9, column: 3, scope: !28) -!31 = distinct !{!31, !30, !32, !33} -!32 = !DILocation(line: 11, column: 13, scope: !28) -!33 = !{!"llvm.loop.mustprogress"} -!34 = !DILocation(line: 12, column: 3, scope: !18) -!35 = !DILocation(line: 13, column: 1, scope: !18) -!36 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 15, type: !37, scopeLine: 15, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0) -!37 = !DISubroutineType(types: !38) -!38 = !{!13} -!39 = !DILocation(line: 16, column: 3, scope: !36) -!40 = !DILocation(line: 17, column: 1, scope: !36) diff --git a/llvm/test/Transforms/IndVarSimplify/pr51735.ll b/llvm/test/Transforms/IndVarSimplify/pr51735.ll deleted file mode 100644 index 3014b3467852..000000000000 --- a/llvm/test/Transforms/IndVarSimplify/pr51735.ll +++ /dev/null @@ -1,104 +0,0 @@ -; RUN: opt -passes="loop(indvars)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --check-prefix=PRE-CHECK %s -; RUN: opt -passes="loop(indvars,loop-deletion)" \ -; RUN: --experimental-debuginfo-iterators=false -S -o - < %s | \ -; RUN: FileCheck --check-prefix=POST-CHECK %s - -; Make sure that when we delete the loop in the code below, that the variable -; Index has the 777 value. - -; 1 __attribute__((optnone)) int nop() { -; 2 return 0; -; 3 } -; 4 -; 5 void bar() { -; 6 int End = 777; -; 7 int Index = 27; -; 8 char Var = 1; -; 9 for (; Index < End; ++Index) -; 10 ; -; 11 nop(); -; 12 } -; 13 -; 14 int main () { -; 15 bar(); -; 16 } - -; Only the 'indvars' pass is executed. -; As this test case does not fire the 'indvars' transformation, no debug values -; are preserved and or added. - -; PRE-CHECK: for.cond: -; PRE-CHECK: call void @llvm.dbg.value(metadata i32 poison, metadata ![[DBG_1:[0-9]+]], {{.*}} -; PRE-CHECK: call void @llvm.dbg.value(metadata i32 poison, metadata ![[DBG_1]], {{.*}} -; PRE-CHECK: br i1 false, label %for.cond, label %for.end - -; PRE-CHECK: for.end: -; PRE-CHECK-NOT: call void @llvm.dbg.value -; PRE-CHECK: ret void -; PRE-CHECK-DAG: ![[DBG_1]] = !DILocalVariable(name: "Index"{{.*}}) - -; The 'indvars' and 'loop-deletion' passes are executed. -; The loop is deleted and the debug values collected by 'indvars' are used by -; 'loop-deletion' to add the induction variable debug value. - -; POST-CHECK: for.end: -; POST-CHECK: call void @llvm.dbg.value(metadata i32 777, metadata ![[DBG_2:[0-9]+]], {{.*}} -; POST-CHECK: ret void -; POST-CHECK-DAG: ![[DBG_2]] = !DILocalVariable(name: "Index"{{.*}}) - -define dso_local void @_Z3barv() local_unnamed_addr #1 !dbg !15 { -entry: - call void @llvm.dbg.value(metadata i32 777, metadata !19, metadata !DIExpression()), !dbg !20 - call void @llvm.dbg.value(metadata i32 27, metadata !21, metadata !DIExpression()), !dbg !20 - call void @llvm.dbg.value(metadata i32 1, metadata !22, metadata !DIExpression()), !dbg !20 - br label %for.cond, !dbg !23 - -for.cond: ; preds = %for.cond, %entry - %Index.0 = phi i32 [ 27, %entry ], [ %inc, %for.cond ], !dbg !20 - call void @llvm.dbg.value(metadata i32 %Index.0, metadata !21, metadata !DIExpression()), !dbg !20 - %cmp = icmp ult i32 %Index.0, 777, !dbg !24 - %inc = add nuw nsw i32 %Index.0, 1, !dbg !27 - call void @llvm.dbg.value(metadata i32 %inc, metadata !21, metadata !DIExpression()), !dbg !20 - br i1 %cmp, label %for.cond, label %for.end, !dbg !28, !llvm.loop !29 - -for.end: ; preds = %for.cond - ret void, !dbg !33 -} - -declare void @llvm.dbg.value(metadata, metadata, metadata) - -!llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!2, !3, !4, !5, !6, !7, !8} -!llvm.ident = !{!9} - -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) -!1 = !DIFile(filename: "test.cpp", directory: "") -!2 = !{i32 7, !"Dwarf Version", i32 5} -!3 = !{i32 2, !"Debug Info Version", i32 3} -!4 = !{i32 1, !"wchar_size", i32 4} -!5 = !{i32 8, !"PIC Level", i32 2} -!6 = !{i32 7, !"PIE Level", i32 2} -!7 = !{i32 7, !"uwtable", i32 2} -!8 = !{i32 7, !"frame-pointer", i32 2} -!9 = !{!"clang version 18.0.0"} -!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -!15 = distinct !DISubprogram(name: "bar", linkageName: "_Z3barv", scope: !1, file: !1, line: 5, type: !16, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !18) -!16 = !DISubroutineType(types: !17) -!17 = !{null} -!18 = !{} -!19 = !DILocalVariable(name: "End", scope: !15, file: !1, line: 6, type: !13) -!20 = !DILocation(line: 0, scope: !15) -!21 = !DILocalVariable(name: "Index", scope: !15, file: !1, line: 7, type: !13) -!22 = !DILocalVariable(name: "Var", scope: !15, file: !1, line: 8, type: !13) -!23 = !DILocation(line: 9, column: 3, scope: !15) -!24 = !DILocation(line: 9, column: 16, scope: !25) -!25 = distinct !DILexicalBlock(scope: !26, file: !1, line: 9, column: 3) -!26 = distinct !DILexicalBlock(scope: !15, file: !1, line: 9, column: 3) -!27 = !DILocation(line: 9, column: 23, scope: !25) -!28 = !DILocation(line: 9, column: 3, scope: !26) -!29 = distinct !{!29, !28, !30, !31} -!30 = !DILocation(line: 10, column: 5, scope: !26) -!31 = !{!"llvm.loop.mustprogress"} -!33 = !DILocation(line: 12, column: 1, scope: !15) -- GitLab From 73ddb2a7471986a7ed600dbea14efc60f0d0db47 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Mon, 8 Apr 2024 13:35:37 +0800 Subject: [PATCH 112/695] [RISCV] Store VLMul/NF into RegisterClass's TSFlags This TSFlags was introduced by https://reviews.llvm.org/D108767. A base class of all RISCV RegisterClass is added and we store IsVRegClass/VLMul/NF into TSFlags and add helpers to get them. This can reduce some lines and I think there will be more usages. Reviewers: preames, topperc Reviewed By: topperc Pull Request: https://github.com/llvm/llvm-project/pull/84894 --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 106 ++++----------------- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 55 +++++++---- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 68 +++++++------ 4 files changed, 97 insertions(+), 134 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index a1befaf40d09..153f936326a7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -295,12 +295,13 @@ static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI, return false; } -void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - const DebugLoc &DL, MCRegister DstReg, - MCRegister SrcReg, bool KillSrc, - RISCVII::VLMUL LMul, unsigned NF) const { +void RISCVInstrInfo::copyPhysRegVector( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, + const TargetRegisterClass *RegClass) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); + RISCVII::VLMUL LMul = RISCVRI::getLMul(RegClass->TSFlags); + unsigned NF = RISCVRI::getNF(RegClass->TSFlags); uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg); uint16_t DstEncoding = TRI->getEncodingValue(DstReg); @@ -522,90 +523,17 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } // VR->VR copies. - if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1); - return; - } - - if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2); - return; - } - - if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4); - return; - } - - if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_8); - return; - } - - if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/2); - return; - } - - if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2, - /*NF=*/2); - return; - } - - if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_4, - /*NF=*/2); - return; - } - - if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/3); - return; - } - - if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2, - /*NF=*/3); - return; - } - - if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/4); - return; - } - - if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_2, - /*NF=*/4); - return; - } - - if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/5); - return; - } - - if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/6); - return; - } - - if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/7); - return; - } - - if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) { - copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1, - /*NF=*/8); - return; + static const TargetRegisterClass *RVVRegClasses[] = { + &RISCV::VRRegClass, &RISCV::VRM2RegClass, &RISCV::VRM4RegClass, + &RISCV::VRM8RegClass, &RISCV::VRN2M1RegClass, &RISCV::VRN2M2RegClass, + &RISCV::VRN2M4RegClass, &RISCV::VRN3M1RegClass, &RISCV::VRN3M2RegClass, + &RISCV::VRN4M1RegClass, &RISCV::VRN4M2RegClass, &RISCV::VRN5M1RegClass, + &RISCV::VRN6M1RegClass, &RISCV::VRN7M1RegClass, &RISCV::VRN8M1RegClass}; + for (const auto &RegClass : RVVRegClasses) { + if (RegClass->contains(DstReg, SrcReg)) { + copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass); + return; + } } llvm_unreachable("Impossible reg-to-reg copy"); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index dd049fca0597..3470012d1518 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -69,7 +69,7 @@ public: void copyPhysRegVector(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, - RISCVII::VLMUL LMul, unsigned NF = 1) const; + const TargetRegisterClass *RegClass) const; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc) const override; diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h index 943c4f2627cf..7e04e9154b52 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -14,12 +14,45 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +namespace RISCVRI { +enum { + // The IsVRegClass value of this RegisterClass. + IsVRegClassShift = 0, + IsVRegClassShiftMask = 0b1 << IsVRegClassShift, + // The VLMul value of this RegisterClass. This value is valid iff IsVRegClass + // is true. + VLMulShift = IsVRegClassShift + 1, + VLMulShiftMask = 0b111 << VLMulShift, + + // The NF value of this RegisterClass. This value is valid iff IsVRegClass is + // true. + NFShift = VLMulShift + 3, + NFShiftMask = 0b111 << NFShift, +}; + +/// \returns the IsVRegClass for the register class. +static inline bool isVRegClass(uint64_t TSFlags) { + return TSFlags & IsVRegClassShiftMask >> IsVRegClassShift; +} + +/// \returns the LMUL for the register class. +static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) { + return static_cast((TSFlags & VLMulShiftMask) >> VLMulShift); +} + +/// \returns the NF for the register class. +static inline unsigned getNF(uint64_t TSFlags) { + return static_cast((TSFlags & NFShiftMask) >> NFShift) + 1; +} +} // namespace RISCVRI + struct RISCVRegisterInfo : public RISCVGenRegisterInfo { RISCVRegisterInfo(unsigned HwMode); @@ -116,30 +149,18 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo { } static bool isVRRegClass(const TargetRegisterClass *RC) { - return RISCV::VRRegClass.hasSubClassEq(RC) || - RISCV::VRM2RegClass.hasSubClassEq(RC) || - RISCV::VRM4RegClass.hasSubClassEq(RC) || - RISCV::VRM8RegClass.hasSubClassEq(RC); + return RISCVRI::isVRegClass(RC->TSFlags) && + RISCVRI::getNF(RC->TSFlags) == 1; } static bool isVRNRegClass(const TargetRegisterClass *RC) { - return RISCV::VRN2M1RegClass.hasSubClassEq(RC) || - RISCV::VRN2M2RegClass.hasSubClassEq(RC) || - RISCV::VRN2M4RegClass.hasSubClassEq(RC) || - RISCV::VRN3M1RegClass.hasSubClassEq(RC) || - RISCV::VRN3M2RegClass.hasSubClassEq(RC) || - RISCV::VRN4M1RegClass.hasSubClassEq(RC) || - RISCV::VRN4M2RegClass.hasSubClassEq(RC) || - RISCV::VRN5M1RegClass.hasSubClassEq(RC) || - RISCV::VRN6M1RegClass.hasSubClassEq(RC) || - RISCV::VRN7M1RegClass.hasSubClassEq(RC) || - RISCV::VRN8M1RegClass.hasSubClassEq(RC); + return RISCVRI::isVRegClass(RC->TSFlags) && RISCVRI::getNF(RC->TSFlags) > 1; } static bool isRVVRegClass(const TargetRegisterClass *RC) { - return isVRRegClass(RC) || isVRNRegClass(RC); + return RISCVRI::isVRegClass(RC->TSFlags); } }; -} +} // namespace llvm #endif diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 90c4a7193ee3..316daf2763ca 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -132,8 +132,21 @@ def XLenRI : RegInfoByHwMode< [RV32, RV64], [RegInfo<32,32,32>, RegInfo<64,64,64>]>; +class RISCVRegisterClass regTypes, int align, dag regList> + : RegisterClass<"RISCV", regTypes, align, regList> { + bit IsVRegClass = 0; + int VLMul = 1; + int NF = 1; + + let Size = !if(IsVRegClass, !mul(VLMul, NF, 64), 0); + + let TSFlags{0} = IsVRegClass; + let TSFlags{3-1} = !logtwo(VLMul); + let TSFlags{6-4} = !sub(NF, 1); +} + class GPRRegisterClass - : RegisterClass<"RISCV", [XLenVT, XLenFVT, i32], 32, regList> { + : RISCVRegisterClass<[XLenVT, XLenFVT, i32], 32, regList> { let RegInfos = XLenRI; } @@ -229,7 +242,7 @@ let RegAltNameIndices = [ABIRegAltName] in { // meaning caller-save regs are listed before callee-save. // We start by allocating argument registers in reverse order since they are // compressible. -def FPR16 : RegisterClass<"RISCV", [f16, bf16], 16, (add +def FPR16 : RISCVRegisterClass<[f16, bf16], 16, (add (sequence "F%u_H", 15, 10), // fa5-fa0 (sequence "F%u_H", 0, 7), // ft0-f7 (sequence "F%u_H", 16, 17), // fa6-fa7 @@ -238,7 +251,7 @@ def FPR16 : RegisterClass<"RISCV", [f16, bf16], 16, (add (sequence "F%u_H", 18, 27) // fs2-fs11 )>; -def FPR32 : RegisterClass<"RISCV", [f32], 32, (add +def FPR32 : RISCVRegisterClass<[f32], 32, (add (sequence "F%u_F", 15, 10), (sequence "F%u_F", 0, 7), (sequence "F%u_F", 16, 17), @@ -247,14 +260,14 @@ def FPR32 : RegisterClass<"RISCV", [f32], 32, (add (sequence "F%u_F", 18, 27) )>; -def FPR32C : RegisterClass<"RISCV", [f32], 32, (add +def FPR32C : RISCVRegisterClass<[f32], 32, (add (sequence "F%u_F", 15, 10), (sequence "F%u_F", 8, 9) )>; // The order of registers represents the preferred allocation sequence, // meaning caller-save regs are listed before callee-save. -def FPR64 : RegisterClass<"RISCV", [f64], 64, (add +def FPR64 : RISCVRegisterClass<[f64], 64, (add (sequence "F%u_D", 15, 10), (sequence "F%u_D", 0, 7), (sequence "F%u_D", 16, 17), @@ -263,7 +276,7 @@ def FPR64 : RegisterClass<"RISCV", [f64], 64, (add (sequence "F%u_D", 18, 27) )>; -def FPR64C : RegisterClass<"RISCV", [f64], 64, (add +def FPR64C : RISCVRegisterClass<[f64], 64, (add (sequence "F%u_D", 15, 10), (sequence "F%u_D", 8, 9) )>; @@ -464,8 +477,8 @@ let isConstant = true in def VLENB : RISCVReg<0, "vlenb">, DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>; -def VCSR : RegisterClass<"RISCV", [XLenVT], 32, - (add VTYPE, VL, VLENB)> { +def VCSR : RISCVRegisterClass<[XLenVT], 32, + (add VTYPE, VL, VLENB)> { let RegInfos = XLenRI; let isAllocatable = 0; } @@ -483,12 +496,11 @@ foreach m = [1, 2, 4] in { } class VReg regTypes, dag regList, int Vlmul> - : RegisterClass<"RISCV", - regTypes, - 64, // The maximum supported ELEN is 64. - regList> { - int VLMul = Vlmul; - int Size = !mul(Vlmul, 64); + : RISCVRegisterClass { + let IsVRegClass = 1; + let VLMul = Vlmul; } defvar VMaskVTs = [vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, @@ -537,13 +549,11 @@ def VRM8 : VReg; def VRM8NoV0 : VReg; -def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { - let Size = 64; -} +def VMV0 : VReg; let RegInfos = XLenRI in { -def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add GPR)>; -def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add GPR)>; +def GPRF16 : RISCVRegisterClass<[f16], 16, (add GPR)>; +def GPRF32 : RISCVRegisterClass<[f32], 32, (add GPR)>; } // RegInfos = XLenRI // Dummy zero register for use in the register pair containing X0 (as X1 is @@ -580,7 +590,7 @@ let RegAltNameIndices = [ABIRegAltName] in { let RegInfos = RegInfoByHwMode<[RV32, RV64], [RegInfo<64, 64, 32>, RegInfo<128, 128, 64>]>, DecoderMethod = "DecodeGPRPairRegisterClass" in -def GPRPair : RegisterClass<"RISCV", [XLenPairFVT], 64, (add +def GPRPair : RISCVRegisterClass<[XLenPairFVT], 64, (add X10_X11, X12_X13, X14_X15, X16_X17, X6_X7, X28_X29, X30_X31, @@ -594,13 +604,17 @@ def VM : VReg; foreach m = LMULList in { foreach nf = NFList.L in { - def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], - (add !cast("VN" # nf # "M" # m # "NoV0")), - !mul(nf, m)>; - def "VRN" # nf # "M" # m: VReg<[untyped], - (add !cast("VN" # nf # "M" # m # "NoV0"), - !cast("VN" # nf # "M" # m # "V0")), - !mul(nf, m)>; + let NF = nf in { + def "VRN" # nf # "M" # m # "NoV0" + : VReg<[untyped], + (add !cast("VN" # nf # "M" # m # "NoV0")), + m>; + def "VRN" # nf # "M" # m + : VReg<[untyped], + (add !cast("VN" # nf # "M" # m # "NoV0"), + !cast("VN" # nf # "M" # m # "V0")), + m>; + } } } -- GitLab From b80e51ce4d90a3443f98fe5413171392ae768597 Mon Sep 17 00:00:00 2001 From: Christian Sigg Date: Mon, 8 Apr 2024 07:57:54 +0200 Subject: [PATCH 113/695] [mlir][bazel] Fix BUILD after a2c4b7c8e2740a83f141dcf06cf50359588190b9. --- utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel index 30130131c465..684b59e7f62f 100644 --- a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel @@ -387,6 +387,8 @@ cc_library( ":TestOpsIncGen", ":TestOpsSyntaxIncGen", ":TestTypeDefsIncGen", + "//llvm:Core", + "//llvm:IRReader", "//llvm:Support", "//mlir:ArithDialect", "//mlir:BytecodeOpInterface", @@ -399,6 +401,7 @@ cc_library( "//mlir:DestinationStyleOpInterface", "//mlir:Dialect", "//mlir:DialectUtils", + "//mlir:FromLLVMIRTranslation", "//mlir:FuncDialect", "//mlir:FuncTransforms", "//mlir:FunctionInterfaces", @@ -407,6 +410,7 @@ cc_library( "//mlir:InferTypeOpInterface", "//mlir:InliningUtils", "//mlir:LLVMDialect", + "//mlir:LLVMIRToLLVMTranslation", "//mlir:LinalgDialect", "//mlir:LoopLikeInterface", "//mlir:Pass", @@ -414,6 +418,7 @@ cc_library( "//mlir:SideEffectInterfaces", "//mlir:Support", "//mlir:TensorDialect", + "//mlir:TranslateLib", "//mlir:TransformUtils", "//mlir:Transforms", "//mlir:ViewLikeInterface", -- GitLab From fdd023612ce401d7a1a310fcad2477d19e1d0a5e Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Mon, 8 Apr 2024 00:00:33 -0600 Subject: [PATCH 114/695] Revert "[ORC] Replace some KV loop variables with structured bindings." This reverts commit 006aaf32258fc27656c936f6aad729e4c77e3847 while I investigate some bot failures (See e.g. https://lab.llvm.org/buildbot/#/builders/109/builds/86659). --- llvm/lib/ExecutionEngine/Orc/Core.cpp | 315 +++++++++++++------------- 1 file changed, 162 insertions(+), 153 deletions(-) diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp index 43be471fc3c5..8bb68b45951d 100644 --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -87,13 +87,13 @@ FailedToMaterialize::FailedToMaterialize( // FIXME: Use a new dep-map type for FailedToMaterialize errors so that we // don't have to manually retain/release. - for (auto &[JD, Syms] : *this->Symbols) - JD->Retain(); + for (auto &KV : *this->Symbols) + KV.first->Retain(); } FailedToMaterialize::~FailedToMaterialize() { - for (auto &[JD, Syms] : *Symbols) - JD->Release(); + for (auto &KV : *Symbols) + KV.first->Release(); } std::error_code FailedToMaterialize::convertToErrorCode() const { @@ -187,8 +187,8 @@ AsynchronousSymbolQuery::AsynchronousSymbolQuery( OutstandingSymbolsCount = Symbols.size(); - for (auto &[Name, Flags] : Symbols) - ResolvedSymbols[Name] = ExecutorSymbolDef(); + for (auto &KV : Symbols) + ResolvedSymbols[KV.first] = ExecutorSymbolDef(); } void AsynchronousSymbolQuery::notifySymbolMetRequiredState( @@ -271,8 +271,8 @@ void AsynchronousSymbolQuery::dropSymbol(const SymbolStringPtr &Name) { void AsynchronousSymbolQuery::detach() { ResolvedSymbols.clear(); OutstandingSymbolsCount = 0; - for (auto &[JD, Syms] : QueryRegistrations) - JD->detachQueryHelper(*this, Syms); + for (auto &KV : QueryRegistrations) + KV.first->detachQueryHelper(*this, KV.second); QueryRegistrations.clear(); } @@ -312,8 +312,8 @@ void AbsoluteSymbolsMaterializationUnit::discard(const JITDylib &JD, MaterializationUnit::Interface AbsoluteSymbolsMaterializationUnit::extractFlags(const SymbolMap &Symbols) { SymbolFlagsMap Flags; - for (const auto &[Sym, Def] : Symbols) - Flags[Sym] = Def.getFlags(); + for (const auto &KV : Symbols) + Flags[KV.first] = KV.second.getFlags(); return MaterializationUnit::Interface(std::move(Flags), nullptr); } @@ -397,23 +397,23 @@ void ReExportsMaterializationUnit::materialize( SymbolAliasMap QueryAliases; // Collect as many aliases as we can without including a chain. - for (auto &[Alias, Entry] : RequestedAliases) { + for (auto &KV : RequestedAliases) { // Chain detected. Skip this symbol for this round. - if (&SrcJD == &TgtJD && (QueryAliases.count(Entry.Aliasee) || - RequestedAliases.count(Entry.Aliasee))) + if (&SrcJD == &TgtJD && (QueryAliases.count(KV.second.Aliasee) || + RequestedAliases.count(KV.second.Aliasee))) continue; - ResponsibilitySymbols.insert(Alias); - QuerySymbols.add(Entry.Aliasee, - Entry.AliasFlags.hasMaterializationSideEffectsOnly() + ResponsibilitySymbols.insert(KV.first); + QuerySymbols.add(KV.second.Aliasee, + KV.second.AliasFlags.hasMaterializationSideEffectsOnly() ? SymbolLookupFlags::WeaklyReferencedSymbol : SymbolLookupFlags::RequiredSymbol); - QueryAliases[Alias] = std::move(Entry); + QueryAliases[KV.first] = std::move(KV.second); } // Remove the aliases collected this round from the RequestedAliases map. - for (auto &[Alias, Entry] : QueryAliases) - RequestedAliases.erase(Alias); + for (auto &KV : QueryAliases) + RequestedAliases.erase(KV.first); assert(!QuerySymbols.empty() && "Alias cycle detected!"); @@ -458,16 +458,16 @@ void ReExportsMaterializationUnit::materialize( auto &ES = QueryInfo->R->getTargetJITDylib().getExecutionSession(); if (Result) { SymbolMap ResolutionMap; - for (auto &[Alias, Entry] : QueryInfo->Aliases) { - assert((Entry.AliasFlags.hasMaterializationSideEffectsOnly() || - Result->count(Entry.Aliasee)) && + for (auto &KV : QueryInfo->Aliases) { + assert((KV.second.AliasFlags.hasMaterializationSideEffectsOnly() || + Result->count(KV.second.Aliasee)) && "Result map missing entry?"); // Don't try to resolve materialization-side-effects-only symbols. - if (Entry.AliasFlags.hasMaterializationSideEffectsOnly()) + if (KV.second.AliasFlags.hasMaterializationSideEffectsOnly()) continue; - ResolutionMap[Alias] = {(*Result)[Entry.Aliasee].getAddress(), - Entry.AliasFlags}; + ResolutionMap[KV.first] = {(*Result)[KV.second.Aliasee].getAddress(), + KV.second.AliasFlags}; } if (auto Err = QueryInfo->R->notifyResolved(ResolutionMap)) { ES.reportError(std::move(Err)); @@ -502,8 +502,8 @@ void ReExportsMaterializationUnit::discard(const JITDylib &JD, MaterializationUnit::Interface ReExportsMaterializationUnit::extractFlags(const SymbolAliasMap &Aliases) { SymbolFlagsMap SymbolFlags; - for (auto &[Alias, Entry] : Aliases) - SymbolFlags[Alias] = Entry.AliasFlags; + for (auto &KV : Aliases) + SymbolFlags[KV.first] = KV.second.AliasFlags; return MaterializationUnit::Interface(std::move(SymbolFlags), nullptr); } @@ -628,9 +628,9 @@ Error ReexportsGenerator::tryToGenerate(LookupState &LS, LookupKind K, // Create an alias map. orc::SymbolAliasMap AliasMap; - for (auto &[Name, Flags] : *Flags) - if (!Allow || Allow(Name)) - AliasMap[Name] = SymbolAliasMapEntry(Name, Flags); + for (auto &KV : *Flags) + if (!Allow || Allow(KV.first)) + AliasMap[KV.first] = SymbolAliasMapEntry(KV.first, KV.second); if (AliasMap.empty()) return Error::success(); @@ -677,8 +677,8 @@ Error JITDylib::clear() { std::vector TrackersToRemove; ES.runSessionLocked([&]() { assert(State != Closed && "JD is defunct"); - for (auto &[RT, Syms] : TrackerSymbols) - TrackersToRemove.push_back(RT); + for (auto &KV : TrackerSymbols) + TrackersToRemove.push_back(KV.first); TrackersToRemove.push_back(getDefaultResourceTracker()); }); @@ -783,27 +783,28 @@ Error JITDylib::replace(MaterializationResponsibility &FromMR, auto Err = ES.runSessionLocked([&, this]() -> Error { - // If the tracker is defunct we need to bail out immediately. if (FromMR.RT->isDefunct()) return make_error(std::move(FromMR.RT)); #ifndef NDEBUG - for (auto &[Name, Flags] : MU->getSymbols()) { - auto SymI = Symbols.find(Name); + for (auto &KV : MU->getSymbols()) { + auto SymI = Symbols.find(KV.first); assert(SymI != Symbols.end() && "Replacing unknown symbol"); assert(SymI->second.getState() == SymbolState::Materializing && "Can not replace a symbol that ha is not materializing"); assert(!SymI->second.hasMaterializerAttached() && "Symbol should not have materializer attached already"); - assert(UnmaterializedInfos.count(Name) == 0 && + assert(UnmaterializedInfos.count(KV.first) == 0 && "Symbol being replaced should have no UnmaterializedInfo"); } #endif // NDEBUG + // If the tracker is defunct we need to bail out immediately. + // If any symbol has pending queries against it then we need to // materialize MU immediately. - for (auto &[Name, Flags] : MU->getSymbols()) { - auto MII = MaterializingInfos.find(Name); + for (auto &KV : MU->getSymbols()) { + auto MII = MaterializingInfos.find(KV.first); if (MII != MaterializingInfos.end()) { if (MII->second.hasQueriesPending()) { MustRunMR = ES.createMaterializationResponsibility( @@ -818,18 +819,18 @@ Error JITDylib::replace(MaterializationResponsibility &FromMR, // Otherwise, make MU responsible for all the symbols. auto UMI = std::make_shared(std::move(MU), FromMR.RT.get()); - for (auto &[Name, Flags] : UMI->MU->getSymbols()) { - auto SymI = Symbols.find(Name); + for (auto &KV : UMI->MU->getSymbols()) { + auto SymI = Symbols.find(KV.first); assert(SymI->second.getState() == SymbolState::Materializing && "Can not replace a symbol that is not materializing"); assert(!SymI->second.hasMaterializerAttached() && "Can not replace a symbol that has a materializer attached"); - assert(UnmaterializedInfos.count(Name) == 0 && + assert(UnmaterializedInfos.count(KV.first) == 0 && "Unexpected materializer entry in map"); SymI->second.setAddress(SymI->second.getAddress()); SymI->second.setMaterializerAttached(true); - auto &UMIEntry = UnmaterializedInfos[Name]; + auto &UMIEntry = UnmaterializedInfos[KV.first]; assert((!UMIEntry || !UMIEntry->MU) && "Replacing symbol with materializer still attached"); UMIEntry = UMI; @@ -871,19 +872,19 @@ JITDylib::getRequestedSymbols(const SymbolFlagsMap &SymbolFlags) const { return ES.runSessionLocked([&]() { SymbolNameSet RequestedSymbols; - for (auto &[Name, Flags] : SymbolFlags) { - assert(Symbols.count(Name) && "JITDylib does not cover this symbol?"); - assert(Symbols.find(Name)->second.getState() != + for (auto &KV : SymbolFlags) { + assert(Symbols.count(KV.first) && "JITDylib does not cover this symbol?"); + assert(Symbols.find(KV.first)->second.getState() != SymbolState::NeverSearched && - Symbols.find(Name)->second.getState() != SymbolState::Ready && + Symbols.find(KV.first)->second.getState() != SymbolState::Ready && "getRequestedSymbols can only be called for symbols that have " "started materializing"); - auto I = MaterializingInfos.find(Name); + auto I = MaterializingInfos.find(KV.first); if (I == MaterializingInfos.end()) continue; if (I->second.hasQueriesPending()) - RequestedSymbols.insert(Name); + RequestedSymbols.insert(KV.first); } return RequestedSymbols; @@ -913,12 +914,12 @@ Error JITDylib::resolve(MaterializationResponsibility &MR, Worklist.reserve(Resolved.size()); // Build worklist and check for any symbols in the error state. - for (const auto &[Name, Def] : Resolved) { + for (const auto &KV : Resolved) { - assert(!Def.getFlags().hasError() && + assert(!KV.second.getFlags().hasError() && "Resolution result can not have error flag set"); - auto SymI = Symbols.find(Name); + auto SymI = Symbols.find(KV.first); assert(SymI != Symbols.end() && "Symbol not found"); assert(!SymI->second.hasMaterializerAttached() && @@ -929,15 +930,15 @@ Error JITDylib::resolve(MaterializationResponsibility &MR, "Symbol has already been resolved"); if (SymI->second.getFlags().hasError()) - SymbolsInErrorState.insert(Name); + SymbolsInErrorState.insert(KV.first); else { - auto Flags = Def.getFlags(); + auto Flags = KV.second.getFlags(); Flags &= ~JITSymbolFlags::Common; assert(Flags == (SymI->second.getFlags() & ~JITSymbolFlags::Common) && "Resolved flags should match the declared flags"); - Worklist.push_back({SymI, {Def.getAddress(), Flags}}); + Worklist.push_back({SymI, {KV.second.getAddress(), Flags}}); } } @@ -1018,12 +1019,12 @@ void JITDylib::setLinkOrder(JITDylibSearchOrder NewLinkOrder, void JITDylib::addToLinkOrder(const JITDylibSearchOrder &NewLinks) { ES.runSessionLocked([&]() { - for (auto &Elem : NewLinks) { + for (auto &KV : NewLinks) { // Skip elements of NewLinks that are already in the link order. - if (llvm::is_contained(LinkOrder, Elem)) + if (llvm::is_contained(LinkOrder, KV)) continue; - LinkOrder.push_back(std::move(Elem)); + LinkOrder.push_back(std::move(KV)); } }); } @@ -1139,23 +1140,23 @@ void JITDylib::dump(raw_ostream &OS) { // Sort symbols so we get a deterministic order and can check them in tests. std::vector> SymbolsSorted; - for (auto &[Name, Entry] : Symbols) - SymbolsSorted.emplace_back(Name, &Entry); + for (auto &KV : Symbols) + SymbolsSorted.emplace_back(KV.first, &KV.second); std::sort(SymbolsSorted.begin(), SymbolsSorted.end(), [](const auto &L, const auto &R) { return *L.first < *R.first; }); - for (auto &[Name, Entry] : SymbolsSorted) { - OS << " \"" << Name << "\": "; - if (auto Addr = Entry->getAddress()) + for (auto &KV : SymbolsSorted) { + OS << " \"" << *KV.first << "\": "; + if (auto Addr = KV.second->getAddress()) OS << Addr; else OS << " "; - OS << " " << Entry->getFlags() << " " << Entry->getState(); + OS << " " << KV.second->getFlags() << " " << KV.second->getState(); - if (Entry->hasMaterializerAttached()) { + if (KV.second->hasMaterializerAttached()) { OS << " (Materializer "; - auto I = UnmaterializedInfos.find(Name); + auto I = UnmaterializedInfos.find(KV.first); assert(I != UnmaterializedInfos.end() && "Lazy symbol should have UnmaterializedInfo"); OS << I->second->MU.get() << ", " << I->second->MU->getName() << ")\n"; @@ -1165,20 +1166,21 @@ void JITDylib::dump(raw_ostream &OS) { if (!MaterializingInfos.empty()) OS << " MaterializingInfos entries:\n"; - for (auto &[Name, Entry] : MaterializingInfos) { - OS << " \"" << Name << "\":\n" - << " " << Entry.pendingQueries().size() << " pending queries: { "; - for (const auto &Q : Entry.pendingQueries()) + for (auto &KV : MaterializingInfos) { + OS << " \"" << *KV.first << "\":\n" + << " " << KV.second.pendingQueries().size() + << " pending queries: { "; + for (const auto &Q : KV.second.pendingQueries()) OS << Q.get() << " (" << Q->getRequiredState() << ") "; OS << "}\n Defining EDU: "; - if (Entry.DefiningEDU) { - OS << Entry.DefiningEDU.get() << " { "; - for (auto &[Name, Flags] : Entry.DefiningEDU->Symbols) + if (KV.second.DefiningEDU) { + OS << KV.second.DefiningEDU.get() << " { "; + for (auto &[Name, Flags] : KV.second.DefiningEDU->Symbols) OS << Name << " "; OS << "}\n"; OS << " Dependencies:\n"; - if (!Entry.DefiningEDU->Dependencies.empty()) { - for (auto &[DepJD, Deps] : Entry.DefiningEDU->Dependencies) { + if (!KV.second.DefiningEDU->Dependencies.empty()) { + for (auto &[DepJD, Deps] : KV.second.DefiningEDU->Dependencies) { OS << " " << DepJD->getName() << ": [ "; for (auto &Dep : Deps) OS << Dep << " "; @@ -1189,8 +1191,8 @@ void JITDylib::dump(raw_ostream &OS) { } else OS << "none\n"; OS << " Dependant EDUs:\n"; - if (!Entry.DependantEDUs.empty()) { - for (auto &DependantEDU : Entry.DependantEDUs) { + if (!KV.second.DependantEDUs.empty()) { + for (auto &DependantEDU : KV.second.DependantEDUs) { OS << " " << DependantEDU << ": " << DependantEDU->JD->getName() << " { "; for (auto &[Name, Flags] : DependantEDU->Symbols) @@ -1199,9 +1201,9 @@ void JITDylib::dump(raw_ostream &OS) { } } else OS << " none\n"; - assert((Symbols[Name].getState() != SymbolState::Ready || - (Entry.pendingQueries().empty() && !Entry.DefiningEDU && - !Entry.DependantEDUs.empty())) && + assert((Symbols[KV.first].getState() != SymbolState::Ready || + (KV.second.pendingQueries().empty() && !KV.second.DefiningEDU && + !KV.second.DependantEDUs.empty())) && "Stale materializing info entry"); } }); @@ -1260,13 +1262,14 @@ JITDylib::removeTracker(ResourceTracker &RT) { if (&RT == DefaultTracker.get()) { SymbolNameSet TrackedSymbols; - for (auto &[RT, Syms] : TrackerSymbols) - for (auto &Sym : Syms) + for (auto &KV : TrackerSymbols) + for (auto &Sym : KV.second) TrackedSymbols.insert(Sym); - for (auto &[Name, Entry] : Symbols) { - if (!TrackedSymbols.count(Name)) - SymbolsToRemove.push_back(Name); + for (auto &KV : Symbols) { + auto &Sym = KV.first; + if (!TrackedSymbols.count(Sym)) + SymbolsToRemove.push_back(Sym); } DefaultTracker.reset(); @@ -1320,9 +1323,9 @@ void JITDylib::transferTracker(ResourceTracker &DstRT, ResourceTracker &SrcRT) { assert(&SrcRT.getJITDylib() == this && "SrcRT is not for this JITDylib"); // Update trackers for any not-yet materialized units. - for (auto &[Name, Entry] : UnmaterializedInfos) { - if (Entry->RT == &SrcRT) - Entry->RT = &DstRT; + for (auto &KV : UnmaterializedInfos) { + if (KV.second->RT == &SrcRT) + KV.second->RT = &DstRT; } // Update trackers for any active materialization responsibilities. @@ -1360,13 +1363,14 @@ void JITDylib::transferTracker(ResourceTracker &DstRT, ResourceTracker &SrcRT) { SymbolNameVector SymbolsToTrack; SymbolNameSet CurrentlyTrackedSymbols; - for (auto &[Name, Syms] : TrackerSymbols) - for (auto &Sym : Syms) + for (auto &KV : TrackerSymbols) + for (auto &Sym : KV.second) CurrentlyTrackedSymbols.insert(Sym); - for (auto &[Name, Entry] : Symbols) { - if (!CurrentlyTrackedSymbols.count(Name)) - SymbolsToTrack.push_back(Name); + for (auto &KV : Symbols) { + auto &Sym = KV.first; + if (!CurrentlyTrackedSymbols.count(Sym)) + SymbolsToTrack.push_back(Sym); } TrackerSymbols[&DstRT] = std::move(SymbolsToTrack); @@ -1394,22 +1398,22 @@ Error JITDylib::defineImpl(MaterializationUnit &MU) { std::vector ExistingDefsOverridden; std::vector MUDefsOverridden; - for (const auto &[Name, Flags] : MU.getSymbols()) { - auto I = Symbols.find(Name); + for (const auto &KV : MU.getSymbols()) { + auto I = Symbols.find(KV.first); if (I != Symbols.end()) { - if (Flags.isStrong()) { + if (KV.second.isStrong()) { if (I->second.getFlags().isStrong() || I->second.getState() > SymbolState::NeverSearched) - Duplicates.insert(Name); + Duplicates.insert(KV.first); else { assert(I->second.getState() == SymbolState::NeverSearched && "Overridden existing def should be in the never-searched " "state"); - ExistingDefsOverridden.push_back(Name); + ExistingDefsOverridden.push_back(KV.first); } } else - MUDefsOverridden.push_back(Name); + MUDefsOverridden.push_back(KV.first); } } @@ -1443,9 +1447,9 @@ Error JITDylib::defineImpl(MaterializationUnit &MU) { } // Finally, add the defs from this MU. - for (auto &[Name, Flags] : MU.getSymbols()) { - auto &SymEntry = Symbols[Name]; - SymEntry.setFlags(Flags); + for (auto &KV : MU.getSymbols()) { + auto &SymEntry = Symbols[KV.first]; + SymEntry.setFlags(KV.second); SymEntry.setState(SymbolState::NeverSearched); SymEntry.setMaterializerAttached(true); } @@ -1460,13 +1464,13 @@ void JITDylib::installMaterializationUnit( if (&RT != DefaultTracker.get()) { auto &TS = TrackerSymbols[&RT]; TS.reserve(TS.size() + MU->getSymbols().size()); - for (auto &[Name, Flags] : MU->getSymbols()) - TS.push_back(Name); + for (auto &KV : MU->getSymbols()) + TS.push_back(KV.first); } auto UMI = std::make_shared(std::move(MU), &RT); - for (auto &[Name, Flags] : UMI->MU->getSymbols()) - UnmaterializedInfos[Name] = UMI; + for (auto &KV : UMI->MU->getSymbols()) + UnmaterializedInfos[KV.first] = UMI; } void JITDylib::detachQueryHelper(AsynchronousSymbolQuery &Q, @@ -1493,18 +1497,18 @@ Expected> Platform::lookupInitSymbols( LLVM_DEBUG({ dbgs() << "Issuing init-symbol lookup:\n"; - for (auto &[JD, Syms] : InitSyms) - dbgs() << " " << JD->getName() << ": " << Syms << "\n"; + for (auto &KV : InitSyms) + dbgs() << " " << KV.first->getName() << ": " << KV.second << "\n"; }); for (auto &KV : InitSyms) { auto *JD = KV.first; - auto &Names = KV.second; + auto Names = std::move(KV.second); ES.lookup( LookupKind::Static, JITDylibSearchOrder({{JD, JITDylibLookupFlags::MatchAllSymbols}}), std::move(Names), SymbolState::Ready, - [&](Expected Result) { + [&, JD](Expected Result) { { std::lock_guard Lock(LookupMutex); --Count; @@ -1553,13 +1557,15 @@ void Platform::lookupInitSymbolsAsync( LLVM_DEBUG({ dbgs() << "Issuing init-symbol lookup:\n"; - for (auto &[JD, Syms] : InitSyms) - dbgs() << " " << JD->getName() << ": " << Syms << "\n"; + for (auto &KV : InitSyms) + dbgs() << " " << KV.first->getName() << ": " << KV.second << "\n"; }); auto TOC = std::make_shared(std::move(OnComplete)); - for (auto &[JD, Names] : InitSyms) { + for (auto &KV : InitSyms) { + auto *JD = KV.first; + auto Names = std::move(KV.second); ES.lookup( LookupKind::Static, JITDylibSearchOrder({{JD, JITDylibLookupFlags::MatchAllSymbols}}), @@ -1726,10 +1732,11 @@ JITDylib::getDFSLinkOrder(ArrayRef JDs) { Result.push_back(std::move(WorkStack.back())); WorkStack.pop_back(); - for (auto &[JD, Flags] : llvm::reverse(Result.back()->LinkOrder)) { - if (!Visited.insert(JD).second) + for (auto &KV : llvm::reverse(Result.back()->LinkOrder)) { + auto &JD = *KV.first; + if (!Visited.insert(&JD).second) continue; - WorkStack.push_back(JD); + WorkStack.push_back(&JD); } } } @@ -1899,21 +1906,21 @@ Error ExecutionSession::registerJITDispatchHandlers( // Associate tag addresses with implementations. std::lock_guard Lock(JITDispatchHandlersMutex); - for (auto &[Name, Def] : *TagAddrs) { - auto TagAddr = Def.getAddress(); + for (auto &KV : *TagAddrs) { + auto TagAddr = KV.second.getAddress(); if (JITDispatchHandlers.count(TagAddr)) return make_error("Tag " + formatv("{0:x16}", TagAddr) + - " (for " + *Name + + " (for " + *KV.first + ") already registered", inconvertibleErrorCode()); - auto I = WFs.find(Name); + auto I = WFs.find(KV.first); assert(I != WFs.end() && I->second && "JITDispatchHandler implementation missing"); - JITDispatchHandlers[Def.getAddress()] = + JITDispatchHandlers[KV.second.getAddress()] = std::make_shared(std::move(I->second)); LLVM_DEBUG({ - dbgs() << "Associated function tag \"" << *Name << "\" (" - << formatv("{0:x}", Def.getAddress()) << ") with handler\n"; + dbgs() << "Associated function tag \"" << *KV.first << "\" (" + << formatv("{0:x}", KV.second.getAddress()) << ") with handler\n"; }); } return Error::success(); @@ -2346,11 +2353,11 @@ void ExecutionSession::OL_applyQueryPhase1( // Get the next JITDylib and lookup flags. auto &KV = IPLS->SearchOrder[IPLS->CurSearchOrderIndex]; - auto *JD = KV.first; + auto &JD = *KV.first; auto JDLookupFlags = KV.second; LLVM_DEBUG({ - dbgs() << "Visiting \"" << JD->getName() << "\" (" << JDLookupFlags + dbgs() << "Visiting \"" << JD.getName() << "\" (" << JDLookupFlags << ") with lookup set " << IPLS->LookupSet << ":\n"; }); @@ -2364,14 +2371,14 @@ void ExecutionSession::OL_applyQueryPhase1( IPLS->DefGeneratorCandidates.append(std::move(Tmp)); LLVM_DEBUG({ - dbgs() << " First time visiting " << JD->getName() + dbgs() << " First time visiting " << JD.getName() << ", resetting candidate sets and building generator stack\n"; }); // Build the definition generator stack for this JITDylib. runSessionLocked([&] { - IPLS->CurDefGeneratorStack.reserve(JD->DefGenerators.size()); - for (auto &DG : reverse(JD->DefGenerators)) + IPLS->CurDefGeneratorStack.reserve(JD.DefGenerators.size()); + for (auto &DG : reverse(JD.DefGenerators)) IPLS->CurDefGeneratorStack.push_back(DG); }); @@ -2386,9 +2393,9 @@ void ExecutionSession::OL_applyQueryPhase1( // generation. LLVM_DEBUG(dbgs() << " Updating candidate set...\n"); Err = IL_updateCandidatesFor( - *JD, JDLookupFlags, IPLS->DefGeneratorCandidates, - JD->DefGenerators.empty() ? nullptr - : &IPLS->DefGeneratorNonCandidates); + JD, JDLookupFlags, IPLS->DefGeneratorCandidates, + JD.DefGenerators.empty() ? nullptr + : &IPLS->DefGeneratorNonCandidates); LLVM_DEBUG({ dbgs() << " Remaining candidates = " << IPLS->DefGeneratorCandidates << "\n"; @@ -2455,7 +2462,7 @@ void ExecutionSession::OL_applyQueryPhase1( { LLVM_DEBUG(dbgs() << " Attempting to generate " << LookupSet << "\n"); LookupState LS(std::move(IPLS)); - Err = DG->tryToGenerate(LS, K, *JD, JDLookupFlags, LookupSet); + Err = DG->tryToGenerate(LS, K, JD, JDLookupFlags, LookupSet); IPLS = std::move(LS.IPLS); } @@ -2485,9 +2492,9 @@ void ExecutionSession::OL_applyQueryPhase1( runSessionLocked([&] { LLVM_DEBUG(dbgs() << " Updating candidate set post-generation\n"); Err = IL_updateCandidatesFor( - *JD, JDLookupFlags, IPLS->DefGeneratorCandidates, - JD->DefGenerators.empty() ? nullptr - : &IPLS->DefGeneratorNonCandidates); + JD, JDLookupFlags, IPLS->DefGeneratorCandidates, + JD.DefGenerators.empty() ? nullptr + : &IPLS->DefGeneratorNonCandidates); }); // If updating candidates failed then fail the query. @@ -2642,13 +2649,13 @@ void ExecutionSession::OL_completeLookup( // Move all symbols associated with this MaterializationUnit into // materializing state. - for (auto &[MUSymName, MUSymFlags] : UMI->MU->getSymbols()) { - auto SymK = JD.Symbols.find(MUSymName); + for (auto &KV : UMI->MU->getSymbols()) { + auto SymK = JD.Symbols.find(KV.first); assert(SymK != JD.Symbols.end() && "No entry for symbol covered by MaterializationUnit"); SymK->second.setMaterializerAttached(false); SymK->second.setState(SymbolState::Materializing); - JD.UnmaterializedInfos.erase(MUSymName); + JD.UnmaterializedInfos.erase(KV.first); } // Add MU to the list of MaterializationUnits to be materialized. @@ -2679,19 +2686,20 @@ void ExecutionSession::OL_completeLookup( Q->detach(); // Replace the MUs. - for (auto &[JD, UMIs] : CollectedUMIs) { - for (auto &UMI : UMIs) - for (auto &[Name, Flags] : UMI->MU->getSymbols()) { - assert(!JD->UnmaterializedInfos.count(Name) && + for (auto &KV : CollectedUMIs) { + auto &JD = *KV.first; + for (auto &UMI : KV.second) + for (auto &KV2 : UMI->MU->getSymbols()) { + assert(!JD.UnmaterializedInfos.count(KV2.first) && "Unexpected materializer in map"); - auto SymI = JD->Symbols.find(Name); - assert(SymI != JD->Symbols.end() && "Missing symbol entry"); + auto SymI = JD.Symbols.find(KV2.first); + assert(SymI != JD.Symbols.end() && "Missing symbol entry"); assert(SymI->second.getState() == SymbolState::Materializing && "Can not replace symbol that is not materializing"); assert(!SymI->second.hasMaterializerAttached() && "MaterializerAttached flag should not be set"); SymI->second.setMaterializerAttached(true); - JD->UnmaterializedInfos[Name] = UMI; + JD.UnmaterializedInfos[KV2.first] = UMI; } } @@ -2728,12 +2736,13 @@ void ExecutionSession::OL_completeLookup( std::lock_guard Lock(OutstandingMUsMutex); LLVM_DEBUG(dbgs() << "Adding MUs to dispatch:\n"); - for (auto &[JD, UMIs] : CollectedUMIs) { + for (auto &KV : CollectedUMIs) { LLVM_DEBUG({ - dbgs() << " For " << JD->getName() << ": Adding " << UMIs.size() + auto &JD = *KV.first; + dbgs() << " For " << JD.getName() << ": Adding " << KV.second.size() << " MUs.\n"; }); - for (auto &UMI : UMIs) { + for (auto &UMI : KV.second) { auto MR = createMaterializationResponsibility( *UMI->RT, std::move(UMI->MU->SymbolFlags), std::move(UMI->MU->InitSymbol)); @@ -2868,13 +2877,13 @@ Error ExecutionSession::OL_notifyResolved(MaterializationResponsibility &MR, dbgs() << "In " << MR.JD.getName() << " resolving " << Symbols << "\n"; }); #ifndef NDEBUG - for (auto &[Name, Def] : Symbols) { - auto I = MR.SymbolFlags.find(Name); + for (auto &KV : Symbols) { + auto I = MR.SymbolFlags.find(KV.first); assert(I != MR.SymbolFlags.end() && "Resolving symbol outside this responsibility set"); assert(!I->second.hasMaterializationSideEffectsOnly() && "Can't resolve materialization-side-effects-only symbol"); - assert((Def.getFlags() & ~JITSymbolFlags::Common) == + assert((KV.second.getFlags() & ~JITSymbolFlags::Common) == (I->second & ~JITSymbolFlags::Common) && "Resolving symbol with incorrect flags"); } @@ -3676,10 +3685,10 @@ void ExecutionSession::OL_notifyFailed(MaterializationResponsibility &MR) { Error ExecutionSession::OL_replace(MaterializationResponsibility &MR, std::unique_ptr MU) { - for (auto &[Name, Flags] : MU->getSymbols()) { - assert(MR.SymbolFlags.count(Name) && + for (auto &KV : MU->getSymbols()) { + assert(MR.SymbolFlags.count(KV.first) && "Replacing definition outside this responsibility set"); - MR.SymbolFlags.erase(Name); + MR.SymbolFlags.erase(KV.first); } if (MU->getInitializerSymbol() == MR.InitSymbol) -- GitLab From 9ffecef1c651a5c1a3f284b3257ec01ff526b49c Mon Sep 17 00:00:00 2001 From: Prashant Kumar Date: Mon, 8 Apr 2024 12:04:36 +0530 Subject: [PATCH 115/695] [mlir][vector][NFC] Fix typo temp -> tmp. (#87878) --- mlir/include/mlir/Dialect/Vector/IR/VectorOps.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td index 06360bd10e52..147bc2354977 100644 --- a/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td +++ b/mlir/include/mlir/Dialect/Vector/IR/VectorOps.td @@ -1325,7 +1325,7 @@ def Vector_TransferReadOp : // Update the temporary gathered slice with the individual element %slice = memref.load %tmp : memref> -> vector<3x4x5xf32> %updated = vector.insert %a, %slice[%i, %j, %k] : f32 into vector<3x4x5xf32> - memref.store %updated, %temp : memref> + memref.store %updated, %tmp : memref> }}} // At this point we gathered the elements from the original // memref into the desired vector layout, stored in the `%tmp` allocation. @@ -1348,7 +1348,7 @@ def Vector_TransferReadOp : %slice = memref.load %tmp : memref> -> vector<3x4x5xf32> // Here we only store to the first element in dimension one %updated = vector.insert %a, %slice[%i, 0, %k] : f32 into vector<3x4x5xf32> - memref.store %updated, %temp : memref> + memref.store %updated, %tmp : memref> }} // At this point we gathered the elements from the original // memref into the desired vector layout, stored in the `%tmp` allocation. -- GitLab From eaa063f0c6d51a3b561bc2007fe95420949f42d1 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Mon, 8 Apr 2024 14:58:40 +0800 Subject: [PATCH 116/695] [RISCV] Remove duplicated --target --- clang/test/Driver/riscv-profiles.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 0227487015ba..ec9206f2f453 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -50,7 +50,7 @@ // RVA20S64: "-target-feature" "+svade" // RVA20S64: "-target-feature" "+svbare" -// RUN: %clang --target=riscv64 --target=riscv64 -### -c %s 2>&1 -march=rva22u64 \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva22u64 \ // RUN: | FileCheck -check-prefix=RVA22U64 %s // RVA22U64: "-target-feature" "+m" // RVA22U64: "-target-feature" "+a" @@ -76,7 +76,7 @@ // RVA22U64: "-target-feature" "+zbs" // RVA22U64: "-target-feature" "+zkt" -// RUN: %clang --target=riscv64 --target=riscv64 -### -c %s 2>&1 -march=rva22s64 \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva22s64 \ // RUN: | FileCheck -check-prefix=RVA22S64 %s // RVA22S64: "-target-feature" "+m" // RVA22S64: "-target-feature" "+a" @@ -111,7 +111,7 @@ // RVA22S64: "-target-feature" "+svinval" // RVA22S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \ // RUN: | FileCheck -check-prefix=RVA23U64 %s // RVA23U64: "-target-feature" "+m" // RVA23U64: "-target-feature" "+a" -- GitLab From 110c22fe127f0c8c0d8acfddd123b9e9423d087a Mon Sep 17 00:00:00 2001 From: Bevin Hansson <59652494+bevin-hansson@users.noreply.github.com> Date: Mon, 8 Apr 2024 09:07:55 +0200 Subject: [PATCH 117/695] [ExpandLargeFpConvert] Support bfloat. (#87619) The conversion expansions did not properly handle bfloat types. I'm not certain that these expansions are completely correct; I don't have any experience with AMDGPU or the ability to run anything to test it. Note that it doesn't seem like AMDGPU with GlobalISel can handle fptrunc of float to bfloat, which is needed for itofp. I've omitted the GISEL run for the bfloat case. This fixes #85379. --- llvm/lib/CodeGen/ExpandLargeFpConvert.cpp | 6 +- llvm/test/CodeGen/AMDGPU/fptoi.i128.ll | 709 +++++++++++++++++++++- llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll | 275 +++++++++ llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 10 - 4 files changed, 979 insertions(+), 21 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll diff --git a/llvm/lib/CodeGen/ExpandLargeFpConvert.cpp b/llvm/lib/CodeGen/ExpandLargeFpConvert.cpp index 62135304e859..938dda37b9f6 100644 --- a/llvm/lib/CodeGen/ExpandLargeFpConvert.cpp +++ b/llvm/lib/CodeGen/ExpandLargeFpConvert.cpp @@ -116,7 +116,8 @@ static void expandFPToI(Instruction *FPToI) { // fp80 conversion is implemented by fpext to fp128 first then do the // conversion. FPMantissaWidth = FPMantissaWidth == 63 ? 112 : FPMantissaWidth; - unsigned FloatWidth = PowerOf2Ceil(FPMantissaWidth); + unsigned FloatWidth = + PowerOf2Ceil(FloatVal->getType()->getScalarSizeInBits()); unsigned ExponentWidth = FloatWidth - FPMantissaWidth - 1; unsigned ExponentBias = (1 << (ExponentWidth - 1)) - 1; Value *ImplicitBit = Builder.CreateShl( @@ -319,6 +320,7 @@ static void expandIToFP(Instruction *IToFP) { // FIXME: As there is no related builtins added in compliler-rt, // here currently utilized the fp32 <-> fp16 lib calls to implement. FPMantissaWidth = FPMantissaWidth == 10 ? 23 : FPMantissaWidth; + FPMantissaWidth = FPMantissaWidth == 7 ? 23 : FPMantissaWidth; unsigned FloatWidth = PowerOf2Ceil(FPMantissaWidth); bool IsSigned = IToFP->getOpcode() == Instruction::SIToFP; @@ -547,7 +549,7 @@ static void expandIToFP(Instruction *IToFP) { Value *A40 = Builder.CreateBitCast(Or35, Type::getFP128Ty(Builder.getContext())); A4 = Builder.CreateFPTrunc(A40, IToFP->getType()); - } else if (IToFP->getType()->isHalfTy()) { + } else if (IToFP->getType()->isHalfTy() || IToFP->getType()->isBFloatTy()) { // Deal with "half" situation. This is a workaround since we don't have // floattihf.c currently as referring. Value *A40 = diff --git a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll index 66bf0d5abb73..99818df6175b 100644 --- a/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll +++ b/llvm/test/CodeGen/AMDGPU/fptoi.i128.ll @@ -1490,13 +1490,704 @@ define i128 @fptoui_f16_to_i128(half %x) { ret i128 %cvt } -; FIXME: ExpandLargeFpConvert asserts on bfloat -; define i128 @fptosi_bf16_to_i128(bfloat %x) { -; %cvt = fptosi bfloat %x to i128 -; ret i128 %cvt -; } +define i128 @fptosi_bf16_to_i128(bfloat %x) { +; SDAG-LABEL: fptosi_bf16_to_i128: +; SDAG: ; %bb.0: ; %fp-to-i-entry +; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v4, v0 +; SDAG-NEXT: v_bfe_u32 v5, v4, 7, 8 +; SDAG-NEXT: s_movk_i32 s4, 0x7e +; SDAG-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-NEXT: v_mov_b32_e32 v2, 0 +; SDAG-NEXT: v_mov_b32_e32 v6, 0 +; SDAG-NEXT: v_mov_b32_e32 v1, 0 +; SDAG-NEXT: v_mov_b32_e32 v3, 0 +; SDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v5 +; SDAG-NEXT: s_and_saveexec_b64 s[8:9], vcc +; SDAG-NEXT: s_cbranch_execz .LBB6_10 +; SDAG-NEXT: ; %bb.1: ; %fp-to-i-if-end +; SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff01, v5 +; SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v6, vcc +; SDAG-NEXT: v_addc_co_u32_e32 v2, vcc, -1, v6, vcc +; SDAG-NEXT: s_movk_i32 s4, 0xff7f +; SDAG-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v6, vcc +; SDAG-NEXT: s_mov_b32 s5, -1 +; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[4:5], v[0:1] +; SDAG-NEXT: v_cmp_eq_u64_e64 s[6:7], -1, v[2:3] +; SDAG-NEXT: v_cmp_lt_i16_e32 vcc, -1, v4 +; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5] +; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 +; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3 +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_xor_b64 s[10:11], exec, s[6:7] +; SDAG-NEXT: s_cbranch_execz .LBB6_7 +; SDAG-NEXT: ; %bb.2: ; %fp-to-i-if-end9 +; SDAG-NEXT: s_movk_i32 s4, 0x7f +; SDAG-NEXT: v_and_b32_sdwa v0, v4, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; SDAG-NEXT: s_mov_b64 s[4:5], 0x85 +; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[4:5], v[5:6] +; SDAG-NEXT: v_mov_b32_e32 v7, 0 +; SDAG-NEXT: v_cndmask_b32_e64 v9, -1, 0, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v8, -1, 1, vcc +; SDAG-NEXT: v_or_b32_e32 v6, 0x80, v0 +; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 +; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3 +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_xor_b64 s[12:13], exec, s[6:7] +; SDAG-NEXT: s_cbranch_execz .LBB6_4 +; SDAG-NEXT: ; %bb.3: ; %fp-to-i-if-else +; SDAG-NEXT: v_sub_u32_e32 v0, 0xc6, v5 +; SDAG-NEXT: v_add_u32_e32 v2, 0xffffff3a, v5 +; SDAG-NEXT: v_add_u32_e32 v4, 0xffffff7a, v5 +; SDAG-NEXT: v_lshrrev_b64 v[0:1], v0, v[6:7] +; SDAG-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7] +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v4 +; SDAG-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] +; SDAG-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4 +; SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v1, s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5] +; SDAG-NEXT: v_lshlrev_b64 v[0:1], v4, v[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v12, 0, v0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v1, s[4:5] +; SDAG-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v8, 0 +; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; SDAG-NEXT: v_mul_lo_u32 v13, v9, v2 +; SDAG-NEXT: v_mov_b32_e32 v6, v1 +; SDAG-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v11, v8, v[6:7] +; SDAG-NEXT: v_mul_lo_u32 v14, v8, v3 +; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v2, 0 +; SDAG-NEXT: v_add_co_u32_e64 v6, s[4:5], -1, v10 +; SDAG-NEXT: v_mov_b32_e32 v10, v5 +; SDAG-NEXT: v_mov_b32_e32 v5, v7 +; SDAG-NEXT: v_addc_co_u32_e64 v8, s[4:5], 0, -1, s[4:5] +; SDAG-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v9, v[4:5] +; SDAG-NEXT: v_add3_u32 v3, v3, v14, v13 +; SDAG-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v6, v12, v[2:3] +; SDAG-NEXT: v_add_co_u32_e64 v5, s[4:5], v10, v5 +; SDAG-NEXT: v_mul_lo_u32 v3, v6, v11 +; SDAG-NEXT: v_addc_co_u32_e64 v6, s[4:5], 0, 0, s[4:5] +; SDAG-NEXT: v_mul_lo_u32 v7, v8, v12 +; SDAG-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v11, v9, v[5:6] +; SDAG-NEXT: ; implicit-def: $vgpr8 +; SDAG-NEXT: v_add3_u32 v3, v7, v2, v3 +; SDAG-NEXT: v_add_co_u32_e64 v2, s[4:5], v5, v1 +; SDAG-NEXT: v_addc_co_u32_e64 v3, s[4:5], v6, v3, s[4:5] +; SDAG-NEXT: ; implicit-def: $vgpr5_vgpr6 +; SDAG-NEXT: v_mov_b32_e32 v1, v4 +; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7 +; SDAG-NEXT: .LBB6_4: ; %Flow +; SDAG-NEXT: s_andn2_saveexec_b64 s[6:7], s[12:13] +; SDAG-NEXT: ; %bb.5: ; %fp-to-i-if-then12 +; SDAG-NEXT: v_sub_u32_e32 v2, 0x86, v5 +; SDAG-NEXT: v_lshrrev_b64 v[0:1], v2, v[6:7] +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v2 +; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[4:5] +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2 +; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5] +; SDAG-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v8 +; SDAG-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; SDAG-NEXT: v_mul_i32_i24_e32 v0, v0, v8 +; SDAG-NEXT: v_mov_b32_e32 v3, v2 +; SDAG-NEXT: ; %bb.6: ; %Flow1 +; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] +; SDAG-NEXT: .LBB6_7: ; %Flow2 +; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11] +; SDAG-NEXT: ; %bb.8: ; %fp-to-i-if-then5 +; SDAG-NEXT: v_bfrev_b32_e32 v0, 1 +; SDAG-NEXT: v_bfrev_b32_e32 v1, -2 +; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; SDAG-NEXT: v_mov_b32_e32 v0, v2 +; SDAG-NEXT: v_mov_b32_e32 v1, v2 +; SDAG-NEXT: ; %bb.9: ; %Flow3 +; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; SDAG-NEXT: .LBB6_10: ; %fp-to-i-cleanup +; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] +; SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: fptosi_bf16_to_i128: +; GISEL: ; %bb.0: ; %fp-to-i-entry +; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-NEXT: v_mov_b32_e32 v4, v0 +; GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v4 +; GISEL-NEXT: v_mov_b32_e32 v6, 0 +; GISEL-NEXT: v_lshrrev_b64 v[0:1], 7, v[5:6] +; GISEL-NEXT: v_mov_b32_e32 v1, 0x7f +; GISEL-NEXT: s_mov_b64 s[4:5], 0 +; GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-NEXT: v_bfe_u32 v5, v0, 0, 8 +; GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[5:6], v[1:2] +; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5] +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 +; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc +; GISEL-NEXT: s_cbranch_execz .LBB6_10 +; GISEL-NEXT: ; %bb.1: ; %fp-to-i-if-end +; GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff01, v5 +; GISEL-NEXT: v_mov_b32_e32 v2, 0xffffff80 +; GISEL-NEXT: v_addc_co_u32_e64 v1, s[6:7], 0, -1, vcc +; GISEL-NEXT: v_mov_b32_e32 v3, -1 +; GISEL-NEXT: v_addc_co_u32_e64 v7, s[6:7], 0, -1, s[6:7] +; GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[0:1], v[2:3] +; GISEL-NEXT: v_addc_co_u32_e64 v8, s[6:7], 0, -1, s[6:7] +; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GISEL-NEXT: v_cmp_le_u64_e32 vcc, -1, v[7:8] +; GISEL-NEXT: v_cmp_lt_i16_e64 s[4:5], -1, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, -1, v[7:8] +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_and_b32_e32 v0, 1, v0 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GISEL-NEXT: s_xor_b64 s[14:15], exec, s[6:7] +; GISEL-NEXT: s_cbranch_execz .LBB6_7 +; GISEL-NEXT: ; %bb.2: ; %fp-to-i-if-end9 +; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[6:7] +; GISEL-NEXT: v_and_b32_e32 v0, 1, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v2, 1, v0 +; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[6:7] +; GISEL-NEXT: v_lshlrev_b16_e32 v3, 2, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v7, 3, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v8, 4, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v9, 5, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v10, 6, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v11, 7, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v12, 8, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v13, 9, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v14, 10, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v15, 11, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v16, 12, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v17, 13, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v18, 14, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v19, 15, v0 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v2 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v2 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v3 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v3 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v7 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v7 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v8 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v8 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v9 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v9 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v10 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v10 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v11 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v11 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v12 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v12 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v13 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v13 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v14 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v14 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v15 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v15 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v16 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v16 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v17 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v17 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v18 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v18 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v19 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v19 +; GISEL-NEXT: v_and_b32_e32 v11, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v11 +; GISEL-NEXT: v_or3_b32 v9, v1, v0, 1 +; GISEL-NEXT: v_or3_b32 v10, v11, v0, 0 +; GISEL-NEXT: v_mov_b32_e32 v0, 0x86 +; GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-NEXT: v_and_b32_e32 v2, 0x7f, v4 +; GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[5:6], v[0:1] +; GISEL-NEXT: v_or_b32_e32 v7, 0x80, v2 +; GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GISEL-NEXT: s_xor_b64 s[16:17], exec, s[6:7] +; GISEL-NEXT: s_cbranch_execz .LBB6_4 +; GISEL-NEXT: ; %bb.3: ; %fp-to-i-if-else +; GISEL-NEXT: v_add_u32_e32 v6, 0xffffff7a, v5 +; GISEL-NEXT: v_lshlrev_b64 v[0:1], v6, v[7:8] +; GISEL-NEXT: v_subrev_u32_e32 v4, 64, v6 +; GISEL-NEXT: v_sub_u32_e32 v2, 64, v6 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6 +; GISEL-NEXT: v_lshl_or_b32 v11, v11, 16, v11 +; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[7:8] +; GISEL-NEXT: v_lshlrev_b64 v[4:5], v4, v[7:8] +; GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v1, vcc +; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v8, v11, 0 +; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 +; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v10, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v13, v2, 0, s[6:7] +; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v8, v9, 0 +; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v9, v[6:7] +; GISEL-NEXT: v_mul_lo_u32 v4, v12, v11 +; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GISEL-NEXT: v_mov_b32_e32 v2, v6 +; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v8, v10, v[1:2] +; GISEL-NEXT: v_mul_lo_u32 v6, v8, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7] +; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v12, v9, v[1:2] +; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11] +; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9] +; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v10, v[4:5] +; GISEL-NEXT: ; implicit-def: $vgpr5 +; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v9, v[6:7] +; GISEL-NEXT: ; implicit-def: $vgpr7_vgpr8 +; GISEL-NEXT: ; implicit-def: $vgpr9 +; GISEL-NEXT: .LBB6_4: ; %Flow +; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17] +; GISEL-NEXT: s_cbranch_execz .LBB6_6 +; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12 +; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x86, v5 +; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3 +; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[7:8] +; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc +; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v9 +; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; GISEL-NEXT: v_mul_i32_i24_e32 v0, v0, v9 +; GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GISEL-NEXT: .LBB6_6: ; %Flow1 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: .LBB6_7: ; %Flow2 +; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[14:15] +; GISEL-NEXT: s_cbranch_execz .LBB6_9 +; GISEL-NEXT: ; %bb.8: ; %fp-to-i-if-then5 +; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5] +; GISEL-NEXT: v_and_b32_e32 v1, 1, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GISEL-NEXT: v_lshlrev_b32_e32 v2, 1, v1 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v2 +; GISEL-NEXT: v_lshlrev_b32_e32 v3, 2, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v1 +; GISEL-NEXT: v_or_b32_e32 v2, v1, v2 +; GISEL-NEXT: v_or3_b32 v0, v0, v3, v4 +; GISEL-NEXT: v_lshlrev_b32_e32 v5, 4, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v3, v4 +; GISEL-NEXT: v_or3_b32 v0, v0, v5, v6 +; GISEL-NEXT: v_lshlrev_b32_e32 v7, 6, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v8, 7, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v5, v6 +; GISEL-NEXT: v_or3_b32 v0, v0, v7, v8 +; GISEL-NEXT: v_lshlrev_b32_e32 v9, 8, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v10, 9, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v7, v8 +; GISEL-NEXT: v_or3_b32 v0, v0, v9, v10 +; GISEL-NEXT: v_lshlrev_b32_e32 v11, 10, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v12, 11, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v9, v10 +; GISEL-NEXT: v_or3_b32 v0, v0, v11, v12 +; GISEL-NEXT: v_lshlrev_b32_e32 v13, 12, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v14, 13, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v11, v12 +; GISEL-NEXT: v_or3_b32 v0, v0, v13, v14 +; GISEL-NEXT: v_lshlrev_b32_e32 v15, 14, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v16, 15, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v13, v14 +; GISEL-NEXT: v_or3_b32 v0, v0, v15, v16 +; GISEL-NEXT: v_lshlrev_b32_e32 v17, 16, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v18, 17, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v15, v16 +; GISEL-NEXT: v_or3_b32 v0, v0, v17, v18 +; GISEL-NEXT: v_lshlrev_b32_e32 v19, 18, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v20, 19, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v17, v18 +; GISEL-NEXT: v_or3_b32 v0, v0, v19, v20 +; GISEL-NEXT: v_lshlrev_b32_e32 v3, 20, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v4, 21, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v19, v20 +; GISEL-NEXT: v_or3_b32 v0, v0, v3, v4 +; GISEL-NEXT: v_lshlrev_b32_e32 v5, 22, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v6, 23, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v3, v4 +; GISEL-NEXT: v_or3_b32 v0, v0, v5, v6 +; GISEL-NEXT: v_lshlrev_b32_e32 v7, 24, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v8, 25, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v5, v6 +; GISEL-NEXT: v_or3_b32 v0, v0, v7, v8 +; GISEL-NEXT: v_lshlrev_b32_e32 v9, 26, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v10, 27, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v7, v8 +; GISEL-NEXT: v_or3_b32 v0, v0, v9, v10 +; GISEL-NEXT: v_lshlrev_b32_e32 v11, 28, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v12, 29, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v9, v10 +; GISEL-NEXT: v_or3_b32 v0, v0, v11, v12 +; GISEL-NEXT: v_lshlrev_b32_e32 v13, 30, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v1, 31, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v11, v12 +; GISEL-NEXT: v_or3_b32 v0, v0, v13, v1 +; GISEL-NEXT: v_or3_b32 v1, v2, v13, v1 +; GISEL-NEXT: v_add_u32_e32 v3, 0x80000000, v1 +; GISEL-NEXT: v_mov_b32_e32 v2, v1 +; GISEL-NEXT: .LBB6_9: ; %Flow3 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: .LBB6_10: ; %fp-to-i-cleanup +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: s_setpc_b64 s[30:31] + %cvt = fptosi bfloat %x to i128 + ret i128 %cvt +} -; define i128 @fptoui_bf16_to_i128(bfloat %x) { -; %cvt = fptoui bfloat %x to i128 -; ret i128 %cvt -; } +define i128 @fptoui_bf16_to_i128(bfloat %x) { +; SDAG-LABEL: fptoui_bf16_to_i128: +; SDAG: ; %bb.0: ; %fp-to-i-entry +; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SDAG-NEXT: v_mov_b32_e32 v4, v0 +; SDAG-NEXT: v_bfe_u32 v5, v4, 7, 8 +; SDAG-NEXT: s_movk_i32 s4, 0x7e +; SDAG-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-NEXT: v_mov_b32_e32 v2, 0 +; SDAG-NEXT: v_mov_b32_e32 v6, 0 +; SDAG-NEXT: v_mov_b32_e32 v1, 0 +; SDAG-NEXT: v_mov_b32_e32 v3, 0 +; SDAG-NEXT: v_cmp_lt_u32_e32 vcc, s4, v5 +; SDAG-NEXT: s_and_saveexec_b64 s[8:9], vcc +; SDAG-NEXT: s_cbranch_execz .LBB7_10 +; SDAG-NEXT: ; %bb.1: ; %fp-to-i-if-end +; SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff01, v5 +; SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v6, vcc +; SDAG-NEXT: v_addc_co_u32_e32 v2, vcc, -1, v6, vcc +; SDAG-NEXT: s_movk_i32 s4, 0xff7f +; SDAG-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v6, vcc +; SDAG-NEXT: s_mov_b32 s5, -1 +; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[4:5], v[0:1] +; SDAG-NEXT: v_cmp_eq_u64_e64 s[6:7], -1, v[2:3] +; SDAG-NEXT: v_cmp_lt_i16_e32 vcc, -1, v4 +; SDAG-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5] +; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 +; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3 +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_xor_b64 s[10:11], exec, s[6:7] +; SDAG-NEXT: s_cbranch_execz .LBB7_7 +; SDAG-NEXT: ; %bb.2: ; %fp-to-i-if-end9 +; SDAG-NEXT: s_movk_i32 s4, 0x7f +; SDAG-NEXT: v_and_b32_sdwa v0, v4, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD +; SDAG-NEXT: s_mov_b64 s[4:5], 0x85 +; SDAG-NEXT: v_cmp_lt_u64_e64 s[4:5], s[4:5], v[5:6] +; SDAG-NEXT: v_mov_b32_e32 v7, 0 +; SDAG-NEXT: v_cndmask_b32_e64 v9, -1, 0, vcc +; SDAG-NEXT: v_cndmask_b32_e64 v8, -1, 1, vcc +; SDAG-NEXT: v_or_b32_e32 v6, 0x80, v0 +; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 +; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3 +; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] +; SDAG-NEXT: s_xor_b64 s[12:13], exec, s[6:7] +; SDAG-NEXT: s_cbranch_execz .LBB7_4 +; SDAG-NEXT: ; %bb.3: ; %fp-to-i-if-else +; SDAG-NEXT: v_sub_u32_e32 v0, 0xc6, v5 +; SDAG-NEXT: v_add_u32_e32 v2, 0xffffff3a, v5 +; SDAG-NEXT: v_add_u32_e32 v4, 0xffffff7a, v5 +; SDAG-NEXT: v_lshrrev_b64 v[0:1], v0, v[6:7] +; SDAG-NEXT: v_lshlrev_b64 v[2:3], v2, v[6:7] +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v4 +; SDAG-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] +; SDAG-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v4 +; SDAG-NEXT: v_cndmask_b32_e64 v3, 0, v1, s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v2, v2, v0, s[4:5] +; SDAG-NEXT: v_lshlrev_b64 v[0:1], v4, v[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[6:7] +; SDAG-NEXT: v_cndmask_b32_e64 v12, 0, v0, s[4:5] +; SDAG-NEXT: v_cndmask_b32_e64 v11, 0, v1, s[4:5] +; SDAG-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v12, v8, 0 +; SDAG-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc +; SDAG-NEXT: v_mul_lo_u32 v13, v9, v2 +; SDAG-NEXT: v_mov_b32_e32 v6, v1 +; SDAG-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v11, v8, v[6:7] +; SDAG-NEXT: v_mul_lo_u32 v14, v8, v3 +; SDAG-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v8, v2, 0 +; SDAG-NEXT: v_add_co_u32_e64 v6, s[4:5], -1, v10 +; SDAG-NEXT: v_mov_b32_e32 v10, v5 +; SDAG-NEXT: v_mov_b32_e32 v5, v7 +; SDAG-NEXT: v_addc_co_u32_e64 v8, s[4:5], 0, -1, s[4:5] +; SDAG-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v12, v9, v[4:5] +; SDAG-NEXT: v_add3_u32 v3, v3, v14, v13 +; SDAG-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v6, v12, v[2:3] +; SDAG-NEXT: v_add_co_u32_e64 v5, s[4:5], v10, v5 +; SDAG-NEXT: v_mul_lo_u32 v3, v6, v11 +; SDAG-NEXT: v_addc_co_u32_e64 v6, s[4:5], 0, 0, s[4:5] +; SDAG-NEXT: v_mul_lo_u32 v7, v8, v12 +; SDAG-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v11, v9, v[5:6] +; SDAG-NEXT: ; implicit-def: $vgpr8 +; SDAG-NEXT: v_add3_u32 v3, v7, v2, v3 +; SDAG-NEXT: v_add_co_u32_e64 v2, s[4:5], v5, v1 +; SDAG-NEXT: v_addc_co_u32_e64 v3, s[4:5], v6, v3, s[4:5] +; SDAG-NEXT: ; implicit-def: $vgpr5_vgpr6 +; SDAG-NEXT: v_mov_b32_e32 v1, v4 +; SDAG-NEXT: ; implicit-def: $vgpr6_vgpr7 +; SDAG-NEXT: .LBB7_4: ; %Flow +; SDAG-NEXT: s_andn2_saveexec_b64 s[6:7], s[12:13] +; SDAG-NEXT: ; %bb.5: ; %fp-to-i-if-then12 +; SDAG-NEXT: v_sub_u32_e32 v2, 0x86, v5 +; SDAG-NEXT: v_lshrrev_b64 v[0:1], v2, v[6:7] +; SDAG-NEXT: v_cmp_gt_u32_e64 s[4:5], 64, v2 +; SDAG-NEXT: v_cndmask_b32_e64 v0, 0, v0, s[4:5] +; SDAG-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2 +; SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[4:5] +; SDAG-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v8 +; SDAG-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; SDAG-NEXT: v_mul_i32_i24_e32 v0, v0, v8 +; SDAG-NEXT: v_mov_b32_e32 v3, v2 +; SDAG-NEXT: ; %bb.6: ; %Flow1 +; SDAG-NEXT: s_or_b64 exec, exec, s[6:7] +; SDAG-NEXT: .LBB7_7: ; %Flow2 +; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11] +; SDAG-NEXT: ; %bb.8: ; %fp-to-i-if-then5 +; SDAG-NEXT: v_bfrev_b32_e32 v0, 1 +; SDAG-NEXT: v_bfrev_b32_e32 v1, -2 +; SDAG-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; SDAG-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; SDAG-NEXT: v_mov_b32_e32 v0, v2 +; SDAG-NEXT: v_mov_b32_e32 v1, v2 +; SDAG-NEXT: ; %bb.9: ; %Flow3 +; SDAG-NEXT: s_or_b64 exec, exec, s[4:5] +; SDAG-NEXT: .LBB7_10: ; %fp-to-i-cleanup +; SDAG-NEXT: s_or_b64 exec, exec, s[8:9] +; SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GISEL-LABEL: fptoui_bf16_to_i128: +; GISEL: ; %bb.0: ; %fp-to-i-entry +; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GISEL-NEXT: v_mov_b32_e32 v4, v0 +; GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v4 +; GISEL-NEXT: v_mov_b32_e32 v6, 0 +; GISEL-NEXT: v_lshrrev_b64 v[0:1], 7, v[5:6] +; GISEL-NEXT: v_mov_b32_e32 v1, 0x7f +; GISEL-NEXT: s_mov_b64 s[4:5], 0 +; GISEL-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-NEXT: v_bfe_u32 v5, v0, 0, 8 +; GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[5:6], v[1:2] +; GISEL-NEXT: s_mov_b64 s[6:7], s[4:5] +; GISEL-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-NEXT: v_mov_b32_e32 v2, s6 +; GISEL-NEXT: v_mov_b32_e32 v3, s7 +; GISEL-NEXT: s_and_saveexec_b64 s[12:13], vcc +; GISEL-NEXT: s_cbranch_execz .LBB7_10 +; GISEL-NEXT: ; %bb.1: ; %fp-to-i-if-end +; GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff01, v5 +; GISEL-NEXT: v_mov_b32_e32 v2, 0xffffff80 +; GISEL-NEXT: v_addc_co_u32_e64 v1, s[6:7], 0, -1, vcc +; GISEL-NEXT: v_mov_b32_e32 v3, -1 +; GISEL-NEXT: v_addc_co_u32_e64 v7, s[6:7], 0, -1, s[6:7] +; GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[0:1], v[2:3] +; GISEL-NEXT: v_addc_co_u32_e64 v8, s[6:7], 0, -1, s[6:7] +; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GISEL-NEXT: v_cmp_le_u64_e32 vcc, -1, v[7:8] +; GISEL-NEXT: v_cmp_lt_i16_e64 s[4:5], -1, v4 +; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc +; GISEL-NEXT: v_cmp_eq_u64_e32 vcc, -1, v[7:8] +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_and_b32_e32 v0, 1, v0 +; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GISEL-NEXT: s_xor_b64 s[14:15], exec, s[6:7] +; GISEL-NEXT: s_cbranch_execz .LBB7_7 +; GISEL-NEXT: ; %bb.2: ; %fp-to-i-if-end9 +; GISEL-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[6:7] +; GISEL-NEXT: v_and_b32_e32 v0, 1, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v2, 1, v0 +; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[6:7] +; GISEL-NEXT: v_lshlrev_b16_e32 v3, 2, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v7, 3, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v8, 4, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v9, 5, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v10, 6, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v11, 7, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v12, 8, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v13, 9, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v14, 10, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v15, 11, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v16, 12, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v17, 13, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v18, 14, v0 +; GISEL-NEXT: v_lshlrev_b16_e32 v19, 15, v0 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v2 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v2 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v3 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v3 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v7 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v7 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v8 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v8 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v9 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v9 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v10 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v10 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v11 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v11 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v12 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v12 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v13 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v13 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v14 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v14 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v15 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v15 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v16 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v16 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v17 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v17 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v18 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v18 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v19 +; GISEL-NEXT: v_or_b32_e32 v1, v1, v19 +; GISEL-NEXT: v_and_b32_e32 v11, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v11 +; GISEL-NEXT: v_or3_b32 v9, v1, v0, 1 +; GISEL-NEXT: v_or3_b32 v10, v11, v0, 0 +; GISEL-NEXT: v_mov_b32_e32 v0, 0x86 +; GISEL-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-NEXT: v_and_b32_e32 v2, 0x7f, v4 +; GISEL-NEXT: v_cmp_ge_u64_e32 vcc, v[5:6], v[0:1] +; GISEL-NEXT: v_or_b32_e32 v7, 0x80, v2 +; GISEL-NEXT: v_mov_b32_e32 v8, 0 +; GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3 +; GISEL-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GISEL-NEXT: s_xor_b64 s[16:17], exec, s[6:7] +; GISEL-NEXT: s_cbranch_execz .LBB7_4 +; GISEL-NEXT: ; %bb.3: ; %fp-to-i-if-else +; GISEL-NEXT: v_add_u32_e32 v6, 0xffffff7a, v5 +; GISEL-NEXT: v_lshlrev_b64 v[0:1], v6, v[7:8] +; GISEL-NEXT: v_subrev_u32_e32 v4, 64, v6 +; GISEL-NEXT: v_sub_u32_e32 v2, 64, v6 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v6 +; GISEL-NEXT: v_lshl_or_b32 v11, v11, 16, v11 +; GISEL-NEXT: v_lshrrev_b64 v[2:3], v2, v[7:8] +; GISEL-NEXT: v_lshlrev_b64 v[4:5], v4, v[7:8] +; GISEL-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc +; GISEL-NEXT: v_cndmask_b32_e32 v12, 0, v1, vcc +; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v8, v11, 0 +; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6 +; GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v12, v10, v[0:1] +; GISEL-NEXT: v_cndmask_b32_e64 v13, v2, 0, s[6:7] +; GISEL-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v8, v9, 0 +; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v9, v[6:7] +; GISEL-NEXT: v_mul_lo_u32 v4, v12, v11 +; GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GISEL-NEXT: v_mov_b32_e32 v2, v6 +; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v8, v10, v[1:2] +; GISEL-NEXT: v_mul_lo_u32 v6, v8, v11 +; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[6:7] +; GISEL-NEXT: v_mad_u64_u32 v[1:2], s[10:11], v12, v9, v[1:2] +; GISEL-NEXT: v_addc_co_u32_e64 v6, s[10:11], v7, v6, s[10:11] +; GISEL-NEXT: v_addc_co_u32_e64 v4, s[8:9], v6, v4, s[8:9] +; GISEL-NEXT: v_mad_u64_u32 v[6:7], s[8:9], v13, v10, v[4:5] +; GISEL-NEXT: ; implicit-def: $vgpr5 +; GISEL-NEXT: v_mad_u64_u32 v[3:4], s[6:7], v3, v9, v[6:7] +; GISEL-NEXT: ; implicit-def: $vgpr7_vgpr8 +; GISEL-NEXT: ; implicit-def: $vgpr9 +; GISEL-NEXT: .LBB7_4: ; %Flow +; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[16:17] +; GISEL-NEXT: s_cbranch_execz .LBB7_6 +; GISEL-NEXT: ; %bb.5: ; %fp-to-i-if-then12 +; GISEL-NEXT: v_sub_co_u32_e32 v3, vcc, 0x86, v5 +; GISEL-NEXT: v_subrev_u32_e32 v2, 64, v3 +; GISEL-NEXT: v_lshrrev_b64 v[0:1], v3, v[7:8] +; GISEL-NEXT: v_lshrrev_b64 v[1:2], v2, 0 +; GISEL-NEXT: v_cmp_gt_u32_e32 vcc, 64, v3 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc +; GISEL-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v9 +; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; GISEL-NEXT: v_mul_i32_i24_e32 v0, v0, v9 +; GISEL-NEXT: v_mov_b32_e32 v3, v2 +; GISEL-NEXT: .LBB7_6: ; %Flow1 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: .LBB7_7: ; %Flow2 +; GISEL-NEXT: s_andn2_saveexec_b64 s[6:7], s[14:15] +; GISEL-NEXT: s_cbranch_execz .LBB7_9 +; GISEL-NEXT: ; %bb.8: ; %fp-to-i-if-then5 +; GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5] +; GISEL-NEXT: v_and_b32_e32 v1, 1, v1 +; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GISEL-NEXT: v_lshlrev_b32_e32 v2, 1, v1 +; GISEL-NEXT: v_or_b32_e32 v0, v0, v2 +; GISEL-NEXT: v_lshlrev_b32_e32 v3, 2, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v1 +; GISEL-NEXT: v_or_b32_e32 v2, v1, v2 +; GISEL-NEXT: v_or3_b32 v0, v0, v3, v4 +; GISEL-NEXT: v_lshlrev_b32_e32 v5, 4, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v6, 5, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v3, v4 +; GISEL-NEXT: v_or3_b32 v0, v0, v5, v6 +; GISEL-NEXT: v_lshlrev_b32_e32 v7, 6, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v8, 7, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v5, v6 +; GISEL-NEXT: v_or3_b32 v0, v0, v7, v8 +; GISEL-NEXT: v_lshlrev_b32_e32 v9, 8, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v10, 9, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v7, v8 +; GISEL-NEXT: v_or3_b32 v0, v0, v9, v10 +; GISEL-NEXT: v_lshlrev_b32_e32 v11, 10, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v12, 11, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v9, v10 +; GISEL-NEXT: v_or3_b32 v0, v0, v11, v12 +; GISEL-NEXT: v_lshlrev_b32_e32 v13, 12, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v14, 13, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v11, v12 +; GISEL-NEXT: v_or3_b32 v0, v0, v13, v14 +; GISEL-NEXT: v_lshlrev_b32_e32 v15, 14, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v16, 15, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v13, v14 +; GISEL-NEXT: v_or3_b32 v0, v0, v15, v16 +; GISEL-NEXT: v_lshlrev_b32_e32 v17, 16, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v18, 17, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v15, v16 +; GISEL-NEXT: v_or3_b32 v0, v0, v17, v18 +; GISEL-NEXT: v_lshlrev_b32_e32 v19, 18, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v20, 19, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v17, v18 +; GISEL-NEXT: v_or3_b32 v0, v0, v19, v20 +; GISEL-NEXT: v_lshlrev_b32_e32 v3, 20, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v4, 21, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v19, v20 +; GISEL-NEXT: v_or3_b32 v0, v0, v3, v4 +; GISEL-NEXT: v_lshlrev_b32_e32 v5, 22, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v6, 23, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v3, v4 +; GISEL-NEXT: v_or3_b32 v0, v0, v5, v6 +; GISEL-NEXT: v_lshlrev_b32_e32 v7, 24, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v8, 25, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v5, v6 +; GISEL-NEXT: v_or3_b32 v0, v0, v7, v8 +; GISEL-NEXT: v_lshlrev_b32_e32 v9, 26, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v10, 27, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v7, v8 +; GISEL-NEXT: v_or3_b32 v0, v0, v9, v10 +; GISEL-NEXT: v_lshlrev_b32_e32 v11, 28, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v12, 29, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v9, v10 +; GISEL-NEXT: v_or3_b32 v0, v0, v11, v12 +; GISEL-NEXT: v_lshlrev_b32_e32 v13, 30, v1 +; GISEL-NEXT: v_lshlrev_b32_e32 v1, 31, v1 +; GISEL-NEXT: v_or3_b32 v2, v2, v11, v12 +; GISEL-NEXT: v_or3_b32 v0, v0, v13, v1 +; GISEL-NEXT: v_or3_b32 v1, v2, v13, v1 +; GISEL-NEXT: v_add_u32_e32 v3, 0x80000000, v1 +; GISEL-NEXT: v_mov_b32_e32 v2, v1 +; GISEL-NEXT: .LBB7_9: ; %Flow3 +; GISEL-NEXT: s_or_b64 exec, exec, s[6:7] +; GISEL-NEXT: .LBB7_10: ; %fp-to-i-cleanup +; GISEL-NEXT: s_or_b64 exec, exec, s[12:13] +; GISEL-NEXT: s_setpc_b64 s[30:31] + %cvt = fptoui bfloat %x to i128 + ret i128 %cvt +} diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll new file mode 100644 index 000000000000..f950717c591a --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.bf.ll @@ -0,0 +1,275 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,SDAG %s +; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s 2>&1 | FileCheck -check-prefix=GISEL %s + +; FIXME: GISEL can't handle the "fptrunc float to bfloat" that expand-large-fp-convert emits. + +; GISEL: unable to translate instruction: fptrunc + +define bfloat @sitofp_i128_to_bf16(i128 %x) { +; GCN-LABEL: sitofp_i128_to_bf16: +; GCN: ; %bb.0: ; %itofp-entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_or_b32_e32 v5, v1, v3 +; GCN-NEXT: v_or_b32_e32 v4, v0, v2 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GCN-NEXT: s_cbranch_execz .LBB0_14 +; GCN-NEXT: ; %bb.1: ; %itofp-if-end +; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v3 +; GCN-NEXT: v_xor_b32_e32 v0, v5, v0 +; GCN-NEXT: v_xor_b32_e32 v1, v5, v1 +; GCN-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v5 +; GCN-NEXT: v_xor_b32_e32 v2, v5, v2 +; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc +; GCN-NEXT: v_xor_b32_e32 v6, v5, v3 +; GCN-NEXT: v_subb_co_u32_e32 v4, vcc, v2, v5, vcc +; GCN-NEXT: v_subb_co_u32_e32 v5, vcc, v6, v5, vcc +; GCN-NEXT: v_ffbh_u32_e32 v2, v4 +; GCN-NEXT: v_add_u32_e32 v2, 32, v2 +; GCN-NEXT: v_ffbh_u32_e32 v6, v5 +; GCN-NEXT: v_min_u32_e32 v2, v2, v6 +; GCN-NEXT: v_ffbh_u32_e32 v6, v0 +; GCN-NEXT: v_add_u32_e32 v6, 32, v6 +; GCN-NEXT: v_ffbh_u32_e32 v7, v1 +; GCN-NEXT: v_min_u32_e32 v6, v6, v7 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GCN-NEXT: v_add_u32_e32 v6, 64, v6 +; GCN-NEXT: v_cndmask_b32_e32 v7, v6, v2, vcc +; GCN-NEXT: v_sub_u32_e32 v6, 0x80, v7 +; GCN-NEXT: v_sub_u32_e32 v2, 0x7f, v7 +; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 25, v6 +; GCN-NEXT: ; implicit-def: $vgpr8 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: ; %bb.2: ; %itofp-if-else +; GCN-NEXT: v_add_u32_e32 v4, 0xffffff98, v7 +; GCN-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1] +; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v4 +; GCN-NEXT: v_cndmask_b32_e32 v8, 0, v0, vcc +; GCN-NEXT: ; implicit-def: $vgpr6 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GCN-NEXT: ; implicit-def: $vgpr7 +; GCN-NEXT: ; implicit-def: $vgpr4_vgpr5 +; GCN-NEXT: ; %bb.3: ; %Flow3 +; GCN-NEXT: s_andn2_saveexec_b64 s[8:9], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB0_13 +; GCN-NEXT: ; %bb.4: ; %NodeBlock +; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 25, v6 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[10:11], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB0_8 +; GCN-NEXT: ; %bb.5: ; %LeafBlock +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 26, v6 +; GCN-NEXT: s_and_saveexec_b64 s[12:13], vcc +; GCN-NEXT: s_cbranch_execz .LBB0_7 +; GCN-NEXT: ; %bb.6: ; %itofp-sw-default +; GCN-NEXT: v_sub_u32_e32 v12, 0x66, v7 +; GCN-NEXT: v_sub_u32_e32 v10, 64, v12 +; GCN-NEXT: v_lshrrev_b64 v[8:9], v12, v[0:1] +; GCN-NEXT: v_lshlrev_b64 v[10:11], v10, v[4:5] +; GCN-NEXT: v_sub_u32_e32 v13, 38, v7 +; GCN-NEXT: v_or_b32_e32 v11, v9, v11 +; GCN-NEXT: v_or_b32_e32 v10, v8, v10 +; GCN-NEXT: v_lshrrev_b64 v[8:9], v13, v[4:5] +; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v12 +; GCN-NEXT: v_add_u32_e32 v14, 26, v7 +; GCN-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v12 +; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; GCN-NEXT: v_lshrrev_b64 v[10:11], v13, v[0:1] +; GCN-NEXT: v_lshlrev_b64 v[12:13], v14, v[4:5] +; GCN-NEXT: v_subrev_u32_e32 v7, 38, v7 +; GCN-NEXT: v_cndmask_b32_e64 v15, v8, v0, s[4:5] +; GCN-NEXT: v_lshlrev_b64 v[7:8], v7, v[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v1, s[4:5] +; GCN-NEXT: v_or_b32_e32 v11, v13, v11 +; GCN-NEXT: v_or_b32_e32 v10, v12, v10 +; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v14 +; GCN-NEXT: v_lshlrev_b64 v[0:1], v14, v[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v14 +; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc +; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-NEXT: v_or_b32_e32 v1, v1, v5 +; GCN-NEXT: v_or_b32_e32 v0, v0, v4 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GCN-NEXT: v_or_b32_e32 v8, v15, v0 +; GCN-NEXT: v_mov_b32_e32 v0, v8 +; GCN-NEXT: v_mov_b32_e32 v1, v9 +; GCN-NEXT: .LBB0_7: ; %Flow1 +; GCN-NEXT: s_or_b64 exec, exec, s[12:13] +; GCN-NEXT: .LBB0_8: ; %Flow2 +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11] +; GCN-NEXT: ; %bb.9: ; %itofp-sw-bb +; GCN-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] +; GCN-NEXT: ; %bb.10: ; %itofp-sw-epilog +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_lshrrev_b32_e32 v4, 2, v0 +; GCN-NEXT: v_and_or_b32 v0, v4, 1, v0 +; GCN-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_and_b32_e32 v4, 0x4000000, v0 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GCN-NEXT: v_alignbit_b32 v8, v1, v0, 2 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: ; %bb.11: ; %itofp-if-then20 +; GCN-NEXT: v_alignbit_b32 v8, v1, v0, 3 +; GCN-NEXT: v_mov_b32_e32 v2, v6 +; GCN-NEXT: ; %bb.12: ; %Flow +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: .LBB0_13: ; %Flow4 +; GCN-NEXT: s_or_b64 exec, exec, s[8:9] +; GCN-NEXT: v_and_b32_e32 v0, 0x80000000, v3 +; GCN-NEXT: v_lshl_add_u32 v1, v2, 23, 1.0 +; GCN-NEXT: v_and_b32_e32 v2, 0x7fffff, v8 +; GCN-NEXT: v_or3_b32 v0, v2, v0, v1 +; GCN-NEXT: v_bfe_u32 v1, v8, 16, 1 +; GCN-NEXT: s_movk_i32 s4, 0x7fff +; GCN-NEXT: v_add3_u32 v1, v1, v0, s4 +; GCN-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GCN-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v0 +; GCN-NEXT: .LBB0_14: ; %Flow5 +; GCN-NEXT: s_or_b64 exec, exec, s[6:7] +; GCN-NEXT: v_mov_b32_e32 v0, v4 +; GCN-NEXT: s_setpc_b64 s[30:31] + %cvt = sitofp i128 %x to bfloat + ret bfloat %cvt +} + +define bfloat @uitofp_i128_to_bf16(i128 %x) { +; GCN-LABEL: uitofp_i128_to_bf16: +; GCN: ; %bb.0: ; %itofp-entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_or_b32_e32 v5, v1, v3 +; GCN-NEXT: v_or_b32_e32 v4, v0, v2 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GCN-NEXT: s_cbranch_execz .LBB1_14 +; GCN-NEXT: ; %bb.1: ; %itofp-if-end +; GCN-NEXT: v_ffbh_u32_e32 v4, v2 +; GCN-NEXT: v_add_u32_e32 v4, 32, v4 +; GCN-NEXT: v_ffbh_u32_e32 v5, v3 +; GCN-NEXT: v_min_u32_e32 v4, v4, v5 +; GCN-NEXT: v_ffbh_u32_e32 v5, v0 +; GCN-NEXT: v_add_u32_e32 v5, 32, v5 +; GCN-NEXT: v_ffbh_u32_e32 v6, v1 +; GCN-NEXT: v_min_u32_e32 v5, v5, v6 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[2:3] +; GCN-NEXT: v_add_u32_e32 v5, 64, v5 +; GCN-NEXT: v_cndmask_b32_e32 v6, v5, v4, vcc +; GCN-NEXT: v_sub_u32_e32 v5, 0x80, v6 +; GCN-NEXT: v_sub_u32_e32 v4, 0x7f, v6 +; GCN-NEXT: v_cmp_gt_i32_e32 vcc, 25, v5 +; GCN-NEXT: ; implicit-def: $vgpr7 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[4:5], exec, s[4:5] +; GCN-NEXT: ; %bb.2: ; %itofp-if-else +; GCN-NEXT: v_add_u32_e32 v2, 0xffffff98, v6 +; GCN-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1] +; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v2 +; GCN-NEXT: v_cndmask_b32_e32 v7, 0, v0, vcc +; GCN-NEXT: ; implicit-def: $vgpr5 +; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GCN-NEXT: ; implicit-def: $vgpr6 +; GCN-NEXT: ; implicit-def: $vgpr2_vgpr3 +; GCN-NEXT: ; %bb.3: ; %Flow3 +; GCN-NEXT: s_andn2_saveexec_b64 s[8:9], s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB1_13 +; GCN-NEXT: ; %bb.4: ; %NodeBlock +; GCN-NEXT: v_cmp_lt_i32_e32 vcc, 25, v5 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: s_xor_b64 s[10:11], exec, s[4:5] +; GCN-NEXT: s_cbranch_execz .LBB1_8 +; GCN-NEXT: ; %bb.5: ; %LeafBlock +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 26, v5 +; GCN-NEXT: s_and_saveexec_b64 s[12:13], vcc +; GCN-NEXT: s_cbranch_execz .LBB1_7 +; GCN-NEXT: ; %bb.6: ; %itofp-sw-default +; GCN-NEXT: v_sub_u32_e32 v11, 0x66, v6 +; GCN-NEXT: v_sub_u32_e32 v9, 64, v11 +; GCN-NEXT: v_lshrrev_b64 v[7:8], v11, v[0:1] +; GCN-NEXT: v_lshlrev_b64 v[9:10], v9, v[2:3] +; GCN-NEXT: v_sub_u32_e32 v12, 38, v6 +; GCN-NEXT: v_or_b32_e32 v10, v8, v10 +; GCN-NEXT: v_or_b32_e32 v9, v7, v9 +; GCN-NEXT: v_lshrrev_b64 v[7:8], v12, v[2:3] +; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v11 +; GCN-NEXT: v_add_u32_e32 v13, 26, v6 +; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11 +; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc +; GCN-NEXT: v_lshrrev_b64 v[9:10], v12, v[0:1] +; GCN-NEXT: v_lshlrev_b64 v[11:12], v13, v[2:3] +; GCN-NEXT: v_subrev_u32_e32 v6, 38, v6 +; GCN-NEXT: v_cndmask_b32_e64 v14, v7, v0, s[4:5] +; GCN-NEXT: v_lshlrev_b64 v[6:7], v6, v[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[4:5] +; GCN-NEXT: v_or_b32_e32 v10, v12, v10 +; GCN-NEXT: v_or_b32_e32 v9, v11, v9 +; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 64, v13 +; GCN-NEXT: v_lshlrev_b64 v[0:1], v13, v[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v13 +; GCN-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc +; GCN-NEXT: v_or_b32_e32 v7, v14, v0 +; GCN-NEXT: v_mov_b32_e32 v0, v7 +; GCN-NEXT: v_mov_b32_e32 v1, v8 +; GCN-NEXT: .LBB1_7: ; %Flow1 +; GCN-NEXT: s_or_b64 exec, exec, s[12:13] +; GCN-NEXT: .LBB1_8: ; %Flow2 +; GCN-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11] +; GCN-NEXT: ; %bb.9: ; %itofp-sw-bb +; GCN-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1] +; GCN-NEXT: ; %bb.10: ; %itofp-sw-epilog +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: v_lshrrev_b32_e32 v2, 2, v0 +; GCN-NEXT: v_and_or_b32 v0, v2, 1, v0 +; GCN-NEXT: v_add_co_u32_e32 v0, vcc, 1, v0 +; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_and_b32_e32 v2, 0x4000000, v0 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_alignbit_b32 v7, v1, v0, 2 +; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GCN-NEXT: ; %bb.11: ; %itofp-if-then20 +; GCN-NEXT: v_alignbit_b32 v7, v1, v0, 3 +; GCN-NEXT: v_mov_b32_e32 v4, v5 +; GCN-NEXT: ; %bb.12: ; %Flow +; GCN-NEXT: s_or_b64 exec, exec, s[4:5] +; GCN-NEXT: .LBB1_13: ; %Flow4 +; GCN-NEXT: s_or_b64 exec, exec, s[8:9] +; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v7 +; GCN-NEXT: v_lshl_or_b32 v0, v4, 23, v0 +; GCN-NEXT: v_add_u32_e32 v0, 1.0, v0 +; GCN-NEXT: v_bfe_u32 v1, v0, 16, 1 +; GCN-NEXT: s_movk_i32 s4, 0x7fff +; GCN-NEXT: v_add3_u32 v1, v1, v0, s4 +; GCN-NEXT: v_or_b32_e32 v2, 0x400000, v0 +; GCN-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc +; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v0 +; GCN-NEXT: .LBB1_14: ; %Flow5 +; GCN-NEXT: s_or_b64 exec, exec, s[6:7] +; GCN-NEXT: v_mov_b32_e32 v0, v4 +; GCN-NEXT: s_setpc_b64 s[30:31] + %cvt = uitofp i128 %x to bfloat + ret bfloat %cvt +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll index bfeb214c5af8..c6aa2182aec8 100644 --- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll +++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll @@ -1604,15 +1604,5 @@ define half @uitofp_i128_to_f16(i128 %x) { ret half %cvt } -; FIXME: ExpandLargeFpConvert asserts on bfloat -; define bfloat @sitofp_i128_to_bf16(i128 %x) { -; %cvt = sitofp i128 %x to bfloat -; ret bfloat %cvt -; } - -; define bfloat @uitofp_i128_to_bf16(i128 %x) { -; %cvt = uitofp i128 %x to bfloat -; ret bfloat %cvt -; } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN: {{.*}} -- GitLab From 2084a07087a55b55bb3c2a8aafbe1c4464fdf796 Mon Sep 17 00:00:00 2001 From: Saiyedul Islam Date: Mon, 8 Apr 2024 03:35:23 -0400 Subject: [PATCH 118/695] Revert "[compiler-rt] Allow running tests without installing first" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit c91254db1dcace869f4d3f1ac659bdd7700a1459. It was throwing error: g++: error: unrecognized command line option ‘-resource-dir= --- compiler-rt/CMakeLists.txt | 23 ----- compiler-rt/cmake/Modules/AddCompilerRT.cmake | 1 - compiler-rt/test/CMakeLists.txt | 8 ++ compiler-rt/test/fuzzer/lit.cfg.py | 1 - compiler-rt/test/lit.common.cfg.py | 86 +++++-------------- compiler-rt/test/lit.common.configured.in | 1 - compiler-rt/test/safestack/lit.cfg.py | 10 +-- 7 files changed, 32 insertions(+), 98 deletions(-) diff --git a/compiler-rt/CMakeLists.txt b/compiler-rt/CMakeLists.txt index 8649507ce1c7..f4e92f14db85 100644 --- a/compiler-rt/CMakeLists.txt +++ b/compiler-rt/CMakeLists.txt @@ -584,29 +584,6 @@ string(APPEND COMPILER_RT_TEST_COMPILER_CFLAGS " ${stdlib_flag}") string(REPLACE " " ";" COMPILER_RT_UNITTEST_CFLAGS "${COMPILER_RT_TEST_COMPILER_CFLAGS}") set(COMPILER_RT_UNITTEST_LINK_FLAGS ${COMPILER_RT_UNITTEST_CFLAGS}) -option(COMPILER_RT_TEST_STANDALONE_BUILD_LIBS - "When set to ON and testing in a standalone build, test the runtime \ - libraries built by this standalone build rather than the runtime libraries \ - shipped with the compiler (used for testing). When set to OFF and testing \ - in a standalone build, test the runtime libraries shipped with the compiler \ - (used for testing). This option has no effect if the compiler and this \ - build are configured to use the same runtime library path." - ON) -if (COMPILER_RT_TEST_STANDALONE_BUILD_LIBS) - # Ensure that the unit tests can find the sanitizer headers prior to installation. - list(APPEND COMPILER_RT_UNITTEST_CFLAGS "-I${CMAKE_CURRENT_LIST_DIR}/include") - # Ensure that unit tests link against the just-built runtime libraries instead - # of the ones bundled with the compiler by overriding the resource directory. - # - if ("${COMPILER_RT_TEST_COMPILER_ID}" MATCHES "Clang") - list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-resource-dir=${COMPILER_RT_OUTPUT_DIR}") - endif() - get_compiler_rt_output_dir(${COMPILER_RT_DEFAULT_TARGET_ARCH} rtlib_dir) - if (NOT WIN32) - list(APPEND COMPILER_RT_UNITTEST_LINK_FLAGS "-Wl,-rpath,${rtlib_dir}") - endif() -endif() - if(COMPILER_RT_USE_LLVM_UNWINDER) # We're linking directly against the libunwind that we're building so don't # try to link in the toolchain's default libunwind which may be missing. diff --git a/compiler-rt/cmake/Modules/AddCompilerRT.cmake b/compiler-rt/cmake/Modules/AddCompilerRT.cmake index 567b123b7abc..e0400a8ea952 100644 --- a/compiler-rt/cmake/Modules/AddCompilerRT.cmake +++ b/compiler-rt/cmake/Modules/AddCompilerRT.cmake @@ -768,7 +768,6 @@ function(configure_compiler_rt_lit_site_cfg input output) get_compiler_rt_output_dir(${COMPILER_RT_DEFAULT_TARGET_ARCH} output_dir) string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} COMPILER_RT_RESOLVED_TEST_COMPILER ${COMPILER_RT_TEST_COMPILER}) - string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} COMPILER_RT_RESOLVED_OUTPUT_DIR ${COMPILER_RT_OUTPUT_DIR}) string(REPLACE ${CMAKE_CFG_INTDIR} ${LLVM_BUILD_MODE} COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR ${output_dir}) configure_lit_site_cfg(${input} ${output}) diff --git a/compiler-rt/test/CMakeLists.txt b/compiler-rt/test/CMakeLists.txt index edc007aaf477..c186be1e44fd 100644 --- a/compiler-rt/test/CMakeLists.txt +++ b/compiler-rt/test/CMakeLists.txt @@ -1,6 +1,14 @@ # Needed for lit support in standalone builds. include(AddLLVM) +option(COMPILER_RT_TEST_STANDALONE_BUILD_LIBS + "When set to ON and testing in a standalone build, test the runtime \ + libraries built by this standalone build rather than the runtime libraries \ + shipped with the compiler (used for testing). When set to OFF and testing \ + in a standalone build, test the runtime libraries shipped with the compiler \ + (used for testing). This option has no effect if the compiler and this \ + build are configured to use the same runtime library path." + ON) pythonize_bool(COMPILER_RT_TEST_STANDALONE_BUILD_LIBS) pythonize_bool(LLVM_ENABLE_EXPENSIVE_CHECKS) diff --git a/compiler-rt/test/fuzzer/lit.cfg.py b/compiler-rt/test/fuzzer/lit.cfg.py index 0c0550ac729d..9084254b3b15 100644 --- a/compiler-rt/test/fuzzer/lit.cfg.py +++ b/compiler-rt/test/fuzzer/lit.cfg.py @@ -106,7 +106,6 @@ def generate_compiler_cmd(is_cpp=True, fuzzer_enabled=True, msan_enabled=False): return " ".join( [ compiler_cmd, - config.target_cflags, std_cmd, "-O2 -gline-tables-only", sanitizers_cmd, diff --git a/compiler-rt/test/lit.common.cfg.py b/compiler-rt/test/lit.common.cfg.py index ca9ce130dd51..0ac20a9831d9 100644 --- a/compiler-rt/test/lit.common.cfg.py +++ b/compiler-rt/test/lit.common.cfg.py @@ -14,27 +14,6 @@ import lit.formats import lit.util -def get_path_from_clang(args, allow_failure): - clang_cmd = [ - config.clang.strip(), - f"--target={config.target_triple}", - *args, - ] - path = None - try: - result = subprocess.run( - clang_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=True - ) - path = result.stdout.decode().strip() - except subprocess.CalledProcessError as e: - msg = f"Failed to run {clang_cmd}\nrc:{e.returncode}\nstdout:{e.stdout}\ne.stderr{e.stderr}" - if allow_failure: - lit_config.warning(msg) - else: - lit_config.fatal(msg) - return path, clang_cmd - - def find_compiler_libdir(): """ Returns the path to library resource directory used @@ -47,6 +26,26 @@ def find_compiler_libdir(): # TODO: Support other compilers. return None + def get_path_from_clang(args, allow_failure): + clang_cmd = [ + config.clang.strip(), + f"--target={config.target_triple}", + ] + clang_cmd.extend(args) + path = None + try: + result = subprocess.run( + clang_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE, check=True + ) + path = result.stdout.decode().strip() + except subprocess.CalledProcessError as e: + msg = f"Failed to run {clang_cmd}\nrc:{e.returncode}\nstdout:{e.stdout}\ne.stderr{e.stderr}" + if allow_failure: + lit_config.warning(msg) + else: + lit_config.fatal(msg) + return path, clang_cmd + # Try using `-print-runtime-dir`. This is only supported by very new versions of Clang. # so allow failure here. runtime_dir, clang_cmd = get_path_from_clang( @@ -169,51 +168,10 @@ if config.enable_per_target_runtime_dir: r"/i386(?=-[^/]+$)", "/x86_64", config.compiler_rt_libdir ) - -# Check if the test compiler resource dir matches the local build directory -# (which happens with -DLLVM_ENABLE_PROJECTS=clang;compiler-rt) or if we are -# using an installed clang to test compiler-rt standalone. In the latter case -# we may need to override the resource dir to match the path of the just-built -# compiler-rt libraries. -test_cc_resource_dir, _ = get_path_from_clang( - shlex.split(config.target_cflags) + ["-print-resource-dir"], allow_failure=True -) -# Normalize the path for comparison -if test_cc_resource_dir is not None: - test_cc_resource_dir = os.path.realpath(test_cc_resource_dir) -if lit_config.debug: - lit_config.note(f"Resource dir for {config.clang} is {test_cc_resource_dir}") -local_build_resource_dir = os.path.realpath(config.compiler_rt_output_dir) -if test_cc_resource_dir != local_build_resource_dir and config.test_standalone_build_libs: - if config.compiler_id == "Clang": - if lit_config.debug: - lit_config.note( - f"Overriding test compiler resource dir to use " - f'libraries in "{config.compiler_rt_libdir}"' - ) - # Ensure that we use the just-built static libraries when linking by - # overriding the Clang resource directory. Additionally, we want to use - # the builtin headers shipped with clang (e.g. stdint.h), so we - # explicitly add this as an include path (since the headers are not - # going to be in the current compiler-rt build directory). - # We also tell the linker to add an RPATH entry for the local library - # directory so that the just-built shared libraries are used. - config.target_cflags += f" -nobuiltininc" - config.target_cflags += f" -I{config.compiler_rt_src_root}/include" - config.target_cflags += f" -idirafter {test_cc_resource_dir}/include" - config.target_cflags += f" -resource-dir={config.compiler_rt_output_dir}" - config.target_cflags += f" -Wl,-rpath,{config.compiler_rt_libdir}" - else: - lit_config.warning( - f"Cannot override compiler-rt library directory with non-Clang " - f"compiler: {config.compiler_id}" - ) - - # Ask the compiler for the path to libraries it is going to use. If this # doesn't match config.compiler_rt_libdir then it means we might be testing the # compiler's own runtime libraries rather than the ones we just built. -# Warn about this and handle appropriately. +# Warn about about this and handle appropriately. compiler_libdir = find_compiler_libdir() if compiler_libdir: compiler_rt_libdir_real = os.path.realpath(config.compiler_rt_libdir) @@ -224,7 +182,7 @@ if compiler_libdir: f'compiler-rt libdir: "{compiler_rt_libdir_real}"' ) if config.test_standalone_build_libs: - # Use just built runtime libraries, i.e. the libraries this build just built. + # Use just built runtime libraries, i.e. the the libraries this built just built. if not config.test_suite_supports_overriding_runtime_lib_path: # Test suite doesn't support this configuration. # TODO(dliew): This should be an error but it seems several bots are diff --git a/compiler-rt/test/lit.common.configured.in b/compiler-rt/test/lit.common.configured.in index 8889b816b149..fff5dc6cc750 100644 --- a/compiler-rt/test/lit.common.configured.in +++ b/compiler-rt/test/lit.common.configured.in @@ -27,7 +27,6 @@ set_default("compiler_id", "@COMPILER_RT_TEST_COMPILER_ID@") set_default("python_executable", "@Python3_EXECUTABLE@") set_default("compiler_rt_debug", @COMPILER_RT_DEBUG_PYBOOL@) set_default("compiler_rt_intercept_libdispatch", @COMPILER_RT_INTERCEPT_LIBDISPATCH_PYBOOL@) -set_default("compiler_rt_output_dir", "@COMPILER_RT_RESOLVED_OUTPUT_DIR@") set_default("compiler_rt_libdir", "@COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR@") set_default("emulator", "@COMPILER_RT_EMULATOR@") set_default("asan_shadow_scale", "@COMPILER_RT_ASAN_SHADOW_SCALE@") diff --git a/compiler-rt/test/safestack/lit.cfg.py b/compiler-rt/test/safestack/lit.cfg.py index aadb8bf0d5c7..adf27a0d7e5e 100644 --- a/compiler-rt/test/safestack/lit.cfg.py +++ b/compiler-rt/test/safestack/lit.cfg.py @@ -13,16 +13,10 @@ config.suffixes = [".c", ".cpp", ".m", ".mm", ".ll", ".test"] # Add clang substitutions. config.substitutions.append( - ( - "%clang_nosafestack ", - config.clang + config.target_cflags + " -O0 -fno-sanitize=safe-stack ", - ) + ("%clang_nosafestack ", config.clang + " -O0 -fno-sanitize=safe-stack ") ) config.substitutions.append( - ( - "%clang_safestack ", - config.clang + config.target_cflags + " -O0 -fsanitize=safe-stack ", - ) + ("%clang_safestack ", config.clang + " -O0 -fsanitize=safe-stack ") ) if config.lto_supported: -- GitLab From ac321cbb0350996ceef4e6d9e8a1035880609288 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 8 Apr 2024 08:44:13 +0100 Subject: [PATCH 119/695] [AArch64][GlobalISel] Legalize Insert vector element (#81453) This attempts to standardize and extend some of the insert vector element lowering. Most notably: - More types are handled by splitting illegal vectors. - The index type for G_INSERT_VECTOR_ELT is canonicalized to TLI.getVectorIdxTy(), similar to extact_vector_element. - Some of the existing patterns now have the index type specified to make sure they can apply to GISel too. - The C++ selection code has been removed, relying on tablegen patterns. - G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to use a i32 type, allowing the existing patterns to apply. - Variable index inserts are lowered in post-legalizer lowering, expanding into a stack store and reload. --- .../CodeGen/GlobalISel/MachineIRBuilder.h | 7 +- .../Target/GlobalISel/SelectionDAGCompat.td | 1 + llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 16 +- llvm/lib/CodeGen/MachineVerifier.cpp | 55 + llvm/lib/Target/AArch64/AArch64Combine.td | 12 +- .../lib/Target/AArch64/AArch64InstrAtomics.td | 4 +- .../lib/Target/AArch64/AArch64InstrFormats.td | 6 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 39 +- .../GISel/AArch64InstructionSelector.cpp | 62 -- .../AArch64/GISel/AArch64LegalizerInfo.cpp | 10 +- .../GISel/AArch64PostLegalizerLowering.cpp | 50 + .../AArch64/GISel/AArch64RegisterBankInfo.cpp | 27 +- .../AArch64/GlobalISel/arm64-fallback.ll | 16 - .../AArch64/GlobalISel/arm64-irtranslator.ll | 3 +- .../GlobalISel/combine-build-vector.mir | 44 +- .../GlobalISel/combine-extract-vec-elt.mir | 116 +-- .../combine-icmp-to-lhs-known-bits.mir | 27 +- .../GlobalISel/combine-insert-vec-elt.mir | 74 +- .../AArch64/GlobalISel/legalize-cmp.mir | 28 +- .../legalize-extract-vector-elt.mir | 4 +- .../GlobalISel/legalize-insert-vector-elt.mir | 80 +- .../AArch64/GlobalISel/legalize-phi.mir | 24 +- .../postlegalizer-lowering-shuffle-splat.mir | 62 +- ...combiner-icmp-to-true-false-known-bits.mir | 36 +- .../GlobalISel/regbank-insert-vector-elt.mir | 93 +- .../GlobalISel/select-insert-vector-elt.mir | 54 +- llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll | 89 +- llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll | 200 ++-- llvm/test/CodeGen/AArch64/arm64-neon-copy.ll | 244 ++--- llvm/test/CodeGen/AArch64/insertextract.ll | 938 ++++++++++++------ .../combine-extract-vector-load.mir | 9 +- ...tor-non-integral-address-spaces-vectors.ll | 4 +- .../legalize-extract-vector-elt.mir | 6 +- .../legalize-extractelement-crash.mir | 5 +- .../GlobalISel/legalize-insert-vector-elt.mir | 28 +- .../GlobalISel/irtranslator/insertelement.ll | 305 +++--- .../GlobalISel/irtranslator/shufflevector.ll | 300 +++--- 37 files changed, 1759 insertions(+), 1319 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index 4c9d85fd9f51..be39eb7891f3 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -17,6 +17,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/IR/DebugLoc.h" #include "llvm/IR/Module.h" @@ -1300,8 +1301,10 @@ public: MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx) { - return buildExtractVectorElement(Res, Val, - buildConstant(LLT::scalar(64), Idx)); + auto TLI = getMF().getSubtarget().getTargetLowering(); + unsigned VecIdxWidth = TLI->getVectorIdxTy(getDataLayout()).getSizeInBits(); + return buildExtractVectorElement( + Res, Val, buildConstant(LLT::scalar(VecIdxWidth), Idx)); } /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td index 3208c63fb42d..dd4e7d790bc6 100644 --- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td +++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td @@ -142,6 +142,7 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 47e980e05281..312e564f5d80 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -3087,7 +3087,21 @@ bool IRTranslator::translateInsertElement(const User &U, Register Res = getOrCreateVReg(U); Register Val = getOrCreateVReg(*U.getOperand(0)); Register Elt = getOrCreateVReg(*U.getOperand(1)); - Register Idx = getOrCreateVReg(*U.getOperand(2)); + unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits(); + Register Idx; + if (auto *CI = dyn_cast(U.getOperand(2))) { + if (CI->getBitWidth() != PreferredVecIdxWidth) { + APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth); + auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx); + Idx = getOrCreateVReg(*NewIdxCI); + } + } + if (!Idx) + Idx = getOrCreateVReg(*U.getOperand(2)); + if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) { + const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth); + Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0); + } MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx); return true; } diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index fd7ea2842647..074408948631 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -55,6 +55,7 @@ #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackMaps.h" #include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" @@ -1788,6 +1789,60 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) { break; } + case TargetOpcode::G_EXTRACT_VECTOR_ELT: { + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + LLT SrcTy = MRI->getType(MI->getOperand(1).getReg()); + LLT IdxTy = MRI->getType(MI->getOperand(2).getReg()); + + if (!DstTy.isScalar() && !DstTy.isPointer()) { + report("Destination type must be a scalar or pointer", MI); + break; + } + + if (!SrcTy.isVector()) { + report("First source must be a vector", MI); + break; + } + + auto TLI = MF->getSubtarget().getTargetLowering(); + if (IdxTy.getSizeInBits() != + TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) { + report("Index type must match VectorIdxTy", MI); + break; + } + + break; + } + case TargetOpcode::G_INSERT_VECTOR_ELT: { + LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); + LLT VecTy = MRI->getType(MI->getOperand(1).getReg()); + LLT ScaTy = MRI->getType(MI->getOperand(2).getReg()); + LLT IdxTy = MRI->getType(MI->getOperand(3).getReg()); + + if (!DstTy.isVector()) { + report("Destination type must be a vector", MI); + break; + } + + if (VecTy != DstTy) { + report("Destination type and vector type must match", MI); + break; + } + + if (!ScaTy.isScalar() && !ScaTy.isPointer()) { + report("Inserted element must be a scalar or pointer", MI); + break; + } + + auto TLI = MF->getSubtarget().getTargetLowering(); + if (IdxTy.getSizeInBits() != + TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) { + report("Index type must match VectorIdxTy", MI); + break; + } + + break; + } case TargetOpcode::G_DYN_STACKALLOC: { const MachineOperand &DstOp = MI->getOperand(0); const MachineOperand &AllocOp = MI->getOperand(1); diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td index 1e1c6ece85b2..10cad6d19244 100644 --- a/llvm/lib/Target/AArch64/AArch64Combine.td +++ b/llvm/lib/Target/AArch64/AArch64Combine.td @@ -114,6 +114,13 @@ def ext: GICombineRule < (apply [{ applyEXT(*${root}, ${matchinfo}); }]) >; +def insertelt_nonconst: GICombineRule < + (defs root:$root, shuffle_matchdata:$matchinfo), + (match (wip_match_opcode G_INSERT_VECTOR_ELT):$root, + [{ return matchNonConstInsert(*${root}, MRI); }]), + (apply [{ applyNonConstInsert(*${root}, MRI, B); }]) +>; + def shuf_to_ins_matchdata : GIDefMatchData<"std::tuple">; def shuf_to_ins: GICombineRule < (defs root:$root, shuf_to_ins_matchdata:$matchinfo), @@ -140,8 +147,7 @@ def form_duplane : GICombineRule < >; def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn, - form_duplane, - shuf_to_ins]>; + form_duplane, shuf_to_ins]>; // Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's def vector_unmerge_lowering : GICombineRule < @@ -269,7 +275,7 @@ def AArch64PostLegalizerLowering lower_vector_fcmp, form_truncstore, vector_sext_inreg_to_shift, unmerge_ext_to_unmerge, lower_mull, - vector_unmerge_lowering]> { + vector_unmerge_lowering, insertelt_nonconst]> { } // Post-legalization combines which are primarily optimizations. diff --git a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td index 0002db52b199..de94cf64c980 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrAtomics.td +++ b/llvm/lib/Target/AArch64/AArch64InstrAtomics.td @@ -547,10 +547,10 @@ let Predicates = [HasLSE] in { let Predicates = [HasRCPC3, HasNEON] in { // LDAP1 loads def : Pat<(vector_insert (v2i64 VecListOne128:$Rd), - (i64 (acquiring_load GPR64sp:$Rn)), VectorIndexD:$idx), + (i64 (acquiring_load GPR64sp:$Rn)), (i64 VectorIndexD:$idx)), (LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>; def : Pat<(vector_insert (v2f64 VecListOne128:$Rd), - (f64 (bitconvert (i64 (acquiring_load GPR64sp:$Rn)))), VectorIndexD:$idx), + (f64 (bitconvert (i64 (acquiring_load GPR64sp:$Rn)))), (i64 VectorIndexD:$idx)), (LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>; def : Pat<(v1i64 (scalar_to_vector (i64 (acquiring_load GPR64sp:$Rn)))), diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 8360bef8e2f8..1f437d0ed6f8 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -7983,7 +7983,7 @@ class SIMDInsFromMain { + (vector_insert (vectype V128:$Rd), regtype:$Rn, (i64 idxtype:$idx)))]> { let Inst{14-11} = 0b0011; } @@ -7997,8 +7997,8 @@ class SIMDInsFromElement; + (elttype (vector_extract (vectype V128:$Rn), (i64 idxtype:$idx2))), + (i64 idxtype:$idx)))]>; class SIMDInsMainMovAlias diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index b1f514f75207..e1624f70185e 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -6601,6 +6601,15 @@ def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndex VectorIndexB:$imm, GPR32:$Rm), dsub)>; +def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))), + (EXTRACT_SUBREG + (INSvi8lane (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), V64:$Rn, dsub)), + VectorIndexB:$imm, (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0)), + dsub)>; +def : Pat<(v16i8 (vector_insert (v16i8 V128:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))), + (INSvi8lane V128:$Rn, VectorIndexB:$imm, + (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0))>; + // Copy an element at a constant index in one vector into a constant indexed // element of another. // FIXME refactor to a shared class/dev parameterized on vector type, vector @@ -6633,26 +6642,26 @@ def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane multiclass Neon_INS_elt_pattern { def : Pat<(VT128 (vector_insert V128:$src, - (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>; def : Pat<(VT128 (vector_insert V128:$src, - (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (INS V128:$src, imm:$Immd, (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>; def : Pat<(VT64 (vector_insert V64:$src, - (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, V128:$Rn, imm:$Immn), dsub)>; def : Pat<(VT64 (vector_insert V64:$src, - (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)), - imm:$Immd)), + (VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))), + (i64 imm:$Immd))), (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd, (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn), @@ -6671,14 +6680,14 @@ defm : Neon_INS_elt_pattern; // Insert from bitcast // vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0) -def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)), +def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))), (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>; -def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)), +def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))), (EXTRACT_SUBREG (INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)), imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0), dsub)>; -def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), imm:$Immd)), +def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))), (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>; // bitcast of an extract @@ -8100,7 +8109,7 @@ def : Pat<(v8bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))), class Ld1Lane128Pat : Pat<(vector_insert (VTy VecListOne128:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>; def : Ld1Lane128Pat; @@ -8123,14 +8132,14 @@ class Ld1Lane128IdxOpPat : Pat<(vector_insert (VTy VecListOne128:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (LD1 VecListOne128:$Rd, (IdxOp VecIndex:$idx), GPR64sp:$Rn)>; class Ld1Lane64IdxOpPat : Pat<(vector_insert (VTy VecListOne64:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (EXTRACT_SUBREG (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), (IdxOp VecIndex:$idx), GPR64sp:$Rn), @@ -8170,7 +8179,7 @@ let Predicates = [IsNeonAvailable] in { class Ld1Lane64Pat : Pat<(vector_insert (VTy VecListOne64:$Rd), - (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx), + (STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)), (EXTRACT_SUBREG (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub), VecIndex:$idx, GPR64sp:$Rn), diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp index d4daf17a39d5..61f5bc2464ee 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -191,7 +191,6 @@ private: MachineInstr *tryAdvSIMDModImmFP(Register Dst, unsigned DstSize, APInt Bits, MachineIRBuilder &MIRBuilder); - bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI); bool tryOptConstantBuildVec(MachineInstr &MI, LLT DstTy, MachineRegisterInfo &MRI); /// \returns true if a G_BUILD_VECTOR instruction \p MI can be selected as a @@ -3498,8 +3497,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) { return selectShuffleVector(I, MRI); case TargetOpcode::G_EXTRACT_VECTOR_ELT: return selectExtractElt(I, MRI); - case TargetOpcode::G_INSERT_VECTOR_ELT: - return selectInsertElt(I, MRI); case TargetOpcode::G_CONCAT_VECTORS: return selectConcatVectors(I, MRI); case TargetOpcode::G_JUMP_TABLE: @@ -5330,65 +5327,6 @@ bool AArch64InstructionSelector::selectUSMovFromExtend( return true; } -bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I, - MachineRegisterInfo &MRI) { - assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT); - - // Get information on the destination. - Register DstReg = I.getOperand(0).getReg(); - const LLT DstTy = MRI.getType(DstReg); - unsigned VecSize = DstTy.getSizeInBits(); - - // Get information on the element we want to insert into the destination. - Register EltReg = I.getOperand(2).getReg(); - const LLT EltTy = MRI.getType(EltReg); - unsigned EltSize = EltTy.getSizeInBits(); - if (EltSize < 8 || EltSize > 64) - return false; - - // Find the definition of the index. Bail out if it's not defined by a - // G_CONSTANT. - Register IdxReg = I.getOperand(3).getReg(); - auto VRegAndVal = getIConstantVRegValWithLookThrough(IdxReg, MRI); - if (!VRegAndVal) - return false; - unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); - - // Perform the lane insert. - Register SrcReg = I.getOperand(1).getReg(); - const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); - - if (VecSize < 128) { - // If the vector we're inserting into is smaller than 128 bits, widen it - // to 128 to do the insert. - MachineInstr *ScalarToVec = - emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB); - if (!ScalarToVec) - return false; - SrcReg = ScalarToVec->getOperand(0).getReg(); - } - - // Create an insert into a new FPR128 register. - // Note that if our vector is already 128 bits, we end up emitting an extra - // register. - MachineInstr *InsMI = - emitLaneInsert(std::nullopt, SrcReg, EltReg, LaneIdx, EltRB, MIB); - - if (VecSize < 128) { - // If we had to widen to perform the insert, then we have to demote back to - // the original size to get the result we want. - if (!emitNarrowVector(DstReg, InsMI->getOperand(0).getReg(), MIB, MRI)) - return false; - } else { - // No widening needed. - InsMI->getOperand(0).setReg(DstReg); - constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI); - } - - I.eraseFromParent(); - return true; -} - MachineInstr *AArch64InstructionSelector::tryAdvSIMDModImm8( Register Dst, unsigned DstSize, APInt Bits, MachineIRBuilder &Builder) { unsigned int Op; diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 043f142f3099..96ded69905f7 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -886,9 +886,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .clampMaxNumElements(1, p0, 2); getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT) - .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64})) + .legalIf( + typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0})) .moreElementsToNextPow2(0) - .widenVectorEltsToVectorMinSize(0, 64); + .widenVectorEltsToVectorMinSize(0, 64) + .clampNumElements(0, v8s8, v16s8) + .clampNumElements(0, v4s16, v8s16) + .clampNumElements(0, v2s32, v4s32) + .clampMaxNumElements(0, s64, 2) + .clampMaxNumElements(0, p0, 2); getActionDefinitionsBuilder(G_BUILD_VECTOR) .legalFor({{v8s8, s8}, diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp index 3cee2de4f5df..b571f56bf9e1 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp @@ -36,6 +36,7 @@ #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/Utils.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -475,6 +476,55 @@ void applyEXT(MachineInstr &MI, ShuffleVectorPseudo &MatchInfo) { MI.eraseFromParent(); } +bool matchNonConstInsert(MachineInstr &MI, MachineRegisterInfo &MRI) { + assert(MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT); + + auto ValAndVReg = + getIConstantVRegValWithLookThrough(MI.getOperand(3).getReg(), MRI); + return !ValAndVReg; +} + +void applyNonConstInsert(MachineInstr &MI, MachineRegisterInfo &MRI, + MachineIRBuilder &Builder) { + auto &Insert = cast(MI); + Builder.setInstrAndDebugLoc(Insert); + + Register Offset = Insert.getIndexReg(); + LLT VecTy = MRI.getType(Insert.getReg(0)); + LLT EltTy = MRI.getType(Insert.getElementReg()); + LLT IdxTy = MRI.getType(Insert.getIndexReg()); + + // Create a stack slot and store the vector into it + MachineFunction &MF = Builder.getMF(); + Align Alignment( + std::min(VecTy.getSizeInBytes().getKnownMinValue(), 16)); + int FrameIdx = MF.getFrameInfo().CreateStackObject(VecTy.getSizeInBytes(), + Alignment, false); + LLT FramePtrTy = LLT::pointer(0, 64); + MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); + auto StackTemp = Builder.buildFrameIndex(FramePtrTy, FrameIdx); + + Builder.buildStore(Insert.getOperand(1), StackTemp, PtrInfo, Align(8)); + + // Get the pointer to the element, and be sure not to hit undefined behavior + // if the index is out of bounds. + assert(isPowerOf2_64(VecTy.getNumElements()) && + "Expected a power-2 vector size"); + auto Mask = Builder.buildConstant(IdxTy, VecTy.getNumElements() - 1); + Register And = Builder.buildAnd(IdxTy, Offset, Mask).getReg(0); + auto EltSize = Builder.buildConstant(IdxTy, EltTy.getSizeInBytes()); + Register Mul = Builder.buildMul(IdxTy, And, EltSize).getReg(0); + Register EltPtr = + Builder.buildPtrAdd(MRI.getType(StackTemp.getReg(0)), StackTemp, Mul) + .getReg(0); + + // Write the inserted element + Builder.buildStore(Insert.getElementReg(), EltPtr, PtrInfo, Align(1)); + // Reload the whole vector. + Builder.buildLoad(Insert.getReg(0), StackTemp, PtrInfo, Align(8)); + Insert.eraseFromParent(); +} + /// Match a G_SHUFFLE_VECTOR with a mask which corresponds to a /// G_INSERT_VECTOR_ELT and G_EXTRACT_VECTOR_ELT pair. /// diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp index 0fc4d7f19910..58d000b6b2a9 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp @@ -17,6 +17,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h" +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" #include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/CodeGen/LowLevelTypeUtils.h" #include "llvm/CodeGen/MachineFunction.h" @@ -398,7 +399,10 @@ AArch64RegisterBankInfo::getInstrAlternativeMappings( void AArch64RegisterBankInfo::applyMappingImpl( MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const { - switch (OpdMapper.getMI().getOpcode()) { + MachineInstr &MI = OpdMapper.getMI(); + MachineRegisterInfo &MRI = OpdMapper.getMRI(); + + switch (MI.getOpcode()) { case TargetOpcode::G_OR: case TargetOpcode::G_BITCAST: case TargetOpcode::G_LOAD: @@ -407,6 +411,14 @@ void AArch64RegisterBankInfo::applyMappingImpl( OpdMapper.getInstrMapping().getID() <= 4) && "Don't know how to handle that ID"); return applyDefaultMapping(OpdMapper); + case TargetOpcode::G_INSERT_VECTOR_ELT: { + // Extend smaller gpr operands to 32 bit. + Builder.setInsertPt(*MI.getParent(), MI.getIterator()); + auto Ext = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(2).getReg()); + MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); + MI.getOperand(2).setReg(Ext.getReg(0)); + return applyDefaultMapping(OpdMapper); + } default: llvm_unreachable("Don't know how to handle that operation"); } @@ -752,6 +764,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } unsigned NumOperands = MI.getNumOperands(); + unsigned MappingID = DefaultMappingID; // Track the size and bank of each register. We don't do partial mappings. SmallVector OpSize(NumOperands); @@ -1002,8 +1015,14 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // The element may be either a GPR or FPR. Preserve that behaviour. if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank) OpRegBankIdx[2] = PMI_FirstFPR; - else + else { + // If the type is i8/i16, and the regank will be GPR, then we change the + // type to i32 in applyMappingImpl. + LLT Ty = MRI.getType(MI.getOperand(2).getReg()); + if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16) + MappingID = 1; OpRegBankIdx[2] = PMI_FirstGPR; + } // Index needs to be a GPR. OpRegBankIdx[3] = PMI_FirstGPR; @@ -1124,6 +1143,6 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } } - return getInstructionMapping(DefaultMappingID, Cost, - getOperandsMapping(OpdsMapping), NumOperands); + return getInstructionMapping(MappingID, Cost, getOperandsMapping(OpdsMapping), + NumOperands); } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 0a2d695acb4e..29c320da6c0a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -27,22 +27,6 @@ define void @test_write_register_intrin() { @_ZTIi = external global ptr declare i32 @__gxx_personality_v0(...) -; FALLBACK-WITH-REPORT-ERR: remark: :0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %{{[0-9]+}}:_(p0), %{{[0-9]+}}:_(s32) (in function: vector_of_pointers_insertelement) -; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement -; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement: -define void @vector_of_pointers_insertelement() { - br label %end - -block: - %dummy = insertelement <2 x ptr> %vec, ptr null, i32 0 - store <2 x ptr> %dummy, ptr undef - ret void - -end: - %vec = load <2 x ptr>, ptr undef - br label %block -} - ; FALLBACK-WITH-REPORT-ERR: remark: :0:0: cannot select: RET_ReallyLR implicit $x0 (in function: strict_align_feature) ; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for strict_align_feature ; FALLBACK-WITH-REPORT-OUT-LABEL: strict_align_feature diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 92ddc6309546..a131f35e66d0 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1538,7 +1538,8 @@ define <2 x i32> @test_insertelement(<2 x i32> %vec, i32 %elt, i32 %idx){ ; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = COPY $d0 ; CHECK: [[ELT:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[IDX:%[0-9]+]]:_(s32) = COPY $w1 -; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX]](s32) +; CHECK: [[IDX2:%[0-9]+]]:_(s64) = G_ZEXT [[IDX]] +; CHECK: [[RES:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[VEC]], [[ELT]](s32), [[IDX2]](s64) ; CHECK: $d0 = COPY [[RES]](<2 x s32>) %res = insertelement <2 x i32> %vec, i32 %elt, i32 %idx ret <2 x i32> %res diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir index 2d36fb3df033..93f6051c3bd3 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-build-vector.mir @@ -25,11 +25,11 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) RET_ReallyLR implicit $x0 @@ -55,22 +55,22 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 - ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - ; CHECK-NEXT: %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + ; CHECK-NEXT: %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: $x1 = COPY %extract2(s64) ; CHECK-NEXT: $q0 = COPY %bv(<2 x s64>) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) $q0 = COPY %bv(<2 x s64>) @@ -103,12 +103,12 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) - %extract3:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) + %extract3:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) $x2 = COPY %extract3(s64) @@ -140,12 +140,12 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 - %two:_(s32) = G_CONSTANT i32 2 + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) - %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %two(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) + %extract2:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %two(s64) $x0 = COPY %extract(s64) $x1 = COPY %extract2(s64) RET_ReallyLR implicit $x0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir index a65b43d33e49..587d53c300f8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-extract-vec-elt.mir @@ -23,9 +23,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -55,10 +55,10 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) %truncbv:_(<2 x s32>) = G_TRUNC %bv - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %truncbv(<2 x s32>), %zero(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %truncbv(<2 x s32>), %zero(s64) %zext:_(s64) = G_ZEXT %extract $x0 = COPY %zext(s64) RET_ReallyLR implicit $x0 @@ -87,9 +87,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %one:_(s32) = G_CONSTANT i32 1 + %one:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %one(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -117,9 +117,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %idx:_(s32) = G_CONSTANT i32 4 + %idx:_(s64) = G_CONSTANT i64 4 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -148,9 +148,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $w0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64) - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %zero(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %zero(s64) $w0 = COPY %extract(s32) RET_ReallyLR implicit $w0 @@ -175,17 +175,17 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 - ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: $q0 = COPY %bv(<2 x s64>) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 + %zero:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %zero(s64) $x0 = COPY %extract(s64) $q0 = COPY %bv(<2 x s64>) RET_ReallyLR implicit $x0 @@ -212,11 +212,11 @@ body: | %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 %undef:_(<2 x s64>) = G_IMPLICIT_DEF - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 - %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %undef, %arg1(s64), %zero(s32) - %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s32) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %ins2(<2 x s64>), %zero(s32) + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 + %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %undef, %arg1(s64), %zero(s64) + %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s64) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %ins2(<2 x s64>), %zero(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -244,10 +244,10 @@ body: | %arg0:_(<2 x s64>) = COPY $q0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %zero:_(s32) = G_CONSTANT i32 0 - %one:_(s32) = G_CONSTANT i32 1 - %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %arg0, %arg1(s64), %zero(s32) - %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s32) + %zero:_(s64) = G_CONSTANT i64 0 + %one:_(s64) = G_CONSTANT i64 1 + %ins1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %arg0, %arg1(s64), %zero(s64) + %ins2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %ins1, %arg2(s64), %one(s64) $q0 = COPY %ins2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -270,8 +270,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 -2 - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_CONSTANT i64 -2 + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -294,8 +294,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = G_IMPLICIT_DEF - %idx:_(s32) = G_CONSTANT i32 -2 - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_CONSTANT i64 -2 + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -315,8 +315,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_IMPLICIT_DEF - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_IMPLICIT_DEF + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -339,8 +339,8 @@ body: | ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 3000 - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + %idx:_(s64) = G_CONSTANT i64 3000 + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -360,15 +360,15 @@ body: | ; CHECK: liveins: $x0, $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vec:_(<2 x s64>) = COPY $q0 - ; CHECK-NEXT: %idx:_(s32) = COPY $w1 - ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s32) + ; CHECK-NEXT: %idx:_(s64) = COPY $x1 + ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx(s64) ; CHECK-NEXT: %extract:_(s64) = G_FREEZE [[EVEC]] ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = COPY $w1 + %idx:_(s64) = COPY $x1 %fvec:_(<2 x s64>) = G_FREEZE %vec - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %fvec(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %fvec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -391,10 +391,10 @@ body: | ; CHECK-NEXT: $x0 = COPY %element(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = COPY $w1 + %idx:_(s64) = COPY $x1 %element:_(s64) = COPY $x1 - %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s32) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx(s32) + %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s64) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -414,16 +414,16 @@ body: | ; CHECK: liveins: $x0, $x1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %vec:_(<2 x s64>) = COPY $q0 - ; CHECK-NEXT: %idx2:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx2(s32) + ; CHECK-NEXT: %idx2:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %vec(<2 x s64>), %idx2(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 0 - %idx2:_(s32) = G_CONSTANT i32 1 + %idx:_(s64) = G_CONSTANT i64 0 + %idx2:_(s64) = G_CONSTANT i64 1 %element:_(s64) = COPY $x1 - %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s32) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx2(s32) + %invec:_(<2 x s64>) = G_INSERT_VECTOR_ELT %vec(<2 x s64>), %element(s64), %idx(s64) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %invec(<2 x s64>), %idx2(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -442,19 +442,19 @@ body: | ; CHECK-LABEL: name: extract_from_build_vector_non_const ; CHECK: liveins: $x0, $x1 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %idx:_(s32) = COPY $w0 + ; CHECK-NEXT: %idx:_(s64) = COPY $x0 ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 ; CHECK-NEXT: %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + ; CHECK-NEXT: %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) ; CHECK-NEXT: $x0 = COPY %extract(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = COPY $w0 + %idx:_(s64) = COPY $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -477,11 +477,11 @@ body: | ; CHECK-NEXT: $x0 = COPY %arg1(s64) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %vec:_(<2 x s64>) = COPY $q0 - %idx:_(s32) = G_CONSTANT i32 0 + %idx:_(s64) = G_CONSTANT i64 0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 %bv:_(<2 x s64>) = G_BUILD_VECTOR %arg1(s64), %arg2(s64) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 @@ -509,9 +509,9 @@ body: | %arg2:_(s64) = COPY $x1 %arg3:_(s64) = COPY $x0 %arg4:_(s64) = COPY $x1 - %idx:_(s32) = G_CONSTANT i32 0 + %idx:_(s64) = G_CONSTANT i64 0 %bv:_(<4 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64), %arg3(s64), %arg4(s64) - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<4 x s32>), %idx(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<4 x s32>), %idx(s64) $w0 = COPY %extract(s32) RET_ReallyLR implicit $x0 ... @@ -531,16 +531,16 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: %arg1:_(s64) = COPY $x0 ; CHECK-NEXT: %arg2:_(s64) = COPY $x1 - ; CHECK-NEXT: %idx:_(s32) = COPY $w0 + ; CHECK-NEXT: %idx:_(s64) = COPY $x0 ; CHECK-NEXT: %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64) - ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s32) + ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s64) ; CHECK-NEXT: $w0 = COPY %extract(s32) ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s64) = COPY $x0 %arg2:_(s64) = COPY $x1 - %idx:_(s32) = COPY $w0 + %idx:_(s64) = COPY $x0 %bv:_(<2 x s32>) = G_BUILD_VECTOR_TRUNC %arg1(s64), %arg2(s64) - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s32) + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %bv(<2 x s32>), %idx(s64) $w0 = COPY %extract(s32) RET_ReallyLR implicit $x0 ... @@ -564,9 +564,9 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $x0 %arg1:_(s128) = COPY $q0 %arg2:_(s128) = COPY $q1 - %idx:_(s32) = G_CONSTANT i32 0 + %idx:_(s64) = G_CONSTANT i64 0 %bv:_(<2 x s64>) = G_BUILD_VECTOR_TRUNC %arg1(s128), %arg2(s128) - %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s32) + %extract:_(s64) = G_EXTRACT_VECTOR_ELT %bv(<2 x s64>), %idx(s64) $x0 = COPY %extract(s64) RET_ReallyLR implicit $x0 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir index fb072fbe97c1..63343dd8ad93 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-to-lhs-known-bits.mir @@ -129,25 +129,28 @@ body: | ; CHECK-LABEL: name: dont_apply_vector ; CHECK: liveins: $x0 - ; CHECK: %x:_(<2 x s32>) = COPY $x0 - ; CHECK: %one:_(s32) = G_CONSTANT i32 1 - ; CHECK: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32) - ; CHECK: %vec_and:_(<2 x s32>) = G_AND %x, %one_vec - ; CHECK: %zero:_(s32) = G_CONSTANT i32 0 - ; CHECK: %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32) - ; CHECK: %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec - ; CHECK: %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %zero(s32) - ; CHECK: %ext:_(s32) = G_ZEXT %elt(s1) - ; CHECK: $w0 = COPY %ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:_(<2 x s32>) = COPY $x0 + ; CHECK-NEXT: %one:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32) + ; CHECK-NEXT: %vec_and:_(<2 x s32>) = G_AND %x, %one_vec + ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: %zero64:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero(s32), %zero(s32) + ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec + ; CHECK-NEXT: %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %zero64(s64) + ; CHECK-NEXT: %ext:_(s32) = G_ZEXT %elt(s1) + ; CHECK-NEXT: $w0 = COPY %ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %x:_(<2 x s32>) = COPY $x0 %one:_(s32) = G_CONSTANT i32 1 %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one %vec_and:_(<2 x s32>) = G_AND %x, %one_vec %zero:_(s32) = G_CONSTANT i32 0 + %zero64:_(s64) = G_CONSTANT i64 0 %zero_vec:_(<2 x s32>) = G_BUILD_VECTOR %zero, %zero %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %vec_and(<2 x s32>), %zero_vec - %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp, %zero + %elt:_(s1) = G_EXTRACT_VECTOR_ELT %cmp, %zero64 %ext:_(s32) = G_ZEXT %elt(s1) $w0 = COPY %ext(s32) RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir index 254467192fb3..06fb2ce161c2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir @@ -16,10 +16,10 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 1 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 1 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s64) $x0 = COPY %4 ... --- @@ -38,10 +38,10 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 1 - %8:_(s32) = G_CONSTANT i32 0 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 1 + %8:_(s64) = G_CONSTANT i64 0 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s64) $x0 = COPY %4 ... --- @@ -63,8 +63,8 @@ body: | %6:_(s32) = COPY $w2 %7:_(s32) = COPY $w3 %2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7 - %3:_(s32) = G_CONSTANT i32 1 - %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) $q0 = COPY %4 ... --- @@ -83,33 +83,33 @@ body: | %6:_(s32) = COPY $w2 %7:_(s32) = COPY $w3 %2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7 - %3:_(s32) = G_CONSTANT i32 4 - %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 4 + %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) $q0 = COPY %4 ... --- name: test_combine_insert_vec_build_vec_variable body: | bb.1: - liveins: $w0, $w1, $w2, $w3 + liveins: $x0, $w1, $w2, $w3 ; CHECK-LABEL: name: test_combine_insert_vec_build_vec_variable - ; CHECK: liveins: $w0, $w1, $w2, $w3 + ; CHECK: liveins: $x0, $w1, $w2, $w3 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3 - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY]](s32), [[COPY]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[COPY1]](s32), [[COPY]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>) - %0:_(s32) = COPY $w0 + %0:_(s64) = COPY $x0 %1:_(s32) = COPY $w1 %6:_(s32) = COPY $w2 %7:_(s32) = COPY $w3 - %2:_(<4 x s32>) = G_BUILD_VECTOR %0, %1, %6, %7 - %3:_(s32) = COPY %0 - %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %2:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %6, %7 + %3:_(s64) = COPY %0 + %4:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %1(s32), %3(s64) $q0 = COPY %4 ... --- @@ -128,11 +128,11 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 1 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s32) - %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 1 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %8(s64) + %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s64) $x0 = COPY %5 ... --- @@ -150,11 +150,11 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 1 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %7(s32) - %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 1 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %4:_(<2 x s32>) = G_INSERT_VECTOR_ELT %3, %1(s32), %7(s64) + %5:_(<2 x s32>) = G_INSERT_VECTOR_ELT %4, %1(s32), %8(s64) $x0 = COPY %5 ... --- @@ -174,12 +174,12 @@ body: | %0:_(s32) = COPY $w0 %1:_(s32) = COPY $w1 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %7:_(s32) = G_CONSTANT i32 0 - %8:_(s32) = G_CONSTANT i32 2 - %9:_(s32) = G_CONSTANT i32 3 - %10:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s32) - %11:_(<4 x s32>) = G_INSERT_VECTOR_ELT %10, %1(s32), %8(s32) - %12:_(<4 x s32>) = G_INSERT_VECTOR_ELT %11, %0(s32), %9(s32) + %7:_(s64) = G_CONSTANT i64 0 + %8:_(s64) = G_CONSTANT i64 2 + %9:_(s64) = G_CONSTANT i64 3 + %10:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %7(s64) + %11:_(<4 x s32>) = G_INSERT_VECTOR_ELT %10, %1(s32), %8(s64) + %12:_(<4 x s32>) = G_INSERT_VECTOR_ELT %11, %0(s32), %9(s64) $q0 = COPY %12 ... --- diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir index 542cf018a6c0..5883da137a24 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir @@ -352,8 +352,8 @@ body: | %rhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32) %lhs:_(<3 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32) %cmp:_(<3 x s32>) = G_ICMP intpred(eq), %lhs(<3 x s32>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s32>), %1(s64) $w0 = COPY %2(s32) RET_ReallyLR ... @@ -386,8 +386,8 @@ body: | %rhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16) %lhs:_(<3 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16) %cmp:_(<3 x s16>) = G_ICMP intpred(eq), %lhs(<3 x s16>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s16>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s16>), %1(s64) %zext:_(s32) = G_ZEXT %2(s16) $w0 = COPY %zext(s32) RET_ReallyLR @@ -422,8 +422,8 @@ body: | %rhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8) %lhs:_(<3 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8) %cmp:_(<3 x s8>) = G_ICMP intpred(eq), %lhs(<3 x s8>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s8>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s8>), %1(s64) %zext:_(s32) = G_ZEXT %2(s8) $w0 = COPY %zext(s32) RET_ReallyLR @@ -449,8 +449,8 @@ body: | %rhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64) %lhs:_(<3 x s64>) = G_BUILD_VECTOR %const(s64), %const(s64), %const(s64) %cmp:_(<3 x s64>) = G_ICMP intpred(eq), %lhs(<3 x s64>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s64) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s64>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s64) = G_EXTRACT_VECTOR_ELT %cmp(<3 x s64>), %1(s64) $x0 = COPY %2(s64) RET_ReallyLR ... @@ -475,8 +475,8 @@ body: | %rhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32) %lhs:_(<5 x s32>) = G_BUILD_VECTOR %const(s32), %const(s32), %const(s32), %const(s32), %const(s32) %cmp:_(<5 x s32>) = G_ICMP intpred(eq), %lhs(<5 x s32>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<5 x s32>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s32) = G_EXTRACT_VECTOR_ELT %cmp(<5 x s32>), %1(s64) $w0 = COPY %2(s32) RET_ReallyLR ... @@ -502,8 +502,8 @@ body: | %rhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16) %lhs:_(<7 x s16>) = G_BUILD_VECTOR %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16), %const(s16) %cmp:_(<7 x s16>) = G_ICMP intpred(eq), %lhs(<7 x s16>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<7 x s16>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s16) = G_EXTRACT_VECTOR_ELT %cmp(<7 x s16>), %1(s64) %zext:_(s32) = G_ZEXT %2(s16) $w0 = COPY %zext(s32) RET_ReallyLR @@ -530,8 +530,8 @@ body: | %rhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8) %lhs:_(<9 x s8>) = G_BUILD_VECTOR %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8), %const(s8) %cmp:_(<9 x s8>) = G_ICMP intpred(eq), %lhs(<9 x s8>), %rhs - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<9 x s8>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s8) = G_EXTRACT_VECTOR_ELT %cmp(<9 x s8>), %1(s64) %zext:_(s32) = G_ZEXT %2(s8) $w0 = COPY %zext(s32) RET_ReallyLR diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir index 2209287284b7..c03f51a89dfb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir @@ -13,8 +13,8 @@ body: | ; CHECK-NEXT: $x0 = COPY [[EVEC]](s64) ; CHECK-NEXT: RET_ReallyLR %0:_(<2 x s64>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 - %2:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %1(s32) + %1:_(s64) = G_CONSTANT i64 1 + %2:_(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %1(s64) $x0 = COPY %2(s64) RET_ReallyLR ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir index d3db2432e84c..a74bf9a5438b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir @@ -9,16 +9,16 @@ body: | ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $d0 %1:_(<2 x s32>) = COPY $d0 %0:_(<2 x s16>) = G_TRUNC %1(<2 x s32>) - %4:_(s32) = G_CONSTANT i32 0 + %4:_(s64) = G_CONSTANT i64 0 %3:_(s16) = G_CONSTANT i16 1 - %2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s32) + %2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s64) %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>) $d0 = COPY %5(<2 x s32>) RET_ReallyLR implicit $d0 @@ -32,16 +32,16 @@ body: | ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $d0 %1:_(<2 x s32>) = COPY $d0 %0:_(<2 x s8>) = G_TRUNC %1(<2 x s32>) - %4:_(s32) = G_CONSTANT i32 0 + %4:_(s64) = G_CONSTANT i64 0 %3:_(s8) = G_CONSTANT i8 1 - %2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32) + %2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s64) %5:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>) $d0 = COPY %5(<2 x s32>) RET_ReallyLR implicit $d0 @@ -55,16 +55,16 @@ body: | ; CHECK: liveins: $d0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>) ; CHECK-NEXT: RET_ReallyLR implicit $d0 %1:_(<4 x s16>) = COPY $d0 %0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>) - %4:_(s32) = G_CONSTANT i32 0 + %4:_(s64) = G_CONSTANT i64 0 %3:_(s8) = G_CONSTANT i8 1 - %2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32) + %2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s64) %5:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>) $d0 = COPY %5(<4 x s16>) RET_ReallyLR implicit $d0 @@ -78,15 +78,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<8 x s8>) ; CHECK-NEXT: RET_ReallyLR %0:_(<8 x s8>) = COPY $d0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s8) = G_CONSTANT i8 42 - %2:_(<8 x s8>) = G_INSERT_VECTOR_ELT %0(<8 x s8>), %val(s8), %1(s32) + %2:_(<8 x s8>) = G_INSERT_VECTOR_ELT %0(<8 x s8>), %val(s8), %1(s64) $d0 = COPY %2(<8 x s8>) RET_ReallyLR ... @@ -99,15 +99,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<16 x s8>) ; CHECK-NEXT: RET_ReallyLR %0:_(<16 x s8>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s8) = G_CONSTANT i8 42 - %2:_(<16 x s8>) = G_INSERT_VECTOR_ELT %0(<16 x s8>), %val(s8), %1(s32) + %2:_(<16 x s8>) = G_INSERT_VECTOR_ELT %0(<16 x s8>), %val(s8), %1(s64) $q0 = COPY %2(<16 x s8>) RET_ReallyLR ... @@ -120,15 +120,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>) ; CHECK-NEXT: RET_ReallyLR %0:_(<4 x s16>) = COPY $d0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s16) = G_CONSTANT i16 42 - %2:_(<4 x s16>) = G_INSERT_VECTOR_ELT %0(<4 x s16>), %val(s16), %1(s32) + %2:_(<4 x s16>) = G_INSERT_VECTOR_ELT %0(<4 x s16>), %val(s16), %1(s64) $d0 = COPY %2(<4 x s16>) RET_ReallyLR ... @@ -141,15 +141,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<8 x s16>) ; CHECK-NEXT: RET_ReallyLR %0:_(<8 x s16>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s16) = G_CONSTANT i16 42 - %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s32) + %2:_(<8 x s16>) = G_INSERT_VECTOR_ELT %0(<8 x s16>), %val(s16), %1(s64) $q0 = COPY %2(<8 x s16>) RET_ReallyLR ... @@ -162,15 +162,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s64) ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) ; CHECK-NEXT: RET_ReallyLR %0:_(<2 x s32>) = COPY $d0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s32) = G_CONSTANT i32 42 - %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s32) + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %val(s32), %1(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR ... @@ -183,15 +183,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>) ; CHECK-NEXT: RET_ReallyLR %0:_(<4 x s32>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s32) = G_CONSTANT i32 42 - %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s32) + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0(<4 x s32>), %val(s32), %1(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR ... @@ -204,15 +204,15 @@ body: | ; CHECK: liveins: $q0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: %val:_(s64) = G_CONSTANT i64 42 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s64) ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>) ; CHECK-NEXT: RET_ReallyLR %0:_(<2 x s64>) = COPY $q0 - %1:_(s32) = G_CONSTANT i32 1 + %1:_(s64) = G_CONSTANT i64 1 %val:_(s64) = G_CONSTANT i64 42 - %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s32) + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %0(<2 x s64>), %val(s64), %1(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir index 8803da265aa1..8bd62c592254 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir @@ -782,8 +782,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<4 x s32>) = G_PHI [[BUILD_VECTOR1]](<4 x s32>), %bb.1, [[BUILD_VECTOR]](<4 x s32>), %bb.0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), [[C1]](s64) + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s32) = G_EXTRACT_VECTOR_ELT [[PHI]](<4 x s32>), %one(s64) ; CHECK-NEXT: $w0 = COPY %extract(s32) ; CHECK-NEXT: RET_ReallyLR implicit $w0 bb.0: @@ -797,8 +797,8 @@ body: | %val_2:_(<8 x s32>) = G_IMPLICIT_DEF bb.2: %phi:_(<8 x s32>) = G_PHI %val_2(<8 x s32>), %bb.1, %val_1(<8 x s32>), %bb.0 - %one:_(s32) = G_CONSTANT i32 1 - %extract:_(s32) = G_EXTRACT_VECTOR_ELT %phi(<8 x s32>), %one(s32) + %one:_(s64) = G_CONSTANT i64 1 + %extract:_(s32) = G_EXTRACT_VECTOR_ELT %phi(<8 x s32>), %one(s64) $w0 = COPY %extract RET_ReallyLR implicit $w0 ... @@ -828,8 +828,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<8 x s16>) = G_PHI [[BUILD_VECTOR1]](<8 x s16>), %bb.1, [[BUILD_VECTOR]](<8 x s16>), %bb.0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), [[C1]](s64) + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s16) = G_EXTRACT_VECTOR_ELT [[PHI]](<8 x s16>), %one(s64) ; CHECK-NEXT: $h0 = COPY %extract(s16) ; CHECK-NEXT: RET_ReallyLR implicit $h0 bb.0: @@ -843,8 +843,8 @@ body: | %val_2:_(<16 x s16>) = G_IMPLICIT_DEF bb.2: %phi:_(<16 x s16>) = G_PHI %val_2(<16 x s16>), %bb.1, %val_1(<16 x s16>), %bb.0 - %one:_(s16) = G_CONSTANT i16 1 - %extract:_(s16) = G_EXTRACT_VECTOR_ELT %phi(<16 x s16>), %one(s16) + %one:_(s64) = G_CONSTANT i64 1 + %extract:_(s16) = G_EXTRACT_VECTOR_ELT %phi(<16 x s16>), %one(s64) $h0 = COPY %extract RET_ReallyLR implicit $h0 ... @@ -874,8 +874,8 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.2: ; CHECK-NEXT: [[PHI:%[0-9]+]]:_(<16 x s8>) = G_PHI [[BUILD_VECTOR1]](<16 x s8>), %bb.1, [[BUILD_VECTOR]](<16 x s8>), %bb.0 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: %extract:_(s8) = G_EXTRACT_VECTOR_ELT [[PHI]](<16 x s8>), [[C1]](s64) + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %extract:_(s8) = G_EXTRACT_VECTOR_ELT [[PHI]](<16 x s8>), %one(s64) ; CHECK-NEXT: $b0 = COPY %extract(s8) ; CHECK-NEXT: RET_ReallyLR implicit $b0 bb.0: @@ -889,8 +889,8 @@ body: | %val_2:_(<32 x s8>) = G_IMPLICIT_DEF bb.2: %phi:_(<32 x s8>) = G_PHI %val_2(<32 x s8>), %bb.1, %val_1(<32 x s8>), %bb.0 - %one:_(s8) = G_CONSTANT i8 1 - %extract:_(s8) = G_EXTRACT_VECTOR_ELT %phi(<32 x s8>), %one(s8) + %one:_(s64) = G_CONSTANT i64 1 + %extract:_(s8) = G_EXTRACT_VECTOR_ELT %phi(<32 x s8>), %one(s64) $b0 = COPY %extract RET_ReallyLR implicit $b0 ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir index f4374feadcdf..9d12c3c32c7f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-shuffle-splat.mir @@ -19,8 +19,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $w0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -44,8 +44,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -69,8 +69,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $w0 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0) $d0 = COPY %4(<2 x s32>) RET_ReallyLR implicit $d0 @@ -94,8 +94,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -119,8 +119,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $d0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -144,8 +144,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $s0 %2:_(<2 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<2 x s32>) = G_SHUFFLE_VECTOR %1(<2 x s32>), %2, shufflemask(0, 0) $d0 = COPY %4(<2 x s32>) RET_ReallyLR implicit $d0 @@ -172,8 +172,8 @@ body: | %0:_(s64) = COPY $d0 %2:_(<2 x s64>) = G_IMPLICIT_DEF %6:_(<2 x s64>) = COPY %2 - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s64) %7:_(<2 x s64>) = COPY %1 %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) @@ -194,15 +194,15 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[IVEC]](<2 x s64>) ; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x s64>) ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 1) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -230,8 +230,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %2:_(<2 x s64>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s64) %4:_(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(-1, -1) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -258,8 +258,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, -1, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -273,22 +273,20 @@ tracksRegLiveness: true body: | bb.1.entry: liveins: $s0 - ; Check a non-splat mask with an undef value. We shouldn't get a G_DUP here. - ; ; CHECK-LABEL: name: not_all_zeros_with_undefs ; CHECK: liveins: $s0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s64) ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[IVEC]](<4 x s32>), [[DEF]], shufflemask(undef, 0, 0, 3) ; CHECK-NEXT: $q0 = COPY [[SHUF]](<4 x s32>) ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %2:_(<4 x s32>) = G_IMPLICIT_DEF - %3:_(s32) = G_CONSTANT i32 0 - %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %1:_(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s64) %4:_(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(-1, 0, 0, 3) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -311,8 +309,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %copy:_(s16) = COPY $h0 %undef:_(<4 x s16>) = G_IMPLICIT_DEF - %cst:_(s32) = G_CONSTANT i32 0 - %ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %undef, %copy(s16), %cst(s32) + %cst:_(s64) = G_CONSTANT i64 0 + %ins:_(<4 x s16>) = G_INSERT_VECTOR_ELT %undef, %copy(s16), %cst(s64) %splat:_(<4 x s16>) = G_SHUFFLE_VECTOR %ins(<4 x s16>), %undef, shufflemask(0, 0, 0, 0) $d0 = COPY %splat(<4 x s16>) RET_ReallyLR implicit $d0 @@ -335,8 +333,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %copy:_(s32) = COPY $w0 %undef:_(<8 x s8>) = G_IMPLICIT_DEF - %cst:_(s32) = G_CONSTANT i32 0 - %ins:_(<8 x s8>) = G_INSERT_VECTOR_ELT %undef, %copy(s32), %cst(s32) + %cst:_(s64) = G_CONSTANT i64 0 + %ins:_(<8 x s8>) = G_INSERT_VECTOR_ELT %undef, %copy(s32), %cst(s64) %splat:_(<8 x s8>) = G_SHUFFLE_VECTOR %ins(<8 x s8>), %undef, shufflemask(0, 0, 0, 0, 0, 0, 0, 0) $d0 = COPY %splat(<8 x s8>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir index 7666b2fb8368..8adf5b2d26bf 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir @@ -534,18 +534,20 @@ body: | liveins: $x0 ; CHECK-LABEL: name: vector_true ; CHECK: liveins: $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) - ; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - ; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1) - ; CHECK: $w0 = COPY %extract_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %cst64:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true + ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) + ; CHECK-NEXT: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) + ; CHECK-NEXT: %extract_ext:_(s32) = G_ZEXT %extract(s1) + ; CHECK-NEXT: $w0 = COPY %extract_ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %ptr:_(p0) = COPY $x0 %cst:_(s32) = G_CONSTANT i32 1 + %cst64:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst %cmp:_(<2 x s1>) = G_ICMP intpred(eq), %bv(<2 x s32>), %bv - %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) + %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) %extract_ext:_(s32) = G_ZEXT %extract(s1) $w0 = COPY %extract_ext(s32) RET_ReallyLR implicit $w0 @@ -559,18 +561,20 @@ body: | liveins: $x0 ; CHECK-LABEL: name: vector_false ; CHECK: liveins: $x0 - ; CHECK: %cst:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; CHECK: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) - ; CHECK: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) - ; CHECK: %extract_ext:_(s32) = G_ZEXT %extract(s1) - ; CHECK: $w0 = COPY %extract_ext(s32) - ; CHECK: RET_ReallyLR implicit $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %cst64:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false + ; CHECK-NEXT: %cmp:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1) + ; CHECK-NEXT: %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) + ; CHECK-NEXT: %extract_ext:_(s32) = G_ZEXT %extract(s1) + ; CHECK-NEXT: $w0 = COPY %extract_ext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 %ptr:_(p0) = COPY $x0 %cst:_(s32) = G_CONSTANT i32 1 + %cst64:_(s64) = G_CONSTANT i64 1 %bv:_(<2 x s32>) = G_BUILD_VECTOR %cst, %cst %cmp:_(<2 x s1>) = G_ICMP intpred(ne), %bv(<2 x s32>), %bv - %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst(s32) + %extract:_(s1) = G_EXTRACT_VECTOR_ELT %cmp(<2 x s1>), %cst64(s64) %extract_ext:_(s32) = G_ZEXT %extract(s1) $w0 = COPY %extract_ext(s32) RET_ReallyLR implicit $w0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir index eb539aacc4bf..b0620a8f81dc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-insert-vector-elt.mir @@ -24,14 +24,14 @@ body: | ; CHECK: liveins: $q1, $s0 ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q1 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) + ; CHECK: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) ; CHECK: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $s0 %1:_(<4 x s32>) = COPY $q1 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -47,16 +47,17 @@ body: | ; CHECK-LABEL: name: v4s32_gpr ; CHECK: liveins: $q0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) - ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>) - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) + ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s32) = COPY $w0 %1:_(<4 x s32>) = COPY $q0 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -72,16 +73,17 @@ body: | ; CHECK-LABEL: name: v2s64_fpr ; CHECK: liveins: $d0, $q1 - ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32) - ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q1 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $d0 %1:_(<2 x s64>) = COPY $q1 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -97,16 +99,17 @@ body: | ; CHECK-LABEL: name: v2s64_gpr ; CHECK: liveins: $q0, $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s32) - ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>) - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s64), [[C]](s64) + ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>) + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:_(s64) = COPY $x0 %1:_(<2 x s64>) = COPY $q0 - %3:_(s32) = G_CONSTANT i32 0 - %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:_(s64) = G_CONSTANT i64 0 + %2:_(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -122,16 +125,17 @@ body: | ; CHECK-LABEL: name: v2s32_fpr ; CHECK: liveins: $d1, $s0 - ; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) - ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d1 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) + ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $s0 %1:_(<2 x s32>) = COPY $d1 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 @@ -147,16 +151,17 @@ body: | ; CHECK-LABEL: name: v2s32_gpr ; CHECK: liveins: $d0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0 - ; CHECK: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 1 - ; CHECK: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s32) - ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>) - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0 + ; CHECK-NEXT: [[C:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY1]], [[COPY]](s32), [[C]](s64) + ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:_(s32) = COPY $w0 %1:_(<2 x s32>) = COPY $d0 - %3:_(s32) = G_CONSTANT i32 1 - %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:_(s64) = G_CONSTANT i64 1 + %2:_(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir index d6618d440f42..33f7e58804f1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir @@ -21,8 +21,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s8) = G_TRUNC %0 %1:fpr(<16 x s8>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s8), %3:gpr(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64) $q0 = COPY %2(<16 x s8>) RET_ReallyLR implicit $q0 @@ -51,8 +52,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s8) = G_TRUNC %0 %1:fpr(<8 x s8>) = COPY $d0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %trunc(s8), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64) $d0 = COPY %2(<8 x s8>) RET_ReallyLR implicit $d0 @@ -78,8 +80,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s16) = G_TRUNC %0 %1:fpr(<8 x s16>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64) $q0 = COPY %2(<8 x s16>) RET_ReallyLR implicit $q0 @@ -106,8 +109,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s16) = COPY $h0 %1:fpr(<8 x s16>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s64) $q0 = COPY %2(<8 x s16>) RET_ReallyLR implicit $q0 @@ -134,8 +137,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s32) = COPY $s0 %1:fpr(<4 x s32>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -160,8 +163,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s32) = COPY $w0 %1:fpr(<4 x s32>) = COPY $q0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -190,8 +193,9 @@ body: | %0:gpr(s32) = COPY $w0 %trunc:gpr(s16) = G_TRUNC %0 %1:fpr(<4 x s16>) = COPY $d0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc(s16), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %4:gpr(s32) = G_ANYEXT %trunc + %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64) $d0 = COPY %2(<4 x s16>) RET_ReallyLR implicit $d0 @@ -218,8 +222,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s64) = COPY $d0 %1:fpr(<2 x s64>) = COPY $q1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -244,8 +248,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s64) = COPY $x0 %1:fpr(<2 x s64>) = COPY $q0 - %3:gpr(s32) = G_CONSTANT i32 0 - %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 0 + %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 @@ -266,17 +270,17 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub - ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub ; CHECK-NEXT: $d0 = COPY [[COPY2]] ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(s32) = COPY $s0 %1:fpr(<2 x s32>) = COPY $d1 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 @@ -304,8 +308,8 @@ body: | ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:gpr(s32) = COPY $w0 %1:fpr(<2 x s32>) = COPY $d0 - %3:gpr(s32) = G_CONSTANT i32 1 - %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32) + %3:gpr(s64) = G_CONSTANT i64 1 + %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll index 5c006508d284..3a17a95ed71d 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll @@ -1,8 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI - -; CHECK-GI: warning: Instruction selection used fallback path for test_bit_sink_operand +; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI ; BIT Bitwise Insert if True ; @@ -200,34 +198,63 @@ define <16 x i8> @test_bit_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) { } define <4 x i32> @test_bit_sink_operand(<4 x i32> %src, <4 x i32> %dst, <4 x i32> %mask, i32 %scratch) { -; CHECK-LABEL: test_bit_sink_operand: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #32 -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w9, wzr -; CHECK-NEXT: cinc w8, w0, lt -; CHECK-NEXT: asr w8, w8, #1 -; CHECK-NEXT: .LBB11_1: // %do.body -; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: bit v1.16b, v0.16b, v2.16b -; CHECK-NEXT: add x10, sp, #16 -; CHECK-NEXT: mov x11, sp -; CHECK-NEXT: bfi x10, x9, #2, #2 -; CHECK-NEXT: bfi x11, x9, #2, #2 -; CHECK-NEXT: add w9, w9, #1 -; CHECK-NEXT: cmp w9, #5 -; CHECK-NEXT: str q1, [sp, #16] -; CHECK-NEXT: str w0, [x10] -; CHECK-NEXT: ldr q1, [sp, #16] -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: str w8, [x11] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: b.ne .LBB11_1 -; CHECK-NEXT: // %bb.2: // %do.end -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bit_sink_operand: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #32 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: cmp w0, #0 +; CHECK-SD-NEXT: mov w9, wzr +; CHECK-SD-NEXT: cinc w8, w0, lt +; CHECK-SD-NEXT: asr w8, w8, #1 +; CHECK-SD-NEXT: .LBB11_1: // %do.body +; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-SD-NEXT: bit v1.16b, v0.16b, v2.16b +; CHECK-SD-NEXT: add x10, sp, #16 +; CHECK-SD-NEXT: mov x11, sp +; CHECK-SD-NEXT: bfi x10, x9, #2, #2 +; CHECK-SD-NEXT: bfi x11, x9, #2, #2 +; CHECK-SD-NEXT: add w9, w9, #1 +; CHECK-SD-NEXT: cmp w9, #5 +; CHECK-SD-NEXT: str q1, [sp, #16] +; CHECK-SD-NEXT: str w0, [x10] +; CHECK-SD-NEXT: ldr q1, [sp, #16] +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: str w8, [x11] +; CHECK-SD-NEXT: ldr q0, [sp] +; CHECK-SD-NEXT: b.ne .LBB11_1 +; CHECK-SD-NEXT: // %bb.2: // %do.end +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: add sp, sp, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bit_sink_operand: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #32 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 32 +; CHECK-GI-NEXT: asr w9, w0, #31 +; CHECK-GI-NEXT: mov w8, wzr +; CHECK-GI-NEXT: add x10, sp, #16 +; CHECK-GI-NEXT: mov x11, sp +; CHECK-GI-NEXT: add w9, w0, w9, lsr #31 +; CHECK-GI-NEXT: asr w9, w9, #1 +; CHECK-GI-NEXT: .LBB11_1: // %do.body +; CHECK-GI-NEXT: // =>This Inner Loop Header: Depth=1 +; CHECK-GI-NEXT: bit v1.16b, v0.16b, v2.16b +; CHECK-GI-NEXT: mov w12, w8 +; CHECK-GI-NEXT: add w8, w8, #1 +; CHECK-GI-NEXT: and x12, x12, #0x3 +; CHECK-GI-NEXT: cmp w8, #5 +; CHECK-GI-NEXT: str q1, [sp, #16] +; CHECK-GI-NEXT: str w0, [x10, x12, lsl #2] +; CHECK-GI-NEXT: ldr q1, [sp, #16] +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: str w9, [x11, x12, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp] +; CHECK-GI-NEXT: b.ne .LBB11_1 +; CHECK-GI-NEXT: // %bb.2: // %do.end +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: add sp, sp, #32 +; CHECK-GI-NEXT: ret entry: %0 = xor <4 x i32> %mask, diff --git a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll index 76790d128d06..f7aa57a068a4 100644 --- a/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll @@ -1,14 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 ; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI +; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" -; CHECK-GI: warning: Instruction selection used fallback path for sminv_v3i64 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for smaxv_v3i64 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uminv_v3i64 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for umaxv_v3i64 - declare i8 @llvm.vector.reduce.smin.v2i8(<2 x i8>) declare i8 @llvm.vector.reduce.smin.v3i8(<3 x i8>) declare i8 @llvm.vector.reduce.smin.v4i8(<4 x i8>) @@ -713,21 +708,39 @@ entry: } define i64 @sminv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: sminv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v2.d[1], x8 -; CHECK-NEXT: cmgt v1.2d, v2.2d, v0.2d -; CHECK-NEXT: bif v0.16b, v2.16b, v1.16b -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: cmgt d2, d1, d0 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: sminv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v2.d[1], x8 +; CHECK-SD-NEXT: cmgt v1.2d, v2.2d, v0.2d +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: cmgt d2, d1, d0 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: sminv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], x8 +; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, v0.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, lt +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.smin.v3i64(<3 x i64> %a) ret i64 %arg1 @@ -1056,21 +1069,39 @@ entry: } define i64 @smaxv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: smaxv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v2.d[1], x8 -; CHECK-NEXT: cmgt v1.2d, v0.2d, v2.2d -; CHECK-NEXT: bif v0.16b, v2.16b, v1.16b -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: cmgt d2, d0, d1 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: smaxv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v2.d[1], x8 +; CHECK-SD-NEXT: cmgt v1.2d, v0.2d, v2.2d +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: cmgt d2, d0, d1 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: smaxv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], x8 +; CHECK-GI-NEXT: cmgt v1.2d, v0.2d, v2.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, gt +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.smax.v3i64(<3 x i64> %a) ret i64 %arg1 @@ -1397,21 +1428,39 @@ entry: } define i64 @uminv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: uminv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov x8, #-1 // =0xffffffffffffffff -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v2.d[1], x8 -; CHECK-NEXT: cmhi v1.2d, v2.2d, v0.2d -; CHECK-NEXT: bif v0.16b, v2.16b, v1.16b -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: cmhi d2, d1, d0 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: uminv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov x8, #-1 // =0xffffffffffffffff +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v2.d[1], x8 +; CHECK-SD-NEXT: cmhi v1.2d, v2.2d, v0.2d +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: cmhi d2, d1, d0 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: uminv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov x8, #-1 // =0xffffffffffffffff +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], x8 +; CHECK-GI-NEXT: cmhi v1.2d, v2.2d, v0.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, lo +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.umin.v3i64(<3 x i64> %a) ret i64 %arg1 @@ -1736,22 +1785,39 @@ entry: } define i64 @umaxv_v3i64(<3 x i64> %a) { -; CHECK-LABEL: umaxv_v3i64: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: mov v3.16b, v2.16b -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: mov v3.d[1], xzr -; CHECK-NEXT: cmhi v3.2d, v0.2d, v3.2d -; CHECK-NEXT: ext v4.16b, v3.16b, v3.16b, #8 -; CHECK-NEXT: bif v0.16b, v2.16b, v3.16b -; CHECK-NEXT: and v1.8b, v1.8b, v4.8b -; CHECK-NEXT: cmhi d2, d0, d1 -; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: umaxv_v3i64: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: mov v3.16b, v2.16b +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: mov v3.d[1], xzr +; CHECK-SD-NEXT: cmhi v3.2d, v0.2d, v3.2d +; CHECK-SD-NEXT: ext v4.16b, v3.16b, v3.16b, #8 +; CHECK-SD-NEXT: bif v0.16b, v2.16b, v3.16b +; CHECK-SD-NEXT: and v1.8b, v1.8b, v4.8b +; CHECK-SD-NEXT: cmhi d2, d0, d1 +; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: umaxv_v3i64: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: mov v2.d[1], xzr +; CHECK-GI-NEXT: cmhi v1.2d, v0.2d, v2.2d +; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: fmov x9, d1 +; CHECK-GI-NEXT: cmp x8, x9 +; CHECK-GI-NEXT: fcsel d0, d0, d1, hi +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret entry: %arg1 = call i64 @llvm.vector.reduce.umax.v3i64(<3 x i64> %a) ret i64 %arg1 diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll index d282bee81827..749d6071c98d 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -4,9 +4,6 @@ ; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64 ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_extracts_inserts_varidx_insert -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) { ; CHECK-LABEL: ins16bw: @@ -96,36 +93,22 @@ define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) { } define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) { -; CHECK-SD-LABEL: ins8h8: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: mov v1.h[7], v0.h[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins8h8: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.h[7], v2.h[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins8h8: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v1.h[7], v0.h[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <8 x i16> %tmp1, i32 2 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7 ret <8 x i16> %tmp4 } define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) { -; CHECK-SD-LABEL: ins4s4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4s4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4s4: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1 ret <4 x i32> %tmp4 @@ -143,18 +126,11 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) { } define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) { -; CHECK-SD-LABEL: ins4f4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4f4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4f4: +; CHECK: // %bb.0: +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <4 x float> %tmp1, i32 2 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1 ret <4 x float> %tmp4 @@ -192,40 +168,24 @@ define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) { } define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) { -; CHECK-SD-LABEL: ins4h8: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.h[7], v0.h[2] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4h8: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.h[7], v2.h[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4h8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.h[7], v0.h[2] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i16> %tmp1, i32 2 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7 ret <8 x i16> %tmp4 } define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) { -; CHECK-SD-LABEL: ins2s4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[1] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins2s4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov s2, v0.s[1] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins2s4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.s[1], v0.s[1] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <2 x i32> %tmp1, i32 1 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1 ret <4 x i32> %tmp4 @@ -244,20 +204,12 @@ define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) { } define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) { -; CHECK-SD-LABEL: ins2f4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[1] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins2f4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov s2, v0.s[1] -; CHECK-GI-NEXT: mov v0.16b, v1.16b -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins2f4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.s[1], v0.s[1] +; CHECK-NEXT: mov v0.16b, v1.16b +; CHECK-NEXT: ret %tmp3 = extractelement <2 x float> %tmp1, i32 1 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1 ret <4 x float> %tmp4 @@ -307,40 +259,24 @@ define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) { } define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) { -; CHECK-SD-LABEL: ins8h4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: mov v1.h[3], v0.h[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins8h4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.h[3], v2.h[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins8h4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v1.h[3], v0.h[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <8 x i16> %tmp1, i32 2 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3 ret <4 x i16> %tmp4 } define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) { -; CHECK-SD-LABEL: ins4s2: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4s2: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4s2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1 ret <2 x i32> %tmp4 @@ -357,20 +293,12 @@ define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) { } define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) { -; CHECK-SD-LABEL: ins4f2: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4f2: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: mov s2, v0.s[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4f2: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v1.s[1], v0.s[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <4 x float> %tmp1, i32 2 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1 ret <2 x float> %tmp4 @@ -415,22 +343,13 @@ define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) { } define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) { -; CHECK-SD-LABEL: ins4h4: -; CHECK-SD: // %bb.0: -; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-SD-NEXT: mov v1.h[3], v0.h[2] -; CHECK-SD-NEXT: fmov d0, d1 -; CHECK-SD-NEXT: ret -; -; CHECK-GI-LABEL: ins4h4: -; CHECK-GI: // %bb.0: -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-GI-NEXT: mov h2, v0.h[2] -; CHECK-GI-NEXT: fmov d0, d1 -; CHECK-GI-NEXT: mov v0.h[3], v2.h[0] -; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-GI-NEXT: ret +; CHECK-LABEL: ins4h4: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v1.h[3], v0.h[2] +; CHECK-NEXT: fmov d0, d1 +; CHECK-NEXT: ret %tmp3 = extractelement <4 x i16> %tmp1, i32 2 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3 ret <4 x i16> %tmp4 @@ -1516,21 +1435,38 @@ define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) { } define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) { -; CHECK-LABEL: test_extracts_inserts_varidx_insert: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: bfi x8, x0, #1, #2 -; CHECK-NEXT: str h0, [x8] -; CHECK-NEXT: ldr d1, [sp, #8] -; CHECK-NEXT: mov v1.h[1], v0.h[1] -; CHECK-NEXT: mov v1.h[2], v0.h[2] -; CHECK-NEXT: mov v1.h[3], v0.h[3] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_extracts_inserts_varidx_insert: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: bfi x8, x0, #1, #2 +; CHECK-SD-NEXT: str h0, [x8] +; CHECK-SD-NEXT: ldr d1, [sp, #8] +; CHECK-SD-NEXT: mov v1.h[1], v0.h[1] +; CHECK-SD-NEXT: mov v1.h[2], v0.h[2] +; CHECK-SD-NEXT: mov v1.h[3], v0.h[3] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_extracts_inserts_varidx_insert: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: add x9, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: str h0, [x9, x8, lsl #1] +; CHECK-GI-NEXT: ldr d1, [sp, #8] +; CHECK-GI-NEXT: mov v1.h[1], v0.h[1] +; CHECK-GI-NEXT: mov v1.h[2], v0.h[2] +; CHECK-GI-NEXT: mov v1.h[3], v0.h[3] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret %tmp = extractelement <8 x i16> %x, i32 0 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx %tmp3 = extractelement <8 x i16> %x, i32 1 diff --git a/llvm/test/CodeGen/AArch64/insertextract.ll b/llvm/test/CodeGen/AArch64/insertextract.ll index 5c2dd761bdc0..c6b2d07231bf 100644 --- a/llvm/test/CodeGen/AArch64/insertextract.ll +++ b/llvm/test/CodeGen/AArch64/insertextract.ll @@ -1,44 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD -; RUN: llc -mtriple=aarch64 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI - -; CHECK-GI: warning: Instruction selection used fallback path for insert_v2f64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3f64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f64_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f64_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f32_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f32_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4f16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8f16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16f16_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16f16_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16f16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i8_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i8_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v32i8_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v32i8_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v32i8_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i16_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i16_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v16i16_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i32_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i32_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v8i32_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v2i64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v3i64_c -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i64_0 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i64_2 -; CHECK-GI-NEXT: warning: Instruction selection used fallback path for insert_v4i64_c +; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI define <2 x double> @insert_v2f64_0(<2 x double> %a, double %b, i32 %c) { ; CHECK-LABEL: insert_v2f64_0: @@ -63,17 +25,29 @@ entry: } define <2 x double> @insert_v2f64_c(<2 x double> %a, double %b, i32 %c) { -; CHECK-LABEL: insert_v2f64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #3, #1 -; CHECK-NEXT: str d1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2f64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #3, #1 +; CHECK-SD-NEXT: str d1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2f64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str d1, [x8, x9, lsl #3] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x double> %a, double %b, i32 %c ret <2 x double> %d @@ -111,25 +85,51 @@ entry: } define <3 x double> @insert_v3f64_c(<3 x double> %a, double %b, i32 %c) { -; CHECK-LABEL: insert_v3f64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: stp q0, q2, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: and x9, x0, #0x3 -; CHECK-NEXT: str d3, [x8, x9, lsl #3] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: ldr d2, [sp, #16] -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1 -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3f64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: stp q0, q2, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: and x9, x0, #0x3 +; CHECK-SD-NEXT: str d3, [x8, x9, lsl #3] +; CHECK-SD-NEXT: ldr q0, [sp] +; CHECK-SD-NEXT: ldr d2, [sp, #16] +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 +; CHECK-SD-NEXT: add sp, sp, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3f64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: stp q0, q2, [sp] +; CHECK-GI-NEXT: str d3, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q2, [sp] +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2 +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x double> %a, double %b, i32 %c ret <3 x double> %d @@ -158,16 +158,35 @@ entry: } define <4 x double> @insert_v4f64_c(<4 x double> %a, double %b, i32 %c) { -; CHECK-LABEL: insert_v4f64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x0, #0x3 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str d2, [x9, x8, lsl #3] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4f64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x0, #0x3 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str d2, [x9, x8, lsl #3] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4f64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: str d2, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x double> %a, double %b, i32 %c ret <4 x double> %d @@ -200,18 +219,31 @@ entry: } define <2 x float> @insert_v2f32_c(<2 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v2f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x0, #2, #1 -; CHECK-NEXT: str s1, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x0, #2, #1 +; CHECK-SD-NEXT: str s1, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str s1, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x float> %a, float %b, i32 %c ret <2 x float> %d @@ -260,17 +292,29 @@ entry: } define <3 x float> @insert_v3f32_c(<3 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v3f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #2, #2 -; CHECK-NEXT: str s1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #2, #2 +; CHECK-SD-NEXT: str s1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str s1, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x float> %a, float %b, i32 %c ret <3 x float> %d @@ -299,17 +343,29 @@ entry: } define <4 x float> @insert_v4f32_c(<4 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v4f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #2, #2 -; CHECK-NEXT: str s1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #2, #2 +; CHECK-SD-NEXT: str s1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str s1, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x float> %a, float %b, i32 %c ret <4 x float> %d @@ -338,16 +394,35 @@ entry: } define <8 x float> @insert_v8f32_c(<8 x float> %a, float %b, i32 %c) { -; CHECK-LABEL: insert_v8f32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x0, #0x7 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str s2, [x9, x8, lsl #2] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8f32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x0, #0x7 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str s2, [x9, x8, lsl #2] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8f32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x7 +; CHECK-GI-NEXT: str s2, [x9, x8, lsl #2] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x float> %a, float %b, i32 %c ret <8 x float> %d @@ -380,18 +455,31 @@ entry: } define <4 x half> @insert_v4f16_c(<4 x half> %a, half %b, i32 %c) { -; CHECK-LABEL: insert_v4f16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x0, #1, #2 -; CHECK-NEXT: str h1, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4f16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x0, #1, #2 +; CHECK-SD-NEXT: str h1, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4f16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str h1, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x half> %a, half %b, i32 %c ret <4 x half> %d @@ -420,17 +508,29 @@ entry: } define <8 x half> @insert_v8f16_c(<8 x half> %a, half %b, i32 %c) { -; CHECK-LABEL: insert_v8f16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #1, #3 -; CHECK-NEXT: str h1, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8f16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #1, #3 +; CHECK-SD-NEXT: str h1, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8f16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: str h1, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x half> %a, half %b, i32 %c ret <8 x half> %d @@ -459,16 +559,35 @@ entry: } define <16 x half> @insert_v16f16_c(<16 x half> %a, half %b, i32 %c) { -; CHECK-LABEL: insert_v16f16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x0, #0xf -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str h2, [x9, x8, lsl #1] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v16f16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x0, #0xf +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str h2, [x9, x8, lsl #1] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v16f16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w0 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0xf +; CHECK-GI-NEXT: str h2, [x9, x8, lsl #1] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <16 x half> %a, half %b, i32 %c ret <16 x half> %d @@ -499,18 +618,33 @@ entry: } define <8 x i8> @insert_v8i8_c(<8 x i8> %a, i8 %b, i32 %c) { -; CHECK-LABEL: insert_v8i8_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfxil x8, x1, #0, #3 -; CHECK-NEXT: strb w0, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8i8_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfxil x8, x1, #0, #3 +; CHECK-SD-NEXT: strb w0, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8i8_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: mul x8, x9, x8 +; CHECK-GI-NEXT: add x9, sp, #8 +; CHECK-GI-NEXT: strb w0, [x9, x8] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x i8> %a, i8 %b, i32 %c ret <8 x i8> %d @@ -537,17 +671,31 @@ entry: } define <16 x i8> @insert_v16i8_c(<16 x i8> %a, i8 %b, i32 %c) { -; CHECK-LABEL: insert_v16i8_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfxil x8, x1, #0, #4 -; CHECK-NEXT: strb w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v16i8_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfxil x8, x1, #0, #4 +; CHECK-SD-NEXT: strb w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v16i8_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0xf +; CHECK-GI-NEXT: mul x8, x9, x8 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: strb w0, [x9, x8] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <16 x i8> %a, i8 %b, i32 %c ret <16 x i8> %d @@ -574,16 +722,37 @@ entry: } define <32 x i8> @insert_v32i8_c(<32 x i8> %a, i8 %b, i32 %c) { -; CHECK-LABEL: insert_v32i8_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0x1f -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: strb w0, [x9, x8] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v32i8_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0x1f +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: strb w0, [x9, x8] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v32i8_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x10, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x1f +; CHECK-GI-NEXT: lsl x9, x8, #1 +; CHECK-GI-NEXT: sub x8, x9, x8 +; CHECK-GI-NEXT: strb w0, [x10, x8] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <32 x i8> %a, i8 %b, i32 %c ret <32 x i8> %d @@ -614,18 +783,31 @@ entry: } define <4 x i16> @insert_v4i16_c(<4 x i16> %a, i16 %b, i32 %c) { -; CHECK-LABEL: insert_v4i16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x1, #1, #2 -; CHECK-NEXT: strh w0, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4i16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x1, #1, #2 +; CHECK-SD-NEXT: strh w0, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4i16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: strh w0, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x i16> %a, i16 %b, i32 %c ret <4 x i16> %d @@ -652,17 +834,29 @@ entry: } define <8 x i16> @insert_v8i16_c(<8 x i16> %a, i16 %b, i32 %c) { -; CHECK-LABEL: insert_v8i16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #1, #3 -; CHECK-NEXT: strh w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8i16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #1, #3 +; CHECK-SD-NEXT: strh w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8i16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: strh w0, [x8, x9, lsl #1] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x i16> %a, i16 %b, i32 %c ret <8 x i16> %d @@ -689,16 +883,35 @@ entry: } define <16 x i16> @insert_v16i16_c(<16 x i16> %a, i16 %b, i32 %c) { -; CHECK-LABEL: insert_v16i16_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0xf -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: strh w0, [x9, x8, lsl #1] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v16i16_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0xf +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: strh w0, [x9, x8, lsl #1] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v16i16_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0xf +; CHECK-GI-NEXT: strh w0, [x9, x8, lsl #1] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <16 x i16> %a, i16 %b, i32 %c ret <16 x i16> %d @@ -729,18 +942,31 @@ entry: } define <2 x i32> @insert_v2i32_c(<2 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v2i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: add x8, sp, #8 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str d0, [sp, #8] -; CHECK-NEXT: bfi x8, x1, #2, #1 -; CHECK-NEXT: str w0, [x8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: add x8, sp, #8 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str d0, [sp, #8] +; CHECK-SD-NEXT: bfi x8, x1, #2, #1 +; CHECK-SD-NEXT: str w0, [x8] +; CHECK-SD-NEXT: ldr d0, [sp, #8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: add x8, sp, #8 +; CHECK-GI-NEXT: str d0, [sp, #8] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str w0, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr d0, [sp, #8] +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x i32> %a, i32 %b, i32 %c ret <2 x i32> %d @@ -789,17 +1015,29 @@ entry: } define <3 x i32> @insert_v3i32_c(<3 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v3i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #2, #2 -; CHECK-NEXT: str w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #2, #2 +; CHECK-SD-NEXT: str w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str w0, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x i32> %a, i32 %b, i32 %c ret <3 x i32> %d @@ -826,17 +1064,29 @@ entry: } define <4 x i32> @insert_v4i32_c(<4 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v4i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #2, #2 -; CHECK-NEXT: str w0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #2, #2 +; CHECK-SD-NEXT: str w0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x3 +; CHECK-GI-NEXT: str w0, [x8, x9, lsl #2] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x i32> %a, i32 %b, i32 %c ret <4 x i32> %d @@ -863,16 +1113,35 @@ entry: } define <8 x i32> @insert_v8i32_c(<8 x i32> %a, i32 %b, i32 %c) { -; CHECK-LABEL: insert_v8i32_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0x7 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str w0, [x9, x8, lsl #2] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v8i32_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0x7 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str w0, [x9, x8, lsl #2] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v8i32_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x7 +; CHECK-GI-NEXT: str w0, [x9, x8, lsl #2] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <8 x i32> %a, i32 %b, i32 %c ret <8 x i32> %d @@ -899,17 +1168,29 @@ entry: } define <2 x i64> @insert_v2i64_c(<2 x i64> %a, i64 %b, i32 %c) { -; CHECK-LABEL: insert_v2i64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x1, #3, #1 -; CHECK-NEXT: str x0, [x8] -; CHECK-NEXT: ldr q0, [sp], #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v2i64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x1, #3, #1 +; CHECK-SD-NEXT: str x0, [x8] +; CHECK-SD-NEXT: ldr q0, [sp], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v2i64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w1 +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x1 +; CHECK-GI-NEXT: str x0, [x8, x9, lsl #3] +; CHECK-GI-NEXT: ldr q0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = insertelement <2 x i64> %a, i64 %b, i32 %c ret <2 x i64> %d @@ -946,25 +1227,51 @@ entry: } define <3 x i64> @insert_v3i64_c(<3 x i64> %a, i64 %b, i32 %c) { -; CHECK-LABEL: insert_v3i64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: stp q0, q2, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: and x9, x1, #0x3 -; CHECK-NEXT: str x0, [x8, x9, lsl #3] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: ldr d2, [sp, #16] -; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1 -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v3i64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: stp q0, q2, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: and x9, x1, #0x3 +; CHECK-SD-NEXT: str x0, [x8, x9, lsl #3] +; CHECK-SD-NEXT: ldr q0, [sp] +; CHECK-SD-NEXT: ldr d2, [sp, #16] +; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1 +; CHECK-SD-NEXT: add sp, sp, #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v3i64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-GI-NEXT: mov v0.d[1], v1.d[0] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: stp q0, q2, [sp] +; CHECK-GI-NEXT: str x0, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q2, [sp] +; CHECK-GI-NEXT: // kill: def $d2 killed $d2 killed $q2 +; CHECK-GI-NEXT: mov d1, v0.d[1] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <3 x i64> %a, i64 %b, i32 %c ret <3 x i64> %d @@ -991,16 +1298,35 @@ entry: } define <4 x i64> @insert_v4i64_c(<4 x i64> %a, i64 %b, i32 %c) { -; CHECK-LABEL: insert_v4i64_c: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1 -; CHECK-NEXT: stp q0, q1, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: and x8, x1, #0x3 -; CHECK-NEXT: mov x9, sp -; CHECK-NEXT: str x0, [x9, x8, lsl #3] -; CHECK-NEXT: ldp q0, q1, [sp], #32 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: insert_v4i64_c: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: stp q0, q1, [sp, #-32]! +; CHECK-SD-NEXT: .cfi_def_cfa_offset 32 +; CHECK-SD-NEXT: and x8, x1, #0x3 +; CHECK-SD-NEXT: mov x9, sp +; CHECK-SD-NEXT: str x0, [x9, x8, lsl #3] +; CHECK-SD-NEXT: ldp q0, q1, [sp], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: insert_v4i64_c: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill +; CHECK-GI-NEXT: sub x9, sp, #48 +; CHECK-GI-NEXT: mov x29, sp +; CHECK-GI-NEXT: and sp, x9, #0xffffffffffffffe0 +; CHECK-GI-NEXT: .cfi_def_cfa w29, 16 +; CHECK-GI-NEXT: .cfi_offset w30, -8 +; CHECK-GI-NEXT: .cfi_offset w29, -16 +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: mov x9, sp +; CHECK-GI-NEXT: stp q0, q1, [sp] +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: str x0, [x9, x8, lsl #3] +; CHECK-GI-NEXT: ldp q0, q1, [sp] +; CHECK-GI-NEXT: mov sp, x29 +; CHECK-GI-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload +; CHECK-GI-NEXT: ret entry: %d = insertelement <4 x i64> %a, i64 %b, i32 %c ret <4 x i64> %d diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir index b49f51609851..0a2b3da7f7d9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir @@ -28,16 +28,13 @@ tracksRegLiveness: true body: | bb.0: ; CHECK-LABEL: name: test_ptradd_crash__offset_wider - ; CHECK: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 3 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C1]](s64) - ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[SHL]](s64) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12 + ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1) ; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32) ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0 %1:_(p1) = G_CONSTANT i64 0 - %3:_(s128) = G_CONSTANT i128 3 + %3:_(s32) = G_CONSTANT i32 3 %0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1) %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3 $sgpr0 = COPY %2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll index ae0556c1b21f..c509cf4b1bf3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll @@ -48,10 +48,10 @@ define <2 x ptr addrspace(7)> @gep_vector_splat(<2 x ptr addrspace(7)> %ptrs, i6 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11 ; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32) ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x p8>) = G_IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF - ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV2]](s64), [[C]](s64) + ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV2]](s64), [[C]](s32) ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[SHUF]](<2 x s64>) ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD [[BUILD_VECTOR1]], [[TRUNC]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir index af03b3e20ecb..93155335e208 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir @@ -294,7 +294,8 @@ body: | ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32) %0:_(<2 x s1>) = G_IMPLICIT_DEF %1:_(s1) = G_CONSTANT i1 false - %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1 + %4:_(s32) = G_ZEXT %1 + %2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %4 %3:_(s32) = G_ANYEXT %2 $vgpr0 = COPY %3 ... @@ -948,7 +949,8 @@ body: | ; CHECK-NEXT: $vgpr0 = COPY [[EVEC]](s32) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(s64) = COPY $vgpr2_vgpr3 - %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1 + %3:_(s32) = G_TRUNC %1 + %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3 $vgpr0 = COPY %2 ... --- diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir index b5dca793bc50..805890a75d40 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir @@ -18,8 +18,9 @@ body: | %7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %6(s32), %5(s32) %8:_(s1) = G_CONSTANT i1 1 - %9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s1) - %10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %8(s1) + %11:_(s32) = G_ZEXT %8 + %9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %11(s32) + %10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %11(s32) SI_RETURN ... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir index 1dcb2bf3e42a..b57dd396ae35 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir @@ -82,7 +82,8 @@ body: | %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(s32) = COPY $vgpr2 %2:_(s64) = COPY $vgpr3_vgpr4 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 + %4:_(s32) = G_TRUNC %2 + %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 $vgpr0_vgpr1 = COPY %3 ... @@ -105,7 +106,8 @@ body: | %0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 %1:_(s32) = COPY $vgpr16 %2:_(s64) = COPY $vgpr17_vgpr18 - %3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 + %4:_(s32) = G_TRUNC %2 + %3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4 S_ENDPGM 0, implicit %3 ... @@ -131,28 +133,6 @@ body: | S_ENDPGM 0, implicit %3 ... ---- -name: insert_vector_elt_0_v2s32_s8 - -body: | - bb.0: - liveins: $vgpr0_vgpr1, $vgpr2 - - ; CHECK-LABEL: name: insert_vector_elt_0_v2s32_s8 - ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2 - ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[UV1]](s32) - ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) - %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 - %1:_(s32) = COPY $vgpr2 - %2:_(s8) = G_CONSTANT i8 0 - %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2 - $vgpr0_vgpr1 = COPY %3 -... - --- name: insert_vector_elt_0_v2i8_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll index c23d1e7c7099..a1347d2306ca 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll @@ -18,8 +18,8 @@ define @insertelement_nxv1i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 0, i32 0 @@ -40,8 +40,8 @@ define @insertelement_nxv1i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 -1, i32 0 @@ -70,7 +70,8 @@ define @insertelement_nxv1i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 %x, i32 %idx @@ -91,8 +92,8 @@ define @insertelement_nxv2i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 0, i32 1 @@ -113,8 +114,8 @@ define @insertelement_nxv2i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 -1, i32 0 @@ -143,7 +144,8 @@ define @insertelement_nxv2i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 %x, i32 %idx @@ -164,8 +166,8 @@ define @insertelement_nxv4i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 0, i32 2 @@ -186,8 +188,8 @@ define @insertelement_nxv4i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 -1, i32 0 @@ -214,8 +216,8 @@ define @insertelement_nxv4i1_2(i1 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 %x, i32 0 @@ -236,8 +238,8 @@ define @insertelement_nxv8i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 0, i32 0 @@ -258,8 +260,8 @@ define @insertelement_nxv8i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 -1, i32 0 @@ -288,7 +290,8 @@ define @insertelement_nxv8i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 %x, i32 %idx @@ -309,8 +312,8 @@ define @insertelement_nxv16i1_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 0, i32 15 @@ -331,8 +334,8 @@ define @insertelement_nxv16i1_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 -1, i32 0 @@ -361,7 +364,8 @@ define @insertelement_nxv16i1_2(i1 %x, i32 %idx) { ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[TRUNC1]](s32) + ; RV64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement poison, i1 %x, i32 %idx @@ -388,8 +392,8 @@ define @insertelement_nxv4i1_3( %v, i1 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s64) ; RV64-NEXT: $v0 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v0 %a = insertelement %v, i1 %x, i32 0 @@ -410,8 +414,8 @@ define @insertelement_nxv1i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 0, i32 0 @@ -432,8 +436,8 @@ define @insertelement_nxv1i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 -1, i32 0 @@ -460,8 +464,8 @@ define @insertelement_nxv1i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 %x, i32 0 @@ -482,8 +486,8 @@ define @insertelement_nxv2i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 0, i32 0 @@ -504,8 +508,8 @@ define @insertelement_nxv2i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 -1, i32 0 @@ -532,8 +536,8 @@ define @insertelement_nxv2i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 %x, i32 0 @@ -554,8 +558,8 @@ define @insertelement_nxv4i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 0, i32 0 @@ -576,8 +580,8 @@ define @insertelement_nxv4i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 -1, i32 0 @@ -604,8 +608,8 @@ define @insertelement_nxv4i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 %x, i32 0 @@ -626,8 +630,8 @@ define @insertelement_nxv8i8_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 0, i32 0 @@ -648,8 +652,8 @@ define @insertelement_nxv8i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 -1, i32 0 @@ -676,8 +680,8 @@ define @insertelement_nxv8i8_2(i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i8 %x, i32 0 @@ -689,8 +693,8 @@ define @insertelement_nxv16i8_0() { ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0 - ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) ; RV32-NEXT: $v8m2 = COPY [[IVEC]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -720,8 +724,8 @@ define @insertelement_nxv16i8_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i8 -1, i32 0 @@ -739,7 +743,8 @@ define @insertelement_nxv16i8_2(i8 %x, i64 %idx) { ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32) ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[MV]](s64) + ; RV32-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64) + ; RV32-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[TRUNC1]](s32) ; RV32-NEXT: $v8m2 = COPY [[IVEC]]() ; RV32-NEXT: PseudoRET implicit $v8m2 ; @@ -778,8 +783,8 @@ define @insertelement_nxv4i8_3( %v, i8 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement %v, i8 %x, i32 0 @@ -800,8 +805,8 @@ define @insertelement_nxv1i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 0, i32 0 @@ -822,8 +827,8 @@ define @insertelement_nxv1i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 -1, i32 0 @@ -850,8 +855,8 @@ define @insertelement_nxv1i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 %x, i32 0 @@ -863,8 +868,8 @@ define @insertelement_nxv2i16_0() { ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; RV32-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) + ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; RV32-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) ; RV32-NEXT: $v8 = COPY [[IVEC]]() ; RV32-NEXT: PseudoRET implicit $v8 ; @@ -894,8 +899,8 @@ define @insertelement_nxv2i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 -1, i32 0 @@ -922,8 +927,8 @@ define @insertelement_nxv2i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 %x, i32 0 @@ -944,8 +949,8 @@ define @insertelement_nxv4i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 0, i32 0 @@ -966,8 +971,8 @@ define @insertelement_nxv4i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 -1, i32 0 @@ -994,8 +999,8 @@ define @insertelement_nxv4i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i16 %x, i32 0 @@ -1016,8 +1021,8 @@ define @insertelement_nxv8i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i16 0, i32 0 @@ -1038,8 +1043,8 @@ define @insertelement_nxv8i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i16 -1, i32 0 @@ -1066,8 +1071,8 @@ define @insertelement_nxv8i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i16 %x, i32 0 @@ -1088,8 +1093,8 @@ define @insertelement_nxv16i16_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i16 0, i32 0 @@ -1110,8 +1115,8 @@ define @insertelement_nxv16i16_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i16 -1, i32 0 @@ -1138,8 +1143,8 @@ define @insertelement_nxv16i16_2(i16 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i16 %x, i32 0 @@ -1166,8 +1171,8 @@ define @insertelement_nxv4i16( %v, i16 %x) ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement %v, i16 %x, i32 0 @@ -1187,7 +1192,8 @@ define @insertelement_nxv1i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i32 0, i32 0 @@ -1208,8 +1214,8 @@ define @insertelement_nxv1i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i32 -1, i32 0 @@ -1235,8 +1241,8 @@ define @insertelement_nxv1i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i32 %x, i32 0 @@ -1256,7 +1262,8 @@ define @insertelement_nxv2i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i32 0, i32 0 @@ -1277,8 +1284,8 @@ define @insertelement_nxv2i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i32 -1, i32 0 @@ -1304,8 +1311,8 @@ define @insertelement_nxv2i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i32 %x, i32 0 @@ -1325,7 +1332,8 @@ define @insertelement_nxv4i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i32 0, i32 0 @@ -1346,8 +1354,8 @@ define @insertelement_nxv4i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i32 -1, i32 0 @@ -1373,8 +1381,8 @@ define @insertelement_nxv4i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i32 %x, i32 0 @@ -1394,7 +1402,8 @@ define @insertelement_nxv8i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i32 0, i32 0 @@ -1415,8 +1424,8 @@ define @insertelement_nxv8i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i32 -1, i32 0 @@ -1442,8 +1451,8 @@ define @insertelement_nxv8i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i32 %x, i32 0 @@ -1463,7 +1472,8 @@ define @insertelement_nxv16i32_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement poison, i32 0, i32 0 @@ -1484,8 +1494,8 @@ define @insertelement_nxv16i32_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement poison, i32 -1, i32 0 @@ -1511,8 +1521,8 @@ define @insertelement_nxv16i32_2(i32 %x) { ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement poison, i32 %x, i32 0 @@ -1538,8 +1548,8 @@ define @insertelement_nxv4i32( %v, i32 %x) ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement %v, i32 %x, i32 0 @@ -1560,8 +1570,7 @@ define @insertelement_nxv1i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i64 0, i32 0 @@ -1582,8 +1591,8 @@ define @insertelement_nxv1i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i64 -1, i32 0 @@ -1610,8 +1619,8 @@ define @insertelement_nxv1i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8 %a = insertelement poison, i64 %x, i32 0 @@ -1632,8 +1641,7 @@ define @insertelement_nxv2i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i64 0, i32 0 @@ -1654,8 +1662,8 @@ define @insertelement_nxv2i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i64 -1, i32 0 @@ -1682,8 +1690,8 @@ define @insertelement_nxv2i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8m2 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m2 %a = insertelement poison, i64 %x, i32 0 @@ -1704,8 +1712,7 @@ define @insertelement_nxv4i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i64 0, i32 0 @@ -1726,8 +1733,8 @@ define @insertelement_nxv4i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i64 -1, i32 0 @@ -1754,8 +1761,8 @@ define @insertelement_nxv4i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement poison, i64 %x, i32 0 @@ -1776,8 +1783,7 @@ define @insertelement_nxv8i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement poison, i64 0, i32 0 @@ -1798,8 +1804,8 @@ define @insertelement_nxv8i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement poison, i64 -1, i32 0 @@ -1826,8 +1832,8 @@ define @insertelement_nxv8i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: $v8m8 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m8 %a = insertelement poison, i64 %x, i32 0 @@ -1850,8 +1856,7 @@ define @insertelement_nxv16i64_0() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64) ; RV64-NEXT: [[UV:%[0-9]+]]:_(), [[UV1:%[0-9]+]]:_() = G_UNMERGE_VALUES [[IVEC]]() ; RV64-NEXT: $v8m8 = COPY [[UV]]() ; RV64-NEXT: $v16m8 = COPY [[UV1]]() @@ -1876,8 +1881,8 @@ define @insertelement_nxv16i64_1() { ; RV64: bb.1 (%ir-block.0): ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 - ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32) + ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64) ; RV64-NEXT: [[UV:%[0-9]+]]:_(), [[UV1:%[0-9]+]]:_() = G_UNMERGE_VALUES [[IVEC]]() ; RV64-NEXT: $v8m8 = COPY [[UV]]() ; RV64-NEXT: $v16m8 = COPY [[UV1]]() @@ -1908,8 +1913,8 @@ define @insertelement_nxv16i64_2(i64 %x) { ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64) ; RV64-NEXT: [[UV:%[0-9]+]]:_(), [[UV1:%[0-9]+]]:_() = G_UNMERGE_VALUES [[IVEC]]() ; RV64-NEXT: $v8m8 = COPY [[UV]]() ; RV64-NEXT: $v16m8 = COPY [[UV1]]() @@ -1938,8 +1943,8 @@ define @insertelement_nxv4i64( %v, i64 %x) ; RV64-NEXT: {{ $}} ; RV64-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s64), [[C]](s32) + ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; RV64-NEXT: [[IVEC:%[0-9]+]]:_() = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s64), [[C]](s64) ; RV64-NEXT: $v8m4 = COPY [[IVEC]]() ; RV64-NEXT: PseudoRET implicit $v8m4 %a = insertelement %v, i64 %x, i32 0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll index df7778899b0d..7ea67073bc28 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll @@ -8,8 +8,8 @@ define @shufflevector_nxv1i1_0() { ; RV32-LABEL: name: shufflevector_nxv1i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -30,8 +30,8 @@ define @shufflevector_nxv1i1_1() { ; RV32-LABEL: name: shufflevector_nxv1i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -54,8 +54,8 @@ define @shufflevector_nxv1i1_2( %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -78,8 +78,8 @@ define @shufflevector_nxv2i1_0() { ; RV32-LABEL: name: shufflevector_nxv2i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -100,8 +100,8 @@ define @shufflevector_nxv2i1_1() { ; RV32-LABEL: name: shufflevector_nxv2i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -124,8 +124,8 @@ define @shufflevector_nxv2i1_2( %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -148,8 +148,8 @@ define @shufflevector_nxv4i1_0() { ; RV32-LABEL: name: shufflevector_nxv4i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -170,8 +170,8 @@ define @shufflevector_nxv4i1_1() { ; RV32-LABEL: name: shufflevector_nxv4i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -194,8 +194,8 @@ define @shufflevector_nxv4i1_2( %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -218,8 +218,8 @@ define @shufflevector_nxv8i1_0() { ; RV32-LABEL: name: shufflevector_nxv8i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -240,8 +240,8 @@ define @shufflevector_nxv8i1_1() { ; RV32-LABEL: name: shufflevector_nxv8i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -264,8 +264,8 @@ define @shufflevector_nxv8i1_2( %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -288,8 +288,8 @@ define @shufflevector_nxv16i1_0() { ; RV32-LABEL: name: shufflevector_nxv16i1_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -310,8 +310,8 @@ define @shufflevector_nxv16i1_1() { ; RV32-LABEL: name: shufflevector_nxv16i1_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -334,8 +334,8 @@ define @shufflevector_nxv16i1_2( %a) { ; RV32-NEXT: liveins: $v0 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v0 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s1) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s1) ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v0 @@ -358,8 +358,8 @@ define @shufflevector_nxv1i8_0() { ; RV32-LABEL: name: shufflevector_nxv1i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -380,8 +380,8 @@ define @shufflevector_nxv1i8_1() { ; RV32-LABEL: name: shufflevector_nxv1i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -404,8 +404,8 @@ define @shufflevector_nxv1i8_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -428,8 +428,8 @@ define @shufflevector_nxv2i8_0() { ; RV32-LABEL: name: shufflevector_nxv2i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -450,8 +450,8 @@ define @shufflevector_nxv2i8_1() { ; RV32-LABEL: name: shufflevector_nxv2i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -474,8 +474,8 @@ define @shufflevector_nxv2i8_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -498,8 +498,8 @@ define @shufflevector_nxv4i8_0() { ; RV32-LABEL: name: shufflevector_nxv4i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -520,8 +520,8 @@ define @shufflevector_nxv4i8_1() { ; RV32-LABEL: name: shufflevector_nxv4i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -544,8 +544,8 @@ define @shufflevector_nxv4i8_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -568,8 +568,8 @@ define @shufflevector_nxv8i8_0() { ; RV32-LABEL: name: shufflevector_nxv8i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -590,8 +590,8 @@ define @shufflevector_nxv8i8_1() { ; RV32-LABEL: name: shufflevector_nxv8i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -614,8 +614,8 @@ define @shufflevector_nxv8i8_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -638,8 +638,8 @@ define @shufflevector_nxv16i8_0() { ; RV32-LABEL: name: shufflevector_nxv16i8_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -660,8 +660,8 @@ define @shufflevector_nxv16i8_1() { ; RV32-LABEL: name: shufflevector_nxv16i8_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -684,8 +684,8 @@ define @shufflevector_nxv16i8_2( %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s8) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -708,8 +708,8 @@ define @shufflevector_nxv1i16_0() { ; RV32-LABEL: name: shufflevector_nxv1i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -730,8 +730,8 @@ define @shufflevector_nxv1i16_1() { ; RV32-LABEL: name: shufflevector_nxv1i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -754,8 +754,8 @@ define @shufflevector_nxv1i16_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -778,8 +778,8 @@ define @shufflevector_nxv2i16_0() { ; RV32-LABEL: name: shufflevector_nxv2i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -800,8 +800,8 @@ define @shufflevector_nxv2i16_1() { ; RV32-LABEL: name: shufflevector_nxv2i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -824,8 +824,8 @@ define @shufflevector_nxv2i16_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -848,8 +848,8 @@ define @shufflevector_nxv4i16_0() { ; RV32-LABEL: name: shufflevector_nxv4i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -870,8 +870,8 @@ define @shufflevector_nxv4i16_1() { ; RV32-LABEL: name: shufflevector_nxv4i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -894,8 +894,8 @@ define @shufflevector_nxv4i16_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -918,8 +918,8 @@ define @shufflevector_nxv8i16_0() { ; RV32-LABEL: name: shufflevector_nxv8i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -940,8 +940,8 @@ define @shufflevector_nxv8i16_1() { ; RV32-LABEL: name: shufflevector_nxv8i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -964,8 +964,8 @@ define @shufflevector_nxv8i16_2( %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -988,8 +988,8 @@ define @shufflevector_nxv16i16_0() { ; RV32-LABEL: name: shufflevector_nxv16i16_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1010,8 +1010,8 @@ define @shufflevector_nxv16i16_1() { ; RV32-LABEL: name: shufflevector_nxv16i16_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1034,8 +1034,8 @@ define @shufflevector_nxv16i16_2( %a) { ; RV32-NEXT: liveins: $v8m4 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s16) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1058,8 +1058,8 @@ define @shufflevector_nxv1i32_0() { ; RV32-LABEL: name: shufflevector_nxv1i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1080,8 +1080,8 @@ define @shufflevector_nxv1i32_1() { ; RV32-LABEL: name: shufflevector_nxv1i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1104,8 +1104,8 @@ define @shufflevector_nxv1i32_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1128,8 +1128,8 @@ define @shufflevector_nxv2i32_0() { ; RV32-LABEL: name: shufflevector_nxv2i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1150,8 +1150,8 @@ define @shufflevector_nxv2i32_1() { ; RV32-LABEL: name: shufflevector_nxv2i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1174,8 +1174,8 @@ define @shufflevector_nxv2i32_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1198,8 +1198,8 @@ define @shufflevector_nxv4i32_0() { ; RV32-LABEL: name: shufflevector_nxv4i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1220,8 +1220,8 @@ define @shufflevector_nxv4i32_1() { ; RV32-LABEL: name: shufflevector_nxv4i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1244,8 +1244,8 @@ define @shufflevector_nxv4i32_2( %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1268,8 +1268,8 @@ define @shufflevector_nxv8i32_0() { ; RV32-LABEL: name: shufflevector_nxv8i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1290,8 +1290,8 @@ define @shufflevector_nxv8i32_1() { ; RV32-LABEL: name: shufflevector_nxv8i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1314,8 +1314,8 @@ define @shufflevector_nxv8i32_2( %a) { ; RV32-NEXT: liveins: $v8m4 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1338,8 +1338,8 @@ define @shufflevector_nxv16i32_0() { ; RV32-LABEL: name: shufflevector_nxv16i32_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1360,8 +1360,8 @@ define @shufflevector_nxv16i32_1() { ; RV32-LABEL: name: shufflevector_nxv16i32_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1384,8 +1384,8 @@ define @shufflevector_nxv16i32_2( %a) { ; RV32-NEXT: liveins: $v8m8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s32) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1408,8 +1408,8 @@ define @shufflevector_nxv1i64_0() { ; RV32-LABEL: name: shufflevector_nxv1i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1430,8 +1430,8 @@ define @shufflevector_nxv1i64_1() { ; RV32-LABEL: name: shufflevector_nxv1i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1454,8 +1454,8 @@ define @shufflevector_nxv1i64_2( %a) { ; RV32-NEXT: liveins: $v8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8 @@ -1478,8 +1478,8 @@ define @shufflevector_nxv2i64_0() { ; RV32-LABEL: name: shufflevector_nxv2i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1500,8 +1500,8 @@ define @shufflevector_nxv2i64_1() { ; RV32-LABEL: name: shufflevector_nxv2i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1524,8 +1524,8 @@ define @shufflevector_nxv2i64_2( %a) { ; RV32-NEXT: liveins: $v8m2 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m2 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m2 @@ -1548,8 +1548,8 @@ define @shufflevector_nxv4i64_0() { ; RV32-LABEL: name: shufflevector_nxv4i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1570,8 +1570,8 @@ define @shufflevector_nxv4i64_1() { ; RV32-LABEL: name: shufflevector_nxv4i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1594,8 +1594,8 @@ define @shufflevector_nxv4i64_2( %a) { ; RV32-NEXT: liveins: $v8m4 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m4 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m4 @@ -1618,8 +1618,8 @@ define @shufflevector_nxv8i64_0() { ; RV32-LABEL: name: shufflevector_nxv8i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1640,8 +1640,8 @@ define @shufflevector_nxv8i64_1() { ; RV32-LABEL: name: shufflevector_nxv8i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1664,8 +1664,8 @@ define @shufflevector_nxv8i64_2( %a) { ; RV32-NEXT: liveins: $v8m8 ; RV32-NEXT: {{ $}} ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m8 - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]]() ; RV32-NEXT: PseudoRET implicit $v8m8 @@ -1688,8 +1688,8 @@ define @shufflevector_nxv16i64_0() { ; RV32-LABEL: name: shufflevector_nxv16i64_0 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: [[UV:%[0-9]+]]:_(), [[UV1:%[0-9]+]]:_() = G_UNMERGE_VALUES [[SPLAT_VECTOR]]() ; RV32-NEXT: $v8m8 = COPY [[UV]]() @@ -1714,8 +1714,8 @@ define @shufflevector_nxv16i64_1() { ; RV32-LABEL: name: shufflevector_nxv16i64_1 ; RV32: bb.1 (%ir-block.0): ; RV32-NEXT: [[DEF:%[0-9]+]]:_() = G_IMPLICIT_DEF - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[DEF]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: [[UV:%[0-9]+]]:_(), [[UV1:%[0-9]+]]:_() = G_UNMERGE_VALUES [[SPLAT_VECTOR]]() ; RV32-NEXT: $v8m8 = COPY [[UV]]() @@ -1744,8 +1744,8 @@ define @shufflevector_nxv16i64_2( %a) { ; RV32-NEXT: [[COPY:%[0-9]+]]:_() = COPY $v8m8 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_() = COPY $v16m8 ; RV32-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_() = G_CONCAT_VECTORS [[COPY]](), [[COPY1]]() - ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 - ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS]](), [[C]](s64) + ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; RV32-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[CONCAT_VECTORS]](), [[C]](s32) ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_() = G_SPLAT_VECTOR [[EVEC]](s64) ; RV32-NEXT: [[UV:%[0-9]+]]:_(), [[UV1:%[0-9]+]]:_() = G_UNMERGE_VALUES [[SPLAT_VECTOR]]() ; RV32-NEXT: $v8m8 = COPY [[UV]]() -- GitLab From 9fd2e2c2fd0dbd5d11a5899bd6bb4db0fd3f2c35 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 8 Apr 2024 08:53:27 +0100 Subject: [PATCH 120/695] [DAG][AArch64] Support masked loads/stores with nontemporal flags (#87608) SVE has some non-temporal masked loads and stores. The metadata coming from the nodes is not copied to the MMO at the moment though, meaning it will generate a normal instruction. This patch ensures that the right flags are set if the instruction has non-temporal metadata. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 +++--- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 12 ++++++++++-- .../CodeGen/AArch64/sve-nontemporal-masked-ldst.ll | 11 ++++++----- 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f20080c8f108..8fe074666a3d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -11824,8 +11824,8 @@ SDValue DAGCombiner::visitMSTORE(SDNode *N) { !MST->isCompressingStore() && !MST->isTruncatingStore()) return DAG.getStore(MST->getChain(), SDLoc(N), MST->getValue(), MST->getBasePtr(), MST->getPointerInfo(), - MST->getOriginalAlign(), MachineMemOperand::MOStore, - MST->getAAInfo()); + MST->getOriginalAlign(), + MST->getMemOperand()->getFlags(), MST->getAAInfo()); // Try transforming N to an indexed store. if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) @@ -11962,7 +11962,7 @@ SDValue DAGCombiner::visitMLOAD(SDNode *N) { SDValue NewLd = DAG.getLoad( N->getValueType(0), SDLoc(N), MLD->getChain(), MLD->getBasePtr(), MLD->getPointerInfo(), MLD->getOriginalAlign(), - MachineMemOperand::MOLoad, MLD->getAAInfo(), MLD->getRanges()); + MLD->getMemOperand()->getFlags(), MLD->getAAInfo(), MLD->getRanges()); return CombineTo(N, NewLd, NewLd.getValue(1)); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 618bdee7f405..4ba27157ec1c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -4754,8 +4754,12 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I, EVT VT = Src0.getValueType(); + auto MMOFlags = MachineMemOperand::MOStore; + if (I.hasMetadata(LLVMContext::MD_nontemporal)) + MMOFlags |= MachineMemOperand::MONonTemporal; + MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( - MachinePointerInfo(PtrOperand), MachineMemOperand::MOStore, + MachinePointerInfo(PtrOperand), MMOFlags, LocationSize::beforeOrAfterPointer(), Alignment, I.getAAMetadata()); SDValue StoreNode = DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO, @@ -4924,8 +4928,12 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { SDValue InChain = AddToChain ? DAG.getRoot() : DAG.getEntryNode(); + auto MMOFlags = MachineMemOperand::MOLoad; + if (I.hasMetadata(LLVMContext::MD_nontemporal)) + MMOFlags |= MachineMemOperand::MONonTemporal; + MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand( - MachinePointerInfo(PtrOperand), MachineMemOperand::MOLoad, + MachinePointerInfo(PtrOperand), MMOFlags, LocationSize::beforeOrAfterPointer(), Alignment, AAInfo, Ranges); SDValue Load = diff --git a/llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll b/llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll index bcfc7b336f3e..bcb878ad744b 100644 --- a/llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll +++ b/llvm/test/CodeGen/AArch64/sve-nontemporal-masked-ldst.ll @@ -9,7 +9,7 @@ define <4 x i32> @masked_load_v4i32(ptr %a, <4 x i1> %mask) nounwind { ; CHECK-NEXT: shl v0.4s, v0.4s, #31 ; CHECK-NEXT: cmlt v0.4s, v0.4s, #0 ; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0 -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] +; CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret %load = call <4 x i32> @llvm.masked.load.v4i32(ptr %a, i32 1, <4 x i1> %mask, <4 x i32> undef), !nontemporal !0 @@ -25,7 +25,7 @@ define void @masked_store_v4i32(<4 x i32> %x, ptr %a, <4 x i1> %mask) nounwind { ; CHECK-NEXT: shl v1.4s, v1.4s, #31 ; CHECK-NEXT: cmlt v1.4s, v1.4s, #0 ; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #0 -; CHECK-NEXT: st1w { z0.s }, p0, [x0] +; CHECK-NEXT: stnt1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret call void @llvm.masked.store.v4i32.p0(<4 x i32> %x, ptr %a, i32 1, <4 x i1> %mask), !nontemporal !0 ret void @@ -43,7 +43,8 @@ define <4 x i32> @load_v4i32(ptr %a) nounwind { define void @store_v4i32(<4 x i32> %x, ptr %a) nounwind { ; CHECK-LABEL: store_v4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: mov d1, v0.d[1] +; CHECK-NEXT: stnp d0, d1, [x0] ; CHECK-NEXT: ret call void @llvm.masked.store.v4i32.p0(<4 x i32> %x, ptr %a, i32 1, <4 x i1> ), !nontemporal !0 ret void @@ -52,7 +53,7 @@ define void @store_v4i32(<4 x i32> %x, ptr %a) nounwind { define @masked_load_nxv4i32(ptr %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] +; CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0] ; CHECK-NEXT: ret %load = call @llvm.masked.load.nxv4i32(ptr %a, i32 1, %mask, undef), !nontemporal !0 ret %load @@ -61,7 +62,7 @@ define @masked_load_nxv4i32(ptr %a, %mask) define void @masked_store_nxv4i32( %x, ptr %a, %mask) nounwind { ; CHECK-LABEL: masked_store_nxv4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: st1w { z0.s }, p0, [x0] +; CHECK-NEXT: stnt1w { z0.s }, p0, [x0] ; CHECK-NEXT: ret call void @llvm.masked.store.nxv4i32.p0( %x, ptr %a, i32 1, %mask), !nontemporal !0 ret void -- GitLab From 81a7b6454e195f2051b76d9e5b1f0c430df0f502 Mon Sep 17 00:00:00 2001 From: Billy Zhu Date: Mon, 8 Apr 2024 01:09:54 -0700 Subject: [PATCH 121/695] [MLIR][LLVM] Recursion importer handle repeated self-references (#87295) Followup to this discussion: https://github.com/llvm/llvm-project/pull/80251#discussion_r1535599920. The previous debug importer was correct but inefficient. For cases with mutual recursion that contain more than one back-edge, each back-edge would result in a new translated instance. This is because the previous implementation never caches any translated result with unbounded self-references. This means all translation inside a recursive context is performed from scratch, which will incur repeated run-time cost as well as repeated attribute sub-trees in the translated IR (differing only in their `recId`s). This PR refactors the importer to handle caching inside a recursive context. - In the presence of unbound self-refs, the translation result is cached in a separate cache that keeps track of the set of dependent unbound self-refs. - A dependent cache entry is valid only when all the unbound self-refs are in scope. Whenever a cached entry goes out of scope, it will be removed the next time it is looked up. --- mlir/lib/Target/LLVMIR/DebugImporter.cpp | 188 +++++++++++++------ mlir/lib/Target/LLVMIR/DebugImporter.h | 105 +++++++++-- mlir/lib/Target/LLVMIR/DebugTranslation.cpp | 13 +- mlir/test/Target/LLVMIR/Import/debug-info.ll | 143 ++++++++++++++ mlir/test/Target/LLVMIR/llvmir-debug.mlir | 28 +++ 5 files changed, 398 insertions(+), 79 deletions(-) diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index 779ad26fc847..3dc2d4e3a750 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -13,6 +13,7 @@ #include "mlir/IR/Location.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/ScopeExit.h" +#include "llvm/ADT/SetOperations.h" #include "llvm/ADT/TypeSwitch.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/Constants.h" @@ -25,6 +26,10 @@ using namespace mlir; using namespace mlir::LLVM; using namespace mlir::LLVM::detail; +DebugImporter::DebugImporter(ModuleOp mlirModule) + : recursionPruner(mlirModule.getContext()), + context(mlirModule.getContext()), mlirModule(mlirModule) {} + Location DebugImporter::translateFuncLocation(llvm::Function *func) { llvm::DISubprogram *subprogram = func->getSubprogram(); if (!subprogram) @@ -246,42 +251,13 @@ DINodeAttr DebugImporter::translate(llvm::DINode *node) { if (DINodeAttr attr = nodeToAttr.lookup(node)) return attr; - // If the node type is capable of being recursive, check if it's seen before. - auto recSelfCtor = getRecSelfConstructor(node); - if (recSelfCtor) { - // If a cyclic dependency is detected since the same node is being traversed - // twice, emit a recursive self type, and mark the duplicate node on the - // translationStack so it can emit a recursive decl type. - auto [iter, inserted] = translationStack.try_emplace(node, nullptr); - if (!inserted) { - // The original node may have already been assigned a recursive ID from - // a different self-reference. Use that if possible. - DistinctAttr recId = iter->second; - if (!recId) { - recId = DistinctAttr::create(UnitAttr::get(context)); - iter->second = recId; - } - unboundRecursiveSelfRefs.back().insert(recId); - return cast(recSelfCtor(recId)); - } - } - - unboundRecursiveSelfRefs.emplace_back(); - - auto guard = llvm::make_scope_exit([&]() { - if (recSelfCtor) - translationStack.pop_back(); + // Register with the recursive translator. If it can be handled without + // recursing into it, return the result immediately. + if (DINodeAttr attr = recursionPruner.pruneOrPushTranslationStack(node)) + return attr; - // Copy unboundRecursiveSelfRefs down to the previous level. - if (unboundRecursiveSelfRefs.size() == 1) - assert(unboundRecursiveSelfRefs.back().empty() && - "internal error: unbound recursive self reference at top level."); - else - unboundRecursiveSelfRefs[unboundRecursiveSelfRefs.size() - 2].insert( - unboundRecursiveSelfRefs.back().begin(), - unboundRecursiveSelfRefs.back().end()); - unboundRecursiveSelfRefs.pop_back(); - }); + auto guard = llvm::make_scope_exit( + [&]() { recursionPruner.popTranslationStack(node); }); // Convert the debug metadata if possible. auto translateNode = [this](llvm::DINode *node) -> DINodeAttr { @@ -318,22 +294,130 @@ DINodeAttr DebugImporter::translate(llvm::DINode *node) { return nullptr; }; if (DINodeAttr attr = translateNode(node)) { - // If this node was marked as recursive, set its recId. - if (auto recType = dyn_cast(attr)) { - if (DistinctAttr recId = translationStack.lookup(node)) { - attr = cast(recType.withRecId(recId)); - // Remove the unbound recursive ID from the set of unbound self - // references in the translation stack. - unboundRecursiveSelfRefs.back().erase(recId); + auto [result, isSelfContained] = + recursionPruner.finalizeTranslation(node, attr); + // Only cache fully self-contained nodes. + if (isSelfContained) + nodeToAttr.try_emplace(node, result); + return result; + } + return nullptr; +} + +//===----------------------------------------------------------------------===// +// RecursionPruner +//===----------------------------------------------------------------------===// + +/// Get the `getRecSelf` constructor for the translated type of `node` if its +/// translated DITypeAttr supports recursion. Otherwise, returns nullptr. +static function_ref +getRecSelfConstructor(llvm::DINode *node) { + using CtorType = function_ref; + return TypeSwitch(node) + .Case([&](llvm::DICompositeType *) { + return CtorType(DICompositeTypeAttr::getRecSelf); + }) + .Default(CtorType()); +} + +DINodeAttr DebugImporter::RecursionPruner::pruneOrPushTranslationStack( + llvm::DINode *node) { + // If the node type is capable of being recursive, check if it's seen + // before. + auto recSelfCtor = getRecSelfConstructor(node); + if (recSelfCtor) { + // If a cyclic dependency is detected since the same node is being + // traversed twice, emit a recursive self type, and mark the duplicate + // node on the translationStack so it can emit a recursive decl type. + auto [iter, inserted] = translationStack.try_emplace(node); + if (!inserted) { + // The original node may have already been assigned a recursive ID from + // a different self-reference. Use that if possible. + DIRecursiveTypeAttrInterface recSelf = iter->second.recSelf; + if (!recSelf) { + DistinctAttr recId = nodeToRecId.lookup(node); + if (!recId) { + recId = DistinctAttr::create(UnitAttr::get(context)); + nodeToRecId[node] = recId; + } + recSelf = recSelfCtor(recId); + iter->second.recSelf = recSelf; } + // Inject the self-ref into the previous layer. + translationStack.back().second.unboundSelfRefs.insert(recSelf); + return cast(recSelf); } + } - // Only cache fully self-contained nodes. - if (unboundRecursiveSelfRefs.back().empty()) - nodeToAttr.try_emplace(node, attr); - return attr; + return lookup(node); +} + +std::pair +DebugImporter::RecursionPruner::finalizeTranslation(llvm::DINode *node, + DINodeAttr result) { + // If `node` is not a potentially recursive type, it will not be on the + // translation stack. Nothing to set in this case. + if (translationStack.empty()) + return {result, true}; + if (translationStack.back().first != node) + return {result, translationStack.back().second.unboundSelfRefs.empty()}; + + TranslationState &state = translationStack.back().second; + + // If this node is actually recursive, set the recId onto `result`. + if (DIRecursiveTypeAttrInterface recSelf = state.recSelf) { + auto recType = cast(result); + result = cast(recType.withRecId(recSelf.getRecId())); + // Remove this recSelf from the set of unbound selfRefs. + state.unboundSelfRefs.erase(recSelf); } - return nullptr; + + // Insert the result into our internal cache if it's not self-contained. + if (!state.unboundSelfRefs.empty()) { + auto [_, inserted] = dependentCache.try_emplace( + node, DependentTranslation{result, state.unboundSelfRefs}); + assert(inserted && "invalid state: caching the same DINode twice"); + return {result, false}; + } + return {result, true}; +} + +void DebugImporter::RecursionPruner::popTranslationStack(llvm::DINode *node) { + // If `node` is not a potentially recursive type, it will not be on the + // translation stack. Nothing to handle in this case. + if (translationStack.empty() || translationStack.back().first != node) + return; + + // At the end of the stack, all unbound self-refs must be resolved already, + // and the entire cache should be accounted for. + TranslationState &currLayerState = translationStack.back().second; + if (translationStack.size() == 1) { + assert(currLayerState.unboundSelfRefs.empty() && + "internal error: unbound recursive self reference at top level."); + translationStack.pop_back(); + return; + } + + // Copy unboundSelfRefs down to the previous level. + TranslationState &nextLayerState = (++translationStack.rbegin())->second; + nextLayerState.unboundSelfRefs.insert(currLayerState.unboundSelfRefs.begin(), + currLayerState.unboundSelfRefs.end()); + translationStack.pop_back(); +} + +DINodeAttr DebugImporter::RecursionPruner::lookup(llvm::DINode *node) { + auto cacheIter = dependentCache.find(node); + if (cacheIter == dependentCache.end()) + return {}; + + DependentTranslation &entry = cacheIter->second; + if (llvm::set_is_subset(entry.unboundSelfRefs, + translationStack.back().second.unboundSelfRefs)) + return entry.attr; + + // Stale cache entry. + dependentCache.erase(cacheIter); + return {}; } //===----------------------------------------------------------------------===// @@ -394,13 +478,3 @@ DistinctAttr DebugImporter::getOrCreateDistinctID(llvm::DINode *node) { id = DistinctAttr::create(UnitAttr::get(context)); return id; } - -function_ref -DebugImporter::getRecSelfConstructor(llvm::DINode *node) { - using CtorType = function_ref; - return TypeSwitch(node) - .Case([&](llvm::DICompositeType *concreteNode) { - return CtorType(DICompositeTypeAttr::getRecSelf); - }) - .Default(CtorType()); -} diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.h b/mlir/lib/Target/LLVMIR/DebugImporter.h index bcf628fc4234..8b22dc634567 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.h +++ b/mlir/lib/Target/LLVMIR/DebugImporter.h @@ -29,8 +29,7 @@ namespace detail { class DebugImporter { public: - DebugImporter(ModuleOp mlirModule) - : context(mlirModule.getContext()), mlirModule(mlirModule) {} + DebugImporter(ModuleOp mlirModule); /// Translates the given LLVM debug location to an MLIR location. Location translateLoc(llvm::DILocation *loc); @@ -86,24 +85,102 @@ private: /// for it, or create a new one if not. DistinctAttr getOrCreateDistinctID(llvm::DINode *node); - /// Get the `getRecSelf` constructor for the translated type of `node` if its - /// translated DITypeAttr supports recursion. Otherwise, returns nullptr. - function_ref - getRecSelfConstructor(llvm::DINode *node); - /// A mapping between LLVM debug metadata and the corresponding attribute. DenseMap nodeToAttr; /// A mapping between distinct LLVM debug metadata nodes and the corresponding /// distinct id attribute. DenseMap nodeToDistinctAttr; - /// A stack that stores the metadata nodes that are being traversed. The stack - /// is used to detect cyclic dependencies during the metadata translation. - /// A node is pushed with a null value. If it is ever seen twice, it is given - /// a recursive id attribute, indicating that it is a recursive node. - llvm::MapVector translationStack; - /// All the unbound recursive self references in the translation stack. - SmallVector> unboundRecursiveSelfRefs; + /// Translation helper for recursive DINodes. + /// Works alongside a stack-based DINode translator (the "main translator") + /// for gracefully handling DINodes that are recursive. + /// + /// Usage: + /// - Before translating a node, call `pruneOrPushTranslationStack` to see if + /// the pruner can preempt this translation. If this is a node that the + /// pruner already knows how to handle, it will return the translated + /// DINodeAttr. + /// - After a node is successfully translated by the main translator, call + /// `finalizeTranslation` to save the translated result with the pruner, and + /// give it a chance to further modify the result. + /// - Regardless of success or failure by the main translator, always call + /// `popTranslationStack` at the end of translating a node. This is + /// necessary to keep the internal book-keeping in sync. + /// + /// This helper maintains an internal cache so that no recursive type will + /// be translated more than once by the main translator. + /// This internal cache is different from the cache maintained by the main + /// translator because it may store nodes that are not self-contained (i.e. + /// contain unbounded recursive self-references). + class RecursionPruner { + public: + RecursionPruner(MLIRContext *context) : context(context) {} + + /// If this node is a recursive instance that was previously seen, returns a + /// self-reference. If this node was previously cached, returns the cached + /// result. Otherwise, returns null attr, and a translation stack frame is + /// created for this node. Expects `finalizeTranslation` & + /// `popTranslationStack` to be called on this node later. + DINodeAttr pruneOrPushTranslationStack(llvm::DINode *node); + + /// Register the translated result of `node`. Returns the finalized result + /// (with recId if recursive) and whether the result is self-contained + /// (i.e. contains no unbound self-refs). + std::pair finalizeTranslation(llvm::DINode *node, + DINodeAttr result); + + /// Pop off a frame from the translation stack after a node is done being + /// translated. + void popTranslationStack(llvm::DINode *node); + + private: + /// Returns the cached result (if exists) or null. + /// The cache entry will be removed if not all of its dependent self-refs + /// exists. + DINodeAttr lookup(llvm::DINode *node); + + MLIRContext *context; + + /// A cached translation that contains the translated attribute as well + /// as any unbound self-references that it depends on. + struct DependentTranslation { + /// The translated attr. May contain unbound self-references for other + /// recursive attrs. + DINodeAttr attr; + /// The set of unbound self-refs that this cached entry refers to. All + /// these self-refs must exist for the cached entry to be valid. + DenseSet unboundSelfRefs; + }; + /// A mapping between LLVM debug metadata and the corresponding attribute. + /// Only contains those with unboundSelfRefs. Fully self-contained attrs + /// will be cached by the outer main translator. + DenseMap dependentCache; + + /// Each potentially recursive node will have a TranslationState pushed onto + /// the `translationStack` to keep track of whether this node is actually + /// recursive (i.e. has self-references inside), and other book-keeping. + struct TranslationState { + /// The rec-self if this node is indeed a recursive node (i.e. another + /// instance of itself is seen while translating it). Null if this node + /// has not been seen again deeper in the translation stack. + DIRecursiveTypeAttrInterface recSelf; + /// All the unbound recursive self references in this layer of the + /// translation stack. + DenseSet unboundSelfRefs; + }; + /// A stack that stores the metadata nodes that are being traversed. The + /// stack is used to handle cyclic dependencies during metadata translation. + /// Each node is pushed with an empty TranslationState. If it is ever seen + /// later when the stack is deeper, the node is recursive, and its + /// TranslationState is assigned a recSelf. + llvm::MapVector translationStack; + + /// A mapping between DINodes that are recursive, and their assigned recId. + /// This is kept so that repeated occurrences of the same node can reuse the + /// same ID and be deduplicated. + DenseMap nodeToRecId; + }; + RecursionPruner recursionPruner; MLIRContext *context; ModuleOp mlirModule; diff --git a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp index 642359a23756..f6e05e25ace6 100644 --- a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp @@ -216,18 +216,15 @@ DebugTranslation::translateImpl(DIGlobalVariableAttr attr) { llvm::DIType * DebugTranslation::translateRecursive(DIRecursiveTypeAttrInterface attr) { DistinctAttr recursiveId = attr.getRecId(); - if (attr.isRecSelf()) { - auto *iter = recursiveTypeMap.find(recursiveId); - assert(iter != recursiveTypeMap.end() && "unbound DI recursive self type"); + if (auto *iter = recursiveTypeMap.find(recursiveId); + iter != recursiveTypeMap.end()) { return iter->second; + } else { + assert(!attr.isRecSelf() && "unbound DI recursive self type"); } auto setRecursivePlaceholder = [&](llvm::DIType *placeholder) { - [[maybe_unused]] auto [iter, inserted] = - recursiveTypeMap.try_emplace(recursiveId, placeholder); - (void)iter; - (void)inserted; - assert(inserted && "illegal reuse of recursive id"); + recursiveTypeMap.try_emplace(recursiveId, placeholder); }; llvm::DIType *result = diff --git a/mlir/test/Target/LLVMIR/Import/debug-info.ll b/mlir/test/Target/LLVMIR/Import/debug-info.ll index 959a5a1cd971..e2ef94617dd7 100644 --- a/mlir/test/Target/LLVMIR/Import/debug-info.ll +++ b/mlir/test/Target/LLVMIR/Import/debug-info.ll @@ -607,3 +607,146 @@ declare !dbg !1 void @declaration() !0 = !{i32 2, !"Debug Info Version", i32 3} !1 = !DISubprogram(name: "declaration", scope: !2, file: !2, flags: DIFlagPrototyped, spFlags: 0) !2 = !DIFile(filename: "debug-info.ll", directory: "/") + +; // ----- + +; Ensure that repeated occurence of recursive subtree does not result in +; duplicate MLIR entries. +; +; +--> B:B1 ----+ +; | ^ v +; A <---+------ B +; | v ^ +; +--> B:B2 ----+ +; This should result in only one B instance. + +; CHECK-DAG: #[[B1_INNER:.+]] = #llvm.di_derived_type<{{.*}}name = "B:B1", baseType = #[[B_SELF:.+]]> +; CHECK-DAG: #[[B2_INNER:.+]] = #llvm.di_derived_type<{{.*}}name = "B:B2", baseType = #[[B_SELF]]> +; CHECK-DAG: #[[B_INNER:.+]] = #llvm.di_composite_type<{{.*}}recId = [[B_RECID:.+]], {{.*}}name = "B", {{.*}}elements = #[[B1_INNER]], #[[B2_INNER]] + +; CHECK-DAG: #[[B1_OUTER:.+]] = #llvm.di_derived_type<{{.*}}name = "B:B1", baseType = #[[B_INNER]]> +; CHECK-DAG: #[[B2_OUTER:.+]] = #llvm.di_derived_type<{{.*}}name = "B:B2", baseType = #[[B_INNER]]> +; CHECK-DAG: #[[A_OUTER:.+]] = #llvm.di_composite_type<{{.*}}recId = [[A_RECID:.+]], {{.*}}name = "A", {{.*}}elements = #[[B1_OUTER]], #[[B2_OUTER]] + +; CHECK-DAG: #[[A_SELF:.+]] = #llvm.di_composite_type<{{.*}}recId = [[A_RECID]] +; CHECK-DAG: #[[B_SELF:.+]] = #llvm.di_composite_type<{{.*}}recId = [[B_RECID]] + +; CHECK: #llvm.di_subprogram<{{.*}}scope = #[[A_OUTER]] + +define void @class_field(ptr %arg1) !dbg !18 { + ret void +} + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!0} +!0 = !{i32 2, !"Debug Info Version", i32 3} +!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2) +!2 = !DIFile(filename: "debug-info.ll", directory: "/") + +!3 = !DICompositeType(tag: DW_TAG_class_type, name: "A", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !4) +!4 = !{!7, !8} + +!5 = !DICompositeType(tag: DW_TAG_class_type, name: "B", scope: !3, file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !9) +!7 = !DIDerivedType(tag: DW_TAG_member, name: "B:B1", file: !2, baseType: !5) +!8 = !DIDerivedType(tag: DW_TAG_member, name: "B:B2", file: !2, baseType: !5) +!9 = !{!7, !8} + +!18 = distinct !DISubprogram(name: "A", scope: !3, file: !2, spFlags: DISPFlagDefinition, unit: !1) + +; // ----- + +; Ensure that recursive cycles with multiple entry points are cached correctly. +; +; +---- A ----+ +; v v +; B <-------> C +; This should result in a cached instance of B --> C --> B_SELF to be reused +; when visiting B from C (after visiting B from A). + +; CHECK-DAG: #[[A:.+]] = #llvm.di_composite_type<{{.*}}name = "A", {{.*}}elements = #[[TO_B_OUTER:.+]], #[[TO_C_OUTER:.+]]> +; CHECK-DAG: #llvm.di_subprogram<{{.*}}scope = #[[A]], + +; CHECK-DAG: #[[TO_B_OUTER]] = #llvm.di_derived_type<{{.*}}name = "->B", {{.*}}baseType = #[[B_OUTER:.+]]> +; CHECK-DAG: #[[B_OUTER]] = #llvm.di_composite_type<{{.*}}recId = [[B_RECID:.+]], {{.*}}name = "B", {{.*}}elements = #[[TO_C_INNER:.+]]> +; CHECK-DAG: #[[TO_C_INNER]] = #llvm.di_derived_type<{{.*}}name = "->C", {{.*}}baseType = #[[C_INNER:.+]]> +; CHECK-DAG: #[[C_INNER]] = #llvm.di_composite_type<{{.*}}name = "C", {{.*}}elements = #[[TO_B_SELF:.+]]> +; CHECK-DAG: #[[TO_B_SELF]] = #llvm.di_derived_type<{{.*}}name = "->B", {{.*}}baseType = #[[B_SELF:.+]]> +; CHECK-DAG: #[[B_SELF]] = #llvm.di_composite_type<{{.*}}recId = [[B_RECID]]> + +; CHECK-DAG: #[[TO_C_OUTER]] = #llvm.di_derived_type<{{.*}}name = "->C", {{.*}}baseType = #[[C_OUTER:.+]]> +; CHECK-DAG: #[[C_OUTER]] = #llvm.di_composite_type<{{.*}}name = "C", {{.*}}elements = #[[TO_B_OUTER]]> + +define void @class_field(ptr %arg1) !dbg !18 { + ret void +} + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!0} +!0 = !{i32 2, !"Debug Info Version", i32 3} +!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2) +!2 = !DIFile(filename: "debug-info.ll", directory: "/") + +!3 = !DICompositeType(tag: DW_TAG_class_type, name: "A", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !4) +!5 = !DICompositeType(tag: DW_TAG_class_type, name: "B", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !10) +!6 = !DICompositeType(tag: DW_TAG_class_type, name: "C", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !9) + +!7 = !DIDerivedType(tag: DW_TAG_member, name: "->B", file: !2, baseType: !5) +!8 = !DIDerivedType(tag: DW_TAG_member, name: "->C", file: !2, baseType: !6) +!4 = !{!7, !8} +!9 = !{!7} +!10 = !{!8} + +!18 = distinct !DISubprogram(name: "SP", scope: !3, file: !2, spFlags: DISPFlagDefinition, unit: !1) + +; // ----- + +; Ensures that replacing a nested mutually recursive decl does not result in +; nested duplicate recursive decls. +; +; A ---> B <--> C +; ^ ^ +; +-------------+ + +; CHECK-DAG: #[[A:.+]] = #llvm.di_composite_type<{{.*}}recId = [[A_RECID:.+]], {{.*}}name = "A", {{.*}}elements = #[[A_TO_B:.+]], #[[A_TO_C:.+]]> +; CHECK-DAG: #llvm.di_subprogram<{{.*}}scope = #[[A]], +; CHECK-DAG: #[[A_TO_B]] = #llvm.di_derived_type<{{.*}}name = "->B", {{.*}}baseType = #[[B_FROM_A:.+]]> +; CHECK-DAG: #[[A_TO_C]] = #llvm.di_derived_type<{{.*}}name = "->C", {{.*}}baseType = #[[C_FROM_A:.+]]> + +; CHECK-DAG: #[[B_FROM_A]] = #llvm.di_composite_type<{{.*}}recId = [[B_RECID:.+]], {{.*}}name = "B", {{.*}}elements = #[[B_TO_C:.+]]> +; CHECK-DAG: #[[B_TO_C]] = #llvm.di_derived_type<{{.*}}name = "->C", {{.*}}baseType = #[[C_FROM_B:.+]]> +; CHECK-DAG: #[[C_FROM_B]] = #llvm.di_composite_type<{{.*}}recId = [[C_RECID:.+]], {{.*}}name = "C", {{.*}}elements = #[[TO_A_SELF:.+]], #[[TO_B_SELF:.+]], #[[TO_C_SELF:.+]]> + +; CHECK-DAG: #[[C_FROM_A]] = #llvm.di_composite_type<{{.*}}recId = [[C_RECID]], {{.*}}name = "C", {{.*}}elements = #[[TO_A_SELF]], #[[TO_B_INNER:.+]], #[[TO_C_SELF]] +; CHECK-DAG: #[[TO_B_INNER]] = #llvm.di_derived_type<{{.*}}name = "->B", {{.*}}baseType = #[[B_INNER:.+]]> +; CHECK-DAG: #[[B_INNER]] = #llvm.di_composite_type<{{.*}}name = "B", {{.*}}elements = #[[TO_C_SELF]]> + +; CHECK-DAG: #[[TO_A_SELF]] = #llvm.di_derived_type<{{.*}}name = "->A", {{.*}}baseType = #[[A_SELF:.+]]> +; CHECK-DAG: #[[TO_B_SELF]] = #llvm.di_derived_type<{{.*}}name = "->B", {{.*}}baseType = #[[B_SELF:.+]]> +; CHECK-DAG: #[[TO_C_SELF]] = #llvm.di_derived_type<{{.*}}name = "->C", {{.*}}baseType = #[[C_SELF:.+]]> +; CHECK-DAG: #[[A_SELF]] = #llvm.di_composite_type<{{.*}}recId = [[A_RECID]]> +; CHECK-DAG: #[[B_SELF]] = #llvm.di_composite_type<{{.*}}recId = [[B_RECID]]> +; CHECK-DAG: #[[C_SELF]] = #llvm.di_composite_type<{{.*}}recId = [[C_RECID]]> + +define void @class_field(ptr %arg1) !dbg !18 { + ret void +} + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!0} +!0 = !{i32 2, !"Debug Info Version", i32 3} +!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2) +!2 = !DIFile(filename: "debug-info.ll", directory: "/") + +!3 = !DICompositeType(tag: DW_TAG_class_type, name: "A", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !9) +!4 = !DICompositeType(tag: DW_TAG_class_type, name: "B", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !10) +!5 = !DICompositeType(tag: DW_TAG_class_type, name: "C", file: !2, line: 42, flags: DIFlagTypePassByReference | DIFlagNonTrivial, elements: !11) + +!6 = !DIDerivedType(tag: DW_TAG_member, name: "->A", file: !2, baseType: !3) +!7 = !DIDerivedType(tag: DW_TAG_member, name: "->B", file: !2, baseType: !4) +!8 = !DIDerivedType(tag: DW_TAG_member, name: "->C", file: !2, baseType: !5) + +!9 = !{!7, !8} ; A -> B, C +!10 = !{!8} ; B -> C +!11 = !{!6, !7, !8} ; C -> A, B, C + +!18 = distinct !DISubprogram(name: "SP", scope: !3, file: !2, spFlags: DISPFlagDefinition, unit: !1) diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index 785a525caab8..c4ca0e83f81e 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -423,3 +423,31 @@ llvm.mlir.global @global_variable() {dbg_expr = #di_global_variable_expression} // CHECK: ![[SCOPE]] = !DISubprogram({{.*}}type: ![[SUBROUTINE:[0-9]+]], // CHECK: ![[SUBROUTINE]] = !DISubroutineType(types: ![[SR_TYPES:[0-9]+]]) // CHECK: ![[SR_TYPES]] = !{![[COMP]]} + +// ----- + +// Ensures nested recursive decls work. +// The output should be identical to if the inner composite type decl was +// replaced with the recursive self reference. + +#di_file = #llvm.di_file<"test.mlir" in "/"> +#di_composite_type_self = #llvm.di_composite_type> + +#di_subroutine_type_inner = #llvm.di_subroutine_type +#di_subprogram_inner = #llvm.di_subprogram +#di_composite_type_inner = #llvm.di_composite_type, scope = #di_subprogram_inner> + +#di_subroutine_type = #llvm.di_subroutine_type +#di_subprogram = #llvm.di_subprogram +#di_composite_type = #llvm.di_composite_type, scope = #di_subprogram> + +#di_global_variable = #llvm.di_global_variable +#di_global_variable_expression = #llvm.di_global_variable_expression + +llvm.mlir.global @global_variable() {dbg_expr = #di_global_variable_expression} : !llvm.struct<()> + +// CHECK: distinct !DIGlobalVariable({{.*}}type: ![[COMP:[0-9]+]], +// CHECK: ![[COMP]] = distinct !DICompositeType({{.*}}scope: ![[SCOPE:[0-9]+]], +// CHECK: ![[SCOPE]] = !DISubprogram({{.*}}type: ![[SUBROUTINE:[0-9]+]], +// CHECK: ![[SUBROUTINE]] = !DISubroutineType(types: ![[SR_TYPES:[0-9]+]]) +// CHECK: ![[SR_TYPES]] = !{![[COMP]]} -- GitLab From 8ddfb66903969224ebd4e10c1461d2be323f4798 Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Mon, 8 Apr 2024 10:18:56 +0200 Subject: [PATCH 122/695] [flang] Fix MASKR/MASKL lowering for INTEGER(16) (#87496) The all one masks was not properly created for i128 types because builder.createIntegerConstant ended-up truncating -1 to something positive. Add a builder.createAllOnesInteger/createMinusOneInteger helpers and use them where createIntegerConstant(..., -1) was used. Add an assert in createIntegerConstant to catch negative numbers for i128 type. --- .../flang/Optimizer/Builder/FIRBuilder.h | 13 ++++ flang/lib/Lower/ConvertVariable.cpp | 2 +- flang/lib/Lower/DirectivesCommon.h | 2 +- flang/lib/Optimizer/Builder/FIRBuilder.cpp | 12 ++++ flang/lib/Optimizer/Builder/IntrinsicCall.cpp | 59 ++++++--------- .../Optimizer/Builder/PPCIntrinsicCall.cpp | 4 +- flang/test/Lower/Intrinsics/maskl.f90 | 72 ++++++++++++------- flang/test/Lower/Intrinsics/maskr.f90 | 72 ++++++++++++------- 8 files changed, 141 insertions(+), 95 deletions(-) diff --git a/flang/include/flang/Optimizer/Builder/FIRBuilder.h b/flang/include/flang/Optimizer/Builder/FIRBuilder.h index 940866b25d2f..e4c954159f71 100644 --- a/flang/include/flang/Optimizer/Builder/FIRBuilder.h +++ b/flang/include/flang/Optimizer/Builder/FIRBuilder.h @@ -164,9 +164,22 @@ public: mlir::Value createNullConstant(mlir::Location loc, mlir::Type ptrType = {}); /// Create an integer constant of type \p type and value \p i. + /// Should not be used with negative values with integer types of more + /// than 64 bits. mlir::Value createIntegerConstant(mlir::Location loc, mlir::Type integerType, std::int64_t i); + /// Create an integer of \p integerType where all the bits have been set to + /// ones. Safe to use regardless of integerType bitwidth. + mlir::Value createAllOnesInteger(mlir::Location loc, mlir::Type integerType); + + /// Create -1 constant of \p integerType. Safe to use regardless of + /// integerType bitwidth. + mlir::Value createMinusOneInteger(mlir::Location loc, + mlir::Type integerType) { + return createAllOnesInteger(loc, integerType); + } + /// Create a real constant from an integer value. mlir::Value createRealConstant(mlir::Location loc, mlir::Type realType, llvm::APFloat::integerPart val); diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index f59c784cff6f..01473f7f6cd7 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -1469,7 +1469,7 @@ static void lowerExplicitLowerBounds( /// CFI_desc_t requirements in 18.5.3 point 5.). static mlir::Value getAssumedSizeExtent(mlir::Location loc, fir::FirOpBuilder &builder) { - return builder.createIntegerConstant(loc, builder.getIndexType(), -1); + return builder.createMinusOneInteger(loc, builder.getIndexType()); } /// Lower explicit extents into \p result if this is an explicit-shape or diff --git a/flang/lib/Lower/DirectivesCommon.h b/flang/lib/Lower/DirectivesCommon.h index 6daa72b84d90..3ebf3fd965da 100644 --- a/flang/lib/Lower/DirectivesCommon.h +++ b/flang/lib/Lower/DirectivesCommon.h @@ -744,7 +744,7 @@ genBoundsOpsFromBox(fir::FirOpBuilder &builder, mlir::Location loc, // Box is not present. Populate bound values with default values. llvm::SmallVector boundValues; mlir::Value zero = builder.createIntegerConstant(loc, idxTy, 0); - mlir::Value mOne = builder.createIntegerConstant(loc, idxTy, -1); + mlir::Value mOne = builder.createMinusOneInteger(loc, idxTy); for (unsigned dim = 0; dim < dataExv.rank(); ++dim) { boundValues.push_back(zero); // lb boundValues.push_back(mOne); // ub diff --git a/flang/lib/Optimizer/Builder/FIRBuilder.cpp b/flang/lib/Optimizer/Builder/FIRBuilder.cpp index e4362b2f9e69..b09da4929a8a 100644 --- a/flang/lib/Optimizer/Builder/FIRBuilder.cpp +++ b/flang/lib/Optimizer/Builder/FIRBuilder.cpp @@ -128,9 +128,21 @@ mlir::Value fir::FirOpBuilder::createNullConstant(mlir::Location loc, mlir::Value fir::FirOpBuilder::createIntegerConstant(mlir::Location loc, mlir::Type ty, std::int64_t cst) { + assert((cst >= 0 || mlir::isa(ty) || + mlir::cast(ty).getWidth() <= 64) && + "must use APint"); return create(loc, ty, getIntegerAttr(ty, cst)); } +mlir::Value fir::FirOpBuilder::createAllOnesInteger(mlir::Location loc, + mlir::Type ty) { + if (mlir::isa(ty)) + return createIntegerConstant(loc, ty, -1); + llvm::APInt allOnes = + llvm::APInt::getAllOnes(mlir::cast(ty).getWidth()); + return create(loc, ty, getIntegerAttr(ty, allOnes)); +} + mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, llvm::APFloat::integerPart val) { diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index 5f6de9439b4b..4ee7258004fa 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -3621,7 +3621,7 @@ mlir::Value IntrinsicLibrary::genIbclr(mlir::Type resultType, assert(args.size() == 2); mlir::Value pos = builder.createConvert(loc, resultType, args[1]); mlir::Value one = builder.createIntegerConstant(loc, resultType, 1); - mlir::Value ones = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, resultType); auto mask = builder.create(loc, one, pos); auto res = builder.create(loc, ones, mask); return builder.create(loc, args[0], res); @@ -3645,7 +3645,7 @@ mlir::Value IntrinsicLibrary::genIbits(mlir::Type resultType, loc, resultType, resultType.cast().getWidth()); auto shiftCount = builder.create(loc, bitSize, len); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); - mlir::Value ones = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, resultType); auto mask = builder.create(loc, ones, shiftCount); auto res1 = builder.create(loc, args[0], pos); auto res2 = builder.create(loc, res1, mask); @@ -3805,7 +3805,8 @@ mlir::Value IntrinsicLibrary::genIeeeClass(mlir::Type resultType, assert(args.size() == 1); mlir::Value realVal = args[0]; mlir::FloatType realType = realVal.getType().dyn_cast(); - mlir::Type intType = builder.getIntegerType(realType.getWidth()); + const unsigned intWidth = realType.getWidth(); + mlir::Type intType = builder.getIntegerType(intWidth); mlir::Value intVal = builder.create(loc, intType, realVal); llvm::StringRef tableName = RTNAME_STRING(IeeeClassTable); @@ -3816,41 +3817,25 @@ mlir::Value IntrinsicLibrary::genIeeeClass(mlir::Type resultType, auto createIntegerConstant = [&](uint64_t k) { return builder.createIntegerConstant(loc, intType, k); }; + auto createIntegerConstantAPI = [&](const llvm::APInt &apInt) { + return builder.create( + loc, intType, builder.getIntegerAttr(intType, apInt)); + }; auto getMasksAndShifts = [&](uint64_t totalSize, uint64_t exponentSize, uint64_t significandSize, bool hasExplicitBit = false) { assert(1 + exponentSize + significandSize == totalSize && "invalid floating point fields"); - constexpr uint64_t one = 1; // type promotion uint64_t lowSignificandSize = significandSize - hasExplicitBit - 1; signShift = createIntegerConstant(totalSize - 1 - hasExplicitBit - 4); highSignificandShift = createIntegerConstant(lowSignificandSize); - if (totalSize <= 64) { - exponentMask = - createIntegerConstant(((one << exponentSize) - 1) << significandSize); - lowSignificandMask = - createIntegerConstant((one << lowSignificandSize) - 1); - return; - } - // Mlir can't directly build large constants. Build them in steps. - // The folded end result is the same. - mlir::Value sixtyfour = createIntegerConstant(64); - exponentMask = createIntegerConstant(((one << exponentSize) - 1) - << (significandSize - 64)); - exponentMask = - builder.create(loc, exponentMask, sixtyfour); - if (lowSignificandSize <= 64) { - lowSignificandMask = - createIntegerConstant((one << lowSignificandSize) - 1); - return; - } - mlir::Value ones = createIntegerConstant(0xffffffffffffffff); - lowSignificandMask = - createIntegerConstant((one << (lowSignificandSize - 64)) - 1); - lowSignificandMask = - builder.create(loc, lowSignificandMask, sixtyfour); - lowSignificandMask = - builder.create(loc, lowSignificandMask, ones); + llvm::APInt exponentMaskAPI = + llvm::APInt::getBitsSet(intWidth, /*lo=*/significandSize, + /*hi=*/significandSize + exponentSize); + exponentMask = createIntegerConstantAPI(exponentMaskAPI); + llvm::APInt lowSignificandMaskAPI = + llvm::APInt::getLowBitsSet(intWidth, lowSignificandSize); + lowSignificandMask = createIntegerConstantAPI(lowSignificandMaskAPI); }; switch (realType.getWidth()) { case 16: @@ -4318,7 +4303,7 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType, // X is zero -- result is -infinity builder.setInsertionPointToStart(&outerIfOp.getThenRegion().front()); genRaiseExcept(_FORTRAN_RUNTIME_IEEE_DIVIDE_BY_ZERO); - mlir::Value ones = builder.createIntegerConstant(loc, intType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, intType); mlir::Value result = builder.create( loc, ones, builder.createIntegerConstant(loc, intType, @@ -4937,7 +4922,7 @@ mlir::Value IntrinsicLibrary::genIshftc(mlir::Type resultType, mlir::Value size = args[2] ? builder.createConvert(loc, resultType, args[2]) : bitSize; mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); - mlir::Value ones = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, resultType); mlir::Value absShift = genAbs(resultType, {shift}); auto elseSize = builder.create(loc, size, absShift); auto shiftIsZero = builder.create( @@ -5073,7 +5058,7 @@ mlir::Value IntrinsicLibrary::genMask(mlir::Type resultType, assert(args.size() == 2); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); - mlir::Value ones = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, resultType); mlir::Value bitSize = builder.createIntegerConstant( loc, resultType, resultType.getIntOrFloatBitWidth()); mlir::Value bitsToSet = builder.createConvert(loc, resultType, args[0]); @@ -5206,7 +5191,7 @@ mlir::Value IntrinsicLibrary::genMergeBits(mlir::Type resultType, mlir::Value i = builder.createConvert(loc, resultType, args[0]); mlir::Value j = builder.createConvert(loc, resultType, args[1]); mlir::Value mask = builder.createConvert(loc, resultType, args[2]); - mlir::Value ones = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, resultType); // MERGE_BITS(I, J, MASK) = IOR(IAND(I, MASK), IAND(J, NOT(MASK))) mlir::Value notMask = builder.create(loc, mask, ones); @@ -5353,7 +5338,7 @@ void IntrinsicLibrary::genMvbits(llvm::ArrayRef args) { auto to = builder.create(loc, resultType, toAddr); mlir::Value topos = builder.createConvert(loc, resultType, unbox(args[4])); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); - mlir::Value ones = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value ones = builder.createAllOnesInteger(loc, resultType); mlir::Value bitSize = builder.createIntegerConstant( loc, resultType, resultType.cast().getWidth()); auto shiftCount = builder.create(loc, bitSize, len); @@ -5432,7 +5417,7 @@ IntrinsicLibrary::genNorm2(mlir::Type resultType, mlir::Value IntrinsicLibrary::genNot(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 1); - mlir::Value allOnes = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value allOnes = builder.createAllOnesInteger(loc, resultType); return builder.create(loc, args[0], allOnes); } @@ -5875,7 +5860,7 @@ mlir::Value IntrinsicLibrary::genShiftA(mlir::Type resultType, // the shift amount is equal to the element size. // So if SHIFT is equal to the bit width then it is handled as a special case. mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); - mlir::Value minusOne = builder.createIntegerConstant(loc, resultType, -1); + mlir::Value minusOne = builder.createMinusOneInteger(loc, resultType); mlir::Value valueIsNeg = builder.create( loc, mlir::arith::CmpIPredicate::slt, args[0], zero); mlir::Value specialRes = diff --git a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp index e588b19dded4..160118e2c050 100644 --- a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp @@ -2120,7 +2120,7 @@ PPCIntrinsicLibrary::genVecPerm(mlir::Type resultType, if (isNativeVecElemOrderOnLE()) { auto i8Ty{mlir::IntegerType::get(context, 8)}; auto v8Ty{mlir::VectorType::get(16, i8Ty)}; - auto negOne{builder.createIntegerConstant(loc, i8Ty, -1)}; + auto negOne{builder.createMinusOneInteger(loc, i8Ty)}; auto vNegOne{ builder.create(loc, v8Ty, negOne)}; @@ -2209,7 +2209,7 @@ PPCIntrinsicLibrary::genVecSel(mlir::Type resultType, auto vargs{convertVecArgs(builder, loc, vecTyInfos, argBases)}; auto i8Ty{mlir::IntegerType::get(builder.getContext(), 8)}; - auto negOne{builder.createIntegerConstant(loc, i8Ty, -1)}; + auto negOne{builder.createMinusOneInteger(loc, i8Ty)}; // construct a constant <16 x i8> vector with value -1 for bitcast auto bcVecTy{mlir::VectorType::get(16, i8Ty)}; diff --git a/flang/test/Lower/Intrinsics/maskl.f90 b/flang/test/Lower/Intrinsics/maskl.f90 index fab0122f6be7..ea77df480d52 100644 --- a/flang/test/Lower/Intrinsics/maskl.f90 +++ b/flang/test/Lower/Intrinsics/maskl.f90 @@ -1,17 +1,18 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s +! RUN: bbc -emit-fir %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-fir %s -o - | FileCheck %s ! CHECK-LABEL: maskl_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskl_test(a, b) integer :: a integer :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 32 : i32 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i32 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i32 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskl(a) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i32 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i32 - ! CHECK: %[[BITS:.*]] = arith.constant 32 : i32 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_VAL]] : i32 ! CHECK: %[[SHIFT:.*]] = arith.shli %[[C__1]], %[[LEN]] : i32 ! CHECK: %[[IS0:.*]] = arith.cmpi eq, %[[A_VAL]], %[[C__0]] : i32 @@ -20,16 +21,17 @@ subroutine maskl_test(a, b) end subroutine maskl_test ! CHECK-LABEL: maskl1_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskl1_test(a, b) integer :: a integer(kind=1) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 8 : i8 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i8 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i8 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskl(a, 1) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i8 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i8 - ! CHECK: %[[BITS:.*]] = arith.constant 8 : i8 ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i8 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i8 ! CHECK: %[[SHIFT:.*]] = arith.shli %[[C__1]], %[[LEN]] : i8 @@ -39,16 +41,17 @@ subroutine maskl1_test(a, b) end subroutine maskl1_test ! CHECK-LABEL: maskl2_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskl2_test(a, b) integer :: a integer(kind=2) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 16 : i16 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i16 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i16 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskl(a, 2) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i16 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i16 - ! CHECK: %[[BITS:.*]] = arith.constant 16 : i16 ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i16 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i16 ! CHECK: %[[SHIFT:.*]] = arith.shli %[[C__1]], %[[LEN]] : i16 @@ -58,16 +61,17 @@ subroutine maskl2_test(a, b) end subroutine maskl2_test ! CHECK-LABEL: maskl4_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskl4_test(a, b) integer :: a integer(kind=4) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 32 : i32 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i32 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i32 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskl(a, 4) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i32 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i32 - ! CHECK: %[[BITS:.*]] = arith.constant 32 : i32 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_VAL]] : i32 ! CHECK: %[[SHIFT:.*]] = arith.shli %[[C__1]], %[[LEN]] : i32 ! CHECK: %[[IS0:.*]] = arith.cmpi eq, %[[A_VAL]], %[[C__0]] : i32 @@ -76,16 +80,17 @@ subroutine maskl4_test(a, b) end subroutine maskl4_test ! CHECK-LABEL: maskl8_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskl8_test(a, b) integer :: a integer(kind=8) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 64 : i64 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i64 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i64 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskl(a, 8) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i64 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i64 - ! CHECK: %[[BITS:.*]] = arith.constant 64 : i64 ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i64 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i64 ! CHECK: %[[SHIFT:.*]] = arith.shli %[[C__1]], %[[LEN]] : i64 @@ -94,8 +99,21 @@ subroutine maskl8_test(a, b) ! CHECK: fir.store %[[RESULT]] to %[[B]] : !fir.ref end subroutine maskl8_test -! TODO: Code containing 128-bit integer literals current breaks. This is -! probably related to the issue linked below. When that is fixed, a test -! for kind=16 should be added here. -! -! https://github.com/llvm/llvm-project/issues/56446 +subroutine maskl16_test(a, b) + integer :: a + integer(16) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 128 : i128 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i128 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i128 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb + + ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref + b = maskl(a, 16) + ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i128 + ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i128 + ! CHECK: %[[SHIFT:.*]] = arith.shli %[[C__1]], %[[LEN]] : i128 + ! CHECK: %[[IS0:.*]] = arith.cmpi eq, %[[A_CONV]], %[[C__0]] : i128 + ! CHECK: %[[RESULT:.*]] = arith.select %[[IS0]], %[[C__0]], %[[SHIFT]] : i128 + ! CHECK: fir.store %[[RESULT]] to %[[B]] : !fir.ref +end subroutine diff --git a/flang/test/Lower/Intrinsics/maskr.f90 b/flang/test/Lower/Intrinsics/maskr.f90 index 85077a19541c..8c87da2a5829 100644 --- a/flang/test/Lower/Intrinsics/maskr.f90 +++ b/flang/test/Lower/Intrinsics/maskr.f90 @@ -1,17 +1,18 @@ -! RUN: bbc -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s +! RUN: bbc -emit-fir %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-fir %s -o - | FileCheck %s ! CHECK-LABEL: maskr_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskr_test(a, b) integer :: a integer :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 32 : i32 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i32 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i32 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskr(a) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i32 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i32 - ! CHECK: %[[BITS:.*]] = arith.constant 32 : i32 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_VAL]] : i32 ! CHECK: %[[SHIFT:.*]] = arith.shrui %[[C__1]], %[[LEN]] : i32 ! CHECK: %[[IS0:.*]] = arith.cmpi eq, %[[A_VAL]], %[[C__0]] : i32 @@ -20,16 +21,17 @@ subroutine maskr_test(a, b) end subroutine maskr_test ! CHECK-LABEL: maskr1_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskr1_test(a, b) integer :: a integer(kind=1) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 8 : i8 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i8 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i8 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskr(a, 1) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i8 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i8 - ! CHECK: %[[BITS:.*]] = arith.constant 8 : i8 ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i8 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i8 ! CHECK: %[[SHIFT:.*]] = arith.shrui %[[C__1]], %[[LEN]] : i8 @@ -39,16 +41,17 @@ subroutine maskr1_test(a, b) end subroutine maskr1_test ! CHECK-LABEL: maskr2_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskr2_test(a, b) integer :: a integer(kind=2) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 16 : i16 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i16 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i16 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskr(a, 2) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i16 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i16 - ! CHECK: %[[BITS:.*]] = arith.constant 16 : i16 ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i16 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i16 ! CHECK: %[[SHIFT:.*]] = arith.shrui %[[C__1]], %[[LEN]] : i16 @@ -58,16 +61,17 @@ subroutine maskr2_test(a, b) end subroutine maskr2_test ! CHECK-LABEL: maskr4_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskr4_test(a, b) integer :: a integer(kind=4) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 32 : i32 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i32 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i32 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskr(a, 4) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i32 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i32 - ! CHECK: %[[BITS:.*]] = arith.constant 32 : i32 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_VAL]] : i32 ! CHECK: %[[SHIFT:.*]] = arith.shrui %[[C__1]], %[[LEN]] : i32 ! CHECK: %[[IS0:.*]] = arith.cmpi eq, %[[A_VAL]], %[[C__0]] : i32 @@ -76,16 +80,17 @@ subroutine maskr4_test(a, b) end subroutine maskr4_test ! CHECK-LABEL: maskr8_test -! CHECK-SAME: %[[A:.*]]: !fir.ref{{.*}}, %[[B:.*]]: !fir.ref{{.*}} subroutine maskr8_test(a, b) integer :: a integer(kind=8) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 64 : i64 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i64 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i64 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref b = maskr(a, 8) - ! CHECK: %[[C__0:.*]] = arith.constant 0 : i64 - ! CHECK: %[[C__1:.*]] = arith.constant -1 : i64 - ! CHECK: %[[BITS:.*]] = arith.constant 64 : i64 ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i64 ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i64 ! CHECK: %[[SHIFT:.*]] = arith.shrui %[[C__1]], %[[LEN]] : i64 @@ -94,8 +99,21 @@ subroutine maskr8_test(a, b) ! CHECK: fir.store %[[RESULT]] to %[[B]] : !fir.ref end subroutine maskr8_test -! TODO: Code containing 128-bit integer literals current breaks. This is -! probably related to the issue linked below. When that is fixed, a test -! for kind=16 should be added here. -! -! https://github.com/llvm/llvm-project/issues/56446 +subroutine maskr16_test(a, b) + integer :: a + integer(16) :: b + ! CHECK-DAG: %[[BITS:.*]] = arith.constant 128 : i128 + ! CHECK-DAG: %[[C__1:.*]] = arith.constant -1 : i128 + ! CHECK-DAG: %[[C__0:.*]] = arith.constant 0 : i128 + ! CHECK: %[[A:.*]] = fir.declare %{{.*}}Ea + ! CHECK: %[[B:.*]] = fir.declare %{{.*}}Eb + + ! CHECK: %[[A_VAL:.*]] = fir.load %[[A]] : !fir.ref + b = maskr(a, 16) + ! CHECK: %[[A_CONV:.*]] = fir.convert %[[A_VAL]] : (i32) -> i128 + ! CHECK: %[[LEN:.*]] = arith.subi %[[BITS]], %[[A_CONV]] : i128 + ! CHECK: %[[SHIFT:.*]] = arith.shrui %[[C__1]], %[[LEN]] : i128 + ! CHECK: %[[IS0:.*]] = arith.cmpi eq, %[[A_CONV]], %[[C__0]] : i128 + ! CHECK: %[[RESULT:.*]] = arith.select %[[IS0]], %[[C__0]], %[[SHIFT]] : i128 + ! CHECK: fir.store %[[RESULT]] to %[[B]] : !fir.ref +end subroutine -- GitLab From 3c210d1cfdf4d8cd56de70fa40d01398e29044dc Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Mon, 8 Apr 2024 10:19:34 +0200 Subject: [PATCH 123/695] [flang][NFC] document BOZ error in DIM, MOD, MODULO, and SIGN (#87779) It is highly ambiguous to what type BOZ should be resolved in DIM, MOD, MODULO, and SIGN intrinsic arguments. Some other compilers accept them, but none agree. See table below. List them explicitly as non supported extensions (semantics already reject them, this is an NFC). Table listing the resolved types of the intrinsic results when there is a BOZ argument: | | gfortran | nvfortran | ifort | nagfor | xlf | | ------------------- | -------- | --------- | ----- | ------ | ------ | | DIM(INT4, BOZ) | INT16 | INT4 | INT8 | crash | INT4 | | DIM(BOZ, REAL4) | error | INT8 | error | error | REAL4 | | DIM(REAL4, BOZ) | error | REAL4 | error | error | REAL4 | | DIM(BOZ, INT4) | INT16 | INT8 | INT8 | INT8 | INT4 | | DIM(BOZ, BOZ) | INT16 | INT8 | INT8 | INT8 | REAL4 | | MOD(INT4, BOZ) | INT16 | INT4 | INT8 | crash | INT4 | | MOD(BOZ, REAL4) | error | INT8 | error | error | REAL4 | | MOD(REAL4, BOZ) | error | REAL4 | error | error | REAL4 | | MOD(BOZ, INT4) | INT16 | INT8 | INT8 | INT8 | INT4 | | MOD(BOZ, BOZ) | INT16 | INT8 | INT8 | INT8 | INT4 | | MODULO(INT4, BOZ) | INT16 | INT4 | INT8 | crash | INT4 | | MODULO(BOZ, REAL4) | error | INT8 | error | error | REAL4 | | MODULO(REAL4, BOZ) | error | REAL4 | error | error | REAL4 | | MODULO(BOZ, INT4) | INT16 | INT8 | INT8 | INT8 | INT4 | | MODULO(BOZ, BOZ) | INT16 | INT8 | INT8 | INT8 | INT8 | | SIGN(INT4, BOZ) | error | INT4 | INT8 | INT4 | INT4 | | SIGN(BOZ, REAL4) | error | INT8 | error | error | REAL4 | | SIGN(REAL4, BOZ) | error | REAL4 | error | error | REAL4 | | SIGN(BOZ, INT4) | error | INT8 | INT8 | INT8 | INT4 | | SIGN(BOZ, BOZ) | INT16 | INT8 | INT8 | INT8 | REAL4 | --- flang/docs/Extensions.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/flang/docs/Extensions.md b/flang/docs/Extensions.md index 697bd131c04c..d44242de17d5 100644 --- a/flang/docs/Extensions.md +++ b/flang/docs/Extensions.md @@ -193,7 +193,9 @@ end converted. BOZ literals are interpreted as default INTEGER only when they appear as the first items of array constructors with no explicit type. Otherwise, they generally cannot be used if the type would - not be known (e.g., `IAND(X'1',X'2')`). + not be known (e.g., `IAND(X'1',X'2')`, or as arguments of `DIM`, `MOD`, + `MODULO`, and `SIGN`. Note that while other compilers may accept such usages, + the type resolution of such BOZ literals usages is highly non portable). * BOZ literals can also be used as REAL values in some contexts where the type is unambiguous, such as initializations of REAL parameters. * EQUIVALENCE of numeric and character sequences (a ubiquitous extension), -- GitLab From 0bfea40101c10f80ee35d7fbfd4459e98cdb289c Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 8 Apr 2024 09:19:47 +0100 Subject: [PATCH 124/695] [AArch64] More shuffle-store test cases. NFC --- .../CostModel/AArch64/shuffle-other.ll | 88 ++++++++++++++++++ .../CostModel/AArch64/shuffle-store.ll | 93 +++++++++++++++++++ 2 files changed, 181 insertions(+) diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll index 90ec92a35a1c..aec181ec8d24 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll @@ -402,3 +402,91 @@ define void @multipart() { ret void } + + +define void @vst3(ptr %p) { +; CHECK-LABEL: 'vst3' +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %v64i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v64i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v64i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v64i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <6 x i32> + %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <12 x i32> + %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <24 x i32> + %v64i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <48 x i32> + + %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <6 x i32> + %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <12 x i32> + %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <24 x i32> + %v64i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <48 x i32> + + %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <6 x i32> + %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <12 x i32> + %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <24 x i32> + %v64i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <48 x i32> + + %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <6 x i32> + %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <12 x i32> + %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <24 x i32> + %v64i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <48 x i32> + + ret void +} + + +define void @vst4(ptr %p) { +; CHECK-LABEL: 'vst4' +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> + %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> + %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> + %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> + + %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> + %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> + %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> + %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> + + %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> + %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> + %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> + %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> + + %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> + %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> + %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> + %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> + + ret void +} diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll index fc8e1dd052bb..ebf913ece3a9 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll @@ -229,3 +229,96 @@ define void @vst4(ptr %p) { ret void } + + +define void @splatstore(ptr %p) { +; CHECK-LABEL: 'splatstore' +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i8> %v4i8, ptr %p, align 4 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> %v16i8, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <64 x i8> %v64i8, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %v4i16, ptr %p, align 8 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> %v8i16, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <64 x i16> %v64i16, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %v4i32, ptr %p, align 16 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <64 x i32> %v64i32, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i64> %v4i64, ptr %p, align 32 +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <16 x i64> %v16i64, ptr %p, align 128 +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <32 x i64> %v32i64, ptr %p, align 256 +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> zeroinitializer +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <64 x i64> %v64i64, ptr %p, align 512 +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> zeroinitializer + store <4 x i8> %v4i8, ptr %p + %v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> zeroinitializer + store <8 x i8> %v8i8, ptr %p + %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> zeroinitializer + store <16 x i8> %v16i8, ptr %p + %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> zeroinitializer + store <32 x i8> %v32i8, ptr %p + %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> zeroinitializer + store <64 x i8> %v64i8, ptr %p + + %v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> zeroinitializer + store <4 x i16> %v4i16, ptr %p + %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> zeroinitializer + store <8 x i16> %v8i16, ptr %p + %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> zeroinitializer + store <16 x i16> %v16i16, ptr %p + %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> zeroinitializer + store <32 x i16> %v32i16, ptr %p + %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> zeroinitializer + store <64 x i16> %v64i16, ptr %p + + %v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> zeroinitializer + store <4 x i32> %v4i32, ptr %p + %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> zeroinitializer + store <8 x i32> %v8i32, ptr %p + %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> zeroinitializer + store <16 x i32> %v16i32, ptr %p + %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> zeroinitializer + store <32 x i32> %v32i32, ptr %p + %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> zeroinitializer + store <64 x i32> %v64i32, ptr %p + + %v4i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <4 x i32> zeroinitializer + store <4 x i64> %v4i64, ptr %p + %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> zeroinitializer + store <8 x i64> %v8i64, ptr %p + %v16i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <16 x i32> zeroinitializer + store <16 x i64> %v16i64, ptr %p + %v32i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <32 x i32> zeroinitializer + store <32 x i64> %v32i64, ptr %p + %v64i64 = shufflevector <64 x i64> undef, <64 x i64> undef, <64 x i32> zeroinitializer + store <64 x i64> %v64i64, ptr %p + + ret void +} + -- GitLab From 6a7da2e30dc38ba92875bfe1da5520c950bab1e3 Mon Sep 17 00:00:00 2001 From: jeanPerier Date: Mon, 8 Apr 2024 10:22:44 +0200 Subject: [PATCH 125/695] [flang] Fix source allocation to explicit length after deferred length object (#87785) Flang supports source allocation to allocatable or pointers with a non deferred length that do not match the source length. This documented at: https://github.com/llvm/llvm-project/blob/9708d0900311503aa4685d6810d8caf0412e15d7/flang/docs/Extensions.md?plain=1#L312 The current lowering code was bugged when such explicit length allocate object appeared after a deferred length object in the source allocation list: Since "lenParams" had been computed when generating allocation of the deferred length object, the call to genSetDeferredLengthParameters was not a no-op on when lowering the explicit length allocation, and the explicit length was overridden with the source length. The output of the program added in test was: ``` ZZheZZ ZZhelloZZ ZZhelloZZ ``` Instead of: ``` ZZheZZ ZZhelloZZ ZZhello ZZ ``` Skip genSetDeferredLengthParameters when the allocate object has non deferred length. --- flang/lib/Lower/Allocatable.cpp | 8 +-- .../Lower/allocate-source-allocatables-2.f90 | 49 +++++++++++++++++++ 2 files changed, 54 insertions(+), 3 deletions(-) create mode 100644 flang/test/Lower/allocate-source-allocatables-2.f90 diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index 3557ea93e138..09180518ea41 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -588,13 +588,15 @@ private: TODO(loc, "coarray: allocation of a coarray object"); // Set length of the allocate object if it has. Otherwise, get the length // from source for the deferred length parameter. - if (lenParams.empty() && box.isCharacter() && - !box.hasNonDeferredLenParams()) + const bool isDeferredLengthCharacter = + box.isCharacter() && !box.hasNonDeferredLenParams(); + if (lenParams.empty() && isDeferredLengthCharacter) lenParams.push_back(fir::factory::readCharLen(builder, loc, exv)); if (!isSource || alloc.type.IsPolymorphic()) genRuntimeAllocateApplyMold(builder, loc, box, exv, alloc.getSymbol().Rank()); - genSetDeferredLengthParameters(alloc, box); + if (isDeferredLengthCharacter) + genSetDeferredLengthParameters(alloc, box); genAllocateObjectBounds(alloc, box); mlir::Value stat; if (isSource) diff --git a/flang/test/Lower/allocate-source-allocatables-2.f90 b/flang/test/Lower/allocate-source-allocatables-2.f90 new file mode 100644 index 000000000000..39b9f04a5f67 --- /dev/null +++ b/flang/test/Lower/allocate-source-allocatables-2.f90 @@ -0,0 +1,49 @@ +! RUN: bbc -emit-hlfir %s -o - | FileCheck %s +! Test lowering of extension of SOURCE allocation (non deferred length +! of character allocate-object need not to match the SOURCE length, truncation +! and padding are performed instead as in assignments). + +subroutine test() +! CHECK-LABEL: func.func @_QPtest() { +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %{{.*}} {{.*}}Ec_deferred +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_6:.*]] {{.*}}Ec_longer +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_11:.*]] {{.*}}Ec_shorter +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %{{.*}} typeparams %[[VAL_16:.*]] {{{.*}}Ec_source + character(5) :: c_source = "hello" + character(2), allocatable :: c_shorter + character(:), allocatable :: c_deferred + character(7), allocatable :: c_longer +! CHECK: %[[VAL_18:.*]] = arith.constant false +! CHECK: %[[VAL_22:.*]] = fir.embox %[[VAL_17]]#1 : (!fir.ref>) -> !fir.box> + +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_14]]#1 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.box>) -> !fir.box +! CHECK: %[[VAL_26:.*]] = fir.call @_FortranAAllocatableAllocateSource(%[[VAL_23]], %[[VAL_24]], %[[VAL_18]] + +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_4]]#1 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[VAL_28:.*]] = fir.convert %[[VAL_16]] : (index) -> i64 +! CHECK: %[[VAL_29:.*]] = arith.constant 1 : i32 +! CHECK: %[[VAL_30:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_31:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_32:.*]] = fir.call @_FortranAAllocatableInitCharacterForAllocate(%[[VAL_27]], %[[VAL_28]], %[[VAL_29]], %[[VAL_30]], %[[VAL_31]] +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_4]]#1 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.convert %[[VAL_22]] : (!fir.box>) -> !fir.box +! CHECK: %[[VAL_36:.*]] = fir.call @_FortranAAllocatableAllocateSource(%[[VAL_33]], %[[VAL_34]], %[[VAL_18]], + +! CHECK-NOT: AllocatableInitCharacterForAllocate +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_9]]#1 : (!fir.ref>>>) -> !fir.ref> +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_22]] : (!fir.box>) -> !fir.box +! CHECK: %[[VAL_40:.*]] = fir.call @_FortranAAllocatableAllocateSource(%[[VAL_37]], %[[VAL_38]], %[[VAL_18]], + allocate(c_shorter, c_deferred, c_longer, source=c_source) + +! Expect at runtime: +! ZZheZZ +! ZZhelloZZ +! ZZhello ZZ + write(*,"('ZZ',A,'ZZ')") c_shorter + write(*,"('ZZ',A,'ZZ')") c_deferred + write(*,"('ZZ',A,'ZZ')") c_longer +end subroutine + + call test() +end -- GitLab From 364028a1a51689d2b33d3ec50c426fbeac269679 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Mon, 8 Apr 2024 16:40:02 +0800 Subject: [PATCH 126/695] [RISCV] Zimop/Zcmop are ratified Remove them from experimental. See also: https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc Reviewers: kito-cheng Reviewed By: kito-cheng Pull Request: https://github.com/llvm/llvm-project/pull/87966 --- clang/test/Driver/riscv-profiles.c | 26 +++++++------- .../test/Preprocessor/riscv-target-features.c | 36 +++++++++---------- llvm/docs/RISCVUsage.rst | 6 ---- llvm/lib/Support/RISCVISAInfo.cpp | 26 +++++++------- llvm/lib/Target/RISCV/RISCVFeatures.td | 4 +-- llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td | 2 -- llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td | 2 -- llvm/test/CodeGen/RISCV/attributes.ll | 16 ++++----- .../test/CodeGen/RISCV/rv32zimop-intrinsic.ll | 2 +- .../test/CodeGen/RISCV/rv64zimop-intrinsic.ll | 2 +- llvm/test/MC/RISCV/attribute-arch.s | 2 +- llvm/test/MC/RISCV/compressed-zicfiss.s | 12 +++---- llvm/test/MC/RISCV/rv32zcmop-invalid.s | 2 +- llvm/test/MC/RISCV/rv32zimop-invalid.s | 2 +- llvm/test/MC/RISCV/rvzcmop-valid.s | 12 +++---- llvm/test/MC/RISCV/rvzimop-valid.s | 12 +++---- llvm/unittests/Support/RISCVISAInfoTest.cpp | 4 +-- 17 files changed, 78 insertions(+), 90 deletions(-) diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index ec9206f2f453..647567d4c971 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -111,7 +111,7 @@ // RVA22S64: "-target-feature" "+svinval" // RVA22S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23u64 \ // RUN: | FileCheck -check-prefix=RVA23U64 %s // RVA23U64: "-target-feature" "+m" // RVA23U64: "-target-feature" "+a" @@ -133,13 +133,13 @@ // RVA23U64: "-target-feature" "+zihintntl" // RVA23U64: "-target-feature" "+zihintpause" // RVA23U64: "-target-feature" "+zihpm" -// RVA23U64: "-target-feature" "+experimental-zimop" +// RVA23U64: "-target-feature" "+zimop" // RVA23U64: "-target-feature" "+za64rs" // RVA23U64: "-target-feature" "+zawrs" // RVA23U64: "-target-feature" "+zfa" // RVA23U64: "-target-feature" "+zfhmin" // RVA23U64: "-target-feature" "+zcb" -// RVA23U64: "-target-feature" "+experimental-zcmop" +// RVA23U64: "-target-feature" "+zcmop" // RVA23U64: "-target-feature" "+zba" // RVA23U64: "-target-feature" "+zbb" // RVA23U64: "-target-feature" "+zbs" @@ -172,13 +172,13 @@ // RVA23S64: "-target-feature" "+zihintntl" // RVA23S64: "-target-feature" "+zihintpause" // RVA23S64: "-target-feature" "+zihpm" -// RVA23S64: "-target-feature" "+experimental-zimop" +// RVA23S64: "-target-feature" "+zimop" // RVA23S64: "-target-feature" "+za64rs" // RVA23S64: "-target-feature" "+zawrs" // RVA23S64: "-target-feature" "+zfa" // RVA23S64: "-target-feature" "+zfhmin" // RVA23S64: "-target-feature" "+zcb" -// RVA23S64: "-target-feature" "+experimental-zcmop" +// RVA23S64: "-target-feature" "+zcmop" // RVA23S64: "-target-feature" "+zba" // RVA23S64: "-target-feature" "+zbb" // RVA23S64: "-target-feature" "+zbs" @@ -207,7 +207,7 @@ // RVA23S64: "-target-feature" "+svnapot" // RVA23S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23u64 \ // RUN: | FileCheck -check-prefix=RVB23U64 %s // RVB23U64: "-target-feature" "+m" // RVB23U64: "-target-feature" "+a" @@ -228,12 +228,12 @@ // RVB23U64: "-target-feature" "+zihintntl" // RVB23U64: "-target-feature" "+zihintpause" // RVB23U64: "-target-feature" "+zihpm" -// RVB23U64: "-target-feature" "+experimental-zimop" +// RVB23U64: "-target-feature" "+zimop" // RVB23U64: "-target-feature" "+za64rs" // RVB23U64: "-target-feature" "+zawrs" // RVB23U64: "-target-feature" "+zfa" // RVB23U64: "-target-feature" "+zcb" -// RVB23U64: "-target-feature" "+experimental-zcmop" +// RVB23U64: "-target-feature" "+zcmop" // RVB23U64: "-target-feature" "+zba" // RVB23U64: "-target-feature" "+zbb" // RVB23U64: "-target-feature" "+zbs" @@ -261,12 +261,12 @@ // RVB23S64: "-target-feature" "+zihintntl" // RVB23S64: "-target-feature" "+zihintpause" // RVB23S64: "-target-feature" "+zihpm" -// RVB23S64: "-target-feature" "+experimental-zimop" +// RVB23S64: "-target-feature" "+zimop" // RVB23S64: "-target-feature" "+za64rs" // RVB23S64: "-target-feature" "+zawrs" // RVB23S64: "-target-feature" "+zfa" // RVB23S64: "-target-feature" "+zcb" -// RVB23S64: "-target-feature" "+experimental-zcmop" +// RVB23S64: "-target-feature" "+zcmop" // RVB23S64: "-target-feature" "+zba" // RVB23S64: "-target-feature" "+zbb" // RVB23S64: "-target-feature" "+zbs" @@ -284,7 +284,7 @@ // RVB23S64: "-target-feature" "+svnapot" // RVB23S64: "-target-feature" "+svpbmt" -// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 -menable-experimental-extensions \ +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 \ // RUN: | FileCheck -check-prefix=RVM23U32 %s // RVM23U32: "-target-feature" "+m" // RVM23U32: "-target-feature" "+zicbop" @@ -292,9 +292,9 @@ // RVM23U32: "-target-feature" "+zicsr" // RVM23U32: "-target-feature" "+zihintntl" // RVM23U32: "-target-feature" "+zihintpause" -// RVM23U32: "-target-feature" "+experimental-zimop" +// RVM23U32: "-target-feature" "+zimop" // RVM23U32: "-target-feature" "+zce" -// RVM23U32: "-target-feature" "+experimental-zcmop" +// RVM23U32: "-target-feature" "+zcmop" // RVM23U32: "-target-feature" "+zba" // RVM23U32: "-target-feature" "+zbb" // RVM23U32: "-target-feature" "+zbs" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index dfc6d18dee50..ec7764bb5381 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -92,6 +92,7 @@ // CHECK-NOT: __riscv_zcd {{.*$}} // CHECK-NOT: __riscv_zce {{.*$}} // CHECK-NOT: __riscv_zcf {{.*$}} +// CHECK-NOT: __riscv_zcmop {{.*$}} // CHECK-NOT: __riscv_zcmp {{.*$}} // CHECK-NOT: __riscv_zcmt {{.*$}} // CHECK-NOT: __riscv_zdinx {{.*$}} @@ -116,6 +117,7 @@ // CHECK-NOT: __riscv_zihintntl {{.*$}} // CHECK-NOT: __riscv_zihintpause {{.*$}} // CHECK-NOT: __riscv_zihpm {{.*$}} +// CHECK-NOT: __riscv_zimop {{.*$}} // CHECK-NOT: __riscv_zk {{.*$}} // CHECK-NOT: __riscv_zkn {{.*$}} // CHECK-NOT: __riscv_zknd {{.*$}} @@ -173,11 +175,9 @@ // CHECK-NOT: __riscv_zaamo {{.*$}} // CHECK-NOT: __riscv_zalasr {{.*$}} // CHECK-NOT: __riscv_zalrsc {{.*$}} -// CHECK-NOT: __riscv_zcmop {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} // CHECK-NOT: __riscv_zicfilp {{.*$}} // CHECK-NOT: __riscv_zicfiss {{.*$}} -// CHECK-NOT: __riscv_zimop {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} // CHECK-NOT: __riscv_zvfbfmin {{.*$}} // CHECK-NOT: __riscv_zvfbfwma {{.*$}} @@ -830,6 +830,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s // CHECK-ZCF-EXT: __riscv_zcf 1000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32i_zcmop1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64i_zcmop1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s +// CHECK-ZCMOP-EXT: __riscv_zcmop 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izcmp1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZCMP-EXT %s @@ -1018,6 +1026,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZIHPM-EXT %s // CHECK-ZIHPM-EXT: __riscv_zihpm 2000000{{$}} +// RUN: %clang --target=riscv32-unknown-linux-gnu \ +// RUN: -march=rv32i_zimop1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s +// RUN: %clang --target=riscv64-unknown-linux-gnu \ +// RUN: -march=rv64i_zimop1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s +// CHECK-ZIMOP-EXT: __riscv_zimop 1000000{{$}} + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izk1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZK-EXT %s @@ -1561,22 +1577,6 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZICFILP-EXT %s // CHECK-ZICFILP-EXT: __riscv_zicfilp 4000{{$}} -// RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zimop0p1 -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s -// RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zimop0p1 -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZIMOP-EXT %s -// CHECK-ZIMOP-EXT: __riscv_zimop 1000{{$}} - -// RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zcmop0p2 -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s -// RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zcmop0p2 -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZCMOP-EXT %s -// CHECK-ZCMOP-EXT: __riscv_zcmop 2000{{$}} - // RUN: %clang --target=riscv32-unknown-linux-gnu -menable-experimental-extensions \ // RUN: -march=rv32iztso0p1 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 2f17c9d7dda0..283f258d7e5f 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -271,12 +271,6 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-ztso`` LLVM implements the `v0.1 proposed specification `__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware. -``experimental-zimop`` - LLVM implements the `v0.1 proposed specification `__. - -``experimental-zcmop`` - LLVM implements the `v0.2 proposed specification `__. - ``experimental-zaamo``, ``experimental-zalrsc`` LLVM implements the `v0.2 proposed specification `__. diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 67e6e5b962b1..7a19d24d1ff4 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -134,6 +134,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zcd", {1, 0}}, {"zce", {1, 0}}, {"zcf", {1, 0}}, + {"zcmop", {1, 0}}, {"zcmp", {1, 0}}, {"zcmt", {1, 0}}, @@ -162,6 +163,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zihintntl", {1, 0}}, {"zihintpause", {2, 0}}, {"zihpm", {2, 0}}, + {"zimop", {1, 0}}, {"zk", {1, 0}}, {"zkn", {1, 0}}, @@ -233,15 +235,11 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zalasr", {0, 1}}, {"zalrsc", {0, 2}}, - {"zcmop", {0, 2}}, - {"zfbfmin", {1, 0}}, {"zicfilp", {0, 4}}, {"zicfiss", {0, 4}}, - {"zimop", {0, 1}}, - {"ztso", {0, 1}}, {"zvfbfmin", {1, 0}}, @@ -264,25 +262,25 @@ static constexpr RISCVProfile SupportedProfiles[] = { "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"}, {"rva23u64", "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_zfa_" - "zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"}, + "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_" + "zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"}, {"rva23s64", "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_" - "zfa_zfhmin_zcb_zcmop0p2_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_" + "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" + "zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_" "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_" "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_" "svbare_svinval_svnapot_svpbmt"}, {"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_" "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_" - "zimop0p1_za64rs_zawrs_zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt"}, + "zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"}, {"rvb23s64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop0p1_za64rs_zawrs_" - "zfa_zcb_zcmop0p2_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_" - "sstvala_sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"}, - {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop0p1_" - "zca_zcb_zce_zcmop0p2_zcmp_zcmt_zba_zbb_zbs"}, + "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" + "zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_" + "sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"}, + {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_" + "zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"}, }; static void verifyTables() { diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 6ef2289bb4be..794455aa7304 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -104,7 +104,7 @@ def FeatureStdExtZihpm "'Zihpm' (Hardware Performance Counters)", [FeatureStdExtZicsr]>; -def FeatureStdExtZimop : SubtargetFeature<"experimental-zimop", "HasStdExtZimop", "true", +def FeatureStdExtZimop : SubtargetFeature<"zimop", "HasStdExtZimop", "true", "'Zimop' (May-Be-Operations)">; def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), @@ -390,7 +390,7 @@ def HasStdExtCOrZcfOrZce "'C' (Compressed Instructions) or " "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; -def FeatureStdExtZcmop : SubtargetFeature<"experimental-zcmop", "HasStdExtZcmop", "true", +def FeatureStdExtZcmop : SubtargetFeature<"zcmop", "HasStdExtZcmop", "true", "'Zcmop' (Compressed May-Be-Operations)", [FeatureStdExtZca]>; def HasStdExtZcmop : Predicate<"Subtarget->hasStdExtZcmop()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td index 6fbfde5ef488..dd13a07d606d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZcmop.td @@ -8,8 +8,6 @@ // // This file describes the RISC-V instructions from the standard Compressed // May-Be-Operations Extension (Zcmop). -// This version is still experimental as the 'Zcmop' extension hasn't been -// ratified yet. It is based on v0.2 of the specification. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td index f8ec099ca819..6b26550a2902 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td @@ -8,8 +8,6 @@ // // This file describes the RISC-V instructions from the standard // May-Be-Operations Extension (Zimop). -// This version is still experimental as the 'Zimop' extension hasn't been -// ratified yet. It is based on v0.1 of the specification. // //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index cc332df27104..2326599bf351 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -103,8 +103,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV32ZVKT %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV32ZVFH %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s +; RUN: llc -mtriple=riscv32 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV32ZIMOP %s +; RUN: llc -mtriple=riscv32 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV32ZCMOP %s ; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s @@ -233,8 +233,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+zvkt %s -o - | FileCheck --check-prefix=RV64ZVKT %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfh %s -o - | FileCheck --check-prefix=RV64ZVFH %s ; RUN: llc -mtriple=riscv64 -mattr=+zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s +; RUN: llc -mtriple=riscv64 -mattr=+zimop %s -o - | FileCheck --check-prefix=RV64ZIMOP %s +; RUN: llc -mtriple=riscv64 -mattr=+zcmop %s -o - | FileCheck --check-prefix=RV64ZCMOP %s ; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s @@ -358,8 +358,8 @@ ; RV32ZVKT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV32ZVFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" -; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop0p1" -; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop0p2" +; RV32ZIMOP: .attribute 5, "rv32i2p1_zimop1p0" +; RV32ZCMOP: .attribute 5, "rv32i2p1_zca1p0_zcmop1p0" ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0" ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" @@ -487,8 +487,8 @@ ; RV64ZVKT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkt1p0_zvl32b1p0" ; RV64ZVFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" -; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop0p1" -; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop0p2" +; RV64ZIMOP: .attribute 5, "rv64i2p1_zimop1p0" +; RV64ZCMOP: .attribute 5, "rv64i2p1_zca1p0_zcmop1p0" ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" diff --git a/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll index e5f36086f1cf..8e843fa47db6 100644 --- a/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zimop -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zimop -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZIMOP declare i32 @llvm.riscv.mopr.i32(i32 %a, i32 %b) diff --git a/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll index cd57739a955d..a407fe552ff7 100644 --- a/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zimop -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+zimop -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64ZIMOP declare i64 @llvm.riscv.mopr.i64(i64 %a, i64 %b) diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 09daeee2c1b3..a8f493f781ec 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -394,7 +394,7 @@ # CHECK: attribute 5, "rv32i2p1_zicfilp0p4" .attribute arch, "rv32i_zicfiss0p4" -# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop0p1" +# CHECK: .attribute 5, "rv32i2p1_zicfiss0p4_zicsr2p0_zimop1p0" .attribute arch, "rv64i_xsfvfwmaccqqq" # CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0" diff --git a/llvm/test/MC/RISCV/compressed-zicfiss.s b/llvm/test/MC/RISCV/compressed-zicfiss.s index 50ea2e24083e..2ebf9d3af3be 100644 --- a/llvm/test/MC/RISCV/compressed-zicfiss.s +++ b/llvm/test/MC/RISCV/compressed-zicfiss.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+experimental-zcmop -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+experimental-zcmop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+experimental-zcmop -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfiss,+zcmop < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+experimental-zcmop -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+experimental-zcmop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+experimental-zcmop -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfiss,+zcmop < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zicfiss,+zcmop -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ diff --git a/llvm/test/MC/RISCV/rv32zcmop-invalid.s b/llvm/test/MC/RISCV/rv32zcmop-invalid.s index 1641c8ddd00b..71d72d59b020 100644 --- a/llvm/test/MC/RISCV/rv32zcmop-invalid.s +++ b/llvm/test/MC/RISCV/rv32zcmop-invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zcmop < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+zcmop < %s 2>&1 | FileCheck %s cmop.0 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic diff --git a/llvm/test/MC/RISCV/rv32zimop-invalid.s b/llvm/test/MC/RISCV/rv32zimop-invalid.s index e6c3adc4cd30..e4672016bbf7 100644 --- a/llvm/test/MC/RISCV/rv32zimop-invalid.s +++ b/llvm/test/MC/RISCV/rv32zimop-invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zimop < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+zimop < %s 2>&1 | FileCheck %s # Too few operands mop.r.0 t0 # CHECK: :[[@LINE]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/rvzcmop-valid.s b/llvm/test/MC/RISCV/rvzcmop-valid.s index c26bb2959fed..c6bb4a158082 100644 --- a/llvm/test/MC/RISCV/rvzcmop-valid.s +++ b/llvm/test/MC/RISCV/rvzcmop-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zcmop -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcmop -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zcmop -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zcmop -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zcmop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zcmop -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcmop < %s \ +# RUN: | llvm-objdump --mattr=+zcmop -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zcmop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zcmop -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcmop < %s \ +# RUN: | llvm-objdump --mattr=+zcmop -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: cmop.1 diff --git a/llvm/test/MC/RISCV/rvzimop-valid.s b/llvm/test/MC/RISCV/rvzimop-valid.s index 155293662990..deb6d41f0445 100644 --- a/llvm/test/MC/RISCV/rvzimop-valid.s +++ b/llvm/test/MC/RISCV/rvzimop-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zimop -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zimop -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zimop -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+zimop -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zimop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zimop -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zimop < %s \ +# RUN: | llvm-objdump --mattr=+zimop -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zimop < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zimop -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zimop < %s \ +# RUN: | llvm-objdump --mattr=+zimop -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: mop.r.0 a2, a1 diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp index a331e6a74ceb..67012d2e6dc7 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -764,6 +764,7 @@ R"(All available -march extensions for RISC-V zihintntl 1.0 zihintpause 2.0 zihpm 2.0 + zimop 1.0 zmmul 1.0 za128rs 1.0 za64rs 1.0 @@ -779,6 +780,7 @@ R"(All available -march extensions for RISC-V zcd 1.0 zce 1.0 zcf 1.0 + zcmop 1.0 zcmp 1.0 zcmt 1.0 zba 1.0 @@ -890,13 +892,11 @@ R"(All available -march extensions for RISC-V Experimental extensions zicfilp 0.4 This is a long dummy description zicfiss 0.4 - zimop 0.1 zaamo 0.2 zabha 1.0 zalasr 0.1 zalrsc 0.2 zfbfmin 1.0 - zcmop 0.2 ztso 0.1 zvfbfmin 1.0 zvfbfwma 1.0 -- GitLab From 221f438af1c1292d787b58da99a5a7b371888456 Mon Sep 17 00:00:00 2001 From: Mats Petersson Date: Mon, 8 Apr 2024 10:18:14 +0100 Subject: [PATCH 127/695] [flang][OpenMP] Add support for complex reductions (#87488) This adds support for complex type to the OpenMP reductions. Note that some more work would be needed to give decent error messages when complex is used in ways that need client supplied functions (e.g. MAX or MIN). It does fail these with a not so user friendly message at present. --- flang/lib/Lower/OpenMP/ReductionProcessor.cpp | 22 ++++++-- flang/lib/Lower/OpenMP/ReductionProcessor.h | 21 +++++++- .../OpenMP/parallel-reduction-complex-mul.f90 | 50 +++++++++++++++++++ .../OpenMP/parallel-reduction-complex.f90 | 50 +++++++++++++++++++ 4 files changed, 137 insertions(+), 6 deletions(-) create mode 100644 flang/test/Lower/OpenMP/parallel-reduction-complex-mul.f90 create mode 100644 flang/test/Lower/OpenMP/parallel-reduction-complex.f90 diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp index c1c94119fd90..0453c0152277 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp @@ -13,7 +13,9 @@ #include "ReductionProcessor.h" #include "flang/Lower/AbstractConverter.h" +#include "flang/Lower/ConvertType.h" #include "flang/Lower/SymbolMap.h" +#include "flang/Optimizer/Builder/Complex.h" #include "flang/Optimizer/Builder/HLFIRTools.h" #include "flang/Optimizer/Builder/Todo.h" #include "flang/Optimizer/Dialect/FIRType.h" @@ -131,7 +133,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, fir::FirOpBuilder &builder) { type = fir::unwrapRefType(type); if (!fir::isa_integer(type) && !fir::isa_real(type) && - !mlir::isa(type)) + !fir::isa_complex(type) && !mlir::isa(type)) TODO(loc, "Reduction of some types is not supported"); switch (redId) { case ReductionIdentifier::MAX: { @@ -175,6 +177,16 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, case ReductionIdentifier::OR: case ReductionIdentifier::EQV: case ReductionIdentifier::NEQV: + if (auto cplxTy = mlir::dyn_cast(type)) { + mlir::Type realTy = + Fortran::lower::convertReal(builder.getContext(), cplxTy.getFKind()); + mlir::Value initRe = builder.createRealConstant( + loc, realTy, getOperationIdentity(redId, loc)); + mlir::Value initIm = builder.createRealConstant(loc, realTy, 0); + + return fir::factory::Complex{builder, loc}.createComplex(type, initRe, + initIm); + } if (type.isa()) return builder.create( loc, type, @@ -229,13 +241,13 @@ mlir::Value ReductionProcessor::createScalarCombiner( break; case ReductionIdentifier::ADD: reductionOp = - getReductionOperation( - builder, type, loc, op1, op2); + getReductionOperation(builder, type, loc, op1, op2); break; case ReductionIdentifier::MULTIPLY: reductionOp = - getReductionOperation( - builder, type, loc, op1, op2); + getReductionOperation(builder, type, loc, op1, op2); break; case ReductionIdentifier::AND: { mlir::Value op1I1 = builder.createConvert(loc, builder.getI1Type(), op1); diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.h b/flang/lib/Lower/OpenMP/ReductionProcessor.h index ee2732547fc2..7ea252fde360 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.h +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.h @@ -97,6 +97,10 @@ public: fir::FirOpBuilder &builder); template + static mlir::Value getReductionOperation(fir::FirOpBuilder &builder, + mlir::Type type, mlir::Location loc, + mlir::Value op1, mlir::Value op2); + template static mlir::Value getReductionOperation(fir::FirOpBuilder &builder, mlir::Type type, mlir::Location loc, mlir::Value op1, mlir::Value op2); @@ -136,12 +140,27 @@ ReductionProcessor::getReductionOperation(fir::FirOpBuilder &builder, mlir::Value op1, mlir::Value op2) { type = fir::unwrapRefType(type); assert(type.isIntOrIndexOrFloat() && - "only integer and float types are currently supported"); + "only integer, float and complex types are currently supported"); if (type.isIntOrIndex()) return builder.create(loc, op1, op2); return builder.create(loc, op1, op2); } +template +mlir::Value +ReductionProcessor::getReductionOperation(fir::FirOpBuilder &builder, + mlir::Type type, mlir::Location loc, + mlir::Value op1, mlir::Value op2) { + assert(type.isIntOrIndexOrFloat() || + fir::isa_complex(type) && + "only integer, float and complex types are currently supported"); + if (type.isIntOrIndex()) + return builder.create(loc, op1, op2); + if (fir::isa_real(type)) + return builder.create(loc, op1, op2); + return builder.create(loc, op1, op2); +} + } // namespace omp } // namespace lower } // namespace Fortran diff --git a/flang/test/Lower/OpenMP/parallel-reduction-complex-mul.f90 b/flang/test/Lower/OpenMP/parallel-reduction-complex-mul.f90 new file mode 100644 index 000000000000..376defb82358 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-reduction-complex-mul.f90 @@ -0,0 +1,50 @@ +! RUN: bbc -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s + +!CHECK-LABEL: omp.declare_reduction +!CHECK-SAME: @[[RED_NAME:.*]] : !fir.complex<8> init { +!CHECK: ^bb0(%{{.*}}: !fir.complex<8>): +!CHECK: %[[C0_1:.*]] = arith.constant 1.000000e+00 : f64 +!CHECK: %[[C0_2:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[UNDEF:.*]] = fir.undefined !fir.complex<8> +!CHECK: %[[RES_1:.*]] = fir.insert_value %[[UNDEF]], %[[C0_1]], [0 : index] +!CHECK: %[[RES_2:.*]] = fir.insert_value %[[RES_1]], %[[C0_2]], [1 : index] +!CHECK: omp.yield(%[[RES_2]] : !fir.complex<8>) +!CHECK: } combiner { +!CHECK: ^bb0(%[[ARG0:.*]]: !fir.complex<8>, %[[ARG1:.*]]: !fir.complex<8>): +!CHECK: %[[RES:.*]] = fir.mulc %[[ARG0]], %[[ARG1]] {{.*}}: !fir.complex<8> +!CHECK: omp.yield(%[[RES]] : !fir.complex<8>) +!CHECK: } + +!CHECK-LABEL: func.func @_QPsimple_complex_mul +!CHECK: %[[CREF:.*]] = fir.alloca !fir.complex<8> {bindc_name = "c", {{.*}}} +!CHECK: %[[C_DECL:.*]]:2 = hlfir.declare %[[CREF]] {uniq_name = "_QFsimple_complex_mulEc"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[C_START_RE:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[C_START_IM:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[UNDEF_1:.*]] = fir.undefined !fir.complex<8> +!CHECK: %[[VAL_1:.*]] = fir.insert_value %[[UNDEF_1]], %[[C_START_RE]], [0 : index] +!CHECK: %[[VAL_2:.*]] = fir.insert_value %[[VAL_1]], %[[C_START_IM]], [1 : index] +!CHECK: hlfir.assign %[[VAL_2]] to %[[C_DECL]]#0 : !fir.complex<8>, !fir.ref> +!CHECK: omp.parallel reduction(@[[RED_NAME]] %[[C_DECL]]#0 -> %[[PRV:.+]] : !fir.ref>) { +!CHECK: %[[P_DECL:.+]]:2 = hlfir.declare %[[PRV]] {{.*}} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[LPRV:.+]] = fir.load %[[P_DECL]]#0 : !fir.ref> +!CHECK: %[[C_INCR_RE:.*]] = arith.constant 1.000000e+00 : f64 +!CHECK: %[[C_INCR_IM:.*]] = arith.constant -2.000000e+00 : f64 +!CHECK: %[[UNDEF_2:.*]] = fir.undefined !fir.complex<8> +!CHECK: %[[INCR_1:.*]] = fir.insert_value %[[UNDEF_2]], %[[C_INCR_RE]], [0 : index] +!CHECK: %[[INCR_2:.*]] = fir.insert_value %[[INCR_1]], %[[C_INCR_IM]], [1 : index] +!CHECK: %[[RES:.+]] = fir.mulc %[[LPRV]], %[[INCR_2]] {{.*}} : !fir.complex<8> +!CHECK: hlfir.assign %[[RES]] to %[[P_DECL]]#0 : !fir.complex<8>, !fir.ref> +!CHECK: omp.terminator +!CHECK: } +!CHECK: return +subroutine simple_complex_mul + complex(8) :: c + c = 0 + + !$omp parallel reduction(*:c) + c = c * cmplx(1, -2) + !$omp end parallel + + print *, c +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-reduction-complex.f90 b/flang/test/Lower/OpenMP/parallel-reduction-complex.f90 new file mode 100644 index 000000000000..bc5a6b475e25 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-reduction-complex.f90 @@ -0,0 +1,50 @@ +! RUN: bbc -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s + +!CHECK-LABEL: omp.declare_reduction +!CHECK-SAME: @[[RED_NAME:.*]] : !fir.complex<8> init { +!CHECK: ^bb0(%{{.*}}: !fir.complex<8>): +!CHECK: %[[C0_1:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[C0_2:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[UNDEF:.*]] = fir.undefined !fir.complex<8> +!CHECK: %[[RES_1:.*]] = fir.insert_value %[[UNDEF]], %[[C0_1]], [0 : index] +!CHECK: %[[RES_2:.*]] = fir.insert_value %[[RES_1]], %[[C0_2]], [1 : index] +!CHECK: omp.yield(%[[RES_2]] : !fir.complex<8>) +!CHECK: } combiner { +!CHECK: ^bb0(%[[ARG0:.*]]: !fir.complex<8>, %[[ARG1:.*]]: !fir.complex<8>): +!CHECK: %[[RES:.*]] = fir.addc %[[ARG0]], %[[ARG1]] {{.*}}: !fir.complex<8> +!CHECK: omp.yield(%[[RES]] : !fir.complex<8>) +!CHECK: } + +!CHECK-LABEL: func.func @_QPsimple_complex_add +!CHECK: %[[CREF:.*]] = fir.alloca !fir.complex<8> {bindc_name = "c", {{.*}}} +!CHECK: %[[C_DECL:.*]]:2 = hlfir.declare %[[CREF]] {uniq_name = "_QFsimple_complex_addEc"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[C_START_RE:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[C_START_IM:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[UNDEF_1:.*]] = fir.undefined !fir.complex<8> +!CHECK: %[[VAL_1:.*]] = fir.insert_value %[[UNDEF_1]], %[[C_START_RE]], [0 : index] +!CHECK: %[[VAL_2:.*]] = fir.insert_value %[[VAL_1]], %[[C_START_IM]], [1 : index] +!CHECK: hlfir.assign %[[VAL_2]] to %[[C_DECL]]#0 : !fir.complex<8>, !fir.ref> +!CHECK: omp.parallel reduction(@[[RED_NAME]] %[[C_DECL]]#0 -> %[[PRV:.+]] : !fir.ref>) { +!CHECK: %[[P_DECL:.+]]:2 = hlfir.declare %[[PRV]] {{.*}} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +!CHECK: %[[LPRV:.+]] = fir.load %[[P_DECL]]#0 : !fir.ref> +!CHECK: %[[C_INCR_RE:.*]] = arith.constant 1.000000e+00 : f64 +!CHECK: %[[C_INCR_IM:.*]] = arith.constant 0.000000e+00 : f64 +!CHECK: %[[UNDEF_2:.*]] = fir.undefined !fir.complex<8> +!CHECK: %[[INCR_1:.*]] = fir.insert_value %[[UNDEF_2]], %[[C_INCR_RE]], [0 : index] +!CHECK: %[[INCR_2:.*]] = fir.insert_value %[[INCR_1]], %[[C_INCR_IM]], [1 : index] +!CHECK: %[[RES:.+]] = fir.addc %[[LPRV]], %[[INCR_2]] {{.*}} : !fir.complex<8> +!CHECK: hlfir.assign %[[RES]] to %[[P_DECL]]#0 : !fir.complex<8>, !fir.ref> +!CHECK: omp.terminator +!CHECK: } +!CHECK: return +subroutine simple_complex_add + complex(8) :: c + c = 0 + + !$omp parallel reduction(+:c) + c = c + 1 + !$omp end parallel + + print *, c +end subroutine -- GitLab From cf7d36fe342c5c5ac39150ca0b4b70a3d17ae66b Mon Sep 17 00:00:00 2001 From: Zentrik Date: Mon, 8 Apr 2024 10:18:59 +0100 Subject: [PATCH 128/695] [NFC] Fix misspellings of effects (#87795) --- .../lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp | 2 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp index 6cc886794581..845a5f9b390d 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp @@ -30,7 +30,7 @@ // was not consciously intended, and therefore it might have been unreachable. // // This checker uses eval::Call for modeling pure functions (functions without -// side effets), for which their `Summary' is a precise model. This avoids +// side effects), for which their `Summary' is a precise model. This avoids // unnecessary invalidation passes. Conflicts with other checkers are unlikely // because if the function has no other effects, other checkers would probably // never want to improve upon the modeling done by this checker. diff --git a/llvm/lib/Transforms/Scalar/NewGVN.cpp b/llvm/lib/Transforms/Scalar/NewGVN.cpp index 9caaf720ec91..056be8629b96 100644 --- a/llvm/lib/Transforms/Scalar/NewGVN.cpp +++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp @@ -4019,7 +4019,7 @@ bool NewGVN::eliminateInstructions(Function &F) { // dominated defs as dead. if (Def) { // For anything in this case, what and how we value number - // guarantees that any side-effets that would have occurred (ie + // guarantees that any side-effects that would have occurred (ie // throwing, etc) can be proven to either still occur (because it's // dominated by something that has the same side-effects), or never // occur. Otherwise, we would not have been able to prove it value -- GitLab From 170c525d79a4ab3659041b0655ac9697768fc915 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Apr 2024 11:01:06 +0100 Subject: [PATCH 129/695] [X86] combineExtractVectorElt - fold extract(trunc(x),c) -> trunc(extract(x,c)) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 11 +++++++ .../test/CodeGen/X86/avx512-insert-extract.ll | 29 ++++++---------- .../CodeGen/X86/insertelement-var-index.ll | 22 ++++++------- llvm/test/CodeGen/X86/movmsk-cmp.ll | 16 +++------ llvm/test/CodeGen/X86/pr63439.ll | 33 +++++++------------ llvm/test/CodeGen/X86/pr64439.ll | 7 ++-- llvm/test/CodeGen/X86/vec_cast.ll | 2 +- 7 files changed, 52 insertions(+), 68 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6f65344215c0..f24e0fc25fac 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -44710,6 +44710,17 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG, } } + // Attempt to fold extract(trunc(x),c) -> trunc(extract(x,c)). + if (CIdx && InputVector.getOpcode() == ISD::TRUNCATE) { + SDValue TruncSrc = InputVector.getOperand(0); + EVT TruncSVT = TruncSrc.getValueType().getScalarType(); + if (DCI.isBeforeLegalize() && TLI.isTypeLegal(TruncSVT)) { + SDValue NewExt = + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TruncSVT, TruncSrc, EltIdx); + return DAG.getAnyExtOrTrunc(NewExt, dl, VT); + } + } + return SDValue(); } diff --git a/llvm/test/CodeGen/X86/avx512-insert-extract.ll b/llvm/test/CodeGen/X86/avx512-insert-extract.ll index 3e40bfa1e791..2a77d0238721 100644 --- a/llvm/test/CodeGen/X86/avx512-insert-extract.ll +++ b/llvm/test/CodeGen/X86/avx512-insert-extract.ll @@ -1050,11 +1050,9 @@ define zeroext i8 @test_extractelement_v32i1(<32 x i8> %a, <32 x i8> %b) nounwin ; KNL: ## %bb.0: ; KNL-NEXT: vpminub %xmm1, %xmm0, %xmm1 ; KNL-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 -; KNL-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 -; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 -; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 -; KNL-NEXT: kshiftrw $2, %k0, %k0 -; KNL-NEXT: kmovw %k0, %eax +; KNL-NEXT: vpextrb $2, %xmm0, %eax +; KNL-NEXT: notb %al +; KNL-NEXT: movzbl %al, %eax ; KNL-NEXT: andl $1, %eax ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq @@ -1081,11 +1079,9 @@ define zeroext i8 @test_extractelement_v64i1(<64 x i8> %a, <64 x i8> %b) nounwin ; KNL-NEXT: vpminub %ymm1, %ymm0, %ymm1 ; KNL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; KNL-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 -; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 -; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 -; KNL-NEXT: kshiftrw $15, %k0, %k0 -; KNL-NEXT: kmovw %k0, %ecx +; KNL-NEXT: vpextrb $15, %xmm0, %eax +; KNL-NEXT: notb %al +; KNL-NEXT: movzbl %al, %ecx ; KNL-NEXT: andl $1, %ecx ; KNL-NEXT: movl $4, %eax ; KNL-NEXT: subl %ecx, %eax @@ -1116,15 +1112,10 @@ define zeroext i8 @extractelement_v64i1_alt(<64 x i8> %a, <64 x i8> %b) nounwind ; KNL-NEXT: vpminub %ymm1, %ymm0, %ymm1 ; KNL-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm0 ; KNL-NEXT: vextracti128 $1, %ymm0, %xmm0 -; KNL-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0 -; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 -; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 -; KNL-NEXT: kshiftrw $15, %k0, %k0 -; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: andb $1, %al -; KNL-NEXT: movb $4, %cl -; KNL-NEXT: subb %al, %cl -; KNL-NEXT: movzbl %cl, %eax +; KNL-NEXT: vpextrb $15, %xmm0, %eax +; KNL-NEXT: notb %al +; KNL-NEXT: addb $4, %al +; KNL-NEXT: movzbl %al, %eax ; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/insertelement-var-index.ll b/llvm/test/CodeGen/X86/insertelement-var-index.ll index 5420e6b5ce86..16946caf9a32 100644 --- a/llvm/test/CodeGen/X86/insertelement-var-index.ll +++ b/llvm/test/CodeGen/X86/insertelement-var-index.ll @@ -2294,13 +2294,13 @@ define i32 @PR44139(ptr %p) { ; ; AVX1-LABEL: PR44139: ; AVX1: # %bb.0: +; AVX1-NEXT: movq (%rdi), %rax ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm0 -; AVX1-NEXT: vpinsrq $1, (%rdi), %xmm0, %xmm1 +; AVX1-NEXT: vpinsrq $1, %rax, %xmm0, %xmm1 ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX1-NEXT: vmovaps %ymm0, 64(%rdi) ; AVX1-NEXT: vmovaps %ymm0, 96(%rdi) ; AVX1-NEXT: vmovaps %ymm0, 32(%rdi) -; AVX1-NEXT: movl (%rdi), %eax ; AVX1-NEXT: vmovaps %ymm1, (%rdi) ; AVX1-NEXT: leal 2147483647(%rax), %ecx ; AVX1-NEXT: testl %eax, %eax @@ -2315,13 +2315,13 @@ define i32 @PR44139(ptr %p) { ; ; AVX2-LABEL: PR44139: ; AVX2: # %bb.0: +; AVX2-NEXT: movq (%rdi), %rax ; AVX2-NEXT: vpbroadcastq (%rdi), %ymm0 -; AVX2-NEXT: vpinsrq $1, (%rdi), %xmm0, %xmm1 +; AVX2-NEXT: vpinsrq $1, %rax, %xmm0, %xmm1 ; AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm0[4,5,6,7] ; AVX2-NEXT: vmovdqa %ymm0, 64(%rdi) ; AVX2-NEXT: vmovdqa %ymm0, 96(%rdi) ; AVX2-NEXT: vmovdqa %ymm0, 32(%rdi) -; AVX2-NEXT: movl (%rdi), %eax ; AVX2-NEXT: vmovdqa %ymm1, (%rdi) ; AVX2-NEXT: leal 2147483647(%rax), %ecx ; AVX2-NEXT: testl %eax, %eax @@ -2336,14 +2336,12 @@ define i32 @PR44139(ptr %p) { ; ; AVX512-LABEL: PR44139: ; AVX512: # %bb.0: -; AVX512-NEXT: vmovdqa64 (%rdi), %zmm0 -; AVX512-NEXT: vpbroadcastq (%rdi), %zmm1 -; AVX512-NEXT: vpmovqd %zmm0, %ymm0 -; AVX512-NEXT: vpinsrq $1, (%rdi), %xmm1, %xmm2 -; AVX512-NEXT: vinserti32x4 $0, %xmm2, %zmm1, %zmm2 -; AVX512-NEXT: vmovdqa64 %zmm1, 64(%rdi) -; AVX512-NEXT: vmovdqa64 %zmm2, (%rdi) -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: movq (%rdi), %rax +; AVX512-NEXT: vpbroadcastq (%rdi), %zmm0 +; AVX512-NEXT: vpinsrq $1, %rax, %xmm0, %xmm1 +; AVX512-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm1 +; AVX512-NEXT: vmovdqa64 %zmm0, 64(%rdi) +; AVX512-NEXT: vmovdqa64 %zmm1, (%rdi) ; AVX512-NEXT: leal 2147483647(%rax), %ecx ; AVX512-NEXT: testl %eax, %eax ; AVX512-NEXT: cmovnsl %eax, %ecx diff --git a/llvm/test/CodeGen/X86/movmsk-cmp.ll b/llvm/test/CodeGen/X86/movmsk-cmp.ll index e8b3121ecfb5..253f990f8735 100644 --- a/llvm/test/CodeGen/X86/movmsk-cmp.ll +++ b/llvm/test/CodeGen/X86/movmsk-cmp.ll @@ -3682,18 +3682,12 @@ define i1 @movmsk_v16i8(<16 x i8> %x, <16 x i8> %y) { ; KNL-LABEL: movmsk_v16i8: ; KNL: # %bb.0: ; KNL-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm0 -; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 -; KNL-NEXT: vptestmd %zmm0, %zmm0, %k0 -; KNL-NEXT: kshiftrw $15, %k0, %k1 -; KNL-NEXT: kmovw %k1, %ecx -; KNL-NEXT: kshiftrw $8, %k0, %k1 -; KNL-NEXT: kmovw %k1, %edx -; KNL-NEXT: kshiftrw $3, %k0, %k0 -; KNL-NEXT: kmovw %k0, %eax -; KNL-NEXT: xorb %dl, %al -; KNL-NEXT: andb %cl, %al +; KNL-NEXT: vpextrb $15, %xmm0, %ecx +; KNL-NEXT: vpextrb $8, %xmm0, %edx +; KNL-NEXT: vpextrb $3, %xmm0, %eax +; KNL-NEXT: xorl %edx, %eax +; KNL-NEXT: andl %ecx, %eax ; KNL-NEXT: # kill: def $al killed $al killed $eax -; KNL-NEXT: vzeroupper ; KNL-NEXT: retq ; ; SKX-LABEL: movmsk_v16i8: diff --git a/llvm/test/CodeGen/X86/pr63439.ll b/llvm/test/CodeGen/X86/pr63439.ll index 155da0c62912..7018940faa81 100644 --- a/llvm/test/CodeGen/X86/pr63439.ll +++ b/llvm/test/CodeGen/X86/pr63439.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE -; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX +; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s define i16 @mulhs(i16 %a0, i16 %a1) { ; CHECK-LABEL: mulhs: ; CHECK: # %bb.0: -; CHECK-NEXT: movswl %si, %ecx -; CHECK-NEXT: movswl %di, %eax +; CHECK-NEXT: movswl %di, %ecx +; CHECK-NEXT: movswl %si, %eax ; CHECK-NEXT: imull %ecx, %eax ; CHECK-NEXT: shrl $16, %eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax @@ -23,23 +23,14 @@ define i16 @mulhs(i16 %a0, i16 %a1) { } define i16 @mulhu(i16 %a0, i16 %a1) { -; SSE-LABEL: mulhu: -; SSE: # %bb.0: -; SSE-NEXT: movzwl %si, %ecx -; SSE-NEXT: movzwl %di, %eax -; SSE-NEXT: imull %ecx, %eax -; SSE-NEXT: shrl $16, %eax -; SSE-NEXT: # kill: def $ax killed $ax killed $eax -; SSE-NEXT: retq -; -; AVX-LABEL: mulhu: -; AVX: # %bb.0: -; AVX-NEXT: vmovd %edi, %xmm0 -; AVX-NEXT: vmovd %esi, %xmm1 -; AVX-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vmovd %xmm0, %eax -; AVX-NEXT: # kill: def $ax killed $ax killed $eax -; AVX-NEXT: retq +; CHECK-LABEL: mulhu: +; CHECK: # %bb.0: +; CHECK-NEXT: movzwl %di, %ecx +; CHECK-NEXT: movzwl %si, %eax +; CHECK-NEXT: imull %ecx, %eax +; CHECK-NEXT: shrl $16, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: retq %x0 = zext i16 %a0 to i32 %x1 = zext i16 %a1 to i32 %v0 = insertelement <1 x i32> , i32 %x0, i32 0 diff --git a/llvm/test/CodeGen/X86/pr64439.ll b/llvm/test/CodeGen/X86/pr64439.ll index 7aa52fc49a9f..6e3d007dd78c 100644 --- a/llvm/test/CodeGen/X86/pr64439.ll +++ b/llvm/test/CodeGen/X86/pr64439.ll @@ -4,10 +4,9 @@ define void @f(ptr %0, <32 x i1> %1, i32 %2) nounwind { ; CHECK-LABEL: f: ; CHECK: # %bb.0: -; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0 -; CHECK-NEXT: vpmovb2m %ymm0, %k0 -; CHECK-NEXT: kshiftrd $3, %k0, %k1 -; CHECK-NEXT: kmovd %k1, %eax +; CHECK-NEXT: vpsllw $7, %ymm0, %ymm1 +; CHECK-NEXT: vpmovb2m %ymm1, %k0 +; CHECK-NEXT: vpextrb $3, %xmm0, %eax ; CHECK-NEXT: vpbroadcastb %esi, %ymm0 ; CHECK-NEXT: vpcmpeqb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k1 ; CHECK-NEXT: vpmovm2b %k0, %ymm0 diff --git a/llvm/test/CodeGen/X86/vec_cast.ll b/llvm/test/CodeGen/X86/vec_cast.ll index 0a6bc2f59b68..e0089354cc95 100644 --- a/llvm/test/CodeGen/X86/vec_cast.ll +++ b/llvm/test/CodeGen/X86/vec_cast.ll @@ -156,7 +156,7 @@ define <3 x i16> @h(<3 x i32> %a) nounwind { ; CHECK-WIN-LABEL: h: ; CHECK-WIN: # %bb.0: ; CHECK-WIN-NEXT: movdqa (%rcx), %xmm0 -; CHECK-WIN-NEXT: movd %xmm0, %eax +; CHECK-WIN-NEXT: movl (%rcx), %eax ; CHECK-WIN-NEXT: pextrw $2, %xmm0, %edx ; CHECK-WIN-NEXT: pextrw $4, %xmm0, %ecx ; CHECK-WIN-NEXT: # kill: def $ax killed $ax killed $eax -- GitLab From 8461d901a770516cf2069fe3bce979a6f8fc8d76 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Mon, 8 Apr 2024 11:01:58 +0100 Subject: [PATCH 130/695] [libclc] Restore linking against dynamic libLLVM for out-of-tree builds This fixes a regression where building against an installation without the static libraries would fail. This just reinstates the old behaviour for out-of-tree builds, assuming that in-tree builds (which still aren't officially supported) will have the static libraries available. We can refine this as we move towards supporting in-tree builds. --- libclc/CMakeLists.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt index 21e5cac68822..8750a65a717f 100644 --- a/libclc/CMakeLists.txt +++ b/libclc/CMakeLists.txt @@ -122,7 +122,11 @@ set(LLVM_LINK_COMPONENTS IRReader Support ) -add_llvm_utility( prepare_builtins utils/prepare-builtins.cpp ) +if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) + add_llvm_executable( prepare_builtins utils/prepare-builtins.cpp ) +else() + add_llvm_utility( prepare_builtins utils/prepare-builtins.cpp ) +endif() target_compile_definitions( prepare_builtins PRIVATE ${LLVM_VERSION_DEFINE} ) # These were not properly reported in early LLVM and we don't need them target_compile_options( prepare_builtins PRIVATE -fno-rtti -fno-exceptions ) -- GitLab From c2067c1f471ac54312cb5e1e0efd4ea5fd21cc79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bal=C3=A1zs=20K=C3=A9ri?= Date: Mon, 8 Apr 2024 12:19:03 +0200 Subject: [PATCH 131/695] [clang][analyzer] Add "pedantic" mode to StreamChecker. (#87322) The checker may create failure branches for all stream write operations only if the new option "pedantic" is set to true. Result of the write operations is often not checked in typical code. If failure branches are created the checker will warn for unchecked write operations and generate a lot of "false positives" (these are valid warnings but the programmer does not care about this problem). --- clang/docs/analyzer/checkers.rst | 21 +++- .../clang/StaticAnalyzer/Checkers/Checkers.td | 9 ++ .../StaticAnalyzer/Checkers/StreamChecker.cpp | 32 +++++-- clang/test/Analysis/analyzer-config.c | 1 + ...td-c-library-functions-vs-stream-checker.c | 2 + clang/test/Analysis/stream-errno-note.c | 1 + clang/test/Analysis/stream-errno.c | 1 + clang/test/Analysis/stream-error.c | 1 + clang/test/Analysis/stream-note.c | 2 + clang/test/Analysis/stream-pedantic.c | 95 +++++++++++++++++++ .../Analysis/stream-stdlibraryfunctionargs.c | 3 + clang/test/Analysis/stream.c | 12 ++- 12 files changed, 166 insertions(+), 14 deletions(-) create mode 100644 clang/test/Analysis/stream-pedantic.c diff --git a/clang/docs/analyzer/checkers.rst b/clang/docs/analyzer/checkers.rst index f188f18ba555..fb748d23a53d 100644 --- a/clang/docs/analyzer/checkers.rst +++ b/clang/docs/analyzer/checkers.rst @@ -3138,10 +3138,16 @@ are detected: allowed in this state. * Invalid 3rd ("``whence``") argument to ``fseek``. -The checker does not track the correspondence between integer file descriptors -and ``FILE *`` pointers. Operations on standard streams like ``stdin`` are not -treated specially and are therefore often not recognized (because these streams -are usually not opened explicitly by the program, and are global variables). +The stream operations are by this checker usually split into two cases, a success +and a failure case. However, in the case of write operations (like ``fwrite``, +``fprintf`` and even ``fsetpos``) this behavior could produce a large amount of +unwanted reports on projects that don't have error checks around the write +operations, so by default the checker assumes that write operations always succeed. +This behavior can be controlled by the ``Pedantic`` flag: With +``-analyzer-config alpha.unix.Stream:Pedantic=true`` the checker will model the +cases where a write operation fails and report situations where this leads to +erroneous behavior. (The default is ``Pedantic=false``, where write operations +are assumed to succeed.) .. code-block:: c @@ -3196,6 +3202,13 @@ are usually not opened explicitly by the program, and are global variables). fclose(p); } +**Limitations** + +The checker does not track the correspondence between integer file descriptors +and ``FILE *`` pointers. Operations on standard streams like ``stdin`` are not +treated specially and are therefore often not recognized (because these streams +are usually not opened explicitly by the program, and are global variables). + .. _alpha-unix-cstring-BufferOverlap: alpha.unix.cstring.BufferOverlap (C) diff --git a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td index 5fe5c9286dab..9aa1c6ddfe44 100644 --- a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td +++ b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td @@ -604,6 +604,15 @@ def PthreadLockChecker : Checker<"PthreadLock">, def StreamChecker : Checker<"Stream">, HelpText<"Check stream handling functions">, WeakDependencies<[NonNullParamChecker]>, + CheckerOptions<[ + CmdLineOption + ]>, Documentation; def SimpleStreamChecker : Checker<"SimpleStream">, diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index 069e3a633c12..31c756ab0c58 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -297,6 +297,9 @@ public: /// If true, evaluate special testing stream functions. bool TestMode = false; + /// If true, generate failure branches for cases that are often not checked. + bool PedanticMode = false; + private: CallDescriptionMap FnDescriptions = { {{{"fopen"}, 2}, {nullptr, &StreamChecker::evalFopen, ArgNone}}, @@ -945,6 +948,10 @@ void StreamChecker::evalFreadFwrite(const FnDescription *Desc, } // Add transition for the failed state. + // At write, add failure case only if "pedantic mode" is on. + if (!IsFread && !PedanticMode) + return; + NonLoc RetVal = makeRetVal(C, E.CE).castAs(); ProgramStateRef StateFailed = State->BindExpr(E.CE, C.getLocationContext(), RetVal); @@ -1057,6 +1064,9 @@ void StreamChecker::evalFputx(const FnDescription *Desc, const CallEvent &Call, C.addTransition(StateNotFailed); } + if (!PedanticMode) + return; + // Add transition for the failed state. The resulting value of the file // position indicator for the stream is indeterminate. ProgramStateRef StateFailed = E.bindReturnValue(State, C, *EofVal); @@ -1092,6 +1102,9 @@ void StreamChecker::evalFprintf(const FnDescription *Desc, E.setStreamState(StateNotFailed, StreamState::getOpened(Desc)); C.addTransition(StateNotFailed); + if (!PedanticMode) + return; + // Add transition for the failed state. The resulting value of the file // position indicator for the stream is indeterminate. StateFailed = E.setStreamState( @@ -1264,21 +1277,23 @@ void StreamChecker::evalFseek(const FnDescription *Desc, const CallEvent &Call, if (!E.Init(Desc, Call, C, State)) return; - // Bifurcate the state into failed and non-failed. - // Return zero on success, -1 on error. + // Add success state. ProgramStateRef StateNotFailed = E.bindReturnValue(State, C, 0); - ProgramStateRef StateFailed = E.bindReturnValue(State, C, -1); - // No failure: Reset the state to opened with no error. StateNotFailed = E.setStreamState(StateNotFailed, StreamState::getOpened(Desc)); C.addTransition(StateNotFailed); + if (!PedanticMode) + return; + + // Add failure state. // At error it is possible that fseek fails but sets none of the error flags. // If fseek failed, assume that the file position becomes indeterminate in any // case. // It is allowed to set the position beyond the end of the file. EOF error // should not occur. + ProgramStateRef StateFailed = E.bindReturnValue(State, C, -1); StateFailed = E.setStreamState( StateFailed, StreamState::getOpened(Desc, ErrorNone | ErrorFError, true)); C.addTransition(StateFailed, E.getFailureNoteTag(this, C)); @@ -1316,6 +1331,10 @@ void StreamChecker::evalFsetpos(const FnDescription *Desc, StateNotFailed = E.setStreamState( StateNotFailed, StreamState::getOpened(Desc, ErrorNone, false)); + C.addTransition(StateNotFailed); + + if (!PedanticMode) + return; // At failure ferror could be set. // The standards do not tell what happens with the file position at failure. @@ -1324,7 +1343,6 @@ void StreamChecker::evalFsetpos(const FnDescription *Desc, StateFailed = E.setStreamState( StateFailed, StreamState::getOpened(Desc, ErrorNone | ErrorFError, true)); - C.addTransition(StateNotFailed); C.addTransition(StateFailed, E.getFailureNoteTag(this, C)); } @@ -1794,7 +1812,9 @@ ProgramStateRef StreamChecker::checkPointerEscape( //===----------------------------------------------------------------------===// void ento::registerStreamChecker(CheckerManager &Mgr) { - Mgr.registerChecker(); + auto *Checker = Mgr.registerChecker(); + Checker->PedanticMode = + Mgr.getAnalyzerOptions().getCheckerBooleanOption(Checker, "Pedantic"); } bool ento::shouldRegisterStreamChecker(const CheckerManager &Mgr) { diff --git a/clang/test/Analysis/analyzer-config.c b/clang/test/Analysis/analyzer-config.c index 2167a2b32f59..23e37a856d09 100644 --- a/clang/test/Analysis/analyzer-config.c +++ b/clang/test/Analysis/analyzer-config.c @@ -12,6 +12,7 @@ // CHECK-NEXT: alpha.security.MmapWriteExec:MmapProtExec = 0x04 // CHECK-NEXT: alpha.security.MmapWriteExec:MmapProtRead = 0x01 // CHECK-NEXT: alpha.security.taint.TaintPropagation:Config = "" +// CHECK-NEXT: alpha.unix.Stream:Pedantic = false // CHECK-NEXT: apply-fixits = false // CHECK-NEXT: assume-controlled-environment = false // CHECK-NEXT: avoid-suppressing-null-argument-paths = false diff --git a/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c b/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c index 281fbaaffe70..cac3fe5c5151 100644 --- a/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c +++ b/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c @@ -1,6 +1,7 @@ // Check the case when only the StreamChecker is enabled. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core,alpha.unix.Stream \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple x86_64-unknown-linux \ @@ -19,6 +20,7 @@ // StdLibraryFunctionsChecker are enabled. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core,alpha.unix.Stream \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-checker=unix.StdCLibraryFunctions \ // RUN: -analyzer-config unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ diff --git a/clang/test/Analysis/stream-errno-note.c b/clang/test/Analysis/stream-errno-note.c index 2411a2d9a00a..fb12f0bace93 100644 --- a/clang/test/Analysis/stream-errno-note.c +++ b/clang/test/Analysis/stream-errno-note.c @@ -1,5 +1,6 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core \ // RUN: -analyzer-checker=alpha.unix.Stream \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-checker=unix.Errno \ // RUN: -analyzer-checker=unix.StdCLibraryFunctions \ // RUN: -analyzer-config unix.StdCLibraryFunctions:ModelPOSIX=true \ diff --git a/clang/test/Analysis/stream-errno.c b/clang/test/Analysis/stream-errno.c index 5f0a58032fa2..08382eaf6abf 100644 --- a/clang/test/Analysis/stream-errno.c +++ b/clang/test/Analysis/stream-errno.c @@ -1,4 +1,5 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,unix.Errno,unix.StdCLibraryFunctions,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-config unix.StdCLibraryFunctions:ModelPOSIX=true -verify %s #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/stream-error.c b/clang/test/Analysis/stream-error.c index 7f9116ff4014..2abf4b900a04 100644 --- a/clang/test/Analysis/stream-error.c +++ b/clang/test/Analysis/stream-error.c @@ -1,6 +1,7 @@ // RUN: %clang_analyze_cc1 -verify %s \ // RUN: -analyzer-checker=core \ // RUN: -analyzer-checker=alpha.unix.Stream \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-checker=debug.StreamTester \ // RUN: -analyzer-checker=debug.ExprInspection diff --git a/clang/test/Analysis/stream-note.c b/clang/test/Analysis/stream-note.c index 54ea699f4667..03a8ff4e468f 100644 --- a/clang/test/Analysis/stream-note.c +++ b/clang/test/Analysis/stream-note.c @@ -1,6 +1,8 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream -analyzer-output text \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -verify %s // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,unix.StdCLibraryFunctions -analyzer-output text \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-config unix.StdCLibraryFunctions:ModelPOSIX=true -verify=expected,stdargs %s #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/stream-pedantic.c b/clang/test/Analysis/stream-pedantic.c new file mode 100644 index 000000000000..2bbea81d47ef --- /dev/null +++ b/clang/test/Analysis/stream-pedantic.c @@ -0,0 +1,95 @@ +// RUN: %clang_analyze_cc1 -triple=x86_64-pc-linux-gnu -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=false -verify=nopedantic %s + +// RUN: %clang_analyze_cc1 -triple=x86_64-pc-linux-gnu -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true -verify=pedantic %s + +#include "Inputs/system-header-simulator.h" + +void clang_analyzer_eval(int); + +void check_fwrite(void) { + char *Buf = "123456789"; + FILE *Fp = tmpfile(); + if (!Fp) + return; + size_t Ret = fwrite(Buf, 1, 10, Fp); + clang_analyzer_eval(Ret == 0); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} + +void check_fputc(void) { + FILE *Fp = tmpfile(); + if (!Fp) + return; + int Ret = fputc('A', Fp); + clang_analyzer_eval(Ret == EOF); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} + +void check_fputs(void) { + FILE *Fp = tmpfile(); + if (!Fp) + return; + int Ret = fputs("ABC", Fp); + clang_analyzer_eval(Ret == EOF); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} + +void check_fprintf(void) { + FILE *Fp = tmpfile(); + if (!Fp) + return; + int Ret = fprintf(Fp, "ABC"); + clang_analyzer_eval(Ret < 0); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} + +void check_fseek(void) { + FILE *Fp = tmpfile(); + if (!Fp) + return; + int Ret = fseek(Fp, 0, 0); + clang_analyzer_eval(Ret == -1); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} + +void check_fseeko(void) { + FILE *Fp = tmpfile(); + if (!Fp) + return; + int Ret = fseeko(Fp, 0, 0); + clang_analyzer_eval(Ret == -1); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} + +void check_fsetpos(void) { + FILE *Fp = tmpfile(); + if (!Fp) + return; + fpos_t Pos; + int Ret = fsetpos(Fp, &Pos); + clang_analyzer_eval(Ret); // nopedantic-warning {{FALSE}} \ + // pedantic-warning {{FALSE}} \ + // pedantic-warning {{TRUE}} + fputc('A', Fp); // pedantic-warning {{might be 'indeterminate'}} + fclose(Fp); +} diff --git a/clang/test/Analysis/stream-stdlibraryfunctionargs.c b/clang/test/Analysis/stream-stdlibraryfunctionargs.c index 0053510163ef..2ea6a8c472c6 100644 --- a/clang/test/Analysis/stream-stdlibraryfunctionargs.c +++ b/clang/test/Analysis/stream-stdlibraryfunctionargs.c @@ -1,10 +1,13 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,unix.StdCLibraryFunctions,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-config unix.StdCLibraryFunctions:ModelPOSIX=true -verify=stream,any %s // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-config unix.StdCLibraryFunctions:ModelPOSIX=true -verify=stream,any %s // RUN: %clang_analyze_cc1 -analyzer-checker=core,unix.StdCLibraryFunctions,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true \ // RUN: -analyzer-config unix.StdCLibraryFunctions:ModelPOSIX=true -verify=stdfunc,any %s #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/stream.c b/clang/test/Analysis/stream.c index ba5e66a4102e..93ed555c89eb 100644 --- a/clang/test/Analysis/stream.c +++ b/clang/test/Analysis/stream.c @@ -1,7 +1,11 @@ -// RUN: %clang_analyze_cc1 -triple=x86_64-pc-linux-gnu -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection -verify %s -// RUN: %clang_analyze_cc1 -triple=armv8-none-linux-eabi -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection -verify %s -// RUN: %clang_analyze_cc1 -triple=aarch64-linux-gnu -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection -verify %s -// RUN: %clang_analyze_cc1 -triple=hexagon -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection -verify %s +// RUN: %clang_analyze_cc1 -triple=x86_64-pc-linux-gnu -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true -verify %s +// RUN: %clang_analyze_cc1 -triple=armv8-none-linux-eabi -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true -verify %s +// RUN: %clang_analyze_cc1 -triple=aarch64-linux-gnu -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true -verify %s +// RUN: %clang_analyze_cc1 -triple=hexagon -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.Stream:Pedantic=true -verify %s #include "Inputs/system-header-simulator.h" #include "Inputs/system-header-simulator-for-malloc.h" -- GitLab From 2abd71ec51079d84a29639389dc9a66edd4909e5 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Mon, 8 Apr 2024 18:22:06 +0800 Subject: [PATCH 132/695] [mlir] Fix -Wunused-variable in DebugImporter.cpp (NFC) llvm-project/mlir/lib/Target/LLVMIR/DebugImporter.cpp:377:10: error: unused variable '[_, inserted]' [-Werror,-Wunused-variable] auto [_, inserted] = dependentCache.try_emplace( ^ 1 error generated. --- mlir/lib/Target/LLVMIR/DebugImporter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index 3dc2d4e3a750..aa8c307ba2ce 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -374,7 +374,7 @@ DebugImporter::RecursionPruner::finalizeTranslation(llvm::DINode *node, // Insert the result into our internal cache if it's not self-contained. if (!state.unboundSelfRefs.empty()) { - auto [_, inserted] = dependentCache.try_emplace( + [[maybe_unused]] auto [_, inserted] = dependentCache.try_emplace( node, DependentTranslation{result, state.unboundSelfRefs}); assert(inserted && "invalid state: caching the same DINode twice"); return {result, false}; -- GitLab From 8b3b4a92adee40483c27f26c478a384cd69c6f05 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 8 Apr 2024 19:20:36 +0800 Subject: [PATCH 133/695] [RISCV] Fix canFoldToVWWithSameExtension allowing different FP extensions (#87978) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 279d8a435a04..b426f1a7b379 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -14090,7 +14090,7 @@ canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS, return CombineResult(NodeExtensionHelper::getSExtOpcode(Root->getOpcode()), Root, LHS, /*LHSExt=*/{ExtKind::SExt}, RHS, /*RHSExt=*/{ExtKind::SExt}); - if ((AllowExtMask & ExtKind::FPExt) && RHS.SupportsFPExt) + if ((AllowExtMask & ExtKind::FPExt) && LHS.SupportsFPExt && RHS.SupportsFPExt) return CombineResult(NodeExtensionHelper::getFPExtOpcode(Root->getOpcode()), Root, LHS, /*LHSExt=*/{ExtKind::FPExt}, RHS, /*RHSExt=*/{ExtKind::FPExt}); -- GitLab From 5a855d51272608e2122c45d86676aa2247a11d19 Mon Sep 17 00:00:00 2001 From: Hirofumi Nakamura Date: Mon, 8 Apr 2024 21:12:12 +0900 Subject: [PATCH 134/695] [clang-format] Added unittest of TableGen formatting w.r.t. block type calculation. (#87924) --- clang/unittests/Format/FormatTestTableGen.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/clang/unittests/Format/FormatTestTableGen.cpp b/clang/unittests/Format/FormatTestTableGen.cpp index 8ca6bf97e5a6..d235c85c8eaa 100644 --- a/clang/unittests/Format/FormatTestTableGen.cpp +++ b/clang/unittests/Format/FormatTestTableGen.cpp @@ -290,6 +290,16 @@ TEST_F(FormatTestTableGen, MultiClass) { "}\n"); } +TEST_F(FormatTestTableGen, MultiClassesWithPasteOperator) { + // This is a sensitive example for the handling of the paste operators in + // brace type calculation. + verifyFormat("multiclass MultiClass1 {\n" + " def : Def#x;\n" + " def : Def#y;\n" + "}\n" + "multiclass MultiClass2 { def : Def#x; }\n"); +} + TEST_F(FormatTestTableGen, Defm) { verifyFormat("defm : Multiclass<0>;\n"); -- GitLab From 86b0918e8e5f8e1aacebf4ba8901fc66aed3412f Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 8 Apr 2024 07:14:52 -0500 Subject: [PATCH 135/695] [LinkerWrapper] Do not include config files for device linking (#87659) Summary: The device linking phase only wants to create the necessary commands to emit the device binary. There were issues where the user's default config file was being used and passing incompatible arguments to the device compilation step. Simply disable this since we do not want any additional arguments to these clang invocations. --- clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index c60be2789bd6..73e695a67093 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -458,6 +458,7 @@ Expected clang(ArrayRef InputFiles, const ArgList &Args) { StringRef OptLevel = Args.getLastArgValue(OPT_opt_level, "O2"); SmallVector CmdArgs{ *ClangPath, + "--no-default-config", "-o", *TempFileOrErr, Args.MakeArgString("--target=" + Triple.getTriple()), -- GitLab From acb2a475766b621fe7e5d792ff7948a5794c3e87 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 14:55:03 -0400 Subject: [PATCH 136/695] AMDGPU: Regenerate test checks --- .../AMDGPU/amdgpu-codegenprepare-fdiv.ll | 194 +++++++++--------- 1 file changed, 97 insertions(+), 97 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll index d9e046494218..6bda962d1b9c 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll @@ -12,7 +12,7 @@ define amdgpu_kernel void @noop_fdiv_fpmath(ptr addrspace(1) %out, float %a, float %b) #0 { ; CHECK-LABEL: define amdgpu_kernel void @noop_fdiv_fpmath( ; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[MD_25ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !0 +; CHECK-NEXT: [[MD_25ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META0:![0-9]+]] ; CHECK-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; CHECK-NEXT: ret void ; @@ -26,7 +26,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32(ptr addrspace(1) %out, float %a, floa ; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]]) #[[ATTR1:[0-9]+]] { ; IEEE-GOODFREXP-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1:![0-9]+]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -61,9 +61,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32(ptr addrspace(1) %out, float %a, floa ; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = sub i32 [[TMP25]], [[TMP21]] ; IEEE-GOODFREXP-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP26]], i32 [[TMP27]]) ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -89,7 +89,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32(ptr addrspace(1) %out, float %a, floa ; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]]) #[[ATTR1:[0-9]+]] { ; IEEE-BADFREXP-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1:![0-9]+]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -124,9 +124,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32(ptr addrspace(1) %out, float %a, floa ; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = sub i32 [[TMP25]], [[TMP21]] ; IEEE-BADFREXP-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP26]], i32 [[TMP27]]) ; IEEE-BADFREXP-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -152,7 +152,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32(ptr addrspace(1) %out, float %a, floa ; DAZ-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float [[B:%.*]]) #[[ATTR1:[0-9]+]] { ; DAZ-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1:![0-9]+]] ; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; DAZ-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -169,9 +169,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32(ptr addrspace(1) %out, float %a, floa ; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]]) ; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; DAZ-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -430,15 +430,15 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath(ptr addrspace(1) %out, float %x) ; IEEE-GOODFREXP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; IEEE-GOODFREXP-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP10]], i32 [[TMP9]]) ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float 1.000000e+00, [[X]], !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float 1.000000e+00, [[X]], !fpmath [[META1]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[AFN_NO_MD:%.*]] = fdiv afn float 1.000000e+00, [[X]] ; IEEE-GOODFREXP-NEXT: store volatile float [[AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[AFN_25ULP:%.*]] = fdiv afn float 1.000000e+00, [[X]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[AFN_25ULP:%.*]] = fdiv afn float 1.000000e+00, [[X]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[AFN_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[FAST_NO_MD:%.*]] = fdiv fast float 1.000000e+00, [[X]] ; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[FAST_25ULP:%.*]] = fdiv fast float 1.000000e+00, [[X]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[FAST_25ULP:%.*]] = fdiv fast float 1.000000e+00, [[X]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[TMP11:%.*]] = fneg float [[X]] ; IEEE-GOODFREXP-NEXT: [[TMP12:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP11]]) @@ -458,7 +458,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath(ptr addrspace(1) %out, float %x) ; IEEE-GOODFREXP-NEXT: store volatile float [[NEG_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[NEG_AFN_NO_MD:%.*]] = fdiv afn float -1.000000e+00, [[X]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NEG_AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[NEG_AFN_25ULP:%.*]] = fdiv afn float -1.000000e+00, [[X]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[NEG_AFN_25ULP:%.*]] = fdiv afn float -1.000000e+00, [[X]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NEG_AFN_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[NEG_FAST_NO_MD:%.*]] = fdiv fast float -1.000000e+00, [[X]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NEG_FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4 @@ -482,15 +482,15 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath(ptr addrspace(1) %out, float %x) ; IEEE-BADFREXP-NEXT: [[TMP10:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; IEEE-BADFREXP-NEXT: [[MD_25ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP10]], i32 [[TMP9]]) ; IEEE-BADFREXP-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float 1.000000e+00, [[X]], !fpmath !1 +; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float 1.000000e+00, [[X]], !fpmath [[META1]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[AFN_NO_MD:%.*]] = fdiv afn float 1.000000e+00, [[X]] ; IEEE-BADFREXP-NEXT: store volatile float [[AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[AFN_25ULP:%.*]] = fdiv afn float 1.000000e+00, [[X]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[AFN_25ULP:%.*]] = fdiv afn float 1.000000e+00, [[X]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[AFN_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[FAST_NO_MD:%.*]] = fdiv fast float 1.000000e+00, [[X]] ; IEEE-BADFREXP-NEXT: store volatile float [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[FAST_25ULP:%.*]] = fdiv fast float 1.000000e+00, [[X]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[FAST_25ULP:%.*]] = fdiv fast float 1.000000e+00, [[X]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[TMP11:%.*]] = fneg float [[X]] ; IEEE-BADFREXP-NEXT: [[TMP12:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP11]]) @@ -510,7 +510,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath(ptr addrspace(1) %out, float %x) ; IEEE-BADFREXP-NEXT: store volatile float [[NEG_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[NEG_AFN_NO_MD:%.*]] = fdiv afn float -1.000000e+00, [[X]] ; IEEE-BADFREXP-NEXT: store volatile float [[NEG_AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[NEG_AFN_25ULP:%.*]] = fdiv afn float -1.000000e+00, [[X]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[NEG_AFN_25ULP:%.*]] = fdiv afn float -1.000000e+00, [[X]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[NEG_AFN_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[NEG_FAST_NO_MD:%.*]] = fdiv fast float -1.000000e+00, [[X]] ; IEEE-BADFREXP-NEXT: store volatile float [[NEG_FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4 @@ -524,15 +524,15 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath(ptr addrspace(1) %out, float %x) ; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[X]]) ; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float 1.000000e+00, [[X]], !fpmath !1 +; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float 1.000000e+00, [[X]], !fpmath [[META1]] ; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[AFN_NO_MD:%.*]] = fdiv afn float 1.000000e+00, [[X]] ; DAZ-NEXT: store volatile float [[AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[AFN_25ULP:%.*]] = fdiv afn float 1.000000e+00, [[X]], !fpmath !0 +; DAZ-NEXT: [[AFN_25ULP:%.*]] = fdiv afn float 1.000000e+00, [[X]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[AFN_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[FAST_NO_MD:%.*]] = fdiv fast float 1.000000e+00, [[X]] ; DAZ-NEXT: store volatile float [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[FAST_25ULP:%.*]] = fdiv fast float 1.000000e+00, [[X]], !fpmath !0 +; DAZ-NEXT: [[FAST_25ULP:%.*]] = fdiv fast float 1.000000e+00, [[X]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[TMP1:%.*]] = fneg float [[X]] ; DAZ-NEXT: [[NEG_MD_1ULP:%.*]] = call float @llvm.amdgcn.rcp.f32(float [[TMP1]]) @@ -542,7 +542,7 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath(ptr addrspace(1) %out, float %x) ; DAZ-NEXT: store volatile float [[NEG_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[NEG_AFN_NO_MD:%.*]] = fdiv afn float -1.000000e+00, [[X]] ; DAZ-NEXT: store volatile float [[NEG_AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[NEG_AFN_25ULP:%.*]] = fdiv afn float -1.000000e+00, [[X]], !fpmath !0 +; DAZ-NEXT: [[NEG_AFN_25ULP:%.*]] = fdiv afn float -1.000000e+00, [[X]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[NEG_AFN_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[NEG_FAST_NO_MD:%.*]] = fdiv fast float -1.000000e+00, [[X]] ; DAZ-NEXT: store volatile float [[NEG_FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 4 @@ -1179,7 +1179,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_vector(ptr addrspace(1) %out, <2 x fl ; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR1]] { ; IEEE-GOODFREXP-NEXT: [[NO_MD:%.*]] = fdiv <2 x float> [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 8 -; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> [[A]], [[B]], !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> [[A]], [[B]], !fpmath [[META1]] ; IEEE-GOODFREXP-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 8 ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[A]], i64 0 ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[A]], i64 1 @@ -1241,7 +1241,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_vector(ptr addrspace(1) %out, <2 x fl ; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR1]] { ; IEEE-BADFREXP-NEXT: [[NO_MD:%.*]] = fdiv <2 x float> [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 8 -; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> [[A]], [[B]], !fpmath !1 +; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> [[A]], [[B]], !fpmath [[META1]] ; IEEE-BADFREXP-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 8 ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[A]], i64 0 ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[A]], i64 1 @@ -1303,7 +1303,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_vector(ptr addrspace(1) %out, <2 x fl ; DAZ-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR1]] { ; DAZ-NEXT: [[NO_MD:%.*]] = fdiv <2 x float> [[A]], [[B]] ; DAZ-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 8 -; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> [[A]], [[B]], !fpmath !1 +; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> [[A]], [[B]], !fpmath [[META1]] ; DAZ-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 8 ; DAZ-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[A]], i64 0 ; DAZ-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[A]], i64 1 @@ -1359,15 +1359,15 @@ define amdgpu_kernel void @rcp_fdiv_f32_vector_fpmath(ptr addrspace(1) %out, <2 ; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]]) #[[ATTR1:[0-9]+]] { ; CHECK-NEXT: [[NO_MD:%.*]] = fdiv <2 x float> , [[X]] ; CHECK-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 8 -; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> , [[X]], !fpmath !1 +; CHECK-NEXT: [[MD_HALF_ULP:%.*]] = fdiv <2 x float> , [[X]], !fpmath [[META1:![0-9]+]] ; CHECK-NEXT: store volatile <2 x float> [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 8 ; CHECK-NEXT: [[AFN_NO_MD:%.*]] = fdiv afn <2 x float> , [[X]] ; CHECK-NEXT: store volatile <2 x float> [[AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 8 ; CHECK-NEXT: [[FAST_NO_MD:%.*]] = fdiv fast <2 x float> , [[X]] ; CHECK-NEXT: store volatile <2 x float> [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 8 -; CHECK-NEXT: [[AFN_25ULP:%.*]] = fdiv afn <2 x float> , [[X]], !fpmath !0 +; CHECK-NEXT: [[AFN_25ULP:%.*]] = fdiv afn <2 x float> , [[X]], !fpmath [[META0]] ; CHECK-NEXT: store volatile <2 x float> [[AFN_25ULP]], ptr addrspace(1) [[OUT]], align 8 -; CHECK-NEXT: [[FAST_25ULP:%.*]] = fdiv fast <2 x float> , [[X]], !fpmath !0 +; CHECK-NEXT: [[FAST_25ULP:%.*]] = fdiv fast <2 x float> , [[X]], !fpmath [[META0]] ; CHECK-NEXT: store volatile <2 x float> [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 8 ; CHECK-NEXT: ret void ; @@ -1395,9 +1395,9 @@ define amdgpu_kernel void @rcp_fdiv_f32_fpmath_vector_nonsplat(ptr addrspace(1) ; CHECK-NEXT: store volatile <2 x float> [[AFN_NO_MD]], ptr addrspace(1) [[OUT]], align 8 ; CHECK-NEXT: [[FAST_NO_MD:%.*]] = fdiv fast <2 x float> , [[X]] ; CHECK-NEXT: store volatile <2 x float> [[FAST_NO_MD]], ptr addrspace(1) [[OUT]], align 8 -; CHECK-NEXT: [[AFN_25ULP:%.*]] = fdiv afn <2 x float> , [[X]], !fpmath !0 +; CHECK-NEXT: [[AFN_25ULP:%.*]] = fdiv afn <2 x float> , [[X]], !fpmath [[META0]] ; CHECK-NEXT: store volatile <2 x float> [[AFN_25ULP]], ptr addrspace(1) [[OUT]], align 8 -; CHECK-NEXT: [[FAST_25ULP:%.*]] = fdiv fast <2 x float> , [[X]], !fpmath !0 +; CHECK-NEXT: [[FAST_25ULP:%.*]] = fdiv fast <2 x float> , [[X]], !fpmath [[META0]] ; CHECK-NEXT: store volatile <2 x float> [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 8 ; CHECK-NEXT: ret void ; @@ -1418,9 +1418,9 @@ define amdgpu_kernel void @rcp_fdiv_f32_vector_fpmath_partial_constant(ptr addrs ; CHECK-LABEL: define amdgpu_kernel void @rcp_fdiv_f32_vector_fpmath_partial_constant( ; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR1]] { ; CHECK-NEXT: [[X_INSERT:%.*]] = insertelement <2 x float> [[X]], float 1.000000e+00, i32 0 -; CHECK-NEXT: [[AFN_25ULP:%.*]] = fdiv afn <2 x float> [[X_INSERT]], [[Y]], !fpmath !0 +; CHECK-NEXT: [[AFN_25ULP:%.*]] = fdiv afn <2 x float> [[X_INSERT]], [[Y]], !fpmath [[META0]] ; CHECK-NEXT: store volatile <2 x float> [[AFN_25ULP]], ptr addrspace(1) [[OUT]], align 8 -; CHECK-NEXT: [[FAST_25ULP:%.*]] = fdiv fast <2 x float> [[X_INSERT]], [[Y]], !fpmath !0 +; CHECK-NEXT: [[FAST_25ULP:%.*]] = fdiv fast <2 x float> [[X_INSERT]], [[Y]], !fpmath [[META0]] ; CHECK-NEXT: store volatile <2 x float> [[FAST_25ULP]], ptr addrspace(1) [[OUT]], align 8 ; CHECK-NEXT: ret void ; @@ -1520,7 +1520,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; IEEE-GOODFREXP-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00 ; IEEE-GOODFREXP-NEXT: [[MD_1ULP:%.*]] = fmul contract float [[TMP4]], [[TMP5]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[SQRT_MD_1ULP_MULTI_USE:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[SQRT_MD_1ULP_MULTI_USE:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2:![0-9]+]] ; IEEE-GOODFREXP-NEXT: store volatile float [[SQRT_MD_1ULP_MULTI_USE]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[TMP6:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_MD_1ULP_MULTI_USE]]) ; IEEE-GOODFREXP-NEXT: [[TMP7:%.*]] = extractvalue { float, i32 } [[TMP6]], 0 @@ -1536,8 +1536,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; IEEE-GOODFREXP-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00 ; IEEE-GOODFREXP-NEXT: [[MD_25ULP:%.*]] = fmul contract float [[TMP14]], [[TMP15]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[SQRT_MD_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !1 -; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_MD_HALF_ULP]], !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[SQRT_MD_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]] +; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_MD_HALF_ULP]], !fpmath [[META1]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[SQRT_X_AFN_NO_MD:%.*]] = call contract afn float @llvm.sqrt.f32(float [[X]]) ; IEEE-GOODFREXP-NEXT: [[AFN_NO_MD:%.*]] = fdiv contract afn float 1.000000e+00, [[SQRT_X_AFN_NO_MD]] @@ -1563,7 +1563,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; IEEE-GOODFREXP-NEXT: [[TMP25:%.*]] = select contract i1 [[TMP21]], float -4.096000e+03, float -1.000000e+00 ; IEEE-GOODFREXP-NEXT: [[NEG_FDIV_OPENCL:%.*]] = fmul contract float [[TMP24]], [[TMP25]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NEG_FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[SQRT_X_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[SQRT_X_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]] ; IEEE-GOODFREXP-NEXT: [[TMP26:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_X_HALF_ULP]]) ; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = extractvalue { float, i32 } [[TMP26]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP28:%.*]] = extractvalue { float, i32 } [[TMP26]], 1 @@ -1601,7 +1601,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; IEEE-BADFREXP-NEXT: [[TMP5:%.*]] = select contract i1 [[TMP1]], float 4.096000e+03, float 1.000000e+00 ; IEEE-BADFREXP-NEXT: [[MD_1ULP:%.*]] = fmul contract float [[TMP4]], [[TMP5]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[SQRT_MD_1ULP_MULTI_USE:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[SQRT_MD_1ULP_MULTI_USE:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2:![0-9]+]] ; IEEE-BADFREXP-NEXT: store volatile float [[SQRT_MD_1ULP_MULTI_USE]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[TMP6:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_MD_1ULP_MULTI_USE]]) ; IEEE-BADFREXP-NEXT: [[TMP7:%.*]] = extractvalue { float, i32 } [[TMP6]], 0 @@ -1617,8 +1617,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; IEEE-BADFREXP-NEXT: [[TMP15:%.*]] = select contract i1 [[TMP11]], float 4.096000e+03, float 1.000000e+00 ; IEEE-BADFREXP-NEXT: [[MD_25ULP:%.*]] = fmul contract float [[TMP14]], [[TMP15]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[SQRT_MD_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !1 -; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_MD_HALF_ULP]], !fpmath !1 +; IEEE-BADFREXP-NEXT: [[SQRT_MD_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]] +; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_MD_HALF_ULP]], !fpmath [[META1]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[SQRT_X_AFN_NO_MD:%.*]] = call contract afn float @llvm.sqrt.f32(float [[X]]) ; IEEE-BADFREXP-NEXT: [[AFN_NO_MD:%.*]] = fdiv contract afn float 1.000000e+00, [[SQRT_X_AFN_NO_MD]] @@ -1644,7 +1644,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; IEEE-BADFREXP-NEXT: [[TMP25:%.*]] = select contract i1 [[TMP21]], float -4.096000e+03, float -1.000000e+00 ; IEEE-BADFREXP-NEXT: [[NEG_FDIV_OPENCL:%.*]] = fmul contract float [[TMP24]], [[TMP25]] ; IEEE-BADFREXP-NEXT: store volatile float [[NEG_FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[SQRT_X_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !1 +; IEEE-BADFREXP-NEXT: [[SQRT_X_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]] ; IEEE-BADFREXP-NEXT: [[TMP26:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_X_HALF_ULP]]) ; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = extractvalue { float, i32 } [[TMP26]], 0 ; IEEE-BADFREXP-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float [[SQRT_X_HALF_ULP]]) @@ -1683,8 +1683,8 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; DAZ-NEXT: store volatile float [[MD_1ULP_MULTI_USE]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[MD_25ULP:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[X]]) ; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[SQRT_MD_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !1 -; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_MD_HALF_ULP]], !fpmath !1 +; DAZ-NEXT: [[SQRT_MD_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]] +; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv contract float 1.000000e+00, [[SQRT_MD_HALF_ULP]], !fpmath [[META1]] ; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[SQRT_X_AFN_NO_MD:%.*]] = call contract afn float @llvm.sqrt.f32(float [[X]]) ; DAZ-NEXT: [[AFN_NO_MD:%.*]] = fdiv contract afn float 1.000000e+00, [[SQRT_X_AFN_NO_MD]] @@ -1701,7 +1701,7 @@ define amdgpu_kernel void @rsq_f32_fpmath(ptr addrspace(1) %out, float %x) { ; DAZ-NEXT: [[TMP1:%.*]] = call contract float @llvm.amdgcn.rsq.f32(float [[X]]) ; DAZ-NEXT: [[NEG_FDIV_OPENCL:%.*]] = fneg contract float [[TMP1]] ; DAZ-NEXT: store volatile float [[NEG_FDIV_OPENCL]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[SQRT_X_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !1 +; DAZ-NEXT: [[SQRT_X_HALF_ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META1]] ; DAZ-NEXT: [[FDIV_SQRT_MISMATCH_MD0:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[SQRT_X_HALF_ULP]]) ; DAZ-NEXT: store volatile float [[FDIV_SQRT_MISMATCH_MD0]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[SQRT_MISMATCH_MD1:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]) @@ -1873,7 +1873,7 @@ define amdgpu_kernel void @rsq_f32_fpmath_flags(ptr addrspace(1) %out, float %x) define float @rsq_f32_missing_contract0(float %x) { ; IEEE-GOODFREXP-LABEL: define float @rsq_f32_missing_contract0( ; IEEE-GOODFREXP-SAME: float [[X:%.*]]) #[[ATTR1]] { -; IEEE-GOODFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2]] ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_X_3ULP]]) ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = extractvalue { float, i32 } [[TMP1]], 1 @@ -1884,7 +1884,7 @@ define float @rsq_f32_missing_contract0(float %x) { ; ; IEEE-BADFREXP-LABEL: define float @rsq_f32_missing_contract0( ; IEEE-BADFREXP-SAME: float [[X:%.*]]) #[[ATTR1]] { -; IEEE-BADFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2]] ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_X_3ULP]]) ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 ; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float [[SQRT_X_3ULP]]) @@ -1907,7 +1907,7 @@ define float @rsq_f32_missing_contract0(float %x) { define float @rsq_f32_missing_contract1(float %x) { ; IEEE-GOODFREXP-LABEL: define float @rsq_f32_missing_contract1( ; IEEE-GOODFREXP-SAME: float [[X:%.*]]) #[[ATTR1]] { -; IEEE-GOODFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2]] ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_X_3ULP]]) ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = extractvalue { float, i32 } [[TMP1]], 1 @@ -1918,7 +1918,7 @@ define float @rsq_f32_missing_contract1(float %x) { ; ; IEEE-BADFREXP-LABEL: define float @rsq_f32_missing_contract1( ; IEEE-BADFREXP-SAME: float [[X:%.*]]) #[[ATTR1]] { -; IEEE-BADFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract float @llvm.sqrt.f32(float [[X]]), !fpmath [[META2]] ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[SQRT_X_3ULP]]) ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 ; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float [[SQRT_X_3ULP]]) @@ -2116,7 +2116,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; IEEE-GOODFREXP-NEXT: [[SQRT_X_NO_MD:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]) ; IEEE-GOODFREXP-NEXT: [[NO_MD:%.*]] = fdiv contract <2 x float> , [[SQRT_X_NO_MD]] ; IEEE-GOODFREXP-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[SQRT_MD_1ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[SQRT_MD_1ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META2]] ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 0 ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 1 ; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2136,7 +2136,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = insertelement <2 x float> poison, float [[TMP10]], i64 0 ; IEEE-GOODFREXP-NEXT: [[MD_1ULP:%.*]] = insertelement <2 x float> [[TMP17]], float [[TMP16]], i64 1 ; IEEE-GOODFREXP-NEXT: store volatile <2 x float> [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[SQRT_MD_1ULP_UNDEF:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[SQRT_MD_1ULP_UNDEF:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META2]] ; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP_UNDEF]], i64 0 ; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP_UNDEF]], i64 1 ; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2160,7 +2160,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; IEEE-GOODFREXP-NEXT: [[TMP38:%.*]] = insertelement <2 x float> poison, float [[TMP27]], i64 0 ; IEEE-GOODFREXP-NEXT: [[MD_1ULP_UNDEF:%.*]] = insertelement <2 x float> [[TMP38]], float [[TMP37]], i64 1 ; IEEE-GOODFREXP-NEXT: store volatile <2 x float> [[MD_1ULP_UNDEF]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !3 +; IEEE-GOODFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META3:![0-9]+]] ; IEEE-GOODFREXP-NEXT: [[TMP39:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 0 ; IEEE-GOODFREXP-NEXT: [[TMP40:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 1 ; IEEE-GOODFREXP-NEXT: [[TMP41:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2187,7 +2187,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; IEEE-BADFREXP-NEXT: [[SQRT_X_NO_MD:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]) ; IEEE-BADFREXP-NEXT: [[NO_MD:%.*]] = fdiv contract <2 x float> , [[SQRT_X_NO_MD]] ; IEEE-BADFREXP-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[SQRT_MD_1ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[SQRT_MD_1ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META2]] ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 0 ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 1 ; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2207,7 +2207,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = insertelement <2 x float> poison, float [[TMP10]], i64 0 ; IEEE-BADFREXP-NEXT: [[MD_1ULP:%.*]] = insertelement <2 x float> [[TMP17]], float [[TMP16]], i64 1 ; IEEE-BADFREXP-NEXT: store volatile <2 x float> [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[SQRT_MD_1ULP_UNDEF:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[SQRT_MD_1ULP_UNDEF:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META2]] ; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP_UNDEF]], i64 0 ; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP_UNDEF]], i64 1 ; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2231,7 +2231,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; IEEE-BADFREXP-NEXT: [[TMP38:%.*]] = insertelement <2 x float> poison, float [[TMP27]], i64 0 ; IEEE-BADFREXP-NEXT: [[MD_1ULP_UNDEF:%.*]] = insertelement <2 x float> [[TMP38]], float [[TMP37]], i64 1 ; IEEE-BADFREXP-NEXT: store volatile <2 x float> [[MD_1ULP_UNDEF]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !3 +; IEEE-BADFREXP-NEXT: [[SQRT_X_3ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META3:![0-9]+]] ; IEEE-BADFREXP-NEXT: [[TMP39:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 0 ; IEEE-BADFREXP-NEXT: [[TMP40:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 1 ; IEEE-BADFREXP-NEXT: [[TMP41:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2258,7 +2258,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; DAZ-NEXT: [[SQRT_X_NO_MD:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]) ; DAZ-NEXT: [[NO_MD:%.*]] = fdiv contract <2 x float> , [[SQRT_X_NO_MD]] ; DAZ-NEXT: store volatile <2 x float> [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[SQRT_MD_1ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !2 +; DAZ-NEXT: [[SQRT_MD_1ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META2:![0-9]+]] ; DAZ-NEXT: [[TMP1:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 0 ; DAZ-NEXT: [[TMP2:%.*]] = extractelement <2 x float> [[SQRT_MD_1ULP]], i64 1 ; DAZ-NEXT: [[TMP3:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -2290,7 +2290,7 @@ define amdgpu_kernel void @rsq_f32_vector_fpmath(ptr addrspace(1) %out, <2 x flo ; DAZ-NEXT: [[TMP26:%.*]] = insertelement <2 x float> poison, float [[TMP15]], i64 0 ; DAZ-NEXT: [[MD_1ULP_UNDEF:%.*]] = insertelement <2 x float> [[TMP26]], float [[TMP25]], i64 1 ; DAZ-NEXT: store volatile <2 x float> [[MD_1ULP_UNDEF]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[SQRT_X_3ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath !3 +; DAZ-NEXT: [[SQRT_X_3ULP:%.*]] = call contract <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META3:![0-9]+]] ; DAZ-NEXT: [[TMP27:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 0 ; DAZ-NEXT: [[TMP28:%.*]] = extractelement <2 x float> [[SQRT_X_3ULP]], i64 1 ; DAZ-NEXT: [[TMP29:%.*]] = extractelement <2 x float> [[X]], i64 0 @@ -3086,7 +3086,7 @@ define amdgpu_kernel void @multiple_arcp_fdiv_sqrt_denom_25ulp_x3(ptr addrspace( define <4 x float> @rsq_f32_vector_mixed_constant_numerator(<4 x float> %arg) { ; IEEE-GOODFREXP-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator( ; IEEE-GOODFREXP-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-GOODFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2]] ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[DENOM]], i64 0 ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[DENOM]], i64 1 ; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[DENOM]], i64 2 @@ -3135,7 +3135,7 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator(<4 x float> %arg) { ; ; IEEE-BADFREXP-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator( ; IEEE-BADFREXP-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-BADFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2]] ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[DENOM]], i64 0 ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[DENOM]], i64 1 ; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[DENOM]], i64 2 @@ -3381,7 +3381,7 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_afn_sqrt(<4 x float> define <4 x float> @rsq_f32_vector_mixed_constant_numerator_afn_div(<4 x float> %arg) { ; IEEE-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator_afn_div( ; IEEE-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2:![0-9]+]] ; IEEE-NEXT: [[PARTIAL_RSQ:%.*]] = fdiv contract afn <4 x float> , [[DENOM]] ; IEEE-NEXT: ret <4 x float> [[PARTIAL_RSQ]] ; @@ -3410,7 +3410,7 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_afn_div(<4 x float> define <4 x float> @rsq_f32_vector_mixed_constant_numerator_correct_fdiv(<4 x float> %arg) { ; IEEE-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator_correct_fdiv( ; IEEE-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2]] ; IEEE-NEXT: [[PARTIAL_RSQ:%.*]] = fdiv contract <4 x float> , [[DENOM]] ; IEEE-NEXT: ret <4 x float> [[PARTIAL_RSQ]] ; @@ -3573,7 +3573,7 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_correct_sqrt(<4 x fl define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp(<4 x float> %arg) { ; IEEE-GOODFREXP-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp( ; IEEE-GOODFREXP-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-GOODFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-GOODFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2]] ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[DENOM]], i64 0 ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[DENOM]], i64 1 ; IEEE-GOODFREXP-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[DENOM]], i64 2 @@ -3616,7 +3616,7 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp(<4 x float> %ar ; ; IEEE-BADFREXP-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp( ; IEEE-BADFREXP-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-BADFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-BADFREXP-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2]] ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[DENOM]], i64 0 ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[DENOM]], i64 1 ; IEEE-BADFREXP-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[DENOM]], i64 2 @@ -3696,7 +3696,7 @@ define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp(<4 x float> %ar define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp_correct(<4 x float> %arg) { ; IEEE-LABEL: define <4 x float> @rsq_f32_vector_mixed_constant_numerator_arcp_correct( ; IEEE-SAME: <4 x float> [[ARG:%.*]]) #[[ATTR1]] { -; IEEE-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath !2 +; IEEE-NEXT: [[DENOM:%.*]] = call contract <4 x float> @llvm.sqrt.v4f32(<4 x float> [[ARG]]), !fpmath [[META2]] ; IEEE-NEXT: [[PARTIAL_RSQ:%.*]] = fdiv arcp contract <4 x float> , [[DENOM]] ; IEEE-NEXT: ret <4 x float> [[PARTIAL_RSQ]] ; @@ -3857,21 +3857,21 @@ define <4 x float> @rsq_f32_vector_const_denom(ptr addrspace(1) %out, <2 x float ; IEEE-GOODFREXP-NEXT: [[TMP16:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP13]]) ; IEEE-GOODFREXP-NEXT: [[TMP17:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP16]], i32 [[TMP15]]) ; IEEE-GOODFREXP-NEXT: [[TMP18:%.*]] = fneg contract float [[TMP9]] -; IEEE-GOODFREXP-NEXT: [[TMP19:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP18]]) -; IEEE-GOODFREXP-NEXT: [[TMP20:%.*]] = extractvalue { float, i32 } [[TMP19]], 0 -; IEEE-GOODFREXP-NEXT: [[TMP21:%.*]] = extractvalue { float, i32 } [[TMP19]], 1 -; IEEE-GOODFREXP-NEXT: [[TMP22:%.*]] = sub i32 0, [[TMP21]] -; IEEE-GOODFREXP-NEXT: [[TMP23:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP20]]) -; IEEE-GOODFREXP-NEXT: [[TMP24:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP23]], i32 [[TMP22]]) -; IEEE-GOODFREXP-NEXT: [[TMP25:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP10]]) +; IEEE-GOODFREXP-NEXT: [[TMP25:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP18]]) ; IEEE-GOODFREXP-NEXT: [[TMP26:%.*]] = extractvalue { float, i32 } [[TMP25]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = extractvalue { float, i32 } [[TMP25]], 1 +; IEEE-GOODFREXP-NEXT: [[TMP22:%.*]] = sub i32 0, [[TMP27]] ; IEEE-GOODFREXP-NEXT: [[TMP28:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP26]]) +; IEEE-GOODFREXP-NEXT: [[TMP24:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP28]], i32 [[TMP22]]) +; IEEE-GOODFREXP-NEXT: [[TMP48:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP10]]) +; IEEE-GOODFREXP-NEXT: [[TMP49:%.*]] = extractvalue { float, i32 } [[TMP48]], 0 +; IEEE-GOODFREXP-NEXT: [[TMP50:%.*]] = extractvalue { float, i32 } [[TMP48]], 1 +; IEEE-GOODFREXP-NEXT: [[TMP51:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP49]]) ; IEEE-GOODFREXP-NEXT: [[TMP29:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef) ; IEEE-GOODFREXP-NEXT: [[TMP30:%.*]] = extractvalue { float, i32 } [[TMP29]], 0 ; IEEE-GOODFREXP-NEXT: [[TMP31:%.*]] = extractvalue { float, i32 } [[TMP29]], 1 -; IEEE-GOODFREXP-NEXT: [[TMP32:%.*]] = fmul contract float [[TMP30]], [[TMP28]] -; IEEE-GOODFREXP-NEXT: [[TMP33:%.*]] = sub i32 [[TMP31]], [[TMP27]] +; IEEE-GOODFREXP-NEXT: [[TMP32:%.*]] = fmul contract float [[TMP30]], [[TMP51]] +; IEEE-GOODFREXP-NEXT: [[TMP33:%.*]] = sub i32 [[TMP31]], [[TMP50]] ; IEEE-GOODFREXP-NEXT: [[TMP34:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP32]], i32 [[TMP33]]) ; IEEE-GOODFREXP-NEXT: [[TMP35:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP11]]) ; IEEE-GOODFREXP-NEXT: [[TMP36:%.*]] = extractvalue { float, i32 } [[TMP35]], 0 @@ -3910,20 +3910,20 @@ define <4 x float> @rsq_f32_vector_const_denom(ptr addrspace(1) %out, <2 x float ; IEEE-BADFREXP-NEXT: [[TMP16:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP13]]) ; IEEE-BADFREXP-NEXT: [[TMP17:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP16]], i32 [[TMP15]]) ; IEEE-BADFREXP-NEXT: [[TMP18:%.*]] = fneg contract float [[TMP9]] -; IEEE-BADFREXP-NEXT: [[TMP19:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP18]]) -; IEEE-BADFREXP-NEXT: [[TMP20:%.*]] = extractvalue { float, i32 } [[TMP19]], 0 +; IEEE-BADFREXP-NEXT: [[TMP25:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP18]]) +; IEEE-BADFREXP-NEXT: [[TMP26:%.*]] = extractvalue { float, i32 } [[TMP25]], 0 ; IEEE-BADFREXP-NEXT: [[TMP21:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float [[TMP18]]) ; IEEE-BADFREXP-NEXT: [[TMP22:%.*]] = sub i32 0, [[TMP21]] -; IEEE-BADFREXP-NEXT: [[TMP23:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP20]]) -; IEEE-BADFREXP-NEXT: [[TMP24:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP23]], i32 [[TMP22]]) -; IEEE-BADFREXP-NEXT: [[TMP25:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP10]]) -; IEEE-BADFREXP-NEXT: [[TMP26:%.*]] = extractvalue { float, i32 } [[TMP25]], 0 -; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float [[TMP10]]) ; IEEE-BADFREXP-NEXT: [[TMP28:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP26]]) +; IEEE-BADFREXP-NEXT: [[TMP24:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP28]], i32 [[TMP22]]) +; IEEE-BADFREXP-NEXT: [[TMP48:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP10]]) +; IEEE-BADFREXP-NEXT: [[TMP49:%.*]] = extractvalue { float, i32 } [[TMP48]], 0 +; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float [[TMP10]]) +; IEEE-BADFREXP-NEXT: [[TMP50:%.*]] = call contract float @llvm.amdgcn.rcp.f32(float [[TMP49]]) ; IEEE-BADFREXP-NEXT: [[TMP29:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float undef) ; IEEE-BADFREXP-NEXT: [[TMP30:%.*]] = extractvalue { float, i32 } [[TMP29]], 0 ; IEEE-BADFREXP-NEXT: [[TMP31:%.*]] = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float undef) -; IEEE-BADFREXP-NEXT: [[TMP32:%.*]] = fmul contract float [[TMP30]], [[TMP28]] +; IEEE-BADFREXP-NEXT: [[TMP32:%.*]] = fmul contract float [[TMP30]], [[TMP50]] ; IEEE-BADFREXP-NEXT: [[TMP33:%.*]] = sub i32 [[TMP31]], [[TMP27]] ; IEEE-BADFREXP-NEXT: [[TMP34:%.*]] = call contract float @llvm.ldexp.f32.i32(float [[TMP32]], i32 [[TMP33]]) ; IEEE-BADFREXP-NEXT: [[TMP35:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[TMP11]]) @@ -4110,7 +4110,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, floa ; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[A:%.*]], float [[B:%.*]]) #[[ATTR1]] { ; IEEE-GOODFREXP-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -4145,9 +4145,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, floa ; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = sub i32 [[TMP25]], [[TMP21]] ; IEEE-GOODFREXP-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP26]], i32 [[TMP27]]) ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -4173,7 +4173,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, floa ; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[A:%.*]], float [[B:%.*]]) #[[ATTR1]] { ; IEEE-BADFREXP-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -4208,9 +4208,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, floa ; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = sub i32 [[TMP25]], [[TMP21]] ; IEEE-BADFREXP-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP26]], i32 [[TMP27]]) ; IEEE-BADFREXP-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -4236,7 +4236,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, floa ; DAZ-SAME: ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[A:%.*]], float [[B:%.*]]) #[[ATTR1]] { ; DAZ-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1]] ; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; DAZ-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -4253,9 +4253,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, floa ; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]]) ; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; DAZ-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -4295,7 +4295,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, floa ; IEEE-GOODFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float nofpclass(sub) [[B:%.*]]) #[[ATTR1]] { ; IEEE-GOODFREXP-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; IEEE-GOODFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1]] ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; IEEE-GOODFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -4330,9 +4330,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, floa ; IEEE-GOODFREXP-NEXT: [[TMP27:%.*]] = sub i32 [[TMP25]], [[TMP21]] ; IEEE-GOODFREXP-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP26]], i32 [[TMP27]]) ; IEEE-GOODFREXP-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-GOODFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; IEEE-GOODFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; IEEE-GOODFREXP-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-GOODFREXP-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; IEEE-GOODFREXP-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -4358,7 +4358,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, floa ; IEEE-BADFREXP-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float nofpclass(sub) [[B:%.*]]) #[[ATTR1]] { ; IEEE-BADFREXP-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; IEEE-BADFREXP-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1]] ; IEEE-BADFREXP-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; IEEE-BADFREXP-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -4393,9 +4393,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, floa ; IEEE-BADFREXP-NEXT: [[TMP27:%.*]] = sub i32 [[TMP25]], [[TMP21]] ; IEEE-BADFREXP-NEXT: [[MD_3ULP:%.*]] = call float @llvm.ldexp.f32.i32(float [[TMP26]], i32 [[TMP27]]) ; IEEE-BADFREXP-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; IEEE-BADFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; IEEE-BADFREXP-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; IEEE-BADFREXP-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; IEEE-BADFREXP-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; IEEE-BADFREXP-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 @@ -4421,7 +4421,7 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, floa ; DAZ-SAME: ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float nofpclass(sub) [[B:%.*]]) #[[ATTR1]] { ; DAZ-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]] ; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1 +; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath [[META1]] ; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[TMP1:%.*]] = call { float, i32 } @llvm.frexp.f32.i32(float [[B]]) ; DAZ-NEXT: [[TMP2:%.*]] = extractvalue { float, i32 } [[TMP1]], 0 @@ -4438,9 +4438,9 @@ define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, floa ; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]]) ; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath !0 +; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fdiv fast float [[A]], [[B]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 -; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath !0 +; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fdiv afn float [[A]], [[B]], !fpmath [[META0]] ; DAZ-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4 ; DAZ-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]] ; DAZ-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4 -- GitLab From fc9a5076c31139878da2fa12ef16090a58d55782 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 11:06:52 -0400 Subject: [PATCH 137/695] llvm-reduce: Reduce nuw/nsw flags from trunc --- llvm/test/tools/llvm-reduce/reduce-flags.ll | 32 +++++++++++++++++++ .../deltas/ReduceInstructionFlags.cpp | 5 +++ 2 files changed, 37 insertions(+) diff --git a/llvm/test/tools/llvm-reduce/reduce-flags.ll b/llvm/test/tools/llvm-reduce/reduce-flags.ll index 036bfdc84ac4..5d6d1260ac50 100644 --- a/llvm/test/tools/llvm-reduce/reduce-flags.ll +++ b/llvm/test/tools/llvm-reduce/reduce-flags.ll @@ -232,3 +232,35 @@ define i32 @or_disjoint_keep(i32 %a, i32 %b) { %op = or disjoint i32 %a, %b ret i32 %op } + +; CHECK-LABEL: @trunc_nuw_drop( +; INTERESTING: = trunc +; RESULT: trunc i64 +define i32 @trunc_nuw_drop(i64 %a) { + %op = trunc nuw i64 %a to i32 + ret i32 %op +} + +; CHECK-LABEL: @trunc_nuw_keep( +; INTERESTING: = trunc nuw +; RESULT: trunc nuw i64 +define i32 @trunc_nuw_keep(i64 %a) { + %op = trunc nuw i64 %a to i32 + ret i32 %op +} + +; CHECK-LABEL: @trunc_nsw_drop( +; INTERESTING: = trunc +; RESULT: trunc i64 +define i32 @trunc_nsw_drop(i64 %a) { + %op = trunc nsw i64 %a to i32 + ret i32 %op +} + +; CHECK-LABEL: @trunc_nsw_keep( +; INTERESTING: = trunc nsw +; RESULT: trunc nsw i64 +define i32 @trunc_nsw_keep(i64 %a) { + %op = trunc nsw i64 %a to i32 + ret i32 %op +} diff --git a/llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp b/llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp index 7b6fe7e5f917..ad619a6c02a4 100644 --- a/llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp +++ b/llvm/tools/llvm-reduce/deltas/ReduceInstructionFlags.cpp @@ -27,6 +27,11 @@ static void reduceFlagsInModule(Oracle &O, ReducerWorkItem &WorkItem) { I.setHasNoSignedWrap(false); if (OBO->hasNoUnsignedWrap() && !O.shouldKeep()) I.setHasNoUnsignedWrap(false); + } else if (auto *Trunc = dyn_cast(&I)) { + if (Trunc->hasNoSignedWrap() && !O.shouldKeep()) + Trunc->setHasNoSignedWrap(false); + if (Trunc->hasNoUnsignedWrap() && !O.shouldKeep()) + Trunc->setHasNoUnsignedWrap(false); } else if (auto *PE = dyn_cast(&I)) { if (PE->isExact() && !O.shouldKeep()) I.setIsExact(false); -- GitLab From 38f996bb2bc4f922c7b441d730ab3a3ad2fa1506 Mon Sep 17 00:00:00 2001 From: Malay Sanghi Date: Mon, 8 Apr 2024 20:31:51 +0800 Subject: [PATCH 138/695] Replace copy with a reference. (#87975) --- llvm/lib/CodeGen/MachinePipeliner.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index b9c6765be445..930504067832 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -1247,7 +1247,7 @@ private: for (auto &MI : *OrigMBB) { if (MI.isDebugInstr()) continue; - for (auto Use : ROMap[&MI].Uses) { + for (auto &Use : ROMap[&MI].Uses) { auto Reg = Use.RegUnit; // Ignore the variable that appears only on one side of phi instruction // because it's used only at the first iteration. @@ -1345,7 +1345,7 @@ private: DenseMap LastUseMI; for (MachineInstr *MI : llvm::reverse(OrderedInsts)) { - for (auto Use : ROMap.find(MI)->getSecond().Uses) { + for (auto &Use : ROMap.find(MI)->getSecond().Uses) { auto Reg = Use.RegUnit; if (!TargetRegs.contains(Reg)) continue; -- GitLab From 8cb642bf18bfd3e6e8576f4f090fa584f68bb0cc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 08:51:53 -0400 Subject: [PATCH 139/695] GlobalISel: Regenerate test checks --- .../call-translator-tail-call-sret.ll | 92 ++++++++++--------- .../AArch64/GlobalISel/constant-dbg-loc.ll | 41 +++++---- .../GlobalISel/irtranslator-store-metadata.ll | 44 +++++---- .../GlobalISel/irtranslator-callingconv.ll | 20 ++++ 4 files changed, 115 insertions(+), 82 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll index ecd7c3ca71be..0ff6ae28279f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call-sret.ll @@ -8,10 +8,11 @@ declare void @test_explicit_sret(ptr sret(i64)) define void @can_tail_call_forwarded_explicit_sret_ptr(ptr sret(i64) %arg) { ; CHECK-LABEL: name: can_tail_call_forwarded_explicit_sret_ptr ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x8 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x8 - ; CHECK: $x8 = COPY [[COPY]](p0) - ; CHECK: TCRETURNdi @test_explicit_sret, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x8 + ; CHECK-NEXT: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8 + ; CHECK-NEXT: $x8 = COPY [[COPY]](p0) + ; CHECK-NEXT: TCRETURNdi @test_explicit_sret, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x8 tail call void @test_explicit_sret(ptr %arg) ret void } @@ -20,13 +21,14 @@ define void @can_tail_call_forwarded_explicit_sret_ptr(ptr sret(i64) %arg) { define void @test_call_explicit_sret(ptr sret(i64) %arg) { ; CHECK-LABEL: name: test_call_explicit_sret ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x8 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x8 - ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp - ; CHECK: $x8 = COPY [[COPY]](p0) - ; CHECK: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 - ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x8 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x8 = COPY [[COPY]](p0) + ; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: RET_ReallyLR call void @test_explicit_sret(ptr %arg) ret void } @@ -34,12 +36,12 @@ define void @test_call_explicit_sret(ptr sret(i64) %arg) { define void @dont_tail_call_explicit_sret_alloca_unused() { ; CHECK-LABEL: name: dont_tail_call_explicit_sret_alloca_unused ; CHECK: bb.1 (%ir-block.0): - ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l - ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp - ; CHECK: $x8 = COPY [[FRAME_INDEX]](p0) - ; CHECK: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 - ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: RET_ReallyLR %l = alloca i64, align 8 tail call void @test_explicit_sret(ptr %l) ret void @@ -48,16 +50,17 @@ define void @dont_tail_call_explicit_sret_alloca_unused() { define void @dont_tail_call_explicit_sret_alloca_dummyusers(ptr %ptr) { ; CHECK-LABEL: name: dont_tail_call_explicit_sret_alloca_dummyusers ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l - ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr) - ; CHECK: G_STORE [[LOAD]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.l) - ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp - ; CHECK: $x8 = COPY [[FRAME_INDEX]](p0) - ; CHECK: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 - ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64) from %ir.ptr) + ; CHECK-NEXT: G_STORE [[LOAD]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.l) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: RET_ReallyLR %l = alloca i64, align 8 %r = load i64, ptr %ptr, align 8 store i64 %r, ptr %l, align 8 @@ -68,15 +71,16 @@ define void @dont_tail_call_explicit_sret_alloca_dummyusers(ptr %ptr) { define void @dont_tail_call_tailcall_explicit_sret_gep(ptr %ptr) { ; CHECK-LABEL: name: dont_tail_call_tailcall_explicit_sret_gep ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 - ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) - ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp - ; CHECK: $x8 = COPY [[PTR_ADD]](p0) - ; CHECK: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 - ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x8 = COPY [[PTR_ADD]](p0) + ; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: RET_ReallyLR %ptr2 = getelementptr i64, ptr %ptr, i32 1 tail call void @test_explicit_sret(ptr %ptr2) ret void @@ -85,14 +89,14 @@ define void @dont_tail_call_tailcall_explicit_sret_gep(ptr %ptr) { define i64 @dont_tail_call_sret_alloca_returned() { ; CHECK-LABEL: name: dont_tail_call_sret_alloca_returned ; CHECK: bb.1 (%ir-block.0): - ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l - ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp - ; CHECK: $x8 = COPY [[FRAME_INDEX]](p0) - ; CHECK: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 - ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp - ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.l) - ; CHECK: $x0 = COPY [[LOAD]](s64) - ; CHECK: RET_ReallyLR implicit $x0 + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.l + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: $x8 = COPY [[FRAME_INDEX]](p0) + ; CHECK-NEXT: BL @test_explicit_sret, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x8 + ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load (s64) from %ir.l) + ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 %l = alloca i64, align 8 tail call void @test_explicit_sret(ptr %l) %r = load i64, ptr %l, align 8 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll index 75865695ea20..5e667eba741a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/constant-dbg-loc.ll @@ -10,24 +10,29 @@ target triple = "arm64-apple-ios5.0.0" define i32 @main() #0 !dbg !14 { ; CHECK-LABEL: name: main ; CHECK: bb.1.entry: - ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1 - ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2 - ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval - ; CHECK: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.retval) - ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load (s32) from @var1) - ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]], debug-location !19 - ; CHECK: G_BRCOND [[ICMP]](s1), %bb.2, debug-location !20 - ; CHECK: G_BR %bb.3, debug-location !20 - ; CHECK: bb.2.if.then: - ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: G_STORE [[C2]](s32), [[GV1]](p0), debug-location !21 :: (store (s32) into @var2) - ; CHECK: bb.3.if.end: - ; CHECK: $w0 = COPY [[C]](s32), debug-location !24 - ; CHECK: RET_ReallyLR implicit $w0, debug-location !24 + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[GV1:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var2 + ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.retval + ; CHECK-NEXT: G_STORE [[C]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %ir.retval) + ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0), debug-location !17 :: (dereferenceable load (s32) from @var1) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[LOAD]](s32), [[C1]], debug-location !19 + ; CHECK-NEXT: G_BRCOND [[ICMP]](s1), %bb.2, debug-location !20 + ; CHECK-NEXT: G_BR %bb.3, debug-location !20 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.if.then: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: G_STORE [[C2]](s32), [[GV1]](p0), debug-location !21 :: (store (s32) into @var2) + ; CHECK-NEXT: G_BR %bb.3, debug-location !23 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.if.end: + ; CHECK-NEXT: $w0 = COPY [[C]](s32), debug-location !24 + ; CHECK-NEXT: RET_ReallyLR implicit $w0, debug-location !24 entry: %retval = alloca i32, align 4 store i32 0, ptr %retval, align 4 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll index f9f92b9e2190..baed1263008d 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll @@ -4,11 +4,12 @@ define void @store_nontemporal(ptr dereferenceable(4) %ptr) { ; CHECK-LABEL: name: store_nontemporal ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: (non-temporal store (s32) into %ir.ptr) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (non-temporal store (s32) into %ir.ptr) + ; CHECK-NEXT: RET_ReallyLR store i32 0, ptr %ptr, align 4, !nontemporal !0 ret void } @@ -16,11 +17,12 @@ define void @store_nontemporal(ptr dereferenceable(4) %ptr) { define void @store_dereferenceable(ptr dereferenceable(4) %ptr) { ; CHECK-LABEL: name: store_dereferenceable ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.ptr) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.ptr) + ; CHECK-NEXT: RET_ReallyLR store i32 0, ptr %ptr, align 4 ret void } @@ -28,11 +30,12 @@ define void @store_dereferenceable(ptr dereferenceable(4) %ptr) { define void @store_volatile_dereferenceable(ptr dereferenceable(4) %ptr) { ; CHECK-LABEL: name: store_volatile_dereferenceable ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: (volatile store (s32) into %ir.ptr) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (volatile store (s32) into %ir.ptr) + ; CHECK-NEXT: RET_ReallyLR store volatile i32 0, ptr %ptr, align 4 ret void } @@ -40,11 +43,12 @@ define void @store_volatile_dereferenceable(ptr dereferenceable(4) %ptr) { define void @store_falkor_strided_access(ptr %ptr) { ; CHECK-LABEL: name: store_falkor_strided_access ; CHECK: bb.1 (%ir-block.0): - ; CHECK: liveins: $x0 - ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store (s32) into %ir.ptr) - ; CHECK: RET_ReallyLR + ; CHECK-NEXT: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store (s32) into %ir.ptr) + ; CHECK-NEXT: RET_ReallyLR store i32 0, ptr %ptr, align 4, !falkor.strided.access !0 ret void } diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll index d1a7339db9af..55e73dc5d29e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll @@ -41,6 +41,7 @@ define i8 @test_i8_args_8(i8 %arg1, i8 %arg2, i8 %arg3, i8 %arg4, i8 %arg5, i8 % ; X86-NEXT: G_STORE [[TRUNC7]](s8), [[GV2]](p0) :: (store (s8) into @a8_8bit) ; X86-NEXT: $al = COPY [[TRUNC]](s8) ; X86-NEXT: RET 0, implicit $al + ; ; X64-LABEL: name: test_i8_args_8 ; X64: bb.1.entry: ; X64-NEXT: liveins: $ecx, $edi, $edx, $esi, $r8d, $r9d @@ -109,6 +110,7 @@ define i32 @test_i32_args_8(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg ; X86-NEXT: G_STORE [[LOAD7]](s32), [[GV2]](p0) :: (store (s32) into @a8_32bit) ; X86-NEXT: $eax = COPY [[LOAD]](s32) ; X86-NEXT: RET 0, implicit $eax + ; ; X64-LABEL: name: test_i32_args_8 ; X64: bb.1.entry: ; X64-NEXT: liveins: $ecx, $edi, $edx, $esi, $r8d, $r9d @@ -196,6 +198,7 @@ define i64 @test_i64_args_8(i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg ; X86-NEXT: $eax = COPY [[UV]](s32) ; X86-NEXT: $edx = COPY [[UV1]](s32) ; X86-NEXT: RET 0, implicit $eax, implicit $edx + ; ; X64-LABEL: name: test_i64_args_8 ; X64: bb.1.entry: ; X64-NEXT: liveins: $rcx, $rdi, $rdx, $rsi, $r8, $r9 @@ -234,6 +237,7 @@ define float @test_float_args(float %arg1, float %arg2) { ; X86-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0) ; X86-NEXT: $fp0 = COPY [[LOAD1]](s32) ; X86-NEXT: RET 0, implicit $fp0 + ; ; X64-LABEL: name: test_float_args ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $xmm0, $xmm1 @@ -254,6 +258,7 @@ define double @test_double_args(double %arg1, double %arg2) { ; X86-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s64) from %fixed-stack.0) ; X86-NEXT: $fp0 = COPY [[LOAD1]](s64) ; X86-NEXT: RET 0, implicit $fp0 + ; ; X64-LABEL: name: test_double_args ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $xmm0, $xmm1 @@ -274,6 +279,7 @@ define <4 x i32> @test_v4i32_args(<4 x i32> %arg1, <4 x i32> %arg2) { ; X86-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $xmm1 ; X86-NEXT: $xmm0 = COPY [[COPY1]](<4 x s32>) ; X86-NEXT: RET 0, implicit $xmm0 + ; ; X64-LABEL: name: test_v4i32_args ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $xmm0, $xmm1 @@ -297,6 +303,7 @@ define <8 x i32> @test_v8i32_args(<8 x i32> %arg1) { ; X86-NEXT: $xmm0 = COPY [[UV]](<4 x s32>) ; X86-NEXT: $xmm1 = COPY [[UV1]](<4 x s32>) ; X86-NEXT: RET 0, implicit $xmm0, implicit $xmm1 + ; ; X64-LABEL: name: test_v8i32_args ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $xmm0, $xmm1 @@ -315,6 +322,7 @@ define void @test_void_return() { ; X86-LABEL: name: test_void_return ; X86: bb.1.entry: ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_void_return ; X64: bb.1.entry: ; X64-NEXT: RET 0 @@ -329,6 +337,7 @@ define ptr @test_memop_i32(ptr %p1) { ; X86-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (p0) from %fixed-stack.0, align 16) ; X86-NEXT: $eax = COPY [[LOAD]](p0) ; X86-NEXT: RET 0, implicit $eax + ; ; X64-LABEL: name: test_memop_i32 ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $rdi @@ -347,6 +356,7 @@ define void @test_trivial_call() { ; X86-NEXT: CALLpcrel32 @trivial_callee, csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_trivial_call ; X64: bb.1 (%ir-block.0): ; X64-NEXT: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp @@ -377,6 +387,7 @@ define void @test_simple_arg(i32 %in0, i32 %in1) { ; X86-NEXT: CALLpcrel32 @simple_arg_callee, csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 8, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_simple_arg ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $edi, $esi @@ -435,6 +446,7 @@ define void @test_simple_arg8_call(i32 %in0) { ; X86-NEXT: CALLpcrel32 @simple_arg8_callee, csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 32, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_simple_arg8_call ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $edi @@ -478,6 +490,7 @@ define i32 @test_simple_return_callee() { ; X86-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY1]] ; X86-NEXT: $eax = COPY [[ADD]](s32) ; X86-NEXT: RET 0, implicit $eax + ; ; X64-LABEL: name: test_simple_return_callee ; X64: bb.1 (%ir-block.0): ; X64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 @@ -521,6 +534,7 @@ define <8 x i32> @test_split_return_callee(<8 x i32> %arg1, <8 x i32> %arg2) { ; X86-NEXT: $xmm0 = COPY [[UV2]](<4 x s32>) ; X86-NEXT: $xmm1 = COPY [[UV3]](<4 x s32>) ; X86-NEXT: RET 0, implicit $xmm0, implicit $xmm1 + ; ; X64-LABEL: name: test_split_return_callee ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $xmm0, $xmm1, $xmm2, $xmm3 @@ -559,6 +573,7 @@ define void @test_indirect_call(ptr %func) { ; X86-NEXT: CALL32r [[LOAD]](p0), csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_indirect_call ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $rdi @@ -603,6 +618,7 @@ define void @test_abi_exts_call(ptr %addr) { ; X86-NEXT: CALLpcrel32 @take_char, csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 4, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_abi_exts_call ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $rdi @@ -654,6 +670,7 @@ define void @test_variadic_call_1(ptr %addr_ptr, ptr %val_ptr) { ; X86-NEXT: CALLpcrel32 @variadic_callee, csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 8, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_variadic_call_1 ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $rdi, $rsi @@ -696,6 +713,7 @@ define void @test_variadic_call_2(ptr %addr_ptr, ptr %val_ptr) { ; X86-NEXT: CALLpcrel32 @variadic_callee, csr_32, implicit $esp, implicit $ssp ; X86-NEXT: ADJCALLSTACKUP32 12, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_variadic_call_2 ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $rdi, $rsi @@ -728,6 +746,7 @@ define <32 x float> @test_return_v32f32() { ; X86-NEXT: G_STORE [[BUILD_VECTOR]](<32 x s32>), [[LOAD]](p0) :: (store (<32 x s32>)) ; X86-NEXT: $eax = COPY [[LOAD]](p0) ; X86-NEXT: RET 0 + ; ; X64-LABEL: name: test_return_v32f32 ; X64: bb.1 (%ir-block.0): ; X64-NEXT: liveins: $rdi @@ -757,6 +776,7 @@ define float @test_call_v32f32() { ; X86-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[LOAD]](<32 x s32>), [[C]](s32) ; X86-NEXT: $fp0 = COPY [[EVEC]](s32) ; X86-NEXT: RET 0, implicit $fp0 + ; ; X64-LABEL: name: test_call_v32f32 ; X64: bb.1 (%ir-block.0): ; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 -- GitLab From 95f984f37e390a6d2e8a4b0852ea4d5a83126287 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 11:50:53 -0400 Subject: [PATCH 140/695] ValueTracking: Don't use unnecessary null checked dyn_cast --- llvm/lib/Analysis/ValueTracking.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 0b0e2653f8df..5279f03767ed 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -4501,7 +4501,7 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth"); - if (auto *CFP = dyn_cast_or_null(V)) { + if (auto *CFP = dyn_cast(V)) { Known.KnownFPClasses = CFP->getValueAPF().classify(); Known.SignBit = CFP->isNegative(); return; -- GitLab From 8c6e0459c49da298f3b911fc3699c2254a20d882 Mon Sep 17 00:00:00 2001 From: bahareh-farhadi <53280095+bahareh-farhadi@users.noreply.github.com> Date: Mon, 8 Apr 2024 08:35:28 -0400 Subject: [PATCH 141/695] [zOS] Turn CLANG_INTERPRETER_PLATFORM_CANNOT_CREATE_LLJIT on for zOS (#87797) PR [https://github.com/llvm/llvm-project/pull/84461](https://github.com/llvm/llvm-project/pull/84461) disabled `clang/unittests/Interpreter/InterpreterExtensionsTest.cpp` for AIX by turning on `CLANG_INTERPRETER_PLATFORM_CANNOT_CREATE_LLJIT`. This PR turns `CLANG_INTERPRETER_PLATFORM_CANNOT_CREATE_LLJIT` on for zOS as well, since LLJIT cannot be created on zOS either. Co-authored-by: Bahareh --- clang/unittests/Interpreter/InterpreterExtensionsTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp b/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp index 1ba865a79ed7..b971cd550dc5 100644 --- a/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp +++ b/clang/unittests/Interpreter/InterpreterExtensionsTest.cpp @@ -30,7 +30,7 @@ #include -#if defined(_AIX) +#if defined(_AIX) || defined(__MVS__) #define CLANG_INTERPRETER_PLATFORM_CANNOT_CREATE_LLJIT #endif -- GitLab From eb07600f8eff793664a4d6b181e6f31de1f5f973 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Mon, 8 Apr 2024 20:52:37 +0800 Subject: [PATCH 142/695] [NewPM] support `disablePass`, `insertPass` in `CodeGenPassBuilder` (#87147) Currently only machine function passes support `insertPass`, but it seems to be enough, all targets tune their pipelines when adding machine function passes. --- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 37 ++++++++++++------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 00eb9b096a93..ab231dbbb6a6 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -176,9 +176,6 @@ protected: // Add Function Pass if constexpr (is_detected::value) { FPM.addPass(std::forward(Pass)); - - for (auto &C : PB.AfterCallbacks) - C(Name); } else { // Add Module Pass if (!FPM.isEmpty()) { @@ -187,9 +184,6 @@ protected: } MPM.addPass(std::forward(Pass)); - - for (auto &C : PB.AfterCallbacks) - C(Name); } } @@ -222,9 +216,6 @@ protected: // Add Function Pass if constexpr (is_detected::value) { MFPM.addPass(std::forward(Pass)); - - for (auto &C : PB.AfterCallbacks) - C(Name); } else { // Add Module Pass if (!MFPM.isEmpty()) { @@ -234,10 +225,10 @@ protected: } MPM.addPass(std::forward(Pass)); - - for (auto &C : PB.AfterCallbacks) - C(Name); } + + for (auto &C : PB.AfterCallbacks) + C(Name, MFPM); } private: @@ -461,6 +452,24 @@ protected: Error addRegAssignmentFast(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; + /// Allow the target to disable a specific pass by default. + /// Backend can declare unwanted passes in constructor. + template void disablePass() { + BeforeCallbacks.emplace_back( + [](StringRef Name) { return ((Name != PassTs::name()) && ...); }); + } + + /// Insert InsertedPass pass after TargetPass pass. + /// Only machine function passes are supported. + template + void insertPass(InsertedPassT &&Pass) { + AfterCallbacks.emplace_back( + [&](StringRef Name, MachineFunctionPassManager &MFPM) mutable { + if (Name == TargetPassT::name()) + MFPM.addPass(std::forward(Pass)); + }); + } + private: DerivedT &derived() { return static_cast(*this); } const DerivedT &derived() const { @@ -480,7 +489,9 @@ private: mutable SmallVector, 4> BeforeCallbacks; - mutable SmallVector, 4> AfterCallbacks; + mutable SmallVector< + llvm::unique_function, 4> + AfterCallbacks; /// Helper variable for `-start-before/-start-after/-stop-before/-stop-after` mutable bool Started = true; -- GitLab From 662c62609e8ee2dc996da69e11c0d594e799c299 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Mon, 8 Apr 2024 13:59:27 +0100 Subject: [PATCH 143/695] [mlir][arith] Refine the verifier for arith.constant (#86178) Disallows initialization of scalable vectors with an attribute of arbitrary values, e.g.: ```mlir %c = arith.constant dense<[0, 1]> : vector<[2] x i32> ``` Initialization using vector splats remains allowed (i.e. when all the init values are identical): ```mlir %c = arith.constant dense<[1, 1]> : vector<[2] x i32> ``` --- mlir/lib/Dialect/Arith/IR/ArithOps.cpp | 6 ++++++ mlir/test/Dialect/Arith/invalid.mlir | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp index 1d68a4f7292b..efc4bfe622d5 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp @@ -213,6 +213,12 @@ LogicalResult arith::ConstantOp::verify() { return emitOpError( "value must be an integer, float, or elements attribute"); } + + auto vecType = dyn_cast(type); + if (vecType && vecType.isScalable() && !isa(getValue())) + return emitOpError( + "intializing scalable vectors with elements attribute is not supported" + " unless it's a vector splat"); return success(); } diff --git a/mlir/test/Dialect/Arith/invalid.mlir b/mlir/test/Dialect/Arith/invalid.mlir index 6d8ac0ada52b..fdc907a7c6af 100644 --- a/mlir/test/Dialect/Arith/invalid.mlir +++ b/mlir/test/Dialect/Arith/invalid.mlir @@ -64,6 +64,15 @@ func.func @constant_out_of_range() { // ----- +func.func @constant_invalid_scalable_vec_initialization() { +^bb0: + // expected-error@+1 {{'arith.constant' op intializing scalable vectors with elements attribute is not supported unless it's a vector splat}} + %c = arith.constant dense<[0, 1]> : vector<[2] x i32> + return +} + +// ----- + func.func @constant_wrong_type() { ^bb: %x = "arith.constant"(){value = 10.} : () -> f32 // expected-error {{'arith.constant' op failed to verify that all of {value, result} have same type}} -- GitLab From 4308c7422d12c8a7efe6cf1c5c6136e54ba410ce Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 8 Apr 2024 09:01:28 -0400 Subject: [PATCH 144/695] [BOLT][NFC] Refactor relocation arch selection (#87829) Convert the relocation routines to switch on architecture and have an explicit unreachable default. --- bolt/lib/Core/Relocation.cpp | 195 ++++++++++++++++++++++++++--------- 1 file changed, 144 insertions(+), 51 deletions(-) diff --git a/bolt/lib/Core/Relocation.cpp b/bolt/lib/Core/Relocation.cpp index cbf95a7db08b..d16b7a94787c 100644 --- a/bolt/lib/Core/Relocation.cpp +++ b/bolt/lib/Core/Relocation.cpp @@ -774,60 +774,95 @@ static bool isPCRelativeRISCV(uint64_t Type) { } bool Relocation::isSupported(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + return false; + case Triple::aarch64: return isSupportedAArch64(Type); - if (Arch == Triple::riscv64) + case Triple::riscv64: return isSupportedRISCV(Type); - return isSupportedX86(Type); + case Triple::x86_64: + return isSupportedX86(Type); + } } size_t Relocation::getSizeForType(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return getSizeForTypeAArch64(Type); - if (Arch == Triple::riscv64) + case Triple::riscv64: return getSizeForTypeRISCV(Type); - return getSizeForTypeX86(Type); + case Triple::x86_64: + return getSizeForTypeX86(Type); + } } bool Relocation::skipRelocationType(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return skipRelocationTypeAArch64(Type); - if (Arch == Triple::riscv64) + case Triple::riscv64: return skipRelocationTypeRISCV(Type); - return skipRelocationTypeX86(Type); + case Triple::x86_64: + return skipRelocationTypeX86(Type); + } } bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return skipRelocationProcessAArch64(Type, Contents); - if (Arch == Triple::riscv64) - skipRelocationProcessRISCV(Type, Contents); - return skipRelocationProcessX86(Type, Contents); + case Triple::riscv64: + return skipRelocationProcessRISCV(Type, Contents); + case Triple::x86_64: + return skipRelocationProcessX86(Type, Contents); + } } uint64_t Relocation::encodeValue(uint64_t Type, uint64_t Value, uint64_t PC) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return encodeValueAArch64(Type, Value, PC); - if (Arch == Triple::riscv64) + case Triple::riscv64: return encodeValueRISCV(Type, Value, PC); - return encodeValueX86(Type, Value, PC); + case Triple::x86_64: + return encodeValueX86(Type, Value, PC); + } } uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents, uint64_t PC) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return extractValueAArch64(Type, Contents, PC); - if (Arch == Triple::riscv64) + case Triple::riscv64: return extractValueRISCV(Type, Contents, PC); - return extractValueX86(Type, Contents, PC); + case Triple::x86_64: + return extractValueX86(Type, Contents, PC); + } } bool Relocation::isGOT(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return isGOTAArch64(Type); - if (Arch == Triple::riscv64) + case Triple::riscv64: return isGOTRISCV(Type); - return isGOTX86(Type); + case Triple::x86_64: + return isGOTX86(Type); + } } bool Relocation::isX86GOTPCRELX(uint64_t Type) { @@ -845,27 +880,42 @@ bool Relocation::isX86GOTPC64(uint64_t Type) { bool Relocation::isNone(uint64_t Type) { return Type == getNone(); } bool Relocation::isRelative(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return Type == ELF::R_AARCH64_RELATIVE; - if (Arch == Triple::riscv64) + case Triple::riscv64: return Type == ELF::R_RISCV_RELATIVE; - return Type == ELF::R_X86_64_RELATIVE; + case Triple::x86_64: + return Type == ELF::R_X86_64_RELATIVE; + } } bool Relocation::isIRelative(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return Type == ELF::R_AARCH64_IRELATIVE; - if (Arch == Triple::riscv64) + case Triple::riscv64: llvm_unreachable("not implemented"); - return Type == ELF::R_X86_64_IRELATIVE; + case Triple::x86_64: + return Type == ELF::R_X86_64_IRELATIVE; + } } bool Relocation::isTLS(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return isTLSAArch64(Type); - if (Arch == Triple::riscv64) + case Triple::riscv64: return isTLSRISCV(Type); - return isTLSX86(Type); + case Triple::x86_64: + return isTLSX86(Type); + } } bool Relocation::isInstructionReference(uint64_t Type) { @@ -882,49 +932,81 @@ bool Relocation::isInstructionReference(uint64_t Type) { } uint64_t Relocation::getNone() { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return ELF::R_AARCH64_NONE; - if (Arch == Triple::riscv64) + case Triple::riscv64: return ELF::R_RISCV_NONE; - return ELF::R_X86_64_NONE; + case Triple::x86_64: + return ELF::R_X86_64_NONE; + } } uint64_t Relocation::getPC32() { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return ELF::R_AARCH64_PREL32; - if (Arch == Triple::riscv64) + case Triple::riscv64: return ELF::R_RISCV_32_PCREL; - return ELF::R_X86_64_PC32; + case Triple::x86_64: + return ELF::R_X86_64_PC32; + } } uint64_t Relocation::getPC64() { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return ELF::R_AARCH64_PREL64; - if (Arch == Triple::riscv64) + case Triple::riscv64: llvm_unreachable("not implemented"); - return ELF::R_X86_64_PC64; + case Triple::x86_64: + return ELF::R_X86_64_PC64; + } } bool Relocation::isPCRelative(uint64_t Type) { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return isPCRelativeAArch64(Type); - if (Arch == Triple::riscv64) + case Triple::riscv64: return isPCRelativeRISCV(Type); - return isPCRelativeX86(Type); + case Triple::x86_64: + return isPCRelativeX86(Type); + } } uint64_t Relocation::getAbs64() { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return ELF::R_AARCH64_ABS64; - if (Arch == Triple::riscv64) + case Triple::riscv64: return ELF::R_RISCV_64; - return ELF::R_X86_64_64; + case Triple::x86_64: + return ELF::R_X86_64_64; + } } uint64_t Relocation::getRelative() { - if (Arch == Triple::aarch64) + switch (Arch) { + default: + llvm_unreachable("Unsupported architecture"); + case Triple::aarch64: return ELF::R_AARCH64_RELATIVE; - return ELF::R_X86_64_RELATIVE; + case Triple::riscv64: + llvm_unreachable("not implemented"); + case Triple::x86_64: + return ELF::R_X86_64_RELATIVE; + } } size_t Relocation::emit(MCStreamer *Streamer) const { @@ -991,9 +1073,16 @@ void Relocation::print(raw_ostream &OS) const { static const char *AArch64RelocNames[] = { #include "llvm/BinaryFormat/ELFRelocs/AArch64.def" }; - if (Arch == Triple::aarch64) + switch (Arch) { + default: + OS << "RType:" << Twine::utohexstr(Type); + break; + + case Triple::aarch64: OS << AArch64RelocNames[Type]; - else if (Arch == Triple::riscv64) { + break; + + case Triple::riscv64: // RISC-V relocations are not sequentially numbered so we cannot use an // array switch (Type) { @@ -1006,8 +1095,12 @@ void Relocation::print(raw_ostream &OS) const { break; #include "llvm/BinaryFormat/ELFRelocs/RISCV.def" } - } else + break; + + case Triple::x86_64: OS << X86RelocNames[Type]; + break; + } OS << ", 0x" << Twine::utohexstr(Offset); if (Symbol) { OS << ", " << Symbol->getName(); -- GitLab From f6357bb4283e72d1248b9c7eb67d98bea71d5f50 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 8 Apr 2024 09:02:10 -0400 Subject: [PATCH 145/695] [llvm][docs] Resort cmake macros (#87551) The cmake macro documentation had once again become unsorted. For names of the form 'PREFIX_{list-or-category}_SUFFIX' I collate as 'PREFIX_SUFFIX'. --- llvm/docs/CMake.rst | 137 ++++++++++++++++++++++---------------------- 1 file changed, 68 insertions(+), 69 deletions(-) diff --git a/llvm/docs/CMake.rst b/llvm/docs/CMake.rst index 7a809d44d3d8..f7f8ed2e1a85 100644 --- a/llvm/docs/CMake.rst +++ b/llvm/docs/CMake.rst @@ -283,14 +283,14 @@ manual, or execute ``cmake --help-variable VARIABLE_NAME``. The path to install executables, relative to the *CMAKE_INSTALL_PREFIX*. Defaults to "bin". -**CMAKE_INSTALL_INCLUDEDIR**:PATH - The path to install header files, relative to the *CMAKE_INSTALL_PREFIX*. - Defaults to "include". - **CMAKE_INSTALL_DOCDIR**:PATH The path to install documentation, relative to the *CMAKE_INSTALL_PREFIX*. Defaults to "share/doc". +**CMAKE_INSTALL_INCLUDEDIR**:PATH + The path to install header files, relative to the *CMAKE_INSTALL_PREFIX*. + Defaults to "include". + **CMAKE_INSTALL_MANDIR**:PATH The path to install manpage files, relative to the *CMAKE_INSTALL_PREFIX*. Defaults to "share/man". @@ -328,12 +328,6 @@ enabled sub-projects. Nearly all of these variable names begin with allows for them to be specified as values in CMAKE_BUILD_TYPE without encountering a fatal error during the configuration process. -**LLVM_UNREACHABLE_OPTIMIZE**:BOOL - This flag controls the behavior of `llvm_unreachable()` in release build - (when assertions are disabled in general). When ON (default) then - `llvm_unreachable()` is considered "undefined behavior" and optimized as - such. When OFF it is instead replaced with a guaranteed "trap". - **LLVM_APPEND_VC_REV**:BOOL Embed version control revision info (Git revision id). The version info is provided by the ``LLVM_REVISION`` macro in @@ -341,15 +335,15 @@ enabled sub-projects. Nearly all of these variable names begin with need revision info can disable this option to avoid re-linking most binaries after a branch switch. Defaults to ON. +**LLVM_FORCE_VC_REPOSITORY**:STRING + Set the git repository to include in version info rather than calling git to + determine it. + **LLVM_FORCE_VC_REVISION**:STRING Force a specific Git revision id rather than calling to git to determine it. This is useful in environments where git is not available or non-functional but the VC revision is available through other means. -**LLVM_FORCE_VC_REPOSITORY**:STRING - Set the git repository to include in version info rather than calling git to - determine it. - **LLVM_BUILD_32_BITS**:BOOL Build 32-bit executables and libraries on 64-bit systems. This option is available only on some 64-bit Unix systems. Defaults to OFF. @@ -381,22 +375,6 @@ enabled sub-projects. Nearly all of these variable names begin with *LLVM_CODE_COVERAGE_TARGETS* and *LLVM_COVERAGE_SOURCE_DIRS* for more information on configuring code coverage reports. -**LLVM_CODE_COVERAGE_TARGETS**:STRING - If set to a semicolon separated list of targets, those targets will be used - to drive the code coverage reports. If unset, the target list will be - constructed using the LLVM build's CMake export list. - -**LLVM_COVERAGE_SOURCE_DIRS**:STRING - If set to a semicolon separated list of directories, the coverage reports - will limit code coverage summaries to just the listed directories. If unset, - coverage reports will include all sources identified by the tooling. - -**LLVM_INDIVIDUAL_TEST_COVERAGE**:BOOL - Enable individual test case coverage. When set to ON, code coverage data for - each test case will be generated and stored in a separate directory under the - config.test_exec_root path. This feature allows code coverage analysis of each - individual test case. Defaults to OFF. - **LLVM_BUILD_LLVM_DYLIB**:BOOL If enabled, the target for building the libLLVM shared library is added. This library contains all of LLVM's components in a single shared library. @@ -429,15 +407,22 @@ enabled sub-projects. Nearly all of these variable names begin with options, which are passed to the CCACHE_MAXSIZE and CCACHE_DIR environment variables, respectively. +**LLVM_CODE_COVERAGE_TARGETS**:STRING + If set to a semicolon separated list of targets, those targets will be used + to drive the code coverage reports. If unset, the target list will be + constructed using the LLVM build's CMake export list. + +**LLVM_COVERAGE_SOURCE_DIRS**:STRING + If set to a semicolon separated list of directories, the coverage reports + will limit code coverage summaries to just the listed directories. If unset, + coverage reports will include all sources identified by the tooling. + **LLVM_CREATE_XCODE_TOOLCHAIN**:BOOL macOS Only: If enabled CMake will generate a target named 'install-xcode-toolchain'. This target will create a directory at $CMAKE_INSTALL_PREFIX/Toolchains containing an xctoolchain directory which can be used to override the default system tools. -**LLVM__LINKER_FLAGS**:STRING - Defines the set of linker flags that should be applied to a . - **LLVM_DEFAULT_TARGET_TRIPLE**:STRING LLVM target to use for code generation when no target is explicitly specified. It defaults to "host", meaning that it shall pick the architecture @@ -514,11 +499,6 @@ enabled sub-projects. Nearly all of these variable names begin with **LLVM_ENABLE_EXPENSIVE_CHECKS**:BOOL Enable additional time/memory expensive checking. Defaults to OFF. -**LLVM_ENABLE_HTTPLIB**:BOOL - Enables the optional cpp-httplib dependency which is used by llvm-debuginfod - to serve debug info over HTTP. `cpp-httplib `_ - must be installed, or `httplib_ROOT` must be set. Defaults to OFF. - **LLVM_ENABLE_FFI**:BOOL Indicates whether the LLVM Interpreter will be linked with the Foreign Function Interface library (libffi) in order to enable calling external functions. @@ -527,6 +507,11 @@ enabled sub-projects. Nearly all of these variable names begin with FFI_LIBRARY_DIR to the directories where ffi.h and libffi.so can be found, respectively. Defaults to OFF. +**LLVM_ENABLE_HTTPLIB**:BOOL + Enables the optional cpp-httplib dependency which is used by llvm-debuginfod + to serve debug info over HTTP. `cpp-httplib `_ + must be installed, or `httplib_ROOT` must be set. Defaults to OFF. + **LLVM_ENABLE_IDE**:BOOL Tell the build system that an IDE is being used. This in turn disables the creation of certain convenience build system targets, such as the various @@ -539,11 +524,6 @@ enabled sub-projects. Nearly all of these variable names begin with passed to invocations of both so that the project is built using libc++ instead of stdlibc++. Defaults to OFF. -**LLVM_ENABLE_LLVM_LIBC**: BOOL - If the LLVM libc overlay is installed in a location where the host linker - can access it, all built executables will be linked against the LLVM libc - overlay before linking against the system libc. Defaults to OFF. - **LLVM_ENABLE_LIBPFM**:BOOL Enable building with libpfm to support hardware counter measurements in LLVM tools. @@ -554,6 +534,11 @@ enabled sub-projects. Nearly all of these variable names begin with build where a dependency is added from the first stage to the second ensuring that lld is built before stage2 begins. +**LLVM_ENABLE_LLVM_LIBC**: BOOL + If the LLVM libc overlay is installed in a location where the host linker + can access it, all built executables will be linked against the LLVM libc + overlay before linking against the system libc. Defaults to OFF. + **LLVM_ENABLE_LTO**:STRING Add ``-flto`` or ``-flto=`` flags to the compile and link command lines, enabling link-time optimization. Possible values are ``Off``, @@ -581,6 +566,9 @@ enabled sub-projects. Nearly all of these variable names begin with The full list is: ``clang;clang-tools-extra;cross-project-tests;libc;libclc;lld;lldb;openmp;polly;pstl`` +**LLVM_ENABLE_RTTI**:BOOL + Build LLVM with run-time type information. Defaults to OFF. + **LLVM_ENABLE_RUNTIMES**:STRING Build libc++, libc++abi, libunwind or compiler-rt using the just-built compiler. This is the correct way to build runtimes when putting together a toolchain. @@ -593,10 +581,6 @@ enabled sub-projects. Nearly all of these variable names begin with To enable all of them, use: ``LLVM_ENABLE_RUNTIMES=all`` - -**LLVM_ENABLE_RTTI**:BOOL - Build LLVM with run-time type information. Defaults to OFF. - **LLVM_ENABLE_SPHINX**:BOOL If specified, CMake will search for the ``sphinx-build`` executable and will make the ``SPHINX_OUTPUT_HTML`` and ``SPHINX_OUTPUT_MAN`` CMake options available. @@ -634,14 +618,6 @@ enabled sub-projects. Nearly all of these variable names begin with llvm. This will build the experimental target without needing it to add to the list of all the targets available in the LLVM's main CMakeLists.txt. -**LLVM_EXTERNAL_{CLANG,LLD,POLLY}_SOURCE_DIR**:PATH - These variables specify the path to the source directory for the external - LLVM projects Clang, lld, and Polly, respectively, relative to the top-level - source directory. If the in-tree subdirectory for an external project - exists (e.g., llvm/tools/clang for Clang), then the corresponding variable - will not be used. If the variable for an external project does not point - to a valid path, then that project will not be built. - **LLVM_EXTERNAL_PROJECTS**:STRING Semicolon-separated list of additional external projects to build as part of llvm. For each project LLVM_EXTERNAL__SOURCE_DIR have to be specified @@ -650,6 +626,14 @@ enabled sub-projects. Nearly all of these variable names begin with -DLLVM_EXTERNAL_FOO_SOURCE_DIR=/src/foo -DLLVM_EXTERNAL_BAR_SOURCE_DIR=/src/bar``. +**LLVM_EXTERNAL_{CLANG,LLD,POLLY}_SOURCE_DIR**:PATH + These variables specify the path to the source directory for the external + LLVM projects Clang, lld, and Polly, respectively, relative to the top-level + source directory. If the in-tree subdirectory for an external project + exists (e.g., llvm/tools/clang for Clang), then the corresponding variable + will not be used. If the variable for an external project does not point + to a valid path, then that project will not be built. + **LLVM_EXTERNALIZE_DEBUGINFO**:BOOL Generate dSYM files and strip executables and libraries (Darwin Only). Defaults to OFF. @@ -680,6 +664,12 @@ enabled sub-projects. Nearly all of these variable names begin with Generate build targets for the LLVM tools. Defaults to ON. You can use this option to disable the generation of build targets for the LLVM tools. +**LLVM_INDIVIDUAL_TEST_COVERAGE**:BOOL + Enable individual test case coverage. When set to ON, code coverage data for + each test case will be generated and stored in a separate directory under the + config.test_exec_root path. This feature allows code coverage analysis of each + individual test case. Defaults to OFF. + **LLVM_INSTALL_BINUTILS_SYMLINKS**:BOOL Install symlinks from the binutils tool names to the corresponding LLVM tools. For example, ar will be symlinked to llvm-ar. @@ -702,6 +692,11 @@ enabled sub-projects. Nearly all of these variable names begin with If enabled, utility binaries like ``FileCheck`` and ``not`` will be installed to CMAKE_INSTALL_PREFIX. +**LLVM_INSTALL_DOXYGEN_HTML_DIR**:STRING + The path to install Doxygen-generated HTML documentation to. This path can + either be absolute or relative to the *CMAKE_INSTALL_PREFIX*. Defaults to + ``${CMAKE_INSTALL_DOCDIR}/llvm/doxygen-html``. + **LLVM_INTEGRATED_CRT_ALLOC**:PATH On Windows, allows embedding a different C runtime allocator into the LLVM tools and libraries. Using a lock-free allocator such as the ones listed below @@ -718,17 +713,15 @@ enabled sub-projects. Nearly all of these variable names begin with This flag needs to be used along with the static CRT, ie. if building the Release target, add -DCMAKE_MSVC_RUNTIME_LIBRARY=MultiThreaded. -**LLVM_INSTALL_DOXYGEN_HTML_DIR**:STRING - The path to install Doxygen-generated HTML documentation to. This path can - either be absolute or relative to the *CMAKE_INSTALL_PREFIX*. Defaults to - ``${CMAKE_INSTALL_DOCDIR}/llvm/doxygen-html``. - **LLVM_LINK_LLVM_DYLIB**:BOOL If enabled, tools will be linked with the libLLVM shared library. Defaults to OFF. Setting LLVM_LINK_LLVM_DYLIB to ON also sets LLVM_BUILD_LLVM_DYLIB to ON. This option is not available on Windows. +**LLVM__LINKER_FLAGS**:STRING + Defines the set of linker flags that should be applied to a . + **LLVM_LIT_ARGS**:STRING Arguments given to lit. ``make check`` and ``make clang-test`` are affected. By default, ``'-sv --no-progress-bar'`` on Visual C++ and Xcode, ``'-sv'`` on @@ -770,6 +763,10 @@ enabled sub-projects. Nearly all of these variable names begin with **LLVM_PARALLEL_TABLEGEN_JOBS**:STRING Define the maximum number of concurrent tablegen jobs. +**LLVM_PROFDATA_FILE**:PATH + Path to a profdata file to pass into clang's -fprofile-instr-use flag. This + can only be specified if you're building with clang. + **LLVM_RAM_PER_COMPILE_JOB**:STRING Calculates the amount of Ninja compile jobs according to available resources. Value has to be in MB, overwrites LLVM_PARALLEL_COMPILE_JOBS. Compile jobs @@ -788,10 +785,6 @@ enabled sub-projects. Nearly all of these variable names begin with Value has to be in MB, overwrites LLVM_PARALLEL_TABLEGEN_JOBS. Tablegen jobs will be between one and amount of logical cores. -**LLVM_PROFDATA_FILE**:PATH - Path to a profdata file to pass into clang's -fprofile-instr-use flag. This - can only be specified if you're building with clang. - **LLVM_REVERSE_ITERATION**:BOOL If enabled, all supported unordered llvm containers would be iterated in reverse order. This is useful for uncovering non-determinism caused by @@ -829,6 +822,12 @@ enabled sub-projects. Nearly all of these variable names begin with ``LLVM_USE_SANITIZER`` contains ``Undefined``. This can be used to override the default set of UBSan flags. +**LLVM_UNREACHABLE_OPTIMIZE**:BOOL + This flag controls the behavior of `llvm_unreachable()` in release build + (when assertions are disabled in general). When ON (default) then + `llvm_unreachable()` is considered "undefined behavior" and optimized as + such. When OFF it is instead replaced with a guaranteed "trap". + **LLVM_USE_INTEL_JITEVENTS**:BOOL Enable building support for Intel JIT Events API. Defaults to OFF. @@ -892,6 +891,11 @@ Advanced variables These are niche, and changing them from their defaults is more likely to cause things to go wrong. They are also unstable across LLVM versions. +**LLVM_EXAMPLES_INSTALL_DIR**:STRING + The path for examples of using LLVM, relative to the *CMAKE_INSTALL_PREFIX*. + Only matters if *LLVM_BUILD_EXAMPLES* is enabled. + Defaults to "examples". + **LLVM_TOOLS_INSTALL_DIR**:STRING The path to install the main LLVM tools, relative to the *CMAKE_INSTALL_PREFIX*. Defaults to *CMAKE_INSTALL_BINDIR*. @@ -901,11 +905,6 @@ things to go wrong. They are also unstable across LLVM versions. Only matters if *LLVM_INSTALL_UTILS* is enabled. Defaults to *LLVM_TOOLS_INSTALL_DIR*. -**LLVM_EXAMPLES_INSTALL_DIR**:STRING - The path for examples of using LLVM, relative to the *CMAKE_INSTALL_PREFIX*. - Only matters if *LLVM_BUILD_EXAMPLES* is enabled. - Defaults to "examples". - CMake Caches ============ -- GitLab From 2921a0928c71f4ee652a2478283e47ab5ffebf58 Mon Sep 17 00:00:00 2001 From: Jefferson Le Quellec Date: Wed, 27 Mar 2024 15:25:16 +0100 Subject: [PATCH 146/695] Make the argument -Xcuda-ptxas visible to the driver in cl-mode It has been noticed that the arguments are being passed twice to ptxas. This also has been fixed by filtering out the arguments before appending them to the new DAL created by CudaToolChain::TranslateArgs. github:https://github.com/llvm/llvm-project/pull/86807 --- clang/include/clang/Driver/Options.td | 3 ++- clang/lib/Driver/ToolChains/Cuda.cpp | 5 ++++- clang/test/Driver/cuda-external-tools.cu | 8 ++++++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 827d9d7c0c18..f745e573eb26 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1003,7 +1003,8 @@ def : Joined<["-"], "Xclang=">, Group, def Xcuda_fatbinary : Separate<["-"], "Xcuda-fatbinary">, HelpText<"Pass to fatbinary invocation">, MetaVarName<"">; def Xcuda_ptxas : Separate<["-"], "Xcuda-ptxas">, - HelpText<"Pass to the ptxas assembler">, MetaVarName<"">; + HelpText<"Pass to the ptxas assembler">, MetaVarName<"">, + Visibility<[ClangOption, CLOption]>; def Xopenmp_target : Separate<["-"], "Xopenmp-target">, Group, HelpText<"Pass to the target offloading toolchain.">, MetaVarName<"">; def Xopenmp_target_EQ : JoinedAndSeparate<["-"], "Xopenmp-target=">, Group, diff --git a/clang/lib/Driver/ToolChains/Cuda.cpp b/clang/lib/Driver/ToolChains/Cuda.cpp index 5f0b516e1a1a..6634e6d818b3 100644 --- a/clang/lib/Driver/ToolChains/Cuda.cpp +++ b/clang/lib/Driver/ToolChains/Cuda.cpp @@ -990,7 +990,10 @@ CudaToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args, } for (Arg *A : Args) { - DAL->append(A); + // Make sure flags are not duplicated. + if (!llvm::is_contained(*DAL, A)) { + DAL->append(A); + } } if (!BoundArch.empty()) { diff --git a/clang/test/Driver/cuda-external-tools.cu b/clang/test/Driver/cuda-external-tools.cu index 946e144fce38..d9564d026b4f 100644 --- a/clang/test/Driver/cuda-external-tools.cu +++ b/clang/test/Driver/cuda-external-tools.cu @@ -86,6 +86,12 @@ // RUN: -Xcuda-fatbinary -bar1 -Xcuda-ptxas -foo2 -Xcuda-fatbinary -bar2 %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHECK,SM35,PTXAS-EXTRA,FATBINARY-EXTRA %s +// Check -Xcuda-ptxas with clang-cl +// RUN: %clang_cl -### -c -Xcuda-ptxas -foo1 \ +// RUN: --offload-arch=sm_35 --cuda-path=%S/Inputs/CUDA/usr/local/cuda \ +// RUN: -Xcuda-ptxas -foo2 %s 2>&1 \ +// RUN: | FileCheck -check-prefixes=CHECK,SM35,PTXAS-EXTRA %s + // MacOS spot-checks // RUN: %clang -### --target=x86_64-apple-macosx -O0 -c %s 2>&1 \ // RUN: --offload-arch=sm_35 --cuda-path=%S/Inputs/CUDA/usr/local/cuda \ @@ -140,6 +146,8 @@ // CHECK-SAME: "[[PTXFILE]]" // PTXAS-EXTRA-SAME: "-foo1" // PTXAS-EXTRA-SAME: "-foo2" +// CHECK-NOT: "-foo1" +// CHECK-NOT: "-foo2" // RDC-SAME: "-c" // CHECK-NOT: "-c" -- GitLab From a4c84d6ac1014b00257618663a243419630ff626 Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Mon, 8 Apr 2024 13:12:26 +0000 Subject: [PATCH 147/695] [mlir] Only inline if properties are used. This is a followup to 0f52f4ddd909eb38f2a691ffed8469263fe5f635 It breaks dialects that don't use properties yet. --- mlir/test/mlir-tblgen/op-decl-and-defs.td | 4 ++-- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/mlir/test/mlir-tblgen/op-decl-and-defs.td b/mlir/test/mlir-tblgen/op-decl-and-defs.td index 4fa2f308978a..499e3ceecaf0 100644 --- a/mlir/test/mlir-tblgen/op-decl-and-defs.td +++ b/mlir/test/mlir-tblgen/op-decl-and-defs.td @@ -59,9 +59,9 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove, IsolatedFromAbove]> { // CHECK: class AOpGenericAdaptorBase { // CHECK: public: // CHECK: AOpGenericAdaptorBase(AOp{{[[:space:]]}} -// CHECK: ::mlir::IntegerAttr getAttr1Attr() { +// CHECK: ::mlir::IntegerAttr getAttr1Attr(); // CHECK: uint32_t getAttr1(); -// CHECK: ::mlir::FloatAttr getSomeAttr2Attr() { +// CHECK: ::mlir::FloatAttr getSomeAttr2Attr(); // CHECK: ::std::optional< ::llvm::APFloat > getSomeAttr2(); // CHECK: ::mlir::Region &getSomeRegion() { // CHECK: ::mlir::RegionRange getSomeRegions() { diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp index 5739c7e1124f..53ed5cb7c043 100644 --- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp +++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp @@ -4167,8 +4167,8 @@ OpOperandAdaptorEmitter::OpOperandAdaptorEmitter( // value, in which case the default value may be arbitrary code. auto *method = genericAdaptorBase.addMethod( attr.getStorageType(), emitName + "Attr", - attr.hasDefaultValue() ? Method::Properties::None - : Method::Properties::Inline); + attr.hasDefaultValue() || !useProperties ? Method::Properties::None + : Method::Properties::Inline); ERROR_IF_PRUNED(method, "Adaptor::" + emitName + "Attr", op); auto &body = method->body().indent(); if (!useProperties) -- GitLab From 0832b85e0f5b684ad2e5eaf29911ca806eb0db3d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 12:50:42 -0400 Subject: [PATCH 148/695] ValueTracking: Add baseline tests for vector fpclass handling --- llvm/test/Transforms/Attributor/nofpclass.ll | 71 ++++++++++++++++++-- 1 file changed, 67 insertions(+), 4 deletions(-) diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll index 4370cea3c285..96052815c044 100644 --- a/llvm/test/Transforms/Attributor/nofpclass.ll +++ b/llvm/test/Transforms/Attributor/nofpclass.ll @@ -100,14 +100,24 @@ define <2 x double> @returned_strange_constant_vector_elt() { ret <2 x double> } -; Test a vector element that's an undef/poison +; Test a vector element that's undef define <3 x double> @returned_undef_constant_vector_elt() { -; CHECK-LABEL: define nofpclass(nan inf pzero sub norm) <3 x double> @returned_undef_constant_vector_elt() { +; CHECK-LABEL: define nofpclass(nan inf sub norm) <3 x double> @returned_undef_constant_vector_elt() { ; CHECK-NEXT: call void @unknown() -; CHECK-NEXT: ret <3 x double> +; CHECK-NEXT: ret <3 x double> ; call void @unknown() - ret <3 x double> + ret <3 x double> +} + +; Test a vector element that's poison +define <3 x double> @returned_poison_constant_vector_elt() { +; CHECK-LABEL: define nofpclass(nan inf sub norm) <3 x double> @returned_poison_constant_vector_elt() { +; CHECK-NEXT: call void @unknown() +; CHECK-NEXT: ret <3 x double> +; + call void @unknown() + ret <3 x double> } define <2 x double> @returned_qnan_zero_vector() { @@ -1790,6 +1800,32 @@ define float @shufflevector_extractelt3(<2 x float> %arg0, <2 x float> nofpclass ret float %extract } +define float @shufflevector_constantdatavector_demanded0() { +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK-LABEL: define nofpclass(snan inf nzero sub nnorm) float @shufflevector_constantdatavector_demanded0 +; CHECK-SAME: () #[[ATTR3]] { +; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> , <3 x float> poison, <2 x i32> +; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x float> [[SHUFFLE]], i32 0 +; CHECK-NEXT: ret float [[EXTRACT]] +; + %shuffle = shufflevector <3 x float> , <3 x float> poison, <2 x i32> + %extract = extractelement <2 x float> %shuffle, i32 0 + ret float %extract +} + +define float @shufflevector_constantdatavector_demanded1() { +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK-LABEL: define nofpclass(snan inf nzero sub nnorm) float @shufflevector_constantdatavector_demanded1 +; CHECK-SAME: () #[[ATTR3]] { +; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> , <3 x float> poison, <2 x i32> +; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x float> [[SHUFFLE]], i32 1 +; CHECK-NEXT: ret float [[EXTRACT]] +; + %shuffle = shufflevector <3 x float> , <3 x float> poison, <2 x i32> + %extract = extractelement <2 x float> %shuffle, i32 1 + ret float %extract +} + define i32 @fptosi(float nofpclass(inf nan) %arg) { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) ; CHECK-LABEL: define i32 @fptosi @@ -2606,6 +2642,33 @@ bb: ret float %implement.pow } +define [4 x float] @constant_aggregate_zero() { +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK-LABEL: define [4 x float] @constant_aggregate_zero +; CHECK-SAME: () #[[ATTR3]] { +; CHECK-NEXT: ret [4 x float] zeroinitializer +; + ret [4 x float] zeroinitializer +} + +define @scalable_splat_pnorm() { +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK-LABEL: define @scalable_splat_pnorm +; CHECK-SAME: () #[[ATTR3]] { +; CHECK-NEXT: ret shufflevector ( insertelement ( poison, float 1.000000e+00, i64 0), poison, zeroinitializer) +; + ret splat (float 1.0) +} + +define @scalable_splat_zero() { +; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +; CHECK-LABEL: define noundef @scalable_splat_zero +; CHECK-SAME: () #[[ATTR3]] { +; CHECK-NEXT: ret zeroinitializer +; + ret zeroinitializer +} + declare i64 @_Z13get_global_idj(i32 noundef) attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" } -- GitLab From 2bc637b1ce935550b6e09618c76474253943a7cc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 11:43:09 -0400 Subject: [PATCH 149/695] ValueTracking: Handle ConstantAggregateZero in computeKnownFPClass --- llvm/lib/Analysis/ValueTracking.cpp | 6 ++++++ llvm/test/Transforms/Attributor/nofpclass.ll | 4 ++-- llvm/unittests/Analysis/ValueTrackingTest.cpp | 21 +++++++++++++++++++ 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 5279f03767ed..0c8ab4c66cd1 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -4507,6 +4507,12 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, return; } + if (isa(V)) { + Known.KnownFPClasses = fcPosZero; + Known.SignBit = false; + return; + } + // Try to handle fixed width vector constants auto *VFVTy = dyn_cast(V->getType()); const Constant *CV = dyn_cast(V); diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll index 96052815c044..8f3e9d2fd96b 100644 --- a/llvm/test/Transforms/Attributor/nofpclass.ll +++ b/llvm/test/Transforms/Attributor/nofpclass.ll @@ -2644,7 +2644,7 @@ bb: define [4 x float] @constant_aggregate_zero() { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) -; CHECK-LABEL: define [4 x float] @constant_aggregate_zero +; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) [4 x float] @constant_aggregate_zero ; CHECK-SAME: () #[[ATTR3]] { ; CHECK-NEXT: ret [4 x float] zeroinitializer ; @@ -2662,7 +2662,7 @@ define @scalable_splat_pnorm() { define @scalable_splat_zero() { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) -; CHECK-LABEL: define noundef @scalable_splat_zero +; CHECK-LABEL: define noundef nofpclass(nan inf nzero sub norm) @scalable_splat_zero ; CHECK-SAME: () #[[ATTR3]] { ; CHECK-NEXT: ret zeroinitializer ; diff --git a/llvm/unittests/Analysis/ValueTrackingTest.cpp b/llvm/unittests/Analysis/ValueTrackingTest.cpp index 6c6897d83a25..b4d2270d7070 100644 --- a/llvm/unittests/Analysis/ValueTrackingTest.cpp +++ b/llvm/unittests/Analysis/ValueTrackingTest.cpp @@ -2016,6 +2016,27 @@ TEST_F(ComputeKnownFPClassTest, SqrtNszSignBit) { } } +TEST_F(ComputeKnownFPClassTest, Constants) { + parseAssembly("declare float @func()\n" + "define float @test() {\n" + " %A = call float @func()\n" + " ret float %A\n" + "}\n"); + + Type *F32 = Type::getFloatTy(Context); + Type *V4F32 = FixedVectorType::get(F32, 4); + + { + KnownFPClass ConstAggZero = computeKnownFPClass( + ConstantAggregateZero::get(V4F32), M->getDataLayout(), fcAllFlags, 0, + nullptr, nullptr, nullptr, nullptr); + + EXPECT_EQ(fcPosZero, ConstAggZero.KnownFPClasses); + ASSERT_TRUE(ConstAggZero.SignBit); + EXPECT_FALSE(*ConstAggZero.SignBit); + } +} + TEST_F(ValueTrackingTest, isNonZeroRecurrence) { parseAssembly(R"( define i1 @test(i8 %n, i8 %r) { -- GitLab From 0e8736694f752898ed7957a11a11c42f8f6a98d1 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Apr 2024 14:29:17 +0100 Subject: [PATCH 150/695] TextNodeDumper.cpp - remove empty switch to fix MSVC "switch statement contains 'default' but no 'case' labels" warning. NFC. --- clang/lib/AST/TextNodeDumper.cpp | 8 -------- 1 file changed, 8 deletions(-) diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index 0ffbf47c9a2f..f498de637434 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -390,14 +390,6 @@ void TextNodeDumper::Visit(const OpenACCClause *C) { { ColorScope Color(OS, ShowColors, AttrColor); OS << C->getClauseKind(); - - // Handle clauses with parens for types that have no children, likely - // because there is no sub expression. - switch (C->getClauseKind()) { - default: - // Nothing to do here. - break; - } } dumpPointer(C); dumpSourceRange(SourceRange(C->getBeginLoc(), C->getEndLoc())); -- GitLab From f139387fb6e76a5249e8d7c2d124565e6b566ef4 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Apr 2024 14:31:12 +0100 Subject: [PATCH 151/695] Fix MSVC "not all control paths return a value" warning. NFC. --- clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp b/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp index 1fa988f93bdd..cc252d51e3b6 100644 --- a/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp +++ b/clang/lib/InstallAPI/DiagnosticBuilderWrappers.cpp @@ -81,8 +81,9 @@ const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, return DB; case FileType::Invalid: case FileType::All: - llvm_unreachable("Unexpected file type for diagnostics."); + break; } + llvm_unreachable("Unexpected file type for diagnostics."); } const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, -- GitLab From bdf428af9825e684d9ed22d0137a456c131389f7 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 4 Apr 2024 12:50:53 -0400 Subject: [PATCH 152/695] ValueTracking: Consider demanded elts for vector constants in computeKnownFPClass --- llvm/lib/Analysis/ValueTracking.cpp | 3 +++ llvm/test/Transforms/Attributor/nofpclass.ll | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 0c8ab4c66cd1..d50ccd8af287 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -4524,6 +4524,9 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts, // For vectors, verify that each element is not NaN. unsigned NumElts = VFVTy->getNumElements(); for (unsigned i = 0; i != NumElts; ++i) { + if (!DemandedElts[i]) + continue; + Constant *Elt = CV->getAggregateElement(i); if (!Elt) { Known = KnownFPClass(); diff --git a/llvm/test/Transforms/Attributor/nofpclass.ll b/llvm/test/Transforms/Attributor/nofpclass.ll index 8f3e9d2fd96b..7828629f9fc0 100644 --- a/llvm/test/Transforms/Attributor/nofpclass.ll +++ b/llvm/test/Transforms/Attributor/nofpclass.ll @@ -1802,7 +1802,7 @@ define float @shufflevector_extractelt3(<2 x float> %arg0, <2 x float> nofpclass define float @shufflevector_constantdatavector_demanded0() { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) -; CHECK-LABEL: define nofpclass(snan inf nzero sub nnorm) float @shufflevector_constantdatavector_demanded0 +; CHECK-LABEL: define nofpclass(nan inf zero sub nnorm) float @shufflevector_constantdatavector_demanded0 ; CHECK-SAME: () #[[ATTR3]] { ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> , <3 x float> poison, <2 x i32> ; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x float> [[SHUFFLE]], i32 0 @@ -1815,7 +1815,7 @@ define float @shufflevector_constantdatavector_demanded0() { define float @shufflevector_constantdatavector_demanded1() { ; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) -; CHECK-LABEL: define nofpclass(snan inf nzero sub nnorm) float @shufflevector_constantdatavector_demanded1 +; CHECK-LABEL: define nofpclass(nan inf nzero sub norm) float @shufflevector_constantdatavector_demanded1 ; CHECK-SAME: () #[[ATTR3]] { ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <3 x float> , <3 x float> poison, <2 x i32> ; CHECK-NEXT: [[EXTRACT:%.*]] = extractelement <2 x float> [[SHUFFLE]], i32 1 -- GitLab From 40327a628ace90870c7caa0db448a0f2d9863df0 Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski Date: Mon, 8 Apr 2024 14:38:54 +0100 Subject: [PATCH 153/695] Revert "[mlir][arith] Refine the verifier for arith.constant (#86178)" This reverts commit 662c62609e8ee2dc996da69e11c0d594e799c299. Broken both: * https://lab.llvm.org/buildbot/#/builders/61/builds/56565 --- mlir/lib/Dialect/Arith/IR/ArithOps.cpp | 6 ------ mlir/test/Dialect/Arith/invalid.mlir | 9 --------- 2 files changed, 15 deletions(-) diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp index efc4bfe622d5..1d68a4f7292b 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp @@ -213,12 +213,6 @@ LogicalResult arith::ConstantOp::verify() { return emitOpError( "value must be an integer, float, or elements attribute"); } - - auto vecType = dyn_cast(type); - if (vecType && vecType.isScalable() && !isa(getValue())) - return emitOpError( - "intializing scalable vectors with elements attribute is not supported" - " unless it's a vector splat"); return success(); } diff --git a/mlir/test/Dialect/Arith/invalid.mlir b/mlir/test/Dialect/Arith/invalid.mlir index fdc907a7c6af..6d8ac0ada52b 100644 --- a/mlir/test/Dialect/Arith/invalid.mlir +++ b/mlir/test/Dialect/Arith/invalid.mlir @@ -64,15 +64,6 @@ func.func @constant_out_of_range() { // ----- -func.func @constant_invalid_scalable_vec_initialization() { -^bb0: - // expected-error@+1 {{'arith.constant' op intializing scalable vectors with elements attribute is not supported unless it's a vector splat}} - %c = arith.constant dense<[0, 1]> : vector<[2] x i32> - return -} - -// ----- - func.func @constant_wrong_type() { ^bb: %x = "arith.constant"(){value = 10.} : () -> f32 // expected-error {{'arith.constant' op failed to verify that all of {value, result} have same type}} -- GitLab From 8ccf1c117b0dc08f7e9c24fe98f45ebe32e95cd1 Mon Sep 17 00:00:00 2001 From: "Kevin P. Neal" Date: Mon, 8 Apr 2024 10:14:02 -0400 Subject: [PATCH 154/695] [FPEnv][X86] Correct strictfp tests. (#87791) Correct strictfp tests to follow the rules documented in the LangRef: https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics These tests needed the strictfp attribute added to some function definitions. FP wait instructions now appear as a result. Test changes verified with D146845. --- llvm/test/CodeGen/X86/strict-fadd-combines.ll | 12 ++++++++---- llvm/test/CodeGen/X86/strict-fsub-combines.ll | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/llvm/test/CodeGen/X86/strict-fadd-combines.ll b/llvm/test/CodeGen/X86/strict-fadd-combines.ll index e0c61ac8d395..14944fab7d00 100644 --- a/llvm/test/CodeGen/X86/strict-fadd-combines.ll +++ b/llvm/test/CodeGen/X86/strict-fadd-combines.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X64 -define float @fneg_strict_fadd_to_strict_fsub(float %x, float %y) nounwind { +define float @fneg_strict_fadd_to_strict_fsub(float %x, float %y) nounwind strictfp { ; X86-LABEL: fneg_strict_fadd_to_strict_fsub: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -10,6 +10,7 @@ define float @fneg_strict_fadd_to_strict_fsub(float %x, float %y) nounwind { ; X86-NEXT: subss {{[0-9]+}}(%esp), %xmm0 ; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: flds (%esp) +; X86-NEXT: wait ; X86-NEXT: popl %eax ; X86-NEXT: retl ; @@ -22,7 +23,7 @@ define float @fneg_strict_fadd_to_strict_fsub(float %x, float %y) nounwind { ret float %add } -define float @fneg_strict_fadd_to_strict_fsub_2(float %x, float %y) nounwind { +define float @fneg_strict_fadd_to_strict_fsub_2(float %x, float %y) nounwind strictfp { ; X86-LABEL: fneg_strict_fadd_to_strict_fsub_2: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -30,6 +31,7 @@ define float @fneg_strict_fadd_to_strict_fsub_2(float %x, float %y) nounwind { ; X86-NEXT: subss {{[0-9]+}}(%esp), %xmm0 ; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: flds (%esp) +; X86-NEXT: wait ; X86-NEXT: popl %eax ; X86-NEXT: retl ; @@ -42,7 +44,7 @@ define float @fneg_strict_fadd_to_strict_fsub_2(float %x, float %y) nounwind { ret float %add } -define double @fneg_strict_fadd_to_strict_fsub_d(double %x, double %y) nounwind { +define double @fneg_strict_fadd_to_strict_fsub_d(double %x, double %y) nounwind strictfp { ; X86-LABEL: fneg_strict_fadd_to_strict_fsub_d: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -53,6 +55,7 @@ define double @fneg_strict_fadd_to_strict_fsub_d(double %x, double %y) nounwind ; X86-NEXT: subsd 16(%ebp), %xmm0 ; X86-NEXT: movsd %xmm0, (%esp) ; X86-NEXT: fldl (%esp) +; X86-NEXT: wait ; X86-NEXT: movl %ebp, %esp ; X86-NEXT: popl %ebp ; X86-NEXT: retl @@ -66,7 +69,7 @@ define double @fneg_strict_fadd_to_strict_fsub_d(double %x, double %y) nounwind ret double %add } -define double @fneg_strict_fadd_to_strict_fsub_2d(double %x, double %y) nounwind { +define double @fneg_strict_fadd_to_strict_fsub_2d(double %x, double %y) nounwind strictfp { ; X86-LABEL: fneg_strict_fadd_to_strict_fsub_2d: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -77,6 +80,7 @@ define double @fneg_strict_fadd_to_strict_fsub_2d(double %x, double %y) nounwind ; X86-NEXT: subsd 16(%ebp), %xmm0 ; X86-NEXT: movsd %xmm0, (%esp) ; X86-NEXT: fldl (%esp) +; X86-NEXT: wait ; X86-NEXT: movl %ebp, %esp ; X86-NEXT: popl %ebp ; X86-NEXT: retl diff --git a/llvm/test/CodeGen/X86/strict-fsub-combines.ll b/llvm/test/CodeGen/X86/strict-fsub-combines.ll index 8cb591a980e1..774ea02ccd87 100644 --- a/llvm/test/CodeGen/X86/strict-fsub-combines.ll +++ b/llvm/test/CodeGen/X86/strict-fsub-combines.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X64 ; FIXME: Missing fsub(x,fneg(y)) -> fadd(x,y) fold -define float @fneg_strict_fsub_to_strict_fadd(float %x, float %y) nounwind { +define float @fneg_strict_fsub_to_strict_fadd(float %x, float %y) nounwind strictfp { ; X86-LABEL: fneg_strict_fsub_to_strict_fadd: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -13,6 +13,7 @@ define float @fneg_strict_fsub_to_strict_fadd(float %x, float %y) nounwind { ; X86-NEXT: subss %xmm1, %xmm0 ; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: flds (%esp) +; X86-NEXT: wait ; X86-NEXT: popl %eax ; X86-NEXT: retl ; @@ -27,7 +28,7 @@ define float @fneg_strict_fsub_to_strict_fadd(float %x, float %y) nounwind { } ; FIXME: Missing fsub(x,fneg(y)) -> fadd(x,y) fold -define double @fneg_strict_fsub_to_strict_fadd_d(double %x, double %y) nounwind { +define double @fneg_strict_fsub_to_strict_fadd_d(double %x, double %y) nounwind strictfp { ; X86-LABEL: fneg_strict_fsub_to_strict_fadd_d: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -40,6 +41,7 @@ define double @fneg_strict_fsub_to_strict_fadd_d(double %x, double %y) nounwind ; X86-NEXT: subsd %xmm1, %xmm0 ; X86-NEXT: movsd %xmm0, (%esp) ; X86-NEXT: fldl (%esp) +; X86-NEXT: wait ; X86-NEXT: movl %ebp, %esp ; X86-NEXT: popl %ebp ; X86-NEXT: retl @@ -55,7 +57,7 @@ define double @fneg_strict_fsub_to_strict_fadd_d(double %x, double %y) nounwind } ; FIXME: Missing fneg(fsub(x,y)) -> fsub(y,x) fold -define float @strict_fsub_fneg_to_strict_fsub(float %x, float %y) nounwind { +define float @strict_fsub_fneg_to_strict_fsub(float %x, float %y) nounwind strictfp { ; X86-LABEL: strict_fsub_fneg_to_strict_fsub: ; X86: # %bb.0: ; X86-NEXT: pushl %eax @@ -64,6 +66,7 @@ define float @strict_fsub_fneg_to_strict_fsub(float %x, float %y) nounwind { ; X86-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: flds (%esp) +; X86-NEXT: wait ; X86-NEXT: popl %eax ; X86-NEXT: retl ; @@ -78,7 +81,7 @@ define float @strict_fsub_fneg_to_strict_fsub(float %x, float %y) nounwind { } ; FIXME: Missing fneg(fsub(x,y)) -> fsub(y,x) fold -define double @strict_fsub_fneg_to_strict_fsub_d(double %x, double %y) nounwind { +define double @strict_fsub_fneg_to_strict_fsub_d(double %x, double %y) nounwind strictfp { ; X86-LABEL: strict_fsub_fneg_to_strict_fsub_d: ; X86: # %bb.0: ; X86-NEXT: pushl %ebp @@ -90,6 +93,7 @@ define double @strict_fsub_fneg_to_strict_fsub_d(double %x, double %y) nounwind ; X86-NEXT: xorpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-NEXT: movlpd %xmm0, (%esp) ; X86-NEXT: fldl (%esp) +; X86-NEXT: wait ; X86-NEXT: movl %ebp, %esp ; X86-NEXT: popl %ebp ; X86-NEXT: retl -- GitLab From f46f6465062bd6ddc96e3838c50e1a0f85f92dd4 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Mon, 8 Apr 2024 15:46:03 +0100 Subject: [PATCH 155/695] [libclc] Fix spirv build dependencies These were accidentally broken in 61efea7. Thanks to @mgorny and @rjodinchr for spotting this. --- libclc/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt index 8750a65a717f..770f69a15a30 100644 --- a/libclc/CMakeLists.txt +++ b/libclc/CMakeLists.txt @@ -332,7 +332,7 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) if( ${ARCH} STREQUAL "spirv" OR ${ARCH} STREQUAL "spirv64" ) set( spv_suffix ${arch_suffix}.spv ) add_custom_command( OUTPUT "${spv_suffix}" - COMMAND ${LLVM_SPIRV} ${spvflags} -o "${spv_suffix}" ${builtins_opt_lib_tgt} + COMMAND ${LLVM_SPIRV} ${spvflags} -o "${spv_suffix}" ${builtins_link_lib_tgt} DEPENDS ${builtins_link_lib_tgt} ) add_custom_target( "prepare-${spv_suffix}" ALL DEPENDS "${spv_suffix}" ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${spv_suffix} -- GitLab From 4c718fdbeacfc3385a493349b66b61c857b8e772 Mon Sep 17 00:00:00 2001 From: Yusra Syeda <99052248+ysyeda@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:05:42 -0400 Subject: [PATCH 156/695] [SystemZ][z/OS] TXT records in the GOFF reader (#87648) This PR adds handling for TXT records in the GOFF reader. --------- Co-authored-by: Yusra Syeda --- llvm/include/llvm/Object/GOFF.h | 20 +++ llvm/include/llvm/Object/GOFFObjectFile.h | 56 +++++-- llvm/lib/Object/GOFFObjectFile.cpp | 167 +++++++++++++++++++ llvm/unittests/Object/GOFFObjectFileTest.cpp | 97 +++++++++++ 4 files changed, 326 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/Object/GOFF.h b/llvm/include/llvm/Object/GOFF.h index 91762457ae05..9fb8876e893d 100644 --- a/llvm/include/llvm/Object/GOFF.h +++ b/llvm/include/llvm/Object/GOFF.h @@ -73,6 +73,26 @@ protected: } }; +class TXTRecord : public Record { +public: + /// \brief Maximum length of data; any more must go in continuation. + static const uint8_t TXTMaxDataLength = 56; + + static Error getData(const uint8_t *Record, SmallString<256> &CompleteData); + + static void getElementEsdId(const uint8_t *Record, uint32_t &EsdId) { + get(Record, 4, EsdId); + } + + static void getOffset(const uint8_t *Record, uint32_t &Offset) { + get(Record, 12, Offset); + } + + static void getDataLength(const uint8_t *Record, uint16_t &Length) { + get(Record, 22, Length); + } +}; + class HDRRecord : public Record { public: static Error getData(const uint8_t *Record, SmallString<256> &CompleteData); diff --git a/llvm/include/llvm/Object/GOFFObjectFile.h b/llvm/include/llvm/Object/GOFFObjectFile.h index 7e1ceb95f667..6871641e97ec 100644 --- a/llvm/include/llvm/Object/GOFFObjectFile.h +++ b/llvm/include/llvm/Object/GOFFObjectFile.h @@ -29,7 +29,10 @@ namespace llvm { namespace object { class GOFFObjectFile : public ObjectFile { + friend class GOFFSymbolRef; + IndexedMap EsdPtrs; // Indexed by EsdId. + SmallVector TextPtrs; mutable DenseMap>> EsdNamesCache; @@ -38,7 +41,7 @@ class GOFFObjectFile : public ObjectFile { // (EDID, 0) code, r/o data section // (EDID,PRID) r/w data section SmallVector SectionList; - mutable DenseMap SectionDataCache; + mutable DenseMap> SectionDataCache; public: Expected getSymbolName(SymbolRef Symbol) const; @@ -66,6 +69,10 @@ public: return true; } + bool isSectionNoLoad(DataRefImpl Sec) const; + bool isSectionReadOnlyData(DataRefImpl Sec) const; + bool isSectionZeroInit(DataRefImpl Sec) const; + private: // SymbolRef. Expected getSymbolName(DataRefImpl Symb) const override; @@ -75,27 +82,24 @@ private: Expected getSymbolFlags(DataRefImpl Symb) const override; Expected getSymbolType(DataRefImpl Symb) const override; Expected getSymbolSection(DataRefImpl Symb) const override; + uint64_t getSymbolSize(DataRefImpl Symb) const; const uint8_t *getSymbolEsdRecord(DataRefImpl Symb) const; bool isSymbolUnresolved(DataRefImpl Symb) const; bool isSymbolIndirect(DataRefImpl Symb) const; // SectionRef. - void moveSectionNext(DataRefImpl &Sec) const override {} - virtual Expected getSectionName(DataRefImpl Sec) const override { - return StringRef(); - } - uint64_t getSectionAddress(DataRefImpl Sec) const override { return 0; } - uint64_t getSectionSize(DataRefImpl Sec) const override { return 0; } + void moveSectionNext(DataRefImpl &Sec) const override; + virtual Expected getSectionName(DataRefImpl Sec) const override; + uint64_t getSectionAddress(DataRefImpl Sec) const override; + uint64_t getSectionSize(DataRefImpl Sec) const override; virtual Expected> - getSectionContents(DataRefImpl Sec) const override { - return ArrayRef(); - } - uint64_t getSectionIndex(DataRefImpl Sec) const override { return 0; } - uint64_t getSectionAlignment(DataRefImpl Sec) const override { return 0; } + getSectionContents(DataRefImpl Sec) const override; + uint64_t getSectionIndex(DataRefImpl Sec) const override { return Sec.d.a; } + uint64_t getSectionAlignment(DataRefImpl Sec) const override; bool isSectionCompressed(DataRefImpl Sec) const override { return false; } - bool isSectionText(DataRefImpl Sec) const override { return false; } - bool isSectionData(DataRefImpl Sec) const override { return false; } + bool isSectionText(DataRefImpl Sec) const override; + bool isSectionData(DataRefImpl Sec) const override; bool isSectionBSS(DataRefImpl Sec) const override { return false; } bool isSectionVirtual(DataRefImpl Sec) const override { return false; } relocation_iterator section_rel_begin(DataRefImpl Sec) const override { @@ -109,6 +113,7 @@ private: const uint8_t *getSectionPrEsdRecord(DataRefImpl &Sec) const; const uint8_t *getSectionEdEsdRecord(uint32_t SectionIndex) const; const uint8_t *getSectionPrEsdRecord(uint32_t SectionIndex) const; + uint32_t getSectionDefEsdId(DataRefImpl &Sec) const; // RelocationRef. void moveRelocationNext(DataRefImpl &Rel) const override {} @@ -122,6 +127,29 @@ private: SmallVectorImpl &Result) const override {} }; +class GOFFSymbolRef : public SymbolRef { +public: + GOFFSymbolRef(const SymbolRef &B) : SymbolRef(B) { + assert(isa(SymbolRef::getObject())); + } + + const GOFFObjectFile *getObject() const { + return cast(BasicSymbolRef::getObject()); + } + + Expected getSymbolGOFFFlags() const { + return getObject()->getSymbolFlags(getRawDataRefImpl()); + } + + Expected getSymbolGOFFType() const { + return getObject()->getSymbolType(getRawDataRefImpl()); + } + + uint64_t getSize() const { + return getObject()->getSymbolSize(getRawDataRefImpl()); + } +}; + } // namespace object } // namespace llvm diff --git a/llvm/lib/Object/GOFFObjectFile.cpp b/llvm/lib/Object/GOFFObjectFile.cpp index d3dfd5d1540c..550aebfe0670 100644 --- a/llvm/lib/Object/GOFFObjectFile.cpp +++ b/llvm/lib/Object/GOFFObjectFile.cpp @@ -165,6 +165,11 @@ GOFFObjectFile::GOFFObjectFile(MemoryBufferRef Object, Error &Err) LLVM_DEBUG(dbgs() << " -- ESD " << EsdId << "\n"); break; } + case GOFF::RT_TXT: + // Save TXT records. + TextPtrs.emplace_back(I); + LLVM_DEBUG(dbgs() << " -- TXT\n"); + break; case GOFF::RT_END: LLVM_DEBUG(dbgs() << " -- END (GOFF record type) unhandled\n"); break; @@ -361,6 +366,13 @@ GOFFObjectFile::getSymbolSection(DataRefImpl Symb) const { std::to_string(SymEdId)); } +uint64_t GOFFObjectFile::getSymbolSize(DataRefImpl Symb) const { + const uint8_t *Record = getSymbolEsdRecord(Symb); + uint32_t Length; + ESDRecord::getLength(Record, Length); + return Length; +} + const uint8_t *GOFFObjectFile::getSectionEdEsdRecord(DataRefImpl &Sec) const { SectionEntryImpl EsdIds = SectionList[Sec.d.a]; const uint8_t *EsdRecord = EsdPtrs[EsdIds.d.a]; @@ -391,6 +403,154 @@ GOFFObjectFile::getSectionPrEsdRecord(uint32_t SectionIndex) const { return EsdRecord; } +uint32_t GOFFObjectFile::getSectionDefEsdId(DataRefImpl &Sec) const { + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + uint32_t Length; + ESDRecord::getLength(EsdRecord, Length); + if (Length == 0) { + const uint8_t *PrEsdRecord = getSectionPrEsdRecord(Sec); + if (PrEsdRecord) + EsdRecord = PrEsdRecord; + } + + uint32_t DefEsdId; + ESDRecord::getEsdId(EsdRecord, DefEsdId); + LLVM_DEBUG(dbgs() << "Got def EsdId: " << DefEsdId << '\n'); + return DefEsdId; +} + +void GOFFObjectFile::moveSectionNext(DataRefImpl &Sec) const { + Sec.d.a++; + if ((Sec.d.a) >= SectionList.size()) + Sec.d.a = 0; +} + +Expected GOFFObjectFile::getSectionName(DataRefImpl Sec) const { + DataRefImpl EdSym; + SectionEntryImpl EsdIds = SectionList[Sec.d.a]; + EdSym.d.a = EsdIds.d.a; + Expected Name = getSymbolName(EdSym); + if (Name) { + StringRef Res = *Name; + LLVM_DEBUG(dbgs() << "Got section: " << Res << '\n'); + LLVM_DEBUG(dbgs() << "Final section name: " << Res << '\n'); + Name = Res; + } + return Name; +} + +uint64_t GOFFObjectFile::getSectionAddress(DataRefImpl Sec) const { + uint32_t Offset; + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + ESDRecord::getOffset(EsdRecord, Offset); + return Offset; +} + +uint64_t GOFFObjectFile::getSectionSize(DataRefImpl Sec) const { + uint32_t Length; + uint32_t DefEsdId = getSectionDefEsdId(Sec); + const uint8_t *EsdRecord = EsdPtrs[DefEsdId]; + ESDRecord::getLength(EsdRecord, Length); + LLVM_DEBUG(dbgs() << "Got section size: " << Length << '\n'); + return static_cast(Length); +} + +// Unravel TXT records and expand fill characters to produce +// a contiguous sequence of bytes. +Expected> +GOFFObjectFile::getSectionContents(DataRefImpl Sec) const { + if (SectionDataCache.count(Sec.d.a)) { + auto &Buf = SectionDataCache[Sec.d.a]; + return ArrayRef(Buf); + } + uint64_t SectionSize = getSectionSize(Sec); + uint32_t DefEsdId = getSectionDefEsdId(Sec); + + const uint8_t *EdEsdRecord = getSectionEdEsdRecord(Sec); + bool FillBytePresent; + ESDRecord::getFillBytePresent(EdEsdRecord, FillBytePresent); + uint8_t FillByte = '\0'; + if (FillBytePresent) + ESDRecord::getFillByteValue(EdEsdRecord, FillByte); + + // Initialize section with fill byte. + SmallVector Data(SectionSize, FillByte); + + // Replace section with content from text records. + for (const uint8_t *TxtRecordInt : TextPtrs) { + const uint8_t *TxtRecordPtr = TxtRecordInt; + uint32_t TxtEsdId; + TXTRecord::getElementEsdId(TxtRecordPtr, TxtEsdId); + LLVM_DEBUG(dbgs() << "Got txt EsdId: " << TxtEsdId << '\n'); + + if (TxtEsdId != DefEsdId) + continue; + + uint32_t TxtDataOffset; + TXTRecord::getOffset(TxtRecordPtr, TxtDataOffset); + + uint16_t TxtDataSize; + TXTRecord::getDataLength(TxtRecordPtr, TxtDataSize); + + LLVM_DEBUG(dbgs() << "Record offset " << TxtDataOffset << ", data size " + << TxtDataSize << "\n"); + + SmallString<256> CompleteData; + CompleteData.reserve(TxtDataSize); + if (Error Err = TXTRecord::getData(TxtRecordPtr, CompleteData)) + return std::move(Err); + assert(CompleteData.size() == TxtDataSize && "Wrong length of data"); + std::copy(CompleteData.data(), CompleteData.data() + TxtDataSize, + Data.begin() + TxtDataOffset); + } + SectionDataCache[Sec.d.a] = Data; + return ArrayRef(SectionDataCache[Sec.d.a]); +} + +uint64_t GOFFObjectFile::getSectionAlignment(DataRefImpl Sec) const { + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + GOFF::ESDAlignment Pow2Alignment; + ESDRecord::getAlignment(EsdRecord, Pow2Alignment); + return 1 << static_cast(Pow2Alignment); +} + +bool GOFFObjectFile::isSectionText(DataRefImpl Sec) const { + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + GOFF::ESDExecutable Executable; + ESDRecord::getExecutable(EsdRecord, Executable); + return Executable == GOFF::ESD_EXE_CODE; +} + +bool GOFFObjectFile::isSectionData(DataRefImpl Sec) const { + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + GOFF::ESDExecutable Executable; + ESDRecord::getExecutable(EsdRecord, Executable); + return Executable == GOFF::ESD_EXE_DATA; +} + +bool GOFFObjectFile::isSectionNoLoad(DataRefImpl Sec) const { + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + GOFF::ESDLoadingBehavior LoadingBehavior; + ESDRecord::getLoadingBehavior(EsdRecord, LoadingBehavior); + return LoadingBehavior == GOFF::ESD_LB_NoLoad; +} + +bool GOFFObjectFile::isSectionReadOnlyData(DataRefImpl Sec) const { + if (!isSectionData(Sec)) + return false; + + const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); + GOFF::ESDLoadingBehavior LoadingBehavior; + ESDRecord::getLoadingBehavior(EsdRecord, LoadingBehavior); + return LoadingBehavior == GOFF::ESD_LB_Initial; +} + +bool GOFFObjectFile::isSectionZeroInit(DataRefImpl Sec) const { + // GOFF uses fill characters and fill characters are applied + // on getSectionContents() - so we say false to zero init. + return false; +} + section_iterator GOFFObjectFile::section_begin() const { DataRefImpl Sec; moveSectionNext(Sec); @@ -473,6 +633,13 @@ Error ESDRecord::getData(const uint8_t *Record, return getContinuousData(Record, DataSize, 72, CompleteData); } +Error TXTRecord::getData(const uint8_t *Record, + SmallString<256> &CompleteData) { + uint16_t Length; + getDataLength(Record, Length); + return getContinuousData(Record, Length, 24, CompleteData); +} + Error ENDRecord::getData(const uint8_t *Record, SmallString<256> &CompleteData) { uint16_t Length = getNameLength(Record); diff --git a/llvm/unittests/Object/GOFFObjectFileTest.cpp b/llvm/unittests/Object/GOFFObjectFileTest.cpp index 734dac6b8507..69f60d016a80 100644 --- a/llvm/unittests/Object/GOFFObjectFileTest.cpp +++ b/llvm/unittests/Object/GOFFObjectFileTest.cpp @@ -502,3 +502,100 @@ TEST(GOFFObjectFileTest, InvalidERSymbolType) { FailedWithMessage("ESD record 1 has unknown Executable type 0x03")); } } + +TEST(GOFFObjectFileTest, TXTConstruct) { + char GOFFData[GOFF::RecordLength * 6] = {}; + + // HDR record. + GOFFData[0] = 0x03; + GOFFData[1] = 0xF0; + GOFFData[50] = 0x01; + + // ESD record. + GOFFData[GOFF::RecordLength] = 0x03; + GOFFData[GOFF::RecordLength + 7] = 0x01; // ESDID. + GOFFData[GOFF::RecordLength + 71] = 0x05; // Size of symbol name. + GOFFData[GOFF::RecordLength + 72] = 0xa5; // Symbol name is v. + GOFFData[GOFF::RecordLength + 73] = 0x81; // Symbol name is a. + GOFFData[GOFF::RecordLength + 74] = 0x99; // Symbol name is r. + GOFFData[GOFF::RecordLength + 75] = 0x7b; // Symbol name is #. + GOFFData[GOFF::RecordLength + 76] = 0x83; // Symbol name is c. + + // ESD record. + GOFFData[GOFF::RecordLength * 2] = 0x03; + GOFFData[GOFF::RecordLength * 2 + 3] = 0x01; + GOFFData[GOFF::RecordLength * 2 + 7] = 0x02; // ESDID. + GOFFData[GOFF::RecordLength * 2 + 11] = 0x01; // Parent ESDID. + GOFFData[GOFF::RecordLength * 2 + 27] = 0x08; // Length. + GOFFData[GOFF::RecordLength * 2 + 40] = 0x01; // Name Space ID. + GOFFData[GOFF::RecordLength * 2 + 41] = 0x80; + GOFFData[GOFF::RecordLength * 2 + 60] = 0x04; // Size of symbol name. + GOFFData[GOFF::RecordLength * 2 + 61] = 0x04; // Size of symbol name. + GOFFData[GOFF::RecordLength * 2 + 63] = 0x0a; // Size of symbol name. + GOFFData[GOFF::RecordLength * 2 + 66] = 0x03; // Size of symbol name. + GOFFData[GOFF::RecordLength * 2 + 71] = 0x08; // Size of symbol name. + GOFFData[GOFF::RecordLength * 2 + 72] = 0xc3; // Symbol name is c. + GOFFData[GOFF::RecordLength * 2 + 73] = 0x6d; // Symbol name is _. + GOFFData[GOFF::RecordLength * 2 + 74] = 0xc3; // Symbol name is c. + GOFFData[GOFF::RecordLength * 2 + 75] = 0xd6; // Symbol name is o. + GOFFData[GOFF::RecordLength * 2 + 76] = 0xc4; // Symbol name is D. + GOFFData[GOFF::RecordLength * 2 + 77] = 0xc5; // Symbol name is E. + GOFFData[GOFF::RecordLength * 2 + 78] = 0xf6; // Symbol name is 6. + GOFFData[GOFF::RecordLength * 2 + 79] = 0xf4; // Symbol name is 4. + + // ESD record. + GOFFData[GOFF::RecordLength * 3] = 0x03; + GOFFData[GOFF::RecordLength * 3 + 3] = 0x02; + GOFFData[GOFF::RecordLength * 3 + 7] = 0x03; // ESDID. + GOFFData[GOFF::RecordLength * 3 + 11] = 0x02; // Parent ESDID. + GOFFData[GOFF::RecordLength * 3 + 71] = 0x05; // Size of symbol name. + GOFFData[GOFF::RecordLength * 3 + 72] = 0xa5; // Symbol name is v. + GOFFData[GOFF::RecordLength * 3 + 73] = 0x81; // Symbol name is a. + GOFFData[GOFF::RecordLength * 3 + 74] = 0x99; // Symbol name is r. + GOFFData[GOFF::RecordLength * 3 + 75] = 0x7b; // Symbol name is #. + GOFFData[GOFF::RecordLength * 3 + 76] = 0x83; // Symbol name is c. + + // TXT record. + GOFFData[GOFF::RecordLength * 4] = 0x03; + GOFFData[GOFF::RecordLength * 4 + 1] = 0x10; + GOFFData[GOFF::RecordLength * 4 + 7] = 0x02; + GOFFData[GOFF::RecordLength * 4 + 23] = 0x08; // Data Length. + GOFFData[GOFF::RecordLength * 4 + 24] = 0x12; + GOFFData[GOFF::RecordLength * 4 + 25] = 0x34; + GOFFData[GOFF::RecordLength * 4 + 26] = 0x56; + GOFFData[GOFF::RecordLength * 4 + 27] = 0x78; + GOFFData[GOFF::RecordLength * 4 + 28] = 0x9a; + GOFFData[GOFF::RecordLength * 4 + 29] = 0xbc; + GOFFData[GOFF::RecordLength * 4 + 30] = 0xde; + GOFFData[GOFF::RecordLength * 4 + 31] = 0xf0; + + // END record. + GOFFData[GOFF::RecordLength * 5] = 0x03; + GOFFData[GOFF::RecordLength * 5 + 1] = 0x40; + GOFFData[GOFF::RecordLength * 5 + 11] = 0x06; + + StringRef Data(GOFFData, GOFF::RecordLength * 6); + + Expected> GOFFObjOrErr = + object::ObjectFile::createGOFFObjectFile( + MemoryBufferRef(Data, "dummyGOFF")); + + ASSERT_THAT_EXPECTED(GOFFObjOrErr, Succeeded()); + + GOFFObjectFile *GOFFObj = dyn_cast((*GOFFObjOrErr).get()); + auto Symbols = GOFFObj->symbols(); + ASSERT_EQ(std::distance(Symbols.begin(), Symbols.end()), 1); + SymbolRef Symbol = *Symbols.begin(); + Expected SymbolNameOrErr = GOFFObj->getSymbolName(Symbol); + ASSERT_THAT_EXPECTED(SymbolNameOrErr, Succeeded()); + StringRef SymbolName = SymbolNameOrErr.get(); + EXPECT_EQ(SymbolName, "var#c"); + + auto Sections = GOFFObj->sections(); + ASSERT_EQ(std::distance(Sections.begin(), Sections.end()), 1); + SectionRef Section = *Sections.begin(); + Expected SectionContent = Section.getContents(); + ASSERT_THAT_EXPECTED(SectionContent, Succeeded()); + StringRef Contents = SectionContent.get(); + EXPECT_EQ(Contents, "\x12\x34\x56\x78\x9a\xbc\xde\xf0"); +} -- GitLab From 1107b47dcd145518c7b811bf10e2b848782b0478 Mon Sep 17 00:00:00 2001 From: Edwin Vane Date: Mon, 8 Apr 2024 11:22:19 -0400 Subject: [PATCH 157/695] [clang-tidy] rename designated initializers (#86976) readability-identifier-naming now supports renaming designated initializers. --- .../utils/RenamerClangTidyCheck.cpp | 22 ++++++++++++++++--- clang-tools-extra/docs/ReleaseNotes.rst | 3 ++- .../readability/identifier-naming.cpp | 10 +++++++++ 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp index da1433aa2d05..69b7d40ef628 100644 --- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp +++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp @@ -31,13 +31,12 @@ struct DenseMapInfo { using NamingCheckId = clang::tidy::RenamerClangTidyCheck::NamingCheckId; static inline NamingCheckId getEmptyKey() { - return {DenseMapInfo::getEmptyKey(), - "EMPTY"}; + return {DenseMapInfo::getEmptyKey(), "EMPTY"}; } static inline NamingCheckId getTombstoneKey() { return {DenseMapInfo::getTombstoneKey(), - "TOMBSTONE"}; + "TOMBSTONE"}; } static unsigned getHashValue(NamingCheckId Val) { @@ -367,6 +366,23 @@ public: return true; } + bool VisitDesignatedInitExpr(DesignatedInitExpr *Expr) { + for (const DesignatedInitExpr::Designator &D : Expr->designators()) { + if (!D.isFieldDesignator()) + continue; + const FieldDecl *FD = D.getFieldDecl(); + if (!FD) + continue; + const IdentifierInfo *II = FD->getIdentifier(); + if (!II) + continue; + SourceRange FixLocation{D.getFieldLoc(), D.getFieldLoc()}; + Check->addUsage(FD, FixLocation, SM); + } + + return true; + } + private: RenamerClangTidyCheck *Check; const SourceManager *SM; diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 2babb1406b97..bdd53f06e7e2 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -266,7 +266,8 @@ Changes in existing checks - Improved :doc:`readability-identifier-naming ` check in `GetConfigPerFile` mode by resolving symbolic links to header files. Fixed handling of Hungarian - Prefix when configured to `LowerCase`. + Prefix when configured to `LowerCase`. Added support for renaming designated + initializers. - Improved :doc:`readability-implicit-bool-conversion ` check to provide diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp index d2e89a7c9855..57ef4aae5ddb 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp @@ -766,3 +766,13 @@ STATIC_MACRO void someFunc(MyFunPtr, const MyFunPtr****) {} // CHECK-FIXES: {{^}}STATIC_MACRO void someFunc(my_fun_ptr_t, const my_fun_ptr_t****) {} #undef STATIC_MACRO } + +struct Some_struct { + int SomeMember; +// CHECK-MESSAGES: :[[@LINE-1]]:7: warning: invalid case style for public member 'SomeMember' [readability-identifier-naming] +// CHECK-FIXES: {{^}} int some_member; +}; +Some_struct g_s1{ .SomeMember = 1 }; +// CHECK-FIXES: {{^}}Some_struct g_s1{ .some_member = 1 }; +Some_struct g_s2{.SomeMember=1}; +// CHECK-FIXES: {{^}}Some_struct g_s2{.some_member=1}; -- GitLab From 312b9297bb9284bddb36980f64661c24c876eef0 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:31:07 -0400 Subject: [PATCH 158/695] [libc] Increase timeout for death tests. (#87959) Fix test timeout on RISCV bots. Fixes https://github.com/llvm/llvm-project/issues/87096 --- libc/test/UnitTest/LibcDeathTestExecutors.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libc/test/UnitTest/LibcDeathTestExecutors.cpp b/libc/test/UnitTest/LibcDeathTestExecutors.cpp index e891c4e3c0b5..fa6d16410bb7 100644 --- a/libc/test/UnitTest/LibcDeathTestExecutors.cpp +++ b/libc/test/UnitTest/LibcDeathTestExecutors.cpp @@ -19,7 +19,7 @@ namespace testing { bool Test::testProcessKilled(testutils::FunctionCaller *Func, int Signal, const char *LHSStr, const char *RHSStr, internal::Location Loc) { - testutils::ProcessStatus Result = testutils::invoke_in_subprocess(Func, 500); + testutils::ProcessStatus Result = testutils::invoke_in_subprocess(Func, 1000); if (const char *error = Result.get_error()) { Ctx->markFail(); @@ -31,7 +31,7 @@ bool Test::testProcessKilled(testutils::FunctionCaller *Func, int Signal, if (Result.timed_out()) { Ctx->markFail(); tlog << Loc; - tlog << "Process timed out after " << 500 << " milliseconds.\n"; + tlog << "Process timed out after " << 1000 << " milliseconds.\n"; return false; } @@ -62,7 +62,7 @@ bool Test::testProcessKilled(testutils::FunctionCaller *Func, int Signal, bool Test::testProcessExits(testutils::FunctionCaller *Func, int ExitCode, const char *LHSStr, const char *RHSStr, internal::Location Loc) { - testutils::ProcessStatus Result = testutils::invoke_in_subprocess(Func, 500); + testutils::ProcessStatus Result = testutils::invoke_in_subprocess(Func, 1000); if (const char *error = Result.get_error()) { Ctx->markFail(); @@ -74,7 +74,7 @@ bool Test::testProcessExits(testutils::FunctionCaller *Func, int ExitCode, if (Result.timed_out()) { Ctx->markFail(); tlog << Loc; - tlog << "Process timed out after " << 500 << " milliseconds.\n"; + tlog << "Process timed out after " << 1000 << " milliseconds.\n"; return false; } -- GitLab From ed1b24bf8b76871ab00f365d8dc066b3f7f76202 Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Mon, 8 Apr 2024 08:32:03 -0700 Subject: [PATCH 159/695] [flang][runtime] Added simplified std::toupper implementation. (#87850) --- .../flang/Runtime/freestanding-tools.h | 19 +++++++++++++++++++ flang/lib/Decimal/decimal-to-binary.cpp | 16 ++++++++-------- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/flang/include/flang/Runtime/freestanding-tools.h b/flang/include/flang/Runtime/freestanding-tools.h index 7f8d37d87e0e..e94cb0a6c938 100644 --- a/flang/include/flang/Runtime/freestanding-tools.h +++ b/flang/include/flang/Runtime/freestanding-tools.h @@ -12,6 +12,7 @@ #include "flang/Common/api-attrs.h" #include "flang/Runtime/c-or-cpp.h" #include +#include #include // The file defines a set of utilities/classes that might be @@ -57,6 +58,11 @@ #define STD_STRCMP_UNSUPPORTED 1 #endif +#if !defined(STD_TOUPPER_UNSUPPORTED) && \ + (defined(__CUDACC__) || defined(__CUDA__)) && defined(__CUDA_ARCH__) +#define STD_TOUPPER_UNSUPPORTED 1 +#endif + namespace Fortran::runtime { #if STD_FILL_N_UNSUPPORTED @@ -195,5 +201,18 @@ static inline RT_API_ATTRS int strcmp(const char *lhs, const char *rhs) { using std::strcmp; #endif // !STD_STRCMP_UNSUPPORTED +#if STD_TOUPPER_UNSUPPORTED +// Provides alternative implementation for std::toupper(), if +// it is not supported. +static inline RT_API_ATTRS int toupper(int ch) { + if (ch >= 'a' && ch <= 'z') { + return ch - 'a' + 'A'; + } + return ch; +} +#else // !STD_TOUPPER_UNSUPPORTED +using std::toupper; +#endif // !STD_TOUPPER_UNSUPPORTED + } // namespace Fortran::runtime #endif // FORTRAN_RUNTIME_FREESTANDING_TOOLS_H_ diff --git a/flang/lib/Decimal/decimal-to-binary.cpp b/flang/lib/Decimal/decimal-to-binary.cpp index dc4aa82ac6fe..eebd0736b67a 100644 --- a/flang/lib/Decimal/decimal-to-binary.cpp +++ b/flang/lib/Decimal/decimal-to-binary.cpp @@ -11,9 +11,9 @@ #include "flang/Common/leading-zero-bit-count.h" #include "flang/Decimal/binary-floating-point.h" #include "flang/Decimal/decimal.h" +#include "flang/Runtime/freestanding-tools.h" #include #include -#include #include namespace Fortran::decimal { @@ -468,8 +468,8 @@ BigRadixFloatingPointNumber::ConvertToBinary( ++q; } } - if ((!limit || limit >= q + 3) && toupper(q[0]) == 'N' && - toupper(q[1]) == 'A' && toupper(q[2]) == 'N') { + if ((!limit || limit >= q + 3) && runtime::toupper(q[0]) == 'N' && + runtime::toupper(q[1]) == 'A' && runtime::toupper(q[2]) == 'N') { // NaN p = q + 3; bool isQuiet{true}; @@ -493,11 +493,11 @@ BigRadixFloatingPointNumber::ConvertToBinary( } return {Real{NaN(isQuiet)}}; } else { // Inf? - if ((!limit || limit >= q + 3) && toupper(q[0]) == 'I' && - toupper(q[1]) == 'N' && toupper(q[2]) == 'F') { - if ((!limit || limit >= q + 8) && toupper(q[3]) == 'I' && - toupper(q[4]) == 'N' && toupper(q[5]) == 'I' && - toupper(q[6]) == 'T' && toupper(q[7]) == 'Y') { + if ((!limit || limit >= q + 3) && runtime::toupper(q[0]) == 'I' && + runtime::toupper(q[1]) == 'N' && runtime::toupper(q[2]) == 'F') { + if ((!limit || limit >= q + 8) && runtime::toupper(q[3]) == 'I' && + runtime::toupper(q[4]) == 'N' && runtime::toupper(q[5]) == 'I' && + runtime::toupper(q[6]) == 'T' && runtime::toupper(q[7]) == 'Y') { p = q + 8; } else { p = q + 3; -- GitLab From 4a1c53f9fabbc18d436dcd4d5b572b82656fbbf9 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Fri, 5 Apr 2024 14:29:26 -0400 Subject: [PATCH 160/695] [SLP]Improve minbitwidth analysis for abs/smin/smax/umin/umax intrinsics. https://alive2.llvm.org/ce/z/ivPZ26 for the abs transformations. Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/86135 --- .../Transforms/Vectorize/SLPVectorizer.cpp | 119 +++++++++++++++--- .../X86/call-arg-reduced-by-minbitwidth.ll | 4 +- .../cmp-after-intrinsic-call-minbitwidth.ll | 12 +- .../X86/store-abs-minbitwidth.ll | 9 +- 4 files changed, 117 insertions(+), 27 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 6a662b2791bd..b41229e25a34 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -7056,19 +7056,16 @@ bool BoUpSLP::areAllUsersVectorized( static std::pair getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, - TargetTransformInfo *TTI, TargetLibraryInfo *TLI) { + TargetTransformInfo *TTI, TargetLibraryInfo *TLI, + ArrayRef ArgTys) { Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); // Calculate the cost of the scalar and vector calls. - SmallVector VecTys; - for (Use &Arg : CI->args()) - VecTys.push_back( - FixedVectorType::get(Arg->getType(), VecTy->getNumElements())); FastMathFlags FMF; if (auto *FPCI = dyn_cast(CI)) FMF = FPCI->getFastMathFlags(); SmallVector Arguments(CI->args()); - IntrinsicCostAttributes CostAttrs(ID, VecTy, Arguments, VecTys, FMF, + IntrinsicCostAttributes CostAttrs(ID, VecTy, Arguments, ArgTys, FMF, dyn_cast(CI)); auto IntrinsicCost = TTI->getIntrinsicInstrCost(CostAttrs, TTI::TCK_RecipThroughput); @@ -7081,8 +7078,8 @@ getVectorCallCosts(CallInst *CI, FixedVectorType *VecTy, if (!CI->isNoBuiltin() && VecFunc) { // Calculate the cost of the vector library call. // If the corresponding vector call is cheaper, return its cost. - LibCost = TTI->getCallInstrCost(nullptr, VecTy, VecTys, - TTI::TCK_RecipThroughput); + LibCost = + TTI->getCallInstrCost(nullptr, VecTy, ArgTys, TTI::TCK_RecipThroughput); } return {IntrinsicCost, LibCost}; } @@ -8508,6 +8505,30 @@ TTI::CastContextHint BoUpSLP::getCastContextHint(const TreeEntry &TE) const { return TTI::CastContextHint::None; } +/// Builds the arguments types vector for the given call instruction with the +/// given \p ID for the specified vector factor. +static SmallVector buildIntrinsicArgTypes(const CallInst *CI, + const Intrinsic::ID ID, + const unsigned VF, + unsigned MinBW) { + SmallVector ArgTys; + for (auto [Idx, Arg] : enumerate(CI->args())) { + if (ID != Intrinsic::not_intrinsic) { + if (isVectorIntrinsicWithScalarOpAtArg(ID, Idx)) { + ArgTys.push_back(Arg->getType()); + continue; + } + if (MinBW > 0) { + ArgTys.push_back(FixedVectorType::get( + IntegerType::get(CI->getContext(), MinBW), VF)); + continue; + } + } + ArgTys.push_back(FixedVectorType::get(Arg->getType(), VF)); + } + return ArgTys; +} + InstructionCost BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, SmallPtrSetImpl &CheckedExtracts) { @@ -9074,7 +9095,11 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, }; auto GetVectorCost = [=](InstructionCost CommonCost) { auto *CI = cast(VL0); - auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI); + Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); + SmallVector ArgTys = + buildIntrinsicArgTypes(CI, ID, VecTy->getNumElements(), + It != MinBWs.end() ? It->second.first : 0); + auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI, ArgTys); return std::min(VecCallCosts.first, VecCallCosts.second) + CommonCost; }; return GetCostDiff(GetScalarCost, GetVectorCost); @@ -12548,7 +12573,10 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { Intrinsic::ID ID = getVectorIntrinsicIDForCall(CI, TLI); - auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI); + SmallVector ArgTys = + buildIntrinsicArgTypes(CI, ID, VecTy->getNumElements(), + It != MinBWs.end() ? It->second.first : 0); + auto VecCallCosts = getVectorCallCosts(CI, VecTy, TTI, TLI, ArgTys); bool UseIntrinsic = ID != Intrinsic::not_intrinsic && VecCallCosts.first <= VecCallCosts.second; @@ -12557,8 +12585,7 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { SmallVector TysForDecl; // Add return type if intrinsic is overloaded on it. if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1)) - TysForDecl.push_back( - FixedVectorType::get(CI->getType(), E->Scalars.size())); + TysForDecl.push_back(VecTy); auto *CEI = cast(VL0); for (unsigned I : seq(0, CI->arg_size())) { ValueList OpVL; @@ -12566,7 +12593,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { // vectorized. if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) { ScalarArg = CEI->getArgOperand(I); - OpVecs.push_back(CEI->getArgOperand(I)); + // if decided to reduce bitwidth of abs intrinsic, it second argument + // must be set false (do not return poison, if value issigned min). + if (ID == Intrinsic::abs && It != MinBWs.end() && + It->second.first < DL->getTypeSizeInBits(CEI->getType())) + ScalarArg = Builder.getFalse(); + OpVecs.push_back(ScalarArg); if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I)) TysForDecl.push_back(ScalarArg->getType()); continue; @@ -12579,10 +12611,13 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { } ScalarArg = CEI->getArgOperand(I); if (cast(OpVec->getType())->getElementType() != - ScalarArg->getType()) { + ScalarArg->getType() && + It == MinBWs.end()) { auto *CastTy = FixedVectorType::get(ScalarArg->getType(), VecTy->getNumElements()); OpVec = Builder.CreateIntCast(OpVec, CastTy, GetOperandSignedness(I)); + } else if (It != MinBWs.end()) { + OpVec = Builder.CreateIntCast(OpVec, VecTy, GetOperandSignedness(I)); } LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n"); OpVecs.push_back(OpVec); @@ -14326,6 +14361,62 @@ bool BoUpSLP::collectValuesToDemote( return TryProcessInstruction(I, *ITE, BitWidth, Ops); } + case Instruction::Call: { + auto *IC = dyn_cast(I); + if (!IC) + break; + Intrinsic::ID ID = getVectorIntrinsicIDForCall(IC, TLI); + if (ID != Intrinsic::abs && ID != Intrinsic::smin && + ID != Intrinsic::smax && ID != Intrinsic::umin && ID != Intrinsic::umax) + break; + SmallVector Operands(1, I->getOperand(0)); + function_ref CallChecker; + auto CompChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) { + assert(BitWidth <= OrigBitWidth && "Unexpected bitwidths!"); + if (ID == Intrinsic::umin || ID == Intrinsic::umax) { + APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); + return MaskedValueIsZero(I->getOperand(0), Mask, SimplifyQuery(*DL)) && + MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)); + } + assert((ID == Intrinsic::smin || ID == Intrinsic::smax) && + "Expected min/max intrinsics only."); + unsigned SignBits = OrigBitWidth - BitWidth; + return SignBits <= ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, + nullptr, DT) && + SignBits <= + ComputeNumSignBits(I->getOperand(1), *DL, 0, AC, nullptr, DT); + }; + End = 1; + if (ID != Intrinsic::abs) { + Operands.push_back(I->getOperand(1)); + End = 2; + CallChecker = CompChecker; + } + InstructionCost BestCost = + std::numeric_limits::max(); + unsigned BestBitWidth = BitWidth; + unsigned VF = ITE->Scalars.size(); + // Choose the best bitwidth based on cost estimations. + auto Checker = [&](unsigned BitWidth, unsigned) { + unsigned MinBW = PowerOf2Ceil(BitWidth); + SmallVector ArgTys = buildIntrinsicArgTypes(IC, ID, VF, MinBW); + auto VecCallCosts = getVectorCallCosts( + IC, + FixedVectorType::get(IntegerType::get(IC->getContext(), MinBW), VF), + TTI, TLI, ArgTys); + InstructionCost Cost = std::min(VecCallCosts.first, VecCallCosts.second); + if (Cost < BestCost) { + BestCost = Cost; + BestBitWidth = BitWidth; + } + return false; + }; + [[maybe_unused]] bool NeedToExit; + (void)AttemptCheckBitwidth(Checker, NeedToExit); + BitWidth = BestBitWidth; + return TryProcessInstruction(I, *ITE, BitWidth, Operands, CallChecker); + } + // Otherwise, conservatively give up. default: break; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll index 27c9655f94d3..82966124d3ba 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/call-arg-reduced-by-minbitwidth.ll @@ -11,9 +11,7 @@ define void @test(ptr %0, i8 %1, i1 %cmp12.i) { ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x i8> [[TMP4]], <8 x i8> poison, <8 x i32> zeroinitializer ; CHECK-NEXT: br label [[PRE:%.*]] ; CHECK: pre: -; CHECK-NEXT: [[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i32> -; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i32> @llvm.umax.v8i32(<8 x i32> [[TMP6]], <8 x i32> ) -; CHECK-NEXT: [[TMP8:%.*]] = trunc <8 x i32> [[TMP7]] to <8 x i8> +; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i8> @llvm.umax.v8i8(<8 x i8> [[TMP5]], <8 x i8> ) ; CHECK-NEXT: [[TMP9:%.*]] = add <8 x i8> [[TMP8]], ; CHECK-NEXT: [[TMP10:%.*]] = select <8 x i1> [[TMP3]], <8 x i8> [[TMP9]], <8 x i8> [[TMP5]] ; CHECK-NEXT: store <8 x i8> [[TMP10]], ptr [[TMP0]], align 1 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll index a05d4fdd6315..9fa88084aaa0 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp-after-intrinsic-call-minbitwidth.ll @@ -5,12 +5,14 @@ define void @test() { ; CHECK-LABEL: define void @test( ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.smin.v2i32(<2 x i32> zeroinitializer, <2 x i32> zeroinitializer) -; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i32> zeroinitializer, <2 x i32> [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i32> [[TMP1]], zeroinitializer -; CHECK-NEXT: [[ADD:%.*]] = extractelement <2 x i32> [[TMP2]], i32 1 +; CHECK-NEXT: [[TMP0:%.*]] = call <2 x i2> @llvm.smin.v2i2(<2 x i2> zeroinitializer, <2 x i2> zeroinitializer) +; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> zeroinitializer, <2 x i2> zeroinitializer, <2 x i2> [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i2> [[TMP1]], zeroinitializer +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i2> [[TMP2]], i32 1 +; CHECK-NEXT: [[ADD:%.*]] = zext i2 [[TMP3]] to i32 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[ADD]], 0 -; CHECK-NEXT: [[ADD45:%.*]] = extractelement <2 x i32> [[TMP2]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i2> [[TMP2]], i32 0 +; CHECK-NEXT: [[ADD45:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[ADD152:%.*]] = or i32 [[ADD45]], [[ADD]] ; CHECK-NEXT: [[IDXPROM153:%.*]] = sext i32 [[ADD152]] to i64 ; CHECK-NEXT: [[ARRAYIDX154:%.*]] = getelementptr i8, ptr null, i64 [[IDXPROM153]] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll index e8b854b7cea6..df7312e3d2b5 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/store-abs-minbitwidth.ll @@ -13,14 +13,13 @@ define i32 @test(ptr noalias %in, ptr noalias %inn, ptr %out) { ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i8> [[TMP3]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i8> [[TMP2]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i8> [[TMP5]], <4 x i8> [[TMP6]], <4 x i32> -; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i32> +; CHECK-NEXT: [[TMP8:%.*]] = sext <4 x i8> [[TMP7]] to <4 x i16> ; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i8> [[TMP4]], <2 x i8> poison, <4 x i32> ; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x i8> [[TMP9]], <4 x i8> [[TMP10]], <4 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i32> -; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i32> [[TMP12]], [[TMP8]] -; CHECK-NEXT: [[TMP14:%.*]] = call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP13]], i1 true) -; CHECK-NEXT: [[TMP15:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16> +; CHECK-NEXT: [[TMP12:%.*]] = sext <4 x i8> [[TMP11]] to <4 x i16> +; CHECK-NEXT: [[TMP13:%.*]] = sub <4 x i16> [[TMP12]], [[TMP8]] +; CHECK-NEXT: [[TMP15:%.*]] = call <4 x i16> @llvm.abs.v4i16(<4 x i16> [[TMP13]], i1 false) ; CHECK-NEXT: store <4 x i16> [[TMP15]], ptr [[OUT:%.*]], align 2 ; CHECK-NEXT: ret i32 undef ; -- GitLab From b439140e2982dd77ef28a9069e16ae77bbe2bc5a Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Mon, 8 Apr 2024 16:51:30 +0100 Subject: [PATCH 161/695] [libclc] Fix more spirv build dependencies The last fix was incomplete. --- libclc/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt index 770f69a15a30..c6e3cdf23fe0 100644 --- a/libclc/CMakeLists.txt +++ b/libclc/CMakeLists.txt @@ -332,7 +332,7 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) if( ${ARCH} STREQUAL "spirv" OR ${ARCH} STREQUAL "spirv64" ) set( spv_suffix ${arch_suffix}.spv ) add_custom_command( OUTPUT "${spv_suffix}" - COMMAND ${LLVM_SPIRV} ${spvflags} -o "${spv_suffix}" ${builtins_link_lib_tgt} + COMMAND ${LLVM_SPIRV} ${spvflags} -o "${spv_suffix}" $ DEPENDS ${builtins_link_lib_tgt} ) add_custom_target( "prepare-${spv_suffix}" ALL DEPENDS "${spv_suffix}" ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${spv_suffix} -- GitLab From 26fee0ff1251fa70babaf419c08383e7ec71c56c Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Mon, 8 Apr 2024 09:05:09 -0700 Subject: [PATCH 162/695] [OpenACC] Implement Sema work for OpenACC Clauses (#87821) Now that we have AST nodes for OpenACC Clauses, this patch adds their creation to Sema and makes the Parser call all the required functions. This also redoes TreeTransform to work with the clauses/make sure they are transformed. Much of this is NFC, since there is no clause we can test this behavior with. However, there IS one noticable change; we are now no longer diagnosing that a clause is 'not implemented' unless it there was no errors parsing its parameters. This is because it cleans up how we create and diagnose clauses. --- .../clang/Basic/DiagnosticSemaKinds.td | 2 + clang/include/clang/Parse/Parser.h | 34 +- clang/include/clang/Sema/SemaOpenACC.h | 40 +- clang/lib/Parse/ParseOpenACC.cpp | 143 +++-- clang/lib/Sema/SemaOpenACC.cpp | 46 +- clang/lib/Sema/TreeTransform.h | 41 +- clang/test/ParserOpenACC/parse-clauses.c | 573 +++++++----------- clang/test/ParserOpenACC/parse-clauses.cpp | 9 +- clang/test/ParserOpenACC/parse-wait-clause.c | 102 ++-- 9 files changed, 490 insertions(+), 500 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index a1dda2d2461c..4fbbc42273ba 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -12252,6 +12252,8 @@ def warn_acc_clause_unimplemented def err_acc_construct_appertainment : Error<"OpenACC construct '%0' cannot be used here; it can only " "be used in a statement context">; +def err_acc_clause_appertainment + : Error<"OpenACC '%1' clause is not valid on '%0' directive">; def err_acc_branch_in_out_compute_construct : Error<"invalid %select{branch|return|throw}0 %select{out of|into}1 " "OpenACC Compute Construct">; diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 580bf2a5d79d..8bc929b1dfe4 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -41,6 +41,7 @@ namespace clang { class InMessageExpressionRAIIObject; class PoisonSEHIdentifiersRAIIObject; class OMPClause; + class OpenACCClause; class ObjCTypeParamList; struct OMPTraitProperty; struct OMPTraitSelector; @@ -3594,11 +3595,26 @@ private: OpenACCDirectiveKind DirKind; SourceLocation StartLoc; SourceLocation EndLoc; - // TODO OpenACC: Add Clause list here once we have a type for that. + SmallVector Clauses; // TODO OpenACC: As we implement support for the Atomic, Routine, Cache, and // Wait constructs, we likely want to put that information in here as well. }; + /// Represents the 'error' state of parsing an OpenACC Clause, and stores + /// whether we can continue parsing, or should give up on the directive. + enum class OpenACCParseCanContinue { Cannot = 0, Can = 1 }; + + /// A type to represent the state of parsing an OpenACC Clause. Situations + /// that result in an OpenACCClause pointer are a success and can continue + /// parsing, however some other situations can also continue. + /// FIXME: This is better represented as a std::expected when we get C++23. + using OpenACCClauseParseResult = + llvm::PointerIntPair; + + OpenACCClauseParseResult OpenACCCanContinue(); + OpenACCClauseParseResult OpenACCCannotContinue(); + OpenACCClauseParseResult OpenACCSuccess(OpenACCClause *Clause); + /// Parses the OpenACC directive (the entire pragma) including the clause /// list, but does not produce the main AST node. OpenACCDirectiveParseInfo ParseOpenACCDirective(); @@ -3613,12 +3629,18 @@ private: bool ParseOpenACCClauseVarList(OpenACCClauseKind Kind); /// Parses any parameters for an OpenACC Clause, including required/optional /// parens. - bool ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, - OpenACCClauseKind Kind); - /// Parses a single clause in a clause-list for OpenACC. - bool ParseOpenACCClause(OpenACCDirectiveKind DirKind); + OpenACCClauseParseResult + ParseOpenACCClauseParams(ArrayRef ExistingClauses, + OpenACCDirectiveKind DirKind, OpenACCClauseKind Kind, + SourceLocation ClauseLoc); + /// Parses a single clause in a clause-list for OpenACC. Returns nullptr on + /// error. + OpenACCClauseParseResult + ParseOpenACCClause(ArrayRef ExistingClauses, + OpenACCDirectiveKind DirKind); /// Parses the clause-list for an OpenACC directive. - void ParseOpenACCClauseList(OpenACCDirectiveKind DirKind); + SmallVector + ParseOpenACCClauseList(OpenACCDirectiveKind DirKind); bool ParseOpenACCWaitArgument(); /// Parses the clause of the 'bind' argument, which can be a string literal or /// an ID expression. diff --git a/clang/include/clang/Sema/SemaOpenACC.h b/clang/include/clang/Sema/SemaOpenACC.h index ad4cff04ec9c..45929e4a9db3 100644 --- a/clang/include/clang/Sema/SemaOpenACC.h +++ b/clang/include/clang/Sema/SemaOpenACC.h @@ -21,13 +21,46 @@ #include "clang/Sema/SemaBase.h" namespace clang { +class OpenACCClause; class SemaOpenACC : public SemaBase { public: + /// A type to represent all the data for an OpenACC Clause that has been + /// parsed, but not yet created/semantically analyzed. This is effectively a + /// discriminated union on the 'Clause Kind', with all of the individual + /// clause details stored in a std::variant. + class OpenACCParsedClause { + OpenACCDirectiveKind DirKind; + OpenACCClauseKind ClauseKind; + SourceRange ClauseRange; + SourceLocation LParenLoc; + + // TODO OpenACC: Add variant here to store details of individual clauses. + + public: + OpenACCParsedClause(OpenACCDirectiveKind DirKind, + OpenACCClauseKind ClauseKind, SourceLocation BeginLoc) + : DirKind(DirKind), ClauseKind(ClauseKind), ClauseRange(BeginLoc, {}) {} + + OpenACCDirectiveKind getDirectiveKind() const { return DirKind; } + + OpenACCClauseKind getClauseKind() const { return ClauseKind; } + + SourceLocation getBeginLoc() const { return ClauseRange.getBegin(); } + + SourceLocation getLParenLoc() const { return LParenLoc; } + + SourceLocation getEndLoc() const { return ClauseRange.getEnd(); } + + void setLParenLoc(SourceLocation EndLoc) { LParenLoc = EndLoc; } + void setEndLoc(SourceLocation EndLoc) { ClauseRange.setEnd(EndLoc); } + }; + SemaOpenACC(Sema &S); /// Called after parsing an OpenACC Clause so that it can be checked. - bool ActOnClause(OpenACCClauseKind ClauseKind, SourceLocation StartLoc); + OpenACCClause *ActOnClause(ArrayRef ExistingClauses, + OpenACCParsedClause &Clause); /// Called after the construct has been parsed, but clauses haven't been /// parsed. This allows us to diagnose not-implemented, as well as set up any @@ -53,7 +86,10 @@ public: /// declaration group or associated statement. StmtResult ActOnEndStmtDirective(OpenACCDirectiveKind K, SourceLocation StartLoc, - SourceLocation EndLoc, StmtResult AssocStmt); + SourceLocation EndLoc, + ArrayRef Clauses, + StmtResult AssocStmt); + /// Called after the directive has been completely parsed, including the /// declaration group or associated statement. DeclGroupRef ActOnEndDeclDirective(); diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 07dd2ba0106a..3034d24b2ab9 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "clang/AST/OpenACCClause.h" #include "clang/Basic/OpenACCKinds.h" #include "clang/Parse/ParseDiagnostic.h" #include "clang/Parse/Parser.h" @@ -582,12 +583,26 @@ unsigned getOpenACCScopeFlags(OpenACCDirectiveKind DirKind) { } // namespace +Parser::OpenACCClauseParseResult Parser::OpenACCCanContinue() { + return {nullptr, OpenACCParseCanContinue::Can}; +} + +Parser::OpenACCClauseParseResult Parser::OpenACCCannotContinue() { + return {nullptr, OpenACCParseCanContinue::Cannot}; +} + +Parser::OpenACCClauseParseResult Parser::OpenACCSuccess(OpenACCClause *Clause) { + return {Clause, OpenACCParseCanContinue::Can}; +} + // OpenACC 3.3, section 1.7: // To simplify the specification and convey appropriate constraint information, // a pqr-list is a comma-separated list of pdr items. The one exception is a // clause-list, which is a list of one or more clauses optionally separated by // commas. -void Parser::ParseOpenACCClauseList(OpenACCDirectiveKind DirKind) { +SmallVector +Parser::ParseOpenACCClauseList(OpenACCDirectiveKind DirKind) { + SmallVector Clauses; bool FirstClause = true; while (getCurToken().isNot(tok::annot_pragma_openacc_end)) { // Comma is optional in a clause-list. @@ -595,13 +610,17 @@ void Parser::ParseOpenACCClauseList(OpenACCDirectiveKind DirKind) { ConsumeToken(); FirstClause = false; - // Recovering from a bad clause is really difficult, so we just give up on - // error. - if (ParseOpenACCClause(DirKind)) { + OpenACCClauseParseResult Result = ParseOpenACCClause(Clauses, DirKind); + if (OpenACCClause *Clause = Result.getPointer()) { + Clauses.push_back(Clause); + } else if (Result.getInt() == OpenACCParseCanContinue::Cannot) { + // Recovering from a bad clause is really difficult, so we just give up on + // error. SkipUntilEndOfDirective(*this); - return; + return Clauses; } } + return Clauses; } ExprResult Parser::ParseOpenACCIntExpr() { @@ -762,42 +781,48 @@ bool Parser::ParseOpenACCGangArgList() { // really have its owner grammar and each individual one has its own definition. // However, they all are named with a single-identifier (or auto/default!) // token, followed in some cases by either braces or parens. -bool Parser::ParseOpenACCClause(OpenACCDirectiveKind DirKind) { +Parser::OpenACCClauseParseResult +Parser::ParseOpenACCClause(ArrayRef ExistingClauses, + OpenACCDirectiveKind DirKind) { // A number of clause names are actually keywords, so accept a keyword that // can be converted to a name. if (expectIdentifierOrKeyword(*this)) - return true; + return OpenACCCannotContinue(); OpenACCClauseKind Kind = getOpenACCClauseKind(getCurToken()); - if (Kind == OpenACCClauseKind::Invalid) - return Diag(getCurToken(), diag::err_acc_invalid_clause) - << getCurToken().getIdentifierInfo(); + if (Kind == OpenACCClauseKind::Invalid) { + Diag(getCurToken(), diag::err_acc_invalid_clause) + << getCurToken().getIdentifierInfo(); + return OpenACCCannotContinue(); + } // Consume the clause name. SourceLocation ClauseLoc = ConsumeToken(); - bool Result = ParseOpenACCClauseParams(DirKind, Kind); - getActions().OpenACC().ActOnClause(Kind, ClauseLoc); - return Result; + return ParseOpenACCClauseParams(ExistingClauses, DirKind, Kind, ClauseLoc); } -bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, - OpenACCClauseKind Kind) { +Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( + ArrayRef ExistingClauses, + OpenACCDirectiveKind DirKind, OpenACCClauseKind ClauseKind, + SourceLocation ClauseLoc) { BalancedDelimiterTracker Parens(*this, tok::l_paren, tok::annot_pragma_openacc_end); + SemaOpenACC::OpenACCParsedClause ParsedClause(DirKind, ClauseKind, ClauseLoc); - if (ClauseHasRequiredParens(DirKind, Kind)) { + if (ClauseHasRequiredParens(DirKind, ClauseKind)) { + ParsedClause.setLParenLoc(getCurToken().getLocation()); if (Parens.expectAndConsume()) { // We are missing a paren, so assume that the person just forgot the // parameter. Return 'false' so we try to continue on and parse the next // clause. SkipUntil(tok::comma, tok::r_paren, tok::annot_pragma_openacc_end, Parser::StopBeforeMatch); - return false; + return OpenACCCanContinue(); } - switch (Kind) { + switch (ClauseKind) { case OpenACCClauseKind::Default: { Token DefKindTok = getCurToken(); @@ -818,34 +843,34 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, // this clause list. if (CondExpr.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } case OpenACCClauseKind::CopyIn: tryParseAndConsumeSpecialTokenKind( - *this, OpenACCSpecialTokenKind::ReadOnly, Kind); - if (ParseOpenACCClauseVarList(Kind)) { + *this, OpenACCSpecialTokenKind::ReadOnly, ClauseKind); + if (ParseOpenACCClauseVarList(ClauseKind)) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; case OpenACCClauseKind::Create: case OpenACCClauseKind::CopyOut: tryParseAndConsumeSpecialTokenKind(*this, OpenACCSpecialTokenKind::Zero, - Kind); - if (ParseOpenACCClauseVarList(Kind)) { + ClauseKind); + if (ParseOpenACCClauseVarList(ClauseKind)) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; case OpenACCClauseKind::Reduction: // If we're missing a clause-kind (or it is invalid), see if we can parse // the var-list anyway. ParseReductionOperator(*this); - if (ParseOpenACCClauseVarList(Kind)) { + if (ParseOpenACCClauseVarList(ClauseKind)) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; case OpenACCClauseKind::Self: @@ -868,19 +893,19 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, case OpenACCClauseKind::Present: case OpenACCClauseKind::Private: case OpenACCClauseKind::UseDevice: - if (ParseOpenACCClauseVarList(Kind)) { + if (ParseOpenACCClauseVarList(ClauseKind)) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; case OpenACCClauseKind::Collapse: { tryParseAndConsumeSpecialTokenKind(*this, OpenACCSpecialTokenKind::Force, - Kind); + ClauseKind); ExprResult NumLoops = getActions().CorrectDelayedTyposInExpr(ParseConstantExpression()); if (NumLoops.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } @@ -888,7 +913,7 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, ExprResult BindArg = ParseOpenACCBindClauseArgument(); if (BindArg.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } @@ -900,7 +925,7 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, ExprResult IntExpr = ParseOpenACCIntExpr(); if (IntExpr.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } @@ -912,23 +937,28 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, ConsumeToken(); } else if (ParseOpenACCDeviceTypeList()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; case OpenACCClauseKind::Tile: if (ParseOpenACCSizeExprList()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; default: llvm_unreachable("Not a required parens type?"); } - return Parens.consumeClose(); - } else if (ClauseHasOptionalParens(DirKind, Kind)) { + ParsedClause.setEndLoc(getCurToken().getLocation()); + + if (Parens.consumeClose()) + return OpenACCCannotContinue(); + + } else if (ClauseHasOptionalParens(DirKind, ClauseKind)) { + ParsedClause.setLParenLoc(getCurToken().getLocation()); if (!Parens.consumeOpen()) { - switch (Kind) { + switch (ClauseKind) { case OpenACCClauseKind::Self: { assert(DirKind != OpenACCDirectiveKind::Update); ExprResult CondExpr = ParseOpenACCConditionalExpr(*this); @@ -936,21 +966,22 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, // this clause list. if (CondExpr.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } case OpenACCClauseKind::Vector: case OpenACCClauseKind::Worker: { tryParseAndConsumeSpecialTokenKind(*this, - Kind == OpenACCClauseKind::Vector + ClauseKind == + OpenACCClauseKind::Vector ? OpenACCSpecialTokenKind::Length : OpenACCSpecialTokenKind::Num, - Kind); + ClauseKind); ExprResult IntExpr = ParseOpenACCIntExpr(); if (IntExpr.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } @@ -958,29 +989,32 @@ bool Parser::ParseOpenACCClauseParams(OpenACCDirectiveKind DirKind, ExprResult AsyncArg = ParseOpenACCAsyncArgument(); if (AsyncArg.isInvalid()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; } case OpenACCClauseKind::Gang: if (ParseOpenACCGangArgList()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; case OpenACCClauseKind::Wait: if (ParseOpenACCWaitArgument()) { Parens.skipToEnd(); - return false; + return OpenACCCanContinue(); } break; default: llvm_unreachable("Not an optional parens type?"); } - Parens.consumeClose(); + ParsedClause.setEndLoc(getCurToken().getLocation()); + if (Parens.consumeClose()) + return OpenACCCannotContinue(); } } - return false; + return OpenACCSuccess( + Actions.OpenACC().ActOnClause(ExistingClauses, ParsedClause)); } /// OpenACC 3.3 section 2.16: @@ -1204,15 +1238,17 @@ Parser::OpenACCDirectiveParseInfo Parser::ParseOpenACCDirective() { Diag(Tok, diag::err_expected) << tok::l_paren; } - // Parses the list of clauses, if present. - ParseOpenACCClauseList(DirKind); + // Parses the list of clauses, if present, plus set up return value. + OpenACCDirectiveParseInfo ParseInfo{DirKind, StartLoc, SourceLocation{}, + ParseOpenACCClauseList(DirKind)}; assert(Tok.is(tok::annot_pragma_openacc_end) && "Didn't parse all OpenACC Clauses"); - SourceLocation EndLoc = ConsumeAnnotationToken(); - assert(EndLoc.isValid()); + ParseInfo.EndLoc = ConsumeAnnotationToken(); + assert(ParseInfo.EndLoc.isValid(), + "Terminating annotation token not present"); - return OpenACCDirectiveParseInfo{DirKind, StartLoc, EndLoc}; + return ParseInfo; } // Parse OpenACC directive on a declaration. @@ -1255,5 +1291,6 @@ StmtResult Parser::ParseOpenACCDirectiveStmt() { } return getActions().OpenACC().ActOnEndStmtDirective( - DirInfo.DirKind, DirInfo.StartLoc, DirInfo.EndLoc, AssocStmt); + DirInfo.DirKind, DirInfo.StartLoc, DirInfo.EndLoc, DirInfo.Clauses, + AssocStmt); } diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index f66cc1a69ce4..f520b9bfe811 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -36,20 +36,44 @@ bool diagnoseConstructAppertainment(SemaOpenACC &S, OpenACCDirectiveKind K, } return false; } + +bool doesClauseApplyToDirective(OpenACCDirectiveKind DirectiveKind, + OpenACCClauseKind ClauseKind) { + switch (ClauseKind) { + // FIXME: For each clause as we implement them, we can add the + // 'legalization' list here. + default: + // Do nothing so we can go to the 'unimplemented' diagnostic instead. + return true; + } + llvm_unreachable("Invalid clause kind"); +} } // namespace SemaOpenACC::SemaOpenACC(Sema &S) : SemaBase(S) {} -bool SemaOpenACC::ActOnClause(OpenACCClauseKind ClauseKind, - SourceLocation StartLoc) { - if (ClauseKind == OpenACCClauseKind::Invalid) - return false; - // For now just diagnose that it is unsupported and leave the parsing to do - // whatever it can do. This function will eventually need to start returning - // some sort of Clause AST type, but for now just return true/false based on - // success. - return Diag(StartLoc, diag::warn_acc_clause_unimplemented) << ClauseKind; +OpenACCClause * +SemaOpenACC::ActOnClause(ArrayRef ExistingClauses, + OpenACCParsedClause &Clause) { + if (Clause.getClauseKind() == OpenACCClauseKind::Invalid) + return nullptr; + + // Diagnose that we don't support this clause on this directive. + if (!doesClauseApplyToDirective(Clause.getDirectiveKind(), + Clause.getClauseKind())) { + Diag(Clause.getBeginLoc(), diag::err_acc_clause_appertainment) + << Clause.getDirectiveKind() << Clause.getClauseKind(); + return nullptr; + } + + // TODO OpenACC: Switch over the clauses we implement here and 'create' + // them. + + Diag(Clause.getBeginLoc(), diag::warn_acc_clause_unimplemented) + << Clause.getClauseKind(); + return nullptr; } + void SemaOpenACC::ActOnConstruct(OpenACCDirectiveKind K, SourceLocation StartLoc) { switch (K) { @@ -79,6 +103,7 @@ bool SemaOpenACC::ActOnStartStmtDirective(OpenACCDirectiveKind K, StmtResult SemaOpenACC::ActOnEndStmtDirective(OpenACCDirectiveKind K, SourceLocation StartLoc, SourceLocation EndLoc, + ArrayRef Clauses, StmtResult AssocStmt) { switch (K) { default: @@ -90,8 +115,7 @@ StmtResult SemaOpenACC::ActOnEndStmtDirective(OpenACCDirectiveKind K, case OpenACCDirectiveKind::Kernels: // TODO OpenACC: Add clauses to the construct here. return OpenACCComputeConstruct::Create( - getASTContext(), K, StartLoc, EndLoc, - /*Clauses=*/std::nullopt, + getASTContext(), K, StartLoc, EndLoc, Clauses, AssocStmt.isUsable() ? AssocStmt.get() : nullptr); } llvm_unreachable("Unhandled case in directive handling?"); diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 66c2c7dd6be8..ab97b375f516 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -4005,17 +4005,10 @@ public: StmtResult RebuildOpenACCComputeConstruct(OpenACCDirectiveKind K, SourceLocation BeginLoc, SourceLocation EndLoc, + ArrayRef Clauses, StmtResult StrBlock) { - getSema().OpenACC().ActOnConstruct(K, BeginLoc); - - // TODO OpenACC: Include clauses. - if (getSema().OpenACC().ActOnStartStmtDirective(K, BeginLoc)) - return StmtError(); - - StrBlock = getSema().OpenACC().ActOnAssociatedStmt(K, StrBlock); - return getSema().OpenACC().ActOnEndStmtDirective(K, BeginLoc, EndLoc, - StrBlock); + Clauses, StrBlock); } private: @@ -4036,6 +4029,10 @@ private: QualType TransformDependentNameType(TypeLocBuilder &TLB, DependentNameTypeLoc TL, bool DeducibleTSTContext); + + llvm::SmallVector + TransformOpenACCClauseList(OpenACCDirectiveKind DirKind, + ArrayRef OldClauses); }; template @@ -11076,16 +11073,38 @@ OMPClause *TreeTransform::TransformOMPXBareClause(OMPXBareClause *C) { //===----------------------------------------------------------------------===// // OpenACC transformation //===----------------------------------------------------------------------===// +template +llvm::SmallVector +TreeTransform::TransformOpenACCClauseList( + OpenACCDirectiveKind DirKind, ArrayRef OldClauses) { + // TODO OpenACC: Ensure we loop through the list and transform the individual + // clauses. + return {}; +} + template StmtResult TreeTransform::TransformOpenACCComputeConstruct( OpenACCComputeConstruct *C) { - // TODO OpenACC: Transform clauses. + getSema().OpenACC().ActOnConstruct(C->getDirectiveKind(), C->getBeginLoc()); + // FIXME: When implementing this for constructs that can take arguments, we + // should do Sema for them here. + + if (getSema().OpenACC().ActOnStartStmtDirective(C->getDirectiveKind(), + C->getBeginLoc())) + return StmtError(); + + llvm::SmallVector TransformedClauses = + getDerived().TransformOpenACCClauseList(C->getDirectiveKind(), + C->clauses()); // Transform Structured Block. StmtResult StrBlock = getDerived().TransformStmt(C->getStructuredBlock()); + StrBlock = + getSema().OpenACC().ActOnAssociatedStmt(C->getDirectiveKind(), StrBlock); return getDerived().RebuildOpenACCComputeConstruct( - C->getDirectiveKind(), C->getBeginLoc(), C->getEndLoc(), StrBlock); + C->getDirectiveKind(), C->getBeginLoc(), C->getEndLoc(), + TransformedClauses, StrBlock); } //===----------------------------------------------------------------------===// diff --git a/clang/test/ParserOpenACC/parse-clauses.c b/clang/test/ParserOpenACC/parse-clauses.c index a82c3662f2ad..b58b332ad324 100644 --- a/clang/test/ParserOpenACC/parse-clauses.c +++ b/clang/test/ParserOpenACC/parse-clauses.c @@ -86,27 +86,23 @@ void func() { // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop seq, - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'collapse' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop collapse for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'collapse' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop collapse() for(;;){} - // expected-error@+4{{invalid tag 'unknown' on 'collapse' clause}} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'collapse' not yet implemented, clause ignored}} + // expected-error@+3{{invalid tag 'unknown' on 'collapse' clause}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop collapse(unknown:) for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'collapse' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop collapse(force:) for(;;){} @@ -127,62 +123,53 @@ void func() { #pragma acc loop collapse(5) for(;;){} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'collapse' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop collapse(5, 6) for(;;){} } void DefaultClause() { - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop default for(;;){} - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc serial default seq for(;;){} - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial default, seq for(;;){} - // expected-error@+4{{expected identifier}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+3{{expected identifier}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial default( for(;;){} - // expected-error@+4{{invalid value for 'default' clause; expected 'present' or 'none'}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+3{{invalid value for 'default' clause; expected 'present' or 'none'}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial default( seq for(;;){} - // expected-error@+4{{expected identifier}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+3{{expected identifier}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial default(, seq for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial default) for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial default), seq for(;;){} @@ -231,87 +218,73 @@ void DefaultClause() { } void IfClause() { - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop if for(;;){} - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc serial if seq for(;;){} - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial if, seq for(;;){} - // expected-error@+4{{expected expression}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial if( for(;;){} - // expected-error@+4{{use of undeclared identifier 'seq'}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+3{{use of undeclared identifier 'seq'}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial if( seq for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{use of undeclared identifier 'seq'}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{use of undeclared identifier 'seq'}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial if(, seq for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial if) for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial if) seq for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial if), seq for(;;){} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc serial if() for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial if() seq for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial if(), seq for(;;){} - // expected-error@+2{{use of undeclared identifier 'invalid_expr'}} - // expected-warning@+1{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+1{{use of undeclared identifier 'invalid_expr'}} #pragma acc serial if(invalid_expr) for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'if' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial if() seq for(;;){} @@ -340,27 +313,24 @@ void SelfClause() { #pragma acc serial loop self, seq for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop self( for(;;){} - // expected-error@+5{{use of undeclared identifier 'seq'}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+4{{use of undeclared identifier 'seq'}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop self( seq for(;;){} - // expected-error@+6{{expected expression}} - // expected-error@+5{{use of undeclared identifier 'seq'}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+5{{expected expression}} + // expected-error@+4{{use of undeclared identifier 'seq'}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop self(, seq for(;;){} @@ -384,23 +354,20 @@ void SelfClause() { for(;;){} - // expected-error@+4{{expected expression}} - // expected-warning@+3{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} // expected-warning@+2{{OpenACC clause 'seq' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop self(), seq for(;;){} - // expected-error@+5{{expected expression}} // expected-error@+4{{expected expression}} - // expected-warning@+3{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} // expected-warning@+2{{OpenACC clause 'seq' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop self(,), seq for(;;){} - // expected-error@+4{{use of undeclared identifier 'invalid_expr'}} - // expected-warning@+3{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+3{{use of undeclared identifier 'invalid_expr'}} // expected-warning@+2{{OpenACC clause 'seq' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'serial loop' not yet implemented, pragma ignored}} #pragma acc serial loop self(invalid_expr), seq @@ -408,16 +375,14 @@ void SelfClause() { int i, j; - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial self(i > j for(;;){} - // expected-error@+4{{use of undeclared identifier 'seq'}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+3{{use of undeclared identifier 'seq'}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial self(i > j, seq for(;;){} @@ -448,14 +413,12 @@ struct HasMembersArray { void SelfUpdate() { struct Members s; - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'update' not yet implemented, pragma ignored}} #pragma acc update self for(;;){} - // expected-error@+4{{use of undeclared identifier 'zero'}} - // expected-warning@+3{{OpenACC clause 'self' not yet implemented, clause ignored}} + // expected-error@+3{{use of undeclared identifier 'zero'}} // expected-warning@+2{{OpenACC clause 'seq' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'update' not yet implemented, pragma ignored}} #pragma acc update self(zero : s.array[s.value : 5], s.value), seq @@ -469,50 +432,42 @@ void SelfUpdate() { } void VarListClauses() { - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc serial copy for(;;){} - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copy, seq for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial copy) for(;;){} - // expected-error@+3{{expected '('}} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} + // expected-error@+1{{expected identifier}} #pragma acc serial copy), seq for(;;){} - // expected-error@+4{{expected expression}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial copy( for(;;){} - // expected-error@+4{{expected expression}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc serial copy(, seq for(;;){} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc serial copy() for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copy(), seq for(;;){} @@ -552,28 +507,24 @@ void VarListClauses() { #pragma acc serial copy(HasMem.MemArr[1:3].array[1:2]), seq for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copy(HasMem.MemArr[:]), seq for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copy(HasMem.MemArr[::]), seq for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ']'}} - // expected-note@+3{{to match this '['}} - // expected-warning@+2{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ']'}} + // expected-note@+2{{to match this '['}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copy(HasMem.MemArr[: :]), seq for(;;){} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'copy' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copy(HasMem.MemArr[3:]), seq for(;;){} @@ -753,8 +704,7 @@ void VarListClauses() { #pragma acc serial copyout(zero : s.array[s.value : 5], s.value), seq for(;;){} - // expected-error@+3{{use of undeclared identifier 'zero'}} - // expected-warning@+2{{OpenACC clause 'copyout' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'zero'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copyout(zero s.array[s.value : 5], s.value), seq for(;;){} @@ -777,8 +727,7 @@ void VarListClauses() { #pragma acc serial copyout(invalid:s.array[s.value : 5], s.value), seq for(;;){} - // expected-error@+3{{use of undeclared identifier 'invalid'}} - // expected-warning@+2{{OpenACC clause 'copyout' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'invalid'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copyout(invalid s.array[s.value : 5], s.value), seq for(;;){} @@ -804,8 +753,7 @@ void VarListClauses() { #pragma acc serial create(zero : s.array[s.value : 5], s.value), seq for(;;){} - // expected-error@+3{{use of undeclared identifier 'zero'}} - // expected-warning@+2{{OpenACC clause 'create' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'zero'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial create(zero s.array[s.value : 5], s.value), seq for(;;){} @@ -828,8 +776,7 @@ void VarListClauses() { #pragma acc serial create(invalid:s.array[s.value : 5], s.value), seq for(;;){} - // expected-error@+3{{use of undeclared identifier 'invalid'}} - // expected-warning@+2{{OpenACC clause 'create' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'invalid'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial create(invalid s.array[s.value : 5], s.value), seq for(;;){} @@ -855,8 +802,7 @@ void VarListClauses() { #pragma acc serial copyin(readonly : s.array[s.value : 5], s.value), seq for(;;){} - // expected-error@+3{{use of undeclared identifier 'readonly'}} - // expected-warning@+2{{OpenACC clause 'copyin' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'readonly'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copyin(readonly s.array[s.value : 5], s.value), seq for(;;){} @@ -879,8 +825,7 @@ void VarListClauses() { #pragma acc serial copyin(invalid:s.array[s.value : 5], s.value), seq for(;;){} - // expected-error@+3{{use of undeclared identifier 'invalid'}} - // expected-warning@+2{{OpenACC clause 'copyin' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'invalid'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial copyin(invalid s.array[s.value : 5], s.value), seq for(;;){} @@ -888,13 +833,11 @@ void VarListClauses() { void ReductionClauseParsing() { char *Begin, *End; - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'reduction' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc serial reduction for(;;){} - // expected-error@+3{{missing reduction operator, expected '+', '*', 'max', 'min', '&', '|', '^', '&&', or '||', follwed by a ':'}} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'reduction' not yet implemented, clause ignored}} + // expected-error@+2{{missing reduction operator, expected '+', '*', 'max', 'min', '&', '|', '^', '&&', or '||', follwed by a ':'}} + // expected-error@+1{{expected expression}} #pragma acc serial reduction() for(;;){} // expected-error@+2{{missing reduction operator, expected '+', '*', 'max', 'min', '&', '|', '^', '&&', or '||', follwed by a ':'}} @@ -946,24 +889,20 @@ void ReductionClauseParsing() { int returns_int(); void IntExprParsing() { - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'vector_length' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc parallel vector_length {} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'vector_length' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc parallel vector_length() {} - // expected-error@+2{{use of undeclared identifier 'invalid'}} - // expected-warning@+1{{OpenACC clause 'vector_length' not yet implemented, clause ignored}} + // expected-error@+1{{use of undeclared identifier 'invalid'}} #pragma acc parallel vector_length(invalid) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'vector_length' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel vector_length(5, 4) {} @@ -975,24 +914,20 @@ void IntExprParsing() { #pragma acc parallel vector_length(returns_int()) {} - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'num_gangs' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc parallel num_gangs {} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'num_gangs' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc parallel num_gangs() {} - // expected-error@+2{{use of undeclared identifier 'invalid'}} - // expected-warning@+1{{OpenACC clause 'num_gangs' not yet implemented, clause ignored}} + // expected-error@+1{{use of undeclared identifier 'invalid'}} #pragma acc parallel num_gangs(invalid) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'num_gangs' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel num_gangs(5, 4) {} @@ -1004,24 +939,20 @@ void IntExprParsing() { #pragma acc parallel num_gangs(returns_int()) {} - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'num_workers' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc parallel num_workers {} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'num_workers' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc parallel num_workers() {} - // expected-error@+2{{use of undeclared identifier 'invalid'}} - // expected-warning@+1{{OpenACC clause 'num_workers' not yet implemented, clause ignored}} + // expected-error@+1{{use of undeclared identifier 'invalid'}} #pragma acc parallel num_workers(invalid) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'num_workers' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel num_workers(5, 4) {} @@ -1033,24 +964,20 @@ void IntExprParsing() { #pragma acc parallel num_workers(returns_int()) {} - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'device_num' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'init' not yet implemented, pragma ignored}} #pragma acc init device_num - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'device_num' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'init' not yet implemented, pragma ignored}} #pragma acc init device_num() - // expected-error@+3{{use of undeclared identifier 'invalid'}} - // expected-warning@+2{{OpenACC clause 'device_num' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'invalid'}} // expected-warning@+1{{OpenACC construct 'init' not yet implemented, pragma ignored}} #pragma acc init device_num(invalid) - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'device_num' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'init' not yet implemented, pragma ignored}} #pragma acc init device_num(5, 4) @@ -1062,24 +989,20 @@ void IntExprParsing() { // expected-warning@+1{{OpenACC construct 'init' not yet implemented, pragma ignored}} #pragma acc init device_num(returns_int()) - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'default_async' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'set' not yet implemented, pragma ignored}} #pragma acc set default_async - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'default_async' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'set' not yet implemented, pragma ignored}} #pragma acc set default_async() - // expected-error@+3{{use of undeclared identifier 'invalid'}} - // expected-warning@+2{{OpenACC clause 'default_async' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'invalid'}} // expected-warning@+1{{OpenACC construct 'set' not yet implemented, pragma ignored}} #pragma acc set default_async(invalid) - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'default_async' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'set' not yet implemented, pragma ignored}} #pragma acc set default_async(5, 4) @@ -1095,42 +1018,35 @@ void IntExprParsing() { // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector() - // expected-error@+4{{invalid tag 'invalid' on 'vector' clause}} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+3{{invalid tag 'invalid' on 'vector' clause}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(invalid:) // expected-error@+3{{invalid tag 'invalid' on 'vector' clause}} // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(invalid:5) - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(length:) - // expected-error@+4{{invalid tag 'num' on 'vector' clause}} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+3{{invalid tag 'num' on 'vector' clause}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(num:) - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(5, 4) - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(length:6,4) - // expected-error@+5{{invalid tag 'num' on 'vector' clause}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} + // expected-error@+4{{invalid tag 'num' on 'vector' clause}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop vector(num:6,4) // expected-warning@+2{{OpenACC clause 'vector' not yet implemented, clause ignored}} @@ -1153,42 +1069,35 @@ void IntExprParsing() { // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker() - // expected-error@+4{{invalid tag 'invalid' on 'worker' clause}} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+3{{invalid tag 'invalid' on 'worker' clause}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(invalid:) // expected-error@+3{{invalid tag 'invalid' on 'worker' clause}} // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(invalid:5) - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(num:) - // expected-error@+4{{invalid tag 'length' on 'worker' clause}} - // expected-error@+3{{expected expression}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+3{{invalid tag 'length' on 'worker' clause}} + // expected-error@+2{{expected expression}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(length:) - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(5, 4) - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(num:6,4) - // expected-error@+5{{invalid tag 'length' on 'worker' clause}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} + // expected-error@+4{{invalid tag 'length' on 'worker' clause}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop worker(length:6,4) // expected-warning@+2{{OpenACC clause 'worker' not yet implemented, clause ignored}} @@ -1211,25 +1120,21 @@ void IntExprParsing() { } void device_type() { - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc parallel device_type {} - // expected-error@+2{{expected '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+1{{expected '('}} #pragma acc parallel dtype {} - // expected-error@+4{{expected identifier}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+3{{expected identifier}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type( {} - // expected-error@+4{{expected identifier}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+3{{expected identifier}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype( {} @@ -1242,49 +1147,41 @@ void device_type() { #pragma acc parallel dtype() {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type(* {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype(* {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type(ident {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype(ident {} - // expected-error@+4{{expected ','}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+3{{expected ','}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type(ident ident2 {} - // expected-error@+4{{expected ','}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+3{{expected ','}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype(ident ident2 {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type(ident, ident2 {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype(ident, ident2 {} @@ -1297,25 +1194,21 @@ void device_type() { #pragma acc parallel dtype(ident, ident2,) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type(*,) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype(*,) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'device_type' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel device_type(*,ident) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'dtype' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel dtype(*,ident) {} @@ -1356,19 +1249,16 @@ void AsyncArgument() { #pragma acc parallel async {} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'async' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc parallel async() {} - // expected-error@+2{{use of undeclared identifier 'invalid'}} - // expected-warning@+1{{OpenACC clause 'async' not yet implemented, clause ignored}} + // expected-error@+1{{use of undeclared identifier 'invalid'}} #pragma acc parallel async(invalid) {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'async' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel async(4, 3) {} @@ -1388,15 +1278,13 @@ void AsyncArgument() { void Tile() { int* Foo; - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'tile' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop tile for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'tile' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop tile( for(;;){} @@ -1405,10 +1293,9 @@ void Tile() { // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop tile() for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'tile' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop tile(, for(;;){} @@ -1466,10 +1353,9 @@ void Gang() { // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang( for(;;){} @@ -1552,77 +1438,67 @@ void Gang() { #pragma acc loop gang(static:45, 5) for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(static:45, for(;;){} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(static:45 for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(static:*, for(;;){} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(static:* for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(45, for(;;){} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(45 for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(num:45, for(;;){} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(num:45 for(;;){} - // expected-error@+5{{expected expression}} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+4{{expected expression}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(dim:45, for(;;){} - // expected-error@+4{{expected ')'}} - // expected-note@+3{{to match this '('}} - // expected-warning@+2{{OpenACC clause 'gang' not yet implemented, clause ignored}} + // expected-error@+3{{expected ')'}} + // expected-note@+2{{to match this '('}} // expected-warning@+1{{OpenACC construct 'loop' not yet implemented, pragma ignored}} #pragma acc loop gang(dim:45 for(;;){} @@ -1657,14 +1533,12 @@ void bar(); // Bind Clause Parsing. - // expected-error@+3{{expected '('}} - // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} + // expected-error@+2{{expected '('}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine bind void BCP1(); - // expected-error@+3{{expected identifier or string literal}} - // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} + // expected-error@+2{{expected identifier or string literal}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(BCP1) bind() @@ -1677,7 +1551,6 @@ void BCP2(); // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(BCP1) bind(BCP2) - // expected-error@+3{{use of undeclared identifier 'unknown_thing'}} - // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'unknown_thing'}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(BCP1) bind(unknown_thing) diff --git a/clang/test/ParserOpenACC/parse-clauses.cpp b/clang/test/ParserOpenACC/parse-clauses.cpp index 497b1c7bcd0d..09a90726c693 100644 --- a/clang/test/ParserOpenACC/parse-clauses.cpp +++ b/clang/test/ParserOpenACC/parse-clauses.cpp @@ -56,9 +56,8 @@ void function(); // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(use) bind(NS::NSFunc) - // expected-error@+4{{'RecordTy' does not refer to a value}} + // expected-error@+3{{'RecordTy' does not refer to a value}} // expected-note@#RecTy{{declared here}} - // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(use) bind(NS::RecordTy) // expected-error@+4{{'Value' is a private member of 'NS::RecordTy'}} @@ -72,8 +71,7 @@ void function(); // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(use) bind(NS::TemplTy) - // expected-error@+3{{no member named 'unknown' in namespace 'NS'}} - // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} + // expected-error@+2{{no member named 'unknown' in namespace 'NS'}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(use) bind(NS::unknown) // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} @@ -88,8 +86,7 @@ void function(); // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(use) bind(NS::RecordTy::mem_function) - // expected-error@+3{{string literal with user-defined suffix cannot be used here}} - // expected-warning@+2{{OpenACC clause 'bind' not yet implemented, clause ignored}} + // expected-error@+2{{string literal with user-defined suffix cannot be used here}} // expected-warning@+1{{OpenACC construct 'routine' not yet implemented, pragma ignored}} #pragma acc routine(use) bind("unknown udl"_UDL) diff --git a/clang/test/ParserOpenACC/parse-wait-clause.c b/clang/test/ParserOpenACC/parse-wait-clause.c index cce050d5da98..f3e651de4583 100644 --- a/clang/test/ParserOpenACC/parse-wait-clause.c +++ b/clang/test/ParserOpenACC/parse-wait-clause.c @@ -12,9 +12,8 @@ void func() { #pragma acc parallel wait clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait ( {} @@ -27,45 +26,38 @@ void func() { #pragma acc parallel wait () clause-list {} - // expected-error@+4{{expected expression}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait (devnum: {} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc parallel wait (devnum:) {} - // expected-error@+3{{expected expression}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait (devnum:) clause-list {} - // expected-error@+4{{expected ':'}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+3{{expected ':'}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait (devnum: i + j {} - // expected-error@+2{{expected ':'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{expected ':'}} #pragma acc parallel wait (devnum: i + j) {} - // expected-error@+3{{expected ':'}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ':'}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait (devnum: i + j) clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait (queues: {} @@ -78,9 +70,8 @@ void func() { #pragma acc parallel wait (queues:) clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait (devnum: i + j:queues: {} @@ -93,27 +84,23 @@ void func() { #pragma acc parallel wait (devnum: i + j:queues:) clause-list {} - // expected-error@+4{{use of undeclared identifier 'devnum'}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+3{{use of undeclared identifier 'devnum'}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait (queues:devnum: i + j {} - // expected-error@+2{{use of undeclared identifier 'devnum'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{use of undeclared identifier 'devnum'}} #pragma acc parallel wait (queues:devnum: i + j) {} - // expected-error@+3{{use of undeclared identifier 'devnum'}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{use of undeclared identifier 'devnum'}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait (queues:devnum: i + j) clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait(i, j, 1+1, 3.3 {} @@ -125,34 +112,29 @@ void func() { #pragma acc parallel wait(i, j, 1+1, 3.3) clause-list {} - // expected-error@+4{{expected expression}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait(, {} - // expected-error@+2{{expected expression}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+1{{expected expression}} #pragma acc parallel wait(,) {} - // expected-error@+3{{expected expression}} - // expected-error@+2{{invalid OpenACC clause 'clause'}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected expression}} + // expected-error@+1{{invalid OpenACC clause 'clause'}} #pragma acc parallel wait(,) clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait(queues:i, j, 1+1, 3.3 {} - // expected-error@+4{{expected expression}} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+3{{expected expression}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait(queues:i, j, 1+1, 3.3, {} @@ -165,9 +147,8 @@ void func() { #pragma acc parallel wait(queues:i, j, 1+1, 3.3) clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait(devnum:3:i, j, 1+1, 3.3 {} // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} @@ -178,9 +159,8 @@ void func() { #pragma acc parallel wait(devnum:3:i, j, 1+1, 3.3) clause-list {} - // expected-error@+3{{expected ')'}} - // expected-note@+2{{to match this '('}} - // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} + // expected-error@+2{{expected ')'}} + // expected-note@+1{{to match this '('}} #pragma acc parallel wait(devnum:3:queues:i, j, 1+1, 3.3 {} // expected-warning@+1{{OpenACC clause 'wait' not yet implemented, clause ignored}} -- GitLab From 4d6e67f677bdf40360e6aaba171bcdec93990b01 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Mon, 8 Apr 2024 09:08:21 -0700 Subject: [PATCH 163/695] Fix build issue committed in 26fee0ff12 I brain-farted on how assert works :) --- clang/lib/Parse/ParseOpenACC.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 3034d24b2ab9..f434e1542c80 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -1245,7 +1245,7 @@ Parser::OpenACCDirectiveParseInfo Parser::ParseOpenACCDirective() { assert(Tok.is(tok::annot_pragma_openacc_end) && "Didn't parse all OpenACC Clauses"); ParseInfo.EndLoc = ConsumeAnnotationToken(); - assert(ParseInfo.EndLoc.isValid(), + assert(ParseInfo.EndLoc.isValid() && "Terminating annotation token not present"); return ParseInfo; -- GitLab From f6315a957232b2f5c27476138e3f4e552861f956 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Mon, 8 Apr 2024 09:10:23 -0700 Subject: [PATCH 164/695] [AArch64][LoopIdiom] Disable LoopIdiomTransform when NoImplicitFloat is present (#87677) This behavior is aligned with both LoopVectorizer and SLPVectorizer. --- .../AArch64/AArch64LoopIdiomTransform.cpp | 14 ++- .../LoopIdiom/AArch64/byte-compare-index.ll | 96 +++++++++++++++++++ 2 files changed, 106 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp index 6dfb2b9df713..a9bd8d877fb2 100644 --- a/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp @@ -190,17 +190,23 @@ AArch64LoopIdiomTransformPass::run(Loop &L, LoopAnalysisManager &AM, bool AArch64LoopIdiomTransform::run(Loop *L) { CurLoop = L; - if (DisableAll || L->getHeader()->getParent()->hasOptSize()) + Function &F = *L->getHeader()->getParent(); + if (DisableAll || F.hasOptSize()) return false; + if (F.hasFnAttribute(Attribute::NoImplicitFloat)) { + LLVM_DEBUG(dbgs() << DEBUG_TYPE << " is disabled on " << F.getName() + << " due to its NoImplicitFloat attribute"); + return false; + } + // If the loop could not be converted to canonical form, it must have an // indirectbr in it, just give up. if (!L->getLoopPreheader()) return false; - LLVM_DEBUG(dbgs() << DEBUG_TYPE " Scanning: F[" - << CurLoop->getHeader()->getParent()->getName() - << "] Loop %" << CurLoop->getHeader()->getName() << "\n"); + LLVM_DEBUG(dbgs() << DEBUG_TYPE " Scanning: F[" << F.getName() << "] Loop %" + << CurLoop->getHeader()->getName() << "\n"); return recognizeByteCompare(); } diff --git a/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll b/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll index daa64f2e2ea7..27ab11446b57 100644 --- a/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll +++ b/llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll @@ -2090,3 +2090,99 @@ while.end: ret i32 %res } +; The optimization should be disabled when noimplicitfloat is present. +define i32 @no_implicit_float(ptr %a, ptr %b, i32 %len, i32 %extra, i32 %n) noimplicitfloat { +; CHECK-LABEL: define i32 @no_implicit_float( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[WHILE_COND:%.*]] +; CHECK: while.cond: +; CHECK-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; CHECK-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; CHECK: while.body: +; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; CHECK: while.end: +; CHECK-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; CHECK-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; CHECK-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; CHECK-NEXT: ret i32 [[RES]] +; +; LOOP-DEL-LABEL: define i32 @no_implicit_float( +; LOOP-DEL-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR2:[0-9]+]] { +; LOOP-DEL-NEXT: entry: +; LOOP-DEL-NEXT: br label [[WHILE_COND:%.*]] +; LOOP-DEL: while.cond: +; LOOP-DEL-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; LOOP-DEL-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; LOOP-DEL-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; LOOP-DEL: while.body: +; LOOP-DEL-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; LOOP-DEL-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; LOOP-DEL-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; LOOP-DEL-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; LOOP-DEL-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; LOOP-DEL-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; LOOP-DEL: while.end: +; LOOP-DEL-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; LOOP-DEL-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; LOOP-DEL-NEXT: ret i32 [[RES]] +; +; NO-TRANSFORM-LABEL: define i32 @no_implicit_float( +; NO-TRANSFORM-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[LEN:%.*]], i32 [[EXTRA:%.*]], i32 [[N:%.*]]) #[[ATTR1:[0-9]+]] { +; NO-TRANSFORM-NEXT: entry: +; NO-TRANSFORM-NEXT: br label [[WHILE_COND:%.*]] +; NO-TRANSFORM: while.cond: +; NO-TRANSFORM-NEXT: [[LEN_ADDR:%.*]] = phi i32 [ [[LEN]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[WHILE_BODY:%.*]] ] +; NO-TRANSFORM-NEXT: [[INC]] = add i32 [[LEN_ADDR]], 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[INC]], [[N]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END:%.*]], label [[WHILE_BODY]] +; NO-TRANSFORM: while.body: +; NO-TRANSFORM-NEXT: [[IDXPROM:%.*]] = zext i32 [[INC]] to i64 +; NO-TRANSFORM-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP0:%.*]] = load i8, ptr [[ARRAYIDX]], align 1 +; NO-TRANSFORM-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[IDXPROM]] +; NO-TRANSFORM-NEXT: [[TMP1:%.*]] = load i8, ptr [[ARRAYIDX2]], align 1 +; NO-TRANSFORM-NEXT: [[CMP_NOT2:%.*]] = icmp eq i8 [[TMP0]], [[TMP1]] +; NO-TRANSFORM-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_COND]], label [[WHILE_END]] +; NO-TRANSFORM: while.end: +; NO-TRANSFORM-NEXT: [[INC_LCSSA:%.*]] = phi i32 [ [[INC]], [[WHILE_BODY]] ], [ [[INC]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[EXTRA_PHI:%.*]] = phi i32 [ [[EXTRA]], [[WHILE_BODY]] ], [ [[EXTRA]], [[WHILE_COND]] ] +; NO-TRANSFORM-NEXT: [[RES:%.*]] = add i32 [[INC_LCSSA]], [[EXTRA_PHI]] +; NO-TRANSFORM-NEXT: ret i32 [[RES]] +; +entry: + br label %while.cond + +while.cond: + %len.addr = phi i32 [ %len, %entry ], [ %inc, %while.body ] + %inc = add i32 %len.addr, 1 + %cmp.not = icmp eq i32 %inc, %n + br i1 %cmp.not, label %while.end, label %while.body + +while.body: + %idxprom = zext i32 %inc to i64 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx + %arrayidx2 = getelementptr inbounds i8, ptr %b, i64 %idxprom + %1 = load i8, ptr %arrayidx2 + %cmp.not2 = icmp eq i8 %0, %1 + br i1 %cmp.not2, label %while.cond, label %while.end + +while.end: + %inc.lcssa = phi i32 [ %inc, %while.body ], [ %inc, %while.cond ] + %extra.phi = phi i32 [ %extra, %while.body ], [ %extra, %while.cond ] + %res = add i32 %inc.lcssa, %extra.phi + ret i32 %res +} + -- GitLab From 78c50bbd45de595e9992bf97aa097f7f589f8370 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 8 Apr 2024 09:12:56 -0700 Subject: [PATCH 165/695] [SLP][NFC]Remove unused variable, NFC. --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index b41229e25a34..b48317588ac5 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11169,7 +11169,7 @@ public: VF = std::max(VF, SubVecVF); } // Adjust SubMask. - for (auto [I, Idx] : enumerate(SubMask)) + for (int &Idx : SubMask) if (Idx != PoisonMaskElem) Idx += VF; copy(SubMask, std::next(VecMask.begin(), Part * SliceSize)); -- GitLab From 54c24ec976a52f6ad8499a1a337d7ae2ab84e88d Mon Sep 17 00:00:00 2001 From: Schrodinger ZHU Yifan Date: Mon, 8 Apr 2024 12:53:02 -0400 Subject: [PATCH 166/695] [libc] remove MPFR and related tests in full build (#87693) In full build mode, the fuzzing tests fail to build. This PR disabled MPFR related tests in full build ``` [2/4] Building CXX object projects/libc/fuzzing/stdio/CMakeFiles/libc.fuzzing.stdio.printf_float_conv_fuzz.dir/printf_float_conv_fuzz.cpp.o FAILED: projects/libc/fuzzing/stdio/CMakeFiles/libc.fuzzing.stdio.printf_float_conv_fuzz.dir/printf_float_conv_fuzz.cpp.o /usr/bin/clang++ -DLIBC_NAMESPACE=__llvm_libc_19_0_0_git -I/home/schrodingerzy/Documents/llvm/llvm-project/build/projects/libc/fuzzing/stdio -I/home/schrodingerzy/Documents/llvm/llvm-project/libc/fuzzing/stdio -I/home/schrodingerzy/Documents/llvm/llvm-project/libc -isystem /home/schrodingerzy/Documents/llvm/llvm-project/build/projects/libc/include -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough -Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion -Wmisleading-indentation -Wctad-maybe-unsupported -fdiagnostics-color -ffunction-sections -fdata-sections -fsanitize=fuzzer -O2 -g -DNDEBUG -std=c++17 -MD -MT projects/libc/fuzzing/stdio/CMakeFiles/libc.fuzzing.stdio.printf_float_conv_fuzz.dir/printf_float_conv_fuzz.cpp.o -MF projects/libc/fuzzing/stdio/CMakeFiles/libc.fuzzing.stdio.printf_float_conv_fuzz.dir/printf_float_conv_fuzz.cpp.o.d -o projects/libc/fuzzing/stdio/CMakeFiles/libc.fuzzing.stdio.printf_float_conv_fuzz.dir/printf_float_conv_fuzz.cpp.o -c /home/schrodingerzy/Documents/llvm/llvm-project/libc/fuzzing/stdio/printf_float_conv_fuzz.cpp In file included from /home/schrodingerzy/Documents/llvm/llvm-project/libc/fuzzing/stdio/printf_float_conv_fuzz.cpp:19: In file included from /home/schrodingerzy/Documents/llvm/llvm-project/libc/utils/MPFRWrapper/mpfr_inc.h:21: In file included from /usr/include/mpfr.h:53: In file included from /usr/include/gmp.h:35: In file included from /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/iosfwd:38: In file included from /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/bits/requires_hosted.h:31: In file included from /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/x86_64-pc-linux-gnu/bits/c++config.h:679: /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/x86_64-pc-linux-gnu/bits/os_defines.h:44:5: error: function-like macro '__GLIBC_PREREQ' is not defined 44 | #if __GLIBC_PREREQ(2,15) && defined(_GNU_SOURCE) | ^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/x86_64-pc-linux-gnu/bits/os_defines.h:55:5: error: function-like macro '__GLIBC_PREREQ' is not defined 55 | #if __GLIBC_PREREQ(2, 26) \ | ^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/x86_64-pc-linux-gnu/bits/os_defines.h:66:6: error: function-like macro '__GLIBC_PREREQ' is not defined 66 | # if __GLIBC_PREREQ(2, 27) | ^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/x86_64-pc-linux-gnu/bits/os_defines.h:78:6: error: function-like macro '__GLIBC_PREREQ' is not defined 78 | # if __GLIBC_PREREQ(2, 34) | ^ In file included from /home/schrodingerzy/Documents/llvm/llvm-project/libc/fuzzing/stdio/printf_float_conv_fuzz.cpp:19: In file included from /home/schrodingerzy/Documents/llvm/llvm-project/libc/utils/MPFRWrapper/mpfr_inc.h:21: In file included from /usr/include/mpfr.h:53: In file included from /usr/include/gmp.h:35: In file included from /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/iosfwd:42: In file included from /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/bits/postypes.h:40: /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:64:11: error: no member named 'mbstate_t' in the global namespace 64 | using ::mbstate_t; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:143:11: error: no member named 'btowc' in the global namespace 143 | using ::btowc; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:144:11: error: no member named 'fgetwc' in the global namespace 144 | using ::fgetwc; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:145:11: error: no member named 'fgetws' in the global namespace 145 | using ::fgetws; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:146:11: error: no member named 'fputwc' in the global namespace 146 | using ::fputwc; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:147:11: error: no member named 'fputws' in the global namespace 147 | using ::fputws; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:148:11: error: no member named 'fwide' in the global namespace 148 | using ::fwide; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:149:11: error: no member named 'fwprintf' in the global namespace 149 | using ::fwprintf; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:150:11: error: no member named 'fwscanf' in the global namespace 150 | using ::fwscanf; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:151:11: error: no member named 'getwc' in the global namespace 151 | using ::getwc; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:152:11: error: no member named 'getwchar' in the global namespace 152 | using ::getwchar; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:153:11: error: no member named 'mbrlen' in the global namespace 153 | using ::mbrlen; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:154:11: error: no member named 'mbrtowc' in the global namespace 154 | using ::mbrtowc; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:155:11: error: no member named 'mbsinit' in the global namespace 155 | using ::mbsinit; | ~~^ /usr/bin/../lib64/gcc/x86_64-pc-linux-gnu/13.2.1/../../../../include/c++/13.2.1/cwchar:156:11: error: no member named 'mbsrtowcs' in the global namespace 156 | using ::mbsrtowcs; | ~~^ fatal error: too many errors emitted, stopping now [-ferror-limit=] ``` --- libc/cmake/modules/LLVMLibCCheckMPFR.cmake | 4 +++- libc/utils/MPFRWrapper/CMakeLists.txt | 8 +------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/libc/cmake/modules/LLVMLibCCheckMPFR.cmake b/libc/cmake/modules/LLVMLibCCheckMPFR.cmake index bbaeb9f0dc05..45334a54431e 100644 --- a/libc/cmake/modules/LLVMLibCCheckMPFR.cmake +++ b/libc/cmake/modules/LLVMLibCCheckMPFR.cmake @@ -2,7 +2,9 @@ set(LLVM_LIBC_MPFR_INSTALL_PATH "" CACHE PATH "Path to where MPFR is installed ( if(LLVM_LIBC_MPFR_INSTALL_PATH) set(LIBC_TESTS_CAN_USE_MPFR TRUE) -elseif(LIBC_TARGET_OS_IS_GPU) +elseif(LIBC_TARGET_OS_IS_GPU OR LLVM_LIBC_FULL_BUILD) + # In full build mode, the MPFR library should be built using our own facilities, + # which is currently not possible. set(LIBC_TESTS_CAN_USE_MPFR FALSE) else() try_compile( diff --git a/libc/utils/MPFRWrapper/CMakeLists.txt b/libc/utils/MPFRWrapper/CMakeLists.txt index 2f2b0ac09df9..6af6fd770704 100644 --- a/libc/utils/MPFRWrapper/CMakeLists.txt +++ b/libc/utils/MPFRWrapper/CMakeLists.txt @@ -5,12 +5,6 @@ if(LIBC_TESTS_CAN_USE_MPFR) mpfr_inc.h ) target_compile_options(libcMPFRWrapper PRIVATE -O3) - if (LLVM_LIBC_FULL_BUILD) - # It is not easy to make libcMPFRWrapper a standalone library because gmp.h may unconditionally - # pull in some STL headers. As a result, targets using this library will need to link against - # C++ and unwind libraries. Since we are using MPFR anyway, we directly specifies the GNU toolchain. - target_link_libraries(libcMPFRWrapper PUBLIC -lstdc++ -lgcc_s) - endif() add_dependencies( libcMPFRWrapper libc.src.__support.CPP.string_view @@ -24,6 +18,6 @@ if(LIBC_TESTS_CAN_USE_MPFR) target_link_directories(libcMPFRWrapper PUBLIC ${LLVM_LIBC_MPFR_INSTALL_PATH}/lib) endif() target_link_libraries(libcMPFRWrapper PUBLIC LibcFPTestHelpers.unit LibcTest.unit mpfr gmp) -elseif(NOT LIBC_TARGET_OS_IS_GPU) +elseif(NOT LIBC_TARGET_OS_IS_GPU AND NOT LLVM_LIBC_FULL_BUILD) message(WARNING "Math tests using MPFR will be skipped.") endif() -- GitLab From 896b5e55711121b3de4630fe1412b50d96061c1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Mon, 8 Apr 2024 09:59:12 -0700 Subject: [PATCH 167/695] [flang][cuda] Allow list-directed PRINT and WRITE stmt in device code (#87415) The specification allow list-directed PRINT and WRITE statements to appear in device code. This patch relax the semantic check to allow them. 3.6.11. List-directed PRINT and WRITE statements to the default unit may be used when compiling for compute capability 2.0 and higher; all other uses of PRINT and WRITE are disallowed. --- flang/lib/Semantics/check-cuda.cpp | 64 ++++++++++++++++++++++++++++++ flang/test/Semantics/cuf09.cuf | 8 ++++ 2 files changed, 72 insertions(+) diff --git a/flang/lib/Semantics/check-cuda.cpp b/flang/lib/Semantics/check-cuda.cpp index 39bfc47a8eb1..e0a796972441 100644 --- a/flang/lib/Semantics/check-cuda.cpp +++ b/flang/lib/Semantics/check-cuda.cpp @@ -277,9 +277,73 @@ private: }, ec.u); } + template + static const SEEK *GetIOControl(const A &stmt) { + for (const auto &spec : stmt.controls) { + if (const auto *result{std::get_if(&spec.u)}) { + return result; + } + } + return nullptr; + } + template static bool IsInternalIO(const A &stmt) { + if (stmt.iounit.has_value()) { + return std::holds_alternative(stmt.iounit->u); + } + if (auto *unit{GetIOControl(stmt)}) { + return std::holds_alternative(unit->u); + } + return false; + } + void WarnOnIoStmt(const parser::CharBlock &source) { + context_.Say( + source, "I/O statement might not be supported on device"_warn_en_US); + } + template + void WarnIfNotInternal(const A &stmt, const parser::CharBlock &source) { + if (!IsInternalIO(stmt)) { + WarnOnIoStmt(source); + } + } void Check(const parser::ActionStmt &stmt, const parser::CharBlock &source) { common::visit( common::visitors{ + [&](const common::Indirection &) {}, + [&](const common::Indirection &x) { + if (x.value().format) { // Formatted write to '*' or '6' + if (std::holds_alternative( + x.value().format->u)) { + if (x.value().iounit) { + if (std::holds_alternative( + x.value().iounit->u)) { + return; + } + } + } + } + WarnIfNotInternal(x.value(), source); + }, + [&](const common::Indirection &x) { + WarnOnIoStmt(source); + }, + [&](const common::Indirection &x) { + WarnOnIoStmt(source); + }, + [&](const common::Indirection &x) { + WarnOnIoStmt(source); + }, + [&](const common::Indirection &x) { + WarnIfNotInternal(x.value(), source); + }, + [&](const common::Indirection &x) { + WarnOnIoStmt(source); + }, + [&](const common::Indirection &x) { + WarnOnIoStmt(source); + }, + [&](const common::Indirection &x) { + WarnOnIoStmt(source); + }, [&](const auto &x) { if (auto msg{ActionStmtChecker::WhyNotOk(x)}) { context_.Say(source, std::move(*msg)); diff --git a/flang/test/Semantics/cuf09.cuf b/flang/test/Semantics/cuf09.cuf index 4bc93132044f..d2d4d239815e 100644 --- a/flang/test/Semantics/cuf09.cuf +++ b/flang/test/Semantics/cuf09.cuf @@ -7,6 +7,14 @@ module m do k=1,10 end do end + attributes(device) subroutine devsub2 + real, device :: x(10) + print*,'from device' + print '(f10.5)', (x(ivar), ivar = 1, 10) + write(*,*), "Hello world from device!" + !WARNING: I/O statement might not be supported on device + write(12,'(10F4.1)'), x + end end program main -- GitLab From 39f6d015ddd69717ff1f9b817bce84d621d37731 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Mon, 8 Apr 2024 10:24:27 -0700 Subject: [PATCH 168/695] [RISCV] Eliminate getVLENFactoredAmount and expose muladd [nfc] (#87881) This restructures the code to make the fact that most of getVLENFactoredAmount is just a generic multiply w/immediate more obvious and prepare for a couple of upcoming enhancements to this code. Note that I plan to switch mulImm to early return, but decided I'd do that as a separate commit to keep this diff readable. --------- Co-authored-by: Luke Lau --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 59 +++++++++------------ llvm/lib/Target/RISCV/RISCVInstrInfo.h | 10 ++-- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 11 +++- 3 files changed, 40 insertions(+), 40 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 153f936326a7..be63bc936ae8 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2998,24 +2998,13 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI, #undef CASE_WIDEOP_OPCODE_LMULS #undef CASE_WIDEOP_OPCODE_COMMON -void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator II, - const DebugLoc &DL, Register DestReg, - int64_t Amount, - MachineInstr::MIFlag Flag) const { - assert(Amount > 0 && "There is no need to get VLEN scaled value."); - assert(Amount % 8 == 0 && - "Reserve the stack by the multiple of one vector size."); - +void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator II, const DebugLoc &DL, + Register DestReg, uint32_t Amount, + MachineInstr::MIFlag Flag) const { MachineRegisterInfo &MRI = MF.getRegInfo(); - assert(isInt<32>(Amount / 8) && - "Expect the number of vector registers within 32-bits."); - uint32_t NumOfVReg = Amount / 8; - - BuildMI(MBB, II, DL, get(RISCV::PseudoReadVLENB), DestReg).setMIFlag(Flag); - if (llvm::has_single_bit(NumOfVReg)) { - uint32_t ShiftAmount = Log2_32(NumOfVReg); + if (llvm::has_single_bit(Amount)) { + uint32_t ShiftAmount = Log2_32(Amount); if (ShiftAmount == 0) return; BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) @@ -3023,23 +3012,23 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, .addImm(ShiftAmount) .setMIFlag(Flag); } else if (STI.hasStdExtZba() && - ((NumOfVReg % 3 == 0 && isPowerOf2_64(NumOfVReg / 3)) || - (NumOfVReg % 5 == 0 && isPowerOf2_64(NumOfVReg / 5)) || - (NumOfVReg % 9 == 0 && isPowerOf2_64(NumOfVReg / 9)))) { + ((Amount % 3 == 0 && isPowerOf2_64(Amount / 3)) || + (Amount % 5 == 0 && isPowerOf2_64(Amount / 5)) || + (Amount % 9 == 0 && isPowerOf2_64(Amount / 9)))) { // We can use Zba SHXADD+SLLI instructions for multiply in some cases. unsigned Opc; uint32_t ShiftAmount; - if (NumOfVReg % 9 == 0) { + if (Amount % 9 == 0) { Opc = RISCV::SH3ADD; - ShiftAmount = Log2_64(NumOfVReg / 9); - } else if (NumOfVReg % 5 == 0) { + ShiftAmount = Log2_64(Amount / 9); + } else if (Amount % 5 == 0) { Opc = RISCV::SH2ADD; - ShiftAmount = Log2_64(NumOfVReg / 5); - } else if (NumOfVReg % 3 == 0) { + ShiftAmount = Log2_64(Amount / 5); + } else if (Amount % 3 == 0) { Opc = RISCV::SH1ADD; - ShiftAmount = Log2_64(NumOfVReg / 3); + ShiftAmount = Log2_64(Amount / 3); } else { - llvm_unreachable("Unexpected number of vregs"); + llvm_unreachable("implied by if-clause"); } if (ShiftAmount) BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) @@ -3050,9 +3039,9 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, .addReg(DestReg, RegState::Kill) .addReg(DestReg) .setMIFlag(Flag); - } else if (llvm::has_single_bit(NumOfVReg - 1)) { + } else if (llvm::has_single_bit(Amount - 1)) { Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass); - uint32_t ShiftAmount = Log2_32(NumOfVReg - 1); + uint32_t ShiftAmount = Log2_32(Amount - 1); BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) .addReg(DestReg) .addImm(ShiftAmount) @@ -3061,9 +3050,9 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, .addReg(ScaledRegister, RegState::Kill) .addReg(DestReg, RegState::Kill) .setMIFlag(Flag); - } else if (llvm::has_single_bit(NumOfVReg + 1)) { + } else if (llvm::has_single_bit(Amount + 1)) { Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass); - uint32_t ShiftAmount = Log2_32(NumOfVReg + 1); + uint32_t ShiftAmount = Log2_32(Amount + 1); BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) .addReg(DestReg) .addImm(ShiftAmount) @@ -3074,7 +3063,7 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, .setMIFlag(Flag); } else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) { Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass); - movImm(MBB, II, DL, N, NumOfVReg, Flag); + movImm(MBB, II, DL, N, Amount, Flag); BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg) .addReg(DestReg, RegState::Kill) .addReg(N, RegState::Kill) @@ -3082,14 +3071,14 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF, } else { Register Acc; uint32_t PrevShiftAmount = 0; - for (uint32_t ShiftAmount = 0; NumOfVReg >> ShiftAmount; ShiftAmount++) { - if (NumOfVReg & (1U << ShiftAmount)) { + for (uint32_t ShiftAmount = 0; Amount >> ShiftAmount; ShiftAmount++) { + if (Amount & (1U << ShiftAmount)) { if (ShiftAmount) BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) .addReg(DestReg, RegState::Kill) .addImm(ShiftAmount - PrevShiftAmount) .setMIFlag(Flag); - if (NumOfVReg >> (ShiftAmount + 1)) { + if (Amount >> (ShiftAmount + 1)) { // If we don't have an accmulator yet, create it and copy DestReg. if (!Acc) { Acc = MRI.createVirtualRegister(&RISCV::GPRRegClass); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 3470012d1518..81d9c9db783c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -229,10 +229,12 @@ public: unsigned OpIdx, const TargetRegisterInfo *TRI) const override; - void getVLENFactoredAmount( - MachineFunction &MF, MachineBasicBlock &MBB, - MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, - int64_t Amount, MachineInstr::MIFlag Flag = MachineInstr::NoFlags) const; + /// Generate code to multiply the value in DestReg by Amt - handles all + /// the common optimizations for this idiom, and supports fallback for + /// subtargets which don't support multiply instructions. + void mulImm(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator II, const DebugLoc &DL, + Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const; bool useMachineCombiner() const override { return true; } diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 11c3f2d57eb0..713260b090e9 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -195,7 +195,16 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB, Register ScratchReg = DestReg; if (DestReg == SrcReg) ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); - TII->getVLENFactoredAmount(MF, MBB, II, DL, ScratchReg, ScalableValue, Flag); + + assert(ScalableValue > 0 && "There is no need to get VLEN scaled value."); + assert(ScalableValue % 8 == 0 && + "Reserve the stack by the multiple of one vector size."); + assert(isInt<32>(ScalableValue / 8) && + "Expect the number of vector registers within 32-bits."); + uint32_t NumOfVReg = ScalableValue / 8; + BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), ScratchReg) + .setMIFlag(Flag); + TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag); BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) .addReg(SrcReg).addReg(ScratchReg, RegState::Kill) .setMIFlag(Flag); -- GitLab From d345f6a25343f926f55e70b442dfa507ba31b597 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Mon, 8 Apr 2024 21:32:38 +0400 Subject: [PATCH 169/695] [clang] Introduce `SemaHLSL` (#87912) This patch introduces `SemaHLSL` class, and moves some HLSL-related functions there. No functional changes intended. Removing "HLSL" from function names inside `SemaHLSL` is left for a subsequent PR by HLSL contributors, if they deem that desirable. This is a part of the effort to split `Sema` into smaller manageable parts, and follows the example of OpenACC. See #82217, #84184, #87634 for additional context. --- clang/include/clang/Sema/Sema.h | 40 ++++++++++------------------- clang/include/clang/Sema/SemaHLSL.h | 37 ++++++++++++++++++++++++++ clang/lib/Parse/ParseHLSL.cpp | 11 ++++---- clang/lib/Sema/Sema.cpp | 2 ++ clang/lib/Sema/SemaHLSL.cpp | 24 +++++++++-------- 5 files changed, 73 insertions(+), 41 deletions(-) create mode 100644 clang/include/clang/Sema/SemaHLSL.h diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 56d66a4486e0..3fe2b6dd422a 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -182,6 +182,7 @@ class Preprocessor; class PseudoDestructorTypeStorage; class PseudoObjectExpr; class QualType; +class SemaHLSL; class SemaOpenACC; class StandardConversionSequence; class Stmt; @@ -465,9 +466,8 @@ class Sema final : public SemaBase { // 36. FixIt Helpers (SemaFixItUtils.cpp) // 37. Name Lookup for RISC-V Vector Intrinsic (SemaRISCVVectorLookup.cpp) // 38. CUDA (SemaCUDA.cpp) - // 39. HLSL Constructs (SemaHLSL.cpp) - // 40. OpenMP Directives and Clauses (SemaOpenMP.cpp) - // 41. SYCL Constructs (SemaSYCL.cpp) + // 39. OpenMP Directives and Clauses (SemaOpenMP.cpp) + // 40. SYCL Constructs (SemaSYCL.cpp) /// \name Semantic Analysis /// Implementations are in Sema.cpp @@ -964,6 +964,11 @@ public: /// CurContext - This is the current declaration context of parsing. DeclContext *CurContext; + SemaHLSL &HLSL() { + assert(HLSLPtr); + return *HLSLPtr; + } + SemaOpenACC &OpenACC() { assert(OpenACCPtr); return *OpenACCPtr; @@ -999,6 +1004,7 @@ private: mutable IdentifierInfo *Ident_super; + std::unique_ptr HLSLPtr; std::unique_ptr OpenACCPtr; ///@} @@ -1967,6 +1973,11 @@ public: bool CheckFunctionCall(FunctionDecl *FDecl, CallExpr *TheCall, const FunctionProtoType *Proto); + bool BuiltinVectorMath(CallExpr *TheCall, QualType &Res); + bool BuiltinVectorToScalarMath(CallExpr *TheCall); + + bool CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); + private: void CheckArrayAccess(const Expr *BaseExpr, const Expr *IndexExpr, const ArraySubscriptExpr *ASE = nullptr, @@ -13145,29 +13156,6 @@ private: // // - /// \name HLSL Constructs - /// Implementations are in SemaHLSL.cpp - ///@{ - -public: - Decl *ActOnStartHLSLBuffer(Scope *BufferScope, bool CBuffer, - SourceLocation KwLoc, IdentifierInfo *Ident, - SourceLocation IdentLoc, SourceLocation LBrace); - void ActOnFinishHLSLBuffer(Decl *Dcl, SourceLocation RBrace); - - bool CheckHLSLBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall); - - bool BuiltinVectorMath(CallExpr *TheCall, QualType &Res); - bool BuiltinVectorToScalarMath(CallExpr *TheCall); - - ///@} - - // - // - // ------------------------------------------------------------------------- - // - // - /// \name OpenMP Directives and Clauses /// Implementations are in SemaOpenMP.cpp ///@{ diff --git a/clang/include/clang/Sema/SemaHLSL.h b/clang/include/clang/Sema/SemaHLSL.h new file mode 100644 index 000000000000..acc675963c23 --- /dev/null +++ b/clang/include/clang/Sema/SemaHLSL.h @@ -0,0 +1,37 @@ +//===----- SemaHLSL.h ----- Semantic Analysis for HLSL constructs ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares semantic analysis for HLSL constructs. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_SEMA_SEMAHLSL_H +#define LLVM_CLANG_SEMA_SEMAHLSL_H + +#include "clang/AST/DeclBase.h" +#include "clang/AST/Expr.h" +#include "clang/Basic/IdentifierTable.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Sema/Scope.h" +#include "clang/Sema/SemaBase.h" + +namespace clang { + +class SemaHLSL : public SemaBase { +public: + SemaHLSL(Sema &S); + + Decl *ActOnStartHLSLBuffer(Scope *BufferScope, bool CBuffer, + SourceLocation KwLoc, IdentifierInfo *Ident, + SourceLocation IdentLoc, SourceLocation LBrace); + void ActOnFinishHLSLBuffer(Decl *Dcl, SourceLocation RBrace); +}; + +} // namespace clang + +#endif // LLVM_CLANG_SEMA_SEMAHLSL_H diff --git a/clang/lib/Parse/ParseHLSL.cpp b/clang/lib/Parse/ParseHLSL.cpp index 4fc6a2203cec..5afc958600fa 100644 --- a/clang/lib/Parse/ParseHLSL.cpp +++ b/clang/lib/Parse/ParseHLSL.cpp @@ -15,6 +15,7 @@ #include "clang/Parse/ParseDiagnostic.h" #include "clang/Parse/Parser.h" #include "clang/Parse/RAIIObjectsForParser.h" +#include "clang/Sema/SemaHLSL.h" using namespace clang; @@ -71,9 +72,9 @@ Decl *Parser::ParseHLSLBuffer(SourceLocation &DeclEnd) { return nullptr; } - Decl *D = Actions.ActOnStartHLSLBuffer(getCurScope(), IsCBuffer, BufferLoc, - Identifier, IdentifierLoc, - T.getOpenLocation()); + Decl *D = Actions.HLSL().ActOnStartHLSLBuffer( + getCurScope(), IsCBuffer, BufferLoc, Identifier, IdentifierLoc, + T.getOpenLocation()); while (Tok.isNot(tok::r_brace) && Tok.isNot(tok::eof)) { // FIXME: support attribute on constants inside cbuffer/tbuffer. @@ -87,7 +88,7 @@ Decl *Parser::ParseHLSLBuffer(SourceLocation &DeclEnd) { T.skipToEnd(); DeclEnd = T.getCloseLocation(); BufferScope.Exit(); - Actions.ActOnFinishHLSLBuffer(D, DeclEnd); + Actions.HLSL().ActOnFinishHLSLBuffer(D, DeclEnd); return nullptr; } } @@ -95,7 +96,7 @@ Decl *Parser::ParseHLSLBuffer(SourceLocation &DeclEnd) { T.consumeClose(); DeclEnd = T.getCloseLocation(); BufferScope.Exit(); - Actions.ActOnFinishHLSLBuffer(D, DeclEnd); + Actions.HLSL().ActOnFinishHLSLBuffer(D, DeclEnd); Actions.ProcessDeclAttributeList(Actions.CurScope, D, Attrs); return D; diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 6b8e88e88500..04eadb5f3b8a 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -42,6 +42,7 @@ #include "clang/Sema/Scope.h" #include "clang/Sema/ScopeInfo.h" #include "clang/Sema/SemaConsumer.h" +#include "clang/Sema/SemaHLSL.h" #include "clang/Sema/SemaInternal.h" #include "clang/Sema/SemaOpenACC.h" #include "clang/Sema/TemplateDeduction.h" @@ -198,6 +199,7 @@ Sema::Sema(Preprocessor &pp, ASTContext &ctxt, ASTConsumer &consumer, LateTemplateParser(nullptr), LateTemplateParserCleanup(nullptr), OpaqueParser(nullptr), CurContext(nullptr), ExternalSource(nullptr), CurScope(nullptr), Ident_super(nullptr), + HLSLPtr(std::make_unique(*this)), OpenACCPtr(std::make_unique(*this)), MSPointerToMemberRepresentationMethod( LangOpts.getMSPointerToMemberRepresentationMethod()), diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index cf82cc9bccdf..681849d6e6c8 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -8,27 +8,31 @@ // This implements Semantic Analysis for HLSL constructs. //===----------------------------------------------------------------------===// +#include "clang/Sema/SemaHLSL.h" #include "clang/Sema/Sema.h" using namespace clang; -Decl *Sema::ActOnStartHLSLBuffer(Scope *BufferScope, bool CBuffer, - SourceLocation KwLoc, IdentifierInfo *Ident, - SourceLocation IdentLoc, - SourceLocation LBrace) { +SemaHLSL::SemaHLSL(Sema &S) : SemaBase(S) {} + +Decl *SemaHLSL::ActOnStartHLSLBuffer(Scope *BufferScope, bool CBuffer, + SourceLocation KwLoc, + IdentifierInfo *Ident, + SourceLocation IdentLoc, + SourceLocation LBrace) { // For anonymous namespace, take the location of the left brace. - DeclContext *LexicalParent = getCurLexicalContext(); + DeclContext *LexicalParent = SemaRef.getCurLexicalContext(); HLSLBufferDecl *Result = HLSLBufferDecl::Create( - Context, LexicalParent, CBuffer, KwLoc, Ident, IdentLoc, LBrace); + getASTContext(), LexicalParent, CBuffer, KwLoc, Ident, IdentLoc, LBrace); - PushOnScopeChains(Result, BufferScope); - PushDeclContext(BufferScope, Result); + SemaRef.PushOnScopeChains(Result, BufferScope); + SemaRef.PushDeclContext(BufferScope, Result); return Result; } -void Sema::ActOnFinishHLSLBuffer(Decl *Dcl, SourceLocation RBrace) { +void SemaHLSL::ActOnFinishHLSLBuffer(Decl *Dcl, SourceLocation RBrace) { auto *BufDecl = cast(Dcl); BufDecl->setRBraceLoc(RBrace); - PopDeclContext(); + SemaRef.PopDeclContext(); } -- GitLab From 93e2a9ab1b28e1b89d30b89dc2d5bb6f8cc66dc9 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Mon, 8 Apr 2024 21:55:53 +0400 Subject: [PATCH 170/695] [clang] Add CodeGen tests for CWG 6xx issues (#87876) This patch covers [CWG605](https://cplusplus.github.io/CWG/issues/605.html) "Linkage of explicit specializations", [CWG650](https://cplusplus.github.io/CWG/issues/650.html) "Order of destruction for temporaries bound to the returned value of a function", [CWG653](https://cplusplus.github.io/CWG/issues/653.html) "Copy assignment of unions", [CWG658](https://cplusplus.github.io/CWG/issues/658.html) "Defining `reinterpret_cast` for pointer types", [CWG661](https://cplusplus.github.io/CWG/issues/661.html) "Semantics of arithmetic comparisons", [CWG672](https://cplusplus.github.io/CWG/issues/672.html) "Sequencing of initialization in _new-expression_s". [CWG624](https://cplusplus.github.io/CWG/issues/624.html) "Overflow in calculating size of allocation" and [CWG668](https://cplusplus.github.io/CWG/issues/668.html) "Throwing an exception from the destructor of a local static object" are marked as requiring libc++abi tests. --- clang/test/CXX/drs/dr605.cpp | 23 +++++++++++++++++++++ clang/test/CXX/drs/dr650.cpp | 40 ++++++++++++++++++++++++++++++++++++ clang/test/CXX/drs/dr653.cpp | 25 ++++++++++++++++++++++ clang/test/CXX/drs/dr658.cpp | 25 ++++++++++++++++++++++ clang/test/CXX/drs/dr661.cpp | 29 ++++++++++++++++++++++++++ clang/test/CXX/drs/dr672.cpp | 32 +++++++++++++++++++++++++++++ clang/test/CXX/drs/dr6xx.cpp | 16 +++++++-------- clang/www/cxx_dr_status.html | 12 +++++------ 8 files changed, 188 insertions(+), 14 deletions(-) create mode 100644 clang/test/CXX/drs/dr605.cpp create mode 100644 clang/test/CXX/drs/dr650.cpp create mode 100644 clang/test/CXX/drs/dr653.cpp create mode 100644 clang/test/CXX/drs/dr658.cpp create mode 100644 clang/test/CXX/drs/dr661.cpp create mode 100644 clang/test/CXX/drs/dr672.cpp diff --git a/clang/test/CXX/drs/dr605.cpp b/clang/test/CXX/drs/dr605.cpp new file mode 100644 index 000000000000..6c212d8dabc0 --- /dev/null +++ b/clang/test/CXX/drs/dr605.cpp @@ -0,0 +1,23 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +namespace dr605 { // dr605: 2.7 + +template +static T f(T t) {} + +template <> +int f(int t) {} + +void g(int a) { + f(a); +} + +} // namespace dr605 + +// CHECK: define internal {{.*}} i32 @int dr605::f(int) diff --git a/clang/test/CXX/drs/dr650.cpp b/clang/test/CXX/drs/dr650.cpp new file mode 100644 index 000000000000..715b4fdf04a7 --- /dev/null +++ b/clang/test/CXX/drs/dr650.cpp @@ -0,0 +1,40 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +#if __cplusplus == 199711L +#define NOTHROW throw() +#else +#define NOTHROW noexcept(true) +#endif + +namespace dr650 { // dr650: 2.8 + +struct Q { + ~Q() NOTHROW; +}; + +struct R { + ~R() NOTHROW; +}; + +struct S { + ~S() NOTHROW; +}; + +const S& f() { + Q q; + return (R(), S()); +} + +} // namespace dr650 + +// CHECK-LABEL: define {{.*}} @dr650::f()() +// CHECK: call void @dr650::S::~S() +// CHECK: call void @dr650::R::~R() +// CHECK: call void @dr650::Q::~Q() +// CHECK-LABEL: } diff --git a/clang/test/CXX/drs/dr653.cpp b/clang/test/CXX/drs/dr653.cpp new file mode 100644 index 000000000000..fd1f0153bfb7 --- /dev/null +++ b/clang/test/CXX/drs/dr653.cpp @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +namespace dr653 { // dr653: 2.7 + +union U { + int a; + float b; +}; + +void f(U u) { + U v; + v = u; +} + +} // namespace dr653 + +// CHECK-LABEL: define {{.*}} void @dr653::f(dr653::U) +// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}} %v, ptr {{.*}} %u, {{.*}}) +// CHECK-LABEL: } diff --git a/clang/test/CXX/drs/dr658.cpp b/clang/test/CXX/drs/dr658.cpp new file mode 100644 index 000000000000..51034c2af3bf --- /dev/null +++ b/clang/test/CXX/drs/dr658.cpp @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +namespace dr658 { // dr658: 2.7 + +void f(int* p1) { + char* p2 = reinterpret_cast(p1); +} + +} // namespace dr658 + +// We're checking that p1 is stored into p2 without changes. + +// CHECK-LABEL: define {{.*}} void @dr658::f(int*)(ptr noundef %p1) +// CHECK: [[P1_ADDR:%.+]] = alloca ptr, align 8 +// CHECK-NEXT: [[P2:%.+]] = alloca ptr, align 8 +// CHECK: store ptr %p1, ptr [[P1_ADDR]] +// CHECK-NEXT: [[TEMP:%.+]] = load ptr, ptr [[P1_ADDR]] +// CHECK-NEXT: store ptr [[TEMP]], ptr [[P2]] +// CHECK-LABEL: } diff --git a/clang/test/CXX/drs/dr661.cpp b/clang/test/CXX/drs/dr661.cpp new file mode 100644 index 000000000000..4e97bb708847 --- /dev/null +++ b/clang/test/CXX/drs/dr661.cpp @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +namespace dr661 { + +void f(int a, int b) { // dr661: 2.7 + a == b; + a != b; + a < b; + a <= b; + a > b; + a >= b; +} + +} // namespace dr661 + +// CHECK-LABEL: define {{.*}} void @dr661::f(int, int) +// CHECK: icmp eq +// CHECK: icmp ne +// CHECK: icmp slt +// CHECK: icmp sle +// CHECK: icmp sgt +// CHECK: icmp sge +// CHECK-LABEL: } diff --git a/clang/test/CXX/drs/dr672.cpp b/clang/test/CXX/drs/dr672.cpp new file mode 100644 index 000000000000..d5f0530ecbc9 --- /dev/null +++ b/clang/test/CXX/drs/dr672.cpp @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +#if __cplusplus == 199711L +#define NOTHROW throw() +#else +#define NOTHROW noexcept(true) +#endif + +namespace dr672 { // dr672: 2.7 + +struct A { + A() NOTHROW; +}; + +void f() { + A *a = new A; +} + +} // namespace dr672 + +// CHECK-LABEL: define {{.*}} void @dr672::f()() +// CHECK: [[A:%.+]] = alloca ptr +// CHECK: [[CALL:%.+]] = call {{.*}} ptr @operator new(unsigned long) +// CHECK: call void @dr672::A::A() +// CHECK: store ptr [[CALL]], ptr [[A]] +// CHECK-LABEL: } diff --git a/clang/test/CXX/drs/dr6xx.cpp b/clang/test/CXX/drs/dr6xx.cpp index 190e05784f32..eeb41eee9c30 100644 --- a/clang/test/CXX/drs/dr6xx.cpp +++ b/clang/test/CXX/drs/dr6xx.cpp @@ -81,7 +81,7 @@ namespace dr603 { // dr603: yes } // dr604: na -// dr605 needs IRGen test +// dr605 is in dr605.cpp namespace dr606 { // dr606: 3.0 #if __cplusplus >= 201103L @@ -253,7 +253,7 @@ namespace dr621 { // dr621: yes // dr623: na // FIXME: Add documentation saying we allow invalid pointer values. -// dr624 needs an IRGen check. +// dr624 needs a libc++abi test. namespace dr625 { // dr625: yes template struct A {}; @@ -650,7 +650,7 @@ struct Y { } #endif -// dr650 FIXME: add codegen test +// dr650 is in dr650.cpp #if __cplusplus >= 201103L namespace dr651 { // dr651: yes @@ -672,7 +672,7 @@ namespace dr652 { // dr652: yes } #endif -// dr653 FIXME: add codegen test +// dr653 is in dr653.cpp #if __cplusplus >= 201103L namespace dr654 { // dr654: sup 1423 @@ -798,7 +798,7 @@ namespace dr657 { // dr657: partial Cnvt2::type err; } -// dr658 FIXME: add codegen test +// dr658 is in dr658.cpp #if __cplusplus >= 201103L namespace dr659 { // dr659: 3.0 @@ -829,7 +829,7 @@ namespace dr660 { // dr660: 3.0 } #endif -// dr661 FIXME: add codegen test +// dr661 is in dr661.cpp namespace dr662 { // dr662: yes template void f(T t) { @@ -931,7 +931,7 @@ namespace dr667 { // dr667: 8 } #endif -// dr668 FIXME: add codegen test +// dr668 needs an libc++abi test #if __cplusplus >= 201103L namespace dr669 { // dr669: yes @@ -971,7 +971,7 @@ namespace dr671 { // dr671: 2.9 int m = static_cast(e); } -// dr672 FIXME: add codegen test +// dr672 is in dr672.cpp namespace dr673 { // dr673: yes template struct X { static const int n = 0; }; diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index a4c133c13c49..df0ab414d9a0 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -3672,7 +3672,7 @@ and POD class 605 C++11 Linkage of explicit specializations - Unknown + Clang 2.7 606 @@ -3942,7 +3942,7 @@ and POD class 650 CD2 Order of destruction for temporaries bound to the returned value of a function - Unknown + Clang 2.8 651 @@ -3960,7 +3960,7 @@ and POD class 653 CD2 Copy assignment of unions - Unknown + Clang 2.7 654 @@ -3990,7 +3990,7 @@ and POD class 658 CD2 Defining reinterpret_cast for pointer types - Unknown + Clang 2.7 659 @@ -4008,7 +4008,7 @@ and POD class 661 CD1 Semantics of arithmetic comparisons - Unknown + Clang 2.7 662 @@ -4074,7 +4074,7 @@ and POD class 672 CD2 Sequencing of initialization in new-expressions - Unknown + Clang 2.7 673 -- GitLab From ea2392ed33f765018002f833da9a04cd0571ab83 Mon Sep 17 00:00:00 2001 From: Hristo Hristov Date: Mon, 8 Apr 2024 21:12:31 +0300 Subject: [PATCH 171/695] [libc++][format] Fixed `println.blank_line.sh.cpp` test on llvm-clang-win-x-* configurations (#88011) Fix for issue: https://github.com/llvm/llvm-project/pull/87277#issuecomment-2041864530 The test fails on the windows to linux cross builders. The proposed resolution is to print some text. The issue is possibly due to the original test outputting a single `\n` character. --- .../iostream.format/print.fun/println.blank_line.sh.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp b/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp index 93c3563d501b..a262c287108a 100644 --- a/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp +++ b/libcxx/test/std/input.output/iostream.format/print.fun/println.blank_line.sh.cpp @@ -35,13 +35,15 @@ // FILE_DEPENDENCIES: echo.sh // RUN: %{build} -// RUN: %{exec} bash echo.sh -ne "\n" > %t.expected +// RUN: %{exec} bash echo.sh -ne "println blank line test: \n" > %t.expected // RUN: %{exec} "%t.exe" > %t.actual // RUN: diff -u %t.actual %t.expected #include int main(int, char**) { + // On some configurations the `diff -u` test fails if we print a single blank line character `\n`, so we print some text first. + std::print("println blank line test: "); std::println(); return 0; -- GitLab From 977c0a6d29fe836f75b64a6f08a58cb3c00a56d9 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Mon, 8 Apr 2024 19:18:38 +0100 Subject: [PATCH 172/695] [LAA] Add tests with non-constant strides & distances. Add a number of LAA test cases with both forward and backward dependences with non-constant strides and dependence distances. This includes test coverage for https://github.com/llvm/llvm-project/issues/87336 Also includes a LoopLoadElimination test to make sure the pass does not crash on non-constant dependence distances. --- .../non-constant-strides-backward.ll | 369 ++++++++++++++++++ .../non-constant-strides-forward.ll | 182 +++++++++ ...endence-distance-different-access-sizes.ll | 141 +++++++ .../LoopLoadElim/non-const-distance.ll | 44 +++ 4 files changed, 736 insertions(+) create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-backward.ll create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-forward.ll create mode 100644 llvm/test/Analysis/LoopAccessAnalysis/positive-dependence-distance-different-access-sizes.ll create mode 100644 llvm/test/Transforms/LoopLoadElim/non-const-distance.ll diff --git a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-backward.ll b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-backward.ll new file mode 100644 index 000000000000..416742a94e0d --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-backward.ll @@ -0,0 +1,369 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +declare void @llvm.assume(i1) + +define void @different_non_constant_strides_known_backward(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep.mul.2, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_distance_larger_than_trip_count(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_distance_larger_than_trip_count' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep.mul.2, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.1024 = getelementptr inbounds i8, ptr %A, i64 1024 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A.1024, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_min_distance_16(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_min_distance_16' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep.mul.2, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.16 = getelementptr inbounds i8, ptr %A, i64 16 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A.16, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_min_distance_15(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_min_distance_15' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep.mul.2, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.15 = getelementptr inbounds i8, ptr %A, i64 15 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A.15, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_min_distance_8(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_min_distance_8' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep.mul.2, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.8 = getelementptr inbounds i8, ptr %A, i64 8 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A.8, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_min_distance_3(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_min_distance_3' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep.mul.2, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.3 = getelementptr inbounds i8, ptr %A, i64 3 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A.3, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_via_assume(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_via_assume' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %scale, 0 + call void @llvm.assume(i1 %c) + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_via_assume_distance_larger_than_trip_count(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_via_assume_distance_larger_than_trip_count' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.1024 = getelementptr inbounds i8, ptr %A, i64 1024 + %c = icmp sgt i64 %scale, 0 + call void @llvm.assume(i1 %c) + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A.1024, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_backward_via_assume_min_distance_3(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_known_backward_via_assume_min_distance_3' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.3 = getelementptr inbounds i8, ptr %A, i64 3 + %c = icmp sgt i64 %scale, 0 + call void @llvm.assume(i1 %c) + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A.3, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_not_known_backward(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_not_known_backward' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + %l = load i32, ptr %gep, align 4 + %add = add nsw i32 %l, 5 + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv.mul.2 + store i32 %add, ptr %gep.mul.2, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-forward.ll b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-forward.ll new file mode 100644 index 000000000000..aa22a2143352 --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-strides-forward.ll @@ -0,0 +1,182 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +declare void @llvm.assume(i1) + +define void @different_non_constant_strides_known_forward(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_forward' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep.mul.2, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv.mul.2 + %l = load i32, ptr %gep.mul.2, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_forward_min_distance_3(ptr %A) { +; CHECK-LABEL: 'different_non_constant_strides_known_forward_min_distance_3' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop +; CHECK-NEXT: Unknown data dependence. +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Unknown: +; CHECK-NEXT: %l = load i32, ptr %gep.mul.2, align 4 -> +; CHECK-NEXT: store i32 %add, ptr %gep, align 4 +; CHECK-EMPTY: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.3 = getelementptr inbounds i8, ptr %A, i64 3 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.mul.2 = shl nuw nsw i64 %iv, 1 + %gep.mul.2 = getelementptr inbounds i32, ptr %A.3, i64 %iv.mul.2 + %l = load i32, ptr %gep.mul.2, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_forward_via_assume(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_known_forward_via_assume' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %scale, 0 + call void @llvm.assume(i1 %c) + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv.mul.2 + %l = load i32, ptr %gep.mul.2, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_known_forward_via_assume_min_distance_3(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_known_forward_via_assume_min_distance_3' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.3 = getelementptr inbounds i8, ptr %A, i64 3 + %c = icmp sgt i64 %scale, 0 + call void @llvm.assume(i1 %c) + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A.3, i64 %iv.mul.2 + %l = load i32, ptr %gep.mul.2, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} + +define void @different_non_constant_strides_not_known_forward(ptr %A, i64 %scale) { +; CHECK-LABEL: 'different_non_constant_strides_not_known_forward' +; CHECK-NEXT: loop: +; CHECK-NEXT: Report: cannot identify array bounds +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Grouped accesses: +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.mul.2 = shl nuw nsw i64 %iv, %scale + %gep.mul.2 = getelementptr inbounds i32, ptr %A, i64 %iv.mul.2 + %l = load i32, ptr %gep.mul.2, align 4 + %add = add nsw i32 %l, 5 + %gep = getelementptr inbounds i32, ptr %A, i64 %iv + store i32 %add, ptr %gep, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %exitcond.not = icmp eq i64 %iv.next, 256 + br i1 %exitcond.not, label %exit, label %loop + +exit: + ret void +} diff --git a/llvm/test/Analysis/LoopAccessAnalysis/positive-dependence-distance-different-access-sizes.ll b/llvm/test/Analysis/LoopAccessAnalysis/positive-dependence-distance-different-access-sizes.ll new file mode 100644 index 000000000000..08e0bae7f05b --- /dev/null +++ b/llvm/test/Analysis/LoopAccessAnalysis/positive-dependence-distance-different-access-sizes.ll @@ -0,0 +1,141 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; TODO: No runtime checks should be needed, as the distance between accesses +; is large enough to need runtime checks. +define void @test_distance_positive_independent_via_trip_count(ptr %A) { +; CHECK-LABEL: 'test_distance_positive_independent_via_trip_count' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.A.400 = getelementptr inbounds i32, ptr %A.400, i64 %iv +; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP1]]: +; CHECK-NEXT: (Low: (400 + %A) High: (804 + %A)) +; CHECK-NEXT: Member: {(400 + %A),+,4}<%loop> +; CHECK-NEXT: Group [[GRP2]]: +; CHECK-NEXT: (Low: %A High: (101 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.400 = getelementptr inbounds i8, ptr %A, i64 400 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.A.400 = getelementptr inbounds i32, ptr %A.400, i64 %iv + %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8, ptr %gep.A, align 1 + %ext = zext i8 %l to i32 + store i32 %ext, ptr %gep.A.400, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv, 100 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +; TODO: Currently this is considered vectorizable with runtime checks, but the +; runtime checks are never true. +define void @test_distance_positive_backwards(ptr %A) { +; CHECK-LABEL: 'test_distance_positive_backwards' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.A.400 = getelementptr inbounds i32, ptr %A.1, i64 %iv +; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP3]]: +; CHECK-NEXT: (Low: (1 + %A) High: (405 + %A)) +; CHECK-NEXT: Member: {(1 + %A),+,4}<%loop> +; CHECK-NEXT: Group [[GRP4]]: +; CHECK-NEXT: (Low: %A High: (101 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %A.1 = getelementptr inbounds i8, ptr %A, i64 1 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.A.400 = getelementptr inbounds i32, ptr %A.1, i64 %iv + %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8, ptr %gep.A, align 1 + %ext = zext i8 %l to i32 + store i32 %ext, ptr %gep.A.400, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv, 100 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +define void @test_distance_positive_via_assume(ptr %A, i64 %off) { +; CHECK-LABEL: 'test_distance_positive_via_assume' +; CHECK-NEXT: loop: +; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Dependences: +; CHECK-NEXT: Run-time memory checks: +; CHECK-NEXT: Check 0: +; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.A.400 = getelementptr inbounds i32, ptr %A.off, i64 %iv +; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): +; CHECK-NEXT: %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv +; CHECK-NEXT: Grouped accesses: +; CHECK-NEXT: Group [[GRP5]]: +; CHECK-NEXT: (Low: (%off + %A) High: (404 + %off + %A)) +; CHECK-NEXT: Member: {(%off + %A),+,4}<%loop> +; CHECK-NEXT: Group [[GRP6]]: +; CHECK-NEXT: (Low: %A High: (101 + %A)) +; CHECK-NEXT: Member: {%A,+,1}<%loop> +; CHECK-EMPTY: +; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. +; CHECK-NEXT: SCEV assumptions: +; CHECK-EMPTY: +; CHECK-NEXT: Expressions re-written: +; +entry: + %c = icmp sgt i64 %off, 0 + call void @llvm.assume(i1 %c) + %A.off = getelementptr inbounds i8, ptr %A, i64 %off + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.A.400 = getelementptr inbounds i32, ptr %A.off, i64 %iv + %gep.A = getelementptr inbounds i8, ptr %A, i64 %iv + %l = load i8, ptr %gep.A, align 1 + %ext = zext i8 %l to i32 + store i32 %ext, ptr %gep.A.400, align 4 + %iv.next = add nuw nsw i64 %iv, 1 + %ec = icmp eq i64 %iv, 100 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +declare void @llvm.assume(i1) diff --git a/llvm/test/Transforms/LoopLoadElim/non-const-distance.ll b/llvm/test/Transforms/LoopLoadElim/non-const-distance.ll new file mode 100644 index 000000000000..b97d4c23c73d --- /dev/null +++ b/llvm/test/Transforms/LoopLoadElim/non-const-distance.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=loop-load-elim -S %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +define void @non_const_distance(i64 %start, ptr %A, i1 %c) { +; CHECK-LABEL: define void @non_const_distance( +; CHECK-SAME: i64 [[START:%.*]], ptr [[A:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C]], i64 1, i64 0 +; CHECK-NEXT: [[SEL_NOT:%.*]] = xor i64 [[SEL]], -1 +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[START]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[A]], [[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr i32, ptr [[PTR_IV]], i64 [[SEL_NOT]] +; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[ADD_PTR]], align 4 +; CHECK-NEXT: store i32 [[L]], ptr [[PTR_IV]], align 4 +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1000 +; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %sel = select i1 %c, i64 1, i64 0 + %sel.not = xor i64 %sel, -1 + br label %loop + +loop: + %iv = phi i64 [ %start, %entry ], [ %iv.next, %loop ] + %ptr.iv = phi ptr [ %A, %entry ], [ %ptr.iv.next, %loop ] + %add.ptr = getelementptr i32, ptr %ptr.iv, i64 %sel.not + %l = load i32, ptr %add.ptr, align 4 + store i32 %l, ptr %ptr.iv, align 4 + %iv.next = add i64 %iv, 1 + %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 + %ec = icmp eq i64 %iv, 1000 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} -- GitLab From 125c9cf1b2f5d1b33884ddcd33ce983b2e927d2f Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Mon, 8 Apr 2024 22:36:41 +0400 Subject: [PATCH 173/695] [clang] Add test for CWG593 (#87752) [CWG593](https://cplusplus.github.io/CWG/issues/593.html) "Falling off the end of a destructor's function-try-block handler". As usual with CWG issues resolved as NAD, we test for status-quo confirmed by CWG. --- clang/test/CXX/drs/dr593.cpp | 35 +++++++++++++++++++++++++++++++++++ clang/test/CXX/drs/dr5xx.cpp | 2 +- clang/www/cxx_dr_status.html | 2 +- 3 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 clang/test/CXX/drs/dr593.cpp diff --git a/clang/test/CXX/drs/dr593.cpp b/clang/test/CXX/drs/dr593.cpp new file mode 100644 index 000000000000..4998af966ebb --- /dev/null +++ b/clang/test/CXX/drs/dr593.cpp @@ -0,0 +1,35 @@ +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK + +#if __cplusplus == 199711L +#define NOTHROW throw() +#else +#define NOTHROW noexcept(true) +#endif + +namespace dr593 { // dr593: 2.8 + +void f(); +void fence() NOTHROW; + +struct A { + ~A() try { + f(); + } catch (...) { + fence(); + } +}; + +void g() { + A(); +} + +} // namespace dr593 + +// CHECK: call void @dr593::fence()() +// CHECK-NEXT: invoke void @__cxa_rethrow() diff --git a/clang/test/CXX/drs/dr5xx.cpp b/clang/test/CXX/drs/dr5xx.cpp index 426b368b390a..0ea306a04116 100644 --- a/clang/test/CXX/drs/dr5xx.cpp +++ b/clang/test/CXX/drs/dr5xx.cpp @@ -1098,7 +1098,7 @@ namespace dr591 { // dr591: no } // dr592: na -// dr593 needs an IRGen test. +// dr593 is in dr593.cpp // dr594: na namespace dr595 { // dr595: dup 1330 diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index df0ab414d9a0..6daa5ad2d131 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -3600,7 +3600,7 @@ and POD class 593 NAD Falling off the end of a destructor's function-try-block handler - Unknown + Clang 2.8 594 -- GitLab From fd2ffc1cbf51a75884369ec9253f47ae2fdba83c Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Mon, 8 Apr 2024 22:37:48 +0400 Subject: [PATCH 174/695] [clang] Reject incomplete types in `__is_layout_compatible()` (#87869) This is a follow-up to #81506. As discussed in #87737, we're rejecting incomplete types, save for exceptions listed in the C++ standard (`void` and arrays of unknown bound). Note that arrays of unknown bound of incomplete types are accepted. Since we're happy with the current behavior of this intrinsic for flexible array members (https://github.com/llvm/llvm-project/pull/87737#discussion_r1553652570), I added a couple of tests for that as well. --- clang/lib/Sema/SemaExprCXX.cpp | 5 ++++ clang/test/SemaCXX/type-traits.cpp | 39 +++++++++++++++++++++++++----- 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index cfb5c6b6f283..901c3c4d00cf 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -6025,6 +6025,11 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, QualType LhsT, return false; } case BTT_IsLayoutCompatible: { + if (!LhsT->isVoidType() && !LhsT->isIncompleteArrayType()) + Self.RequireCompleteType(KeyLoc, LhsT, diag::err_incomplete_type); + if (!RhsT->isVoidType() && !RhsT->isIncompleteArrayType()) + Self.RequireCompleteType(KeyLoc, RhsT, diag::err_incomplete_type); + if (LhsT->isVariableArrayType() || RhsT->isVariableArrayType()) Self.Diag(KeyLoc, diag::err_vla_unsupported) << 1 << tok::kw___is_layout_compatible; diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index e99ad11666e5..e29763714341 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -1622,7 +1622,7 @@ enum class EnumClassLayout {}; enum EnumForward : int; enum class EnumClassForward; -struct CStructIncomplete; +struct CStructIncomplete; // #CStructIncomplete struct CStructNested { int a; @@ -1719,6 +1719,20 @@ struct StructWithAnonUnion3 { } u; }; +struct CStructWithArrayAtTheEnd { + int a; + int b[4]; +}; + +struct CStructWithFMA { + int c; + int d[]; +}; + +struct CStructWithFMA2 { + int e; + int f[]; +}; void is_layout_compatible(int n) { @@ -1800,15 +1814,28 @@ void is_layout_compatible(int n) static_assert(__is_layout_compatible(EnumLayout, EnumClassLayout)); static_assert(__is_layout_compatible(EnumForward, EnumForward)); static_assert(__is_layout_compatible(EnumForward, EnumClassForward)); - // Layout compatibility for enums might be relaxed in the future. See https://github.com/cplusplus/CWG/issues/39#issuecomment-1184791364 + static_assert(__is_layout_compatible(CStructIncomplete, CStructIncomplete)); + // expected-error@-1 {{incomplete type 'CStructIncomplete' where a complete type is required}} + // expected-note@#CStructIncomplete {{forward declaration of 'CStructIncomplete'}} + // expected-error@-3 {{incomplete type 'CStructIncomplete' where a complete type is required}} + // expected-note@#CStructIncomplete {{forward declaration of 'CStructIncomplete'}} + static_assert(!__is_layout_compatible(CStruct, CStructIncomplete)); + // expected-error@-1 {{incomplete type 'CStructIncomplete' where a complete type is required}} + // expected-note@#CStructIncomplete {{forward declaration of 'CStructIncomplete'}} + static_assert(__is_layout_compatible(CStructIncomplete[2], CStructIncomplete[2])); + // expected-error@-1 {{incomplete type 'CStructIncomplete[2]' where a complete type is required}} + // expected-note@#CStructIncomplete {{forward declaration of 'CStructIncomplete'}} + // expected-error@-3 {{incomplete type 'CStructIncomplete[2]' where a complete type is required}} + // expected-note@#CStructIncomplete {{forward declaration of 'CStructIncomplete'}} + static_assert(__is_layout_compatible(CStructIncomplete[], CStructIncomplete[])); + static_assert(!__is_layout_compatible(CStructWithArrayAtTheEnd, CStructWithFMA)); + static_assert(__is_layout_compatible(CStructWithFMA, CStructWithFMA)); + static_assert(__is_layout_compatible(CStructWithFMA, CStructWithFMA2)); + // Layout compatibility rules for enums might be relaxed in the future. See https://github.com/cplusplus/CWG/issues/39#issuecomment-1184791364 static_assert(!__is_layout_compatible(EnumLayout, int)); static_assert(!__is_layout_compatible(EnumClassLayout, int)); static_assert(!__is_layout_compatible(EnumForward, int)); static_assert(!__is_layout_compatible(EnumClassForward, int)); - // FIXME: the following should be rejected (array of unknown bound and void are the only allowed incomplete types) - static_assert(__is_layout_compatible(CStructIncomplete, CStructIncomplete)); - static_assert(!__is_layout_compatible(CStruct, CStructIncomplete)); - static_assert(__is_layout_compatible(CStructIncomplete[2], CStructIncomplete[2])); } void is_signed() -- GitLab From eeedb1e962977caeb699ef9aa714c8878c4d62d2 Mon Sep 17 00:00:00 2001 From: "Kevin P. Neal" Date: Wed, 26 Jul 2023 11:39:17 -0400 Subject: [PATCH 175/695] [FPEnv][X86] Correct one more strictfp test. Correct a strictfp test to follow the rules documented in the LangRef: https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics This test needed the strictfp attribute added to some function definitions. FP wait instructions now appear as a result. The need for the wait instructions is explained by Andy Kaylor in PR#87791: https://github.com/llvm/llvm-project/pull/87791 Test changes verified with D146845. --- .../CodeGen/X86/i128-fpconv-win64-strict.ll | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/llvm/test/CodeGen/X86/i128-fpconv-win64-strict.ll b/llvm/test/CodeGen/X86/i128-fpconv-win64-strict.ll index 7f7ea09dbc0c..64869da48e6c 100644 --- a/llvm/test/CodeGen/X86/i128-fpconv-win64-strict.ll +++ b/llvm/test/CodeGen/X86/i128-fpconv-win64-strict.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64 ; RUN: llc < %s -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=WIN64 -define i64 @double_to_i128(double %d) nounwind { +define i64 @double_to_i128(double %d) nounwind strictfp { ; WIN64-LABEL: double_to_i128: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $40, %rsp @@ -15,7 +15,7 @@ define i64 @double_to_i128(double %d) nounwind { ret i64 %2 } -define i64 @double_to_ui128(double %d) nounwind { +define i64 @double_to_ui128(double %d) nounwind strictfp { ; WIN64-LABEL: double_to_ui128: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $40, %rsp @@ -28,7 +28,7 @@ define i64 @double_to_ui128(double %d) nounwind { ret i64 %2 } -define i64 @float_to_i128(float %d) nounwind { +define i64 @float_to_i128(float %d) nounwind strictfp { ; WIN64-LABEL: float_to_i128: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $40, %rsp @@ -41,7 +41,7 @@ define i64 @float_to_i128(float %d) nounwind { ret i64 %2 } -define i64 @float_to_ui128(float %d) nounwind { +define i64 @float_to_ui128(float %d) nounwind strictfp { ; WIN64-LABEL: float_to_ui128: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $40, %rsp @@ -54,12 +54,13 @@ define i64 @float_to_ui128(float %d) nounwind { ret i64 %2 } -define i64 @longdouble_to_i128(ptr nocapture readonly %0) nounwind { +define i64 @longdouble_to_i128(ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: longdouble_to_i128: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $56, %rsp ; WIN64-NEXT: fldt (%rcx) ; WIN64-NEXT: fstpt {{[0-9]+}}(%rsp) +; WIN64-NEXT: wait ; WIN64-NEXT: leaq {{[0-9]+}}(%rsp), %rcx ; WIN64-NEXT: callq __fixxfti ; WIN64-NEXT: movq %xmm0, %rax @@ -71,12 +72,13 @@ define i64 @longdouble_to_i128(ptr nocapture readonly %0) nounwind { ret i64 %4 } -define i64 @longdouble_to_ui128(ptr nocapture readonly %0) nounwind { +define i64 @longdouble_to_ui128(ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: longdouble_to_ui128: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $56, %rsp ; WIN64-NEXT: fldt (%rcx) ; WIN64-NEXT: fstpt {{[0-9]+}}(%rsp) +; WIN64-NEXT: wait ; WIN64-NEXT: leaq {{[0-9]+}}(%rsp), %rcx ; WIN64-NEXT: callq __fixunsxfti ; WIN64-NEXT: movq %xmm0, %rax @@ -88,7 +90,7 @@ define i64 @longdouble_to_ui128(ptr nocapture readonly %0) nounwind { ret i64 %4 } -define double @i128_to_double(ptr nocapture readonly %0) nounwind { +define double @i128_to_double(ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: i128_to_double: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $56, %rsp @@ -103,7 +105,7 @@ define double @i128_to_double(ptr nocapture readonly %0) nounwind { ret double %3 } -define double @ui128_to_double(ptr nocapture readonly %0) nounwind { +define double @ui128_to_double(ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: ui128_to_double: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $56, %rsp @@ -118,7 +120,7 @@ define double @ui128_to_double(ptr nocapture readonly %0) nounwind { ret double %3 } -define float @i128_to_float(ptr nocapture readonly %0) nounwind { +define float @i128_to_float(ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: i128_to_float: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $56, %rsp @@ -133,7 +135,7 @@ define float @i128_to_float(ptr nocapture readonly %0) nounwind { ret float %3 } -define float @ui128_to_float(ptr nocapture readonly %0) nounwind { +define float @ui128_to_float(ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: ui128_to_float: ; WIN64: # %bb.0: ; WIN64-NEXT: subq $56, %rsp @@ -148,7 +150,7 @@ define float @ui128_to_float(ptr nocapture readonly %0) nounwind { ret float %3 } -define void @i128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 %agg.result, ptr nocapture readonly %0) nounwind { +define void @i128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 %agg.result, ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: i128_to_longdouble: ; WIN64: # %bb.0: ; WIN64-NEXT: pushq %rsi @@ -161,6 +163,7 @@ define void @i128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 %a ; WIN64-NEXT: callq __floattixf ; WIN64-NEXT: fldt {{[0-9]+}}(%rsp) ; WIN64-NEXT: fstpt (%rsi) +; WIN64-NEXT: wait ; WIN64-NEXT: movq %rsi, %rax ; WIN64-NEXT: addq $64, %rsp ; WIN64-NEXT: popq %rsi @@ -171,7 +174,7 @@ define void @i128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 %a ret void } -define void @ui128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 %agg.result, ptr nocapture readonly %0) nounwind { +define void @ui128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 %agg.result, ptr nocapture readonly %0) nounwind strictfp { ; WIN64-LABEL: ui128_to_longdouble: ; WIN64: # %bb.0: ; WIN64-NEXT: pushq %rsi @@ -184,6 +187,7 @@ define void @ui128_to_longdouble(ptr noalias nocapture sret(x86_fp80) align 16 % ; WIN64-NEXT: callq __floatuntixf ; WIN64-NEXT: fldt {{[0-9]+}}(%rsp) ; WIN64-NEXT: fstpt (%rsi) +; WIN64-NEXT: wait ; WIN64-NEXT: movq %rsi, %rax ; WIN64-NEXT: addq $64, %rsp ; WIN64-NEXT: popq %rsi -- GitLab From 92ecc22b8d18ad937053177533bd23c775556be6 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:53:49 -0700 Subject: [PATCH 176/695] [flang] Fix crash in semantics on bad program (#87199) Don't accept a putative statement function definition for a symbol that is a subprogram but can't possibly be a statement function. Fixes https://github.com/llvm/llvm-project/issues/86936. --- flang/lib/Semantics/resolve-names.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 2e88a2daff2c..f2db329e30be 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -8525,7 +8525,9 @@ void ResolveNamesVisitor::AnalyzeStmtFunctionStmt( Symbol *symbol{name.symbol}; auto *details{symbol ? symbol->detailsIf() : nullptr}; if (!details || !symbol->scope() || - &symbol->scope()->parent() != &currScope()) { + &symbol->scope()->parent() != &currScope() || details->isInterface() || + details->isDummy() || details->entryScope() || + details->moduleInterface() || symbol->test(Symbol::Flag::Subroutine)) { return; // error recovery } // Resolve the symbols on the RHS of the statement function. -- GitLab From b685597c0373882e58dabf587581d00989e40f71 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:54:13 -0700 Subject: [PATCH 177/695] [flang] Fix crash in reduction folding (#87201) A reduction folding template assumed lower bounds were 1. Fixes https://github.com/llvm/llvm-project/issues/86935. --- flang/lib/Evaluate/fold-reduction.h | 24 +++++++++++++----------- flang/test/Evaluate/folding32.f90 | 6 ++++++ 2 files changed, 19 insertions(+), 11 deletions(-) create mode 100644 flang/test/Evaluate/folding32.f90 diff --git a/flang/lib/Evaluate/fold-reduction.h b/flang/lib/Evaluate/fold-reduction.h index 1ee957c0faeb..c84d35734ab5 100644 --- a/flang/lib/Evaluate/fold-reduction.h +++ b/flang/lib/Evaluate/fold-reduction.h @@ -182,25 +182,27 @@ static Constant DoReduction(const Constant &array, ConstantSubscript &maskDimAt{maskAt[*dim - 1]}; ConstantSubscript maskDimLbound{maskDimAt}; for (auto n{GetSize(resultShape)}; n-- > 0; - IncrementSubscripts(at, array.shape()), - IncrementSubscripts(maskAt, mask.shape())) { - dimAt = dimLbound; - maskDimAt = maskDimLbound; + array.IncrementSubscripts(at), mask.IncrementSubscripts(maskAt)) { elements.push_back(identity); - bool firstUnmasked{true}; - for (ConstantSubscript j{0}; j < dimExtent; ++j, ++dimAt, ++maskDimAt) { - if (mask.At(maskAt).IsTrue()) { - accumulator(elements.back(), at, firstUnmasked); - firstUnmasked = false; + if (dimExtent > 0) { + dimAt = dimLbound; + maskDimAt = maskDimLbound; + bool firstUnmasked{true}; + for (ConstantSubscript j{0}; j < dimExtent; ++j, ++dimAt, ++maskDimAt) { + if (mask.At(maskAt).IsTrue()) { + accumulator(elements.back(), at, firstUnmasked); + firstUnmasked = false; + } } + --dimAt, --maskDimAt; } accumulator.Done(elements.back()); } } else { // no DIM=, result is scalar elements.push_back(identity); bool firstUnmasked{true}; - for (auto n{array.size()}; n-- > 0; IncrementSubscripts(at, array.shape()), - IncrementSubscripts(maskAt, mask.shape())) { + for (auto n{array.size()}; n-- > 0; + array.IncrementSubscripts(at), mask.IncrementSubscripts(maskAt)) { if (mask.At(maskAt).IsTrue()) { accumulator(elements.back(), at, firstUnmasked); firstUnmasked = false; diff --git a/flang/test/Evaluate/folding32.f90 b/flang/test/Evaluate/folding32.f90 new file mode 100644 index 000000000000..e4c8b26ca8fd --- /dev/null +++ b/flang/test/Evaluate/folding32.f90 @@ -0,0 +1,6 @@ +! RUN: %python %S/test_folding.py %s %flang_fc1 +! Fold NORM2 reduction of array with non-default lower bound +module m + real, parameter :: a(2:3) = 0.0 + logical, parameter :: test1 = norm2(a) == 0. +end -- GitLab From af61d08280a90becb5a710a812f0d3d6485737a8 Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:54:37 -0700 Subject: [PATCH 178/695] [flang] Handle forward reference to shadowing derived type from IMPLICIT (#87280) A derived type name in an IMPLICIT statement might be a host association or it might be a forward reference to a local derived type, which may be shadowing a host-associated name. Add a scan over the specification part in search of derived type definitions to determine the right interpretation. Fixes https://github.com/llvm/llvm-project/issues/87215. --- flang/lib/Semantics/resolve-names.cpp | 65 +++++++++++++++++++++++++++ flang/test/Semantics/resolve29.f90 | 12 +++++ 2 files changed, 77 insertions(+) diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index f2db329e30be..b04de2648017 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -1635,6 +1635,8 @@ private: void FinishDerivedTypeInstantiation(Scope &); void ResolveExecutionParts(const ProgramTree &); void UseCUDABuiltinNames(); + void HandleDerivedTypesInImplicitStmts(const parser::ImplicitPart &, + const std::list &); }; // ImplicitRules implementation @@ -2035,6 +2037,7 @@ bool ImplicitRulesVisitor::Pre(const parser::ImplicitSpec &) { } void ImplicitRulesVisitor::Post(const parser::ImplicitSpec &) { + set_allowForwardReferenceToDerivedType(false); EndDeclTypeSpec(); } @@ -8329,6 +8332,67 @@ static bool NeedsExplicitType(const Symbol &symbol) { } } +void ResolveNamesVisitor::HandleDerivedTypesInImplicitStmts( + const parser::ImplicitPart &implicitPart, + const std::list &decls) { + // Detect derived type definitions and create symbols for them now if + // they appear in IMPLICIT statements so that these forward-looking + // references will not be ambiguous with host associations. + std::set implicitDerivedTypes; + for (const auto &ipStmt : implicitPart.v) { + if (const auto *impl{std::get_if< + parser::Statement>>( + &ipStmt.u)}) { + if (const auto *specs{std::get_if>( + &impl->statement.value().u)}) { + for (const auto &spec : *specs) { + const auto &declTypeSpec{ + std::get(spec.t)}; + if (const auto *dtSpec{common::visit( + common::visitors{ + [](const parser::DeclarationTypeSpec::Type &x) { + return &x.derived; + }, + [](const parser::DeclarationTypeSpec::Class &x) { + return &x.derived; + }, + [](const auto &) -> const parser::DerivedTypeSpec * { + return nullptr; + }}, + declTypeSpec.u)}) { + implicitDerivedTypes.emplace( + std::get(dtSpec->t).source); + } + } + } + } + } + if (!implicitDerivedTypes.empty()) { + for (const auto &decl : decls) { + if (const auto *spec{ + std::get_if(&decl.u)}) { + if (const auto *dtDef{ + std::get_if>( + &spec->u)}) { + const parser::DerivedTypeStmt &dtStmt{ + std::get>( + dtDef->value().t) + .statement}; + const parser::Name &name{std::get(dtStmt.t)}; + if (implicitDerivedTypes.find(name.source) != + implicitDerivedTypes.end() && + !FindInScope(name)) { + DerivedTypeDetails details; + details.set_isForwardReferenced(true); + Resolve(name, MakeSymbol(name, std::move(details))); + implicitDerivedTypes.erase(name.source); + } + } + } + } + } +} + bool ResolveNamesVisitor::Pre(const parser::SpecificationPart &x) { const auto &[accDecls, ompDecls, compilerDirectives, useStmts, importStmts, implicitPart, decls] = x.t; @@ -8347,6 +8411,7 @@ bool ResolveNamesVisitor::Pre(const parser::SpecificationPart &x) { ClearUseOnly(); ClearModuleUses(); Walk(importStmts); + HandleDerivedTypesInImplicitStmts(implicitPart, decls); Walk(implicitPart); for (const auto &decl : decls) { if (const auto *spec{ diff --git a/flang/test/Semantics/resolve29.f90 b/flang/test/Semantics/resolve29.f90 index 3e6a8a0ba697..c6a9b036c582 100644 --- a/flang/test/Semantics/resolve29.f90 +++ b/flang/test/Semantics/resolve29.f90 @@ -3,6 +3,7 @@ module m1 type t1 end type type t3 + integer t3c end type interface subroutine s1(x) @@ -64,6 +65,17 @@ contains end type type(t2) x end + subroutine s10() + !Forward shadowing derived type in IMPLICIT + !(supported by all other compilers) + implicit type(t1) (c) ! forward shadow + implicit type(t3) (d) ! host associated + type t1 + integer a + end type + c%a = 1 + d%t3c = 2 + end end module module m2 integer, parameter :: ck = kind('a') -- GitLab From aace1e1719a1610ce9fa93c7dae38a4272d7b6bf Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:55:03 -0700 Subject: [PATCH 179/695] [flang] Improve error message with declaration (#87294) When a program attempts to use a non-object entity as the base of a component reference or type parameter inquiry, the message is somewhat uninformative and the position of the entity's declaration will not reflect any updates made to the symbol during name resolution. Includes some NFC C++17 style clean-up on some code noticed while debugging (missing mandatory braces). --- flang/include/flang/Parser/char-block.h | 19 +++++++++++-------- flang/lib/Semantics/resolve-names.cpp | 4 ++-- flang/test/Semantics/resolve21.f90 | 6 +++--- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/flang/include/flang/Parser/char-block.h b/flang/include/flang/Parser/char-block.h index acd8aee98bf8..38f4f7b82e1e 100644 --- a/flang/include/flang/Parser/char-block.h +++ b/flang/include/flang/Parser/char-block.h @@ -132,17 +132,20 @@ private: // "memcmp" in glibc has "nonnull" attributes on the input pointers. // Avoid passing null pointers, since it would result in an undefined // behavior. - if (size() == 0) + if (size() == 0) { return that.size() == 0 ? 0 : -1; - if (that.size() == 0) + } else if (that.size() == 0) { return 1; - std::size_t bytes{std::min(size(), that.size())}; - int cmp{std::memcmp(static_cast(begin()), - static_cast(that.begin()), bytes)}; - if (cmp != 0) { - return cmp; + } else { + std::size_t bytes{std::min(size(), that.size())}; + int cmp{std::memcmp(static_cast(begin()), + static_cast(that.begin()), bytes)}; + if (cmp != 0) { + return cmp; + } else { + return size() < that.size() ? -1 : size() > that.size(); + } } - return size() < that.size() ? -1 : size() > that.size(); } int Compare(const char *that) const { diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index b04de2648017..c69c702ecae2 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -2253,7 +2253,7 @@ void ScopeHandler::SayWithDecl( const parser::Name &name, Symbol &symbol, MessageFixedText &&msg) { bool isFatal{msg.IsFatal()}; Say(name, std::move(msg), symbol.name()) - .Attach(Message{name.source, + .Attach(Message{symbol.name(), symbol.test(Symbol::Flag::Implicit) ? "Implicit declaration of '%s'"_en_US : "Declaration of '%s'"_en_US, @@ -7843,7 +7843,7 @@ const parser::Name *DeclarationVisitor::FindComponent( auto &symbol{base->symbol->GetUltimate()}; if (!symbol.has() && !ConvertToObjectEntity(symbol)) { SayWithDecl(*base, symbol, - "'%s' is an invalid base for a component reference"_err_en_US); + "'%s' is not an object and may not be used as the base of a component reference or type parameter inquiry"_err_en_US); return nullptr; } auto *type{symbol.GetType()}; diff --git a/flang/test/Semantics/resolve21.f90 b/flang/test/Semantics/resolve21.f90 index 3be7602b539d..76f83d554fc2 100644 --- a/flang/test/Semantics/resolve21.f90 +++ b/flang/test/Semantics/resolve21.f90 @@ -16,15 +16,15 @@ subroutine s1 external :: w !ERROR: 'z' is not an object of derived type; it is implicitly typed i = z%i - !ERROR: 's1' is an invalid base for a component reference + !ERROR: 's1' is not an object and may not be used as the base of a component reference or type parameter inquiry i = s1%i !ERROR: 'j' is not an object of derived type i = j%i !ERROR: Component 'j' not found in derived type 't' i = x%j - !ERROR: 'v' is an invalid base for a component reference + !ERROR: 'v' is not an object and may not be used as the base of a component reference or type parameter inquiry i = v%i - !ERROR: 'w' is an invalid base for a component reference + !ERROR: 'w' is not an object and may not be used as the base of a component reference or type parameter inquiry i = w%i i = x%i !OK end subroutine -- GitLab From 97e3f605d5b574899d9f012032349bbf84c4dcfb Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:56:36 -0700 Subject: [PATCH 180/695] =?UTF-8?q?[flang]=20Don't=20allow=20non-standard?= =?UTF-8?q?=20data=20conversions=20of=20potentially=20abse=E2=80=A6=20(#87?= =?UTF-8?q?391)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …nt arguments Arguments to the intrinsic functions MAX and MIN after the first two are optional. When these actual arguments might not be present at run time, emit a compilation time error if they require data conversion (a non-standard but nearly universal language extension); such a conversion would crash if the argument was absent. Other compilers either disallow data conversions entirely on MAX/MIN or crash at run time if a converted argument is absent. Fixes https://github.com/llvm/llvm-project/issues/87046. --- flang/docs/Extensions.md | 4 ++++ flang/lib/Semantics/check-call.cpp | 33 +++++++++++++++++++++++---- flang/test/Semantics/intrinsics04.f90 | 25 ++++++++++++++++++++ 3 files changed, 58 insertions(+), 4 deletions(-) create mode 100644 flang/test/Semantics/intrinsics04.f90 diff --git a/flang/docs/Extensions.md b/flang/docs/Extensions.md index d44242de17d5..4c3847291a3f 100644 --- a/flang/docs/Extensions.md +++ b/flang/docs/Extensions.md @@ -346,6 +346,10 @@ end * A `NAMELIST` input group may begin with either `&` or `$`. * A comma in a fixed-width numeric input field terminates the field rather than signaling an invalid character error. +* Arguments to the intrinsic functions `MAX` and `MIN` are converted + when necessary to the type of the result. + An `OPTIONAL`, `POINTER`, or `ALLOCATABLE` argument after + the first two cannot be converted, as it may not be present. ### Extensions supported when enabled by options diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index 51a16ee155fa..bd2f75585517 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -1466,6 +1466,29 @@ static void CheckImage_Index(evaluate::ActualArguments &arguments, } } +// Ensure that any optional argument that might be absent at run time +// does not require data conversion. +static void CheckMaxMin(const characteristics::Procedure &proc, + evaluate::ActualArguments &arguments, + parser::ContextualMessages &messages) { + if (proc.functionResult) { + if (const auto *typeAndShape{proc.functionResult->GetTypeAndShape()}) { + for (std::size_t j{2}; j < arguments.size(); ++j) { + if (arguments[j]) { + if (const auto *expr{arguments[j]->UnwrapExpr()}; + expr && evaluate::MayBePassedAsAbsentOptional(*expr)) { + if (auto thisType{expr->GetType()}; + thisType && *thisType != typeAndShape->type()) { + messages.Say(arguments[j]->sourceLocation(), + "An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE"_err_en_US); + } + } + } + } + } + } +} + // MOVE_ALLOC (F'2023 16.9.147) static void CheckMove_Alloc(evaluate::ActualArguments &arguments, parser::ContextualMessages &messages) { @@ -1733,13 +1756,15 @@ static void CheckTransfer(evaluate::ActualArguments &arguments, } } -static void CheckSpecificIntrinsic(evaluate::ActualArguments &arguments, - SemanticsContext &context, const Scope *scope, - const evaluate::SpecificIntrinsic &intrinsic) { +static void CheckSpecificIntrinsic(const characteristics::Procedure &proc, + evaluate::ActualArguments &arguments, SemanticsContext &context, + const Scope *scope, const evaluate::SpecificIntrinsic &intrinsic) { if (intrinsic.name == "associated") { CheckAssociated(arguments, context, scope); } else if (intrinsic.name == "image_index") { CheckImage_Index(arguments, context.foldingContext().messages()); + } else if (intrinsic.name == "max" || intrinsic.name == "min") { + CheckMaxMin(proc, arguments, context.foldingContext().messages()); } else if (intrinsic.name == "move_alloc") { CheckMove_Alloc(arguments, context.foldingContext().messages()); } else if (intrinsic.name == "present") { @@ -1790,7 +1815,7 @@ static parser::Messages CheckExplicitInterface( CheckElementalConformance(messages, proc, actuals, foldingContext); } if (intrinsic) { - CheckSpecificIntrinsic(actuals, context, scope, *intrinsic); + CheckSpecificIntrinsic(proc, actuals, context, scope, *intrinsic); } return buffer; } diff --git a/flang/test/Semantics/intrinsics04.f90 b/flang/test/Semantics/intrinsics04.f90 new file mode 100644 index 000000000000..a7d646e5c016 --- /dev/null +++ b/flang/test/Semantics/intrinsics04.f90 @@ -0,0 +1,25 @@ +! RUN: %python %S/test_errors.py %s %flang_fc1 +! A potentially absent actual argument cannot require data type conversion. +subroutine s(o,a,p) + integer(2), intent(in), optional :: o + integer(2), intent(in), allocatable :: a + integer(2), intent(in), pointer :: p + !ERROR: An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE + print *, max(1, 2, o) + !ERROR: An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE + print *, max(1, 2, a) + !ERROR: An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE + print *, max(1, 2, p) + !ERROR: An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE + print *, min(1, 2, o) + !ERROR: An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE + print *, min(1, 2, a) + !ERROR: An actual argument to MAX/MIN requiring data conversion may not be OPTIONAL, POINTER, or ALLOCATABLE + print *, min(1, 2, p) + print *, max(1_2, 2_2, o) ! ok + print *, max(1_2, 2_2, a) ! ok + print *, max(1_2, 2_2, p) ! ok + print *, min(1_2, 2_2, o) ! ok + print *, min(1_2, 2_2, a) ! ok + print *, min(1_2, 2_2, p) ! ok +end -- GitLab From e1ad2735c3e7b0af94159f585458c7383255f03e Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 11:57:01 -0700 Subject: [PATCH 181/695] [flang] Clean up ISO_FORTRAN_ENV, fix NUMERIC_STORAGE_SIZE (#87566) Address TODOs in the intrinsic module ISO_FORTRAN_ENV, and extend the implementation of NUMERIC_STORAGE_SIZE so that the calculation of its value is deferred until it is needed so that the effects of -fdefault-integer-8 or -fdefault-real-8 are reflected. Emit a warning when NUMERIC_STORAGE_SIZE is used from the module file and the default integer and real sizes do not match. Fixes https://github.com/llvm/llvm-project/issues/87476. --- flang/include/flang/Evaluate/common.h | 10 ++- flang/lib/Evaluate/check-expression.cpp | 8 ++ flang/lib/Evaluate/fold-implementation.h | 2 +- flang/lib/Evaluate/fold-integer.cpp | 18 ++++ flang/lib/Evaluate/intrinsics.cpp | 5 +- flang/lib/Semantics/mod-file.cpp | 6 +- flang/lib/Semantics/resolve-names.cpp | 4 +- flang/module/iso_fortran_env.f90 | 86 +++++++++---------- flang/test/Semantics/numeric_storage_size.f90 | 40 +++++++++ flang/tools/f18/CMakeLists.txt | 15 ++-- 10 files changed, 129 insertions(+), 65 deletions(-) create mode 100644 flang/test/Semantics/numeric_storage_size.f90 diff --git a/flang/include/flang/Evaluate/common.h b/flang/include/flang/Evaluate/common.h index d04c901929e7..c2c7711c4684 100644 --- a/flang/include/flang/Evaluate/common.h +++ b/flang/include/flang/Evaluate/common.h @@ -256,9 +256,11 @@ public: const common::LanguageFeatureControl &languageFeatures() const { return languageFeatures_; } - bool inModuleFile() const { return inModuleFile_; } - FoldingContext &set_inModuleFile(bool yes = true) { - inModuleFile_ = yes; + std::optional moduleFileName() const { + return moduleFileName_; + } + FoldingContext &set_moduleFileName(std::optional n) { + moduleFileName_ = n; return *this; } @@ -288,7 +290,7 @@ private: const IntrinsicProcTable &intrinsics_; const TargetCharacteristics &targetCharacteristics_; const semantics::DerivedTypeSpec *pdtInstance_{nullptr}; - bool inModuleFile_{false}; + std::optional moduleFileName_; std::map impliedDos_; const common::LanguageFeatureControl &languageFeatures_; std::set &tempNames_; diff --git a/flang/lib/Evaluate/check-expression.cpp b/flang/lib/Evaluate/check-expression.cpp index 7d721399072c..0e14aa095729 100644 --- a/flang/lib/Evaluate/check-expression.cpp +++ b/flang/lib/Evaluate/check-expression.cpp @@ -478,6 +478,14 @@ std::optional> NonPointerInitializationExpr(const Symbol &symbol, return {std::move(folded)}; } } else if (IsNamedConstant(symbol)) { + if (symbol.name() == "numeric_storage_size" && + symbol.owner().IsModule() && + DEREF(symbol.owner().symbol()).name() == "iso_fortran_env") { + // Very special case: numeric_storage_size is not folded until + // it read from the iso_fortran_env module file, as its value + // depends on compilation options. + return {std::move(folded)}; + } context.messages().Say( "Value of named constant '%s' (%s) cannot be computed as a constant value"_err_en_US, symbol.name(), folded.AsFortran()); diff --git a/flang/lib/Evaluate/fold-implementation.h b/flang/lib/Evaluate/fold-implementation.h index 9dd8c3843465..470dbe9e7409 100644 --- a/flang/lib/Evaluate/fold-implementation.h +++ b/flang/lib/Evaluate/fold-implementation.h @@ -1969,7 +1969,7 @@ Expr FoldOperation(FoldingContext &context, Divide &&x) { // NaN, and Inf respectively. bool isCanonicalNaNOrInf{false}; if constexpr (T::category == TypeCategory::Real) { - if (folded->second.IsZero() && context.inModuleFile()) { + if (folded->second.IsZero() && context.moduleFileName().has_value()) { using IntType = typename T::Scalar::Word; auto intNumerator{folded->first.template ToInteger()}; isCanonicalNaNOrInf = intNumerator.flags == RealFlags{} && diff --git a/flang/lib/Evaluate/fold-integer.cpp b/flang/lib/Evaluate/fold-integer.cpp index 25ae4831ab20..0a6ff12049f3 100644 --- a/flang/lib/Evaluate/fold-integer.cpp +++ b/flang/lib/Evaluate/fold-integer.cpp @@ -1302,6 +1302,24 @@ Expr> FoldIntrinsicFunction( return FoldSum(context, std::move(funcRef)); } else if (name == "ubound") { return UBOUND(context, std::move(funcRef)); + } else if (name == "__builtin_numeric_storage_size") { + if (!context.moduleFileName()) { + // Don't fold this reference until it appears in the module file + // for ISO_FORTRAN_ENV -- the value depends on the compiler options + // that might be in force. + } else { + auto intBytes{ + context.targetCharacteristics().GetByteSize(TypeCategory::Integer, + context.defaults().GetDefaultKind(TypeCategory::Integer))}; + auto realBytes{ + context.targetCharacteristics().GetByteSize(TypeCategory::Real, + context.defaults().GetDefaultKind(TypeCategory::Real))}; + if (intBytes != realBytes) { + context.messages().Say(*context.moduleFileName(), + "NUMERIC_STORAGE_SIZE from ISO_FORTRAN_ENV is not well-defined when default INTEGER and REAL are not consistent due to compiler options"_warn_en_US); + } + return Expr{8 * std::min(intBytes, realBytes)}; + } } return Expr{std::move(funcRef)}; } diff --git a/flang/lib/Evaluate/intrinsics.cpp b/flang/lib/Evaluate/intrinsics.cpp index 9b98d22cc58e..7226d69f6391 100644 --- a/flang/lib/Evaluate/intrinsics.cpp +++ b/flang/lib/Evaluate/intrinsics.cpp @@ -903,6 +903,8 @@ static const IntrinsicInterface genericIntrinsicFunction[]{ {"back", AnyLogical, Rank::elemental, Optionality::optional}, DefaultingKIND}, KINDInt}, + {"__builtin_compiler_options", {}, DefaultChar}, + {"__builtin_compiler_version", {}, DefaultChar}, {"__builtin_fma", {{"f1", SameReal}, {"f2", SameReal}, {"f3", SameReal}}, SameReal}, {"__builtin_ieee_is_nan", {{"a", AnyFloating}}, DefaultLogical}, @@ -941,8 +943,7 @@ static const IntrinsicInterface genericIntrinsicFunction[]{ {"__builtin_ieee_support_underflow_control", {{"x", AnyReal, Rank::elemental, Optionality::optional}}, DefaultLogical}, - {"__builtin_compiler_options", {}, DefaultChar}, - {"__builtin_compiler_version", {}, DefaultChar}, + {"__builtin_numeric_storage_size", {}, DefaultInt}, }; // TODO: Coarray intrinsic functions diff --git a/flang/lib/Semantics/mod-file.cpp b/flang/lib/Semantics/mod-file.cpp index 5d0d210fa348..4a531c3c0f99 100644 --- a/flang/lib/Semantics/mod-file.cpp +++ b/flang/lib/Semantics/mod-file.cpp @@ -1458,11 +1458,11 @@ Scope *ModFileReader::Read(SourceName name, std::optional isIntrinsic, parentScope = ancestor; } // Process declarations from the module file - bool wasInModuleFile{context_.foldingContext().inModuleFile()}; - context_.foldingContext().set_inModuleFile(true); + auto wasModuleFileName{context_.foldingContext().moduleFileName()}; + context_.foldingContext().set_moduleFileName(name); GetModuleDependences(context_.moduleDependences(), sourceFile->content()); ResolveNames(context_, parseTree, topScope); - context_.foldingContext().set_inModuleFile(wasInModuleFile); + context_.foldingContext().set_moduleFileName(wasModuleFileName); if (!moduleSymbol) { // Submodule symbols' storage are owned by their parents' scopes, // but their names are not in their parents' dictionaries -- we diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index c69c702ecae2..f0198cb79228 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -175,7 +175,9 @@ public: } } - bool InModuleFile() const { return GetFoldingContext().inModuleFile(); } + bool InModuleFile() const { + return GetFoldingContext().moduleFileName().has_value(); + } // Make a placeholder symbol for a Name that otherwise wouldn't have one. // It is not in any scope and always has MiscDetails. diff --git a/flang/module/iso_fortran_env.f90 b/flang/module/iso_fortran_env.f90 index 23e22e1f64de..6ca98e518aea 100644 --- a/flang/module/iso_fortran_env.f90 +++ b/flang/module/iso_fortran_env.f90 @@ -6,8 +6,7 @@ ! !===------------------------------------------------------------------------===! -! See Fortran 2018, clause 16.10.2 -! TODO: These are placeholder values so that some tests can be run. +! See Fortran 2023, subclause 16.10.2 include '../include/flang/Runtime/magic-numbers.h' @@ -24,27 +23,20 @@ module iso_fortran_env compiler_version => __builtin_compiler_version implicit none - - ! Set PRIVATE by default to explicitly only export what is meant - ! to be exported by this MODULE. private public :: event_type, notify_type, lock_type, team_type, & atomic_int_kind, atomic_logical_kind, compiler_options, & compiler_version - - ! TODO: Use PACK([x],test) in place of the array constructor idiom - ! [(x, integer::j=1,COUNT([test]))] below once PACK() can be folded. - integer, parameter :: & selectedASCII = selected_char_kind('ASCII'), & selectedUCS_2 = selected_char_kind('UCS-2'), & selectedUnicode = selected_char_kind('ISO_10646') integer, parameter, public :: character_kinds(*) = [ & - [(selectedASCII, integer :: j=1, count([selectedASCII >= 0]))], & - [(selectedUCS_2, integer :: j=1, count([selectedUCS_2 >= 0]))], & - [(selectedUnicode, integer :: j=1, count([selectedUnicode >= 0]))]] + pack([selectedASCII], selectedASCII >= 0), & + pack([selectedUCS_2], selectedUCS_2 >= 0), & + pack([selectedUnicode], selectedUnicode >= 0)] integer, parameter :: & selectedInt8 = selected_int_kind(2), & @@ -76,19 +68,18 @@ module iso_fortran_env integer, parameter, public :: integer_kinds(*) = [ & selected_int_kind(0), & - ((selected_int_kind(k), & - integer :: j=1, count([selected_int_kind(k) >= 0 .and. & - selected_int_kind(k) /= & - selected_int_kind(k-1)])), & - integer :: k=1, 39)] + [(pack([selected_int_kind(k)], & + selected_int_kind(k) >= 0 .and. & + selected_int_kind(k) /= selected_int_kind(k-1)), & + integer :: k=1, 39)]] integer, parameter, public :: & logical8 = int8, logical16 = int16, logical32 = int32, logical64 = int64 integer, parameter, public :: logical_kinds(*) = [ & - [(logical8, integer :: j=1, count([logical8 >= 0]))], & - [(logical16, integer :: j=1, count([logical16 >= 0]))], & - [(logical32, integer :: j=1, count([logical32 >= 0]))], & - [(logical64, integer :: j=1, count([logical64 >= 0]))]] + pack([logical8], logical8 >= 0), & + pack([logical16], logical16 >= 0), & + pack([logical32], logical32 >= 0), & + pack([logical64], logical64 >= 0)] integer, parameter :: & selectedReal16 = selected_real_kind(3, 4), & ! IEEE half @@ -129,35 +120,40 @@ module iso_fortran_env digits(real(0,kind=safeReal128)) == 113) integer, parameter, public :: real_kinds(*) = [ & - [(real16, integer :: j=1, count([real16 >= 0]))], & - [(bfloat16, integer :: j=1, count([bfloat16 >= 0]))], & - [(real32, integer :: j=1, count([real32 >= 0]))], & - [(real64, integer :: j=1, count([real64 >= 0]))], & - [(real80, integer :: j=1, count([real80 >= 0]))], & - [(real64x2, integer :: j=1, count([real64x2 >= 0]))], & - [(real128, integer :: j=1, count([real128 >= 0]))]] - - integer, parameter, public :: current_team = -1, initial_team = -2, parent_team = -3 - - integer, parameter, public :: output_unit = FORTRAN_DEFAULT_OUTPUT_UNIT - integer, parameter, public :: input_unit = FORTRAN_DEFAULT_INPUT_UNIT - integer, parameter, public :: error_unit = FORTRAN_ERROR_UNIT - integer, parameter, public :: iostat_end = FORTRAN_RUNTIME_IOSTAT_END - integer, parameter, public :: iostat_eor = FORTRAN_RUNTIME_IOSTAT_EOR - integer, parameter, public :: iostat_inquire_internal_unit = & - FORTRAN_RUNTIME_IOSTAT_INQUIRE_INTERNAL_UNIT + pack([real16], real16 >= 0), & + pack([bfloat16], bfloat16 >= 0), & + pack([real32], real32 >= 0), & + pack([real64], real64 >= 0), & + pack([real80], real80 >= 0), & + pack([real64x2], real64x2 >= 0), & + pack([real128], real128 >= 0)] + + integer, parameter, public :: current_team = -1, & + initial_team = -2, & + parent_team = -3 integer, parameter, public :: character_storage_size = 8 integer, parameter, public :: file_storage_size = 8 - integer, parameter, public :: numeric_storage_size = 32 - integer, parameter, public :: stat_failed_image = FORTRAN_RUNTIME_STAT_FAILED_IMAGE - integer, parameter, public :: stat_locked = FORTRAN_RUNTIME_STAT_LOCKED - integer, parameter, public :: & - stat_locked_other_image = FORTRAN_RUNTIME_STAT_LOCKED_OTHER_IMAGE - integer, parameter, public :: stat_stopped_image = FORTRAN_RUNTIME_STAT_STOPPED_IMAGE - integer, parameter, public :: stat_unlocked = FORTRAN_RUNTIME_STAT_UNLOCKED + intrinsic :: __builtin_numeric_storage_size + ! This value depends on any -fdefault-integer-N and -fdefault-real-N + ! compiler options that are active when the module file is read. + integer, parameter, public :: numeric_storage_size = & + __builtin_numeric_storage_size() + + ! From Runtime/magic-numbers.h: integer, parameter, public :: & + output_unit = FORTRAN_DEFAULT_OUTPUT_UNIT, & + input_unit = FORTRAN_DEFAULT_INPUT_UNIT, & + error_unit = FORTRAN_ERROR_UNIT, & + iostat_end = FORTRAN_RUNTIME_IOSTAT_END, & + iostat_eor = FORTRAN_RUNTIME_IOSTAT_EOR, & + iostat_inquire_internal_unit = FORTRAN_RUNTIME_IOSTAT_INQUIRE_INTERNAL_UNIT, & + stat_failed_image = FORTRAN_RUNTIME_STAT_FAILED_IMAGE, & + stat_locked = FORTRAN_RUNTIME_STAT_LOCKED, & + stat_locked_other_image = FORTRAN_RUNTIME_STAT_LOCKED_OTHER_IMAGE, & + stat_stopped_image = FORTRAN_RUNTIME_STAT_STOPPED_IMAGE, & + stat_unlocked = FORTRAN_RUNTIME_STAT_UNLOCKED, & stat_unlocked_failed_image = FORTRAN_RUNTIME_STAT_UNLOCKED_FAILED_IMAGE end module iso_fortran_env diff --git a/flang/test/Semantics/numeric_storage_size.f90 b/flang/test/Semantics/numeric_storage_size.f90 new file mode 100644 index 000000000000..720297c0feb3 --- /dev/null +++ b/flang/test/Semantics/numeric_storage_size.f90 @@ -0,0 +1,40 @@ +! RUN: %flang_fc1 -fdebug-unparse %s 2>&1 | FileCheck %s --check-prefix=CHECK +! RUN: %flang_fc1 -fdebug-unparse -fdefault-integer-8 %s 2>&1 | FileCheck %s --check-prefix=CHECK-I8 +! RUN: %flang_fc1 -fdebug-unparse %s -fdefault-real-8 2>&1 | FileCheck %s --check-prefix=CHECK-R8 +! RUN: %flang_fc1 -fdebug-unparse %s -fdefault-integer-8 -fdefault-real-8 2>&1 | FileCheck %s --check-prefix=CHECK-I8-R8 + +use iso_fortran_env + +!CHECK-NOT: warning +!CHECK: nss = 32_4 +!CHECK-I8: warning: NUMERIC_STORAGE_SIZE from ISO_FORTRAN_ENV is not well-defined when default INTEGER and REAL are not consistent due to compiler options +!CHECK-I8: nss = 32_4 +!CHECK-R8: warning: NUMERIC_STORAGE_SIZE from ISO_FORTRAN_ENV is not well-defined when default INTEGER and REAL are not consistent due to compiler options +!CHECK-R8: nss = 32_4 +!CHECK-I8-R8: nss = 64_4 +integer, parameter :: nss = numeric_storage_size + +!CHECK: iss = 32_4 +!CHECK-I8: iss = 64_8 +!CHECK-R8: iss = 32_4 +!CHECK-I8-R8: iss = 64_8 +integer, parameter :: iss = storage_size(1) + +!CHECK: rss = 32_4 +!CHECK-I8: rss = 32_8 +!CHECK-R8: rss = 64_4 +!CHECK-I8-R8: rss = 64_8 +integer, parameter :: rss = storage_size(1.) + +!CHECK: zss = 64_4 +!CHECK-I8: zss = 64_8 +!CHECK-R8: zss = 128_4 +!CHECK-I8-R8: zss = 128_8 +integer, parameter :: zss = storage_size((1.,0.)) + +!CHECK: lss = 32_4 +!CHECK-I8: lss = 64_8 +!CHECK-R8: lss = 32_4 +!CHECK-I8-R8: lss = 64_8 +integer, parameter :: lss = storage_size(.true.) +end diff --git a/flang/tools/f18/CMakeLists.txt b/flang/tools/f18/CMakeLists.txt index 3a31f4df1607..e266055a4bf0 100644 --- a/flang/tools/f18/CMakeLists.txt +++ b/flang/tools/f18/CMakeLists.txt @@ -17,8 +17,6 @@ set(MODULES "ieee_features" "iso_c_binding" "iso_fortran_env" - "__fortran_builtins" - "__fortran_type_info" ) # Create module files directly from the top-level module source directory. @@ -27,22 +25,20 @@ set(MODULES # can't be used for generating module files. if (NOT CMAKE_CROSSCOMPILING) foreach(filename ${MODULES}) - set(base ${FLANG_INTRINSIC_MODULES_DIR}/${filename}) - if(${filename} STREQUAL "__fortran_builtins") - set(depends "") - elseif(${filename} STREQUAL "__ppc_types") - set(depends "") + set(depends "") + if(${filename} STREQUAL "__fortran_builtins" OR + ${filename} STREQUAL "__ppc_types") elseif(${filename} STREQUAL "__ppc_intrinsics" OR ${filename} STREQUAL "mma") set(depends ${FLANG_INTRINSIC_MODULES_DIR}/__ppc_types.mod) else() set(depends ${FLANG_INTRINSIC_MODULES_DIR}/__fortran_builtins.mod) if(NOT ${filename} STREQUAL "__fortran_type_info") - set(depends ${FLANG_INTRINSIC_MODULES_DIR}/__fortran_type_info.mod) + set(depends ${depends} ${FLANG_INTRINSIC_MODULES_DIR}/__fortran_type_info.mod) endif() if(${filename} STREQUAL "ieee_arithmetic" OR ${filename} STREQUAL "ieee_exceptions") - set(depends ${FLANG_INTRINSIC_MODULES_DIR}/__fortran_ieee_exceptions.mod) + set(depends ${depends} ${FLANG_INTRINSIC_MODULES_DIR}/__fortran_ieee_exceptions.mod) endif() endif() @@ -58,6 +54,7 @@ if (NOT CMAKE_CROSSCOMPILING) endif() endif() + set(base ${FLANG_INTRINSIC_MODULES_DIR}/${filename}) # TODO: We may need to flag this with conditional, in case Flang is built w/o OpenMP support add_custom_command(OUTPUT ${base}.mod COMMAND ${CMAKE_COMMAND} -E make_directory ${FLANG_INTRINSIC_MODULES_DIR} -- GitLab From 89eb1a5a8e35a3bb77e4a1ca4fcac6757efc9339 Mon Sep 17 00:00:00 2001 From: Daniil Kovalev Date: Mon, 8 Apr 2024 22:27:50 +0300 Subject: [PATCH 182/695] [test][AArch64][CodeGen] Delete redundant check lines (#87965) llvm/test/CodeGen/AArch64/elf-globals-pic.ll: Since https://reviews.llvm.org/D91734, elf-globals-static.ll test contains several `CHECK-PIC` lines. They do not seem to bring any value since there are no FileCheck run lines checking against this prefix. The right place for such tests should be elf-globals-pic.ll, which already contains check lines being deleted in this commit. Both elf-globals-pic.ll and elf-globals-static.ll were created after splitting arm64-elf-globals.ll in 6dbd0ea, and having `CHECK-PIC` lines in elf-globals-static.ll seems like an issue occurred because of git thinking that elf-globals-pic.ll is a new file and elf-global-static.ll is a rename of arm64-elf-globals.ll. llvm/test/CodeGen/AArch64/tagged-globals-pic.ll: Similar to elf-globals-pic.ll, contains unneeded `CHECK-SELECTIONDAGISEL` and `CHECK-GLOBALISEL` directives not checked by any FileCheck invocation. These directives are present in tagged-globals-static.ll. Both tests are present in the code tree since fd32639 when tagged-globals.ll was splitted into tagged-globals-{pic|static}.ll. --- .../CodeGen/AArch64/elf-globals-static.ll | 5 ---- .../CodeGen/AArch64/tagged-globals-pic.ll | 24 ------------------- 2 files changed, 29 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/elf-globals-static.ll b/llvm/test/CodeGen/AArch64/elf-globals-static.ll index 86b7c401b9a2..855312f8927c 100644 --- a/llvm/test/CodeGen/AArch64/elf-globals-static.ll +++ b/llvm/test/CodeGen/AArch64/elf-globals-static.ll @@ -15,11 +15,6 @@ define i8 @test_i8(i8 %new) { ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] -; CHECK-PIC-LABEL: test_i8: -; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8 -; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8] -; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]] - ; CHECK-FAST-LABEL: test_i8: ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] diff --git a/llvm/test/CodeGen/AArch64/tagged-globals-pic.ll b/llvm/test/CodeGen/AArch64/tagged-globals-pic.ll index 6ee0dd193c3d..3c4274abdd56 100644 --- a/llvm/test/CodeGen/AArch64/tagged-globals-pic.ll +++ b/llvm/test/CodeGen/AArch64/tagged-globals-pic.ll @@ -31,18 +31,6 @@ define ptr @global_addr() #0 { } define i32 @global_load() #0 { - ; CHECK-SELECTIONDAGISEL: global_load: - ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global - ; CHECK-SELECTIONDAGISEL: ldr w0, [[[REG]], :lo12:global] - ; CHECK-SELECTIONDAGISEL: ret - - ; CHECK-GLOBALISEL: global_load: - ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global - ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296 - ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global - ; CHECK-GLOBALISEL: ldr w0, [[[REG]]] - ; CHECK-GLOBALISEL: ret - ; CHECK-PIC: global_load: ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global ; CHECK-PIC: ldr [[REG]], [[[REG]], :got_lo12:global] @@ -54,18 +42,6 @@ define i32 @global_load() #0 { } define void @global_store() #0 { - ; CHECK-SELECTIONDAGISEL: global_store: - ; CHECK-SELECTIONDAGISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global - ; CHECK-SELECTIONDAGISEL: str wzr, [[[REG]], :lo12:global] - ; CHECK-SELECTIONDAGISEL: ret - - ; CHECK-GLOBALISEL: global_store: - ; CHECK-GLOBALISEL: adrp [[REG:x[0-9]+]], :pg_hi21_nc:global - ; CHECK-GLOBALISEL: movk [[REG]], #:prel_g3:global+4294967296 - ; CHECK-GLOBALISEL: add [[REG]], [[REG]], :lo12:global - ; CHECK-GLOBALISEL: str wzr, [[[REG]]] - ; CHECK-GLOBALISEL: ret - ; CHECK-PIC: global_store: ; CHECK-PIC: adrp [[REG:x[0-9]+]], :got:global ; CHECK-PIC: ldr [[REG]], [[[REG]], :got_lo12:global] -- GitLab From 708c8cd7435002027a2cc9b99a0916a3dc255d63 Mon Sep 17 00:00:00 2001 From: Axel Lundberg <19574357+Zonotora@users.noreply.github.com> Date: Mon, 8 Apr 2024 21:30:27 +0200 Subject: [PATCH 183/695] Fix "[clang][UBSan] Add implicit conversion check for bitfields" (#87761) Fix since #75481 got reverted. - Explicitly set BitfieldBits to 0 to avoid uninitialized field member for the integer checks: ```diff - llvm::ConstantInt::get(Builder.getInt8Ty(), Check.first)}; + llvm::ConstantInt::get(Builder.getInt8Ty(), Check.first), + llvm::ConstantInt::get(Builder.getInt32Ty(), 0)}; ``` - `Value **Previous` was erroneously `Value *Previous` in `CodeGenFunction::EmitWithOriginalRHSBitfieldAssignment`, fixed now. - Update following: ```diff - if (Kind == CK_IntegralCast) { + if (Kind == CK_IntegralCast || Kind == CK_LValueToRValue) { ``` CK_LValueToRValue when going from, e.g., char to char, and CK_IntegralCast otherwise. - Make sure that `Value *Previous = nullptr;` is initialized (see https://github.com/llvm/llvm-project/commit/1189e87951e59a81ee097eae847c06008276fef1) - Add another extensive testcase `ubsan/TestCases/ImplicitConversion/bitfield-conversion.c` --------- Co-authored-by: Vitaly Buka --- clang/docs/ReleaseNotes.rst | 7 + clang/docs/UndefinedBehaviorSanitizer.rst | 19 +- clang/include/clang/Basic/Sanitizers.def | 20 +- clang/lib/CodeGen/CGExpr.cpp | 37 +- clang/lib/CodeGen/CGExprScalar.cpp | 264 ++++++- clang/lib/CodeGen/CodeGenFunction.h | 15 + .../catch-implicit-conversions-basics.c | 18 +- ...catch-implicit-conversions-incdec-basics.c | 32 +- ...t-integer-arithmetic-value-change-basics.c | 16 +- ...er-arithmetic-value-change-incdec-basics.c | 32 +- ...atch-implicit-integer-conversions-basics.c | 18 +- ...plicit-integer-conversions-incdec-basics.c | 32 +- ...eger-sign-changes-CompoundAssignOperator.c | 162 ++--- ...tch-implicit-integer-sign-changes-basics.c | 16 +- ...licit-integer-sign-changes-incdec-basics.c | 32 +- ...tch-implicit-integer-sign-changes-incdec.c | 16 +- .../catch-implicit-integer-sign-changes.c | 18 +- ...teger-truncations-CompoundAssignOperator.c | 178 ++--- ...cit-integer-truncations-basics-negatives.c | 8 +- ...atch-implicit-integer-truncations-basics.c | 8 +- ...plicit-integer-truncations-incdec-basics.c | 32 +- .../catch-implicit-integer-truncations.c | 10 +- ...on-or-sign-change-CompoundAssignOperator.c | 162 ++--- ...signed-integer-truncation-or-sign-change.c | 8 +- ...ned-integer-truncations-basics-negatives.c | 4 +- ...plicit-signed-integer-truncations-basics.c | 6 +- ...signed-integer-truncations-incdec-basics.c | 32 +- ...plicit-signed-integer-truncations-incdec.c | 16 +- ...ned-integer-truncations-basics-negatives.c | 4 +- ...icit-unsigned-integer-truncations-basics.c | 2 +- .../test/CodeGen/ubsan-bitfield-conversion.c | 61 ++ .../CodeGenCXX/ubsan-bitfield-conversion.cpp | 94 +++ clang/test/Driver/fsanitize.c | 28 +- compiler-rt/lib/ubsan/ubsan_handlers.cpp | 27 +- compiler-rt/lib/ubsan/ubsan_handlers.h | 1 + .../ImplicitConversion/bitfield-conversion.c | 649 ++++++++++++++++++ 36 files changed, 1578 insertions(+), 506 deletions(-) create mode 100644 clang/test/CodeGen/ubsan-bitfield-conversion.c create mode 100644 clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp create mode 100644 compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 28e8ddb3c41c..abf15c8dc49d 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -198,6 +198,10 @@ Non-comprehensive list of changes in this release New Compiler Flags ------------------ +- ``-fsanitize=implicit-bitfield-conversion`` checks implicit truncation and + sign change. +- ``-fsanitize=implicit-integer-conversion`` a group that replaces the previous + group ``-fsanitize=implicit-conversion``. - ``-Wmissing-designated-field-initializers``, grouped under ``-Wmissing-field-initializers``. This diagnostic can be disabled to make ``-Wmissing-field-initializers`` behave @@ -211,6 +215,9 @@ Modified Compiler Flags - Added a new diagnostic flag ``-Wreturn-mismatch`` which is grouped under ``-Wreturn-type``, and moved some of the diagnostics previously controlled by ``-Wreturn-type`` under this new flag. Fixes #GH72116. +- ``-fsanitize=implicit-conversion`` is now a group for both + ``-fsanitize=implicit-integer-conversion`` and + ``-fsanitize=implicit-bitfield-conversion``. - Added ``-Wcast-function-type-mismatch`` under the ``-Wcast-function-type`` warning group. Moved the diagnostic previously controlled by diff --git a/clang/docs/UndefinedBehaviorSanitizer.rst b/clang/docs/UndefinedBehaviorSanitizer.rst index 8f58c92bd2a1..531d56e31382 100644 --- a/clang/docs/UndefinedBehaviorSanitizer.rst +++ b/clang/docs/UndefinedBehaviorSanitizer.rst @@ -148,6 +148,11 @@ Available checks are: Issues caught by this sanitizer are not undefined behavior, but are often unintentional. - ``-fsanitize=integer-divide-by-zero``: Integer division by zero. + - ``-fsanitize=implicit-bitfield-conversion``: Implicit conversion from + integer of larger bit width to smaller bitfield, if that results in data + loss. This includes unsigned/signed truncations and sign changes, similarly + to how the ``-fsanitize=implicit-integer-conversion`` group works, but + explicitly for bitfields. - ``-fsanitize=nonnull-attribute``: Passing null pointer as a function parameter which is declared to never be null. - ``-fsanitize=null``: Use of a null pointer or creation of a null @@ -193,8 +198,8 @@ Available checks are: signed division overflow (``INT_MIN/-1``). Note that checks are still added even when ``-fwrapv`` is enabled. This sanitizer does not check for lossy implicit conversions performed before the computation (see - ``-fsanitize=implicit-conversion``). Both of these two issues are handled - by ``-fsanitize=implicit-conversion`` group of checks. + ``-fsanitize=implicit-integer-conversion``). Both of these two issues are handled + by ``-fsanitize=implicit-integer-conversion`` group of checks. - ``-fsanitize=unreachable``: If control flow reaches an unreachable program point. - ``-fsanitize=unsigned-integer-overflow``: Unsigned integer overflow, where @@ -202,7 +207,7 @@ Available checks are: type. Unlike signed integer overflow, this is not undefined behavior, but it is often unintentional. This sanitizer does not check for lossy implicit conversions performed before such a computation - (see ``-fsanitize=implicit-conversion``). + (see ``-fsanitize=implicit-integer-conversion``). - ``-fsanitize=vla-bound``: A variable-length array whose bound does not evaluate to a positive value. - ``-fsanitize=vptr``: Use of an object whose vptr indicates that it is of @@ -224,11 +229,15 @@ You can also use the following check groups: - ``-fsanitize=implicit-integer-arithmetic-value-change``: Catches implicit conversions that change the arithmetic value of the integer. Enables ``implicit-signed-integer-truncation`` and ``implicit-integer-sign-change``. - - ``-fsanitize=implicit-conversion``: Checks for suspicious - behavior of implicit conversions. Enables + - ``-fsanitize=implicit-integer-conversion``: Checks for suspicious + behavior of implicit integer conversions. Enables ``implicit-unsigned-integer-truncation``, ``implicit-signed-integer-truncation``, and ``implicit-integer-sign-change``. + - ``-fsanitize=implicit-conversion``: Checks for suspicious + behavior of implicit conversions. Enables + ``implicit-integer-conversion``, and + ``implicit-bitfield-conversion``. - ``-fsanitize=integer``: Checks for undefined or suspicious integer behavior (e.g. unsigned integer overflow). Enables ``signed-integer-overflow``, ``unsigned-integer-overflow``, diff --git a/clang/include/clang/Basic/Sanitizers.def b/clang/include/clang/Basic/Sanitizers.def index c2137e3f61f6..b228ffd07ee7 100644 --- a/clang/include/clang/Basic/Sanitizers.def +++ b/clang/include/clang/Basic/Sanitizers.def @@ -163,24 +163,24 @@ SANITIZER_GROUP("implicit-integer-arithmetic-value-change", ImplicitIntegerArithmeticValueChange, ImplicitIntegerSignChange | ImplicitSignedIntegerTruncation) -SANITIZER("objc-cast", ObjCCast) +SANITIZER_GROUP("implicit-integer-conversion", ImplicitIntegerConversion, + ImplicitIntegerArithmeticValueChange | + ImplicitUnsignedIntegerTruncation) -// FIXME: -//SANITIZER_GROUP("implicit-integer-conversion", ImplicitIntegerConversion, -// ImplicitIntegerArithmeticValueChange | -// ImplicitUnsignedIntegerTruncation) -//SANITIZER_GROUP("implicit-conversion", ImplicitConversion, -// ImplicitIntegerConversion) +// Implicit bitfield sanitizers +SANITIZER("implicit-bitfield-conversion", ImplicitBitfieldConversion) SANITIZER_GROUP("implicit-conversion", ImplicitConversion, - ImplicitIntegerArithmeticValueChange | - ImplicitUnsignedIntegerTruncation) + ImplicitIntegerConversion | + ImplicitBitfieldConversion) SANITIZER_GROUP("integer", Integer, - ImplicitConversion | IntegerDivideByZero | Shift | + ImplicitIntegerConversion | IntegerDivideByZero | Shift | SignedIntegerOverflow | UnsignedIntegerOverflow | UnsignedShiftBase) +SANITIZER("objc-cast", ObjCCast) + SANITIZER("local-bounds", LocalBounds) SANITIZER_GROUP("bounds", Bounds, ArrayBounds | LocalBounds) diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index 2480972f1432..cf696a1c9f56 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -5597,11 +5597,44 @@ LValue CodeGenFunction::EmitBinaryOperatorLValue(const BinaryOperator *E) { break; } - RValue RV = EmitAnyExpr(E->getRHS()); + // TODO: Can we de-duplicate this code with the corresponding code in + // CGExprScalar, similar to the way EmitCompoundAssignmentLValue works? + RValue RV; + llvm::Value *Previous = nullptr; + QualType SrcType = E->getRHS()->getType(); + // Check if LHS is a bitfield, if RHS contains an implicit cast expression + // we want to extract that value and potentially (if the bitfield sanitizer + // is enabled) use it to check for an implicit conversion. + if (E->getLHS()->refersToBitField()) { + llvm::Value *RHS = + EmitWithOriginalRHSBitfieldAssignment(E, &Previous, &SrcType); + RV = RValue::get(RHS); + } else + RV = EmitAnyExpr(E->getRHS()); + LValue LV = EmitCheckedLValue(E->getLHS(), TCK_Store); + if (RV.isScalar()) EmitNullabilityCheck(LV, RV.getScalarVal(), E->getExprLoc()); - EmitStoreThroughLValue(RV, LV); + + if (LV.isBitField()) { + llvm::Value *Result = nullptr; + // If bitfield sanitizers are enabled we want to use the result + // to check whether a truncation or sign change has occurred. + if (SanOpts.has(SanitizerKind::ImplicitBitfieldConversion)) + EmitStoreThroughBitfieldLValue(RV, LV, &Result); + else + EmitStoreThroughBitfieldLValue(RV, LV); + + // If the expression contained an implicit conversion, make sure + // to use the value before the scalar conversion. + llvm::Value *Src = Previous ? Previous : RV.getScalarVal(); + QualType DstType = E->getLHS()->getType(); + EmitBitfieldConversionCheck(Src, SrcType, Result, DstType, + LV.getBitFieldInfo(), E->getExprLoc()); + } else + EmitStoreThroughLValue(RV, LV); + if (getLangOpts().OpenMP) CGM.getOpenMPRuntime().checkAndEmitLastprivateConditional(*this, E->getLHS()); diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 397b4977acc3..1f18e0d5ba40 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -15,6 +15,7 @@ #include "CGDebugInfo.h" #include "CGObjCRuntime.h" #include "CGOpenMPRuntime.h" +#include "CGRecordLayout.h" #include "CodeGenFunction.h" #include "CodeGenModule.h" #include "ConstantEmitter.h" @@ -308,6 +309,7 @@ public: llvm::Type *DstTy, SourceLocation Loc); /// Known implicit conversion check kinds. + /// This is used for bitfield conversion checks as well. /// Keep in sync with the enum of the same name in ubsan_handlers.h enum ImplicitConversionCheckKind : unsigned char { ICCK_IntegerTruncation = 0, // Legacy, was only used by clang 7. @@ -1098,11 +1100,28 @@ void ScalarExprEmitter::EmitIntegerTruncationCheck(Value *Src, QualType SrcType, llvm::Constant *StaticArgs[] = { CGF.EmitCheckSourceLocation(Loc), CGF.EmitCheckTypeDescriptor(SrcType), CGF.EmitCheckTypeDescriptor(DstType), - llvm::ConstantInt::get(Builder.getInt8Ty(), Check.first)}; + llvm::ConstantInt::get(Builder.getInt8Ty(), Check.first), + llvm::ConstantInt::get(Builder.getInt32Ty(), 0)}; + CGF.EmitCheck(Check.second, SanitizerHandler::ImplicitConversion, StaticArgs, {Src, Dst}); } +static llvm::Value *EmitIsNegativeTestHelper(Value *V, QualType VType, + const char *Name, + CGBuilderTy &Builder) { + bool VSigned = VType->isSignedIntegerOrEnumerationType(); + llvm::Type *VTy = V->getType(); + if (!VSigned) { + // If the value is unsigned, then it is never negative. + return llvm::ConstantInt::getFalse(VTy->getContext()); + } + llvm::Constant *Zero = llvm::ConstantInt::get(VTy, 0); + return Builder.CreateICmp(llvm::ICmpInst::ICMP_SLT, V, Zero, + llvm::Twine(Name) + "." + V->getName() + + ".negativitycheck"); +} + // Should be called within CodeGenFunction::SanitizerScope RAII scope. // Returns 'i1 false' when the conversion Src -> Dst changed the sign. static std::pair Value * { - // Is this value a signed type? - bool VSigned = VType->isSignedIntegerOrEnumerationType(); - llvm::Type *VTy = V->getType(); - if (!VSigned) { - // If the value is unsigned, then it is never negative. - // FIXME: can we encounter non-scalar VTy here? - return llvm::ConstantInt::getFalse(VTy->getContext()); - } - // Get the zero of the same type with which we will be comparing. - llvm::Constant *Zero = llvm::ConstantInt::get(VTy, 0); - // %V.isnegative = icmp slt %V, 0 - // I.e is %V *strictly* less than zero, does it have negative value? - return Builder.CreateICmp(llvm::ICmpInst::ICMP_SLT, V, Zero, - llvm::Twine(Name) + "." + V->getName() + - ".negativitycheck"); - }; - // 1. Was the old Value negative? - llvm::Value *SrcIsNegative = EmitIsNegativeTest(Src, SrcType, "src"); + llvm::Value *SrcIsNegative = + EmitIsNegativeTestHelper(Src, SrcType, "src", Builder); // 2. Is the new Value negative? - llvm::Value *DstIsNegative = EmitIsNegativeTest(Dst, DstType, "dst"); + llvm::Value *DstIsNegative = + EmitIsNegativeTestHelper(Dst, DstType, "dst", Builder); // 3. Now, was the 'negativity status' preserved during the conversion? // NOTE: conversion from negative to zero is considered to change the sign. // (We want to get 'false' when the conversion changed the sign) @@ -1239,12 +1240,143 @@ void ScalarExprEmitter::EmitIntegerSignChangeCheck(Value *Src, QualType SrcType, llvm::Constant *StaticArgs[] = { CGF.EmitCheckSourceLocation(Loc), CGF.EmitCheckTypeDescriptor(SrcType), CGF.EmitCheckTypeDescriptor(DstType), - llvm::ConstantInt::get(Builder.getInt8Ty(), CheckKind)}; + llvm::ConstantInt::get(Builder.getInt8Ty(), CheckKind), + llvm::ConstantInt::get(Builder.getInt32Ty(), 0)}; // EmitCheck() will 'and' all the checks together. CGF.EmitCheck(Checks, SanitizerHandler::ImplicitConversion, StaticArgs, {Src, Dst}); } +// Should be called within CodeGenFunction::SanitizerScope RAII scope. +// Returns 'i1 false' when the truncation Src -> Dst was lossy. +static std::pair> +EmitBitfieldTruncationCheckHelper(Value *Src, QualType SrcType, Value *Dst, + QualType DstType, CGBuilderTy &Builder) { + bool SrcSigned = SrcType->isSignedIntegerOrEnumerationType(); + bool DstSigned = DstType->isSignedIntegerOrEnumerationType(); + + ScalarExprEmitter::ImplicitConversionCheckKind Kind; + if (!SrcSigned && !DstSigned) + Kind = ScalarExprEmitter::ICCK_UnsignedIntegerTruncation; + else + Kind = ScalarExprEmitter::ICCK_SignedIntegerTruncation; + + llvm::Value *Check = nullptr; + // 1. Extend the truncated value back to the same width as the Src. + Check = Builder.CreateIntCast(Dst, Src->getType(), DstSigned, "bf.anyext"); + // 2. Equality-compare with the original source value + Check = Builder.CreateICmpEQ(Check, Src, "bf.truncheck"); + // If the comparison result is 'i1 false', then the truncation was lossy. + + return std::make_pair( + Kind, std::make_pair(Check, SanitizerKind::ImplicitBitfieldConversion)); +} + +// Should be called within CodeGenFunction::SanitizerScope RAII scope. +// Returns 'i1 false' when the conversion Src -> Dst changed the sign. +static std::pair> +EmitBitfieldSignChangeCheckHelper(Value *Src, QualType SrcType, Value *Dst, + QualType DstType, CGBuilderTy &Builder) { + // 1. Was the old Value negative? + llvm::Value *SrcIsNegative = + EmitIsNegativeTestHelper(Src, SrcType, "bf.src", Builder); + // 2. Is the new Value negative? + llvm::Value *DstIsNegative = + EmitIsNegativeTestHelper(Dst, DstType, "bf.dst", Builder); + // 3. Now, was the 'negativity status' preserved during the conversion? + // NOTE: conversion from negative to zero is considered to change the sign. + // (We want to get 'false' when the conversion changed the sign) + // So we should just equality-compare the negativity statuses. + llvm::Value *Check = nullptr; + Check = + Builder.CreateICmpEQ(SrcIsNegative, DstIsNegative, "bf.signchangecheck"); + // If the comparison result is 'false', then the conversion changed the sign. + return std::make_pair( + ScalarExprEmitter::ICCK_IntegerSignChange, + std::make_pair(Check, SanitizerKind::ImplicitBitfieldConversion)); +} + +void CodeGenFunction::EmitBitfieldConversionCheck(Value *Src, QualType SrcType, + Value *Dst, QualType DstType, + const CGBitFieldInfo &Info, + SourceLocation Loc) { + + if (!SanOpts.has(SanitizerKind::ImplicitBitfieldConversion)) + return; + + // We only care about int->int conversions here. + // We ignore conversions to/from pointer and/or bool. + if (!PromotionIsPotentiallyEligibleForImplicitIntegerConversionCheck(SrcType, + DstType)) + return; + + if (DstType->isBooleanType() || SrcType->isBooleanType()) + return; + + // This should be truncation of integral types. + assert(isa(Src->getType()) && + isa(Dst->getType()) && "non-integer llvm type"); + + // TODO: Calculate src width to avoid emitting code + // for unecessary cases. + unsigned SrcBits = ConvertType(SrcType)->getScalarSizeInBits(); + unsigned DstBits = Info.Size; + + bool SrcSigned = SrcType->isSignedIntegerOrEnumerationType(); + bool DstSigned = DstType->isSignedIntegerOrEnumerationType(); + + CodeGenFunction::SanitizerScope SanScope(this); + + std::pair> + Check; + + // Truncation + bool EmitTruncation = DstBits < SrcBits; + // If Dst is signed and Src unsigned, we want to be more specific + // about the CheckKind we emit, in this case we want to emit + // ICCK_SignedIntegerTruncationOrSignChange. + bool EmitTruncationFromUnsignedToSigned = + EmitTruncation && DstSigned && !SrcSigned; + // Sign change + bool SameTypeSameSize = SrcSigned == DstSigned && SrcBits == DstBits; + bool BothUnsigned = !SrcSigned && !DstSigned; + bool LargerSigned = (DstBits > SrcBits) && DstSigned; + // We can avoid emitting sign change checks in some obvious cases + // 1. If Src and Dst have the same signedness and size + // 2. If both are unsigned sign check is unecessary! + // 3. If Dst is signed and bigger than Src, either + // sign-extension or zero-extension will make sure + // the sign remains. + bool EmitSignChange = !SameTypeSameSize && !BothUnsigned && !LargerSigned; + + if (EmitTruncation) + Check = + EmitBitfieldTruncationCheckHelper(Src, SrcType, Dst, DstType, Builder); + else if (EmitSignChange) { + assert(((SrcBits != DstBits) || (SrcSigned != DstSigned)) && + "either the widths should be different, or the signednesses."); + Check = + EmitBitfieldSignChangeCheckHelper(Src, SrcType, Dst, DstType, Builder); + } else + return; + + ScalarExprEmitter::ImplicitConversionCheckKind CheckKind = Check.first; + if (EmitTruncationFromUnsignedToSigned) + CheckKind = ScalarExprEmitter::ICCK_SignedIntegerTruncationOrSignChange; + + llvm::Constant *StaticArgs[] = { + EmitCheckSourceLocation(Loc), EmitCheckTypeDescriptor(SrcType), + EmitCheckTypeDescriptor(DstType), + llvm::ConstantInt::get(Builder.getInt8Ty(), CheckKind), + llvm::ConstantInt::get(Builder.getInt32Ty(), Info.Size)}; + + EmitCheck(Check.second, SanitizerHandler::ImplicitConversion, StaticArgs, + {Src, Dst}); +} + Value *ScalarExprEmitter::EmitScalarCast(Value *Src, QualType SrcType, QualType DstType, llvm::Type *SrcTy, llvm::Type *DstTy, @@ -2620,6 +2752,8 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, llvm::PHINode *atomicPHI = nullptr; llvm::Value *value; llvm::Value *input; + llvm::Value *Previous = nullptr; + QualType SrcType = E->getType(); int amount = (isInc ? 1 : -1); bool isSubtraction = !isInc; @@ -2708,7 +2842,8 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, "base or promoted) will be signed, or the bitwidths will match."); } if (CGF.SanOpts.hasOneOf( - SanitizerKind::ImplicitIntegerArithmeticValueChange) && + SanitizerKind::ImplicitIntegerArithmeticValueChange | + SanitizerKind::ImplicitBitfieldConversion) && canPerformLossyDemotionCheck) { // While `x += 1` (for `x` with width less than int) is modeled as // promotion+arithmetics+demotion, and we can catch lossy demotion with @@ -2719,13 +2854,26 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, // the increment/decrement in the wider type, and finally // perform the demotion. This will catch lossy demotions. + // We have a special case for bitfields defined using all the bits of the + // type. In this case we need to do the same trick as for the integer + // sanitizer checks, i.e., promotion -> increment/decrement -> demotion. + value = EmitScalarConversion(value, type, promotedType, E->getExprLoc()); Value *amt = llvm::ConstantInt::get(value->getType(), amount, true); value = Builder.CreateAdd(value, amt, isInc ? "inc" : "dec"); // Do pass non-default ScalarConversionOpts so that sanitizer check is - // emitted. + // emitted if LV is not a bitfield, otherwise the bitfield sanitizer + // checks will take care of the conversion. + ScalarConversionOpts Opts; + if (!LV.isBitField()) + Opts = ScalarConversionOpts(CGF.SanOpts); + else if (CGF.SanOpts.has(SanitizerKind::ImplicitBitfieldConversion)) { + Previous = value; + SrcType = promotedType; + } + value = EmitScalarConversion(value, promotedType, type, E->getExprLoc(), - ScalarConversionOpts(CGF.SanOpts)); + Opts); // Note that signed integer inc/dec with width less than int can't // overflow because of promotion rules; we're just eliding a few steps @@ -2910,9 +3058,12 @@ ScalarExprEmitter::EmitScalarPrePostIncDec(const UnaryOperator *E, LValue LV, } // Store the updated result through the lvalue. - if (LV.isBitField()) + if (LV.isBitField()) { + Value *Src = Previous ? Previous : value; CGF.EmitStoreThroughBitfieldLValue(RValue::get(value), LV, &value); - else + CGF.EmitBitfieldConversionCheck(Src, SrcType, value, E->getType(), + LV.getBitFieldInfo(), E->getExprLoc()); + } else CGF.EmitStoreThroughLValue(RValue::get(value), LV); // If this is a postinc, return the value read from memory, otherwise use the @@ -3417,8 +3568,15 @@ LValue ScalarExprEmitter::EmitCompoundAssignLValue( // Convert the result back to the LHS type, // potentially with Implicit Conversion sanitizer check. - Result = EmitScalarConversion(Result, PromotionTypeCR, LHSTy, Loc, - ScalarConversionOpts(CGF.SanOpts)); + // If LHSLV is a bitfield, use default ScalarConversionOpts + // to avoid emit any implicit integer checks. + Value *Previous = nullptr; + if (LHSLV.isBitField()) { + Previous = Result; + Result = EmitScalarConversion(Result, PromotionTypeCR, LHSTy, Loc); + } else + Result = EmitScalarConversion(Result, PromotionTypeCR, LHSTy, Loc, + ScalarConversionOpts(CGF.SanOpts)); if (atomicPHI) { llvm::BasicBlock *curBlock = Builder.GetInsertBlock(); @@ -3437,9 +3595,14 @@ LValue ScalarExprEmitter::EmitCompoundAssignLValue( // specially because the result is altered by the store, i.e., [C99 6.5.16p1] // 'An assignment expression has the value of the left operand after the // assignment...'. - if (LHSLV.isBitField()) + if (LHSLV.isBitField()) { + Value *Src = Previous ? Previous : Result; + QualType SrcType = E->getRHS()->getType(); + QualType DstType = E->getLHS()->getType(); CGF.EmitStoreThroughBitfieldLValue(RValue::get(Result), LHSLV, &Result); - else + CGF.EmitBitfieldConversionCheck(Src, SrcType, Result, DstType, + LHSLV.getBitFieldInfo(), E->getExprLoc()); + } else CGF.EmitStoreThroughLValue(RValue::get(Result), LHSLV); if (CGF.getLangOpts().OpenMP) @@ -4551,6 +4714,24 @@ Value *ScalarExprEmitter::EmitCompare(const BinaryOperator *E, E->getExprLoc()); } +llvm::Value *CodeGenFunction::EmitWithOriginalRHSBitfieldAssignment( + const BinaryOperator *E, Value **Previous, QualType *SrcType) { + // In case we have the integer or bitfield sanitizer checks enabled + // we want to get the expression before scalar conversion. + if (auto *ICE = dyn_cast(E->getRHS())) { + CastKind Kind = ICE->getCastKind(); + if (Kind == CK_IntegralCast || Kind == CK_LValueToRValue) { + *SrcType = ICE->getSubExpr()->getType(); + *Previous = EmitScalarExpr(ICE->getSubExpr()); + // Pass default ScalarConversionOpts to avoid emitting + // integer sanitizer checks as E refers to bitfield. + return EmitScalarConversion(*Previous, *SrcType, ICE->getType(), + ICE->getExprLoc()); + } + } + return EmitScalarExpr(E->getRHS()); +} + Value *ScalarExprEmitter::VisitBinAssign(const BinaryOperator *E) { bool Ignore = TestAndClearIgnoreResultAssign(); @@ -4579,7 +4760,16 @@ Value *ScalarExprEmitter::VisitBinAssign(const BinaryOperator *E) { case Qualifiers::OCL_None: // __block variables need to have the rhs evaluated first, plus // this should improve codegen just a little. - RHS = Visit(E->getRHS()); + Value *Previous = nullptr; + QualType SrcType = E->getRHS()->getType(); + // Check if LHS is a bitfield, if RHS contains an implicit cast expression + // we want to extract that value and potentially (if the bitfield sanitizer + // is enabled) use it to check for an implicit conversion. + if (E->getLHS()->refersToBitField()) + RHS = CGF.EmitWithOriginalRHSBitfieldAssignment(E, &Previous, &SrcType); + else + RHS = Visit(E->getRHS()); + LHS = EmitCheckedLValue(E->getLHS(), CodeGenFunction::TCK_Store); // Store the value into the LHS. Bit-fields are handled specially @@ -4588,6 +4778,12 @@ Value *ScalarExprEmitter::VisitBinAssign(const BinaryOperator *E) { // the assignment...'. if (LHS.isBitField()) { CGF.EmitStoreThroughBitfieldLValue(RValue::get(RHS), LHS, &RHS); + // If the expression contained an implicit conversion, make sure + // to use the value before the scalar conversion. + Value *Src = Previous ? Previous : RHS; + QualType DstType = E->getLHS()->getType(); + CGF.EmitBitfieldConversionCheck(Src, SrcType, RHS, DstType, + LHS.getBitFieldInfo(), E->getExprLoc()); } else { CGF.EmitNullabilityCheck(LHS, RHS, E->getExprLoc()); CGF.EmitStoreThroughLValue(RValue::get(RHS), LHS); diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index e2a7e28c8211..ff1873325d40 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -2786,6 +2786,21 @@ public: /// expression and compare the result against zero, returning an Int1Ty value. llvm::Value *EvaluateExprAsBool(const Expr *E); + /// Retrieve the implicit cast expression of the rhs in a binary operator + /// expression by passing pointers to Value and QualType + /// This is used for implicit bitfield conversion checks, which + /// must compare with the value before potential truncation. + llvm::Value *EmitWithOriginalRHSBitfieldAssignment(const BinaryOperator *E, + llvm::Value **Previous, + QualType *SrcType); + + /// Emit a check that an [implicit] conversion of a bitfield. It is not UB, + /// so we use the value after conversion. + void EmitBitfieldConversionCheck(llvm::Value *Src, QualType SrcType, + llvm::Value *Dst, QualType DstType, + const CGBitFieldInfo &Info, + SourceLocation Loc); + /// EmitIgnoredExpr - Emit an expression in a context which ignores the result. void EmitIgnoredExpr(const Expr *E); diff --git a/clang/test/CodeGen/catch-implicit-conversions-basics.c b/clang/test/CodeGen/catch-implicit-conversions-basics.c index 6bc5472bf39d..e658a9aab50f 100644 --- a/clang/test/CodeGen/catch-implicit-conversions-basics.c +++ b/clang/test/CodeGen/catch-implicit-conversions-basics.c @@ -9,15 +9,15 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1 } -// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 4 } -// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } +// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 4, i32 0 } +// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } // CHECK-LABEL: @convert_unsigned_int_to_unsigned_int unsigned int convert_unsigned_int_to_unsigned_int(unsigned int x) { diff --git a/clang/test/CodeGen/catch-implicit-conversions-incdec-basics.c b/clang/test/CodeGen/catch-implicit-conversions-incdec-basics.c index 2ce0c6ef21b4..da2e0d00d51e 100644 --- a/clang/test/CodeGen/catch-implicit-conversions-incdec-basics.c +++ b/clang/test/CodeGen/catch-implicit-conversions-incdec-basics.c @@ -2,25 +2,25 @@ // CHECK-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-DAG: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-LABEL: @t0( unsigned short t0(unsigned short x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-basics.c b/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-basics.c index 32ed6b1a7bac..645c0708e369 100644 --- a/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-basics.c @@ -9,14 +9,14 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 4 } -// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 4, i32 0 } +// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } // CHECK-LABEL: @convert_unsigned_int_to_unsigned_int unsigned int convert_unsigned_int_to_unsigned_int(unsigned int x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-incdec-basics.c b/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-incdec-basics.c index 8bc89f43e55c..50cde38bb854 100644 --- a/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-incdec-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-arithmetic-value-change-incdec-basics.c @@ -2,25 +2,25 @@ // CHECK-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-DAG: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-LABEL: @t0( unsigned short t0(unsigned short x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-conversions-basics.c b/clang/test/CodeGen/catch-implicit-integer-conversions-basics.c index 6bc5472bf39d..e658a9aab50f 100644 --- a/clang/test/CodeGen/catch-implicit-integer-conversions-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-conversions-basics.c @@ -9,15 +9,15 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1 } -// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 4 } -// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } +// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 4, i32 0 } +// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } // CHECK-LABEL: @convert_unsigned_int_to_unsigned_int unsigned int convert_unsigned_int_to_unsigned_int(unsigned int x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-conversions-incdec-basics.c b/clang/test/CodeGen/catch-implicit-integer-conversions-incdec-basics.c index 2ce0c6ef21b4..da2e0d00d51e 100644 --- a/clang/test/CodeGen/catch-implicit-integer-conversions-incdec-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-conversions-incdec-basics.c @@ -2,25 +2,25 @@ // CHECK-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-DAG: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-LABEL: @t0( unsigned short t0(unsigned short x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-sign-changes-CompoundAssignOperator.c b/clang/test/CodeGen/catch-implicit-integer-sign-changes-CompoundAssignOperator.c index d6aff6c0b54e..197ec53edaed 100644 --- a/clang/test/CodeGen/catch-implicit-integer-sign-changes-CompoundAssignOperator.c +++ b/clang/test/CodeGen/catch-implicit-integer-sign-changes-CompoundAssignOperator.c @@ -12,89 +12,89 @@ // CHECK-SANITIZE-ANYRECOVER: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_SIGN_CHANGE:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGN_CHANGE:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGN_CHANGE:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_SIGN_CHANGE:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGN_CHANGE:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGN_CHANGE:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_SIGN_CHANGE:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_600_SIGN_CHANGE:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_SIGN_CHANGE:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_600_SIGN_CHANGE:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_INT:.*]] = {{.*}} c"'unsigned int'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_700_SIGN_CHANGE:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_800_SIGN_CHANGE:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1500_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1600_SIGN_CHANGE:.*]] = {{.*}}, i32 1600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1700_SIGN_CHANGE:.*]] = {{.*}}, i32 1700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1800_SIGN_CHANGE:.*]] = {{.*}}, i32 1800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2000_SIGN_CHANGE:.*]] = {{.*}}, i32 2000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2100_SIGN_CHANGE:.*]] = {{.*}}, i32 2100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2200_SIGN_CHANGE:.*]] = {{.*}}, i32 2200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2300_SIGN_CHANGE:.*]] = {{.*}}, i32 2300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2400_SIGN_CHANGE:.*]] = {{.*}}, i32 2400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2500_SIGN_CHANGE:.*]] = {{.*}}, i32 2500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2600_SIGN_CHANGE:.*]] = {{.*}}, i32 2600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2800_SIGN_CHANGE:.*]] = {{.*}}, i32 2800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2900_SIGN_CHANGE:.*]] = {{.*}}, i32 2900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3000_SIGN_CHANGE:.*]] = {{.*}}, i32 3000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3100_SIGN_CHANGE:.*]] = {{.*}}, i32 3100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3200_SIGN_CHANGE:.*]] = {{.*}}, i32 3200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3300_SIGN_CHANGE:.*]] = {{.*}}, i32 3300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3400_SIGN_CHANGE:.*]] = {{.*}}, i32 3400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3600_SIGN_CHANGE:.*]] = {{.*}}, i32 3600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3700_SIGN_CHANGE:.*]] = {{.*}}, i32 3700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3800_SIGN_CHANGE:.*]] = {{.*}}, i32 3800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3900_SIGN_CHANGE:.*]] = {{.*}}, i32 3900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4000_SIGN_CHANGE:.*]] = {{.*}}, i32 4000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4100_SIGN_CHANGE:.*]] = {{.*}}, i32 4100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4200_SIGN_CHANGE:.*]] = {{.*}}, i32 4200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4300_SIGN_CHANGE:.*]] = {{.*}}, i32 4300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4400_SIGN_CHANGE:.*]] = {{.*}}, i32 4400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4500_SIGN_CHANGE:.*]] = {{.*}}, i32 4500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4600_SIGN_CHANGE:.*]] = {{.*}}, i32 4600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4700_SIGN_CHANGE:.*]] = {{.*}}, i32 4700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4800_SIGN_CHANGE:.*]] = {{.*}}, i32 4800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4900_SIGN_CHANGE:.*]] = {{.*}}, i32 4900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5000_SIGN_CHANGE:.*]] = {{.*}}, i32 5000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5100_SIGN_CHANGE:.*]] = {{.*}}, i32 5100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5200_SIGN_CHANGE:.*]] = {{.*}}, i32 5200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5300_SIGN_CHANGE:.*]] = {{.*}}, i32 5300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5400_SIGN_CHANGE:.*]] = {{.*}}, i32 5400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5500_SIGN_CHANGE:.*]] = {{.*}}, i32 5500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5600_SIGN_CHANGE:.*]] = {{.*}}, i32 5600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5700_SIGN_CHANGE:.*]] = {{.*}}, i32 5700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5800_SIGN_CHANGE:.*]] = {{.*}}, i32 5800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6000_SIGN_CHANGE:.*]] = {{.*}}, i32 6000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6100_SIGN_CHANGE:.*]] = {{.*}}, i32 6100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6200_SIGN_CHANGE:.*]] = {{.*}}, i32 6200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6300_SIGN_CHANGE:.*]] = {{.*}}, i32 6300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6400_SIGN_CHANGE:.*]] = {{.*}}, i32 6400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6500_SIGN_CHANGE:.*]] = {{.*}}, i32 6500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6600_SIGN_CHANGE:.*]] = {{.*}}, i32 6600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6800_SIGN_CHANGE:.*]] = {{.*}}, i32 6800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6900_SIGN_CHANGE:.*]] = {{.*}}, i32 6900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7000_SIGN_CHANGE:.*]] = {{.*}}, i32 7000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7100_SIGN_CHANGE:.*]] = {{.*}}, i32 7100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7200_SIGN_CHANGE:.*]] = {{.*}}, i32 7200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7300_SIGN_CHANGE:.*]] = {{.*}}, i32 7300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7400_SIGN_CHANGE:.*]] = {{.*}}, i32 7400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7600_SIGN_CHANGE:.*]] = {{.*}}, i32 7600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7700_SIGN_CHANGE:.*]] = {{.*}}, i32 7700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7800_SIGN_CHANGE:.*]] = {{.*}}, i32 7800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7900_SIGN_CHANGE:.*]] = {{.*}}, i32 7900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_8000_SIGN_CHANGE:.*]] = {{.*}}, i32 8000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_700_SIGN_CHANGE:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_800_SIGN_CHANGE:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1500_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1600_SIGN_CHANGE:.*]] = {{.*}}, i32 1600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1700_SIGN_CHANGE:.*]] = {{.*}}, i32 1700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1800_SIGN_CHANGE:.*]] = {{.*}}, i32 1800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2000_SIGN_CHANGE:.*]] = {{.*}}, i32 2000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2100_SIGN_CHANGE:.*]] = {{.*}}, i32 2100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2200_SIGN_CHANGE:.*]] = {{.*}}, i32 2200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2300_SIGN_CHANGE:.*]] = {{.*}}, i32 2300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2400_SIGN_CHANGE:.*]] = {{.*}}, i32 2400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2500_SIGN_CHANGE:.*]] = {{.*}}, i32 2500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2600_SIGN_CHANGE:.*]] = {{.*}}, i32 2600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2800_SIGN_CHANGE:.*]] = {{.*}}, i32 2800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2900_SIGN_CHANGE:.*]] = {{.*}}, i32 2900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3000_SIGN_CHANGE:.*]] = {{.*}}, i32 3000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3100_SIGN_CHANGE:.*]] = {{.*}}, i32 3100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3200_SIGN_CHANGE:.*]] = {{.*}}, i32 3200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3300_SIGN_CHANGE:.*]] = {{.*}}, i32 3300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3400_SIGN_CHANGE:.*]] = {{.*}}, i32 3400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3600_SIGN_CHANGE:.*]] = {{.*}}, i32 3600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3700_SIGN_CHANGE:.*]] = {{.*}}, i32 3700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3800_SIGN_CHANGE:.*]] = {{.*}}, i32 3800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3900_SIGN_CHANGE:.*]] = {{.*}}, i32 3900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4000_SIGN_CHANGE:.*]] = {{.*}}, i32 4000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4100_SIGN_CHANGE:.*]] = {{.*}}, i32 4100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4200_SIGN_CHANGE:.*]] = {{.*}}, i32 4200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4300_SIGN_CHANGE:.*]] = {{.*}}, i32 4300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4400_SIGN_CHANGE:.*]] = {{.*}}, i32 4400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4500_SIGN_CHANGE:.*]] = {{.*}}, i32 4500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4600_SIGN_CHANGE:.*]] = {{.*}}, i32 4600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4700_SIGN_CHANGE:.*]] = {{.*}}, i32 4700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4800_SIGN_CHANGE:.*]] = {{.*}}, i32 4800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4900_SIGN_CHANGE:.*]] = {{.*}}, i32 4900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5000_SIGN_CHANGE:.*]] = {{.*}}, i32 5000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5100_SIGN_CHANGE:.*]] = {{.*}}, i32 5100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5200_SIGN_CHANGE:.*]] = {{.*}}, i32 5200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5300_SIGN_CHANGE:.*]] = {{.*}}, i32 5300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5400_SIGN_CHANGE:.*]] = {{.*}}, i32 5400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5500_SIGN_CHANGE:.*]] = {{.*}}, i32 5500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5600_SIGN_CHANGE:.*]] = {{.*}}, i32 5600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5700_SIGN_CHANGE:.*]] = {{.*}}, i32 5700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5800_SIGN_CHANGE:.*]] = {{.*}}, i32 5800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6000_SIGN_CHANGE:.*]] = {{.*}}, i32 6000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6100_SIGN_CHANGE:.*]] = {{.*}}, i32 6100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6200_SIGN_CHANGE:.*]] = {{.*}}, i32 6200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6300_SIGN_CHANGE:.*]] = {{.*}}, i32 6300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6400_SIGN_CHANGE:.*]] = {{.*}}, i32 6400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6500_SIGN_CHANGE:.*]] = {{.*}}, i32 6500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6600_SIGN_CHANGE:.*]] = {{.*}}, i32 6600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6800_SIGN_CHANGE:.*]] = {{.*}}, i32 6800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6900_SIGN_CHANGE:.*]] = {{.*}}, i32 6900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7000_SIGN_CHANGE:.*]] = {{.*}}, i32 7000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7100_SIGN_CHANGE:.*]] = {{.*}}, i32 7100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7200_SIGN_CHANGE:.*]] = {{.*}}, i32 7200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7300_SIGN_CHANGE:.*]] = {{.*}}, i32 7300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7400_SIGN_CHANGE:.*]] = {{.*}}, i32 7400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7600_SIGN_CHANGE:.*]] = {{.*}}, i32 7600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7700_SIGN_CHANGE:.*]] = {{.*}}, i32 7700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7800_SIGN_CHANGE:.*]] = {{.*}}, i32 7800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7900_SIGN_CHANGE:.*]] = {{.*}}, i32 7900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_8000_SIGN_CHANGE:.*]] = {{.*}}, i32 8000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } //----------------------------------------------------------------------------// // Compound add operator. // diff --git a/clang/test/CodeGen/catch-implicit-integer-sign-changes-basics.c b/clang/test/CodeGen/catch-implicit-integer-sign-changes-basics.c index 22d44e6ab9e4..bc912827d29d 100644 --- a/clang/test/CodeGen/catch-implicit-integer-sign-changes-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-sign-changes-basics.c @@ -9,14 +9,14 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1100_SIGN_CHANGE:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1500_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 3 } -// CHECK-DAG: @[[LINE_1600_SIGN_CHANGE:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 3 } +// CHECK-DAG: @[[LINE_900_SIGN_CHANGE:.*]] = {{.*}}, i32 900, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1000_SIGN_CHANGE:.*]] = {{.*}}, i32 1000, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1100_SIGN_CHANGE:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1200_SIGN_CHANGE:.*]] = {{.*}}, i32 1200, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1300_SIGN_CHANGE:.*]] = {{.*}}, i32 1300, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1400_SIGN_CHANGE:.*]] = {{.*}}, i32 1400, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1500_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1600_SIGN_CHANGE:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 3, i32 0 } //============================================================================// // Half of the cases do not need the check. // diff --git a/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec-basics.c b/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec-basics.c index 9f3f53fa1fd0..fec90fa4b6c7 100644 --- a/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec-basics.c @@ -2,25 +2,25 @@ // CHECK-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } -// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } -// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } -// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } +// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } // CHECK-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } -// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } -// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } -// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } +// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } // CHECK-DAG: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } +// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } // CHECK-DAG: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3 } +// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } // CHECK-LABEL: @t0( unsigned short t0(unsigned short x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec.c b/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec.c index 0de45720e956..00cf75af2286 100644 --- a/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec.c +++ b/clang/test/CodeGen/catch-implicit-integer-sign-changes-incdec.c @@ -6,15 +6,15 @@ // CHECK-SANITIZE-ANYRECOVER-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-SANITIZE-ANYRECOVER-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 3, i32 0 } // CHECK-SANITIZE-ANYRECOVER-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 3, i32 0 } unsigned short t0(unsigned short x) { // CHECK-NOSANITIZE-LABEL: @t0( diff --git a/clang/test/CodeGen/catch-implicit-integer-sign-changes.c b/clang/test/CodeGen/catch-implicit-integer-sign-changes.c index e91aec61a430..8d5bad73112e 100644 --- a/clang/test/CodeGen/catch-implicit-integer-sign-changes.c +++ b/clang/test/CodeGen/catch-implicit-integer-sign-changes.c @@ -5,19 +5,19 @@ // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_INT:.*]] = {{.*}} c"'unsigned int'\00" } // CHECK-SANITIZE-ANYRECOVER-NEXT: @[[SIGNED_INT:.*]] = {{.*}} c"'int'\00" } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_INT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[UNSIGNED_INT]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_INT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[UNSIGNED_INT]], i8 3, i32 0 } // CHECK-SANITIZE-ANYRECOVER-NEXT: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } // CHECK-SANITIZE-ANYRECOVER-NEXT: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[SIGNED_CHAR]], ptr @[[UNSIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[UNSIGNED_CHAR]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[SIGNED_CHAR]], ptr @[[UNSIGNED_INT]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[SIGNED_CHAR]], ptr @[[UNSIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[UNSIGNED_CHAR]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[SIGNED_CHAR]], ptr @[[UNSIGNED_INT]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[UINT32:.*]] = {{.*}} c"'uint32_t' (aka 'unsigned int')\00" } // CHECK-SANITIZE-ANYRECOVER: @[[INT32:.*]] = {{.*}} c"'int32_t' (aka 'int')\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[UINT32]], ptr @[[INT32]], i8 3 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[UINT32]], ptr @[[INT32]], i8 3, i32 0 } // ========================================================================== // // The expected true-positives. diff --git a/clang/test/CodeGen/catch-implicit-integer-truncations-CompoundAssignOperator.c b/clang/test/CodeGen/catch-implicit-integer-truncations-CompoundAssignOperator.c index 866e25ef127f..2c81a5c93ee1 100644 --- a/clang/test/CodeGen/catch-implicit-integer-truncations-CompoundAssignOperator.c +++ b/clang/test/CodeGen/catch-implicit-integer-truncations-CompoundAssignOperator.c @@ -12,97 +12,97 @@ // CHECK-SANITIZE-ANYRECOVER: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_INT:.*]] = {{.*}} c"'unsigned int'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_300_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_300_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1900_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 1900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2700_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 2700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 3500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5900_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 5900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6700_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 6700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 7500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_8000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 8000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1900_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 1900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2700_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 2700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 3500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5900_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 5900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6700_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 6700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 7500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_8000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 8000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } //----------------------------------------------------------------------------// // Compound add operator. // diff --git a/clang/test/CodeGen/catch-implicit-integer-truncations-basics-negatives.c b/clang/test/CodeGen/catch-implicit-integer-truncations-basics-negatives.c index 3acd1c5e5f3b..c1837f39180d 100644 --- a/clang/test/CodeGen/catch-implicit-integer-truncations-basics-negatives.c +++ b/clang/test/CodeGen/catch-implicit-integer-truncations-basics-negatives.c @@ -1,9 +1,9 @@ // RUN: %clang_cc1 -fsanitize=implicit-unsigned-integer-truncation,implicit-signed-integer-truncation -fsanitize-recover=implicit-unsigned-integer-truncation,implicit-signed-integer-truncation -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s -implicit-check-not="call void @__ubsan_handle_implicit_conversion" --check-prefixes=CHECK -// CHECK-DAG: @[[LINE_100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}, {{.*}}, i8 1 } -// CHECK-DAG: @[[LINE_200_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, {{.*}}, {{.*}}, i8 1 } -// CHECK-DAG: @[[LINE_300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 300, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } +// CHECK-DAG: @[[LINE_200_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } +// CHECK-DAG: @[[LINE_300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 300, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } //----------------------------------------------------------------------------// // Unsigned case. diff --git a/clang/test/CodeGen/catch-implicit-integer-truncations-basics.c b/clang/test/CodeGen/catch-implicit-integer-truncations-basics.c index eccfc374c05c..16320b8822d7 100644 --- a/clang/test/CodeGen/catch-implicit-integer-truncations-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-truncations-basics.c @@ -9,10 +9,10 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1 } -// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } +// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } // CHECK-LABEL: @convert_unsigned_int_to_unsigned_int unsigned int convert_unsigned_int_to_unsigned_int(unsigned int x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-truncations-incdec-basics.c b/clang/test/CodeGen/catch-implicit-integer-truncations-incdec-basics.c index 5bf859dd893a..40a1e789b543 100644 --- a/clang/test/CodeGen/catch-implicit-integer-truncations-incdec-basics.c +++ b/clang/test/CodeGen/catch-implicit-integer-truncations-incdec-basics.c @@ -2,25 +2,25 @@ // CHECK-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-DAG: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-LABEL: @t0( unsigned short t0(unsigned short x) { diff --git a/clang/test/CodeGen/catch-implicit-integer-truncations.c b/clang/test/CodeGen/catch-implicit-integer-truncations.c index 17b64b9bbe39..8f991b14ad77 100644 --- a/clang/test/CodeGen/catch-implicit-integer-truncations.c +++ b/clang/test/CodeGen/catch-implicit-integer-truncations.c @@ -6,16 +6,16 @@ // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_INT:.*]] = {{.*}} c"'unsigned int'\00" } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 1, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[SIGNED_INT:.*]] = {{.*}} c"'int'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[SIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[UINT32:.*]] = {{.*}} c"'uint32_t' (aka 'unsigned int')\00" } // CHECK-SANITIZE-ANYRECOVER: @[[UINT8:.*]] = {{.*}} c"'uint8_t' (aka 'unsigned char')\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[UINT32]], ptr @[[UINT8]], i8 1 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[UINT32]], ptr @[[UINT8]], i8 1, i32 0 } // ========================================================================== // // The expected true-positives. These are implicit conversions, and they truncate. diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change-CompoundAssignOperator.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change-CompoundAssignOperator.c index c131bbba1c58..34ffc8bf56a4 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change-CompoundAssignOperator.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change-CompoundAssignOperator.c @@ -12,89 +12,89 @@ // CHECK-SANITIZE-ANYRECOVER: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_INT:.*]] = {{.*}} c"'unsigned int'\00" } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_700_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2300_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 2300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3100_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 3100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3900_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 3900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6300_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 6300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7100_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 7100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } - -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7900_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 7900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER: @[[LINE_8000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 8000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_700_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1500_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 1500, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_1800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2300_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 2300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_2900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 2900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3100_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 3100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 3800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_3900_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 3900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_4900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 4900, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5100, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5200, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5300, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5500, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5600, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5700, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_5800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 5800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6000, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6100, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6300_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 6300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6400, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6500, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6800, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_6900_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 6900, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7100_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 7100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7200, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } + +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7300_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7600, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7700_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7700, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7800_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 7800, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_7900_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 7900, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER: @[[LINE_8000_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 8000, i32 10 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } //----------------------------------------------------------------------------// // Compound add operator. // diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c index b26d4b1924c1..758fc85f894f 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncation-or-sign-change.c @@ -5,10 +5,10 @@ // CHECK-SANITIZE-ANYRECOVER: @[[UNSIGNED_INT:.*]] = {{.*}} c"'unsigned int'\00" } // CHECK-SANITIZE-ANYRECOVER-NEXT: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_100_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_200_SIGN_CHANGE:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_300_SIGN_CHANGE:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3 } -// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_100_SIGNED_TRUNCATION_OR_SIGN_CHANGE:.*]] = {{.*}}, i32 100, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 4, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_200_SIGN_CHANGE:.*]] = {{.*}}, i32 200, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_300_SIGN_CHANGE:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 3, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-NEXT: @[[LINE_400_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[UNSIGNED_INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } //============================================================================// // Both sanitizers are enabled, and not disabled per-function. diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics-negatives.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics-negatives.c index 496599a650d2..9466af731478 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics-negatives.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics-negatives.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -fsanitize=implicit-signed-integer-truncation -fsanitize-recover=implicit-signed-integer-truncation -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s -implicit-check-not="call void @__ubsan_handle_implicit_conversion" --check-prefixes=CHECK -// CHECK-DAG: @[[LINE_100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_200_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } // CHECK-LABEL: @ignorelist_0_convert_signed_int_to_signed_char __attribute__((no_sanitize("undefined"))) signed char ignorelist_0_convert_signed_int_to_signed_char(signed int x) { diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics.c index 12cb864b7df6..76d522799a6b 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-basics.c @@ -9,9 +9,9 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 2 } -// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2 } +// CHECK-DAG: @[[LINE_1100_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1100, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1500, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600_SIGNED_TRUNCATION:.*]] = {{.*}}, i32 1600, i32 10 }, {{.*}}, {{.*}}, i8 2, i32 0 } // CHECK-LABEL: @convert_unsigned_int_to_unsigned_int unsigned int convert_unsigned_int_to_unsigned_int(unsigned int x) { diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec-basics.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec-basics.c index d0c016a994b6..5885d2dba8f9 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec-basics.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec-basics.c @@ -2,25 +2,25 @@ // CHECK-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } +// CHECK-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 4 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 3 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } // CHECK-DAG: @[[UNSIGNED_CHAR:.*]] = {{.*}} c"'unsigned char'\00" } -// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_900:.*]] = {{.*}}, i32 900, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1000:.*]] = {{.*}}, i32 1000, i32 4 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1100:.*]] = {{.*}}, i32 1100, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1200:.*]] = {{.*}}, i32 1200, i32 3 }, ptr @[[INT]], ptr @[[UNSIGNED_CHAR]], i8 2, i32 0 } // CHECK-DAG: @[[SIGNED_CHAR:.*]] = {{.*}} c"'signed char'\00" } -// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } -// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2 } +// CHECK-DAG: @[[LINE_1300:.*]] = {{.*}}, i32 1300, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1400:.*]] = {{.*}}, i32 1400, i32 4 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1500:.*]] = {{.*}}, i32 1500, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } +// CHECK-DAG: @[[LINE_1600:.*]] = {{.*}}, i32 1600, i32 3 }, ptr @[[INT]], ptr @[[SIGNED_CHAR]], i8 2, i32 0 } // CHECK-LABEL: @t0( unsigned short t0(unsigned short x) { diff --git a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec.c b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec.c index 101cdc83c8dc..84183d7eb72a 100644 --- a/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec.c +++ b/clang/test/CodeGen/catch-implicit-signed-integer-truncations-incdec.c @@ -6,15 +6,15 @@ // CHECK-SANITIZE-ANYRECOVER-DAG: @[[INT:.*]] = {{.*}} c"'int'\00" } // CHECK-SANITIZE-ANYRECOVER-DAG: @[[UNSIGNED_SHORT:.*]] = {{.*}} c"'unsigned short'\00" } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_100:.*]] = {{.*}}, i32 100, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_200:.*]] = {{.*}}, i32 200, i32 11 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_300:.*]] = {{.*}}, i32 300, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_400:.*]] = {{.*}}, i32 400, i32 10 }, ptr @[[INT]], ptr @[[UNSIGNED_SHORT]], i8 2, i32 0 } // CHECK-SANITIZE-ANYRECOVER-DAG: @[[SHORT:.*]] = {{.*}} c"'short'\00" } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } -// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 2 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_500:.*]] = {{.*}}, i32 500, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_600:.*]] = {{.*}}, i32 600, i32 11 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_700:.*]] = {{.*}}, i32 700, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } +// CHECK-SANITIZE-ANYRECOVER-DAG: @[[LINE_800:.*]] = {{.*}}, i32 800, i32 10 }, ptr @[[INT]], ptr @[[SHORT]], i8 2, i32 0 } unsigned short t0(unsigned short x) { // CHECK-NOSANITIZE-LABEL: @t0( diff --git a/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics-negatives.c b/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics-negatives.c index 82f6afd36f2f..297962ec2e53 100644 --- a/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics-negatives.c +++ b/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics-negatives.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -fsanitize=implicit-unsigned-integer-truncation -fsanitize-recover=implicit-unsigned-integer-truncation -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s -implicit-check-not="call void @__ubsan_handle_implicit_conversion" --check-prefixes=CHECK -// CHECK-DAG: @[[LINE_100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}, {{.*}}, i8 1 } -// CHECK-DAG: @[[LINE_200_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, {{.*}}, {{.*}}, i8 1 } +// CHECK-DAG: @[[LINE_100_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 100, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } +// CHECK-DAG: @[[LINE_200_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 200, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } // CHECK-LABEL: @ignorelist_0_convert_unsigned_int_to_unsigned_char __attribute__((no_sanitize("undefined"))) unsigned char ignorelist_0_convert_unsigned_int_to_unsigned_char(unsigned int x) { diff --git a/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics.c b/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics.c index 7eca6e1957c2..156ab208107d 100644 --- a/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics.c +++ b/clang/test/CodeGen/catch-implicit-unsigned-integer-truncations-basics.c @@ -9,7 +9,7 @@ // However, not all of them should result in the check. // So here, we *only* check which should and which should not result in checks. -// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1 } +// CHECK-DAG: @[[LINE_500_UNSIGNED_TRUNCATION:.*]] = {{.*}}, i32 500, i32 10 }, {{.*}}, {{.*}}, i8 1, i32 0 } // CHECK-LABEL: @convert_unsigned_int_to_unsigned_int unsigned int convert_unsigned_int_to_unsigned_int(unsigned int x) { diff --git a/clang/test/CodeGen/ubsan-bitfield-conversion.c b/clang/test/CodeGen/ubsan-bitfield-conversion.c new file mode 100644 index 000000000000..ea9bdd7da6bc --- /dev/null +++ b/clang/test/CodeGen/ubsan-bitfield-conversion.c @@ -0,0 +1,61 @@ +// RUN: %clang -fsanitize=implicit-bitfield-conversion -target x86_64-linux -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BITFIELD-CONVERSION +// RUN: %clang -fsanitize=implicit-integer-conversion -target x86_64-linux -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK +// RUN: %clang -fsanitize=implicit-conversion -target x86_64-linux -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BITFIELD-CONVERSION + +typedef struct _xx { + int x1:3; + char x2:2; +} xx, *pxx; + +xx vxx; + +// CHECK-LABEL: define{{.*}} void @foo1 +void foo1(int x) { + vxx.x1 = x; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} + +// CHECK-LABEL: define{{.*}} void @foo2 +void foo2(int x) { + vxx.x2 = x; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 6 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 6 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} + +// CHECK-LABEL: define{{.*}} void @foo3 +void foo3() { + vxx.x1++; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} + +// CHECK-LABEL: define{{.*}} void @foo4 +void foo4(int x) { + vxx.x1 += x; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} \ No newline at end of file diff --git a/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp b/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp new file mode 100644 index 000000000000..92f6e247c5f5 --- /dev/null +++ b/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp @@ -0,0 +1,94 @@ +// RUN: %clang -x c++ -fsanitize=implicit-bitfield-conversion -target x86_64-linux -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BITFIELD-CONVERSION +// RUN: %clang -x c++ -fsanitize=implicit-integer-conversion -target x86_64-linux -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK +// RUN: %clang -x c++ -fsanitize=implicit-conversion -target x86_64-linux -S -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BITFIELD-CONVERSION + +struct S { + int a:3; + char b:2; +}; + +class C : public S { + public: + short c:3; +}; + +S s; +C c; + +// CHECK-LABEL: define{{.*}} void @{{.*foo1.*}} +void foo1(int x) { + s.a = x; + // CHECK: store i8 %{{.*}} + // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + c.a = x; + // CHECK: store i8 %{{.*}} + // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} + +// CHECK-LABEL: define{{.*}} void @{{.*foo2.*}} +void foo2(int x) { + s.b = x; + // CHECK: store i8 %{{.*}} + // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 6 + // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 6 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + c.b = x; + // CHECK: store i8 %{{.*}} + // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 6 + // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 6 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} + +// CHECK-LABEL: define{{.*}} void @{{.*foo3.*}} +void foo3() { + s.a++; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + c.a++; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} + +// CHECK-LABEL: define{{.*}} void @{{.*foo4.*}} +void foo4(int x) { + s.a += x; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + c.a += x; + // CHECK: store i8 %{{.*}} + // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 + // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 + // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 + // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION: [[CONT]]: + // CHECK-NEXT: ret void +} \ No newline at end of file diff --git a/clang/test/Driver/fsanitize.c b/clang/test/Driver/fsanitize.c index 1671825042c3..571f79a6e7f7 100644 --- a/clang/test/Driver/fsanitize.c +++ b/clang/test/Driver/fsanitize.c @@ -35,20 +35,20 @@ // RUN: %clang --target=%itanium_abi_triple -fsanitize=integer %s -### 2>&1 | FileCheck %s --check-prefix=CHECK-INTEGER -implicit-check-not="-fsanitize-address-use-after-scope" // CHECK-INTEGER: "-fsanitize={{((signed-integer-overflow|unsigned-integer-overflow|integer-divide-by-zero|shift-base|shift-exponent|implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change|unsigned-shift-base),?){9}"}} -// RUN: %clang -fsanitize=implicit-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-conversion,CHECK-implicit-conversion-RECOVER -// RUN: %clang -fsanitize=implicit-conversion -fsanitize-recover=implicit-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-conversion,CHECK-implicit-conversion-RECOVER -// RUN: %clang -fsanitize=implicit-conversion -fno-sanitize-recover=implicit-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-conversion,CHECK-implicit-conversion-NORECOVER -// RUN: %clang -fsanitize=implicit-conversion -fsanitize-trap=implicit-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-conversion,CHECK-implicit-conversion-TRAP -// CHECK-implicit-conversion: "-fsanitize={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-RECOVER: "-fsanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-RECOVER-NOT: "-fno-sanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-RECOVER-NOT: "-fsanitize-trap={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-NORECOVER-NOT: "-fno-sanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} // ??? -// CHECK-implicit-conversion-NORECOVER-NOT: "-fsanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-NORECOVER-NOT: "-fsanitize-trap={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-TRAP: "-fsanitize-trap={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-TRAP-NOT: "-fsanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} -// CHECK-implicit-conversion-TRAP-NOT: "-fno-sanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// RUN: %clang -fsanitize=implicit-integer-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-integer-conversion,CHECK-implicit-integer-conversion-RECOVER +// RUN: %clang -fsanitize=implicit-integer-conversion -fsanitize-recover=implicit-integer-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-integer-conversion,CHECK-implicit-integer-conversion-RECOVER +// RUN: %clang -fsanitize=implicit-integer-conversion -fno-sanitize-recover=implicit-integer-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-integer-conversion,CHECK-implicit-integer-conversion-NORECOVER +// RUN: %clang -fsanitize=implicit-integer-conversion -fsanitize-trap=implicit-integer-conversion %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-integer-conversion,CHECK-implicit-integer-conversion-TRAP +// CHECK-implicit-integer-conversion: "-fsanitize={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-RECOVER: "-fsanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-RECOVER-NOT: "-fno-sanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-RECOVER-NOT: "-fsanitize-trap={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-NORECOVER-NOT: "-fno-sanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} // ??? +// CHECK-implicit-integer-conversion-NORECOVER-NOT: "-fsanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-NORECOVER-NOT: "-fsanitize-trap={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-TRAP: "-fsanitize-trap={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-TRAP-NOT: "-fsanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} +// CHECK-implicit-integer-conversion-TRAP-NOT: "-fno-sanitize-recover={{((implicit-unsigned-integer-truncation|implicit-signed-integer-truncation|implicit-integer-sign-change),?){3}"}} // RUN: %clang -fsanitize=implicit-integer-arithmetic-value-change %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-integer-arithmetic-value-change,CHECK-implicit-integer-arithmetic-value-change-RECOVER // RUN: %clang -fsanitize=implicit-integer-arithmetic-value-change -fsanitize-recover=implicit-integer-arithmetic-value-change %s -### 2>&1 | FileCheck %s --check-prefixes=CHECK-implicit-integer-arithmetic-value-change,CHECK-implicit-integer-arithmetic-value-change-RECOVER diff --git a/compiler-rt/lib/ubsan/ubsan_handlers.cpp b/compiler-rt/lib/ubsan/ubsan_handlers.cpp index 0f16507d5d88..27d01653f088 100644 --- a/compiler-rt/lib/ubsan/ubsan_handlers.cpp +++ b/compiler-rt/lib/ubsan/ubsan_handlers.cpp @@ -555,13 +555,11 @@ static void handleImplicitConversion(ImplicitConversionData *Data, ReportOptions Opts, ValueHandle Src, ValueHandle Dst) { SourceLocation Loc = Data->Loc.acquire(); - ErrorType ET = ErrorType::GenericUB; - const TypeDescriptor &SrcTy = Data->FromType; const TypeDescriptor &DstTy = Data->ToType; - bool SrcSigned = SrcTy.isSignedIntegerTy(); bool DstSigned = DstTy.isSignedIntegerTy(); + ErrorType ET = ErrorType::GenericUB; switch (Data->Kind) { case ICCK_IntegerTruncation: { // Legacy, no longer used. @@ -594,14 +592,23 @@ static void handleImplicitConversion(ImplicitConversionData *Data, ScopedReport R(Opts, Loc, ET); + // In the case we have a bitfield, we want to explicitly say so in the + // error message. // FIXME: is it possible to dump the values as hex with fixed width? - - Diag(Loc, DL_Error, ET, - "implicit conversion from type %0 of value %1 (%2-bit, %3signed) to " - "type %4 changed the value to %5 (%6-bit, %7signed)") - << SrcTy << Value(SrcTy, Src) << SrcTy.getIntegerBitWidth() - << (SrcSigned ? "" : "un") << DstTy << Value(DstTy, Dst) - << DstTy.getIntegerBitWidth() << (DstSigned ? "" : "un"); + if (Data->BitfieldBits) + Diag(Loc, DL_Error, ET, + "implicit conversion from type %0 of value %1 (%2-bit, %3signed) to " + "type %4 changed the value to %5 (%6-bit bitfield, %7signed)") + << SrcTy << Value(SrcTy, Src) << SrcTy.getIntegerBitWidth() + << (SrcSigned ? "" : "un") << DstTy << Value(DstTy, Dst) + << Data->BitfieldBits << (DstSigned ? "" : "un"); + else + Diag(Loc, DL_Error, ET, + "implicit conversion from type %0 of value %1 (%2-bit, %3signed) to " + "type %4 changed the value to %5 (%6-bit, %7signed)") + << SrcTy << Value(SrcTy, Src) << SrcTy.getIntegerBitWidth() + << (SrcSigned ? "" : "un") << DstTy << Value(DstTy, Dst) + << DstTy.getIntegerBitWidth() << (DstSigned ? "" : "un"); } void __ubsan::__ubsan_handle_implicit_conversion(ImplicitConversionData *Data, diff --git a/compiler-rt/lib/ubsan/ubsan_handlers.h b/compiler-rt/lib/ubsan/ubsan_handlers.h index 3bd5046de3d7..bae661a56833 100644 --- a/compiler-rt/lib/ubsan/ubsan_handlers.h +++ b/compiler-rt/lib/ubsan/ubsan_handlers.h @@ -147,6 +147,7 @@ struct ImplicitConversionData { const TypeDescriptor &FromType; const TypeDescriptor &ToType; /* ImplicitConversionCheckKind */ unsigned char Kind; + unsigned int BitfieldBits; }; /// \brief Implict conversion that changed the value. diff --git a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c new file mode 100644 index 000000000000..a0c5ba55c43d --- /dev/null +++ b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c @@ -0,0 +1,649 @@ +// RUN: %clang -x c -fsanitize=implicit-bitfield-conversion -O0 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clang -x c -fsanitize=implicit-bitfield-conversion -O1 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clang -x c -fsanitize=implicit-bitfield-conversion -O2 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clang -x c -fsanitize=implicit-bitfield-conversion -O3 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clang -x c -fsanitize=implicit-conversion -O0 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK + +// RUN: %clangxx -x c++ -fsanitize=implicit-bitfield-conversion -O0 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clangxx -x c++ -fsanitize=implicit-bitfield-conversion -O1 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clangxx -x c++ -fsanitize=implicit-bitfield-conversion -O2 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clangxx -x c++ -fsanitize=implicit-bitfield-conversion -O3 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK +// RUN: %clangxx -x c++ -fsanitize=implicit-conversion -O0 %s -o %t && %run %t 2>&1 | FileCheck %s --check-prefixes=CHECK + +#include +#include + +#define UINT4_MIN 0 +#define UINT4_MAX (1 << 4) - 1 +#define UINT5_MIN 0 +#define UINT5_MAX (1 << 5) - 1 +#define INT7_MIN -(1 << 6) +#define INT7_MAX (1 << 6) - 1 + +typedef struct _X { + uint8_t a : 4; + uint32_t b : 5; + int8_t c : 7; + int32_t d : 16; + uint8_t e : 8; + uint16_t f : 16; + uint32_t g : 32; + int8_t h : 8; + int16_t i : 16; + int32_t j : 32; + uint32_t k : 1; + int32_t l : 1; + _Bool m : 1; +} X; + +void test_a() { + X x; + uint32_t min = UINT4_MIN; + uint32_t max = UINT4_MAX; + + uint8_t v8 = max + 1; + uint16_t v16 = (UINT8_MAX + 1) + (max + 1); + uint32_t v32 = (UINT8_MAX + 1) + (max + 1); + + // Assignment + x.a = v8; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 16 (8-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) + x.a = v16; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint16_t' (aka 'unsigned short') of value 272 (16-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) + x.a = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 272 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) + + // PrePostIncDec + x.a = min; + x.a--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -1 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 15 (4-bit bitfield, unsigned) + x.a = min; + --x.a; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -1 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 15 (4-bit bitfield, unsigned) + + x.a = max; + x.a++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 16 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) + x.a = max; + ++x.a; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 16 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) + + x.a = min + 1; + x.a++; + x.a = min + 1; + ++x.a; + + x.a = min + 1; + x.a--; + x.a = min + 1; + --x.a; + + x.a = max - 1; + x.a++; + x.a = max - 1; + ++x.a; + + x.a = max - 1; + x.a--; + x.a = max - 1; + --x.a; + + // Compound assignment + x.a = 0; + x.a += max; + x.a = 0; + x.a += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 16 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) + + x.a = max; + x.a -= max; + x.a = max; + x.a -= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 15 (4-bit bitfield, unsigned) + + x.a = 1; + x.a *= max; + x.a = 1; + x.a *= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 16 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (4-bit bitfield, unsigned) +} + +void test_b() { + X x; + uint32_t min = UINT5_MIN; + uint32_t max = UINT5_MAX; + + uint8_t v8 = max + 1; + uint16_t v16 = max + 1; + uint32_t v32 = max + 1; + + // Assignment + x.b = v8; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 32 (8-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) + x.b = v16; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint16_t' (aka 'unsigned short') of value 32 (16-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) + x.b = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 32 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) + + // PrePostIncDec + x.b = min; + x.b--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 31 (5-bit bitfield, unsigned) + x.b = min; + --x.b; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 31 (5-bit bitfield, unsigned) + + x.b = max; + x.b++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 32 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) + x.b = max; + ++x.b; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 32 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) + + x.b = min + 1; + x.b++; + x.b = min + 1; + ++x.b; + + x.b = min + 1; + x.b--; + x.b = min + 1; + --x.b; + + x.b = max - 1; + x.b++; + x.b = max - 1; + ++x.b; + + x.b = max - 1; + x.b--; + x.b = max - 1; + --x.b; + + // Compound assignment + x.b = 0; + x.b += max; + x.b = 0; + x.b += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 32 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) + + x.b = max; + x.b -= max; + x.b = max; + x.b -= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 31 (5-bit bitfield, unsigned) + + x.b = 1; + x.b *= max; + x.b = 1; + x.b *= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 32 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (5-bit bitfield, unsigned) +} + +void test_c() { + X x; + int32_t min = INT7_MIN; + int32_t max = INT7_MAX; + + uint8_t v8 = max + 1; + uint16_t v16 = (UINT8_MAX + 1) + (max + 1); + uint32_t v32 = (UINT8_MAX + 1) + (max + 1); + + // Assignment + x.c = v8; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 64 (8-bit, unsigned) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + x.c = v16; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint16_t' (aka 'unsigned short') of value 320 (16-bit, unsigned) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + x.c = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 320 (32-bit, unsigned) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + + // PrePostIncDec + x.c = min; + x.c--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 63 (7-bit bitfield, signed) + x.c = min; + --x.c; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 63 (7-bit bitfield, signed) + + x.c = max; + x.c++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + x.c = max; + ++x.c; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + + x.c = min + 1; + x.c++; + x.c = min + 1; + ++x.c; + + x.c = min + 1; + x.c--; + x.c = min + 1; + --x.c; + + x.c = max - 1; + x.c++; + x.c = max - 1; + ++x.c; + + x.c = max - 1; + x.c--; + x.c = max - 1; + --x.c; + + // Compound assignment + x.c = 0; + x.c += max; + x.c = 0; + x.c += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + + x.c = 0; + x.c -= (-min); + x.c = 0; + x.c -= (-min + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 63 (7-bit bitfield, signed) + + x.c = 1; + x.c *= max; + x.c = 1; + x.c *= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) +} + +void test_d() { + X x; + int32_t min = INT16_MIN; + int32_t max = INT16_MAX; + + uint32_t v32 = max + 1; + + // Assignment + x.d = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 32768 (32-bit, unsigned) to type 'int32_t' (aka 'int') changed the value to -32768 (16-bit bitfield, signed) + + // PrePostIncDec + x.d = min; + x.d--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value -32769 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to 32767 (16-bit bitfield, signed) + x.d = min; + --x.d; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value -32769 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to 32767 (16-bit bitfield, signed) + + x.d = max; + x.d++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 32768 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to -32768 (16-bit bitfield, signed) + x.d = max; + ++x.d; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 32768 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to -32768 (16-bit bitfield, signed) + + x.d = min + 1; + x.d++; + x.d = min + 1; + ++x.d; + + x.d = min + 1; + x.d--; + x.d = min + 1; + --x.d; + + x.d = max - 1; + x.d++; + x.d = max - 1; + ++x.d; + + x.d = max - 1; + x.d--; + x.d = max - 1; + --x.d; + + // Compound assignment + x.d = 0; + x.d += max; + x.d = 0; + x.d += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 32768 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to -32768 (16-bit bitfield, signed) + + x.d = 0; + x.d -= (-min); + x.d = 0; + x.d -= (-min + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -32769 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to 32767 (16-bit bitfield, signed) + + x.d = 1; + x.d *= max; + x.d = 1; + x.d *= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 32768 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to -32768 (16-bit bitfield, signed) +} + +void test_e() { + X x; + uint32_t min = 0; + uint32_t max = UINT8_MAX; + + uint16_t v16 = max + 1; + uint32_t v32 = max + 1; + + // Assignment + x.e = v16; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint16_t' (aka 'unsigned short') of value 256 (16-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (8-bit bitfield, unsigned) + x.e = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 256 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (8-bit bitfield, unsigned) + + // PrePostIncDec + x.e = min; + x.e--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -1 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 255 (8-bit bitfield, unsigned) + x.e = min; + --x.e; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -1 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 255 (8-bit bitfield, unsigned) + x.e = min + 1; + x.e--; + + x.e = max; + x.e++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 256 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (8-bit bitfield, unsigned) + x.e = max; + ++x.e; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 256 (32-bit, signed) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (8-bit bitfield, unsigned) + x.e = max - 1; + x.e++; + + // Compound assignment + x.e = 0; + x.e += max; + x.e = 0; + x.e += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 256 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 0 (8-bit bitfield, unsigned) + + x.e = max; + x.e -= max; + x.e = max; + x.e -= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint8_t' (aka 'unsigned char') changed the value to 255 (8-bit bitfield, unsigned) +} + +void test_f() { + X x; + uint32_t min = 0; + uint32_t max = UINT16_MAX; + + uint32_t v32 = max + 1; + + // Assignment + x.f = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 65536 (32-bit, unsigned) to type 'uint16_t' (aka 'unsigned short') changed the value to 0 (16-bit bitfield, unsigned) + + // PrePostIncDec + x.f = min; + x.f--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -1 (32-bit, signed) to type 'uint16_t' (aka 'unsigned short') changed the value to 65535 (16-bit bitfield, unsigned) + x.f = min; + --x.f; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -1 (32-bit, signed) to type 'uint16_t' (aka 'unsigned short') changed the value to 65535 (16-bit bitfield, unsigned) + x.f = min + 1; + x.f--; + + x.f = max; + x.f++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 65536 (32-bit, signed) to type 'uint16_t' (aka 'unsigned short') changed the value to 0 (16-bit bitfield, unsigned) + x.f = max; + ++x.f; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 65536 (32-bit, signed) to type 'uint16_t' (aka 'unsigned short') changed the value to 0 (16-bit bitfield, unsigned) + x.f = max - 1; + x.f++; + + // Compound assignment + x.f = 0; + x.f += max; + x.f = 0; + x.f += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 65536 (32-bit, unsigned) to type 'uint16_t' (aka 'unsigned short') changed the value to 0 (16-bit bitfield, unsigned) + + x.f = max; + x.f -= max; + x.f = max; + x.f -= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint16_t' (aka 'unsigned short') changed the value to 65535 (16-bit bitfield, unsigned) +} + +void test_g() { + X x; + uint64_t min = 0; + uint64_t max = UINT32_MAX; + + uint64_t v64 = max + 1; + + // Assignment + x.g = v64; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned {{long|long long}}') of value 4294967296 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (32-bit bitfield, unsigned) + + // PrePostIncDec + x.g = min; + x.g--; + x.g = min; + --x.g; + x.g = min + 1; + x.g--; + + x.g = max; + x.g++; + x.g = max; + ++x.g; + x.g = max - 1; + x.g++; + + // Compound assignment + x.g = 0; + x.g += max; + x.g = 0; + x.g += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned {{long|long long}}') of value 4294967296 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (32-bit bitfield, unsigned) + + x.g = max; + x.g -= max; + x.g = max; + x.g -= (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned {{long|long long}}') of value 18446744073709551615 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 4294967295 (32-bit bitfield, unsigned) +} + +void test_h() { + X x; + int32_t min = INT8_MIN; + int32_t max = INT8_MAX; + + int16_t v16 = max + 1; + int32_t v32 = max + 1; + + // Assignment + x.h = v16; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int16_t' (aka 'short') of value 128 (16-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + x.h = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + + // PrePostIncDec + x.h = min; + x.h--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 127 (8-bit bitfield, signed) + x.h = min; + --x.h; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 127 (8-bit bitfield, signed) + x.h = min + 1; + x.h--; + + x.h = max; + x.h++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + x.h = max; + ++x.h; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + x.h = max - 1; + x.h++; + + // Compound assignment + x.h = 0; + x.h += max; + x.h = 0; + x.h += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + + x.h = 0; + x.h -= (-min); + x.h = 0; + x.h -= (-min + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 127 (8-bit bitfield, signed) +} + +void test_i() { + X x; + int32_t min = INT16_MIN; + int32_t max = INT16_MAX; + + int32_t v32 = max + 1; + + // Assignment + x.i = v32; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 32768 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to -32768 (16-bit bitfield, signed) + + // PrePostIncDec + x.i = min; + x.i--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -32769 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to 32767 (16-bit bitfield, signed) + x.i = min; + --x.i; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -32769 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to 32767 (16-bit bitfield, signed) + x.i = min + 1; + x.i--; + + x.i = max; + x.i++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 32768 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to -32768 (16-bit bitfield, signed) + x.i = max; + ++x.i; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 32768 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to -32768 (16-bit bitfield, signed) + x.i = max - 1; + x.i++; + + // Compound assignment + x.i = 0; + x.i += max; + x.i = 0; + x.i += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 32768 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to -32768 (16-bit bitfield, signed) + + x.i = 0; + x.i -= (-min); + x.i = 0; + x.i -= (-min + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -32769 (32-bit, signed) to type 'int16_t' (aka 'short') changed the value to 32767 (16-bit bitfield, signed) +} + +void test_j() { + X x; + int64_t min = INT32_MIN; + int64_t max = INT32_MAX; + + int64_t v64 = max + 1; + + // Assignment + x.j = v64; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka '{{long|long long}}') of value 2147483648 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to -2147483648 (32-bit bitfield, signed) + + // PrePostIncDec + x.j = min; + x.j--; + x.j = min; + --x.j; + x.j = min + 1; + x.j--; + + x.j = max; + x.j++; + x.j = max; + ++x.j; + x.j = max - 1; + x.j++; + + // Compound assignment + x.j = 0; + x.j += max; + x.j = 0; + x.j += (max + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka '{{long|long long}}') of value 2147483648 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to -2147483648 (32-bit bitfield, signed) + + x.j = 0; + x.j -= (-min); + x.j = 0; + x.j -= (-min + 1); + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka '{{long|long long}}') of value -2147483649 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to 2147483647 (32-bit bitfield, signed) +} + +void test_k_l() { + X x; + int32_t one = 1; + int32_t neg_one = -1; + + // k + uint8_t v8 = 2; + x.k = v8; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 2 (8-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (1-bit bitfield, unsigned) + x.k = one; + x.k = neg_one; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value -1 (32-bit, signed) to type 'uint32_t' (aka 'unsigned int') changed the value to 1 (1-bit bitfield, unsigned) + + x.k = 0; + x.k--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 4294967295 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 1 (1-bit bitfield, unsigned) + x.k = 1; + x.k--; + + x.k = 1; + x.k++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 2 (32-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (1-bit bitfield, unsigned) + x.k = 0; + x.k++; + + // l + x.l = v8; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 2 (8-bit, unsigned) to type 'int32_t' (aka 'int') changed the value to 0 (1-bit bitfield, signed) + x.l = one; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 1 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to -1 (1-bit bitfield, signed) + x.l = neg_one; + + x.l = 0; + x.l--; + x.l = -1; + x.l--; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value -2 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to 0 (1-bit bitfield, signed) + + x.l = 0; + x.l++; + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 1 (32-bit, signed) to type 'int32_t' (aka 'int') changed the value to -1 (1-bit bitfield, signed) + x.l = -1; + x.l++; +} + +void test_m() { + X x; + + uint8_t v8 = 2; + x.m = v8; +} + +int main() { + test_a(); + test_b(); + test_c(); + test_d(); + test_e(); + test_f(); + test_g(); + test_h(); + test_i(); + test_j(); + test_k_l(); + test_m(); + return 0; +} -- GitLab From aa6a089c367e024921bae050b8999a7bc4d58f76 Mon Sep 17 00:00:00 2001 From: Mike Rice Date: Mon, 8 Apr 2024 12:53:30 -0700 Subject: [PATCH 184/695] [NFC][OpenMP] Split nesting_of_regions test (#87842) This test is the bottleneck for OpenMP lit tests, running about twice as long as the others. Break it into five tests based on run lines with the same version. --- .../test/OpenMP/{ => Inputs}/nesting_of_regions.cpp | 13 ------------- clang/test/OpenMP/nesting_of_regions_45.cpp | 4 ++++ clang/test/OpenMP/nesting_of_regions_50.cpp | 4 ++++ clang/test/OpenMP/nesting_of_regions_51.cpp | 4 ++++ clang/test/OpenMP/nesting_of_regions_simd_45.cpp | 3 +++ clang/test/OpenMP/nesting_of_regions_simd_50.cpp | 3 +++ 6 files changed, 18 insertions(+), 13 deletions(-) rename clang/test/OpenMP/{ => Inputs}/nesting_of_regions.cpp (99%) create mode 100644 clang/test/OpenMP/nesting_of_regions_45.cpp create mode 100644 clang/test/OpenMP/nesting_of_regions_50.cpp create mode 100644 clang/test/OpenMP/nesting_of_regions_51.cpp create mode 100644 clang/test/OpenMP/nesting_of_regions_simd_45.cpp create mode 100644 clang/test/OpenMP/nesting_of_regions_simd_50.cpp diff --git a/clang/test/OpenMP/nesting_of_regions.cpp b/clang/test/OpenMP/Inputs/nesting_of_regions.cpp similarity index 99% rename from clang/test/OpenMP/nesting_of_regions.cpp rename to clang/test/OpenMP/Inputs/nesting_of_regions.cpp index 9442fb20647d..e671f9b0cf41 100644 --- a/clang/test/OpenMP/nesting_of_regions.cpp +++ b/clang/test/OpenMP/Inputs/nesting_of_regions.cpp @@ -1,15 +1,3 @@ -// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=45 -fno-openmp-extensions -verify=expected,omp45,omp45warn,omp %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp -fno-openmp-extensions -verify=expected,omp50,omp %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-extensions -verify=expected,omp50 %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=45 -verify=expected,omp45,omp -fno-openmp-extensions -Wno-openmp %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=45 -verify=expected,omp45,omp -fno-openmp-extensions -Wno-source-uses-openmp %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=51 -verify=expected,omp51,omp -fno-openmp-extensions -Wno-source-uses-openmp %s - -// RUN: %clang_cc1 -fsyntax-only -fopenmp-simd -fopenmp-version=45 -fno-openmp-extensions -verify=expected,omp45,omp45warn,omp %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp-simd -verify=expected,omp50,omp -fno-openmp-extensions %s -// RUN: %clang_cc1 -fsyntax-only -fopenmp-simd -fopenmp-version=51 -verify=expected,omp51,omp -fno-openmp-extensions %s -// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} - void bar(); template @@ -19577,4 +19565,3 @@ void foo() { return foo(); } - diff --git a/clang/test/OpenMP/nesting_of_regions_45.cpp b/clang/test/OpenMP/nesting_of_regions_45.cpp new file mode 100644 index 000000000000..d5870ec36486 --- /dev/null +++ b/clang/test/OpenMP/nesting_of_regions_45.cpp @@ -0,0 +1,4 @@ +// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=45 -fno-openmp-extensions -verify=expected,omp45,omp45warn,omp %s +// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=45 -verify=expected,omp45,omp -fno-openmp-extensions -Wno-openmp %s + +#include "Inputs/nesting_of_regions.cpp" diff --git a/clang/test/OpenMP/nesting_of_regions_50.cpp b/clang/test/OpenMP/nesting_of_regions_50.cpp new file mode 100644 index 000000000000..f2061553a804 --- /dev/null +++ b/clang/test/OpenMP/nesting_of_regions_50.cpp @@ -0,0 +1,4 @@ +// RUN: %clang_cc1 -fsyntax-only -fopenmp -fno-openmp-extensions -verify=expected,omp50,omp %s +// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-extensions -verify=expected,omp50 %s + +#include "Inputs/nesting_of_regions.cpp" diff --git a/clang/test/OpenMP/nesting_of_regions_51.cpp b/clang/test/OpenMP/nesting_of_regions_51.cpp new file mode 100644 index 000000000000..856489b04282 --- /dev/null +++ b/clang/test/OpenMP/nesting_of_regions_51.cpp @@ -0,0 +1,4 @@ +// RUN: %clang_cc1 -fsyntax-only -fopenmp-simd -fopenmp-version=51 -verify=expected,omp51,omp -fno-openmp-extensions %s +// RUN: %clang_cc1 -fsyntax-only -fopenmp -fopenmp-version=51 -verify=expected,omp51,omp -fno-openmp-extensions -Wno-source-uses-openmp %s + +#include "Inputs/nesting_of_regions.cpp" diff --git a/clang/test/OpenMP/nesting_of_regions_simd_45.cpp b/clang/test/OpenMP/nesting_of_regions_simd_45.cpp new file mode 100644 index 000000000000..fb0d8bbfe3e4 --- /dev/null +++ b/clang/test/OpenMP/nesting_of_regions_simd_45.cpp @@ -0,0 +1,3 @@ +// RUN: %clang_cc1 -fsyntax-only -fopenmp-simd -fopenmp-version=45 -fno-openmp-extensions -verify=expected,omp45,omp45warn,omp %s + +#include "Inputs/nesting_of_regions.cpp" diff --git a/clang/test/OpenMP/nesting_of_regions_simd_50.cpp b/clang/test/OpenMP/nesting_of_regions_simd_50.cpp new file mode 100644 index 000000000000..ba87ba38e74a --- /dev/null +++ b/clang/test/OpenMP/nesting_of_regions_simd_50.cpp @@ -0,0 +1,3 @@ +// RUN: %clang_cc1 -fsyntax-only -fopenmp-simd -verify=expected,omp50,omp -fno-openmp-extensions %s + +#include "Inputs/nesting_of_regions.cpp" -- GitLab From 01d9528ef989610e968386ea1f270698015d2410 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 8 Apr 2024 15:54:30 -0400 Subject: [PATCH 185/695] [SLP]Improve final minbitwidth analysis attempt. Added part for demanded bits analysis in the IsPotentiallyTruncated to improve minbitwidth analysis final attempts. Metric: size..text Program size..text results results0 diff test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 43069.00 42973.00 -0.2% test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 43066.00 42970.00 -0.2% Extra trunc instructions are emitted to operate with <32 x i8> instead of <32 x i16>, will be removed in the next patches. Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/87786 --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 5 +++++ .../SLPVectorizer/AArch64/extractelements-to-shuffle.ll | 5 +++-- .../SLPVectorizer/RISCV/trunc-to-large-than-bw.ll | 9 +++++---- .../SLPVectorizer/X86/int-bitcast-minbitwidth.ll | 7 ++++--- 4 files changed, 17 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index b48317588ac5..e2be6e0fa366 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -14160,6 +14160,11 @@ bool BoUpSLP::collectValuesToDemote( unsigned BitWidth1 = OrigBitWidth - NumSignBits; if (!isKnownNonNegative(V, SimplifyQuery(*DL))) ++BitWidth1; + if (auto *I = dyn_cast(V)) { + APInt Mask = DB->getDemandedBits(I); + unsigned BitWidth2 = Mask.getBitWidth() - Mask.countl_zero(); + BitWidth1 = std::min(BitWidth1, BitWidth2); + } BitWidth = std::max(BitWidth, BitWidth1); return BitWidth > 0 && OrigBitWidth >= (BitWidth * 2); }; diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll index 44542f32bf14..d2711d0546c0 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll @@ -81,8 +81,9 @@ define void @dist_vec(ptr nocapture noundef readonly %pA, ptr nocapture noundef ; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[TMP4FT_0_LCSSA]], <2 x i64> [[TMP4TF_0_LCSSA]], <2 x i32> ; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[TMP4FF_0_LCSSA]], <2 x i64> [[TMP4TT_0_LCSSA]], <2 x i32> ; CHECK-NEXT: [[TMP15:%.*]] = shufflevector <2 x i64> [[TMP13]], <2 x i64> [[TMP14]], <4 x i32> -; CHECK-NEXT: [[TMP16:%.*]] = add <4 x i64> [[TMP12]], [[TMP15]] -; CHECK-NEXT: [[TMP17:%.*]] = trunc <4 x i64> [[TMP16]] to <4 x i32> +; CHECK-NEXT: [[TMP16:%.*]] = trunc <4 x i64> [[TMP12]] to <4 x i32> +; CHECK-NEXT: [[TMP57:%.*]] = trunc <4 x i64> [[TMP15]] to <4 x i32> +; CHECK-NEXT: [[TMP17:%.*]] = add <4 x i32> [[TMP16]], [[TMP57]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[NUMBEROFBOOLS]], 127 ; CHECK-NEXT: [[CMP86284:%.*]] = icmp ugt i32 [[AND]], 31 ; CHECK-NEXT: br i1 [[CMP86284]], label [[WHILE_BODY88:%.*]], label [[WHILE_END122:%.*]] diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-to-large-than-bw.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-to-large-than-bw.ll index 2d69c7c984dc..04d275742832 100644 --- a/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-to-large-than-bw.ll +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-to-large-than-bw.ll @@ -8,10 +8,11 @@ define i32 @test() { ; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i64(ptr align 8 @c, i64 24, <4 x i1> , i32 4) -; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[TMP0]] to <4 x i32> -; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i32> [[TMP2]], -; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP3]]) +; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[TMP0]] to <4 x i16> +; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i16> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i16> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[TMP4]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP5]], i32 1) ; CHECK-NEXT: ret i32 [[TMP6]] ; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll index f4a471493f1b..55da3e5f9f37 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/int-bitcast-minbitwidth.ll @@ -7,9 +7,10 @@ define void @t(i64 %v) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> poison, i64 [[V]], i32 0 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i64> [[TMP0]], <4 x i64> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i32> -; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i32> [[TMP2]], -; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP3]]) +; CHECK-NEXT: [[TMP2:%.*]] = trunc <4 x i64> [[TMP1]] to <4 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = mul <4 x i16> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = sext i16 [[TMP4]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP5]], 65535 ; CHECK-NEXT: store i32 [[TMP6]], ptr null, align 4 ; CHECK-NEXT: ret void -- GitLab From c23135c5488fbfaf6439433a10b3ddef33ff112c Mon Sep 17 00:00:00 2001 From: Leonard Grey Date: Mon, 8 Apr 2024 16:05:52 -0400 Subject: [PATCH 186/695] -fsanitize=function: fix .subsections_via_symbols (#87527) -fsanitize=function emits a signature and function hash before a function. Similar to 7f6e2c9, these can be sheared off when `.subsections_via_symbols` is used. This change uses the same technique 7f6e2c9 introduced for prefixes: emitting a symbol for the metadata, then marking the actual function entry as an .alt_entry symbol. --- llvm/include/llvm/CodeGen/AsmPrinter.h | 3 ++ llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 43 ++++++++++++--------- llvm/test/CodeGen/AArch64/func-sanitizer.ll | 9 +++++ llvm/test/CodeGen/X86/func-sanitizer.ll | 10 +++++ 4 files changed, 46 insertions(+), 19 deletions(-) diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index a7fbf4aeb744..81c3e4be95e9 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -868,6 +868,9 @@ private: /// This method emits a comment next to header for the current function. virtual void emitFunctionHeaderComment(); + /// This method emits prefix-like data before the current function. + void emitFunctionPrefix(ArrayRef Prefix); + /// Emit a blob of inline asm to the output streamer. void emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI, diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 293bb5a3c6f6..721d144d7f4c 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -927,6 +927,27 @@ void AsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const { void AsmPrinter::emitFunctionHeaderComment() {} +void AsmPrinter::emitFunctionPrefix(ArrayRef Prefix) { + const Function &F = MF->getFunction(); + if (!MAI->hasSubsectionsViaSymbols()) { + for (auto &C : Prefix) + emitGlobalConstant(F.getParent()->getDataLayout(), C); + return; + } + // Preserving prefix-like data on platforms which use subsections-via-symbols + // is a bit tricky. Here we introduce a symbol for the prefix-like data + // and use the .alt_entry attribute to mark the function's real entry point + // as an alternative entry point to the symbol that precedes the function.. + OutStreamer->emitLabel(OutContext.createLinkerPrivateTempSymbol()); + + for (auto &C : Prefix) { + emitGlobalConstant(F.getParent()->getDataLayout(), C); + } + + // Emit an .alt_entry directive for the actual function symbol. + OutStreamer->emitSymbolAttribute(CurrentFnSym, MCSA_AltEntry); +} + /// EmitFunctionHeader - This method emits the header for the current /// function. void AsmPrinter::emitFunctionHeader() { @@ -966,23 +987,8 @@ void AsmPrinter::emitFunctionHeader() { OutStreamer->emitSymbolAttribute(CurrentFnSym, MCSA_Cold); // Emit the prefix data. - if (F.hasPrefixData()) { - if (MAI->hasSubsectionsViaSymbols()) { - // Preserving prefix data on platforms which use subsections-via-symbols - // is a bit tricky. Here we introduce a symbol for the prefix data - // and use the .alt_entry attribute to mark the function's real entry point - // as an alternative entry point to the prefix-data symbol. - MCSymbol *PrefixSym = OutContext.createLinkerPrivateTempSymbol(); - OutStreamer->emitLabel(PrefixSym); - - emitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData()); - - // Emit an .alt_entry directive for the actual function symbol. - OutStreamer->emitSymbolAttribute(CurrentFnSym, MCSA_AltEntry); - } else { - emitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData()); - } - } + if (F.hasPrefixData()) + emitFunctionPrefix({F.getPrefixData()}); // Emit KCFI type information before patchable-function-prefix nops. emitKCFITypeId(*MF); @@ -1014,8 +1020,7 @@ void AsmPrinter::emitFunctionHeader() { auto *PrologueSig = mdconst::extract(MD->getOperand(0)); auto *TypeHash = mdconst::extract(MD->getOperand(1)); - emitGlobalConstant(F.getParent()->getDataLayout(), PrologueSig); - emitGlobalConstant(F.getParent()->getDataLayout(), TypeHash); + emitFunctionPrefix({PrologueSig, TypeHash}); } if (isVerbose()) { diff --git a/llvm/test/CodeGen/AArch64/func-sanitizer.ll b/llvm/test/CodeGen/AArch64/func-sanitizer.ll index 89f23e7ed80e..de83d70a5784 100644 --- a/llvm/test/CodeGen/AArch64/func-sanitizer.ll +++ b/llvm/test/CodeGen/AArch64/func-sanitizer.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=MACHO ; CHECK-LABEL: .type _Z3funv,@function ; CHECK-NEXT: .word 3238382334 // 0xc105cafe @@ -7,6 +8,14 @@ ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: ret +; MACHO: ltmp0: +; MACHO-NEXT: .long 3238382334 ; 0xc105cafe +; MACHO-NEXT: .long 42 ; 0x2a +; MACHO-NEXT: .alt_entry __Z3funv +; MACHO-NEXT: __Z3funv: +; MACHO-NEXT: ; %bb.0: +; MACHO-NEXT: ret + define dso_local void @_Z3funv() nounwind !func_sanitize !0 { ret void } diff --git a/llvm/test/CodeGen/X86/func-sanitizer.ll b/llvm/test/CodeGen/X86/func-sanitizer.ll index b421cb53ddfe..71f062ae2f8c 100644 --- a/llvm/test/CodeGen/X86/func-sanitizer.ll +++ b/llvm/test/CodeGen/X86/func-sanitizer.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=MACHO ; CHECK: .type _Z3funv,@function ; CHECK-NEXT: .long 3238382334 # 0xc105cafe @@ -8,6 +9,15 @@ ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: retq +; MACHO: ltmp0: +; MACHO-NEXT: .long 3238382334 ## 0xc105cafe +; MACHO-NEXT: .long 42 ## 0x2a +; MACHO-NEXT: .alt_entry __Z3funv +; MACHO-NEXT: __Z3funv: +; MACHO-NEXT: .cfi_startproc +; MACHO-NEXT: # %bb.0: +; MACHO-NEXT: retq + define dso_local void @_Z3funv() !func_sanitize !0 { ret void } -- GitLab From 3b43ae9a68256a77e8879a32a1670fd4b327802f Mon Sep 17 00:00:00 2001 From: Christopher Ferris Date: Mon, 8 Apr 2024 13:08:35 -0700 Subject: [PATCH 187/695] [scudo] Remove end of line checks. (#88022) The regex to verify that there is nothing else at the end of the line doesn't work in all cases, so remove it. --- compiler-rt/lib/scudo/standalone/tests/report_test.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/tests/report_test.cpp b/compiler-rt/lib/scudo/standalone/tests/report_test.cpp index 2c790247a2f6..6c46243053d9 100644 --- a/compiler-rt/lib/scudo/standalone/tests/report_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/report_test.cpp @@ -63,18 +63,18 @@ TEST(ScudoReportDeathTest, CSpecific) { TEST(ScudoReportDeathTest, Linux) { errno = ENOMEM; EXPECT_DEATH(scudo::reportMapError(), - "Scudo ERROR:.*internal map failure \\(error desc=.*\\)\\s*$"); + "Scudo ERROR:.*internal map failure \\(error desc=.*\\)"); errno = ENOMEM; EXPECT_DEATH(scudo::reportMapError(1024U), "Scudo ERROR:.*internal map failure \\(error desc=.*\\) " - "requesting 1KB\\s*$"); + "requesting 1KB"); errno = ENOMEM; EXPECT_DEATH(scudo::reportUnmapError(0x1000U, 100U), "Scudo ERROR:.*internal unmap failure \\(error desc=.*\\) Addr " - "0x1000 Size 100\\s*$"); + "0x1000 Size 100"); errno = ENOMEM; EXPECT_DEATH(scudo::reportProtectError(0x1000U, 100U, PROT_READ), "Scudo ERROR:.*internal protect failure \\(error desc=.*\\) " - "Addr 0x1000 Size 100 Prot 1\\s*$"); + "Addr 0x1000 Size 100 Prot 1"); } #endif -- GitLab From e276dcec173bc0123444c162c3becb2354382248 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20Warzy=C5=84ski?= Date: Mon, 8 Apr 2024 21:22:00 +0100 Subject: [PATCH 188/695] [mlir][arith] Refine the verifier for arith.constant (#87999) Disallows initialization of scalable vectors with an attribute of arbitrary values, e.g.: ```mlir %c = arith.constant dense<[0, 1]> : vector<[2] x i32> ``` Initialization using vector splats remains allowed (i.e. when all the init values are identical): ```mlir %c = arith.constant dense<[1, 1]> : vector<[2] x i32> ``` Note: This is a re-upload of #86178 --- mlir/lib/Dialect/Arith/IR/ArithOps.cpp | 9 +++++++++ mlir/test/Dialect/Arith/invalid.mlir | 18 ++++++++++++++++++ mlir/test/Dialect/Vector/linearize.mlir | 11 ----------- 3 files changed, 27 insertions(+), 11 deletions(-) diff --git a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp index 1d68a4f7292b..6f995b93bc3e 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithOps.cpp +++ b/mlir/lib/Dialect/Arith/IR/ArithOps.cpp @@ -213,6 +213,15 @@ LogicalResult arith::ConstantOp::verify() { return emitOpError( "value must be an integer, float, or elements attribute"); } + + // Note, we could relax this for vectors with 1 scalable dim, e.g.: + // * arith.constant dense<[[3, 3], [1, 1]]> : vector<2 x [2] x i32> + // However, this would most likely require updating the lowerings to LLVM. + auto vecType = dyn_cast(type); + if (vecType && vecType.isScalable() && !isa(getValue())) + return emitOpError( + "intializing scalable vectors with elements attribute is not supported" + " unless it's a vector splat"); return success(); } diff --git a/mlir/test/Dialect/Arith/invalid.mlir b/mlir/test/Dialect/Arith/invalid.mlir index 6d8ac0ada52b..ada849220bb8 100644 --- a/mlir/test/Dialect/Arith/invalid.mlir +++ b/mlir/test/Dialect/Arith/invalid.mlir @@ -64,6 +64,24 @@ func.func @constant_out_of_range() { // ----- +func.func @constant_invalid_scalable_1d_vec_initialization() { +^bb0: + // expected-error@+1 {{'arith.constant' op intializing scalable vectors with elements attribute is not supported unless it's a vector splat}} + %c = arith.constant dense<[0, 1]> : vector<[2] x i32> + return +} + +// ----- + +func.func @constant_invalid_scalable_2d_vec_initialization() { +^bb0: + // expected-error@+1 {{'arith.constant' op intializing scalable vectors with elements attribute is not supported unless it's a vector splat}} + %c = arith.constant dense<[[3, 3], [1, 1]]> : vector<2 x [2] x i32> + return +} + +// ----- + func.func @constant_wrong_type() { ^bb: %x = "arith.constant"(){value = 10.} : () -> f32 // expected-error {{'arith.constant' op failed to verify that all of {value, result} have same type}} diff --git a/mlir/test/Dialect/Vector/linearize.mlir b/mlir/test/Dialect/Vector/linearize.mlir index 212541c79565..22be78cd6820 100644 --- a/mlir/test/Dialect/Vector/linearize.mlir +++ b/mlir/test/Dialect/Vector/linearize.mlir @@ -153,14 +153,3 @@ func.func @test_0d_vector() -> vector { // ALL: return %[[CST]] return %0 : vector } - -// ----- - -func.func @test_scalable_no_linearize(%arg0: vector<2x[2]xf32>) -> vector<2x[2]xf32> { - // expected-error@+1 {{failed to legalize operation 'arith.constant' that was explicitly marked illegal}} - %0 = arith.constant dense<[[1., 1.], [3., 3.]]> : vector<2x[2]xf32> - %1 = math.sin %arg0 : vector<2x[2]xf32> - %2 = arith.addf %0, %1 : vector<2x[2]xf32> - - return %2 : vector<2x[2]xf32> -} -- GitLab From 8671429151d5e67d3f21a737809953ae8bdfbfde Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 8 Apr 2024 15:26:54 -0500 Subject: [PATCH 189/695] [Libomp] Place generated OpenMP headers into build resource directory (#88007) Summary: These headers are a part of the compiler's resource directory once installed. However, they are currently placed in the binary directory temporarily. This makes it more difficult to use the compiler out of the build directory and will cause issues when moving to `liboffload`. This patch changes the logic to write these instead to the copmiler's resource directory inside of the build tree. NOTE: This doesn't change the Fortran headers, I don't know enough about those and it won't use the same directory. --- clang/test/Headers/Inputs/include/stdint.h | 8 +++++++ openmp/runtime/src/CMakeLists.txt | 25 ++++++++++++++-------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/clang/test/Headers/Inputs/include/stdint.h b/clang/test/Headers/Inputs/include/stdint.h index 5bf26a7b67b0..67b27b8dfc7b 100644 --- a/clang/test/Headers/Inputs/include/stdint.h +++ b/clang/test/Headers/Inputs/include/stdint.h @@ -16,4 +16,12 @@ typedef unsigned __INTPTR_TYPE__ uintptr_t; #error Every target should have __INTPTR_TYPE__ #endif +#ifdef __INTPTR_MAX__ +#define INTPTR_MAX __INTPTR_MAX__ +#endif + +#ifdef __UINTPTR_MAX__ +#define UINTPTR_MAX __UINTPTR_MAX__ +#endif + #endif /* STDINT_H */ diff --git a/openmp/runtime/src/CMakeLists.txt b/openmp/runtime/src/CMakeLists.txt index f05bcabb4417..000d02c33dc0 100644 --- a/openmp/runtime/src/CMakeLists.txt +++ b/openmp/runtime/src/CMakeLists.txt @@ -10,12 +10,19 @@ include(ExtendPath) +# The generated headers will be placed in clang's resource directory if present. +if(${OPENMP_STANDALONE_BUILD}) + set(LIBOMP_HEADERS_INTDIR ${CMAKE_CURRENT_BINARY_DIR}) +else() + set(LIBOMP_HEADERS_INTDIR ${LLVM_BINARY_DIR}/${LIBOMP_HEADERS_INSTALL_PATH}) +endif() + # Configure omp.h, kmp_config.h and omp-tools.h if necessary -configure_file(${LIBOMP_INC_DIR}/omp.h.var omp.h @ONLY) -configure_file(${LIBOMP_INC_DIR}/ompx.h.var ompx.h @ONLY) -configure_file(kmp_config.h.cmake kmp_config.h @ONLY) +configure_file(${LIBOMP_INC_DIR}/omp.h.var ${LIBOMP_HEADERS_INTDIR}/omp.h @ONLY) +configure_file(${LIBOMP_INC_DIR}/ompx.h.var ${LIBOMP_HEADERS_INTDIR}/ompx.h @ONLY) +configure_file(kmp_config.h.cmake ${LIBOMP_HEADERS_INTDIR}/kmp_config.h @ONLY) if(${LIBOMP_OMPT_SUPPORT}) - configure_file(${LIBOMP_INC_DIR}/omp-tools.h.var omp-tools.h @ONLY) + configure_file(${LIBOMP_INC_DIR}/omp-tools.h.var ${LIBOMP_HEADERS_INTDIR}/omp-tools.h @ONLY) endif() # Generate message catalog files: kmp_i18n_id.inc and kmp_i18n_default.inc @@ -419,15 +426,15 @@ else() endif() install( FILES - ${CMAKE_CURRENT_BINARY_DIR}/omp.h - ${CMAKE_CURRENT_BINARY_DIR}/ompx.h + ${LIBOMP_HEADERS_INTDIR}/omp.h + ${LIBOMP_HEADERS_INTDIR}/ompx.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} ) if(${LIBOMP_OMPT_SUPPORT}) - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) + install(FILES ${LIBOMP_HEADERS_INTDIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) # install under legacy name ompt.h - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} RENAME ompt.h) - set(LIBOMP_OMP_TOOLS_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR} PARENT_SCOPE) + install(FILES ${LIBOMP_HEADERS_INTDIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} RENAME ompt.h) + set(LIBOMP_OMP_TOOLS_INCLUDE_DIR ${LIBOMP_HEADERS_INTDIR} PARENT_SCOPE) endif() if(${BUILD_FORTRAN_MODULES}) set (destination ${LIBOMP_HEADERS_INSTALL_PATH}) -- GitLab From 1e6ce5e284f5c0e8d64eee21af727bb164eb3caf Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Mon, 8 Apr 2024 16:55:50 -0400 Subject: [PATCH 190/695] [libc] Clean up unused math_utils.(h|cpp). (#88036) --- .../__support/FPUtil/generic/CMakeLists.txt | 1 - libc/src/__support/FPUtil/generic/FMod.h | 1 - libc/src/math/generic/CMakeLists.txt | 14 --- libc/src/math/generic/exp_utils.cpp | 1 - libc/src/math/generic/explogxf.h | 1 - libc/src/math/generic/math_utils.cpp | 21 ---- libc/src/math/generic/math_utils.h | 95 ------------------- .../llvm-project-overlay/libc/BUILD.bazel | 16 ---- 8 files changed, 150 deletions(-) delete mode 100644 libc/src/math/generic/math_utils.cpp delete mode 100644 libc/src/math/generic/math_utils.h diff --git a/libc/src/__support/FPUtil/generic/CMakeLists.txt b/libc/src/__support/FPUtil/generic/CMakeLists.txt index 0ae62f40dc61..17b1fffea82e 100644 --- a/libc/src/__support/FPUtil/generic/CMakeLists.txt +++ b/libc/src/__support/FPUtil/generic/CMakeLists.txt @@ -41,5 +41,4 @@ add_header_library( libc.src.__support.FPUtil.fp_bits libc.src.__support.FPUtil.rounding_mode libc.src.__support.macros.optimization - libc.src.math.generic.math_utils ) diff --git a/libc/src/__support/FPUtil/generic/FMod.h b/libc/src/__support/FPUtil/generic/FMod.h index 24fb264b779b..211ab926d28b 100644 --- a/libc/src/__support/FPUtil/generic/FMod.h +++ b/libc/src/__support/FPUtil/generic/FMod.h @@ -15,7 +15,6 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/macros/optimization.h" // LIBC_UNLIKELY -#include "src/math/generic/math_utils.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/src/math/generic/CMakeLists.txt b/libc/src/math/generic/CMakeLists.txt index afbcdea3cf7a..574e000b82a8 100644 --- a/libc/src/math/generic/CMakeLists.txt +++ b/libc/src/math/generic/CMakeLists.txt @@ -95,18 +95,6 @@ add_entrypoint_object( libc.src.__support.FPUtil.nearest_integer_operations ) -add_object_library( - math_utils - SRCS - math_utils.cpp - HDRS - math_utils.h - DEPENDS - libc.hdr.math_macros - libc.include.errno - libc.src.errno.errno -) - add_header_library( range_reduction HDRS @@ -749,8 +737,6 @@ add_object_library( exp_utils.h SRCS exp_utils.cpp - DEPENDS - .math_utils ) add_entrypoint_object( diff --git a/libc/src/math/generic/exp_utils.cpp b/libc/src/math/generic/exp_utils.cpp index afdaea347478..ad13919578ec 100644 --- a/libc/src/math/generic/exp_utils.cpp +++ b/libc/src/math/generic/exp_utils.cpp @@ -7,7 +7,6 @@ //===----------------------------------------------------------------------===// #include "exp_utils.h" -#include "math_utils.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/math/generic/explogxf.h b/libc/src/math/generic/explogxf.h index 8817ba1011a8..f7d04f517ce5 100644 --- a/libc/src/math/generic/explogxf.h +++ b/libc/src/math/generic/explogxf.h @@ -10,7 +10,6 @@ #define LLVM_LIBC_SRC_MATH_GENERIC_EXPLOGXF_H #include "common_constants.h" -#include "math_utils.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/optional.h" #include "src/__support/FPUtil/FEnvImpl.h" diff --git a/libc/src/math/generic/math_utils.cpp b/libc/src/math/generic/math_utils.cpp deleted file mode 100644 index 14bbb2babc60..000000000000 --- a/libc/src/math/generic/math_utils.cpp +++ /dev/null @@ -1,21 +0,0 @@ -//===-- Implementation of math utils --------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "math_utils.h" - -namespace LIBC_NAMESPACE { - -constexpr float XFlowValues::OVERFLOW_VALUE = 0x1p97f; -constexpr float XFlowValues::UNDERFLOW_VALUE = 0x1p-95f; -constexpr float XFlowValues::MAY_UNDERFLOW_VALUE = 0x1.4p-75f; - -constexpr double XFlowValues::OVERFLOW_VALUE = 0x1p769; -constexpr double XFlowValues::UNDERFLOW_VALUE = 0x1p-767; -constexpr double XFlowValues::MAY_UNDERFLOW_VALUE = 0x1.8p-538; - -} // namespace LIBC_NAMESPACE diff --git a/libc/src/math/generic/math_utils.h b/libc/src/math/generic/math_utils.h deleted file mode 100644 index 3ddfeccfd648..000000000000 --- a/libc/src/math/generic/math_utils.h +++ /dev/null @@ -1,95 +0,0 @@ -//===-- Collection of utils for implementing math functions -----*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC_MATH_GENERIC_MATH_UTILS_H -#define LLVM_LIBC_SRC_MATH_GENERIC_MATH_UTILS_H - -#include "hdr/math_macros.h" -#include "src/__support/CPP/bit.h" -#include "src/__support/CPP/type_traits.h" -#include "src/__support/common.h" -#include "src/errno/libc_errno.h" - -#include - -// TODO: evaluate which functions from this file are actually used. - -namespace LIBC_NAMESPACE { - -// TODO: Remove this, or move it to exp_utils.cpp which is its only user. -LIBC_INLINE double as_double(uint64_t x) { return cpp::bit_cast(x); } - -// Values to trigger underflow and overflow. -template struct XFlowValues; - -template <> struct XFlowValues { - static const float OVERFLOW_VALUE; - static const float UNDERFLOW_VALUE; - static const float MAY_UNDERFLOW_VALUE; -}; - -template <> struct XFlowValues { - static const double OVERFLOW_VALUE; - static const double UNDERFLOW_VALUE; - static const double MAY_UNDERFLOW_VALUE; -}; - -template LIBC_INLINE T with_errno(T x, int err) { - if (math_errhandling & MATH_ERRNO) - libc_errno = err; - return x; -} - -template LIBC_INLINE void force_eval(T x) { - volatile T y LIBC_UNUSED = x; -} - -template LIBC_INLINE T opt_barrier(T x) { - volatile T y = x; - return y; -} - -template struct IsFloatOrDouble { - static constexpr bool - Value = // NOLINT so that this Value can match the ones for IsSame - cpp::is_same_v || cpp::is_same_v; -}; - -template -using EnableIfFloatOrDouble = cpp::enable_if_t::Value, int>; - -template = 0> -T xflow(uint32_t sign, T y) { - // Underflow happens when two extremely small values are multiplied. - // Likewise, overflow happens when two large values are multiplied. - y = opt_barrier(sign ? -y : y) * y; - return with_errno(y, ERANGE); -} - -template = 0> T overflow(uint32_t sign) { - return xflow(sign, XFlowValues::OVERFLOW_VALUE); -} - -template = 0> T underflow(uint32_t sign) { - return xflow(sign, XFlowValues::UNDERFLOW_VALUE); -} - -template = 0> -T may_underflow(uint32_t sign) { - return xflow(sign, XFlowValues::MAY_UNDERFLOW_VALUE); -} - -template = 0> -LIBC_INLINE constexpr float invalid(T x) { - T y = (x - x) / (x - x); - return isnan(x) ? y : with_errno(y, EDOM); -} - -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC_MATH_GENERIC_MATH_UTILS_H diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index fd5309e688c3..e8d8320a42e9 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -702,7 +702,6 @@ libc_support_library( ":__support_cpp_type_traits", ":__support_fputil_fenv_impl", ":__support_fputil_fp_bits", - ":math_utils", ], ) @@ -1243,19 +1242,6 @@ libc_function( ################################ math targets ################################ -libc_support_library( - name = "math_utils", - srcs = ["src/math/generic/math_utils.cpp"], - hdrs = ["src/math/generic/math_utils.h"], - deps = [ - "__support_cpp_bit", - "__support_cpp_type_traits", - ":__support_common", - ":errno", - ":hdr_math_macros", - ], -) - libc_support_library( name = "common_constants", srcs = ["src/math/generic/common_constants.cpp"], @@ -1304,7 +1290,6 @@ libc_support_library( ":__support_fputil_nearest_integer", ":__support_fputil_polyeval", ":common_constants", - ":math_utils", ], ) @@ -1712,7 +1697,6 @@ libc_math_function( ":__support_fputil_rounding_mode", ":__support_macros_optimization", ":inv_trigf_utils", - ":math_utils", ], ) -- GitLab From 119b9cdb388f33e78fbb2a73e244ec3031c7f84c Mon Sep 17 00:00:00 2001 From: Peter Klausler <35819229+klausler@users.noreply.github.com> Date: Mon, 8 Apr 2024 14:01:13 -0700 Subject: [PATCH 191/695] [flang][omp] Heed valid build warning (#88015) Address a bug found by a compiler warning, and thereby also fix -Werror builds. --- flang/lib/Lower/OpenMP/ReductionProcessor.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.h b/flang/lib/Lower/OpenMP/ReductionProcessor.h index 7ea252fde360..8b116a4c5204 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.h +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.h @@ -151,9 +151,8 @@ mlir::Value ReductionProcessor::getReductionOperation(fir::FirOpBuilder &builder, mlir::Type type, mlir::Location loc, mlir::Value op1, mlir::Value op2) { - assert(type.isIntOrIndexOrFloat() || - fir::isa_complex(type) && - "only integer, float and complex types are currently supported"); + assert((type.isIntOrIndexOrFloat() || fir::isa_complex(type)) && + "only integer, float and complex types are currently supported"); if (type.isIntOrIndex()) return builder.create(loc, op1, op2); if (fir::isa_real(type)) -- GitLab From ac8ed7f16e5355d7062535afc08ff4be15875c47 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Mon, 8 Apr 2024 17:25:32 -0400 Subject: [PATCH 192/695] [libc] Remove RandUtils.(h|cpp). (#88044) --- libc/test/src/CMakeLists.txt | 2 +- libc/test/src/math/CMakeLists.txt | 12 ++---------- libc/test/src/math/FmaTest.h | 5 ++--- libc/test/src/math/RandUtils.cpp | 19 ------------------- libc/test/src/math/RandUtils.h | 21 --------------------- 5 files changed, 5 insertions(+), 54 deletions(-) delete mode 100644 libc/test/src/math/RandUtils.cpp delete mode 100644 libc/test/src/math/RandUtils.h diff --git a/libc/test/src/CMakeLists.txt b/libc/test/src/CMakeLists.txt index 95f1768c96aa..a5e7a2a4dee7 100644 --- a/libc/test/src/CMakeLists.txt +++ b/libc/test/src/CMakeLists.txt @@ -24,7 +24,7 @@ function(add_fp_unittest name) message(FATAL_ERROR "Hermetic math test cannot require MPFR.") endif() set(test_type UNIT_TEST_ONLY) - list(APPEND MATH_UNITTEST_LINK_LIBRARIES libcMPFRWrapper libc_math_test_utils -lmpfr -lgmp) + list(APPEND MATH_UNITTEST_LINK_LIBRARIES libcMPFRWrapper -lmpfr -lgmp) endif() list(APPEND MATH_UNITTEST_LINK_LIBRARIES LibcFPTestHelpers) diff --git a/libc/test/src/math/CMakeLists.txt b/libc/test/src/math/CMakeLists.txt index 01416eefc15e..274018e59da5 100644 --- a/libc/test/src/math/CMakeLists.txt +++ b/libc/test/src/math/CMakeLists.txt @@ -1,15 +1,5 @@ add_custom_target(libc-math-unittests) -# FIXME: We shouldn't have regular libraries created because we could be -# cross-compiling the tests and running through an emulator. -if(NOT LIBC_TARGET_OS_IS_GPU) - add_library( - libc_math_test_utils - RandUtils.cpp - RandUtils.h - ) -endif() - add_fp_unittest( cosf_test NEED_MPFR @@ -1280,6 +1270,7 @@ add_fp_unittest( fmaf_test.cpp DEPENDS libc.src.math.fmaf + libc.src.stdlib.rand libc.src.__support.FPUtil.fp_bits FLAGS FMA_OPT__ONLY @@ -1294,6 +1285,7 @@ add_fp_unittest( fma_test.cpp DEPENDS libc.src.math.fma + libc.src.stdlib.rand libc.src.__support.FPUtil.fp_bits ) diff --git a/libc/test/src/math/FmaTest.h b/libc/test/src/math/FmaTest.h index 0c93ec858a12..a3b1c9bb8f9b 100644 --- a/libc/test/src/math/FmaTest.h +++ b/libc/test/src/math/FmaTest.h @@ -10,9 +10,9 @@ #define LLVM_LIBC_TEST_SRC_MATH_FMATEST_H #include "src/__support/FPUtil/FPBits.h" +#include "src/stdlib/rand.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include "test/src/math/RandUtils.h" #include "utils/MPFRWrapper/MPFRUtils.h" namespace mpfr = LIBC_NAMESPACE::testing::mpfr; @@ -43,8 +43,7 @@ private: StorageType get_random_bit_pattern() { StorageType bits{0}; for (StorageType i = 0; i < sizeof(StorageType) / 2; ++i) { - bits = (bits << 2) + - static_cast(LIBC_NAMESPACE::testutils::rand()); + bits = (bits << 2) + static_cast(LIBC_NAMESPACE::rand()); } return bits; } diff --git a/libc/test/src/math/RandUtils.cpp b/libc/test/src/math/RandUtils.cpp deleted file mode 100644 index 0d09764f6056..000000000000 --- a/libc/test/src/math/RandUtils.cpp +++ /dev/null @@ -1,19 +0,0 @@ -//===-- RandUtils.cpp -----------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "RandUtils.h" - -#include - -namespace LIBC_NAMESPACE { -namespace testutils { - -int rand() { return std::rand(); } - -} // namespace testutils -} // namespace LIBC_NAMESPACE diff --git a/libc/test/src/math/RandUtils.h b/libc/test/src/math/RandUtils.h deleted file mode 100644 index fecbd8eaabf2..000000000000 --- a/libc/test/src/math/RandUtils.h +++ /dev/null @@ -1,21 +0,0 @@ -//===-- RandUtils.h ---------------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_TEST_SRC_MATH_RANDUTILS_H -#define LLVM_LIBC_TEST_SRC_MATH_RANDUTILS_H - -namespace LIBC_NAMESPACE { -namespace testutils { - -// Wrapper for std::rand. -int rand(); - -} // namespace testutils -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_TEST_SRC_MATH_RANDUTILS_H -- GitLab From 50a6738636d1b1dda0c5887cf0623ee084854272 Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Mon, 8 Apr 2024 17:32:13 -0400 Subject: [PATCH 193/695] [clang][NFC] Adjust TBAA Base Info API (#73263) A couple of cleanups. 1) remove an unnecessary check from isValidBaseType. 2) Add a new internal entrypoint 'getValidBaseTypeInfo', for uses where the type is known to be valid. --- clang/lib/CodeGen/CodeGenTBAA.cpp | 23 +++++++++++++---------- clang/lib/CodeGen/CodeGenTBAA.h | 9 +++++++-- 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/clang/lib/CodeGen/CodeGenTBAA.cpp b/clang/lib/CodeGen/CodeGenTBAA.cpp index 837bf725da38..da689ee6a13d 100644 --- a/clang/lib/CodeGen/CodeGenTBAA.cpp +++ b/clang/lib/CodeGen/CodeGenTBAA.cpp @@ -98,8 +98,6 @@ static bool TypeHasMayAlias(QualType QTy) { /// Check if the given type is a valid base type to be used in access tags. static bool isValidBaseType(QualType QTy) { - if (QTy->isReferenceType()) - return false; if (const RecordType *TTy = QTy->getAs()) { const RecordDecl *RD = TTy->getDecl()->getDefinition(); // Incomplete types are not valid base access types. @@ -243,9 +241,10 @@ llvm::MDNode *CodeGenTBAA::getTypeInfo(QualType QTy) { // aggregate will result into the may-alias access descriptor, meaning all // subsequent accesses to direct and indirect members of that aggregate will // be considered may-alias too. - // TODO: Combine getTypeInfo() and getBaseTypeInfo() into a single function. + // TODO: Combine getTypeInfo() and getValidBaseTypeInfo() into a single + // function. if (isValidBaseType(QTy)) - return getBaseTypeInfo(QTy); + return getValidBaseTypeInfo(QTy); const Type *Ty = Context.getCanonicalType(QTy).getTypePtr(); if (llvm::MDNode *N = MetadataCache[Ty]) @@ -394,7 +393,7 @@ llvm::MDNode *CodeGenTBAA::getBaseTypeInfoHelper(const Type *Ty) { if (BaseRD->isEmpty()) continue; llvm::MDNode *TypeNode = isValidBaseType(BaseQTy) - ? getBaseTypeInfo(BaseQTy) + ? getValidBaseTypeInfo(BaseQTy) : getTypeInfo(BaseQTy); if (!TypeNode) return nullptr; @@ -418,8 +417,9 @@ llvm::MDNode *CodeGenTBAA::getBaseTypeInfoHelper(const Type *Ty) { if (Field->isZeroSize(Context) || Field->isUnnamedBitfield()) continue; QualType FieldQTy = Field->getType(); - llvm::MDNode *TypeNode = isValidBaseType(FieldQTy) ? - getBaseTypeInfo(FieldQTy) : getTypeInfo(FieldQTy); + llvm::MDNode *TypeNode = isValidBaseType(FieldQTy) + ? getValidBaseTypeInfo(FieldQTy) + : getTypeInfo(FieldQTy); if (!TypeNode) return nullptr; @@ -456,9 +456,8 @@ llvm::MDNode *CodeGenTBAA::getBaseTypeInfoHelper(const Type *Ty) { return nullptr; } -llvm::MDNode *CodeGenTBAA::getBaseTypeInfo(QualType QTy) { - if (!isValidBaseType(QTy)) - return nullptr; +llvm::MDNode *CodeGenTBAA::getValidBaseTypeInfo(QualType QTy) { + assert(isValidBaseType(QTy) && "Must be a valid base type"); const Type *Ty = Context.getCanonicalType(QTy).getTypePtr(); @@ -477,6 +476,10 @@ llvm::MDNode *CodeGenTBAA::getBaseTypeInfo(QualType QTy) { return TypeNode; } +llvm::MDNode *CodeGenTBAA::getBaseTypeInfo(QualType QTy) { + return isValidBaseType(QTy) ? getValidBaseTypeInfo(QTy) : nullptr; +} + llvm::MDNode *CodeGenTBAA::getAccessTagInfo(TBAAAccessInfo Info) { assert(!Info.isIncomplete() && "Access to an object of an incomplete type!"); diff --git a/clang/lib/CodeGen/CodeGenTBAA.h b/clang/lib/CodeGen/CodeGenTBAA.h index aa6da2731a41..5d9ecec3ff0f 100644 --- a/clang/lib/CodeGen/CodeGenTBAA.h +++ b/clang/lib/CodeGen/CodeGenTBAA.h @@ -168,6 +168,10 @@ class CodeGenTBAA { /// used to describe accesses to objects of the given base type. llvm::MDNode *getBaseTypeInfoHelper(const Type *Ty); + /// getValidBaseTypeInfo - Return metadata that describes the given base + /// access type. The type must be suitable. + llvm::MDNode *getValidBaseTypeInfo(QualType QTy); + public: CodeGenTBAA(ASTContext &Ctx, CodeGenTypes &CGTypes, llvm::Module &M, const CodeGenOptions &CGO, const LangOptions &Features, @@ -190,8 +194,9 @@ public: /// the given type. llvm::MDNode *getTBAAStructInfo(QualType QTy); - /// getBaseTypeInfo - Get metadata that describes the given base access type. - /// Return null if the type is not suitable for use in TBAA access tags. + /// getBaseTypeInfo - Get metadata that describes the given base access + /// type. Return null if the type is not suitable for use in TBAA access + /// tags. llvm::MDNode *getBaseTypeInfo(QualType QTy); /// getAccessTagInfo - Get TBAA tag for a given memory access. -- GitLab From f5cf98c02655de50401f6547ea181efed6a4c1f1 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Mon, 8 Apr 2024 14:38:47 -0700 Subject: [PATCH 194/695] [RISCV] Improve test coverage for #87950 Noticed in review that we want both the LUI and LUI/ADDI cases with different behavior for each. --- llvm/test/CodeGen/RISCV/prolog-epilogue.ll | 130 +++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/prolog-epilogue.ll b/llvm/test/CodeGen/RISCV/prolog-epilogue.ll index 700481d9e130..1204499deef5 100644 --- a/llvm/test/CodeGen/RISCV/prolog-epilogue.ll +++ b/llvm/test/CodeGen/RISCV/prolog-epilogue.ll @@ -181,6 +181,50 @@ define void @frame_4kb() { ret void } +define void @frame_4kb_offset_128() { +; RV32-LABEL: frame_4kb_offset_128: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 1 +; RV32-NEXT: addi a0, a0, 128 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 6256 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 1 +; RV32-NEXT: addi a0, a0, 128 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_4kb_offset_128: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 1 +; RV64-NEXT: addiw a0, a0, 128 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 6256 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 1 +; RV64-NEXT: addiw a0, a0, 128 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [6240 x i8] + call void @callee(ptr %a) + ret void +} + + ;; 2^13-16+2032 define void @frame_8kb() { ; RV32-LABEL: frame_8kb: @@ -221,6 +265,92 @@ define void @frame_8kb() { ret void } +define void @frame_8kb_offset_128() { +; RV32-LABEL: frame_8kb_offset_128: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 2 +; RV32-NEXT: addi a0, a0, 128 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 10352 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 2 +; RV32-NEXT: addi a0, a0, 128 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_8kb_offset_128: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 2 +; RV64-NEXT: addiw a0, a0, 128 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 10352 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 2 +; RV64-NEXT: addiw a0, a0, 128 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [10336 x i8] + call void @callee(ptr %a) + ret void +} + +define void @frame_16kb_minus_80() { +; RV32-LABEL: frame_16kb_minus_80: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -2032 +; RV32-NEXT: .cfi_def_cfa_offset 2032 +; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: lui a0, 4 +; RV32-NEXT: addi a0, a0, -80 +; RV32-NEXT: sub sp, sp, a0 +; RV32-NEXT: .cfi_def_cfa_offset 18336 +; RV32-NEXT: addi a0, sp, 12 +; RV32-NEXT: call callee +; RV32-NEXT: lui a0, 4 +; RV32-NEXT: addi a0, a0, -80 +; RV32-NEXT: add sp, sp, a0 +; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 2032 +; RV32-NEXT: ret +; +; RV64-LABEL: frame_16kb_minus_80: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -2032 +; RV64-NEXT: .cfi_def_cfa_offset 2032 +; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: lui a0, 4 +; RV64-NEXT: addiw a0, a0, -80 +; RV64-NEXT: sub sp, sp, a0 +; RV64-NEXT: .cfi_def_cfa_offset 18336 +; RV64-NEXT: addi a0, sp, 8 +; RV64-NEXT: call callee +; RV64-NEXT: lui a0, 4 +; RV64-NEXT: addiw a0, a0, -80 +; RV64-NEXT: add sp, sp, a0 +; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 2032 +; RV64-NEXT: ret + %a = alloca [18320 x i8] + call void @callee(ptr %a) + ret void +} + ;; 2^14-16+2032 define void @frame_16kb() { ; RV32-LABEL: frame_16kb: -- GitLab From eb26edbbf8479aacac0b03413159c8836994a734 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Mon, 8 Apr 2024 14:53:21 -0700 Subject: [PATCH 195/695] [RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950) If we're falling back to generic constant formation in a register + add/sub, we can check if we have a constant which is 12-bits but left shifted by 2 or 3. If so, we can use a sh2add or sh3add to perform the shift and add in a single instruction. This is profitable when the unshifted constant would require two instructions (LUI/ADDI) to form, but is never harmful since we're going to need at least two instructions regardless of the constant value. Since stacks are aligned to 16 bytes by default, sh3add allows addresing (aligned) data out to 2^14 (i.e. 16kb) in at most two instructions w/zba. --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 25 ++ llvm/test/CodeGen/RISCV/prolog-epilogue.ll | 323 +++++++++++------ llvm/test/CodeGen/RISCV/stack-offset.ll | 375 +++++++++++++------- 3 files changed, 481 insertions(+), 242 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 713260b090e9..426a8b66b2e1 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -248,6 +248,31 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB, return; } + // Use shNadd if doing so lets us materialize a 12 bit immediate with a single + // instruction. This saves 1 instruction over the full lui/addi+add fallback + // path. We avoid anything which can be done with a single lui as it might + // be compressible. Note that the sh1add case is fully covered by the 2x addi + // case just above and is thus ommitted. + if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) { + unsigned Opc = 0; + if (isShiftedInt<12, 3>(Val)) { + Opc = RISCV::SH3ADD; + Val = Val >> 3; + } else if (isShiftedInt<12, 2>(Val)) { + Opc = RISCV::SH2ADD; + Val = Val >> 2; + } + if (Opc) { + Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); + TII->movImm(MBB, II, DL, ScratchReg, Val, Flag); + BuildMI(MBB, II, DL, TII->get(Opc), DestReg) + .addReg(ScratchReg, RegState::Kill) + .addReg(SrcReg, getKillRegState(KillSrcReg)) + .setMIFlag(Flag); + return; + } + } + unsigned Opc = RISCV::ADD; if (Val < 0) { Val = -Val; diff --git a/llvm/test/CodeGen/RISCV/prolog-epilogue.ll b/llvm/test/CodeGen/RISCV/prolog-epilogue.ll index 1204499deef5..50b236470ae6 100644 --- a/llvm/test/CodeGen/RISCV/prolog-epilogue.ll +++ b/llvm/test/CodeGen/RISCV/prolog-epilogue.ll @@ -182,43 +182,77 @@ define void @frame_4kb() { } define void @frame_4kb_offset_128() { -; RV32-LABEL: frame_4kb_offset_128: -; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -2032 -; RV32-NEXT: .cfi_def_cfa_offset 2032 -; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: lui a0, 1 -; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: sub sp, sp, a0 -; RV32-NEXT: .cfi_def_cfa_offset 6256 -; RV32-NEXT: addi a0, sp, 12 -; RV32-NEXT: call callee -; RV32-NEXT: lui a0, 1 -; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: add sp, sp, a0 -; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: ret +; RV32I-LABEL: frame_4kb_offset_128: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -2032 +; RV32I-NEXT: .cfi_def_cfa_offset 2032 +; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: lui a0, 1 +; RV32I-NEXT: addi a0, a0, 128 +; RV32I-NEXT: sub sp, sp, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 6256 +; RV32I-NEXT: addi a0, sp, 12 +; RV32I-NEXT: call callee +; RV32I-NEXT: lui a0, 1 +; RV32I-NEXT: addi a0, a0, 128 +; RV32I-NEXT: add sp, sp, a0 +; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: ret ; -; RV64-LABEL: frame_4kb_offset_128: -; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -2032 -; RV64-NEXT: .cfi_def_cfa_offset 2032 -; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: lui a0, 1 -; RV64-NEXT: addiw a0, a0, 128 -; RV64-NEXT: sub sp, sp, a0 -; RV64-NEXT: .cfi_def_cfa_offset 6256 -; RV64-NEXT: addi a0, sp, 8 -; RV64-NEXT: call callee -; RV64-NEXT: lui a0, 1 -; RV64-NEXT: addiw a0, a0, 128 -; RV64-NEXT: add sp, sp, a0 -; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: ret +; RV32ZBA-LABEL: frame_4kb_offset_128: +; RV32ZBA: # %bb.0: +; RV32ZBA-NEXT: addi sp, sp, -2032 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV32ZBA-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32ZBA-NEXT: .cfi_offset ra, -4 +; RV32ZBA-NEXT: li a0, -528 +; RV32ZBA-NEXT: sh3add sp, a0, sp +; RV32ZBA-NEXT: .cfi_def_cfa_offset 6256 +; RV32ZBA-NEXT: addi a0, sp, 12 +; RV32ZBA-NEXT: call callee +; RV32ZBA-NEXT: li a0, 528 +; RV32ZBA-NEXT: sh3add sp, a0, sp +; RV32ZBA-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: ret +; +; RV64I-LABEL: frame_4kb_offset_128: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -2032 +; RV64I-NEXT: .cfi_def_cfa_offset 2032 +; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: lui a0, 1 +; RV64I-NEXT: addiw a0, a0, 128 +; RV64I-NEXT: sub sp, sp, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 6256 +; RV64I-NEXT: addi a0, sp, 8 +; RV64I-NEXT: call callee +; RV64I-NEXT: lui a0, 1 +; RV64I-NEXT: addiw a0, a0, 128 +; RV64I-NEXT: add sp, sp, a0 +; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: frame_4kb_offset_128: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: addi sp, sp, -2032 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV64ZBA-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64ZBA-NEXT: .cfi_offset ra, -8 +; RV64ZBA-NEXT: li a0, -528 +; RV64ZBA-NEXT: sh3add sp, a0, sp +; RV64ZBA-NEXT: .cfi_def_cfa_offset 6256 +; RV64ZBA-NEXT: addi a0, sp, 8 +; RV64ZBA-NEXT: call callee +; RV64ZBA-NEXT: li a0, 528 +; RV64ZBA-NEXT: sh3add sp, a0, sp +; RV64ZBA-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: ret %a = alloca [6240 x i8] call void @callee(ptr %a) ret void @@ -266,86 +300,154 @@ define void @frame_8kb() { } define void @frame_8kb_offset_128() { -; RV32-LABEL: frame_8kb_offset_128: -; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -2032 -; RV32-NEXT: .cfi_def_cfa_offset 2032 -; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: lui a0, 2 -; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: sub sp, sp, a0 -; RV32-NEXT: .cfi_def_cfa_offset 10352 -; RV32-NEXT: addi a0, sp, 12 -; RV32-NEXT: call callee -; RV32-NEXT: lui a0, 2 -; RV32-NEXT: addi a0, a0, 128 -; RV32-NEXT: add sp, sp, a0 -; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: ret +; RV32I-LABEL: frame_8kb_offset_128: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -2032 +; RV32I-NEXT: .cfi_def_cfa_offset 2032 +; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: lui a0, 2 +; RV32I-NEXT: addi a0, a0, 128 +; RV32I-NEXT: sub sp, sp, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 10352 +; RV32I-NEXT: addi a0, sp, 12 +; RV32I-NEXT: call callee +; RV32I-NEXT: lui a0, 2 +; RV32I-NEXT: addi a0, a0, 128 +; RV32I-NEXT: add sp, sp, a0 +; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: ret ; -; RV64-LABEL: frame_8kb_offset_128: -; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -2032 -; RV64-NEXT: .cfi_def_cfa_offset 2032 -; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: lui a0, 2 -; RV64-NEXT: addiw a0, a0, 128 -; RV64-NEXT: sub sp, sp, a0 -; RV64-NEXT: .cfi_def_cfa_offset 10352 -; RV64-NEXT: addi a0, sp, 8 -; RV64-NEXT: call callee -; RV64-NEXT: lui a0, 2 -; RV64-NEXT: addiw a0, a0, 128 -; RV64-NEXT: add sp, sp, a0 -; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: ret +; RV32ZBA-LABEL: frame_8kb_offset_128: +; RV32ZBA: # %bb.0: +; RV32ZBA-NEXT: addi sp, sp, -2032 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV32ZBA-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32ZBA-NEXT: .cfi_offset ra, -4 +; RV32ZBA-NEXT: li a0, -1040 +; RV32ZBA-NEXT: sh3add sp, a0, sp +; RV32ZBA-NEXT: .cfi_def_cfa_offset 10352 +; RV32ZBA-NEXT: addi a0, sp, 12 +; RV32ZBA-NEXT: call callee +; RV32ZBA-NEXT: li a0, 1040 +; RV32ZBA-NEXT: sh3add sp, a0, sp +; RV32ZBA-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: ret +; +; RV64I-LABEL: frame_8kb_offset_128: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -2032 +; RV64I-NEXT: .cfi_def_cfa_offset 2032 +; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: lui a0, 2 +; RV64I-NEXT: addiw a0, a0, 128 +; RV64I-NEXT: sub sp, sp, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 10352 +; RV64I-NEXT: addi a0, sp, 8 +; RV64I-NEXT: call callee +; RV64I-NEXT: lui a0, 2 +; RV64I-NEXT: addiw a0, a0, 128 +; RV64I-NEXT: add sp, sp, a0 +; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: frame_8kb_offset_128: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: addi sp, sp, -2032 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV64ZBA-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64ZBA-NEXT: .cfi_offset ra, -8 +; RV64ZBA-NEXT: li a0, -1040 +; RV64ZBA-NEXT: sh3add sp, a0, sp +; RV64ZBA-NEXT: .cfi_def_cfa_offset 10352 +; RV64ZBA-NEXT: addi a0, sp, 8 +; RV64ZBA-NEXT: call callee +; RV64ZBA-NEXT: li a0, 1040 +; RV64ZBA-NEXT: sh3add sp, a0, sp +; RV64ZBA-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: ret %a = alloca [10336 x i8] call void @callee(ptr %a) ret void } define void @frame_16kb_minus_80() { -; RV32-LABEL: frame_16kb_minus_80: -; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -2032 -; RV32-NEXT: .cfi_def_cfa_offset 2032 -; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: lui a0, 4 -; RV32-NEXT: addi a0, a0, -80 -; RV32-NEXT: sub sp, sp, a0 -; RV32-NEXT: .cfi_def_cfa_offset 18336 -; RV32-NEXT: addi a0, sp, 12 -; RV32-NEXT: call callee -; RV32-NEXT: lui a0, 4 -; RV32-NEXT: addi a0, a0, -80 -; RV32-NEXT: add sp, sp, a0 -; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: ret +; RV32I-LABEL: frame_16kb_minus_80: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -2032 +; RV32I-NEXT: .cfi_def_cfa_offset 2032 +; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: lui a0, 4 +; RV32I-NEXT: addi a0, a0, -80 +; RV32I-NEXT: sub sp, sp, a0 +; RV32I-NEXT: .cfi_def_cfa_offset 18336 +; RV32I-NEXT: addi a0, sp, 12 +; RV32I-NEXT: call callee +; RV32I-NEXT: lui a0, 4 +; RV32I-NEXT: addi a0, a0, -80 +; RV32I-NEXT: add sp, sp, a0 +; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: ret ; -; RV64-LABEL: frame_16kb_minus_80: -; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -2032 -; RV64-NEXT: .cfi_def_cfa_offset 2032 -; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: lui a0, 4 -; RV64-NEXT: addiw a0, a0, -80 -; RV64-NEXT: sub sp, sp, a0 -; RV64-NEXT: .cfi_def_cfa_offset 18336 -; RV64-NEXT: addi a0, sp, 8 -; RV64-NEXT: call callee -; RV64-NEXT: lui a0, 4 -; RV64-NEXT: addiw a0, a0, -80 -; RV64-NEXT: add sp, sp, a0 -; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: ret +; RV32ZBA-LABEL: frame_16kb_minus_80: +; RV32ZBA: # %bb.0: +; RV32ZBA-NEXT: addi sp, sp, -2032 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV32ZBA-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32ZBA-NEXT: .cfi_offset ra, -4 +; RV32ZBA-NEXT: li a0, -2038 +; RV32ZBA-NEXT: sh3add sp, a0, sp +; RV32ZBA-NEXT: .cfi_def_cfa_offset 18336 +; RV32ZBA-NEXT: addi a0, sp, 12 +; RV32ZBA-NEXT: call callee +; RV32ZBA-NEXT: li a0, 2038 +; RV32ZBA-NEXT: sh3add sp, a0, sp +; RV32ZBA-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: ret +; +; RV64I-LABEL: frame_16kb_minus_80: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -2032 +; RV64I-NEXT: .cfi_def_cfa_offset 2032 +; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: lui a0, 4 +; RV64I-NEXT: addiw a0, a0, -80 +; RV64I-NEXT: sub sp, sp, a0 +; RV64I-NEXT: .cfi_def_cfa_offset 18336 +; RV64I-NEXT: addi a0, sp, 8 +; RV64I-NEXT: call callee +; RV64I-NEXT: lui a0, 4 +; RV64I-NEXT: addiw a0, a0, -80 +; RV64I-NEXT: add sp, sp, a0 +; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: frame_16kb_minus_80: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: addi sp, sp, -2032 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV64ZBA-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64ZBA-NEXT: .cfi_offset ra, -8 +; RV64ZBA-NEXT: li a0, -2038 +; RV64ZBA-NEXT: sh3add sp, a0, sp +; RV64ZBA-NEXT: .cfi_def_cfa_offset 18336 +; RV64ZBA-NEXT: addi a0, sp, 8 +; RV64ZBA-NEXT: call callee +; RV64ZBA-NEXT: li a0, 2038 +; RV64ZBA-NEXT: sh3add sp, a0, sp +; RV64ZBA-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: ret %a = alloca [18320 x i8] call void @callee(ptr %a) ret void @@ -430,8 +532,3 @@ define void @frame_32kb() { call void @callee(ptr %a) ret void } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; RV32I: {{.*}} -; RV32ZBA: {{.*}} -; RV64I: {{.*}} -; RV64ZBA: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/stack-offset.ll b/llvm/test/CodeGen/RISCV/stack-offset.ll index 6a24e5dcdbc3..cc81fd62eba9 100644 --- a/llvm/test/CodeGen/RISCV/stack-offset.ll +++ b/llvm/test/CodeGen/RISCV/stack-offset.ll @@ -11,55 +11,101 @@ declare void @inspect(...) define void @test() { -; RV32-LABEL: test: -; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -2032 -; RV32-NEXT: .cfi_def_cfa_offset 2032 -; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: addi sp, sp, -2048 -; RV32-NEXT: addi sp, sp, -1120 -; RV32-NEXT: .cfi_def_cfa_offset 5200 -; RV32-NEXT: addi a0, sp, 12 -; RV32-NEXT: addi a1, sp, 2047 -; RV32-NEXT: addi a1, a1, 13 -; RV32-NEXT: lui a2, 1 -; RV32-NEXT: addi a2, a2, 12 -; RV32-NEXT: add a2, sp, a2 -; RV32-NEXT: lui a3, 1 -; RV32-NEXT: addi a3, a3, 1036 -; RV32-NEXT: add a3, sp, a3 -; RV32-NEXT: call inspect -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: addi sp, sp, 1136 -; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: ret +; RV32I-LABEL: test: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -2032 +; RV32I-NEXT: .cfi_def_cfa_offset 2032 +; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: addi sp, sp, -2048 +; RV32I-NEXT: addi sp, sp, -1120 +; RV32I-NEXT: .cfi_def_cfa_offset 5200 +; RV32I-NEXT: addi a0, sp, 12 +; RV32I-NEXT: addi a1, sp, 2047 +; RV32I-NEXT: addi a1, a1, 13 +; RV32I-NEXT: lui a2, 1 +; RV32I-NEXT: addi a2, a2, 12 +; RV32I-NEXT: add a2, sp, a2 +; RV32I-NEXT: lui a3, 1 +; RV32I-NEXT: addi a3, a3, 1036 +; RV32I-NEXT: add a3, sp, a3 +; RV32I-NEXT: call inspect +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: addi sp, sp, 1136 +; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: ret ; -; RV64-LABEL: test: -; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -2032 -; RV64-NEXT: .cfi_def_cfa_offset 2032 -; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: addi sp, sp, -2048 -; RV64-NEXT: addi sp, sp, -1120 -; RV64-NEXT: .cfi_def_cfa_offset 5200 -; RV64-NEXT: addi a0, sp, 8 -; RV64-NEXT: addi a1, sp, 2047 -; RV64-NEXT: addi a1, a1, 9 -; RV64-NEXT: lui a2, 1 -; RV64-NEXT: addiw a2, a2, 8 -; RV64-NEXT: add a2, sp, a2 -; RV64-NEXT: lui a3, 1 -; RV64-NEXT: addiw a3, a3, 1032 -; RV64-NEXT: add a3, sp, a3 -; RV64-NEXT: call inspect -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: addi sp, sp, 1136 -; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: ret +; RV32ZBA-LABEL: test: +; RV32ZBA: # %bb.0: +; RV32ZBA-NEXT: addi sp, sp, -2032 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV32ZBA-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32ZBA-NEXT: .cfi_offset ra, -4 +; RV32ZBA-NEXT: addi sp, sp, -2048 +; RV32ZBA-NEXT: addi sp, sp, -1120 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 5200 +; RV32ZBA-NEXT: addi a0, sp, 12 +; RV32ZBA-NEXT: addi a1, sp, 2047 +; RV32ZBA-NEXT: addi a1, a1, 13 +; RV32ZBA-NEXT: li a2, 1027 +; RV32ZBA-NEXT: sh2add a2, a2, sp +; RV32ZBA-NEXT: li a3, 1283 +; RV32ZBA-NEXT: sh2add a3, a3, sp +; RV32ZBA-NEXT: call inspect +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: addi sp, sp, 1136 +; RV32ZBA-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: ret +; +; RV64I-LABEL: test: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -2032 +; RV64I-NEXT: .cfi_def_cfa_offset 2032 +; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: addi sp, sp, -2048 +; RV64I-NEXT: addi sp, sp, -1120 +; RV64I-NEXT: .cfi_def_cfa_offset 5200 +; RV64I-NEXT: addi a0, sp, 8 +; RV64I-NEXT: addi a1, sp, 2047 +; RV64I-NEXT: addi a1, a1, 9 +; RV64I-NEXT: lui a2, 1 +; RV64I-NEXT: addiw a2, a2, 8 +; RV64I-NEXT: add a2, sp, a2 +; RV64I-NEXT: lui a3, 1 +; RV64I-NEXT: addiw a3, a3, 1032 +; RV64I-NEXT: add a3, sp, a3 +; RV64I-NEXT: call inspect +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: addi sp, sp, 1136 +; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: test: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: addi sp, sp, -2032 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV64ZBA-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64ZBA-NEXT: .cfi_offset ra, -8 +; RV64ZBA-NEXT: addi sp, sp, -2048 +; RV64ZBA-NEXT: addi sp, sp, -1120 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 5200 +; RV64ZBA-NEXT: addi a0, sp, 8 +; RV64ZBA-NEXT: addi a1, sp, 2047 +; RV64ZBA-NEXT: addi a1, a1, 9 +; RV64ZBA-NEXT: li a2, 513 +; RV64ZBA-NEXT: sh3add a2, a2, sp +; RV64ZBA-NEXT: li a3, 641 +; RV64ZBA-NEXT: sh3add a3, a3, sp +; RV64ZBA-NEXT: call inspect +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: addi sp, sp, 1136 +; RV64ZBA-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: ret %p4 = alloca [64 x i8], align 1 %p3 = alloca [1024 x i8], align 1 %p2 = alloca [2048 x i8], align 1 @@ -69,45 +115,83 @@ define void @test() { } define void @align_8() { -; RV32-LABEL: align_8: -; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -2032 -; RV32-NEXT: .cfi_def_cfa_offset 2032 -; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: addi sp, sp, -2048 -; RV32-NEXT: addi sp, sp, -32 -; RV32-NEXT: .cfi_def_cfa_offset 4112 -; RV32-NEXT: addi a0, sp, 7 -; RV32-NEXT: lui a1, 1 -; RV32-NEXT: addi a1, a1, 8 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: call inspect -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: addi sp, sp, 48 -; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: ret +; RV32I-LABEL: align_8: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -2032 +; RV32I-NEXT: .cfi_def_cfa_offset 2032 +; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: addi sp, sp, -2048 +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: .cfi_def_cfa_offset 4112 +; RV32I-NEXT: addi a0, sp, 7 +; RV32I-NEXT: lui a1, 1 +; RV32I-NEXT: addi a1, a1, 8 +; RV32I-NEXT: add a1, sp, a1 +; RV32I-NEXT: call inspect +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: addi sp, sp, 48 +; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: ret ; -; RV64-LABEL: align_8: -; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -2032 -; RV64-NEXT: .cfi_def_cfa_offset 2032 -; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: addi sp, sp, -2048 -; RV64-NEXT: addi sp, sp, -48 -; RV64-NEXT: .cfi_def_cfa_offset 4128 -; RV64-NEXT: addi a0, sp, 15 -; RV64-NEXT: lui a1, 1 -; RV64-NEXT: addiw a1, a1, 16 -; RV64-NEXT: add a1, sp, a1 -; RV64-NEXT: call inspect -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: addi sp, sp, 64 -; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: ret +; RV32ZBA-LABEL: align_8: +; RV32ZBA: # %bb.0: +; RV32ZBA-NEXT: addi sp, sp, -2032 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV32ZBA-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32ZBA-NEXT: .cfi_offset ra, -4 +; RV32ZBA-NEXT: addi sp, sp, -2048 +; RV32ZBA-NEXT: addi sp, sp, -32 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 4112 +; RV32ZBA-NEXT: addi a0, sp, 7 +; RV32ZBA-NEXT: li a1, 513 +; RV32ZBA-NEXT: sh3add a1, a1, sp +; RV32ZBA-NEXT: call inspect +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: addi sp, sp, 48 +; RV32ZBA-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: ret +; +; RV64I-LABEL: align_8: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -2032 +; RV64I-NEXT: .cfi_def_cfa_offset 2032 +; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: addi sp, sp, -2048 +; RV64I-NEXT: addi sp, sp, -48 +; RV64I-NEXT: .cfi_def_cfa_offset 4128 +; RV64I-NEXT: addi a0, sp, 15 +; RV64I-NEXT: lui a1, 1 +; RV64I-NEXT: addiw a1, a1, 16 +; RV64I-NEXT: add a1, sp, a1 +; RV64I-NEXT: call inspect +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: addi sp, sp, 64 +; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: align_8: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: addi sp, sp, -2032 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV64ZBA-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64ZBA-NEXT: .cfi_offset ra, -8 +; RV64ZBA-NEXT: addi sp, sp, -2048 +; RV64ZBA-NEXT: addi sp, sp, -48 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 4128 +; RV64ZBA-NEXT: addi a0, sp, 15 +; RV64ZBA-NEXT: li a1, 514 +; RV64ZBA-NEXT: sh3add a1, a1, sp +; RV64ZBA-NEXT: call inspect +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: addi sp, sp, 64 +; RV64ZBA-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: ret %p2 = alloca i8, align 8 %p1 = alloca [4097 x i8], align 1 call void (...) @inspect(ptr %p1, ptr %p2) @@ -115,45 +199,83 @@ define void @align_8() { } define void @align_4() { -; RV32-LABEL: align_4: -; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -2032 -; RV32-NEXT: .cfi_def_cfa_offset 2032 -; RV32-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill -; RV32-NEXT: .cfi_offset ra, -4 -; RV32-NEXT: addi sp, sp, -2048 -; RV32-NEXT: addi sp, sp, -32 -; RV32-NEXT: .cfi_def_cfa_offset 4112 -; RV32-NEXT: addi a0, sp, 7 -; RV32-NEXT: lui a1, 1 -; RV32-NEXT: addi a1, a1, 8 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: call inspect -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: addi sp, sp, 48 -; RV32-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload -; RV32-NEXT: addi sp, sp, 2032 -; RV32-NEXT: ret +; RV32I-LABEL: align_4: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -2032 +; RV32I-NEXT: .cfi_def_cfa_offset 2032 +; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: addi sp, sp, -2048 +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: .cfi_def_cfa_offset 4112 +; RV32I-NEXT: addi a0, sp, 7 +; RV32I-NEXT: lui a1, 1 +; RV32I-NEXT: addi a1, a1, 8 +; RV32I-NEXT: add a1, sp, a1 +; RV32I-NEXT: call inspect +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: addi sp, sp, 48 +; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 2032 +; RV32I-NEXT: ret ; -; RV64-LABEL: align_4: -; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -2032 -; RV64-NEXT: .cfi_def_cfa_offset 2032 -; RV64-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill -; RV64-NEXT: .cfi_offset ra, -8 -; RV64-NEXT: addi sp, sp, -2048 -; RV64-NEXT: addi sp, sp, -48 -; RV64-NEXT: .cfi_def_cfa_offset 4128 -; RV64-NEXT: addi a0, sp, 19 -; RV64-NEXT: lui a1, 1 -; RV64-NEXT: addiw a1, a1, 20 -; RV64-NEXT: add a1, sp, a1 -; RV64-NEXT: call inspect -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: addi sp, sp, 64 -; RV64-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 2032 -; RV64-NEXT: ret +; RV32ZBA-LABEL: align_4: +; RV32ZBA: # %bb.0: +; RV32ZBA-NEXT: addi sp, sp, -2032 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV32ZBA-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill +; RV32ZBA-NEXT: .cfi_offset ra, -4 +; RV32ZBA-NEXT: addi sp, sp, -2048 +; RV32ZBA-NEXT: addi sp, sp, -32 +; RV32ZBA-NEXT: .cfi_def_cfa_offset 4112 +; RV32ZBA-NEXT: addi a0, sp, 7 +; RV32ZBA-NEXT: li a1, 513 +; RV32ZBA-NEXT: sh3add a1, a1, sp +; RV32ZBA-NEXT: call inspect +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: addi sp, sp, 48 +; RV32ZBA-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload +; RV32ZBA-NEXT: addi sp, sp, 2032 +; RV32ZBA-NEXT: ret +; +; RV64I-LABEL: align_4: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -2032 +; RV64I-NEXT: .cfi_def_cfa_offset 2032 +; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: addi sp, sp, -2048 +; RV64I-NEXT: addi sp, sp, -48 +; RV64I-NEXT: .cfi_def_cfa_offset 4128 +; RV64I-NEXT: addi a0, sp, 19 +; RV64I-NEXT: lui a1, 1 +; RV64I-NEXT: addiw a1, a1, 20 +; RV64I-NEXT: add a1, sp, a1 +; RV64I-NEXT: call inspect +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: addi sp, sp, 64 +; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 2032 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: align_4: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: addi sp, sp, -2032 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 2032 +; RV64ZBA-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill +; RV64ZBA-NEXT: .cfi_offset ra, -8 +; RV64ZBA-NEXT: addi sp, sp, -2048 +; RV64ZBA-NEXT: addi sp, sp, -48 +; RV64ZBA-NEXT: .cfi_def_cfa_offset 4128 +; RV64ZBA-NEXT: addi a0, sp, 19 +; RV64ZBA-NEXT: li a1, 1029 +; RV64ZBA-NEXT: sh2add a1, a1, sp +; RV64ZBA-NEXT: call inspect +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: addi sp, sp, 64 +; RV64ZBA-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload +; RV64ZBA-NEXT: addi sp, sp, 2032 +; RV64ZBA-NEXT: ret %p2 = alloca i8, align 4 %p1 = alloca [4097 x i8], align 1 call void (...) @inspect(ptr %p1, ptr %p2) @@ -252,8 +374,3 @@ define void @align_1() { call void (...) @inspect(ptr %p1, ptr %p2) ret void } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; RV32I: {{.*}} -; RV32ZBA: {{.*}} -; RV64I: {{.*}} -; RV64ZBA: {{.*}} -- GitLab From 16b3e43a030b0322e0d81debba3d63f145c8fd0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Mon, 8 Apr 2024 23:54:29 +0200 Subject: [PATCH 196/695] [clang-tidy] Ignore non-forwarded arguments if they are unused (#87832) --- .../MissingStdForwardCheck.cpp | 21 ++++++++++++------- clang-tools-extra/docs/ReleaseNotes.rst | 5 +++-- .../cppcoreguidelines/missing-std-forward.cpp | 13 ++++++++++++ 3 files changed, 30 insertions(+), 9 deletions(-) diff --git a/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp b/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp index 87fd8adf9970..bbb35228ce47 100644 --- a/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp +++ b/clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp @@ -9,8 +9,8 @@ #include "MissingStdForwardCheck.h" #include "../utils/Matchers.h" #include "clang/AST/ASTContext.h" -#include "clang/AST/ExprConcepts.h" #include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/Basic/IdentifierTable.h" using namespace clang::ast_matchers; @@ -79,6 +79,11 @@ AST_MATCHER_P(LambdaExpr, hasCaptureDefaultKind, LambdaCaptureDefault, Kind) { return Node.getCaptureDefault() == Kind; } +AST_MATCHER(VarDecl, hasIdentifier) { + const IdentifierInfo *ID = Node.getIdentifier(); + return ID != NULL && !ID->isPlaceholder(); +} + } // namespace void MissingStdForwardCheck::registerMatchers(MatchFinder *Finder) { @@ -125,12 +130,14 @@ void MissingStdForwardCheck::registerMatchers(MatchFinder *Finder) { hasAncestor(expr(hasUnevaluatedContext()))))); Finder->addMatcher( - parmVarDecl(parmVarDecl().bind("param"), isTemplateTypeParameter(), - hasAncestor(functionDecl().bind("func")), - hasAncestor(functionDecl( - isDefinition(), equalsBoundNode("func"), ToParam, - unless(anyOf(isDeleted(), hasDescendant(std::move( - ForwardCallMatcher))))))), + parmVarDecl( + parmVarDecl().bind("param"), hasIdentifier(), + unless(hasAttr(attr::Kind::Unused)), isTemplateTypeParameter(), + hasAncestor(functionDecl().bind("func")), + hasAncestor(functionDecl( + isDefinition(), equalsBoundNode("func"), ToParam, + unless(anyOf(isDeleted(), + hasDescendant(std::move(ForwardCallMatcher))))))), this); } diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index bdd53f06e7e2..a7193e90c38d 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -179,8 +179,9 @@ Changes in existing checks - Improved :doc:`cppcoreguidelines-missing-std-forward ` check by no longer - giving false positives for deleted functions and fix false negative when some - parameters are forwarded, but other aren't. + giving false positives for deleted functions, by fixing false negatives when only + a few parameters are forwarded and by ignoring parameters without a name (unused + arguments). - Improved :doc:`cppcoreguidelines-owning-memory ` check to properly handle diff --git a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp index 9a50eabf619b..8116db58c937 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp @@ -198,3 +198,16 @@ struct S { }; } // namespace deleted_functions + +namespace unused_arguments { + +template +void unused_argument1(F&&) {} + +template +void unused_argument2([[maybe_unused]] F&& f) {} + +template +void unused_argument3(F&& _) {} + +} // namespace unused_arguments -- GitLab From 1950ebd17bbf1f2ad2a3799cd5966412ccfee9c4 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Mon, 8 Apr 2024 15:03:34 -0700 Subject: [PATCH 197/695] [ARM64EC] Fix compilation of intrin.h in ARM64EC mode. (#87717) intrin.h checks for x86_64. But the "x86_64" define is also defined for ARM64EC, and we don't support all the intrinsics in ARM64EC mode. Fix the preprocessor checks to handle this correctly. (If we actually need some of these intrinsics in ARM64EC mode, we can revisit later.) Not exactly sure how I didn't run into this issue before now... I think I've built code that requires these headers, but maybe not since the define fix landed. --- clang/lib/Headers/intrin.h | 17 +++++++++-------- clang/lib/Headers/intrin0.h | 10 +++++----- clang/test/Headers/ms-intrin.cpp | 14 ++++++++++++-- 3 files changed, 26 insertions(+), 15 deletions(-) diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h index fd27955fbe00..e890dcd7feeb 100644 --- a/clang/lib/Headers/intrin.h +++ b/clang/lib/Headers/intrin.h @@ -18,7 +18,7 @@ #include /* First include the standard intrinsics. */ -#if defined(__i386__) || defined(__x86_64__) +#if defined(__i386__) || (defined(__x86_64__) && !defined(__arm64ec__)) #include #endif @@ -166,7 +166,7 @@ unsigned __int32 xbegin(void); void _xend(void); /* These additional intrinsics are turned on in x64/amd64/x86_64 mode. */ -#ifdef __x86_64__ +#if defined(__x86_64__) && !defined(__arm64ec__) void __addgsbyte(unsigned long, unsigned char); void __addgsdword(unsigned long, unsigned long); void __addgsqword(unsigned long, unsigned __int64); @@ -236,7 +236,8 @@ __int64 _mul128(__int64, __int64, __int64 *); /*----------------------------------------------------------------------------*\ |* movs, stos \*----------------------------------------------------------------------------*/ -#if defined(__i386__) || defined(__x86_64__) + +#if defined(__i386__) || (defined(__x86_64__) && !defined(__arm64ec__)) static __inline__ void __DEFAULT_FN_ATTRS __movsb(unsigned char *__dst, unsigned char const *__src, size_t __n) { @@ -305,7 +306,7 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosw(unsigned short *__dst, : "memory"); } #endif -#ifdef __x86_64__ +#if defined(__x86_64__) && !defined(__arm64ec__) static __inline__ void __DEFAULT_FN_ATTRS __movsq( unsigned long long *__dst, unsigned long long const *__src, size_t __n) { __asm__ __volatile__("rep movsq" @@ -324,7 +325,7 @@ static __inline__ void __DEFAULT_FN_ATTRS __stosq(unsigned __int64 *__dst, /*----------------------------------------------------------------------------*\ |* Misc \*----------------------------------------------------------------------------*/ -#if defined(__i386__) || defined(__x86_64__) +#if defined(__i386__) || (defined(__x86_64__) && !defined(__arm64ec__)) static __inline__ void __DEFAULT_FN_ATTRS __halt(void) { __asm__ volatile("hlt"); } @@ -339,7 +340,7 @@ static __inline__ void __DEFAULT_FN_ATTRS __nop(void) { /*----------------------------------------------------------------------------*\ |* MS AArch64 specific \*----------------------------------------------------------------------------*/ -#if defined(__aarch64__) +#if defined(__aarch64__) || defined(__arm64ec__) unsigned __int64 __getReg(int); long _InterlockedAdd(long volatile *Addend, long Value); __int64 _InterlockedAdd64(__int64 volatile *Addend, __int64 Value); @@ -383,7 +384,7 @@ void __cdecl __prefetch(void *); /*----------------------------------------------------------------------------*\ |* Privileged intrinsics \*----------------------------------------------------------------------------*/ -#if defined(__i386__) || defined(__x86_64__) +#if defined(__i386__) || (defined(__x86_64__) && !defined(__arm64ec__)) static __inline__ unsigned __int64 __DEFAULT_FN_ATTRS __readmsr(unsigned long __register) { // Loads the contents of a 64-bit model specific register (MSR) specified in @@ -397,7 +398,6 @@ __readmsr(unsigned long __register) { __asm__ ("rdmsr" : "=d"(__edx), "=a"(__eax) : "c"(__register)); return (((unsigned __int64)__edx) << 32) | (unsigned __int64)__eax; } -#endif static __inline__ unsigned __LPTRINT_TYPE__ __DEFAULT_FN_ATTRS __readcr3(void) { unsigned __LPTRINT_TYPE__ __cr3_val; @@ -413,6 +413,7 @@ static __inline__ void __DEFAULT_FN_ATTRS __writecr3(unsigned __INTPTR_TYPE__ __cr3_val) { __asm__ ("mov {%0, %%cr3|cr3, %0}" : : "r"(__cr3_val) : "memory"); } +#endif #ifdef __cplusplus } diff --git a/clang/lib/Headers/intrin0.h b/clang/lib/Headers/intrin0.h index 31f362ec84d5..866c8896617d 100644 --- a/clang/lib/Headers/intrin0.h +++ b/clang/lib/Headers/intrin0.h @@ -15,7 +15,7 @@ #ifndef __INTRIN0_H #define __INTRIN0_H -#ifdef __x86_64__ +#if defined(__x86_64__) && !defined(__arm64ec__) #include #endif @@ -27,7 +27,7 @@ unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask); unsigned char _BitScanReverse(unsigned long *_Index, unsigned long _Mask); void _ReadWriteBarrier(void); -#if defined(__aarch64__) +#if defined(__aarch64__) || defined(__arm64ec__) unsigned int _CountLeadingZeros(unsigned long); unsigned int _CountLeadingZeros64(unsigned _int64); unsigned char _InterlockedCompareExchange128_acq(__int64 volatile *_Destination, @@ -44,7 +44,7 @@ unsigned char _InterlockedCompareExchange128_rel(__int64 volatile *_Destination, __int64 *_ComparandResult); #endif -#ifdef __x86_64__ +#ifdef __x86_64__ && !defined(__arm64ec__) unsigned __int64 _umul128(unsigned __int64, unsigned __int64, unsigned __int64 *); unsigned __int64 __shiftleft128(unsigned __int64 _LowPart, @@ -55,7 +55,7 @@ unsigned __int64 __shiftright128(unsigned __int64 _LowPart, unsigned char _Shift); #endif -#if defined(__x86_64__) || defined(__i386__) +#if defined(__i386__) || (defined(__x86_64__) && !defined(__arm64ec__)) void _mm_pause(void); #endif @@ -83,7 +83,7 @@ __int64 _InterlockedXor64(__int64 volatile *_Value, __int64 _Mask); __int64 _InterlockedAnd64(__int64 volatile *_Value, __int64 _Mask); #endif -#if defined(__arm__) || defined(__aarch64__) +#if defined(__arm__) || defined(__aarch64__) || defined(__arm64ec__) /*----------------------------------------------------------------------------*\ |* Interlocked Exchange Add \*----------------------------------------------------------------------------*/ diff --git a/clang/test/Headers/ms-intrin.cpp b/clang/test/Headers/ms-intrin.cpp index d3b6a1a278da..cb7cd4795620 100644 --- a/clang/test/Headers/ms-intrin.cpp +++ b/clang/test/Headers/ms-intrin.cpp @@ -18,6 +18,16 @@ // RUN: -ffreestanding -fsyntax-only -Werror \ // RUN: -isystem %S/Inputs/include %s +// RUN: %clang_cc1 -triple aarch64--windows \ +// RUN: -fms-compatibility -fms-compatibility-version=17.00 \ +// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -isystem %S/Inputs/include %s + +// RUN: %clang_cc1 -triple arm64ec--windows \ +// RUN: -fms-compatibility -fms-compatibility-version=17.00 \ +// RUN: -ffreestanding -fsyntax-only -Werror \ +// RUN: -isystem %S/Inputs/include %s + // REQUIRES: x86-registered-target // intrin.h needs size_t, but -ffreestanding prevents us from getting it from @@ -41,7 +51,7 @@ void f() { __stosd(0, 0, 0); __stosw(0, 0, 0); -#ifdef _M_X64 +#if defined(_M_X64) && !defined(_M_ARM64EC) __movsq(0, 0, 0); __stosq(0, 0, 0); #endif @@ -49,7 +59,7 @@ void f() { int info[4]; __cpuid(info, 0); __cpuidex(info, 0, 0); -#if defined(_M_X64) || defined(_M_IX86) +#if (defined(_M_X64) && !defined(_M_ARM64EC)) || defined(_M_IX86) _xgetbv(0); #endif __halt(); -- GitLab From ff9b63f8d0487b69b35cf90a7089ad075f7fab88 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Apr 2024 15:14:39 -0700 Subject: [PATCH 198/695] [test][UBSAN] Fix windows after #87761 --- .../ubsan/TestCases/ImplicitConversion/bitfield-conversion.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c index a0c5ba55c43d..cd718fb55847 100644 --- a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c +++ b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c @@ -33,7 +33,7 @@ typedef struct _X { int32_t j : 32; uint32_t k : 1; int32_t l : 1; - _Bool m : 1; + bool m : 1; } X; void test_a() { -- GitLab From 7ad481e76c9bee5b9895ebfa0fdb52f31cb7de77 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Mon, 8 Apr 2024 15:16:00 -0700 Subject: [PATCH 199/695] Revert "[AArch64] Add support for -ffixed-x30" (#88019) This reverts commit e770153865c53c4fd72a68f23acff33c24e42a08. This wasn't reviewed, and the functionality in question was intentionally rejected the last time it was discussed in https://reviews.llvm.org/D56305 . --- clang/lib/Driver/ToolChains/Arch/AArch64.cpp | 3 --- clang/test/Driver/aarch64-fixed-x-register.c | 4 ---- llvm/lib/Target/AArch64/AArch64.td | 2 +- llvm/test/CodeGen/AArch64/arm64-platform-reg.ll | 7 +------ 4 files changed, 2 insertions(+), 14 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 3e6e29584df3..2cd2b35ee51b 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -402,9 +402,6 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, if (Args.hasArg(options::OPT_ffixed_x28)) Features.push_back("+reserve-x28"); - if (Args.hasArg(options::OPT_ffixed_x30)) - Features.push_back("+reserve-x30"); - if (Args.hasArg(options::OPT_fcall_saved_x8)) Features.push_back("+call-saved-x8"); diff --git a/clang/test/Driver/aarch64-fixed-x-register.c b/clang/test/Driver/aarch64-fixed-x-register.c index 29024fde4125..7fc3e3e61105 100644 --- a/clang/test/Driver/aarch64-fixed-x-register.c +++ b/clang/test/Driver/aarch64-fixed-x-register.c @@ -94,10 +94,6 @@ // RUN: FileCheck --check-prefix=CHECK-FIXED-X28 < %t %s // CHECK-FIXED-X28: "-target-feature" "+reserve-x28" -// RUN: %clang --target=aarch64-none-gnu -ffixed-x30 -### %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-FIXED-X30 < %t %s -// CHECK-FIXED-X30: "-target-feature" "+reserve-x30" - // Test multiple of reserve-x# options together. // RUN: %clang --target=aarch64-none-gnu \ // RUN: -ffixed-x1 \ diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 3af427d526f8..741c97a3dc00 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -212,7 +212,7 @@ def FeatureStrictAlign : SubtargetFeature<"strict-align", "Disallow all unaligned memory " "access">; -foreach i = {1-7,9-15,18,20-28,30} in +foreach i = {1-7,9-15,18,20-28} in def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", "Reserve X"#i#", making it unavailable " "as a GPR">; diff --git a/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll b/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll index c598306c2de3..3df2ef7aa59f 100644 --- a/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll +++ b/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll @@ -34,7 +34,6 @@ ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x26 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X26 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x27 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X27 ; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x28 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X28 -; RUN: llc -mtriple=arm64-linux-gnu -mattr=+reserve-x30 -o - %s | FileCheck %s --check-prefixes=CHECK-RESERVE,CHECK-RESERVE-X30 ; Test multiple of reserve-x# options together. ; RUN: llc -mtriple=arm64-linux-gnu \ @@ -73,7 +72,6 @@ ; RUN: -mattr=+reserve-x26 \ ; RUN: -mattr=+reserve-x27 \ ; RUN: -mattr=+reserve-x28 \ -; RUN: -mattr=+reserve-x30 \ ; RUN: -reserve-regs-for-regalloc=X8,X16,X17,X19 \ ; RUN: -o - %s | FileCheck %s \ ; RUN: --check-prefix=CHECK-RESERVE \ @@ -104,8 +102,7 @@ ; RUN: --check-prefix=CHECK-RESERVE-X25 \ ; RUN: --check-prefix=CHECK-RESERVE-X26 \ ; RUN: --check-prefix=CHECK-RESERVE-X27 \ -; RUN: --check-prefix=CHECK-RESERVE-X28 \ -; RUN: --check-prefix=CHECK-RESERVE-X30 +; RUN: --check-prefix=CHECK-RESERVE-X28 ; x18 is reserved as a platform register on Darwin but not on other ; systems. Create loads of register pressure and make sure this is respected. @@ -152,7 +149,6 @@ define void @keep_live() { ; CHECK-RESERVE-X26-NOT: ldr x26 ; CHECK-RESERVE-X27-NOT: ldr x27 ; CHECK-RESERVE-X28-NOT: ldr x28 -; CHECK-RESERVE-X30-NOT: ldr x30 ; CHECK-RESERVE: Spill ; CHECK-RESERVE-NOT: ldr fp ; CHECK-RESERVE-X1-NOT: ldr x1, @@ -182,7 +178,6 @@ define void @keep_live() { ; CHECK-RESERVE-X26-NOT: ldr x26 ; CHECK-RESERVE-X27-NOT: ldr x27 ; CHECK-RESERVE-X28-NOT: ldr x28 -; CHECK-RESERVE-X30-NOT: ldr x30 ; CHECK-RESERVE: ret ret void } -- GitLab From 96bba13bd6bfb4ff0635972723adcd9c72b65bae Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Apr 2024 15:20:51 -0700 Subject: [PATCH 200/695] [test][UBSAN] Fix Solaris after #87761 --- .../ImplicitConversion/bitfield-conversion.c | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c index cd718fb55847..fc53552a8adc 100644 --- a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c +++ b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c @@ -191,26 +191,26 @@ void test_c() { // Assignment x.c = v8; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 64 (8-bit, unsigned) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint8_t' (aka 'unsigned char') of value 64 (8-bit, unsigned) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) x.c = v16; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint16_t' (aka 'unsigned short') of value 320 (16-bit, unsigned) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint16_t' (aka 'unsigned short') of value 320 (16-bit, unsigned) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) x.c = v32; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 320 (32-bit, unsigned) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint32_t' (aka 'unsigned int') of value 320 (32-bit, unsigned) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) // PrePostIncDec x.c = min; x.c--; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 63 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to 63 (7-bit bitfield, signed) x.c = min; --x.c; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 63 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to 63 (7-bit bitfield, signed) x.c = max; x.c++; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) x.c = max; ++x.c; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) x.c = min + 1; x.c++; @@ -237,19 +237,19 @@ void test_c() { x.c += max; x.c = 0; x.c += (max + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) x.c = 0; x.c -= (-min); x.c = 0; x.c -= (-min + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 63 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -65 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to 63 (7-bit bitfield, signed) x.c = 1; x.c *= max; x.c = 1; x.c *= (max + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -64 (7-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 64 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -64 (7-bit bitfield, signed) } void test_d() { @@ -459,26 +459,26 @@ void test_h() { // Assignment x.h = v16; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int16_t' (aka 'short') of value 128 (16-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int16_t' (aka 'short') of value 128 (16-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -128 (8-bit bitfield, signed) x.h = v32; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int32_t' (aka 'int') of value 128 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -128 (8-bit bitfield, signed) // PrePostIncDec x.h = min; x.h--; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 127 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to 127 (8-bit bitfield, signed) x.h = min; --x.h; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 127 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to 127 (8-bit bitfield, signed) x.h = min + 1; x.h--; x.h = max; x.h++; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:6: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -128 (8-bit bitfield, signed) x.h = max; ++x.h; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:3: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -128 (8-bit bitfield, signed) x.h = max - 1; x.h++; @@ -487,13 +487,13 @@ void test_h() { x.h += max; x.h = 0; x.h += (max + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to -128 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value 128 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to -128 (8-bit bitfield, signed) x.h = 0; x.h -= (-min); x.h = 0; x.h -= (-min + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka 'signed char') changed the value to 127 (8-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int' of value -129 (32-bit, signed) to type 'int8_t' (aka '{{(signed )?}}char') changed the value to 127 (8-bit bitfield, signed) } void test_i() { -- GitLab From bee33770188f29d0369655c6d178c0bfb937e872 Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Mon, 8 Apr 2024 22:21:45 +0000 Subject: [PATCH 201/695] [bazel] Add `nobuildkite` tags for incompatible targets --- utils/bazel/llvm-project-overlay/lldb/BUILD.bazel | 6 ++++++ .../llvm-project-overlay/lldb/source/Plugins/BUILD.bazel | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel index 300f2798f7aa..6dfe8085b928 100644 --- a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel @@ -440,6 +440,7 @@ cc_library( "source/Host/macosx/objcxx/*.h", ]), strip_include_prefix = "source", + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], @@ -453,6 +454,7 @@ objc_library( "source/Host/macosx/objcxx/*.mm", ]), copts = OBJCPP_COPTS, + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], @@ -780,6 +782,7 @@ objc_library( name = "DebugServerMacOSX", srcs = glob(["tools/debugserver/source/MacOSX/*.mm"]), copts = OBJCPP_COPTS, + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], @@ -796,6 +799,7 @@ cc_library( ["tools/debugserver/source/**/*.cpp"], exclude = ["tools/debugserver/source/debugserver.cpp"], ), + tags = ["nobuildkite"], local_defines = ["LLDB_USE_OS_LOG"], deps = [ ":DebugServerCommonHeaders", @@ -814,6 +818,7 @@ genrule( "mach_excUser.c", ], cmd = "mig -header $(location :mach_exc.h) -server $(location :mach_excServer.c) -user $(location :mach_excUser.c) $(SRCS)", + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], @@ -834,6 +839,7 @@ cc_binary( ":debugserver_version_gen", ":mach_gen", ], + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], diff --git a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel index 95773ed653b8..bbc523f54a19 100644 --- a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel @@ -232,6 +232,7 @@ cc_library( name = "PluginPlatformMacOSXObjCXXHeaders", hdrs = glob(["Platform/MacOSX/objcxx/*.h"]), include_prefix = "Plugins", + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], @@ -243,6 +244,7 @@ objc_library( name = "PluginPlatformMacOSXObjCXX", srcs = glob(["Platform/MacOSX/objcxx/*.mm"]), copts = OBJCPP_COPTS, + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], @@ -1750,6 +1752,7 @@ cc_library( srcs = glob(["SymbolLocator/DebugSymbols/*.cpp"]), hdrs = glob(["SymbolLocator/DebugSymbols/*.h"]), include_prefix = "Plugins", + tags = ["nobuildkite"], deps = [ ":PluginObjectFileWasm", "//lldb:Core", @@ -2178,6 +2181,7 @@ cc_library( srcs = glob(["Process/MacOSX-Kernel/*.cpp"]), hdrs = glob(["Process/MacOSX-Kernel/*.h"]), include_prefix = "Plugins", + tags = ["nobuildkite"], target_compatible_with = select({ "@platforms//os:macos": [], "//conditions:default": ["@platforms//:incompatible"], -- GitLab From f94bbfed7cf08f60e20756dce8965d2c6ed70ea1 Mon Sep 17 00:00:00 2001 From: Max Winkler Date: Mon, 8 Apr 2024 18:24:08 -0400 Subject: [PATCH 202/695] [Clang][CodeGen] Fix `CanSkipVTablePointerInitialization` for dynamic classes with a trivial anonymous union (#84651) Hit this when trying upgrade an old project of mine. I couldn't find a corresponding existing issue for this when spelunking the open issues here on github. Thankfully I can work-around it today with the `[[clang::no_destroy]]` attribute for my use case. However it should still be properly fixed. ### Issue and History ### https://godbolt.org/z/EYnhce8MK for reference. All subsequent text below refers to the example in the godbolt above. Anonymous unions never have their destructor invoked automatically. Therefore we can skip vtable initialization of the destructor of a dynamic class if that destructor effectively does no work. This worked previously as the following check would be hit and return true for the trivial anonymous union, https://github.com/llvm/llvm-project/blob/release/18.x/clang/lib/CodeGen/CGClass.cpp#L1348, resulting in the code skipping vtable initialization. This was broken here https://github.com/llvm/llvm-project/commit/982bbf404eba2d968afda5c674d4821652159c53 in relation to comments made on this review here https://reviews.llvm.org/D10508. ### Fixes ### The check the code is doing is correct however the return value is inverted. We want to return true here since a field with anonymous union never has its destructor invoked and thus effectively has a trivial destructor body from the perspective of requiring vtable init in the parent dynamic class. Also added some extra missing unit tests to test for this use case and a couple others. --- clang/lib/CodeGen/CGClass.cpp | 2 +- .../skip-vtable-pointer-initialization.cpp | 62 +++++++++++++++++++ 2 files changed, 63 insertions(+), 1 deletion(-) diff --git a/clang/lib/CodeGen/CGClass.cpp b/clang/lib/CodeGen/CGClass.cpp index 8c1c8ee455d2..b3077292f4a2 100644 --- a/clang/lib/CodeGen/CGClass.cpp +++ b/clang/lib/CodeGen/CGClass.cpp @@ -1404,7 +1404,7 @@ FieldHasTrivialDestructorBody(ASTContext &Context, // The destructor for an implicit anonymous union member is never invoked. if (FieldClassDecl->isUnion() && FieldClassDecl->isAnonymousStructOrUnion()) - return false; + return true; return HasTrivialDestructorBody(Context, FieldClassDecl, FieldClassDecl); } diff --git a/clang/test/CodeGenCXX/skip-vtable-pointer-initialization.cpp b/clang/test/CodeGenCXX/skip-vtable-pointer-initialization.cpp index c001ce9b755d..714ce3e67be7 100644 --- a/clang/test/CodeGenCXX/skip-vtable-pointer-initialization.cpp +++ b/clang/test/CodeGenCXX/skip-vtable-pointer-initialization.cpp @@ -198,3 +198,65 @@ struct C : virtual B { C::~C() {} } + +namespace Test10 { + +// Check that we don't initialize the vtable pointer in A::~A(), since the class has an anonymous union which +// never has its destructor invoked. +struct A { + virtual void f(); + ~A(); + + union + { + int i; + unsigned u; + }; +}; + +// CHECK-LABEL: define{{.*}} void @_ZN6Test101AD2Ev +// CHECK-NOT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTVN6Test101AE, i32 0, inrange i32 0, i32 2), ptr +A::~A() { +} + +} + +namespace Test11 { + +// Check that we don't initialize the vtable pointer in A::~A(), even if the base class has a non trivial destructor. +struct Field { + ~Field(); +}; + +struct A : public Field { + virtual void f(); + ~A(); +}; + +// CHECK-LABEL: define{{.*}} void @_ZN6Test111AD2Ev +// CHECK-NOT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTVN6Test111AE, i32 0, inrange i32 0, i32 2), ptr +A::~A() { +} + +} + +namespace Test12 { + +// Check that we don't initialize the vtable pointer in A::~A(), since the class has an anonymous struct with trivial fields. +struct A { + virtual void f(); + ~A(); + + struct + { + int i; + unsigned u; + }; +}; + +// CHECK-LABEL: define{{.*}} void @_ZN6Test121AD2Ev +// CHECK-NOT: store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTVN6Test121AE, i32 0, inrange i32 0, i32 2), ptr +A::~A() { +} + +} -- GitLab From 59aba90ab6648b968b67677ce445ba11c05a3823 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Apr 2024 15:24:04 -0700 Subject: [PATCH 203/695] [test][UBSAN] Simplify regex in the test --- .../ImplicitConversion/bitfield-conversion.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c index fc53552a8adc..3b359f071a61 100644 --- a/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c +++ b/compiler-rt/test/ubsan/TestCases/ImplicitConversion/bitfield-conversion.c @@ -418,7 +418,7 @@ void test_g() { // Assignment x.g = v64; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned {{long|long long}}') of value 4294967296 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (32-bit bitfield, unsigned) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned long{{( long)?}}') of value 4294967296 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (32-bit bitfield, unsigned) // PrePostIncDec x.g = min; @@ -440,13 +440,13 @@ void test_g() { x.g += max; x.g = 0; x.g += (max + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned {{long|long long}}') of value 4294967296 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (32-bit bitfield, unsigned) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned long{{( long)?}}') of value 4294967296 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 0 (32-bit bitfield, unsigned) x.g = max; x.g -= max; x.g = max; x.g -= (max + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned {{long|long long}}') of value 18446744073709551615 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 4294967295 (32-bit bitfield, unsigned) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'uint64_t' (aka 'unsigned long{{( long)?}}') of value 18446744073709551615 (64-bit, unsigned) to type 'uint32_t' (aka 'unsigned int') changed the value to 4294967295 (32-bit bitfield, unsigned) } void test_h() { @@ -549,7 +549,7 @@ void test_j() { // Assignment x.j = v64; - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka '{{long|long long}}') of value 2147483648 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to -2147483648 (32-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka 'long{{( long)?}}') of value 2147483648 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to -2147483648 (32-bit bitfield, signed) // PrePostIncDec x.j = min; @@ -571,13 +571,13 @@ void test_j() { x.j += max; x.j = 0; x.j += (max + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka '{{long|long long}}') of value 2147483648 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to -2147483648 (32-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka 'long{{( long)?}}') of value 2147483648 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to -2147483648 (32-bit bitfield, signed) x.j = 0; x.j -= (-min); x.j = 0; x.j -= (-min + 1); - // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka '{{long|long long}}') of value -2147483649 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to 2147483647 (32-bit bitfield, signed) + // CHECK: {{.*}}bitfield-conversion.c:[[@LINE-1]]:7: runtime error: implicit conversion from type 'int64_t' (aka 'long{{( long)?}}') of value -2147483649 (64-bit, signed) to type 'int32_t' (aka 'int') changed the value to 2147483647 (32-bit bitfield, signed) } void test_k_l() { -- GitLab From e27c3736f975ca463476223c465e4777186f603f Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Mon, 8 Apr 2024 16:40:19 -0600 Subject: [PATCH 204/695] [X86] Change how we treat functions with explicit sections as small/large (#87838) Following #78348, we should treat functions with an explicit section as small, unless the section name is (or has the prefix) ".ltext". Clang emits global initializers into a ".text.startup" section on Linux. If we mix small/medium code model object files with large code model object files, we'll end up mixing sections with and without the large section flag. --- llvm/lib/Target/TargetMachine.cpp | 20 +++++++++++----- .../X86/code-model-elf-text-sections.ll | 23 +++++++++++++++++++ 2 files changed, 37 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index a7fe329b064e..61abb85b6458 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -51,9 +51,20 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { auto *GV = dyn_cast(GO); + auto IsPrefix = [](StringRef Name, StringRef Prefix) { + return Name.consume_front(Prefix) && (Name.empty() || Name[0] == '.'); + }; + // Functions/GlobalIFuncs are only large under the large code model. - if (!GV) + if (!GV) { + // Handle explicit sections as we do for GlobalVariables with an explicit + // section, see comments below. + if (GO->hasSection()) { + StringRef Name = GO->getSection(); + return IsPrefix(Name, ".ltext"); + } return getCodeModel() == CodeModel::Large; + } if (GV->isThreadLocal()) return false; @@ -73,11 +84,8 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { // data sections. The code model attribute overrides this above. if (GV->hasSection()) { StringRef Name = GV->getSection(); - auto IsPrefix = [&](StringRef Prefix) { - StringRef S = Name; - return S.consume_front(Prefix) && (S.empty() || S[0] == '.'); - }; - return IsPrefix(".lbss") || IsPrefix(".ldata") || IsPrefix(".lrodata"); + return IsPrefix(Name, ".lbss") || IsPrefix(Name, ".ldata") || + IsPrefix(Name, ".lrodata"); } // Respect large data threshold for medium and large code models. diff --git a/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll b/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll index 016c9a4d7b83..66a6fd376754 100644 --- a/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll +++ b/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll @@ -13,9 +13,20 @@ ; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=LARGE-DS ; SMALL: .text {{.*}} AX {{.*}} +; SMALL: .ltext {{.*}} AXl {{.*}} +; SMALL: .ltext.2 {{.*}} AXl {{.*}} +; SMALL: .foo {{.*}} AX {{.*}} ; SMALL-DS: .text.func {{.*}} AX {{.*}} +; SMALL-DS: .ltext {{.*}} AXl {{.*}} +; SMALL-DS: .ltext.2 {{.*}} AXl {{.*}} +; SMALL-DS: .foo {{.*}} AX {{.*}} ; LARGE: .ltext {{.*}} AXl {{.*}} +; LARGE: .ltext.2 {{.*}} AXl {{.*}} +; LARGE: .foo {{.*}} AX {{.*}} ; LARGE-DS: .ltext.func {{.*}} AXl {{.*}} +; LARGE-DS: .ltext {{.*}} AXl {{.*}} +; LARGE-DS: .ltext.2 {{.*}} AXl {{.*}} +; LARGE-DS: .foo {{.*}} AX {{.*}} target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64--linux" @@ -23,3 +34,15 @@ target triple = "x86_64--linux" define void @func() { ret void } + +define void @ltext() section ".ltext" { + ret void +} + +define void @ltext2() section ".ltext.2" { + ret void +} + +define void @foo() section ".foo" { + ret void +} -- GitLab From 50b937331ff44ac4b4ee70c3bfc0c4da51a02855 Mon Sep 17 00:00:00 2001 From: Corentin Ferry Date: Tue, 9 Apr 2024 00:41:12 +0200 Subject: [PATCH 205/695] [mlir] Add missing libm member operations to MathToLibm (#87981) This PR adds support for lowering the following Math operations to `libm` calls: * `math.absf` -> `fabsf, fabs` * `math.exp` -> `expf, exp` * `math.exp2` -> `exp2f, exp2` * `math.fma` -> `fmaf, fma` * `math.log` -> `logf, log` * `math.log2` -> `log2f, log2` * `math.log10` -> `log10f, log10` * `math.powf` -> `powf, pow` * `math.sqrt` -> `sqrtf, sqrt` These operations are direct members of `libm`, and do not seem to require any special manipulations on their operands. --- mlir/lib/Conversion/MathToLibm/MathToLibm.cpp | 9 + .../MathToLibm/convert-to-libm.mlir | 367 ++++++++++++++++++ 2 files changed, 376 insertions(+) diff --git a/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp b/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp index d1372576407f..5b1c59d0c95e 100644 --- a/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp +++ b/mlir/lib/Conversion/MathToLibm/MathToLibm.cpp @@ -162,6 +162,7 @@ ScalarOpToLibmCall::matchAndRewrite(Op op, void mlir::populateMathToLibmConversionPatterns(RewritePatternSet &patterns) { MLIRContext *ctx = patterns.getContext(); + populatePatternsForOp(patterns, ctx, "fabsf", "fabs"); populatePatternsForOp(patterns, ctx, "acosf", "acos"); populatePatternsForOp(patterns, ctx, "acoshf", "acosh"); populatePatternsForOp(patterns, ctx, "asinf", "asin"); @@ -174,14 +175,22 @@ void mlir::populateMathToLibmConversionPatterns(RewritePatternSet &patterns) { populatePatternsForOp(patterns, ctx, "cosf", "cos"); populatePatternsForOp(patterns, ctx, "coshf", "cosh"); populatePatternsForOp(patterns, ctx, "erff", "erf"); + populatePatternsForOp(patterns, ctx, "expf", "exp"); + populatePatternsForOp(patterns, ctx, "exp2f", "exp2"); populatePatternsForOp(patterns, ctx, "expm1f", "expm1"); populatePatternsForOp(patterns, ctx, "floorf", "floor"); + populatePatternsForOp(patterns, ctx, "fmaf", "fma"); + populatePatternsForOp(patterns, ctx, "logf", "log"); + populatePatternsForOp(patterns, ctx, "log2f", "log2"); + populatePatternsForOp(patterns, ctx, "log10f", "log10"); populatePatternsForOp(patterns, ctx, "log1pf", "log1p"); + populatePatternsForOp(patterns, ctx, "powf", "pow"); populatePatternsForOp(patterns, ctx, "roundevenf", "roundeven"); populatePatternsForOp(patterns, ctx, "roundf", "round"); populatePatternsForOp(patterns, ctx, "sinf", "sin"); populatePatternsForOp(patterns, ctx, "sinhf", "sinh"); + populatePatternsForOp(patterns, ctx, "sqrtf", "sqrt"); populatePatternsForOp(patterns, ctx, "tanf", "tan"); populatePatternsForOp(patterns, ctx, "tanhf", "tanh"); populatePatternsForOp(patterns, ctx, "truncf", "trunc"); diff --git a/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir b/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir index ffc2939afe7f..ffef12250595 100644 --- a/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir +++ b/mlir/test/Conversion/MathToLibm/convert-to-libm.mlir @@ -14,8 +14,24 @@ // CHECK-DAG: @atanhf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @erf(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @erff(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @exp(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @expf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @exp2(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @exp2f(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @expm1(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @expm1f(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @log(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @logf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @log2(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @log2f(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @log10(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @log10f(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @log1p(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @log1pf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @fabs(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @fabsf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @fma(f64, f64, f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @fmaf(f32, f32, f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @atan2(f64, f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @atan2f(f32, f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @cbrt(f64) -> f64 attributes {llvm.readnone} @@ -40,6 +56,47 @@ // CHECK-DAG: @floorf(f32) -> f32 attributes {llvm.readnone} // CHECK-DAG: @ceil(f64) -> f64 attributes {llvm.readnone} // CHECK-DAG: @ceilf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @sqrt(f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @sqrtf(f32) -> f32 attributes {llvm.readnone} +// CHECK-DAG: @pow(f64, f64) -> f64 attributes {llvm.readnone} +// CHECK-DAG: @powf(f32, f32) -> f32 attributes {llvm.readnone} + +// CHECK-LABEL: func @absf_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @absf_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @fabsf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.absf %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @fabs(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.absf %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +// CHECK-LABEL: func @absf_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @fabsf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @fabsf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @fabs(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @fabs(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } +func.func @absf_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.absf %float : vector<2xf32> + %double_result = math.absf %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} // CHECK-LABEL: func @acos_caller // CHECK-SAME: %[[FLOAT:.*]]: f32 @@ -379,6 +436,191 @@ func.func @erf_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vec return %float_result, %double_result : vector<2xf32>, vector<2xf64> } +// CHECK-LABEL: func @exp_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @exp_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @expf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.exp %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @exp(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.exp %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @exp_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.exp %float : vector<2xf32> + %double_result = math.exp %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @exp_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @expf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @expf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @exp(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @exp(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + +// CHECK-LABEL: func @exp2_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @exp2_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @exp2f(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.exp2 %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @exp2(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.exp2 %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @exp2_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.exp2 %float : vector<2xf32> + %double_result = math.exp2 %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @exp2_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @exp2f(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @exp2f(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @exp2(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @exp2(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + +// CHECK-LABEL: func @log_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @log_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @logf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.log %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @log(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.log %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @log_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.log %float : vector<2xf32> + %double_result = math.log %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @log_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @logf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @logf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @log(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @log(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + +// CHECK-LABEL: func @log2_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @log2_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @log2f(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.log2 %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @log2(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.log2 %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @log2_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.log2 %float : vector<2xf32> + %double_result = math.log2 %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @log2_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @log2f(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @log2f(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @log2(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @log2(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + +// CHECK-LABEL: func @log10_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @log10_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @log10f(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.log10 %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @log10(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.log10 %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @log10_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.log10 %float : vector<2xf32> + %double_result = math.log10 %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @log10_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @log10f(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @log10f(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @log10(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @log10(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + // CHECK-LABEL: func @expm1_caller // CHECK-SAME: %[[FLOAT:.*]]: f32 // CHECK-SAME: %[[DOUBLE:.*]]: f64 @@ -438,6 +680,52 @@ func.func @expm1_multidim_vec_caller(%float: vector<2x2xf32>) -> (vector<2x2xf32 // CHECK: return %[[VAL_4]] : vector<2x2xf32> // CHECK: } +// CHECK-LABEL: func @fma_caller( +// CHECK-SAME: %[[FLOATA:.*]]: f32, %[[FLOATB:.*]]: f32, %[[FLOATC:.*]]: f32 +// CHECK-SAME: %[[DOUBLEA:.*]]: f64, %[[DOUBLEB:.*]]: f64, %[[DOUBLEC:.*]]: f64 +func.func @fma_caller(%float_a: f32, %float_b: f32, %float_c: f32, %double_a: f64, %double_b: f64, %double_c: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @fmaf(%[[FLOATA]], %[[FLOATB]], %[[FLOATC]]) : (f32, f32, f32) -> f32 + %float_result = math.fma %float_a, %float_b, %float_c : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @fma(%[[DOUBLEA]], %[[DOUBLEB]], %[[DOUBLEC]]) : (f64, f64, f64) -> f64 + %double_result = math.fma %double_a, %double_b, %double_c : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @fma_vec_caller(%float_a: vector<2xf32>, %float_b: vector<2xf32>, %float_c: vector<2xf32>, %double_a: vector<2xf64>, %double_b: vector<2xf64>, %double_c: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.fma %float_a, %float_b, %float_c : vector<2xf32> + %double_result = math.fma %double_a, %double_b, %double_c : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @fma_vec_caller( +// CHECK-SAME: %[[VAL_0A:.*]]: vector<2xf32>, %[[VAL_0B:.*]]: vector<2xf32>, %[[VAL_0C:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1A:.*]]: vector<2xf64>, %[[VAL_1B:.*]]: vector<2xf64>, %[[VAL_1C:.*]]: vector<2xf64> +// CHECK-SAME: ) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32A:.*]] = vector.extract %[[VAL_0A]][0] : f32 from vector<2xf32> +// CHECK: %[[IN0_F32B:.*]] = vector.extract %[[VAL_0B]][0] : f32 from vector<2xf32> +// CHECK: %[[IN0_F32C:.*]] = vector.extract %[[VAL_0C]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @fmaf(%[[IN0_F32A]], %[[IN0_F32B]], %[[IN0_F32C]]) : (f32, f32, f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32A:.*]] = vector.extract %[[VAL_0A]][1] : f32 from vector<2xf32> +// CHECK: %[[IN1_F32B:.*]] = vector.extract %[[VAL_0B]][1] : f32 from vector<2xf32> +// CHECK: %[[IN1_F32C:.*]] = vector.extract %[[VAL_0C]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @fmaf(%[[IN1_F32A]], %[[IN1_F32B]], %[[IN1_F32C]]) : (f32, f32, f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64A:.*]] = vector.extract %[[VAL_1A]][0] : f64 from vector<2xf64> +// CHECK: %[[IN0_F64B:.*]] = vector.extract %[[VAL_1B]][0] : f64 from vector<2xf64> +// CHECK: %[[IN0_F64C:.*]] = vector.extract %[[VAL_1C]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @fma(%[[IN0_F64A]], %[[IN0_F64B]], %[[IN0_F64C]]) : (f64, f64, f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64A:.*]] = vector.extract %[[VAL_1A]][1] : f64 from vector<2xf64> +// CHECK: %[[IN1_F64B:.*]] = vector.extract %[[VAL_1B]][1] : f64 from vector<2xf64> +// CHECK: %[[IN1_F64C:.*]] = vector.extract %[[VAL_1C]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @fma(%[[IN1_F64A]], %[[IN1_F64B]], %[[IN1_F64C]]) : (f64, f64, f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + // CHECK-LABEL: func @round_caller // CHECK-SAME: %[[FLOAT:.*]]: f32 // CHECK-SAME: %[[DOUBLE:.*]]: f64 @@ -673,3 +961,82 @@ func.func @ceil_caller(%float: f32, %double: f64) -> (f32, f64) { // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] return %float_result, %double_result : f32, f64 } + +// CHECK-LABEL: func @sqrt_caller +// CHECK-SAME: %[[FLOAT:.*]]: f32 +// CHECK-SAME: %[[DOUBLE:.*]]: f64 +func.func @sqrt_caller(%float: f32, %double: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @sqrtf(%[[FLOAT]]) : (f32) -> f32 + %float_result = math.sqrt %float : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @sqrt(%[[DOUBLE]]) : (f64) -> f64 + %double_result = math.sqrt %double : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @sqrt_vec_caller(%float: vector<2xf32>, %double: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.sqrt %float : vector<2xf32> + %double_result = math.sqrt %double : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @sqrt_vec_caller( +// CHECK-SAME: %[[VAL_0:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1:.*]]: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32:.*]] = vector.extract %[[VAL_0]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @sqrtf(%[[IN0_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32:.*]] = vector.extract %[[VAL_0]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @sqrtf(%[[IN1_F32]]) : (f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64:.*]] = vector.extract %[[VAL_1]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @sqrt(%[[IN0_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64:.*]] = vector.extract %[[VAL_1]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @sqrt(%[[IN1_F64]]) : (f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } + +// CHECK-LABEL: func @powf_caller( +// CHECK-SAME: %[[FLOATA:.*]]: f32, %[[FLOATB:.*]]: f32 +// CHECK-SAME: %[[DOUBLEA:.*]]: f64, %[[DOUBLEB:.*]]: f64 +func.func @powf_caller(%float_a: f32, %float_b: f32, %double_a: f64, %double_b: f64) -> (f32, f64) { + // CHECK-DAG: %[[FLOAT_RESULT:.*]] = call @powf(%[[FLOATA]], %[[FLOATB]]) : (f32, f32) -> f32 + %float_result = math.powf %float_a, %float_b : f32 + // CHECK-DAG: %[[DOUBLE_RESULT:.*]] = call @pow(%[[DOUBLEA]], %[[DOUBLEB]]) : (f64, f64) -> f64 + %double_result = math.powf %double_a, %double_b : f64 + // CHECK: return %[[FLOAT_RESULT]], %[[DOUBLE_RESULT]] + return %float_result, %double_result : f32, f64 +} + +func.func @powf_vec_caller(%float_a: vector<2xf32>, %float_b: vector<2xf32>, %double_a: vector<2xf64>, %double_b: vector<2xf64>) -> (vector<2xf32>, vector<2xf64>) { + %float_result = math.powf %float_a, %float_b : vector<2xf32> + %double_result = math.powf %double_a, %double_b : vector<2xf64> + return %float_result, %double_result : vector<2xf32>, vector<2xf64> +} +// CHECK-LABEL: func @powf_vec_caller( +// CHECK-SAME: %[[VAL_0A:.*]]: vector<2xf32>, %[[VAL_0B:.*]]: vector<2xf32>, +// CHECK-SAME: %[[VAL_1A:.*]]: vector<2xf64>, %[[VAL_1B:.*]]: vector<2xf64> +// CHECK-SAME: ) -> (vector<2xf32>, vector<2xf64>) { +// CHECK-DAG: %[[CVF:.*]] = arith.constant dense<0.000000e+00> : vector<2xf32> +// CHECK-DAG: %[[CVD:.*]] = arith.constant dense<0.000000e+00> : vector<2xf64> +// CHECK: %[[IN0_F32A:.*]] = vector.extract %[[VAL_0A]][0] : f32 from vector<2xf32> +// CHECK: %[[IN0_F32B:.*]] = vector.extract %[[VAL_0B]][0] : f32 from vector<2xf32> +// CHECK: %[[OUT0_F32:.*]] = call @powf(%[[IN0_F32A]], %[[IN0_F32B]]) : (f32, f32) -> f32 +// CHECK: %[[VAL_8:.*]] = vector.insert %[[OUT0_F32]], %[[CVF]] [0] : f32 into vector<2xf32> +// CHECK: %[[IN1_F32A:.*]] = vector.extract %[[VAL_0A]][1] : f32 from vector<2xf32> +// CHECK: %[[IN1_F32B:.*]] = vector.extract %[[VAL_0B]][1] : f32 from vector<2xf32> +// CHECK: %[[OUT1_F32:.*]] = call @powf(%[[IN1_F32A]], %[[IN1_F32B]]) : (f32, f32) -> f32 +// CHECK: %[[VAL_11:.*]] = vector.insert %[[OUT1_F32]], %[[VAL_8]] [1] : f32 into vector<2xf32> +// CHECK: %[[IN0_F64A:.*]] = vector.extract %[[VAL_1A]][0] : f64 from vector<2xf64> +// CHECK: %[[IN0_F64B:.*]] = vector.extract %[[VAL_1B]][0] : f64 from vector<2xf64> +// CHECK: %[[OUT0_F64:.*]] = call @pow(%[[IN0_F64A]], %[[IN0_F64B]]) : (f64, f64) -> f64 +// CHECK: %[[VAL_14:.*]] = vector.insert %[[OUT0_F64]], %[[CVD]] [0] : f64 into vector<2xf64> +// CHECK: %[[IN1_F64A:.*]] = vector.extract %[[VAL_1A]][1] : f64 from vector<2xf64> +// CHECK: %[[IN1_F64B:.*]] = vector.extract %[[VAL_1B]][1] : f64 from vector<2xf64> +// CHECK: %[[OUT1_F64:.*]] = call @pow(%[[IN1_F64A]], %[[IN1_F64B]]) : (f64, f64) -> f64 +// CHECK: %[[VAL_17:.*]] = vector.insert %[[OUT1_F64]], %[[VAL_14]] [1] : f64 into vector<2xf64> +// CHECK: return %[[VAL_11]], %[[VAL_17]] : vector<2xf32>, vector<2xf64> +// CHECK: } -- GitLab From 89ebb56152192e8ad535ddd11ae0f60334fd748a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Apr 2024 15:36:34 -0700 Subject: [PATCH 206/695] [RISCV] Resolve CHECK prefix conflict in fixed-vectors-vwsll.ll. NFC riscv32 and riscv64 generate different code for one test case so we need RV32 and RV64 CHECK lines. --- .../CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll | 57 +++++++++++++++++-- 1 file changed, 53 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll index 83d1d1b3f94c..59b3d752cc20 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB-RV64 ; ============================================================================== ; i32 -> i64 @@ -499,6 +499,55 @@ define <16 x i16> @vwsll_vv_v16i16_zext(<16 x i8> %a, <16 x i8> %b) { } define <16 x i16> @vwsll_vx_i64_v16i16(<16 x i8> %a, i64 %b) { +; RV32-LABEL: vwsll_vx_i64_v16i16: +; RV32: # %bb.0: +; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; RV32-NEXT: vmv.v.x v16, a0 +; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma +; RV32-NEXT: vrgather.vi v24, v16, 0 +; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV32-NEXT: vzext.vf2 v10, v8 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV32-NEXT: vnsrl.wi v12, v24, 0 +; RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV32-NEXT: vnsrl.wi v8, v12, 0 +; RV32-NEXT: vsll.vv v8, v10, v8 +; RV32-NEXT: ret +; +; RV64-LABEL: vwsll_vx_i64_v16i16: +; RV64: # %bb.0: +; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma +; RV64-NEXT: vmv.v.x v16, a0 +; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV64-NEXT: vzext.vf2 v10, v8 +; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV64-NEXT: vnsrl.wi v12, v16, 0 +; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV64-NEXT: vnsrl.wi v8, v12, 0 +; RV64-NEXT: vsll.vv v8, v10, v8 +; RV64-NEXT: ret +; +; CHECK-ZVBB-RV32-LABEL: vwsll_vx_i64_v16i16: +; CHECK-ZVBB-RV32: # %bb.0: +; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma +; CHECK-ZVBB-RV32-NEXT: vmv.v.x v16, a0 +; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma +; CHECK-ZVBB-RV32-NEXT: vrgather.vi v24, v16, 0 +; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; CHECK-ZVBB-RV32-NEXT: vzext.vf2 v10, v8 +; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v12, v24, 0 +; CHECK-ZVBB-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; CHECK-ZVBB-RV32-NEXT: vnsrl.wi v8, v12, 0 +; CHECK-ZVBB-RV32-NEXT: vsll.vv v8, v10, v8 +; CHECK-ZVBB-RV32-NEXT: ret +; +; CHECK-ZVBB-RV64-LABEL: vwsll_vx_i64_v16i16: +; CHECK-ZVBB-RV64: # %bb.0: +; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma +; CHECK-ZVBB-RV64-NEXT: vwsll.vx v10, v8, a0 +; CHECK-ZVBB-RV64-NEXT: vmv2r.v v8, v10 +; CHECK-ZVBB-RV64-NEXT: ret %head = insertelement <8 x i64> poison, i64 %b, i32 0 %splat = shufflevector <8 x i64> %head, <8 x i64> poison, <16 x i32> zeroinitializer %x = zext <16 x i8> %a to <16 x i16> -- GitLab From 279c758b5d681eb7b24d5e3a1da64a7571e61903 Mon Sep 17 00:00:00 2001 From: Zander Dumont-Strom Date: Mon, 8 Apr 2024 15:51:31 -0700 Subject: [PATCH 207/695] [libc][docs] generate docs for ctype.h (#87946) Fixes #87833 --- libc/docs/ctype.rst | 53 ++++++++++++++++++++++++++++++++++++ libc/docs/index.rst | 1 + libc/utils/docgen/ctype.json | 46 +++++++++++++++++++++++++++++-- 3 files changed, 97 insertions(+), 3 deletions(-) create mode 100644 libc/docs/ctype.rst diff --git a/libc/docs/ctype.rst b/libc/docs/ctype.rst new file mode 100644 index 000000000000..c2897e0c58dc --- /dev/null +++ b/libc/docs/ctype.rst @@ -0,0 +1,53 @@ +ctype.h Functions +================= + +.. list-table:: + :widths: auto + :align: center + :header-rows: 1 + + * - Function + - Implemented + - Standard + * - isalnum + - |check| + - 7.4.1.1 + * - isalpha + - |check| + - 7.4.1.2 + * - isblank + - |check| + - 7.4.1.3 + * - iscntrl + - |check| + - 7.4.1.4 + * - isdigit + - |check| + - 7.4.1.5 + * - isgraph + - |check| + - 7.4.1.6 + * - islower + - |check| + - 7.4.1.7 + * - isprint + - |check| + - 7.4.1.8 + * - ispunct + - |check| + - 7.4.1.9 + * - isspace + - |check| + - 7.4.1.10 + * - isupper + - |check| + - 7.4.1.11 + * - isxdigit + - |check| + - 7.4.1.12 + * - tolower + - |check| + - 7.4.2.1 + * - toupper + - |check| + - 7.4.2.2 diff --git a/libc/docs/index.rst b/libc/docs/index.rst index 65ccb91e92ff..8470c8d9287c 100644 --- a/libc/docs/index.rst +++ b/libc/docs/index.rst @@ -69,6 +69,7 @@ stages there is no ABI stability in any form. fenv libc_search c23 + ctype .. toctree:: :hidden: diff --git a/libc/utils/docgen/ctype.json b/libc/utils/docgen/ctype.json index 4102c2dd1109..25eeb683846c 100644 --- a/libc/utils/docgen/ctype.json +++ b/libc/utils/docgen/ctype.json @@ -1,7 +1,47 @@ { "functions": { - "isalnum": null, - "isalpha": null, - "isblank": null + "isalnum": { + "defined": "7.4.1.1" + }, + "isalpha": { + "defined": "7.4.1.2" + }, + "isblank": { + "defined": "7.4.1.3" + }, + "iscntrl": { + "defined": "7.4.1.4" + }, + "isdigit": { + "defined": "7.4.1.5" + }, + "isgraph": { + "defined": "7.4.1.6" + }, + "islower": { + "defined": "7.4.1.7" + }, + "isprint": { + "defined": "7.4.1.8" + }, + "ispunct": { + "defined": "7.4.1.9" + }, + "isspace": { + "defined": "7.4.1.10" + }, + "isupper": { + "defined": "7.4.1.11" + }, + "isxdigit": { + "defined": "7.4.1.12" + }, + "tolower" : { + "defined": "7.4.2.1" + }, + "toupper": { + "defined": "7.4.2.2" + } } } + -- GitLab From e127997155a1cd1c5692c42aad074064c8dad099 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 8 Apr 2024 15:58:36 -0700 Subject: [PATCH 208/695] [libc][docs] fix missing include Fixes #87946 --- libc/docs/ctype.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/libc/docs/ctype.rst b/libc/docs/ctype.rst index c2897e0c58dc..7d77dadccc9b 100644 --- a/libc/docs/ctype.rst +++ b/libc/docs/ctype.rst @@ -1,3 +1,5 @@ +.. include:: check.rst + ctype.h Functions ================= -- GitLab From 922700df44b7fd93dfaf642567283b2b7482e5df Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Mon, 8 Apr 2024 23:00:01 +0000 Subject: [PATCH 209/695] Revert "[X86] Change how we treat functions with explicit sections as small/large (#87838)" This reverts commit e27c3736f975ca463476223c465e4777186f603f. Breaks ExecutionEngine/MCJIT/test-global-ctors.ll on windows, e.g. https://lab.llvm.org/buildbot/#/builders/117/builds/18749. --- llvm/lib/Target/TargetMachine.cpp | 20 +++++----------- .../X86/code-model-elf-text-sections.ll | 23 ------------------- 2 files changed, 6 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp index 61abb85b6458..a7fe329b064e 100644 --- a/llvm/lib/Target/TargetMachine.cpp +++ b/llvm/lib/Target/TargetMachine.cpp @@ -51,20 +51,9 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { auto *GV = dyn_cast(GO); - auto IsPrefix = [](StringRef Name, StringRef Prefix) { - return Name.consume_front(Prefix) && (Name.empty() || Name[0] == '.'); - }; - // Functions/GlobalIFuncs are only large under the large code model. - if (!GV) { - // Handle explicit sections as we do for GlobalVariables with an explicit - // section, see comments below. - if (GO->hasSection()) { - StringRef Name = GO->getSection(); - return IsPrefix(Name, ".ltext"); - } + if (!GV) return getCodeModel() == CodeModel::Large; - } if (GV->isThreadLocal()) return false; @@ -84,8 +73,11 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { // data sections. The code model attribute overrides this above. if (GV->hasSection()) { StringRef Name = GV->getSection(); - return IsPrefix(Name, ".lbss") || IsPrefix(Name, ".ldata") || - IsPrefix(Name, ".lrodata"); + auto IsPrefix = [&](StringRef Prefix) { + StringRef S = Name; + return S.consume_front(Prefix) && (S.empty() || S[0] == '.'); + }; + return IsPrefix(".lbss") || IsPrefix(".ldata") || IsPrefix(".lrodata"); } // Respect large data threshold for medium and large code models. diff --git a/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll b/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll index 66a6fd376754..016c9a4d7b83 100644 --- a/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll +++ b/llvm/test/CodeGen/X86/code-model-elf-text-sections.ll @@ -13,20 +13,9 @@ ; RUN: llvm-readelf -S %t | FileCheck %s --check-prefix=LARGE-DS ; SMALL: .text {{.*}} AX {{.*}} -; SMALL: .ltext {{.*}} AXl {{.*}} -; SMALL: .ltext.2 {{.*}} AXl {{.*}} -; SMALL: .foo {{.*}} AX {{.*}} ; SMALL-DS: .text.func {{.*}} AX {{.*}} -; SMALL-DS: .ltext {{.*}} AXl {{.*}} -; SMALL-DS: .ltext.2 {{.*}} AXl {{.*}} -; SMALL-DS: .foo {{.*}} AX {{.*}} ; LARGE: .ltext {{.*}} AXl {{.*}} -; LARGE: .ltext.2 {{.*}} AXl {{.*}} -; LARGE: .foo {{.*}} AX {{.*}} ; LARGE-DS: .ltext.func {{.*}} AXl {{.*}} -; LARGE-DS: .ltext {{.*}} AXl {{.*}} -; LARGE-DS: .ltext.2 {{.*}} AXl {{.*}} -; LARGE-DS: .foo {{.*}} AX {{.*}} target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64--linux" @@ -34,15 +23,3 @@ target triple = "x86_64--linux" define void @func() { ret void } - -define void @ltext() section ".ltext" { - ret void -} - -define void @ltext2() section ".ltext.2" { - ret void -} - -define void @foo() section ".foo" { - ret void -} -- GitLab From afc7cc7b123666a8917b26c7e483d78cbb79ff8d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Apr 2024 15:52:45 -0700 Subject: [PATCH 210/695] [RISCV] Fix missing CHECK prefixes in vector lrint test files. NFC All of these test cases had iXLen in their name which got replaced by sed. This prevented FileCheck from finding the function. The other test cases in these files do not have that issue. --- .../RISCV/rvv/fixed-vectors-lrint-vp.ll | 20 +- .../CodeGen/RISCV/rvv/fixed-vectors-lrint.ll | 241 +++++++++++++++++- llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll | 21 +- llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll | 36 ++- 4 files changed, 314 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll index 08dd1c79f24c..1c920e42f7d4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint-vp.ll @@ -126,7 +126,25 @@ define <8 x iXLen> @lrint_v8f32(<8 x float> %x, <8 x i1> %m, i32 zeroext %evl) { } declare <8 x iXLen> @llvm.vp.lrint.v8iXLen.v8f32(<8 x float>, <8 x i1>, i32) -define <16 x iXLen> @lrint_v16iXLen_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) { +define <16 x iXLen> @lrint_v16f32(<16 x float> %x, <16 x i1> %m, i32 zeroext %evl) { +; RV32-LABEL: lrint_v16f32: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t +; RV32-NEXT: ret +; +; RV64-i32-LABEL: lrint_v16f32: +; RV64-i32: # %bb.0: +; RV64-i32-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t +; RV64-i32-NEXT: ret +; +; RV64-i64-LABEL: lrint_v16f32: +; RV64-i64: # %bb.0: +; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; RV64-i64-NEXT: vfwcvt.x.f.v v16, v8, v0.t +; RV64-i64-NEXT: vmv8r.v v8, v16 +; RV64-i64-NEXT: ret %a = call <16 x iXLen> @llvm.vp.lrint.v16iXLen.v16f32(<16 x float> %x, <16 x i1> %m, i32 %evl) ret <16 x iXLen> %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll index 224f5066138c..35baa6808db6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll @@ -380,7 +380,246 @@ define <8 x iXLen> @lrint_v8f32(<8 x float> %x) { } declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f32(<8 x float>) -define <16 x iXLen> @lrint_v16iXLen_v16f32(<16 x float> %x) { +define <16 x iXLen> @lrint_v16f32(<16 x float> %x) { +; RV32-LABEL: lrint_v16f32: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -192 +; RV32-NEXT: .cfi_def_cfa_offset 192 +; RV32-NEXT: sw ra, 188(sp) # 4-byte Folded Spill +; RV32-NEXT: sw s0, 184(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: .cfi_offset s0, -8 +; RV32-NEXT: addi s0, sp, 192 +; RV32-NEXT: .cfi_def_cfa s0, 0 +; RV32-NEXT: andi sp, sp, -64 +; RV32-NEXT: mv a0, sp +; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; RV32-NEXT: vse32.v v8, (a0) +; RV32-NEXT: flw fa5, 60(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 124(sp) +; RV32-NEXT: flw fa5, 56(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 120(sp) +; RV32-NEXT: flw fa5, 52(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 116(sp) +; RV32-NEXT: flw fa5, 48(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 112(sp) +; RV32-NEXT: flw fa5, 44(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 108(sp) +; RV32-NEXT: flw fa5, 40(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 104(sp) +; RV32-NEXT: flw fa5, 36(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 100(sp) +; RV32-NEXT: flw fa5, 32(sp) +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 96(sp) +; RV32-NEXT: vfmv.f.s fa5, v8 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 64(sp) +; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32-NEXT: vslidedown.vi v10, v8, 3 +; RV32-NEXT: vfmv.f.s fa5, v10 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 76(sp) +; RV32-NEXT: vslidedown.vi v10, v8, 2 +; RV32-NEXT: vfmv.f.s fa5, v10 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 72(sp) +; RV32-NEXT: vslidedown.vi v10, v8, 1 +; RV32-NEXT: vfmv.f.s fa5, v10 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 68(sp) +; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma +; RV32-NEXT: vslidedown.vi v10, v8, 7 +; RV32-NEXT: vfmv.f.s fa5, v10 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 92(sp) +; RV32-NEXT: vslidedown.vi v10, v8, 6 +; RV32-NEXT: vfmv.f.s fa5, v10 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 88(sp) +; RV32-NEXT: vslidedown.vi v10, v8, 5 +; RV32-NEXT: vfmv.f.s fa5, v10 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 84(sp) +; RV32-NEXT: vslidedown.vi v8, v8, 4 +; RV32-NEXT: vfmv.f.s fa5, v8 +; RV32-NEXT: fcvt.w.s a0, fa5 +; RV32-NEXT: sw a0, 80(sp) +; RV32-NEXT: addi a0, sp, 64 +; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; RV32-NEXT: vle32.v v8, (a0) +; RV32-NEXT: addi sp, s0, -192 +; RV32-NEXT: lw ra, 188(sp) # 4-byte Folded Reload +; RV32-NEXT: lw s0, 184(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 192 +; RV32-NEXT: ret +; +; RV64-i32-LABEL: lrint_v16f32: +; RV64-i32: # %bb.0: +; RV64-i32-NEXT: addi sp, sp, -192 +; RV64-i32-NEXT: .cfi_def_cfa_offset 192 +; RV64-i32-NEXT: sd ra, 184(sp) # 8-byte Folded Spill +; RV64-i32-NEXT: sd s0, 176(sp) # 8-byte Folded Spill +; RV64-i32-NEXT: .cfi_offset ra, -8 +; RV64-i32-NEXT: .cfi_offset s0, -16 +; RV64-i32-NEXT: addi s0, sp, 192 +; RV64-i32-NEXT: .cfi_def_cfa s0, 0 +; RV64-i32-NEXT: andi sp, sp, -64 +; RV64-i32-NEXT: mv a0, sp +; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; RV64-i32-NEXT: vse32.v v8, (a0) +; RV64-i32-NEXT: flw fa5, 60(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 124(sp) +; RV64-i32-NEXT: flw fa5, 56(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 120(sp) +; RV64-i32-NEXT: flw fa5, 52(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 116(sp) +; RV64-i32-NEXT: flw fa5, 48(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 112(sp) +; RV64-i32-NEXT: flw fa5, 44(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 108(sp) +; RV64-i32-NEXT: flw fa5, 40(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 104(sp) +; RV64-i32-NEXT: flw fa5, 36(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 100(sp) +; RV64-i32-NEXT: flw fa5, 32(sp) +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 96(sp) +; RV64-i32-NEXT: vfmv.f.s fa5, v8 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 64(sp) +; RV64-i32-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64-i32-NEXT: vslidedown.vi v10, v8, 3 +; RV64-i32-NEXT: vfmv.f.s fa5, v10 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 76(sp) +; RV64-i32-NEXT: vslidedown.vi v10, v8, 2 +; RV64-i32-NEXT: vfmv.f.s fa5, v10 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 72(sp) +; RV64-i32-NEXT: vslidedown.vi v10, v8, 1 +; RV64-i32-NEXT: vfmv.f.s fa5, v10 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 68(sp) +; RV64-i32-NEXT: vsetivli zero, 1, e32, m2, ta, ma +; RV64-i32-NEXT: vslidedown.vi v10, v8, 7 +; RV64-i32-NEXT: vfmv.f.s fa5, v10 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 92(sp) +; RV64-i32-NEXT: vslidedown.vi v10, v8, 6 +; RV64-i32-NEXT: vfmv.f.s fa5, v10 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 88(sp) +; RV64-i32-NEXT: vslidedown.vi v10, v8, 5 +; RV64-i32-NEXT: vfmv.f.s fa5, v10 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 84(sp) +; RV64-i32-NEXT: vslidedown.vi v8, v8, 4 +; RV64-i32-NEXT: vfmv.f.s fa5, v8 +; RV64-i32-NEXT: fcvt.l.s a0, fa5 +; RV64-i32-NEXT: sw a0, 80(sp) +; RV64-i32-NEXT: addi a0, sp, 64 +; RV64-i32-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; RV64-i32-NEXT: vle32.v v8, (a0) +; RV64-i32-NEXT: addi sp, s0, -192 +; RV64-i32-NEXT: ld ra, 184(sp) # 8-byte Folded Reload +; RV64-i32-NEXT: ld s0, 176(sp) # 8-byte Folded Reload +; RV64-i32-NEXT: addi sp, sp, 192 +; RV64-i32-NEXT: ret +; +; RV64-i64-LABEL: lrint_v16f32: +; RV64-i64: # %bb.0: +; RV64-i64-NEXT: addi sp, sp, -384 +; RV64-i64-NEXT: .cfi_def_cfa_offset 384 +; RV64-i64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill +; RV64-i64-NEXT: sd s0, 368(sp) # 8-byte Folded Spill +; RV64-i64-NEXT: .cfi_offset ra, -8 +; RV64-i64-NEXT: .cfi_offset s0, -16 +; RV64-i64-NEXT: addi s0, sp, 384 +; RV64-i64-NEXT: .cfi_def_cfa s0, 0 +; RV64-i64-NEXT: andi sp, sp, -128 +; RV64-i64-NEXT: addi a0, sp, 64 +; RV64-i64-NEXT: vsetivli zero, 16, e32, m4, ta, ma +; RV64-i64-NEXT: vse32.v v8, (a0) +; RV64-i64-NEXT: flw fa5, 124(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 248(sp) +; RV64-i64-NEXT: flw fa5, 120(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 240(sp) +; RV64-i64-NEXT: flw fa5, 116(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 232(sp) +; RV64-i64-NEXT: flw fa5, 112(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 224(sp) +; RV64-i64-NEXT: flw fa5, 108(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 216(sp) +; RV64-i64-NEXT: flw fa5, 104(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 208(sp) +; RV64-i64-NEXT: flw fa5, 100(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 200(sp) +; RV64-i64-NEXT: flw fa5, 96(sp) +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 192(sp) +; RV64-i64-NEXT: vfmv.f.s fa5, v8 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 128(sp) +; RV64-i64-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64-i64-NEXT: vslidedown.vi v10, v8, 3 +; RV64-i64-NEXT: vfmv.f.s fa5, v10 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 152(sp) +; RV64-i64-NEXT: vslidedown.vi v10, v8, 2 +; RV64-i64-NEXT: vfmv.f.s fa5, v10 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 144(sp) +; RV64-i64-NEXT: vslidedown.vi v10, v8, 1 +; RV64-i64-NEXT: vfmv.f.s fa5, v10 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 136(sp) +; RV64-i64-NEXT: vsetivli zero, 1, e32, m2, ta, ma +; RV64-i64-NEXT: vslidedown.vi v10, v8, 7 +; RV64-i64-NEXT: vfmv.f.s fa5, v10 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 184(sp) +; RV64-i64-NEXT: vslidedown.vi v10, v8, 6 +; RV64-i64-NEXT: vfmv.f.s fa5, v10 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 176(sp) +; RV64-i64-NEXT: vslidedown.vi v10, v8, 5 +; RV64-i64-NEXT: vfmv.f.s fa5, v10 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 168(sp) +; RV64-i64-NEXT: vslidedown.vi v8, v8, 4 +; RV64-i64-NEXT: vfmv.f.s fa5, v8 +; RV64-i64-NEXT: fcvt.l.s a0, fa5 +; RV64-i64-NEXT: sd a0, 160(sp) +; RV64-i64-NEXT: addi a0, sp, 128 +; RV64-i64-NEXT: vsetivli zero, 16, e64, m8, ta, ma +; RV64-i64-NEXT: vle64.v v8, (a0) +; RV64-i64-NEXT: addi sp, s0, -384 +; RV64-i64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; RV64-i64-NEXT: ld s0, 368(sp) # 8-byte Folded Reload +; RV64-i64-NEXT: addi sp, sp, 384 +; RV64-i64-NEXT: ret %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f32(<16 x float> %x) ret <16 x iXLen> %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll index e75ea700df4f..a9668dff6055 100644 --- a/llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/lrint-sdnode.ll @@ -102,7 +102,26 @@ define @lrint_nxv8f32( %x) { } declare @llvm.lrint.nxv8iXLen.nxv8f32() -define @lrint_nxv16iXLen_nxv16f32( %x) { +define @lrint_nxv16f32( %x) { +; RV32-LABEL: lrint_nxv16f32: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, ma +; RV32-NEXT: vfcvt.x.f.v v8, v8 +; RV32-NEXT: ret +; +; RV64-i32-LABEL: lrint_nxv16f32: +; RV64-i32: # %bb.0: +; RV64-i32-NEXT: vsetvli a0, zero, e32, m8, ta, ma +; RV64-i32-NEXT: vfcvt.x.f.v v8, v8 +; RV64-i32-NEXT: ret +; +; RV64-i64-LABEL: lrint_nxv16f32: +; RV64-i64: # %bb.0: +; RV64-i64-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8 +; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12 +; RV64-i64-NEXT: vmv8r.v v8, v24 +; RV64-i64-NEXT: ret %a = call @llvm.lrint.nxv16iXLen.nxv16f32( %x) ret %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll index 8a826fb3ac1e..9fa8807ed4ad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/lrint-vp.ll @@ -102,7 +102,41 @@ define @lrint_nxv8f32( %x, @llvm.vp.lrint.nxv8iXLen.nxv8f32(, , i32) -define @lrint_nxv16iXLen_nxv16f32( %x, %m, i32 zeroext %evl) { +define @lrint_nxv16f32( %x, %m, i32 zeroext %evl) { +; RV32-LABEL: lrint_nxv16f32: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t +; RV32-NEXT: ret +; +; RV64-i32-LABEL: lrint_nxv16f32: +; RV64-i32: # %bb.0: +; RV64-i32-NEXT: vsetvli zero, a0, e32, m8, ta, ma +; RV64-i32-NEXT: vfcvt.x.f.v v8, v8, v0.t +; RV64-i32-NEXT: ret +; +; RV64-i64-LABEL: lrint_nxv16f32: +; RV64-i64: # %bb.0: +; RV64-i64-NEXT: vmv1r.v v24, v0 +; RV64-i64-NEXT: csrr a1, vlenb +; RV64-i64-NEXT: srli a2, a1, 3 +; RV64-i64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma +; RV64-i64-NEXT: vslidedown.vx v0, v0, a2 +; RV64-i64-NEXT: sub a2, a0, a1 +; RV64-i64-NEXT: sltu a3, a0, a2 +; RV64-i64-NEXT: addi a3, a3, -1 +; RV64-i64-NEXT: and a2, a3, a2 +; RV64-i64-NEXT: vsetvli zero, a2, e32, m4, ta, ma +; RV64-i64-NEXT: vfwcvt.x.f.v v16, v12, v0.t +; RV64-i64-NEXT: bltu a0, a1, .LBB4_2 +; RV64-i64-NEXT: # %bb.1: +; RV64-i64-NEXT: mv a0, a1 +; RV64-i64-NEXT: .LBB4_2: +; RV64-i64-NEXT: vsetvli zero, a0, e32, m4, ta, ma +; RV64-i64-NEXT: vmv1r.v v0, v24 +; RV64-i64-NEXT: vfwcvt.x.f.v v24, v8, v0.t +; RV64-i64-NEXT: vmv8r.v v8, v24 +; RV64-i64-NEXT: ret %a = call @llvm.vp.lrint.nxv16iXLen.nxv16f32( %x, %m, i32 %evl) ret %a } -- GitLab From 472ea6e0159342107ca240018b0c5ad868bf16fe Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Apr 2024 15:54:30 -0700 Subject: [PATCH 211/695] [RISCV] Resolve CHECK prefix conflict in fixed-vectors-vitofp-constrained-sdnode.ll. NFC --- ...fixed-vectors-vitofp-constrained-sdnode.ll | 31 +++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll index b19c30df5511..3dec7daf66ac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ -; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ -; RUN: -verify-machineinstrs < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 declare <1 x half> @llvm.experimental.constrained.sitofp.v1f16.v1i1(<1 x i1>, metadata, metadata) define <1 x half> @vsitofp_v1i1_v1f16(<1 x i1> %va) strictfp { @@ -410,6 +410,33 @@ define <1 x half> @vsitofp_v1i8_v1f16(<1 x i8> %va) strictfp { declare <1 x half> @llvm.experimental.constrained.sitofp.v1f16.v1i7(<1 x i7>, metadata, metadata) define <1 x half> @vsitofp_v1i7_v1f16(<1 x i7> %va) strictfp { +; RV32-LABEL: vsitofp_v1i7_v1f16: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: slli a0, a0, 25 +; RV32-NEXT: srai a0, a0, 25 +; RV32-NEXT: fcvt.h.w fa5, a0 +; RV32-NEXT: fsh fa5, 14(sp) +; RV32-NEXT: addi a0, sp, 14 +; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; RV32-NEXT: vle16.v v8, (a0) +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vsitofp_v1i7_v1f16: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -16 +; RV64-NEXT: .cfi_def_cfa_offset 16 +; RV64-NEXT: slli a0, a0, 57 +; RV64-NEXT: srai a0, a0, 57 +; RV64-NEXT: fcvt.h.w fa5, a0 +; RV64-NEXT: fsh fa5, 14(sp) +; RV64-NEXT: addi a0, sp, 14 +; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma +; RV64-NEXT: vle16.v v8, (a0) +; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: ret %evec = call <1 x half> @llvm.experimental.constrained.sitofp.v1f16.v1i7(<1 x i7> %va, metadata !"round.dynamic", metadata !"fpexcept.strict") ret <1 x half> %evec } -- GitLab From 4e98adf677fe6eb9aea5606c44ccc97f02d2f48a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Apr 2024 15:10:05 -0700 Subject: [PATCH 212/695] [RISCV] Add tests for F/D with non-FP ABI to interrupt-attr.ll. NFC Without a floating point aware ABI for callees, an interrupt handler needs to save all floating point registers even normally callee saved. We are currently unnecessarily saving callee saved FP registers when a floating point ABI is used by the callee. This is different than gcc as noted in this discourse post https://discourse.llvm.org/t/has-bugs-when-optimizing-save-restore-csrs-by-changing-csr-xlen-f32-interrupt/78200/1 --- llvm/test/CodeGen/RISCV/interrupt-attr.ll | 1268 +++++++++++++++++++++ 1 file changed, 1268 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr.ll b/llvm/test/CodeGen/RISCV/interrupt-attr.ll index e22720d6b3e2..50c789f8f86d 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr.ll @@ -6,6 +6,13 @@ ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD ; +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -target-abi ilp32 -o - %s \ +; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-F-ILP3 +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -target-abi ilp32f -o - %s \ +; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD-ILP32F +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -target-abi ilp32 -o - %s \ +; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD-ILP32 + ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+i -target-abi ilp32e -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV32I-ILP32E ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+e -o - %s \ @@ -19,6 +26,13 @@ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD + +; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f -target-abi=lp64 -o - %s \ +; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F-LP64 +; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -target-abi=lp64f -o - %s \ +; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD-LP64F +; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -target-abi=lp64 -o - %s \ +; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD-LP64 ; ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+i -target-abi lp64e -o - %s \ ; RUN: 2>&1 | FileCheck %s -check-prefixes=CHECK,CHECK-RV64I-LP64E @@ -305,6 +319,315 @@ define void @foo_with_call() #1 { ; CHECK-RV32-FD-NEXT: addi sp, sp, 320 ; CHECK-RV32-FD-NEXT: mret ; +; CHECK-RV32-F-ILP3-LABEL: foo_with_call: +; CHECK-RV32-F-ILP3: # %bb.0: +; CHECK-RV32-F-ILP3-NEXT: addi sp, sp, -192 +; CHECK-RV32-F-ILP3-NEXT: sw ra, 188(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t0, 184(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t1, 180(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t2, 176(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a0, 172(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a1, 168(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a2, 164(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a3, 160(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a4, 156(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a5, 152(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a6, 148(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a7, 144(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t3, 140(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t4, 136(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t5, 132(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t6, 128(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs0, 92(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs1, 88(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa1, 80(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa2, 76(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa3, 72(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa4, 68(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa6, 60(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa7, 56(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs2, 52(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs3, 48(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs4, 44(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs5, 40(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs6, 36(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs7, 32(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs8, 28(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs9, 24(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs10, 20(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs11, 16(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft8, 12(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft11, 0(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: call otherfoo +; CHECK-RV32-F-ILP3-NEXT: lw ra, 188(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t0, 184(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t1, 180(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t2, 176(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a0, 172(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a1, 168(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a2, 164(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a3, 160(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a4, 156(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a5, 152(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a6, 148(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a7, 144(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t3, 140(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t4, 136(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t5, 132(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t6, 128(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs0, 92(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs1, 88(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa1, 80(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa2, 76(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa3, 72(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa4, 68(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa6, 60(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa7, 56(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs2, 52(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs3, 48(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs4, 44(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs5, 40(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs6, 36(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs7, 32(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs8, 28(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs9, 24(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs10, 20(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs11, 16(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft8, 12(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft9, 8(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft10, 4(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft11, 0(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: addi sp, sp, 192 +; CHECK-RV32-F-ILP3-NEXT: mret +; +; CHECK-RV32-FD-ILP32F-LABEL: foo_with_call: +; CHECK-RV32-FD-ILP32F: # %bb.0: +; CHECK-RV32-FD-ILP32F-NEXT: addi sp, sp, -320 +; CHECK-RV32-FD-ILP32F-NEXT: sw ra, 316(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t0, 312(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t1, 308(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t2, 304(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a0, 300(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a1, 296(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a2, 292(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a3, 288(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a4, 284(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a5, 280(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a6, 276(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a7, 272(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t3, 268(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t4, 264(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t5, 260(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t6, 256(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs0, 184(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs1, 176(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa1, 160(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa2, 152(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa3, 144(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa4, 136(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa6, 120(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa7, 112(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs2, 104(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs3, 96(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs4, 88(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs5, 80(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs6, 72(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs7, 64(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs8, 56(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs9, 48(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs10, 40(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs11, 32(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft8, 24(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: call otherfoo +; CHECK-RV32-FD-ILP32F-NEXT: lw ra, 316(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t0, 312(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t1, 308(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t2, 304(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a0, 300(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a1, 296(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a2, 292(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a3, 288(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a4, 284(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a5, 280(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a6, 276(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a7, 272(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t3, 268(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t4, 264(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t5, 260(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t6, 256(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs0, 184(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs1, 176(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa1, 160(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa2, 152(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa3, 144(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa4, 136(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa6, 120(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa7, 112(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs2, 104(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs3, 96(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs4, 88(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs5, 80(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs6, 72(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs7, 64(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs8, 56(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs9, 48(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs10, 40(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs11, 32(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft8, 24(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft9, 16(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft10, 8(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft11, 0(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: addi sp, sp, 320 +; CHECK-RV32-FD-ILP32F-NEXT: mret +; +; CHECK-RV32-FD-ILP32-LABEL: foo_with_call: +; CHECK-RV32-FD-ILP32: # %bb.0: +; CHECK-RV32-FD-ILP32-NEXT: addi sp, sp, -320 +; CHECK-RV32-FD-ILP32-NEXT: sw ra, 316(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t0, 312(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t1, 308(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t2, 304(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a0, 300(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a1, 296(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a2, 292(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a3, 288(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a4, 284(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a5, 280(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a6, 276(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a7, 272(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t3, 268(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t4, 264(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t5, 260(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t6, 256(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs0, 184(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs1, 176(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa1, 160(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa2, 152(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa3, 144(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa4, 136(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa6, 120(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa7, 112(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs2, 104(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs3, 96(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs4, 88(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs5, 80(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs6, 72(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs7, 64(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs8, 56(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs9, 48(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs10, 40(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs11, 32(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft8, 24(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: call otherfoo +; CHECK-RV32-FD-ILP32-NEXT: lw ra, 316(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t0, 312(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t1, 308(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t2, 304(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a0, 300(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a1, 296(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a2, 292(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a3, 288(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a4, 284(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a5, 280(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a6, 276(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a7, 272(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t3, 268(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t4, 264(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t5, 260(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t6, 256(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs0, 184(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs1, 176(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa1, 160(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa2, 152(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa3, 144(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa4, 136(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa6, 120(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa7, 112(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs2, 104(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs3, 96(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs4, 88(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs5, 80(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs6, 72(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs7, 64(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs8, 56(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs9, 48(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs10, 40(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs11, 32(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft8, 24(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft9, 16(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft10, 8(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft11, 0(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: addi sp, sp, 320 +; CHECK-RV32-FD-ILP32-NEXT: mret +; ; CHECK-RV32I-ILP32E-LABEL: foo_with_call: ; CHECK-RV32I-ILP32E: # %bb.0: ; CHECK-RV32I-ILP32E-NEXT: addi sp, sp, -104 @@ -727,6 +1050,315 @@ define void @foo_with_call() #1 { ; CHECK-RV64-FD-NEXT: addi sp, sp, 384 ; CHECK-RV64-FD-NEXT: mret ; +; CHECK-RV64-F-LP64-LABEL: foo_with_call: +; CHECK-RV64-F-LP64: # %bb.0: +; CHECK-RV64-F-LP64-NEXT: addi sp, sp, -256 +; CHECK-RV64-F-LP64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t0, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t1, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t2, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a0, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a1, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a2, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a3, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a4, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a5, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a6, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a7, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t3, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t4, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t5, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t6, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs0, 92(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs1, 88(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa1, 80(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa2, 76(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa3, 72(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa4, 68(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa6, 60(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa7, 56(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs2, 52(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs3, 48(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs4, 44(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs5, 40(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs6, 36(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs7, 32(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs8, 28(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs9, 24(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs10, 20(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs11, 16(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft8, 12(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft11, 0(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: call otherfoo +; CHECK-RV64-F-LP64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t0, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t1, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t2, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a0, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a1, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a2, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a3, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a4, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a5, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a6, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a7, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t3, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t4, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t5, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t6, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs0, 92(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs1, 88(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa1, 80(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa2, 76(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa3, 72(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa4, 68(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa6, 60(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa7, 56(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs2, 52(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs3, 48(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs4, 44(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs5, 40(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs6, 36(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs7, 32(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs8, 28(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs9, 24(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs10, 20(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs11, 16(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft8, 12(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft9, 8(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft10, 4(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft11, 0(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: addi sp, sp, 256 +; CHECK-RV64-F-LP64-NEXT: mret +; +; CHECK-RV64-FD-LP64F-LABEL: foo_with_call: +; CHECK-RV64-FD-LP64F: # %bb.0: +; CHECK-RV64-FD-LP64F-NEXT: addi sp, sp, -384 +; CHECK-RV64-FD-LP64F-NEXT: sd ra, 376(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t0, 368(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t1, 360(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t2, 352(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a0, 344(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a1, 336(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a2, 328(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a3, 320(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a4, 312(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a5, 304(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a6, 296(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a7, 288(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t3, 280(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t4, 272(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t5, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t6, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs0, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs1, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa1, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa2, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa3, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa4, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa6, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa7, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs2, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs3, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs4, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs5, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs6, 72(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs7, 64(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs8, 56(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs9, 48(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs10, 40(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs11, 32(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft8, 24(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: call otherfoo +; CHECK-RV64-FD-LP64F-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t0, 368(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t1, 360(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t2, 352(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a0, 344(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a1, 336(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a2, 328(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a3, 320(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a4, 312(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a5, 304(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a6, 296(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a7, 288(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t3, 280(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t4, 272(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t5, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t6, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs0, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs1, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa1, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa2, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa3, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa4, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa6, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa7, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs2, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs3, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs4, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs5, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs6, 72(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs7, 64(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs8, 56(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs9, 48(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs10, 40(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs11, 32(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft8, 24(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft9, 16(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft10, 8(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft11, 0(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: addi sp, sp, 384 +; CHECK-RV64-FD-LP64F-NEXT: mret +; +; CHECK-RV64-FD-LP64-LABEL: foo_with_call: +; CHECK-RV64-FD-LP64: # %bb.0: +; CHECK-RV64-FD-LP64-NEXT: addi sp, sp, -384 +; CHECK-RV64-FD-LP64-NEXT: sd ra, 376(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t0, 368(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t1, 360(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t2, 352(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a0, 344(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a1, 336(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a2, 328(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a3, 320(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a4, 312(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a5, 304(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a6, 296(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a7, 288(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t3, 280(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t4, 272(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t5, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t6, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs0, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs1, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa1, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa2, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa3, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa4, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa6, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa7, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs2, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs3, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs4, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs5, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs6, 72(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs7, 64(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs8, 56(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs9, 48(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs10, 40(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs11, 32(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft8, 24(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: call otherfoo +; CHECK-RV64-FD-LP64-NEXT: ld ra, 376(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t0, 368(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t1, 360(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t2, 352(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a0, 344(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a1, 336(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a2, 328(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a3, 320(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a4, 312(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a5, 304(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a6, 296(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a7, 288(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t3, 280(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t4, 272(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t5, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t6, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs0, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs1, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa1, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa2, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa3, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa4, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa6, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa7, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs2, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs3, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs4, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs5, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs6, 72(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs7, 64(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs8, 56(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs9, 48(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs10, 40(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs11, 32(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft8, 24(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft9, 16(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft10, 8(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft11, 0(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: addi sp, sp, 384 +; CHECK-RV64-FD-LP64-NEXT: mret +; ; CHECK-RV64I-LP64E-LABEL: foo_with_call: ; CHECK-RV64I-LP64E: # %bb.0: ; CHECK-RV64I-LP64E-NEXT: addi sp, sp, -208 @@ -1289,6 +1921,324 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV32-FD-NEXT: addi sp, sp, 336 ; CHECK-RV32-FD-NEXT: mret ; +; CHECK-RV32-F-ILP3-LABEL: foo_fp_with_call: +; CHECK-RV32-F-ILP3: # %bb.0: +; CHECK-RV32-F-ILP3-NEXT: addi sp, sp, -208 +; CHECK-RV32-F-ILP3-NEXT: sw ra, 204(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t0, 200(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t1, 196(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t2, 192(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw s0, 188(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a0, 184(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a1, 180(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a2, 176(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a3, 172(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a4, 168(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a5, 164(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a6, 160(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw a7, 156(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t3, 152(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t4, 148(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t5, 144(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: sw t6, 140(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft0, 136(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft1, 132(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft2, 128(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft3, 124(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft4, 120(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft5, 116(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs0, 104(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs1, 100(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa1, 92(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa2, 88(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa3, 84(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa4, 80(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa6, 72(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fa7, 68(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs2, 64(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs3, 60(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs4, 56(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs5, 52(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs6, 48(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs7, 44(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs8, 40(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs9, 36(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs10, 32(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw fs11, 28(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft8, 24(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft9, 20(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft10, 16(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: fsw ft11, 12(sp) # 4-byte Folded Spill +; CHECK-RV32-F-ILP3-NEXT: addi s0, sp, 208 +; CHECK-RV32-F-ILP3-NEXT: call otherfoo +; CHECK-RV32-F-ILP3-NEXT: lw ra, 204(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t0, 200(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t1, 196(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t2, 192(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw s0, 188(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a0, 184(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a1, 180(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a2, 176(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a3, 172(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a4, 168(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a5, 164(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a6, 160(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw a7, 156(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t3, 152(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t4, 148(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t5, 144(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: lw t6, 140(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft0, 136(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft1, 132(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft2, 128(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft3, 124(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft4, 120(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft5, 116(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs0, 104(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs1, 100(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa1, 92(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa2, 88(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa3, 84(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa4, 80(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa6, 72(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fa7, 68(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs2, 64(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs3, 60(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs4, 56(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs5, 52(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs6, 48(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs7, 44(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs8, 40(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs9, 36(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs10, 32(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw fs11, 28(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft8, 24(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft9, 20(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft10, 16(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: flw ft11, 12(sp) # 4-byte Folded Reload +; CHECK-RV32-F-ILP3-NEXT: addi sp, sp, 208 +; CHECK-RV32-F-ILP3-NEXT: mret +; +; CHECK-RV32-FD-ILP32F-LABEL: foo_fp_with_call: +; CHECK-RV32-FD-ILP32F: # %bb.0: +; CHECK-RV32-FD-ILP32F-NEXT: addi sp, sp, -336 +; CHECK-RV32-FD-ILP32F-NEXT: sw ra, 332(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t0, 328(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t1, 324(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t2, 320(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw s0, 316(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a0, 312(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a1, 308(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a2, 304(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a3, 300(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a4, 296(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a5, 292(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a6, 288(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw a7, 284(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t3, 280(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t4, 276(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t5, 272(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: sw t6, 268(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs0, 192(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs1, 184(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa1, 168(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa2, 160(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa3, 152(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa4, 144(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa6, 128(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fa7, 120(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs2, 112(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs3, 104(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs4, 96(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs5, 88(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs6, 80(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs7, 72(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs8, 64(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs9, 56(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs10, 48(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd fs11, 40(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft8, 32(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft9, 24(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32F-NEXT: addi s0, sp, 336 +; CHECK-RV32-FD-ILP32F-NEXT: call otherfoo +; CHECK-RV32-FD-ILP32F-NEXT: lw ra, 332(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t0, 328(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t1, 324(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t2, 320(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw s0, 316(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a0, 312(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a1, 308(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a2, 304(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a3, 300(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a4, 296(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a5, 292(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a6, 288(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw a7, 284(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t3, 280(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t4, 276(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t5, 272(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: lw t6, 268(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs0, 192(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs1, 184(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa1, 168(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa2, 160(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa3, 152(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa4, 144(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa6, 128(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fa7, 120(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs2, 112(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs3, 104(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs4, 96(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs5, 88(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs6, 80(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs7, 72(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs8, 64(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs9, 56(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs10, 48(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld fs11, 40(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft8, 32(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft9, 24(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft10, 16(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: fld ft11, 8(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32F-NEXT: addi sp, sp, 336 +; CHECK-RV32-FD-ILP32F-NEXT: mret +; +; CHECK-RV32-FD-ILP32-LABEL: foo_fp_with_call: +; CHECK-RV32-FD-ILP32: # %bb.0: +; CHECK-RV32-FD-ILP32-NEXT: addi sp, sp, -336 +; CHECK-RV32-FD-ILP32-NEXT: sw ra, 332(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t0, 328(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t1, 324(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t2, 320(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw s0, 316(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a0, 312(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a1, 308(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a2, 304(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a3, 300(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a4, 296(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a5, 292(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a6, 288(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw a7, 284(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t3, 280(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t4, 276(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t5, 272(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: sw t6, 268(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs0, 192(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs1, 184(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa1, 168(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa2, 160(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa3, 152(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa4, 144(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa6, 128(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fa7, 120(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs2, 112(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs3, 104(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs4, 96(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs5, 88(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs6, 80(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs7, 72(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs8, 64(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs9, 56(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs10, 48(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd fs11, 40(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft8, 32(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft9, 24(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-ILP32-NEXT: addi s0, sp, 336 +; CHECK-RV32-FD-ILP32-NEXT: call otherfoo +; CHECK-RV32-FD-ILP32-NEXT: lw ra, 332(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t0, 328(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t1, 324(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t2, 320(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw s0, 316(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a0, 312(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a1, 308(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a2, 304(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a3, 300(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a4, 296(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a5, 292(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a6, 288(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw a7, 284(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t3, 280(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t4, 276(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t5, 272(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: lw t6, 268(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs0, 192(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs1, 184(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa1, 168(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa2, 160(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa3, 152(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa4, 144(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa6, 128(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fa7, 120(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs2, 112(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs3, 104(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs4, 96(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs5, 88(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs6, 80(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs7, 72(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs8, 64(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs9, 56(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs10, 48(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld fs11, 40(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft8, 32(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft9, 24(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft10, 16(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: fld ft11, 8(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-ILP32-NEXT: addi sp, sp, 336 +; CHECK-RV32-FD-ILP32-NEXT: mret +; ; CHECK-RV32I-ILP32E-LABEL: foo_fp_with_call: ; CHECK-RV32I-ILP32E: # %bb.0: ; CHECK-RV32I-ILP32E-NEXT: addi sp, sp, -108 @@ -1729,6 +2679,324 @@ define void @foo_fp_with_call() #2 { ; CHECK-RV64-FD-NEXT: addi sp, sp, 400 ; CHECK-RV64-FD-NEXT: mret ; +; CHECK-RV64-F-LP64-LABEL: foo_fp_with_call: +; CHECK-RV64-F-LP64: # %bb.0: +; CHECK-RV64-F-LP64-NEXT: addi sp, sp, -272 +; CHECK-RV64-F-LP64-NEXT: sd ra, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t0, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t1, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t2, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd s0, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a0, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a1, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a2, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a3, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a4, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a5, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a6, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd a7, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t3, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t4, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t5, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: sd t6, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft1, 128(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft2, 124(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft3, 120(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft4, 116(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft5, 112(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft6, 108(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft7, 104(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs0, 100(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs1, 96(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa1, 88(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa2, 84(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa3, 80(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa4, 76(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa6, 68(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fa7, 64(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs2, 60(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs3, 56(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs4, 52(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs5, 48(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs6, 44(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs7, 40(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs8, 36(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs9, 32(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs10, 28(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw fs11, 24(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft8, 20(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft9, 16(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft10, 12(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: fsw ft11, 8(sp) # 4-byte Folded Spill +; CHECK-RV64-F-LP64-NEXT: addi s0, sp, 272 +; CHECK-RV64-F-LP64-NEXT: call otherfoo +; CHECK-RV64-F-LP64-NEXT: ld ra, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t0, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t1, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t2, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld s0, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a0, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a1, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a2, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a3, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a4, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a5, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a6, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld a7, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t3, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t4, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t5, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: ld t6, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft1, 128(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft2, 124(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft3, 120(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft4, 116(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft5, 112(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft6, 108(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft7, 104(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs0, 100(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs1, 96(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa1, 88(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa2, 84(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa3, 80(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa4, 76(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa6, 68(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fa7, 64(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs2, 60(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs3, 56(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs4, 52(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs5, 48(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs6, 44(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs7, 40(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs8, 36(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs9, 32(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs10, 28(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw fs11, 24(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft8, 20(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft9, 16(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft10, 12(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: flw ft11, 8(sp) # 4-byte Folded Reload +; CHECK-RV64-F-LP64-NEXT: addi sp, sp, 272 +; CHECK-RV64-F-LP64-NEXT: mret +; +; CHECK-RV64-FD-LP64F-LABEL: foo_fp_with_call: +; CHECK-RV64-FD-LP64F: # %bb.0: +; CHECK-RV64-FD-LP64F-NEXT: addi sp, sp, -400 +; CHECK-RV64-FD-LP64F-NEXT: sd ra, 392(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t0, 384(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t1, 376(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t2, 368(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd s0, 360(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a0, 352(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a1, 344(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a2, 336(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a3, 328(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a4, 320(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a5, 312(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a6, 304(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd a7, 296(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t3, 288(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t4, 280(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t5, 272(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: sd t6, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs0, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs1, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa1, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa2, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa3, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa4, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa6, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fa7, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs2, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs3, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs4, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs5, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs6, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs7, 72(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs8, 64(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs9, 56(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs10, 48(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd fs11, 40(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft8, 32(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft9, 24(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64F-NEXT: addi s0, sp, 400 +; CHECK-RV64-FD-LP64F-NEXT: call otherfoo +; CHECK-RV64-FD-LP64F-NEXT: ld ra, 392(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t0, 384(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t1, 376(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t2, 368(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld s0, 360(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a0, 352(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a1, 344(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a2, 336(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a3, 328(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a4, 320(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a5, 312(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a6, 304(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld a7, 296(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t3, 288(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t4, 280(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t5, 272(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: ld t6, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs0, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs1, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa1, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa2, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa3, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa4, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa6, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fa7, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs2, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs3, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs4, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs5, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs6, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs7, 72(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs8, 64(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs9, 56(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs10, 48(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld fs11, 40(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft8, 32(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft9, 24(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft10, 16(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: fld ft11, 8(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64F-NEXT: addi sp, sp, 400 +; CHECK-RV64-FD-LP64F-NEXT: mret +; +; CHECK-RV64-FD-LP64-LABEL: foo_fp_with_call: +; CHECK-RV64-FD-LP64: # %bb.0: +; CHECK-RV64-FD-LP64-NEXT: addi sp, sp, -400 +; CHECK-RV64-FD-LP64-NEXT: sd ra, 392(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t0, 384(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t1, 376(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t2, 368(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd s0, 360(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a0, 352(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a1, 344(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a2, 336(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a3, 328(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a4, 320(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a5, 312(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a6, 304(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd a7, 296(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t3, 288(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t4, 280(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t5, 272(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: sd t6, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs0, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs1, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa1, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa2, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa3, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa4, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa6, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fa7, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs2, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs3, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs4, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs5, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs6, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs7, 72(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs8, 64(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs9, 56(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs10, 48(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd fs11, 40(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft8, 32(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft9, 24(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-LP64-NEXT: addi s0, sp, 400 +; CHECK-RV64-FD-LP64-NEXT: call otherfoo +; CHECK-RV64-FD-LP64-NEXT: ld ra, 392(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t0, 384(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t1, 376(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t2, 368(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld s0, 360(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a0, 352(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a1, 344(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a2, 336(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a3, 328(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a4, 320(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a5, 312(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a6, 304(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld a7, 296(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t3, 288(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t4, 280(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t5, 272(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: ld t6, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs0, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs1, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa1, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa2, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa3, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa4, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa6, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fa7, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs2, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs3, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs4, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs5, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs6, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs7, 72(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs8, 64(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs9, 56(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs10, 48(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld fs11, 40(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft8, 32(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft9, 24(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft10, 16(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: fld ft11, 8(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-LP64-NEXT: addi sp, sp, 400 +; CHECK-RV64-FD-LP64-NEXT: mret +; ; CHECK-RV64I-LP64E-LABEL: foo_fp_with_call: ; CHECK-RV64I-LP64E: # %bb.0: ; CHECK-RV64I-LP64E-NEXT: addi sp, sp, -216 -- GitLab From 79343fa8c3575be12ec4d543f4aebebd1ba4f47f Mon Sep 17 00:00:00 2001 From: Evgenii Stepanov Date: Mon, 8 Apr 2024 16:14:39 -0700 Subject: [PATCH 213/695] [msan] Precommit tests. Precommit tests for overflowing and saturating arithmetic intrinsics. --- .../MemorySanitizer/overflow.ll | 163 ++++++++++++++++++ .../MemorySanitizer/saturating.ll | 113 ++++++++++++ 2 files changed, 276 insertions(+) create mode 100644 llvm/test/Instrumentation/MemorySanitizer/overflow.ll create mode 100644 llvm/test/Instrumentation/MemorySanitizer/saturating.ll diff --git a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll new file mode 100644 index 000000000000..b1304faec3df --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll @@ -0,0 +1,163 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_sadd_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} + +define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_uadd_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} + +define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_smul_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} +define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_umul_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} +define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_ssub_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} +define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_usub_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} + +define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32> %b) #0 { +; CHECK-LABEL: define { <4 x i32>, <4 x i1> } @test_sadd_with_overflow_vec( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] +; CHECK: 5: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 6: +; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] +; + %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) + ret { <4 x i32>, <4 x i1> } %res +} + +attributes #0 = { sanitize_memory } +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} +;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll new file mode 100644 index 000000000000..dcd8a080144b --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll @@ -0,0 +1,113 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @test_sadd_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_sadd_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.sadd.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_uadd_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_uadd_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.uadd.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_ssub_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_ssub_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.ssub.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_usub_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_usub_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.usub.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_sshl_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_sshl_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.sshl.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_ushl_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_ushl_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.ushl.sat(i64 %a, i64 %b) + ret i64 %res +} + +define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 { +; CHECK-LABEL: define <4 x i32> @test_sadd_sat_vec( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + + +attributes #0 = { sanitize_memory } -- GitLab From 22b1f1bc695b8fd3263b709ce9761bf3bb2f8ee9 Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Mon, 8 Apr 2024 19:26:12 -0400 Subject: [PATCH 214/695] [libc] Remove `#ifdef __cplusplus` part from `include/llvm-libc-macros/math-macros.h`. (#87864) Now with the proxy header `hdr/math_macros.h`, the header `include/llvm-libc-macros/math-macros.h` will not be included in overlay mode, and the extra definitions for `__cplusplus` mode is not needed any more. --- libc/include/llvm-libc-macros/math-macros.h | 24 --------------------- 1 file changed, 24 deletions(-) diff --git a/libc/include/llvm-libc-macros/math-macros.h b/libc/include/llvm-libc-macros/math-macros.h index 1cbd1665d0cd..47838969d59a 100644 --- a/libc/include/llvm-libc-macros/math-macros.h +++ b/libc/include/llvm-libc-macros/math-macros.h @@ -51,33 +51,9 @@ #define math_errhandling (MATH_ERRNO | MATH_ERREXCEPT) #endif -// These must be type-generic functions. The C standard specifies them as -// being macros rather than functions, in fact. However, in C++ it's important -// that there be function declarations that don't interfere with other uses of -// the identifier, even in places with parentheses where a function-like macro -// will be expanded (such as a function declaration in a C++ namespace). - // TODO: Move generic functional math macros to a separate header file. -#ifdef __cplusplus - -template inline constexpr bool isfinite(T x) { - return __builtin_isfinite(x); -} - -template inline constexpr bool isinf(T x) { - return __builtin_isinf(x); -} - -template inline constexpr bool isnan(T x) { - return __builtin_isnan(x); -} - -#else - #define isfinite(x) __builtin_isfinite(x) #define isinf(x) __builtin_isinf(x) #define isnan(x) __builtin_isnan(x) -#endif - #endif // LLVM_LIBC_MACROS_MATH_MACROS_H -- GitLab From 118a5d8236d8a483dd401fa35c8b1fcd058eacc1 Mon Sep 17 00:00:00 2001 From: Evgenii Stepanov Date: Mon, 8 Apr 2024 16:33:45 -0700 Subject: [PATCH 215/695] Overflow and saturating intrinsics (#88068) --- .../Instrumentation/MemorySanitizer.cpp | 29 +++++ .../MemorySanitizer/overflow.ll | 103 ++++++------------ .../MemorySanitizer/saturating.ll | 21 ++-- 3 files changed, 78 insertions(+), 75 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 46b9181c8922..b92d358b4aa1 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -3715,8 +3715,37 @@ struct MemorySanitizerVisitor : public InstVisitor { setOrigin(&I, getOrigin(&I, 0)); } + void handleArithmeticWithOverflow(IntrinsicInst &I) { + IRBuilder<> IRB(&I); + Value *Shadow0 = IRB.CreateOr(getShadow(&I, 0), getShadow(&I, 1)); + Value *Shadow1 = IRB.CreateICmpNE(Shadow0, getCleanShadow(Shadow0)); + + Value *Shadow = PoisonValue::get(getShadowTy(&I)); + Shadow = IRB.CreateInsertValue(Shadow, Shadow0, 0); + Shadow = IRB.CreateInsertValue(Shadow, Shadow1, 1); + + setShadow(&I, Shadow); + setOriginForNaryOp(I); + } + void visitIntrinsicInst(IntrinsicInst &I) { switch (I.getIntrinsicID()) { + case Intrinsic::uadd_with_overflow: + case Intrinsic::sadd_with_overflow: + case Intrinsic::usub_with_overflow: + case Intrinsic::ssub_with_overflow: + case Intrinsic::umul_with_overflow: + case Intrinsic::smul_with_overflow: + handleArithmeticWithOverflow(I); + break; + case Intrinsic::sadd_sat: + case Intrinsic::uadd_sat: + case Intrinsic::ssub_sat: + case Intrinsic::usub_sat: + case Intrinsic::sshl_sat: + case Intrinsic::ushl_sat: + handleShadowOr(I); + break; case Intrinsic::abs: handleAbsIntrinsic(I); break; diff --git a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll index b1304faec3df..0cfae0008263 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll @@ -10,16 +10,12 @@ define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) @@ -32,16 +28,12 @@ define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) @@ -54,16 +46,12 @@ define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) @@ -75,16 +63,12 @@ define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) @@ -96,16 +80,12 @@ define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) @@ -117,16 +97,12 @@ define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) @@ -139,18 +115,12 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] -; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 6: +; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { <4 x i32>, <4 x i1> } poison, <4 x i32> [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { <4 x i32>, <4 x i1> } [[TMP5]], <4 x i1> [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { <4 x i32>, <4 x i1> } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] ; %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) @@ -158,6 +128,3 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32 } attributes #0 = { sanitize_memory } -;. -; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} -;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll index dcd8a080144b..b707b3160d9e 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll @@ -11,8 +11,9 @@ define i64 @test_sadd_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.sadd.sat(i64 %a, i64 %b) @@ -26,8 +27,9 @@ define i64 @test_uadd_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.uadd.sat(i64 %a, i64 %b) @@ -41,8 +43,9 @@ define i64 @test_ssub_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.ssub.sat(i64 %a, i64 %b) @@ -56,8 +59,9 @@ define i64 @test_usub_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.usub.sat(i64 %a, i64 %b) @@ -71,8 +75,9 @@ define i64 @test_sshl_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.sshl.sat(i64 %a, i64 %b) @@ -86,8 +91,9 @@ define i64 @test_ushl_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.ushl.sat(i64 %a, i64 %b) @@ -101,8 +107,9 @@ define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b) -- GitLab From f28c8339c12917b11c99432de6609e7d46e17e2b Mon Sep 17 00:00:00 2001 From: Chris Apple Date: Mon, 8 Apr 2024 16:34:30 -0700 Subject: [PATCH 216/695] Fix issue where MACOSX_VERSION_MIN_FLAG was not set on subsequent runs of CMake in compiler-rt (#87580) As discussed here: https://github.com/llvm/llvm-project/pull/74394#issuecomment-2035264683 An unintentional change of behavior was introduced in #74394 This code introduced in #74394 : The first time through * SANITIZER_MIN_OSX_VERSION is not set * parse -mmacosx-version-min and set MACOSX_VERSION_MIN_FLAG * Set and cache SANITIZER_MIN_OSX_VERSION Subsequent times through: * SANITIZER_MIN_OSX_VERSION is cached * (BUG!!) you don't parse -mmacosx-version-min, and don't set MACOSX_VERSION_MIN_FLAG MACOSX_VERSION_MIN_FLAG is used later in the file on this line: https://github.com/llvm/llvm-project/blob/63c925ca808f216f805b76873743450456e350f2/compiler-rt/cmake/config-ix.cmake#L517 Hoisting this assignment outside the if block returns us to the previous behavior before this commit, while maintaining the flexibility introduced with the cache variable --- compiler-rt/cmake/config-ix.cmake | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake index 46a6fdf8728f..b281ac64f5d5 100644 --- a/compiler-rt/cmake/config-ix.cmake +++ b/compiler-rt/cmake/config-ix.cmake @@ -463,9 +463,11 @@ if(APPLE) set(DEFAULT_SANITIZER_MIN_OSX_VERSION 10.13) set(DARWIN_osx_MIN_VER_FLAG "-mmacosx-version-min") + + string(REGEX MATCH "${DARWIN_osx_MIN_VER_FLAG}=([.0-9]+)" + MACOSX_VERSION_MIN_FLAG "${CMAKE_CXX_FLAGS}") + if(NOT SANITIZER_MIN_OSX_VERSION) - string(REGEX MATCH "${DARWIN_osx_MIN_VER_FLAG}=([.0-9]+)" - MACOSX_VERSION_MIN_FLAG "${CMAKE_CXX_FLAGS}") if(MACOSX_VERSION_MIN_FLAG) set(MIN_OSX_VERSION "${CMAKE_MATCH_1}") elseif(CMAKE_OSX_DEPLOYMENT_TARGET) -- GitLab From ccdebbae4d77d3efc236af92c22941de5d437e01 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Mon, 8 Apr 2024 16:51:34 -0700 Subject: [PATCH 217/695] [Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin Follow-up to #81037. ToolChain::LibraryPaths holds the new compiler-rt library directory (e.g. `/tmp/Debug/lib/clang/19/lib/x86_64-unknown-linux-gnu`). However, it might be empty when the directory does not exist (due to the `if (getVFS().exists(P))` change in https://reviews.llvm.org/D158475). If neither the old/new compiler-rt library directories exists, we would suggest the undesired old compiler-rt file name: ``` % /tmp/Debug/bin/clang++ a.cc -fsanitize=memory -o a ld.lld: error: cannot open /tmp/Debug/lib/clang/19/lib/linux/libclang_rt.msan-x86_64.a: No such file or directory clang++: error: linker command failed with exit code 1 (use -v to see invocation) ``` With this change, we will correctly suggest the new compiler-rt file name. Fix #87150 Pull Request: https://github.com/llvm/llvm-project/pull/87866 --- clang/lib/Driver/ToolChain.cpp | 8 ++++- clang/test/Driver/arm-compiler-rt.c | 14 ++++----- clang/test/Driver/cl-link.c | 16 +++++----- clang/test/Driver/compiler-rt-unwind.c | 6 ++-- clang/test/Driver/coverage-ld.c | 8 ++--- clang/test/Driver/instrprof-ld.c | 16 +++++----- clang/test/Driver/linux-ld.c | 6 ++-- clang/test/Driver/mingw-sanitizers.c | 16 +++++----- clang/test/Driver/msp430-toolchain.c | 4 +-- .../Driver/print-libgcc-file-name-clangrt.c | 12 ++++---- clang/test/Driver/print-runtime-dir.c | 6 ---- clang/test/Driver/riscv32-toolchain-extra.c | 6 ++-- clang/test/Driver/riscv32-toolchain.c | 6 ++-- clang/test/Driver/riscv64-toolchain-extra.c | 6 ++-- clang/test/Driver/riscv64-toolchain.c | 6 ++-- clang/test/Driver/sanitizer-ld.c | 30 +++++++++---------- clang/test/Driver/wasm-toolchain.c | 18 +++++------ clang/test/Driver/wasm-toolchain.cpp | 16 +++++----- clang/test/Driver/windows-cross.c | 18 +++++------ clang/test/Driver/zos-ld.c | 12 ++++---- .../test/Driver/msvc-dependent-lib-flags.f90 | 8 ++--- 21 files changed, 119 insertions(+), 119 deletions(-) diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 03450fc0f57b..237092ed07e5 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -796,7 +796,13 @@ ToolChain::getTargetSubDirPath(StringRef BaseDir) const { std::optional ToolChain::getRuntimePath() const { SmallString<128> P(D.ResourceDir); llvm::sys::path::append(P, "lib"); - return getTargetSubDirPath(P); + if (auto Ret = getTargetSubDirPath(P)) + return Ret; + // Darwin does not use per-target runtime directory. + if (Triple.isOSDarwin()) + return {}; + llvm::sys::path::append(P, Triple.str()); + return std::string(P); } std::optional ToolChain::getStdlibPath() const { diff --git a/clang/test/Driver/arm-compiler-rt.c b/clang/test/Driver/arm-compiler-rt.c index 5e9e528400d0..cb6c29f48a78 100644 --- a/clang/test/Driver/arm-compiler-rt.c +++ b/clang/test/Driver/arm-compiler-rt.c @@ -10,47 +10,47 @@ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABI -// ARM-GNUEABI: "{{.*[/\\]}}libclang_rt.builtins-arm.a" +// ARM-GNUEABI: "{{.*[/\\]}}libclang_rt.builtins.a" // RUN: %clang -target arm-linux-gnueabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -mfloat-abi=hard -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABI-ABI -// ARM-GNUEABI-ABI: "{{.*[/\\]}}libclang_rt.builtins-armhf.a" +// ARM-GNUEABI-ABI: "{{.*[/\\]}}libclang_rt.builtins.a" // RUN: %clang -target arm-linux-gnueabihf \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABIHF -// ARM-GNUEABIHF: "{{.*[/\\]}}libclang_rt.builtins-armhf.a" +// ARM-GNUEABIHF: "{{.*[/\\]}}libclang_rt.builtins.a" // RUN: %clang -target arm-linux-gnueabihf \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -mfloat-abi=soft -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABIHF-ABI -// ARM-GNUEABIHF-ABI: "{{.*[/\\]}}libclang_rt.builtins-arm.a" +// ARM-GNUEABIHF-ABI: "{{.*[/\\]}}libclang_rt.builtins.a" // RUN: %clang -target arm-windows-itanium \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-WINDOWS -// ARM-WINDOWS: "{{.*[/\\]}}clang_rt.builtins-arm.lib" +// ARM-WINDOWS: "{{.*[/\\]}}clang_rt.builtins.lib" // RUN: %clang -target arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-ANDROID -// ARM-ANDROID: "{{.*[/\\]}}libclang_rt.builtins-arm-android.a" +// ARM-ANDROID: "{{.*[/\\]}}libclang_rt.builtins.a" // RUN: not %clang --target=arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -mfloat-abi=hard -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-ANDROIDHF -// ARM-ANDROIDHF: "{{.*[/\\]}}libclang_rt.builtins-armhf-android.a" +// ARM-ANDROIDHF: "{{.*[/\\]}}libclang_rt.builtins.a" diff --git a/clang/test/Driver/cl-link.c b/clang/test/Driver/cl-link.c index 444f0c01b3f9..ffd0b5ac4bad 100644 --- a/clang/test/Driver/cl-link.c +++ b/clang/test/Driver/cl-link.c @@ -13,20 +13,20 @@ // ASAN: link.exe // ASAN: "-debug" // ASAN: "-incremental:no" -// ASAN: "{{[^"]*}}clang_rt.asan-i386.lib" -// ASAN: "-wholearchive:{{.*}}clang_rt.asan-i386.lib" -// ASAN: "{{[^"]*}}clang_rt.asan_cxx-i386.lib" -// ASAN: "-wholearchive:{{.*}}clang_rt.asan_cxx-i386.lib" +// ASAN: "{{[^"]*}}clang_rt.asan.lib" +// ASAN: "-wholearchive:{{.*}}clang_rt.asan.lib" +// ASAN: "{{[^"]*}}clang_rt.asan_cxx.lib" +// ASAN: "-wholearchive:{{.*}}clang_rt.asan_cxx.lib" // ASAN: "{{.*}}cl-link{{.*}}.obj" // RUN: %clang_cl -m32 -arch:IA32 --target=i386-pc-win32 /MD /Tc%s -fuse-ld=link -### -fsanitize=address 2>&1 | FileCheck --check-prefix=ASAN-MD %s // ASAN-MD: link.exe // ASAN-MD: "-debug" // ASAN-MD: "-incremental:no" -// ASAN-MD: "{{.*}}clang_rt.asan_dynamic-i386.lib" -// ASAN-MD: "{{[^"]*}}clang_rt.asan_dynamic_runtime_thunk-i386.lib" +// ASAN-MD: "{{.*}}clang_rt.asan_dynamic.lib" +// ASAN-MD: "{{[^"]*}}clang_rt.asan_dynamic_runtime_thunk.lib" // ASAN-MD: "-include:___asan_seh_interceptor" -// ASAN-MD: "-wholearchive:{{.*}}clang_rt.asan_dynamic_runtime_thunk-i386.lib" +// ASAN-MD: "-wholearchive:{{.*}}clang_rt.asan_dynamic_runtime_thunk.lib" // ASAN-MD: "{{.*}}cl-link{{.*}}.obj" // RUN: %clang_cl /LD -fuse-ld=link -### /Tc%s 2>&1 | FileCheck --check-prefix=DLL %s @@ -40,7 +40,7 @@ // ASAN-DLL: "-dll" // ASAN-DLL: "-debug" // ASAN-DLL: "-incremental:no" -// ASAN-DLL: "{{.*}}clang_rt.asan_dll_thunk-i386.lib" +// ASAN-DLL: "{{.*}}clang_rt.asan_dll_thunk.lib" // ASAN-DLL: "{{.*}}cl-link{{.*}}.obj" // RUN: %clang_cl /Zi /Tc%s -fuse-ld=link -### 2>&1 | FileCheck --check-prefix=DEBUG %s diff --git a/clang/test/Driver/compiler-rt-unwind.c b/clang/test/Driver/compiler-rt-unwind.c index 7f4e3f22ab19..c5040d7fd900 100644 --- a/clang/test/Driver/compiler-rt-unwind.c +++ b/clang/test/Driver/compiler-rt-unwind.c @@ -98,14 +98,14 @@ // RUN: --target=x86_64-w64-mingw32 -rtlib=compiler-rt --unwindlib=libunwind \ // RUN: -shared-libgcc \ // RUN: | FileCheck --check-prefix=MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT %s -// MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins-x86_64.a" +// MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins.a" // MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT-SAME: "-l:libunwind.dll.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-w64-mingw32 -rtlib=compiler-rt --unwindlib=libunwind \ // RUN: -static-libgcc \ // RUN: | FileCheck --check-prefix=MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT %s -// MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins-x86_64.a" +// MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins.a" // MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT-SAME: "-l:libunwind.a" // // RUN: %clang -### %s 2>&1 \ @@ -114,5 +114,5 @@ // RUN: %clangxx -### %s 2>&1 \ // RUN: --target=x86_64-w64-mingw32 -rtlib=compiler-rt --unwindlib=libunwind \ // RUN: | FileCheck --check-prefix=MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT %s -// MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins-x86_64.a" +// MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins.a" // MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT-SAME: "-lunwind" diff --git a/clang/test/Driver/coverage-ld.c b/clang/test/Driver/coverage-ld.c index acb08eb5db59..be1d8320ab8b 100644 --- a/clang/test/Driver/coverage-ld.c +++ b/clang/test/Driver/coverage-ld.c @@ -33,7 +33,7 @@ // RUN: | FileCheck --check-prefix=CHECK-FREEBSD-X86-64 %s // // CHECK-FREEBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}freebsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-freebsd{{/|\\\\}}libclang_rt.profile.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-netbsd --coverage -fuse-ld=ld \ @@ -42,7 +42,7 @@ // RUN: | FileCheck --check-prefix=CHECK-NETBSD-X86-64 %s // CHECK-NETBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}netbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-netbsd{{/|\\\\}}libclang_rt.profile.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-openbsd --coverage -fuse-ld=ld \ @@ -51,7 +51,7 @@ // RUN: | FileCheck --check-prefix=CHECK-OPENBSD-X86-64 %s // CHECK-OPENBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}openbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-openbsd{{/|\\\\}}libclang_rt.profile.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=arm-linux-androideabi --coverage -fuse-ld=ld \ @@ -60,4 +60,4 @@ // RUN: | FileCheck --check-prefix=CHECK-ANDROID-ARM %s // // CHECK-ANDROID-ARM: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" -// CHECK-ANDROID-ARM: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}linux{{/|\\\\}}libclang_rt.profile-arm-android.a" +// CHECK-ANDROID-ARM: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}arm-unknown-linux-android{{/|\\\\}}libclang_rt.profile.a" diff --git a/clang/test/Driver/instrprof-ld.c b/clang/test/Driver/instrprof-ld.c index 674580b349d4..a96bba4a1e76 100644 --- a/clang/test/Driver/instrprof-ld.c +++ b/clang/test/Driver/instrprof-ld.c @@ -34,7 +34,7 @@ // RUN: | FileCheck --check-prefix=CHECK-FREEBSD-X86-64 %s // // CHECK-FREEBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}freebsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-freebsd{{/|\\\\}}libclang_rt.profile.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-netbsd -fprofile-instr-generate -fuse-ld=ld \ @@ -43,7 +43,7 @@ // RUN: | FileCheck --check-prefix=CHECK-NETBSD-X86-64 %s // CHECK-NETBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}netbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-netbsd{{/|\\\\}}libclang_rt.profile.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-openbsd -fprofile-instr-generate -fuse-ld=ld \ @@ -52,7 +52,7 @@ // RUN: | FileCheck --check-prefix=CHECK-OPENBSD-X86-64 %s // CHECK-OPENBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}openbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-openbsd{{/|\\\\}}libclang_rt.profile.a" // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -72,7 +72,7 @@ // RUN: | FileCheck --check-prefix=CHECK-LINUX-X86-64-SHARED %s // // CHECK-LINUX-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-LINUX-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{.*}}linux{{.*}}libclang_rt.profile.a" {{.*}} "-lc" +// CHECK-LINUX-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{.*}}x86_64-unknown-linux{{.*}}libclang_rt.profile.a" {{.*}} "-lc" // // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -82,7 +82,7 @@ // RUN: | FileCheck --check-prefix=CHECK-FREEBSD-X86-64-SHARED %s // // CHECK-FREEBSD-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-FREEBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}freebsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-FREEBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-freebsd{{/|\\\\}}libclang_rt.profile.a" // // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -92,7 +92,7 @@ // RUN: | FileCheck --check-prefix=CHECK-NETBSD-X86-64-SHARED %s // CHECK-NETBSD-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-NETBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}netbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-NETBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-netbsd{{/|\\\\}}libclang_rt.profile.a" // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -102,7 +102,7 @@ // RUN: | FileCheck --check-prefix=CHECK-OPENBSD-X86-64-SHARED %s // CHECK-OPENBSD-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-OPENBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}openbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-OPENBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-openbsd{{/|\\\\}}libclang_rt.profile.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-apple-darwin14 -fprofile-instr-generate -fuse-ld=ld \ @@ -174,7 +174,7 @@ // RUN: | FileCheck --check-prefix=CHECK-MINGW-X86-64 %s // // CHECK-MINGW-X86-64: "{{(.*[^.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-MINGW-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}windows{{/|\\\\}}libclang_rt.profile-x86_64.a" +// CHECK-MINGW-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-windows-gnu{{/|\\\\}}libclang_rt.profile.a" // Test instrumented profiling dependent-lib flags // diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c index 4020b138dc8f..e5c556367385 100644 --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -99,9 +99,9 @@ // CHECK-LD-RT-ANDROID: "--eh-frame-hdr" // CHECK-LD-RT-ANDROID: "-m" "armelf_linux_eabi" // CHECK-LD-RT-ANDROID: "-dynamic-linker" -// CHECK-LD-RT-ANDROID: libclang_rt.builtins-arm-android.a" +// CHECK-LD-RT-ANDROID: libclang_rt.builtins.a" // CHECK-LD-RT-ANDROID: "-lc" -// CHECK-LD-RT-ANDROID: libclang_rt.builtins-arm-android.a" +// CHECK-LD-RT-ANDROID: libclang_rt.builtins.a" // // RUN: %clang -### %s -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ @@ -264,7 +264,7 @@ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-CLANG-ANDROID-STATIC %s // CHECK-CLANG-ANDROID-STATIC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" -// CHECK-CLANG-ANDROID-STATIC: "--start-group" "{{[^"]*}}{{/|\\\\}}libclang_rt.builtins-aarch64-android.a" "-l:libunwind.a" "-lc" "--end-group" +// CHECK-CLANG-ANDROID-STATIC: "--start-group" "{{[^"]*}}{{/|\\\\}}libclang_rt.builtins.a" "-l:libunwind.a" "-lc" "--end-group" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ diff --git a/clang/test/Driver/mingw-sanitizers.c b/clang/test/Driver/mingw-sanitizers.c index d165648a8fdf..2325f8f0f1f2 100644 --- a/clang/test/Driver/mingw-sanitizers.c +++ b/clang/test/Driver/mingw-sanitizers.c @@ -4,17 +4,17 @@ // // ASAN-ALL-NOT:"-l{{[^"]+"]}}" // ASAN-ALL-NOT:"[[INPUT]]" -// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic-i386.dll.a" -// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic-x86_64.dll.a" +// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" +// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" // ASAN-ALL: "-lcomponent" // ASAN-ALL: "[[INPUT]]" -// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic-i386.dll.a" -// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-i386.a" +// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" +// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" // ASAN-I686: "--require-defined" "___asan_seh_interceptor" -// ASAN-I686: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-i386.a" "--no-whole-archive" -// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic-x86_64.dll.a" -// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-x86_64.a" +// ASAN-I686: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" "--no-whole-archive" +// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" +// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" // ASAN-X86_64: "--require-defined" "__asan_seh_interceptor" -// ASAN-X86_64: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-x86_64.a" "--no-whole-archive" +// ASAN-X86_64: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" "--no-whole-archive" // RUN: %clang -target x86_64-windows-gnu %s -### -fsanitize=vptr diff --git a/clang/test/Driver/msp430-toolchain.c b/clang/test/Driver/msp430-toolchain.c index ef6780c38f2e..3c3042b482ef 100644 --- a/clang/test/Driver/msp430-toolchain.c +++ b/clang/test/Driver/msp430-toolchain.c @@ -103,8 +103,8 @@ // LIBS-COMPILER-RT-POS: "{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430{{/|\\\\}}crtbegin_no_eh.o" // LIBS-COMPILER-RT-POS: "-L{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430" // LIBS-COMPILER-RT-POS: "-L{{.*}}/Inputs/basic_msp430_tree{{/|\\\\}}msp430-elf{{/|\\\\}}lib/430" -// LIBS-COMPILER-RT-POS: "{{[^"]*}}libclang_rt.builtins-msp430.a" "--start-group" "-lmul_none" "-lc" "{{[^"]*}}libclang_rt.builtins-msp430.a" "-lcrt" "-lnosys" "--end-group" "{{[^"]*}}libclang_rt.builtins-msp430.a" -// LIBS-COMPILER-RT-POS: "{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430{{/|\\\\}}crtend_no_eh.o" "{{[^"]*}}libclang_rt.builtins-msp430.a" +// LIBS-COMPILER-RT-POS: "{{[^"]*}}libclang_rt.builtins.a" "--start-group" "-lmul_none" "-lc" "{{[^"]*}}libclang_rt.builtins.a" "-lcrt" "-lnosys" "--end-group" "{{[^"]*}}libclang_rt.builtins.a" +// LIBS-COMPILER-RT-POS: "{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430{{/|\\\\}}crtend_no_eh.o" "{{[^"]*}}libclang_rt.builtins.a" // LIBS-COMPILER-RT-NEG-NOT: crtbegin.o // LIBS-COMPILER-RT-NEG-NOT: -lssp_nonshared // LIBS-COMPILER-RT-NEG-NOT: -lssp diff --git a/clang/test/Driver/print-libgcc-file-name-clangrt.c b/clang/test/Driver/print-libgcc-file-name-clangrt.c index ed740e0d2917..a902eedc8520 100644 --- a/clang/test/Driver/print-libgcc-file-name-clangrt.c +++ b/clang/test/Driver/print-libgcc-file-name-clangrt.c @@ -5,14 +5,14 @@ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-X8664 %s -// CHECK-CLANGRT-X8664: libclang_rt.builtins-x86_64.a +// CHECK-CLANGRT-X8664: libclang_rt.builtins.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=i386-pc-linux \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-I386 %s -// CHECK-CLANGRT-I386: libclang_rt.builtins-i386.a +// CHECK-CLANGRT-I386: libclang_rt.builtins.a // Check whether alternate arch values map to the correct library. // @@ -27,28 +27,28 @@ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARM %s -// CHECK-CLANGRT-ARM: libclang_rt.builtins-arm.a +// CHECK-CLANGRT-ARM: libclang_rt.builtins.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARM-ANDROID %s -// CHECK-CLANGRT-ARM-ANDROID: libclang_rt.builtins-arm-android.a +// CHECK-CLANGRT-ARM-ANDROID: libclang_rt.builtins.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=arm-linux-gnueabihf \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARMHF %s -// CHECK-CLANGRT-ARMHF: libclang_rt.builtins-armhf.a +// CHECK-CLANGRT-ARMHF: libclang_rt.builtins.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=arm-linux-gnueabi -mfloat-abi=hard \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARM-ABI %s -// CHECK-CLANGRT-ARM-ABI: libclang_rt.builtins-armhf.a +// CHECK-CLANGRT-ARM-ABI: libclang_rt.builtins.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=armv7m-none-eabi \ diff --git a/clang/test/Driver/print-runtime-dir.c b/clang/test/Driver/print-runtime-dir.c index 550ffef1aaf6..ac1ff7e634b8 100644 --- a/clang/test/Driver/print-runtime-dir.c +++ b/clang/test/Driver/print-runtime-dir.c @@ -1,9 +1,3 @@ -// Default directory layout -// RUN: %clang -print-runtime-dir --target=x86_64-pc-windows-msvc \ -// RUN: -resource-dir=%S/Inputs/resource_dir \ -// RUN: | FileCheck --check-prefix=PRINT-RUNTIME-DIR -DFILE=%S/Inputs/resource_dir %s -// PRINT-RUNTIME-DIR: [[FILE]]{{/|\\}}lib{{/|\\}}windows - // Per-target directory layout // RUN: %clang -print-runtime-dir --target=x86_64-pc-windows-msvc \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_per_target_subdir \ diff --git a/clang/test/Driver/riscv32-toolchain-extra.c b/clang/test/Driver/riscv32-toolchain-extra.c index 2d38aa3b545f..aab6b36f3cfc 100644 --- a/clang/test/Driver/riscv32-toolchain-extra.c +++ b/clang/test/Driver/riscv32-toolchain-extra.c @@ -29,8 +29,8 @@ // C-RV32-BAREMETAL-ILP32-NOGCC: "-internal-isystem" "{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/include" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/bin/riscv32-unknown-elf-ld" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib/crt0.o" -// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/lib/clang_rt.crtbegin-riscv32.o" +// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/clang_rt.crtbegin.o" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib" // C-RV32-BAREMETAL-ILP32-NOGCC: "--start-group" "-lc" "-lgloss" "--end-group" -// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/lib/libclang_rt.builtins-riscv32.a" -// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/lib/clang_rt.crtend-riscv32.o" +// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/libclang_rt.builtins.a" +// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/clang_rt.crtend.o" diff --git a/clang/test/Driver/riscv32-toolchain.c b/clang/test/Driver/riscv32-toolchain.c index bb2533cdf1bc..322a6ca2840f 100644 --- a/clang/test/Driver/riscv32-toolchain.c +++ b/clang/test/Driver/riscv32-toolchain.c @@ -195,9 +195,9 @@ // RUN: --target=riscv32-unknown-elf --rtlib=compiler-rt --unwindlib=compiler-rt 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-RTLIB-COMPILERRT-ILP32 %s // C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}crt0.o" -// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtbegin-riscv32.o" -// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins-riscv32.a" -// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o" +// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtbegin.o" +// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins.a" +// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend.o" // RUN: %clang -### %s --target=riscv32 \ // RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree --sysroot= \ diff --git a/clang/test/Driver/riscv64-toolchain-extra.c b/clang/test/Driver/riscv64-toolchain-extra.c index a6ec9b16cc5c..d8d9b5844167 100644 --- a/clang/test/Driver/riscv64-toolchain-extra.c +++ b/clang/test/Driver/riscv64-toolchain-extra.c @@ -29,8 +29,8 @@ // C-RV64-BAREMETAL-LP64-NOGCC: "-internal-isystem" "{{.*}}/riscv64-nogcc/bin/../riscv64-unknown-elf/include" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/bin/riscv64-unknown-elf-ld" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/bin/../riscv64-unknown-elf/lib/crt0.o" -// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/lib/clang_rt.crtbegin-riscv64.o" +// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/riscv64-unknown-unknown-elf/clang_rt.crtbegin.o" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/bin/../riscv64-unknown-elf/lib" // C-RV64-BAREMETAL-LP64-NOGCC: "--start-group" "-lc" "-lgloss" "--end-group" -// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/lib/libclang_rt.builtins-riscv64.a" -// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/lib/clang_rt.crtend-riscv64.o" +// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/riscv64-unknown-unknown-elf/libclang_rt.builtins.a" +// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/riscv64-unknown-unknown-elf/clang_rt.crtend.o" diff --git a/clang/test/Driver/riscv64-toolchain.c b/clang/test/Driver/riscv64-toolchain.c index 381ee58c470c..b3216de30754 100644 --- a/clang/test/Driver/riscv64-toolchain.c +++ b/clang/test/Driver/riscv64-toolchain.c @@ -151,9 +151,9 @@ // RUN: --target=riscv64-unknown-elf --rtlib=compiler-rt --unwindlib=compiler-rt 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-RTLIB-COMPILERRT-LP64 %s // C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}crt0.o" -// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtbegin-riscv64.o" -// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins-riscv64.a" -// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o" +// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtbegin.o" +// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins.a" +// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend.o" // RUN: %clang -### %s --target=riscv64 \ // RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree --sysroot= \ diff --git a/clang/test/Driver/sanitizer-ld.c b/clang/test/Driver/sanitizer-ld.c index 53e536d77292..1d52fc126095 100644 --- a/clang/test/Driver/sanitizer-ld.c +++ b/clang/test/Driver/sanitizer-ld.c @@ -111,7 +111,7 @@ // CHECK-ASAN-FREEBSD: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-FREEBSD-NOT: "-lc" // CHECK-ASAN-FREEBSD-NOT: libclang_rt.asan_cxx -// CHECK-ASAN-FREEBSD: freebsd{{/|\\+}}libclang_rt.asan-i386.a" +// CHECK-ASAN-FREEBSD: freebsd{{/|\\+}}libclang_rt.asan.a" // CHECK-ASAN-FREEBSD-NOT: libclang_rt.asan_cxx // CHECK-ASAN-FREEBSD-NOT: "--dynamic-list" // CHECK-ASAN-FREEBSD: "--export-dynamic" @@ -135,8 +135,8 @@ // // CHECK-ASAN-LINUX-CXX: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-LINUX-CXX-NOT: "-lc" -// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan-i386.a" "--no-whole-archive" -// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan_cxx-i386.a" "--no-whole-archive" +// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan.a" "--no-whole-archive" +// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan_cxx.a" "--no-whole-archive" // CHECK-ASAN-LINUX-CXX-NOT: "--dynamic-list" // CHECK-ASAN-LINUX-CXX: "--export-dynamic" // CHECK-ASAN-LINUX-CXX: stdc++ @@ -163,7 +163,7 @@ // // CHECK-ASAN-ARM: "{{(.*[^.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-ARM-NOT: "-lc" -// CHECK-ASAN-ARM: libclang_rt.asan-arm.a" +// CHECK-ASAN-ARM: libclang_rt.asan.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=armv7l-linux-gnueabi -fuse-ld=ld -fsanitize=address \ @@ -172,7 +172,7 @@ // // CHECK-ASAN-ARMv7: "{{(.*[^.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-ARMv7-NOT: "-lc" -// CHECK-ASAN-ARMv7: libclang_rt.asan-arm.a" +// CHECK-ASAN-ARMv7: libclang_rt.asan.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=arm-linux-androideabi -fuse-ld=ld -fsanitize=address \ @@ -184,7 +184,7 @@ // CHECK-ASAN-ANDROID-NOT: "-lc" // CHECK-ASAN-ANDROID-NOT: "-lpthread" // CHECK-ASAN-ANDROID-NOT: "-lresolv" -// CHECK-ASAN-ANDROID: libclang_rt.asan-arm-android.so" +// CHECK-ASAN-ANDROID: libclang_rt.asan.so" // CHECK-ASAN-ANDROID-NOT: "-lpthread" // CHECK-ASAN-ANDROID-NOT: "-lresolv" @@ -195,7 +195,7 @@ // RUN: | FileCheck --check-prefix=CHECK-ASAN-ANDROID-STATICLIBASAN %s // // CHECK-ASAN-ANDROID-STATICLIBASAN: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" -// CHECK-ASAN-ANDROID-STATICLIBASAN: libclang_rt.asan-arm-android.a" +// CHECK-ASAN-ANDROID-STATICLIBASAN: libclang_rt.asan.a" // CHECK-ASAN-ANDROID-STATICLIBASAN-NOT: "-lpthread" // CHECK-ASAN-ANDROID-STATICLIBASAN-NOT: "-lrt" // CHECK-ASAN-ANDROID-STATICLIBASAN-NOT: "-lresolv" @@ -210,7 +210,7 @@ // CHECK-UBSAN-ANDROID-NOT: "-lc" // CHECK-UBSAN-ANDROID-NOT: "-lpthread" // CHECK-UBSAN-ANDROID-NOT: "-lresolv" -// CHECK-UBSAN-ANDROID: libclang_rt.ubsan_standalone-arm-android.so" +// CHECK-UBSAN-ANDROID: libclang_rt.ubsan_standalone.so" // CHECK-UBSAN-ANDROID-NOT: "-lpthread" // CHECK-UBSAN-ANDROID-NOT: "-lresolv" @@ -221,7 +221,7 @@ // RUN: | FileCheck --check-prefix=CHECK-UBSAN-ANDROID-STATICLIBASAN %s // // CHECK-UBSAN-ANDROID-STATICLIBASAN: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" -// CHECK-UBSAN-ANDROID-STATICLIBASAN: libclang_rt.ubsan_standalone-arm-android.a" +// CHECK-UBSAN-ANDROID-STATICLIBASAN: libclang_rt.ubsan_standalone.a" // CHECK-UBSAN-ANDROID-STATICLIBASAN-NOT: "-lpthread" // CHECK-UBSAN-ANDROID-STATICLIBASAN-NOT: "-lrt" // CHECK-UBSAN-ANDROID-STATICLIBASAN-NOT: "-lresolv" @@ -237,7 +237,7 @@ // CHECK-ASAN-ANDROID-X86-NOT: "-lc" // CHECK-ASAN-ANDROID-X86-NOT: "-lpthread" // CHECK-ASAN-ANDROID-X86-NOT: "-lresolv" -// CHECK-ASAN-ANDROID-X86: libclang_rt.asan-i686-android.so" +// CHECK-ASAN-ANDROID-X86: libclang_rt.asan.so" // CHECK-ASAN-ANDROID-X86-NOT: "-lpthread" // CHECK-ASAN-ANDROID-X86-NOT: "-lresolv" // @@ -257,7 +257,7 @@ // // CHECK-ASAN-ANDROID-SHARED: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" // CHECK-ASAN-ANDROID-SHARED-NOT: "-lc" -// CHECK-ASAN-ANDROID-SHARED: libclang_rt.asan-arm-android.so" +// CHECK-ASAN-ANDROID-SHARED: libclang_rt.asan.so" // CHECK-ASAN-ANDROID-SHARED-NOT: "-lpthread" // CHECK-ASAN-ANDROID-SHARED-NOT: "-lresolv" @@ -347,7 +347,7 @@ // CHECK-UBSAN-LINUX: "{{.*}}ld{{(.exe)?}}" // CHECK-UBSAN-LINUX-NOT: libclang_rt.asan // CHECK-UBSAN-LINUX-NOT: libclang_rt.ubsan_standalone_cxx -// CHECK-UBSAN-LINUX: "--whole-archive" "{{.*}}libclang_rt.ubsan_standalone-x32.a" "--no-whole-archive" +// CHECK-UBSAN-LINUX: "--whole-archive" "{{.*}}libclang_rt.ubsan_standalone.a" "--no-whole-archive" // CHECK-UBSAN-LINUX-NOT: libclang_rt.asan // CHECK-UBSAN-LINUX-NOT: libclang_rt.ubsan_standalone_cxx // CHECK-UBSAN-LINUX-NOT: "-lstdc++" @@ -678,7 +678,7 @@ // RUN: --sysroot=%S/Inputs/basic_android_tree \ // RUN: | FileCheck --check-prefix=CHECK-CFI-CROSS-DSO-DIAG-ANDROID %s // CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{.*}}ld{{(.exe)?}}" -// CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{[^"]*}}libclang_rt.ubsan_standalone-aarch64-android.so" +// CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{[^"]*}}libclang_rt.ubsan_standalone.so" // CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "--export-dynamic-symbol=__cfi_check" // RUN: %clangxx -fsanitize=address -### %s 2>&1 \ @@ -929,7 +929,7 @@ // CHECK-SCUDO-ANDROID: "-pie" // CHECK-SCUDO-ANDROID-NOT: "-lpthread" // CHECK-SCUDO-ANDROID-NOT: "-lresolv" -// CHECK-SCUDO-ANDROID: libclang_rt.scudo_standalone-arm-android.so" +// CHECK-SCUDO-ANDROID: libclang_rt.scudo_standalone.so" // CHECK-SCUDO-ANDROID-NOT: "-lpthread" // CHECK-SCUDO-ANDROID-NOT: "-lresolv" @@ -940,7 +940,7 @@ // RUN: | FileCheck --check-prefix=CHECK-SCUDO-ANDROID-STATIC %s // CHECK-SCUDO-ANDROID-STATIC: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" // CHECK-SCUDO-ANDROID-STATIC: "-pie" -// CHECK-SCUDO-ANDROID-STATIC: "--whole-archive" "{{.*}}libclang_rt.scudo_standalone-arm-android.a" "--no-whole-archive" +// CHECK-SCUDO-ANDROID-STATIC: "--whole-archive" "{{.*}}libclang_rt.scudo_standalone.a" "--no-whole-archive" // CHECK-SCUDO-ANDROID-STATIC-NOT: "-lstdc++" // CHECK-SCUDO-ANDROID-STATIC-NOT: "-lpthread" // CHECK-SCUDO-ANDROID-STATIC-NOT: "-lrt" diff --git a/clang/test/Driver/wasm-toolchain.c b/clang/test/Driver/wasm-toolchain.c index 88590a3ba4c4..dabf0ac2433b 100644 --- a/clang/test/Driver/wasm-toolchain.c +++ b/clang/test/Driver/wasm-toolchain.c @@ -17,42 +17,42 @@ // RUN: %clang -### --target=wasm32-unknown-unknown --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK %s // LINK: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C link command-line with optimization with unknown OS. // RUN: %clang -### -O2 --target=wasm32-unknown-unknown --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT %s // LINK_OPT: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C link command-line with known OS. // RUN: %clang -### --target=wasm32-wasi --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN %s // LINK_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // -shared should be passed through to `wasm-ld` and include crt1-reactor.o with a known OS. // RUN: %clang -### -shared -mexec-model=reactor --target=wasm32-wasi --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN_SHARED %s // LINK_KNOWN_SHARED: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN_SHARED: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_KNOWN_SHARED: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // -shared should be passed through to `wasm-ld` and include crt1-reactor.o with an unknown OS. // RUN: %clang -### -shared -mexec-model=reactor --target=wasm32-unknown-unknown --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_UNKNOWN_SHARED %s // LINK_UNKNOWN_SHARED: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_UNKNOWN_SHARED: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_UNKNOWN_SHARED: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C link command-line with optimization with known OS. // RUN: %clang -### -O2 --target=wasm32-wasi --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_KNOWN %s // LINK_OPT_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C compile command-line with known OS. @@ -180,12 +180,12 @@ // RUN: %clang -### %s --target=wasm32-unknown-unknown --sysroot=%s/no-sysroot-there -mexec-model=command 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-COMMAND %s // CHECK-COMMAND: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// CHECK-COMMAND: wasm-ld{{.*}}" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// CHECK-COMMAND: wasm-ld{{.*}}" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // RUN: %clang -### %s --target=wasm32-unknown-unknown --sysroot=%s/no-sysroot-there -mexec-model=reactor 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-REACTOR %s // CHECK-REACTOR: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// CHECK-REACTOR: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// CHECK-REACTOR: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // -fPIC implies +mutable-globals @@ -204,7 +204,7 @@ // RUN: %clang -### -O2 --target=wasm32-wasip2 %s --sysroot /foo 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_WASIP2 %s // LINK_WASIP2: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_WASIP2: wasm-component-ld{{.*}}" "-L/foo/lib/wasm32-wasip2" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_WASIP2: wasm-component-ld{{.*}}" "-L/foo/lib/wasm32-wasip2" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // Test that on `wasm32-wasip2` the `wasm-component-ld` programs is told where // to find `wasm-ld` by default. diff --git a/clang/test/Driver/wasm-toolchain.cpp b/clang/test/Driver/wasm-toolchain.cpp index 4af011097021..ba1c55b33edc 100644 --- a/clang/test/Driver/wasm-toolchain.cpp +++ b/clang/test/Driver/wasm-toolchain.cpp @@ -17,48 +17,48 @@ // RUN: %clangxx -### --target=wasm32-unknown-unknown --sysroot=/foo --stdlib=libc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK %s // LINK: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // RUN: %clangxx -### --target=wasm32-unknown-unknown --sysroot=/foo --stdlib=libstdc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_STDCXX %s // LINK_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C++ link command-line with optimization with unknown OS. // RUN: %clangxx -### -O2 --target=wasm32-unknown-unknown --sysroot=/foo %s --stdlib=libc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT %s // LINK_OPT: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // RUN: %clangxx -### -O2 --target=wasm32-unknown-unknown --sysroot=/foo %s --stdlib=libstdc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_STDCXX %s // LINK_OPT_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_OPT_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C++ link command-line with known OS. // RUN: %clangxx -### --target=wasm32-wasi --sysroot=/foo --stdlib=libc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN %s // LINK_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // RUN: %clangxx -### --target=wasm32-wasi --sysroot=/foo --stdlib=libstdc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN_STDCXX %s // LINK_KNOWN_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C++ link command-line with optimization with known OS. // RUN: %clangxx -### -O2 --target=wasm32-wasi --sysroot=/foo %s --stdlib=libc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_KNOWN %s // LINK_OPT_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // RUN: %clangxx -### -O2 --target=wasm32-wasi --sysroot=/foo %s --stdlib=libstdc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_KNOWN_STDCXX %s // LINK_OPT_KNOWN_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" +// LINK_OPT_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" // A basic C++ compile command-line with known OS. diff --git a/clang/test/Driver/windows-cross.c b/clang/test/Driver/windows-cross.c index 75490b992d78..f6e831f00e13 100644 --- a/clang/test/Driver/windows-cross.c +++ b/clang/test/Driver/windows-cross.c @@ -11,32 +11,32 @@ // RUN: %clang -### -target armv7-windows-itanium --sysroot %s/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -rtlib=compiler-rt -stdlib=libstdc++ -o /dev/null %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-RTLIB -// CHECK-RTLIB: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" +// CHECK-RTLIB: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -rtlib=compiler-rt -stdlib=libc++ -o /dev/null %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-C-LIBCXX -// CHECK-C-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" +// CHECK-C-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" // RUN: %clangxx -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -rtlib=compiler-rt -stdlib=libc++ -o /dev/null %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-LIBCXX -// CHECK-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lc++" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" +// CHECK-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lc++" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SHARED -// CHECK-SHARED: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" +// CHECK-SHARED: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -static -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SHARED-STATIC -// CHECK-SHARED-STATIC: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bstatic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" +// CHECK-SHARED-STATIC: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bstatic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %s/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -nostartfiles -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-NOSTARTFILES -// CHECK-NOSTARTFILES: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" +// CHECK-NOSTARTFILES: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -nostartfiles -nodefaultlibs -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-STANDALONE @@ -52,19 +52,19 @@ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-ADDRESS // CHECK-SANITIZE-ADDRESS: "-fsanitize=address" -// CHECK-SANITIZE-ADDRESS: "{{.*}}clang_rt.asan_dll_thunk-arm.lib" +// CHECK-SANITIZE-ADDRESS: "{{.*}}clang_rt.asan_dll_thunk.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=lld-link2 -o test.exe -fsanitize=address -x c++ %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-ADDRESS-EXE // CHECK-SANITIZE-ADDRESS-EXE: "-fsanitize=address" -// CHECK-SANITIZE-ADDRESS-EXE: "{{.*}}clang_rt.asan_dynamic-arm.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk-arm.lib" "--undefined" "__asan_seh_interceptor" +// CHECK-SANITIZE-ADDRESS-EXE: "{{.*}}clang_rt.asan_dynamic.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk.lib" "--undefined" "__asan_seh_interceptor" // RUN: %clang -### -target i686-windows-itanium -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=lld-link2 -o test.exe -fsanitize=address -x c++ %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-ADDRESS-EXE-X86 // CHECK-SANITIZE-ADDRESS-EXE-X86: "-fsanitize=address" -// CHECK-SANITIZE-ADDRESS-EXE-X86: "{{.*}}clang_rt.asan_dynamic-i386.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk-i386.lib" "--undefined" "___asan_seh_interceptor" +// CHECK-SANITIZE-ADDRESS-EXE-X86: "{{.*}}clang_rt.asan_dynamic.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk.lib" "--undefined" "___asan_seh_interceptor" // RUN: not %clang -### --target=armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=lld-link2 -shared -o shared.dll -fsanitize=tsan -x c++ %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-TSAN diff --git a/clang/test/Driver/zos-ld.c b/clang/test/Driver/zos-ld.c index 4d4decdd0e65..87d169936e12 100644 --- a/clang/test/Driver/zos-ld.c +++ b/clang/test/Driver/zos-ld.c @@ -14,7 +14,7 @@ // C-LD-SAME: "-S" "//'SYS1.CSSLIB'" // C-LD-SAME: "//'CEE.SCEELIB(CELQS001)'" // C-LD-SAME: "//'CEE.SCEELIB(CELQS003)'" -// C-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" +// C-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" // 2. General C link for dll // RUN: %clang -### --shared --target=s390x-ibm-zos %s 2>&1 \ @@ -30,7 +30,7 @@ // C-LD-DLL-SAME: "-S" "//'SYS1.CSSLIB'" // C-LD-DLL-SAME: "//'CEE.SCEELIB(CELQS001)'" // C-LD-DLL-SAME: "//'CEE.SCEELIB(CELQS003)'" -// C-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" +// C-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" // 3. General C++ link for executable // RUN: %clangxx -### --target=s390x-ibm-zos %s 2>&1 \ @@ -52,7 +52,7 @@ // CXX-LD-SAME: "//'CEE.SCEELIB(CRTDQCXA)'" // CXX-LD-SAME: "//'CEE.SCEELIB(CRTDQXLA)'" // CXX-LD-SAME: "//'CEE.SCEELIB(CRTDQUNW)'" -// CXX-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" +// CXX-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" // 4. General C++ link for dll // RUN: %clangxx -### --shared --target=s390x-ibm-zos %s 2>&1 \ @@ -74,7 +74,7 @@ // CXX-LD-DLL-SAME: "//'CEE.SCEELIB(CRTDQCXA)'" // CXX-LD-DLL-SAME: "//'CEE.SCEELIB(CRTDQXLA)'" // CXX-LD-DLL-SAME: "//'CEE.SCEELIB(CRTDQUNW)'" -// CXX-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" +// CXX-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" // 5. C++ link for executable w/ -mzos-hlq-le=, -mzos-hlq-csslib= // RUN: %clangxx -### --target=s390x-ibm-zos %s 2>&1 \ @@ -97,7 +97,7 @@ // CXX-LD5-SAME: "//'AAAA.SCEELIB(CRTDQCXA)'" // CXX-LD5-SAME: "//'AAAA.SCEELIB(CRTDQXLA)'" // CXX-LD5-SAME: "//'AAAA.SCEELIB(CRTDQUNW)'" -// CXX-LD5-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" +// CXX-LD5-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" // 6. C++ link for executable w/ -mzos-hlq-clang= // RUN: %clangxx -### --target=s390x-ibm-zos %s 2>&1 \ @@ -120,4 +120,4 @@ // CXX-LD6-SAME: "//'AAAA.SCEELIB(CRTDQCXA)'" // CXX-LD6-SAME: "//'AAAA.SCEELIB(CRTDQXLA)'" // CXX-LD6-SAME: "//'AAAA.SCEELIB(CRTDQUNW)'" -// CXX-LD6-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" +// CXX-LD6-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" diff --git a/flang/test/Driver/msvc-dependent-lib-flags.f90 b/flang/test/Driver/msvc-dependent-lib-flags.f90 index 7c1f962e339f..643dbe9e949c 100644 --- a/flang/test/Driver/msvc-dependent-lib-flags.f90 +++ b/flang/test/Driver/msvc-dependent-lib-flags.f90 @@ -4,7 +4,7 @@ ! RUN: %flang -### --target=aarch64-windows-msvc -fms-runtime-lib=dll_dbg %S/Inputs/hello.f90 -v 2>&1 | FileCheck %s --check-prefixes=MSVC-DLL-DEBUG ! MSVC: -fc1 -! MSVC-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib +! MSVC-SAME: --dependent-lib=clang_rt.builtins.lib ! MSVC-SAME: -D_MT ! MSVC-SAME: --dependent-lib=libcmt ! MSVC-SAME: --dependent-lib=Fortran_main.static.lib @@ -12,7 +12,7 @@ ! MSVC-SAME: --dependent-lib=FortranDecimal.static.lib ! MSVC-DEBUG: -fc1 -! MSVC-DEBUG-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib +! MSVC-DEBUG-SAME: --dependent-lib=clang_rt.builtins.lib ! MSVC-DEBUG-SAME: -D_MT ! MSVC-DEBUG-SAME: -D_DEBUG ! MSVC-DEBUG-SAME: --dependent-lib=libcmtd @@ -21,7 +21,7 @@ ! MSVC-DEBUG-SAME: --dependent-lib=FortranDecimal.static_dbg.lib ! MSVC-DLL: -fc1 -! MSVC-DLL-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib +! MSVC-DLL-SAME: --dependent-lib=clang_rt.builtins.lib ! MSVC-DLL-SAME: -D_MT ! MSVC-DLL-SAME: -D_DLL ! MSVC-DLL-SAME: --dependent-lib=msvcrt @@ -30,7 +30,7 @@ ! MSVC-DLL-SAME: --dependent-lib=FortranDecimal.dynamic.lib ! MSVC-DLL-DEBUG: -fc1 -! MSVC-DLL-DEBUG-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib +! MSVC-DLL-DEBUG-SAME: --dependent-lib=clang_rt.builtins.lib ! MSVC-DLL-DEBUG-SAME: -D_MT ! MSVC-DLL-DEBUG-SAME: -D_DEBUG ! MSVC-DLL-DEBUG-SAME: -D_DLL -- GitLab From ec1af63dde58c735fe60d6f2aafdb10fa93f410d Mon Sep 17 00:00:00 2001 From: Alexandre Ganea <37383324+aganea@users.noreply.github.com> Date: Mon, 8 Apr 2024 20:02:19 -0400 Subject: [PATCH 218/695] [Codegen][X86] Fix /HOTPATCH with clang-cl and inline asm (#87639) This fixes an edge case where functions starting with inline assembly would assert while trying to lower that inline asm instruction. After this PR, for now we always add a no-op (xchgw in this case) without considering the size of the next inline asm instruction. We might want to revisit this in the future. This fixes Unreal Engine 5.3.2 compilation with clang-cl and /HOTPATCH. Should close https://github.com/llvm/llvm-project/issues/56234 --- llvm/lib/Target/X86/X86MCInstLower.cpp | 4 +++- llvm/test/CodeGen/X86/patchable-prologue.ll | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index e2330ff34c17..e6510be6b9af 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -980,8 +980,10 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, SmallString<256> Code; unsigned MinSize = MI.getOperand(0).getImm(); - if (NextMI != MI.getParent()->end()) { + if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) { // Lower the next MachineInstr to find its byte size. + // If the next instruction is inline assembly, we skip lowering it for now, + // and assume we should always generate NOPs. MCInst MCI; MCIL.Lower(&*NextMI, MCI); diff --git a/llvm/test/CodeGen/X86/patchable-prologue.ll b/llvm/test/CodeGen/X86/patchable-prologue.ll index 71a392845fde..43761e3d1e1e 100644 --- a/llvm/test/CodeGen/X86/patchable-prologue.ll +++ b/llvm/test/CodeGen/X86/patchable-prologue.ll @@ -193,3 +193,20 @@ do.body: ; preds = %do.body, %entry do.end: ; preds = %do.body ret void } + + +; Test that inline asm is properly hotpatched. We currently don't examine the +; asm instruction when printing it, thus we always emit patching NOPs. + +; 64: inline_asm: +; 64-NEXT: # %bb.0: +; 64-NEXT: xchgw %ax, %ax # encoding: [0x66,0x90] +; 64-NEXT: #APP +; 64-NEXT: int3 # encoding: [0xcc] +; 64-NEXT: #NO_APP + +define dso_local void @inline_asm() "patchable-function"="prologue-short-redirect" { +entry: + call void asm sideeffect "int3", "~{dirflag},~{fpsr},~{flags}"() + ret void +} -- GitLab From 5bc87dac75762027e614da31b968c67a94f0e7b1 Mon Sep 17 00:00:00 2001 From: Evgenii Stepanov Date: Mon, 8 Apr 2024 17:01:24 -0700 Subject: [PATCH 219/695] Revert "Overflow and saturating intrinsics (#88068)" This reverts commit 118a5d8236d8a483dd401fa35c8b1fcd058eacc1. --- .../Instrumentation/MemorySanitizer.cpp | 29 ----- .../MemorySanitizer/overflow.ll | 103 ++++++++++++------ .../MemorySanitizer/saturating.ll | 21 ++-- 3 files changed, 75 insertions(+), 78 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index b92d358b4aa1..46b9181c8922 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -3715,37 +3715,8 @@ struct MemorySanitizerVisitor : public InstVisitor { setOrigin(&I, getOrigin(&I, 0)); } - void handleArithmeticWithOverflow(IntrinsicInst &I) { - IRBuilder<> IRB(&I); - Value *Shadow0 = IRB.CreateOr(getShadow(&I, 0), getShadow(&I, 1)); - Value *Shadow1 = IRB.CreateICmpNE(Shadow0, getCleanShadow(Shadow0)); - - Value *Shadow = PoisonValue::get(getShadowTy(&I)); - Shadow = IRB.CreateInsertValue(Shadow, Shadow0, 0); - Shadow = IRB.CreateInsertValue(Shadow, Shadow1, 1); - - setShadow(&I, Shadow); - setOriginForNaryOp(I); - } - void visitIntrinsicInst(IntrinsicInst &I) { switch (I.getIntrinsicID()) { - case Intrinsic::uadd_with_overflow: - case Intrinsic::sadd_with_overflow: - case Intrinsic::usub_with_overflow: - case Intrinsic::ssub_with_overflow: - case Intrinsic::umul_with_overflow: - case Intrinsic::smul_with_overflow: - handleArithmeticWithOverflow(I); - break; - case Intrinsic::sadd_sat: - case Intrinsic::uadd_sat: - case Intrinsic::ssub_sat: - case Intrinsic::usub_sat: - case Intrinsic::sshl_sat: - case Intrinsic::ushl_sat: - handleShadowOr(I); - break; case Intrinsic::abs: handleAbsIntrinsic(I); break; diff --git a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll index 0cfae0008263..b1304faec3df 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll @@ -10,12 +10,16 @@ define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) @@ -28,12 +32,16 @@ define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) @@ -46,12 +54,16 @@ define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) @@ -63,12 +75,16 @@ define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) @@ -80,12 +96,16 @@ define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) @@ -97,12 +117,16 @@ define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) @@ -115,12 +139,18 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { <4 x i32>, <4 x i1> } poison, <4 x i32> [[TMP3]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { <4 x i32>, <4 x i1> } [[TMP5]], <4 x i1> [[TMP4]], 1 +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] +; CHECK: 5: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store { <4 x i32>, <4 x i1> } [[TMP6]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] ; %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) @@ -128,3 +158,6 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32 } attributes #0 = { sanitize_memory } +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} +;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll index b707b3160d9e..dcd8a080144b 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll @@ -11,9 +11,8 @@ define i64 @test_sadd_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.sadd.sat(i64 %a, i64 %b) @@ -27,9 +26,8 @@ define i64 @test_uadd_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.uadd.sat(i64 %a, i64 %b) @@ -43,9 +41,8 @@ define i64 @test_ssub_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.ssub.sat(i64 %a, i64 %b) @@ -59,9 +56,8 @@ define i64 @test_usub_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.usub.sat(i64 %a, i64 %b) @@ -75,9 +71,8 @@ define i64 @test_sshl_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.sshl.sat(i64 %a, i64 %b) @@ -91,9 +86,8 @@ define i64 @test_ushl_sat(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0 ; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i64 [[RES]] ; %res = call i64 @llvm.ushl.sat(i64 %a, i64 %b) @@ -107,9 +101,8 @@ define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 { ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b) -- GitLab From 3b74f8c1de72aa90445249f55923690301da024a Mon Sep 17 00:00:00 2001 From: Evgenii Stepanov Date: Mon, 8 Apr 2024 17:01:43 -0700 Subject: [PATCH 220/695] Revert "[msan] Precommit tests." This reverts commit 79343fa8c3575be12ec4d543f4aebebd1ba4f47f. --- .../MemorySanitizer/overflow.ll | 163 ------------------ .../MemorySanitizer/saturating.ll | 113 ------------ 2 files changed, 276 deletions(-) delete mode 100644 llvm/test/Instrumentation/MemorySanitizer/overflow.ll delete mode 100644 llvm/test/Instrumentation/MemorySanitizer/saturating.ll diff --git a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll deleted file mode 100644 index b1304faec3df..000000000000 --- a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll +++ /dev/null @@ -1,163 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s - -target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-unknown-linux-gnu" - -define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define { i64, i1 } @test_sadd_with_overflow( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] -; CHECK-NEXT: unreachable -; CHECK: 4: -; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { i64, i1 } [[RES]] -; - %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) - ret { i64, i1 } %res -} - -define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define { i64, i1 } @test_uadd_with_overflow( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: -; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { i64, i1 } [[RES]] -; - %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) - ret { i64, i1 } %res -} - -define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define { i64, i1 } @test_smul_with_overflow( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: -; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { i64, i1 } [[RES]] -; - %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) - ret { i64, i1 } %res -} -define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define { i64, i1 } @test_umul_with_overflow( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: -; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { i64, i1 } [[RES]] -; - %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) - ret { i64, i1 } %res -} -define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define { i64, i1 } @test_ssub_with_overflow( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: -; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { i64, i1 } [[RES]] -; - %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) - ret { i64, i1 } %res -} -define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define { i64, i1 } @test_usub_with_overflow( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: -; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { i64, i1 } [[RES]] -; - %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) - ret { i64, i1 } %res -} - -define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32> %b) #0 { -; CHECK-LABEL: define { <4 x i32>, <4 x i1> } @test_sadd_with_overflow_vec( -; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] -; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 6: -; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] -; - %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) - ret { <4 x i32>, <4 x i1> } %res -} - -attributes #0 = { sanitize_memory } -;. -; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} -;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll deleted file mode 100644 index dcd8a080144b..000000000000 --- a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll +++ /dev/null @@ -1,113 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s - -target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-unknown-linux-gnu" - -define i64 @test_sadd_sat(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define i64 @test_sadd_sat( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret i64 [[RES]] -; - %res = call i64 @llvm.sadd.sat(i64 %a, i64 %b) - ret i64 %res -} - -define i64 @test_uadd_sat(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define i64 @test_uadd_sat( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret i64 [[RES]] -; - %res = call i64 @llvm.uadd.sat(i64 %a, i64 %b) - ret i64 %res -} - -define i64 @test_ssub_sat(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define i64 @test_ssub_sat( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret i64 [[RES]] -; - %res = call i64 @llvm.ssub.sat(i64 %a, i64 %b) - ret i64 %res -} - -define i64 @test_usub_sat(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define i64 @test_usub_sat( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret i64 [[RES]] -; - %res = call i64 @llvm.usub.sat(i64 %a, i64 %b) - ret i64 %res -} - -define i64 @test_sshl_sat(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define i64 @test_sshl_sat( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret i64 [[RES]] -; - %res = call i64 @llvm.sshl.sat(i64 %a, i64 %b) - ret i64 %res -} - -define i64 @test_ushl_sat(i64 %a, i64 %b) #0 { -; CHECK-LABEL: define i64 @test_ushl_sat( -; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret i64 [[RES]] -; - %res = call i64 @llvm.ushl.sat(i64 %a, i64 %b) - ret i64 %res -} - -define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 { -; CHECK-LABEL: define <4 x i32> @test_sadd_sat_vec( -; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 -; CHECK-NEXT: ret <4 x i32> [[RES]] -; - %res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b) - ret <4 x i32> %res -} - - -attributes #0 = { sanitize_memory } -- GitLab From be006372f3bbcab1e2e51af93dd3302398dac9a4 Mon Sep 17 00:00:00 2001 From: Andrei Golubev Date: Tue, 9 Apr 2024 03:08:32 +0300 Subject: [PATCH 221/695] [mlir][OpPrintingFlags] Allow to disable ElementsAttr hex printing (#85766) At present, large ElementsAttr is unconditionally printed with a hex string. This means that in IR large constant values often look like: dense<"0x000000000004000000080000000004000000080000000..."> : tensor<10x10xi32> Hoisting hex printing control to the user level for tooling means that one can disable the feature and get human-readable values when necessary: dense<[16, 32, 48, 500...]> : tensor<10x10xi32> Note: AsmPrinterOptions::printElementsAttrWithHexIfLarger is not always possible to be used as it requires that one exposes MLIR's command-line options in user tooling (including an actual compiler). Co-authored-by: Harald Rotuna --- mlir/include/mlir/IR/OperationSupport.h | 17 ++++++++++ mlir/lib/IR/AsmPrinter.cpp | 43 +++++++++++++------------ 2 files changed, 40 insertions(+), 20 deletions(-) diff --git a/mlir/include/mlir/IR/OperationSupport.h b/mlir/include/mlir/IR/OperationSupport.h index 90e63ff8fcb3..2c1c490aac49 100644 --- a/mlir/include/mlir/IR/OperationSupport.h +++ b/mlir/include/mlir/IR/OperationSupport.h @@ -1136,6 +1136,13 @@ public: /// elements. OpPrintingFlags &elideLargeElementsAttrs(int64_t largeElementLimit = 16); + /// Enables the printing of large element attributes with a hex string. The + /// `largeElementLimit` is used to configure what is considered to be a + /// "large" ElementsAttr by providing an upper limit to the number of + /// elements. Use -1 to disable the hex printing. + OpPrintingFlags & + printLargeElementsAttrWithHex(int64_t largeElementLimit = 100); + /// Enables the elision of large resources strings by omitting them from the /// `dialect_resources` section. The `largeResourceLimit` is used to configure /// what is considered to be a "large" resource by providing an upper limit to @@ -1169,9 +1176,15 @@ public: /// Return if the given ElementsAttr should be elided. bool shouldElideElementsAttr(ElementsAttr attr) const; + /// Return if the given ElementsAttr should be printed as hex string. + bool shouldPrintElementsAttrWithHex(ElementsAttr attr) const; + /// Return the size limit for printing large ElementsAttr. std::optional getLargeElementsAttrLimit() const; + /// Return the size limit for printing large ElementsAttr as hex string. + int64_t getLargeElementsAttrHexLimit() const; + /// Return the size limit in chars for printing large resources. std::optional getLargeResourceStringLimit() const; @@ -1204,6 +1217,10 @@ private: /// Elide printing large resources based on size of string. std::optional resourceStringCharLimit; + /// Print large element attributes with hex strings if the number of elements + /// is larger than the upper limit. + int64_t elementsAttrHexElementLimit = 100; + /// Print debug information. bool printDebugInfoFlag : 1; bool printDebugInfoPrettyFormFlag : 1; diff --git a/mlir/lib/IR/AsmPrinter.cpp b/mlir/lib/IR/AsmPrinter.cpp index 456cf6a2c277..e915b97d9ff1 100644 --- a/mlir/lib/IR/AsmPrinter.cpp +++ b/mlir/lib/IR/AsmPrinter.cpp @@ -212,6 +212,9 @@ OpPrintingFlags::OpPrintingFlags() return; if (clOptions->elideElementsAttrIfLarger.getNumOccurrences()) elementsAttrElementLimit = clOptions->elideElementsAttrIfLarger; + if (clOptions->printElementsAttrWithHexIfLarger.getNumOccurrences()) + elementsAttrHexElementLimit = + clOptions->printElementsAttrWithHexIfLarger.getValue(); if (clOptions->elideResourceStringsIfLarger.getNumOccurrences()) resourceStringCharLimit = clOptions->elideResourceStringsIfLarger; printDebugInfoFlag = clOptions->printDebugInfoOpt; @@ -233,6 +236,12 @@ OpPrintingFlags::elideLargeElementsAttrs(int64_t largeElementLimit) { return *this; } +OpPrintingFlags & +OpPrintingFlags::printLargeElementsAttrWithHex(int64_t largeElementLimit) { + elementsAttrHexElementLimit = largeElementLimit; + return *this; +} + OpPrintingFlags & OpPrintingFlags::elideLargeResourceString(int64_t largeResourceLimit) { resourceStringCharLimit = largeResourceLimit; @@ -287,11 +296,24 @@ bool OpPrintingFlags::shouldElideElementsAttr(ElementsAttr attr) const { !llvm::isa(attr); } +/// Return if the given ElementsAttr should be printed as hex string. +bool OpPrintingFlags::shouldPrintElementsAttrWithHex(ElementsAttr attr) const { + // -1 is used to disable hex printing. + return (elementsAttrHexElementLimit != -1) && + (elementsAttrHexElementLimit < int64_t(attr.getNumElements())) && + !llvm::isa(attr); +} + /// Return the size limit for printing large ElementsAttr. std::optional OpPrintingFlags::getLargeElementsAttrLimit() const { return elementsAttrElementLimit; } +/// Return the size limit for printing large ElementsAttr as hex string. +int64_t OpPrintingFlags::getLargeElementsAttrHexLimit() const { + return elementsAttrHexElementLimit; +} + /// Return the size limit for printing large ElementsAttr. std::optional OpPrintingFlags::getLargeResourceStringLimit() const { return resourceStringCharLimit; @@ -328,23 +350,6 @@ bool OpPrintingFlags::shouldPrintValueUsers() const { return printValueUsersFlag; } -/// Returns true if an ElementsAttr with the given number of elements should be -/// printed with hex. -static bool shouldPrintElementsAttrWithHex(int64_t numElements) { - // Check to see if a command line option was provided for the limit. - if (clOptions.isConstructed()) { - if (clOptions->printElementsAttrWithHexIfLarger.getNumOccurrences()) { - // -1 is used to disable hex printing. - if (clOptions->printElementsAttrWithHexIfLarger == -1) - return false; - return numElements > clOptions->printElementsAttrWithHexIfLarger; - } - } - - // Otherwise, default to printing with hex if the number of elements is >100. - return numElements > 100; -} - //===----------------------------------------------------------------------===// // NewLineCounter //===----------------------------------------------------------------------===// @@ -2435,9 +2440,7 @@ void AsmPrinter::Impl::printDenseIntOrFPElementsAttr( auto elementType = type.getElementType(); // Check to see if we should format this attribute as a hex string. - auto numElements = type.getNumElements(); - if (!attr.isSplat() && allowHex && - shouldPrintElementsAttrWithHex(numElements)) { + if (allowHex && printerFlags.shouldPrintElementsAttrWithHex(attr)) { ArrayRef rawData = attr.getRawData(); if (llvm::endianness::native == llvm::endianness::big) { // Convert endianess in big-endian(BE) machines. `rawData` is BE in BE -- GitLab From b2f8172d721d9e1cdaf052155aea880d731b1bf7 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Tue, 9 Apr 2024 00:16:50 +0000 Subject: [PATCH 222/695] [gn build] Port 27b2d7d4bb79 --- llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn index 2f43a915b2a6..9f7749d6847c 100644 --- a/llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/InstallAPI/BUILD.gn @@ -8,6 +8,7 @@ static_library("InstallAPI") { "//llvm/lib/TextAPI", ] sources = [ + "DiagnosticBuilderWrappers.cpp", "DylibVerifier.cpp", "FileList.cpp", "Frontend.cpp", -- GitLab From 65c57bf2429e395aed811c05f35d28a6123a5965 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Tue, 9 Apr 2024 00:16:51 +0000 Subject: [PATCH 223/695] [gn build] Port 7a4e89761a13 --- .../gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn index da3a37d46153..adcebcab7ef7 100644 --- a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn +++ b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/utils/BUILD.gn @@ -13,6 +13,7 @@ static_library("utils") { sources = [ "ASTUtils.cpp", "Aliasing.cpp", + "BracesAroundStatement.cpp", "DeclRefExprUtils.cpp", "DesignatedInitializers.cpp", "ExceptionAnalyzer.cpp", -- GitLab From 1c4ec8def6bb18934f300f6e630e92e7efdb60be Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Tue, 9 Apr 2024 00:16:52 +0000 Subject: [PATCH 224/695] [gn build] Port d2884444472e --- llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn index b03032300a76..e9ba5fb132b0 100644 --- a/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Sema/BUILD.gn @@ -54,6 +54,7 @@ static_library("Sema") { "SemaAccess.cpp", "SemaAttr.cpp", "SemaAvailability.cpp", + "SemaBase.cpp", "SemaCUDA.cpp", "SemaCXXScopeSpec.cpp", "SemaCast.cpp", -- GitLab From 064634406277e4786ce12caac94f7fa57ed5973e Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Mon, 8 Apr 2024 17:23:47 -0700 Subject: [PATCH 225/695] [HWASAN][UBSAN] Reverse random logic (#88070) It feels more intuitive to make higher P to keep more checks. --- .../Instrumentation/HWAddressSanitizer.cpp | 6 +- .../Instrumentation/LowerAllowCheckPass.cpp | 4 +- .../HWAddressSanitizer/pgo-opt-out.ll | 12 +- .../Transforms/lower-builtin-allow-check.ll | 154 +++++++++--------- 4 files changed, 88 insertions(+), 88 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp index ad1cd9c1f6bf..82f60f4feed4 100644 --- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp @@ -186,9 +186,9 @@ static cl::opt ClHotPercentileCutoff("hwasan-percentile-cutoff-hot", cl::desc("Hot percentile cuttoff.")); static cl::opt - ClRandomSkipRate("hwasan-random-skip-rate", + ClRandomSkipRate("hwasan-random-rate", cl::desc("Probability value in the range [0.0, 1.0] " - "to skip instrumentation of a function.")); + "to keep instrumentation of a function.")); STATISTIC(NumTotalFuncs, "Number of total funcs"); STATISTIC(NumInstrumentedFuncs, "Number of instrumented funcs"); @@ -1496,7 +1496,7 @@ bool HWAddressSanitizer::selectiveInstrumentationShouldSkip( Function &F, FunctionAnalysisManager &FAM) const { if (ClRandomSkipRate.getNumOccurrences()) { std::bernoulli_distribution D(ClRandomSkipRate); - return (D(*Rng)); + return !D(*Rng); } if (!ClHotPercentileCutoff.getNumOccurrences()) return false; diff --git a/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp b/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp index 54b63278e9dd..cdc8318f088c 100644 --- a/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp +++ b/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp @@ -30,7 +30,7 @@ static cl::opt static cl::opt RandomRate("lower-allow-check-random-rate", cl::desc("Probability value in the range [0.0, 1.0] of " - "unconditional pseudo-random checks removal.")); + "unconditional pseudo-random checks.")); STATISTIC(NumChecksTotal, "Number of checks"); STATISTIC(NumChecksRemoved, "Number of removed checks"); @@ -48,7 +48,7 @@ static bool removeUbsanTraps(Function &F, const BlockFrequencyInfo &BFI, if (!Rng) Rng = F.getParent()->createRNG(F.getName()); std::bernoulli_distribution D(RandomRate); - return D(*Rng); + return !D(*Rng); }; for (BasicBlock &BB : F) { diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll b/llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll index ab3f56dbee9e..f2661a02da7a 100644 --- a/llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/pgo-opt-out.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -passes='require,hwasan' -S -hwasan-percentile-cutoff-hot=700000 | FileCheck %s --check-prefix=HOT70 ; RUN: opt < %s -passes='require,hwasan' -S -hwasan-percentile-cutoff-hot=990000 | FileCheck %s --check-prefix=HOT99 -; RUN: opt < %s -passes='require,hwasan' -S -hwasan-random-skip-rate=0.0 | FileCheck %s --check-prefix=RANDOM0 -; RUN: opt < %s -passes='require,hwasan' -S -hwasan-random-skip-rate=1.0 | FileCheck %s --check-prefix=RANDOM1 +; RUN: opt < %s -passes='require,hwasan' -S -hwasan-random-rate=1.0 | FileCheck %s --check-prefix=ALL +; RUN: opt < %s -passes='require,hwasan' -S -hwasan-random-rate=0.0 | FileCheck %s --check-prefix=NONE ; HOT70: @sanitized ; HOT70-NEXT: @__hwasan_tls @@ -9,11 +9,11 @@ ; HOT99: @sanitized ; HOT99-NEXT: %x = alloca i8, i64 4 -; RANDOM0: @sanitized -; RANDOM0-NEXT: @__hwasan_tls +; ALL: @sanitized +; ALL-NEXT: @__hwasan_tls -; RANDOM1: @sanitized -; RANDOM1-NEXT: %x = alloca i8, i64 4 +; NONE: @sanitized +; NONE-NEXT: %x = alloca i8, i64 4 declare void @use(ptr) diff --git a/llvm/test/Transforms/lower-builtin-allow-check.ll b/llvm/test/Transforms/lower-builtin-allow-check.ll index a9f4e200c42c..05d940a46716 100644 --- a/llvm/test/Transforms/lower-builtin-allow-check.ll +++ b/llvm/test/Transforms/lower-builtin-allow-check.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes='function(lower-allow-check)' -S | FileCheck %s --check-prefixes=NOPROFILE -; RUN: opt < %s -passes='function(lower-allow-check)' -lower-allow-check-random-rate=1 -S | FileCheck %s --check-prefixes=ALL +; RUN: opt < %s -passes='function(lower-allow-check)' -lower-allow-check-random-rate=0 -S | FileCheck %s --check-prefixes=NONE ; RUN: opt < %s -passes='require,function(lower-allow-check)' -lower-allow-check-percentile-cutoff-hot=990000 -S | FileCheck %s --check-prefixes=HOT99 ; RUN: opt < %s -passes='require,function(lower-allow-check)' -lower-allow-check-percentile-cutoff-hot=700000 -S | FileCheck %s --check-prefixes=HOT70 @@ -23,18 +23,18 @@ define dso_local noundef i32 @simple(ptr noundef readonly %0) { ; NOPROFILE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 ; NOPROFILE-NEXT: ret i32 [[TMP5]] ; -; ALL-LABEL: define dso_local noundef i32 @simple( -; ALL-SAME: ptr noundef readonly [[TMP0:%.*]]) { -; ALL-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0]], null -; ALL-NEXT: [[HOT:%.*]] = xor i1 false, true -; ALL-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[HOT]] -; ALL-NEXT: br i1 [[TMP6]], label [[TMP3:%.*]], label [[TMP4:%.*]] -; ALL: 3: -; ALL-NEXT: tail call void @llvm.ubsantrap(i8 22) -; ALL-NEXT: unreachable -; ALL: 4: -; ALL-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 -; ALL-NEXT: ret i32 [[TMP5]] +; NONE-LABEL: define dso_local noundef i32 @simple( +; NONE-SAME: ptr noundef readonly [[TMP0:%.*]]) { +; NONE-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0]], null +; NONE-NEXT: [[HOT:%.*]] = xor i1 false, true +; NONE-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[HOT]] +; NONE-NEXT: br i1 [[TMP6]], label [[TMP3:%.*]], label [[TMP4:%.*]] +; NONE: 3: +; NONE-NEXT: tail call void @llvm.ubsantrap(i8 22) +; NONE-NEXT: unreachable +; NONE: 4: +; NONE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 +; NONE-NEXT: ret i32 [[TMP5]] ; ; HOT99-LABEL: define dso_local noundef i32 @simple( ; HOT99-SAME: ptr noundef readonly [[TMP0:%.*]]) { @@ -92,18 +92,18 @@ define dso_local noundef i32 @hot(ptr noundef readonly %0) !prof !36 { ; NOPROFILE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 ; NOPROFILE-NEXT: ret i32 [[TMP5]] ; -; ALL-LABEL: define dso_local noundef i32 @hot( -; ALL-SAME: ptr noundef readonly [[TMP0:%.*]]) !prof [[PROF16:![0-9]+]] { -; ALL-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0]], null -; ALL-NEXT: [[HOT:%.*]] = xor i1 false, true -; ALL-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[HOT]] -; ALL-NEXT: br i1 [[TMP6]], label [[TMP3:%.*]], label [[TMP4:%.*]] -; ALL: 3: -; ALL-NEXT: tail call void @llvm.ubsantrap(i8 22) -; ALL-NEXT: unreachable -; ALL: 4: -; ALL-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 -; ALL-NEXT: ret i32 [[TMP5]] +; NONE-LABEL: define dso_local noundef i32 @hot( +; NONE-SAME: ptr noundef readonly [[TMP0:%.*]]) !prof [[PROF16:![0-9]+]] { +; NONE-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0]], null +; NONE-NEXT: [[HOT:%.*]] = xor i1 false, true +; NONE-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[HOT]] +; NONE-NEXT: br i1 [[TMP6]], label [[TMP3:%.*]], label [[TMP4:%.*]] +; NONE: 3: +; NONE-NEXT: tail call void @llvm.ubsantrap(i8 22) +; NONE-NEXT: unreachable +; NONE: 4: +; NONE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 +; NONE-NEXT: ret i32 [[TMP5]] ; ; HOT99-LABEL: define dso_local noundef i32 @hot( ; HOT99-SAME: ptr noundef readonly [[TMP0:%.*]]) !prof [[PROF16:![0-9]+]] { @@ -160,18 +160,18 @@ define dso_local noundef i32 @veryHot(ptr noundef readonly %0) !prof !39 { ; NOPROFILE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 ; NOPROFILE-NEXT: ret i32 [[TMP5]] ; -; ALL-LABEL: define dso_local noundef i32 @veryHot( -; ALL-SAME: ptr noundef readonly [[TMP0:%.*]]) !prof [[PROF17:![0-9]+]] { -; ALL-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0]], null -; ALL-NEXT: [[HOT:%.*]] = xor i1 false, true -; ALL-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[HOT]] -; ALL-NEXT: br i1 [[TMP6]], label [[TMP3:%.*]], label [[TMP4:%.*]] -; ALL: 3: -; ALL-NEXT: tail call void @llvm.ubsantrap(i8 22) -; ALL-NEXT: unreachable -; ALL: 4: -; ALL-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 -; ALL-NEXT: ret i32 [[TMP5]] +; NONE-LABEL: define dso_local noundef i32 @veryHot( +; NONE-SAME: ptr noundef readonly [[TMP0:%.*]]) !prof [[PROF17:![0-9]+]] { +; NONE-NEXT: [[TMP2:%.*]] = icmp eq ptr [[TMP0]], null +; NONE-NEXT: [[HOT:%.*]] = xor i1 false, true +; NONE-NEXT: [[TMP6:%.*]] = or i1 [[TMP2]], [[HOT]] +; NONE-NEXT: br i1 [[TMP6]], label [[TMP3:%.*]], label [[TMP4:%.*]] +; NONE: 3: +; NONE-NEXT: tail call void @llvm.ubsantrap(i8 22) +; NONE-NEXT: unreachable +; NONE: 4: +; NONE-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 +; NONE-NEXT: ret i32 [[TMP5]] ; ; HOT99-LABEL: define dso_local noundef i32 @veryHot( ; HOT99-SAME: ptr noundef readonly [[TMP0:%.*]]) !prof [[PROF17:![0-9]+]] { @@ -235,24 +235,24 @@ define dso_local noundef i32 @branchColdFnHot(i32 noundef %0, ptr noundef readon ; NOPROFILE-NEXT: [[TMP10:%.*]] = phi i32 [ [[TMP8]], [[TMP7]] ], [ 0, [[TMP2:%.*]] ] ; NOPROFILE-NEXT: ret i32 [[TMP10]] ; -; ALL-LABEL: define dso_local noundef i32 @branchColdFnHot( -; ALL-SAME: i32 noundef [[TMP0:%.*]], ptr noundef readonly [[TMP1:%.*]]) !prof [[PROF17]] { -; ALL-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP0]], 0 -; ALL-NEXT: br i1 [[TMP3]], label [[TMP9:%.*]], label [[TMP4:%.*]], !prof [[PROF18:![0-9]+]] -; ALL: 4: -; ALL-NEXT: [[TMP5:%.*]] = icmp eq ptr [[TMP1]], null -; ALL-NEXT: [[HOT:%.*]] = xor i1 false, true -; ALL-NEXT: [[TMP11:%.*]] = or i1 [[TMP5]], [[HOT]] -; ALL-NEXT: br i1 [[TMP11]], label [[TMP6:%.*]], label [[TMP7:%.*]] -; ALL: 6: -; ALL-NEXT: tail call void @llvm.ubsantrap(i8 22) -; ALL-NEXT: unreachable -; ALL: 7: -; ALL-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP1]], align 4 -; ALL-NEXT: br label [[TMP9]] -; ALL: 9: -; ALL-NEXT: [[TMP10:%.*]] = phi i32 [ [[TMP8]], [[TMP7]] ], [ 0, [[TMP2:%.*]] ] -; ALL-NEXT: ret i32 [[TMP10]] +; NONE-LABEL: define dso_local noundef i32 @branchColdFnHot( +; NONE-SAME: i32 noundef [[TMP0:%.*]], ptr noundef readonly [[TMP1:%.*]]) !prof [[PROF17]] { +; NONE-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP0]], 0 +; NONE-NEXT: br i1 [[TMP3]], label [[TMP9:%.*]], label [[TMP4:%.*]], !prof [[PROF18:![0-9]+]] +; NONE: 4: +; NONE-NEXT: [[TMP5:%.*]] = icmp eq ptr [[TMP1]], null +; NONE-NEXT: [[HOT:%.*]] = xor i1 false, true +; NONE-NEXT: [[TMP11:%.*]] = or i1 [[TMP5]], [[HOT]] +; NONE-NEXT: br i1 [[TMP11]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; NONE: 6: +; NONE-NEXT: tail call void @llvm.ubsantrap(i8 22) +; NONE-NEXT: unreachable +; NONE: 7: +; NONE-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP1]], align 4 +; NONE-NEXT: br label [[TMP9]] +; NONE: 9: +; NONE-NEXT: [[TMP10:%.*]] = phi i32 [ [[TMP8]], [[TMP7]] ], [ 0, [[TMP2:%.*]] ] +; NONE-NEXT: ret i32 [[TMP10]] ; ; HOT99-LABEL: define dso_local noundef i32 @branchColdFnHot( ; HOT99-SAME: i32 noundef [[TMP0:%.*]], ptr noundef readonly [[TMP1:%.*]]) !prof [[PROF17]] { @@ -335,24 +335,24 @@ define dso_local noundef i32 @branchHotFnCold(i32 noundef %0, ptr noundef readon ; NOPROFILE-NEXT: [[TMP10:%.*]] = phi i32 [ [[TMP8]], [[TMP7]] ], [ 0, [[TMP2:%.*]] ] ; NOPROFILE-NEXT: ret i32 [[TMP10]] ; -; ALL-LABEL: define dso_local noundef i32 @branchHotFnCold( -; ALL-SAME: i32 noundef [[TMP0:%.*]], ptr noundef readonly [[TMP1:%.*]]) !prof [[PROF16]] { -; ALL-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP0]], 0 -; ALL-NEXT: br i1 [[TMP3]], label [[TMP9:%.*]], label [[TMP4:%.*]], !prof [[PROF19:![0-9]+]] -; ALL: 4: -; ALL-NEXT: [[TMP5:%.*]] = icmp eq ptr [[TMP1]], null -; ALL-NEXT: [[HOT:%.*]] = xor i1 false, true -; ALL-NEXT: [[TMP11:%.*]] = or i1 [[TMP5]], [[HOT]] -; ALL-NEXT: br i1 [[TMP11]], label [[TMP6:%.*]], label [[TMP7:%.*]] -; ALL: 6: -; ALL-NEXT: tail call void @llvm.ubsantrap(i8 22) -; ALL-NEXT: unreachable -; ALL: 7: -; ALL-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP1]], align 4 -; ALL-NEXT: br label [[TMP9]] -; ALL: 9: -; ALL-NEXT: [[TMP10:%.*]] = phi i32 [ [[TMP8]], [[TMP7]] ], [ 0, [[TMP2:%.*]] ] -; ALL-NEXT: ret i32 [[TMP10]] +; NONE-LABEL: define dso_local noundef i32 @branchHotFnCold( +; NONE-SAME: i32 noundef [[TMP0:%.*]], ptr noundef readonly [[TMP1:%.*]]) !prof [[PROF16]] { +; NONE-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP0]], 0 +; NONE-NEXT: br i1 [[TMP3]], label [[TMP9:%.*]], label [[TMP4:%.*]], !prof [[PROF19:![0-9]+]] +; NONE: 4: +; NONE-NEXT: [[TMP5:%.*]] = icmp eq ptr [[TMP1]], null +; NONE-NEXT: [[HOT:%.*]] = xor i1 false, true +; NONE-NEXT: [[TMP11:%.*]] = or i1 [[TMP5]], [[HOT]] +; NONE-NEXT: br i1 [[TMP11]], label [[TMP6:%.*]], label [[TMP7:%.*]] +; NONE: 6: +; NONE-NEXT: tail call void @llvm.ubsantrap(i8 22) +; NONE-NEXT: unreachable +; NONE: 7: +; NONE-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP1]], align 4 +; NONE-NEXT: br label [[TMP9]] +; NONE: 9: +; NONE-NEXT: [[TMP10:%.*]] = phi i32 [ [[TMP8]], [[TMP7]] ], [ 0, [[TMP2:%.*]] ] +; NONE-NEXT: ret i32 [[TMP10]] ; ; HOT99-LABEL: define dso_local noundef i32 @branchHotFnCold( ; HOT99-SAME: i32 noundef [[TMP0:%.*]], ptr noundef readonly [[TMP1:%.*]]) !prof [[PROF16]] { @@ -445,10 +445,10 @@ define dso_local noundef i32 @branchHotFnCold(i32 noundef %0, ptr noundef readon ; NOPROFILE: [[PROF18]] = !{!"branch_weights", i32 1000, i32 1} ; NOPROFILE: [[PROF19]] = !{!"branch_weights", i32 1, i32 1000} ;. -; ALL: [[PROF16]] = !{!"function_entry_count", i64 1000} -; ALL: [[PROF17]] = !{!"function_entry_count", i64 7000} -; ALL: [[PROF18]] = !{!"branch_weights", i32 1000, i32 1} -; ALL: [[PROF19]] = !{!"branch_weights", i32 1, i32 1000} +; NONE: [[PROF16]] = !{!"function_entry_count", i64 1000} +; NONE: [[PROF17]] = !{!"function_entry_count", i64 7000} +; NONE: [[PROF18]] = !{!"branch_weights", i32 1000, i32 1} +; NONE: [[PROF19]] = !{!"branch_weights", i32 1, i32 1000} ;. ; HOT99: [[PROF16]] = !{!"function_entry_count", i64 1000} ; HOT99: [[PROF17]] = !{!"function_entry_count", i64 7000} -- GitLab From 4a812b5912d3149592cae195c9007b05649d9b41 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Mon, 8 Apr 2024 17:47:57 -0700 Subject: [PATCH 226/695] Verify threadlocal_address constraints (#87841) Check invariants for `llvm.threadlocal.address` intrinsic in IR Verifier. --- llvm/docs/LangRef.rst | 2 +- llvm/lib/IR/Verifier.cpp | 8 ++++++++ .../HipStdPar/unsupported-thread-local-indirect-use.ll | 1 + mlir/test/Target/LLVMIR/Import/intrinsic.ll | 6 ++++-- mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir | 9 ++++++--- 5 files changed, 20 insertions(+), 6 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index a3722ecdf0c5..18fc46584d09 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -28120,7 +28120,7 @@ Syntax: Arguments: """""""""" -The first argument is a pointer, which refers to a thread local global. +The first argument is a thread local :ref:`global variable `. Semantics: """""""""" diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index e63efe98a2e2..4092f0cb12ff 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -6224,6 +6224,14 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) { &Call); break; } + case Intrinsic::threadlocal_address: { + const Value &Arg0 = *Call.getArgOperand(0); + Check(isa(Arg0), + "llvm.threadlocal.address first argument must be a GlobalVariable"); + Check(cast(Arg0).isThreadLocal(), + "llvm.threadlocal.address operand isThreadLocal() must no be false"); + break; + } }; // Verify that there aren't any unmediated control transfers between funclets. diff --git a/llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll b/llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll index 40014853d8ac..960828c76f78 100644 --- a/llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll +++ b/llvm/test/Transforms/HipStdPar/unsupported-thread-local-indirect-use.ll @@ -1,5 +1,6 @@ ; RUN: not opt -S -mtriple=amdgcn-amd-amdhsa -passes=hipstdpar-select-accelerator-code \ ; RUN: %s 2>&1 | FileCheck %s +; XFAIL: * @tls = hidden thread_local addrspace(1) global i32 0, align 4 diff --git a/mlir/test/Target/LLVMIR/Import/intrinsic.ll b/mlir/test/Target/LLVMIR/Import/intrinsic.ll index 0cefb4f8983a..81a6eadbadd3 100644 --- a/mlir/test/Target/LLVMIR/Import/intrinsic.ll +++ b/mlir/test/Target/LLVMIR/Import/intrinsic.ll @@ -641,10 +641,12 @@ define void @expect_with_probability(i16 %0) { ret void } +@tls_var = dso_local thread_local global i32 0, align 4 + ; CHECK-LABEL: llvm.func @threadlocal_test -define void @threadlocal_test(ptr %0) { +define void @threadlocal_test() { ; CHECK: "llvm.intr.threadlocal.address"(%{{.*}}) : (!llvm.ptr) -> !llvm.ptr - %local = call ptr @llvm.threadlocal.address.p0(ptr %0) + %local = call ptr @llvm.threadlocal.address.p0(ptr @tls_var) ret void } diff --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir index 0013522582a7..db5184a63d98 100644 --- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir @@ -576,10 +576,13 @@ llvm.func @expect_with_probability(%arg0: i16) { llvm.return } +llvm.mlir.global external thread_local @tls_var(0 : i32) {addr_space = 0 : i32, alignment = 4 : i64, dso_local} : i32 + // CHECK-LABEL: @threadlocal_test -llvm.func @threadlocal_test(%arg0 : !llvm.ptr) { - // CHECK: call ptr @llvm.threadlocal.address.p0(ptr %{{.*}}) - "llvm.intr.threadlocal.address"(%arg0) : (!llvm.ptr) -> !llvm.ptr +llvm.func @threadlocal_test() { + // CHECK: call ptr @llvm.threadlocal.address.p0(ptr @tls_var) + %0 = llvm.mlir.addressof @tls_var : !llvm.ptr + "llvm.intr.threadlocal.address"(%0) : (!llvm.ptr) -> !llvm.ptr llvm.return } -- GitLab From 925b7d6f62bf8f0b204cc1cb24a4a75c7bc5e0ae Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Mon, 8 Apr 2024 18:28:18 -0600 Subject: [PATCH 227/695] [ORC] Replace some KV loop variables with structured bindings. Same idea as 006aaf32258 -- reduce boilerplate and improve readability. This time updates will be piecemeal to make it easier to identify errors. Coding my way home: 2.18555S, 93.78063W --- llvm/lib/ExecutionEngine/Orc/Core.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp index 8bb68b45951d..a9d1998e0930 100644 --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -87,13 +87,13 @@ FailedToMaterialize::FailedToMaterialize( // FIXME: Use a new dep-map type for FailedToMaterialize errors so that we // don't have to manually retain/release. - for (auto &KV : *this->Symbols) - KV.first->Retain(); + for (auto &[JD, Syms] : *this->Symbols) + JD->Retain(); } FailedToMaterialize::~FailedToMaterialize() { - for (auto &KV : *Symbols) - KV.first->Release(); + for (auto &[JD, Syms] : *Symbols) + JD->Release(); } std::error_code FailedToMaterialize::convertToErrorCode() const { -- GitLab From e35fb3fb8bfcb732ace3738f9589989b3fac1508 Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Mon, 8 Apr 2024 17:57:35 -0700 Subject: [PATCH 228/695] [lldb] [NFC] Fix swig docstring annotations (#88073) Some of the SB API method description docstrings for swing are annotated as `%feature("autodoc")` - but `"autodoc"` annotations are only to substitute a string showing the arguments and return variables - either in a single line, or in multiple lines. SBMemoryRegionInfo used `"autodoc"` correctly describing the parameters and return type, but then it added a description too which is not correct either. Change all of these that are adding a method description to use `%feature("docstring")` instead. There were a half dozen instances where `"autodoc"` was correctly being used and we have overriden the parameter and return types with a more readable version. --- .../interface/SBMemoryRegionInfoDocstrings.i | 12 ++--- lldb/bindings/interface/SBProcessDocstrings.i | 50 +++++++++---------- lldb/bindings/interface/SBQueueDocstrings.i | 4 +- lldb/bindings/interface/SBThreadDocstrings.i | 36 +++++++------ 4 files changed, 48 insertions(+), 54 deletions(-) diff --git a/lldb/bindings/interface/SBMemoryRegionInfoDocstrings.i b/lldb/bindings/interface/SBMemoryRegionInfoDocstrings.i index bd80740f3fdd..d7c68baf100e 100644 --- a/lldb/bindings/interface/SBMemoryRegionInfoDocstrings.i +++ b/lldb/bindings/interface/SBMemoryRegionInfoDocstrings.i @@ -2,8 +2,7 @@ "API clients can get information about memory regions in processes." ) lldb::SBMemoryRegionInfo; -%feature("autodoc", " - GetRegionEnd(SBMemoryRegionInfo self) -> lldb::addr_t +%feature("docstring", " Returns whether this memory region has a list of modified (dirty) pages available or not. When calling GetNumDirtyPages(), you will have 0 returned for both \"dirty page list is not known\" and @@ -11,8 +10,7 @@ memory region). You must use this method to disambiguate." ) lldb::SBMemoryRegionInfo::HasDirtyMemoryPageList; -%feature("autodoc", " - GetNumDirtyPages(SBMemoryRegionInfo self) -> uint32_t +%feature("docstring", " Return the number of dirty (modified) memory pages in this memory region, if available. You must use the SBMemoryRegionInfo::HasDirtyMemoryPageList() method to @@ -20,16 +18,14 @@ on the target system can provide this information." ) lldb::SBMemoryRegionInfo::GetNumDirtyPages; -%feature("autodoc", " - GetDirtyPageAddressAtIndex(SBMemoryRegionInfo self, uint32_t idx) -> lldb::addr_t +%feature("docstring", " Return the address of a modified, or dirty, page of memory. If the provided index is out of range, or this memory region does not have dirty page information, LLDB_INVALID_ADDRESS is returned." ) lldb::SBMemoryRegionInfo::GetDirtyPageAddressAtIndex; -%feature("autodoc", " - GetPageSize(SBMemoryRegionInfo self) -> int +%feature("docstring", " Return the size of pages in this memory region. 0 will be returned if this information was unavailable." ) lldb::SBMemoryRegionInfo::GetPageSize(); diff --git a/lldb/bindings/interface/SBProcessDocstrings.i b/lldb/bindings/interface/SBProcessDocstrings.i index 3ee17e0c7f2f..c20ef3e4655b 100644 --- a/lldb/bindings/interface/SBProcessDocstrings.i +++ b/lldb/bindings/interface/SBProcessDocstrings.i @@ -20,18 +20,18 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: " ) lldb::SBProcess; -%feature("autodoc", " +%feature("docstring", " Writes data into the current process's stdin. API client specifies a Python string as the only argument." ) lldb::SBProcess::PutSTDIN; -%feature("autodoc", " +%feature("docstring", " Reads data from the current process's stdout stream. API client specifies the size of the buffer to read data into. It returns the byte buffer in a Python string." ) lldb::SBProcess::GetSTDOUT; -%feature("autodoc", " +%feature("docstring", " Reads data from the current process's stderr stream. API client specifies the size of the buffer to read data into. It returns the byte buffer in a Python string." @@ -47,34 +47,34 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: "See SBTarget.Launch for argument description and usage." ) lldb::SBProcess::RemoteLaunch; -%feature("autodoc", " +%feature("docstring", " Returns the INDEX'th thread from the list of current threads. The index of a thread is only valid for the current stop. For a persistent thread identifier use either the thread ID or the IndexID. See help on SBThread for more details." ) lldb::SBProcess::GetThreadAtIndex; -%feature("autodoc", " +%feature("docstring", " Returns the thread with the given thread ID." ) lldb::SBProcess::GetThreadByID; -%feature("autodoc", " +%feature("docstring", " Returns the thread with the given thread IndexID." ) lldb::SBProcess::GetThreadByIndexID; -%feature("autodoc", " +%feature("docstring", " Returns the currently selected thread." ) lldb::SBProcess::GetSelectedThread; -%feature("autodoc", " +%feature("docstring", " Lazily create a thread on demand through the current OperatingSystem plug-in, if the current OperatingSystem plug-in supports it." ) lldb::SBProcess::CreateOSPluginThread; -%feature("autodoc", " +%feature("docstring", " Returns the process ID of the process." ) lldb::SBProcess::GetProcessID; -%feature("autodoc", " +%feature("docstring", " Returns an integer ID that is guaranteed to be unique across all process instances. This is not the process ID, just a unique integer for comparison and caching purposes." ) lldb::SBProcess::GetUniqueID; @@ -95,7 +95,7 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: will always increase, but may increase by more than one per stop." ) lldb::SBProcess::GetStopID; -%feature("autodoc", " +%feature("docstring", " Reads memory from the current process's address space and removes any traps that may have been inserted into the memory. It returns the byte buffer in a Python string. Example: :: @@ -105,7 +105,7 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: new_bytes = bytearray(content)" ) lldb::SBProcess::ReadMemory; -%feature("autodoc", " +%feature("docstring", " Writes memory to the current process's address space and maintains any traps that might be present due to software breakpoints. Example: :: @@ -116,8 +116,8 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: print('SBProcess.WriteMemory() failed!')" ) lldb::SBProcess::WriteMemory; -%feature("autodoc", " - Reads a NULL terminated C string from the current process's address space. +%feature("docstring", " + Reads a NUL terminated C string from the current process's address space. It returns a python string of the exact length, or truncates the string if the maximum character limit is reached. Example: :: @@ -131,7 +131,7 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: ) lldb::SBProcess::ReadCStringFromMemory; -%feature("autodoc", " +%feature("docstring", " Reads an unsigned integer from memory given a byte size and an address. Returns the unsigned integer that was read. Example: :: @@ -145,7 +145,7 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: ) lldb::SBProcess::ReadUnsignedFromMemory; -%feature("autodoc", " +%feature("docstring", " Reads a pointer from memory from an address and returns the value. Example: :: # Read a pointer from address 0x1000 @@ -158,16 +158,16 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: ) lldb::SBProcess::ReadPointerFromMemory; -%feature("autodoc", " +%feature("docstring", " Returns the implementation object of the process plugin if available. None otherwise." ) lldb::SBProcess::GetScriptedImplementation; -%feature("autodoc", " +%feature("docstring", " Returns the process' extended crash information." ) lldb::SBProcess::GetExtendedCrashInformation; -%feature("autodoc", " +%feature("docstring", " Load the library whose filename is given by image_spec looking in all the paths supplied in the paths argument. If successful, return a token that can be passed to UnloadImage and fill loaded_path with the path that was @@ -175,7 +175,7 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: lldb.LLDB_INVALID_IMAGE_TOKEN." ) lldb::SBProcess::LoadImageUsingPaths; -%feature("autodoc", " +%feature("docstring", " Return the number of different thread-origin extended backtraces this process can support as a uint32_t. When the process is stopped and you have an SBThread, lldb may be @@ -184,12 +184,12 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: queue)." ) lldb::SBProcess::GetNumExtendedBacktraceTypes; -%feature("autodoc", " +%feature("docstring", " Takes an index argument, returns the name of one of the thread-origin extended backtrace methods as a str." ) lldb::SBProcess::GetExtendedBacktraceTypeAtIndex; -%feature("autodoc", " +%feature("docstring", " Get information about the process. Valid process info will only be returned when the process is alive, use IsValid() to check if the info returned is valid. :: @@ -199,7 +199,7 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: process_info.GetProcessID()" ) lldb::SBProcess::GetProcessInfo; -%feature("autodoc", " +%feature("docstring", " Allocates a block of memory within the process, with size and access permissions specified in the arguments. The permissions argument is an or-combination of zero or more of @@ -209,11 +209,11 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: lldb.LLDB_INVALID_ADDRESS if the allocation failed." ) lldb::SBProcess::AllocateMemory; -%feature("autodoc", "Get default process broadcaster class name (lldb.process)." +%feature("docstring", "Get default process broadcaster class name (lldb.process)." ) lldb::SBProcess::GetBroadcasterClass; -%feature("autodoc", " +%feature("docstring", " Deallocates the block of memory (previously allocated using AllocateMemory) given in the argument." ) lldb::SBProcess::DeallocateMemory; diff --git a/lldb/bindings/interface/SBQueueDocstrings.i b/lldb/bindings/interface/SBQueueDocstrings.i index fa472d5bed17..c3baf39a299d 100644 --- a/lldb/bindings/interface/SBQueueDocstrings.i +++ b/lldb/bindings/interface/SBQueueDocstrings.i @@ -2,14 +2,14 @@ "Represents a libdispatch queue in the process." ) lldb::SBQueue; -%feature("autodoc", " +%feature("docstring", " Returns an lldb::queue_id_t type unique identifier number for this queue that will not be used by any other queue during this process' execution. These ID numbers often start at 1 with the first system-created queues and increment from there." ) lldb::SBQueue::GetQueueID; -%feature("autodoc", " +%feature("docstring", " Returns an lldb::QueueKind enumerated value (e.g. eQueueKindUnknown, eQueueKindSerial, eQueueKindConcurrent) describing the type of this queue." diff --git a/lldb/bindings/interface/SBThreadDocstrings.i b/lldb/bindings/interface/SBThreadDocstrings.i index f307212f0114..76822e49c638 100644 --- a/lldb/bindings/interface/SBThreadDocstrings.i +++ b/lldb/bindings/interface/SBThreadDocstrings.i @@ -55,24 +55,24 @@ See also :py:class:`SBFrame` ." eStopReasonPlanComplete 0" ) lldb::SBThread::GetStopReasonDataAtIndex; -%feature("autodoc", " +%feature("docstring", " Collects a thread's stop reason extended information dictionary and prints it into the SBStream in a JSON format. The format of this JSON dictionary depends on the stop reason and is currently used only for instrumentation plugins." ) lldb::SBThread::GetStopReasonExtendedInfoAsJSON; -%feature("autodoc", " +%feature("docstring", " Returns a collection of historical stack traces that are significant to the current stop reason. Used by ThreadSanitizer, where we provide various stack traces that were involved in a data race or other type of detected issue." ) lldb::SBThread::GetStopReasonExtendedBacktraces; -%feature("autodoc", " +%feature("docstring", " Pass only an (int)length and expect to get a Python string describing the stop reason." ) lldb::SBThread::GetStopDescription; -%feature("autodoc", " +%feature("docstring", " Returns a unique thread identifier (type lldb::tid_t, typically a 64-bit type) for the current SBThread that will remain constant throughout the thread's lifetime in this process and will not be reused by another thread during this @@ -81,7 +81,7 @@ See also :py:class:`SBFrame` ." to associate data from those tools with lldb. See related GetIndexID." ) lldb::SBThread::GetThreadID; -%feature("autodoc", " +%feature("docstring", " Return the index number for this SBThread. The index number is the same thing that a user gives as an argument to 'thread select' in the command line lldb. These numbers start at 1 (for the first thread lldb sees in a debug session) @@ -91,12 +91,12 @@ See also :py:class:`SBFrame` ." This method returns a uint32_t index number, takes no arguments." ) lldb::SBThread::GetIndexID; -%feature("autodoc", " +%feature("docstring", " Return the queue name associated with this thread, if any, as a str. For example, with a libdispatch (aka Grand Central Dispatch) queue." ) lldb::SBThread::GetQueueName; -%feature("autodoc", " +%feature("docstring", " Return the dispatch_queue_id for this thread, if any, as a lldb::queue_id_t. For example, with a libdispatch (aka Grand Central Dispatch) queue." ) lldb::SBThread::GetQueueID; @@ -109,7 +109,7 @@ See also :py:class:`SBFrame` ." anything was printed into the stream (true) or not (false)." ) lldb::SBThread::GetInfoItemByPathAsString; -%feature("autodoc", " +%feature("docstring", " Return the SBQueue for this thread. If this thread is not currently associated with a libdispatch queue, the SBQueue object's IsValid() method will return false. If this SBThread is actually a HistoryThread, we may be able to provide QueueID @@ -141,14 +141,14 @@ See also :py:class:`SBFrame` ." "Do an instruction level single step in the currently selected thread." ) lldb::SBThread::StepInstruction; -%feature("autodoc", " +%feature("docstring", " Force a return from the frame passed in (and any frames younger than it) without executing any more code in those frames. If return_value contains a valid SBValue, that will be set as the return value from frame. Note, at present only scalar return values are supported." ) lldb::SBThread::ReturnFromFrame; -%feature("autodoc", " +%feature("docstring", " Unwind the stack frames from the innermost expression evaluation. This API is equivalent to 'thread return -x'." ) lldb::SBThread::UnwindInnermostExpression; @@ -181,7 +181,7 @@ See also :py:class:`SBFrame` ." or thread-stop-format (stop_format = true)." ) lldb::SBThread::GetDescription; -%feature("autodoc"," +%feature("docstring"," Given an argument of str to specify the type of thread-origin extended backtrace to retrieve, query whether the origin of this thread is available. An SBThread is retured; SBThread.IsValid will return true @@ -192,8 +192,7 @@ See also :py:class:`SBFrame` ." the returned thread's own thread origin in turn." ) lldb::SBThread::GetExtendedBacktraceThread; -%feature("autodoc"," - Takes no arguments, returns a uint32_t. +%feature("docstring"," If this SBThread is an ExtendedBacktrace thread, get the IndexID of the original thread that this ExtendedBacktrace thread represents, if available. The thread that was running this backtrace in the past may @@ -202,29 +201,28 @@ See also :py:class:`SBFrame` ." In that case, this ExtendedBacktrace thread's IndexID will be returned." ) lldb::SBThread::GetExtendedBacktraceOriginatingIndexID; -%feature("autodoc"," +%feature("docstring"," Returns an SBValue object represeting the current exception for the thread, if there is any. Currently, this works for Obj-C code and returns an SBValue representing the NSException object at the throw site or that's currently being processes." ) lldb::SBThread::GetCurrentException; -%feature("autodoc"," +%feature("docstring"," Returns a historical (fake) SBThread representing the stack trace of an exception, if there is one for the thread. Currently, this works for Obj-C code, and can retrieve the throw-site backtrace of an NSException object even when the program is no longer at the throw site." ) lldb::SBThread::GetCurrentExceptionBacktrace; -%feature("autodoc"," - Takes no arguments, returns a bool. +%feature("docstring"," lldb may be able to detect that function calls should not be executed on a given thread at a particular point in time. It is recommended that this is checked before performing an inferior function call on a given thread." ) lldb::SBThread::SafeToCallFunctions; -%feature("autodoc"," - Retruns a SBValue object representing the siginfo for the current signal. +%feature("docstring"," + Returns a SBValue object representing the siginfo for the current signal. " ) lldb::SBThread::GetSiginfo; -- GitLab From f7d93373969b2b757f5d5ef5e157dabe3bb9b0ae Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Tue, 9 Apr 2024 09:53:58 +0800 Subject: [PATCH 229/695] [Sema][NFC] Cleanups after 843cc474f (#87996) I forgot to tidy up these lines that should've been done in the previous commit, specifically: 1. Merge two `CodeSynthesisContext`s into one in `CheckTemplateIdType`. 2. Remove some gratuitous `Sema::` specifiers. 3. Rename the parameter `Template` to `Entity` to avoid confusion. --- clang/include/clang/Sema/Sema.h | 2 +- clang/lib/Frontend/FrontendActions.cpp | 2 +- clang/lib/Sema/SemaTemplate.cpp | 10 ++++------ clang/lib/Sema/SemaTemplateInstantiate.cpp | 19 +++++++++---------- .../lib/Sema/SemaTemplateInstantiateDecl.cpp | 2 ++ 5 files changed, 17 insertions(+), 18 deletions(-) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 3fe2b6dd422a..9769d3690066 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -10077,7 +10077,7 @@ public: /// Note that we are instantiating a type alias template declaration. InstantiatingTemplate(Sema &SemaRef, SourceLocation PointOfInstantiation, - TypeAliasTemplateDecl *Template, + TypeAliasTemplateDecl *Entity, ArrayRef TemplateArgs, SourceRange InstantiationRange = SourceRange()); diff --git a/clang/lib/Frontend/FrontendActions.cpp b/clang/lib/Frontend/FrontendActions.cpp index 7ee6ccf396a8..58fcb2217b05 100644 --- a/clang/lib/Frontend/FrontendActions.cpp +++ b/clang/lib/Frontend/FrontendActions.cpp @@ -453,7 +453,7 @@ private: return "BuildingBuiltinDumpStructCall"; case CodeSynthesisContext::BuildingDeductionGuides: return "BuildingDeductionGuides"; - case Sema::CodeSynthesisContext::TypeAliasTemplateInstantiation: + case CodeSynthesisContext::TypeAliasTemplateInstantiation: return "TypeAliasTemplateInstantiation"; } return ""; diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 73030cf4b722..2013799b5eb8 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -4494,15 +4494,13 @@ QualType Sema::CheckTemplateIdType(TemplateName Name, AliasTemplate->getTemplateParameters()->getDepth()); LocalInstantiationScope Scope(*this); - InstantiatingTemplate Inst(*this, TemplateLoc, Template); + InstantiatingTemplate Inst( + *this, /*PointOfInstantiation=*/TemplateLoc, + /*Entity=*/AliasTemplate, + /*TemplateArgs=*/TemplateArgLists.getInnermost()); if (Inst.isInvalid()) return QualType(); - InstantiatingTemplate InstTemplate( - *this, /*PointOfInstantiation=*/AliasTemplate->getBeginLoc(), - /*Template=*/AliasTemplate, - /*TemplateArgs=*/TemplateArgLists.getInnermost()); - std::optional SavedContext; if (!AliasTemplate->getDeclContext()->isFileContext()) SavedContext.emplace(*this, AliasTemplate->getDeclContext()); diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index d7b7291091ec..a265fd1c46a6 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -737,11 +737,11 @@ Sema::InstantiatingTemplate::InstantiatingTemplate( Sema::InstantiatingTemplate::InstantiatingTemplate( Sema &SemaRef, SourceLocation PointOfInstantiation, - TypeAliasTemplateDecl *Template, ArrayRef TemplateArgs, + TypeAliasTemplateDecl *Entity, ArrayRef TemplateArgs, SourceRange InstantiationRange) : InstantiatingTemplate( - SemaRef, Sema::CodeSynthesisContext::TypeAliasTemplateInstantiation, - PointOfInstantiation, InstantiationRange, /*Entity=*/Template, + SemaRef, CodeSynthesisContext::TypeAliasTemplateInstantiation, + PointOfInstantiation, InstantiationRange, /*Entity=*/Entity, /*Template=*/nullptr, TemplateArgs) {} Sema::InstantiatingTemplate::InstantiatingTemplate( @@ -983,11 +983,6 @@ void Sema::PrintInstantiationStack() { Diags.Report(Active->PointOfInstantiation, diag::note_template_class_instantiation_here) << CTD << Active->InstantiationRange; - } else { - Diags.Report(Active->PointOfInstantiation, - diag::note_template_type_alias_instantiation_here) - << cast(D) - << Active->InstantiationRange; } break; } @@ -1262,6 +1257,10 @@ void Sema::PrintInstantiationStack() { diag::note_building_deduction_guide_here); break; case CodeSynthesisContext::TypeAliasTemplateInstantiation: + Diags.Report(Active->PointOfInstantiation, + diag::note_template_type_alias_instantiation_here) + << cast(Active->Entity) + << Active->InstantiationRange; break; } } @@ -1278,12 +1277,13 @@ std::optional Sema::isSFINAEContext() const { ++Active) { switch (Active->Kind) { - case CodeSynthesisContext::TemplateInstantiation: + case CodeSynthesisContext::TypeAliasTemplateInstantiation: // An instantiation of an alias template may or may not be a SFINAE // context, depending on what else is on the stack. if (isa(Active->Entity)) break; [[fallthrough]]; + case CodeSynthesisContext::TemplateInstantiation: case CodeSynthesisContext::DefaultFunctionArgumentInstantiation: case CodeSynthesisContext::ExceptionSpecInstantiation: case CodeSynthesisContext::ConstraintsCheck: @@ -1340,7 +1340,6 @@ std::optional Sema::isSFINAEContext() const { break; case CodeSynthesisContext::Memoization: - case CodeSynthesisContext::TypeAliasTemplateInstantiation: break; } diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp index 1cb071e4eb7d..127a432367b9 100644 --- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp @@ -1119,6 +1119,8 @@ TemplateDeclInstantiator::VisitTypeAliasTemplateDecl(TypeAliasTemplateDecl *D) { : (TemplateArgs.begin() + TemplateArgs.getNumLevels() - 1 - D->getTemplateDepth()) ->Args); + if (InstTemplate.isInvalid()) + return nullptr; TypeAliasTemplateDecl *PrevAliasTemplate = nullptr; if (getPreviousDeclForInstantiation(Pattern)) { -- GitLab From 41dc04e5283adef9979cad2b126ab3e6c156034a Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Mon, 8 Apr 2024 18:55:29 -0700 Subject: [PATCH 230/695] [lldb] Add swig doc for SBProcess address mask methods Add descriptions of `GetAddressMask`, `SetAddressMask`, `SetAddressableBits`, and `FixAddress` SBProcess methods. --- lldb/bindings/interface/SBProcessDocstrings.i | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/lldb/bindings/interface/SBProcessDocstrings.i b/lldb/bindings/interface/SBProcessDocstrings.i index c20ef3e4655b..1b98a79e4f6d 100644 --- a/lldb/bindings/interface/SBProcessDocstrings.i +++ b/lldb/bindings/interface/SBProcessDocstrings.i @@ -199,6 +199,47 @@ SBProcess supports thread iteration. For example (from test/lldbutil.py), :: process_info.GetProcessID()" ) lldb::SBProcess::GetProcessInfo; +%feature("docstring", " + Get the current address mask in this Process of a given type. + There are lldb.eAddressMaskTypeCode and lldb.eAddressMaskTypeData address + masks, and on most Targets, the the Data address mask is more general + because there are no alignment restrictions, as there can be with Code + addresses. + lldb.eAddressMaskTypeAny may be used to get the most general mask. + The bits which are not used for addressing are set to 1 in the returned + mask. + In an unusual environment with different address masks for high and low + memory, this may also be specified. This is uncommon, default is + lldb.eAddressMaskRangeLow." +) lldb::SBProcess::GetAddressMask; + +%feature("docstring", " + Set the current address mask in this Process for a given type, + lldb.eAddressMaskTypeCode or lldb.eAddressMaskTypeData. Bits that are not + used for addressing should be set to 1 in the mask. + When setting all masks, lldb.eAddressMaskTypeAll may be specified. + In an unusual environment with different address masks for high and low + memory, this may also be specified. This is uncommon, default is + lldb.eAddressMaskRangeLow." +) lldb::SBProcess::SetAddressMask; + +%feature("docstring", " + Set the number of low bits relevant for addressing in this Process + for a given type, lldb.eAddressMaskTypeCode or lldb.eAddressMaskTypeData. + When setting all masks, lldb.eAddressMaskTypeAll may be specified. + In an unusual environment with different address masks for high and low + memory, the address range may also be specified. This is uncommon, + default is lldb.eAddressMaskRangeLow." +) lldb::SBProcess::SetAddressableBits; + +%feature("docstring", " + Given a virtual address, clear the bits that are not used for addressing + (and may be used for metadata, memory tagging, point authentication, etc). + By default the most general mask, lldb.eAddressMaskTypeAny is used to + process the address, but lldb.eAddressMaskTypeData and + lldb.eAddressMaskTypeCode may be specified if the type of address is known." +) lldb::SBProcess::FixAddress; + %feature("docstring", " Allocates a block of memory within the process, with size and access permissions specified in the arguments. The permissions -- GitLab From 71eda17a0674317b05975be79ed4a2c8ee99c43c Mon Sep 17 00:00:00 2001 From: Qiu Chaofan Date: Tue, 9 Apr 2024 10:26:24 +0800 Subject: [PATCH 231/695] [Legalizer] Soften EXTRACT_ELEMENT on ppcf128 (#77412) ppc_fp128 values are always split into two f64. Implement soften operation in soft-float mode to handle output f64 correctly. --- .../SelectionDAG/LegalizeFloatTypes.cpp | 11 +++- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 1 + llvm/test/CodeGen/PowerPC/ppcsoftops.ll | 60 +++++++++++++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index a8b1f41ee40d..7685bc73cf96 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -61,7 +61,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { #endif report_fatal_error("Do not know how to soften the result of this " "operator!"); - + case ISD::EXTRACT_ELEMENT: R = SoftenFloatRes_EXTRACT_ELEMENT(N); break; case ISD::ARITH_FENCE: R = SoftenFloatRes_ARITH_FENCE(N); break; case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; @@ -258,6 +258,15 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(SDNode *N) { } } +SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N) { + SDValue Src = N->getOperand(0); + assert(Src.getValueType() == MVT::ppcf128 && + "In floats only ppcf128 can be extracted by element!"); + return DAG.getNode(ISD::EXTRACT_ELEMENT, SDLoc(N), + N->getValueType(0).changeTypeToInteger(), + DAG.getBitcast(MVT::i128, Src), N->getOperand(1)); +} + SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) { SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0)); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index e08acd36b41d..919c0d4fd200 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -530,6 +530,7 @@ private: SDValue SoftenFloatRes_BITCAST(SDNode *N); SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N); SDValue SoftenFloatRes_ConstantFP(SDNode *N); + SDValue SoftenFloatRes_EXTRACT_ELEMENT(SDNode *N); SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo); SDValue SoftenFloatRes_FABS(SDNode *N); SDValue SoftenFloatRes_FMINNUM(SDNode *N); diff --git a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll index dee2701bf6dc..fcb7ce6db529 100644 --- a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll +++ b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll @@ -312,8 +312,68 @@ define dso_local zeroext i32 @func(double noundef %0, double noundef %1) #0 { ret i32 %9 } +; To check ppc_fp128 soften without crash +define zeroext i1 @ppcf128_soften(ppc_fp128 %a) #0 { +; PPC-LABEL: ppcf128_soften: +; PPC: # %bb.0: # %entry +; PPC-NEXT: stwu 1, -16(1) +; PPC-NEXT: stw 5, 8(1) # 4-byte Folded Spill +; PPC-NEXT: mr 5, 4 +; PPC-NEXT: lwz 4, 8(1) # 4-byte Folded Reload +; PPC-NEXT: stw 5, 12(1) # 4-byte Folded Spill +; PPC-NEXT: mr 5, 3 +; PPC-NEXT: lwz 3, 12(1) # 4-byte Folded Reload +; PPC-NEXT: # kill: def $r4 killed $r3 +; PPC-NEXT: # kill: def $r4 killed $r5 +; PPC-NEXT: xoris 4, 5, 65520 +; PPC-NEXT: or 4, 3, 4 +; PPC-NEXT: cntlzw 4, 4 +; PPC-NEXT: clrlwi 5, 5, 1 +; PPC-NEXT: or 3, 3, 5 +; PPC-NEXT: cntlzw 3, 3 +; PPC-NEXT: or 3, 3, 4 +; PPC-NEXT: srwi 3, 3, 5 +; PPC-NEXT: addi 1, 1, 16 +; PPC-NEXT: blr +; +; PPC64-LABEL: ppcf128_soften: +; PPC64: # %bb.0: # %entry +; PPC64-NEXT: li 4, 4095 +; PPC64-NEXT: rldic 4, 4, 52, 0 +; PPC64-NEXT: cmpld 7, 3, 4 +; PPC64-NEXT: mfcr 4 # cr7 +; PPC64-NEXT: rlwinm 4, 4, 31, 31, 31 +; PPC64-NEXT: clrldi 3, 3, 1 +; PPC64-NEXT: cmpldi 7, 3, 0 +; PPC64-NEXT: mfcr 3 # cr7 +; PPC64-NEXT: rlwinm 3, 3, 31, 31, 31 +; PPC64-NEXT: or 4, 3, 4 +; PPC64-NEXT: # implicit-def: $x3 +; PPC64-NEXT: mr 3, 4 +; PPC64-NEXT: clrldi 3, 3, 32 +; PPC64-NEXT: blr +; +; PPC64LE-LABEL: ppcf128_soften: +; PPC64LE: # %bb.0: # %entry +; PPC64LE-NEXT: li 3, 4095 +; PPC64LE-NEXT: rldic 3, 3, 52, 0 +; PPC64LE-NEXT: cmpd 4, 3 +; PPC64LE-NEXT: crmove 21, 2 +; PPC64LE-NEXT: clrldi. 3, 4, 1 +; PPC64LE-NEXT: crmove 20, 2 +; PPC64LE-NEXT: cror 20, 20, 21 +; PPC64LE-NEXT: li 4, 0 +; PPC64LE-NEXT: li 3, 1 +; PPC64LE-NEXT: isel 3, 3, 4, 20 +; PPC64LE-NEXT: blr +entry: + %fpclass = tail call i1 @llvm.is.fpclass.ppcf128(ppc_fp128 %a, i32 100) + ret i1 %fpclass +} + ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) declare double @llvm.fmuladd.f64(double, double, double) #1 +declare i1 @llvm.is.fpclass.ppcf128(ppc_fp128, i32 immarg) #1 attributes #0 = {"use-soft-float"="true" nounwind } attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } -- GitLab From 0e5a53cc01e406436cb7c703c84598e474d635de Mon Sep 17 00:00:00 2001 From: Uday Bondhugula Date: Tue, 9 Apr 2024 08:37:57 +0530 Subject: [PATCH 232/695] [MLIR] Fix typo bug in AffineExprVisitor for WalkResult return case (#86138) Fix typo bug in AffineExprVisitor for the WalkResult return case. This didn't show up immmediately because most walks in the tree didn't use walk result. --- mlir/include/mlir/IR/AffineExprVisitor.h | 2 +- mlir/test/IR/affine-walk.mlir | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/mlir/include/mlir/IR/AffineExprVisitor.h b/mlir/include/mlir/IR/AffineExprVisitor.h index 3e1bbb4b3fa0..27c49cd80018 100644 --- a/mlir/include/mlir/IR/AffineExprVisitor.h +++ b/mlir/include/mlir/IR/AffineExprVisitor.h @@ -222,7 +222,7 @@ private: walkPostOrder(expr.getLHS()); } if constexpr (std::is_same::value) { - if (walkPostOrder(expr.getLHS()).wasInterrupted()) + if (walkPostOrder(expr.getRHS()).wasInterrupted()) return WalkResult::interrupt(); return WalkResult::advance(); } else { diff --git a/mlir/test/IR/affine-walk.mlir b/mlir/test/IR/affine-walk.mlir index 1de675ac70be..0ee7abf9415c 100644 --- a/mlir/test/IR/affine-walk.mlir +++ b/mlir/test/IR/affine-walk.mlir @@ -7,3 +7,8 @@ "test.check_first_mod"() {"map" = #map} : () -> () // expected-remark@-1 {{mod expression}} + +#map_rhs_mod = affine_map<(i, j) -> (i + i mod 2, j)> + +"test.check_first_mod"() {"map" = #map_rhs_mod} : () -> () +// expected-remark@-1 {{mod expression}} -- GitLab From 25e3d2b0fc1e2b4df19d7f18fbdd04c154e1d0e8 Mon Sep 17 00:00:00 2001 From: Pete Steinfeld <47540744+psteinfeld@users.noreply.github.com> Date: Mon, 8 Apr 2024 20:20:27 -0700 Subject: [PATCH 233/695] =?UTF-8?q?Revert=20"[Libomp]=20Place=20generated?= =?UTF-8?q?=20OpenMP=20headers=20into=20build=20resource=20d=E2=80=A6=20(#?= =?UTF-8?q?88083)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …irectory (#88007)" This reverts commit 8671429151d5e67d3f21a737809953ae8bdfbfde. This commit broke the flang build, so I'm reverting it. See the comments in merge request #88007 for more information. --- clang/test/Headers/Inputs/include/stdint.h | 8 ------- openmp/runtime/src/CMakeLists.txt | 25 ++++++++-------------- 2 files changed, 9 insertions(+), 24 deletions(-) diff --git a/clang/test/Headers/Inputs/include/stdint.h b/clang/test/Headers/Inputs/include/stdint.h index 67b27b8dfc7b..5bf26a7b67b0 100644 --- a/clang/test/Headers/Inputs/include/stdint.h +++ b/clang/test/Headers/Inputs/include/stdint.h @@ -16,12 +16,4 @@ typedef unsigned __INTPTR_TYPE__ uintptr_t; #error Every target should have __INTPTR_TYPE__ #endif -#ifdef __INTPTR_MAX__ -#define INTPTR_MAX __INTPTR_MAX__ -#endif - -#ifdef __UINTPTR_MAX__ -#define UINTPTR_MAX __UINTPTR_MAX__ -#endif - #endif /* STDINT_H */ diff --git a/openmp/runtime/src/CMakeLists.txt b/openmp/runtime/src/CMakeLists.txt index 000d02c33dc0..f05bcabb4417 100644 --- a/openmp/runtime/src/CMakeLists.txt +++ b/openmp/runtime/src/CMakeLists.txt @@ -10,19 +10,12 @@ include(ExtendPath) -# The generated headers will be placed in clang's resource directory if present. -if(${OPENMP_STANDALONE_BUILD}) - set(LIBOMP_HEADERS_INTDIR ${CMAKE_CURRENT_BINARY_DIR}) -else() - set(LIBOMP_HEADERS_INTDIR ${LLVM_BINARY_DIR}/${LIBOMP_HEADERS_INSTALL_PATH}) -endif() - # Configure omp.h, kmp_config.h and omp-tools.h if necessary -configure_file(${LIBOMP_INC_DIR}/omp.h.var ${LIBOMP_HEADERS_INTDIR}/omp.h @ONLY) -configure_file(${LIBOMP_INC_DIR}/ompx.h.var ${LIBOMP_HEADERS_INTDIR}/ompx.h @ONLY) -configure_file(kmp_config.h.cmake ${LIBOMP_HEADERS_INTDIR}/kmp_config.h @ONLY) +configure_file(${LIBOMP_INC_DIR}/omp.h.var omp.h @ONLY) +configure_file(${LIBOMP_INC_DIR}/ompx.h.var ompx.h @ONLY) +configure_file(kmp_config.h.cmake kmp_config.h @ONLY) if(${LIBOMP_OMPT_SUPPORT}) - configure_file(${LIBOMP_INC_DIR}/omp-tools.h.var ${LIBOMP_HEADERS_INTDIR}/omp-tools.h @ONLY) + configure_file(${LIBOMP_INC_DIR}/omp-tools.h.var omp-tools.h @ONLY) endif() # Generate message catalog files: kmp_i18n_id.inc and kmp_i18n_default.inc @@ -426,15 +419,15 @@ else() endif() install( FILES - ${LIBOMP_HEADERS_INTDIR}/omp.h - ${LIBOMP_HEADERS_INTDIR}/ompx.h + ${CMAKE_CURRENT_BINARY_DIR}/omp.h + ${CMAKE_CURRENT_BINARY_DIR}/ompx.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} ) if(${LIBOMP_OMPT_SUPPORT}) - install(FILES ${LIBOMP_HEADERS_INTDIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) + install(FILES ${CMAKE_CURRENT_BINARY_DIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) # install under legacy name ompt.h - install(FILES ${LIBOMP_HEADERS_INTDIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} RENAME ompt.h) - set(LIBOMP_OMP_TOOLS_INCLUDE_DIR ${LIBOMP_HEADERS_INTDIR} PARENT_SCOPE) + install(FILES ${CMAKE_CURRENT_BINARY_DIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} RENAME ompt.h) + set(LIBOMP_OMP_TOOLS_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR} PARENT_SCOPE) endif() if(${BUILD_FORTRAN_MODULES}) set (destination ${LIBOMP_HEADERS_INSTALL_PATH}) -- GitLab From 74c085fcfc8fab7822127cb46ff82a6f0d3597f3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Apr 2024 20:35:46 -0700 Subject: [PATCH 234/695] [RISCV] Add Zcmop and Zimop to RISCVUsage.rst. NFC (#88033) These extensions are ratified so they were removed from the experimental section, but not added to the non-experimental section. --- llvm/docs/RISCVUsage.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 283f258d7e5f..6f5eba263def 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -131,6 +131,7 @@ on support follow. ``Zcb`` Supported ``Zcd`` Supported ``Zcf`` Supported + ``Zcmop`` Supported ``Zcmp`` Supported ``Zcmt`` Assembly Support ``Zdinx`` Supported @@ -155,6 +156,7 @@ on support follow. ``Zihintntl`` Supported ``Zihintpause`` Assembly Support ``Zihpm`` (`See Note <#riscv-i2p1-note>`__) + ``Zimop`` Supported ``Zkn`` Supported ``Zknd`` Supported (`See note <#riscv-scalar-crypto-note2>`__) ``Zkne`` Supported (`See note <#riscv-scalar-crypto-note2>`__) -- GitLab From 04f33a3ac2e8ca96840606f812eaef974ff61c80 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Apr 2024 20:38:29 -0700 Subject: [PATCH 235/695] [APInt] Use a std::move() to avoid a copy in the loop in multiplicativeInverse. (#87655) This allows the subtract to reuse the storage of T. T will be assigned over by the condition on the next iteration. I think assigning over a moved from value should be ok. --- llvm/lib/Support/APInt.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index 224ea0924f0a..8825025ec321 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -1249,7 +1249,7 @@ APInt APInt::multiplicativeInverse() const { APInt Factor = *this; APInt T; while (!(T = *this * Factor).isOne()) - Factor *= 2 - T; + Factor *= 2 - std::move(T); return Factor; } -- GitLab From a30662fc2acdd73ca1a9217716299a4676999fb4 Mon Sep 17 00:00:00 2001 From: Vassil Vassilev Date: Tue, 9 Apr 2024 07:14:43 +0300 Subject: [PATCH 236/695] Rework the printing of attributes (#87281) Commit https://github.com/llvm/llvm-project/commit/46f3ade introduced a notion of printing the attributes on the left to improve the printing of attributes attached to variable declarations. The intent was to produce more GCC compatible code because clang tends to print the attributes on the right hand side which is not accepted by gcc. This approach has increased the complexity in tablegen and the attrubutes themselves as now the are supposed to know where they could appear. That lead to mishandling of the `override` keyword which is modelled as an attribute in clang. This patch takes an inspiration from the existing approach and tries to keep the position of the attributes as they were written. To do so we use simpler heuristic which checks if the source locations of the attribute precedes the declaration. If so, it is considered to be printed before the declaration. Fixes https://github.com/llvm/llvm-project/issues/87151 --- clang/include/clang/Basic/Attr.td | 14 +- clang/include/clang/Basic/CMakeLists.txt | 10 - clang/lib/AST/DeclPrinter.cpp | 184 ++++++------------- clang/lib/AST/StmtPrinter.cpp | 5 +- clang/test/AST/ast-print-method-decl.cpp | 2 +- clang/test/AST/ast-print-no-sanitize.cpp | 2 +- clang/test/AST/attr-print-emit.cpp | 15 ++ clang/test/Analysis/scopes-cfg-output.cpp | 2 +- clang/test/OpenMP/assumes_codegen.cpp | 8 +- clang/test/OpenMP/assumes_print.cpp | 2 +- clang/test/OpenMP/assumes_template_print.cpp | 10 +- clang/test/OpenMP/declare_simd_ast_print.cpp | 4 +- clang/test/SemaCXX/attr-no-sanitize.cpp | 6 +- clang/test/SemaCXX/cxx11-attr-print.cpp | 8 +- clang/utils/TableGen/ClangAttrEmitter.cpp | 37 +--- clang/utils/TableGen/TableGen.cpp | 16 -- clang/utils/TableGen/TableGenBackends.h | 2 - 17 files changed, 97 insertions(+), 230 deletions(-) diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 6584460cf568..dc87a8c6f022 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -324,13 +324,10 @@ class Spelling { } class GNU : Spelling; -class Declspec : Spelling { - bit PrintOnLeft = 1; -} +class Declspec : Spelling; class Microsoft : Spelling; class CXX11 : Spelling { - bit CanPrintOnLeft = 0; string Namespace = namespace; } class C23 @@ -596,12 +593,6 @@ class AttrSubjectMatcherAggregateRule { def SubjectMatcherForNamed : AttrSubjectMatcherAggregateRule; class Attr { - // Specifies that when printed, this attribute is meaningful on the - // 'left side' of the declaration. - bit CanPrintOnLeft = 1; - // Specifies that when printed, this attribute is required to be printed on - // the 'left side' of the declaration. - bit PrintOnLeft = 0; // The various ways in which an attribute can be spelled in source list Spellings; // The things to which an attribute can appertain @@ -937,7 +928,6 @@ def AVRSignal : InheritableAttr, TargetSpecificAttr { } def AsmLabel : InheritableAttr { - let CanPrintOnLeft = 0; let Spellings = [CustomKeyword<"asm">, CustomKeyword<"__asm__">]; let Args = [ // Label specifies the mangled name for the decl. @@ -1534,7 +1524,6 @@ def AllocSize : InheritableAttr { } def EnableIf : InheritableAttr { - let CanPrintOnLeft = 0; // Does not have a [[]] spelling because this attribute requires the ability // to parse function arguments but the attribute is not written in the type // position. @@ -3171,7 +3160,6 @@ def Unavailable : InheritableAttr { } def DiagnoseIf : InheritableAttr { - let CanPrintOnLeft = 0; // Does not have a [[]] spelling because this attribute requires the ability // to parse function arguments but the attribute is not written in the type // position. diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt index 7d53c751c13a..2ef6ddc68f4b 100644 --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -31,16 +31,6 @@ clang_tablegen(AttrList.inc -gen-clang-attr-list SOURCE Attr.td TARGET ClangAttrList) -clang_tablegen(AttrLeftSideCanPrintList.inc -gen-clang-attr-can-print-left-list - -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ - SOURCE Attr.td - TARGET ClangAttrCanPrintLeftList) - -clang_tablegen(AttrLeftSideMustPrintList.inc -gen-clang-attr-must-print-left-list - -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ - SOURCE Attr.td - TARGET ClangAttrMustPrintLeftList) - clang_tablegen(AttrSubMatchRulesList.inc -gen-clang-attr-subject-match-rule-list -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ SOURCE Attr.td diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index edbcdfe4d55b..0d03288a491a 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -21,6 +21,7 @@ #include "clang/AST/ExprCXX.h" #include "clang/AST/PrettyPrinter.h" #include "clang/Basic/Module.h" +#include "clang/Basic/SourceManager.h" #include "llvm/Support/raw_ostream.h" using namespace clang; @@ -49,18 +50,6 @@ namespace { void PrintObjCTypeParams(ObjCTypeParamList *Params); - enum class AttrPrintLoc { - None = 0, - Left = 1, - Right = 2, - Any = Left | Right, - - LLVM_MARK_AS_BITMASK_ENUM(/*DefaultValue=*/Any) - }; - - void prettyPrintAttributes(Decl *D, raw_ostream &out, - AttrPrintLoc loc = AttrPrintLoc::Any); - public: DeclPrinter(raw_ostream &Out, const PrintingPolicy &Policy, const ASTContext &Context, unsigned Indentation = 0, @@ -129,11 +118,10 @@ namespace { const TemplateParameterList *Params); void printTemplateArguments(llvm::ArrayRef Args, const TemplateParameterList *Params); - - inline void prettyPrintAttributes(Decl *D) { - prettyPrintAttributes(D, Out); - } - + enum class AttrPosAsWritten { Unknown = 0, Default, Left, Right }; + void + prettyPrintAttributes(const Decl *D, + AttrPosAsWritten Pos = AttrPosAsWritten::Default); void prettyPrintPragmas(Decl *D); void printDeclType(QualType T, StringRef DeclName, bool Pack = false); }; @@ -250,87 +238,53 @@ raw_ostream& DeclPrinter::Indent(unsigned Indentation) { return Out; } -// For CLANG_ATTR_LIST_CanPrintOnLeft macro. -#include "clang/Basic/AttrLeftSideCanPrintList.inc" +static DeclPrinter::AttrPosAsWritten getPosAsWritten(const Attr *A, + const Decl *D) { + SourceLocation ALoc = A->getLoc(); + SourceLocation DLoc = D->getLocation(); + const ASTContext &C = D->getASTContext(); + if (ALoc.isInvalid() || DLoc.isInvalid()) + return DeclPrinter::AttrPosAsWritten::Unknown; -// For CLANG_ATTR_LIST_PrintOnLeft macro. -#include "clang/Basic/AttrLeftSideMustPrintList.inc" + if (C.getSourceManager().isBeforeInTranslationUnit(ALoc, DLoc)) + return DeclPrinter::AttrPosAsWritten::Left; -static bool canPrintOnLeftSide(attr::Kind kind) { -#ifdef CLANG_ATTR_LIST_CanPrintOnLeft - switch (kind) { - CLANG_ATTR_LIST_CanPrintOnLeft - return true; - default: - return false; - } -#else - return false; -#endif -} - -static bool canPrintOnLeftSide(const Attr *A) { - if (A->isStandardAttributeSyntax()) - return false; - - return canPrintOnLeftSide(A->getKind()); + return DeclPrinter::AttrPosAsWritten::Right; } -static bool mustPrintOnLeftSide(attr::Kind kind) { -#ifdef CLANG_ATTR_LIST_PrintOnLeft - switch (kind) { - CLANG_ATTR_LIST_PrintOnLeft - return true; - default: - return false; - } -#else - return false; -#endif -} - -static bool mustPrintOnLeftSide(const Attr *A) { - if (A->isDeclspecAttribute()) - return true; - - return mustPrintOnLeftSide(A->getKind()); -} - -void DeclPrinter::prettyPrintAttributes(Decl *D, llvm::raw_ostream &Out, - AttrPrintLoc Loc) { +void DeclPrinter::prettyPrintAttributes(const Decl *D, + AttrPosAsWritten Pos /*=Default*/) { if (Policy.PolishForDeclaration) return; if (D->hasAttrs()) { - AttrVec &Attrs = D->getAttrs(); + assert(Pos != AttrPosAsWritten::Unknown && "Use Default"); + const AttrVec &Attrs = D->getAttrs(); for (auto *A : Attrs) { if (A->isInherited() || A->isImplicit()) continue; - - AttrPrintLoc AttrLoc = AttrPrintLoc::Right; - if (mustPrintOnLeftSide(A)) { - // If we must always print on left side (e.g. declspec), then mark as - // so. - AttrLoc = AttrPrintLoc::Left; - } else if (canPrintOnLeftSide(A)) { - // For functions with body defined we print the attributes on the left - // side so that GCC accept our dumps as well. - if (const FunctionDecl *FD = dyn_cast(D); - FD && FD->isThisDeclarationADefinition()) - // In case Decl is a function with a body, then attrs should be print - // on the left side. - AttrLoc = AttrPrintLoc::Left; - - // In case it is a variable declaration with a ctor, then allow - // printing on the left side for readbility. - else if (const VarDecl *VD = dyn_cast(D); - VD && VD->getInit() && - VD->getInitStyle() == VarDecl::CallInit) - AttrLoc = AttrPrintLoc::Left; + switch (A->getKind()) { +#define ATTR(X) +#define PRAGMA_SPELLING_ATTR(X) case attr::X: +#include "clang/Basic/AttrList.inc" + break; + default: + AttrPosAsWritten APos = getPosAsWritten(A, D); + // Might trigger on programatically created attributes or declarations + // with no source locations. + assert(APos != AttrPosAsWritten::Unknown && + "Invalid source location for attribute or decl."); + assert(APos != AttrPosAsWritten::Default && + "Default not a valid for an attribute location"); + if (Pos == AttrPosAsWritten::Default || Pos == APos) { + if (Pos != AttrPosAsWritten::Left) + Out << ' '; + A->printPretty(Out, Policy); + if (Pos == AttrPosAsWritten::Left) + Out << ' '; + } + break; } - // Only print the side matches the user requested. - if ((Loc & AttrLoc) != AttrPrintLoc::None) - A->printPretty(Out, Policy); } } } @@ -691,8 +645,10 @@ static void MaybePrintTagKeywordIfSupressingScopes(PrintingPolicy &Policy, void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { if (!D->getDescribedFunctionTemplate() && - !D->isFunctionTemplateSpecialization()) + !D->isFunctionTemplateSpecialization()) { prettyPrintPragmas(D); + prettyPrintAttributes(D, AttrPosAsWritten::Left); + } if (D->isFunctionTemplateSpecialization()) Out << "template<> "; @@ -702,22 +658,6 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { printTemplateParameters(D->getTemplateParameterList(I)); } - std::string LeftsideAttrs; - llvm::raw_string_ostream LSAS(LeftsideAttrs); - - prettyPrintAttributes(D, LSAS, AttrPrintLoc::Left); - - // prettyPrintAttributes print a space on left side of the attribute. - if (LeftsideAttrs[0] == ' ') { - // Skip the space prettyPrintAttributes generated. - LeftsideAttrs.erase(0, LeftsideAttrs.find_first_not_of(' ')); - - // Add a single space between the attribute and the Decl name. - LSAS << ' '; - } - - Out << LeftsideAttrs; - CXXConstructorDecl *CDecl = dyn_cast(D); CXXConversionDecl *ConversionDecl = dyn_cast(D); CXXDeductionGuideDecl *GuideDecl = dyn_cast(D); @@ -883,7 +823,7 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { Ty.print(Out, Policy, Proto); } - prettyPrintAttributes(D, Out, AttrPrintLoc::Right); + prettyPrintAttributes(D, AttrPosAsWritten::Right); if (D->isPureVirtual()) Out << " = 0"; @@ -976,27 +916,12 @@ void DeclPrinter::VisitLabelDecl(LabelDecl *D) { void DeclPrinter::VisitVarDecl(VarDecl *D) { prettyPrintPragmas(D); + prettyPrintAttributes(D, AttrPosAsWritten::Left); + if (const auto *Param = dyn_cast(D); Param && Param->isExplicitObjectParameter()) Out << "this "; - std::string LeftSide; - llvm::raw_string_ostream LeftSideStream(LeftSide); - - // Print attributes that should be placed on the left, such as __declspec. - prettyPrintAttributes(D, LeftSideStream, AttrPrintLoc::Left); - - // prettyPrintAttributes print a space on left side of the attribute. - if (LeftSide[0] == ' ') { - // Skip the space prettyPrintAttributes generated. - LeftSide.erase(0, LeftSide.find_first_not_of(' ')); - - // Add a single space between the attribute and the Decl name. - LeftSideStream << ' '; - } - - Out << LeftSide; - QualType T = D->getTypeSourceInfo() ? D->getTypeSourceInfo()->getType() : D->getASTContext().getUnqualifiedObjCPointerType(D->getType()); @@ -1029,21 +954,16 @@ void DeclPrinter::VisitVarDecl(VarDecl *D) { } } - StringRef Name; - - Name = (isa(D) && Policy.CleanUglifiedParameters && - D->getIdentifier()) - ? D->getIdentifier()->deuglifiedName() - : D->getName(); - if (!Policy.SuppressTagKeyword && Policy.SuppressScope && !Policy.SuppressUnwrittenScope) MaybePrintTagKeywordIfSupressingScopes(Policy, T, Out); - printDeclType(T, Name); - // Print the attributes that should be placed right before the end of the - // decl. - prettyPrintAttributes(D, Out, AttrPrintLoc::Right); + printDeclType(T, (isa(D) && Policy.CleanUglifiedParameters && + D->getIdentifier()) + ? D->getIdentifier()->deuglifiedName() + : D->getName()); + + prettyPrintAttributes(D, AttrPosAsWritten::Right); Expr *Init = D->getInit(); if (!Policy.SuppressInitializers && Init) { diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index 74b18e50bf1f..2ba93d17f267 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -292,8 +292,11 @@ void StmtPrinter::VisitLabelStmt(LabelStmt *Node) { } void StmtPrinter::VisitAttributedStmt(AttributedStmt *Node) { - for (const auto *Attr : Node->getAttrs()) { + llvm::ArrayRef Attrs = Node->getAttrs(); + for (const auto *Attr : Attrs) { Attr->printPretty(OS, Policy); + if (Attr != Attrs.back()) + OS << ' '; } PrintStmt(Node->getSubStmt(), 0); diff --git a/clang/test/AST/ast-print-method-decl.cpp b/clang/test/AST/ast-print-method-decl.cpp index 75dea0cac16b..cb5d10096381 100644 --- a/clang/test/AST/ast-print-method-decl.cpp +++ b/clang/test/AST/ast-print-method-decl.cpp @@ -94,7 +94,7 @@ struct DefMethodsWithoutBody { // CHECK-NEXT: DefMethodsWithoutBody() = default; ~DefMethodsWithoutBody() = default; - // CHECK-NEXT: __attribute__((alias("X"))) void m1(); + // CHECK-NEXT: void m1() __attribute__((alias("X"))); void m1() __attribute__((alias("X"))); // CHECK-NEXT: }; diff --git a/clang/test/AST/ast-print-no-sanitize.cpp b/clang/test/AST/ast-print-no-sanitize.cpp index 4ff97190955a..a5ada8246f0c 100644 --- a/clang/test/AST/ast-print-no-sanitize.cpp +++ b/clang/test/AST/ast-print-no-sanitize.cpp @@ -4,4 +4,4 @@ void should_not_crash_1() __attribute__((no_sanitize_memory)); [[clang::no_sanitize_memory]] void should_not_crash_2(); // CHECK: void should_not_crash_1() __attribute__((no_sanitize("memory"))); -// CHECK: void should_not_crash_2() {{\[\[}}clang::no_sanitize("memory"){{\]\]}}; +// CHECK: {{\[\[}}clang::no_sanitize("memory"){{\]\]}} void should_not_crash_2(); diff --git a/clang/test/AST/attr-print-emit.cpp b/clang/test/AST/attr-print-emit.cpp index 8c48eb92daba..8c8a2b208059 100644 --- a/clang/test/AST/attr-print-emit.cpp +++ b/clang/test/AST/attr-print-emit.cpp @@ -73,3 +73,18 @@ class C { // CHECK: void pwtt(void *, int) __attribute__((pointer_with_type_tag(foo, 2, 3))); void pwtt(void *, int) __attribute__((pointer_with_type_tag(foo, 2, 3))); }; + +#define ANNOTATE_ATTR __attribute__((annotate("Annotated"))) +ANNOTATE_ATTR int annotated_attr ANNOTATE_ATTR = 0; +// CHECK: __attribute__((annotate("Annotated"))) int annotated_attr __attribute__((annotate("Annotated"))) = 0; + +// FIXME: We do not print the attribute as written after the type specifier. +int ANNOTATE_ATTR annotated_attr_fixme = 0; +// CHECK: __attribute__((annotate("Annotated"))) int annotated_attr_fixme = 0; + +#define NONNULL_ATTR __attribute__((nonnull(1))) +ANNOTATE_ATTR NONNULL_ATTR void fn_non_null_annotated_attr(int *) __attribute__((annotate("AnnotatedRHS"))); +// CHECK:__attribute__((annotate("Annotated"))) __attribute__((nonnull(1))) void fn_non_null_annotated_attr(int *) __attribute__((annotate("AnnotatedRHS"))); + +[[gnu::nonnull(1)]] [[gnu::always_inline]] void cxx11_attr(int*) ANNOTATE_ATTR; +// CHECK: {{\[\[}}gnu::nonnull(1)]] {{\[\[}}gnu::always_inline]] void cxx11_attr(int *) __attribute__((annotate("Annotated"))); diff --git a/clang/test/Analysis/scopes-cfg-output.cpp b/clang/test/Analysis/scopes-cfg-output.cpp index 4eb8967e3735..5e6706602d45 100644 --- a/clang/test/Analysis/scopes-cfg-output.cpp +++ b/clang/test/Analysis/scopes-cfg-output.cpp @@ -1469,7 +1469,7 @@ void test_cleanup_functions2(int m) { // CHECK: [B1] // CHECK-NEXT: 1: CFGScopeBegin(f) // CHECK-NEXT: 2: (CXXConstructExpr, [B1.3], F) -// CHECK-NEXT: 3: __attribute__((cleanup(cleanup_F))) F f; +// CHECK-NEXT: 3: F f __attribute__((cleanup(cleanup_F))); // CHECK-NEXT: 4: CleanupFunction (cleanup_F) // CHECK-NEXT: 5: [B1.3].~F() (Implicit destructor) // CHECK-NEXT: 6: CFGScopeEnd(f) diff --git a/clang/test/OpenMP/assumes_codegen.cpp b/clang/test/OpenMP/assumes_codegen.cpp index 6a5871c303aa..4a2518a51ec3 100644 --- a/clang/test/OpenMP/assumes_codegen.cpp +++ b/clang/test/OpenMP/assumes_codegen.cpp @@ -67,7 +67,7 @@ int lambda_outer() { } #pragma omp end assumes -// AST: __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void foo() { +// AST: void foo() __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) { // AST-NEXT: } // AST-NEXT: class BAR { // AST-NEXT: public: @@ -81,7 +81,7 @@ int lambda_outer() { // AST-NEXT: __attribute__((assume("ompx_range_bar_only"))) __attribute__((assume("ompx_range_bar_only_2"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void bar() { // AST-NEXT: BAR b; // AST-NEXT: } -// AST-NEXT: void baz() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); +// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz(); // AST-NEXT: template class BAZ { // AST-NEXT: public: // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) BAZ() { @@ -95,8 +95,8 @@ int lambda_outer() { // AST-NEXT: public: // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) BAZ() { // AST-NEXT: } -// AST-NEXT: void baz1() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); -// AST-NEXT: static void baz2() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); +// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz1(); +// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) static void baz2(); // AST-NEXT: }; // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz() { // AST-NEXT: BAZ b; diff --git a/clang/test/OpenMP/assumes_print.cpp b/clang/test/OpenMP/assumes_print.cpp index a7f04edb3b1a..da3629f70408 100644 --- a/clang/test/OpenMP/assumes_print.cpp +++ b/clang/test/OpenMP/assumes_print.cpp @@ -37,7 +37,7 @@ void baz() { } #pragma omp end assumes -// CHECK: __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void foo() +// CHECK: void foo() __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) // CHECK: __attribute__((assume("ompx_range_bar_only"))) __attribute__((assume("ompx_range_bar_only_2"))) __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void bar() // CHECK: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void baz() diff --git a/clang/test/OpenMP/assumes_template_print.cpp b/clang/test/OpenMP/assumes_template_print.cpp index bd1100fbefff..e0bc3e9884ca 100644 --- a/clang/test/OpenMP/assumes_template_print.cpp +++ b/clang/test/OpenMP/assumes_template_print.cpp @@ -17,7 +17,7 @@ template struct S { int a; // CHECK: template struct S { -// CHECK: __attribute__((assume("ompx_global_assumption"))) void foo() { +// CHECK: void foo() __attribute__((assume("ompx_global_assumption"))) { void foo() { #pragma omp parallel {} @@ -25,15 +25,15 @@ struct S { }; // CHECK: template<> struct S { -// CHECK: __attribute__((assume("ompx_global_assumption"))) void foo() { +// CHECK: void foo() __attribute__((assume("ompx_global_assumption"))) { #pragma omp begin assumes no_openmp -// CHECK: __attribute__((assume("omp_no_openmp"))) __attribute__((assume("ompx_global_assumption"))) void S_with_assumes_no_call() { +// CHECK: __attribute__((assume("omp_no_openmp"))) void S_with_assumes_no_call() __attribute__((assume("ompx_global_assumption"))) { void S_with_assumes_no_call() { S s; s.a = 0; } -// CHECK: __attribute__((assume("omp_no_openmp"))) __attribute__((assume("ompx_global_assumption"))) void S_with_assumes_call() { +// CHECK: __attribute__((assume("omp_no_openmp"))) void S_with_assumes_call() __attribute__((assume("ompx_global_assumption"))) { void S_with_assumes_call() { S s; s.a = 0; @@ -42,7 +42,7 @@ void S_with_assumes_call() { } #pragma omp end assumes -// CHECK: __attribute__((assume("ompx_global_assumption"))) void S_without_assumes() { +// CHECK: void S_without_assumes() __attribute__((assume("ompx_global_assumption"))) { void S_without_assumes() { S s; s.foo(); diff --git a/clang/test/OpenMP/declare_simd_ast_print.cpp b/clang/test/OpenMP/declare_simd_ast_print.cpp index 1adf95226c8b..565dc2dfc04d 100644 --- a/clang/test/OpenMP/declare_simd_ast_print.cpp +++ b/clang/test/OpenMP/declare_simd_ast_print.cpp @@ -60,11 +60,11 @@ void h(int *hp, int *hp2, int *hq, int *lin) class VV { // CHECK: #pragma omp declare simd uniform(this, a) linear(val(b): a) - // CHECK-NEXT: __attribute__((cold)) int add(int a, int b) { + // CHECK-NEXT: int add(int a, int b) __attribute__((cold)) { // CHECK-NEXT: return a + b; // CHECK-NEXT: } #pragma omp declare simd uniform(this, a) linear(val(b): a) - __attribute__((cold)) int add(int a, int b) { return a + b; } + int add(int a, int b) __attribute__((cold)) { return a + b; } // CHECK: #pragma omp declare simd aligned(b: 4) aligned(a) linear(ref(b): 4) linear(val(this)) linear(val(a)) // CHECK-NEXT: float taddpf(float *a, float *&b) { diff --git a/clang/test/SemaCXX/attr-no-sanitize.cpp b/clang/test/SemaCXX/attr-no-sanitize.cpp index a464947fe5a3..8951f616ce0f 100644 --- a/clang/test/SemaCXX/attr-no-sanitize.cpp +++ b/clang/test/SemaCXX/attr-no-sanitize.cpp @@ -16,12 +16,12 @@ int f3() __attribute__((no_sanitize("address"))); // DUMP-LABEL: FunctionDecl {{.*}} f4 // DUMP: NoSanitizeAttr {{.*}} thread -// PRINT: int f4() {{\[\[}}clang::no_sanitize("thread")]] +// PRINT: {{\[\[}}clang::no_sanitize("thread")]] int f4() [[clang::no_sanitize("thread")]] int f4(); // DUMP-LABEL: FunctionDecl {{.*}} f4 // DUMP: NoSanitizeAttr {{.*}} hwaddress -// PRINT: int f4() {{\[\[}}clang::no_sanitize("hwaddress")]] +// PRINT: {{\[\[}}clang::no_sanitize("hwaddress")]] int f4() [[clang::no_sanitize("hwaddress")]] int f4(); // DUMP-LABEL: FunctionDecl {{.*}} f5 @@ -36,5 +36,5 @@ int f6() __attribute__((no_sanitize("unknown"))); // expected-warning{{unknown s // DUMP-LABEL: FunctionDecl {{.*}} f7 // DUMP: NoSanitizeAttr {{.*}} memtag -// PRINT: int f7() {{\[\[}}clang::no_sanitize("memtag")]] +// PRINT: {{\[\[}}clang::no_sanitize("memtag")]] int f7() [[clang::no_sanitize("memtag")]] int f7(); diff --git a/clang/test/SemaCXX/cxx11-attr-print.cpp b/clang/test/SemaCXX/cxx11-attr-print.cpp index c988972aeb1a..a169d1b4409b 100644 --- a/clang/test/SemaCXX/cxx11-attr-print.cpp +++ b/clang/test/SemaCXX/cxx11-attr-print.cpp @@ -24,10 +24,10 @@ int d [[deprecated("warning")]]; // CHECK: __attribute__((deprecated("warning", "fixit"))); int e __attribute__((deprecated("warning", "fixit"))); -// CHECK: int cxx11_alignas alignas(4); +// CHECK: alignas(4) int cxx11_alignas; alignas(4) int cxx11_alignas; -// CHECK: int c11_alignas _Alignas(int); +// CHECK: _Alignas(int) int c11_alignas; _Alignas(int) int c11_alignas; // CHECK: int foo() __attribute__((const)); @@ -66,7 +66,7 @@ void f8 (void *, const char *, ...) __attribute__ ((format (printf, 2, 3))); // CHECK: int n alignas(4 // CHECK: int p alignas(int // CHECK: __attribute__((pure)) static int f() -// CHECK: static int g() {{\[}}[gnu::pure]] +// CHECK: {{\[}}[gnu::pure]] static int g() template struct S { __attribute__((aligned(4))) int m; alignas(4) int n; @@ -82,7 +82,7 @@ template struct S { // CHECK: int m __attribute__((aligned(4 // CHECK: int n alignas(4 // CHECK: __attribute__((pure)) static int f() -// CHECK: static int g() {{\[}}[gnu::pure]] +// CHECK: {{\[}}[gnu::pure]] static int g() template struct S; // CHECK: using Small2 {{\[}}[gnu::mode(byte)]] = int; diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp index eb5c34d15693..6c56f99f503d 100644 --- a/clang/utils/TableGen/ClangAttrEmitter.cpp +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp @@ -1591,10 +1591,10 @@ writePrettyPrintFunction(const Record &R, std::string Variety = Spellings[I].variety(); if (Variety == "GNU") { - Prefix = " __attribute__(("; + Prefix = "__attribute__(("; Suffix = "))"; } else if (Variety == "CXX11" || Variety == "C23") { - Prefix = " [["; + Prefix = "[["; Suffix = "]]"; std::string Namespace = Spellings[I].nameSpace(); if (!Namespace.empty()) { @@ -1602,7 +1602,7 @@ writePrettyPrintFunction(const Record &R, Spelling += "::"; } } else if (Variety == "Declspec") { - Prefix = " __declspec("; + Prefix = "__declspec("; Suffix = ")"; } else if (Variety == "Microsoft") { Prefix = "["; @@ -3316,37 +3316,6 @@ void EmitClangAttrList(RecordKeeper &Records, raw_ostream &OS) { OS << "#undef PRAGMA_SPELLING_ATTR\n"; } -// Emits the enumeration list for attributes. -void EmitClangAttrPrintList(const std::string &FieldName, RecordKeeper &Records, - raw_ostream &OS) { - emitSourceFileHeader( - "List of attributes that can be print on the left side of a decl", OS, - Records); - - AttrClassHierarchy Hierarchy(Records); - - std::vector Attrs = Records.getAllDerivedDefinitions("Attr"); - std::vector PragmaAttrs; - bool first = false; - - for (auto *Attr : Attrs) { - if (!Attr->getValueAsBit("ASTNode")) - continue; - - if (!Attr->getValueAsBit(FieldName)) - continue; - - if (!first) { - first = true; - OS << "#define CLANG_ATTR_LIST_" << FieldName; - } - - OS << " \\\n case attr::" << Attr->getName() << ":"; - } - - OS << '\n'; -} - // Emits the enumeration list for attributes. void EmitClangAttrSubjectMatchRuleList(RecordKeeper &Records, raw_ostream &OS) { emitSourceFileHeader( diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index 3f22e43b97ec..42cc704543f1 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -31,8 +31,6 @@ enum ActionType { GenClangAttrSubjectMatchRulesParserStringSwitches, GenClangAttrImpl, GenClangAttrList, - GenClangAttrCanPrintLeftList, - GenClangAttrMustPrintLeftList, GenClangAttrDocTable, GenClangAttrSubjectMatchRuleList, GenClangAttrPCHRead, @@ -134,14 +132,6 @@ cl::opt Action( "Generate clang attribute implementations"), clEnumValN(GenClangAttrList, "gen-clang-attr-list", "Generate a clang attribute list"), - clEnumValN(GenClangAttrCanPrintLeftList, - "gen-clang-attr-can-print-left-list", - "Generate list of attributes that can be printed on left " - "side of a decl"), - clEnumValN(GenClangAttrMustPrintLeftList, - "gen-clang-attr-must-print-left-list", - "Generate list of attributes that must be printed on left " - "side of a decl"), clEnumValN(GenClangAttrDocTable, "gen-clang-attr-doc-table", "Generate a table of attribute documentation"), clEnumValN(GenClangAttrSubjectMatchRuleList, @@ -345,12 +335,6 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenClangAttrList: EmitClangAttrList(Records, OS); break; - case GenClangAttrCanPrintLeftList: - EmitClangAttrPrintList("CanPrintOnLeft", Records, OS); - break; - case GenClangAttrMustPrintLeftList: - EmitClangAttrPrintList("PrintOnLeft", Records, OS); - break; case GenClangAttrDocTable: EmitClangAttrDocTable(Records, OS); break; diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index ecd506b7b6b5..5f2dd257cb90 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -47,8 +47,6 @@ void EmitClangAttrSubjectMatchRulesParserStringSwitches( void EmitClangAttrClass(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrImpl(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); -void EmitClangAttrPrintList(const std::string &FieldName, - llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrSubjectMatchRuleList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHRead(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); -- GitLab From 5c056b32350e834924356b1af78504d261d24e42 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Mon, 8 Apr 2024 21:17:12 -0700 Subject: [PATCH 237/695] [clang-format] Clean up unit tests from commit 13be0d4a34c4 - Use 1-parameter verifyFormat() to verify formatted input in LLVM style. - Pass string literal instead of constructed StringRef to verifyFormat(). - Don't include trailing newlines if not needed. --- clang/unittests/Format/FormatTest.cpp | 50 +++++++++++++-------------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 91a8ff11889d..71450f433cec 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -7977,39 +7977,37 @@ TEST_F(FormatTest, AllowAllArgumentsOnNextLineDontAlign) { } TEST_F(FormatTest, BreakFunctionDefinitionParameters) { - FormatStyle Style = getLLVMStyle(); - EXPECT_FALSE(Style.BreakFunctionDefinitionParameters); StringRef Input = "void functionDecl(paramA, paramB, paramC);\n" "void emptyFunctionDefinition() {}\n" "void functionDefinition(int A, int B, int C) {}\n" - "Class::Class(int A, int B) : m_A(A), m_B(B) {}\n"; - verifyFormat(StringRef("void functionDecl(paramA, paramB, paramC);\n" - "void emptyFunctionDefinition() {}\n" - "void functionDefinition(int A, int B, int C) {}\n" - "Class::Class(int A, int B) : m_A(A), m_B(B) {}\n"), - Input, Style); + "Class::Class(int A, int B) : m_A(A), m_B(B) {}"; + verifyFormat(Input); + + FormatStyle Style = getLLVMStyle(); + EXPECT_FALSE(Style.BreakFunctionDefinitionParameters); Style.BreakFunctionDefinitionParameters = true; - verifyFormat(StringRef("void functionDecl(paramA, paramB, paramC);\n" - "void emptyFunctionDefinition() {}\n" - "void functionDefinition(\n" - " int A, int B, int C) {}\n" - "Class::Class(\n" - " int A, int B)\n" - " : m_A(A), m_B(B) {}\n"), + verifyFormat("void functionDecl(paramA, paramB, paramC);\n" + "void emptyFunctionDefinition() {}\n" + "void functionDefinition(\n" + " int A, int B, int C) {}\n" + "Class::Class(\n" + " int A, int B)\n" + " : m_A(A), m_B(B) {}", Input, Style); - // Test the style where all parameters are on their own lines + + // Test the style where all parameters are on their own lines. Style.AllowAllParametersOfDeclarationOnNextLine = false; Style.BinPackParameters = false; - verifyFormat(StringRef("void functionDecl(paramA, paramB, paramC);\n" - "void emptyFunctionDefinition() {}\n" - "void functionDefinition(\n" - " int A,\n" - " int B,\n" - " int C) {}\n" - "Class::Class(\n" - " int A,\n" - " int B)\n" - " : m_A(A), m_B(B) {}\n"), + verifyFormat("void functionDecl(paramA, paramB, paramC);\n" + "void emptyFunctionDefinition() {}\n" + "void functionDefinition(\n" + " int A,\n" + " int B,\n" + " int C) {}\n" + "Class::Class(\n" + " int A,\n" + " int B)\n" + " : m_A(A), m_B(B) {}", Input, Style); } -- GitLab From b65ab0b726ce421cc6cd7fdfbf51bf4aba17ce87 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Mon, 8 Apr 2024 23:33:06 -0500 Subject: [PATCH 238/695] [ValueTracking] Add comment clarifying missing `usub.sat` in `isKnownNonZero`; NFC Closes #87700 --- llvm/lib/Analysis/ValueTracking.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index d50ccd8af287..6602db424fc2 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2816,6 +2816,8 @@ static bool isKnownNonZeroFromOperator(const Operator *I, case Intrinsic::bswap: case Intrinsic::ctpop: return isKnownNonZero(II->getArgOperand(0), DemandedElts, Depth, Q); + // NB: We don't do usub_sat here as in any case we can prove its + // non-zero, we will fold it to `sub nuw` in InstCombine. case Intrinsic::ssub_sat: return isNonZeroSub(DemandedElts, Depth, Q, BitWidth, II->getArgOperand(0), II->getArgOperand(1)); -- GitLab From d10983b8a39abdbfaffd207720f67f96227b5ac9 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Mon, 8 Apr 2024 22:36:50 -0600 Subject: [PATCH 239/695] [ORC] Replace KV loop variables with structured bindings, fix typo. Coding my way home: 2.29247S, 94.15173W --- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h index 286112a0b46a..09b2f6a10e35 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h @@ -227,14 +227,14 @@ public: } /// Construct a SymbolLookupSet from DenseMap keys. - template + template static SymbolLookupSet - fromMapKeys(const DenseMap &M, + fromMapKeys(const DenseMap &M, SymbolLookupFlags Flags = SymbolLookupFlags::RequiredSymbol) { SymbolLookupSet Result; Result.Symbols.reserve(M.size()); - for (const auto &KV : M) - Result.add(KV.first, Flags); + for (const auto &[Name, Val] : M) + Result.add(Name, Flags); return Result; } -- GitLab From 62e92573d28d62ab7e6438ac34d513b07c51ce09 Mon Sep 17 00:00:00 2001 From: Vassil Vassilev Date: Tue, 9 Apr 2024 05:02:49 +0000 Subject: [PATCH 240/695] Revert "Rework the printing of attributes (#87281)" This reverts commit a30662fc2acdd73ca1a9217716299a4676999fb4 due to bot failures. --- clang/include/clang/Basic/Attr.td | 14 +- clang/include/clang/Basic/CMakeLists.txt | 10 + clang/lib/AST/DeclPrinter.cpp | 184 +++++++++++++------ clang/lib/AST/StmtPrinter.cpp | 5 +- clang/test/AST/ast-print-method-decl.cpp | 2 +- clang/test/AST/ast-print-no-sanitize.cpp | 2 +- clang/test/AST/attr-print-emit.cpp | 15 -- clang/test/Analysis/scopes-cfg-output.cpp | 2 +- clang/test/OpenMP/assumes_codegen.cpp | 8 +- clang/test/OpenMP/assumes_print.cpp | 2 +- clang/test/OpenMP/assumes_template_print.cpp | 10 +- clang/test/OpenMP/declare_simd_ast_print.cpp | 4 +- clang/test/SemaCXX/attr-no-sanitize.cpp | 6 +- clang/test/SemaCXX/cxx11-attr-print.cpp | 8 +- clang/utils/TableGen/ClangAttrEmitter.cpp | 37 +++- clang/utils/TableGen/TableGen.cpp | 16 ++ clang/utils/TableGen/TableGenBackends.h | 2 + 17 files changed, 230 insertions(+), 97 deletions(-) diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index dc87a8c6f022..6584460cf568 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -324,10 +324,13 @@ class Spelling { } class GNU : Spelling; -class Declspec : Spelling; +class Declspec : Spelling { + bit PrintOnLeft = 1; +} class Microsoft : Spelling; class CXX11 : Spelling { + bit CanPrintOnLeft = 0; string Namespace = namespace; } class C23 @@ -593,6 +596,12 @@ class AttrSubjectMatcherAggregateRule { def SubjectMatcherForNamed : AttrSubjectMatcherAggregateRule; class Attr { + // Specifies that when printed, this attribute is meaningful on the + // 'left side' of the declaration. + bit CanPrintOnLeft = 1; + // Specifies that when printed, this attribute is required to be printed on + // the 'left side' of the declaration. + bit PrintOnLeft = 0; // The various ways in which an attribute can be spelled in source list Spellings; // The things to which an attribute can appertain @@ -928,6 +937,7 @@ def AVRSignal : InheritableAttr, TargetSpecificAttr { } def AsmLabel : InheritableAttr { + let CanPrintOnLeft = 0; let Spellings = [CustomKeyword<"asm">, CustomKeyword<"__asm__">]; let Args = [ // Label specifies the mangled name for the decl. @@ -1524,6 +1534,7 @@ def AllocSize : InheritableAttr { } def EnableIf : InheritableAttr { + let CanPrintOnLeft = 0; // Does not have a [[]] spelling because this attribute requires the ability // to parse function arguments but the attribute is not written in the type // position. @@ -3160,6 +3171,7 @@ def Unavailable : InheritableAttr { } def DiagnoseIf : InheritableAttr { + let CanPrintOnLeft = 0; // Does not have a [[]] spelling because this attribute requires the ability // to parse function arguments but the attribute is not written in the type // position. diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt index 2ef6ddc68f4b..7d53c751c13a 100644 --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -31,6 +31,16 @@ clang_tablegen(AttrList.inc -gen-clang-attr-list SOURCE Attr.td TARGET ClangAttrList) +clang_tablegen(AttrLeftSideCanPrintList.inc -gen-clang-attr-can-print-left-list + -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ + SOURCE Attr.td + TARGET ClangAttrCanPrintLeftList) + +clang_tablegen(AttrLeftSideMustPrintList.inc -gen-clang-attr-must-print-left-list + -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ + SOURCE Attr.td + TARGET ClangAttrMustPrintLeftList) + clang_tablegen(AttrSubMatchRulesList.inc -gen-clang-attr-subject-match-rule-list -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ SOURCE Attr.td diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index 0d03288a491a..edbcdfe4d55b 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -21,7 +21,6 @@ #include "clang/AST/ExprCXX.h" #include "clang/AST/PrettyPrinter.h" #include "clang/Basic/Module.h" -#include "clang/Basic/SourceManager.h" #include "llvm/Support/raw_ostream.h" using namespace clang; @@ -50,6 +49,18 @@ namespace { void PrintObjCTypeParams(ObjCTypeParamList *Params); + enum class AttrPrintLoc { + None = 0, + Left = 1, + Right = 2, + Any = Left | Right, + + LLVM_MARK_AS_BITMASK_ENUM(/*DefaultValue=*/Any) + }; + + void prettyPrintAttributes(Decl *D, raw_ostream &out, + AttrPrintLoc loc = AttrPrintLoc::Any); + public: DeclPrinter(raw_ostream &Out, const PrintingPolicy &Policy, const ASTContext &Context, unsigned Indentation = 0, @@ -118,10 +129,11 @@ namespace { const TemplateParameterList *Params); void printTemplateArguments(llvm::ArrayRef Args, const TemplateParameterList *Params); - enum class AttrPosAsWritten { Unknown = 0, Default, Left, Right }; - void - prettyPrintAttributes(const Decl *D, - AttrPosAsWritten Pos = AttrPosAsWritten::Default); + + inline void prettyPrintAttributes(Decl *D) { + prettyPrintAttributes(D, Out); + } + void prettyPrintPragmas(Decl *D); void printDeclType(QualType T, StringRef DeclName, bool Pack = false); }; @@ -238,53 +250,87 @@ raw_ostream& DeclPrinter::Indent(unsigned Indentation) { return Out; } -static DeclPrinter::AttrPosAsWritten getPosAsWritten(const Attr *A, - const Decl *D) { - SourceLocation ALoc = A->getLoc(); - SourceLocation DLoc = D->getLocation(); - const ASTContext &C = D->getASTContext(); - if (ALoc.isInvalid() || DLoc.isInvalid()) - return DeclPrinter::AttrPosAsWritten::Unknown; +// For CLANG_ATTR_LIST_CanPrintOnLeft macro. +#include "clang/Basic/AttrLeftSideCanPrintList.inc" - if (C.getSourceManager().isBeforeInTranslationUnit(ALoc, DLoc)) - return DeclPrinter::AttrPosAsWritten::Left; +// For CLANG_ATTR_LIST_PrintOnLeft macro. +#include "clang/Basic/AttrLeftSideMustPrintList.inc" - return DeclPrinter::AttrPosAsWritten::Right; +static bool canPrintOnLeftSide(attr::Kind kind) { +#ifdef CLANG_ATTR_LIST_CanPrintOnLeft + switch (kind) { + CLANG_ATTR_LIST_CanPrintOnLeft + return true; + default: + return false; + } +#else + return false; +#endif +} + +static bool canPrintOnLeftSide(const Attr *A) { + if (A->isStandardAttributeSyntax()) + return false; + + return canPrintOnLeftSide(A->getKind()); } -void DeclPrinter::prettyPrintAttributes(const Decl *D, - AttrPosAsWritten Pos /*=Default*/) { +static bool mustPrintOnLeftSide(attr::Kind kind) { +#ifdef CLANG_ATTR_LIST_PrintOnLeft + switch (kind) { + CLANG_ATTR_LIST_PrintOnLeft + return true; + default: + return false; + } +#else + return false; +#endif +} + +static bool mustPrintOnLeftSide(const Attr *A) { + if (A->isDeclspecAttribute()) + return true; + + return mustPrintOnLeftSide(A->getKind()); +} + +void DeclPrinter::prettyPrintAttributes(Decl *D, llvm::raw_ostream &Out, + AttrPrintLoc Loc) { if (Policy.PolishForDeclaration) return; if (D->hasAttrs()) { - assert(Pos != AttrPosAsWritten::Unknown && "Use Default"); - const AttrVec &Attrs = D->getAttrs(); + AttrVec &Attrs = D->getAttrs(); for (auto *A : Attrs) { if (A->isInherited() || A->isImplicit()) continue; - switch (A->getKind()) { -#define ATTR(X) -#define PRAGMA_SPELLING_ATTR(X) case attr::X: -#include "clang/Basic/AttrList.inc" - break; - default: - AttrPosAsWritten APos = getPosAsWritten(A, D); - // Might trigger on programatically created attributes or declarations - // with no source locations. - assert(APos != AttrPosAsWritten::Unknown && - "Invalid source location for attribute or decl."); - assert(APos != AttrPosAsWritten::Default && - "Default not a valid for an attribute location"); - if (Pos == AttrPosAsWritten::Default || Pos == APos) { - if (Pos != AttrPosAsWritten::Left) - Out << ' '; - A->printPretty(Out, Policy); - if (Pos == AttrPosAsWritten::Left) - Out << ' '; - } - break; + + AttrPrintLoc AttrLoc = AttrPrintLoc::Right; + if (mustPrintOnLeftSide(A)) { + // If we must always print on left side (e.g. declspec), then mark as + // so. + AttrLoc = AttrPrintLoc::Left; + } else if (canPrintOnLeftSide(A)) { + // For functions with body defined we print the attributes on the left + // side so that GCC accept our dumps as well. + if (const FunctionDecl *FD = dyn_cast(D); + FD && FD->isThisDeclarationADefinition()) + // In case Decl is a function with a body, then attrs should be print + // on the left side. + AttrLoc = AttrPrintLoc::Left; + + // In case it is a variable declaration with a ctor, then allow + // printing on the left side for readbility. + else if (const VarDecl *VD = dyn_cast(D); + VD && VD->getInit() && + VD->getInitStyle() == VarDecl::CallInit) + AttrLoc = AttrPrintLoc::Left; } + // Only print the side matches the user requested. + if ((Loc & AttrLoc) != AttrPrintLoc::None) + A->printPretty(Out, Policy); } } } @@ -645,10 +691,8 @@ static void MaybePrintTagKeywordIfSupressingScopes(PrintingPolicy &Policy, void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { if (!D->getDescribedFunctionTemplate() && - !D->isFunctionTemplateSpecialization()) { + !D->isFunctionTemplateSpecialization()) prettyPrintPragmas(D); - prettyPrintAttributes(D, AttrPosAsWritten::Left); - } if (D->isFunctionTemplateSpecialization()) Out << "template<> "; @@ -658,6 +702,22 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { printTemplateParameters(D->getTemplateParameterList(I)); } + std::string LeftsideAttrs; + llvm::raw_string_ostream LSAS(LeftsideAttrs); + + prettyPrintAttributes(D, LSAS, AttrPrintLoc::Left); + + // prettyPrintAttributes print a space on left side of the attribute. + if (LeftsideAttrs[0] == ' ') { + // Skip the space prettyPrintAttributes generated. + LeftsideAttrs.erase(0, LeftsideAttrs.find_first_not_of(' ')); + + // Add a single space between the attribute and the Decl name. + LSAS << ' '; + } + + Out << LeftsideAttrs; + CXXConstructorDecl *CDecl = dyn_cast(D); CXXConversionDecl *ConversionDecl = dyn_cast(D); CXXDeductionGuideDecl *GuideDecl = dyn_cast(D); @@ -823,7 +883,7 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { Ty.print(Out, Policy, Proto); } - prettyPrintAttributes(D, AttrPosAsWritten::Right); + prettyPrintAttributes(D, Out, AttrPrintLoc::Right); if (D->isPureVirtual()) Out << " = 0"; @@ -916,12 +976,27 @@ void DeclPrinter::VisitLabelDecl(LabelDecl *D) { void DeclPrinter::VisitVarDecl(VarDecl *D) { prettyPrintPragmas(D); - prettyPrintAttributes(D, AttrPosAsWritten::Left); - if (const auto *Param = dyn_cast(D); Param && Param->isExplicitObjectParameter()) Out << "this "; + std::string LeftSide; + llvm::raw_string_ostream LeftSideStream(LeftSide); + + // Print attributes that should be placed on the left, such as __declspec. + prettyPrintAttributes(D, LeftSideStream, AttrPrintLoc::Left); + + // prettyPrintAttributes print a space on left side of the attribute. + if (LeftSide[0] == ' ') { + // Skip the space prettyPrintAttributes generated. + LeftSide.erase(0, LeftSide.find_first_not_of(' ')); + + // Add a single space between the attribute and the Decl name. + LeftSideStream << ' '; + } + + Out << LeftSide; + QualType T = D->getTypeSourceInfo() ? D->getTypeSourceInfo()->getType() : D->getASTContext().getUnqualifiedObjCPointerType(D->getType()); @@ -954,16 +1029,21 @@ void DeclPrinter::VisitVarDecl(VarDecl *D) { } } + StringRef Name; + + Name = (isa(D) && Policy.CleanUglifiedParameters && + D->getIdentifier()) + ? D->getIdentifier()->deuglifiedName() + : D->getName(); + if (!Policy.SuppressTagKeyword && Policy.SuppressScope && !Policy.SuppressUnwrittenScope) MaybePrintTagKeywordIfSupressingScopes(Policy, T, Out); + printDeclType(T, Name); - printDeclType(T, (isa(D) && Policy.CleanUglifiedParameters && - D->getIdentifier()) - ? D->getIdentifier()->deuglifiedName() - : D->getName()); - - prettyPrintAttributes(D, AttrPosAsWritten::Right); + // Print the attributes that should be placed right before the end of the + // decl. + prettyPrintAttributes(D, Out, AttrPrintLoc::Right); Expr *Init = D->getInit(); if (!Policy.SuppressInitializers && Init) { diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index 2ba93d17f267..74b18e50bf1f 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -292,11 +292,8 @@ void StmtPrinter::VisitLabelStmt(LabelStmt *Node) { } void StmtPrinter::VisitAttributedStmt(AttributedStmt *Node) { - llvm::ArrayRef Attrs = Node->getAttrs(); - for (const auto *Attr : Attrs) { + for (const auto *Attr : Node->getAttrs()) { Attr->printPretty(OS, Policy); - if (Attr != Attrs.back()) - OS << ' '; } PrintStmt(Node->getSubStmt(), 0); diff --git a/clang/test/AST/ast-print-method-decl.cpp b/clang/test/AST/ast-print-method-decl.cpp index cb5d10096381..75dea0cac16b 100644 --- a/clang/test/AST/ast-print-method-decl.cpp +++ b/clang/test/AST/ast-print-method-decl.cpp @@ -94,7 +94,7 @@ struct DefMethodsWithoutBody { // CHECK-NEXT: DefMethodsWithoutBody() = default; ~DefMethodsWithoutBody() = default; - // CHECK-NEXT: void m1() __attribute__((alias("X"))); + // CHECK-NEXT: __attribute__((alias("X"))) void m1(); void m1() __attribute__((alias("X"))); // CHECK-NEXT: }; diff --git a/clang/test/AST/ast-print-no-sanitize.cpp b/clang/test/AST/ast-print-no-sanitize.cpp index a5ada8246f0c..4ff97190955a 100644 --- a/clang/test/AST/ast-print-no-sanitize.cpp +++ b/clang/test/AST/ast-print-no-sanitize.cpp @@ -4,4 +4,4 @@ void should_not_crash_1() __attribute__((no_sanitize_memory)); [[clang::no_sanitize_memory]] void should_not_crash_2(); // CHECK: void should_not_crash_1() __attribute__((no_sanitize("memory"))); -// CHECK: {{\[\[}}clang::no_sanitize("memory"){{\]\]}} void should_not_crash_2(); +// CHECK: void should_not_crash_2() {{\[\[}}clang::no_sanitize("memory"){{\]\]}}; diff --git a/clang/test/AST/attr-print-emit.cpp b/clang/test/AST/attr-print-emit.cpp index 8c8a2b208059..8c48eb92daba 100644 --- a/clang/test/AST/attr-print-emit.cpp +++ b/clang/test/AST/attr-print-emit.cpp @@ -73,18 +73,3 @@ class C { // CHECK: void pwtt(void *, int) __attribute__((pointer_with_type_tag(foo, 2, 3))); void pwtt(void *, int) __attribute__((pointer_with_type_tag(foo, 2, 3))); }; - -#define ANNOTATE_ATTR __attribute__((annotate("Annotated"))) -ANNOTATE_ATTR int annotated_attr ANNOTATE_ATTR = 0; -// CHECK: __attribute__((annotate("Annotated"))) int annotated_attr __attribute__((annotate("Annotated"))) = 0; - -// FIXME: We do not print the attribute as written after the type specifier. -int ANNOTATE_ATTR annotated_attr_fixme = 0; -// CHECK: __attribute__((annotate("Annotated"))) int annotated_attr_fixme = 0; - -#define NONNULL_ATTR __attribute__((nonnull(1))) -ANNOTATE_ATTR NONNULL_ATTR void fn_non_null_annotated_attr(int *) __attribute__((annotate("AnnotatedRHS"))); -// CHECK:__attribute__((annotate("Annotated"))) __attribute__((nonnull(1))) void fn_non_null_annotated_attr(int *) __attribute__((annotate("AnnotatedRHS"))); - -[[gnu::nonnull(1)]] [[gnu::always_inline]] void cxx11_attr(int*) ANNOTATE_ATTR; -// CHECK: {{\[\[}}gnu::nonnull(1)]] {{\[\[}}gnu::always_inline]] void cxx11_attr(int *) __attribute__((annotate("Annotated"))); diff --git a/clang/test/Analysis/scopes-cfg-output.cpp b/clang/test/Analysis/scopes-cfg-output.cpp index 5e6706602d45..4eb8967e3735 100644 --- a/clang/test/Analysis/scopes-cfg-output.cpp +++ b/clang/test/Analysis/scopes-cfg-output.cpp @@ -1469,7 +1469,7 @@ void test_cleanup_functions2(int m) { // CHECK: [B1] // CHECK-NEXT: 1: CFGScopeBegin(f) // CHECK-NEXT: 2: (CXXConstructExpr, [B1.3], F) -// CHECK-NEXT: 3: F f __attribute__((cleanup(cleanup_F))); +// CHECK-NEXT: 3: __attribute__((cleanup(cleanup_F))) F f; // CHECK-NEXT: 4: CleanupFunction (cleanup_F) // CHECK-NEXT: 5: [B1.3].~F() (Implicit destructor) // CHECK-NEXT: 6: CFGScopeEnd(f) diff --git a/clang/test/OpenMP/assumes_codegen.cpp b/clang/test/OpenMP/assumes_codegen.cpp index 4a2518a51ec3..6a5871c303aa 100644 --- a/clang/test/OpenMP/assumes_codegen.cpp +++ b/clang/test/OpenMP/assumes_codegen.cpp @@ -67,7 +67,7 @@ int lambda_outer() { } #pragma omp end assumes -// AST: void foo() __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) { +// AST: __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void foo() { // AST-NEXT: } // AST-NEXT: class BAR { // AST-NEXT: public: @@ -81,7 +81,7 @@ int lambda_outer() { // AST-NEXT: __attribute__((assume("ompx_range_bar_only"))) __attribute__((assume("ompx_range_bar_only_2"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void bar() { // AST-NEXT: BAR b; // AST-NEXT: } -// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz(); +// AST-NEXT: void baz() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); // AST-NEXT: template class BAZ { // AST-NEXT: public: // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) BAZ() { @@ -95,8 +95,8 @@ int lambda_outer() { // AST-NEXT: public: // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) BAZ() { // AST-NEXT: } -// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz1(); -// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) static void baz2(); +// AST-NEXT: void baz1() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); +// AST-NEXT: static void baz2() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); // AST-NEXT: }; // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz() { // AST-NEXT: BAZ b; diff --git a/clang/test/OpenMP/assumes_print.cpp b/clang/test/OpenMP/assumes_print.cpp index da3629f70408..a7f04edb3b1a 100644 --- a/clang/test/OpenMP/assumes_print.cpp +++ b/clang/test/OpenMP/assumes_print.cpp @@ -37,7 +37,7 @@ void baz() { } #pragma omp end assumes -// CHECK: void foo() __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) +// CHECK: __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void foo() // CHECK: __attribute__((assume("ompx_range_bar_only"))) __attribute__((assume("ompx_range_bar_only_2"))) __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void bar() // CHECK: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void baz() diff --git a/clang/test/OpenMP/assumes_template_print.cpp b/clang/test/OpenMP/assumes_template_print.cpp index e0bc3e9884ca..bd1100fbefff 100644 --- a/clang/test/OpenMP/assumes_template_print.cpp +++ b/clang/test/OpenMP/assumes_template_print.cpp @@ -17,7 +17,7 @@ template struct S { int a; // CHECK: template struct S { -// CHECK: void foo() __attribute__((assume("ompx_global_assumption"))) { +// CHECK: __attribute__((assume("ompx_global_assumption"))) void foo() { void foo() { #pragma omp parallel {} @@ -25,15 +25,15 @@ struct S { }; // CHECK: template<> struct S { -// CHECK: void foo() __attribute__((assume("ompx_global_assumption"))) { +// CHECK: __attribute__((assume("ompx_global_assumption"))) void foo() { #pragma omp begin assumes no_openmp -// CHECK: __attribute__((assume("omp_no_openmp"))) void S_with_assumes_no_call() __attribute__((assume("ompx_global_assumption"))) { +// CHECK: __attribute__((assume("omp_no_openmp"))) __attribute__((assume("ompx_global_assumption"))) void S_with_assumes_no_call() { void S_with_assumes_no_call() { S s; s.a = 0; } -// CHECK: __attribute__((assume("omp_no_openmp"))) void S_with_assumes_call() __attribute__((assume("ompx_global_assumption"))) { +// CHECK: __attribute__((assume("omp_no_openmp"))) __attribute__((assume("ompx_global_assumption"))) void S_with_assumes_call() { void S_with_assumes_call() { S s; s.a = 0; @@ -42,7 +42,7 @@ void S_with_assumes_call() { } #pragma omp end assumes -// CHECK: void S_without_assumes() __attribute__((assume("ompx_global_assumption"))) { +// CHECK: __attribute__((assume("ompx_global_assumption"))) void S_without_assumes() { void S_without_assumes() { S s; s.foo(); diff --git a/clang/test/OpenMP/declare_simd_ast_print.cpp b/clang/test/OpenMP/declare_simd_ast_print.cpp index 565dc2dfc04d..1adf95226c8b 100644 --- a/clang/test/OpenMP/declare_simd_ast_print.cpp +++ b/clang/test/OpenMP/declare_simd_ast_print.cpp @@ -60,11 +60,11 @@ void h(int *hp, int *hp2, int *hq, int *lin) class VV { // CHECK: #pragma omp declare simd uniform(this, a) linear(val(b): a) - // CHECK-NEXT: int add(int a, int b) __attribute__((cold)) { + // CHECK-NEXT: __attribute__((cold)) int add(int a, int b) { // CHECK-NEXT: return a + b; // CHECK-NEXT: } #pragma omp declare simd uniform(this, a) linear(val(b): a) - int add(int a, int b) __attribute__((cold)) { return a + b; } + __attribute__((cold)) int add(int a, int b) { return a + b; } // CHECK: #pragma omp declare simd aligned(b: 4) aligned(a) linear(ref(b): 4) linear(val(this)) linear(val(a)) // CHECK-NEXT: float taddpf(float *a, float *&b) { diff --git a/clang/test/SemaCXX/attr-no-sanitize.cpp b/clang/test/SemaCXX/attr-no-sanitize.cpp index 8951f616ce0f..a464947fe5a3 100644 --- a/clang/test/SemaCXX/attr-no-sanitize.cpp +++ b/clang/test/SemaCXX/attr-no-sanitize.cpp @@ -16,12 +16,12 @@ int f3() __attribute__((no_sanitize("address"))); // DUMP-LABEL: FunctionDecl {{.*}} f4 // DUMP: NoSanitizeAttr {{.*}} thread -// PRINT: {{\[\[}}clang::no_sanitize("thread")]] int f4() +// PRINT: int f4() {{\[\[}}clang::no_sanitize("thread")]] [[clang::no_sanitize("thread")]] int f4(); // DUMP-LABEL: FunctionDecl {{.*}} f4 // DUMP: NoSanitizeAttr {{.*}} hwaddress -// PRINT: {{\[\[}}clang::no_sanitize("hwaddress")]] int f4() +// PRINT: int f4() {{\[\[}}clang::no_sanitize("hwaddress")]] [[clang::no_sanitize("hwaddress")]] int f4(); // DUMP-LABEL: FunctionDecl {{.*}} f5 @@ -36,5 +36,5 @@ int f6() __attribute__((no_sanitize("unknown"))); // expected-warning{{unknown s // DUMP-LABEL: FunctionDecl {{.*}} f7 // DUMP: NoSanitizeAttr {{.*}} memtag -// PRINT: {{\[\[}}clang::no_sanitize("memtag")]] int f7() +// PRINT: int f7() {{\[\[}}clang::no_sanitize("memtag")]] [[clang::no_sanitize("memtag")]] int f7(); diff --git a/clang/test/SemaCXX/cxx11-attr-print.cpp b/clang/test/SemaCXX/cxx11-attr-print.cpp index a169d1b4409b..c988972aeb1a 100644 --- a/clang/test/SemaCXX/cxx11-attr-print.cpp +++ b/clang/test/SemaCXX/cxx11-attr-print.cpp @@ -24,10 +24,10 @@ int d [[deprecated("warning")]]; // CHECK: __attribute__((deprecated("warning", "fixit"))); int e __attribute__((deprecated("warning", "fixit"))); -// CHECK: alignas(4) int cxx11_alignas; +// CHECK: int cxx11_alignas alignas(4); alignas(4) int cxx11_alignas; -// CHECK: _Alignas(int) int c11_alignas; +// CHECK: int c11_alignas _Alignas(int); _Alignas(int) int c11_alignas; // CHECK: int foo() __attribute__((const)); @@ -66,7 +66,7 @@ void f8 (void *, const char *, ...) __attribute__ ((format (printf, 2, 3))); // CHECK: int n alignas(4 // CHECK: int p alignas(int // CHECK: __attribute__((pure)) static int f() -// CHECK: {{\[}}[gnu::pure]] static int g() +// CHECK: static int g() {{\[}}[gnu::pure]] template struct S { __attribute__((aligned(4))) int m; alignas(4) int n; @@ -82,7 +82,7 @@ template struct S { // CHECK: int m __attribute__((aligned(4 // CHECK: int n alignas(4 // CHECK: __attribute__((pure)) static int f() -// CHECK: {{\[}}[gnu::pure]] static int g() +// CHECK: static int g() {{\[}}[gnu::pure]] template struct S; // CHECK: using Small2 {{\[}}[gnu::mode(byte)]] = int; diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp index 6c56f99f503d..eb5c34d15693 100644 --- a/clang/utils/TableGen/ClangAttrEmitter.cpp +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp @@ -1591,10 +1591,10 @@ writePrettyPrintFunction(const Record &R, std::string Variety = Spellings[I].variety(); if (Variety == "GNU") { - Prefix = "__attribute__(("; + Prefix = " __attribute__(("; Suffix = "))"; } else if (Variety == "CXX11" || Variety == "C23") { - Prefix = "[["; + Prefix = " [["; Suffix = "]]"; std::string Namespace = Spellings[I].nameSpace(); if (!Namespace.empty()) { @@ -1602,7 +1602,7 @@ writePrettyPrintFunction(const Record &R, Spelling += "::"; } } else if (Variety == "Declspec") { - Prefix = "__declspec("; + Prefix = " __declspec("; Suffix = ")"; } else if (Variety == "Microsoft") { Prefix = "["; @@ -3316,6 +3316,37 @@ void EmitClangAttrList(RecordKeeper &Records, raw_ostream &OS) { OS << "#undef PRAGMA_SPELLING_ATTR\n"; } +// Emits the enumeration list for attributes. +void EmitClangAttrPrintList(const std::string &FieldName, RecordKeeper &Records, + raw_ostream &OS) { + emitSourceFileHeader( + "List of attributes that can be print on the left side of a decl", OS, + Records); + + AttrClassHierarchy Hierarchy(Records); + + std::vector Attrs = Records.getAllDerivedDefinitions("Attr"); + std::vector PragmaAttrs; + bool first = false; + + for (auto *Attr : Attrs) { + if (!Attr->getValueAsBit("ASTNode")) + continue; + + if (!Attr->getValueAsBit(FieldName)) + continue; + + if (!first) { + first = true; + OS << "#define CLANG_ATTR_LIST_" << FieldName; + } + + OS << " \\\n case attr::" << Attr->getName() << ":"; + } + + OS << '\n'; +} + // Emits the enumeration list for attributes. void EmitClangAttrSubjectMatchRuleList(RecordKeeper &Records, raw_ostream &OS) { emitSourceFileHeader( diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index 42cc704543f1..3f22e43b97ec 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -31,6 +31,8 @@ enum ActionType { GenClangAttrSubjectMatchRulesParserStringSwitches, GenClangAttrImpl, GenClangAttrList, + GenClangAttrCanPrintLeftList, + GenClangAttrMustPrintLeftList, GenClangAttrDocTable, GenClangAttrSubjectMatchRuleList, GenClangAttrPCHRead, @@ -132,6 +134,14 @@ cl::opt Action( "Generate clang attribute implementations"), clEnumValN(GenClangAttrList, "gen-clang-attr-list", "Generate a clang attribute list"), + clEnumValN(GenClangAttrCanPrintLeftList, + "gen-clang-attr-can-print-left-list", + "Generate list of attributes that can be printed on left " + "side of a decl"), + clEnumValN(GenClangAttrMustPrintLeftList, + "gen-clang-attr-must-print-left-list", + "Generate list of attributes that must be printed on left " + "side of a decl"), clEnumValN(GenClangAttrDocTable, "gen-clang-attr-doc-table", "Generate a table of attribute documentation"), clEnumValN(GenClangAttrSubjectMatchRuleList, @@ -335,6 +345,12 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenClangAttrList: EmitClangAttrList(Records, OS); break; + case GenClangAttrCanPrintLeftList: + EmitClangAttrPrintList("CanPrintOnLeft", Records, OS); + break; + case GenClangAttrMustPrintLeftList: + EmitClangAttrPrintList("PrintOnLeft", Records, OS); + break; case GenClangAttrDocTable: EmitClangAttrDocTable(Records, OS); break; diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index 5f2dd257cb90..ecd506b7b6b5 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -47,6 +47,8 @@ void EmitClangAttrSubjectMatchRulesParserStringSwitches( void EmitClangAttrClass(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrImpl(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); +void EmitClangAttrPrintList(const std::string &FieldName, + llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrSubjectMatchRuleList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHRead(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); -- GitLab From d4120477130a5f9e472753068dcc627baddc44f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 8 Apr 2024 20:09:35 +0200 Subject: [PATCH 241/695] [clang][Interp] Fix "Initializing" zero-size arrays getIndex() returns 0 here, so we were trying to initalize the 0th element. Fixes #88018 --- clang/lib/AST/Interp/Pointer.cpp | 4 ++++ clang/test/AST/Interp/arrays.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/clang/lib/AST/Interp/Pointer.cpp b/clang/lib/AST/Interp/Pointer.cpp index af60ced0e10e..53998cc3233c 100644 --- a/clang/lib/AST/Interp/Pointer.cpp +++ b/clang/lib/AST/Interp/Pointer.cpp @@ -177,6 +177,10 @@ void Pointer::initialize() const { if (isStatic() && Base == 0) return; + // Nothing to do for these. + if (Desc->getNumElems() == 0) + return; + InitMapPtr &IM = getInitMap(); if (!IM) IM = diff --git a/clang/test/AST/Interp/arrays.cpp b/clang/test/AST/Interp/arrays.cpp index 2443992f75fb..607d67bde020 100644 --- a/clang/test/AST/Interp/arrays.cpp +++ b/clang/test/AST/Interp/arrays.cpp @@ -566,3 +566,7 @@ char melchizedek[2200000000]; typedef decltype(melchizedek[1] - melchizedek[0]) ptrdiff_t; constexpr ptrdiff_t d1 = &melchizedek[0x7fffffff] - &melchizedek[0]; // ok constexpr ptrdiff_t d3 = &melchizedek[0] - &melchizedek[0x80000000u]; // ok + +/// GH#88018 +const int SZA[] = {}; +void testZeroSizedArrayAccess() { unsigned c = SZA[4]; } -- GitLab From 03ffb82c9e0d363c97ca37ede46719236616c88e Mon Sep 17 00:00:00 2001 From: Haohai Wen Date: Tue, 9 Apr 2024 13:31:11 +0800 Subject: [PATCH 242/695] [Support] Make CleanupInstaller public (NFC) (#86758) This can be used by others to automatically remove temp files. --- llvm/include/llvm/Support/ToolOutputFile.h | 26 ++++++++++++---------- llvm/lib/Support/ToolOutputFile.cpp | 4 ++-- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/Support/ToolOutputFile.h b/llvm/include/llvm/Support/ToolOutputFile.h index e3fb83fdfd2c..c16fb03d9b22 100644 --- a/llvm/include/llvm/Support/ToolOutputFile.h +++ b/llvm/include/llvm/Support/ToolOutputFile.h @@ -18,6 +18,19 @@ namespace llvm { +class CleanupInstaller { +public: + /// The name of the file. + std::string Filename; + + /// The flag which indicates whether we should not delete the file. + bool Keep; + + StringRef getFilename() { return Filename; } + explicit CleanupInstaller(StringRef Filename); + ~CleanupInstaller(); +}; + /// This class contains a raw_fd_ostream and adds a few extra features commonly /// needed for compiler-like tool output files: /// - The file is automatically deleted if the process is killed. @@ -28,18 +41,7 @@ class ToolOutputFile { /// before the raw_fd_ostream is constructed and destructed after the /// raw_fd_ostream is destructed. It installs cleanups in its constructor and /// uninstalls them in its destructor. - class CleanupInstaller { - public: - /// The name of the file. - std::string Filename; - - /// The flag which indicates whether we should not delete the file. - bool Keep; - - StringRef getFilename() { return Filename; } - explicit CleanupInstaller(StringRef Filename); - ~CleanupInstaller(); - } Installer; + CleanupInstaller Installer; /// Storage for the stream, if we're owning our own stream. This is /// intentionally declared after Installer. diff --git a/llvm/lib/Support/ToolOutputFile.cpp b/llvm/lib/Support/ToolOutputFile.cpp index 01f7095f3499..7a07286882fe 100644 --- a/llvm/lib/Support/ToolOutputFile.cpp +++ b/llvm/lib/Support/ToolOutputFile.cpp @@ -17,14 +17,14 @@ using namespace llvm; static bool isStdout(StringRef Filename) { return Filename == "-"; } -ToolOutputFile::CleanupInstaller::CleanupInstaller(StringRef Filename) +CleanupInstaller::CleanupInstaller(StringRef Filename) : Filename(std::string(Filename)), Keep(false) { // Arrange for the file to be deleted if the process is killed. if (!isStdout(Filename)) sys::RemoveFileOnSignal(Filename); } -ToolOutputFile::CleanupInstaller::~CleanupInstaller() { +CleanupInstaller::~CleanupInstaller() { if (isStdout(Filename)) return; -- GitLab From c7db450e5c1a83ea768765dcdedfd50f3358d418 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Tue, 9 Apr 2024 08:50:50 +0300 Subject: [PATCH 243/695] [clang][NFC] Refactor `EvaluateBinaryTypeTrait` to accept `TypeSourceInfo` Some type traits issue diagnostics that would benefit from additional source location information. --- clang/lib/Sema/SemaExprCXX.cpp | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 901c3c4d00cf..dee6b658cd00 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -5566,8 +5566,8 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT, } } -static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, QualType LhsT, - QualType RhsT, SourceLocation KeyLoc); +static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceInfo *Lhs, + const TypeSourceInfo *Rhs, SourceLocation KeyLoc); static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, SourceLocation KWLoc, @@ -5583,8 +5583,8 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, // Evaluate ReferenceBindsToTemporary and ReferenceConstructsFromTemporary // alongside the IsConstructible traits to avoid duplication. if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary && Kind != BTT_ReferenceConstructsFromTemporary) - return EvaluateBinaryTypeTrait(S, Kind, Args[0]->getType(), - Args[1]->getType(), RParenLoc); + return EvaluateBinaryTypeTrait(S, Kind, Args[0], + Args[1], RParenLoc); switch (Kind) { case clang::BTT_ReferenceBindsToTemporary: @@ -5679,8 +5679,8 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, if (U->isReferenceType()) return false; - QualType TPtr = S.Context.getPointerType(S.BuiltinRemoveReference(T, UnaryTransformType::RemoveCVRef, {})); - QualType UPtr = S.Context.getPointerType(S.BuiltinRemoveReference(U, UnaryTransformType::RemoveCVRef, {})); + TypeSourceInfo *TPtr = S.Context.CreateTypeSourceInfo(S.Context.getPointerType(S.BuiltinRemoveReference(T, UnaryTransformType::RemoveCVRef, {}))); + TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo(S.Context.getPointerType(S.BuiltinRemoveReference(U, UnaryTransformType::RemoveCVRef, {}))); return EvaluateBinaryTypeTrait(S, TypeTrait::BTT_IsConvertibleTo, UPtr, TPtr, RParenLoc); } @@ -5814,8 +5814,11 @@ ExprResult Sema::ActOnTypeTrait(TypeTrait Kind, SourceLocation KWLoc, return BuildTypeTrait(Kind, KWLoc, ConvertedArgs, RParenLoc); } -static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, QualType LhsT, - QualType RhsT, SourceLocation KeyLoc) { +static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceInfo *Lhs, + const TypeSourceInfo *Rhs, SourceLocation KeyLoc) { + QualType LhsT = Lhs->getType(); + QualType RhsT = Rhs->getType(); + assert(!LhsT->isDependentType() && !RhsT->isDependentType() && "Cannot evaluate traits of dependent types"); -- GitLab From 5d1f779540517f47abb4927f4ded51cac94fd366 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Wed, 3 Apr 2024 07:57:26 +0200 Subject: [PATCH 244/695] [clang][Interp][NFC] Add Dump debug op This is often useful for debugging and dumps the current stack contents. --- clang/lib/AST/Interp/Interp.h | 5 +++++ clang/lib/AST/Interp/Opcodes.td | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 405993eb8270..fe5da47d9027 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1333,6 +1333,11 @@ inline bool FinishInit(InterpState &S, CodePtr OpPC) { return true; } +inline bool Dump(InterpState &S, CodePtr OpPC) { + S.Stk.dump(); + return true; +} + inline bool VirtBaseHelper(InterpState &S, CodePtr OpPC, const RecordDecl *Decl, const Pointer &Ptr) { Pointer Base = Ptr; diff --git a/clang/lib/AST/Interp/Opcodes.td b/clang/lib/AST/Interp/Opcodes.td index cc1310f4c0d5..6e79a03203d2 100644 --- a/clang/lib/AST/Interp/Opcodes.td +++ b/clang/lib/AST/Interp/Opcodes.td @@ -723,3 +723,8 @@ def CheckNonNullArg : Opcode { } def Memcpy : Opcode; + +//===----------------------------------------------------------------------===// +// Debugging. +//===----------------------------------------------------------------------===// +def Dump : Opcode; -- GitLab From acff0b03167f877f783d9386014e1ebc20db1c2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Fri, 5 Apr 2024 16:56:35 +0200 Subject: [PATCH 245/695] [clang][Interp][NFC] Improve Record debugging Add Record::dump() and return the diagnostic name from getName() --- clang/lib/AST/Interp/Disasm.cpp | 31 +++++++++++++++++++++++++++++++ clang/lib/AST/Interp/Record.cpp | 9 +++++++++ clang/lib/AST/Interp/Record.h | 6 +++++- 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/clang/lib/AST/Interp/Disasm.cpp b/clang/lib/AST/Interp/Disasm.cpp index 01ef1c24744a..022b394e58e6 100644 --- a/clang/lib/AST/Interp/Disasm.cpp +++ b/clang/lib/AST/Interp/Disasm.cpp @@ -233,3 +233,34 @@ LLVM_DUMP_METHOD void InterpFrame::dump(llvm::raw_ostream &OS, F = F->Caller; } } + +LLVM_DUMP_METHOD void Record::dump(llvm::raw_ostream &OS, unsigned Indentation, + unsigned Offset) const { + unsigned Indent = Indentation * 2; + OS.indent(Indent); + { + ColorScope SC(OS, true, {llvm::raw_ostream::BLUE, true}); + OS << getName() << "\n"; + } + + unsigned I = 0; + for (const Record::Base &B : bases()) { + OS.indent(Indent) << "- Base " << I << ". Offset " << (Offset + B.Offset) + << "\n"; + B.R->dump(OS, Indentation + 1, Offset + B.Offset); + ++I; + } + + // FIXME: Virtual bases. + + I = 0; + for (const Record::Field &F : fields()) { + OS.indent(Indent) << "- Field " << I << ": "; + { + ColorScope SC(OS, true, {llvm::raw_ostream::BRIGHT_RED, true}); + OS << F.Decl->getName(); + } + OS << ". Offset " << (Offset + F.Offset) << "\n"; + ++I; + } +} diff --git a/clang/lib/AST/Interp/Record.cpp b/clang/lib/AST/Interp/Record.cpp index 909416e6e1a1..6a0a28bc9124 100644 --- a/clang/lib/AST/Interp/Record.cpp +++ b/clang/lib/AST/Interp/Record.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "Record.h" +#include "clang/AST/ASTContext.h" using namespace clang; using namespace clang::interp; @@ -27,6 +28,14 @@ Record::Record(const RecordDecl *Decl, BaseList &&SrcBases, VirtualBaseMap[V.Decl] = &V; } +const std::string Record::getName() const { + std::string Ret; + llvm::raw_string_ostream OS(Ret); + Decl->getNameForDiagnostic(OS, Decl->getASTContext().getPrintingPolicy(), + /*Qualified=*/true); + return Ret; +} + const Record::Field *Record::getField(const FieldDecl *FD) const { auto It = FieldMap.find(FD); assert(It != FieldMap.end() && "Missing field"); diff --git a/clang/lib/AST/Interp/Record.h b/clang/lib/AST/Interp/Record.h index a6bde0106253..cf0480b3f62f 100644 --- a/clang/lib/AST/Interp/Record.h +++ b/clang/lib/AST/Interp/Record.h @@ -51,7 +51,7 @@ public: /// Returns the underlying declaration. const RecordDecl *getDecl() const { return Decl; } /// Returns the name of the underlying declaration. - const std::string getName() const { return Decl->getNameAsString(); } + const std::string getName() const; /// Checks if the record is a union. bool isUnion() const { return getDecl()->isUnion(); } /// Returns the size of the record. @@ -100,6 +100,10 @@ public: unsigned getNumVirtualBases() const { return VirtualBases.size(); } const Base *getVirtualBase(unsigned I) const { return &VirtualBases[I]; } + void dump(llvm::raw_ostream &OS, unsigned Indentation = 0, + unsigned Offset = 0) const; + void dump() const { dump(llvm::errs()); } + private: /// Constructor used by Program to create record descriptors. Record(const RecordDecl *, BaseList &&Bases, FieldList &&Fields, -- GitLab From 11ba795565c231a95a7e34bb0e4dff099234c736 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Fri, 5 Apr 2024 16:58:35 +0200 Subject: [PATCH 246/695] [clang][Interp][NFC] Add sanity checks to This op The instance pointer must be casted to the right base. --- clang/lib/AST/Interp/Interp.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index fe5da47d9027..3dc223f97a8c 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1846,6 +1846,15 @@ inline bool This(InterpState &S, CodePtr OpPC) { if (!CheckThis(S, OpPC, This)) return false; + // Ensure the This pointer has been cast to the correct base. + if (!This.isDummy()) { + assert(isa(S.Current->getFunction()->getDecl())); + assert(This.getRecord()); + assert( + This.getRecord()->getDecl() == + cast(S.Current->getFunction()->getDecl())->getParent()); + } + S.Stk.push(This); return true; } -- GitLab From 3a2367561d7f4eb1795d6972b294562bc66beb2b Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:42:28 -0500 Subject: [PATCH 247/695] [ValueTracking] Add tests for non-constant idx in `computeKnownBits` of `insertelement`; NFC --- .../Transforms/InstCombine/insertelement.ll | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/insertelement.ll b/llvm/test/Transforms/InstCombine/insertelement.ll index 976c495465ce..178e2e25474a 100644 --- a/llvm/test/Transforms/InstCombine/insertelement.ll +++ b/llvm/test/Transforms/InstCombine/insertelement.ll @@ -25,3 +25,53 @@ define <4 x i32> @insert_unknown_idx(<4 x i32> %x, i32 %idx) { %v3 = and <4 x i32> %v2, ret <4 x i32> %v3 } + +define <2 x i8> @insert_known_any_idx(<2 x i8> %xx, i8 %yy, i32 %idx) { +; CHECK-LABEL: @insert_known_any_idx( +; CHECK-NEXT: [[X:%.*]] = or <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = or i8 [[YY:%.*]], 16 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] +; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[INS]], +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %x = or <2 x i8> %xx, + %y = or i8 %yy, 16 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 %idx + %r = and <2 x i8> %ins, + ret <2 x i8> %r +} + +define <2 x i8> @insert_known_any_idx_fail1(<2 x i8> %xx, i8 %yy, i32 %idx) { +; CHECK-LABEL: @insert_known_any_idx_fail1( +; CHECK-NEXT: [[X:%.*]] = or <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = or i8 [[YY:%.*]], 16 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] +; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[INS]], +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %x = or <2 x i8> %xx, + %y = or i8 %yy, 16 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 %idx + %r = and <2 x i8> %ins, + ret <2 x i8> %r +} + + +define <2 x i8> @insert_known_any_idx_fail2(<2 x i8> %xx, i8 %yy, i32 %idx) { +; CHECK-LABEL: @insert_known_any_idx_fail2( +; CHECK-NEXT: [[X:%.*]] = or <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = or i8 [[YY:%.*]], 15 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] +; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[INS]], +; CHECK-NEXT: ret <2 x i8> [[R]] +; + %x = or <2 x i8> %xx, + %y = or i8 %yy, 15 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 %idx + %r = and <2 x i8> %ins, + ret <2 x i8> %r +} + -- GitLab From 964df099e1f8afcb9d052f61e065da82b19cc81b Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:25:57 -0500 Subject: [PATCH 248/695] [ValueTracking] Support non-constant idx for `computeKnownBits` of `insertelement` Its same logic as before, we just need to intersect what we know about the new Elt and the entire pre-existing Vec. Closes #87707 --- llvm/lib/Analysis/ValueTracking.cpp | 21 +++++++++---------- .../Transforms/InstCombine/insertelement.ll | 9 ++------ 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 6602db424fc2..ca48cfe77381 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -1727,26 +1727,25 @@ static void computeKnownBitsFromOperator(const Operator *I, const Value *Vec = I->getOperand(0); const Value *Elt = I->getOperand(1); auto *CIdx = dyn_cast(I->getOperand(2)); - // Early out if the index is non-constant or out-of-range. unsigned NumElts = DemandedElts.getBitWidth(); - if (!CIdx || CIdx->getValue().uge(NumElts)) { - Known.resetAll(); - return; + APInt DemandedVecElts = DemandedElts; + bool NeedsElt = true; + // If we know the index we are inserting too, clear it from Vec check. + if (CIdx && CIdx->getValue().ult(NumElts)) { + DemandedVecElts.clearBit(CIdx->getZExtValue()); + NeedsElt = DemandedElts[CIdx->getZExtValue()]; } + Known.One.setAllBits(); Known.Zero.setAllBits(); - unsigned EltIdx = CIdx->getZExtValue(); - // Do we demand the inserted element? - if (DemandedElts[EltIdx]) { + if (NeedsElt) { computeKnownBits(Elt, Known, Depth + 1, Q); // If we don't know any bits, early out. if (Known.isUnknown()) break; } - // We don't need the base vector element that has been inserted. - APInt DemandedVecElts = DemandedElts; - DemandedVecElts.clearBit(EltIdx); - if (!!DemandedVecElts) { + + if (!DemandedVecElts.isZero()) { computeKnownBits(Vec, DemandedVecElts, Known2, Depth + 1, Q); Known = Known.intersectWith(Known2); } diff --git a/llvm/test/Transforms/InstCombine/insertelement.ll b/llvm/test/Transforms/InstCombine/insertelement.ll index 178e2e25474a..c8df2db6e70c 100644 --- a/llvm/test/Transforms/InstCombine/insertelement.ll +++ b/llvm/test/Transforms/InstCombine/insertelement.ll @@ -17,8 +17,7 @@ define <4 x i32> @insert_unknown_idx(<4 x i32> %x, i32 %idx) { ; CHECK-LABEL: @insert_unknown_idx( ; CHECK-NEXT: [[V1:%.*]] = and <4 x i32> [[X:%.*]], ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 6, i32 [[IDX:%.*]] -; CHECK-NEXT: [[V3:%.*]] = and <4 x i32> [[V2]], -; CHECK-NEXT: ret <4 x i32> [[V3]] +; CHECK-NEXT: ret <4 x i32> [[V2]] ; %v1 = and <4 x i32> %x, %v2 = insertelement <4 x i32> %v1, i32 6, i32 %idx @@ -28,11 +27,7 @@ define <4 x i32> @insert_unknown_idx(<4 x i32> %x, i32 %idx) { define <2 x i8> @insert_known_any_idx(<2 x i8> %xx, i8 %yy, i32 %idx) { ; CHECK-LABEL: @insert_known_any_idx( -; CHECK-NEXT: [[X:%.*]] = or <2 x i8> [[XX:%.*]], -; CHECK-NEXT: [[Y:%.*]] = or i8 [[YY:%.*]], 16 -; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] -; CHECK-NEXT: [[R:%.*]] = and <2 x i8> [[INS]], -; CHECK-NEXT: ret <2 x i8> [[R]] +; CHECK-NEXT: ret <2 x i8> ; %x = or <2 x i8> %xx, %y = or i8 %yy, 16 -- GitLab From 51089e360e37962c7841fe0a494ba9fb5368bab2 Mon Sep 17 00:00:00 2001 From: Kai Sasaki Date: Tue, 9 Apr 2024 15:22:43 +0900 Subject: [PATCH 249/695] [mlir][complex] Support fast math flag for complex.tan op (#87919) See https://discourse.llvm.org/t/rfc-fastmath-flags-support-in-complex-dialect/71981 --- .../ComplexToStandard/ComplexToStandard.cpp | 8 +- .../convert-to-standard.mlir | 141 ++++++++++++++++++ 2 files changed, 146 insertions(+), 3 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index e18b27702e4e..9c3c4d96a301 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -946,9 +946,11 @@ struct TanOpConversion : public OpConversionPattern { matchAndRewrite(complex::TanOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { auto loc = op.getLoc(); - Value cos = rewriter.create(loc, adaptor.getComplex()); - Value sin = rewriter.create(loc, adaptor.getComplex()); - rewriter.replaceOpWithNewOp(op, sin, cos); + arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); + + Value cos = rewriter.create(loc, adaptor.getComplex(), fmf); + Value sin = rewriter.create(loc, adaptor.getComplex(), fmf); + rewriter.replaceOpWithNewOp(op, sin, cos, fmf); return success(); } }; diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index 112918b20d33..f5d9499eadda 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -1923,3 +1923,144 @@ func.func @complex_sign_with_fmf(%arg: complex) -> complex { // CHECK: %[[SIGN:.*]] = complex.create %[[REAL_SIGN]], %[[IMAG_SIGN]] : complex // CHECK: %[[RESULT:.*]] = arith.select %[[IS_ZERO]], %[[ARG]], %[[SIGN]] : complex // CHECK: return %[[RESULT]] : complex + +// ----- + +// CHECK-LABEL: func @complex_tan_with_fmf +// CHECK-SAME: %[[ARG:.*]]: complex +func.func @complex_tan_with_fmf(%arg: complex) -> complex { + %tan = complex.tan %arg fastmath : complex + return %tan : complex +} + +// CHECK-DAG: %[[REAL:.*]] = complex.re %[[ARG]] +// CHECK-DAG: %[[IMAG:.*]] = complex.im %[[ARG]] +// CHECK-DAG: %[[HALF:.*]] = arith.constant 5.000000e-01 : f32 +// CHECK-DAG: %[[EXP:.*]] = math.exp %[[IMAG]] fastmath : f32 +// CHECK-DAG: %[[HALF_EXP:.*]] = arith.mulf %[[HALF]], %[[EXP]] fastmath +// CHECK-DAG: %[[HALF_REXP:.*]] = arith.divf %[[HALF]], %[[EXP]] fastmath +// CHECK-DAG: %[[SIN:.*]] = math.sin %[[REAL]] fastmath : f32 +// CHECK-DAG: %[[COS:.*]] = math.cos %[[REAL]] fastmath : f32 +// CHECK-DAG: %[[EXP_SUM:.*]] = arith.addf %[[HALF_REXP]], %[[HALF_EXP]] fastmath +// CHECK-DAG: %[[COS_REAL:.*]] = arith.mulf %[[EXP_SUM]], %[[COS]] fastmath +// CHECK-DAG: %[[EXP_DIFF:.*]] = arith.subf %[[HALF_REXP]], %[[HALF_EXP]] fastmath +// CHECK-DAG: %[[COS_IMAG:.*]] = arith.mulf %[[EXP_DIFF]], %[[SIN]] fastmath +// CHECK-DAG: %[[COS_COMP:.*]] = complex.create %[[COS_REAL]], %[[COS_IMAG]] : complex + +// CHECK-DAG: %[[REAL:.*]] = complex.re %[[ARG]] +// CHECK-DAG: %[[IMAG:.*]] = complex.im %[[ARG]] +// CHECK-DAG: %[[HALF:.*]] = arith.constant 5.000000e-01 : f32 +// CHECK-DAG: %[[EXP:.*]] = math.exp %[[IMAG]] fastmath : f32 +// CHECK-DAG: %[[HALF_EXP:.*]] = arith.mulf %[[HALF]], %[[EXP]] fastmath +// CHECK-DAG: %[[HALF_REXP:.*]] = arith.divf %[[HALF]], %[[EXP]] fastmath +// CHECK-DAG: %[[SIN:.*]] = math.sin %[[REAL]] fastmath : f32 +// CHECK-DAG: %[[COS:.*]] = math.cos %[[REAL]] fastmath : f32 +// CHECK-DAG: %[[EXP_SUM:.*]] = arith.addf %[[HALF_EXP]], %[[HALF_REXP]] fastmath +// CHECK-DAG: %[[SIN_REAL:.*]] = arith.mulf %[[EXP_SUM]], %[[SIN]] fastmath +// CHECK-DAG: %[[EXP_DIFF:.*]] = arith.subf %[[HALF_EXP]], %[[HALF_REXP]] fastmath +// CHECK-DAG: %[[SIN_IMAG:.*]] = arith.mulf %[[EXP_DIFF]], %[[COS]] fastmath +// CHECK-DAG: %[[SIN_COMP:.*]] = complex.create %[[SIN_REAL]], %[[SIN_IMAG]] : complex + +// CHECK: %[[LHS_REAL:.*]] = complex.re %[[SIN_COMP]] : complex +// CHECK: %[[LHS_IMAG:.*]] = complex.im %[[SIN_COMP]] : complex +// CHECK: %[[RHS_REAL:.*]] = complex.re %[[COS_COMP]] : complex +// CHECK: %[[RHS_IMAG:.*]] = complex.im %[[COS_COMP]] : complex + +// CHECK: %[[RHS_REAL_IMAG_RATIO:.*]] = arith.divf %[[RHS_REAL]], %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[RHS_REAL_TIMES_RHS_REAL_IMAG_RATIO:.*]] = arith.mulf %[[RHS_REAL_IMAG_RATIO]], %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[RHS_REAL_IMAG_DENOM:.*]] = arith.addf %[[RHS_IMAG]], %[[RHS_REAL_TIMES_RHS_REAL_IMAG_RATIO]] fastmath : f32 +// CHECK: %[[LHS_REAL_TIMES_RHS_REAL_IMAG_RATIO:.*]] = arith.mulf %[[LHS_REAL]], %[[RHS_REAL_IMAG_RATIO]] fastmath : f32 +// CHECK: %[[REAL_NUMERATOR_1:.*]] = arith.addf %[[LHS_REAL_TIMES_RHS_REAL_IMAG_RATIO]], %[[LHS_IMAG]] fastmath : f32 +// CHECK: %[[RESULT_REAL_1:.*]] = arith.divf %[[REAL_NUMERATOR_1]], %[[RHS_REAL_IMAG_DENOM]] fastmath : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_REAL_IMAG_RATIO:.*]] = arith.mulf %[[LHS_IMAG]], %[[RHS_REAL_IMAG_RATIO]] fastmath : f32 +// CHECK: %[[IMAG_NUMERATOR_1:.*]] = arith.subf %[[LHS_IMAG_TIMES_RHS_REAL_IMAG_RATIO]], %[[LHS_REAL]] fastmath : f32 +// CHECK: %[[RESULT_IMAG_1:.*]] = arith.divf %[[IMAG_NUMERATOR_1]], %[[RHS_REAL_IMAG_DENOM]] fastmath : f32 + +// CHECK: %[[RHS_IMAG_REAL_RATIO:.*]] = arith.divf %[[RHS_IMAG]], %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[RHS_IMAG_TIMES_RHS_IMAG_REAL_RATIO:.*]] = arith.mulf %[[RHS_IMAG_REAL_RATIO]], %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[RHS_IMAG_REAL_DENOM:.*]] = arith.addf %[[RHS_REAL]], %[[RHS_IMAG_TIMES_RHS_IMAG_REAL_RATIO]] fastmath : f32 +// CHECK: %[[LHS_IMAG_TIMES_RHS_IMAG_REAL_RATIO:.*]] = arith.mulf %[[LHS_IMAG]], %[[RHS_IMAG_REAL_RATIO]] fastmath : f32 +// CHECK: %[[REAL_NUMERATOR_2:.*]] = arith.addf %[[LHS_REAL]], %[[LHS_IMAG_TIMES_RHS_IMAG_REAL_RATIO]] fastmath : f32 +// CHECK: %[[RESULT_REAL_2:.*]] = arith.divf %[[REAL_NUMERATOR_2]], %[[RHS_IMAG_REAL_DENOM]] fastmath : f32 +// CHECK: %[[LHS_REAL_TIMES_RHS_IMAG_REAL_RATIO:.*]] = arith.mulf %[[LHS_REAL]], %[[RHS_IMAG_REAL_RATIO]] fastmath : f32 +// CHECK: %[[IMAG_NUMERATOR_2:.*]] = arith.subf %[[LHS_IMAG]], %[[LHS_REAL_TIMES_RHS_IMAG_REAL_RATIO]] fastmath : f32 +// CHECK: %[[RESULT_IMAG_2:.*]] = arith.divf %[[IMAG_NUMERATOR_2]], %[[RHS_IMAG_REAL_DENOM]] fastmath : f32 + +// Case 1. Zero denominator, numerator contains at most one NaN value. +// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[RHS_REAL_ABS:.*]] = math.absf %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[RHS_REAL_ABS_IS_ZERO:.*]] = arith.cmpf oeq, %[[RHS_REAL_ABS]], %[[ZERO]] : f32 +// CHECK: %[[RHS_IMAG_ABS:.*]] = math.absf %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[RHS_IMAG_ABS_IS_ZERO:.*]] = arith.cmpf oeq, %[[RHS_IMAG_ABS]], %[[ZERO]] : f32 +// CHECK: %[[LHS_REAL_IS_NOT_NAN:.*]] = arith.cmpf ord, %[[LHS_REAL]], %[[ZERO]] : f32 +// CHECK: %[[LHS_IMAG_IS_NOT_NAN:.*]] = arith.cmpf ord, %[[LHS_IMAG]], %[[ZERO]] : f32 +// CHECK: %[[LHS_CONTAINS_NOT_NAN_VALUE:.*]] = arith.ori %[[LHS_REAL_IS_NOT_NAN]], %[[LHS_IMAG_IS_NOT_NAN]] : i1 +// CHECK: %[[RHS_IS_ZERO:.*]] = arith.andi %[[RHS_REAL_ABS_IS_ZERO]], %[[RHS_IMAG_ABS_IS_ZERO]] : i1 +// CHECK: %[[RESULT_IS_INFINITY:.*]] = arith.andi %[[LHS_CONTAINS_NOT_NAN_VALUE]], %[[RHS_IS_ZERO]] : i1 +// CHECK: %[[INF:.*]] = arith.constant 0x7F800000 : f32 +// CHECK: %[[INF_WITH_SIGN_OF_RHS_REAL:.*]] = math.copysign %[[INF]], %[[RHS_REAL]] : f32 +// CHECK: %[[INFINITY_RESULT_REAL:.*]] = arith.mulf %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_REAL]] fastmath : f32 +// CHECK: %[[INFINITY_RESULT_IMAG:.*]] = arith.mulf %[[INF_WITH_SIGN_OF_RHS_REAL]], %[[LHS_IMAG]] fastmath : f32 + +// Case 2. Infinite numerator, finite denominator. +// CHECK: %[[RHS_REAL_FINITE:.*]] = arith.cmpf one, %[[RHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[RHS_IMAG_FINITE:.*]] = arith.cmpf one, %[[RHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[RHS_IS_FINITE:.*]] = arith.andi %[[RHS_REAL_FINITE]], %[[RHS_IMAG_FINITE]] : i1 +// CHECK: %[[LHS_REAL_ABS:.*]] = math.absf %[[LHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_REAL_INFINITE:.*]] = arith.cmpf oeq, %[[LHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IMAG_ABS:.*]] = math.absf %[[LHS_IMAG]] fastmath : f32 +// CHECK: %[[LHS_IMAG_INFINITE:.*]] = arith.cmpf oeq, %[[LHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IS_INFINITE:.*]] = arith.ori %[[LHS_REAL_INFINITE]], %[[LHS_IMAG_INFINITE]] : i1 +// CHECK: %[[INF_NUM_FINITE_DENOM:.*]] = arith.andi %[[LHS_IS_INFINITE]], %[[RHS_IS_FINITE]] : i1 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[LHS_REAL_IS_INF:.*]] = arith.select %[[LHS_REAL_INFINITE]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[LHS_REAL_IS_INF_WITH_SIGN:.*]] = math.copysign %[[LHS_REAL_IS_INF]], %[[LHS_REAL]] : f32 +// CHECK: %[[LHS_IMAG_IS_INF:.*]] = arith.select %[[LHS_IMAG_INFINITE]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[LHS_IMAG_IS_INF_WITH_SIGN:.*]] = math.copysign %[[LHS_IMAG_IS_INF]], %[[LHS_IMAG]] : f32 +// CHECK: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = arith.mulf %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = arith.mulf %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[INF_MULTIPLICATOR_1:.*]] = arith.addf %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]] fastmath : f32 +// CHECK: %[[RESULT_REAL_3:.*]] = arith.mulf %[[INF]], %[[INF_MULTIPLICATOR_1]] fastmath : f32 +// CHECK: %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG:.*]] = arith.mulf %[[LHS_REAL_IS_INF_WITH_SIGN]], %[[RHS_IMAG]] fastmath : f32 +// CHECK: %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL:.*]] = arith.mulf %[[LHS_IMAG_IS_INF_WITH_SIGN]], %[[RHS_REAL]] fastmath : f32 +// CHECK: %[[INF_MULTIPLICATOR_2:.*]] = arith.subf %[[LHS_IMAG_IS_INF_WITH_SIGN_TIMES_RHS_REAL]], %[[LHS_REAL_IS_INF_WITH_SIGN_TIMES_RHS_IMAG]] fastmath : f32 +// CHECK: %[[RESULT_IMAG_3:.*]] = arith.mulf %[[INF]], %[[INF_MULTIPLICATOR_2]] fastmath : f32 + +// Case 3. Finite numerator, infinite denominator. +// CHECK: %[[LHS_REAL_FINITE:.*]] = arith.cmpf one, %[[LHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IMAG_FINITE:.*]] = arith.cmpf one, %[[LHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[LHS_IS_FINITE:.*]] = arith.andi %[[LHS_REAL_FINITE]], %[[LHS_IMAG_FINITE]] : i1 +// CHECK: %[[RHS_REAL_INFINITE:.*]] = arith.cmpf oeq, %[[RHS_REAL_ABS]], %[[INF]] : f32 +// CHECK: %[[RHS_IMAG_INFINITE:.*]] = arith.cmpf oeq, %[[RHS_IMAG_ABS]], %[[INF]] : f32 +// CHECK: %[[RHS_IS_INFINITE:.*]] = arith.ori %[[RHS_REAL_INFINITE]], %[[RHS_IMAG_INFINITE]] : i1 +// CHECK: %[[FINITE_NUM_INFINITE_DENOM:.*]] = arith.andi %[[LHS_IS_FINITE]], %[[RHS_IS_INFINITE]] : i1 +// CHECK: %[[RHS_REAL_IS_INF:.*]] = arith.select %[[RHS_REAL_INFINITE]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[RHS_REAL_IS_INF_WITH_SIGN:.*]] = math.copysign %[[RHS_REAL_IS_INF]], %[[RHS_REAL]] : f32 +// CHECK: %[[RHS_IMAG_IS_INF:.*]] = arith.select %[[RHS_IMAG_INFINITE]], %[[ONE]], %[[ZERO]] : f32 +// CHECK: %[[RHS_IMAG_IS_INF_WITH_SIGN:.*]] = math.copysign %[[RHS_IMAG_IS_INF]], %[[RHS_IMAG]] : f32 +// CHECK: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = arith.mulf %[[LHS_REAL]], %[[RHS_REAL_IS_INF_WITH_SIGN]] fastmath : f32 +// CHECK: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = arith.mulf %[[LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN]] fastmath : f32 +// CHECK: %[[ZERO_MULTIPLICATOR_1:.*]] = arith.addf %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]] fastmath : f32 +// CHECK: %[[RESULT_REAL_4:.*]] = arith.mulf %[[ZERO]], %[[ZERO_MULTIPLICATOR_1]] fastmath : f32 +// CHECK: %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG:.*]] = arith.mulf %[[LHS_IMAG]], %[[RHS_REAL_IS_INF_WITH_SIGN]] fastmath : f32 +// CHECK: %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL:.*]] = arith.mulf %[[LHS_REAL]], %[[RHS_IMAG_IS_INF_WITH_SIGN]] fastmath : f32 +// CHECK: %[[ZERO_MULTIPLICATOR_2:.*]] = arith.subf %[[RHS_REAL_IS_INF_WITH_SIGN_TIMES_LHS_IMAG]], %[[RHS_IMAG_IS_INF_WITH_SIGN_TIMES_LHS_REAL]] fastmath : f32 +// CHECK: %[[RESULT_IMAG_4:.*]] = arith.mulf %[[ZERO]], %[[ZERO_MULTIPLICATOR_2]] fastmath : f32 + +// CHECK: %[[REAL_ABS_SMALLER_THAN_IMAG_ABS:.*]] = arith.cmpf olt, %[[RHS_REAL_ABS]], %[[RHS_IMAG_ABS]] : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[REAL_ABS_SMALLER_THAN_IMAG_ABS]], %[[RESULT_REAL_1]], %[[RESULT_REAL_2]] : f32 +// CHECK: %[[RESULT_IMAG:.*]] = arith.select %[[REAL_ABS_SMALLER_THAN_IMAG_ABS]], %[[RESULT_IMAG_1]], %[[RESULT_IMAG_2]] : f32 +// CHECK: %[[RESULT_REAL_SPECIAL_CASE_3:.*]] = arith.select %[[FINITE_NUM_INFINITE_DENOM]], %[[RESULT_REAL_4]], %[[RESULT_REAL]] : f32 +// CHECK: %[[RESULT_IMAG_SPECIAL_CASE_3:.*]] = arith.select %[[FINITE_NUM_INFINITE_DENOM]], %[[RESULT_IMAG_4]], %[[RESULT_IMAG]] : f32 +// CHECK: %[[RESULT_REAL_SPECIAL_CASE_2:.*]] = arith.select %[[INF_NUM_FINITE_DENOM]], %[[RESULT_REAL_3]], %[[RESULT_REAL_SPECIAL_CASE_3]] : f32 +// CHECK: %[[RESULT_IMAG_SPECIAL_CASE_2:.*]] = arith.select %[[INF_NUM_FINITE_DENOM]], %[[RESULT_IMAG_3]], %[[RESULT_IMAG_SPECIAL_CASE_3]] : f32 +// CHECK: %[[RESULT_REAL_SPECIAL_CASE_1:.*]] = arith.select %[[RESULT_IS_INFINITY]], %[[INFINITY_RESULT_REAL]], %[[RESULT_REAL_SPECIAL_CASE_2]] : f32 +// CHECK: %[[RESULT_IMAG_SPECIAL_CASE_1:.*]] = arith.select %[[RESULT_IS_INFINITY]], %[[INFINITY_RESULT_IMAG]], %[[RESULT_IMAG_SPECIAL_CASE_2]] : f32 +// CHECK: %[[RESULT_REAL_IS_NAN:.*]] = arith.cmpf uno, %[[RESULT_REAL]], %[[ZERO]] : f32 +// CHECK: %[[RESULT_IMAG_IS_NAN:.*]] = arith.cmpf uno, %[[RESULT_IMAG]], %[[ZERO]] : f32 +// CHECK: %[[RESULT_IS_NAN:.*]] = arith.andi %[[RESULT_REAL_IS_NAN]], %[[RESULT_IMAG_IS_NAN]] : i1 +// CHECK: %[[RESULT_REAL_WITH_SPECIAL_CASES:.*]] = arith.select %[[RESULT_IS_NAN]], %[[RESULT_REAL_SPECIAL_CASE_1]], %[[RESULT_REAL]] : f32 +// CHECK: %[[RESULT_IMAG_WITH_SPECIAL_CASES:.*]] = arith.select %[[RESULT_IS_NAN]], %[[RESULT_IMAG_SPECIAL_CASE_1]], %[[RESULT_IMAG]] : f32 +// CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL_WITH_SPECIAL_CASES]], %[[RESULT_IMAG_WITH_SPECIAL_CASES]] : complex +// CHECK: return %[[RESULT]] : complex + -- GitLab From dbb9749862481ad6aa82c96f6889b2ebba6f6062 Mon Sep 17 00:00:00 2001 From: Ding Fei Date: Tue, 9 Apr 2024 15:11:29 +0800 Subject: [PATCH 250/695] [ASTMatchers] fix captureVars assertion failure on capturesVariables (#76619) Matcher `capturesVar` should check for `capturesVariables()` before calling `getCaptureVar()` since it asserts this `LambdaCapture` does capture a variable. Fixes #76425 --- clang/docs/ReleaseNotes.rst | 1 + clang/include/clang/ASTMatchers/ASTMatchers.h | 2 ++ clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp | 2 ++ 3 files changed, 5 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index abf15c8dc49d..8d9ccf789d9c 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -633,6 +633,7 @@ AST Matchers - Add ``isExplicitObjectMemberFunction``. - Fixed ``forEachArgumentWithParam`` and ``forEachArgumentWithParamType`` to not skip the explicit object parameter for operator calls. +- Fixed captureVars assertion failure if not capturesVariables. (#GH76425) clang-format ------------ diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h index 2f71053d030f..8a2bbfff9e9e 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchers.h +++ b/clang/include/clang/ASTMatchers/ASTMatchers.h @@ -4961,6 +4961,8 @@ AST_MATCHER_P(LambdaExpr, hasAnyCapture, internal::Matcher, /// capturesVar(hasName("x")) matches `x` and `x = 1`. AST_MATCHER_P(LambdaCapture, capturesVar, internal::Matcher, InnerMatcher) { + if (!Node.capturesVariable()) + return false; auto *capturedVar = Node.getCapturedVar(); return capturedVar && InnerMatcher.matches(*capturedVar, Finder, Builder); } diff --git a/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp index 0edc65162fbe..b76627cb9be6 100644 --- a/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp +++ b/clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp @@ -2321,6 +2321,8 @@ TEST_P(ASTMatchersTest, LambdaCaptureTest_BindsToCaptureOfVarDecl) { matches("int main() { int cc; auto f = [=](){ return cc; }; }", matcher)); EXPECT_TRUE( matches("int main() { int cc; auto f = [&](){ return cc; }; }", matcher)); + EXPECT_TRUE(matches( + "void f(int a) { int cc[a]; auto f = [&](){ return cc;}; }", matcher)); } TEST_P(ASTMatchersTest, LambdaCaptureTest_BindsToCaptureWithInitializer) { -- GitLab From 9391ff8c86007562d40c240ea082b7c0cbf35947 Mon Sep 17 00:00:00 2001 From: Vassil Vassilev Date: Tue, 9 Apr 2024 05:27:14 +0000 Subject: [PATCH 251/695] Reland "Rework the printing of attributes (#87281)" Original commit message: " Commit https://github.com/llvm/llvm-project/commit/46f3ade introduced a notion of printing the attributes on the left to improve the printing of attributes attached to variable declarations. The intent was to produce more GCC compatible code because clang tends to print the attributes on the right hand side which is not accepted by gcc. This approach has increased the complexity in tablegen and the attrubutes themselves as now the are supposed to know where they could appear. That lead to mishandling of the `override` keyword which is modelled as an attribute in clang. This patch takes an inspiration from the existing approach and tries to keep the position of the attributes as they were written. To do so we use simpler heuristic which checks if the source locations of the attribute precedes the declaration. If so, it is considered to be printed before the declaration. Fixes https://github.com/llvm/llvm-project/issues/87151 " The reason for the bot breakage is that attributes coming from ApiNotes are not marked implicit even though they do not have source locations. This caused an assert to trigger. This patch forces attributes with no source location information to be printed on the left. That change is consistent to the overall intent of the change to increase the chances for attributes to compile across toolchains and at the same time the produced code to be as close as possible to the one written by the user. --- clang/include/clang/Basic/Attr.td | 14 +- clang/include/clang/Basic/CMakeLists.txt | 10 - clang/lib/AST/DeclPrinter.cpp | 179 +++++------------- clang/lib/AST/StmtPrinter.cpp | 5 +- clang/test/APINotes/retain-count-convention.m | 16 +- clang/test/APINotes/versioned.m | 4 +- clang/test/AST/ast-print-method-decl.cpp | 2 +- clang/test/AST/ast-print-no-sanitize.cpp | 2 +- clang/test/AST/attr-print-emit.cpp | 15 ++ clang/test/Analysis/scopes-cfg-output.cpp | 2 +- clang/test/OpenMP/assumes_codegen.cpp | 8 +- clang/test/OpenMP/assumes_print.cpp | 2 +- clang/test/OpenMP/assumes_template_print.cpp | 10 +- clang/test/OpenMP/declare_simd_ast_print.cpp | 4 +- clang/test/SemaCXX/attr-no-sanitize.cpp | 6 +- clang/test/SemaCXX/cxx11-attr-print.cpp | 8 +- clang/utils/TableGen/ClangAttrEmitter.cpp | 37 +--- clang/utils/TableGen/TableGen.cpp | 16 -- clang/utils/TableGen/TableGenBackends.h | 2 - 19 files changed, 102 insertions(+), 240 deletions(-) diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 6584460cf568..dc87a8c6f022 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -324,13 +324,10 @@ class Spelling { } class GNU : Spelling; -class Declspec : Spelling { - bit PrintOnLeft = 1; -} +class Declspec : Spelling; class Microsoft : Spelling; class CXX11 : Spelling { - bit CanPrintOnLeft = 0; string Namespace = namespace; } class C23 @@ -596,12 +593,6 @@ class AttrSubjectMatcherAggregateRule { def SubjectMatcherForNamed : AttrSubjectMatcherAggregateRule; class Attr { - // Specifies that when printed, this attribute is meaningful on the - // 'left side' of the declaration. - bit CanPrintOnLeft = 1; - // Specifies that when printed, this attribute is required to be printed on - // the 'left side' of the declaration. - bit PrintOnLeft = 0; // The various ways in which an attribute can be spelled in source list Spellings; // The things to which an attribute can appertain @@ -937,7 +928,6 @@ def AVRSignal : InheritableAttr, TargetSpecificAttr { } def AsmLabel : InheritableAttr { - let CanPrintOnLeft = 0; let Spellings = [CustomKeyword<"asm">, CustomKeyword<"__asm__">]; let Args = [ // Label specifies the mangled name for the decl. @@ -1534,7 +1524,6 @@ def AllocSize : InheritableAttr { } def EnableIf : InheritableAttr { - let CanPrintOnLeft = 0; // Does not have a [[]] spelling because this attribute requires the ability // to parse function arguments but the attribute is not written in the type // position. @@ -3171,7 +3160,6 @@ def Unavailable : InheritableAttr { } def DiagnoseIf : InheritableAttr { - let CanPrintOnLeft = 0; // Does not have a [[]] spelling because this attribute requires the ability // to parse function arguments but the attribute is not written in the type // position. diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt index 7d53c751c13a..2ef6ddc68f4b 100644 --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -31,16 +31,6 @@ clang_tablegen(AttrList.inc -gen-clang-attr-list SOURCE Attr.td TARGET ClangAttrList) -clang_tablegen(AttrLeftSideCanPrintList.inc -gen-clang-attr-can-print-left-list - -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ - SOURCE Attr.td - TARGET ClangAttrCanPrintLeftList) - -clang_tablegen(AttrLeftSideMustPrintList.inc -gen-clang-attr-must-print-left-list - -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ - SOURCE Attr.td - TARGET ClangAttrMustPrintLeftList) - clang_tablegen(AttrSubMatchRulesList.inc -gen-clang-attr-subject-match-rule-list -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ SOURCE Attr.td diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index edbcdfe4d55b..6afdb6cfccb1 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -21,6 +21,7 @@ #include "clang/AST/ExprCXX.h" #include "clang/AST/PrettyPrinter.h" #include "clang/Basic/Module.h" +#include "clang/Basic/SourceManager.h" #include "llvm/Support/raw_ostream.h" using namespace clang; @@ -49,18 +50,6 @@ namespace { void PrintObjCTypeParams(ObjCTypeParamList *Params); - enum class AttrPrintLoc { - None = 0, - Left = 1, - Right = 2, - Any = Left | Right, - - LLVM_MARK_AS_BITMASK_ENUM(/*DefaultValue=*/Any) - }; - - void prettyPrintAttributes(Decl *D, raw_ostream &out, - AttrPrintLoc loc = AttrPrintLoc::Any); - public: DeclPrinter(raw_ostream &Out, const PrintingPolicy &Policy, const ASTContext &Context, unsigned Indentation = 0, @@ -129,11 +118,10 @@ namespace { const TemplateParameterList *Params); void printTemplateArguments(llvm::ArrayRef Args, const TemplateParameterList *Params); - - inline void prettyPrintAttributes(Decl *D) { - prettyPrintAttributes(D, Out); - } - + enum class AttrPosAsWritten { Default = 0, Left, Right }; + void + prettyPrintAttributes(const Decl *D, + AttrPosAsWritten Pos = AttrPosAsWritten::Default); void prettyPrintPragmas(Decl *D); void printDeclType(QualType T, StringRef DeclName, bool Pack = false); }; @@ -250,87 +238,48 @@ raw_ostream& DeclPrinter::Indent(unsigned Indentation) { return Out; } -// For CLANG_ATTR_LIST_CanPrintOnLeft macro. -#include "clang/Basic/AttrLeftSideCanPrintList.inc" +static DeclPrinter::AttrPosAsWritten getPosAsWritten(const Attr *A, + const Decl *D) { + SourceLocation ALoc = A->getLoc(); + SourceLocation DLoc = D->getLocation(); + const ASTContext &C = D->getASTContext(); + if (ALoc.isInvalid() || DLoc.isInvalid()) + return DeclPrinter::AttrPosAsWritten::Left; -// For CLANG_ATTR_LIST_PrintOnLeft macro. -#include "clang/Basic/AttrLeftSideMustPrintList.inc" + if (C.getSourceManager().isBeforeInTranslationUnit(ALoc, DLoc)) + return DeclPrinter::AttrPosAsWritten::Left; -static bool canPrintOnLeftSide(attr::Kind kind) { -#ifdef CLANG_ATTR_LIST_CanPrintOnLeft - switch (kind) { - CLANG_ATTR_LIST_CanPrintOnLeft - return true; - default: - return false; - } -#else - return false; -#endif -} - -static bool canPrintOnLeftSide(const Attr *A) { - if (A->isStandardAttributeSyntax()) - return false; - - return canPrintOnLeftSide(A->getKind()); + return DeclPrinter::AttrPosAsWritten::Right; } -static bool mustPrintOnLeftSide(attr::Kind kind) { -#ifdef CLANG_ATTR_LIST_PrintOnLeft - switch (kind) { - CLANG_ATTR_LIST_PrintOnLeft - return true; - default: - return false; - } -#else - return false; -#endif -} - -static bool mustPrintOnLeftSide(const Attr *A) { - if (A->isDeclspecAttribute()) - return true; - - return mustPrintOnLeftSide(A->getKind()); -} - -void DeclPrinter::prettyPrintAttributes(Decl *D, llvm::raw_ostream &Out, - AttrPrintLoc Loc) { +void DeclPrinter::prettyPrintAttributes(const Decl *D, + AttrPosAsWritten Pos /*=Default*/) { if (Policy.PolishForDeclaration) return; if (D->hasAttrs()) { - AttrVec &Attrs = D->getAttrs(); + const AttrVec &Attrs = D->getAttrs(); for (auto *A : Attrs) { if (A->isInherited() || A->isImplicit()) continue; - - AttrPrintLoc AttrLoc = AttrPrintLoc::Right; - if (mustPrintOnLeftSide(A)) { - // If we must always print on left side (e.g. declspec), then mark as - // so. - AttrLoc = AttrPrintLoc::Left; - } else if (canPrintOnLeftSide(A)) { - // For functions with body defined we print the attributes on the left - // side so that GCC accept our dumps as well. - if (const FunctionDecl *FD = dyn_cast(D); - FD && FD->isThisDeclarationADefinition()) - // In case Decl is a function with a body, then attrs should be print - // on the left side. - AttrLoc = AttrPrintLoc::Left; - - // In case it is a variable declaration with a ctor, then allow - // printing on the left side for readbility. - else if (const VarDecl *VD = dyn_cast(D); - VD && VD->getInit() && - VD->getInitStyle() == VarDecl::CallInit) - AttrLoc = AttrPrintLoc::Left; + switch (A->getKind()) { +#define ATTR(X) +#define PRAGMA_SPELLING_ATTR(X) case attr::X: +#include "clang/Basic/AttrList.inc" + break; + default: + AttrPosAsWritten APos = getPosAsWritten(A, D); + assert(APos != AttrPosAsWritten::Default && + "Default not a valid for an attribute location"); + if (Pos == AttrPosAsWritten::Default || Pos == APos) { + if (Pos != AttrPosAsWritten::Left) + Out << ' '; + A->printPretty(Out, Policy); + if (Pos == AttrPosAsWritten::Left) + Out << ' '; + } + break; } - // Only print the side matches the user requested. - if ((Loc & AttrLoc) != AttrPrintLoc::None) - A->printPretty(Out, Policy); } } } @@ -691,8 +640,10 @@ static void MaybePrintTagKeywordIfSupressingScopes(PrintingPolicy &Policy, void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { if (!D->getDescribedFunctionTemplate() && - !D->isFunctionTemplateSpecialization()) + !D->isFunctionTemplateSpecialization()) { prettyPrintPragmas(D); + prettyPrintAttributes(D, AttrPosAsWritten::Left); + } if (D->isFunctionTemplateSpecialization()) Out << "template<> "; @@ -702,22 +653,6 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { printTemplateParameters(D->getTemplateParameterList(I)); } - std::string LeftsideAttrs; - llvm::raw_string_ostream LSAS(LeftsideAttrs); - - prettyPrintAttributes(D, LSAS, AttrPrintLoc::Left); - - // prettyPrintAttributes print a space on left side of the attribute. - if (LeftsideAttrs[0] == ' ') { - // Skip the space prettyPrintAttributes generated. - LeftsideAttrs.erase(0, LeftsideAttrs.find_first_not_of(' ')); - - // Add a single space between the attribute and the Decl name. - LSAS << ' '; - } - - Out << LeftsideAttrs; - CXXConstructorDecl *CDecl = dyn_cast(D); CXXConversionDecl *ConversionDecl = dyn_cast(D); CXXDeductionGuideDecl *GuideDecl = dyn_cast(D); @@ -883,7 +818,7 @@ void DeclPrinter::VisitFunctionDecl(FunctionDecl *D) { Ty.print(Out, Policy, Proto); } - prettyPrintAttributes(D, Out, AttrPrintLoc::Right); + prettyPrintAttributes(D, AttrPosAsWritten::Right); if (D->isPureVirtual()) Out << " = 0"; @@ -976,27 +911,12 @@ void DeclPrinter::VisitLabelDecl(LabelDecl *D) { void DeclPrinter::VisitVarDecl(VarDecl *D) { prettyPrintPragmas(D); + prettyPrintAttributes(D, AttrPosAsWritten::Left); + if (const auto *Param = dyn_cast(D); Param && Param->isExplicitObjectParameter()) Out << "this "; - std::string LeftSide; - llvm::raw_string_ostream LeftSideStream(LeftSide); - - // Print attributes that should be placed on the left, such as __declspec. - prettyPrintAttributes(D, LeftSideStream, AttrPrintLoc::Left); - - // prettyPrintAttributes print a space on left side of the attribute. - if (LeftSide[0] == ' ') { - // Skip the space prettyPrintAttributes generated. - LeftSide.erase(0, LeftSide.find_first_not_of(' ')); - - // Add a single space between the attribute and the Decl name. - LeftSideStream << ' '; - } - - Out << LeftSide; - QualType T = D->getTypeSourceInfo() ? D->getTypeSourceInfo()->getType() : D->getASTContext().getUnqualifiedObjCPointerType(D->getType()); @@ -1029,21 +949,16 @@ void DeclPrinter::VisitVarDecl(VarDecl *D) { } } - StringRef Name; - - Name = (isa(D) && Policy.CleanUglifiedParameters && - D->getIdentifier()) - ? D->getIdentifier()->deuglifiedName() - : D->getName(); - if (!Policy.SuppressTagKeyword && Policy.SuppressScope && !Policy.SuppressUnwrittenScope) MaybePrintTagKeywordIfSupressingScopes(Policy, T, Out); - printDeclType(T, Name); - // Print the attributes that should be placed right before the end of the - // decl. - prettyPrintAttributes(D, Out, AttrPrintLoc::Right); + printDeclType(T, (isa(D) && Policy.CleanUglifiedParameters && + D->getIdentifier()) + ? D->getIdentifier()->deuglifiedName() + : D->getName()); + + prettyPrintAttributes(D, AttrPosAsWritten::Right); Expr *Init = D->getInit(); if (!Policy.SuppressInitializers && Init) { diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index 74b18e50bf1f..2ba93d17f267 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -292,8 +292,11 @@ void StmtPrinter::VisitLabelStmt(LabelStmt *Node) { } void StmtPrinter::VisitAttributedStmt(AttributedStmt *Node) { - for (const auto *Attr : Node->getAttrs()) { + llvm::ArrayRef Attrs = Node->getAttrs(); + for (const auto *Attr : Attrs) { Attr->printPretty(OS, Policy); + if (Attr != Attrs.back()) + OS << ' '; } PrintStmt(Node->getSubStmt(), 0); diff --git a/clang/test/APINotes/retain-count-convention.m b/clang/test/APINotes/retain-count-convention.m index 4bf9610a352a..35cfe0581daf 100644 --- a/clang/test/APINotes/retain-count-convention.m +++ b/clang/test/APINotes/retain-count-convention.m @@ -5,15 +5,15 @@ #import -// CHECK: void *getCFOwnedToUnowned(void) __attribute__((cf_returns_not_retained)); -// CHECK: void *getCFUnownedToOwned(void) __attribute__((cf_returns_retained)); -// CHECK: void *getCFOwnedToNone(void) __attribute__((cf_unknown_transfer)); -// CHECK: id getObjCOwnedToUnowned(void) __attribute__((ns_returns_not_retained)); -// CHECK: id getObjCUnownedToOwned(void) __attribute__((ns_returns_retained)); -// CHECK: int indirectGetCFOwnedToUnowned(void * _Nullable *out __attribute__((cf_returns_not_retained))); -// CHECK: int indirectGetCFUnownedToOwned(void * _Nullable *out __attribute__((cf_returns_retained))); +// CHECK: __attribute__((cf_returns_not_retained)) void *getCFOwnedToUnowned(void); +// CHECK: __attribute__((cf_returns_retained)) void *getCFUnownedToOwned(void); +// CHECK: __attribute__((cf_unknown_transfer)) void *getCFOwnedToNone(void); +// CHECK: __attribute__((ns_returns_not_retained)) id getObjCOwnedToUnowned(void); +// CHECK: __attribute__((ns_returns_retained)) id getObjCUnownedToOwned(void); +// CHECK: int indirectGetCFOwnedToUnowned(__attribute__((cf_returns_not_retained)) void * _Nullable *out); +// CHECK: int indirectGetCFUnownedToOwned(__attribute__((cf_returns_retained)) void * _Nullable *out); // CHECK: int indirectGetCFOwnedToNone(void * _Nullable *out); -// CHECK: int indirectGetCFNoneToOwned(void **out __attribute__((cf_returns_not_retained))); +// CHECK: int indirectGetCFNoneToOwned(__attribute__((cf_returns_not_retained)) void **out); // CHECK-LABEL: @interface MethodTest // CHECK: - (id)getOwnedToUnowned __attribute__((ns_returns_not_retained)); diff --git a/clang/test/APINotes/versioned.m b/clang/test/APINotes/versioned.m index 61cc8c3f7c4d..4a8da1556f87 100644 --- a/clang/test/APINotes/versioned.m +++ b/clang/test/APINotes/versioned.m @@ -13,7 +13,7 @@ #import // CHECK-UNVERSIONED: void moveToPointDUMP(double x, double y) __attribute__((swift_name("moveTo(x:y:)"))); -// CHECK-VERSIONED: void moveToPointDUMP(double x, double y) __attribute__((swift_name("moveTo(a:b:)"))); +// CHECK-VERSIONED:__attribute__((swift_name("moveTo(a:b:)"))) void moveToPointDUMP(double x, double y); // CHECK-DUMP-LABEL: Dumping moveToPointDUMP // CHECK-VERSIONED-DUMP: SwiftVersionedAdditionAttr {{.+}} Implicit 3.0 IsReplacedByActive{{$}} @@ -65,7 +65,7 @@ // CHECK-DUMP-NOT: Dumping -// CHECK-UNVERSIONED: void acceptClosure(void (^block)(void) __attribute__((noescape))); +// CHECK-UNVERSIONED: void acceptClosure(__attribute__((noescape)) void (^block)(void)); // CHECK-VERSIONED: void acceptClosure(void (^block)(void)); // CHECK-UNVERSIONED: void privateFunc(void) __attribute__((swift_private)); diff --git a/clang/test/AST/ast-print-method-decl.cpp b/clang/test/AST/ast-print-method-decl.cpp index 75dea0cac16b..cb5d10096381 100644 --- a/clang/test/AST/ast-print-method-decl.cpp +++ b/clang/test/AST/ast-print-method-decl.cpp @@ -94,7 +94,7 @@ struct DefMethodsWithoutBody { // CHECK-NEXT: DefMethodsWithoutBody() = default; ~DefMethodsWithoutBody() = default; - // CHECK-NEXT: __attribute__((alias("X"))) void m1(); + // CHECK-NEXT: void m1() __attribute__((alias("X"))); void m1() __attribute__((alias("X"))); // CHECK-NEXT: }; diff --git a/clang/test/AST/ast-print-no-sanitize.cpp b/clang/test/AST/ast-print-no-sanitize.cpp index 4ff97190955a..a5ada8246f0c 100644 --- a/clang/test/AST/ast-print-no-sanitize.cpp +++ b/clang/test/AST/ast-print-no-sanitize.cpp @@ -4,4 +4,4 @@ void should_not_crash_1() __attribute__((no_sanitize_memory)); [[clang::no_sanitize_memory]] void should_not_crash_2(); // CHECK: void should_not_crash_1() __attribute__((no_sanitize("memory"))); -// CHECK: void should_not_crash_2() {{\[\[}}clang::no_sanitize("memory"){{\]\]}}; +// CHECK: {{\[\[}}clang::no_sanitize("memory"){{\]\]}} void should_not_crash_2(); diff --git a/clang/test/AST/attr-print-emit.cpp b/clang/test/AST/attr-print-emit.cpp index 8c48eb92daba..8c8a2b208059 100644 --- a/clang/test/AST/attr-print-emit.cpp +++ b/clang/test/AST/attr-print-emit.cpp @@ -73,3 +73,18 @@ class C { // CHECK: void pwtt(void *, int) __attribute__((pointer_with_type_tag(foo, 2, 3))); void pwtt(void *, int) __attribute__((pointer_with_type_tag(foo, 2, 3))); }; + +#define ANNOTATE_ATTR __attribute__((annotate("Annotated"))) +ANNOTATE_ATTR int annotated_attr ANNOTATE_ATTR = 0; +// CHECK: __attribute__((annotate("Annotated"))) int annotated_attr __attribute__((annotate("Annotated"))) = 0; + +// FIXME: We do not print the attribute as written after the type specifier. +int ANNOTATE_ATTR annotated_attr_fixme = 0; +// CHECK: __attribute__((annotate("Annotated"))) int annotated_attr_fixme = 0; + +#define NONNULL_ATTR __attribute__((nonnull(1))) +ANNOTATE_ATTR NONNULL_ATTR void fn_non_null_annotated_attr(int *) __attribute__((annotate("AnnotatedRHS"))); +// CHECK:__attribute__((annotate("Annotated"))) __attribute__((nonnull(1))) void fn_non_null_annotated_attr(int *) __attribute__((annotate("AnnotatedRHS"))); + +[[gnu::nonnull(1)]] [[gnu::always_inline]] void cxx11_attr(int*) ANNOTATE_ATTR; +// CHECK: {{\[\[}}gnu::nonnull(1)]] {{\[\[}}gnu::always_inline]] void cxx11_attr(int *) __attribute__((annotate("Annotated"))); diff --git a/clang/test/Analysis/scopes-cfg-output.cpp b/clang/test/Analysis/scopes-cfg-output.cpp index 4eb8967e3735..5e6706602d45 100644 --- a/clang/test/Analysis/scopes-cfg-output.cpp +++ b/clang/test/Analysis/scopes-cfg-output.cpp @@ -1469,7 +1469,7 @@ void test_cleanup_functions2(int m) { // CHECK: [B1] // CHECK-NEXT: 1: CFGScopeBegin(f) // CHECK-NEXT: 2: (CXXConstructExpr, [B1.3], F) -// CHECK-NEXT: 3: __attribute__((cleanup(cleanup_F))) F f; +// CHECK-NEXT: 3: F f __attribute__((cleanup(cleanup_F))); // CHECK-NEXT: 4: CleanupFunction (cleanup_F) // CHECK-NEXT: 5: [B1.3].~F() (Implicit destructor) // CHECK-NEXT: 6: CFGScopeEnd(f) diff --git a/clang/test/OpenMP/assumes_codegen.cpp b/clang/test/OpenMP/assumes_codegen.cpp index 6a5871c303aa..4a2518a51ec3 100644 --- a/clang/test/OpenMP/assumes_codegen.cpp +++ b/clang/test/OpenMP/assumes_codegen.cpp @@ -67,7 +67,7 @@ int lambda_outer() { } #pragma omp end assumes -// AST: __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void foo() { +// AST: void foo() __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) { // AST-NEXT: } // AST-NEXT: class BAR { // AST-NEXT: public: @@ -81,7 +81,7 @@ int lambda_outer() { // AST-NEXT: __attribute__((assume("ompx_range_bar_only"))) __attribute__((assume("ompx_range_bar_only_2"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void bar() { // AST-NEXT: BAR b; // AST-NEXT: } -// AST-NEXT: void baz() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); +// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz(); // AST-NEXT: template class BAZ { // AST-NEXT: public: // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) BAZ() { @@ -95,8 +95,8 @@ int lambda_outer() { // AST-NEXT: public: // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) BAZ() { // AST-NEXT: } -// AST-NEXT: void baz1() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); -// AST-NEXT: static void baz2() __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))); +// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz1(); +// AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) static void baz2(); // AST-NEXT: }; // AST-NEXT: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines,ompx_another_warning,ompx_after_invalid_clauses"))) __attribute__((assume("omp_no_openmp"))) void baz() { // AST-NEXT: BAZ b; diff --git a/clang/test/OpenMP/assumes_print.cpp b/clang/test/OpenMP/assumes_print.cpp index a7f04edb3b1a..da3629f70408 100644 --- a/clang/test/OpenMP/assumes_print.cpp +++ b/clang/test/OpenMP/assumes_print.cpp @@ -37,7 +37,7 @@ void baz() { } #pragma omp end assumes -// CHECK: __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void foo() +// CHECK: void foo() __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) // CHECK: __attribute__((assume("ompx_range_bar_only"))) __attribute__((assume("ompx_range_bar_only_2"))) __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void bar() // CHECK: __attribute__((assume("ompx_1234"))) __attribute__((assume("omp_no_openmp_routines"))) __attribute__((assume("omp_no_openmp"))) void baz() diff --git a/clang/test/OpenMP/assumes_template_print.cpp b/clang/test/OpenMP/assumes_template_print.cpp index bd1100fbefff..e0bc3e9884ca 100644 --- a/clang/test/OpenMP/assumes_template_print.cpp +++ b/clang/test/OpenMP/assumes_template_print.cpp @@ -17,7 +17,7 @@ template struct S { int a; // CHECK: template struct S { -// CHECK: __attribute__((assume("ompx_global_assumption"))) void foo() { +// CHECK: void foo() __attribute__((assume("ompx_global_assumption"))) { void foo() { #pragma omp parallel {} @@ -25,15 +25,15 @@ struct S { }; // CHECK: template<> struct S { -// CHECK: __attribute__((assume("ompx_global_assumption"))) void foo() { +// CHECK: void foo() __attribute__((assume("ompx_global_assumption"))) { #pragma omp begin assumes no_openmp -// CHECK: __attribute__((assume("omp_no_openmp"))) __attribute__((assume("ompx_global_assumption"))) void S_with_assumes_no_call() { +// CHECK: __attribute__((assume("omp_no_openmp"))) void S_with_assumes_no_call() __attribute__((assume("ompx_global_assumption"))) { void S_with_assumes_no_call() { S s; s.a = 0; } -// CHECK: __attribute__((assume("omp_no_openmp"))) __attribute__((assume("ompx_global_assumption"))) void S_with_assumes_call() { +// CHECK: __attribute__((assume("omp_no_openmp"))) void S_with_assumes_call() __attribute__((assume("ompx_global_assumption"))) { void S_with_assumes_call() { S s; s.a = 0; @@ -42,7 +42,7 @@ void S_with_assumes_call() { } #pragma omp end assumes -// CHECK: __attribute__((assume("ompx_global_assumption"))) void S_without_assumes() { +// CHECK: void S_without_assumes() __attribute__((assume("ompx_global_assumption"))) { void S_without_assumes() { S s; s.foo(); diff --git a/clang/test/OpenMP/declare_simd_ast_print.cpp b/clang/test/OpenMP/declare_simd_ast_print.cpp index 1adf95226c8b..565dc2dfc04d 100644 --- a/clang/test/OpenMP/declare_simd_ast_print.cpp +++ b/clang/test/OpenMP/declare_simd_ast_print.cpp @@ -60,11 +60,11 @@ void h(int *hp, int *hp2, int *hq, int *lin) class VV { // CHECK: #pragma omp declare simd uniform(this, a) linear(val(b): a) - // CHECK-NEXT: __attribute__((cold)) int add(int a, int b) { + // CHECK-NEXT: int add(int a, int b) __attribute__((cold)) { // CHECK-NEXT: return a + b; // CHECK-NEXT: } #pragma omp declare simd uniform(this, a) linear(val(b): a) - __attribute__((cold)) int add(int a, int b) { return a + b; } + int add(int a, int b) __attribute__((cold)) { return a + b; } // CHECK: #pragma omp declare simd aligned(b: 4) aligned(a) linear(ref(b): 4) linear(val(this)) linear(val(a)) // CHECK-NEXT: float taddpf(float *a, float *&b) { diff --git a/clang/test/SemaCXX/attr-no-sanitize.cpp b/clang/test/SemaCXX/attr-no-sanitize.cpp index a464947fe5a3..8951f616ce0f 100644 --- a/clang/test/SemaCXX/attr-no-sanitize.cpp +++ b/clang/test/SemaCXX/attr-no-sanitize.cpp @@ -16,12 +16,12 @@ int f3() __attribute__((no_sanitize("address"))); // DUMP-LABEL: FunctionDecl {{.*}} f4 // DUMP: NoSanitizeAttr {{.*}} thread -// PRINT: int f4() {{\[\[}}clang::no_sanitize("thread")]] +// PRINT: {{\[\[}}clang::no_sanitize("thread")]] int f4() [[clang::no_sanitize("thread")]] int f4(); // DUMP-LABEL: FunctionDecl {{.*}} f4 // DUMP: NoSanitizeAttr {{.*}} hwaddress -// PRINT: int f4() {{\[\[}}clang::no_sanitize("hwaddress")]] +// PRINT: {{\[\[}}clang::no_sanitize("hwaddress")]] int f4() [[clang::no_sanitize("hwaddress")]] int f4(); // DUMP-LABEL: FunctionDecl {{.*}} f5 @@ -36,5 +36,5 @@ int f6() __attribute__((no_sanitize("unknown"))); // expected-warning{{unknown s // DUMP-LABEL: FunctionDecl {{.*}} f7 // DUMP: NoSanitizeAttr {{.*}} memtag -// PRINT: int f7() {{\[\[}}clang::no_sanitize("memtag")]] +// PRINT: {{\[\[}}clang::no_sanitize("memtag")]] int f7() [[clang::no_sanitize("memtag")]] int f7(); diff --git a/clang/test/SemaCXX/cxx11-attr-print.cpp b/clang/test/SemaCXX/cxx11-attr-print.cpp index c988972aeb1a..a169d1b4409b 100644 --- a/clang/test/SemaCXX/cxx11-attr-print.cpp +++ b/clang/test/SemaCXX/cxx11-attr-print.cpp @@ -24,10 +24,10 @@ int d [[deprecated("warning")]]; // CHECK: __attribute__((deprecated("warning", "fixit"))); int e __attribute__((deprecated("warning", "fixit"))); -// CHECK: int cxx11_alignas alignas(4); +// CHECK: alignas(4) int cxx11_alignas; alignas(4) int cxx11_alignas; -// CHECK: int c11_alignas _Alignas(int); +// CHECK: _Alignas(int) int c11_alignas; _Alignas(int) int c11_alignas; // CHECK: int foo() __attribute__((const)); @@ -66,7 +66,7 @@ void f8 (void *, const char *, ...) __attribute__ ((format (printf, 2, 3))); // CHECK: int n alignas(4 // CHECK: int p alignas(int // CHECK: __attribute__((pure)) static int f() -// CHECK: static int g() {{\[}}[gnu::pure]] +// CHECK: {{\[}}[gnu::pure]] static int g() template struct S { __attribute__((aligned(4))) int m; alignas(4) int n; @@ -82,7 +82,7 @@ template struct S { // CHECK: int m __attribute__((aligned(4 // CHECK: int n alignas(4 // CHECK: __attribute__((pure)) static int f() -// CHECK: static int g() {{\[}}[gnu::pure]] +// CHECK: {{\[}}[gnu::pure]] static int g() template struct S; // CHECK: using Small2 {{\[}}[gnu::mode(byte)]] = int; diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp index eb5c34d15693..6c56f99f503d 100644 --- a/clang/utils/TableGen/ClangAttrEmitter.cpp +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp @@ -1591,10 +1591,10 @@ writePrettyPrintFunction(const Record &R, std::string Variety = Spellings[I].variety(); if (Variety == "GNU") { - Prefix = " __attribute__(("; + Prefix = "__attribute__(("; Suffix = "))"; } else if (Variety == "CXX11" || Variety == "C23") { - Prefix = " [["; + Prefix = "[["; Suffix = "]]"; std::string Namespace = Spellings[I].nameSpace(); if (!Namespace.empty()) { @@ -1602,7 +1602,7 @@ writePrettyPrintFunction(const Record &R, Spelling += "::"; } } else if (Variety == "Declspec") { - Prefix = " __declspec("; + Prefix = "__declspec("; Suffix = ")"; } else if (Variety == "Microsoft") { Prefix = "["; @@ -3316,37 +3316,6 @@ void EmitClangAttrList(RecordKeeper &Records, raw_ostream &OS) { OS << "#undef PRAGMA_SPELLING_ATTR\n"; } -// Emits the enumeration list for attributes. -void EmitClangAttrPrintList(const std::string &FieldName, RecordKeeper &Records, - raw_ostream &OS) { - emitSourceFileHeader( - "List of attributes that can be print on the left side of a decl", OS, - Records); - - AttrClassHierarchy Hierarchy(Records); - - std::vector Attrs = Records.getAllDerivedDefinitions("Attr"); - std::vector PragmaAttrs; - bool first = false; - - for (auto *Attr : Attrs) { - if (!Attr->getValueAsBit("ASTNode")) - continue; - - if (!Attr->getValueAsBit(FieldName)) - continue; - - if (!first) { - first = true; - OS << "#define CLANG_ATTR_LIST_" << FieldName; - } - - OS << " \\\n case attr::" << Attr->getName() << ":"; - } - - OS << '\n'; -} - // Emits the enumeration list for attributes. void EmitClangAttrSubjectMatchRuleList(RecordKeeper &Records, raw_ostream &OS) { emitSourceFileHeader( diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index 3f22e43b97ec..42cc704543f1 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -31,8 +31,6 @@ enum ActionType { GenClangAttrSubjectMatchRulesParserStringSwitches, GenClangAttrImpl, GenClangAttrList, - GenClangAttrCanPrintLeftList, - GenClangAttrMustPrintLeftList, GenClangAttrDocTable, GenClangAttrSubjectMatchRuleList, GenClangAttrPCHRead, @@ -134,14 +132,6 @@ cl::opt Action( "Generate clang attribute implementations"), clEnumValN(GenClangAttrList, "gen-clang-attr-list", "Generate a clang attribute list"), - clEnumValN(GenClangAttrCanPrintLeftList, - "gen-clang-attr-can-print-left-list", - "Generate list of attributes that can be printed on left " - "side of a decl"), - clEnumValN(GenClangAttrMustPrintLeftList, - "gen-clang-attr-must-print-left-list", - "Generate list of attributes that must be printed on left " - "side of a decl"), clEnumValN(GenClangAttrDocTable, "gen-clang-attr-doc-table", "Generate a table of attribute documentation"), clEnumValN(GenClangAttrSubjectMatchRuleList, @@ -345,12 +335,6 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenClangAttrList: EmitClangAttrList(Records, OS); break; - case GenClangAttrCanPrintLeftList: - EmitClangAttrPrintList("CanPrintOnLeft", Records, OS); - break; - case GenClangAttrMustPrintLeftList: - EmitClangAttrPrintList("PrintOnLeft", Records, OS); - break; case GenClangAttrDocTable: EmitClangAttrDocTable(Records, OS); break; diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index ecd506b7b6b5..5f2dd257cb90 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -47,8 +47,6 @@ void EmitClangAttrSubjectMatchRulesParserStringSwitches( void EmitClangAttrClass(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrImpl(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); -void EmitClangAttrPrintList(const std::string &FieldName, - llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrSubjectMatchRuleList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHRead(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); -- GitLab From d8d131dfa99762ccdd2116661980b7d0493cd7b5 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 9 Apr 2024 15:46:38 +0800 Subject: [PATCH 252/695] [RISCV] Convert more constant splats in tests to splat shorthand. NFC (#87616) A handy shorthand for specifying the shufflevector(insertelement(poison, foo, 0), poison, zeroinitializer) splat pattern was introduced in #74620. Some of the RISC-V tests were converted over to use this new form in dbb65dd330cc1696d7ca3dedc7aa9fa12c55a075, this patch handles the rest which didn't have any codegen diffs. This not only converts some constant expressions to the new form, but also instruction sequences that weren't previously constant expressions to constant expressions as well. In some cases this affects codegen, but these have been omitted here and will be handled in a separate PR. --- llvm/test/CodeGen/RISCV/rvv/abs-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll | 68 +- llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 68 +- llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/combine-sats.ll | 44 +- llvm/test/CodeGen/RISCV/rvv/combine-splats.ll | 56 +- .../CodeGen/RISCV/rvv/constant-folding.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 192 +- llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 192 +- llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll | 16 +- .../CodeGen/RISCV/rvv/extractelt-int-rv32.ll | 20 +- .../CodeGen/RISCV/rvv/extractelt-int-rv64.ll | 20 +- .../CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll | 72 +- .../RISCV/rvv/fixed-vectors-bitreverse-vp.ll | 72 +- .../RISCV/rvv/fixed-vectors-bswap-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-ceil-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-ctlz-vp.ll | 144 +- .../RISCV/rvv/fixed-vectors-ctpop-vp.ll | 72 +- .../RISCV/rvv/fixed-vectors-cttz-vp.ll | 144 +- .../RISCV/rvv/fixed-vectors-floor-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-fmaximum-vp.ll | 52 +- .../RISCV/rvv/fixed-vectors-fminimum-vp.ll | 52 +- .../RISCV/rvv/fixed-vectors-fp-splat.ll | 48 +- .../RISCV/rvv/fixed-vectors-fpext-vp.ll | 6 +- .../RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll | 6 +- .../RISCV/rvv/fixed-vectors-fptosi-vp.ll | 26 +- .../RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll | 6 +- .../RISCV/rvv/fixed-vectors-fptoui-vp.ll | 26 +- .../RISCV/rvv/fixed-vectors-fptrunc-vp.ll | 6 +- .../RISCV/rvv/fixed-vectors-int-setcc.ll | 44 +- .../RISCV/rvv/fixed-vectors-int-splat.ll | 64 +- .../CodeGen/RISCV/rvv/fixed-vectors-int.ll | 208 +- .../RISCV/rvv/fixed-vectors-masked-gather.ll | 10 +- .../RISCV/rvv/fixed-vectors-nearbyint-vp.ll | 56 +- .../rvv/fixed-vectors-peephole-vmerge-vops.ll | 108 +- .../RISCV/rvv/fixed-vectors-rint-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-round-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 216 +- .../RISCV/rvv/fixed-vectors-sext-vp-mask.ll | 6 +- .../RISCV/rvv/fixed-vectors-sext-vp.ll | 14 +- .../RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll | 6 +- .../RISCV/rvv/fixed-vectors-sitofp-vp.ll | 26 +- .../RISCV/rvv/fixed-vectors-strided-vpload.ll | 36 +- .../rvv/fixed-vectors-strided-vpstore.ll | 12 +- .../RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll | 6 +- .../RISCV/rvv/fixed-vectors-uitofp-vp.ll | 26 +- .../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 32 +- .../RISCV/rvv/fixed-vectors-vadd-vp.ll | 332 +-- .../RISCV/rvv/fixed-vectors-vand-vp.ll | 310 +-- .../RISCV/rvv/fixed-vectors-vcopysign-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-vdiv-vp.ll | 128 +- .../RISCV/rvv/fixed-vectors-vdivu-vp.ll | 128 +- .../RISCV/rvv/fixed-vectors-vfabs-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-vfadd-vp.ll | 100 +- .../RISCV/rvv/fixed-vectors-vfclass-vp.ll | 44 +- .../RISCV/rvv/fixed-vectors-vfdiv-vp.ll | 96 +- .../RISCV/rvv/fixed-vectors-vfma-vp.ll | 104 +- .../RISCV/rvv/fixed-vectors-vfmacc-vp.ll | 432 ++-- .../RISCV/rvv/fixed-vectors-vfmax-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-vfmin-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-vfmsac-vp.ll | 624 ++---- .../RISCV/rvv/fixed-vectors-vfmul-vp.ll | 96 +- .../RISCV/rvv/fixed-vectors-vfmuladd-vp.ll | 104 +- .../RISCV/rvv/fixed-vectors-vfneg-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-vfnmacc-vp.ll | 816 +++----- .../RISCV/rvv/fixed-vectors-vfnmsac-vp.ll | 624 ++---- .../RISCV/rvv/fixed-vectors-vfrdiv-vp.ll | 48 +- .../RISCV/rvv/fixed-vectors-vfrsub-vp.ll | 48 +- .../RISCV/rvv/fixed-vectors-vfsqrt-vp.ll | 56 +- .../RISCV/rvv/fixed-vectors-vfsub-vp.ll | 96 +- .../RISCV/rvv/fixed-vectors-vmacc-vp.ll | 720 +++---- .../RISCV/rvv/fixed-vectors-vmax-vp.ll | 140 +- .../RISCV/rvv/fixed-vectors-vmaxu-vp.ll | 140 +- .../RISCV/rvv/fixed-vectors-vmin-vp.ll | 140 +- .../RISCV/rvv/fixed-vectors-vminu-vp.ll | 140 +- .../RISCV/rvv/fixed-vectors-vmul-vp.ll | 136 +- .../RISCV/rvv/fixed-vectors-vnmsac-vp.ll | 720 +++---- .../CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll | 306 +-- .../RISCV/rvv/fixed-vectors-vpgather.ll | 32 +- .../CodeGen/RISCV/rvv/fixed-vectors-vpload.ll | 32 +- .../RISCV/rvv/fixed-vectors-vpmerge.ll | 72 +- .../RISCV/rvv/fixed-vectors-vpscatter.ll | 32 +- .../RISCV/rvv/fixed-vectors-vpstore.ll | 4 +- .../RISCV/rvv/fixed-vectors-vrem-vp.ll | 128 +- .../RISCV/rvv/fixed-vectors-vremu-vp.ll | 128 +- .../CodeGen/RISCV/rvv/fixed-vectors-vror.ll | 88 +- .../RISCV/rvv/fixed-vectors-vrsub-vp.ll | 224 +-- .../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 332 +-- .../CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll | 64 +- .../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 332 +-- .../CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll | 64 +- .../RISCV/rvv/fixed-vectors-vselect.ll | 24 +- .../RISCV/rvv/fixed-vectors-vshl-vp.ll | 288 +-- .../RISCV/rvv/fixed-vectors-vsra-vp.ll | 288 +-- .../RISCV/rvv/fixed-vectors-vsrl-vp.ll | 288 +-- .../RISCV/rvv/fixed-vectors-vssub-vp.ll | 332 +-- .../CodeGen/RISCV/rvv/fixed-vectors-vssub.ll | 64 +- .../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 332 +-- .../CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll | 64 +- .../RISCV/rvv/fixed-vectors-vsub-vp.ll | 136 +- .../RISCV/rvv/fixed-vectors-vxor-vp.ll | 476 +---- .../RISCV/rvv/fixed-vectors-zext-vp-mask.ll | 6 +- .../RISCV/rvv/fixed-vectors-zext-vp.ll | 14 +- llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 68 +- llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll | 56 +- .../RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll | 4 +- .../test/CodeGen/RISCV/rvv/masked-load-int.ll | 4 +- .../CodeGen/RISCV/rvv/masked-store-int.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll | 28 +- .../test/CodeGen/RISCV/rvv/mscatter-sdnode.ll | 28 +- .../CodeGen/RISCV/rvv/narrow-shift-extend.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/rint-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 64 +- .../rvv/rvv-peephole-vmerge-masked-vops.ll | 68 +- .../RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll | 8 +- .../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 130 +- .../CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 432 +--- llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll | 502 ++--- .../CodeGen/RISCV/rvv/sink-splat-operands.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/stepvector.ll | 48 +- .../CodeGen/RISCV/rvv/strided-load-store.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll | 44 +- .../test/CodeGen/RISCV/rvv/strided-vpstore.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll | 118 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll | 190 +- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 442 +--- llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll | 278 +-- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll | 414 +--- llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll | 110 +- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll | 142 +- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 116 +- llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 112 +- .../test/CodeGen/RISCV/rvv/vfma-vp-combine.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll | 1778 ++++++----------- llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll | 540 ++--- llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll | 780 +++----- llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 112 +- llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll | 1778 ++++++----------- llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll | 1020 ++++------ llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll | 780 +++----- llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll | 64 +- llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 112 +- llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll | 226 +-- llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll | 110 +- llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll | 264 +-- llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll | 180 +- llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll | 880 +++----- llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll | 880 +++----- llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll | 100 +- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll | 132 +- llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll | 192 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll | 136 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll | 192 +- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll | 132 +- llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll | 192 +- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll | 146 +- llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll | 192 +- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll | 134 +- llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll | 184 +- llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll | 100 +- llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll | 880 +++----- llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll | 272 +-- llvm/test/CodeGen/RISCV/rvv/vor-vp.ll | 418 +--- .../rvv/vp-reverse-float-fixed-vectors.ll | 8 +- .../CodeGen/RISCV/rvv/vp-reverse-float.ll | 32 +- .../RISCV/rvv/vp-reverse-int-fixed-vectors.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll | 68 +- .../rvv/vp-reverse-mask-fixed-vectors.ll | 16 +- .../test/CodeGen/RISCV/rvv/vp-reverse-mask.ll | 28 +- .../RISCV/rvv/vp-splice-fixed-vectors.ll | 48 +- .../RISCV/rvv/vp-splice-mask-fixed-vectors.ll | 32 +- .../RISCV/rvv/vp-splice-mask-vectors.ll | 56 +- llvm/test/CodeGen/RISCV/rvv/vp-splice.ll | 70 +- .../test/CodeGen/RISCV/rvv/vpgather-sdnode.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vpload.ll | 32 +- llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 100 +- .../CodeGen/RISCV/rvv/vpscatter-sdnode.ll | 28 +- llvm/test/CodeGen/RISCV/rvv/vpstore.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll | 120 +- llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll | 176 +- llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll | 308 +-- llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll | 434 +--- llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll | 434 +--- llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vselect-int.ll | 96 +- llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll | 124 +- llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll | 396 +--- llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll | 396 +--- llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll | 108 +- llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll | 396 +--- llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll | 434 +--- llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll | 88 +- llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll | 434 +--- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll | 98 +- llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll | 184 +- llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll | 268 +-- llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll | 644 ++---- 242 files changed, 10855 insertions(+), 27481 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll index 8898ce509ecb..eb74e2d302f1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll @@ -24,9 +24,7 @@ define @vp_abs_nxv1i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv1i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -50,9 +48,7 @@ define @vp_abs_nxv2i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv2i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -76,9 +72,7 @@ define @vp_abs_nxv4i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv4i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -102,9 +96,7 @@ define @vp_abs_nxv8i8_unmasked( %va, i32 zero ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv8i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -128,9 +120,7 @@ define @vp_abs_nxv16i8_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv16i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -154,9 +144,7 @@ define @vp_abs_nxv32i8_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv32i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv32i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -180,9 +168,7 @@ define @vp_abs_nxv64i8_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv64i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv64i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -206,9 +192,7 @@ define @vp_abs_nxv1i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv1i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +216,7 @@ define @vp_abs_nxv2i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv2i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -258,9 +240,7 @@ define @vp_abs_nxv4i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv4i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -284,9 +264,7 @@ define @vp_abs_nxv8i16_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv8i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -310,9 +288,7 @@ define @vp_abs_nxv16i16_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv16i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -336,9 +312,7 @@ define @vp_abs_nxv32i16_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv32i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv32i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -362,9 +336,7 @@ define @vp_abs_nxv1i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv1i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -388,9 +360,7 @@ define @vp_abs_nxv2i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv2i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -414,9 +384,7 @@ define @vp_abs_nxv4i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv4i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -440,9 +408,7 @@ define @vp_abs_nxv8i32_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv8i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -466,9 +432,7 @@ define @vp_abs_nxv16i32_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv16i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -492,9 +456,7 @@ define @vp_abs_nxv1i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv1i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -518,9 +480,7 @@ define @vp_abs_nxv2i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv2i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -544,9 +504,7 @@ define @vp_abs_nxv4i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv4i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -570,9 +528,7 @@ define @vp_abs_nxv7i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv7i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv7i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -596,9 +552,7 @@ define @vp_abs_nxv8i64_unmasked( %va, i32 z ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv8i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -675,8 +629,6 @@ define @vp_abs_nxv16i64_unmasked( %va, i3 ; CHECK-NEXT: vrsub.vi v24, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.abs.nxv16i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll index 66eab2f65362..879dff4a6e49 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll @@ -70,9 +70,7 @@ define @vp_bitreverse_nxv1i8_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv1i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv1i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +136,7 @@ define @vp_bitreverse_nxv2i8_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv2i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv2i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -206,9 +202,7 @@ define @vp_bitreverse_nxv4i8_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv4i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv4i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -274,9 +268,7 @@ define @vp_bitreverse_nxv8i8_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv8i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv8i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -342,9 +334,7 @@ define @vp_bitreverse_nxv16i8_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv16i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv16i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +400,7 @@ define @vp_bitreverse_nxv32i8_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv32i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv32i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -478,9 +466,7 @@ define @vp_bitreverse_nxv64i8_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv64i8( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv64i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -560,9 +546,7 @@ define @vp_bitreverse_nxv1i16_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv1i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv1i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -642,9 +626,7 @@ define @vp_bitreverse_nxv2i16_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv2i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv2i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -724,9 +706,7 @@ define @vp_bitreverse_nxv4i16_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv4i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv4i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -806,9 +786,7 @@ define @vp_bitreverse_nxv8i16_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv8i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv8i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -888,9 +866,7 @@ define @vp_bitreverse_nxv16i16_unmasked( ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv16i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv16i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -970,9 +946,7 @@ define @vp_bitreverse_nxv32i16_unmasked( ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv32i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv32i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -1068,9 +1042,7 @@ define @vp_bitreverse_nxv1i32_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv1i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv1i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1166,9 +1138,7 @@ define @vp_bitreverse_nxv2i32_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv2i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv2i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1264,9 +1234,7 @@ define @vp_bitreverse_nxv4i32_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv4i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv4i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1362,9 +1330,7 @@ define @vp_bitreverse_nxv8i32_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv8i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv8i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1460,9 +1426,7 @@ define @vp_bitreverse_nxv16i32_unmasked( ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv16i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv16i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1746,9 +1710,7 @@ define @vp_bitreverse_nxv1i64_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv1i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv1i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -2032,9 +1994,7 @@ define @vp_bitreverse_nxv2i64_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv2i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv2i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -2318,9 +2278,7 @@ define @vp_bitreverse_nxv4i64_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv4i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv4i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -2678,9 +2636,7 @@ define @vp_bitreverse_nxv7i64_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv7i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv7i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -3038,9 +2994,7 @@ define @vp_bitreverse_nxv8i64_unmasked( %va ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv8i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv8i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -3237,9 +3191,7 @@ define @vp_bitreverse_nxv64i16_unmasked( ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVBB-NEXT: vbrev.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bitreverse.nxv64i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bitreverse.nxv64i16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll index 800dc7ec3885..800d06c5a78f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll @@ -42,9 +42,7 @@ define @vp_bswap_nxv1i16_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv1i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv1i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -82,9 +80,7 @@ define @vp_bswap_nxv2i16_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv2i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv2i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -122,9 +118,7 @@ define @vp_bswap_nxv4i16_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv4i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv4i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -162,9 +156,7 @@ define @vp_bswap_nxv8i16_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv8i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv8i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -202,9 +194,7 @@ define @vp_bswap_nxv16i16_unmasked( %va, ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv16i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv16i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -242,9 +232,7 @@ define @vp_bswap_nxv32i16_unmasked( %va, ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv32i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv32i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -298,9 +286,7 @@ define @vp_bswap_nxv1i32_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv1i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv1i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +340,7 @@ define @vp_bswap_nxv2i32_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv2i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv2i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +394,7 @@ define @vp_bswap_nxv4i32_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv4i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv4i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -466,9 +448,7 @@ define @vp_bswap_nxv8i32_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv8i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv8i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -522,9 +502,7 @@ define @vp_bswap_nxv16i32_unmasked( %va, ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv16i32( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv16i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -694,9 +672,7 @@ define @vp_bswap_nxv1i64_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv1i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv1i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -866,9 +842,7 @@ define @vp_bswap_nxv2i64_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv2i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv2i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1038,9 +1012,7 @@ define @vp_bswap_nxv4i64_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv4i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv4i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1283,9 +1255,7 @@ define @vp_bswap_nxv7i64_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv7i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv7i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1528,9 +1498,7 @@ define @vp_bswap_nxv8i64_unmasked( %va, i32 ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv8i64( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv8i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1655,9 +1623,7 @@ define @vp_bswap_nxv64i16_unmasked( %va, ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVKB-NEXT: vrev8.v v8, v8 ; CHECK-ZVKB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.bswap.nxv64i16( %va, %m, i32 %evl) + %v = call @llvm.vp.bswap.nxv64i16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll index edc348ebc68f..5b271606f08a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll @@ -42,9 +42,7 @@ define @vp_ceil_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -86,9 +84,7 @@ define @vp_ceil_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -130,9 +126,7 @@ define @vp_ceil_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -176,9 +170,7 @@ define @vp_ceil_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +214,7 @@ define @vp_ceil_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -268,9 +258,7 @@ define @vp_ceil_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -312,9 +300,7 @@ define @vp_ceil_vv_nxv1f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -356,9 +342,7 @@ define @vp_ceil_vv_nxv2f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -402,9 +386,7 @@ define @vp_ceil_vv_nxv4f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -448,9 +430,7 @@ define @vp_ceil_vv_nxv8f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -494,9 +474,7 @@ define @vp_ceil_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -538,9 +516,7 @@ define @vp_ceil_vv_nxv1f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -584,9 +560,7 @@ define @vp_ceil_vv_nxv2f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -630,9 +604,7 @@ define @vp_ceil_vv_nxv4f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -676,9 +648,7 @@ define @vp_ceil_vv_nxv7f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -722,9 +692,7 @@ define @vp_ceil_vv_nxv8f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -837,8 +805,6 @@ define @vp_ceil_vv_nxv16f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ceil.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.ceil.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll b/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll index 7831512c658e..4c40b7c74451 100644 --- a/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll @@ -9,9 +9,7 @@ define @not_icmp_sle_nxv8i16( %a, %a, %b - %tmp = insertelement poison, i1 true, i32 0 - %ones = shufflevector %tmp, poison, zeroinitializer - %not = xor %ones, %icmp + %not = xor splat (i1 true), %icmp ret %not } @@ -22,9 +20,7 @@ define @not_icmp_sgt_nxv4i32( %a, %a, %b - %tmp = insertelement poison, i1 true, i32 0 - %ones = shufflevector %tmp, poison, zeroinitializer - %not = xor %icmp, %ones + %not = xor %icmp, splat (i1 true) ret %not } @@ -35,9 +31,7 @@ define @not_fcmp_une_nxv2f64( %a, %a, %b - %tmp = insertelement poison, i1 true, i32 0 - %ones = shufflevector %tmp, poison, zeroinitializer - %not = xor %icmp, %ones + %not = xor %icmp, splat (i1 true) ret %not } @@ -48,8 +42,6 @@ define @not_fcmp_uge_nxv4f32( %a, %a, %b - %tmp = insertelement poison, i1 true, i32 0 - %ones = shufflevector %tmp, poison, zeroinitializer - %not = xor %icmp, %ones + %not = xor %icmp, splat (i1 true) ret %not } diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll b/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll index 46bedcd4e966..8f917becafec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-sats.ll @@ -25,12 +25,8 @@ define @add_umax_nxv2i64( %a0) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i64 7, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i64 -7, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = call @llvm.umax.nxv2i64( %a0, %splat1) - %v2 = add %v1, %splat2 + %v1 = call @llvm.umax.nxv2i64( %a0, splat (i64 7)) + %v2 = add %v1, splat (i64 -7) ret %v2 } @@ -162,12 +158,8 @@ define @vselect_add_const_nxv2i64( %a0) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %cm1 = insertelement poison, i64 -6, i32 0 - %splatcm1 = shufflevector %cm1, poison, zeroinitializer - %nc = insertelement poison, i64 5, i32 0 - %splatnc = shufflevector %nc, poison, zeroinitializer - %v1 = add %a0, %splatcm1 - %cmp = icmp ugt %a0, %splatnc + %v1 = add %a0, splat (i64 -6) + %cmp = icmp ugt %a0, splat (i64 5) %v2 = select %cmp, %v1, zeroinitializer ret %v2 } @@ -194,12 +186,8 @@ define @vselect_add_const_signbit_nxv2i16( ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %cm1 = insertelement poison, i16 32766, i32 0 - %splatcm1 = shufflevector %cm1, poison, zeroinitializer - %nc = insertelement poison, i16 -32767, i32 0 - %splatnc = shufflevector %nc, poison, zeroinitializer - %cmp = icmp ugt %a0, %splatcm1 - %v1 = add %a0, %splatnc + %cmp = icmp ugt %a0, splat (i16 32766) + %v1 = add %a0, splat (i16 -32767) %v2 = select %cmp, %v1, zeroinitializer ret %v2 } @@ -227,9 +215,7 @@ define @vselect_xor_const_signbit_nxv2i16( ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret %cmp = icmp slt %a0, zeroinitializer - %ins = insertelement poison, i16 -32768, i32 0 - %splat = shufflevector %ins, poison, zeroinitializer - %v1 = xor %a0, %splat + %v1 = xor %a0, splat (i16 -32768) %v2 = select %cmp, %v1, zeroinitializer ret %v2 } @@ -259,9 +245,7 @@ define @vselect_add_nxv2i64( %a0, %a0, %a1 %cmp = icmp ule %a0, %v1 - %allones = insertelement poison, i64 -1, i32 0 - %splatallones = shufflevector %allones, poison, zeroinitializer - %v2 = select %cmp, %v1, %splatallones + %v2 = select %cmp, %v1, splat (i64 -1) ret %v2 } @@ -286,15 +270,9 @@ define @vselect_add_const_2_nxv2i64( %a0) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 6 ; CHECK-NEXT: ret - %cm1 = insertelement poison, i64 6, i32 0 - %splatcm1 = shufflevector %cm1, poison, zeroinitializer - %nc = insertelement poison, i64 -7, i32 0 - %splatnc = shufflevector %nc, poison, zeroinitializer - %v1 = add %a0, %splatcm1 - %cmp = icmp ule %a0, %splatnc - %allones = insertelement poison, i64 -1, i32 0 - %splatallones = shufflevector %allones, poison, zeroinitializer - %v2 = select %cmp, %v1, %splatallones + %v1 = add %a0, splat (i64 6) + %cmp = icmp ule %a0, splat (i64 -7) + %v2 = select %cmp, %v1, splat (i64 -1) ret %v2 } diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll index 80b6c8ced3a4..5a67d0fbebf3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll +++ b/llvm/test/CodeGen/RISCV/rvv/combine-splats.ll @@ -10,12 +10,8 @@ define @and_or_nxv4i32( %A) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 8 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i32 255, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i32 8, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = or %A, %splat1 - %v2 = and %v1, %splat2 + %v1 = or %A, splat (i32 255) + %v2 = and %v1, splat (i32 8) ret %v2 } @@ -28,12 +24,8 @@ define @or_and_nxv2i64( %a0) { ; CHECK-NEXT: vor.vi v8, v8, 3 ; CHECK-NEXT: vand.vi v8, v8, 7 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i64 7, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i64 3, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = and %a0, %splat1 - %v2 = or %v1, %splat2 + %v1 = and %a0, splat (i64 7) + %v2 = or %v1, splat (i64 3) ret %v2 } @@ -45,12 +37,8 @@ define @or_and_nxv2i64_fold( %a0) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 3 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i64 1, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i64 3, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = and %a0, %splat1 - %v2 = or %v1, %splat2 + %v1 = and %a0, splat (i64 1) + %v2 = or %v1, splat (i64 3) ret %v2 } @@ -62,12 +50,8 @@ define @combine_vec_shl_shl( %x) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i32 2, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i32 4, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = shl %x, %splat1 - %v2 = shl %v1, %splat2 + %v1 = shl %x, splat (i32 2) + %v2 = shl %v1, splat (i32 4) ret %v2 } @@ -79,12 +63,8 @@ define @combine_vec_ashr_ashr( %x) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i32 2, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i32 4, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = ashr %x, %splat1 - %v2 = ashr %v1, %splat2 + %v1 = ashr %x, splat (i32 2) + %v2 = ashr %v1, splat (i32 4) ret %v2 } @@ -96,12 +76,8 @@ define @combine_vec_lshr_lshr( %x) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %ins1 = insertelement poison, i16 2, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %ins2 = insertelement poison, i16 4, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %v1 = lshr %x, %splat2 - %v2 = lshr %v1, %splat2 + %v1 = lshr %x, splat (i16 4) + %v2 = lshr %v1, splat (i16 4) ret %v2 } @@ -110,9 +86,7 @@ define @combine_fmul_one( %x) { ; CHECK-LABEL: combine_fmul_one: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %ins = insertelement poison, float 1.0, i32 0 - %splat = shufflevector %ins, poison, zeroinitializer - %v = fmul %x, %splat + %v = fmul %x, splat (float 1.0) ret %v } @@ -121,8 +95,6 @@ define @combine_fmul_one_commuted( %x) ; CHECK-LABEL: combine_fmul_one_commuted: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %ins = insertelement poison, float 1.0, i32 0 - %splat = shufflevector %ins, poison, zeroinitializer - %v = fmul %splat, %x + %v = fmul splat (float 1.0), %x ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll index b3f561a52f41..05747ff0d049 100644 --- a/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll +++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding.ll @@ -21,9 +21,7 @@ define <2 x i16> @fixedlen(<2 x i32> %x) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret - %v41 = insertelement <2 x i32> poison, i32 16, i32 0 - %v42 = shufflevector <2 x i32> %v41, <2 x i32> poison, <2 x i32> zeroinitializer - %v43 = lshr <2 x i32> %x, %v42 + %v43 = lshr <2 x i32> %x, splat (i32 16) %v44 = trunc <2 x i32> %v43 to <2 x i16> %v45 = insertelement <2 x i32> poison, i32 -32768, i32 0 %v46 = shufflevector <2 x i32> %v45, <2 x i32> poison, <2 x i32> zeroinitializer @@ -40,9 +38,7 @@ define @scalable( %x) { ; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %v41 = insertelement poison, i32 16, i32 0 - %v42 = shufflevector %v41, poison, zeroinitializer - %v43 = lshr %x, %v42 + %v43 = lshr %x, splat (i32 16) %v44 = trunc %v43 to %v45 = insertelement poison, i32 -32768, i32 0 %v46 = shufflevector %v45, poison, zeroinitializer diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll index e4f030a642f7..2a75e5ce7175 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll @@ -57,9 +57,7 @@ define @vp_ctlz_nxv1i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -112,9 +110,7 @@ define @vp_ctlz_nxv2i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -167,9 +163,7 @@ define @vp_ctlz_nxv4i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +216,7 @@ define @vp_ctlz_nxv8i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -277,9 +269,7 @@ define @vp_ctlz_nxv16i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -349,9 +339,7 @@ define @vp_ctlz_nxv32i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -421,9 +409,7 @@ define @vp_ctlz_nxv64i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -470,9 +456,7 @@ define @vp_ctlz_nxv1i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -519,9 +503,7 @@ define @vp_ctlz_nxv2i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -568,9 +550,7 @@ define @vp_ctlz_nxv4i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -617,9 +597,7 @@ define @vp_ctlz_nxv8i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -666,9 +644,7 @@ define @vp_ctlz_nxv16i16_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -756,9 +732,7 @@ define @vp_ctlz_nxv32i16_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -807,9 +781,7 @@ define @vp_ctlz_nxv1i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -858,9 +830,7 @@ define @vp_ctlz_nxv2i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -909,9 +879,7 @@ define @vp_ctlz_nxv4i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -960,9 +928,7 @@ define @vp_ctlz_nxv8i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1010,9 +976,7 @@ define @vp_ctlz_nxv16i32_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1062,9 +1026,7 @@ define @vp_ctlz_nxv1i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1114,9 +1076,7 @@ define @vp_ctlz_nxv2i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1166,9 +1126,7 @@ define @vp_ctlz_nxv4i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1218,9 +1176,7 @@ define @vp_ctlz_nxv7i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1270,9 +1226,7 @@ define @vp_ctlz_nxv8i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1386,9 +1340,7 @@ define @vp_ctlz_nxv16i64_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1435,9 +1387,7 @@ define @vp_ctlz_zero_undef_nxv1i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1485,9 +1435,7 @@ define @vp_ctlz_zero_undef_nxv2i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1535,9 +1483,7 @@ define @vp_ctlz_zero_undef_nxv4i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1585,9 +1531,7 @@ define @vp_ctlz_zero_undef_nxv8i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vclz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1635,9 +1579,7 @@ define @vp_ctlz_zero_undef_nxv16i8_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1706,9 +1648,7 @@ define @vp_ctlz_zero_undef_nxv32i8_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1777,9 +1717,7 @@ define @vp_ctlz_zero_undef_nxv64i8_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1821,9 +1759,7 @@ define @vp_ctlz_zero_undef_nxv1i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1865,9 +1801,7 @@ define @vp_ctlz_zero_undef_nxv2i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1909,9 +1843,7 @@ define @vp_ctlz_zero_undef_nxv4i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1953,9 +1885,7 @@ define @vp_ctlz_zero_undef_nxv8i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -1997,9 +1927,7 @@ define @vp_ctlz_zero_undef_nxv16i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2086,9 +2014,7 @@ define @vp_ctlz_zero_undef_nxv32i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2132,9 +2058,7 @@ define @vp_ctlz_zero_undef_nxv1i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2178,9 +2102,7 @@ define @vp_ctlz_zero_undef_nxv2i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2224,9 +2146,7 @@ define @vp_ctlz_zero_undef_nxv4i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2270,9 +2190,7 @@ define @vp_ctlz_zero_undef_nxv8i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2315,9 +2233,7 @@ define @vp_ctlz_zero_undef_nxv16i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2362,9 +2278,7 @@ define @vp_ctlz_zero_undef_nxv1i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2409,9 +2323,7 @@ define @vp_ctlz_zero_undef_nxv2i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2456,9 +2368,7 @@ define @vp_ctlz_zero_undef_nxv4i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2503,9 +2413,7 @@ define @vp_ctlz_zero_undef_nxv7i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2550,9 +2458,7 @@ define @vp_ctlz_zero_undef_nxv8i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2658,9 +2564,7 @@ define @vp_ctlz_zero_undef_nxv16i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll index 2310f85b1fba..883f68aec1f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll @@ -60,9 +60,7 @@ define @vp_ctpop_nxv1i8_unmasked( %va, i32 ze ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv1i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv1i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -118,9 +116,7 @@ define @vp_ctpop_nxv2i8_unmasked( %va, i32 ze ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv2i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv2i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -176,9 +172,7 @@ define @vp_ctpop_nxv4i8_unmasked( %va, i32 ze ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv4i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv4i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -234,9 +228,7 @@ define @vp_ctpop_nxv8i8_unmasked( %va, i32 ze ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv8i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv8i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -292,9 +284,7 @@ define @vp_ctpop_nxv16i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv16i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv16i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -350,9 +340,7 @@ define @vp_ctpop_nxv32i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv32i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv32i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -408,9 +396,7 @@ define @vp_ctpop_nxv64i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv64i8( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv64i8( %va, splat (i1 true), i32 %evl) ret %v } @@ -480,9 +466,7 @@ define @vp_ctpop_nxv1i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv1i16( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv1i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -552,9 +536,7 @@ define @vp_ctpop_nxv2i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv2i16( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv2i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -624,9 +606,7 @@ define @vp_ctpop_nxv4i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv4i16( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv4i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -696,9 +676,7 @@ define @vp_ctpop_nxv8i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv8i16( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv8i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -768,9 +746,7 @@ define @vp_ctpop_nxv16i16_unmasked( %va, ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv16i16( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv16i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -840,9 +816,7 @@ define @vp_ctpop_nxv32i16_unmasked( %va, ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv32i16( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv32i16( %va, splat (i1 true), i32 %evl) ret %v } @@ -914,9 +888,7 @@ define @vp_ctpop_nxv1i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv1i32( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv1i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -988,9 +960,7 @@ define @vp_ctpop_nxv2i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv2i32( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv2i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1062,9 +1032,7 @@ define @vp_ctpop_nxv4i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv4i32( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv4i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1136,9 +1104,7 @@ define @vp_ctpop_nxv8i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv8i32( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv8i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1210,9 +1176,7 @@ define @vp_ctpop_nxv16i32_unmasked( %va, ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv16i32( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv16i32( %va, splat (i1 true), i32 %evl) ret %v } @@ -1378,9 +1342,7 @@ define @vp_ctpop_nxv1i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv1i64( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv1i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1546,9 +1508,7 @@ define @vp_ctpop_nxv2i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv2i64( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv2i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1714,9 +1674,7 @@ define @vp_ctpop_nxv4i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv4i64( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv4i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1882,9 +1840,7 @@ define @vp_ctpop_nxv7i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv7i64( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv7i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -2050,9 +2006,7 @@ define @vp_ctpop_nxv8i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv8i64( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv8i64( %va, splat (i1 true), i32 %evl) ret %v } @@ -2581,9 +2535,7 @@ define @vp_ctpop_nxv16i64_unmasked( %va, ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vcpop.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctpop.nxv16i64( %va, %m, i32 %evl) + %v = call @llvm.vp.ctpop.nxv16i64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll index 145ce6e917f9..ef8a6c704a44 100644 --- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll @@ -68,9 +68,7 @@ define @vp_cttz_nxv1i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -134,9 +132,7 @@ define @vp_cttz_nxv2i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -200,9 +196,7 @@ define @vp_cttz_nxv4i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -266,9 +260,7 @@ define @vp_cttz_nxv8i8_unmasked( %va, i32 zer ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -332,9 +324,7 @@ define @vp_cttz_nxv16i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -398,9 +388,7 @@ define @vp_cttz_nxv32i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv32i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -464,9 +452,7 @@ define @vp_cttz_nxv64i8_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv64i8( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv64i8( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -544,9 +530,7 @@ define @vp_cttz_nxv1i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -624,9 +608,7 @@ define @vp_cttz_nxv2i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -704,9 +686,7 @@ define @vp_cttz_nxv4i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -784,9 +764,7 @@ define @vp_cttz_nxv8i16_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -864,9 +842,7 @@ define @vp_cttz_nxv16i16_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -944,9 +920,7 @@ define @vp_cttz_nxv32i16_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i16( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv32i16( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +1000,7 @@ define @vp_cttz_nxv1i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1108,9 +1080,7 @@ define @vp_cttz_nxv2i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1190,9 +1160,7 @@ define @vp_cttz_nxv4i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1272,9 +1240,7 @@ define @vp_cttz_nxv8i32_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1354,9 +1320,7 @@ define @vp_cttz_nxv16i32_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i32( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i32( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1538,9 +1502,7 @@ define @vp_cttz_nxv1i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1722,9 +1684,7 @@ define @vp_cttz_nxv2i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -1906,9 +1866,7 @@ define @vp_cttz_nxv4i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -2090,9 +2048,7 @@ define @vp_cttz_nxv7i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv7i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv7i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -2274,9 +2230,7 @@ define @vp_cttz_nxv8i64_unmasked( %va, i32 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -2855,9 +2809,7 @@ define @vp_cttz_nxv16i64_unmasked( %va, i ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i64( %va, i1 false, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i64( %va, i1 false, splat (i1 true), i32 %evl) ret %v } @@ -2910,9 +2862,7 @@ define @vp_cttz_zero_undef_nxv1i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -2966,9 +2916,7 @@ define @vp_cttz_zero_undef_nxv2i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3022,9 +2970,7 @@ define @vp_cttz_zero_undef_nxv4i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3078,9 +3024,7 @@ define @vp_cttz_zero_undef_nxv8i8_unmasked( % ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vctz.v v8, v8 ; CHECK-ZVBB-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3134,9 +3078,7 @@ define @vp_cttz_zero_undef_nxv16i8_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3199,9 +3141,7 @@ define @vp_cttz_zero_undef_nxv32i8_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv32i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3264,9 +3204,7 @@ define @vp_cttz_zero_undef_nxv64i8_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv64i8( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv64i8( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3312,9 +3250,7 @@ define @vp_cttz_zero_undef_nxv1i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3360,9 +3296,7 @@ define @vp_cttz_zero_undef_nxv2i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3408,9 +3342,7 @@ define @vp_cttz_zero_undef_nxv4i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3456,9 +3388,7 @@ define @vp_cttz_zero_undef_nxv8i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3504,9 +3434,7 @@ define @vp_cttz_zero_undef_nxv16i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3583,9 +3511,7 @@ define @vp_cttz_zero_undef_nxv32i16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i16( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv32i16( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3633,9 +3559,7 @@ define @vp_cttz_zero_undef_nxv1i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3683,9 +3607,7 @@ define @vp_cttz_zero_undef_nxv2i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3733,9 +3655,7 @@ define @vp_cttz_zero_undef_nxv4i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3783,9 +3703,7 @@ define @vp_cttz_zero_undef_nxv8i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3832,9 +3750,7 @@ define @vp_cttz_zero_undef_nxv16i32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i32( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i32( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3883,9 +3799,7 @@ define @vp_cttz_zero_undef_nxv1i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv1i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3934,9 +3848,7 @@ define @vp_cttz_zero_undef_nxv2i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv2i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -3985,9 +3897,7 @@ define @vp_cttz_zero_undef_nxv4i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv4i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -4036,9 +3946,7 @@ define @vp_cttz_zero_undef_nxv7i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv7i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv7i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -4087,9 +3995,7 @@ define @vp_cttz_zero_undef_nxv8i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv8i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } @@ -4227,9 +4133,7 @@ define @vp_cttz_zero_undef_nxv16i64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i64( %va, i1 true, %m, i32 %evl) + %v = call @llvm.vp.cttz.nxv16i64( %va, i1 true, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll index f1ac9aa53f57..3b7952f9f5e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll @@ -523,9 +523,7 @@ define float @extractelt_fadd_nxv4f32_splat( %x) { ; CHECK-NEXT: fmv.w.x fa4, a0 ; CHECK-NEXT: fadd.s fa0, fa5, fa4 ; CHECK-NEXT: ret - %head = insertelement poison, float 3.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = fadd %x, %splat + %bo = fadd %x, splat (float 3.0) %ext = extractelement %bo, i32 2 ret float %ext } @@ -540,9 +538,7 @@ define float @extractelt_fsub_nxv4f32_splat( %x) { ; CHECK-NEXT: fmv.w.x fa4, a0 ; CHECK-NEXT: fsub.s fa0, fa4, fa5 ; CHECK-NEXT: ret - %head = insertelement poison, float 3.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = fsub %splat, %x + %bo = fsub splat (float 3.0), %x %ext = extractelement %bo, i32 1 ret float %ext } @@ -557,9 +553,7 @@ define float @extractelt_fmul_nxv4f32_splat( %x) { ; CHECK-NEXT: fmv.w.x fa4, a0 ; CHECK-NEXT: fmul.s fa0, fa5, fa4 ; CHECK-NEXT: ret - %head = insertelement poison, float 3.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = fmul %x, %splat + %bo = fmul %x, splat (float 3.0) %ext = extractelement %bo, i32 3 ret float %ext } @@ -573,9 +567,7 @@ define float @extractelt_fdiv_nxv4f32_splat( %x) { ; CHECK-NEXT: fmv.w.x fa4, a0 ; CHECK-NEXT: fdiv.s fa0, fa5, fa4 ; CHECK-NEXT: ret - %head = insertelement poison, float 3.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = fdiv %x, %splat + %bo = fdiv %x, splat (float 3.0) %ext = extractelement %bo, i32 0 ret float %ext } diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll index d9fdec3041cb..df9949e617b8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll @@ -753,9 +753,7 @@ define i32 @extractelt_add_nxv4i32_splat( %x) { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addi a0, a0, 3 ; CHECK-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = add %x, %splat + %bo = add %x, splat (i32 3) %ext = extractelement %bo, i32 2 ret i32 %ext } @@ -769,9 +767,7 @@ define i32 @extractelt_sub_nxv4i32_splat( %x) { ; CHECK-NEXT: li a1, 3 ; CHECK-NEXT: sub a0, a1, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = sub %splat, %x + %bo = sub splat (i32 3), %x %ext = extractelement %bo, i32 1 ret i32 %ext } @@ -795,9 +791,7 @@ define i32 @extractelt_mul_nxv4i32_splat( %x) { ; RV32M-NEXT: slli a1, a0, 1 ; RV32M-NEXT: add a0, a1, a0 ; RV32M-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = mul %x, %splat + %bo = mul %x, splat (i32 3) %ext = extractelement %bo, i32 3 ret i32 %ext } @@ -824,9 +818,7 @@ define i32 @extractelt_sdiv_nxv4i32_splat( %x) { ; RV32M-NEXT: srli a1, a0, 31 ; RV32M-NEXT: add a0, a0, a1 ; RV32M-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = sdiv %x, %splat + %bo = sdiv %x, splat (i32 3) %ext = extractelement %bo, i32 0 ret i32 %ext } @@ -853,9 +845,7 @@ define i32 @extractelt_udiv_nxv4i32_splat( %x) { ; RV32M-NEXT: srli a1, a0, 31 ; RV32M-NEXT: add a0, a0, a1 ; RV32M-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = sdiv %x, %splat + %bo = sdiv %x, splat (i32 3) %ext = extractelement %bo, i32 0 ret i32 %ext } diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll index fcee77ae8d8e..a96cf5807e6c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll @@ -737,9 +737,7 @@ define i32 @extractelt_add_nxv4i32_splat( %x) { ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: addiw a0, a0, 3 ; CHECK-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = add %x, %splat + %bo = add %x, splat (i32 3) %ext = extractelement %bo, i32 2 ret i32 %ext } @@ -753,9 +751,7 @@ define i32 @extractelt_sub_nxv4i32_splat( %x) { ; CHECK-NEXT: li a1, 3 ; CHECK-NEXT: subw a0, a1, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = sub %splat, %x + %bo = sub splat (i32 3), %x %ext = extractelement %bo, i32 1 ret i32 %ext } @@ -779,9 +775,7 @@ define i32 @extractelt_mul_nxv4i32_splat( %x) { ; RV64M-NEXT: slli a1, a0, 1 ; RV64M-NEXT: addw a0, a1, a0 ; RV64M-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = mul %x, %splat + %bo = mul %x, splat (i32 3) %ext = extractelement %bo, i32 3 ret i32 %ext } @@ -809,9 +803,7 @@ define i32 @extractelt_sdiv_nxv4i32_splat( %x) { ; RV64M-NEXT: srli a0, a0, 32 ; RV64M-NEXT: addw a0, a0, a1 ; RV64M-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = sdiv %x, %splat + %bo = sdiv %x, splat (i32 3) %ext = extractelement %bo, i32 0 ret i32 %ext } @@ -839,9 +831,7 @@ define i32 @extractelt_udiv_nxv4i32_splat( %x) { ; RV64M-NEXT: srli a0, a0, 32 ; RV64M-NEXT: addw a0, a0, a1 ; RV64M-NEXT: ret - %head = insertelement poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %bo = sdiv %x, %splat + %bo = sdiv %x, splat (i32 3) %ext = extractelement %bo, i32 0 ret i32 %ext } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll index c273dcdfbca1..c0d366760d07 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll @@ -24,9 +24,7 @@ define <2 x i8> @vp_abs_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -50,9 +48,7 @@ define <4 x i8> @vp_abs_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -76,9 +72,7 @@ define <8 x i8> @vp_abs_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -102,9 +96,7 @@ define <16 x i8> @vp_abs_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -128,9 +120,7 @@ define <2 x i16> @vp_abs_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -154,9 +144,7 @@ define <4 x i16> @vp_abs_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -180,9 +168,7 @@ define <8 x i16> @vp_abs_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -206,9 +192,7 @@ define <16 x i16> @vp_abs_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -232,9 +216,7 @@ define <2 x i32> @vp_abs_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -258,9 +240,7 @@ define <4 x i32> @vp_abs_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -284,9 +264,7 @@ define <8 x i32> @vp_abs_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -310,9 +288,7 @@ define <16 x i32> @vp_abs_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -336,9 +312,7 @@ define <2 x i64> @vp_abs_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -362,9 +336,7 @@ define <4 x i64> @vp_abs_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -388,9 +360,7 @@ define <8 x i64> @vp_abs_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v12, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -414,9 +384,7 @@ define <15 x i64> @vp_abs_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -440,9 +408,7 @@ define <16 x i64> @vp_abs_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v16, v8, 0 ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -495,8 +461,6 @@ define <32 x i64> @vp_abs_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v24, v16, 0 ; CHECK-NEXT: vmax.vv v16, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll index 595c650ffb82..943fc58d637a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll @@ -54,9 +54,7 @@ define <2 x i8> @vp_bitreverse_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.bitreverse.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.bitreverse.v2i8(<2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -110,9 +108,7 @@ define <4 x i8> @vp_bitreverse_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.bitreverse.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.bitreverse.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -166,9 +162,7 @@ define <8 x i8> @vp_bitreverse_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.bitreverse.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.bitreverse.v8i8(<8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -222,9 +216,7 @@ define <16 x i8> @vp_bitreverse_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.bitreverse.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.bitreverse.v16i8(<16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -292,9 +284,7 @@ define <2 x i16> @vp_bitreverse_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.bitreverse.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.bitreverse.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -362,9 +352,7 @@ define <4 x i16> @vp_bitreverse_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.bitreverse.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.bitreverse.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -432,9 +420,7 @@ define <8 x i16> @vp_bitreverse_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.bitreverse.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.bitreverse.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -502,9 +488,7 @@ define <16 x i16> @vp_bitreverse_v16i16_unmasked(<16 x i16> %va, i32 zeroext %ev ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.bitreverse.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.bitreverse.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -588,9 +572,7 @@ define <2 x i32> @vp_bitreverse_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.bitreverse.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.bitreverse.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -674,9 +656,7 @@ define <4 x i32> @vp_bitreverse_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.bitreverse.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.bitreverse.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -760,9 +740,7 @@ define <8 x i32> @vp_bitreverse_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v10, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.bitreverse.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.bitreverse.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -846,9 +824,7 @@ define <16 x i32> @vp_bitreverse_v16i32_unmasked(<16 x i32> %va, i32 zeroext %ev ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: vor.vv v8, v12, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.bitreverse.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.bitreverse.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1120,9 +1096,7 @@ define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) ; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.bitreverse.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.bitreverse.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1394,9 +1368,7 @@ define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) ; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.bitreverse.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.bitreverse.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1668,9 +1640,7 @@ define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) ; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vor.vv v8, v12, v8 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.bitreverse.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.bitreverse.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -2034,9 +2004,7 @@ define <15 x i64> @vp_bitreverse_v15i64_unmasked(<15 x i64> %va, i32 zeroext %ev ; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -2400,9 +2368,7 @@ define <16 x i64> @vp_bitreverse_v16i64_unmasked(<16 x i64> %va, i32 zeroext %ev ; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -2555,8 +2521,6 @@ define <128 x i16> @vp_bitreverse_v128i16_unmasked(<128 x i16> %va, i32 zeroext ; CHECK-NEXT: vadd.vv v16, v16, v16 ; CHECK-NEXT: vor.vv v16, v24, v16 ; CHECK-NEXT: ret - %head = insertelement <128 x i1> poison, i1 true, i32 0 - %m = shufflevector <128 x i1> %head, <128 x i1> poison, <128 x i32> zeroinitializer - %v = call <128 x i16> @llvm.vp.bitreverse.v128i16(<128 x i16> %va, <128 x i1> %m, i32 %evl) + %v = call <128 x i16> @llvm.vp.bitreverse.v128i16(<128 x i16> %va, <128 x i1> splat (i1 true), i32 %evl) ret <128 x i16> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll index 6308f73e219d..f80d4e5c0d7c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll @@ -26,9 +26,7 @@ define <2 x i16> @vp_bswap_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsll.vi v8, v8, 8 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.bswap.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.bswap.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -54,9 +52,7 @@ define <4 x i16> @vp_bswap_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsll.vi v8, v8, 8 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.bswap.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.bswap.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -82,9 +78,7 @@ define <8 x i16> @vp_bswap_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsll.vi v8, v8, 8 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.bswap.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.bswap.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -110,9 +104,7 @@ define <16 x i16> @vp_bswap_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsll.vi v8, v8, 8 ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.bswap.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.bswap.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -154,9 +146,7 @@ define <2 x i32> @vp_bswap_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.bswap.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.bswap.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -198,9 +188,7 @@ define <4 x i32> @vp_bswap_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.bswap.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.bswap.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -242,9 +230,7 @@ define <8 x i32> @vp_bswap_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.bswap.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.bswap.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -286,9 +272,7 @@ define <16 x i32> @vp_bswap_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.bswap.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.bswap.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -446,9 +430,7 @@ define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.bswap.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -606,9 +588,7 @@ define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.bswap.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -766,9 +746,7 @@ define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v12, v8 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.bswap.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -999,9 +977,7 @@ define <15 x i64> @vp_bswap_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -1232,9 +1208,7 @@ define <16 x i64> @vp_bswap_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1315,8 +1289,6 @@ define <128 x i16> @vp_bswap_v128i16_unmasked(<128 x i16> %va, i32 zeroext %evl) ; CHECK-NEXT: vsll.vi v16, v16, 8 ; CHECK-NEXT: vor.vv v16, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <128 x i1> poison, i1 true, i32 0 - %m = shufflevector <128 x i1> %head, <128 x i1> poison, <128 x i32> zeroinitializer - %v = call <128 x i16> @llvm.vp.bswap.v128i16(<128 x i16> %va, <128 x i1> %m, i32 %evl) + %v = call <128 x i16> @llvm.vp.bswap.v128i16(<128 x i16> %va, <128 x i1> splat (i1 true), i32 %evl) ret <128 x i16> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll index 194179f9f470..5d024f140fd5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll @@ -86,9 +86,7 @@ define <2 x half> @vp_ceil_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.ceil.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.ceil.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -170,9 +168,7 @@ define <4 x half> @vp_ceil_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.ceil.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.ceil.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -256,9 +252,7 @@ define <8 x half> @vp_ceil_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.ceil.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.ceil.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -344,9 +338,7 @@ define <16 x half> @vp_ceil_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.ceil.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.ceil.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -388,9 +380,7 @@ define <2 x float> @vp_ceil_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.ceil.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.ceil.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -432,9 +422,7 @@ define <4 x float> @vp_ceil_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.ceil.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.ceil.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -478,9 +466,7 @@ define <8 x float> @vp_ceil_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.ceil.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.ceil.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -524,9 +510,7 @@ define <16 x float> @vp_ceil_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.ceil.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.ceil.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -568,9 +552,7 @@ define <2 x double> @vp_ceil_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.ceil.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.ceil.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -614,9 +596,7 @@ define <4 x double> @vp_ceil_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.ceil.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.ceil.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -660,9 +640,7 @@ define <8 x double> @vp_ceil_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.ceil.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.ceil.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -706,9 +684,7 @@ define <15 x double> @vp_ceil_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.ceil.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.ceil.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -752,9 +728,7 @@ define <16 x double> @vp_ceil_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.ceil.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.ceil.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -867,8 +841,6 @@ define <32 x double> @vp_ceil_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.ceil.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.ceil.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll index 36f22bd3259c..2f4539d5038c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll @@ -58,9 +58,7 @@ define <2 x i8> @vp_ctlz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -118,9 +116,7 @@ define <4 x i8> @vp_ctlz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -178,9 +174,7 @@ define <8 x i8> @vp_ctlz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -238,9 +232,7 @@ define <16 x i8> @vp_ctlz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -316,9 +308,7 @@ define <2 x i16> @vp_ctlz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -394,9 +384,7 @@ define <4 x i16> @vp_ctlz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -472,9 +460,7 @@ define <8 x i16> @vp_ctlz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -550,9 +536,7 @@ define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -634,9 +618,7 @@ define <2 x i32> @vp_ctlz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -718,9 +700,7 @@ define <4 x i32> @vp_ctlz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -802,9 +782,7 @@ define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -886,9 +864,7 @@ define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1098,9 +1074,7 @@ define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1310,9 +1284,7 @@ define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1522,9 +1494,7 @@ define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1764,9 +1734,7 @@ define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -2006,9 +1974,7 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -2623,9 +2589,7 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v16, v16, a5 ; RV64-NEXT: vsrl.vx v16, v16, a6 ; RV64-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } @@ -2681,9 +2645,7 @@ define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -2739,9 +2701,7 @@ define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -2797,9 +2757,7 @@ define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -2855,9 +2813,7 @@ define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext % ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -2931,9 +2887,7 @@ define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -3007,9 +2961,7 @@ define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -3083,9 +3035,7 @@ define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -3159,9 +3109,7 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -3241,9 +3189,7 @@ define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -3323,9 +3269,7 @@ define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -3405,9 +3349,7 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -3487,9 +3429,7 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -3697,9 +3637,7 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext % ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -3907,9 +3845,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext % ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -4117,9 +4053,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext % ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -4357,9 +4291,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -4597,9 +4529,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -5212,8 +5142,6 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex ; RV64-NEXT: vmul.vx v16, v16, a5 ; RV64-NEXT: vsrl.vx v16, v16, a6 ; RV64-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll index c4b22955f84c..0b6d8b33394d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll @@ -44,9 +44,7 @@ define <2 x i8> @vp_ctpop_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ctpop.v2i8(<2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -90,9 +88,7 @@ define <4 x i8> @vp_ctpop_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ctpop.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ctpop.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -136,9 +132,7 @@ define <8 x i8> @vp_ctpop_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ctpop.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ctpop.v8i8(<8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -182,9 +176,7 @@ define <16 x i8> @vp_ctpop_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ctpop.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ctpop.v16i8(<16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -242,9 +234,7 @@ define <2 x i16> @vp_ctpop_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ctpop.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ctpop.v2i16(<2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -302,9 +292,7 @@ define <4 x i16> @vp_ctpop_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ctpop.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ctpop.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -362,9 +350,7 @@ define <8 x i16> @vp_ctpop_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ctpop.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ctpop.v8i16(<8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -422,9 +408,7 @@ define <16 x i16> @vp_ctpop_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ctpop.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ctpop.v16i16(<16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -484,9 +468,7 @@ define <2 x i32> @vp_ctpop_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ctpop.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ctpop.v2i32(<2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -546,9 +528,7 @@ define <4 x i32> @vp_ctpop_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ctpop.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -608,9 +588,7 @@ define <8 x i32> @vp_ctpop_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ctpop.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ctpop.v8i32(<8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -670,9 +648,7 @@ define <16 x i32> @vp_ctpop_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ctpop.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ctpop.v16i32(<16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -826,9 +802,7 @@ define <2 x i64> @vp_ctpop_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ctpop.v2i64(<2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -982,9 +956,7 @@ define <4 x i64> @vp_ctpop_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ctpop.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1138,9 +1110,7 @@ define <8 x i64> @vp_ctpop_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ctpop.v8i64(<8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1324,9 +1294,7 @@ define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -1510,9 +1478,7 @@ define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1962,8 +1928,6 @@ define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v16, v16, a4 ; RV64-NEXT: vsrl.vx v16, v16, a5 ; RV64-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll index 49f6ffd69129..f2926fa91e5c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll @@ -52,9 +52,7 @@ define <2 x i8> @vp_cttz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -106,9 +104,7 @@ define <4 x i8> @vp_cttz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -160,9 +156,7 @@ define <8 x i8> @vp_cttz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -214,9 +208,7 @@ define <16 x i8> @vp_cttz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -282,9 +274,7 @@ define <2 x i16> @vp_cttz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -350,9 +340,7 @@ define <4 x i16> @vp_cttz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -418,9 +406,7 @@ define <8 x i16> @vp_cttz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -486,9 +472,7 @@ define <16 x i16> @vp_cttz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -556,9 +540,7 @@ define <2 x i32> @vp_cttz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -626,9 +608,7 @@ define <4 x i32> @vp_cttz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -696,9 +676,7 @@ define <8 x i32> @vp_cttz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -766,9 +744,7 @@ define <16 x i32> @vp_cttz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -938,9 +914,7 @@ define <2 x i64> @vp_cttz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1110,9 +1084,7 @@ define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1282,9 +1254,7 @@ define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1484,9 +1454,7 @@ define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -1686,9 +1654,7 @@ define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -2223,9 +2189,7 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v16, v16, a5 ; RV64-NEXT: vsrl.vx v16, v16, a6 ; RV64-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } @@ -2275,9 +2239,7 @@ define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -2327,9 +2289,7 @@ define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -2379,9 +2339,7 @@ define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -2431,9 +2389,7 @@ define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext % ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -2497,9 +2453,7 @@ define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -2563,9 +2517,7 @@ define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -2629,9 +2581,7 @@ define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -2695,9 +2645,7 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -2763,9 +2711,7 @@ define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -2831,9 +2777,7 @@ define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -2899,9 +2843,7 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext % ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -2967,9 +2909,7 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -3137,9 +3077,7 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext % ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -3307,9 +3245,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext % ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -3477,9 +3413,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext % ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -3677,9 +3611,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl) + %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> splat (i1 true), i32 %evl) ret <15 x i64> %v } @@ -3877,9 +3809,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0 ; RV64-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -4412,8 +4342,6 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex ; RV64-NEXT: vmul.vx v16, v16, a5 ; RV64-NEXT: vsrl.vx v16, v16, a6 ; RV64-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll index 583742224f8c..6c2be509f7c2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll @@ -86,9 +86,7 @@ define <2 x half> @vp_floor_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.floor.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.floor.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -170,9 +168,7 @@ define <4 x half> @vp_floor_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.floor.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.floor.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -256,9 +252,7 @@ define <8 x half> @vp_floor_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.floor.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.floor.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -344,9 +338,7 @@ define <16 x half> @vp_floor_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.floor.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.floor.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -388,9 +380,7 @@ define <2 x float> @vp_floor_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.floor.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.floor.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -432,9 +422,7 @@ define <4 x float> @vp_floor_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.floor.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.floor.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -478,9 +466,7 @@ define <8 x float> @vp_floor_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.floor.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.floor.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -524,9 +510,7 @@ define <16 x float> @vp_floor_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.floor.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.floor.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -568,9 +552,7 @@ define <2 x double> @vp_floor_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.floor.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.floor.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -614,9 +596,7 @@ define <4 x double> @vp_floor_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.floor.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.floor.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -660,9 +640,7 @@ define <8 x double> @vp_floor_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.floor.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.floor.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -706,9 +684,7 @@ define <15 x double> @vp_floor_v15f64_unmasked(<15 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.floor.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.floor.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -752,9 +728,7 @@ define <16 x double> @vp_floor_v16f64_unmasked(<16 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.floor.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.floor.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -867,8 +841,6 @@ define <32 x double> @vp_floor_v32f64_unmasked(<32 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.floor.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.floor.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll index 3b7480117d37..edb33158e32e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll @@ -76,9 +76,7 @@ define <2 x half> @vfmax_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.maximum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.maximum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -150,9 +148,7 @@ define <4 x half> @vfmax_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.maximum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.maximum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -226,9 +222,7 @@ define <8 x half> @vfmax_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.maximum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.maximum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -304,9 +298,7 @@ define <16 x half> @vfmax_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.maximum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.maximum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -340,9 +332,7 @@ define <2 x float> @vfmax_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i3 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.maximum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.maximum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -376,9 +366,7 @@ define <4 x float> @vfmax_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i3 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.maximum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.maximum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -414,9 +402,7 @@ define <8 x float> @vfmax_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i3 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.maximum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.maximum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -452,9 +438,7 @@ define <16 x float> @vfmax_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.maximum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.maximum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -488,9 +472,7 @@ define <2 x double> @vfmax_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.maximum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.maximum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -526,9 +508,7 @@ define <4 x double> @vfmax_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.maximum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.maximum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -564,9 +544,7 @@ define <8 x double> @vfmax_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.maximum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.maximum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -615,9 +593,7 @@ define <16 x double> @vfmax_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.maximum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.maximum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -808,8 +784,6 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double> ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.maximum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.maximum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll index 57275df57a31..48649c43f782 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll @@ -76,9 +76,7 @@ define <2 x half> @vfmin_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.minimum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.minimum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -150,9 +148,7 @@ define <4 x half> @vfmin_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.minimum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.minimum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -226,9 +222,7 @@ define <8 x half> @vfmin_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.minimum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.minimum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -304,9 +298,7 @@ define <16 x half> @vfmin_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.minimum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.minimum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -340,9 +332,7 @@ define <2 x float> @vfmin_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i3 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.minimum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.minimum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -376,9 +366,7 @@ define <4 x float> @vfmin_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i3 ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.minimum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.minimum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -414,9 +402,7 @@ define <8 x float> @vfmin_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i3 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.minimum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.minimum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -452,9 +438,7 @@ define <16 x float> @vfmin_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.minimum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.minimum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -488,9 +472,7 @@ define <2 x double> @vfmin_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.minimum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.minimum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -526,9 +508,7 @@ define <4 x double> @vfmin_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.minimum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.minimum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -564,9 +544,7 @@ define <8 x double> @vfmin_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.minimum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.minimum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -615,9 +593,7 @@ define <16 x double> @vfmin_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.minimum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.minimum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -808,8 +784,6 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double> ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.minimum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.minimum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll index dc907eed16cc..97842c294036 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll @@ -87,9 +87,7 @@ define void @splat_zero_v8f16(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x half> poison, half 0.0, i32 0 - %b = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> zeroinitializer - store <8 x half> %b, ptr %x + store <8 x half> splat (half 0.0), ptr %x ret void } @@ -100,9 +98,7 @@ define void @splat_zero_v4f32(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x float> poison, float 0.0, i32 0 - %b = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> zeroinitializer - store <4 x float> %b, ptr %x + store <4 x float> splat (float 0.0), ptr %x ret void } @@ -113,9 +109,7 @@ define void @splat_zero_v2f64(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <2 x double> poison, double 0.0, i32 0 - %b = shufflevector <2 x double> %a, <2 x double> poison, <2 x i32> zeroinitializer - store <2 x double> %b, ptr %x + store <2 x double> splat (double 0.0), ptr %x ret void } @@ -126,9 +120,7 @@ define void @splat_zero_16f16(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <16 x half> poison, half 0.0, i32 0 - %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer - store <16 x half> %b, ptr %x + store <16 x half> splat (half 0.0), ptr %x ret void } @@ -139,9 +131,7 @@ define void @splat_zero_v8f32(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x float> poison, float 0.0, i32 0 - %b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer - store <8 x float> %b, ptr %x + store <8 x float> splat (float 0.0), ptr %x ret void } @@ -152,9 +142,7 @@ define void @splat_zero_v4f64(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x double> poison, double 0.0, i32 0 - %b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer - store <4 x double> %b, ptr %x + store <4 x double> splat (double 0.0), ptr %x ret void } @@ -166,9 +154,7 @@ define void @splat_negzero_v8f16(ptr %x) { ; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x half> poison, half -0.0, i32 0 - %b = shufflevector <8 x half> %a, <8 x half> poison, <8 x i32> zeroinitializer - store <8 x half> %b, ptr %x + store <8 x half> splat (half -0.0), ptr %x ret void } @@ -180,9 +166,7 @@ define void @splat_negzero_v4f32(ptr %x) { ; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x float> poison, float -0.0, i32 0 - %b = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> zeroinitializer - store <4 x float> %b, ptr %x + store <4 x float> splat (float -0.0), ptr %x ret void } @@ -204,9 +188,7 @@ define void @splat_negzero_v2f64(ptr %x) { ; CHECK-RV64-NEXT: vmv.v.x v8, a1 ; CHECK-RV64-NEXT: vse64.v v8, (a0) ; CHECK-RV64-NEXT: ret - %a = insertelement <2 x double> poison, double -0.0, i32 0 - %b = shufflevector <2 x double> %a, <2 x double> poison, <2 x i32> zeroinitializer - store <2 x double> %b, ptr %x + store <2 x double> splat (double -0.0), ptr %x ret void } @@ -218,9 +200,7 @@ define void @splat_negzero_16f16(ptr %x) { ; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <16 x half> poison, half -0.0, i32 0 - %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer - store <16 x half> %b, ptr %x + store <16 x half> splat (half -0.0), ptr %x ret void } @@ -232,9 +212,7 @@ define void @splat_negzero_v8f32(ptr %x) { ; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x float> poison, float -0.0, i32 0 - %b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer - store <8 x float> %b, ptr %x + store <8 x float> splat (float -0.0), ptr %x ret void } @@ -256,8 +234,6 @@ define void @splat_negzero_v4f64(ptr %x) { ; CHECK-RV64-NEXT: vmv.v.x v8, a1 ; CHECK-RV64-NEXT: vse64.v v8, (a0) ; CHECK-RV64-NEXT: ret - %a = insertelement <4 x double> poison, double -0.0, i32 0 - %b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer - store <4 x double> %b, ptr %x + store <4 x double> splat (double -0.0), ptr %x ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll index 5de28a0d722d..51ac27acaf47 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll @@ -24,7 +24,7 @@ define <2 x float> @vfpext_v2f16_v2f32_unmasked(<2 x half> %a, i32 zeroext %vl) ; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl) + %v = call <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half> %a, <2 x i1> splat (i1 true), i32 %vl) ret <2 x float> %v } @@ -50,7 +50,7 @@ define <2 x double> @vfpext_v2f16_v2f64_unmasked(<2 x half> %a, i32 zeroext %vl) ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfwcvt.f.f.v v8, v9 ; CHECK-NEXT: ret - %v = call <2 x double> @llvm.vp.fpext.v2f64.v2f16(<2 x half> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl) + %v = call <2 x double> @llvm.vp.fpext.v2f64.v2f16(<2 x half> %a, <2 x i1> splat (i1 true), i32 %vl) ret <2 x double> %v } @@ -74,7 +74,7 @@ define <2 x double> @vfpext_v2f32_v2f64_unmasked(<2 x float> %a, i32 zeroext %vl ; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <2 x double> @llvm.vp.fpext.v2f64.v2f32(<2 x float> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl) + %v = call <2 x double> @llvm.vp.fpext.v2f64.v2f32(<2 x float> %a, <2 x i1> splat (i1 true), i32 %vl) ret <2 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll index dab4b4d9926e..602662b18429 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll @@ -42,7 +42,7 @@ define <4 x i1> @vfptosi_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret - %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i1> %v } @@ -66,7 +66,7 @@ define <4 x i1> @vfptosi_v4i1_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i1> %v } @@ -91,6 +91,6 @@ define <4 x i1> @vfptosi_v4i1_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i1> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll index c673e396914b..49a1b19b58a2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll @@ -67,7 +67,7 @@ define <4 x i8> @vfptosi_v4i8_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0 ; ZVFHMIN-NEXT: ret - %v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -105,7 +105,7 @@ define <4 x i16> @vfptosi_v4i16_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -145,7 +145,7 @@ define <4 x i32> @vfptosi_v4i32_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -187,7 +187,7 @@ define <4 x i64> @vfptosi_v4i64_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.rtz.x.f.v v8, v10 ; ZVFHMIN-NEXT: ret - %v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -213,7 +213,7 @@ define <4 x i8> @vfptosi_v4i8_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -237,7 +237,7 @@ define <4 x i16> @vfptosi_v4i16_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -259,7 +259,7 @@ define <4 x i32> @vfptosi_v4i32_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -283,7 +283,7 @@ define <4 x i64> @vfptosi_v4i64_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -313,7 +313,7 @@ define <4 x i8> @vfptosi_v4i8_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i8> @llvm.vp.fptosi.v4i8.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -339,7 +339,7 @@ define <4 x i16> @vfptosi_v4i16_v4f64_unmasked(<4 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.fptosi.v4i16.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -363,7 +363,7 @@ define <4 x i32> @vfptosi_v4i32_v4f64_unmasked(<4 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.fptosi.v4i32.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -385,7 +385,7 @@ define <4 x i64> @vfptosi_v4i64_v4f64_unmasked(<4 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.fptosi.v4i64.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -434,6 +434,6 @@ define <32 x i64> @vfptosi_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16 ; CHECK-NEXT: ret - %v = call <32 x i64> @llvm.vp.fptosi.v32i64.v32f64(<32 x double> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) + %v = call <32 x i64> @llvm.vp.fptosi.v32i64.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll index f1a78b25e186..c5bfd41ec951 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll @@ -42,7 +42,7 @@ define <4 x i1> @vfptoui_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 ; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0 ; ZVFHMIN-NEXT: ret - %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i1> %v } @@ -66,7 +66,7 @@ define <4 x i1> @vfptoui_v4i1_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i1> %v } @@ -91,6 +91,6 @@ define <4 x i1> @vfptoui_v4i1_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i1> @llvm.vp.fptoui.v4i1.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i1> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll index 0a19dcb550b5..d44efa2f6133 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll @@ -67,7 +67,7 @@ define <4 x i8> @vfptoui_v4i8_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; ZVFHMIN-NEXT: vnsrl.wi v8, v8, 0 ; ZVFHMIN-NEXT: ret - %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -105,7 +105,7 @@ define <4 x i16> @vfptoui_v4i16_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.rtz.xu.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -145,7 +145,7 @@ define <4 x i32> @vfptoui_v4i32_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.rtz.xu.f.v v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -187,7 +187,7 @@ define <4 x i64> @vfptoui_v4i64_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfwcvt.rtz.xu.f.v v8, v10 ; ZVFHMIN-NEXT: ret - %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f16(<4 x half> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -213,7 +213,7 @@ define <4 x i8> @vfptoui_v4i8_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v9, 0 ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -237,7 +237,7 @@ define <4 x i16> @vfptoui_v4i16_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -259,7 +259,7 @@ define <4 x i32> @vfptoui_v4i32_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -283,7 +283,7 @@ define <4 x i64> @vfptoui_v4i64_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f32(<4 x float> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -313,7 +313,7 @@ define <4 x i8> @vfptoui_v4i8_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i8> @llvm.vp.fptoui.v4i8.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -339,7 +339,7 @@ define <4 x i16> @vfptoui_v4i16_v4f64_unmasked(<4 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.fptoui.v4i16.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -363,7 +363,7 @@ define <4 x i32> @vfptoui_v4i32_v4f64_unmasked(<4 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.fptoui.v4i32.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -385,7 +385,7 @@ define <4 x i64> @vfptoui_v4i64_v4f64_unmasked(<4 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f64(<4 x double> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.fptoui.v4i64.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -434,6 +434,6 @@ define <32 x i64> @vfptoui_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16 ; CHECK-NEXT: ret - %v = call <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) + %v = call <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll index 0d5b59b087b4..de11f9e8a9fa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll @@ -25,7 +25,7 @@ define <2 x half> @vfptrunc_v2f16_v2f32_unmasked(<2 x float> %a, i32 zeroext %vl ; CHECK-NEXT: vfncvt.f.f.w v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl) + %v = call <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float> %a, <2 x i1> splat (i1 true), i32 %vl) ret <2 x half> %v } @@ -51,7 +51,7 @@ define <2 x half> @vfptrunc_v2f16_v2f64_unmasked(<2 x double> %a, i32 zeroext %v ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfncvt.f.f.w v8, v9 ; CHECK-NEXT: ret - %v = call <2 x half> @llvm.vp.fptrunc.v2f16.v2f64(<2 x double> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl) + %v = call <2 x half> @llvm.vp.fptrunc.v2f16.v2f64(<2 x double> %a, <2 x i1> splat (i1 true), i32 %vl) ret <2 x half> %v } @@ -75,7 +75,7 @@ define <2 x float> @vfptrunc_v2f32_v2f64_unmasked(<2 x double> %a, i32 zeroext % ; CHECK-NEXT: vfncvt.f.f.w v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <2 x float> @llvm.vp.fptrunc.v2f64.v2f32(<2 x double> %a, <2 x i1> shufflevector (<2 x i1> insertelement (<2 x i1> undef, i1 true, i32 0), <2 x i1> undef, <2 x i32> zeroinitializer), i32 %vl) + %v = call <2 x float> @llvm.vp.fptrunc.v2f64.v2f32(<2 x double> %a, <2 x i1> splat (i1 true), i32 %vl) ret <2 x float> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll index 4da778a35472..0b08d9401402 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll @@ -523,9 +523,7 @@ define void @seteq_vi_v16i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 0, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = icmp eq <16 x i8> %a, %c + %d = icmp eq <16 x i8> %a, splat (i8 0) store <16 x i1> %d, ptr %z ret void } @@ -540,9 +538,7 @@ define void @setne_vi_v32i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <32 x i8>, ptr %x - %b = insertelement <32 x i8> poison, i8 0, i32 0 - %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer - %d = icmp ne <32 x i8> %a, %c + %d = icmp ne <32 x i8> %a, splat (i8 0) store <32 x i1> %d, ptr %z ret void } @@ -557,9 +553,7 @@ define void @setgt_vi_v64i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <64 x i8>, ptr %x - %b = insertelement <64 x i8> poison, i8 0, i32 0 - %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer - %d = icmp sgt <64 x i8> %a, %c + %d = icmp sgt <64 x i8> %a, splat (i8 0) store <64 x i1> %d, ptr %z ret void } @@ -574,9 +568,7 @@ define void @setgt_vi_v64i8_nonzero(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <64 x i8>, ptr %x - %b = insertelement <64 x i8> poison, i8 5, i32 0 - %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer - %d = icmp sgt <64 x i8> %a, %c + %d = icmp sgt <64 x i8> %a, splat (i8 5) store <64 x i1> %d, ptr %z ret void } @@ -591,9 +583,7 @@ define void @setlt_vi_v128i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <128 x i8>, ptr %x - %b = insertelement <128 x i8> poison, i8 0, i32 0 - %c = shufflevector <128 x i8> %b, <128 x i8> poison, <128 x i32> zeroinitializer - %d = icmp slt <128 x i8> %a, %c + %d = icmp slt <128 x i8> %a, splat (i8 0) store <128 x i1> %d, ptr %z ret void } @@ -607,9 +597,7 @@ define void @setge_vi_v8i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i8>, ptr %x - %b = insertelement <8 x i8> poison, i8 0, i32 0 - %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer - %d = icmp sge <8 x i8> %a, %c + %d = icmp sge <8 x i8> %a, splat (i8 0) store <8 x i1> %d, ptr %z ret void } @@ -623,9 +611,7 @@ define void @setle_vi_v16i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 0, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = icmp sle <16 x i8> %a, %c + %d = icmp sle <16 x i8> %a, splat (i8 0) store <16 x i1> %d, ptr %z ret void } @@ -640,9 +626,7 @@ define void @setugt_vi_v32i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v10, (a1) ; CHECK-NEXT: ret %a = load <32 x i8>, ptr %x - %b = insertelement <32 x i8> poison, i8 5, i32 0 - %c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer - %d = icmp ugt <32 x i8> %a, %c + %d = icmp ugt <32 x i8> %a, splat (i8 5) store <32 x i1> %d, ptr %z ret void } @@ -657,9 +641,7 @@ define void @setult_vi_v64i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v12, (a1) ; CHECK-NEXT: ret %a = load <64 x i8>, ptr %x - %b = insertelement <64 x i8> poison, i8 5, i32 0 - %c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer - %d = icmp ult <64 x i8> %a, %c + %d = icmp ult <64 x i8> %a, splat (i8 5) store <64 x i1> %d, ptr %z ret void } @@ -674,9 +656,7 @@ define void @setuge_vi_v128i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v16, (a1) ; CHECK-NEXT: ret %a = load <128 x i8>, ptr %x - %b = insertelement <128 x i8> poison, i8 5, i32 0 - %c = shufflevector <128 x i8> %b, <128 x i8> poison, <128 x i32> zeroinitializer - %d = icmp uge <128 x i8> %a, %c + %d = icmp uge <128 x i8> %a, splat (i8 5) store <128 x i1> %d, ptr %z ret void } @@ -690,9 +670,7 @@ define void @setule_vi_v8i8(ptr %x, ptr %z) { ; CHECK-NEXT: vsm.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i8>, ptr %x - %b = insertelement <8 x i8> poison, i8 5, i32 0 - %c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer - %d = icmp ule <8 x i8> %a, %c + %d = icmp ule <8 x i8> %a, splat (i8 5) store <8 x i1> %d, ptr %z ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll index 60202cfba760..649aa067b01a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll @@ -140,9 +140,7 @@ define void @splat_zero_v16i8(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <16 x i8> poison, i8 0, i32 0 - %b = shufflevector <16 x i8> %a, <16 x i8> poison, <16 x i32> zeroinitializer - store <16 x i8> %b, ptr %x + store <16 x i8> splat (i8 0), ptr %x ret void } @@ -153,9 +151,7 @@ define void @splat_zero_v8i16(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i16> poison, i16 0, i32 0 - %b = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> zeroinitializer - store <8 x i16> %b, ptr %x + store <8 x i16> splat (i16 0), ptr %x ret void } @@ -166,9 +162,7 @@ define void @splat_zero_v4i32(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i32> poison, i32 0, i32 0 - %b = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> zeroinitializer - store <4 x i32> %b, ptr %x + store <4 x i32> splat (i32 0), ptr %x ret void } @@ -179,9 +173,7 @@ define void @splat_zero_v2i64(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <2 x i64> poison, i64 0, i32 0 - %b = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> zeroinitializer - store <2 x i64> %b, ptr %x + store <2 x i64> splat (i64 0), ptr %x ret void } @@ -193,9 +185,7 @@ define void @splat_zero_v32i8(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <32 x i8> poison, i8 0, i32 0 - %b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer - store <32 x i8> %b, ptr %x + store <32 x i8> splat (i8 0), ptr %x ret void } @@ -206,9 +196,7 @@ define void @splat_zero_v16i16(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <16 x i16> poison, i16 0, i32 0 - %b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer - store <16 x i16> %b, ptr %x + store <16 x i16> splat (i16 0), ptr %x ret void } @@ -219,9 +207,7 @@ define void @splat_zero_v8i32(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i32> poison, i32 0, i32 0 - %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer - store <8 x i32> %b, ptr %x + store <8 x i32> splat (i32 0), ptr %x ret void } @@ -232,9 +218,7 @@ define void @splat_zero_v4i64(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i64> poison, i64 0, i32 0 - %b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer - store <4 x i64> %b, ptr %x + store <4 x i64> splat (i64 0), ptr %x ret void } @@ -311,9 +295,7 @@ define void @splat_allones_v16i8(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <16 x i8> poison, i8 -1, i32 0 - %b = shufflevector <16 x i8> %a, <16 x i8> poison, <16 x i32> zeroinitializer - store <16 x i8> %b, ptr %x + store <16 x i8> splat (i8 -1), ptr %x ret void } @@ -324,9 +306,7 @@ define void @splat_allones_v8i16(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i16> poison, i16 -1, i32 0 - %b = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> zeroinitializer - store <8 x i16> %b, ptr %x + store <8 x i16> splat (i16 -1), ptr %x ret void } @@ -337,9 +317,7 @@ define void @splat_allones_v4i32(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i32> poison, i32 -1, i32 0 - %b = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> zeroinitializer - store <4 x i32> %b, ptr %x + store <4 x i32> splat (i32 -1), ptr %x ret void } @@ -350,9 +328,7 @@ define void @splat_allones_v2i64(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <2 x i64> poison, i64 -1, i32 0 - %b = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> zeroinitializer - store <2 x i64> %b, ptr %x + store <2 x i64> splat (i64 -1), ptr %x ret void } @@ -364,9 +340,7 @@ define void @splat_allones_v32i8(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <32 x i8> poison, i8 -1, i32 0 - %b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer - store <32 x i8> %b, ptr %x + store <32 x i8> splat (i8 -1), ptr %x ret void } @@ -377,9 +351,7 @@ define void @splat_allones_v16i16(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <16 x i16> poison, i16 -1, i32 0 - %b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer - store <16 x i16> %b, ptr %x + store <16 x i16> splat (i16 -1), ptr %x ret void } @@ -390,9 +362,7 @@ define void @splat_allones_v8i32(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i32> poison, i32 -1, i32 0 - %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer - store <8 x i32> %b, ptr %x + store <8 x i32> splat (i32 -1), ptr %x ret void } @@ -403,9 +373,7 @@ define void @splat_allones_v4i64(ptr %x) { ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i64> poison, i64 -1, i32 0 - %b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer - store <4 x i64> %b, ptr %x + store <4 x i64> splat (i64 -1), ptr %x ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll index 175b110538ff..03e99baf91c0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -3935,9 +3935,7 @@ define void @add_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 -1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = add <16 x i8> %a, %c + %d = add <16 x i8> %a, splat (i8 -1) store <16 x i8> %d, ptr %x ret void } @@ -3951,9 +3949,7 @@ define void @add_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 -1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = add <8 x i16> %a, %c + %d = add <8 x i16> %a, splat (i16 -1) store <8 x i16> %d, ptr %x ret void } @@ -3967,9 +3963,7 @@ define void @add_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 -1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = add <4 x i32> %a, %c + %d = add <4 x i32> %a, splat (i32 -1) store <4 x i32> %d, ptr %x ret void } @@ -3983,9 +3977,7 @@ define void @add_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 -1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = add <2 x i64> %a, %c + %d = add <2 x i64> %a, splat (i64 -1) store <2 x i64> %d, ptr %x ret void } @@ -3999,9 +3991,7 @@ define void @add_iv_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = add <16 x i8> %c, %a + %d = add <16 x i8> splat (i8 1), %a store <16 x i8> %d, ptr %x ret void } @@ -4015,9 +4005,7 @@ define void @add_iv_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = add <8 x i16> %c, %a + %d = add <8 x i16> splat (i16 1), %a store <8 x i16> %d, ptr %x ret void } @@ -4031,9 +4019,7 @@ define void @add_iv_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = add <4 x i32> %c, %a + %d = add <4 x i32> splat (i32 1), %a store <4 x i32> %d, ptr %x ret void } @@ -4047,9 +4033,7 @@ define void @add_iv_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = add <2 x i64> %c, %a + %d = add <2 x i64> splat (i64 1), %a store <2 x i64> %d, ptr %x ret void } @@ -4160,9 +4144,7 @@ define void @sub_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 -1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = sub <16 x i8> %a, %c + %d = sub <16 x i8> %a, splat (i8 -1) store <16 x i8> %d, ptr %x ret void } @@ -4177,9 +4159,7 @@ define void @sub_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 -1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = sub <8 x i16> %a, %c + %d = sub <8 x i16> %a, splat (i16 -1) store <8 x i16> %d, ptr %x ret void } @@ -4194,9 +4174,7 @@ define void @sub_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 -1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = sub <4 x i32> %a, %c + %d = sub <4 x i32> %a, splat (i32 -1) store <4 x i32> %d, ptr %x ret void } @@ -4211,9 +4189,7 @@ define void @sub_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 -1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = sub <2 x i64> %a, %c + %d = sub <2 x i64> %a, splat (i64 -1) store <2 x i64> %d, ptr %x ret void } @@ -4227,9 +4203,7 @@ define void @sub_iv_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = sub <16 x i8> %c, %a + %d = sub <16 x i8> splat (i8 1), %a store <16 x i8> %d, ptr %x ret void } @@ -4243,9 +4217,7 @@ define void @sub_iv_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = sub <8 x i16> %c, %a + %d = sub <8 x i16> splat (i16 1), %a store <8 x i16> %d, ptr %x ret void } @@ -4259,9 +4231,7 @@ define void @sub_iv_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = sub <4 x i32> %c, %a + %d = sub <4 x i32> splat (i32 1), %a store <4 x i32> %d, ptr %x ret void } @@ -4275,9 +4245,7 @@ define void @sub_iv_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = sub <2 x i64> %c, %a + %d = sub <2 x i64> splat (i64 1), %a store <2 x i64> %d, ptr %x ret void } @@ -4483,9 +4451,7 @@ define void @and_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 -2, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = and <16 x i8> %a, %c + %d = and <16 x i8> %a, splat (i8 -2) store <16 x i8> %d, ptr %x ret void } @@ -4499,9 +4465,7 @@ define void @and_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 -2, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = and <8 x i16> %a, %c + %d = and <8 x i16> %a, splat (i16 -2) store <8 x i16> %d, ptr %x ret void } @@ -4515,9 +4479,7 @@ define void @and_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 -2, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = and <4 x i32> %a, %c + %d = and <4 x i32> %a, splat (i32 -2) store <4 x i32> %d, ptr %x ret void } @@ -4531,9 +4493,7 @@ define void @and_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 -2, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = and <2 x i64> %a, %c + %d = and <2 x i64> %a, splat (i64 -2) store <2 x i64> %d, ptr %x ret void } @@ -4547,9 +4507,7 @@ define void @and_iv_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = and <16 x i8> %c, %a + %d = and <16 x i8> splat (i8 1), %a store <16 x i8> %d, ptr %x ret void } @@ -4563,9 +4521,7 @@ define void @and_iv_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = and <8 x i16> %c, %a + %d = and <8 x i16> splat (i16 1), %a store <8 x i16> %d, ptr %x ret void } @@ -4579,9 +4535,7 @@ define void @and_iv_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = and <4 x i32> %c, %a + %d = and <4 x i32> splat (i32 1), %a store <4 x i32> %d, ptr %x ret void } @@ -4595,9 +4549,7 @@ define void @and_iv_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = and <2 x i64> %c, %a + %d = and <2 x i64> splat (i64 1), %a store <2 x i64> %d, ptr %x ret void } @@ -4707,9 +4659,7 @@ define void @or_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 -2, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = or <16 x i8> %a, %c + %d = or <16 x i8> %a, splat (i8 -2) store <16 x i8> %d, ptr %x ret void } @@ -4723,9 +4673,7 @@ define void @or_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 -2, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = or <8 x i16> %a, %c + %d = or <8 x i16> %a, splat (i16 -2) store <8 x i16> %d, ptr %x ret void } @@ -4739,9 +4687,7 @@ define void @or_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 -2, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = or <4 x i32> %a, %c + %d = or <4 x i32> %a, splat (i32 -2) store <4 x i32> %d, ptr %x ret void } @@ -4755,9 +4701,7 @@ define void @or_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 -2, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = or <2 x i64> %a, %c + %d = or <2 x i64> %a, splat (i64 -2) store <2 x i64> %d, ptr %x ret void } @@ -4771,9 +4715,7 @@ define void @or_iv_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = or <16 x i8> %c, %a + %d = or <16 x i8> splat (i8 1), %a store <16 x i8> %d, ptr %x ret void } @@ -4787,9 +4729,7 @@ define void @or_iv_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = or <8 x i16> %c, %a + %d = or <8 x i16> splat (i16 1), %a store <8 x i16> %d, ptr %x ret void } @@ -4803,9 +4743,7 @@ define void @or_iv_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = or <4 x i32> %c, %a + %d = or <4 x i32> splat (i32 1), %a store <4 x i32> %d, ptr %x ret void } @@ -4819,9 +4757,7 @@ define void @or_iv_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = or <2 x i64> %c, %a + %d = or <2 x i64> splat (i64 1), %a store <2 x i64> %d, ptr %x ret void } @@ -4931,9 +4867,7 @@ define void @xor_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 -1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = xor <16 x i8> %a, %c + %d = xor <16 x i8> %a, splat (i8 -1) store <16 x i8> %d, ptr %x ret void } @@ -4947,9 +4881,7 @@ define void @xor_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 -1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = xor <8 x i16> %a, %c + %d = xor <8 x i16> %a, splat (i16 -1) store <8 x i16> %d, ptr %x ret void } @@ -4963,9 +4895,7 @@ define void @xor_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 -1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = xor <4 x i32> %a, %c + %d = xor <4 x i32> %a, splat (i32 -1) store <4 x i32> %d, ptr %x ret void } @@ -4979,9 +4909,7 @@ define void @xor_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 -1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = xor <2 x i64> %a, %c + %d = xor <2 x i64> %a, splat (i64 -1) store <2 x i64> %d, ptr %x ret void } @@ -4995,9 +4923,7 @@ define void @xor_iv_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 1, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = xor <16 x i8> %c, %a + %d = xor <16 x i8> splat (i8 1), %a store <16 x i8> %d, ptr %x ret void } @@ -5011,9 +4937,7 @@ define void @xor_iv_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 1, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = xor <8 x i16> %c, %a + %d = xor <8 x i16> splat (i16 1), %a store <8 x i16> %d, ptr %x ret void } @@ -5027,9 +4951,7 @@ define void @xor_iv_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 1, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = xor <4 x i32> %c, %a + %d = xor <4 x i32> splat (i32 1), %a store <4 x i32> %d, ptr %x ret void } @@ -5043,9 +4965,7 @@ define void @xor_iv_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 1, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = xor <2 x i64> %c, %a + %d = xor <2 x i64> splat (i64 1), %a store <2 x i64> %d, ptr %x ret void } @@ -5155,9 +5075,7 @@ define void @lshr_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 7, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = lshr <16 x i8> %a, %c + %d = lshr <16 x i8> %a, splat (i8 7) store <16 x i8> %d, ptr %x ret void } @@ -5171,9 +5089,7 @@ define void @lshr_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 15, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = lshr <8 x i16> %a, %c + %d = lshr <8 x i16> %a, splat (i16 15) store <8 x i16> %d, ptr %x ret void } @@ -5187,9 +5103,7 @@ define void @lshr_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 31, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = lshr <4 x i32> %a, %c + %d = lshr <4 x i32> %a, splat (i32 31) store <4 x i32> %d, ptr %x ret void } @@ -5203,9 +5117,7 @@ define void @lshr_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 31, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = lshr <2 x i64> %a, %c + %d = lshr <2 x i64> %a, splat (i64 31) store <2 x i64> %d, ptr %x ret void } @@ -5267,9 +5179,7 @@ define void @ashr_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 7, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = ashr <16 x i8> %a, %c + %d = ashr <16 x i8> %a, splat (i8 7) store <16 x i8> %d, ptr %x ret void } @@ -5283,9 +5193,7 @@ define void @ashr_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 15, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = ashr <8 x i16> %a, %c + %d = ashr <8 x i16> %a, splat (i16 15) store <8 x i16> %d, ptr %x ret void } @@ -5299,9 +5207,7 @@ define void @ashr_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 31, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = ashr <4 x i32> %a, %c + %d = ashr <4 x i32> %a, splat (i32 31) store <4 x i32> %d, ptr %x ret void } @@ -5315,9 +5221,7 @@ define void @ashr_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 31, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = ashr <2 x i64> %a, %c + %d = ashr <2 x i64> %a, splat (i64 31) store <2 x i64> %d, ptr %x ret void } @@ -5379,9 +5283,7 @@ define void @shl_vi_v16i8(ptr %x) { ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x - %b = insertelement <16 x i8> poison, i8 7, i32 0 - %c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer - %d = shl <16 x i8> %a, %c + %d = shl <16 x i8> %a, splat (i8 7) store <16 x i8> %d, ptr %x ret void } @@ -5395,9 +5297,7 @@ define void @shl_vi_v8i16(ptr %x) { ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x - %b = insertelement <8 x i16> poison, i16 15, i32 0 - %c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer - %d = shl <8 x i16> %a, %c + %d = shl <8 x i16> %a, splat (i16 15) store <8 x i16> %d, ptr %x ret void } @@ -5411,9 +5311,7 @@ define void @shl_vi_v4i32(ptr %x) { ; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x - %b = insertelement <4 x i32> poison, i32 31, i32 0 - %c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer - %d = shl <4 x i32> %a, %c + %d = shl <4 x i32> %a, splat (i32 31) store <4 x i32> %d, ptr %x ret void } @@ -5427,9 +5325,7 @@ define void @shl_vi_v2i64(ptr %x) { ; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: ret %a = load <2 x i64>, ptr %x - %b = insertelement <2 x i64> poison, i64 31, i32 0 - %c = shufflevector <2 x i64> %b, <2 x i64> poison, <2 x i32> zeroinitializer - %d = shl <2 x i64> %a, %c + %d = shl <2 x i64> %a, splat (i64 31) store <2 x i64> %d, ptr %x ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index a09ab3ee0252..6ff283b9c807 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -12850,10 +12850,8 @@ define <4 x i32> @mgather_broadcast_load_unmasked(ptr %base) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), zero ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -12864,11 +12862,9 @@ define <4 x i32> @mgather_broadcast_load_unmasked2(ptr %base) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), zero ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrhead = insertelement <4 x ptr> poison, ptr %base, i32 0 %ptrs = shufflevector <4 x ptr> %ptrhead, <4 x ptr> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -12878,8 +12874,6 @@ define <4 x i32> @mgather_broadcast_load_masked(ptr %base, <4 x i1> %m) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), zero, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i8, ptr %base, <4 x i32> zeroinitializer %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %m, <4 x i32> poison) ret <4 x i32> %v diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll index 648fb785cf15..19f3d3ce19fa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll @@ -42,9 +42,7 @@ define <2 x half> @vp_nearbyint_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.nearbyint.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.nearbyint.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -86,9 +84,7 @@ define <4 x half> @vp_nearbyint_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.nearbyint.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.nearbyint.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -130,9 +126,7 @@ define <8 x half> @vp_nearbyint_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.nearbyint.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.nearbyint.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -176,9 +170,7 @@ define <16 x half> @vp_nearbyint_v16f16_unmasked(<16 x half> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.nearbyint.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.nearbyint.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -220,9 +212,7 @@ define <2 x float> @vp_nearbyint_v2f32_unmasked(<2 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.nearbyint.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.nearbyint.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -264,9 +254,7 @@ define <4 x float> @vp_nearbyint_v4f32_unmasked(<4 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.nearbyint.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.nearbyint.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -310,9 +298,7 @@ define <8 x float> @vp_nearbyint_v8f32_unmasked(<8 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.nearbyint.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.nearbyint.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -356,9 +342,7 @@ define <16 x float> @vp_nearbyint_v16f32_unmasked(<16 x float> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.nearbyint.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.nearbyint.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -400,9 +384,7 @@ define <2 x double> @vp_nearbyint_v2f64_unmasked(<2 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.nearbyint.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.nearbyint.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -446,9 +428,7 @@ define <4 x double> @vp_nearbyint_v4f64_unmasked(<4 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.nearbyint.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.nearbyint.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -492,9 +472,7 @@ define <8 x double> @vp_nearbyint_v8f64_unmasked(<8 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.nearbyint.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.nearbyint.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -538,9 +516,7 @@ define <15 x double> @vp_nearbyint_v15f64_unmasked(<15 x double> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.nearbyint.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.nearbyint.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -584,9 +560,7 @@ define <16 x double> @vp_nearbyint_v16f64_unmasked(<16 x double> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.nearbyint.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.nearbyint.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -690,8 +664,6 @@ define <32 x double> @vp_nearbyint_v32f64_unmasked(<32 x double> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.nearbyint.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.nearbyint.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll index 09bc27bdd15e..016be04ffc9b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll @@ -14,9 +14,7 @@ define <8 x i32> @vpmerge_vpadd(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> %y, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -31,10 +29,8 @@ define <8 x i32> @vpmerge_vpadd2(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> %y ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> %mask, i32 %vl) - %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> splat (i1 true), i32 %vl) + %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -46,10 +42,8 @@ define <8 x i32> @vpmerge_vpadd3(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> %y ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> %mask, i32 %vl) - %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %mask, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) + %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> splat (i1 true), i32 %vl) + %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> splat (i1 true), <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -61,9 +55,7 @@ define <8 x float> @vpmerge_vpfadd(<8 x float> %passthru, <8 x float> %x, <8 x f ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %x, <8 x float> %y, <8 x i1> %mask, i32 %vl) + %a = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %x, <8 x float> %y, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %a, <8 x float> %passthru, i32 %vl) ret <8 x float> %b } @@ -76,9 +68,7 @@ define <8 x i16> @vpmerge_vpfptosi(<8 x i16> %passthru, <8 x float> %x, <8 x i1> ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i16> @llvm.vp.fptosi.v8i16.v8f32(<8 x float> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x i16> @llvm.vp.fptosi.v8i16.v8f32(<8 x float> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i16> @llvm.vp.merge.v8i16(<8 x i1> %m, <8 x i16> %a, <8 x i16> %passthru, i32 %vl) ret <8 x i16> %b } @@ -91,9 +81,7 @@ define <8 x float> @vpmerge_vpsitofp(<8 x float> %passthru, <8 x i64> %x, <8 x i ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x float> @llvm.vp.sitofp.v8f32.v8i64(<8 x i64> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x float> @llvm.vp.sitofp.v8f32.v8i64(<8 x i64> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %a, <8 x float> %passthru, i32 %vl) ret <8 x float> %b } @@ -106,9 +94,7 @@ define <8 x i32> @vpmerge_vpzext(<8 x i32> %passthru, <8 x i8> %x, <8 x i1> %m, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.zext.v8i32.v8i8(<8 x i8> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.zext.v8i32.v8i8(<8 x i8> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -121,9 +107,7 @@ define <8 x i32> @vpmerge_vptrunc(<8 x i32> %passthru, <8 x i64> %x, <8 x i1> %m ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -136,9 +120,7 @@ define <8 x double> @vpmerge_vpfpext(<8 x double> %passthru, <8 x float> %x, <8 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %a, <8 x double> %passthru, i32 %vl) ret <8 x double> %b } @@ -151,9 +133,7 @@ define <8 x float> @vpmerge_vpfptrunc(<8 x float> %passthru, <8 x double> %x, <8 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %a, <8 x float> %passthru, i32 %vl) ret <8 x float> %b } @@ -167,9 +147,7 @@ define <8 x i32> @vpmerge_vpload(<8 x i32> %passthru, ptr %p, <8 x i1> %m, i32 z ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -183,10 +161,8 @@ define <8 x i32> @vpmerge_vpload2(<8 x i32> %passthru, ptr %p, <8 x i32> %x, <8 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> %mask, i32 %vl) - %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> splat (i1 true), i32 %vl) + %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -203,9 +179,7 @@ define <8 x i32> @vpselect_vpadd(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> %y ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -218,10 +192,8 @@ define <8 x i32> @vpselect_vpadd2(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> % ; CHECK-NEXT: vmseq.vv v0, v9, v10 ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> %mask, i32 %vl) - %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> splat (i1 true), i32 %vl) + %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -233,10 +205,8 @@ define <8 x i32> @vpselect_vpadd3(<8 x i32> %passthru, <8 x i32> %x, <8 x i32> % ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> %mask, i32 %vl) - %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %mask, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) + %a = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i1> splat (i1 true), i32 %vl) + %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> splat (i1 true), <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -247,9 +217,7 @@ define <8 x float> @vpselect_vpfadd(<8 x float> %passthru, <8 x float> %x, <8 x ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %x, <8 x float> %y, <8 x i1> %mask, i32 %vl) + %a = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %x, <8 x float> %y, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %a, <8 x float> %passthru, i32 %vl) ret <8 x float> %b } @@ -261,9 +229,7 @@ define <8 x i16> @vpselect_vpfptosi(<8 x i16> %passthru, <8 x float> %x, <8 x i1 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i16> @llvm.vp.fptosi.v8i16.v8f32(<8 x float> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x i16> @llvm.vp.fptosi.v8i16.v8f32(<8 x float> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i16> @llvm.vp.select.v8i16(<8 x i1> %m, <8 x i16> %a, <8 x i16> %passthru, i32 %vl) ret <8 x i16> %b } @@ -275,9 +241,7 @@ define <8 x float> @vpselect_vpsitofp(<8 x float> %passthru, <8 x i64> %x, <8 x ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x float> @llvm.vp.sitofp.v8f32.v8i64(<8 x i64> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x float> @llvm.vp.sitofp.v8f32.v8i64(<8 x i64> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %a, <8 x float> %passthru, i32 %vl) ret <8 x float> %b } @@ -289,9 +253,7 @@ define <8 x i32> @vpselect_vpzext(<8 x i32> %passthru, <8 x i8> %x, <8 x i1> %m, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vzext.vf4 v8, v9, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.zext.v8i32.v8i8(<8 x i8> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.zext.v8i32.v8i8(<8 x i8> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -303,9 +265,7 @@ define <8 x i32> @vpselect_vptrunc(<8 x i32> %passthru, <8 x i64> %x, <8 x i1> % ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.trunc.v8i32.v8i64(<8 x i64> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -317,9 +277,7 @@ define <8 x double> @vpselect_vpfpext(<8 x double> %passthru, <8 x float> %x, <8 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x double> @llvm.vp.fpext.v8f64.v8f32(<8 x float> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %a, <8 x double> %passthru, i32 %vl) ret <8 x double> %b } @@ -331,9 +289,7 @@ define <8 x float> @vpselect_vpfptrunc(<8 x float> %passthru, <8 x double> %x, < ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double> %x, <8 x i1> %mask, i32 %vl) + %a = call <8 x float> @llvm.vp.fptrunc.v8f32.v8f64(<8 x double> %x, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %a, <8 x float> %passthru, i32 %vl) ret <8 x float> %b } @@ -345,9 +301,7 @@ define <8 x i32> @vpselect_vpload(<8 x i32> %passthru, ptr %p, <8 x i1> %m, i32 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } @@ -360,10 +314,8 @@ define <8 x i32> @vpselect_vpload2(<8 x i32> %passthru, ptr %p, <8 x i32> %x, <8 ; CHECK-NEXT: vmseq.vv v0, v9, v10 ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 true, i32 0 - %mask = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> %mask, i32 %vl) - %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> %mask, i32 %vl) + %a = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %p, <8 x i1> splat (i1 true), i32 %vl) + %m = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %x, <8 x i32> %y, metadata !"eq", <8 x i1> splat (i1 true), i32 %vl) %b = call <8 x i32> @llvm.vp.select.v8i32(<8 x i1> %m, <8 x i32> %a, <8 x i32> %passthru, i32 %vl) ret <8 x i32> %b } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll index 3e0fb3009c6b..920d0d5fe7ba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll @@ -38,9 +38,7 @@ define <2 x half> @vp_rint_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.rint.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.rint.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -78,9 +76,7 @@ define <4 x half> @vp_rint_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.rint.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.rint.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -118,9 +114,7 @@ define <8 x half> @vp_rint_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.rint.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.rint.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -160,9 +154,7 @@ define <16 x half> @vp_rint_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.rint.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.rint.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -200,9 +192,7 @@ define <2 x float> @vp_rint_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.rint.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.rint.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -240,9 +230,7 @@ define <4 x float> @vp_rint_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.rint.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.rint.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -282,9 +270,7 @@ define <8 x float> @vp_rint_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.rint.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.rint.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -324,9 +310,7 @@ define <16 x float> @vp_rint_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.rint.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.rint.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -364,9 +348,7 @@ define <2 x double> @vp_rint_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.rint.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.rint.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -406,9 +388,7 @@ define <4 x double> @vp_rint_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.rint.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.rint.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -448,9 +428,7 @@ define <8 x double> @vp_rint_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.rint.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.rint.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -490,9 +468,7 @@ define <15 x double> @vp_rint_v15f64_unmasked(<15 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.rint.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.rint.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -532,9 +508,7 @@ define <16 x double> @vp_rint_v16f64_unmasked(<16 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.rint.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.rint.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -639,8 +613,6 @@ define <32 x double> @vp_rint_v32f64_unmasked(<32 x double> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.rint.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.rint.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll index 96a72d0ddd18..6f045349423c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll @@ -86,9 +86,7 @@ define <2 x half> @vp_round_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.round.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.round.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -170,9 +168,7 @@ define <4 x half> @vp_round_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.round.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.round.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -256,9 +252,7 @@ define <8 x half> @vp_round_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.round.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.round.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -344,9 +338,7 @@ define <16 x half> @vp_round_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.round.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.round.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -388,9 +380,7 @@ define <2 x float> @vp_round_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.round.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.round.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -432,9 +422,7 @@ define <4 x float> @vp_round_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.round.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.round.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -478,9 +466,7 @@ define <8 x float> @vp_round_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.round.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.round.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -524,9 +510,7 @@ define <16 x float> @vp_round_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.round.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.round.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -568,9 +552,7 @@ define <2 x double> @vp_round_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.round.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.round.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -614,9 +596,7 @@ define <4 x double> @vp_round_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.round.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.round.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -660,9 +640,7 @@ define <8 x double> @vp_round_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.round.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.round.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -706,9 +684,7 @@ define <15 x double> @vp_round_v15f64_unmasked(<15 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.round.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.round.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -752,9 +728,7 @@ define <16 x double> @vp_round_v16f64_unmasked(<16 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.round.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.round.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -867,8 +841,6 @@ define <32 x double> @vp_round_v32f64_unmasked(<32 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.round.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.round.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll index 74a43f09542a..738d7e37c50b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll @@ -86,9 +86,7 @@ define <2 x half> @vp_roundeven_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.roundeven.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.roundeven.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -170,9 +168,7 @@ define <4 x half> @vp_roundeven_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.roundeven.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.roundeven.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -256,9 +252,7 @@ define <8 x half> @vp_roundeven_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.roundeven.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.roundeven.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -344,9 +338,7 @@ define <16 x half> @vp_roundeven_v16f16_unmasked(<16 x half> %va, i32 zeroext %e ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.roundeven.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.roundeven.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -388,9 +380,7 @@ define <2 x float> @vp_roundeven_v2f32_unmasked(<2 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.roundeven.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.roundeven.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -432,9 +422,7 @@ define <4 x float> @vp_roundeven_v4f32_unmasked(<4 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.roundeven.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.roundeven.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -478,9 +466,7 @@ define <8 x float> @vp_roundeven_v8f32_unmasked(<8 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.roundeven.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.roundeven.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -524,9 +510,7 @@ define <16 x float> @vp_roundeven_v16f32_unmasked(<16 x float> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.roundeven.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.roundeven.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -568,9 +552,7 @@ define <2 x double> @vp_roundeven_v2f64_unmasked(<2 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.roundeven.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.roundeven.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -614,9 +596,7 @@ define <4 x double> @vp_roundeven_v4f64_unmasked(<4 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.roundeven.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.roundeven.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -660,9 +640,7 @@ define <8 x double> @vp_roundeven_v8f64_unmasked(<8 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.roundeven.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.roundeven.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -706,9 +684,7 @@ define <15 x double> @vp_roundeven_v15f64_unmasked(<15 x double> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.roundeven.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.roundeven.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -752,9 +728,7 @@ define <16 x double> @vp_roundeven_v16f64_unmasked(<16 x double> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.roundeven.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.roundeven.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -867,8 +841,6 @@ define <32 x double> @vp_roundeven_v32f64_unmasked(<32 x double> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.roundeven.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.roundeven.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll index 91de65c79bb7..6f5b7875266b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll @@ -86,9 +86,7 @@ define <2 x half> @vp_roundtozero_v2f16_unmasked(<2 x half> %va, i32 zeroext %ev ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.roundtozero.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.roundtozero.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -170,9 +168,7 @@ define <4 x half> @vp_roundtozero_v4f16_unmasked(<4 x half> %va, i32 zeroext %ev ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.roundtozero.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.roundtozero.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -256,9 +252,7 @@ define <8 x half> @vp_roundtozero_v8f16_unmasked(<8 x half> %va, i32 zeroext %ev ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.roundtozero.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.roundtozero.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -344,9 +338,7 @@ define <16 x half> @vp_roundtozero_v16f16_unmasked(<16 x half> %va, i32 zeroext ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.roundtozero.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.roundtozero.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -388,9 +380,7 @@ define <2 x float> @vp_roundtozero_v2f32_unmasked(<2 x float> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.roundtozero.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.roundtozero.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -432,9 +422,7 @@ define <4 x float> @vp_roundtozero_v4f32_unmasked(<4 x float> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.roundtozero.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.roundtozero.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -478,9 +466,7 @@ define <8 x float> @vp_roundtozero_v8f32_unmasked(<8 x float> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.roundtozero.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.roundtozero.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -524,9 +510,7 @@ define <16 x float> @vp_roundtozero_v16f32_unmasked(<16 x float> %va, i32 zeroex ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.roundtozero.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.roundtozero.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -568,9 +552,7 @@ define <2 x double> @vp_roundtozero_v2f64_unmasked(<2 x double> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.roundtozero.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.roundtozero.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -614,9 +596,7 @@ define <4 x double> @vp_roundtozero_v4f64_unmasked(<4 x double> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.roundtozero.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.roundtozero.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -660,9 +640,7 @@ define <8 x double> @vp_roundtozero_v8f64_unmasked(<8 x double> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.roundtozero.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.roundtozero.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -706,9 +684,7 @@ define <15 x double> @vp_roundtozero_v15f64_unmasked(<15 x double> %va, i32 zero ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.roundtozero.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.roundtozero.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -752,9 +728,7 @@ define <16 x double> @vp_roundtozero_v16f64_unmasked(<16 x double> %va, i32 zero ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.roundtozero.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.roundtozero.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -867,8 +841,6 @@ define <32 x double> @vp_roundtozero_v32f64_unmasked(<32 x double> %va, i32 zero ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.roundtozero.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.roundtozero.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll index 8cf069e66e8f..981715bd2b99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll @@ -135,9 +135,7 @@ define <8 x i1> @icmp_eq_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"eq", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"eq", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -147,9 +145,7 @@ define <8 x i1> @icmp_eq_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"eq", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"eq", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -193,9 +189,7 @@ define <8 x i1> @icmp_ne_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"ne", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"ne", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -205,9 +199,7 @@ define <8 x i1> @icmp_ne_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"ne", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"ne", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -251,9 +243,7 @@ define <8 x i1> @icmp_ugt_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"ugt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -263,9 +253,7 @@ define <8 x i1> @icmp_ugt_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -311,9 +299,7 @@ define <8 x i1> @icmp_uge_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -323,9 +309,7 @@ define <8 x i1> @icmp_uge_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"uge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -369,9 +353,7 @@ define <8 x i1> @icmp_ult_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"ult", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -381,9 +363,7 @@ define <8 x i1> @icmp_ult_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"ult", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"ult", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -427,9 +407,7 @@ define <8 x i1> @icmp_sgt_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"sgt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"sgt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -439,9 +417,7 @@ define <8 x i1> @icmp_sgt_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"sgt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"sgt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -487,9 +463,7 @@ define <8 x i1> @icmp_sge_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"sge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -499,9 +473,7 @@ define <8 x i1> @icmp_sge_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"sge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -545,9 +517,7 @@ define <8 x i1> @icmp_slt_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"slt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"slt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -557,9 +527,7 @@ define <8 x i1> @icmp_slt_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"slt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"slt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -605,9 +573,7 @@ define <8 x i1> @icmp_sle_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> %vb, metadata !"sle", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -617,9 +583,7 @@ define <8 x i1> @icmp_sle_vi_swap_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> %vb, <8 x i8> %va, metadata !"sle", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i8(<8 x i8> splat (i8 4), <8 x i8> %va, metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -783,9 +747,7 @@ define <8 x i1> @icmp_eq_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmseq.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"eq", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"eq", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -796,9 +758,7 @@ define <8 x i1> @icmp_eq_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vmseq.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"eq", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"eq", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -846,9 +806,7 @@ define <8 x i1> @icmp_ne_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsne.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"ne", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"ne", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -859,9 +817,7 @@ define <8 x i1> @icmp_ne_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vmsne.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"ne", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"ne", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -909,9 +865,7 @@ define <8 x i1> @icmp_ugt_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgtu.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"ugt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -922,9 +876,7 @@ define <8 x i1> @icmp_ugt_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsleu.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -974,9 +926,7 @@ define <8 x i1> @icmp_uge_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgtu.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -987,9 +937,7 @@ define <8 x i1> @icmp_uge_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsleu.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"uge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1037,9 +985,7 @@ define <8 x i1> @icmp_ult_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsleu.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"ult", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1050,9 +996,7 @@ define <8 x i1> @icmp_ult_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsgtu.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"ult", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"ult", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1100,9 +1044,7 @@ define <8 x i1> @icmp_sgt_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgt.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"sgt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"sgt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1113,9 +1055,7 @@ define <8 x i1> @icmp_sgt_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsle.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"sgt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"sgt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1165,9 +1105,7 @@ define <8 x i1> @icmp_sge_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgt.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"sge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1178,9 +1116,7 @@ define <8 x i1> @icmp_sge_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsle.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"sge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1228,9 +1164,7 @@ define <8 x i1> @icmp_slt_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsle.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"slt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"slt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1241,9 +1175,7 @@ define <8 x i1> @icmp_slt_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsgt.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"slt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"slt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1293,9 +1225,7 @@ define <8 x i1> @icmp_sle_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsle.vi v10, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> %vb, metadata !"sle", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1306,9 +1236,7 @@ define <8 x i1> @icmp_sle_vi_swap_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsgt.vi v10, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> %vb, <8 x i32> %va, metadata !"sle", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i32(<8 x i32> splat (i32 4), <8 x i32> %va, metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1558,9 +1486,7 @@ define <8 x i1> @icmp_eq_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmseq.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"eq", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"eq", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1571,9 +1497,7 @@ define <8 x i1> @icmp_eq_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vmseq.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"eq", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"eq", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1651,9 +1575,7 @@ define <8 x i1> @icmp_ne_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsne.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"ne", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"ne", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1664,9 +1586,7 @@ define <8 x i1> @icmp_ne_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vmsne.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"ne", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"ne", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1744,9 +1664,7 @@ define <8 x i1> @icmp_ugt_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgtu.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"ugt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1757,9 +1675,7 @@ define <8 x i1> @icmp_ugt_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsleu.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"ugt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1839,9 +1755,7 @@ define <8 x i1> @icmp_uge_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgtu.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"uge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1852,9 +1766,7 @@ define <8 x i1> @icmp_uge_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsleu.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"uge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"uge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1932,9 +1844,7 @@ define <8 x i1> @icmp_ult_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsleu.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"ult", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"ult", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -1945,9 +1855,7 @@ define <8 x i1> @icmp_ult_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsgtu.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"ult", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"ult", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2025,9 +1933,7 @@ define <8 x i1> @icmp_sgt_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgt.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"sgt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"sgt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2038,9 +1944,7 @@ define <8 x i1> @icmp_sgt_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsle.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"sgt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"sgt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2120,9 +2024,7 @@ define <8 x i1> @icmp_sge_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsgt.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"sge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2133,9 +2035,7 @@ define <8 x i1> @icmp_sge_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsle.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"sge", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"sge", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2213,9 +2113,7 @@ define <8 x i1> @icmp_slt_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsle.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"slt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"slt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2226,9 +2124,7 @@ define <8 x i1> @icmp_slt_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsgt.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"slt", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"slt", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2308,9 +2204,7 @@ define <8 x i1> @icmp_sle_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vmsle.vi v12, v8, 4, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> %vb, metadata !"sle", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } @@ -2321,8 +2215,6 @@ define <8 x i1> @icmp_sle_vi_swap_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vmsgt.vi v12, v8, 3, v0.t ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> %vb, <8 x i64> %va, metadata !"sle", <8 x i1> %m, i32 %evl) + %v = call <8 x i1> @llvm.vp.icmp.v8i64(<8 x i64> splat (i64 4), <8 x i64> %va, metadata !"sle", <8 x i1> %m, i32 %evl) ret <8 x i1> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll index c2c321bf91fb..bd9b66997ff8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp-mask.ll @@ -22,7 +22,7 @@ define <4 x i16> @vsext_v4i16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.sext.v4i16.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.sext.v4i16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -46,7 +46,7 @@ define <4 x i32> @vsext_v4i32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.sext.v4i32.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.sext.v4i32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -70,6 +70,6 @@ define <4 x i64> @vsext_v4i64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll index b1d3f5c3a3a6..52596d889241 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll @@ -22,7 +22,7 @@ define <4 x i16> @vsext_v4i16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.sext.v4i16.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.sext.v4i16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -46,7 +46,7 @@ define <4 x i32> @vsext_v4i32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsext.vf4 v9, v8 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.sext.v4i32.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.sext.v4i32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -70,7 +70,7 @@ define <4 x i64> @vsext_v4i64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsext.vf8 v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -94,7 +94,7 @@ define <4 x i32> @vsext_v4i32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.sext.v4i32.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.sext.v4i32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -118,7 +118,7 @@ define <4 x i64> @vsext_v4i64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -142,7 +142,7 @@ define <4 x i64> @vsext_v4i64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.sext.v4i64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -197,7 +197,7 @@ define <32 x i64> @vsext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl ; CHECK-NEXT: vsext.vf2 v16, v8 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) + %v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll index 60469eb466b0..67c045cc2b18 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll @@ -25,7 +25,7 @@ define <4 x half> @vsitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -52,7 +52,7 @@ define <4 x float> @vsitofp_v4f32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -79,6 +79,6 @@ define <4 x double> @vsitofp_v4f64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) ; CHECK-NEXT: vmerge.vim v8, v8, -1, v0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll index a6e55fc35325..5e93fdfc7a65 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll @@ -73,7 +73,7 @@ define <4 x half> @vsitofp_v4f16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -111,7 +111,7 @@ define <4 x half> @vsitofp_v4f16_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -151,7 +151,7 @@ define <4 x half> @vsitofp_v4f16_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -193,7 +193,7 @@ define <4 x half> @vsitofp_v4f16_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.sitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -217,7 +217,7 @@ define <4 x float> @vsitofp_v4f32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) ; CHECK-NEXT: vsext.vf2 v9, v8 ; CHECK-NEXT: vfwcvt.f.x.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -241,7 +241,7 @@ define <4 x float> @vsitofp_v4f32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl ; CHECK-NEXT: vfwcvt.f.x.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -263,7 +263,7 @@ define <4 x float> @vsitofp_v4f32_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -287,7 +287,7 @@ define <4 x float> @vsitofp_v4f32_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl ; CHECK-NEXT: vfncvt.f.x.w v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.sitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -311,7 +311,7 @@ define <4 x double> @vsitofp_v4f64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) ; CHECK-NEXT: vsext.vf4 v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -335,7 +335,7 @@ define <4 x double> @vsitofp_v4f64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %ev ; CHECK-NEXT: vsext.vf2 v10, v8 ; CHECK-NEXT: vfwcvt.f.x.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -359,7 +359,7 @@ define <4 x double> @vsitofp_v4f64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %ev ; CHECK-NEXT: vfwcvt.f.x.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -381,7 +381,7 @@ define <4 x double> @vsitofp_v4f64_v4i64_unmasked(<4 x i64> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.sitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -430,6 +430,6 @@ define <32 x double> @vsitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfcvt.f.x.v v16, v16 ; CHECK-NEXT: ret - %v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) + %v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll index 2ae058128eaa..6a8d2008de74 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll @@ -78,9 +78,7 @@ define <4 x i8> @strided_vpload_v4i8_allones_mask(ptr %ptr, i32 signext %stride, ; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma ; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <4 x i1> poison, i1 true, i32 0 - %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer - %load = call <4 x i8> @llvm.experimental.vp.strided.load.v4i8.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %b, i32 %evl) + %load = call <4 x i8> @llvm.experimental.vp.strided.load.v4i8.p0.i32(ptr %ptr, i32 %stride, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %load } @@ -158,9 +156,7 @@ define <8 x i16> @strided_vpload_v8i16_allones_mask(ptr %ptr, i32 signext %strid ; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma ; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <8 x i1> poison, i1 true, i32 0 - %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer - %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %b, i32 %evl) + %load = call <8 x i16> @llvm.experimental.vp.strided.load.v8i16.p0.i32(ptr %ptr, i32 %stride, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %load } @@ -216,9 +212,7 @@ define <8 x i32> @strided_vpload_v8i32_allones_mask(ptr %ptr, i32 signext %strid ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <8 x i1> poison, i1 true, i32 0 - %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer - %load = call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %b, i32 %evl) + %load = call <8 x i32> @llvm.experimental.vp.strided.load.v8i32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %load } @@ -262,9 +256,7 @@ define <4 x i64> @strided_vpload_v4i64_allones_mask(ptr %ptr, i32 signext %strid ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <4 x i1> poison, i1 true, i32 0 - %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer - %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %b, i32 %evl) + %load = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %load } @@ -298,9 +290,7 @@ define <2 x half> @strided_vpload_v2f16_allones_mask(ptr %ptr, i32 signext %stri ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma ; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <2 x i1> poison, i1 true, i32 0 - %b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer - %load = call <2 x half> @llvm.experimental.vp.strided.load.v2f16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> %b, i32 %evl) + %load = call <2 x half> @llvm.experimental.vp.strided.load.v2f16.p0.i32(ptr %ptr, i32 %stride, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %load } @@ -390,9 +380,7 @@ define <8 x float> @strided_vpload_v8f32_allones_mask(ptr %ptr, i32 signext %str ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <8 x i1> poison, i1 true, i32 0 - %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer - %load = call <8 x float> @llvm.experimental.vp.strided.load.v8f32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> %b, i32 %evl) + %load = call <8 x float> @llvm.experimental.vp.strided.load.v8f32.p0.i32(ptr %ptr, i32 %stride, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %load } @@ -437,9 +425,7 @@ define <4 x double> @strided_vpload_v4f64_allones_mask(ptr %ptr, i32 signext %st ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <4 x i1> poison, i1 true, i32 0 - %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer - %load = call <4 x double> @llvm.experimental.vp.strided.load.v4f64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> %b, i32 %evl) + %load = call <4 x double> @llvm.experimental.vp.strided.load.v4f64.p0.i32(ptr %ptr, i32 %stride, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %load } @@ -472,9 +458,7 @@ define <3 x double> @strided_vpload_v3f64_allones_mask(ptr %ptr, i32 signext %st ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement <3 x i1> poison, i1 true, i32 0 - %allones = shufflevector <3 x i1> %one, <3 x i1> poison, <3 x i32> zeroinitializer - %v = call <3 x double> @llvm.experimental.vp.strided.load.v3f64.p0.i32(ptr %ptr, i32 %stride, <3 x i1> %allones, i32 %evl) + %v = call <3 x double> @llvm.experimental.vp.strided.load.v3f64.p0.i32(ptr %ptr, i32 %stride, <3 x i1> splat (i1 true), i32 %evl) ret <3 x double> %v } @@ -530,9 +514,7 @@ define <32 x double> @strided_vpload_v32f64_allones_mask(ptr %ptr, i32 signext % ; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement <32 x i1> poison, i1 true, i32 0 - %allones = shufflevector <32 x i1> %one, <32 x i1> poison, <32 x i32> zeroinitializer - %load = call <32 x double> @llvm.experimental.vp.strided.load.v32f64.p0.i32(ptr %ptr, i32 %stride, <32 x i1> %allones, i32 %evl) + %load = call <32 x double> @llvm.experimental.vp.strided.load.v32f64.p0.i32(ptr %ptr, i32 %stride, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %load } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll index 6c4960bd4078..dee422a4c17d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpstore.ll @@ -376,9 +376,7 @@ define void @strided_vpstore_v2i8_allones_mask(<2 x i8> %val, ptr %ptr, i32 sign ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement <2 x i1> poison, i1 true, i32 0 - %b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer - call void @llvm.experimental.vp.strided.store.v2i8.p0.i32(<2 x i8> %val, ptr %ptr, i32 %stride, <2 x i1> %b, i32 %evl) + call void @llvm.experimental.vp.strided.store.v2i8.p0.i32(<2 x i8> %val, ptr %ptr, i32 %stride, <2 x i1> splat (i1 true), i32 %evl) ret void } @@ -399,9 +397,7 @@ define void @strided_vpstore_v3f32_allones_mask(<3 x float> %v, ptr %ptr, i32 si ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement <3 x i1> poison, i1 true, i32 0 - %allones = shufflevector <3 x i1> %one, <3 x i1> poison, <3 x i32> zeroinitializer - call void @llvm.experimental.vp.strided.store.v3f32.p0.i32(<3 x float> %v, ptr %ptr, i32 %stride, <3 x i1> %allones, i32 %evl) + call void @llvm.experimental.vp.strided.store.v3f32.p0.i32(<3 x float> %v, ptr %ptr, i32 %stride, <3 x i1> splat (i1 true), i32 %evl) ret void } @@ -454,9 +450,7 @@ define void @strided_store_v32f64_allones_mask(<32 x double> %v, ptr %ptr, i32 s ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsse64.v v16, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement <32 x i1> poison, i1 true, i32 0 - %allones = shufflevector <32 x i1> %one, <32 x i1> poison, <32 x i32> zeroinitializer - call void @llvm.experimental.vp.strided.store.v32f64.p0.i32(<32 x double> %v, ptr %ptr, i32 %stride, <32 x i1> %allones, i32 %evl) + call void @llvm.experimental.vp.strided.store.v32f64.p0.i32(<32 x double> %v, ptr %ptr, i32 %stride, <32 x i1> splat (i1 true), i32 %evl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll index 41f956bec903..adfb26cd3106 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll @@ -25,7 +25,7 @@ define <4 x half> @vuitofp_v4f16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -52,7 +52,7 @@ define <4 x float> @vuitofp_v4f32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -79,6 +79,6 @@ define <4 x double> @vuitofp_v4f64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll index 904740042740..698c48bc5565 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll @@ -73,7 +73,7 @@ define <4 x half> @vuitofp_v4f16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -111,7 +111,7 @@ define <4 x half> @vuitofp_v4f16_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -151,7 +151,7 @@ define <4 x half> @vuitofp_v4f16_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -193,7 +193,7 @@ define <4 x half> @vuitofp_v4f16_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x half> @llvm.vp.uitofp.v4f16.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -217,7 +217,7 @@ define <4 x float> @vuitofp_v4f32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) ; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -241,7 +241,7 @@ define <4 x float> @vuitofp_v4f32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -263,7 +263,7 @@ define <4 x float> @vuitofp_v4f32_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -287,7 +287,7 @@ define <4 x float> @vuitofp_v4f32_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl ; CHECK-NEXT: vfncvt.f.xu.w v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x float> @llvm.vp.uitofp.v4f32.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -311,7 +311,7 @@ define <4 x double> @vuitofp_v4f64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) ; CHECK-NEXT: vzext.vf4 v10, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -335,7 +335,7 @@ define <4 x double> @vuitofp_v4f64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %ev ; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -359,7 +359,7 @@ define <4 x double> @vuitofp_v4f64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %ev ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -381,7 +381,7 @@ define <4 x double> @vuitofp_v4f64_v4i64_unmasked(<4 x i64> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: ret - %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x double> @llvm.vp.uitofp.v4f64.v4i64(<4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -430,6 +430,6 @@ define <32 x double> @vuitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfcvt.f.xu.v v16, v16 ; CHECK-NEXT: ret - %v = call <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) + %v = call <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll index 954edf872aff..70b547759938 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll @@ -29,9 +29,7 @@ define <8 x i8> @vaaddu_vx_v8i8_floor(<8 x i8> %x, i8 %y) { %ysplat = shufflevector <8 x i8> %yhead, <8 x i8> poison, <8 x i32> zeroinitializer %yzv = zext <8 x i8> %ysplat to <8 x i16> %add = add nuw nsw <8 x i16> %xzv, %yzv - %one = insertelement <8 x i16> poison, i16 1, i32 0 - %splat = shufflevector <8 x i16> %one, <8 x i16> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i16> %add, %splat + %div = lshr <8 x i16> %add, splat (i16 1) %ret = trunc <8 x i16> %div to <8 x i8> ret <8 x i8> %ret } @@ -109,9 +107,7 @@ define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) { %ysplat = shufflevector <8 x i16> %yhead, <8 x i16> poison, <8 x i32> zeroinitializer %yzv = zext <8 x i16> %ysplat to <8 x i32> %add = add nuw nsw <8 x i32> %xzv, %yzv - %one = insertelement <8 x i32> poison, i32 1, i32 0 - %splat = shufflevector <8 x i32> %one, <8 x i32> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i32> %add, %splat + %div = lshr <8 x i32> %add, splat (i32 1) %ret = trunc <8 x i32> %div to <8 x i16> ret <8 x i16> %ret } @@ -143,9 +139,7 @@ define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) { %ysplat = shufflevector <8 x i32> %yhead, <8 x i32> poison, <8 x i32> zeroinitializer %yzv = zext <8 x i32> %ysplat to <8 x i64> %add = add nuw nsw <8 x i64> %xzv, %yzv - %one = insertelement <8 x i64> poison, i64 1, i64 0 - %splat = shufflevector <8 x i64> %one, <8 x i64> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i64> %add, %splat + %div = lshr <8 x i64> %add, splat (i64 1) %ret = trunc <8 x i64> %div to <8 x i32> ret <8 x i32> %ret } @@ -212,9 +206,7 @@ define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) { %ysplat = shufflevector <8 x i64> %yhead, <8 x i64> poison, <8 x i32> zeroinitializer %yzv = zext <8 x i64> %ysplat to <8 x i128> %add = add nuw nsw <8 x i128> %xzv, %yzv - %one = insertelement <8 x i128> poison, i128 1, i128 0 - %splat = shufflevector <8 x i128> %one, <8 x i128> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i128> %add, %splat + %div = lshr <8 x i128> %add, splat (i128 1) %ret = trunc <8 x i128> %div to <8 x i64> ret <8 x i64> %ret } @@ -248,9 +240,7 @@ define <8 x i8> @vaaddu_vx_v8i8_ceil(<8 x i8> %x, i8 %y) { %yzv = zext <8 x i8> %ysplat to <8 x i16> %add = add nuw nsw <8 x i16> %xzv, %yzv %add1 = add nuw nsw <8 x i16> %add, - %one = insertelement <8 x i16> poison, i16 1, i32 0 - %splat = shufflevector <8 x i16> %one, <8 x i16> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i16> %add1, %splat + %div = lshr <8 x i16> %add1, splat (i16 1) %ret = trunc <8 x i16> %div to <8 x i8> ret <8 x i8> %ret } @@ -359,9 +349,7 @@ define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) { %yzv = zext <8 x i16> %ysplat to <8 x i32> %add = add nuw nsw <8 x i32> %xzv, %yzv %add1 = add nuw nsw <8 x i32> %add, - %one = insertelement <8 x i32> poison, i32 1, i32 0 - %splat = shufflevector <8 x i32> %one, <8 x i32> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i32> %add1, %splat + %div = lshr <8 x i32> %add1, splat (i32 1) %ret = trunc <8 x i32> %div to <8 x i16> ret <8 x i16> %ret } @@ -395,9 +383,7 @@ define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) { %yzv = zext <8 x i32> %ysplat to <8 x i64> %add = add nuw nsw <8 x i64> %xzv, %yzv %add1 = add nuw nsw <8 x i64> %add, - %one = insertelement <8 x i64> poison, i64 1, i64 0 - %splat = shufflevector <8 x i64> %one, <8 x i64> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i64> %add1, %splat + %div = lshr <8 x i64> %add1, splat (i64 1) %ret = trunc <8 x i64> %div to <8 x i32> ret <8 x i32> %ret } @@ -467,9 +453,7 @@ define <8 x i64> @vaaddu_vx_v8i64_ceil(<8 x i64> %x, i64 %y) { %yzv = zext <8 x i64> %ysplat to <8 x i128> %add = add nuw nsw <8 x i128> %xzv, %yzv %add1 = add nuw nsw <8 x i128> %add, - %one = insertelement <8 x i128> poison, i128 1, i128 0 - %splat = shufflevector <8 x i128> %one, <8 x i128> poison, <8 x i32> zeroinitializer - %div = lshr <8 x i128> %add1, %splat + %div = lshr <8 x i128> %add1, splat (i128 1) %ret = trunc <8 x i128> %div to <8 x i64> ret <8 x i64> %ret } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll index e15253b67275..45215480166e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll @@ -34,9 +34,7 @@ define <2 x i8> @vadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -60,9 +58,7 @@ define <2 x i8> @vadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -72,9 +68,7 @@ define <2 x i8> @vadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -84,11 +78,7 @@ define <2 x i8> @vadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.add.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -110,9 +100,7 @@ define <4 x i8> @vadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -148,9 +136,7 @@ define <4 x i8> @vadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -160,9 +146,7 @@ define <4 x i8> @vadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -172,11 +156,7 @@ define <4 x i8> @vadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.add.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -198,9 +178,7 @@ define <5 x i8> @vadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -224,9 +202,7 @@ define <5 x i8> @vadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -236,9 +212,7 @@ define <5 x i8> @vadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl) ret <5 x i8> %v } @@ -248,11 +222,7 @@ define <5 x i8> @vadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.add.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -274,9 +244,7 @@ define <8 x i8> @vadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -300,9 +268,7 @@ define <8 x i8> @vadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -312,9 +278,7 @@ define <8 x i8> @vadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -324,11 +288,7 @@ define <8 x i8> @vadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.add.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -350,9 +310,7 @@ define <16 x i8> @vadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -376,9 +334,7 @@ define <16 x i8> @vadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -388,9 +344,7 @@ define <16 x i8> @vadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -400,11 +354,7 @@ define <16 x i8> @vadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.add.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -431,9 +381,7 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl) ret <256 x i8> %v } @@ -455,11 +403,7 @@ define <256 x i8> @vadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vadd.vi v16, v16, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -476,9 +420,7 @@ define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vadd.vi v16, v16, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 129) + %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129) ret <256 x i8> %v } @@ -491,9 +433,7 @@ define <256 x i8> @vadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 128) + %v = call <256 x i8> @llvm.vp.add.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128) ret <256 x i8> %v } @@ -515,9 +455,7 @@ define <2 x i16> @vadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -541,9 +479,7 @@ define <2 x i16> @vadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -553,9 +489,7 @@ define <2 x i16> @vadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -565,11 +499,7 @@ define <2 x i16> @vadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.add.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -591,9 +521,7 @@ define <4 x i16> @vadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -617,9 +545,7 @@ define <4 x i16> @vadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -629,9 +555,7 @@ define <4 x i16> @vadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -641,11 +565,7 @@ define <4 x i16> @vadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.add.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -667,9 +587,7 @@ define <8 x i16> @vadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -693,9 +611,7 @@ define <8 x i16> @vadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -705,9 +621,7 @@ define <8 x i16> @vadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -717,11 +631,7 @@ define <8 x i16> @vadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.add.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -743,9 +653,7 @@ define <16 x i16> @vadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -769,9 +677,7 @@ define <16 x i16> @vadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -781,9 +687,7 @@ define <16 x i16> @vadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -793,11 +697,7 @@ define <16 x i16> @vadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.add.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -819,9 +719,7 @@ define <2 x i32> @vadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -845,9 +743,7 @@ define <2 x i32> @vadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -857,9 +753,7 @@ define <2 x i32> @vadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -869,11 +763,7 @@ define <2 x i32> @vadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -895,9 +785,7 @@ define <4 x i32> @vadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -921,9 +809,7 @@ define <4 x i32> @vadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -933,9 +819,7 @@ define <4 x i32> @vadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -945,11 +829,7 @@ define <4 x i32> @vadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -971,9 +851,7 @@ define <8 x i32> @vadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -997,9 +875,7 @@ define <8 x i32> @vadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1009,9 +885,7 @@ define <8 x i32> @vadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1021,11 +895,7 @@ define <8 x i32> @vadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1047,9 +917,7 @@ define <16 x i32> @vadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1073,9 +941,7 @@ define <16 x i32> @vadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1085,9 +951,7 @@ define <16 x i32> @vadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1097,11 +961,7 @@ define <16 x i32> @vadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.add.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1123,9 +983,7 @@ define <2 x i64> @vadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1177,9 +1035,7 @@ define <2 x i64> @vadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1189,9 +1045,7 @@ define <2 x i64> @vadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1201,11 +1055,7 @@ define <2 x i64> @vadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.add.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1227,9 +1077,7 @@ define <4 x i64> @vadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1281,9 +1129,7 @@ define <4 x i64> @vadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1293,9 +1139,7 @@ define <4 x i64> @vadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1305,11 +1149,7 @@ define <4 x i64> @vadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.add.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1331,9 +1171,7 @@ define <8 x i64> @vadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1385,9 +1223,7 @@ define <8 x i64> @vadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1397,9 +1233,7 @@ define <8 x i64> @vadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1409,11 +1243,7 @@ define <8 x i64> @vadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.add.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1435,9 +1265,7 @@ define <16 x i64> @vadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1489,9 +1317,7 @@ define <16 x i64> @vadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1501,9 +1327,7 @@ define <16 x i64> @vadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1513,11 +1337,7 @@ define <16 x i64> @vadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.add.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1640,9 +1460,7 @@ define <32 x i64> @vadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vsetivli zero, 12, e64, m8, ta, ma ; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) + %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12) ret <32 x i64> %v } @@ -1671,8 +1489,6 @@ define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 27) + %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll index 80b62a7a0aae..507cf5cc6b80 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll @@ -34,9 +34,7 @@ define <2 x i8> @vand_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -72,9 +70,7 @@ define <2 x i8> @vand_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -86,9 +82,7 @@ define <2 x i8> @vand_vx_v2i8_unmasked_commute(<2 x i8> %va, i8 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -98,9 +92,7 @@ define <2 x i8> @vand_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 4, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> splat (i8 4), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -110,11 +102,7 @@ define <2 x i8> @vand_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 4, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.and.v2i8(<2 x i8> %va, <2 x i8> splat (i8 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -136,9 +124,7 @@ define <4 x i8> @vand_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -162,9 +148,7 @@ define <4 x i8> @vand_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -174,9 +158,7 @@ define <4 x i8> @vand_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 4, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> splat (i8 4), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -186,11 +168,7 @@ define <4 x i8> @vand_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 4, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.and.v4i8(<4 x i8> %va, <4 x i8> splat (i8 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -212,9 +190,7 @@ define <8 x i8> @vand_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -238,9 +214,7 @@ define <8 x i8> @vand_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -250,9 +224,7 @@ define <8 x i8> @vand_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -262,11 +234,7 @@ define <8 x i8> @vand_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.and.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -288,9 +256,7 @@ define <16 x i8> @vand_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -314,9 +280,7 @@ define <16 x i8> @vand_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -326,9 +290,7 @@ define <16 x i8> @vand_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 4, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> splat (i8 4), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -338,11 +300,7 @@ define <16 x i8> @vand_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 4, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.and.v16i8(<16 x i8> %va, <16 x i8> splat (i8 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -364,9 +322,7 @@ define <2 x i16> @vand_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -390,9 +346,7 @@ define <2 x i16> @vand_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -402,9 +356,7 @@ define <2 x i16> @vand_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 4, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> splat (i16 4), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -414,11 +366,7 @@ define <2 x i16> @vand_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 4, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.and.v2i16(<2 x i16> %va, <2 x i16> splat (i16 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -440,9 +388,7 @@ define <4 x i16> @vand_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -466,9 +412,7 @@ define <4 x i16> @vand_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -478,9 +422,7 @@ define <4 x i16> @vand_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 4, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> splat (i16 4), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -490,11 +432,7 @@ define <4 x i16> @vand_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 4, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.and.v4i16(<4 x i16> %va, <4 x i16> splat (i16 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -516,9 +454,7 @@ define <8 x i16> @vand_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -542,9 +478,7 @@ define <8 x i16> @vand_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -554,9 +488,7 @@ define <8 x i16> @vand_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 4, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> splat (i16 4), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -566,11 +498,7 @@ define <8 x i16> @vand_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 4, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.and.v8i16(<8 x i16> %va, <8 x i16> splat (i16 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -592,9 +520,7 @@ define <16 x i16> @vand_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -618,9 +544,7 @@ define <16 x i16> @vand_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -630,9 +554,7 @@ define <16 x i16> @vand_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 4, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> splat (i16 4), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -642,11 +564,7 @@ define <16 x i16> @vand_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 4, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.and.v16i16(<16 x i16> %va, <16 x i16> splat (i16 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -668,9 +586,7 @@ define <2 x i32> @vand_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -694,9 +610,7 @@ define <2 x i32> @vand_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -706,9 +620,7 @@ define <2 x i32> @vand_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 4, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> splat (i32 4), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -718,11 +630,7 @@ define <2 x i32> @vand_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 4, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.and.v2i32(<2 x i32> %va, <2 x i32> splat (i32 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -744,9 +652,7 @@ define <4 x i32> @vand_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -770,9 +676,7 @@ define <4 x i32> @vand_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -782,9 +686,7 @@ define <4 x i32> @vand_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 4, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> splat (i32 4), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -794,11 +696,7 @@ define <4 x i32> @vand_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 4, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.and.v4i32(<4 x i32> %va, <4 x i32> splat (i32 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -820,9 +718,7 @@ define <8 x i32> @vand_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -846,9 +742,7 @@ define <8 x i32> @vand_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -858,9 +752,7 @@ define <8 x i32> @vand_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -870,11 +762,7 @@ define <8 x i32> @vand_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -896,9 +784,7 @@ define <16 x i32> @vand_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -922,9 +808,7 @@ define <16 x i32> @vand_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -934,9 +818,7 @@ define <16 x i32> @vand_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 4, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> splat (i32 4), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -946,11 +828,7 @@ define <16 x i32> @vand_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 4, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.and.v16i32(<16 x i32> %va, <16 x i32> splat (i32 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -972,9 +850,7 @@ define <2 x i64> @vand_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1026,9 +902,7 @@ define <2 x i64> @vand_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1038,9 +912,7 @@ define <2 x i64> @vand_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 4, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> splat (i64 4), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1050,11 +922,7 @@ define <2 x i64> @vand_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 4, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.and.v2i64(<2 x i64> %va, <2 x i64> splat (i64 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1076,9 +944,7 @@ define <4 x i64> @vand_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1130,9 +996,7 @@ define <4 x i64> @vand_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1142,9 +1006,7 @@ define <4 x i64> @vand_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 4, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> splat (i64 4), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1154,11 +1016,7 @@ define <4 x i64> @vand_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 4, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.and.v4i64(<4 x i64> %va, <4 x i64> splat (i64 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1180,9 +1038,7 @@ define <8 x i64> @vand_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1234,9 +1090,7 @@ define <8 x i64> @vand_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1246,9 +1100,7 @@ define <8 x i64> @vand_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1258,11 +1110,7 @@ define <8 x i64> @vand_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.and.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1284,9 +1132,7 @@ define <11 x i64> @vand_vv_v11i64_unmasked(<11 x i64> %va, <11 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <11 x i1> poison, i1 true, i32 0 - %m = shufflevector <11 x i1> %head, <11 x i1> poison, <11 x i32> zeroinitializer - %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> %b, <11 x i1> %m, i32 %evl) + %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> %b, <11 x i1> splat (i1 true), i32 %evl) ret <11 x i64> %v } @@ -1338,9 +1184,7 @@ define <11 x i64> @vand_vx_v11i64_unmasked(<11 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <11 x i64> poison, i64 %b, i32 0 %vb = shufflevector <11 x i64> %elt.head, <11 x i64> poison, <11 x i32> zeroinitializer - %head = insertelement <11 x i1> poison, i1 true, i32 0 - %m = shufflevector <11 x i1> %head, <11 x i1> poison, <11 x i32> zeroinitializer - %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> %vb, <11 x i1> %m, i32 %evl) + %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> %vb, <11 x i1> splat (i1 true), i32 %evl) ret <11 x i64> %v } @@ -1350,9 +1194,7 @@ define <11 x i64> @vand_vi_v11i64(<11 x i64> %va, <11 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <11 x i64> poison, i64 4, i32 0 - %vb = shufflevector <11 x i64> %elt.head, <11 x i64> poison, <11 x i32> zeroinitializer - %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> %vb, <11 x i1> %m, i32 %evl) + %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> splat (i64 4), <11 x i1> %m, i32 %evl) ret <11 x i64> %v } @@ -1362,11 +1204,7 @@ define <11 x i64> @vand_vi_v11i64_unmasked(<11 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <11 x i64> poison, i64 4, i32 0 - %vb = shufflevector <11 x i64> %elt.head, <11 x i64> poison, <11 x i32> zeroinitializer - %head = insertelement <11 x i1> poison, i1 true, i32 0 - %m = shufflevector <11 x i1> %head, <11 x i1> poison, <11 x i32> zeroinitializer - %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> %vb, <11 x i1> %m, i32 %evl) + %v = call <11 x i64> @llvm.vp.and.v11i64(<11 x i64> %va, <11 x i64> splat (i64 4), <11 x i1> splat (i1 true), i32 %evl) ret <11 x i64> %v } @@ -1388,9 +1226,7 @@ define <16 x i64> @vand_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1442,9 +1278,7 @@ define <16 x i64> @vand_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1454,9 +1288,7 @@ define <16 x i64> @vand_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 4, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> splat (i64 4), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1466,10 +1298,6 @@ define <16 x i64> @vand_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 4, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.and.v16i64(<16 x i64> %va, <16 x i64> splat (i64 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll index f83968d54b2c..01b07b4081e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll @@ -22,9 +22,7 @@ define <2 x half> @vfsgnj_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.copysign.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.copysign.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -46,9 +44,7 @@ define <4 x half> @vfsgnj_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.copysign.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.copysign.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -70,9 +66,7 @@ define <8 x half> @vfsgnj_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.copysign.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.copysign.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -94,9 +88,7 @@ define <16 x half> @vfsgnj_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.copysign.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.copysign.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -118,9 +110,7 @@ define <2 x float> @vfsgnj_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.copysign.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.copysign.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -142,9 +132,7 @@ define <4 x float> @vfsgnj_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.copysign.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.copysign.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -166,9 +154,7 @@ define <8 x float> @vfsgnj_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.copysign.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.copysign.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -190,9 +176,7 @@ define <16 x float> @vfsgnj_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %v ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.copysign.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.copysign.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -214,9 +198,7 @@ define <2 x double> @vfsgnj_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.copysign.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.copysign.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -238,9 +220,7 @@ define <4 x double> @vfsgnj_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.copysign.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.copysign.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -262,9 +242,7 @@ define <8 x double> @vfsgnj_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.copysign.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.copysign.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -286,9 +264,7 @@ define <15 x double> @vfsgnj_vv_v15f64_unmasked(<15 x double> %va, <15 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.copysign.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.copysign.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -310,9 +286,7 @@ define <16 x double> @vfsgnj_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.copysign.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.copysign.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -384,8 +358,6 @@ define <32 x double> @vfsgnj_vv_v32f64_unmasked(<32 x double> %va, <32 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsgnj.vv v16, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.copysign.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.copysign.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll index 435d3ff1746d..29f8eaba9005 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll @@ -39,9 +39,7 @@ define <2 x i8> @vdiv_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sdiv.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sdiv.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -65,9 +63,7 @@ define <2 x i8> @vdiv_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sdiv.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sdiv.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -89,9 +85,7 @@ define <4 x i8> @vdiv_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sdiv.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sdiv.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -115,9 +109,7 @@ define <4 x i8> @vdiv_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sdiv.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sdiv.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -151,9 +143,7 @@ define <8 x i8> @vdiv_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sdiv.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sdiv.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -177,9 +167,7 @@ define <8 x i8> @vdiv_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sdiv.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sdiv.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -201,9 +189,7 @@ define <16 x i8> @vdiv_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sdiv.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sdiv.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -227,9 +213,7 @@ define <16 x i8> @vdiv_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sdiv.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sdiv.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -251,9 +235,7 @@ define <2 x i16> @vdiv_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sdiv.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sdiv.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -277,9 +259,7 @@ define <2 x i16> @vdiv_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sdiv.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sdiv.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -301,9 +281,7 @@ define <4 x i16> @vdiv_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sdiv.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sdiv.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -327,9 +305,7 @@ define <4 x i16> @vdiv_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sdiv.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sdiv.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -351,9 +327,7 @@ define <8 x i16> @vdiv_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sdiv.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sdiv.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -377,9 +351,7 @@ define <8 x i16> @vdiv_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sdiv.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sdiv.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -401,9 +373,7 @@ define <16 x i16> @vdiv_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sdiv.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sdiv.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -427,9 +397,7 @@ define <16 x i16> @vdiv_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sdiv.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sdiv.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -451,9 +419,7 @@ define <2 x i32> @vdiv_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sdiv.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sdiv.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -477,9 +443,7 @@ define <2 x i32> @vdiv_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sdiv.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sdiv.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -501,9 +465,7 @@ define <4 x i32> @vdiv_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -527,9 +489,7 @@ define <4 x i32> @vdiv_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sdiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -551,9 +511,7 @@ define <8 x i32> @vdiv_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -577,9 +535,7 @@ define <8 x i32> @vdiv_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -601,9 +557,7 @@ define <16 x i32> @vdiv_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sdiv.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sdiv.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -627,9 +581,7 @@ define <16 x i32> @vdiv_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sdiv.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sdiv.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -651,9 +603,7 @@ define <2 x i64> @vdiv_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sdiv.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sdiv.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -705,9 +655,7 @@ define <2 x i64> @vdiv_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sdiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sdiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -729,9 +677,7 @@ define <4 x i64> @vdiv_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sdiv.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sdiv.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -783,9 +729,7 @@ define <4 x i64> @vdiv_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sdiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sdiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -807,9 +751,7 @@ define <8 x i64> @vdiv_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sdiv.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sdiv.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -861,9 +803,7 @@ define <8 x i64> @vdiv_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sdiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sdiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -885,9 +825,7 @@ define <16 x i64> @vdiv_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sdiv.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sdiv.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -939,8 +877,6 @@ define <16 x i64> @vdiv_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sdiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sdiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll index 4e78c5cde2fa..3f8eb0ff276b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll @@ -38,9 +38,7 @@ define <2 x i8> @vdivu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.udiv.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.udiv.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -64,9 +62,7 @@ define <2 x i8> @vdivu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.udiv.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.udiv.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -88,9 +84,7 @@ define <4 x i8> @vdivu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.udiv.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.udiv.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -114,9 +108,7 @@ define <4 x i8> @vdivu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.udiv.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.udiv.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -150,9 +142,7 @@ define <8 x i8> @vdivu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.udiv.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.udiv.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -176,9 +166,7 @@ define <8 x i8> @vdivu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.udiv.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.udiv.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -200,9 +188,7 @@ define <16 x i8> @vdivu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.udiv.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.udiv.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -226,9 +212,7 @@ define <16 x i8> @vdivu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.udiv.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.udiv.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -250,9 +234,7 @@ define <2 x i16> @vdivu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.udiv.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.udiv.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -276,9 +258,7 @@ define <2 x i16> @vdivu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.udiv.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.udiv.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -300,9 +280,7 @@ define <4 x i16> @vdivu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.udiv.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.udiv.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -326,9 +304,7 @@ define <4 x i16> @vdivu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.udiv.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.udiv.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -350,9 +326,7 @@ define <8 x i16> @vdivu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.udiv.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.udiv.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -376,9 +350,7 @@ define <8 x i16> @vdivu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.udiv.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.udiv.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -400,9 +372,7 @@ define <16 x i16> @vdivu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.udiv.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.udiv.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -426,9 +396,7 @@ define <16 x i16> @vdivu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.udiv.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.udiv.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -450,9 +418,7 @@ define <2 x i32> @vdivu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -476,9 +442,7 @@ define <2 x i32> @vdivu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -500,9 +464,7 @@ define <4 x i32> @vdivu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -526,9 +488,7 @@ define <4 x i32> @vdivu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.udiv.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -550,9 +510,7 @@ define <8 x i32> @vdivu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -576,9 +534,7 @@ define <8 x i32> @vdivu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -600,9 +556,7 @@ define <16 x i32> @vdivu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.udiv.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.udiv.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -626,9 +580,7 @@ define <16 x i32> @vdivu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.udiv.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.udiv.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -650,9 +602,7 @@ define <2 x i64> @vdivu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.udiv.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.udiv.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -704,9 +654,7 @@ define <2 x i64> @vdivu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.udiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.udiv.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -728,9 +676,7 @@ define <4 x i64> @vdivu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.udiv.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.udiv.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -782,9 +728,7 @@ define <4 x i64> @vdivu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.udiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.udiv.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -806,9 +750,7 @@ define <8 x i64> @vdivu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.udiv.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.udiv.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -860,9 +802,7 @@ define <8 x i64> @vdivu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.udiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.udiv.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -884,9 +824,7 @@ define <16 x i64> @vdivu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.udiv.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.udiv.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -938,8 +876,6 @@ define <16 x i64> @vdivu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.udiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.udiv.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll index a30f682d5cf1..f32e2bbf3794 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll @@ -46,9 +46,7 @@ define <2 x half> @vfabs_vv_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fabs.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fabs.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -90,9 +88,7 @@ define <4 x half> @vfabs_vv_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fabs.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fabs.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -134,9 +130,7 @@ define <8 x half> @vfabs_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fabs.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fabs.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -178,9 +172,7 @@ define <16 x half> @vfabs_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fabs.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fabs.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -202,9 +194,7 @@ define <2 x float> @vfabs_vv_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fabs.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fabs.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -226,9 +216,7 @@ define <4 x float> @vfabs_vv_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fabs.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fabs.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -250,9 +238,7 @@ define <8 x float> @vfabs_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fabs.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fabs.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -274,9 +260,7 @@ define <16 x float> @vfabs_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fabs.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fabs.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -298,9 +282,7 @@ define <2 x double> @vfabs_vv_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fabs.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fabs.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -322,9 +304,7 @@ define <4 x double> @vfabs_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fabs.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fabs.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -346,9 +326,7 @@ define <8 x double> @vfabs_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fabs.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fabs.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -370,9 +348,7 @@ define <15 x double> @vfabs_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.fabs.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.fabs.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -394,9 +370,7 @@ define <16 x double> @vfabs_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fabs.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fabs.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -445,8 +419,6 @@ define <32 x double> @vfabs_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfabs.v v16, v16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll index fa01057b2120..f023c760f14a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll @@ -48,9 +48,7 @@ define <2 x half> @vfadd_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fadd.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fadd.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -106,9 +104,7 @@ define <2 x half> @vfadd_vf_v2f16_unmasked(<2 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fadd.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fadd.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -175,9 +171,7 @@ define <4 x half> @vfadd_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fadd.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fadd.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -233,9 +227,7 @@ define <4 x half> @vfadd_vf_v4f16_unmasked(<4 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fadd.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fadd.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -279,9 +271,7 @@ define <8 x half> @vfadd_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fadd.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fadd.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -337,9 +327,7 @@ define <8 x half> @vfadd_vf_v8f16_unmasked(<8 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fadd.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fadd.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -383,9 +371,7 @@ define <16 x half> @vfadd_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %b, i3 ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fadd.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fadd.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -441,9 +427,7 @@ define <16 x half> @vfadd_vf_v16f16_unmasked(<16 x half> %va, half %b, i32 zeroe ; ZVFHMIN-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fadd.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fadd.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -465,9 +449,7 @@ define <2 x float> @vfadd_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fadd.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fadd.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -503,9 +485,7 @@ define <2 x float> @vfadd_vf_v2f32_unmasked(<2 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fadd.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fadd.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -517,9 +497,7 @@ define <2 x float> @vfadd_vf_v2f32_unmasked_commute(<2 x float> %va, float %b, i ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fadd.v2f32(<2 x float> %vb, <2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fadd.v2f32(<2 x float> %vb, <2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -541,9 +519,7 @@ define <4 x float> @vfadd_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -567,9 +543,7 @@ define <4 x float> @vfadd_vf_v4f32_unmasked(<4 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fadd.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -591,9 +565,7 @@ define <8 x float> @vfadd_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -617,9 +589,7 @@ define <8 x float> @vfadd_vf_v8f32_unmasked(<8 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fadd.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -641,9 +611,7 @@ define <16 x float> @vfadd_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %b, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fadd.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fadd.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -667,9 +635,7 @@ define <16 x float> @vfadd_vf_v16f32_unmasked(<16 x float> %va, float %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fadd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fadd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -691,9 +657,7 @@ define <2 x double> @vfadd_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fadd.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fadd.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -717,9 +681,7 @@ define <2 x double> @vfadd_vf_v2f64_unmasked(<2 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fadd.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fadd.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -741,9 +703,7 @@ define <4 x double> @vfadd_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fadd.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fadd.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -767,9 +727,7 @@ define <4 x double> @vfadd_vf_v4f64_unmasked(<4 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fadd.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fadd.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -791,9 +749,7 @@ define <8 x double> @vfadd_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fadd.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fadd.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -817,9 +773,7 @@ define <8 x double> @vfadd_vf_v8f64_unmasked(<8 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fadd.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fadd.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -841,9 +795,7 @@ define <16 x double> @vfadd_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fadd.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fadd.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -867,8 +819,6 @@ define <16 x double> @vfadd_vf_v16f64_unmasked(<16 x double> %va, double %b, i32 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fadd.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fadd.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll index 8eefae291d34..09b9e7ce4c53 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll @@ -26,9 +26,7 @@ define <2 x i1> @isnan_v2f16_unmasked(<2 x half> %x, i32 zeroext %evl) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> %m, i32 %evl) ; nan + %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f16(<2 x half> %x, i32 3, <2 x i1> splat (i1 true), i32 %evl) ; nan ret <2 x i1> %1 } @@ -54,9 +52,7 @@ define <2 x i1> @isnan_v2f32_unmasked(<2 x float> %x, i32 zeroext %evl) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float> %x, i32 639, <2 x i1> %m, i32 %evl) + %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f32(<2 x float> %x, i32 639, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i1> %1 } @@ -82,9 +78,7 @@ define <4 x i1> @isnan_v4f32_unmasked(<4 x float> %x, i32 zeroext %evl) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float> %x, i32 3, <4 x i1> %m, i32 %evl) ; nan + %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f32(<4 x float> %x, i32 3, <4 x i1> splat (i1 true), i32 %evl) ; nan ret <4 x i1> %1 } @@ -109,9 +103,7 @@ define <8 x i1> @isnan_v8f32_unmasked(<8 x float> %x, i32 zeroext %evl) { ; CHECK-NEXT: li a0, 512 ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float> %x, i32 2, <8 x i1> %m, i32 %evl) + %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f32(<8 x float> %x, i32 2, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i1> %1 } @@ -136,9 +128,7 @@ define <16 x i1> @isnan_v16f32_unmasked(<16 x float> %x, i32 zeroext %evl) { ; CHECK-NEXT: li a0, 256 ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float> %x, i32 1, <16 x i1> %m, i32 %evl) + %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f32(<16 x float> %x, i32 1, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i1> %1 } @@ -164,9 +154,7 @@ define <2 x i1> @isnormal_v2f64_unmasked(<2 x double> %x, i32 zeroext %evl) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double> %x, i32 516, <2 x i1> %m, i32 %evl) ; 0x204 = "inf" + %1 = call <2 x i1> @llvm.vp.is.fpclass.v2f64(<2 x double> %x, i32 516, <2 x i1> splat (i1 true), i32 %evl) ; 0x204 = "inf" ret <2 x i1> %1 } @@ -191,9 +179,7 @@ define <4 x i1> @isposinf_v4f64_unmasked(<4 x double> %x, i32 zeroext %evl) { ; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double> %x, i32 512, <4 x i1> %m, i32 %evl) ; 0x200 = "+inf" + %1 = call <4 x i1> @llvm.vp.is.fpclass.v4f64(<4 x double> %x, i32 512, <4 x i1> splat (i1 true), i32 %evl) ; 0x200 = "+inf" ret <4 x i1> %1 } @@ -216,9 +202,7 @@ define <8 x i1> @isneginf_v8f64_unmasked(<8 x double> %x, i32 zeroext %evl) { ; CHECK-NEXT: vfclass.v v8, v8 ; CHECK-NEXT: vmseq.vi v0, v8, 1 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double> %x, i32 4, <8 x i1> %m, i32 %evl) ; "-inf" + %1 = call <8 x i1> @llvm.vp.is.fpclass.v8f64(<8 x double> %x, i32 4, <8 x i1> splat (i1 true), i32 %evl) ; "-inf" ret <8 x i1> %1 } @@ -245,9 +229,7 @@ define <16 x i1> @isfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl) { ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 504, <16 x i1> %m, i32 %evl) ; 0x1f8 = "finite" + %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 504, <16 x i1> splat (i1 true), i32 %evl) ; 0x1f8 = "finite" ret <16 x i1> %1 } @@ -273,9 +255,7 @@ define <16 x i1> @isnegfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl ; CHECK-NEXT: vand.vi v8, v8, 14 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 56, <16 x i1> %m, i32 %evl) ; 0x38 = "-finite" + %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 56, <16 x i1> splat (i1 true), i32 %evl) ; 0x38 = "-finite" ret <16 x i1> %1 } @@ -302,9 +282,7 @@ define <16 x i1> @isnotfinite_v16f64_unmasked(<16 x double> %x, i32 zeroext %evl ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 519, <16 x i1> %m, i32 %evl) ; 0x207 = "inf|nan" + %1 = call <16 x i1> @llvm.vp.is.fpclass.v16f64(<16 x double> %x, i32 519, <16 x i1> splat (i1 true), i32 %evl) ; 0x207 = "inf|nan" ret <16 x i1> %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll index 8c19e0bae81c..9fb8377d5a5e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll @@ -48,9 +48,7 @@ define <2 x half> @vfdiv_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fdiv.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fdiv.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -106,9 +104,7 @@ define <2 x half> @vfdiv_vf_v2f16_unmasked(<2 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fdiv.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fdiv.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -175,9 +171,7 @@ define <4 x half> @vfdiv_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fdiv.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fdiv.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -233,9 +227,7 @@ define <4 x half> @vfdiv_vf_v4f16_unmasked(<4 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fdiv.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fdiv.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -279,9 +271,7 @@ define <8 x half> @vfdiv_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fdiv.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fdiv.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -337,9 +327,7 @@ define <8 x half> @vfdiv_vf_v8f16_unmasked(<8 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fdiv.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fdiv.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -383,9 +371,7 @@ define <16 x half> @vfdiv_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %b, i3 ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fdiv.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fdiv.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -441,9 +427,7 @@ define <16 x half> @vfdiv_vf_v16f16_unmasked(<16 x half> %va, half %b, i32 zeroe ; ZVFHMIN-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fdiv.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fdiv.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -465,9 +449,7 @@ define <2 x float> @vfdiv_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fdiv.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fdiv.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -491,9 +473,7 @@ define <2 x float> @vfdiv_vf_v2f32_unmasked(<2 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fdiv.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fdiv.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -515,9 +495,7 @@ define <4 x float> @vfdiv_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -541,9 +519,7 @@ define <4 x float> @vfdiv_vf_v4f32_unmasked(<4 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -565,9 +541,7 @@ define <8 x float> @vfdiv_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fdiv.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fdiv.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -591,9 +565,7 @@ define <8 x float> @vfdiv_vf_v8f32_unmasked(<8 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fdiv.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fdiv.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -615,9 +587,7 @@ define <16 x float> @vfdiv_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %b, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fdiv.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fdiv.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -641,9 +611,7 @@ define <16 x float> @vfdiv_vf_v16f32_unmasked(<16 x float> %va, float %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fdiv.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fdiv.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -665,9 +633,7 @@ define <2 x double> @vfdiv_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fdiv.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fdiv.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -691,9 +657,7 @@ define <2 x double> @vfdiv_vf_v2f64_unmasked(<2 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fdiv.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fdiv.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -715,9 +679,7 @@ define <4 x double> @vfdiv_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fdiv.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fdiv.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -741,9 +703,7 @@ define <4 x double> @vfdiv_vf_v4f64_unmasked(<4 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fdiv.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fdiv.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -765,9 +725,7 @@ define <8 x double> @vfdiv_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fdiv.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fdiv.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -791,9 +749,7 @@ define <8 x double> @vfdiv_vf_v8f64_unmasked(<8 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fdiv.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fdiv.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -815,9 +771,7 @@ define <16 x double> @vfdiv_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fdiv.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fdiv.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -841,8 +795,6 @@ define <16 x double> @vfdiv_vf_v16f64_unmasked(<16 x double> %va, double %b, i32 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fdiv.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fdiv.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll index d7b89ee054af..0574773fb2fd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll @@ -51,9 +51,7 @@ define <2 x half> @vfma_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %b, <2 x ha ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %b, <2 x half> %c, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -111,9 +109,7 @@ define <2 x half> @vfma_vf_v2f16_unmasked(<2 x half> %va, half %b, <2 x half> %v ; ZVFHMIN-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -160,9 +156,7 @@ define <4 x half> @vfma_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %b, <4 x ha ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %b, <4 x half> %c, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -220,9 +214,7 @@ define <4 x half> @vfma_vf_v4f16_unmasked(<4 x half> %va, half %b, <4 x half> %v ; ZVFHMIN-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -269,9 +261,7 @@ define <8 x half> @vfma_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %b, <8 x ha ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v14 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %b, <8 x half> %c, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -329,9 +319,7 @@ define <8 x half> @vfma_vf_v8f16_unmasked(<8 x half> %va, half %b, <8 x half> %v ; ZVFHMIN-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -378,9 +366,7 @@ define <16 x half> @vfma_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %b, <16 ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v20 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %b, <16 x half> %c, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -438,9 +424,7 @@ define <16 x half> @vfma_vf_v16f16_unmasked(<16 x half> %va, half %b, <16 x half ; ZVFHMIN-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -463,9 +447,7 @@ define <2 x float> @vfma_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %b, <2 x ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %b, <2 x float> %c, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -489,9 +471,7 @@ define <2 x float> @vfma_vf_v2f32_unmasked(<2 x float> %va, float %b, <2 x float ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -514,9 +494,7 @@ define <4 x float> @vfma_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %b, <4 x ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %b, <4 x float> %c, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -540,9 +518,7 @@ define <4 x float> @vfma_vf_v4f32_unmasked(<4 x float> %va, float %b, <4 x float ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -565,9 +541,7 @@ define <8 x float> @vfma_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %b, <8 x ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %b, <8 x float> %c, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -591,9 +565,7 @@ define <8 x float> @vfma_vf_v8f32_unmasked(<8 x float> %va, float %b, <8 x float ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -616,9 +588,7 @@ define <16 x float> @vfma_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %b, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %b, <16 x float> %c, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -642,9 +612,7 @@ define <16 x float> @vfma_vf_v16f32_unmasked(<16 x float> %va, float %b, <16 x f ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -667,9 +635,7 @@ define <2 x double> @vfma_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %b, < ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %b, <2 x double> %c, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -693,9 +659,7 @@ define <2 x double> @vfma_vf_v2f64_unmasked(<2 x double> %va, double %b, <2 x do ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -718,9 +682,7 @@ define <4 x double> @vfma_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %b, < ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %b, <4 x double> %c, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -744,9 +706,7 @@ define <4 x double> @vfma_vf_v4f64_unmasked(<4 x double> %va, double %b, <4 x do ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -769,9 +729,7 @@ define <8 x double> @vfma_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %b, < ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %b, <8 x double> %c, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -795,9 +753,7 @@ define <8 x double> @vfma_vf_v8f64_unmasked(<8 x double> %va, double %b, <8 x do ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -824,9 +780,7 @@ define <15 x double> @vfma_vv_v15f64_unmasked(<15 x double> %va, <15 x double> % ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.fma.v15f64(<15 x double> %va, <15 x double> %b, <15 x double> %c, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.fma.v15f64(<15 x double> %va, <15 x double> %b, <15 x double> %c, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -853,9 +807,7 @@ define <16 x double> @vfma_vv_v16f64_unmasked(<16 x double> %va, <16 x double> % ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fma.v16f64(<16 x double> %va, <16 x double> %b, <16 x double> %c, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fma.v16f64(<16 x double> %va, <16 x double> %b, <16 x double> %c, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -879,9 +831,7 @@ define <16 x double> @vfma_vf_v16f64_unmasked(<16 x double> %va, double %b, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fma.v16f64(<16 x double> %va, <16 x double> %vb, <16 x double> %vc, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fma.v16f64(<16 x double> %va, <16 x double> %vb, <16 x double> %vc, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -1032,8 +982,6 @@ define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> % ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.fma.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.fma.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll index 78b83046738c..2d6e1fd02dee 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll @@ -16,9 +16,7 @@ define <2 x half> @vfmacc_vv_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -30,10 +28,8 @@ define <2 x half> @vfmacc_vv_v2f16_unmasked(<2 x half> %a, <2 x half> %b, <2 x h ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -46,9 +42,7 @@ define <2 x half> @vfmacc_vf_v2f16(<2 x half> %va, half %b, <2 x half> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -62,9 +56,7 @@ define <2 x half> @vfmacc_vf_v2f16_commute(<2 x half> %va, half %b, <2 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %va, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %va, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -78,10 +70,8 @@ define <2 x half> @vfmacc_vf_v2f16_unmasked(<2 x half> %va, half %b, <2 x half> ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -92,9 +82,7 @@ define <2 x half> @vfmacc_vv_v2f16_ta(<2 x half> %a, <2 x half> %b, <2 x half> % ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -108,9 +96,7 @@ define <2 x half> @vfmacc_vf_v2f16_ta(<2 x half> %va, half %b, <2 x half> %c, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -124,9 +110,7 @@ define <2 x half> @vfmacc_vf_v2f16_commute_ta(<2 x half> %va, half %b, <2 x half ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %va, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %va, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -143,9 +127,7 @@ define <4 x half> @vfmacc_vv_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -157,10 +139,8 @@ define <4 x half> @vfmacc_vv_v4f16_unmasked(<4 x half> %a, <4 x half> %b, <4 x h ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -173,9 +153,7 @@ define <4 x half> @vfmacc_vf_v4f16(<4 x half> %va, half %b, <4 x half> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -189,9 +167,7 @@ define <4 x half> @vfmacc_vf_v4f16_commute(<4 x half> %va, half %b, <4 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %va, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %va, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -205,10 +181,8 @@ define <4 x half> @vfmacc_vf_v4f16_unmasked(<4 x half> %va, half %b, <4 x half> ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -219,9 +193,7 @@ define <4 x half> @vfmacc_vv_v4f16_ta(<4 x half> %a, <4 x half> %b, <4 x half> % ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -235,9 +207,7 @@ define <4 x half> @vfmacc_vf_v4f16_ta(<4 x half> %va, half %b, <4 x half> %c, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -251,9 +221,7 @@ define <4 x half> @vfmacc_vf_v4f16_commute_ta(<4 x half> %va, half %b, <4 x half ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %va, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %va, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -270,9 +238,7 @@ define <8 x half> @vfmacc_vv_v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -284,10 +250,8 @@ define <8 x half> @vfmacc_vv_v8f16_unmasked(<8 x half> %a, <8 x half> %b, <8 x h ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -300,9 +264,7 @@ define <8 x half> @vfmacc_vf_v8f16(<8 x half> %va, half %b, <8 x half> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -316,9 +278,7 @@ define <8 x half> @vfmacc_vf_v8f16_commute(<8 x half> %va, half %b, <8 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %va, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %va, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -332,10 +292,8 @@ define <8 x half> @vfmacc_vf_v8f16_unmasked(<8 x half> %va, half %b, <8 x half> ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -346,9 +304,7 @@ define <8 x half> @vfmacc_vv_v8f16_ta(<8 x half> %a, <8 x half> %b, <8 x half> % ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -362,9 +318,7 @@ define <8 x half> @vfmacc_vf_v8f16_ta(<8 x half> %va, half %b, <8 x half> %c, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -378,9 +332,7 @@ define <8 x half> @vfmacc_vf_v8f16_commute_ta(<8 x half> %va, half %b, <8 x half ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %va, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %va, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -397,9 +349,7 @@ define <16 x half> @vfmacc_vv_v16f16(<16 x half> %a, <16 x half> %b, <16 x half> ; CHECK-NEXT: vfmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -411,10 +361,8 @@ define <16 x half> @vfmacc_vv_v16f16_unmasked(<16 x half> %a, <16 x half> %b, <1 ; CHECK-NEXT: vfmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -427,9 +375,7 @@ define <16 x half> @vfmacc_vf_v16f16(<16 x half> %va, half %b, <16 x half> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -443,9 +389,7 @@ define <16 x half> @vfmacc_vf_v16f16_commute(<16 x half> %va, half %b, <16 x hal ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %va, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %va, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -459,10 +403,8 @@ define <16 x half> @vfmacc_vf_v16f16_unmasked(<16 x half> %va, half %b, <16 x ha ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -473,9 +415,7 @@ define <16 x half> @vfmacc_vv_v16f16_ta(<16 x half> %a, <16 x half> %b, <16 x ha ; CHECK-NEXT: vfmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -489,9 +429,7 @@ define <16 x half> @vfmacc_vf_v16f16_ta(<16 x half> %va, half %b, <16 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -505,9 +443,7 @@ define <16 x half> @vfmacc_vf_v16f16_commute_ta(<16 x half> %va, half %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %va, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %va, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -524,9 +460,7 @@ define <32 x half> @vfmacc_vv_v32f16(<32 x half> %a, <32 x half> %b, <32 x half> ; CHECK-NEXT: vfmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -538,10 +472,8 @@ define <32 x half> @vfmacc_vv_v32f16_unmasked(<32 x half> %a, <32 x half> %b, <3 ; CHECK-NEXT: vfmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -554,9 +486,7 @@ define <32 x half> @vfmacc_vf_v32f16(<32 x half> %va, half %b, <32 x half> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -570,9 +500,7 @@ define <32 x half> @vfmacc_vf_v32f16_commute(<32 x half> %va, half %b, <32 x hal ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %va, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %va, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -586,10 +514,8 @@ define <32 x half> @vfmacc_vf_v32f16_unmasked(<32 x half> %va, half %b, <32 x ha ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -600,9 +526,7 @@ define <32 x half> @vfmacc_vv_v32f16_ta(<32 x half> %a, <32 x half> %b, <32 x ha ; CHECK-NEXT: vfmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -616,9 +540,7 @@ define <32 x half> @vfmacc_vf_v32f16_ta(<32 x half> %va, half %b, <32 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %va, <32 x half> %vb, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -632,9 +554,7 @@ define <32 x half> @vfmacc_vf_v32f16_commute_ta(<32 x half> %va, half %b, <32 x ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %va, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %va, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -651,9 +571,7 @@ define <2 x float> @vfmacc_vv_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -665,10 +583,8 @@ define <2 x float> @vfmacc_vv_v2f32_unmasked(<2 x float> %a, <2 x float> %b, <2 ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -681,9 +597,7 @@ define <2 x float> @vfmacc_vf_v2f32(<2 x float> %va, float %b, <2 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -697,9 +611,7 @@ define <2 x float> @vfmacc_vf_v2f32_commute(<2 x float> %va, float %b, <2 x floa ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %va, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %va, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -713,10 +625,8 @@ define <2 x float> @vfmacc_vf_v2f32_unmasked(<2 x float> %va, float %b, <2 x flo ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -727,9 +637,7 @@ define <2 x float> @vfmacc_vv_v2f32_ta(<2 x float> %a, <2 x float> %b, <2 x floa ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -743,9 +651,7 @@ define <2 x float> @vfmacc_vf_v2f32_ta(<2 x float> %va, float %b, <2 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -759,9 +665,7 @@ define <2 x float> @vfmacc_vf_v2f32_commute_ta(<2 x float> %va, float %b, <2 x f ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %va, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %va, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -778,9 +682,7 @@ define <4 x float> @vfmacc_vv_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -792,10 +694,8 @@ define <4 x float> @vfmacc_vv_v4f32_unmasked(<4 x float> %a, <4 x float> %b, <4 ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -808,9 +708,7 @@ define <4 x float> @vfmacc_vf_v4f32(<4 x float> %va, float %b, <4 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -824,9 +722,7 @@ define <4 x float> @vfmacc_vf_v4f32_commute(<4 x float> %va, float %b, <4 x floa ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %va, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %va, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -840,10 +736,8 @@ define <4 x float> @vfmacc_vf_v4f32_unmasked(<4 x float> %va, float %b, <4 x flo ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -854,9 +748,7 @@ define <4 x float> @vfmacc_vv_v4f32_ta(<4 x float> %a, <4 x float> %b, <4 x floa ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -870,9 +762,7 @@ define <4 x float> @vfmacc_vf_v4f32_ta(<4 x float> %va, float %b, <4 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -886,9 +776,7 @@ define <4 x float> @vfmacc_vf_v4f32_commute_ta(<4 x float> %va, float %b, <4 x f ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %va, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %va, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -905,9 +793,7 @@ define <8 x float> @vfmacc_vv_v8f32(<8 x float> %a, <8 x float> %b, <8 x float> ; CHECK-NEXT: vfmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -919,10 +805,8 @@ define <8 x float> @vfmacc_vv_v8f32_unmasked(<8 x float> %a, <8 x float> %b, <8 ; CHECK-NEXT: vfmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -935,9 +819,7 @@ define <8 x float> @vfmacc_vf_v8f32(<8 x float> %va, float %b, <8 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -951,9 +833,7 @@ define <8 x float> @vfmacc_vf_v8f32_commute(<8 x float> %va, float %b, <8 x floa ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %va, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %va, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -967,10 +847,8 @@ define <8 x float> @vfmacc_vf_v8f32_unmasked(<8 x float> %va, float %b, <8 x flo ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -981,9 +859,7 @@ define <8 x float> @vfmacc_vv_v8f32_ta(<8 x float> %a, <8 x float> %b, <8 x floa ; CHECK-NEXT: vfmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -997,9 +873,7 @@ define <8 x float> @vfmacc_vf_v8f32_ta(<8 x float> %va, float %b, <8 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1013,9 +887,7 @@ define <8 x float> @vfmacc_vf_v8f32_commute_ta(<8 x float> %va, float %b, <8 x f ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %va, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %va, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1032,9 +904,7 @@ define <16 x float> @vfmacc_vv_v16f32(<16 x float> %a, <16 x float> %b, <16 x fl ; CHECK-NEXT: vfmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1046,10 +916,8 @@ define <16 x float> @vfmacc_vv_v16f32_unmasked(<16 x float> %a, <16 x float> %b, ; CHECK-NEXT: vfmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1062,9 +930,7 @@ define <16 x float> @vfmacc_vf_v16f32(<16 x float> %va, float %b, <16 x float> % ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1078,9 +944,7 @@ define <16 x float> @vfmacc_vf_v16f32_commute(<16 x float> %va, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %va, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %va, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1094,10 +958,8 @@ define <16 x float> @vfmacc_vf_v16f32_unmasked(<16 x float> %va, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1108,9 +970,7 @@ define <16 x float> @vfmacc_vv_v16f32_ta(<16 x float> %a, <16 x float> %b, <16 x ; CHECK-NEXT: vfmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1124,9 +984,7 @@ define <16 x float> @vfmacc_vf_v16f32_ta(<16 x float> %va, float %b, <16 x float ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1140,9 +998,7 @@ define <16 x float> @vfmacc_vf_v16f32_commute_ta(<16 x float> %va, float %b, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %va, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %va, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1159,9 +1015,7 @@ define <2 x double> @vfmacc_vv_v2f64(<2 x double> %a, <2 x double> %b, <2 x doub ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1173,10 +1027,8 @@ define <2 x double> @vfmacc_vv_v2f64_unmasked(<2 x double> %a, <2 x double> %b, ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1189,9 +1041,7 @@ define <2 x double> @vfmacc_vf_v2f64(<2 x double> %va, double %b, <2 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1205,9 +1055,7 @@ define <2 x double> @vfmacc_vf_v2f64_commute(<2 x double> %va, double %b, <2 x d ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %va, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %va, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1221,10 +1069,8 @@ define <2 x double> @vfmacc_vf_v2f64_unmasked(<2 x double> %va, double %b, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1235,9 +1081,7 @@ define <2 x double> @vfmacc_vv_v2f64_ta(<2 x double> %a, <2 x double> %b, <2 x d ; CHECK-NEXT: vfmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1251,9 +1095,7 @@ define <2 x double> @vfmacc_vf_v2f64_ta(<2 x double> %va, double %b, <2 x double ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1267,9 +1109,7 @@ define <2 x double> @vfmacc_vf_v2f64_commute_ta(<2 x double> %va, double %b, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %va, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %va, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1286,9 +1126,7 @@ define <4 x double> @vfmacc_vv_v4f64(<4 x double> %a, <4 x double> %b, <4 x doub ; CHECK-NEXT: vfmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1300,10 +1138,8 @@ define <4 x double> @vfmacc_vv_v4f64_unmasked(<4 x double> %a, <4 x double> %b, ; CHECK-NEXT: vfmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1316,9 +1152,7 @@ define <4 x double> @vfmacc_vf_v4f64(<4 x double> %va, double %b, <4 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1332,9 +1166,7 @@ define <4 x double> @vfmacc_vf_v4f64_commute(<4 x double> %va, double %b, <4 x d ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %va, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %va, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1348,10 +1180,8 @@ define <4 x double> @vfmacc_vf_v4f64_unmasked(<4 x double> %va, double %b, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1362,9 +1192,7 @@ define <4 x double> @vfmacc_vv_v4f64_ta(<4 x double> %a, <4 x double> %b, <4 x d ; CHECK-NEXT: vfmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1378,9 +1206,7 @@ define <4 x double> @vfmacc_vf_v4f64_ta(<4 x double> %va, double %b, <4 x double ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1394,9 +1220,7 @@ define <4 x double> @vfmacc_vf_v4f64_commute_ta(<4 x double> %va, double %b, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %va, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %va, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1413,9 +1237,7 @@ define <8 x double> @vfmacc_vv_v8f64(<8 x double> %a, <8 x double> %b, <8 x doub ; CHECK-NEXT: vfmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1427,10 +1249,8 @@ define <8 x double> @vfmacc_vv_v8f64_unmasked(<8 x double> %a, <8 x double> %b, ; CHECK-NEXT: vfmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1443,9 +1263,7 @@ define <8 x double> @vfmacc_vf_v8f64(<8 x double> %va, double %b, <8 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1459,9 +1277,7 @@ define <8 x double> @vfmacc_vf_v8f64_commute(<8 x double> %va, double %b, <8 x d ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %va, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %va, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1475,10 +1291,8 @@ define <8 x double> @vfmacc_vf_v8f64_unmasked(<8 x double> %va, double %b, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1489,9 +1303,7 @@ define <8 x double> @vfmacc_vv_v8f64_ta(<8 x double> %a, <8 x double> %b, <8 x d ; CHECK-NEXT: vfmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1505,9 +1317,7 @@ define <8 x double> @vfmacc_vf_v8f64_ta(<8 x double> %va, double %b, <8 x double ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1521,9 +1331,7 @@ define <8 x double> @vfmacc_vf_v8f64_commute_ta(<8 x double> %va, double %b, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %va, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %va, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll index 86218ddb04bd..ffa88e28d7dc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll @@ -48,9 +48,7 @@ define <2 x half> @vfmax_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.maxnum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.maxnum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -94,9 +92,7 @@ define <4 x half> @vfmax_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.maxnum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.maxnum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -140,9 +136,7 @@ define <8 x half> @vfmax_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.maxnum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.maxnum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -186,9 +180,7 @@ define <16 x half> @vfmax_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.maxnum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.maxnum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -210,9 +202,7 @@ define <2 x float> @vfmax_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.maxnum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.maxnum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -234,9 +224,7 @@ define <4 x float> @vfmax_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.maxnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.maxnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -258,9 +246,7 @@ define <8 x float> @vfmax_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.maxnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.maxnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -282,9 +268,7 @@ define <16 x float> @vfmax_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.maxnum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.maxnum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -306,9 +290,7 @@ define <2 x double> @vfmax_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.maxnum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.maxnum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -330,9 +312,7 @@ define <4 x double> @vfmax_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.maxnum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.maxnum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -354,9 +334,7 @@ define <8 x double> @vfmax_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.maxnum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.maxnum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -378,9 +356,7 @@ define <15 x double> @vfmax_vv_v15f64_unmasked(<15 x double> %va, <15 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.maxnum.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.maxnum.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -402,9 +378,7 @@ define <16 x double> @vfmax_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.maxnum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.maxnum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -476,8 +450,6 @@ define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmax.vv v16, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.maxnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.maxnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll index 8b8049ea6c62..17f851e172f8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll @@ -48,9 +48,7 @@ define <2 x half> @vfmin_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.minnum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.minnum.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -94,9 +92,7 @@ define <4 x half> @vfmin_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.minnum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.minnum.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -140,9 +136,7 @@ define <8 x half> @vfmin_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %vb, i32 z ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.minnum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.minnum.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -186,9 +180,7 @@ define <16 x half> @vfmin_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %vb, i ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.minnum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.minnum.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -210,9 +202,7 @@ define <2 x float> @vfmin_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %vb, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.minnum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.minnum.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -234,9 +224,7 @@ define <4 x float> @vfmin_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %vb, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.minnum.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -258,9 +246,7 @@ define <8 x float> @vfmin_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %vb, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.minnum.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -282,9 +268,7 @@ define <16 x float> @vfmin_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %vb ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.minnum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.minnum.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -306,9 +290,7 @@ define <2 x double> @vfmin_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %vb, ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.minnum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.minnum.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -330,9 +312,7 @@ define <4 x double> @vfmin_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %vb, ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.minnum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.minnum.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -354,9 +334,7 @@ define <8 x double> @vfmin_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %vb, ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.minnum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.minnum.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -378,9 +356,7 @@ define <15 x double> @vfmin_vv_v15f64_unmasked(<15 x double> %va, <15 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.minnum.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.minnum.v15f64(<15 x double> %va, <15 x double> %vb, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -402,9 +378,7 @@ define <16 x double> @vfmin_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.minnum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.minnum.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -476,8 +450,6 @@ define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmin.vv v16, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.minnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.minnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll index 3960d061fd66..fc6578225aa6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll @@ -16,10 +16,8 @@ define <2 x half> @vfmsac_vv_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -31,11 +29,9 @@ define <2 x half> @vfmsac_vv_v2f16_unmasked(<2 x half> %a, <2 x half> %b, <2 x h ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -48,10 +44,8 @@ define <2 x half> @vfmsac_vf_v2f16(<2 x half> %a, half %b, <2 x half> %c, <2 x i ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %vb, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %vb, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -65,10 +59,8 @@ define <2 x half> @vfmsac_vf_v2f16_commute(<2 x half> %a, half %b, <2 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %a, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %a, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -82,11 +74,9 @@ define <2 x half> @vfmsac_vf_v2f16_unmasked(<2 x half> %a, half %b, <2 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %vb, <2 x half> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %vb, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -97,10 +87,8 @@ define <2 x half> @vfmsac_vv_v2f16_ta(<2 x half> %a, <2 x half> %b, <2 x half> % ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -114,10 +102,8 @@ define <2 x half> @vfmsac_vf_v2f16_ta(<2 x half> %a, half %b, <2 x half> %c, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %vb, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %a, <2 x half> %vb, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -131,10 +117,8 @@ define <2 x half> @vfmsac_vf_v2f16_commute_ta(<2 x half> %a, half %b, <2 x half> ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %a, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %a, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -151,10 +135,8 @@ define <4 x half> @vfmsac_vv_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -166,11 +148,9 @@ define <4 x half> @vfmsac_vv_v4f16_unmasked(<4 x half> %a, <4 x half> %b, <4 x h ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -183,10 +163,8 @@ define <4 x half> @vfmsac_vf_v4f16(<4 x half> %a, half %b, <4 x half> %c, <4 x i ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %vb, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %vb, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -200,10 +178,8 @@ define <4 x half> @vfmsac_vf_v4f16_commute(<4 x half> %a, half %b, <4 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %a, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %a, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -217,11 +193,9 @@ define <4 x half> @vfmsac_vf_v4f16_unmasked(<4 x half> %a, half %b, <4 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %vb, <4 x half> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %vb, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -232,10 +206,8 @@ define <4 x half> @vfmsac_vv_v4f16_ta(<4 x half> %a, <4 x half> %b, <4 x half> % ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -249,10 +221,8 @@ define <4 x half> @vfmsac_vf_v4f16_ta(<4 x half> %a, half %b, <4 x half> %c, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %vb, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %a, <4 x half> %vb, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -266,10 +236,8 @@ define <4 x half> @vfmsac_vf_v4f16_commute_ta(<4 x half> %a, half %b, <4 x half> ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %a, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %a, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -286,10 +254,8 @@ define <8 x half> @vfmsac_vv_v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -301,11 +267,9 @@ define <8 x half> @vfmsac_vv_v8f16_unmasked(<8 x half> %a, <8 x half> %b, <8 x h ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -318,10 +282,8 @@ define <8 x half> @vfmsac_vf_v8f16(<8 x half> %a, half %b, <8 x half> %c, <8 x i ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %vb, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %vb, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -335,10 +297,8 @@ define <8 x half> @vfmsac_vf_v8f16_commute(<8 x half> %a, half %b, <8 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %a, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %a, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -352,11 +312,9 @@ define <8 x half> @vfmsac_vf_v8f16_unmasked(<8 x half> %a, half %b, <8 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %vb, <8 x half> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %vb, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -367,10 +325,8 @@ define <8 x half> @vfmsac_vv_v8f16_ta(<8 x half> %a, <8 x half> %b, <8 x half> % ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -384,10 +340,8 @@ define <8 x half> @vfmsac_vf_v8f16_ta(<8 x half> %a, half %b, <8 x half> %c, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %vb, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %a, <8 x half> %vb, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -401,10 +355,8 @@ define <8 x half> @vfmsac_vf_v8f16_commute_ta(<8 x half> %a, half %b, <8 x half> ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %a, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %a, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -421,10 +373,8 @@ define <16 x half> @vfmsac_vv_v16f16(<16 x half> %a, <16 x half> %b, <16 x half> ; CHECK-NEXT: vfmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -436,11 +386,9 @@ define <16 x half> @vfmsac_vv_v16f16_unmasked(<16 x half> %a, <16 x half> %b, <1 ; CHECK-NEXT: vfmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -453,10 +401,8 @@ define <16 x half> @vfmsac_vf_v16f16(<16 x half> %a, half %b, <16 x half> %c, <1 ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %vb, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %vb, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -470,10 +416,8 @@ define <16 x half> @vfmsac_vf_v16f16_commute(<16 x half> %a, half %b, <16 x half ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %a, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %a, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -487,11 +431,9 @@ define <16 x half> @vfmsac_vf_v16f16_unmasked(<16 x half> %a, half %b, <16 x hal ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %vb, <16 x half> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %vb, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -502,10 +444,8 @@ define <16 x half> @vfmsac_vv_v16f16_ta(<16 x half> %a, <16 x half> %b, <16 x ha ; CHECK-NEXT: vfmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %b, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -519,10 +459,8 @@ define <16 x half> @vfmsac_vf_v16f16_ta(<16 x half> %a, half %b, <16 x half> %c, ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %vb, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %a, <16 x half> %vb, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -536,10 +474,8 @@ define <16 x half> @vfmsac_vf_v16f16_commute_ta(<16 x half> %a, half %b, <16 x h ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %a, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %a, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -556,10 +492,8 @@ define <32 x half> @vfmsac_vv_v32f16(<32 x half> %a, <32 x half> %b, <32 x half> ; CHECK-NEXT: vfmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -571,11 +505,9 @@ define <32 x half> @vfmsac_vv_v32f16_unmasked(<32 x half> %a, <32 x half> %b, <3 ; CHECK-NEXT: vfmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %negc, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -588,10 +520,8 @@ define <32 x half> @vfmsac_vf_v32f16(<32 x half> %a, half %b, <32 x half> %c, <3 ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %vb, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %vb, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -605,10 +535,8 @@ define <32 x half> @vfmsac_vf_v32f16_commute(<32 x half> %a, half %b, <32 x half ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %a, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %a, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -622,11 +550,9 @@ define <32 x half> @vfmsac_vf_v32f16_unmasked(<32 x half> %a, half %b, <32 x hal ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %vb, <32 x half> %negc, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %vb, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -637,10 +563,8 @@ define <32 x half> @vfmsac_vv_v32f16_ta(<32 x half> %a, <32 x half> %b, <32 x ha ; CHECK-NEXT: vfmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %b, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -654,10 +578,8 @@ define <32 x half> @vfmsac_vf_v32f16_ta(<32 x half> %a, half %b, <32 x half> %c, ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %vb, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %a, <32 x half> %vb, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -671,10 +593,8 @@ define <32 x half> @vfmsac_vf_v32f16_commute_ta(<32 x half> %a, half %b, <32 x h ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %a, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %a, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -691,10 +611,8 @@ define <2 x float> @vfmsac_vv_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -706,11 +624,9 @@ define <2 x float> @vfmsac_vv_v2f32_unmasked(<2 x float> %a, <2 x float> %b, <2 ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -723,10 +639,8 @@ define <2 x float> @vfmsac_vf_v2f32(<2 x float> %a, float %b, <2 x float> %c, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %vb, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %vb, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -740,10 +654,8 @@ define <2 x float> @vfmsac_vf_v2f32_commute(<2 x float> %a, float %b, <2 x float ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %a, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %a, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -757,11 +669,9 @@ define <2 x float> @vfmsac_vf_v2f32_unmasked(<2 x float> %a, float %b, <2 x floa ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %vb, <2 x float> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %vb, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -772,10 +682,8 @@ define <2 x float> @vfmsac_vv_v2f32_ta(<2 x float> %a, <2 x float> %b, <2 x floa ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -789,10 +697,8 @@ define <2 x float> @vfmsac_vf_v2f32_ta(<2 x float> %a, float %b, <2 x float> %c, ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %vb, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %a, <2 x float> %vb, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -806,10 +712,8 @@ define <2 x float> @vfmsac_vf_v2f32_commute_ta(<2 x float> %a, float %b, <2 x fl ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %a, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %a, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -826,10 +730,8 @@ define <4 x float> @vfmsac_vv_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -841,11 +743,9 @@ define <4 x float> @vfmsac_vv_v4f32_unmasked(<4 x float> %a, <4 x float> %b, <4 ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -858,10 +758,8 @@ define <4 x float> @vfmsac_vf_v4f32(<4 x float> %a, float %b, <4 x float> %c, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %vb, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %vb, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -875,10 +773,8 @@ define <4 x float> @vfmsac_vf_v4f32_commute(<4 x float> %a, float %b, <4 x float ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %a, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %a, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -892,11 +788,9 @@ define <4 x float> @vfmsac_vf_v4f32_unmasked(<4 x float> %a, float %b, <4 x floa ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %vb, <4 x float> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %vb, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -907,10 +801,8 @@ define <4 x float> @vfmsac_vv_v4f32_ta(<4 x float> %a, <4 x float> %b, <4 x floa ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -924,10 +816,8 @@ define <4 x float> @vfmsac_vf_v4f32_ta(<4 x float> %a, float %b, <4 x float> %c, ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %vb, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %a, <4 x float> %vb, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -941,10 +831,8 @@ define <4 x float> @vfmsac_vf_v4f32_commute_ta(<4 x float> %a, float %b, <4 x fl ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %a, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %a, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -961,10 +849,8 @@ define <8 x float> @vfmsac_vv_v8f32(<8 x float> %a, <8 x float> %b, <8 x float> ; CHECK-NEXT: vfmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -976,11 +862,9 @@ define <8 x float> @vfmsac_vv_v8f32_unmasked(<8 x float> %a, <8 x float> %b, <8 ; CHECK-NEXT: vfmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -993,10 +877,8 @@ define <8 x float> @vfmsac_vf_v8f32(<8 x float> %a, float %b, <8 x float> %c, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %vb, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %vb, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1010,10 +892,8 @@ define <8 x float> @vfmsac_vf_v8f32_commute(<8 x float> %a, float %b, <8 x float ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %a, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %a, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1027,11 +907,9 @@ define <8 x float> @vfmsac_vf_v8f32_unmasked(<8 x float> %a, float %b, <8 x floa ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %vb, <8 x float> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %vb, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1042,10 +920,8 @@ define <8 x float> @vfmsac_vv_v8f32_ta(<8 x float> %a, <8 x float> %b, <8 x floa ; CHECK-NEXT: vfmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %b, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1059,10 +935,8 @@ define <8 x float> @vfmsac_vf_v8f32_ta(<8 x float> %a, float %b, <8 x float> %c, ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %vb, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %a, <8 x float> %vb, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1076,10 +950,8 @@ define <8 x float> @vfmsac_vf_v8f32_commute_ta(<8 x float> %a, float %b, <8 x fl ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %a, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %a, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1096,10 +968,8 @@ define <16 x float> @vfmsac_vv_v16f32(<16 x float> %a, <16 x float> %b, <16 x fl ; CHECK-NEXT: vfmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1111,11 +981,9 @@ define <16 x float> @vfmsac_vv_v16f32_unmasked(<16 x float> %a, <16 x float> %b, ; CHECK-NEXT: vfmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1128,10 +996,8 @@ define <16 x float> @vfmsac_vf_v16f32(<16 x float> %a, float %b, <16 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %vb, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %vb, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1145,10 +1011,8 @@ define <16 x float> @vfmsac_vf_v16f32_commute(<16 x float> %a, float %b, <16 x f ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %a, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %a, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1162,11 +1026,9 @@ define <16 x float> @vfmsac_vf_v16f32_unmasked(<16 x float> %a, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %vb, <16 x float> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %vb, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1177,10 +1039,8 @@ define <16 x float> @vfmsac_vv_v16f32_ta(<16 x float> %a, <16 x float> %b, <16 x ; CHECK-NEXT: vfmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1194,10 +1054,8 @@ define <16 x float> @vfmsac_vf_v16f32_ta(<16 x float> %a, float %b, <16 x float> ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %vb, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %a, <16 x float> %vb, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1211,10 +1069,8 @@ define <16 x float> @vfmsac_vf_v16f32_commute_ta(<16 x float> %a, float %b, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %a, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %a, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1231,10 +1087,8 @@ define <2 x double> @vfmsac_vv_v2f64(<2 x double> %a, <2 x double> %b, <2 x doub ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1246,11 +1100,9 @@ define <2 x double> @vfmsac_vv_v2f64_unmasked(<2 x double> %a, <2 x double> %b, ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1263,10 +1115,8 @@ define <2 x double> @vfmsac_vf_v2f64(<2 x double> %a, double %b, <2 x double> %c ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %vb, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %vb, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1280,10 +1130,8 @@ define <2 x double> @vfmsac_vf_v2f64_commute(<2 x double> %a, double %b, <2 x do ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %a, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %a, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1297,11 +1145,9 @@ define <2 x double> @vfmsac_vf_v2f64_unmasked(<2 x double> %a, double %b, <2 x d ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %vb, <2 x double> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %vb, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1312,10 +1158,8 @@ define <2 x double> @vfmsac_vv_v2f64_ta(<2 x double> %a, <2 x double> %b, <2 x d ; CHECK-NEXT: vfmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1329,10 +1173,8 @@ define <2 x double> @vfmsac_vf_v2f64_ta(<2 x double> %a, double %b, <2 x double> ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %vb, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %a, <2 x double> %vb, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1346,10 +1188,8 @@ define <2 x double> @vfmsac_vf_v2f64_commute_ta(<2 x double> %a, double %b, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %a, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %a, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1366,10 +1206,8 @@ define <4 x double> @vfmsac_vv_v4f64(<4 x double> %a, <4 x double> %b, <4 x doub ; CHECK-NEXT: vfmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1381,11 +1219,9 @@ define <4 x double> @vfmsac_vv_v4f64_unmasked(<4 x double> %a, <4 x double> %b, ; CHECK-NEXT: vfmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1398,10 +1234,8 @@ define <4 x double> @vfmsac_vf_v4f64(<4 x double> %a, double %b, <4 x double> %c ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %vb, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %vb, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1415,10 +1249,8 @@ define <4 x double> @vfmsac_vf_v4f64_commute(<4 x double> %a, double %b, <4 x do ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %a, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %a, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1432,11 +1264,9 @@ define <4 x double> @vfmsac_vf_v4f64_unmasked(<4 x double> %a, double %b, <4 x d ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %vb, <4 x double> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %vb, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1447,10 +1277,8 @@ define <4 x double> @vfmsac_vv_v4f64_ta(<4 x double> %a, <4 x double> %b, <4 x d ; CHECK-NEXT: vfmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1464,10 +1292,8 @@ define <4 x double> @vfmsac_vf_v4f64_ta(<4 x double> %a, double %b, <4 x double> ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %vb, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %a, <4 x double> %vb, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1481,10 +1307,8 @@ define <4 x double> @vfmsac_vf_v4f64_commute_ta(<4 x double> %a, double %b, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %a, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %a, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1501,10 +1325,8 @@ define <8 x double> @vfmsac_vv_v8f64(<8 x double> %a, <8 x double> %b, <8 x doub ; CHECK-NEXT: vfmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1516,11 +1338,9 @@ define <8 x double> @vfmsac_vv_v8f64_unmasked(<8 x double> %a, <8 x double> %b, ; CHECK-NEXT: vfmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1533,10 +1353,8 @@ define <8 x double> @vfmsac_vf_v8f64(<8 x double> %a, double %b, <8 x double> %c ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %vb, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %vb, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1550,10 +1368,8 @@ define <8 x double> @vfmsac_vf_v8f64_commute(<8 x double> %a, double %b, <8 x do ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %a, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %a, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1567,11 +1383,9 @@ define <8 x double> @vfmsac_vf_v8f64_unmasked(<8 x double> %a, double %b, <8 x d ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %vb, <8 x double> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %vb, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1582,10 +1396,8 @@ define <8 x double> @vfmsac_vv_v8f64_ta(<8 x double> %a, <8 x double> %b, <8 x d ; CHECK-NEXT: vfmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %b, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1599,10 +1411,8 @@ define <8 x double> @vfmsac_vf_v8f64_ta(<8 x double> %a, double %b, <8 x double> ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %vb, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %a, <8 x double> %vb, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1616,10 +1426,8 @@ define <8 x double> @vfmsac_vf_v8f64_commute_ta(<8 x double> %a, double %b, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %a, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %a, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll index 4e06263f4e8b..64ce0a12de8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll @@ -48,9 +48,7 @@ define <2 x half> @vfmul_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fmul.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fmul.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -106,9 +104,7 @@ define <2 x half> @vfmul_vf_v2f16_unmasked(<2 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fmul.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fmul.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -175,9 +171,7 @@ define <4 x half> @vfmul_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fmul.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fmul.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -233,9 +227,7 @@ define <4 x half> @vfmul_vf_v4f16_unmasked(<4 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fmul.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fmul.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -279,9 +271,7 @@ define <8 x half> @vfmul_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fmul.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fmul.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -337,9 +327,7 @@ define <8 x half> @vfmul_vf_v8f16_unmasked(<8 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fmul.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fmul.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -383,9 +371,7 @@ define <16 x half> @vfmul_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %b, i3 ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fmul.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fmul.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -441,9 +427,7 @@ define <16 x half> @vfmul_vf_v16f16_unmasked(<16 x half> %va, half %b, i32 zeroe ; ZVFHMIN-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fmul.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fmul.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -465,9 +449,7 @@ define <2 x float> @vfmul_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fmul.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fmul.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -491,9 +473,7 @@ define <2 x float> @vfmul_vf_v2f32_unmasked(<2 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fmul.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fmul.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -515,9 +495,7 @@ define <4 x float> @vfmul_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -541,9 +519,7 @@ define <4 x float> @vfmul_vf_v4f32_unmasked(<4 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fmul.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -565,9 +541,7 @@ define <8 x float> @vfmul_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fmul.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fmul.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -591,9 +565,7 @@ define <8 x float> @vfmul_vf_v8f32_unmasked(<8 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fmul.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fmul.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -615,9 +587,7 @@ define <16 x float> @vfmul_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %b, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fmul.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fmul.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -641,9 +611,7 @@ define <16 x float> @vfmul_vf_v16f32_unmasked(<16 x float> %va, float %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fmul.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fmul.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -665,9 +633,7 @@ define <2 x double> @vfmul_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fmul.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fmul.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -691,9 +657,7 @@ define <2 x double> @vfmul_vf_v2f64_unmasked(<2 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fmul.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fmul.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -715,9 +679,7 @@ define <4 x double> @vfmul_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fmul.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fmul.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -741,9 +703,7 @@ define <4 x double> @vfmul_vf_v4f64_unmasked(<4 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fmul.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fmul.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -765,9 +725,7 @@ define <8 x double> @vfmul_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fmul.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fmul.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -791,9 +749,7 @@ define <8 x double> @vfmul_vf_v8f64_unmasked(<8 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fmul.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fmul.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -815,9 +771,7 @@ define <16 x double> @vfmul_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fmul.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fmul.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -841,8 +795,6 @@ define <16 x double> @vfmul_vf_v16f64_unmasked(<16 x double> %va, double %b, i32 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fmul.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fmul.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll index 4af566cb5f55..288efb0f1fc2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll @@ -23,9 +23,7 @@ define <2 x half> @vfma_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %b, <2 x ha ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fmuladd.v2f16(<2 x half> %va, <2 x half> %b, <2 x half> %c, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fmuladd.v2f16(<2 x half> %va, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -49,9 +47,7 @@ define <2 x half> @vfma_vf_v2f16_unmasked(<2 x half> %va, half %b, <2 x half> %v ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fmuladd.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fmuladd.v2f16(<2 x half> %va, <2 x half> %vb, <2 x half> %vc, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -74,9 +70,7 @@ define <4 x half> @vfma_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %b, <4 x ha ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fmuladd.v4f16(<4 x half> %va, <4 x half> %b, <4 x half> %c, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fmuladd.v4f16(<4 x half> %va, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -100,9 +94,7 @@ define <4 x half> @vfma_vf_v4f16_unmasked(<4 x half> %va, half %b, <4 x half> %v ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fmuladd.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fmuladd.v4f16(<4 x half> %va, <4 x half> %vb, <4 x half> %vc, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -125,9 +117,7 @@ define <8 x half> @vfma_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %b, <8 x ha ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fmuladd.v8f16(<8 x half> %va, <8 x half> %b, <8 x half> %c, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fmuladd.v8f16(<8 x half> %va, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -151,9 +141,7 @@ define <8 x half> @vfma_vf_v8f16_unmasked(<8 x half> %va, half %b, <8 x half> %v ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fmuladd.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fmuladd.v8f16(<8 x half> %va, <8 x half> %vb, <8 x half> %vc, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -176,9 +164,7 @@ define <16 x half> @vfma_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %b, <16 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fmuladd.v16f16(<16 x half> %va, <16 x half> %b, <16 x half> %c, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fmuladd.v16f16(<16 x half> %va, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -202,9 +188,7 @@ define <16 x half> @vfma_vf_v16f16_unmasked(<16 x half> %va, half %b, <16 x half ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fmuladd.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fmuladd.v16f16(<16 x half> %va, <16 x half> %vb, <16 x half> %vc, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -227,9 +211,7 @@ define <2 x float> @vfma_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %b, <2 x ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fmuladd.v2f32(<2 x float> %va, <2 x float> %b, <2 x float> %c, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fmuladd.v2f32(<2 x float> %va, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -253,9 +235,7 @@ define <2 x float> @vfma_vf_v2f32_unmasked(<2 x float> %va, float %b, <2 x float ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fmuladd.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fmuladd.v2f32(<2 x float> %va, <2 x float> %vb, <2 x float> %vc, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -278,9 +258,7 @@ define <4 x float> @vfma_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %b, <4 x ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float> %va, <4 x float> %b, <4 x float> %c, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float> %va, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -304,9 +282,7 @@ define <4 x float> @vfma_vf_v4f32_unmasked(<4 x float> %va, float %b, <4 x float ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fmuladd.v4f32(<4 x float> %va, <4 x float> %vb, <4 x float> %vc, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -329,9 +305,7 @@ define <8 x float> @vfma_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %b, <8 x ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fmuladd.v8f32(<8 x float> %va, <8 x float> %b, <8 x float> %c, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fmuladd.v8f32(<8 x float> %va, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -355,9 +329,7 @@ define <8 x float> @vfma_vf_v8f32_unmasked(<8 x float> %va, float %b, <8 x float ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fmuladd.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fmuladd.v8f32(<8 x float> %va, <8 x float> %vb, <8 x float> %vc, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -380,9 +352,7 @@ define <16 x float> @vfma_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %b, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fmuladd.v16f32(<16 x float> %va, <16 x float> %b, <16 x float> %c, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fmuladd.v16f32(<16 x float> %va, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -406,9 +376,7 @@ define <16 x float> @vfma_vf_v16f32_unmasked(<16 x float> %va, float %b, <16 x f ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fmuladd.v16f32(<16 x float> %va, <16 x float> %vb, <16 x float> %vc, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -431,9 +399,7 @@ define <2 x double> @vfma_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %b, < ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fmuladd.v2f64(<2 x double> %va, <2 x double> %b, <2 x double> %c, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fmuladd.v2f64(<2 x double> %va, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -457,9 +423,7 @@ define <2 x double> @vfma_vf_v2f64_unmasked(<2 x double> %va, double %b, <2 x do ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fmuladd.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fmuladd.v2f64(<2 x double> %va, <2 x double> %vb, <2 x double> %vc, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -482,9 +446,7 @@ define <4 x double> @vfma_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %b, < ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fmuladd.v4f64(<4 x double> %va, <4 x double> %b, <4 x double> %c, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fmuladd.v4f64(<4 x double> %va, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -508,9 +470,7 @@ define <4 x double> @vfma_vf_v4f64_unmasked(<4 x double> %va, double %b, <4 x do ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fmuladd.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fmuladd.v4f64(<4 x double> %va, <4 x double> %vb, <4 x double> %vc, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -533,9 +493,7 @@ define <8 x double> @vfma_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %b, < ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fmuladd.v8f64(<8 x double> %va, <8 x double> %b, <8 x double> %c, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fmuladd.v8f64(<8 x double> %va, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -559,9 +517,7 @@ define <8 x double> @vfma_vf_v8f64_unmasked(<8 x double> %va, double %b, <8 x do ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fmuladd.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fmuladd.v8f64(<8 x double> %va, <8 x double> %vb, <8 x double> %vc, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -588,9 +544,7 @@ define <15 x double> @vfma_vv_v15f64_unmasked(<15 x double> %va, <15 x double> % ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.fmuladd.v15f64(<15 x double> %va, <15 x double> %b, <15 x double> %c, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.fmuladd.v15f64(<15 x double> %va, <15 x double> %b, <15 x double> %c, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -617,9 +571,7 @@ define <16 x double> @vfma_vv_v16f64_unmasked(<16 x double> %va, <16 x double> % ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fmuladd.v16f64(<16 x double> %va, <16 x double> %b, <16 x double> %c, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fmuladd.v16f64(<16 x double> %va, <16 x double> %b, <16 x double> %c, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -643,9 +595,7 @@ define <16 x double> @vfma_vf_v16f64_unmasked(<16 x double> %va, double %b, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fmuladd.v16f64(<16 x double> %va, <16 x double> %vb, <16 x double> %vc, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fmuladd.v16f64(<16 x double> %va, <16 x double> %vb, <16 x double> %vc, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -796,8 +746,6 @@ define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> % ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll index 3d037a5589a1..c36ec25c04f9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll @@ -46,9 +46,7 @@ define <2 x half> @vfneg_vv_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -90,9 +88,7 @@ define <4 x half> @vfneg_vv_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -134,9 +130,7 @@ define <8 x half> @vfneg_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -178,9 +172,7 @@ define <16 x half> @vfneg_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -202,9 +194,7 @@ define <2 x float> @vfneg_vv_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -226,9 +216,7 @@ define <4 x float> @vfneg_vv_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -250,9 +238,7 @@ define <8 x float> @vfneg_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -274,9 +260,7 @@ define <16 x float> @vfneg_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -298,9 +282,7 @@ define <2 x double> @vfneg_vv_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -322,9 +304,7 @@ define <4 x double> @vfneg_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -346,9 +326,7 @@ define <8 x double> @vfneg_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -370,9 +348,7 @@ define <15 x double> @vfneg_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.fneg.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -394,9 +370,7 @@ define <16 x double> @vfneg_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fneg.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -445,8 +419,6 @@ define <32 x double> @vfneg_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfneg.v v16, v16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll index 7dc921066654..6d65ab4083f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll @@ -16,11 +16,9 @@ define <2 x half> @vfnmacc_vv_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -32,12 +30,10 @@ define <2 x half> @vfnmacc_vv_v2f16_unmasked(<2 x half> %a, <2 x half> %b, <2 x ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -50,11 +46,9 @@ define <2 x half> @vfnmacc_vf_v2f16(<2 x half> %a, half %b, <2 x half> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -68,11 +62,9 @@ define <2 x half> @vfnmacc_vf_v2f16_commute(<2 x half> %a, half %b, <2 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -86,12 +78,10 @@ define <2 x half> @vfnmacc_vf_v2f16_unmasked(<2 x half> %a, half %b, <2 x half> ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -102,11 +92,9 @@ define <2 x half> @vfnmacc_vv_v2f16_ta(<2 x half> %a, <2 x half> %b, <2 x half> ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -120,11 +108,9 @@ define <2 x half> @vfnmacc_vf_v2f16_ta(<2 x half> %a, half %b, <2 x half> %c, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -138,11 +124,9 @@ define <2 x half> @vfnmacc_vf_v2f16_commute_ta(<2 x half> %a, half %b, <2 x half ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -159,11 +143,9 @@ define <4 x half> @vfnmacc_vv_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -175,12 +157,10 @@ define <4 x half> @vfnmacc_vv_v4f16_unmasked(<4 x half> %a, <4 x half> %b, <4 x ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -193,11 +173,9 @@ define <4 x half> @vfnmacc_vf_v4f16(<4 x half> %a, half %b, <4 x half> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -211,11 +189,9 @@ define <4 x half> @vfnmacc_vf_v4f16_commute(<4 x half> %a, half %b, <4 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -229,12 +205,10 @@ define <4 x half> @vfnmacc_vf_v4f16_unmasked(<4 x half> %a, half %b, <4 x half> ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -245,11 +219,9 @@ define <4 x half> @vfnmacc_vv_v4f16_ta(<4 x half> %a, <4 x half> %b, <4 x half> ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -263,11 +235,9 @@ define <4 x half> @vfnmacc_vf_v4f16_ta(<4 x half> %a, half %b, <4 x half> %c, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -281,11 +251,9 @@ define <4 x half> @vfnmacc_vf_v4f16_commute_ta(<4 x half> %a, half %b, <4 x half ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -302,11 +270,9 @@ define <8 x half> @vfnmacc_vv_v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -318,12 +284,10 @@ define <8 x half> @vfnmacc_vv_v8f16_unmasked(<8 x half> %a, <8 x half> %b, <8 x ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -336,11 +300,9 @@ define <8 x half> @vfnmacc_vf_v8f16(<8 x half> %a, half %b, <8 x half> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -354,11 +316,9 @@ define <8 x half> @vfnmacc_vf_v8f16_commute(<8 x half> %a, half %b, <8 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -372,12 +332,10 @@ define <8 x half> @vfnmacc_vf_v8f16_unmasked(<8 x half> %a, half %b, <8 x half> ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -388,11 +346,9 @@ define <8 x half> @vfnmacc_vv_v8f16_ta(<8 x half> %a, <8 x half> %b, <8 x half> ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -406,11 +362,9 @@ define <8 x half> @vfnmacc_vf_v8f16_ta(<8 x half> %a, half %b, <8 x half> %c, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -424,11 +378,9 @@ define <8 x half> @vfnmacc_vf_v8f16_commute_ta(<8 x half> %a, half %b, <8 x half ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -445,11 +397,9 @@ define <16 x half> @vfnmacc_vv_v16f16(<16 x half> %a, <16 x half> %b, <16 x half ; CHECK-NEXT: vfnmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -461,12 +411,10 @@ define <16 x half> @vfnmacc_vv_v16f16_unmasked(<16 x half> %a, <16 x half> %b, < ; CHECK-NEXT: vfnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -479,11 +427,9 @@ define <16 x half> @vfnmacc_vf_v16f16(<16 x half> %a, half %b, <16 x half> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -497,11 +443,9 @@ define <16 x half> @vfnmacc_vf_v16f16_commute(<16 x half> %a, half %b, <16 x hal ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -515,12 +459,10 @@ define <16 x half> @vfnmacc_vf_v16f16_unmasked(<16 x half> %a, half %b, <16 x ha ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -531,11 +473,9 @@ define <16 x half> @vfnmacc_vv_v16f16_ta(<16 x half> %a, <16 x half> %b, <16 x h ; CHECK-NEXT: vfnmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -549,11 +489,9 @@ define <16 x half> @vfnmacc_vf_v16f16_ta(<16 x half> %a, half %b, <16 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -567,11 +505,9 @@ define <16 x half> @vfnmacc_vf_v16f16_commute_ta(<16 x half> %a, half %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -588,11 +524,9 @@ define <32 x half> @vfnmacc_vv_v32f16(<32 x half> %a, <32 x half> %b, <32 x half ; CHECK-NEXT: vfnmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %b, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %b, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -604,12 +538,10 @@ define <32 x half> @vfnmacc_vv_v32f16_unmasked(<32 x half> %a, <32 x half> %b, < ; CHECK-NEXT: vfnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %b, <32 x half> %negc, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %b, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -622,11 +554,9 @@ define <32 x half> @vfnmacc_vf_v32f16(<32 x half> %a, half %b, <32 x half> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -640,11 +570,9 @@ define <32 x half> @vfnmacc_vf_v32f16_commute(<32 x half> %a, half %b, <32 x hal ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -658,12 +586,10 @@ define <32 x half> @vfnmacc_vf_v32f16_unmasked(<32 x half> %a, half %b, <32 x ha ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %negc, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v32f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -674,11 +600,9 @@ define <32 x half> @vfnmacc_vv_v32f16_ta(<32 x half> %a, <32 x half> %b, <32 x h ; CHECK-NEXT: vfnmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %b, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %b, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -692,11 +616,9 @@ define <32 x half> @vfnmacc_vf_v32f16_ta(<32 x half> %a, half %b, <32 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -710,11 +632,9 @@ define <32 x half> @vfnmacc_vf_v32f16_commute_ta(<32 x half> %a, half %b, <32 x ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %negc, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %negc = call <32 x half> @llvm.vp.fneg.v32f16(<32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v32f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %negc, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v32f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -731,11 +651,9 @@ define <2 x float> @vfnmacc_vv_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -747,12 +665,10 @@ define <2 x float> @vfnmacc_vv_v2f32_unmasked(<2 x float> %a, <2 x float> %b, <2 ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -765,11 +681,9 @@ define <2 x float> @vfnmacc_vf_v2f32(<2 x float> %a, float %b, <2 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -783,11 +697,9 @@ define <2 x float> @vfnmacc_vf_v2f32_commute(<2 x float> %a, float %b, <2 x floa ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -801,12 +713,10 @@ define <2 x float> @vfnmacc_vf_v2f32_unmasked(<2 x float> %a, float %b, <2 x flo ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -817,11 +727,9 @@ define <2 x float> @vfnmacc_vv_v2f32_ta(<2 x float> %a, <2 x float> %b, <2 x flo ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -835,11 +743,9 @@ define <2 x float> @vfnmacc_vf_v2f32_ta(<2 x float> %a, float %b, <2 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -853,11 +759,9 @@ define <2 x float> @vfnmacc_vf_v2f32_commute_ta(<2 x float> %a, float %b, <2 x f ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -874,11 +778,9 @@ define <4 x float> @vfnmacc_vv_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -890,12 +792,10 @@ define <4 x float> @vfnmacc_vv_v4f32_unmasked(<4 x float> %a, <4 x float> %b, <4 ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -908,11 +808,9 @@ define <4 x float> @vfnmacc_vf_v4f32(<4 x float> %a, float %b, <4 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -926,11 +824,9 @@ define <4 x float> @vfnmacc_vf_v4f32_commute(<4 x float> %a, float %b, <4 x floa ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -944,12 +840,10 @@ define <4 x float> @vfnmacc_vf_v4f32_unmasked(<4 x float> %a, float %b, <4 x flo ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -960,11 +854,9 @@ define <4 x float> @vfnmacc_vv_v4f32_ta(<4 x float> %a, <4 x float> %b, <4 x flo ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -978,11 +870,9 @@ define <4 x float> @vfnmacc_vf_v4f32_ta(<4 x float> %a, float %b, <4 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -996,11 +886,9 @@ define <4 x float> @vfnmacc_vf_v4f32_commute_ta(<4 x float> %a, float %b, <4 x f ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -1017,11 +905,9 @@ define <8 x float> @vfnmacc_vv_v8f32(<8 x float> %a, <8 x float> %b, <8 x float> ; CHECK-NEXT: vfnmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1033,12 +919,10 @@ define <8 x float> @vfnmacc_vv_v8f32_unmasked(<8 x float> %a, <8 x float> %b, <8 ; CHECK-NEXT: vfnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1051,11 +935,9 @@ define <8 x float> @vfnmacc_vf_v8f32(<8 x float> %a, float %b, <8 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1069,11 +951,9 @@ define <8 x float> @vfnmacc_vf_v8f32_commute(<8 x float> %a, float %b, <8 x floa ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1087,12 +967,10 @@ define <8 x float> @vfnmacc_vf_v8f32_unmasked(<8 x float> %a, float %b, <8 x flo ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1103,11 +981,9 @@ define <8 x float> @vfnmacc_vv_v8f32_ta(<8 x float> %a, <8 x float> %b, <8 x flo ; CHECK-NEXT: vfnmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1121,11 +997,9 @@ define <8 x float> @vfnmacc_vf_v8f32_ta(<8 x float> %a, float %b, <8 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1139,11 +1013,9 @@ define <8 x float> @vfnmacc_vf_v8f32_commute_ta(<8 x float> %a, float %b, <8 x f ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1160,11 +1032,9 @@ define <16 x float> @vfnmacc_vv_v16f32(<16 x float> %a, <16 x float> %b, <16 x f ; CHECK-NEXT: vfnmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1176,12 +1046,10 @@ define <16 x float> @vfnmacc_vv_v16f32_unmasked(<16 x float> %a, <16 x float> %b ; CHECK-NEXT: vfnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1194,11 +1062,9 @@ define <16 x float> @vfnmacc_vf_v16f32(<16 x float> %a, float %b, <16 x float> % ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1212,11 +1078,9 @@ define <16 x float> @vfnmacc_vf_v16f32_commute(<16 x float> %a, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1230,12 +1094,10 @@ define <16 x float> @vfnmacc_vf_v16f32_unmasked(<16 x float> %a, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %negc, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1246,11 +1108,9 @@ define <16 x float> @vfnmacc_vv_v16f32_ta(<16 x float> %a, <16 x float> %b, <16 ; CHECK-NEXT: vfnmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1264,11 +1124,9 @@ define <16 x float> @vfnmacc_vf_v16f32_ta(<16 x float> %a, float %b, <16 x float ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1282,11 +1140,9 @@ define <16 x float> @vfnmacc_vf_v16f32_commute_ta(<16 x float> %a, float %b, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %negc, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %negc = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %negc, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1303,11 +1159,9 @@ define <2 x double> @vfnmacc_vv_v2f64(<2 x double> %a, <2 x double> %b, <2 x dou ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1319,12 +1173,10 @@ define <2 x double> @vfnmacc_vv_v2f64_unmasked(<2 x double> %a, <2 x double> %b, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1337,11 +1189,9 @@ define <2 x double> @vfnmacc_vf_v2f64(<2 x double> %a, double %b, <2 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1355,11 +1205,9 @@ define <2 x double> @vfnmacc_vf_v2f64_commute(<2 x double> %a, double %b, <2 x d ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1373,12 +1221,10 @@ define <2 x double> @vfnmacc_vf_v2f64_unmasked(<2 x double> %a, double %b, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %negc, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1389,11 +1235,9 @@ define <2 x double> @vfnmacc_vv_v2f64_ta(<2 x double> %a, <2 x double> %b, <2 x ; CHECK-NEXT: vfnmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1407,11 +1251,9 @@ define <2 x double> @vfnmacc_vf_v2f64_ta(<2 x double> %a, double %b, <2 x double ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1425,11 +1267,9 @@ define <2 x double> @vfnmacc_vf_v2f64_commute_ta(<2 x double> %a, double %b, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %negc, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %negc = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %negc, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1446,11 +1286,9 @@ define <4 x double> @vfnmacc_vv_v4f64(<4 x double> %a, <4 x double> %b, <4 x dou ; CHECK-NEXT: vfnmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1462,12 +1300,10 @@ define <4 x double> @vfnmacc_vv_v4f64_unmasked(<4 x double> %a, <4 x double> %b, ; CHECK-NEXT: vfnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1480,11 +1316,9 @@ define <4 x double> @vfnmacc_vf_v4f64(<4 x double> %a, double %b, <4 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1498,11 +1332,9 @@ define <4 x double> @vfnmacc_vf_v4f64_commute(<4 x double> %a, double %b, <4 x d ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1516,12 +1348,10 @@ define <4 x double> @vfnmacc_vf_v4f64_unmasked(<4 x double> %a, double %b, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %negc, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1532,11 +1362,9 @@ define <4 x double> @vfnmacc_vv_v4f64_ta(<4 x double> %a, <4 x double> %b, <4 x ; CHECK-NEXT: vfnmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1550,11 +1378,9 @@ define <4 x double> @vfnmacc_vf_v4f64_ta(<4 x double> %a, double %b, <4 x double ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1568,11 +1394,9 @@ define <4 x double> @vfnmacc_vf_v4f64_commute_ta(<4 x double> %a, double %b, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %negc, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %negc = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %negc, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1589,11 +1413,9 @@ define <8 x double> @vfnmacc_vv_v8f64(<8 x double> %a, <8 x double> %b, <8 x dou ; CHECK-NEXT: vfnmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1605,12 +1427,10 @@ define <8 x double> @vfnmacc_vv_v8f64_unmasked(<8 x double> %a, <8 x double> %b, ; CHECK-NEXT: vfnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1623,11 +1443,9 @@ define <8 x double> @vfnmacc_vf_v8f64(<8 x double> %a, double %b, <8 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1641,11 +1459,9 @@ define <8 x double> @vfnmacc_vf_v8f64_commute(<8 x double> %a, double %b, <8 x d ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1659,12 +1475,10 @@ define <8 x double> @vfnmacc_vf_v8f64_unmasked(<8 x double> %a, double %b, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %negc, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1675,11 +1489,9 @@ define <8 x double> @vfnmacc_vv_v8f64_ta(<8 x double> %a, <8 x double> %b, <8 x ; CHECK-NEXT: vfnmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1693,11 +1505,9 @@ define <8 x double> @vfnmacc_vf_v8f64_ta(<8 x double> %a, double %b, <8 x double ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1711,11 +1521,9 @@ define <8 x double> @vfnmacc_vf_v8f64_commute_ta(<8 x double> %a, double %b, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %negc, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %negc = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %negc, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll index 86605446815b..df705270664b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll @@ -16,10 +16,8 @@ define <2 x half> @vfnmsac_vv_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -31,11 +29,9 @@ define <2 x half> @vfnmsac_vv_v2f16_unmasked(<2 x half> %a, <2 x half> %b, <2 x ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -48,10 +44,8 @@ define <2 x half> @vfnmsac_vf_v2f16(<2 x half> %a, half %b, <2 x half> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -65,10 +59,8 @@ define <2 x half> @vfnmsac_vf_v2f16_commute(<2 x half> %a, half %b, <2 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -82,11 +74,9 @@ define <2 x half> @vfnmsac_vf_v2f16_unmasked(<2 x half> %a, half %b, <2 x half> ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> %allones, <2 x half> %v, <2 x half> %c, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x half> @llvm.vp.merge.v2f16(<2 x i1> splat (i1 -1), <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -97,10 +87,8 @@ define <2 x half> @vfnmsac_vv_v2f16_ta(<2 x half> %a, <2 x half> %b, <2 x half> ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %b, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -114,10 +102,8 @@ define <2 x half> @vfnmsac_vf_v2f16_ta(<2 x half> %a, half %b, <2 x half> %c, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %nega, <2 x half> %vb, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -131,10 +117,8 @@ define <2 x half> @vfnmsac_vf_v2f16_commute_ta(<2 x half> %a, half %b, <2 x half ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x half> @llvm.vp.fneg.v2f16(<2 x half> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x half> @llvm.vp.fma.v2f16(<2 x half> %vb, <2 x half> %nega, <2 x half> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x half> @llvm.vp.select.v2f16(<2 x i1> %m, <2 x half> %v, <2 x half> %c, i32 %evl) ret <2 x half> %u } @@ -151,10 +135,8 @@ define <4 x half> @vfnmsac_vv_v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -166,11 +148,9 @@ define <4 x half> @vfnmsac_vv_v4f16_unmasked(<4 x half> %a, <4 x half> %b, <4 x ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -183,10 +163,8 @@ define <4 x half> @vfnmsac_vf_v4f16(<4 x half> %a, half %b, <4 x half> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -200,10 +178,8 @@ define <4 x half> @vfnmsac_vf_v4f16_commute(<4 x half> %a, half %b, <4 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -217,11 +193,9 @@ define <4 x half> @vfnmsac_vf_v4f16_unmasked(<4 x half> %a, half %b, <4 x half> ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> %allones, <4 x half> %v, <4 x half> %c, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x half> @llvm.vp.merge.v4f16(<4 x i1> splat (i1 -1), <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -232,10 +206,8 @@ define <4 x half> @vfnmsac_vv_v4f16_ta(<4 x half> %a, <4 x half> %b, <4 x half> ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %b, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -249,10 +221,8 @@ define <4 x half> @vfnmsac_vf_v4f16_ta(<4 x half> %a, half %b, <4 x half> %c, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %nega, <4 x half> %vb, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -266,10 +236,8 @@ define <4 x half> @vfnmsac_vf_v4f16_commute_ta(<4 x half> %a, half %b, <4 x half ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x half> @llvm.vp.fneg.v4f16(<4 x half> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x half> @llvm.vp.fma.v4f16(<4 x half> %vb, <4 x half> %nega, <4 x half> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x half> @llvm.vp.select.v4f16(<4 x i1> %m, <4 x half> %v, <4 x half> %c, i32 %evl) ret <4 x half> %u } @@ -286,10 +254,8 @@ define <8 x half> @vfnmsac_vv_v8f16(<8 x half> %a, <8 x half> %b, <8 x half> %c, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -301,11 +267,9 @@ define <8 x half> @vfnmsac_vv_v8f16_unmasked(<8 x half> %a, <8 x half> %b, <8 x ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -318,10 +282,8 @@ define <8 x half> @vfnmsac_vf_v8f16(<8 x half> %a, half %b, <8 x half> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -335,10 +297,8 @@ define <8 x half> @vfnmsac_vf_v8f16_commute(<8 x half> %a, half %b, <8 x half> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -352,11 +312,9 @@ define <8 x half> @vfnmsac_vf_v8f16_unmasked(<8 x half> %a, half %b, <8 x half> ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> %allones, <8 x half> %v, <8 x half> %c, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x half> @llvm.vp.merge.v8f16(<8 x i1> splat (i1 -1), <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -367,10 +325,8 @@ define <8 x half> @vfnmsac_vv_v8f16_ta(<8 x half> %a, <8 x half> %b, <8 x half> ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %b, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -384,10 +340,8 @@ define <8 x half> @vfnmsac_vf_v8f16_ta(<8 x half> %a, half %b, <8 x half> %c, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %nega, <8 x half> %vb, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -401,10 +355,8 @@ define <8 x half> @vfnmsac_vf_v8f16_commute_ta(<8 x half> %a, half %b, <8 x half ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x half> @llvm.vp.fneg.v8f16(<8 x half> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x half> @llvm.vp.fma.v8f16(<8 x half> %vb, <8 x half> %nega, <8 x half> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x half> @llvm.vp.select.v8f16(<8 x i1> %m, <8 x half> %v, <8 x half> %c, i32 %evl) ret <8 x half> %u } @@ -421,10 +373,8 @@ define <16 x half> @vfnmsac_vv_v16f16(<16 x half> %a, <16 x half> %b, <16 x half ; CHECK-NEXT: vfnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -436,11 +386,9 @@ define <16 x half> @vfnmsac_vv_v16f16_unmasked(<16 x half> %a, <16 x half> %b, < ; CHECK-NEXT: vfnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -453,10 +401,8 @@ define <16 x half> @vfnmsac_vf_v16f16(<16 x half> %a, half %b, <16 x half> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -470,10 +416,8 @@ define <16 x half> @vfnmsac_vf_v16f16_commute(<16 x half> %a, half %b, <16 x hal ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -487,11 +431,9 @@ define <16 x half> @vfnmsac_vf_v16f16_unmasked(<16 x half> %a, half %b, <16 x ha ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> %allones, <16 x half> %v, <16 x half> %c, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x half> @llvm.vp.merge.v16f16(<16 x i1> splat (i1 -1), <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -502,10 +444,8 @@ define <16 x half> @vfnmsac_vv_v16f16_ta(<16 x half> %a, <16 x half> %b, <16 x h ; CHECK-NEXT: vfnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %b, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -519,10 +459,8 @@ define <16 x half> @vfnmsac_vf_v16f16_ta(<16 x half> %a, half %b, <16 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %nega, <16 x half> %vb, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -536,10 +474,8 @@ define <16 x half> @vfnmsac_vf_v16f16_commute_ta(<16 x half> %a, half %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x half> @llvm.vp.fneg.v16f16(<16 x half> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x half> @llvm.vp.fma.v16f16(<16 x half> %vb, <16 x half> %nega, <16 x half> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x half> @llvm.vp.select.v16f16(<16 x i1> %m, <16 x half> %v, <16 x half> %c, i32 %evl) ret <16 x half> %u } @@ -556,10 +492,8 @@ define <32 x half> @vfnmsac_vv_v26f16(<32 x half> %a, <32 x half> %b, <32 x half ; CHECK-NEXT: vfnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %b, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %b, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -571,11 +505,9 @@ define <32 x half> @vfnmsac_vv_v26f16_unmasked(<32 x half> %a, <32 x half> %b, < ; CHECK-NEXT: vfnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %b, <32 x half> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %b, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -588,10 +520,8 @@ define <32 x half> @vfnmsac_vf_v26f16(<32 x half> %a, half %b, <32 x half> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -605,10 +535,8 @@ define <32 x half> @vfnmsac_vf_v26f16_commute(<32 x half> %a, half %b, <32 x hal ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -622,11 +550,9 @@ define <32 x half> @vfnmsac_vf_v26f16_unmasked(<32 x half> %a, half %b, <32 x ha ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> %allones, <32 x half> %v, <32 x half> %c, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x half> @llvm.vp.merge.v26f16(<32 x i1> splat (i1 -1), <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -637,10 +563,8 @@ define <32 x half> @vfnmsac_vv_v26f16_ta(<32 x half> %a, <32 x half> %b, <32 x h ; CHECK-NEXT: vfnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %b, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %b, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v26f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -654,10 +578,8 @@ define <32 x half> @vfnmsac_vf_v26f16_ta(<32 x half> %a, half %b, <32 x half> %c ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %nega, <32 x half> %vb, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v26f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -671,10 +593,8 @@ define <32 x half> @vfnmsac_vf_v26f16_commute_ta(<32 x half> %a, half %b, <32 x ; CHECK-NEXT: ret %elt.head = insertelement <32 x half> poison, half %b, i32 0 %vb = shufflevector <32 x half> %elt.head, <32 x half> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> %allones, i32 %evl) - %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %c, <32 x i1> %allones, i32 %evl) + %nega = call <32 x half> @llvm.vp.fneg.v26f16(<32 x half> %a, <32 x i1> splat (i1 -1), i32 %evl) + %v = call <32 x half> @llvm.vp.fma.v26f16(<32 x half> %vb, <32 x half> %nega, <32 x half> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x half> @llvm.vp.select.v26f16(<32 x i1> %m, <32 x half> %v, <32 x half> %c, i32 %evl) ret <32 x half> %u } @@ -691,10 +611,8 @@ define <2 x float> @vfnmsac_vv_v2f32(<2 x float> %a, <2 x float> %b, <2 x float> ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -706,11 +624,9 @@ define <2 x float> @vfnmsac_vv_v2f32_unmasked(<2 x float> %a, <2 x float> %b, <2 ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -723,10 +639,8 @@ define <2 x float> @vfnmsac_vf_v2f32(<2 x float> %a, float %b, <2 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -740,10 +654,8 @@ define <2 x float> @vfnmsac_vf_v2f32_commute(<2 x float> %a, float %b, <2 x floa ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -757,11 +669,9 @@ define <2 x float> @vfnmsac_vf_v2f32_unmasked(<2 x float> %a, float %b, <2 x flo ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> %allones, <2 x float> %v, <2 x float> %c, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x float> @llvm.vp.merge.v2f32(<2 x i1> splat (i1 -1), <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -772,10 +682,8 @@ define <2 x float> @vfnmsac_vv_v2f32_ta(<2 x float> %a, <2 x float> %b, <2 x flo ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %b, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -789,10 +697,8 @@ define <2 x float> @vfnmsac_vf_v2f32_ta(<2 x float> %a, float %b, <2 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %nega, <2 x float> %vb, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -806,10 +712,8 @@ define <2 x float> @vfnmsac_vf_v2f32_commute_ta(<2 x float> %a, float %b, <2 x f ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x float> @llvm.vp.fneg.v2f32(<2 x float> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x float> @llvm.vp.fma.v2f32(<2 x float> %vb, <2 x float> %nega, <2 x float> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x float> @llvm.vp.select.v2f32(<2 x i1> %m, <2 x float> %v, <2 x float> %c, i32 %evl) ret <2 x float> %u } @@ -826,10 +730,8 @@ define <4 x float> @vfnmsac_vv_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -841,11 +743,9 @@ define <4 x float> @vfnmsac_vv_v4f32_unmasked(<4 x float> %a, <4 x float> %b, <4 ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -858,10 +758,8 @@ define <4 x float> @vfnmsac_vf_v4f32(<4 x float> %a, float %b, <4 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -875,10 +773,8 @@ define <4 x float> @vfnmsac_vf_v4f32_commute(<4 x float> %a, float %b, <4 x floa ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -892,11 +788,9 @@ define <4 x float> @vfnmsac_vf_v4f32_unmasked(<4 x float> %a, float %b, <4 x flo ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> %allones, <4 x float> %v, <4 x float> %c, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x float> @llvm.vp.merge.v4f32(<4 x i1> splat (i1 -1), <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -907,10 +801,8 @@ define <4 x float> @vfnmsac_vv_v4f32_ta(<4 x float> %a, <4 x float> %b, <4 x flo ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %b, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -924,10 +816,8 @@ define <4 x float> @vfnmsac_vf_v4f32_ta(<4 x float> %a, float %b, <4 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %nega, <4 x float> %vb, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -941,10 +831,8 @@ define <4 x float> @vfnmsac_vf_v4f32_commute_ta(<4 x float> %a, float %b, <4 x f ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x float> @llvm.vp.fneg.v4f32(<4 x float> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x float> @llvm.vp.fma.v4f32(<4 x float> %vb, <4 x float> %nega, <4 x float> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x float> @llvm.vp.select.v4f32(<4 x i1> %m, <4 x float> %v, <4 x float> %c, i32 %evl) ret <4 x float> %u } @@ -961,10 +849,8 @@ define <8 x float> @vfnmsac_vv_v8f32(<8 x float> %a, <8 x float> %b, <8 x float> ; CHECK-NEXT: vfnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -976,11 +862,9 @@ define <8 x float> @vfnmsac_vv_v8f32_unmasked(<8 x float> %a, <8 x float> %b, <8 ; CHECK-NEXT: vfnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -993,10 +877,8 @@ define <8 x float> @vfnmsac_vf_v8f32(<8 x float> %a, float %b, <8 x float> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1010,10 +892,8 @@ define <8 x float> @vfnmsac_vf_v8f32_commute(<8 x float> %a, float %b, <8 x floa ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1027,11 +907,9 @@ define <8 x float> @vfnmsac_vf_v8f32_unmasked(<8 x float> %a, float %b, <8 x flo ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> %allones, <8 x float> %v, <8 x float> %c, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x float> @llvm.vp.merge.v8f32(<8 x i1> splat (i1 -1), <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1042,10 +920,8 @@ define <8 x float> @vfnmsac_vv_v8f32_ta(<8 x float> %a, <8 x float> %b, <8 x flo ; CHECK-NEXT: vfnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %b, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1059,10 +935,8 @@ define <8 x float> @vfnmsac_vf_v8f32_ta(<8 x float> %a, float %b, <8 x float> %c ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %nega, <8 x float> %vb, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1076,10 +950,8 @@ define <8 x float> @vfnmsac_vf_v8f32_commute_ta(<8 x float> %a, float %b, <8 x f ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x float> @llvm.vp.fneg.v8f32(<8 x float> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x float> @llvm.vp.fma.v8f32(<8 x float> %vb, <8 x float> %nega, <8 x float> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x float> @llvm.vp.select.v8f32(<8 x i1> %m, <8 x float> %v, <8 x float> %c, i32 %evl) ret <8 x float> %u } @@ -1096,10 +968,8 @@ define <16 x float> @vfnmsac_vv_v16f32(<16 x float> %a, <16 x float> %b, <16 x f ; CHECK-NEXT: vfnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1111,11 +981,9 @@ define <16 x float> @vfnmsac_vv_v16f32_unmasked(<16 x float> %a, <16 x float> %b ; CHECK-NEXT: vfnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1128,10 +996,8 @@ define <16 x float> @vfnmsac_vf_v16f32(<16 x float> %a, float %b, <16 x float> % ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1145,10 +1011,8 @@ define <16 x float> @vfnmsac_vf_v16f32_commute(<16 x float> %a, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1162,11 +1026,9 @@ define <16 x float> @vfnmsac_vf_v16f32_unmasked(<16 x float> %a, float %b, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> %allones, <16 x float> %v, <16 x float> %c, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x float> @llvm.vp.merge.v16f32(<16 x i1> splat (i1 -1), <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1177,10 +1039,8 @@ define <16 x float> @vfnmsac_vv_v16f32_ta(<16 x float> %a, <16 x float> %b, <16 ; CHECK-NEXT: vfnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %b, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1194,10 +1054,8 @@ define <16 x float> @vfnmsac_vf_v16f32_ta(<16 x float> %a, float %b, <16 x float ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %nega, <16 x float> %vb, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1211,10 +1069,8 @@ define <16 x float> @vfnmsac_vf_v16f32_commute_ta(<16 x float> %a, float %b, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> %allones, i32 %evl) - %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %c, <16 x i1> %allones, i32 %evl) + %nega = call <16 x float> @llvm.vp.fneg.v16f32(<16 x float> %a, <16 x i1> splat (i1 -1), i32 %evl) + %v = call <16 x float> @llvm.vp.fma.v16f32(<16 x float> %vb, <16 x float> %nega, <16 x float> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x float> @llvm.vp.select.v16f32(<16 x i1> %m, <16 x float> %v, <16 x float> %c, i32 %evl) ret <16 x float> %u } @@ -1231,10 +1087,8 @@ define <2 x double> @vfnmsac_vv_v2f64(<2 x double> %a, <2 x double> %b, <2 x dou ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1246,11 +1100,9 @@ define <2 x double> @vfnmsac_vv_v2f64_unmasked(<2 x double> %a, <2 x double> %b, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1263,10 +1115,8 @@ define <2 x double> @vfnmsac_vf_v2f64(<2 x double> %a, double %b, <2 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1280,10 +1130,8 @@ define <2 x double> @vfnmsac_vf_v2f64_commute(<2 x double> %a, double %b, <2 x d ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1297,11 +1145,9 @@ define <2 x double> @vfnmsac_vf_v2f64_unmasked(<2 x double> %a, double %b, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> %allones, <2 x double> %v, <2 x double> %c, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x double> @llvm.vp.merge.v2f64(<2 x i1> splat (i1 -1), <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1312,10 +1158,8 @@ define <2 x double> @vfnmsac_vv_v2f64_ta(<2 x double> %a, <2 x double> %b, <2 x ; CHECK-NEXT: vfnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %b, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1329,10 +1173,8 @@ define <2 x double> @vfnmsac_vf_v2f64_ta(<2 x double> %a, double %b, <2 x double ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %nega, <2 x double> %vb, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1346,10 +1188,8 @@ define <2 x double> @vfnmsac_vf_v2f64_commute_ta(<2 x double> %a, double %b, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> %allones, i32 %evl) - %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %c, <2 x i1> %allones, i32 %evl) + %nega = call <2 x double> @llvm.vp.fneg.v2f64(<2 x double> %a, <2 x i1> splat (i1 -1), i32 %evl) + %v = call <2 x double> @llvm.vp.fma.v2f64(<2 x double> %vb, <2 x double> %nega, <2 x double> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x double> @llvm.vp.select.v2f64(<2 x i1> %m, <2 x double> %v, <2 x double> %c, i32 %evl) ret <2 x double> %u } @@ -1366,10 +1206,8 @@ define <4 x double> @vfnmsac_vv_v4f64(<4 x double> %a, <4 x double> %b, <4 x dou ; CHECK-NEXT: vfnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1381,11 +1219,9 @@ define <4 x double> @vfnmsac_vv_v4f64_unmasked(<4 x double> %a, <4 x double> %b, ; CHECK-NEXT: vfnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1398,10 +1234,8 @@ define <4 x double> @vfnmsac_vf_v4f64(<4 x double> %a, double %b, <4 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1415,10 +1249,8 @@ define <4 x double> @vfnmsac_vf_v4f64_commute(<4 x double> %a, double %b, <4 x d ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1432,11 +1264,9 @@ define <4 x double> @vfnmsac_vf_v4f64_unmasked(<4 x double> %a, double %b, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> %allones, <4 x double> %v, <4 x double> %c, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x double> @llvm.vp.merge.v4f64(<4 x i1> splat (i1 -1), <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1447,10 +1277,8 @@ define <4 x double> @vfnmsac_vv_v4f64_ta(<4 x double> %a, <4 x double> %b, <4 x ; CHECK-NEXT: vfnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %b, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1464,10 +1292,8 @@ define <4 x double> @vfnmsac_vf_v4f64_ta(<4 x double> %a, double %b, <4 x double ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %nega, <4 x double> %vb, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1481,10 +1307,8 @@ define <4 x double> @vfnmsac_vf_v4f64_commute_ta(<4 x double> %a, double %b, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> %allones, i32 %evl) - %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %c, <4 x i1> %allones, i32 %evl) + %nega = call <4 x double> @llvm.vp.fneg.v4f64(<4 x double> %a, <4 x i1> splat (i1 -1), i32 %evl) + %v = call <4 x double> @llvm.vp.fma.v4f64(<4 x double> %vb, <4 x double> %nega, <4 x double> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x double> @llvm.vp.select.v4f64(<4 x i1> %m, <4 x double> %v, <4 x double> %c, i32 %evl) ret <4 x double> %u } @@ -1501,10 +1325,8 @@ define <8 x double> @vfnmsac_vv_v8f64(<8 x double> %a, <8 x double> %b, <8 x dou ; CHECK-NEXT: vfnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1516,11 +1338,9 @@ define <8 x double> @vfnmsac_vv_v8f64_unmasked(<8 x double> %a, <8 x double> %b, ; CHECK-NEXT: vfnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1533,10 +1353,8 @@ define <8 x double> @vfnmsac_vf_v8f64(<8 x double> %a, double %b, <8 x double> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1550,10 +1368,8 @@ define <8 x double> @vfnmsac_vf_v8f64_commute(<8 x double> %a, double %b, <8 x d ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1567,11 +1383,9 @@ define <8 x double> @vfnmsac_vf_v8f64_unmasked(<8 x double> %a, double %b, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> %allones, <8 x double> %v, <8 x double> %c, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x double> @llvm.vp.merge.v8f64(<8 x i1> splat (i1 -1), <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1582,10 +1396,8 @@ define <8 x double> @vfnmsac_vv_v8f64_ta(<8 x double> %a, <8 x double> %b, <8 x ; CHECK-NEXT: vfnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %b, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1599,10 +1411,8 @@ define <8 x double> @vfnmsac_vf_v8f64_ta(<8 x double> %a, double %b, <8 x double ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %nega, <8 x double> %vb, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } @@ -1616,10 +1426,8 @@ define <8 x double> @vfnmsac_vf_v8f64_commute_ta(<8 x double> %a, double %b, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> %allones, i32 %evl) - %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %c, <8 x i1> %allones, i32 %evl) + %nega = call <8 x double> @llvm.vp.fneg.v8f64(<8 x double> %a, <8 x i1> splat (i1 -1), i32 %evl) + %v = call <8 x double> @llvm.vp.fma.v8f64(<8 x double> %vb, <8 x double> %nega, <8 x double> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x double> @llvm.vp.select.v8f64(<8 x i1> %m, <8 x double> %v, <8 x double> %c, i32 %evl) ret <8 x double> %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll index db7de5907769..bd354b7dae80 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll @@ -26,9 +26,7 @@ define <2 x half> @vfrdiv_vf_v2f16_unmasked(<2 x half> %va, half %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fdiv.v2f16(<2 x half> %vb, <2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fdiv.v2f16(<2 x half> %vb, <2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -54,9 +52,7 @@ define <4 x half> @vfrdiv_vf_v4f16_unmasked(<4 x half> %va, half %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fdiv.v4f16(<4 x half> %vb, <4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fdiv.v4f16(<4 x half> %vb, <4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -82,9 +78,7 @@ define <8 x half> @vfrdiv_vf_v8f16_unmasked(<8 x half> %va, half %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fdiv.v8f16(<8 x half> %vb, <8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fdiv.v8f16(<8 x half> %vb, <8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -110,9 +104,7 @@ define <16 x half> @vfrdiv_vf_v16f16_unmasked(<16 x half> %va, half %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fdiv.v16f16(<16 x half> %vb, <16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fdiv.v16f16(<16 x half> %vb, <16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -138,9 +130,7 @@ define <2 x float> @vfrdiv_vf_v2f32_unmasked(<2 x float> %va, float %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fdiv.v2f32(<2 x float> %vb, <2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fdiv.v2f32(<2 x float> %vb, <2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -166,9 +156,7 @@ define <4 x float> @vfrdiv_vf_v4f32_unmasked(<4 x float> %va, float %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %vb, <4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fdiv.v4f32(<4 x float> %vb, <4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -194,9 +182,7 @@ define <8 x float> @vfrdiv_vf_v8f32_unmasked(<8 x float> %va, float %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fdiv.v8f32(<8 x float> %vb, <8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fdiv.v8f32(<8 x float> %vb, <8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -222,9 +208,7 @@ define <16 x float> @vfrdiv_vf_v16f32_unmasked(<16 x float> %va, float %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fdiv.v16f32(<16 x float> %vb, <16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fdiv.v16f32(<16 x float> %vb, <16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -250,9 +234,7 @@ define <2 x double> @vfrdiv_vf_v2f64_unmasked(<2 x double> %va, double %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fdiv.v2f64(<2 x double> %vb, <2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fdiv.v2f64(<2 x double> %vb, <2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -278,9 +260,7 @@ define <4 x double> @vfrdiv_vf_v4f64_unmasked(<4 x double> %va, double %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fdiv.v4f64(<4 x double> %vb, <4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fdiv.v4f64(<4 x double> %vb, <4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -306,9 +286,7 @@ define <8 x double> @vfrdiv_vf_v8f64_unmasked(<8 x double> %va, double %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fdiv.v8f64(<8 x double> %vb, <8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fdiv.v8f64(<8 x double> %vb, <8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -334,8 +312,6 @@ define <16 x double> @vfrdiv_vf_v16f64_unmasked(<16 x double> %va, double %b, i3 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fdiv.v16f64(<16 x double> %vb, <16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fdiv.v16f64(<16 x double> %vb, <16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll index 3391abf8740a..0903ef8c8ec3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll @@ -26,9 +26,7 @@ define <2 x half> @vfrsub_vf_v2f16_unmasked(<2 x half> %va, half %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fsub.v2f16(<2 x half> %vb, <2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fsub.v2f16(<2 x half> %vb, <2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -54,9 +52,7 @@ define <4 x half> @vfrsub_vf_v4f16_unmasked(<4 x half> %va, half %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fsub.v4f16(<4 x half> %vb, <4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fsub.v4f16(<4 x half> %vb, <4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -82,9 +78,7 @@ define <8 x half> @vfrsub_vf_v8f16_unmasked(<8 x half> %va, half %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fsub.v8f16(<8 x half> %vb, <8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fsub.v8f16(<8 x half> %vb, <8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -110,9 +104,7 @@ define <16 x half> @vfrsub_vf_v16f16_unmasked(<16 x half> %va, half %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fsub.v16f16(<16 x half> %vb, <16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fsub.v16f16(<16 x half> %vb, <16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -138,9 +130,7 @@ define <2 x float> @vfrsub_vf_v2f32_unmasked(<2 x float> %va, float %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fsub.v2f32(<2 x float> %vb, <2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fsub.v2f32(<2 x float> %vb, <2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -166,9 +156,7 @@ define <4 x float> @vfrsub_vf_v4f32_unmasked(<4 x float> %va, float %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %vb, <4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %vb, <4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -194,9 +182,7 @@ define <8 x float> @vfrsub_vf_v8f32_unmasked(<8 x float> %va, float %b, i32 zero ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fsub.v8f32(<8 x float> %vb, <8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fsub.v8f32(<8 x float> %vb, <8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -222,9 +208,7 @@ define <16 x float> @vfrsub_vf_v16f32_unmasked(<16 x float> %va, float %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fsub.v16f32(<16 x float> %vb, <16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fsub.v16f32(<16 x float> %vb, <16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -250,9 +234,7 @@ define <2 x double> @vfrsub_vf_v2f64_unmasked(<2 x double> %va, double %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fsub.v2f64(<2 x double> %vb, <2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fsub.v2f64(<2 x double> %vb, <2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -278,9 +260,7 @@ define <4 x double> @vfrsub_vf_v4f64_unmasked(<4 x double> %va, double %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fsub.v4f64(<4 x double> %vb, <4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fsub.v4f64(<4 x double> %vb, <4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -306,9 +286,7 @@ define <8 x double> @vfrsub_vf_v8f64_unmasked(<8 x double> %va, double %b, i32 z ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fsub.v8f64(<8 x double> %vb, <8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fsub.v8f64(<8 x double> %vb, <8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -334,8 +312,6 @@ define <16 x double> @vfrsub_vf_v16f64_unmasked(<16 x double> %va, double %b, i3 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fsub.v16f64(<16 x double> %vb, <16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fsub.v16f64(<16 x double> %vb, <16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll index 60022644e5ab..6004eb4fe217 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll @@ -46,9 +46,7 @@ define <2 x half> @vfsqrt_vv_v2f16_unmasked(<2 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.sqrt.v2f16(<2 x half> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.sqrt.v2f16(<2 x half> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -90,9 +88,7 @@ define <4 x half> @vfsqrt_vv_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.sqrt.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.sqrt.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -134,9 +130,7 @@ define <8 x half> @vfsqrt_vv_v8f16_unmasked(<8 x half> %va, i32 zeroext %evl) { ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.sqrt.v8f16(<8 x half> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.sqrt.v8f16(<8 x half> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -178,9 +172,7 @@ define <16 x half> @vfsqrt_vv_v16f16_unmasked(<16 x half> %va, i32 zeroext %evl) ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.sqrt.v16f16(<16 x half> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.sqrt.v16f16(<16 x half> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -202,9 +194,7 @@ define <2 x float> @vfsqrt_vv_v2f32_unmasked(<2 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.sqrt.v2f32(<2 x float> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.sqrt.v2f32(<2 x float> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -226,9 +216,7 @@ define <4 x float> @vfsqrt_vv_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.sqrt.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.sqrt.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -250,9 +238,7 @@ define <8 x float> @vfsqrt_vv_v8f32_unmasked(<8 x float> %va, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.sqrt.v8f32(<8 x float> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.sqrt.v8f32(<8 x float> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -274,9 +260,7 @@ define <16 x float> @vfsqrt_vv_v16f32_unmasked(<16 x float> %va, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.sqrt.v16f32(<16 x float> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.sqrt.v16f32(<16 x float> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -298,9 +282,7 @@ define <2 x double> @vfsqrt_vv_v2f64_unmasked(<2 x double> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.sqrt.v2f64(<2 x double> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.sqrt.v2f64(<2 x double> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -322,9 +304,7 @@ define <4 x double> @vfsqrt_vv_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.sqrt.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.sqrt.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -346,9 +326,7 @@ define <8 x double> @vfsqrt_vv_v8f64_unmasked(<8 x double> %va, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.sqrt.v8f64(<8 x double> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.sqrt.v8f64(<8 x double> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -370,9 +348,7 @@ define <15 x double> @vfsqrt_vv_v15f64_unmasked(<15 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <15 x i1> poison, i1 true, i32 0 - %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x double> @llvm.vp.sqrt.v15f64(<15 x double> %va, <15 x i1> %m, i32 %evl) + %v = call <15 x double> @llvm.vp.sqrt.v15f64(<15 x double> %va, <15 x i1> splat (i1 true), i32 %evl) ret <15 x double> %v } @@ -394,9 +370,7 @@ define <16 x double> @vfsqrt_vv_v16f64_unmasked(<16 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.sqrt.v16f64(<16 x double> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.sqrt.v16f64(<16 x double> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -445,8 +419,6 @@ define <32 x double> @vfsqrt_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsqrt.v v16, v16 ; CHECK-NEXT: ret - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x double> @llvm.vp.sqrt.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) + %v = call <32 x double> @llvm.vp.sqrt.v32f64(<32 x double> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll index 76ca7d971eb4..eb717a851ed4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll @@ -48,9 +48,7 @@ define <2 x half> @vfsub_vv_v2f16_unmasked(<2 x half> %va, <2 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fsub.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fsub.v2f16(<2 x half> %va, <2 x half> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -106,9 +104,7 @@ define <2 x half> @vfsub_vf_v2f16_unmasked(<2 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <2 x half> poison, half %b, i32 0 %vb = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x half> @llvm.vp.fsub.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x half> @llvm.vp.fsub.v2f16(<2 x half> %va, <2 x half> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %v } @@ -175,9 +171,7 @@ define <4 x half> @vfsub_vv_v4f16_unmasked(<4 x half> %va, <4 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fsub.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fsub.v4f16(<4 x half> %va, <4 x half> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -233,9 +227,7 @@ define <4 x half> @vfsub_vf_v4f16_unmasked(<4 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <4 x half> poison, half %b, i32 0 %vb = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.fsub.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x half> @llvm.vp.fsub.v4f16(<4 x half> %va, <4 x half> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x half> %v } @@ -279,9 +271,7 @@ define <8 x half> @vfsub_vv_v8f16_unmasked(<8 x half> %va, <8 x half> %b, i32 ze ; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fsub.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fsub.v8f16(<8 x half> %va, <8 x half> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -337,9 +327,7 @@ define <8 x half> @vfsub_vf_v8f16_unmasked(<8 x half> %va, half %b, i32 zeroext ; ZVFHMIN-NEXT: ret %elt.head = insertelement <8 x half> poison, half %b, i32 0 %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x half> @llvm.vp.fsub.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x half> @llvm.vp.fsub.v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x half> %v } @@ -383,9 +371,7 @@ define <16 x half> @vfsub_vv_v16f16_unmasked(<16 x half> %va, <16 x half> %b, i3 ; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fsub.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fsub.v16f16(<16 x half> %va, <16 x half> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -441,9 +427,7 @@ define <16 x half> @vfsub_vf_v16f16_unmasked(<16 x half> %va, half %b, i32 zeroe ; ZVFHMIN-NEXT: ret %elt.head = insertelement <16 x half> poison, half %b, i32 0 %vb = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x half> @llvm.vp.fsub.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x half> @llvm.vp.fsub.v16f16(<16 x half> %va, <16 x half> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x half> %v } @@ -465,9 +449,7 @@ define <2 x float> @vfsub_vv_v2f32_unmasked(<2 x float> %va, <2 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fsub.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fsub.v2f32(<2 x float> %va, <2 x float> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -491,9 +473,7 @@ define <2 x float> @vfsub_vf_v2f32_unmasked(<2 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <2 x float> poison, float %b, i32 0 %vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x float> @llvm.vp.fsub.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x float> @llvm.vp.fsub.v2f32(<2 x float> %va, <2 x float> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x float> %v } @@ -515,9 +495,7 @@ define <4 x float> @vfsub_vv_v4f32_unmasked(<4 x float> %va, <4 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %va, <4 x float> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -541,9 +519,7 @@ define <4 x float> @vfsub_vf_v4f32_unmasked(<4 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <4 x float> poison, float %b, i32 0 %vb = shufflevector <4 x float> %elt.head, <4 x float> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x float> @llvm.vp.fsub.v4f32(<4 x float> %va, <4 x float> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x float> %v } @@ -565,9 +541,7 @@ define <8 x float> @vfsub_vv_v8f32_unmasked(<8 x float> %va, <8 x float> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fsub.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fsub.v8f32(<8 x float> %va, <8 x float> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -591,9 +565,7 @@ define <8 x float> @vfsub_vf_v8f32_unmasked(<8 x float> %va, float %b, i32 zeroe ; CHECK-NEXT: ret %elt.head = insertelement <8 x float> poison, float %b, i32 0 %vb = shufflevector <8 x float> %elt.head, <8 x float> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x float> @llvm.vp.fsub.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x float> @llvm.vp.fsub.v8f32(<8 x float> %va, <8 x float> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %v } @@ -615,9 +587,7 @@ define <16 x float> @vfsub_vv_v16f32_unmasked(<16 x float> %va, <16 x float> %b, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fsub.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fsub.v16f32(<16 x float> %va, <16 x float> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -641,9 +611,7 @@ define <16 x float> @vfsub_vf_v16f32_unmasked(<16 x float> %va, float %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <16 x float> poison, float %b, i32 0 %vb = shufflevector <16 x float> %elt.head, <16 x float> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x float> @llvm.vp.fsub.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x float> @llvm.vp.fsub.v16f32(<16 x float> %va, <16 x float> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x float> %v } @@ -665,9 +633,7 @@ define <2 x double> @vfsub_vv_v2f64_unmasked(<2 x double> %va, <2 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fsub.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fsub.v2f64(<2 x double> %va, <2 x double> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -691,9 +657,7 @@ define <2 x double> @vfsub_vf_v2f64_unmasked(<2 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <2 x double> poison, double %b, i32 0 %vb = shufflevector <2 x double> %elt.head, <2 x double> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.vp.fsub.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x double> @llvm.vp.fsub.v2f64(<2 x double> %va, <2 x double> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x double> %v } @@ -715,9 +679,7 @@ define <4 x double> @vfsub_vv_v4f64_unmasked(<4 x double> %va, <4 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fsub.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fsub.v4f64(<4 x double> %va, <4 x double> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -741,9 +703,7 @@ define <4 x double> @vfsub_vf_v4f64_unmasked(<4 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <4 x double> poison, double %b, i32 0 %vb = shufflevector <4 x double> %elt.head, <4 x double> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.fsub.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x double> @llvm.vp.fsub.v4f64(<4 x double> %va, <4 x double> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %v } @@ -765,9 +725,7 @@ define <8 x double> @vfsub_vv_v8f64_unmasked(<8 x double> %va, <8 x double> %b, ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fsub.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fsub.v8f64(<8 x double> %va, <8 x double> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -791,9 +749,7 @@ define <8 x double> @vfsub_vf_v8f64_unmasked(<8 x double> %va, double %b, i32 ze ; CHECK-NEXT: ret %elt.head = insertelement <8 x double> poison, double %b, i32 0 %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x double> @llvm.vp.fsub.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x double> @llvm.vp.fsub.v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x double> %v } @@ -815,9 +771,7 @@ define <16 x double> @vfsub_vv_v16f64_unmasked(<16 x double> %va, <16 x double> ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fsub.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fsub.v16f64(<16 x double> %va, <16 x double> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } @@ -841,8 +795,6 @@ define <16 x double> @vfsub_vf_v16f64_unmasked(<16 x double> %va, double %b, i32 ; CHECK-NEXT: ret %elt.head = insertelement <16 x double> poison, double %b, i32 0 %vb = shufflevector <16 x double> %elt.head, <16 x double> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x double> @llvm.vp.fsub.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x double> @llvm.vp.fsub.v16f64(<16 x double> %va, <16 x double> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll index 792c6231aa4a..2181fd8498f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll @@ -16,10 +16,8 @@ define <2 x i8> @vmacc_vv_nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i1 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -31,11 +29,9 @@ define <2 x i8> @vmacc_vv_nxv2i8_unmasked(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %allones, <2 x i8> %y, <2 x i8> %c, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> splat (i1 -1), <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -48,10 +44,8 @@ define <2 x i8> @vmacc_vx_nxv2i8(<2 x i8> %a, i8 %b, <2 x i8> %c, <2 x i1> %m, ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -65,11 +59,9 @@ define <2 x i8> @vmacc_vx_nxv2i8_unmasked(<2 x i8> %a, i8 %b, <2 x i8> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %allones, <2 x i8> %y, <2 x i8> %c, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> splat (i1 -1), <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -80,10 +72,8 @@ define <2 x i8> @vmacc_vv_nxv2i8_ta(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.select.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -97,10 +87,8 @@ define <2 x i8> @vmacc_vx_nxv2i8_ta(<2 x i8> %a, i8 %b, <2 x i8> %c, <2 x i1> % ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.add.nxv2i8(<2 x i8> %x, <2 x i8> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.select.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -117,10 +105,8 @@ define <4 x i8> @vmacc_vv_nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i1 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -132,11 +118,9 @@ define <4 x i8> @vmacc_vv_nxv4i8_unmasked(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %allones, <4 x i8> %y, <4 x i8> %c, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> splat (i1 -1), <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -149,10 +133,8 @@ define <4 x i8> @vmacc_vx_nxv4i8(<4 x i8> %a, i8 %b, <4 x i8> %c, <4 x i1> %m, ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -166,11 +148,9 @@ define <4 x i8> @vmacc_vx_nxv4i8_unmasked(<4 x i8> %a, i8 %b, <4 x i8> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %allones, <4 x i8> %y, <4 x i8> %c, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> splat (i1 -1), <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -181,10 +161,8 @@ define <4 x i8> @vmacc_vv_nxv4i8_ta(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.select.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -198,10 +176,8 @@ define <4 x i8> @vmacc_vx_nxv4i8_ta(<4 x i8> %a, i8 %b, <4 x i8> %c, <4 x i1> % ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.add.nxv4i8(<4 x i8> %x, <4 x i8> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.select.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -218,10 +194,8 @@ define <8 x i8> @vmacc_vv_nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i1 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -233,11 +207,9 @@ define <8 x i8> @vmacc_vv_nxv8i8_unmasked(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %allones, <8 x i8> %y, <8 x i8> %c, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> splat (i1 -1), <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -250,10 +222,8 @@ define <8 x i8> @vmacc_vx_nxv8i8(<8 x i8> %a, i8 %b, <8 x i8> %c, <8 x i1> %m, ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -267,11 +237,9 @@ define <8 x i8> @vmacc_vx_nxv8i8_unmasked(<8 x i8> %a, i8 %b, <8 x i8> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %allones, <8 x i8> %y, <8 x i8> %c, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> splat (i1 -1), <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -282,10 +250,8 @@ define <8 x i8> @vmacc_vv_nxv8i8_ta(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.select.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -299,10 +265,8 @@ define <8 x i8> @vmacc_vx_nxv8i8_ta(<8 x i8> %a, i8 %b, <8 x i8> %c, <8 x i1> % ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.add.nxv8i8(<8 x i8> %x, <8 x i8> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.select.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -319,10 +283,8 @@ define <16 x i8> @vmacc_vv_nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <1 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -334,11 +296,9 @@ define <16 x i8> @vmacc_vv_nxv16i8_unmasked(<16 x i8> %a, <16 x i8> %b, <16 x i8 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %allones, <16 x i8> %y, <16 x i8> %c, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> splat (i1 -1), <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -351,10 +311,8 @@ define <16 x i8> @vmacc_vx_nxv16i8(<16 x i8> %a, i8 %b, <16 x i8> %c, <16 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -368,11 +326,9 @@ define <16 x i8> @vmacc_vx_nxv16i8_unmasked(<16 x i8> %a, i8 %b, <16 x i8> %c, ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %allones, <16 x i8> %y, <16 x i8> %c, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> splat (i1 -1), <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -383,10 +339,8 @@ define <16 x i8> @vmacc_vv_nxv16i8_ta(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.select.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -400,10 +354,8 @@ define <16 x i8> @vmacc_vx_nxv16i8_ta(<16 x i8> %a, i8 %b, <16 x i8> %c, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.add.nxv16i8(<16 x i8> %x, <16 x i8> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.select.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -420,10 +372,8 @@ define <32 x i8> @vmacc_vv_nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, <3 ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -435,11 +385,9 @@ define <32 x i8> @vmacc_vv_nxv32i8_unmasked(<32 x i8> %a, <32 x i8> %b, <32 x i8 ; CHECK-NEXT: vmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %allones, <32 x i8> %y, <32 x i8> %c, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> splat (i1 -1), <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -452,10 +400,8 @@ define <32 x i8> @vmacc_vx_nxv32i8(<32 x i8> %a, i8 %b, <32 x i8> %c, <32 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <32 x i8> poison, i8 %b, i32 0 %vb = shufflevector <32 x i8> %elt.head, <32 x i8> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -469,11 +415,9 @@ define <32 x i8> @vmacc_vx_nxv32i8_unmasked(<32 x i8> %a, i8 %b, <32 x i8> %c, ; CHECK-NEXT: ret %elt.head = insertelement <32 x i8> poison, i8 %b, i32 0 %vb = shufflevector <32 x i8> %elt.head, <32 x i8> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %allones, <32 x i8> %y, <32 x i8> %c, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> splat (i1 -1), <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -484,10 +428,8 @@ define <32 x i8> @vmacc_vv_nxv32i8_ta(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.select.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -501,10 +443,8 @@ define <32 x i8> @vmacc_vx_nxv32i8_ta(<32 x i8> %a, i8 %b, <32 x i8> %c, <32 x ; CHECK-NEXT: ret %elt.head = insertelement <32 x i8> poison, i8 %b, i32 0 %vb = shufflevector <32 x i8> %elt.head, <32 x i8> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.add.nxv32i8(<32 x i8> %x, <32 x i8> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.select.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -521,10 +461,8 @@ define <64 x i8> @vmacc_vv_nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, <6 ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -536,11 +474,9 @@ define <64 x i8> @vmacc_vv_nxv64i8_unmasked(<64 x i8> %a, <64 x i8> %b, <64 x i8 ; CHECK-NEXT: vmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> %allones, i32 %evl) - %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %allones, <64 x i8> %y, <64 x i8> %c, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> splat (i1 -1), i32 %evl) + %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> splat (i1 -1), <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -553,10 +489,8 @@ define <64 x i8> @vmacc_vx_nxv64i8(<64 x i8> %a, i8 %b, <64 x i8> %c, <64 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <64 x i8> poison, i8 %b, i32 0 %vb = shufflevector <64 x i8> %elt.head, <64 x i8> poison, <64 x i32> zeroinitializer - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -570,11 +504,9 @@ define <64 x i8> @vmacc_vx_nxv64i8_unmasked(<64 x i8> %a, i8 %b, <64 x i8> %c, ; CHECK-NEXT: ret %elt.head = insertelement <64 x i8> poison, i8 %b, i32 0 %vb = shufflevector <64 x i8> %elt.head, <64 x i8> poison, <64 x i32> zeroinitializer - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> %allones, i32 %evl) - %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %allones, <64 x i8> %y, <64 x i8> %c, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> splat (i1 -1), i32 %evl) + %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> splat (i1 -1), <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -585,10 +517,8 @@ define <64 x i8> @vmacc_vv_nxv64i8_ta(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.select.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -602,10 +532,8 @@ define <64 x i8> @vmacc_vx_nxv64i8_ta(<64 x i8> %a, i8 %b, <64 x i8> %c, <64 x ; CHECK-NEXT: ret %elt.head = insertelement <64 x i8> poison, i8 %b, i32 0 %vb = shufflevector <64 x i8> %elt.head, <64 x i8> poison, <64 x i32> zeroinitializer - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.add.nxv64i8(<64 x i8> %x, <64 x i8> %c, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.select.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -622,10 +550,8 @@ define <2 x i16> @vmacc_vv_nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -637,11 +563,9 @@ define <2 x i16> @vmacc_vv_nxv2i16_unmasked(<2 x i16> %a, <2 x i16> %b, <2 x i16 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %allones, <2 x i16> %y, <2 x i16> %c, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> splat (i1 -1), <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -654,10 +578,8 @@ define <2 x i16> @vmacc_vx_nxv2i16(<2 x i16> %a, i16 %b, <2 x i16> %c, <2 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -671,11 +593,9 @@ define <2 x i16> @vmacc_vx_nxv2i16_unmasked(<2 x i16> %a, i16 %b, <2 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %allones, <2 x i16> %y, <2 x i16> %c, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> splat (i1 -1), <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -686,10 +606,8 @@ define <2 x i16> @vmacc_vv_nxv2i16_ta(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.select.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -703,10 +621,8 @@ define <2 x i16> @vmacc_vx_nxv2i16_ta(<2 x i16> %a, i16 %b, <2 x i16> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.add.nxv2i16(<2 x i16> %x, <2 x i16> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.select.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -723,10 +639,8 @@ define <4 x i16> @vmacc_vv_nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -738,11 +652,9 @@ define <4 x i16> @vmacc_vv_nxv4i16_unmasked(<4 x i16> %a, <4 x i16> %b, <4 x i16 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %allones, <4 x i16> %y, <4 x i16> %c, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> splat (i1 -1), <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -755,10 +667,8 @@ define <4 x i16> @vmacc_vx_nxv4i16(<4 x i16> %a, i16 %b, <4 x i16> %c, <4 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -772,11 +682,9 @@ define <4 x i16> @vmacc_vx_nxv4i16_unmasked(<4 x i16> %a, i16 %b, <4 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %allones, <4 x i16> %y, <4 x i16> %c, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> splat (i1 -1), <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -787,10 +695,8 @@ define <4 x i16> @vmacc_vv_nxv4i16_ta(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.select.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -804,10 +710,8 @@ define <4 x i16> @vmacc_vx_nxv4i16_ta(<4 x i16> %a, i16 %b, <4 x i16> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.add.nxv4i16(<4 x i16> %x, <4 x i16> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.select.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -824,10 +728,8 @@ define <8 x i16> @vmacc_vv_nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -839,11 +741,9 @@ define <8 x i16> @vmacc_vv_nxv8i16_unmasked(<8 x i16> %a, <8 x i16> %b, <8 x i16 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %allones, <8 x i16> %y, <8 x i16> %c, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> splat (i1 -1), <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -856,10 +756,8 @@ define <8 x i16> @vmacc_vx_nxv8i16(<8 x i16> %a, i16 %b, <8 x i16> %c, <8 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -873,11 +771,9 @@ define <8 x i16> @vmacc_vx_nxv8i16_unmasked(<8 x i16> %a, i16 %b, <8 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %allones, <8 x i16> %y, <8 x i16> %c, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> splat (i1 -1), <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -888,10 +784,8 @@ define <8 x i16> @vmacc_vv_nxv8i16_ta(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.select.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -905,10 +799,8 @@ define <8 x i16> @vmacc_vx_nxv8i16_ta(<8 x i16> %a, i16 %b, <8 x i16> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.add.nxv8i16(<8 x i16> %x, <8 x i16> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.select.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -925,10 +817,8 @@ define <16 x i16> @vmacc_vv_nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -940,11 +830,9 @@ define <16 x i16> @vmacc_vv_nxv16i16_unmasked(<16 x i16> %a, <16 x i16> %b, <16 ; CHECK-NEXT: vmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %allones, <16 x i16> %y, <16 x i16> %c, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> splat (i1 -1), <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -957,10 +845,8 @@ define <16 x i16> @vmacc_vx_nxv16i16(<16 x i16> %a, i16 %b, <16 x i16> %c, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -974,11 +860,9 @@ define <16 x i16> @vmacc_vx_nxv16i16_unmasked(<16 x i16> %a, i16 %b, <16 x i16> ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %allones, <16 x i16> %y, <16 x i16> %c, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> splat (i1 -1), <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -989,10 +873,8 @@ define <16 x i16> @vmacc_vv_nxv16i16_ta(<16 x i16> %a, <16 x i16> %b, <16 x i16> ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.select.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -1006,10 +888,8 @@ define <16 x i16> @vmacc_vx_nxv16i16_ta(<16 x i16> %a, i16 %b, <16 x i16> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.add.nxv16i16(<16 x i16> %x, <16 x i16> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.select.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -1026,10 +906,8 @@ define <32 x i16> @vmacc_vv_nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> %c ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1041,11 +919,9 @@ define <32 x i16> @vmacc_vv_nxv32i16_unmasked(<32 x i16> %a, <32 x i16> %b, <32 ; CHECK-NEXT: vmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %allones, <32 x i16> %y, <32 x i16> %c, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> splat (i1 -1), <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1058,10 +934,8 @@ define <32 x i16> @vmacc_vx_nxv32i16(<32 x i16> %a, i16 %b, <32 x i16> %c, <32 ; CHECK-NEXT: ret %elt.head = insertelement <32 x i16> poison, i16 %b, i32 0 %vb = shufflevector <32 x i16> %elt.head, <32 x i16> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1075,11 +949,9 @@ define <32 x i16> @vmacc_vx_nxv32i16_unmasked(<32 x i16> %a, i16 %b, <32 x i16> ; CHECK-NEXT: ret %elt.head = insertelement <32 x i16> poison, i16 %b, i32 0 %vb = shufflevector <32 x i16> %elt.head, <32 x i16> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> %allones, i32 %evl) - %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %allones, <32 x i16> %y, <32 x i16> %c, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> splat (i1 -1), <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1090,10 +962,8 @@ define <32 x i16> @vmacc_vv_nxv32i16_ta(<32 x i16> %a, <32 x i16> %b, <32 x i16> ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.select.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1107,10 +977,8 @@ define <32 x i16> @vmacc_vx_nxv32i16_ta(<32 x i16> %a, i16 %b, <32 x i16> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <32 x i16> poison, i16 %b, i32 0 %vb = shufflevector <32 x i16> %elt.head, <32 x i16> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.add.nxv32i16(<32 x i16> %x, <32 x i16> %c, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.select.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1127,10 +995,8 @@ define <2 x i32> @vmacc_vv_nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1142,11 +1008,9 @@ define <2 x i32> @vmacc_vv_nxv2i32_unmasked(<2 x i32> %a, <2 x i32> %b, <2 x i32 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %allones, <2 x i32> %y, <2 x i32> %c, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> splat (i1 -1), <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1159,10 +1023,8 @@ define <2 x i32> @vmacc_vx_nxv2i32(<2 x i32> %a, i32 %b, <2 x i32> %c, <2 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1176,11 +1038,9 @@ define <2 x i32> @vmacc_vx_nxv2i32_unmasked(<2 x i32> %a, i32 %b, <2 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %allones, <2 x i32> %y, <2 x i32> %c, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> splat (i1 -1), <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1191,10 +1051,8 @@ define <2 x i32> @vmacc_vv_nxv2i32_ta(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.select.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1208,10 +1066,8 @@ define <2 x i32> @vmacc_vx_nxv2i32_ta(<2 x i32> %a, i32 %b, <2 x i32> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.add.nxv2i32(<2 x i32> %x, <2 x i32> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.select.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1228,10 +1084,8 @@ define <4 x i32> @vmacc_vv_nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1243,11 +1097,9 @@ define <4 x i32> @vmacc_vv_nxv4i32_unmasked(<4 x i32> %a, <4 x i32> %b, <4 x i32 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %allones, <4 x i32> %y, <4 x i32> %c, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> splat (i1 -1), <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1260,10 +1112,8 @@ define <4 x i32> @vmacc_vx_nxv4i32(<4 x i32> %a, i32 %b, <4 x i32> %c, <4 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1277,11 +1127,9 @@ define <4 x i32> @vmacc_vx_nxv4i32_unmasked(<4 x i32> %a, i32 %b, <4 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %allones, <4 x i32> %y, <4 x i32> %c, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> splat (i1 -1), <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1292,10 +1140,8 @@ define <4 x i32> @vmacc_vv_nxv4i32_ta(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.select.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1309,10 +1155,8 @@ define <4 x i32> @vmacc_vx_nxv4i32_ta(<4 x i32> %a, i32 %b, <4 x i32> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.add.nxv4i32(<4 x i32> %x, <4 x i32> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.select.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1329,10 +1173,8 @@ define <8 x i32> @vmacc_vv_nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1344,11 +1186,9 @@ define <8 x i32> @vmacc_vv_nxv8i32_unmasked(<8 x i32> %a, <8 x i32> %b, <8 x i32 ; CHECK-NEXT: vmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %allones, <8 x i32> %y, <8 x i32> %c, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> splat (i1 -1), <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1361,10 +1201,8 @@ define <8 x i32> @vmacc_vx_nxv8i32(<8 x i32> %a, i32 %b, <8 x i32> %c, <8 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1378,11 +1216,9 @@ define <8 x i32> @vmacc_vx_nxv8i32_unmasked(<8 x i32> %a, i32 %b, <8 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %allones, <8 x i32> %y, <8 x i32> %c, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> splat (i1 -1), <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1393,10 +1229,8 @@ define <8 x i32> @vmacc_vv_nxv8i32_ta(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.select.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1410,10 +1244,8 @@ define <8 x i32> @vmacc_vx_nxv8i32_ta(<8 x i32> %a, i32 %b, <8 x i32> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.add.nxv8i32(<8 x i32> %x, <8 x i32> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.select.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1430,10 +1262,8 @@ define <16 x i32> @vmacc_vv_nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> %c ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1445,11 +1275,9 @@ define <16 x i32> @vmacc_vv_nxv16i32_unmasked(<16 x i32> %a, <16 x i32> %b, <16 ; CHECK-NEXT: vmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %allones, <16 x i32> %y, <16 x i32> %c, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> splat (i1 -1), <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1462,10 +1290,8 @@ define <16 x i32> @vmacc_vx_nxv16i32(<16 x i32> %a, i32 %b, <16 x i32> %c, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1479,11 +1305,9 @@ define <16 x i32> @vmacc_vx_nxv16i32_unmasked(<16 x i32> %a, i32 %b, <16 x i32> ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> %allones, i32 %evl) - %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %allones, <16 x i32> %y, <16 x i32> %c, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> splat (i1 -1), <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1494,10 +1318,8 @@ define <16 x i32> @vmacc_vv_nxv16i32_ta(<16 x i32> %a, <16 x i32> %b, <16 x i32> ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.select.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1511,10 +1333,8 @@ define <16 x i32> @vmacc_vx_nxv16i32_ta(<16 x i32> %a, i32 %b, <16 x i32> %c, < ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.add.nxv16i32(<16 x i32> %x, <16 x i32> %c, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.select.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1531,10 +1351,8 @@ define <2 x i64> @vmacc_vv_nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1546,11 +1364,9 @@ define <2 x i64> @vmacc_vv_nxv2i64_unmasked(<2 x i64> %a, <2 x i64> %b, <2 x i64 ; CHECK-NEXT: vmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %allones, <2 x i64> %y, <2 x i64> %c, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> splat (i1 -1), <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1578,10 +1394,8 @@ define <2 x i64> @vmacc_vx_nxv2i64(<2 x i64> %a, i64 %b, <2 x i64> %c, <2 x i1> ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1610,11 +1424,9 @@ define <2 x i64> @vmacc_vx_nxv2i64_unmasked(<2 x i64> %a, i64 %b, <2 x i64> %c, ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> %allones, i32 %evl) - %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %allones, <2 x i64> %y, <2 x i64> %c, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> splat (i1 -1), <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1625,10 +1437,8 @@ define <2 x i64> @vmacc_vv_nxv2i64_ta(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, ; CHECK-NEXT: vmacc.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.select.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1657,10 +1467,8 @@ define <2 x i64> @vmacc_vx_nxv2i64_ta(<2 x i64> %a, i64 %b, <2 x i64> %c, <2 x ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.add.nxv2i64(<2 x i64> %x, <2 x i64> %c, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.select.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1677,10 +1485,8 @@ define <4 x i64> @vmacc_vv_nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1692,11 +1498,9 @@ define <4 x i64> @vmacc_vv_nxv4i64_unmasked(<4 x i64> %a, <4 x i64> %b, <4 x i64 ; CHECK-NEXT: vmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %allones, <4 x i64> %y, <4 x i64> %c, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> splat (i1 -1), <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1724,10 +1528,8 @@ define <4 x i64> @vmacc_vx_nxv4i64(<4 x i64> %a, i64 %b, <4 x i64> %c, <4 x i1> ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1756,11 +1558,9 @@ define <4 x i64> @vmacc_vx_nxv4i64_unmasked(<4 x i64> %a, i64 %b, <4 x i64> %c, ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> %allones, i32 %evl) - %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %allones, <4 x i64> %y, <4 x i64> %c, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> splat (i1 -1), <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1771,10 +1571,8 @@ define <4 x i64> @vmacc_vv_nxv4i64_ta(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, ; CHECK-NEXT: vmacc.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.select.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1803,10 +1601,8 @@ define <4 x i64> @vmacc_vx_nxv4i64_ta(<4 x i64> %a, i64 %b, <4 x i64> %c, <4 x ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.add.nxv4i64(<4 x i64> %x, <4 x i64> %c, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.select.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1823,10 +1619,8 @@ define <8 x i64> @vmacc_vv_nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1838,11 +1632,9 @@ define <8 x i64> @vmacc_vv_nxv8i64_unmasked(<8 x i64> %a, <8 x i64> %b, <8 x i64 ; CHECK-NEXT: vmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %allones, <8 x i64> %y, <8 x i64> %c, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> splat (i1 -1), <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1870,10 +1662,8 @@ define <8 x i64> @vmacc_vx_nxv8i64(<8 x i64> %a, i64 %b, <8 x i64> %c, <8 x i1> ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1902,11 +1692,9 @@ define <8 x i64> @vmacc_vx_nxv8i64_unmasked(<8 x i64> %a, i64 %b, <8 x i64> %c, ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> %allones, i32 %evl) - %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %allones, <8 x i64> %y, <8 x i64> %c, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> splat (i1 -1), <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1917,10 +1705,8 @@ define <8 x i64> @vmacc_vv_nxv8i64_ta(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, ; CHECK-NEXT: vmacc.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.select.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1949,10 +1735,8 @@ define <8 x i64> @vmacc_vx_nxv8i64_ta(<8 x i64> %a, i64 %b, <8 x i64> %c, <8 x ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.add.nxv8i64(<8 x i64> %x, <8 x i64> %c, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.select.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll index 6af5ba185b8b..3042d9dd1cbb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll @@ -39,9 +39,7 @@ define <2 x i8> @vmax_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.smax.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.smax.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -65,9 +63,7 @@ define <2 x i8> @vmax_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.smax.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.smax.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -89,9 +85,7 @@ define <4 x i8> @vmax_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.smax.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.smax.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -127,9 +121,7 @@ define <4 x i8> @vmax_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.smax.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.smax.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -151,9 +143,7 @@ define <5 x i8> @vmax_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.smax.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.smax.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -177,9 +167,7 @@ define <5 x i8> @vmax_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.smax.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.smax.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -201,9 +189,7 @@ define <8 x i8> @vmax_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.smax.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.smax.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -227,9 +213,7 @@ define <8 x i8> @vmax_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.smax.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.smax.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -251,9 +235,7 @@ define <16 x i8> @vmax_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.smax.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.smax.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -277,9 +259,7 @@ define <16 x i8> @vmax_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.smax.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.smax.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -332,9 +312,7 @@ define <256 x i8> @vmax_vx_v258i8_unmasked(<256 x i8> %va, i8 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0 %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.smax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.smax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -390,9 +368,7 @@ define <2 x i16> @vmax_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.smax.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.smax.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -416,9 +392,7 @@ define <2 x i16> @vmax_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.smax.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.smax.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -440,9 +414,7 @@ define <4 x i16> @vmax_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.smax.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.smax.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -466,9 +438,7 @@ define <4 x i16> @vmax_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.smax.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.smax.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -490,9 +460,7 @@ define <8 x i16> @vmax_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.smax.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.smax.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -516,9 +484,7 @@ define <8 x i16> @vmax_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.smax.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.smax.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -540,9 +506,7 @@ define <16 x i16> @vmax_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.smax.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.smax.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -566,9 +530,7 @@ define <16 x i16> @vmax_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.smax.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.smax.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -590,9 +552,7 @@ define <2 x i32> @vmax_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.smax.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.smax.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -616,9 +576,7 @@ define <2 x i32> @vmax_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.smax.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.smax.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -640,9 +598,7 @@ define <4 x i32> @vmax_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.smax.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.smax.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -666,9 +622,7 @@ define <4 x i32> @vmax_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.smax.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.smax.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -690,9 +644,7 @@ define <8 x i32> @vmax_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.smax.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.smax.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -716,9 +668,7 @@ define <8 x i32> @vmax_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.smax.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.smax.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -740,9 +690,7 @@ define <16 x i32> @vmax_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.smax.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.smax.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -766,9 +714,7 @@ define <16 x i32> @vmax_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.smax.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.smax.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -790,9 +736,7 @@ define <2 x i64> @vmax_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.smax.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.smax.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -844,9 +788,7 @@ define <2 x i64> @vmax_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.smax.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.smax.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -868,9 +810,7 @@ define <4 x i64> @vmax_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.smax.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.smax.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -922,9 +862,7 @@ define <4 x i64> @vmax_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.smax.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.smax.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -946,9 +884,7 @@ define <8 x i64> @vmax_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.smax.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.smax.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1000,9 +936,7 @@ define <8 x i64> @vmax_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.smax.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.smax.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1024,9 +958,7 @@ define <16 x i64> @vmax_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.smax.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.smax.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1078,9 +1010,7 @@ define <16 x i64> @vmax_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.smax.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.smax.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll index 12c6410068c6..36a9e6d42fec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll @@ -38,9 +38,7 @@ define <2 x i8> @vmaxu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -64,9 +62,7 @@ define <2 x i8> @vmaxu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.umax.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -88,9 +84,7 @@ define <4 x i8> @vmaxu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -126,9 +120,7 @@ define <4 x i8> @vmaxu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.umax.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -150,9 +142,7 @@ define <5 x i8> @vmaxu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -176,9 +166,7 @@ define <5 x i8> @vmaxu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.umax.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -200,9 +188,7 @@ define <8 x i8> @vmaxu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -226,9 +212,7 @@ define <8 x i8> @vmaxu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.umax.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -250,9 +234,7 @@ define <16 x i8> @vmaxu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -276,9 +258,7 @@ define <16 x i8> @vmaxu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.umax.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -331,9 +311,7 @@ define <256 x i8> @vmaxu_vx_v258i8_unmasked(<256 x i8> %va, i8 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0 %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.umax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.umax.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -389,9 +367,7 @@ define <2 x i16> @vmaxu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -415,9 +391,7 @@ define <2 x i16> @vmaxu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.umax.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -439,9 +413,7 @@ define <4 x i16> @vmaxu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -465,9 +437,7 @@ define <4 x i16> @vmaxu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.umax.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -489,9 +459,7 @@ define <8 x i16> @vmaxu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -515,9 +483,7 @@ define <8 x i16> @vmaxu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.umax.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -539,9 +505,7 @@ define <16 x i16> @vmaxu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -565,9 +529,7 @@ define <16 x i16> @vmaxu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.umax.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -589,9 +551,7 @@ define <2 x i32> @vmaxu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -615,9 +575,7 @@ define <2 x i32> @vmaxu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.umax.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -639,9 +597,7 @@ define <4 x i32> @vmaxu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -665,9 +621,7 @@ define <4 x i32> @vmaxu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.umax.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -689,9 +643,7 @@ define <8 x i32> @vmaxu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -715,9 +667,7 @@ define <8 x i32> @vmaxu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.umax.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -739,9 +689,7 @@ define <16 x i32> @vmaxu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -765,9 +713,7 @@ define <16 x i32> @vmaxu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.umax.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -789,9 +735,7 @@ define <2 x i64> @vmaxu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -843,9 +787,7 @@ define <2 x i64> @vmaxu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.umax.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -867,9 +809,7 @@ define <4 x i64> @vmaxu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -921,9 +861,7 @@ define <4 x i64> @vmaxu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.umax.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -945,9 +883,7 @@ define <8 x i64> @vmaxu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -999,9 +935,7 @@ define <8 x i64> @vmaxu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.umax.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1023,9 +957,7 @@ define <16 x i64> @vmaxu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1077,9 +1009,7 @@ define <16 x i64> @vmaxu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.umax.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll index f5b9421d28c3..8a6dccd76e9b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll @@ -39,9 +39,7 @@ define <2 x i8> @vmin_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.smin.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.smin.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -65,9 +63,7 @@ define <2 x i8> @vmin_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.smin.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.smin.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -89,9 +85,7 @@ define <4 x i8> @vmin_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.smin.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.smin.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -127,9 +121,7 @@ define <4 x i8> @vmin_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.smin.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.smin.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -151,9 +143,7 @@ define <5 x i8> @vmin_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.smin.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.smin.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -177,9 +167,7 @@ define <5 x i8> @vmin_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.smin.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.smin.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -201,9 +189,7 @@ define <8 x i8> @vmin_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.smin.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.smin.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -227,9 +213,7 @@ define <8 x i8> @vmin_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.smin.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.smin.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -251,9 +235,7 @@ define <16 x i8> @vmin_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.smin.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.smin.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -277,9 +259,7 @@ define <16 x i8> @vmin_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.smin.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.smin.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -332,9 +312,7 @@ define <256 x i8> @vmin_vx_v258i8_unmasked(<256 x i8> %va, i8 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0 %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.smin.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.smin.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -390,9 +368,7 @@ define <2 x i16> @vmin_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.smin.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.smin.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -416,9 +392,7 @@ define <2 x i16> @vmin_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.smin.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.smin.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -440,9 +414,7 @@ define <4 x i16> @vmin_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.smin.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.smin.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -466,9 +438,7 @@ define <4 x i16> @vmin_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.smin.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.smin.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -490,9 +460,7 @@ define <8 x i16> @vmin_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.smin.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.smin.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -516,9 +484,7 @@ define <8 x i16> @vmin_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.smin.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.smin.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -540,9 +506,7 @@ define <16 x i16> @vmin_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.smin.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.smin.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -566,9 +530,7 @@ define <16 x i16> @vmin_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.smin.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.smin.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -590,9 +552,7 @@ define <2 x i32> @vmin_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.smin.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.smin.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -616,9 +576,7 @@ define <2 x i32> @vmin_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.smin.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.smin.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -640,9 +598,7 @@ define <4 x i32> @vmin_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.smin.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.smin.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -666,9 +622,7 @@ define <4 x i32> @vmin_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.smin.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.smin.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -690,9 +644,7 @@ define <8 x i32> @vmin_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.smin.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.smin.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -716,9 +668,7 @@ define <8 x i32> @vmin_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.smin.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.smin.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -740,9 +690,7 @@ define <16 x i32> @vmin_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.smin.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.smin.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -766,9 +714,7 @@ define <16 x i32> @vmin_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.smin.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.smin.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -790,9 +736,7 @@ define <2 x i64> @vmin_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.smin.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.smin.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -844,9 +788,7 @@ define <2 x i64> @vmin_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.smin.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.smin.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -868,9 +810,7 @@ define <4 x i64> @vmin_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.smin.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.smin.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -922,9 +862,7 @@ define <4 x i64> @vmin_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.smin.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.smin.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -946,9 +884,7 @@ define <8 x i64> @vmin_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.smin.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.smin.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1000,9 +936,7 @@ define <8 x i64> @vmin_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.smin.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.smin.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1024,9 +958,7 @@ define <16 x i64> @vmin_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.smin.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.smin.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1078,9 +1010,7 @@ define <16 x i64> @vmin_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.smin.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.smin.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll index d07580efceb5..a56514c70bb0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll @@ -38,9 +38,7 @@ define <2 x i8> @vminu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.umin.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.umin.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -64,9 +62,7 @@ define <2 x i8> @vminu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.umin.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.umin.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -88,9 +84,7 @@ define <4 x i8> @vminu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.umin.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.umin.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -126,9 +120,7 @@ define <4 x i8> @vminu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.umin.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.umin.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -150,9 +142,7 @@ define <5 x i8> @vminu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.umin.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.umin.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -176,9 +166,7 @@ define <5 x i8> @vminu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.umin.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.umin.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -200,9 +188,7 @@ define <8 x i8> @vminu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.umin.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.umin.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -226,9 +212,7 @@ define <8 x i8> @vminu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.umin.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.umin.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -250,9 +234,7 @@ define <16 x i8> @vminu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.umin.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.umin.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -276,9 +258,7 @@ define <16 x i8> @vminu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.umin.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.umin.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -331,9 +311,7 @@ define <256 x i8> @vminu_vx_v258i8_unmasked(<256 x i8> %va, i8 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <256 x i8> poison, i8 %b, i32 0 %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.umin.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.umin.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -389,9 +367,7 @@ define <2 x i16> @vminu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.umin.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.umin.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -415,9 +391,7 @@ define <2 x i16> @vminu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.umin.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.umin.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -439,9 +413,7 @@ define <4 x i16> @vminu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.umin.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.umin.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -465,9 +437,7 @@ define <4 x i16> @vminu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.umin.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.umin.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -489,9 +459,7 @@ define <8 x i16> @vminu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.umin.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.umin.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -515,9 +483,7 @@ define <8 x i16> @vminu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.umin.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.umin.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -539,9 +505,7 @@ define <16 x i16> @vminu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.umin.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.umin.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -565,9 +529,7 @@ define <16 x i16> @vminu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.umin.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.umin.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -589,9 +551,7 @@ define <2 x i32> @vminu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.umin.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.umin.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -615,9 +575,7 @@ define <2 x i32> @vminu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.umin.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.umin.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -639,9 +597,7 @@ define <4 x i32> @vminu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.umin.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.umin.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -665,9 +621,7 @@ define <4 x i32> @vminu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.umin.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.umin.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -689,9 +643,7 @@ define <8 x i32> @vminu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.umin.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.umin.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -715,9 +667,7 @@ define <8 x i32> @vminu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.umin.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.umin.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -739,9 +689,7 @@ define <16 x i32> @vminu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.umin.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.umin.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -765,9 +713,7 @@ define <16 x i32> @vminu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.umin.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.umin.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -789,9 +735,7 @@ define <2 x i64> @vminu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.umin.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.umin.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -843,9 +787,7 @@ define <2 x i64> @vminu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.umin.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.umin.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -867,9 +809,7 @@ define <4 x i64> @vminu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.umin.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.umin.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -921,9 +861,7 @@ define <4 x i64> @vminu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.umin.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.umin.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -945,9 +883,7 @@ define <8 x i64> @vminu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.umin.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.umin.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -999,9 +935,7 @@ define <8 x i64> @vminu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.umin.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.umin.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1023,9 +957,7 @@ define <16 x i64> @vminu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.umin.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.umin.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1077,9 +1009,7 @@ define <16 x i64> @vminu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.umin.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.umin.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll index fbb97d6bf322..2525ac03ea9a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll @@ -34,9 +34,7 @@ define <2 x i8> @vmul_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.mul.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.mul.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -60,9 +58,7 @@ define <2 x i8> @vmul_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.mul.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.mul.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -84,9 +80,7 @@ define <4 x i8> @vmul_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.mul.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.mul.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -110,9 +104,7 @@ define <4 x i8> @vmul_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.mul.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.mul.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -134,9 +126,7 @@ define <8 x i8> @vmul_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.mul.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.mul.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -160,9 +150,7 @@ define <8 x i8> @vmul_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.mul.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.mul.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -184,9 +172,7 @@ define <16 x i8> @vmul_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.mul.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.mul.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -210,9 +196,7 @@ define <16 x i8> @vmul_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.mul.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.mul.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -234,9 +218,7 @@ define <2 x i16> @vmul_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.mul.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.mul.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -260,9 +242,7 @@ define <2 x i16> @vmul_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.mul.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.mul.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -284,9 +264,7 @@ define <4 x i16> @vmul_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.mul.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.mul.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -310,9 +288,7 @@ define <4 x i16> @vmul_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.mul.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.mul.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -334,9 +310,7 @@ define <8 x i16> @vmul_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.mul.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.mul.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -372,9 +346,7 @@ define <8 x i16> @vmul_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.mul.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.mul.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -396,9 +368,7 @@ define <12 x i16> @vmul_vv_v12i16_unmasked(<12 x i16> %va, <12 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <12 x i1> poison, i1 true, i32 0 - %m = shufflevector <12 x i1> %head, <12 x i1> poison, <12 x i32> zeroinitializer - %v = call <12 x i16> @llvm.vp.mul.v12i16(<12 x i16> %va, <12 x i16> %b, <12 x i1> %m, i32 %evl) + %v = call <12 x i16> @llvm.vp.mul.v12i16(<12 x i16> %va, <12 x i16> %b, <12 x i1> splat (i1 true), i32 %evl) ret <12 x i16> %v } @@ -422,9 +392,7 @@ define <12 x i16> @vmul_vx_v12i16_unmasked(<12 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <12 x i16> poison, i16 %b, i32 0 %vb = shufflevector <12 x i16> %elt.head, <12 x i16> poison, <12 x i32> zeroinitializer - %head = insertelement <12 x i1> poison, i1 true, i32 0 - %m = shufflevector <12 x i1> %head, <12 x i1> poison, <12 x i32> zeroinitializer - %v = call <12 x i16> @llvm.vp.mul.v12i16(<12 x i16> %va, <12 x i16> %vb, <12 x i1> %m, i32 %evl) + %v = call <12 x i16> @llvm.vp.mul.v12i16(<12 x i16> %va, <12 x i16> %vb, <12 x i1> splat (i1 true), i32 %evl) ret <12 x i16> %v } @@ -446,9 +414,7 @@ define <16 x i16> @vmul_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.mul.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.mul.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -472,9 +438,7 @@ define <16 x i16> @vmul_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.mul.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.mul.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -496,9 +460,7 @@ define <2 x i32> @vmul_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.mul.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.mul.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -522,9 +484,7 @@ define <2 x i32> @vmul_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.mul.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.mul.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -546,9 +506,7 @@ define <4 x i32> @vmul_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -572,9 +530,7 @@ define <4 x i32> @vmul_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.mul.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -596,9 +552,7 @@ define <8 x i32> @vmul_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -622,9 +576,7 @@ define <8 x i32> @vmul_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -646,9 +598,7 @@ define <16 x i32> @vmul_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.mul.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.mul.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -672,9 +622,7 @@ define <16 x i32> @vmul_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.mul.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.mul.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -696,9 +644,7 @@ define <2 x i64> @vmul_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.mul.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.mul.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -750,9 +696,7 @@ define <2 x i64> @vmul_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.mul.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.mul.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -774,9 +718,7 @@ define <4 x i64> @vmul_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.mul.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.mul.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -828,9 +770,7 @@ define <4 x i64> @vmul_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.mul.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.mul.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -852,9 +792,7 @@ define <8 x i64> @vmul_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.mul.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.mul.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -906,9 +844,7 @@ define <8 x i64> @vmul_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.mul.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.mul.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -930,9 +866,7 @@ define <16 x i64> @vmul_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.mul.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.mul.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -984,8 +918,6 @@ define <16 x i64> @vmul_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.mul.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.mul.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll index 744ed991bccc..695fba6d54e0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll @@ -16,10 +16,8 @@ define <2 x i8> @vnmsac_vv_nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 x i ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -31,11 +29,9 @@ define <2 x i8> @vnmsac_vv_nxv2i8_unmasked(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %allones, <2 x i8> %y, <2 x i8> %c, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> splat (i1 -1), <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -48,10 +44,8 @@ define <2 x i8> @vnmsac_vx_nxv2i8(<2 x i8> %a, i8 %b, <2 x i8> %c, <2 x i1> %m, ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -65,11 +59,9 @@ define <2 x i8> @vnmsac_vx_nxv2i8_unmasked(<2 x i8> %a, i8 %b, <2 x i8> %c, <2 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> %allones, <2 x i8> %y, <2 x i8> %c, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i8> @llvm.vp.merge.nxv2i8(<2 x i1> splat (i1 -1), <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -80,10 +72,8 @@ define <2 x i8> @vnmsac_vv_nxv2i8_ta(<2 x i8> %a, <2 x i8> %b, <2 x i8> %c, <2 ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.select.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -97,10 +87,8 @@ define <2 x i8> @vnmsac_vx_nxv2i8_ta(<2 x i8> %a, i8 %b, <2 x i8> %c, <2 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i8> @llvm.vp.mul.nxv2i8(<2 x i8> %a, <2 x i8> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i8> @llvm.vp.sub.nxv2i8(<2 x i8> %c, <2 x i8> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i8> @llvm.vp.select.nxv2i8(<2 x i1> %m, <2 x i8> %y, <2 x i8> %c, i32 %evl) ret <2 x i8> %u } @@ -117,10 +105,8 @@ define <4 x i8> @vnmsac_vv_nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -132,11 +118,9 @@ define <4 x i8> @vnmsac_vv_nxv4i8_unmasked(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %allones, <4 x i8> %y, <4 x i8> %c, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> splat (i1 -1), <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -149,10 +133,8 @@ define <4 x i8> @vnmsac_vx_nxv4i8(<4 x i8> %a, i8 %b, <4 x i8> %c, <4 x i1> %m, ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -166,11 +148,9 @@ define <4 x i8> @vnmsac_vx_nxv4i8_unmasked(<4 x i8> %a, i8 %b, <4 x i8> %c, <4 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> %allones, <4 x i8> %y, <4 x i8> %c, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i8> @llvm.vp.merge.nxv4i8(<4 x i1> splat (i1 -1), <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -181,10 +161,8 @@ define <4 x i8> @vnmsac_vv_nxv4i8_ta(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.select.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -198,10 +176,8 @@ define <4 x i8> @vnmsac_vx_nxv4i8_ta(<4 x i8> %a, i8 %b, <4 x i8> %c, <4 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i8> @llvm.vp.mul.nxv4i8(<4 x i8> %a, <4 x i8> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i8> @llvm.vp.sub.nxv4i8(<4 x i8> %c, <4 x i8> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i8> @llvm.vp.select.nxv4i8(<4 x i1> %m, <4 x i8> %y, <4 x i8> %c, i32 %evl) ret <4 x i8> %u } @@ -218,10 +194,8 @@ define <8 x i8> @vnmsac_vv_nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -233,11 +207,9 @@ define <8 x i8> @vnmsac_vv_nxv8i8_unmasked(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %allones, <8 x i8> %y, <8 x i8> %c, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> splat (i1 -1), <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -250,10 +222,8 @@ define <8 x i8> @vnmsac_vx_nxv8i8(<8 x i8> %a, i8 %b, <8 x i8> %c, <8 x i1> %m, ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -267,11 +237,9 @@ define <8 x i8> @vnmsac_vx_nxv8i8_unmasked(<8 x i8> %a, i8 %b, <8 x i8> %c, <8 ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> %allones, <8 x i8> %y, <8 x i8> %c, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i8> @llvm.vp.merge.nxv8i8(<8 x i1> splat (i1 -1), <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -282,10 +250,8 @@ define <8 x i8> @vnmsac_vv_nxv8i8_ta(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.select.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -299,10 +265,8 @@ define <8 x i8> @vnmsac_vx_nxv8i8_ta(<8 x i8> %a, i8 %b, <8 x i8> %c, <8 x i1> ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i8> @llvm.vp.mul.nxv8i8(<8 x i8> %a, <8 x i8> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i8> @llvm.vp.sub.nxv8i8(<8 x i8> %c, <8 x i8> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i8> @llvm.vp.select.nxv8i8(<8 x i1> %m, <8 x i8> %y, <8 x i8> %c, i32 %evl) ret <8 x i8> %u } @@ -319,10 +283,8 @@ define <16 x i8> @vnmsac_vv_nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -334,11 +296,9 @@ define <16 x i8> @vnmsac_vv_nxv16i8_unmasked(<16 x i8> %a, <16 x i8> %b, <16 x i ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> %allones, i32 %evl) - %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %allones, <16 x i8> %y, <16 x i8> %c, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> splat (i1 -1), <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -351,10 +311,8 @@ define <16 x i8> @vnmsac_vx_nxv16i8(<16 x i8> %a, i8 %b, <16 x i8> %c, <16 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -368,11 +326,9 @@ define <16 x i8> @vnmsac_vx_nxv16i8_unmasked(<16 x i8> %a, i8 %b, <16 x i8> %c, ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> %allones, i32 %evl) - %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> %allones, <16 x i8> %y, <16 x i8> %c, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i8> @llvm.vp.merge.nxv16i8(<16 x i1> splat (i1 -1), <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -383,10 +339,8 @@ define <16 x i8> @vnmsac_vv_nxv16i8_ta(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.select.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -400,10 +354,8 @@ define <16 x i8> @vnmsac_vx_nxv16i8_ta(<16 x i8> %a, i8 %b, <16 x i8> %c, <16 x ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i8> @llvm.vp.mul.nxv16i8(<16 x i8> %a, <16 x i8> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i8> @llvm.vp.sub.nxv16i8(<16 x i8> %c, <16 x i8> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i8> @llvm.vp.select.nxv16i8(<16 x i1> %m, <16 x i8> %y, <16 x i8> %c, i32 %evl) ret <16 x i8> %u } @@ -420,10 +372,8 @@ define <32 x i8> @vnmsac_vv_nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, < ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -435,11 +385,9 @@ define <32 x i8> @vnmsac_vv_nxv32i8_unmasked(<32 x i8> %a, <32 x i8> %b, <32 x i ; CHECK-NEXT: vnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> %allones, i32 %evl) - %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %allones, <32 x i8> %y, <32 x i8> %c, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> splat (i1 -1), <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -452,10 +400,8 @@ define <32 x i8> @vnmsac_vx_nxv32i8(<32 x i8> %a, i8 %b, <32 x i8> %c, <32 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <32 x i8> poison, i8 %b, i32 0 %vb = shufflevector <32 x i8> %elt.head, <32 x i8> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -469,11 +415,9 @@ define <32 x i8> @vnmsac_vx_nxv32i8_unmasked(<32 x i8> %a, i8 %b, <32 x i8> %c, ; CHECK-NEXT: ret %elt.head = insertelement <32 x i8> poison, i8 %b, i32 0 %vb = shufflevector <32 x i8> %elt.head, <32 x i8> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> %allones, i32 %evl) - %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> %allones, <32 x i8> %y, <32 x i8> %c, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i8> @llvm.vp.merge.nxv32i8(<32 x i1> splat (i1 -1), <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -484,10 +428,8 @@ define <32 x i8> @vnmsac_vv_nxv32i8_ta(<32 x i8> %a, <32 x i8> %b, <32 x i8> %c, ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.select.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -501,10 +443,8 @@ define <32 x i8> @vnmsac_vx_nxv32i8_ta(<32 x i8> %a, i8 %b, <32 x i8> %c, <32 x ; CHECK-NEXT: ret %elt.head = insertelement <32 x i8> poison, i8 %b, i32 0 %vb = shufflevector <32 x i8> %elt.head, <32 x i8> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i8> @llvm.vp.mul.nxv32i8(<32 x i8> %a, <32 x i8> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i8> @llvm.vp.sub.nxv32i8(<32 x i8> %c, <32 x i8> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i8> @llvm.vp.select.nxv32i8(<32 x i1> %m, <32 x i8> %y, <32 x i8> %c, i32 %evl) ret <32 x i8> %u } @@ -521,10 +461,8 @@ define <64 x i8> @vnmsac_vv_nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, < ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -536,11 +474,9 @@ define <64 x i8> @vnmsac_vv_nxv64i8_unmasked(<64 x i8> %a, <64 x i8> %b, <64 x i ; CHECK-NEXT: vnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> %allones, i32 %evl) - %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %allones, <64 x i8> %y, <64 x i8> %c, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> splat (i1 -1), i32 %evl) + %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> splat (i1 -1), <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -553,10 +489,8 @@ define <64 x i8> @vnmsac_vx_nxv64i8(<64 x i8> %a, i8 %b, <64 x i8> %c, <64 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <64 x i8> poison, i8 %b, i32 0 %vb = shufflevector <64 x i8> %elt.head, <64 x i8> poison, <64 x i32> zeroinitializer - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -570,11 +504,9 @@ define <64 x i8> @vnmsac_vx_nxv64i8_unmasked(<64 x i8> %a, i8 %b, <64 x i8> %c, ; CHECK-NEXT: ret %elt.head = insertelement <64 x i8> poison, i8 %b, i32 0 %vb = shufflevector <64 x i8> %elt.head, <64 x i8> poison, <64 x i32> zeroinitializer - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> %allones, i32 %evl) - %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> %allones, <64 x i8> %y, <64 x i8> %c, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> splat (i1 -1), i32 %evl) + %u = call <64 x i8> @llvm.vp.merge.nxv64i8(<64 x i1> splat (i1 -1), <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -585,10 +517,8 @@ define <64 x i8> @vnmsac_vv_nxv64i8_ta(<64 x i8> %a, <64 x i8> %b, <64 x i8> %c, ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %b, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.select.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -602,10 +532,8 @@ define <64 x i8> @vnmsac_vx_nxv64i8_ta(<64 x i8> %a, i8 %b, <64 x i8> %c, <64 x ; CHECK-NEXT: ret %elt.head = insertelement <64 x i8> poison, i8 %b, i32 0 %vb = shufflevector <64 x i8> %elt.head, <64 x i8> poison, <64 x i32> zeroinitializer - %splat = insertelement <64 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <64 x i1> %splat, <64 x i1> poison, <64 x i32> zeroinitializer - %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> %allones, i32 %evl) - %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> %allones, i32 %evl) + %x = call <64 x i8> @llvm.vp.mul.nxv64i8(<64 x i8> %a, <64 x i8> %vb, <64 x i1> splat (i1 -1), i32 %evl) + %y = call <64 x i8> @llvm.vp.sub.nxv64i8(<64 x i8> %c, <64 x i8> %x, <64 x i1> splat (i1 -1), i32 %evl) %u = call <64 x i8> @llvm.vp.select.nxv64i8(<64 x i1> %m, <64 x i8> %y, <64 x i8> %c, i32 %evl) ret <64 x i8> %u } @@ -622,10 +550,8 @@ define <2 x i16> @vnmsac_vv_nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -637,11 +563,9 @@ define <2 x i16> @vnmsac_vv_nxv2i16_unmasked(<2 x i16> %a, <2 x i16> %b, <2 x i1 ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %allones, <2 x i16> %y, <2 x i16> %c, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> splat (i1 -1), <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -654,10 +578,8 @@ define <2 x i16> @vnmsac_vx_nxv2i16(<2 x i16> %a, i16 %b, <2 x i16> %c, <2 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -671,11 +593,9 @@ define <2 x i16> @vnmsac_vx_nxv2i16_unmasked(<2 x i16> %a, i16 %b, <2 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> %allones, <2 x i16> %y, <2 x i16> %c, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i16> @llvm.vp.merge.nxv2i16(<2 x i1> splat (i1 -1), <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -686,10 +606,8 @@ define <2 x i16> @vnmsac_vv_nxv2i16_ta(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.select.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -703,10 +621,8 @@ define <2 x i16> @vnmsac_vx_nxv2i16_ta(<2 x i16> %a, i16 %b, <2 x i16> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i16> @llvm.vp.mul.nxv2i16(<2 x i16> %a, <2 x i16> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i16> @llvm.vp.sub.nxv2i16(<2 x i16> %c, <2 x i16> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i16> @llvm.vp.select.nxv2i16(<2 x i1> %m, <2 x i16> %y, <2 x i16> %c, i32 %evl) ret <2 x i16> %u } @@ -723,10 +639,8 @@ define <4 x i16> @vnmsac_vv_nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -738,11 +652,9 @@ define <4 x i16> @vnmsac_vv_nxv4i16_unmasked(<4 x i16> %a, <4 x i16> %b, <4 x i1 ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %allones, <4 x i16> %y, <4 x i16> %c, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> splat (i1 -1), <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -755,10 +667,8 @@ define <4 x i16> @vnmsac_vx_nxv4i16(<4 x i16> %a, i16 %b, <4 x i16> %c, <4 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -772,11 +682,9 @@ define <4 x i16> @vnmsac_vx_nxv4i16_unmasked(<4 x i16> %a, i16 %b, <4 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> %allones, <4 x i16> %y, <4 x i16> %c, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i16> @llvm.vp.merge.nxv4i16(<4 x i1> splat (i1 -1), <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -787,10 +695,8 @@ define <4 x i16> @vnmsac_vv_nxv4i16_ta(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.select.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -804,10 +710,8 @@ define <4 x i16> @vnmsac_vx_nxv4i16_ta(<4 x i16> %a, i16 %b, <4 x i16> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i16> @llvm.vp.mul.nxv4i16(<4 x i16> %a, <4 x i16> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i16> @llvm.vp.sub.nxv4i16(<4 x i16> %c, <4 x i16> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i16> @llvm.vp.select.nxv4i16(<4 x i1> %m, <4 x i16> %y, <4 x i16> %c, i32 %evl) ret <4 x i16> %u } @@ -824,10 +728,8 @@ define <8 x i16> @vnmsac_vv_nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -839,11 +741,9 @@ define <8 x i16> @vnmsac_vv_nxv8i16_unmasked(<8 x i16> %a, <8 x i16> %b, <8 x i1 ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %allones, <8 x i16> %y, <8 x i16> %c, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> splat (i1 -1), <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -856,10 +756,8 @@ define <8 x i16> @vnmsac_vx_nxv8i16(<8 x i16> %a, i16 %b, <8 x i16> %c, <8 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -873,11 +771,9 @@ define <8 x i16> @vnmsac_vx_nxv8i16_unmasked(<8 x i16> %a, i16 %b, <8 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> %allones, <8 x i16> %y, <8 x i16> %c, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i16> @llvm.vp.merge.nxv8i16(<8 x i1> splat (i1 -1), <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -888,10 +784,8 @@ define <8 x i16> @vnmsac_vv_nxv8i16_ta(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.select.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -905,10 +799,8 @@ define <8 x i16> @vnmsac_vx_nxv8i16_ta(<8 x i16> %a, i16 %b, <8 x i16> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i16> @llvm.vp.mul.nxv8i16(<8 x i16> %a, <8 x i16> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i16> @llvm.vp.sub.nxv8i16(<8 x i16> %c, <8 x i16> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i16> @llvm.vp.select.nxv8i16(<8 x i1> %m, <8 x i16> %y, <8 x i16> %c, i32 %evl) ret <8 x i16> %u } @@ -925,10 +817,8 @@ define <16 x i16> @vnmsac_vv_nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> % ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -940,11 +830,9 @@ define <16 x i16> @vnmsac_vv_nxv16i16_unmasked(<16 x i16> %a, <16 x i16> %b, <16 ; CHECK-NEXT: vnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> %allones, i32 %evl) - %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %allones, <16 x i16> %y, <16 x i16> %c, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> splat (i1 -1), <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -957,10 +845,8 @@ define <16 x i16> @vnmsac_vx_nxv16i16(<16 x i16> %a, i16 %b, <16 x i16> %c, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -974,11 +860,9 @@ define <16 x i16> @vnmsac_vx_nxv16i16_unmasked(<16 x i16> %a, i16 %b, <16 x i16> ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> %allones, i32 %evl) - %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> %allones, <16 x i16> %y, <16 x i16> %c, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i16> @llvm.vp.merge.nxv16i16(<16 x i1> splat (i1 -1), <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -989,10 +873,8 @@ define <16 x i16> @vnmsac_vv_nxv16i16_ta(<16 x i16> %a, <16 x i16> %b, <16 x i16 ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.select.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -1006,10 +888,8 @@ define <16 x i16> @vnmsac_vx_nxv16i16_ta(<16 x i16> %a, i16 %b, <16 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i16> @llvm.vp.mul.nxv16i16(<16 x i16> %a, <16 x i16> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i16> @llvm.vp.sub.nxv16i16(<16 x i16> %c, <16 x i16> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i16> @llvm.vp.select.nxv16i16(<16 x i1> %m, <16 x i16> %y, <16 x i16> %c, i32 %evl) ret <16 x i16> %u } @@ -1026,10 +906,8 @@ define <32 x i16> @vnmsac_vv_nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i16> % ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1041,11 +919,9 @@ define <32 x i16> @vnmsac_vv_nxv32i16_unmasked(<32 x i16> %a, <32 x i16> %b, <32 ; CHECK-NEXT: vnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> %allones, i32 %evl) - %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %allones, <32 x i16> %y, <32 x i16> %c, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> splat (i1 -1), <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1058,10 +934,8 @@ define <32 x i16> @vnmsac_vx_nxv32i16(<32 x i16> %a, i16 %b, <32 x i16> %c, <32 ; CHECK-NEXT: ret %elt.head = insertelement <32 x i16> poison, i16 %b, i32 0 %vb = shufflevector <32 x i16> %elt.head, <32 x i16> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1075,11 +949,9 @@ define <32 x i16> @vnmsac_vx_nxv32i16_unmasked(<32 x i16> %a, i16 %b, <32 x i16> ; CHECK-NEXT: ret %elt.head = insertelement <32 x i16> poison, i16 %b, i32 0 %vb = shufflevector <32 x i16> %elt.head, <32 x i16> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> %allones, i32 %evl) - %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> %allones, <32 x i16> %y, <32 x i16> %c, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> splat (i1 -1), i32 %evl) + %u = call <32 x i16> @llvm.vp.merge.nxv32i16(<32 x i1> splat (i1 -1), <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1090,10 +962,8 @@ define <32 x i16> @vnmsac_vv_nxv32i16_ta(<32 x i16> %a, <32 x i16> %b, <32 x i16 ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %b, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.select.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1107,10 +977,8 @@ define <32 x i16> @vnmsac_vx_nxv32i16_ta(<32 x i16> %a, i16 %b, <32 x i16> %c, ; CHECK-NEXT: ret %elt.head = insertelement <32 x i16> poison, i16 %b, i32 0 %vb = shufflevector <32 x i16> %elt.head, <32 x i16> poison, <32 x i32> zeroinitializer - %splat = insertelement <32 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <32 x i1> %splat, <32 x i1> poison, <32 x i32> zeroinitializer - %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> %allones, i32 %evl) - %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> %allones, i32 %evl) + %x = call <32 x i16> @llvm.vp.mul.nxv32i16(<32 x i16> %a, <32 x i16> %vb, <32 x i1> splat (i1 -1), i32 %evl) + %y = call <32 x i16> @llvm.vp.sub.nxv32i16(<32 x i16> %c, <32 x i16> %x, <32 x i1> splat (i1 -1), i32 %evl) %u = call <32 x i16> @llvm.vp.select.nxv32i16(<32 x i1> %m, <32 x i16> %y, <32 x i16> %c, i32 %evl) ret <32 x i16> %u } @@ -1127,10 +995,8 @@ define <2 x i32> @vnmsac_vv_nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1142,11 +1008,9 @@ define <2 x i32> @vnmsac_vv_nxv2i32_unmasked(<2 x i32> %a, <2 x i32> %b, <2 x i3 ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %allones, <2 x i32> %y, <2 x i32> %c, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> splat (i1 -1), <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1159,10 +1023,8 @@ define <2 x i32> @vnmsac_vx_nxv2i32(<2 x i32> %a, i32 %b, <2 x i32> %c, <2 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1176,11 +1038,9 @@ define <2 x i32> @vnmsac_vx_nxv2i32_unmasked(<2 x i32> %a, i32 %b, <2 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> %allones, <2 x i32> %y, <2 x i32> %c, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i32> @llvm.vp.merge.nxv2i32(<2 x i1> splat (i1 -1), <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1191,10 +1051,8 @@ define <2 x i32> @vnmsac_vv_nxv2i32_ta(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.select.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1208,10 +1066,8 @@ define <2 x i32> @vnmsac_vx_nxv2i32_ta(<2 x i32> %a, i32 %b, <2 x i32> %c, <2 x ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i32> @llvm.vp.mul.nxv2i32(<2 x i32> %a, <2 x i32> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i32> @llvm.vp.sub.nxv2i32(<2 x i32> %c, <2 x i32> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i32> @llvm.vp.select.nxv2i32(<2 x i1> %m, <2 x i32> %y, <2 x i32> %c, i32 %evl) ret <2 x i32> %u } @@ -1228,10 +1084,8 @@ define <4 x i32> @vnmsac_vv_nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1243,11 +1097,9 @@ define <4 x i32> @vnmsac_vv_nxv4i32_unmasked(<4 x i32> %a, <4 x i32> %b, <4 x i3 ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %allones, <4 x i32> %y, <4 x i32> %c, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> splat (i1 -1), <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1260,10 +1112,8 @@ define <4 x i32> @vnmsac_vx_nxv4i32(<4 x i32> %a, i32 %b, <4 x i32> %c, <4 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1277,11 +1127,9 @@ define <4 x i32> @vnmsac_vx_nxv4i32_unmasked(<4 x i32> %a, i32 %b, <4 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> %allones, <4 x i32> %y, <4 x i32> %c, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i32> @llvm.vp.merge.nxv4i32(<4 x i1> splat (i1 -1), <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1292,10 +1140,8 @@ define <4 x i32> @vnmsac_vv_nxv4i32_ta(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.select.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1309,10 +1155,8 @@ define <4 x i32> @vnmsac_vx_nxv4i32_ta(<4 x i32> %a, i32 %b, <4 x i32> %c, <4 x ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i32> @llvm.vp.mul.nxv4i32(<4 x i32> %a, <4 x i32> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i32> @llvm.vp.sub.nxv4i32(<4 x i32> %c, <4 x i32> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i32> @llvm.vp.select.nxv4i32(<4 x i1> %m, <4 x i32> %y, <4 x i32> %c, i32 %evl) ret <4 x i32> %u } @@ -1329,10 +1173,8 @@ define <8 x i32> @vnmsac_vv_nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, < ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1344,11 +1186,9 @@ define <8 x i32> @vnmsac_vv_nxv8i32_unmasked(<8 x i32> %a, <8 x i32> %b, <8 x i3 ; CHECK-NEXT: vnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %allones, <8 x i32> %y, <8 x i32> %c, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> splat (i1 -1), <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1361,10 +1201,8 @@ define <8 x i32> @vnmsac_vx_nxv8i32(<8 x i32> %a, i32 %b, <8 x i32> %c, <8 x i1 ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1378,11 +1216,9 @@ define <8 x i32> @vnmsac_vx_nxv8i32_unmasked(<8 x i32> %a, i32 %b, <8 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> %allones, <8 x i32> %y, <8 x i32> %c, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i32> @llvm.vp.merge.nxv8i32(<8 x i1> splat (i1 -1), <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1393,10 +1229,8 @@ define <8 x i32> @vnmsac_vv_nxv8i32_ta(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.select.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1410,10 +1244,8 @@ define <8 x i32> @vnmsac_vx_nxv8i32_ta(<8 x i32> %a, i32 %b, <8 x i32> %c, <8 x ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i32> @llvm.vp.mul.nxv8i32(<8 x i32> %a, <8 x i32> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i32> @llvm.vp.sub.nxv8i32(<8 x i32> %c, <8 x i32> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i32> @llvm.vp.select.nxv8i32(<8 x i1> %m, <8 x i32> %y, <8 x i32> %c, i32 %evl) ret <8 x i32> %u } @@ -1430,10 +1262,8 @@ define <16 x i32> @vnmsac_vv_nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i32> % ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1445,11 +1275,9 @@ define <16 x i32> @vnmsac_vv_nxv16i32_unmasked(<16 x i32> %a, <16 x i32> %b, <16 ; CHECK-NEXT: vnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> %allones, i32 %evl) - %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %allones, <16 x i32> %y, <16 x i32> %c, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> splat (i1 -1), <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1462,10 +1290,8 @@ define <16 x i32> @vnmsac_vx_nxv16i32(<16 x i32> %a, i32 %b, <16 x i32> %c, <16 ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1479,11 +1305,9 @@ define <16 x i32> @vnmsac_vx_nxv16i32_unmasked(<16 x i32> %a, i32 %b, <16 x i32> ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> %allones, i32 %evl) - %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> %allones, <16 x i32> %y, <16 x i32> %c, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> splat (i1 -1), i32 %evl) + %u = call <16 x i32> @llvm.vp.merge.nxv16i32(<16 x i1> splat (i1 -1), <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1494,10 +1318,8 @@ define <16 x i32> @vnmsac_vv_nxv16i32_ta(<16 x i32> %a, <16 x i32> %b, <16 x i32 ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %b, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.select.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1511,10 +1333,8 @@ define <16 x i32> @vnmsac_vx_nxv16i32_ta(<16 x i32> %a, i32 %b, <16 x i32> %c, ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %splat = insertelement <16 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <16 x i1> %splat, <16 x i1> poison, <16 x i32> zeroinitializer - %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> %allones, i32 %evl) - %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> %allones, i32 %evl) + %x = call <16 x i32> @llvm.vp.mul.nxv16i32(<16 x i32> %a, <16 x i32> %vb, <16 x i1> splat (i1 -1), i32 %evl) + %y = call <16 x i32> @llvm.vp.sub.nxv16i32(<16 x i32> %c, <16 x i32> %x, <16 x i1> splat (i1 -1), i32 %evl) %u = call <16 x i32> @llvm.vp.select.nxv16i32(<16 x i1> %m, <16 x i32> %y, <16 x i32> %c, i32 %evl) ret <16 x i32> %u } @@ -1531,10 +1351,8 @@ define <2 x i64> @vnmsac_vv_nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, < ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1546,11 +1364,9 @@ define <2 x i64> @vnmsac_vv_nxv2i64_unmasked(<2 x i64> %a, <2 x i64> %b, <2 x i6 ; CHECK-NEXT: vnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %allones, <2 x i64> %y, <2 x i64> %c, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> splat (i1 -1), <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1578,10 +1394,8 @@ define <2 x i64> @vnmsac_vx_nxv2i64(<2 x i64> %a, i64 %b, <2 x i64> %c, <2 x i1 ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1610,11 +1424,9 @@ define <2 x i64> @vnmsac_vx_nxv2i64_unmasked(<2 x i64> %a, i64 %b, <2 x i64> %c, ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> %allones, i32 %evl) - %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> %allones, <2 x i64> %y, <2 x i64> %c, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> splat (i1 -1), i32 %evl) + %u = call <2 x i64> @llvm.vp.merge.nxv2i64(<2 x i1> splat (i1 -1), <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1625,10 +1437,8 @@ define <2 x i64> @vnmsac_vv_nxv2i64_ta(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, ; CHECK-NEXT: vnmsac.vv v10, v8, v9, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %b, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.select.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1657,10 +1467,8 @@ define <2 x i64> @vnmsac_vx_nxv2i64_ta(<2 x i64> %a, i64 %b, <2 x i64> %c, <2 x ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %splat = insertelement <2 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <2 x i1> %splat, <2 x i1> poison, <2 x i32> zeroinitializer - %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> %allones, i32 %evl) - %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> %allones, i32 %evl) + %x = call <2 x i64> @llvm.vp.mul.nxv2i64(<2 x i64> %a, <2 x i64> %vb, <2 x i1> splat (i1 -1), i32 %evl) + %y = call <2 x i64> @llvm.vp.sub.nxv2i64(<2 x i64> %c, <2 x i64> %x, <2 x i1> splat (i1 -1), i32 %evl) %u = call <2 x i64> @llvm.vp.select.nxv2i64(<2 x i1> %m, <2 x i64> %y, <2 x i64> %c, i32 %evl) ret <2 x i64> %u } @@ -1677,10 +1485,8 @@ define <4 x i64> @vnmsac_vv_nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, < ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1692,11 +1498,9 @@ define <4 x i64> @vnmsac_vv_nxv4i64_unmasked(<4 x i64> %a, <4 x i64> %b, <4 x i6 ; CHECK-NEXT: vnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %allones, <4 x i64> %y, <4 x i64> %c, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> splat (i1 -1), <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1724,10 +1528,8 @@ define <4 x i64> @vnmsac_vx_nxv4i64(<4 x i64> %a, i64 %b, <4 x i64> %c, <4 x i1 ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1756,11 +1558,9 @@ define <4 x i64> @vnmsac_vx_nxv4i64_unmasked(<4 x i64> %a, i64 %b, <4 x i64> %c, ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> %allones, i32 %evl) - %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> %allones, <4 x i64> %y, <4 x i64> %c, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> splat (i1 -1), i32 %evl) + %u = call <4 x i64> @llvm.vp.merge.nxv4i64(<4 x i1> splat (i1 -1), <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1771,10 +1571,8 @@ define <4 x i64> @vnmsac_vv_nxv4i64_ta(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, ; CHECK-NEXT: vnmsac.vv v12, v8, v10, v0.t ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %b, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.select.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1803,10 +1601,8 @@ define <4 x i64> @vnmsac_vx_nxv4i64_ta(<4 x i64> %a, i64 %b, <4 x i64> %c, <4 x ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %splat = insertelement <4 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <4 x i1> %splat, <4 x i1> poison, <4 x i32> zeroinitializer - %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> %allones, i32 %evl) - %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> %allones, i32 %evl) + %x = call <4 x i64> @llvm.vp.mul.nxv4i64(<4 x i64> %a, <4 x i64> %vb, <4 x i1> splat (i1 -1), i32 %evl) + %y = call <4 x i64> @llvm.vp.sub.nxv4i64(<4 x i64> %c, <4 x i64> %x, <4 x i1> splat (i1 -1), i32 %evl) %u = call <4 x i64> @llvm.vp.select.nxv4i64(<4 x i1> %m, <4 x i64> %y, <4 x i64> %c, i32 %evl) ret <4 x i64> %u } @@ -1823,10 +1619,8 @@ define <8 x i64> @vnmsac_vv_nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, < ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1838,11 +1632,9 @@ define <8 x i64> @vnmsac_vv_nxv8i64_unmasked(<8 x i64> %a, <8 x i64> %b, <8 x i6 ; CHECK-NEXT: vnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %allones, <8 x i64> %y, <8 x i64> %c, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> splat (i1 -1), <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1870,10 +1662,8 @@ define <8 x i64> @vnmsac_vx_nxv8i64(<8 x i64> %a, i64 %b, <8 x i64> %c, <8 x i1 ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1902,11 +1692,9 @@ define <8 x i64> @vnmsac_vx_nxv8i64_unmasked(<8 x i64> %a, i64 %b, <8 x i64> %c, ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> %allones, i32 %evl) - %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> %allones, <8 x i64> %y, <8 x i64> %c, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> splat (i1 -1), i32 %evl) + %u = call <8 x i64> @llvm.vp.merge.nxv8i64(<8 x i1> splat (i1 -1), <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1917,10 +1705,8 @@ define <8 x i64> @vnmsac_vv_nxv8i64_ta(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, ; CHECK-NEXT: vnmsac.vv v16, v8, v12, v0.t ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %b, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.select.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } @@ -1949,10 +1735,8 @@ define <8 x i64> @vnmsac_vx_nxv8i64_ta(<8 x i64> %a, i64 %b, <8 x i64> %c, <8 x ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %splat = insertelement <8 x i1> poison, i1 -1, i32 0 - %allones = shufflevector <8 x i1> %splat, <8 x i1> poison, <8 x i32> zeroinitializer - %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> %allones, i32 %evl) - %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> %allones, i32 %evl) + %x = call <8 x i64> @llvm.vp.mul.nxv8i64(<8 x i64> %a, <8 x i64> %vb, <8 x i1> splat (i1 -1), i32 %evl) + %y = call <8 x i64> @llvm.vp.sub.nxv8i64(<8 x i64> %c, <8 x i64> %x, <8 x i1> splat (i1 -1), i32 %evl) %u = call <8 x i64> @llvm.vp.select.nxv8i64(<8 x i1> %m, <8 x i64> %y, <8 x i64> %c, i32 %evl) ret <8 x i64> %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll index d132608cdf7f..09c281b525a6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll @@ -34,9 +34,7 @@ define <2 x i8> @vor_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -60,9 +58,7 @@ define <2 x i8> @vor_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -72,9 +68,7 @@ define <2 x i8> @vor_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 5, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -84,11 +78,7 @@ define <2 x i8> @vor_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 5, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.or.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -110,9 +100,7 @@ define <4 x i8> @vor_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -148,9 +136,7 @@ define <4 x i8> @vor_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -160,9 +146,7 @@ define <4 x i8> @vor_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 5, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -172,11 +156,7 @@ define <4 x i8> @vor_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 5, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.or.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -198,9 +178,7 @@ define <7 x i8> @vor_vv_v5i8_unmasked(<7 x i8> %va, <7 x i8> %b, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <7 x i1> poison, i1 true, i32 0 - %m = shufflevector <7 x i1> %head, <7 x i1> poison, <7 x i32> zeroinitializer - %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> %m, i32 %evl) + %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %b, <7 x i1> splat (i1 true), i32 %evl) ret <7 x i8> %v } @@ -224,9 +202,7 @@ define <7 x i8> @vor_vx_v5i8_unmasked(<7 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <7 x i8> poison, i8 %b, i32 0 %vb = shufflevector <7 x i8> %elt.head, <7 x i8> poison, <7 x i32> zeroinitializer - %head = insertelement <7 x i1> poison, i1 true, i32 0 - %m = shufflevector <7 x i1> %head, <7 x i1> poison, <7 x i32> zeroinitializer - %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %vb, <7 x i1> %m, i32 %evl) + %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %vb, <7 x i1> splat (i1 true), i32 %evl) ret <7 x i8> %v } @@ -236,9 +212,7 @@ define <7 x i8> @vor_vi_v5i8(<7 x i8> %va, <7 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <7 x i8> poison, i8 5, i32 0 - %vb = shufflevector <7 x i8> %elt.head, <7 x i8> poison, <7 x i32> zeroinitializer - %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %vb, <7 x i1> %m, i32 %evl) + %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> splat (i8 5), <7 x i1> %m, i32 %evl) ret <7 x i8> %v } @@ -248,11 +222,7 @@ define <7 x i8> @vor_vi_v5i8_unmasked(<7 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <7 x i8> poison, i8 5, i32 0 - %vb = shufflevector <7 x i8> %elt.head, <7 x i8> poison, <7 x i32> zeroinitializer - %head = insertelement <7 x i1> poison, i1 true, i32 0 - %m = shufflevector <7 x i1> %head, <7 x i1> poison, <7 x i32> zeroinitializer - %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> %vb, <7 x i1> %m, i32 %evl) + %v = call <7 x i8> @llvm.vp.or.v5i8(<7 x i8> %va, <7 x i8> splat (i8 5), <7 x i1> splat (i1 true), i32 %evl) ret <7 x i8> %v } @@ -274,9 +244,7 @@ define <8 x i8> @vor_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -300,9 +268,7 @@ define <8 x i8> @vor_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -312,9 +278,7 @@ define <8 x i8> @vor_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 5, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -324,11 +288,7 @@ define <8 x i8> @vor_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 5, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.or.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -350,9 +310,7 @@ define <16 x i8> @vor_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -376,9 +334,7 @@ define <16 x i8> @vor_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -388,9 +344,7 @@ define <16 x i8> @vor_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 5, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -400,11 +354,7 @@ define <16 x i8> @vor_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 5, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.or.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -426,9 +376,7 @@ define <2 x i16> @vor_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -452,9 +400,7 @@ define <2 x i16> @vor_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -464,9 +410,7 @@ define <2 x i16> @vor_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 5, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -476,11 +420,7 @@ define <2 x i16> @vor_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 5, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.or.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -502,9 +442,7 @@ define <4 x i16> @vor_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -528,9 +466,7 @@ define <4 x i16> @vor_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -540,9 +476,7 @@ define <4 x i16> @vor_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 5, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -552,11 +486,7 @@ define <4 x i16> @vor_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 5, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.or.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -578,9 +508,7 @@ define <8 x i16> @vor_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -604,9 +532,7 @@ define <8 x i16> @vor_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -616,9 +542,7 @@ define <8 x i16> @vor_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 5, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -628,11 +552,7 @@ define <8 x i16> @vor_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 5, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.or.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -654,9 +574,7 @@ define <16 x i16> @vor_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -680,9 +598,7 @@ define <16 x i16> @vor_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -692,9 +608,7 @@ define <16 x i16> @vor_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 5, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -704,11 +618,7 @@ define <16 x i16> @vor_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 5, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.or.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -730,9 +640,7 @@ define <2 x i32> @vor_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -756,9 +664,7 @@ define <2 x i32> @vor_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -768,9 +674,7 @@ define <2 x i32> @vor_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 5, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -780,11 +684,7 @@ define <2 x i32> @vor_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 5, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.or.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -806,9 +706,7 @@ define <4 x i32> @vor_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -832,9 +730,7 @@ define <4 x i32> @vor_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -844,9 +740,7 @@ define <4 x i32> @vor_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 5, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -856,11 +750,7 @@ define <4 x i32> @vor_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 5, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.or.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -882,9 +772,7 @@ define <8 x i32> @vor_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -908,9 +796,7 @@ define <8 x i32> @vor_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -920,9 +806,7 @@ define <8 x i32> @vor_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 5, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -932,11 +816,7 @@ define <8 x i32> @vor_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 5, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -958,9 +838,7 @@ define <16 x i32> @vor_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -984,9 +862,7 @@ define <16 x i32> @vor_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -996,9 +872,7 @@ define <16 x i32> @vor_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 5, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1008,11 +882,7 @@ define <16 x i32> @vor_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 5, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.or.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1034,9 +904,7 @@ define <2 x i64> @vor_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1088,9 +956,7 @@ define <2 x i64> @vor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl) ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1100,9 +966,7 @@ define <2 x i64> @vor_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 5, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1112,11 +976,7 @@ define <2 x i64> @vor_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 5, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.or.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1138,9 +998,7 @@ define <4 x i64> @vor_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1192,9 +1050,7 @@ define <4 x i64> @vor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl) ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1204,9 +1060,7 @@ define <4 x i64> @vor_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 5, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1216,11 +1070,7 @@ define <4 x i64> @vor_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 5, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.or.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1242,9 +1092,7 @@ define <8 x i64> @vor_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1296,9 +1144,7 @@ define <8 x i64> @vor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl) ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1308,9 +1154,7 @@ define <8 x i64> @vor_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 5, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1320,11 +1164,7 @@ define <8 x i64> @vor_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 5, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.or.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1346,9 +1186,7 @@ define <16 x i64> @vor_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vor.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1400,9 +1238,7 @@ define <16 x i64> @vor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1412,9 +1248,7 @@ define <16 x i64> @vor_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 5, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1424,10 +1258,6 @@ define <16 x i64> @vor_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 5, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.or.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll index 4d2f55b172e4..a13f1eed8efb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll @@ -184,9 +184,7 @@ define <3 x i8> @vpgather_truemask_v3i8(<3 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vluxei64.v v10, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret - %mhead = insertelement <3 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <3 x i1> %mhead, <3 x i1> poison, <3 x i32> zeroinitializer - %v = call <3 x i8> @llvm.vp.gather.v3i8.v3p0(<3 x ptr> %ptrs, <3 x i1> %mtrue, i32 %evl) + %v = call <3 x i8> @llvm.vp.gather.v3i8.v3p0(<3 x ptr> %ptrs, <3 x i1> splat (i1 1), i32 %evl) ret <3 x i8> %v } @@ -224,9 +222,7 @@ define <4 x i8> @vpgather_truemask_v4i8(<4 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vluxei64.v v10, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x i8> @llvm.vp.gather.v4i8.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x i8> %v } @@ -455,9 +451,7 @@ define <4 x i16> @vpgather_truemask_v4i16(<4 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vluxei64.v v10, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x i16> @llvm.vp.gather.v4i16.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x i16> %v } @@ -665,9 +659,7 @@ define <4 x i32> @vpgather_truemask_v4i32(<4 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vluxei64.v v10, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x i32> @llvm.vp.gather.v4i32.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x i32> %v } @@ -905,9 +897,7 @@ define <4 x i64> @vpgather_truemask_v4i64(<4 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vluxei64.v v8, (zero), v8 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.gather.v4i64.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x i64> @llvm.vp.gather.v4i64.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x i64> %v } @@ -1216,9 +1206,7 @@ define <4 x half> @vpgather_truemask_v4f16(<4 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vluxei64.v v10, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.vp.gather.v4f16.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x half> @llvm.vp.gather.v4f16.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x half> %v } @@ -1384,9 +1372,7 @@ define <4 x float> @vpgather_truemask_v4f32(<4 x ptr> %ptrs, i32 zeroext %evl) { ; RV64-NEXT: vluxei64.v v10, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.vp.gather.v4f32.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x float> @llvm.vp.gather.v4f32.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x float> %v } @@ -1624,9 +1610,7 @@ define <4 x double> @vpgather_truemask_v4f64(<4 x ptr> %ptrs, i32 zeroext %evl) ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vluxei64.v v8, (zero), v8 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.vp.gather.v4f64.v4p0(<4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + %v = call <4 x double> @llvm.vp.gather.v4f64.v4p0(<4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret <4 x double> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll index 618b875be566..9ef89352e65e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll @@ -46,9 +46,7 @@ define <4 x i8> @vpload_v4i8_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i1> poison, i1 true, i32 0 - %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer - %load = call <4 x i8> @llvm.vp.load.v4i8.p0(ptr %ptr, <4 x i1> %b, i32 %evl) + %load = call <4 x i8> @llvm.vp.load.v4i8.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %load } @@ -106,9 +104,7 @@ define <8 x i16> @vpload_v8i16_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i1> poison, i1 true, i32 0 - %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer - %load = call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %ptr, <8 x i1> %b, i32 %evl) + %load = call <8 x i16> @llvm.vp.load.v8i16.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %load } @@ -154,9 +150,7 @@ define <6 x i32> @vpload_v6i32_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <6 x i1> poison, i1 true, i32 0 - %b = shufflevector <6 x i1> %a, <6 x i1> poison, <6 x i32> zeroinitializer - %load = call <6 x i32> @llvm.vp.load.v6i32.p0(ptr %ptr, <6 x i1> %b, i32 %evl) + %load = call <6 x i32> @llvm.vp.load.v6i32.p0(ptr %ptr, <6 x i1> splat (i1 true), i32 %evl) ret <6 x i32> %load } @@ -178,9 +172,7 @@ define <8 x i32> @vpload_v8i32_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i1> poison, i1 true, i32 0 - %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer - %load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> %b, i32 %evl) + %load = call <8 x i32> @llvm.vp.load.v8i32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %load } @@ -214,9 +206,7 @@ define <4 x i64> @vpload_v4i64_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i1> poison, i1 true, i32 0 - %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer - %load = call <4 x i64> @llvm.vp.load.v4i64.p0(ptr %ptr, <4 x i1> %b, i32 %evl) + %load = call <4 x i64> @llvm.vp.load.v4i64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %load } @@ -250,9 +240,7 @@ define <2 x half> @vpload_v2f16_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <2 x i1> poison, i1 true, i32 0 - %b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer - %load = call <2 x half> @llvm.vp.load.v2f16.p0(ptr %ptr, <2 x i1> %b, i32 %evl) + %load = call <2 x half> @llvm.vp.load.v2f16.p0(ptr %ptr, <2 x i1> splat (i1 true), i32 %evl) ret <2 x half> %load } @@ -322,9 +310,7 @@ define <8 x float> @vpload_v8f32_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <8 x i1> poison, i1 true, i32 0 - %b = shufflevector <8 x i1> %a, <8 x i1> poison, <8 x i32> zeroinitializer - %load = call <8 x float> @llvm.vp.load.v8f32.p0(ptr %ptr, <8 x i1> %b, i32 %evl) + %load = call <8 x float> @llvm.vp.load.v8f32.p0(ptr %ptr, <8 x i1> splat (i1 true), i32 %evl) ret <8 x float> %load } @@ -358,9 +344,7 @@ define <4 x double> @vpload_v4f64_allones_mask(ptr %ptr, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <4 x i1> poison, i1 true, i32 0 - %b = shufflevector <4 x i1> %a, <4 x i1> poison, <4 x i32> zeroinitializer - %load = call <4 x double> @llvm.vp.load.v4f64.p0(ptr %ptr, <4 x i1> %b, i32 %evl) + %load = call <4 x double> @llvm.vp.load.v4f64.p0(ptr %ptr, <4 x i1> splat (i1 true), i32 %evl) ret <4 x double> %load } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll index 6fe83fed6fd9..466448a7a05a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll @@ -89,9 +89,7 @@ define <2 x i8> @vpmerge_vi_v2i8(<2 x i8> %vb, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 2, i32 0 - %va = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.merge.v2i8(<2 x i1> %m, <2 x i8> %va, <2 x i8> %vb, i32 %evl) + %v = call <2 x i8> @llvm.vp.merge.v2i8(<2 x i1> %m, <2 x i8> splat (i8 2), <2 x i8> %vb, i32 %evl) ret <2 x i8> %v } @@ -126,9 +124,7 @@ define <4 x i8> @vpmerge_vi_v4i8(<4 x i8> %vb, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 2, i32 0 - %va = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.merge.v4i8(<4 x i1> %m, <4 x i8> %va, <4 x i8> %vb, i32 %evl) + %v = call <4 x i8> @llvm.vp.merge.v4i8(<4 x i1> %m, <4 x i8> splat (i8 2), <4 x i8> %vb, i32 %evl) ret <4 x i8> %v } @@ -163,9 +159,7 @@ define <6 x i8> @vpmerge_vi_v6i8(<6 x i8> %vb, <6 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <6 x i8> poison, i8 2, i32 0 - %va = shufflevector <6 x i8> %elt.head, <6 x i8> poison, <6 x i32> zeroinitializer - %v = call <6 x i8> @llvm.vp.merge.v6i8(<6 x i1> %m, <6 x i8> %va, <6 x i8> %vb, i32 %evl) + %v = call <6 x i8> @llvm.vp.merge.v6i8(<6 x i1> %m, <6 x i8> splat (i8 2), <6 x i8> %vb, i32 %evl) ret <6 x i8> %v } @@ -200,9 +194,7 @@ define <8 x i7> @vpmerge_vi_v8i7(<8 x i7> %vb, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i7> poison, i7 2, i32 0 - %va = shufflevector <8 x i7> %elt.head, <8 x i7> poison, <8 x i32> zeroinitializer - %v = call <8 x i7> @llvm.vp.merge.v8i7(<8 x i1> %m, <8 x i7> %va, <8 x i7> %vb, i32 %evl) + %v = call <8 x i7> @llvm.vp.merge.v8i7(<8 x i1> %m, <8 x i7> splat (i7 2), <8 x i7> %vb, i32 %evl) ret <8 x i7> %v } @@ -237,9 +229,7 @@ define <8 x i8> @vpmerge_vi_v8i8(<8 x i8> %vb, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 2, i32 0 - %va = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.merge.v8i8(<8 x i1> %m, <8 x i8> %va, <8 x i8> %vb, i32 %evl) + %v = call <8 x i8> @llvm.vp.merge.v8i8(<8 x i1> %m, <8 x i8> splat (i8 2), <8 x i8> %vb, i32 %evl) ret <8 x i8> %v } @@ -274,9 +264,7 @@ define <16 x i8> @vpmerge_vi_v16i8(<16 x i8> %vb, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 2, i32 0 - %va = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.merge.v16i8(<16 x i1> %m, <16 x i8> %va, <16 x i8> %vb, i32 %evl) + %v = call <16 x i8> @llvm.vp.merge.v16i8(<16 x i1> %m, <16 x i8> splat (i8 2), <16 x i8> %vb, i32 %evl) ret <16 x i8> %v } @@ -311,9 +299,7 @@ define <2 x i16> @vpmerge_vi_v2i16(<2 x i16> %vb, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 2, i32 0 - %va = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.merge.v2i16(<2 x i1> %m, <2 x i16> %va, <2 x i16> %vb, i32 %evl) + %v = call <2 x i16> @llvm.vp.merge.v2i16(<2 x i1> %m, <2 x i16> splat (i16 2), <2 x i16> %vb, i32 %evl) ret <2 x i16> %v } @@ -348,9 +334,7 @@ define <4 x i16> @vpmerge_vi_v4i16(<4 x i16> %vb, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 2, i32 0 - %va = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.merge.v4i16(<4 x i1> %m, <4 x i16> %va, <4 x i16> %vb, i32 %evl) + %v = call <4 x i16> @llvm.vp.merge.v4i16(<4 x i1> %m, <4 x i16> splat (i16 2), <4 x i16> %vb, i32 %evl) ret <4 x i16> %v } @@ -385,9 +369,7 @@ define <8 x i16> @vpmerge_vi_v8i16(<8 x i16> %vb, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 2, i32 0 - %va = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.merge.v8i16(<8 x i1> %m, <8 x i16> %va, <8 x i16> %vb, i32 %evl) + %v = call <8 x i16> @llvm.vp.merge.v8i16(<8 x i1> %m, <8 x i16> splat (i16 2), <8 x i16> %vb, i32 %evl) ret <8 x i16> %v } @@ -422,9 +404,7 @@ define <16 x i16> @vpmerge_vi_v16i16(<16 x i16> %vb, <16 x i1> %m, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 2, i32 0 - %va = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.merge.v16i16(<16 x i1> %m, <16 x i16> %va, <16 x i16> %vb, i32 %evl) + %v = call <16 x i16> @llvm.vp.merge.v16i16(<16 x i1> %m, <16 x i16> splat (i16 2), <16 x i16> %vb, i32 %evl) ret <16 x i16> %v } @@ -459,9 +439,7 @@ define <2 x i32> @vpmerge_vi_v2i32(<2 x i32> %vb, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 2, i32 0 - %va = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.merge.v2i32(<2 x i1> %m, <2 x i32> %va, <2 x i32> %vb, i32 %evl) + %v = call <2 x i32> @llvm.vp.merge.v2i32(<2 x i1> %m, <2 x i32> splat (i32 2), <2 x i32> %vb, i32 %evl) ret <2 x i32> %v } @@ -496,9 +474,7 @@ define <4 x i32> @vpmerge_vi_v4i32(<4 x i32> %vb, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 2, i32 0 - %va = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.merge.v4i32(<4 x i1> %m, <4 x i32> %va, <4 x i32> %vb, i32 %evl) + %v = call <4 x i32> @llvm.vp.merge.v4i32(<4 x i1> %m, <4 x i32> splat (i32 2), <4 x i32> %vb, i32 %evl) ret <4 x i32> %v } @@ -533,9 +509,7 @@ define <8 x i32> @vpmerge_vi_v8i32(<8 x i32> %vb, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 2, i32 0 - %va = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> %va, <8 x i32> %vb, i32 %evl) + %v = call <8 x i32> @llvm.vp.merge.v8i32(<8 x i1> %m, <8 x i32> splat (i32 2), <8 x i32> %vb, i32 %evl) ret <8 x i32> %v } @@ -570,9 +544,7 @@ define <16 x i32> @vpmerge_vi_v16i32(<16 x i32> %vb, <16 x i1> %m, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 2, i32 0 - %va = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.merge.v16i32(<16 x i1> %m, <16 x i32> %va, <16 x i32> %vb, i32 %evl) + %v = call <16 x i32> @llvm.vp.merge.v16i32(<16 x i1> %m, <16 x i32> splat (i32 2), <16 x i32> %vb, i32 %evl) ret <16 x i32> %v } @@ -641,9 +613,7 @@ define <2 x i64> @vpmerge_vi_v2i64(<2 x i64> %vb, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 2, i32 0 - %va = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.merge.v2i64(<2 x i1> %m, <2 x i64> %va, <2 x i64> %vb, i32 %evl) + %v = call <2 x i64> @llvm.vp.merge.v2i64(<2 x i1> %m, <2 x i64> splat (i64 2), <2 x i64> %vb, i32 %evl) ret <2 x i64> %v } @@ -712,9 +682,7 @@ define <4 x i64> @vpmerge_vi_v4i64(<4 x i64> %vb, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 2, i32 0 - %va = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.merge.v4i64(<4 x i1> %m, <4 x i64> %va, <4 x i64> %vb, i32 %evl) + %v = call <4 x i64> @llvm.vp.merge.v4i64(<4 x i1> %m, <4 x i64> splat (i64 2), <4 x i64> %vb, i32 %evl) ret <4 x i64> %v } @@ -783,9 +751,7 @@ define <8 x i64> @vpmerge_vi_v8i64(<8 x i64> %vb, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 2, i32 0 - %va = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.merge.v8i64(<8 x i1> %m, <8 x i64> %va, <8 x i64> %vb, i32 %evl) + %v = call <8 x i64> @llvm.vp.merge.v8i64(<8 x i1> %m, <8 x i64> splat (i64 2), <8 x i64> %vb, i32 %evl) ret <8 x i64> %v } @@ -854,9 +820,7 @@ define <16 x i64> @vpmerge_vi_v16i64(<16 x i64> %vb, <16 x i1> %m, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma ; CHECK-NEXT: vmerge.vim v8, v8, 2, v0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 2, i32 0 - %va = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.merge.v16i64(<16 x i1> %m, <16 x i64> %va, <16 x i64> %vb, i32 %evl) + %v = call <16 x i64> @llvm.vp.merge.v16i64(<16 x i1> %m, <16 x i64> splat (i64 2), <16 x i64> %vb, i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll index 83e3422c44b9..cd9a38d5167d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll @@ -127,9 +127,7 @@ define void @vpscatter_truemask_v4i8(<4 x i8> %val, <4 x ptr> %ptrs, i32 zeroext ; RV64-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } @@ -266,9 +264,7 @@ define void @vpscatter_truemask_v3i16(<3 x i16> %val, <3 x ptr> %ptrs, i32 zeroe ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <3 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <3 x i1> %mhead, <3 x i1> poison, <3 x i32> zeroinitializer - call void @llvm.vp.scatter.v3i16.v3p0(<3 x i16> %val, <3 x ptr> %ptrs, <3 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v3i16.v3p0(<3 x i16> %val, <3 x ptr> %ptrs, <3 x i1> splat (i1 1), i32 %evl) ret void } @@ -302,9 +298,7 @@ define void @vpscatter_truemask_v4i16(<4 x i16> %val, <4 x ptr> %ptrs, i32 zeroe ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } @@ -486,9 +480,7 @@ define void @vpscatter_truemask_v4i32(<4 x i32> %val, <4 x ptr> %ptrs, i32 zeroe ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } @@ -722,9 +714,7 @@ define void @vpscatter_truemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs, i32 zeroe ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } @@ -1026,9 +1016,7 @@ define void @vpscatter_truemask_v4f16(<4 x half> %val, <4 x ptr> %ptrs, i32 zero ; RV64-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } @@ -1189,9 +1177,7 @@ define void @vpscatter_truemask_v4f32(<4 x float> %val, <4 x ptr> %ptrs, i32 zer ; RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } @@ -1425,9 +1411,7 @@ define void @vpscatter_truemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs, i32 ze ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v10 ; RV64-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.vp.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, <4 x i1> %mtrue, i32 %evl) + call void @llvm.vp.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, <4 x i1> splat (i1 1), i32 %evl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll index d7643bc30418..c0aa735614b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll @@ -274,9 +274,7 @@ define void @vpstore_v2i8_allones_mask(<2 x i8> %val, ptr %ptr, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement <2 x i1> poison, i1 true, i32 0 - %b = shufflevector <2 x i1> %a, <2 x i1> poison, <2 x i32> zeroinitializer - call void @llvm.vp.store.v2i8.p0(<2 x i8> %val, ptr %ptr, <2 x i1> %b, i32 %evl) + call void @llvm.vp.store.v2i8.p0(<2 x i8> %val, ptr %ptr, <2 x i1> splat (i1 true), i32 %evl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll index 066355198983..4bbbad5ed0e0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll @@ -39,9 +39,7 @@ define <2 x i8> @vrem_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -65,9 +63,7 @@ define <2 x i8> @vrem_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.srem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -89,9 +85,7 @@ define <4 x i8> @vrem_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -115,9 +109,7 @@ define <4 x i8> @vrem_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.srem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -151,9 +143,7 @@ define <8 x i8> @vrem_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -177,9 +167,7 @@ define <8 x i8> @vrem_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.srem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -201,9 +189,7 @@ define <16 x i8> @vrem_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -227,9 +213,7 @@ define <16 x i8> @vrem_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.srem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -251,9 +235,7 @@ define <2 x i16> @vrem_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -277,9 +259,7 @@ define <2 x i16> @vrem_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.srem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -301,9 +281,7 @@ define <4 x i16> @vrem_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -327,9 +305,7 @@ define <4 x i16> @vrem_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.srem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -351,9 +327,7 @@ define <8 x i16> @vrem_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -377,9 +351,7 @@ define <8 x i16> @vrem_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.srem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -401,9 +373,7 @@ define <16 x i16> @vrem_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -427,9 +397,7 @@ define <16 x i16> @vrem_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.srem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -451,9 +419,7 @@ define <2 x i32> @vrem_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -477,9 +443,7 @@ define <2 x i32> @vrem_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.srem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -501,9 +465,7 @@ define <4 x i32> @vrem_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -527,9 +489,7 @@ define <4 x i32> @vrem_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.srem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -551,9 +511,7 @@ define <8 x i32> @vrem_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -577,9 +535,7 @@ define <8 x i32> @vrem_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -601,9 +557,7 @@ define <16 x i32> @vrem_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -627,9 +581,7 @@ define <16 x i32> @vrem_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.srem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -651,9 +603,7 @@ define <2 x i64> @vrem_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -705,9 +655,7 @@ define <2 x i64> @vrem_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.srem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -729,9 +677,7 @@ define <4 x i64> @vrem_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -783,9 +729,7 @@ define <4 x i64> @vrem_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.srem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -807,9 +751,7 @@ define <8 x i64> @vrem_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -861,9 +803,7 @@ define <8 x i64> @vrem_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.srem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -885,9 +825,7 @@ define <16 x i64> @vrem_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -939,8 +877,6 @@ define <16 x i64> @vrem_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.srem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll index a329e73e5e86..ee11307bddc8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll @@ -38,9 +38,7 @@ define <2 x i8> @vremu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -64,9 +62,7 @@ define <2 x i8> @vremu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.urem.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -88,9 +84,7 @@ define <4 x i8> @vremu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -114,9 +108,7 @@ define <4 x i8> @vremu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.urem.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -150,9 +142,7 @@ define <8 x i8> @vremu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -176,9 +166,7 @@ define <8 x i8> @vremu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.urem.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -200,9 +188,7 @@ define <16 x i8> @vremu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -226,9 +212,7 @@ define <16 x i8> @vremu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.urem.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -250,9 +234,7 @@ define <2 x i16> @vremu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -276,9 +258,7 @@ define <2 x i16> @vremu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.urem.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -300,9 +280,7 @@ define <4 x i16> @vremu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -326,9 +304,7 @@ define <4 x i16> @vremu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.urem.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -350,9 +326,7 @@ define <8 x i16> @vremu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -376,9 +350,7 @@ define <8 x i16> @vremu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.urem.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -400,9 +372,7 @@ define <16 x i16> @vremu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -426,9 +396,7 @@ define <16 x i16> @vremu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.urem.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -450,9 +418,7 @@ define <2 x i32> @vremu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -476,9 +442,7 @@ define <2 x i32> @vremu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.urem.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -500,9 +464,7 @@ define <4 x i32> @vremu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -526,9 +488,7 @@ define <4 x i32> @vremu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.urem.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -550,9 +510,7 @@ define <8 x i32> @vremu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -576,9 +534,7 @@ define <8 x i32> @vremu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -600,9 +556,7 @@ define <16 x i32> @vremu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -626,9 +580,7 @@ define <16 x i32> @vremu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.urem.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -650,9 +602,7 @@ define <2 x i64> @vremu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -704,9 +654,7 @@ define <2 x i64> @vremu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.urem.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -728,9 +676,7 @@ define <4 x i64> @vremu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -782,9 +728,7 @@ define <4 x i64> @vremu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.urem.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -806,9 +750,7 @@ define <8 x i64> @vremu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -860,9 +802,7 @@ define <8 x i64> @vremu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.urem.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -884,9 +824,7 @@ define <16 x i64> @vremu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -938,8 +876,6 @@ define <16 x i64> @vremu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.urem.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll index c7c757efc1ba..367c56caf813 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll @@ -66,7 +66,7 @@ define <1 x i8> @vror_vi_v1i8(<1 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> shufflevector(<1 x i8> insertelement(<1 x i8> poison, i8 1, i32 0), <1 x i8> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i8> @llvm.fshr.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> splat (i8 1)) ret <1 x i8> %x } @@ -84,7 +84,7 @@ define <1 x i8> @vror_vi_rotl_v1i8(<1 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> shufflevector(<1 x i8> insertelement(<1 x i8> poison, i8 1, i32 0), <1 x i8> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i8> @llvm.fshl.v1i8(<1 x i8> %a, <1 x i8> %a, <1 x i8> splat (i8 1)) ret <1 x i8> %x } @@ -150,7 +150,7 @@ define <2 x i8> @vror_vi_v2i8(<2 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> shufflevector(<2 x i8> insertelement(<2 x i8> poison, i8 1, i32 0), <2 x i8> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i8> @llvm.fshr.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> splat (i8 1)) ret <2 x i8> %x } @@ -168,7 +168,7 @@ define <2 x i8> @vror_vi_rotl_v2i8(<2 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> shufflevector(<2 x i8> insertelement(<2 x i8> poison, i8 1, i32 0), <2 x i8> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i8> @llvm.fshl.v2i8(<2 x i8> %a, <2 x i8> %a, <2 x i8> splat (i8 1)) ret <2 x i8> %x } @@ -234,7 +234,7 @@ define <4 x i8> @vror_vi_v4i8(<4 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> shufflevector(<4 x i8> insertelement(<4 x i8> poison, i8 1, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i8> @llvm.fshr.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> splat (i8 1)) ret <4 x i8> %x } @@ -252,7 +252,7 @@ define <4 x i8> @vror_vi_rotl_v4i8(<4 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> shufflevector(<4 x i8> insertelement(<4 x i8> poison, i8 1, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i8> @llvm.fshl.v4i8(<4 x i8> %a, <4 x i8> %a, <4 x i8> splat (i8 1)) ret <4 x i8> %x } @@ -318,7 +318,7 @@ define <8 x i8> @vror_vi_v8i8(<8 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> shufflevector(<8 x i8> insertelement(<8 x i8> poison, i8 1, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i8> @llvm.fshr.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> splat (i8 1)) ret <8 x i8> %x } @@ -336,7 +336,7 @@ define <8 x i8> @vror_vi_rotl_v8i8(<8 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> shufflevector(<8 x i8> insertelement(<8 x i8> poison, i8 1, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i8> @llvm.fshl.v8i8(<8 x i8> %a, <8 x i8> %a, <8 x i8> splat (i8 1)) ret <8 x i8> %x } @@ -402,7 +402,7 @@ define <16 x i8> @vror_vi_v16i8(<16 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> shufflevector(<16 x i8> insertelement(<16 x i8> poison, i8 1, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)) + %x = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 1)) ret <16 x i8> %x } @@ -420,7 +420,7 @@ define <16 x i8> @vror_vi_rotl_v16i8(<16 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> shufflevector(<16 x i8> insertelement(<16 x i8> poison, i8 1, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)) + %x = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %a, <16 x i8> %a, <16 x i8> splat (i8 1)) ret <16 x i8> %x } @@ -492,7 +492,7 @@ define <32 x i8> @vror_vi_v32i8(<32 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> shufflevector(<32 x i8> insertelement(<32 x i8> poison, i8 1, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)) + %x = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> splat (i8 1)) ret <32 x i8> %x } @@ -512,7 +512,7 @@ define <32 x i8> @vror_vi_rotl_v32i8(<32 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> shufflevector(<32 x i8> insertelement(<32 x i8> poison, i8 1, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)) + %x = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %a, <32 x i8> %a, <32 x i8> splat (i8 1)) ret <32 x i8> %x } @@ -584,7 +584,7 @@ define <64 x i8> @vror_vi_v64i8(<64 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> shufflevector(<64 x i8> insertelement(<64 x i8> poison, i8 1, i32 0), <64 x i8> poison, <64 x i32> zeroinitializer)) + %x = call <64 x i8> @llvm.fshr.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> splat (i8 1)) ret <64 x i8> %x } @@ -604,7 +604,7 @@ define <64 x i8> @vror_vi_rotl_v64i8(<64 x i8> %a) { ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7 ; CHECK-ZVKB-NEXT: ret - %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> shufflevector(<64 x i8> insertelement(<64 x i8> poison, i8 1, i32 0), <64 x i8> poison, <64 x i32> zeroinitializer)) + %x = call <64 x i8> @llvm.fshl.v64i8(<64 x i8> %a, <64 x i8> %a, <64 x i8> splat (i8 1)) ret <64 x i8> %x } @@ -670,7 +670,7 @@ define <1 x i16> @vror_vi_v1i16(<1 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> shufflevector(<1 x i16> insertelement(<1 x i16> poison, i16 1, i32 0), <1 x i16> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i16> @llvm.fshr.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> splat (i16 1)) ret <1 x i16> %x } @@ -688,7 +688,7 @@ define <1 x i16> @vror_vi_rotl_v1i16(<1 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> shufflevector(<1 x i16> insertelement(<1 x i16> poison, i16 1, i32 0), <1 x i16> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i16> @llvm.fshl.v1i16(<1 x i16> %a, <1 x i16> %a, <1 x i16> splat (i16 1)) ret <1 x i16> %x } @@ -754,7 +754,7 @@ define <2 x i16> @vror_vi_v2i16(<2 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> shufflevector(<2 x i16> insertelement(<2 x i16> poison, i16 1, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i16> @llvm.fshr.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> splat (i16 1)) ret <2 x i16> %x } @@ -772,7 +772,7 @@ define <2 x i16> @vror_vi_rotl_v2i16(<2 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> shufflevector(<2 x i16> insertelement(<2 x i16> poison, i16 1, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i16> @llvm.fshl.v2i16(<2 x i16> %a, <2 x i16> %a, <2 x i16> splat (i16 1)) ret <2 x i16> %x } @@ -838,7 +838,7 @@ define <4 x i16> @vror_vi_v4i16(<4 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> shufflevector(<4 x i16> insertelement(<4 x i16> poison, i16 1, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i16> @llvm.fshr.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> splat (i16 1)) ret <4 x i16> %x } @@ -856,7 +856,7 @@ define <4 x i16> @vror_vi_rotl_v4i16(<4 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> shufflevector(<4 x i16> insertelement(<4 x i16> poison, i16 1, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i16> @llvm.fshl.v4i16(<4 x i16> %a, <4 x i16> %a, <4 x i16> splat (i16 1)) ret <4 x i16> %x } @@ -922,7 +922,7 @@ define <8 x i16> @vror_vi_v8i16(<8 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> shufflevector(<8 x i16> insertelement(<8 x i16> poison, i16 1, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 1)) ret <8 x i16> %x } @@ -940,7 +940,7 @@ define <8 x i16> @vror_vi_rotl_v8i16(<8 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> shufflevector(<8 x i16> insertelement(<8 x i16> poison, i16 1, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %a, <8 x i16> %a, <8 x i16> splat (i16 1)) ret <8 x i16> %x } @@ -1006,7 +1006,7 @@ define <16 x i16> @vror_vi_v16i16(<16 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> shufflevector(<16 x i16> insertelement(<16 x i16> poison, i16 1, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)) + %x = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> splat (i16 1)) ret <16 x i16> %x } @@ -1024,7 +1024,7 @@ define <16 x i16> @vror_vi_rotl_v16i16(<16 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 ; CHECK-ZVKB-NEXT: ret - %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> shufflevector(<16 x i16> insertelement(<16 x i16> poison, i16 1, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)) + %x = call <16 x i16> @llvm.fshl.v16i16(<16 x i16> %a, <16 x i16> %a, <16 x i16> splat (i16 1)) ret <16 x i16> %x } @@ -1096,7 +1096,7 @@ define <32 x i16> @vror_vi_v32i16(<32 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> shufflevector(<32 x i16> insertelement(<32 x i16> poison, i16 1, i32 0), <32 x i16> poison, <32 x i32> zeroinitializer)) + %x = call <32 x i16> @llvm.fshr.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> splat (i16 1)) ret <32 x i16> %x } @@ -1116,7 +1116,7 @@ define <32 x i16> @vror_vi_rotl_v32i16(<32 x i16> %a) { ; CHECK-ZVKB-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15 ; CHECK-ZVKB-NEXT: ret - %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> shufflevector(<32 x i16> insertelement(<32 x i16> poison, i16 1, i32 0), <32 x i16> poison, <32 x i32> zeroinitializer)) + %x = call <32 x i16> @llvm.fshl.v32i16(<32 x i16> %a, <32 x i16> %a, <32 x i16> splat (i16 1)) ret <32 x i16> %x } @@ -1184,7 +1184,7 @@ define <1 x i32> @vror_vi_v1i32(<1 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> shufflevector(<1 x i32> insertelement(<1 x i32> poison, i32 1, i32 0), <1 x i32> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i32> @llvm.fshr.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> splat (i32 1)) ret <1 x i32> %x } @@ -1202,7 +1202,7 @@ define <1 x i32> @vror_vi_rotl_v1i32(<1 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> shufflevector(<1 x i32> insertelement(<1 x i32> poison, i32 1, i32 0), <1 x i32> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i32> @llvm.fshl.v1i32(<1 x i32> %a, <1 x i32> %a, <1 x i32> splat (i32 1)) ret <1 x i32> %x } @@ -1270,7 +1270,7 @@ define <2 x i32> @vror_vi_v2i32(<2 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> shufflevector(<2 x i32> insertelement(<2 x i32> poison, i32 1, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> splat (i32 1)) ret <2 x i32> %x } @@ -1288,7 +1288,7 @@ define <2 x i32> @vror_vi_rotl_v2i32(<2 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> shufflevector(<2 x i32> insertelement(<2 x i32> poison, i32 1, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %a, <2 x i32> %a, <2 x i32> splat (i32 1)) ret <2 x i32> %x } @@ -1356,7 +1356,7 @@ define <4 x i32> @vror_vi_v4i32(<4 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> shufflevector(<4 x i32> insertelement(<4 x i32> poison, i32 1, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 1)) ret <4 x i32> %x } @@ -1374,7 +1374,7 @@ define <4 x i32> @vror_vi_rotl_v4i32(<4 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> shufflevector(<4 x i32> insertelement(<4 x i32> poison, i32 1, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %a, <4 x i32> %a, <4 x i32> splat (i32 1)) ret <4 x i32> %x } @@ -1442,7 +1442,7 @@ define <8 x i32> @vror_vi_v8i32(<8 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> shufflevector(<8 x i32> insertelement(<8 x i32> poison, i32 1, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i32> @llvm.fshr.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> splat (i32 1)) ret <8 x i32> %x } @@ -1460,7 +1460,7 @@ define <8 x i32> @vror_vi_rotl_v8i32(<8 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> shufflevector(<8 x i32> insertelement(<8 x i32> poison, i32 1, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %a, <8 x i32> %a, <8 x i32> splat (i32 1)) ret <8 x i32> %x } @@ -1528,7 +1528,7 @@ define <16 x i32> @vror_vi_v16i32(<16 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> shufflevector(<16 x i32> insertelement(<16 x i32> poison, i32 1, i32 0), <16 x i32> poison, <16 x i32> zeroinitializer)) + %x = call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> splat (i32 1)) ret <16 x i32> %x } @@ -1546,7 +1546,7 @@ define <16 x i32> @vror_vi_rotl_v16i32(<16 x i32> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 31 ; CHECK-ZVKB-NEXT: ret - %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> shufflevector(<16 x i32> insertelement(<16 x i32> poison, i32 1, i32 0), <16 x i32> poison, <16 x i32> zeroinitializer)) + %x = call <16 x i32> @llvm.fshl.v16i32(<16 x i32> %a, <16 x i32> %a, <16 x i32> splat (i32 1)) ret <16 x i32> %x } @@ -1629,7 +1629,7 @@ define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> shufflevector(<1 x i64> insertelement(<1 x i64> poison, i64 1, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> splat (i64 1)) ret <1 x i64> %x } @@ -1662,7 +1662,7 @@ define <1 x i64> @vror_vi_rotl_v1i64(<1 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 ; CHECK-ZVKB-NEXT: ret - %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> shufflevector(<1 x i64> insertelement(<1 x i64> poison, i64 1, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)) + %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> splat (i64 1)) ret <1 x i64> %x } @@ -1745,7 +1745,7 @@ define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> shufflevector(<2 x i64> insertelement(<2 x i64> poison, i64 1, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1)) ret <2 x i64> %x } @@ -1778,7 +1778,7 @@ define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 ; CHECK-ZVKB-NEXT: ret - %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> shufflevector(<2 x i64> insertelement(<2 x i64> poison, i64 1, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)) + %x = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> splat (i64 1)) ret <2 x i64> %x } @@ -1861,7 +1861,7 @@ define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> shufflevector(<4 x i64> insertelement(<4 x i64> poison, i64 1, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> splat (i64 1)) ret <4 x i64> %x } @@ -1894,7 +1894,7 @@ define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 ; CHECK-ZVKB-NEXT: ret - %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> shufflevector(<4 x i64> insertelement(<4 x i64> poison, i64 1, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)) + %x = call <4 x i64> @llvm.fshl.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> splat (i64 1)) ret <4 x i64> %x } @@ -1977,7 +1977,7 @@ define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> splat (i64 1)) ret <8 x i64> %x } @@ -2010,6 +2010,6 @@ define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) { ; CHECK-ZVKB-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-ZVKB-NEXT: vror.vi v8, v8, 63 ; CHECK-ZVKB-NEXT: ret - %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)) + %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> splat (i64 1)) ret <8 x i64> %x } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll index fe433b80a87f..563482b88e8b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll @@ -26,9 +26,7 @@ define <2 x i8> @vrsub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -38,9 +36,7 @@ define <2 x i8> @vrsub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 2, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> splat (i8 2), <2 x i8> %va, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -50,11 +46,7 @@ define <2 x i8> @vrsub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 2, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %vb, <2 x i8> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> splat (i8 2), <2 x i8> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -80,9 +72,7 @@ define <4 x i8> @vrsub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -92,9 +82,7 @@ define <4 x i8> @vrsub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 2, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> splat (i8 2), <4 x i8> %va, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -104,11 +92,7 @@ define <4 x i8> @vrsub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 2, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %vb, <4 x i8> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> splat (i8 2), <4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -134,9 +118,7 @@ define <8 x i8> @vrsub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -146,9 +128,7 @@ define <8 x i8> @vrsub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 2, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> splat (i8 2), <8 x i8> %va, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -158,11 +138,7 @@ define <8 x i8> @vrsub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 2, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %vb, <8 x i8> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> splat (i8 2), <8 x i8> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -188,9 +164,7 @@ define <16 x i8> @vrsub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -200,9 +174,7 @@ define <16 x i8> @vrsub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 2, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> splat (i8 2), <16 x i8> %va, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -212,11 +184,7 @@ define <16 x i8> @vrsub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 2, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %vb, <16 x i8> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> splat (i8 2), <16 x i8> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -242,9 +210,7 @@ define <2 x i16> @vrsub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -254,9 +220,7 @@ define <2 x i16> @vrsub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 2, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> splat (i16 2), <2 x i16> %va, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -266,11 +230,7 @@ define <2 x i16> @vrsub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 2, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %vb, <2 x i16> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> splat (i16 2), <2 x i16> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -296,9 +256,7 @@ define <4 x i16> @vrsub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -308,9 +266,7 @@ define <4 x i16> @vrsub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 2, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> splat (i16 2), <4 x i16> %va, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -320,11 +276,7 @@ define <4 x i16> @vrsub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 2, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %vb, <4 x i16> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> splat (i16 2), <4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -350,9 +302,7 @@ define <8 x i16> @vrsub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -362,9 +312,7 @@ define <8 x i16> @vrsub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 2, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> splat (i16 2), <8 x i16> %va, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -374,11 +322,7 @@ define <8 x i16> @vrsub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 2, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %vb, <8 x i16> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> splat (i16 2), <8 x i16> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -404,9 +348,7 @@ define <16 x i16> @vrsub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -416,9 +358,7 @@ define <16 x i16> @vrsub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 2, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> splat (i16 2), <16 x i16> %va, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -428,11 +368,7 @@ define <16 x i16> @vrsub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 2, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %vb, <16 x i16> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> splat (i16 2), <16 x i16> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -458,9 +394,7 @@ define <2 x i32> @vrsub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -470,9 +404,7 @@ define <2 x i32> @vrsub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 2, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> splat (i32 2), <2 x i32> %va, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -482,11 +414,7 @@ define <2 x i32> @vrsub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 2, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %vb, <2 x i32> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> splat (i32 2), <2 x i32> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -512,9 +440,7 @@ define <4 x i32> @vrsub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -524,9 +450,7 @@ define <4 x i32> @vrsub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 2, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> splat (i32 2), <4 x i32> %va, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -536,11 +460,7 @@ define <4 x i32> @vrsub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 2, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %vb, <4 x i32> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> splat (i32 2), <4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -566,9 +486,7 @@ define <8 x i32> @vrsub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -578,9 +496,7 @@ define <8 x i32> @vrsub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 2, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> splat (i32 2), <8 x i32> %va, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -590,11 +506,7 @@ define <8 x i32> @vrsub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 2, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %vb, <8 x i32> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> splat (i32 2), <8 x i32> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -620,9 +532,7 @@ define <16 x i32> @vrsub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -632,9 +542,7 @@ define <16 x i32> @vrsub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 2, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> splat (i32 2), <16 x i32> %va, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -644,11 +552,7 @@ define <16 x i32> @vrsub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 2, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %vb, <16 x i32> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> splat (i32 2), <16 x i32> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -702,9 +606,7 @@ define <2 x i64> @vrsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -714,9 +616,7 @@ define <2 x i64> @vrsub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 2, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> splat (i64 2), <2 x i64> %va, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -726,11 +626,7 @@ define <2 x i64> @vrsub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 2, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %vb, <2 x i64> %va, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> splat (i64 2), <2 x i64> %va, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -784,9 +680,7 @@ define <4 x i64> @vrsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -796,9 +690,7 @@ define <4 x i64> @vrsub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 2, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> splat (i64 2), <4 x i64> %va, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -808,11 +700,7 @@ define <4 x i64> @vrsub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 2, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %vb, <4 x i64> %va, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> splat (i64 2), <4 x i64> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -866,9 +754,7 @@ define <8 x i64> @vrsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -878,9 +764,7 @@ define <8 x i64> @vrsub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 2, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> splat (i64 2), <8 x i64> %va, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -890,11 +774,7 @@ define <8 x i64> @vrsub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 2, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %vb, <8 x i64> %va, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> splat (i64 2), <8 x i64> %va, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -948,9 +828,7 @@ define <16 x i64> @vrsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -960,9 +838,7 @@ define <16 x i64> @vrsub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 2, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> splat (i64 2), <16 x i64> %va, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -972,10 +848,6 @@ define <16 x i64> @vrsub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 2, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %vb, <16 x i64> %va, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> splat (i64 2), <16 x i64> %va, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll index d7ed20f4e098..348b301ef255 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll @@ -43,9 +43,7 @@ define <2 x i8> @vsadd_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -69,9 +67,7 @@ define <2 x i8> @vsadd_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -81,9 +77,7 @@ define <2 x i8> @vsadd_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -93,11 +87,7 @@ define <2 x i8> @vsadd_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -119,9 +109,7 @@ define <4 x i8> @vsadd_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -157,9 +145,7 @@ define <4 x i8> @vsadd_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -169,9 +155,7 @@ define <4 x i8> @vsadd_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -181,11 +165,7 @@ define <4 x i8> @vsadd_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -207,9 +187,7 @@ define <5 x i8> @vsadd_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -233,9 +211,7 @@ define <5 x i8> @vsadd_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -245,9 +221,7 @@ define <5 x i8> @vsadd_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl) ret <5 x i8> %v } @@ -257,11 +231,7 @@ define <5 x i8> @vsadd_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.sadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -283,9 +253,7 @@ define <8 x i8> @vsadd_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -309,9 +277,7 @@ define <8 x i8> @vsadd_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -321,9 +287,7 @@ define <8 x i8> @vsadd_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -333,11 +297,7 @@ define <8 x i8> @vsadd_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -359,9 +319,7 @@ define <16 x i8> @vsadd_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -385,9 +343,7 @@ define <16 x i8> @vsadd_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -397,9 +353,7 @@ define <16 x i8> @vsadd_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -409,11 +363,7 @@ define <16 x i8> @vsadd_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -440,9 +390,7 @@ define <256 x i8> @vsadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl) ret <256 x i8> %v } @@ -464,11 +412,7 @@ define <256 x i8> @vsadd_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vi v16, v16, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -485,9 +429,7 @@ define <256 x i8> @vsadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 129) + %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129) ret <256 x i8> %v } @@ -504,9 +446,7 @@ define <256 x i8> @vsadd_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vsadd.vi v16, v16, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 128) + %v = call <256 x i8> @llvm.vp.sadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128) ret <256 x i8> %v } @@ -528,9 +468,7 @@ define <2 x i16> @vsadd_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -554,9 +492,7 @@ define <2 x i16> @vsadd_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -566,9 +502,7 @@ define <2 x i16> @vsadd_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -578,11 +512,7 @@ define <2 x i16> @vsadd_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -604,9 +534,7 @@ define <4 x i16> @vsadd_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -630,9 +558,7 @@ define <4 x i16> @vsadd_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -642,9 +568,7 @@ define <4 x i16> @vsadd_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -654,11 +578,7 @@ define <4 x i16> @vsadd_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -680,9 +600,7 @@ define <8 x i16> @vsadd_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -706,9 +624,7 @@ define <8 x i16> @vsadd_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -718,9 +634,7 @@ define <8 x i16> @vsadd_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -730,11 +644,7 @@ define <8 x i16> @vsadd_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -756,9 +666,7 @@ define <16 x i16> @vsadd_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -782,9 +690,7 @@ define <16 x i16> @vsadd_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -794,9 +700,7 @@ define <16 x i16> @vsadd_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -806,11 +710,7 @@ define <16 x i16> @vsadd_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -832,9 +732,7 @@ define <2 x i32> @vsadd_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -858,9 +756,7 @@ define <2 x i32> @vsadd_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -870,9 +766,7 @@ define <2 x i32> @vsadd_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -882,11 +776,7 @@ define <2 x i32> @vsadd_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -908,9 +798,7 @@ define <4 x i32> @vsadd_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -934,9 +822,7 @@ define <4 x i32> @vsadd_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -946,9 +832,7 @@ define <4 x i32> @vsadd_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -958,11 +842,7 @@ define <4 x i32> @vsadd_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -984,9 +864,7 @@ define <8 x i32> @vsadd_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1010,9 +888,7 @@ define <8 x i32> @vsadd_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1022,9 +898,7 @@ define <8 x i32> @vsadd_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1034,11 +908,7 @@ define <8 x i32> @vsadd_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1060,9 +930,7 @@ define <16 x i32> @vsadd_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1086,9 +954,7 @@ define <16 x i32> @vsadd_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1098,9 +964,7 @@ define <16 x i32> @vsadd_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1110,11 +974,7 @@ define <16 x i32> @vsadd_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1136,9 +996,7 @@ define <2 x i64> @vsadd_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1190,9 +1048,7 @@ define <2 x i64> @vsadd_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1202,9 +1058,7 @@ define <2 x i64> @vsadd_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1214,11 +1068,7 @@ define <2 x i64> @vsadd_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1240,9 +1090,7 @@ define <4 x i64> @vsadd_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1294,9 +1142,7 @@ define <4 x i64> @vsadd_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1306,9 +1152,7 @@ define <4 x i64> @vsadd_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1318,11 +1162,7 @@ define <4 x i64> @vsadd_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1344,9 +1184,7 @@ define <8 x i64> @vsadd_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1398,9 +1236,7 @@ define <8 x i64> @vsadd_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1410,9 +1246,7 @@ define <8 x i64> @vsadd_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1422,11 +1256,7 @@ define <8 x i64> @vsadd_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1448,9 +1278,7 @@ define <16 x i64> @vsadd_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1502,9 +1330,7 @@ define <16 x i64> @vsadd_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1514,9 +1340,7 @@ define <16 x i64> @vsadd_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1526,11 +1350,7 @@ define <16 x i64> @vsadd_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1663,9 +1483,7 @@ define <32 x i64> @vsadd_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vsadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) + %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12) ret <32 x i64> %v } @@ -1694,8 +1512,6 @@ define <32 x i64> @vsadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vsadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 27) + %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll index 8e655a7faf3e..741699289e02 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll @@ -34,9 +34,7 @@ define <2 x i8> @sadd_v2i8_vi(<2 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 5, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb) + %v = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5)) ret <2 x i8> %v } @@ -70,9 +68,7 @@ define <4 x i8> @sadd_v4i8_vi(<4 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 5, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb) + %v = call <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5)) ret <4 x i8> %v } @@ -106,9 +102,7 @@ define <8 x i8> @sadd_v8i8_vi(<8 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 5, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb) + %v = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5)) ret <8 x i8> %v } @@ -142,9 +136,7 @@ define <16 x i8> @sadd_v16i8_vi(<16 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 5, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb) + %v = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5)) ret <16 x i8> %v } @@ -178,9 +170,7 @@ define <2 x i16> @sadd_v2i16_vi(<2 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 5, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb) + %v = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5)) ret <2 x i16> %v } @@ -214,9 +204,7 @@ define <4 x i16> @sadd_v4i16_vi(<4 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 5, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb) + %v = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5)) ret <4 x i16> %v } @@ -250,9 +238,7 @@ define <8 x i16> @sadd_v8i16_vi(<8 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 5, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb) + %v = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5)) ret <8 x i16> %v } @@ -286,9 +272,7 @@ define <16 x i16> @sadd_v16i16_vi(<16 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 5, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb) + %v = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5)) ret <16 x i16> %v } @@ -334,9 +318,7 @@ define <2 x i32> @sadd_v2i32_vi(<2 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 5, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb) + %v = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5)) ret <2 x i32> %v } @@ -370,9 +352,7 @@ define <4 x i32> @sadd_v4i32_vi(<4 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 5, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb) + %v = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5)) ret <4 x i32> %v } @@ -406,9 +386,7 @@ define <8 x i32> @sadd_v8i32_vi(<8 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 5, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb) + %v = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5)) ret <8 x i32> %v } @@ -442,9 +420,7 @@ define <16 x i32> @sadd_v16i32_vi(<16 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 5, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb) + %v = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5)) ret <16 x i32> %v } @@ -491,9 +467,7 @@ define <2 x i64> @sadd_v2i64_vi(<2 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 5, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb) + %v = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5)) ret <2 x i64> %v } @@ -540,9 +514,7 @@ define <4 x i64> @sadd_v4i64_vi(<4 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 5, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb) + %v = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5)) ret <4 x i64> %v } @@ -589,9 +561,7 @@ define <8 x i64> @sadd_v8i64_vi(<8 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 5, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb) + %v = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5)) ret <8 x i64> %v } @@ -638,8 +608,6 @@ define <16 x i64> @sadd_v16i64_vi(<16 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 5, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb) + %v = call <16 x i64> @llvm.sadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5)) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll index ea248010ef09..658481746671 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll @@ -39,9 +39,7 @@ define <2 x i8> @vsaddu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -65,9 +63,7 @@ define <2 x i8> @vsaddu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -77,9 +73,7 @@ define <2 x i8> @vsaddu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -89,11 +83,7 @@ define <2 x i8> @vsaddu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -115,9 +105,7 @@ define <4 x i8> @vsaddu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -153,9 +141,7 @@ define <4 x i8> @vsaddu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -165,9 +151,7 @@ define <4 x i8> @vsaddu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -177,11 +161,7 @@ define <4 x i8> @vsaddu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -203,9 +183,7 @@ define <5 x i8> @vsaddu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -229,9 +207,7 @@ define <5 x i8> @vsaddu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -241,9 +217,7 @@ define <5 x i8> @vsaddu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl) ret <5 x i8> %v } @@ -253,11 +227,7 @@ define <5 x i8> @vsaddu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.uadd.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -279,9 +249,7 @@ define <8 x i8> @vsaddu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -305,9 +273,7 @@ define <8 x i8> @vsaddu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -317,9 +283,7 @@ define <8 x i8> @vsaddu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -329,11 +293,7 @@ define <8 x i8> @vsaddu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -355,9 +315,7 @@ define <16 x i8> @vsaddu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -381,9 +339,7 @@ define <16 x i8> @vsaddu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -393,9 +349,7 @@ define <16 x i8> @vsaddu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -405,11 +359,7 @@ define <16 x i8> @vsaddu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -436,9 +386,7 @@ define <256 x i8> @vsaddu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext % ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl) ret <256 x i8> %v } @@ -460,11 +408,7 @@ define <256 x i8> @vsaddu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v16, v16, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -481,9 +425,7 @@ define <256 x i8> @vsaddu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 129) + %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129) ret <256 x i8> %v } @@ -500,9 +442,7 @@ define <256 x i8> @vsaddu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vsaddu.vi v16, v16, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 128) + %v = call <256 x i8> @llvm.vp.uadd.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128) ret <256 x i8> %v } @@ -524,9 +464,7 @@ define <2 x i16> @vsaddu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -550,9 +488,7 @@ define <2 x i16> @vsaddu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -562,9 +498,7 @@ define <2 x i16> @vsaddu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -574,11 +508,7 @@ define <2 x i16> @vsaddu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -600,9 +530,7 @@ define <4 x i16> @vsaddu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -626,9 +554,7 @@ define <4 x i16> @vsaddu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -638,9 +564,7 @@ define <4 x i16> @vsaddu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -650,11 +574,7 @@ define <4 x i16> @vsaddu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -676,9 +596,7 @@ define <8 x i16> @vsaddu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -702,9 +620,7 @@ define <8 x i16> @vsaddu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -714,9 +630,7 @@ define <8 x i16> @vsaddu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -726,11 +640,7 @@ define <8 x i16> @vsaddu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -752,9 +662,7 @@ define <16 x i16> @vsaddu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -778,9 +686,7 @@ define <16 x i16> @vsaddu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -790,9 +696,7 @@ define <16 x i16> @vsaddu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -802,11 +706,7 @@ define <16 x i16> @vsaddu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -828,9 +728,7 @@ define <2 x i32> @vsaddu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -854,9 +752,7 @@ define <2 x i32> @vsaddu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -866,9 +762,7 @@ define <2 x i32> @vsaddu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -878,11 +772,7 @@ define <2 x i32> @vsaddu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -904,9 +794,7 @@ define <4 x i32> @vsaddu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -930,9 +818,7 @@ define <4 x i32> @vsaddu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -942,9 +828,7 @@ define <4 x i32> @vsaddu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -954,11 +838,7 @@ define <4 x i32> @vsaddu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -980,9 +860,7 @@ define <8 x i32> @vsaddu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1006,9 +884,7 @@ define <8 x i32> @vsaddu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1018,9 +894,7 @@ define <8 x i32> @vsaddu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1030,11 +904,7 @@ define <8 x i32> @vsaddu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1056,9 +926,7 @@ define <16 x i32> @vsaddu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1082,9 +950,7 @@ define <16 x i32> @vsaddu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1094,9 +960,7 @@ define <16 x i32> @vsaddu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1106,11 +970,7 @@ define <16 x i32> @vsaddu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1132,9 +992,7 @@ define <2 x i64> @vsaddu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1186,9 +1044,7 @@ define <2 x i64> @vsaddu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1198,9 +1054,7 @@ define <2 x i64> @vsaddu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1210,11 +1064,7 @@ define <2 x i64> @vsaddu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1236,9 +1086,7 @@ define <4 x i64> @vsaddu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1290,9 +1138,7 @@ define <4 x i64> @vsaddu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1302,9 +1148,7 @@ define <4 x i64> @vsaddu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1314,11 +1158,7 @@ define <4 x i64> @vsaddu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1340,9 +1180,7 @@ define <8 x i64> @vsaddu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1394,9 +1232,7 @@ define <8 x i64> @vsaddu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1406,9 +1242,7 @@ define <8 x i64> @vsaddu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1418,11 +1252,7 @@ define <8 x i64> @vsaddu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1444,9 +1274,7 @@ define <16 x i64> @vsaddu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1498,9 +1326,7 @@ define <16 x i64> @vsaddu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1510,9 +1336,7 @@ define <16 x i64> @vsaddu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1522,11 +1346,7 @@ define <16 x i64> @vsaddu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1659,9 +1479,7 @@ define <32 x i64> @vsaddu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vsaddu.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) + %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12) ret <32 x i64> %v } @@ -1690,8 +1508,6 @@ define <32 x i64> @vsaddu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vsaddu.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 27) + %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll index 5764f51c0ff1..7b2cab294aa4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll @@ -34,9 +34,7 @@ define <2 x i8> @uadd_v2i8_vi(<2 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 8, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> %vb) + %v = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 8)) ret <2 x i8> %v } @@ -70,9 +68,7 @@ define <4 x i8> @uadd_v4i8_vi(<4 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 8, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> %vb) + %v = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 8)) ret <4 x i8> %v } @@ -106,9 +102,7 @@ define <8 x i8> @uadd_v8i8_vi(<8 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 8, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> %vb) + %v = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 8)) ret <8 x i8> %v } @@ -142,9 +136,7 @@ define <16 x i8> @uadd_v16i8_vi(<16 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 8, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> %vb) + %v = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 8)) ret <16 x i8> %v } @@ -178,9 +170,7 @@ define <2 x i16> @uadd_v2i16_vi(<2 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 8, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> %vb) + %v = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 8)) ret <2 x i16> %v } @@ -214,9 +204,7 @@ define <4 x i16> @uadd_v4i16_vi(<4 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 8, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> %vb) + %v = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 8)) ret <4 x i16> %v } @@ -250,9 +238,7 @@ define <8 x i16> @uadd_v8i16_vi(<8 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 8, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> %vb) + %v = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 8)) ret <8 x i16> %v } @@ -286,9 +272,7 @@ define <16 x i16> @uadd_v16i16_vi(<16 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 8, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> %vb) + %v = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 8)) ret <16 x i16> %v } @@ -334,9 +318,7 @@ define <2 x i32> @uadd_v2i32_vi(<2 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 8, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> %vb) + %v = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 8)) ret <2 x i32> %v } @@ -370,9 +352,7 @@ define <4 x i32> @uadd_v4i32_vi(<4 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 8, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> %vb) + %v = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 8)) ret <4 x i32> %v } @@ -406,9 +386,7 @@ define <8 x i32> @uadd_v8i32_vi(<8 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 8, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> %vb) + %v = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 8)) ret <8 x i32> %v } @@ -442,9 +420,7 @@ define <16 x i32> @uadd_v16i32_vi(<16 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 8, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> %vb) + %v = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 8)) ret <16 x i32> %v } @@ -491,9 +467,7 @@ define <2 x i64> @uadd_v2i64_vi(<2 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 8, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> %vb) + %v = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 8)) ret <2 x i64> %v } @@ -540,9 +514,7 @@ define <4 x i64> @uadd_v4i64_vi(<4 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 8, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> %vb) + %v = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 8)) ret <4 x i64> %v } @@ -589,9 +561,7 @@ define <8 x i64> @uadd_v8i64_vi(<8 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 8, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> %vb) + %v = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 8)) ret <8 x i64> %v } @@ -638,8 +608,6 @@ define <16 x i64> @uadd_v16i64_vi(<16 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 8, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> %vb) + %v = call <16 x i64> @llvm.uadd.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 8)) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll index ead41b0717ff..7dcd4c419982 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll @@ -204,10 +204,8 @@ define void @vselect_vi_v6i32(ptr %b, ptr %cc, ptr %z) { ; RV64-NEXT: vse32.v v8, (a2) ; RV64-NEXT: ret %vb = load <6 x i32>, ptr %b - %a = insertelement <6 x i32> poison, i32 -1, i32 0 - %va = shufflevector <6 x i32> %a, <6 x i32> poison, <6 x i32> zeroinitializer %vcc = load <6 x i1>, ptr %cc - %vsel = select <6 x i1> %vcc, <6 x i32> %va, <6 x i32> %vb + %vsel = select <6 x i1> %vcc, <6 x i32> splat (i32 -1), <6 x i32> %vb store <6 x i32> %vsel, ptr %z ret void } @@ -415,10 +413,8 @@ define void @vselect_vfpzero_v6f32(ptr %b, ptr %cc, ptr %z) { ; RV64-NEXT: vse32.v v8, (a2) ; RV64-NEXT: ret %vb = load <6 x float>, ptr %b - %a = insertelement <6 x float> poison, float 0.0, i32 0 - %va = shufflevector <6 x float> %a, <6 x float> poison, <6 x i32> zeroinitializer %vcc = load <6 x i1>, ptr %cc - %vsel = select <6 x i1> %vcc, <6 x float> %va, <6 x float> %vb + %vsel = select <6 x i1> %vcc, <6 x float> splat (float 0.0), <6 x float> %vb store <6 x float> %vsel, ptr %z ret void } @@ -468,10 +464,8 @@ define void @vselect_vi_v8i32(ptr %b, ptr %cc, ptr %z) { ; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %vb = load <8 x i32>, ptr %b - %a = insertelement <8 x i32> poison, i32 -1, i32 0 - %va = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer %vcc = load <8 x i1>, ptr %cc - %vsel = select <8 x i1> %vcc, <8 x i32> %va, <8 x i32> %vb + %vsel = select <8 x i1> %vcc, <8 x i32> splat (i32 -1), <8 x i32> %vb store <8 x i32> %vsel, ptr %z ret void } @@ -521,10 +515,8 @@ define void @vselect_vfpzero_v8f32(ptr %b, ptr %cc, ptr %z) { ; CHECK-NEXT: vse32.v v8, (a2) ; CHECK-NEXT: ret %vb = load <8 x float>, ptr %b - %a = insertelement <8 x float> poison, float 0.0, i32 0 - %va = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer %vcc = load <8 x i1>, ptr %cc - %vsel = select <8 x i1> %vcc, <8 x float> %va, <8 x float> %vb + %vsel = select <8 x i1> %vcc, <8 x float> splat (float 0.0), <8 x float> %vb store <8 x float> %vsel, ptr %z ret void } @@ -574,10 +566,8 @@ define void @vselect_vi_v16i16(ptr %b, ptr %cc, ptr %z) { ; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %vb = load <16 x i16>, ptr %b - %a = insertelement <16 x i16> poison, i16 4, i32 0 - %va = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer %vcc = load <16 x i1>, ptr %cc - %vsel = select <16 x i1> %vcc, <16 x i16> %va, <16 x i16> %vb + %vsel = select <16 x i1> %vcc, <16 x i16> splat (i16 4), <16 x i16> %vb store <16 x i16> %vsel, ptr %z ret void } @@ -630,10 +620,8 @@ define void @vselect_vfpzero_v32f16(ptr %b, ptr %cc, ptr %z) { ; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %vb = load <32 x half>, ptr %b - %a = insertelement <32 x half> poison, half 0.0, i32 0 - %va = shufflevector <32 x half> %a, <32 x half> poison, <32 x i32> zeroinitializer %vcc = load <32 x i1>, ptr %cc - %vsel = select <32 x i1> %vcc, <32 x half> %va, <32 x half> %vb + %vsel = select <32 x i1> %vcc, <32 x half> splat (half 0.0), <32 x half> %vb store <32 x half> %vsel, ptr %z ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll index bbbd6d69e37c..c4b7c1f2f19f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll @@ -37,9 +37,7 @@ define <2 x i8> @vsll_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -63,9 +61,7 @@ define <2 x i8> @vsll_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -75,9 +71,7 @@ define <2 x i8> @vsll_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 3, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> splat (i8 3), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -87,11 +81,7 @@ define <2 x i8> @vsll_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 3, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.shl.v2i8(<2 x i8> %va, <2 x i8> splat (i8 3), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -125,9 +115,7 @@ define <4 x i8> @vsll_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -151,9 +139,7 @@ define <4 x i8> @vsll_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -163,9 +149,7 @@ define <4 x i8> @vsll_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 3, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> splat (i8 3), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -175,11 +159,7 @@ define <4 x i8> @vsll_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 3, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.shl.v4i8(<4 x i8> %va, <4 x i8> splat (i8 3), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -201,9 +181,7 @@ define <8 x i8> @vsll_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -227,9 +205,7 @@ define <8 x i8> @vsll_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -239,9 +215,7 @@ define <8 x i8> @vsll_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 3, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> splat (i8 3), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -251,11 +225,7 @@ define <8 x i8> @vsll_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 3, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.shl.v8i8(<8 x i8> %va, <8 x i8> splat (i8 3), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -277,9 +247,7 @@ define <16 x i8> @vsll_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -303,9 +271,7 @@ define <16 x i8> @vsll_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -315,9 +281,7 @@ define <16 x i8> @vsll_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 3, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> splat (i8 3), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -327,11 +291,7 @@ define <16 x i8> @vsll_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 3, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.shl.v16i8(<16 x i8> %va, <16 x i8> splat (i8 3), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -353,9 +313,7 @@ define <2 x i16> @vsll_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -379,9 +337,7 @@ define <2 x i16> @vsll_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -391,9 +347,7 @@ define <2 x i16> @vsll_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 3, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> splat (i16 3), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -403,11 +357,7 @@ define <2 x i16> @vsll_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 3, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.shl.v2i16(<2 x i16> %va, <2 x i16> splat (i16 3), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -429,9 +379,7 @@ define <4 x i16> @vsll_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -455,9 +403,7 @@ define <4 x i16> @vsll_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -467,9 +413,7 @@ define <4 x i16> @vsll_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 3, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> splat (i16 3), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -479,11 +423,7 @@ define <4 x i16> @vsll_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 3, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.shl.v4i16(<4 x i16> %va, <4 x i16> splat (i16 3), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -505,9 +445,7 @@ define <8 x i16> @vsll_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -531,9 +469,7 @@ define <8 x i16> @vsll_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -543,9 +479,7 @@ define <8 x i16> @vsll_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 3, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> splat (i16 3), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -555,11 +489,7 @@ define <8 x i16> @vsll_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 3, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.shl.v8i16(<8 x i16> %va, <8 x i16> splat (i16 3), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -581,9 +511,7 @@ define <16 x i16> @vsll_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -607,9 +535,7 @@ define <16 x i16> @vsll_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -619,9 +545,7 @@ define <16 x i16> @vsll_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 3, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> splat (i16 3), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -631,11 +555,7 @@ define <16 x i16> @vsll_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 3, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.shl.v16i16(<16 x i16> %va, <16 x i16> splat (i16 3), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -657,9 +577,7 @@ define <2 x i32> @vsll_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -683,9 +601,7 @@ define <2 x i32> @vsll_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -695,9 +611,7 @@ define <2 x i32> @vsll_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 3, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> splat (i32 3), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -707,11 +621,7 @@ define <2 x i32> @vsll_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 3, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.shl.v2i32(<2 x i32> %va, <2 x i32> splat (i32 3), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -733,9 +643,7 @@ define <4 x i32> @vsll_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -759,9 +667,7 @@ define <4 x i32> @vsll_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -771,9 +677,7 @@ define <4 x i32> @vsll_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 3, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> splat (i32 3), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -783,11 +687,7 @@ define <4 x i32> @vsll_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 3, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.shl.v4i32(<4 x i32> %va, <4 x i32> splat (i32 3), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -809,9 +709,7 @@ define <8 x i32> @vsll_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -835,9 +733,7 @@ define <8 x i32> @vsll_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -847,9 +743,7 @@ define <8 x i32> @vsll_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 3, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> splat (i32 3), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -859,11 +753,7 @@ define <8 x i32> @vsll_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 3, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %va, <8 x i32> splat (i32 3), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -885,9 +775,7 @@ define <16 x i32> @vsll_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -911,9 +799,7 @@ define <16 x i32> @vsll_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -923,9 +809,7 @@ define <16 x i32> @vsll_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 3, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> splat (i32 3), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -935,11 +819,7 @@ define <16 x i32> @vsll_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 3, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.shl.v16i32(<16 x i32> %va, <16 x i32> splat (i32 3), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -961,9 +841,7 @@ define <2 x i64> @vsll_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -999,9 +877,7 @@ define <2 x i64> @vsll_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1011,9 +887,7 @@ define <2 x i64> @vsll_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 3, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> splat (i64 3), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1023,11 +897,7 @@ define <2 x i64> @vsll_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 3, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.shl.v2i64(<2 x i64> %va, <2 x i64> splat (i64 3), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1049,9 +919,7 @@ define <4 x i64> @vsll_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1087,9 +955,7 @@ define <4 x i64> @vsll_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1099,9 +965,7 @@ define <4 x i64> @vsll_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 3, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> splat (i64 3), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1111,11 +975,7 @@ define <4 x i64> @vsll_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 3, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.shl.v4i64(<4 x i64> %va, <4 x i64> splat (i64 3), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1137,9 +997,7 @@ define <8 x i64> @vsll_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1175,9 +1033,7 @@ define <8 x i64> @vsll_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1187,9 +1043,7 @@ define <8 x i64> @vsll_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 3, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> splat (i64 3), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1199,11 +1053,7 @@ define <8 x i64> @vsll_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 3, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.shl.v8i64(<8 x i64> %va, <8 x i64> splat (i64 3), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1225,9 +1075,7 @@ define <16 x i64> @vsll_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1263,9 +1111,7 @@ define <16 x i64> @vsll_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1275,9 +1121,7 @@ define <16 x i64> @vsll_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 3, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> splat (i64 3), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1287,10 +1131,6 @@ define <16 x i64> @vsll_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 3, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.shl.v16i64(<16 x i64> %va, <16 x i64> splat (i64 3), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll index fc84e6ce3b6c..7ea5b1f0b505 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll @@ -39,9 +39,7 @@ define <2 x i8> @vsra_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -65,9 +63,7 @@ define <2 x i8> @vsra_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -77,9 +73,7 @@ define <2 x i8> @vsra_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 5, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -89,11 +83,7 @@ define <2 x i8> @vsra_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 5, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ashr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -115,9 +105,7 @@ define <4 x i8> @vsra_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -141,9 +129,7 @@ define <4 x i8> @vsra_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -153,9 +139,7 @@ define <4 x i8> @vsra_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 5, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -165,11 +149,7 @@ define <4 x i8> @vsra_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 5, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ashr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -203,9 +183,7 @@ define <8 x i8> @vsra_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -229,9 +207,7 @@ define <8 x i8> @vsra_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -241,9 +217,7 @@ define <8 x i8> @vsra_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 5, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -253,11 +227,7 @@ define <8 x i8> @vsra_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 5, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ashr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -279,9 +249,7 @@ define <16 x i8> @vsra_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -305,9 +273,7 @@ define <16 x i8> @vsra_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -317,9 +283,7 @@ define <16 x i8> @vsra_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 5, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -329,11 +293,7 @@ define <16 x i8> @vsra_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 5, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ashr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -355,9 +315,7 @@ define <2 x i16> @vsra_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -381,9 +339,7 @@ define <2 x i16> @vsra_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -393,9 +349,7 @@ define <2 x i16> @vsra_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 5, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -405,11 +359,7 @@ define <2 x i16> @vsra_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 5, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ashr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -431,9 +381,7 @@ define <4 x i16> @vsra_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -457,9 +405,7 @@ define <4 x i16> @vsra_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -469,9 +415,7 @@ define <4 x i16> @vsra_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 5, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -481,11 +425,7 @@ define <4 x i16> @vsra_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 5, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ashr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -507,9 +447,7 @@ define <8 x i16> @vsra_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -533,9 +471,7 @@ define <8 x i16> @vsra_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -545,9 +481,7 @@ define <8 x i16> @vsra_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 5, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -557,11 +491,7 @@ define <8 x i16> @vsra_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 5, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ashr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -583,9 +513,7 @@ define <16 x i16> @vsra_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -609,9 +537,7 @@ define <16 x i16> @vsra_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -621,9 +547,7 @@ define <16 x i16> @vsra_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 5, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -633,11 +557,7 @@ define <16 x i16> @vsra_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 5, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ashr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -659,9 +579,7 @@ define <2 x i32> @vsra_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -685,9 +603,7 @@ define <2 x i32> @vsra_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -697,9 +613,7 @@ define <2 x i32> @vsra_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 5, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -709,11 +623,7 @@ define <2 x i32> @vsra_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 5, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ashr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -735,9 +645,7 @@ define <4 x i32> @vsra_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -761,9 +669,7 @@ define <4 x i32> @vsra_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -773,9 +679,7 @@ define <4 x i32> @vsra_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 5, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -785,11 +689,7 @@ define <4 x i32> @vsra_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 5, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ashr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -811,9 +711,7 @@ define <8 x i32> @vsra_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -837,9 +735,7 @@ define <8 x i32> @vsra_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -849,9 +745,7 @@ define <8 x i32> @vsra_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 5, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -861,11 +755,7 @@ define <8 x i32> @vsra_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 5, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -887,9 +777,7 @@ define <16 x i32> @vsra_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -913,9 +801,7 @@ define <16 x i32> @vsra_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -925,9 +811,7 @@ define <16 x i32> @vsra_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 5, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -937,11 +821,7 @@ define <16 x i32> @vsra_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 5, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ashr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -963,9 +843,7 @@ define <2 x i64> @vsra_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1001,9 +879,7 @@ define <2 x i64> @vsra_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1013,9 +889,7 @@ define <2 x i64> @vsra_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 5, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1025,11 +899,7 @@ define <2 x i64> @vsra_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 5, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ashr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 5), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1051,9 +921,7 @@ define <4 x i64> @vsra_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1089,9 +957,7 @@ define <4 x i64> @vsra_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1101,9 +967,7 @@ define <4 x i64> @vsra_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 5, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1113,11 +977,7 @@ define <4 x i64> @vsra_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 5, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ashr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 5), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1139,9 +999,7 @@ define <8 x i64> @vsra_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1177,9 +1035,7 @@ define <8 x i64> @vsra_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1189,9 +1045,7 @@ define <8 x i64> @vsra_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 5, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1201,11 +1055,7 @@ define <8 x i64> @vsra_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 5, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ashr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 5), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1227,9 +1077,7 @@ define <16 x i64> @vsra_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1265,9 +1113,7 @@ define <16 x i64> @vsra_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1277,9 +1123,7 @@ define <16 x i64> @vsra_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 5, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1289,10 +1133,6 @@ define <16 x i64> @vsra_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 5, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ashr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 5), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll index ba3287f74462..9f9d4af0cc2f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll @@ -38,9 +38,7 @@ define <2 x i8> @vsrl_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -64,9 +62,7 @@ define <2 x i8> @vsrl_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -76,9 +72,7 @@ define <2 x i8> @vsrl_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 4, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 4), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -88,11 +82,7 @@ define <2 x i8> @vsrl_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 4, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.lshr.v2i8(<2 x i8> %va, <2 x i8> splat (i8 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -114,9 +104,7 @@ define <4 x i8> @vsrl_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -140,9 +128,7 @@ define <4 x i8> @vsrl_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -152,9 +138,7 @@ define <4 x i8> @vsrl_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 4, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 4), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -164,11 +148,7 @@ define <4 x i8> @vsrl_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 4, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.lshr.v4i8(<4 x i8> %va, <4 x i8> splat (i8 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -202,9 +182,7 @@ define <8 x i8> @vsrl_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -228,9 +206,7 @@ define <8 x i8> @vsrl_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -240,9 +216,7 @@ define <8 x i8> @vsrl_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -252,11 +226,7 @@ define <8 x i8> @vsrl_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 4, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.lshr.v8i8(<8 x i8> %va, <8 x i8> splat (i8 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -278,9 +248,7 @@ define <16 x i8> @vsrl_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -304,9 +272,7 @@ define <16 x i8> @vsrl_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -316,9 +282,7 @@ define <16 x i8> @vsrl_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 4, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 4), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -328,11 +292,7 @@ define <16 x i8> @vsrl_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 4, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.lshr.v16i8(<16 x i8> %va, <16 x i8> splat (i8 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -354,9 +314,7 @@ define <2 x i16> @vsrl_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -380,9 +338,7 @@ define <2 x i16> @vsrl_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -392,9 +348,7 @@ define <2 x i16> @vsrl_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 4, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 4), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -404,11 +358,7 @@ define <2 x i16> @vsrl_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 4, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.lshr.v2i16(<2 x i16> %va, <2 x i16> splat (i16 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -430,9 +380,7 @@ define <4 x i16> @vsrl_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -456,9 +404,7 @@ define <4 x i16> @vsrl_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -468,9 +414,7 @@ define <4 x i16> @vsrl_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 4, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 4), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -480,11 +424,7 @@ define <4 x i16> @vsrl_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 4, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.lshr.v4i16(<4 x i16> %va, <4 x i16> splat (i16 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -506,9 +446,7 @@ define <8 x i16> @vsrl_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -532,9 +470,7 @@ define <8 x i16> @vsrl_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -544,9 +480,7 @@ define <8 x i16> @vsrl_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 4, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 4), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -556,11 +490,7 @@ define <8 x i16> @vsrl_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 4, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.lshr.v8i16(<8 x i16> %va, <8 x i16> splat (i16 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -582,9 +512,7 @@ define <16 x i16> @vsrl_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -608,9 +536,7 @@ define <16 x i16> @vsrl_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -620,9 +546,7 @@ define <16 x i16> @vsrl_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 4, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 4), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -632,11 +556,7 @@ define <16 x i16> @vsrl_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 4, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.lshr.v16i16(<16 x i16> %va, <16 x i16> splat (i16 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -658,9 +578,7 @@ define <2 x i32> @vsrl_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -684,9 +602,7 @@ define <2 x i32> @vsrl_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -696,9 +612,7 @@ define <2 x i32> @vsrl_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 4, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 4), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -708,11 +622,7 @@ define <2 x i32> @vsrl_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 4, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.lshr.v2i32(<2 x i32> %va, <2 x i32> splat (i32 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -734,9 +644,7 @@ define <4 x i32> @vsrl_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -760,9 +668,7 @@ define <4 x i32> @vsrl_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -772,9 +678,7 @@ define <4 x i32> @vsrl_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 4, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 4), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -784,11 +688,7 @@ define <4 x i32> @vsrl_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 4, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.lshr.v4i32(<4 x i32> %va, <4 x i32> splat (i32 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -810,9 +710,7 @@ define <8 x i32> @vsrl_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -836,9 +734,7 @@ define <8 x i32> @vsrl_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -848,9 +744,7 @@ define <8 x i32> @vsrl_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -860,11 +754,7 @@ define <8 x i32> @vsrl_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 4, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %va, <8 x i32> splat (i32 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -886,9 +776,7 @@ define <16 x i32> @vsrl_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -912,9 +800,7 @@ define <16 x i32> @vsrl_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -924,9 +810,7 @@ define <16 x i32> @vsrl_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 4, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 4), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -936,11 +820,7 @@ define <16 x i32> @vsrl_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 4, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.lshr.v16i32(<16 x i32> %va, <16 x i32> splat (i32 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -962,9 +842,7 @@ define <2 x i64> @vsrl_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1000,9 +878,7 @@ define <2 x i64> @vsrl_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1012,9 +888,7 @@ define <2 x i64> @vsrl_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 4, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 4), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1024,11 +898,7 @@ define <2 x i64> @vsrl_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 4, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.lshr.v2i64(<2 x i64> %va, <2 x i64> splat (i64 4), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1050,9 +920,7 @@ define <4 x i64> @vsrl_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1088,9 +956,7 @@ define <4 x i64> @vsrl_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1100,9 +966,7 @@ define <4 x i64> @vsrl_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 4, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 4), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1112,11 +976,7 @@ define <4 x i64> @vsrl_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 4, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.lshr.v4i64(<4 x i64> %va, <4 x i64> splat (i64 4), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1138,9 +998,7 @@ define <8 x i64> @vsrl_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1176,9 +1034,7 @@ define <8 x i64> @vsrl_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1188,9 +1044,7 @@ define <8 x i64> @vsrl_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1200,11 +1054,7 @@ define <8 x i64> @vsrl_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 4, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.lshr.v8i64(<8 x i64> %va, <8 x i64> splat (i64 4), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1226,9 +1076,7 @@ define <16 x i64> @vsrl_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1264,9 +1112,7 @@ define <16 x i64> @vsrl_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1276,9 +1122,7 @@ define <16 x i64> @vsrl_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 4, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 4), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1288,10 +1132,6 @@ define <16 x i64> @vsrl_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 4, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.lshr.v16i64(<16 x i64> %va, <16 x i64> splat (i64 4), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll index 32b8d10d8717..586fef71796e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll @@ -43,9 +43,7 @@ define <2 x i8> @vssub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -69,9 +67,7 @@ define <2 x i8> @vssub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -82,9 +78,7 @@ define <2 x i8> @vssub_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -95,11 +89,7 @@ define <2 x i8> @vssub_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -121,9 +111,7 @@ define <4 x i8> @vssub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -161,9 +149,7 @@ define <4 x i8> @vssub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -174,9 +160,7 @@ define <4 x i8> @vssub_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -187,11 +171,7 @@ define <4 x i8> @vssub_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -213,9 +193,7 @@ define <5 x i8> @vssub_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -239,9 +217,7 @@ define <5 x i8> @vssub_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -252,9 +228,7 @@ define <5 x i8> @vssub_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl) ret <5 x i8> %v } @@ -265,11 +239,7 @@ define <5 x i8> @vssub_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.ssub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -291,9 +261,7 @@ define <8 x i8> @vssub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -317,9 +285,7 @@ define <8 x i8> @vssub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -330,9 +296,7 @@ define <8 x i8> @vssub_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -343,11 +307,7 @@ define <8 x i8> @vssub_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -369,9 +329,7 @@ define <16 x i8> @vssub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -395,9 +353,7 @@ define <16 x i8> @vssub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -408,9 +364,7 @@ define <16 x i8> @vssub_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -421,11 +375,7 @@ define <16 x i8> @vssub_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -453,9 +403,7 @@ define <256 x i8> @vssub_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vssub.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl) ret <256 x i8> %v } @@ -478,11 +426,7 @@ define <256 x i8> @vssub_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssub.vx v16, v16, a2 ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -500,9 +444,7 @@ define <256 x i8> @vssub_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 129) + %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129) ret <256 x i8> %v } @@ -520,9 +462,7 @@ define <256 x i8> @vssub_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vssub.vx v16, v16, a0, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 128) + %v = call <256 x i8> @llvm.vp.ssub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128) ret <256 x i8> %v } @@ -544,9 +484,7 @@ define <2 x i16> @vssub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -570,9 +508,7 @@ define <2 x i16> @vssub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -583,9 +519,7 @@ define <2 x i16> @vssub_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -596,11 +530,7 @@ define <2 x i16> @vssub_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -622,9 +552,7 @@ define <4 x i16> @vssub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -648,9 +576,7 @@ define <4 x i16> @vssub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -661,9 +587,7 @@ define <4 x i16> @vssub_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -674,11 +598,7 @@ define <4 x i16> @vssub_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -700,9 +620,7 @@ define <8 x i16> @vssub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -726,9 +644,7 @@ define <8 x i16> @vssub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -739,9 +655,7 @@ define <8 x i16> @vssub_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -752,11 +666,7 @@ define <8 x i16> @vssub_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -778,9 +688,7 @@ define <16 x i16> @vssub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -804,9 +712,7 @@ define <16 x i16> @vssub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -817,9 +723,7 @@ define <16 x i16> @vssub_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -830,11 +734,7 @@ define <16 x i16> @vssub_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -856,9 +756,7 @@ define <2 x i32> @vssub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -882,9 +780,7 @@ define <2 x i32> @vssub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -895,9 +791,7 @@ define <2 x i32> @vssub_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -908,11 +802,7 @@ define <2 x i32> @vssub_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -934,9 +824,7 @@ define <4 x i32> @vssub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -960,9 +848,7 @@ define <4 x i32> @vssub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -973,9 +859,7 @@ define <4 x i32> @vssub_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -986,11 +870,7 @@ define <4 x i32> @vssub_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -1012,9 +892,7 @@ define <8 x i32> @vssub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1038,9 +916,7 @@ define <8 x i32> @vssub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1051,9 +927,7 @@ define <8 x i32> @vssub_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1064,11 +938,7 @@ define <8 x i32> @vssub_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1090,9 +960,7 @@ define <16 x i32> @vssub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1116,9 +984,7 @@ define <16 x i32> @vssub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1129,9 +995,7 @@ define <16 x i32> @vssub_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1142,11 +1006,7 @@ define <16 x i32> @vssub_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1168,9 +1028,7 @@ define <2 x i64> @vssub_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1222,9 +1080,7 @@ define <2 x i64> @vssub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1235,9 +1091,7 @@ define <2 x i64> @vssub_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1248,11 +1102,7 @@ define <2 x i64> @vssub_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1274,9 +1124,7 @@ define <4 x i64> @vssub_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1328,9 +1176,7 @@ define <4 x i64> @vssub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1341,9 +1187,7 @@ define <4 x i64> @vssub_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1354,11 +1198,7 @@ define <4 x i64> @vssub_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1380,9 +1220,7 @@ define <8 x i64> @vssub_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroe ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1434,9 +1272,7 @@ define <8 x i64> @vssub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %ev ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1447,9 +1283,7 @@ define <8 x i64> @vssub_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1460,11 +1294,7 @@ define <8 x i64> @vssub_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1486,9 +1316,7 @@ define <16 x i64> @vssub_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1540,9 +1368,7 @@ define <16 x i64> @vssub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1553,9 +1379,7 @@ define <16 x i64> @vssub_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1566,11 +1390,7 @@ define <16 x i64> @vssub_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1706,9 +1526,7 @@ define <32 x i64> @vssub_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vssub.vx v16, v16, a0, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) + %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12) ret <32 x i64> %v } @@ -1738,8 +1556,6 @@ define <32 x i64> @vssub_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vssub.vx v16, v16, a0, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 27) + %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll index 941be4aba1b9..efe28eb9021c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll @@ -35,9 +35,7 @@ define <2 x i8> @ssub_v2i8_vi(<2 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb) + %v = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 1)) ret <2 x i8> %v } @@ -72,9 +70,7 @@ define <4 x i8> @ssub_v4i8_vi(<4 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb) + %v = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 1)) ret <4 x i8> %v } @@ -109,9 +105,7 @@ define <8 x i8> @ssub_v8i8_vi(<8 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb) + %v = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 1)) ret <8 x i8> %v } @@ -146,9 +140,7 @@ define <16 x i8> @ssub_v16i8_vi(<16 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb) + %v = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 1)) ret <16 x i8> %v } @@ -183,9 +175,7 @@ define <2 x i16> @ssub_v2i16_vi(<2 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb) + %v = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 1)) ret <2 x i16> %v } @@ -220,9 +210,7 @@ define <4 x i16> @ssub_v4i16_vi(<4 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb) + %v = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 1)) ret <4 x i16> %v } @@ -257,9 +245,7 @@ define <8 x i16> @ssub_v8i16_vi(<8 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb) + %v = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 1)) ret <8 x i16> %v } @@ -294,9 +280,7 @@ define <16 x i16> @ssub_v16i16_vi(<16 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb) + %v = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 1)) ret <16 x i16> %v } @@ -331,9 +315,7 @@ define <2 x i32> @ssub_v2i32_vi(<2 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb) + %v = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 1)) ret <2 x i32> %v } @@ -368,9 +350,7 @@ define <4 x i32> @ssub_v4i32_vi(<4 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb) + %v = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 1)) ret <4 x i32> %v } @@ -405,9 +385,7 @@ define <8 x i32> @ssub_v8i32_vi(<8 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb) + %v = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 1)) ret <8 x i32> %v } @@ -442,9 +420,7 @@ define <16 x i32> @ssub_v16i32_vi(<16 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb) + %v = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 1)) ret <16 x i32> %v } @@ -492,9 +468,7 @@ define <2 x i64> @ssub_v2i64_vi(<2 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb) + %v = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 1)) ret <2 x i64> %v } @@ -542,9 +516,7 @@ define <4 x i64> @ssub_v4i64_vi(<4 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb) + %v = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 1)) ret <4 x i64> %v } @@ -592,9 +564,7 @@ define <8 x i64> @ssub_v8i64_vi(<8 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb) + %v = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 1)) ret <8 x i64> %v } @@ -642,8 +612,6 @@ define <16 x i64> @ssub_v16i64_vi(<16 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb) + %v = call <16 x i64> @llvm.ssub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 1)) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll index 60c16ef543a0..5374e44bf9e8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll @@ -38,9 +38,7 @@ define <2 x i8> @vssubu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -64,9 +62,7 @@ define <2 x i8> @vssubu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -77,9 +73,7 @@ define <2 x i8> @vssubu_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -90,11 +84,7 @@ define <2 x i8> @vssubu_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -116,9 +106,7 @@ define <4 x i8> @vssubu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -156,9 +144,7 @@ define <4 x i8> @vssubu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -169,9 +155,7 @@ define <4 x i8> @vssubu_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -182,11 +166,7 @@ define <4 x i8> @vssubu_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -208,9 +188,7 @@ define <5 x i8> @vssubu_vv_v5i8_unmasked(<5 x i8> %va, <5 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %b, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -234,9 +212,7 @@ define <5 x i8> @vssubu_vx_v5i8_unmasked(<5 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <5 x i8> poison, i8 %b, i32 0 %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -247,9 +223,7 @@ define <5 x i8> @vssubu_vi_v5i8(<5 x i8> %va, <5 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> %m, i32 %evl) ret <5 x i8> %v } @@ -260,11 +234,7 @@ define <5 x i8> @vssubu_vi_v5i8_unmasked(<5 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <5 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <5 x i8> %elt.head, <5 x i8> poison, <5 x i32> zeroinitializer - %head = insertelement <5 x i1> poison, i1 true, i32 0 - %m = shufflevector <5 x i1> %head, <5 x i1> poison, <5 x i32> zeroinitializer - %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> %vb, <5 x i1> %m, i32 %evl) + %v = call <5 x i8> @llvm.vp.usub.sat.v5i8(<5 x i8> %va, <5 x i8> splat (i8 -1), <5 x i1> splat (i1 true), i32 %evl) ret <5 x i8> %v } @@ -286,9 +256,7 @@ define <8 x i8> @vssubu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -312,9 +280,7 @@ define <8 x i8> @vssubu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -325,9 +291,7 @@ define <8 x i8> @vssubu_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -338,11 +302,7 @@ define <8 x i8> @vssubu_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -364,9 +324,7 @@ define <16 x i8> @vssubu_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -390,9 +348,7 @@ define <16 x i8> @vssubu_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %ev ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -403,9 +359,7 @@ define <16 x i8> @vssubu_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -416,11 +370,7 @@ define <16 x i8> @vssubu_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -448,9 +398,7 @@ define <256 x i8> @vssubu_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext % ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vssubu.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 %evl) ret <256 x i8> %v } @@ -473,11 +421,7 @@ define <256 x i8> @vssubu_vi_v258i8_unmasked(<256 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssubu.vx v16, v16, a2 ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %head = insertelement <256 x i1> poison, i1 true, i32 0 - %m = shufflevector <256 x i1> %head, <256 x i1> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 %evl) + %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> splat (i1 true), i32 %evl) ret <256 x i8> %v } @@ -495,9 +439,7 @@ define <256 x i8> @vssubu_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 129) + %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 129) ret <256 x i8> %v } @@ -515,9 +457,7 @@ define <256 x i8> @vssubu_vi_v258i8_evl128(<256 x i8> %va, <256 x i1> %m) { ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vssubu.vx v16, v16, a0, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <256 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <256 x i8> %elt.head, <256 x i8> poison, <256 x i32> zeroinitializer - %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> %vb, <256 x i1> %m, i32 128) + %v = call <256 x i8> @llvm.vp.usub.sat.v258i8(<256 x i8> %va, <256 x i8> splat (i8 -1), <256 x i1> %m, i32 128) ret <256 x i8> %v } @@ -539,9 +479,7 @@ define <2 x i16> @vssubu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -565,9 +503,7 @@ define <2 x i16> @vssubu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -578,9 +514,7 @@ define <2 x i16> @vssubu_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -591,11 +525,7 @@ define <2 x i16> @vssubu_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -617,9 +547,7 @@ define <4 x i16> @vssubu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -643,9 +571,7 @@ define <4 x i16> @vssubu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -656,9 +582,7 @@ define <4 x i16> @vssubu_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -669,11 +593,7 @@ define <4 x i16> @vssubu_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -695,9 +615,7 @@ define <8 x i16> @vssubu_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -721,9 +639,7 @@ define <8 x i16> @vssubu_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -734,9 +650,7 @@ define <8 x i16> @vssubu_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -747,11 +661,7 @@ define <8 x i16> @vssubu_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -773,9 +683,7 @@ define <16 x i16> @vssubu_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -799,9 +707,7 @@ define <16 x i16> @vssubu_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -812,9 +718,7 @@ define <16 x i16> @vssubu_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -825,11 +729,7 @@ define <16 x i16> @vssubu_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -851,9 +751,7 @@ define <2 x i32> @vssubu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -877,9 +775,7 @@ define <2 x i32> @vssubu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -890,9 +786,7 @@ define <2 x i32> @vssubu_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -903,11 +797,7 @@ define <2 x i32> @vssubu_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -929,9 +819,7 @@ define <4 x i32> @vssubu_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -955,9 +843,7 @@ define <4 x i32> @vssubu_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -968,9 +854,7 @@ define <4 x i32> @vssubu_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -981,11 +865,7 @@ define <4 x i32> @vssubu_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -1007,9 +887,7 @@ define <8 x i32> @vssubu_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1033,9 +911,7 @@ define <8 x i32> @vssubu_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %e ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1046,9 +922,7 @@ define <8 x i32> @vssubu_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1059,11 +933,7 @@ define <8 x i32> @vssubu_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1085,9 +955,7 @@ define <16 x i32> @vssubu_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1111,9 +979,7 @@ define <16 x i32> @vssubu_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1124,9 +990,7 @@ define <16 x i32> @vssubu_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1137,11 +1001,7 @@ define <16 x i32> @vssubu_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1163,9 +1023,7 @@ define <2 x i64> @vssubu_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1217,9 +1075,7 @@ define <2 x i64> @vssubu_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1230,9 +1086,7 @@ define <2 x i64> @vssubu_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1243,11 +1097,7 @@ define <2 x i64> @vssubu_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1269,9 +1119,7 @@ define <4 x i64> @vssubu_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1323,9 +1171,7 @@ define <4 x i64> @vssubu_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1336,9 +1182,7 @@ define <4 x i64> @vssubu_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1349,11 +1193,7 @@ define <4 x i64> @vssubu_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1375,9 +1215,7 @@ define <8 x i64> @vssubu_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1429,9 +1267,7 @@ define <8 x i64> @vssubu_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %e ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1442,9 +1278,7 @@ define <8 x i64> @vssubu_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1455,11 +1289,7 @@ define <8 x i64> @vssubu_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1481,9 +1311,7 @@ define <16 x i64> @vssubu_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1535,9 +1363,7 @@ define <16 x i64> @vssubu_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1548,9 +1374,7 @@ define <16 x i64> @vssubu_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1561,11 +1385,7 @@ define <16 x i64> @vssubu_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1701,9 +1521,7 @@ define <32 x i64> @vssubu_vx_v32i64_evl12(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vssubu.vx v16, v16, a0, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) + %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 12) ret <32 x i64> %v } @@ -1733,8 +1551,6 @@ define <32 x i64> @vssubu_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vssubu.vx v16, v16, a0, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 27) + %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 27) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll index f31ee23fe7dc..dc9279f6e7fa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll @@ -35,9 +35,7 @@ define <2 x i8> @usub_v2i8_vi(<2 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 2, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %va, <2 x i8> %vb) + %v = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %va, <2 x i8> splat (i8 2)) ret <2 x i8> %v } @@ -72,9 +70,7 @@ define <4 x i8> @usub_v4i8_vi(<4 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 2, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %va, <4 x i8> %vb) + %v = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %va, <4 x i8> splat (i8 2)) ret <4 x i8> %v } @@ -109,9 +105,7 @@ define <8 x i8> @usub_v8i8_vi(<8 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 2, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %va, <8 x i8> %vb) + %v = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %va, <8 x i8> splat (i8 2)) ret <8 x i8> %v } @@ -146,9 +140,7 @@ define <16 x i8> @usub_v16i8_vi(<16 x i8> %va) { ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 2, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %va, <16 x i8> %vb) + %v = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %va, <16 x i8> splat (i8 2)) ret <16 x i8> %v } @@ -183,9 +175,7 @@ define <2 x i16> @usub_v2i16_vi(<2 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 2, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %va, <2 x i16> %vb) + %v = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %va, <2 x i16> splat (i16 2)) ret <2 x i16> %v } @@ -220,9 +210,7 @@ define <4 x i16> @usub_v4i16_vi(<4 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 2, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %va, <4 x i16> %vb) + %v = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %va, <4 x i16> splat (i16 2)) ret <4 x i16> %v } @@ -257,9 +245,7 @@ define <8 x i16> @usub_v8i16_vi(<8 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 2, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %va, <8 x i16> %vb) + %v = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %va, <8 x i16> splat (i16 2)) ret <8 x i16> %v } @@ -294,9 +280,7 @@ define <16 x i16> @usub_v16i16_vi(<16 x i16> %va) { ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 2, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %va, <16 x i16> %vb) + %v = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %va, <16 x i16> splat (i16 2)) ret <16 x i16> %v } @@ -331,9 +315,7 @@ define <2 x i32> @usub_v2i32_vi(<2 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 2, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %va, <2 x i32> %vb) + %v = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %va, <2 x i32> splat (i32 2)) ret <2 x i32> %v } @@ -368,9 +350,7 @@ define <4 x i32> @usub_v4i32_vi(<4 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 2, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %va, <4 x i32> %vb) + %v = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %va, <4 x i32> splat (i32 2)) ret <4 x i32> %v } @@ -405,9 +385,7 @@ define <8 x i32> @usub_v8i32_vi(<8 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 2, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %va, <8 x i32> %vb) + %v = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %va, <8 x i32> splat (i32 2)) ret <8 x i32> %v } @@ -442,9 +420,7 @@ define <16 x i32> @usub_v16i32_vi(<16 x i32> %va) { ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 2, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %va, <16 x i32> %vb) + %v = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %va, <16 x i32> splat (i32 2)) ret <16 x i32> %v } @@ -492,9 +468,7 @@ define <2 x i64> @usub_v2i64_vi(<2 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 2, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %va, <2 x i64> %vb) + %v = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %va, <2 x i64> splat (i64 2)) ret <2 x i64> %v } @@ -542,9 +516,7 @@ define <4 x i64> @usub_v4i64_vi(<4 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 2, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %va, <4 x i64> %vb) + %v = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %va, <4 x i64> splat (i64 2)) ret <4 x i64> %v } @@ -592,9 +564,7 @@ define <8 x i64> @usub_v8i64_vi(<8 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 2, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %va, <8 x i64> %vb) + %v = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %va, <8 x i64> splat (i64 2)) ret <8 x i64> %v } @@ -642,8 +612,6 @@ define <16 x i64> @usub_v16i64_vi(<16 x i64> %va) { ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 2, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> %va, <16 x i64> %vb) + %v = call <16 x i64> @llvm.usub.sat.v16i64(<16 x i64> %va, <16 x i64> splat (i64 2)) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll index 1c1261494008..6052c9ee20fe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll @@ -34,9 +34,7 @@ define <2 x i8> @vsub_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -60,9 +58,7 @@ define <2 x i8> @vsub_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.sub.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -84,9 +80,7 @@ define <3 x i8> @vsub_vv_v3i8_unmasked(<3 x i8> %va, <3 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <3 x i1> poison, i1 true, i32 0 - %m = shufflevector <3 x i1> %head, <3 x i1> poison, <3 x i32> zeroinitializer - %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> %m, i32 %evl) + %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %b, <3 x i1> splat (i1 true), i32 %evl) ret <3 x i8> %v } @@ -110,9 +104,7 @@ define <3 x i8> @vsub_vx_v3i8_unmasked(<3 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <3 x i8> poison, i8 %b, i32 0 %vb = shufflevector <3 x i8> %elt.head, <3 x i8> poison, <3 x i32> zeroinitializer - %head = insertelement <3 x i1> poison, i1 true, i32 0 - %m = shufflevector <3 x i1> %head, <3 x i1> poison, <3 x i32> zeroinitializer - %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %vb, <3 x i1> %m, i32 %evl) + %v = call <3 x i8> @llvm.vp.sub.v3i8(<3 x i8> %va, <3 x i8> %vb, <3 x i1> splat (i1 true), i32 %evl) ret <3 x i8> %v } @@ -134,9 +126,7 @@ define <4 x i8> @vsub_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -160,9 +150,7 @@ define <4 x i8> @vsub_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.sub.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -184,9 +172,7 @@ define <8 x i8> @vsub_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -210,9 +196,7 @@ define <8 x i8> @vsub_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.sub.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -234,9 +218,7 @@ define <16 x i8> @vsub_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -260,9 +242,7 @@ define <16 x i8> @vsub_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.sub.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -284,9 +264,7 @@ define <2 x i16> @vsub_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -310,9 +288,7 @@ define <2 x i16> @vsub_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.sub.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -334,9 +310,7 @@ define <4 x i16> @vsub_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -360,9 +334,7 @@ define <4 x i16> @vsub_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.sub.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -384,9 +356,7 @@ define <8 x i16> @vsub_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -410,9 +380,7 @@ define <8 x i16> @vsub_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.sub.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -434,9 +402,7 @@ define <16 x i16> @vsub_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -460,9 +426,7 @@ define <16 x i16> @vsub_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.sub.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -484,9 +448,7 @@ define <2 x i32> @vsub_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -510,9 +472,7 @@ define <2 x i32> @vsub_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -534,9 +494,7 @@ define <4 x i32> @vsub_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -560,9 +518,7 @@ define <4 x i32> @vsub_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.sub.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -584,9 +540,7 @@ define <8 x i32> @vsub_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -610,9 +564,7 @@ define <8 x i32> @vsub_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -634,9 +586,7 @@ define <16 x i32> @vsub_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -660,9 +610,7 @@ define <16 x i32> @vsub_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.sub.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -684,9 +632,7 @@ define <2 x i64> @vsub_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -738,9 +684,7 @@ define <2 x i64> @vsub_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.sub.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -762,9 +706,7 @@ define <4 x i64> @vsub_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -816,9 +758,7 @@ define <4 x i64> @vsub_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.sub.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -840,9 +780,7 @@ define <8 x i64> @vsub_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -894,9 +832,7 @@ define <8 x i64> @vsub_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.sub.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -918,9 +854,7 @@ define <16 x i64> @vsub_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -972,8 +906,6 @@ define <16 x i64> @vsub_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.sub.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll index 68cffa98cd3d..16487a078412 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll @@ -34,9 +34,7 @@ define <2 x i8> @vxor_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -72,9 +70,7 @@ define <2 x i8> @vxor_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <2 x i8> poison, i8 %b, i32 0 %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -84,9 +80,7 @@ define <2 x i8> @vxor_vi_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 7, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> splat (i8 7), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -96,11 +90,7 @@ define <2 x i8> @vxor_vi_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 7, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> splat (i8 7), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -110,9 +100,7 @@ define <2 x i8> @vxor_vi_v2i8_1(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -122,11 +110,7 @@ define <2 x i8> @vxor_vi_v2i8_unmasked_1(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i8> @llvm.vp.xor.v2i8(<2 x i8> %va, <2 x i8> splat (i8 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i8> %v } @@ -148,9 +132,7 @@ define <4 x i8> @vxor_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -174,9 +156,7 @@ define <4 x i8> @vxor_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <4 x i8> poison, i8 %b, i32 0 %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -186,9 +166,7 @@ define <4 x i8> @vxor_vi_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 7, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> splat (i8 7), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -198,11 +176,7 @@ define <4 x i8> @vxor_vi_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 7, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> splat (i8 7), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -212,9 +186,7 @@ define <4 x i8> @vxor_vi_v4i8_1(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -224,11 +196,7 @@ define <4 x i8> @vxor_vi_v4i8_unmasked_1(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i8> @llvm.vp.xor.v4i8(<4 x i8> %va, <4 x i8> splat (i8 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i8> %v } @@ -250,9 +218,7 @@ define <8 x i8> @vxor_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -276,9 +242,7 @@ define <8 x i8> @vxor_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <8 x i8> poison, i8 %b, i32 0 %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -288,9 +252,7 @@ define <8 x i8> @vxor_vi_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 7, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> splat (i8 7), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -300,11 +262,7 @@ define <8 x i8> @vxor_vi_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 7, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> splat (i8 7), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -314,9 +272,7 @@ define <8 x i8> @vxor_vi_v8i8_1(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -326,11 +282,7 @@ define <8 x i8> @vxor_vi_v8i8_unmasked_1(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <8 x i8> %elt.head, <8 x i8> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i8> @llvm.vp.xor.v8i8(<8 x i8> %va, <8 x i8> splat (i8 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i8> %v } @@ -352,9 +304,7 @@ define <9 x i8> @vxor_vv_v9i8_unmasked(<9 x i8> %va, <9 x i8> %b, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <9 x i1> poison, i1 true, i32 0 - %m = shufflevector <9 x i1> %head, <9 x i1> poison, <9 x i32> zeroinitializer - %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %b, <9 x i1> %m, i32 %evl) + %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %b, <9 x i1> splat (i1 true), i32 %evl) ret <9 x i8> %v } @@ -378,9 +328,7 @@ define <9 x i8> @vxor_vx_v9i8_unmasked(<9 x i8> %va, i8 %b, i32 zeroext %evl) { ; CHECK-NEXT: ret %elt.head = insertelement <9 x i8> poison, i8 %b, i32 0 %vb = shufflevector <9 x i8> %elt.head, <9 x i8> poison, <9 x i32> zeroinitializer - %head = insertelement <9 x i1> poison, i1 true, i32 0 - %m = shufflevector <9 x i1> %head, <9 x i1> poison, <9 x i32> zeroinitializer - %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %vb, <9 x i1> %m, i32 %evl) + %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %vb, <9 x i1> splat (i1 true), i32 %evl) ret <9 x i8> %v } @@ -390,9 +338,7 @@ define <9 x i8> @vxor_vi_v9i8(<9 x i8> %va, <9 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <9 x i8> poison, i8 7, i32 0 - %vb = shufflevector <9 x i8> %elt.head, <9 x i8> poison, <9 x i32> zeroinitializer - %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %vb, <9 x i1> %m, i32 %evl) + %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> splat (i8 7), <9 x i1> %m, i32 %evl) ret <9 x i8> %v } @@ -402,11 +348,7 @@ define <9 x i8> @vxor_vi_v9i8_unmasked(<9 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <9 x i8> poison, i8 7, i32 0 - %vb = shufflevector <9 x i8> %elt.head, <9 x i8> poison, <9 x i32> zeroinitializer - %head = insertelement <9 x i1> poison, i1 true, i32 0 - %m = shufflevector <9 x i1> %head, <9 x i1> poison, <9 x i32> zeroinitializer - %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %vb, <9 x i1> %m, i32 %evl) + %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> splat (i8 7), <9 x i1> splat (i1 true), i32 %evl) ret <9 x i8> %v } @@ -416,9 +358,7 @@ define <9 x i8> @vxor_vi_v9i8_1(<9 x i8> %va, <9 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <9 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <9 x i8> %elt.head, <9 x i8> poison, <9 x i32> zeroinitializer - %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %vb, <9 x i1> %m, i32 %evl) + %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> splat (i8 -1), <9 x i1> %m, i32 %evl) ret <9 x i8> %v } @@ -428,11 +368,7 @@ define <9 x i8> @vxor_vi_v9i8_unmasked_1(<9 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <9 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <9 x i8> %elt.head, <9 x i8> poison, <9 x i32> zeroinitializer - %head = insertelement <9 x i1> poison, i1 true, i32 0 - %m = shufflevector <9 x i1> %head, <9 x i1> poison, <9 x i32> zeroinitializer - %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> %vb, <9 x i1> %m, i32 %evl) + %v = call <9 x i8> @llvm.vp.xor.v9i8(<9 x i8> %va, <9 x i8> splat (i8 -1), <9 x i1> splat (i1 true), i32 %evl) ret <9 x i8> %v } @@ -454,9 +390,7 @@ define <16 x i8> @vxor_vv_v16i8_unmasked(<16 x i8> %va, <16 x i8> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -480,9 +414,7 @@ define <16 x i8> @vxor_vx_v16i8_unmasked(<16 x i8> %va, i8 %b, i32 zeroext %evl) ; CHECK-NEXT: ret %elt.head = insertelement <16 x i8> poison, i8 %b, i32 0 %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -492,9 +424,7 @@ define <16 x i8> @vxor_vi_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 7, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> splat (i8 7), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -504,11 +434,7 @@ define <16 x i8> @vxor_vi_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 7, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> splat (i8 7), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -518,9 +444,7 @@ define <16 x i8> @vxor_vi_v16i8_1(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -530,11 +454,7 @@ define <16 x i8> @vxor_vi_v16i8_unmasked_1(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i8> poison, i8 -1, i32 0 - %vb = shufflevector <16 x i8> %elt.head, <16 x i8> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i8> @llvm.vp.xor.v16i8(<16 x i8> %va, <16 x i8> splat (i8 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i8> %v } @@ -556,9 +476,7 @@ define <2 x i16> @vxor_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -582,9 +500,7 @@ define <2 x i16> @vxor_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i16> poison, i16 %b, i32 0 %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -594,9 +510,7 @@ define <2 x i16> @vxor_vi_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 7, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> splat (i16 7), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -606,11 +520,7 @@ define <2 x i16> @vxor_vi_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 7, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> splat (i16 7), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -620,9 +530,7 @@ define <2 x i16> @vxor_vi_v2i16_1(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -632,11 +540,7 @@ define <2 x i16> @vxor_vi_v2i16_unmasked_1(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <2 x i16> %elt.head, <2 x i16> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i16> @llvm.vp.xor.v2i16(<2 x i16> %va, <2 x i16> splat (i16 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i16> %v } @@ -658,9 +562,7 @@ define <4 x i16> @vxor_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -684,9 +586,7 @@ define <4 x i16> @vxor_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i16> poison, i16 %b, i32 0 %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -696,9 +596,7 @@ define <4 x i16> @vxor_vi_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 7, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> splat (i16 7), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -708,11 +606,7 @@ define <4 x i16> @vxor_vi_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 7, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> splat (i16 7), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -722,9 +616,7 @@ define <4 x i16> @vxor_vi_v4i16_1(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -734,11 +626,7 @@ define <4 x i16> @vxor_vi_v4i16_unmasked_1(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <4 x i16> %elt.head, <4 x i16> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i16> @llvm.vp.xor.v4i16(<4 x i16> %va, <4 x i16> splat (i16 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -760,9 +648,7 @@ define <8 x i16> @vxor_vv_v8i16_unmasked(<8 x i16> %va, <8 x i16> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -786,9 +672,7 @@ define <8 x i16> @vxor_vx_v8i16_unmasked(<8 x i16> %va, i16 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i16> poison, i16 %b, i32 0 %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -798,9 +682,7 @@ define <8 x i16> @vxor_vi_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 7, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> splat (i16 7), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -810,11 +692,7 @@ define <8 x i16> @vxor_vi_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 7, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> splat (i16 7), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -824,9 +702,7 @@ define <8 x i16> @vxor_vi_v8i16_1(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -836,11 +712,7 @@ define <8 x i16> @vxor_vi_v8i16_unmasked_1(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i16> @llvm.vp.xor.v8i16(<8 x i16> %va, <8 x i16> splat (i16 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i16> %v } @@ -862,9 +734,7 @@ define <16 x i16> @vxor_vv_v16i16_unmasked(<16 x i16> %va, <16 x i16> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -888,9 +758,7 @@ define <16 x i16> @vxor_vx_v16i16_unmasked(<16 x i16> %va, i16 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i16> poison, i16 %b, i32 0 %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -900,9 +768,7 @@ define <16 x i16> @vxor_vi_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 7, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> splat (i16 7), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -912,11 +778,7 @@ define <16 x i16> @vxor_vi_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 7, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> splat (i16 7), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -926,9 +788,7 @@ define <16 x i16> @vxor_vi_v16i16_1(<16 x i16> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -938,11 +798,7 @@ define <16 x i16> @vxor_vi_v16i16_unmasked_1(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i16> poison, i16 -1, i32 0 - %vb = shufflevector <16 x i16> %elt.head, <16 x i16> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i16> @llvm.vp.xor.v16i16(<16 x i16> %va, <16 x i16> splat (i16 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i16> %v } @@ -964,9 +820,7 @@ define <2 x i32> @vxor_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -990,9 +844,7 @@ define <2 x i32> @vxor_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <2 x i32> poison, i32 %b, i32 0 %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -1002,9 +854,7 @@ define <2 x i32> @vxor_vi_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 7, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> splat (i32 7), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -1014,11 +864,7 @@ define <2 x i32> @vxor_vi_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 7, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> splat (i32 7), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -1028,9 +874,7 @@ define <2 x i32> @vxor_vi_v2i32_1(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -1040,11 +884,7 @@ define <2 x i32> @vxor_vi_v2i32_unmasked_1(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <2 x i32> %elt.head, <2 x i32> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i32> @llvm.vp.xor.v2i32(<2 x i32> %va, <2 x i32> splat (i32 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i32> %v } @@ -1066,9 +906,7 @@ define <4 x i32> @vxor_vv_v4i32_unmasked(<4 x i32> %va, <4 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -1092,9 +930,7 @@ define <4 x i32> @vxor_vx_v4i32_unmasked(<4 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <4 x i32> poison, i32 %b, i32 0 %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -1104,9 +940,7 @@ define <4 x i32> @vxor_vi_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 7, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> splat (i32 7), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -1116,11 +950,7 @@ define <4 x i32> @vxor_vi_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 7, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> splat (i32 7), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -1130,9 +960,7 @@ define <4 x i32> @vxor_vi_v4i32_1(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -1142,11 +970,7 @@ define <4 x i32> @vxor_vi_v4i32_unmasked_1(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <4 x i32> %elt.head, <4 x i32> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i32> @llvm.vp.xor.v4i32(<4 x i32> %va, <4 x i32> splat (i32 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -1168,9 +992,7 @@ define <8 x i32> @vxor_vv_v8i32_unmasked(<8 x i32> %va, <8 x i32> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1194,9 +1016,7 @@ define <8 x i32> @vxor_vx_v8i32_unmasked(<8 x i32> %va, i32 %b, i32 zeroext %evl ; CHECK-NEXT: ret %elt.head = insertelement <8 x i32> poison, i32 %b, i32 0 %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1206,9 +1026,7 @@ define <8 x i32> @vxor_vi_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 7, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> splat (i32 7), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1218,11 +1036,7 @@ define <8 x i32> @vxor_vi_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 7, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> splat (i32 7), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1232,9 +1046,7 @@ define <8 x i32> @vxor_vi_v8i32_1(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1244,11 +1056,7 @@ define <8 x i32> @vxor_vi_v8i32_unmasked_1(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <8 x i32> %elt.head, <8 x i32> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %va, <8 x i32> splat (i32 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i32> %v } @@ -1270,9 +1078,7 @@ define <16 x i32> @vxor_vv_v16i32_unmasked(<16 x i32> %va, <16 x i32> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1296,9 +1102,7 @@ define <16 x i32> @vxor_vx_v16i32_unmasked(<16 x i32> %va, i32 %b, i32 zeroext % ; CHECK-NEXT: ret %elt.head = insertelement <16 x i32> poison, i32 %b, i32 0 %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1308,9 +1112,7 @@ define <16 x i32> @vxor_vi_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 7, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> splat (i32 7), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1320,11 +1122,7 @@ define <16 x i32> @vxor_vi_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 7, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> splat (i32 7), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1334,9 +1132,7 @@ define <16 x i32> @vxor_vi_v16i32_1(<16 x i32> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1346,11 +1142,7 @@ define <16 x i32> @vxor_vi_v16i32_unmasked_1(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i32> poison, i32 -1, i32 0 - %vb = shufflevector <16 x i32> %elt.head, <16 x i32> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i32> @llvm.vp.xor.v16i32(<16 x i32> %va, <16 x i32> splat (i32 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i32> %v } @@ -1372,9 +1164,7 @@ define <2 x i64> @vxor_vv_v2i64_unmasked(<2 x i64> %va, <2 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %b, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1426,9 +1216,7 @@ define <2 x i64> @vxor_vx_v2i64_unmasked(<2 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <2 x i64> poison, i64 %b, i32 0 %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1438,9 +1226,7 @@ define <2 x i64> @vxor_vi_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 7, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> splat (i64 7), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1450,11 +1236,7 @@ define <2 x i64> @vxor_vi_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 7, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> splat (i64 7), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1464,9 +1246,7 @@ define <2 x i64> @vxor_vi_v2i64_1(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1476,11 +1256,7 @@ define <2 x i64> @vxor_vi_v2i64_unmasked_1(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <2 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <2 x i64> %elt.head, <2 x i64> poison, <2 x i32> zeroinitializer - %head = insertelement <2 x i1> poison, i1 true, i32 0 - %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> %vb, <2 x i1> %m, i32 %evl) + %v = call <2 x i64> @llvm.vp.xor.v2i64(<2 x i64> %va, <2 x i64> splat (i64 -1), <2 x i1> splat (i1 true), i32 %evl) ret <2 x i64> %v } @@ -1502,9 +1278,7 @@ define <4 x i64> @vxor_vv_v4i64_unmasked(<4 x i64> %va, <4 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %b, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1556,9 +1330,7 @@ define <4 x i64> @vxor_vx_v4i64_unmasked(<4 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <4 x i64> poison, i64 %b, i32 0 %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1568,9 +1340,7 @@ define <4 x i64> @vxor_vi_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 7, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> splat (i64 7), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1580,11 +1350,7 @@ define <4 x i64> @vxor_vi_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 7, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> splat (i64 7), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1594,9 +1360,7 @@ define <4 x i64> @vxor_vi_v4i64_1(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1606,11 +1370,7 @@ define <4 x i64> @vxor_vi_v4i64_unmasked_1(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <4 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <4 x i64> %elt.head, <4 x i64> poison, <4 x i32> zeroinitializer - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> %vb, <4 x i1> %m, i32 %evl) + %v = call <4 x i64> @llvm.vp.xor.v4i64(<4 x i64> %va, <4 x i64> splat (i64 -1), <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -1632,9 +1392,7 @@ define <8 x i64> @vxor_vv_v8i64_unmasked(<8 x i64> %va, <8 x i64> %b, i32 zeroex ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %b, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1686,9 +1444,7 @@ define <8 x i64> @vxor_vx_v8i64_unmasked(<8 x i64> %va, i64 %b, i32 zeroext %evl ; RV64-NEXT: ret %elt.head = insertelement <8 x i64> poison, i64 %b, i32 0 %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1698,9 +1454,7 @@ define <8 x i64> @vxor_vi_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 7, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> splat (i64 7), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1710,11 +1464,7 @@ define <8 x i64> @vxor_vi_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 7, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> splat (i64 7), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1724,9 +1474,7 @@ define <8 x i64> @vxor_vi_v8i64_1(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1736,11 +1484,7 @@ define <8 x i64> @vxor_vi_v8i64_unmasked_1(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <8 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <8 x i64> %elt.head, <8 x i64> poison, <8 x i32> zeroinitializer - %head = insertelement <8 x i1> poison, i1 true, i32 0 - %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> %vb, <8 x i1> %m, i32 %evl) + %v = call <8 x i64> @llvm.vp.xor.v8i64(<8 x i64> %va, <8 x i64> splat (i64 -1), <8 x i1> splat (i1 true), i32 %evl) ret <8 x i64> %v } @@ -1762,9 +1506,7 @@ define <16 x i64> @vxor_vv_v16i64_unmasked(<16 x i64> %va, <16 x i64> %b, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %b, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1816,9 +1558,7 @@ define <16 x i64> @vxor_vx_v16i64_unmasked(<16 x i64> %va, i64 %b, i32 zeroext % ; RV64-NEXT: ret %elt.head = insertelement <16 x i64> poison, i64 %b, i32 0 %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1828,9 +1568,7 @@ define <16 x i64> @vxor_vi_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 7, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> splat (i64 7), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1840,11 +1578,7 @@ define <16 x i64> @vxor_vi_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 7, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> splat (i64 7), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } @@ -1854,9 +1588,7 @@ define <16 x i64> @vxor_vi_v16i64_1(<16 x i64> %va, <16 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -1866,10 +1598,6 @@ define <16 x i64> @vxor_vi_v16i64_unmasked_1(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement <16 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <16 x i64> %elt.head, <16 x i64> poison, <16 x i32> zeroinitializer - %head = insertelement <16 x i1> poison, i1 true, i32 0 - %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> %vb, <16 x i1> %m, i32 %evl) + %v = call <16 x i64> @llvm.vp.xor.v16i64(<16 x i64> %va, <16 x i64> splat (i64 -1), <16 x i1> splat (i1 true), i32 %evl) ret <16 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll index d73496683048..d292978c1d5e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp-mask.ll @@ -22,7 +22,7 @@ define <4 x i16> @vzext_v4i16_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -46,7 +46,7 @@ define <4 x i32> @vzext_v4i32_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -70,6 +70,6 @@ define <4 x i64> @vzext_v4i64_v4i1_unmasked(<4 x i1> %va, i32 zeroext %evl) { ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i1(<4 x i1> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i1(<4 x i1> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll index e99a9b800d76..f4d679cd57ca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll @@ -22,7 +22,7 @@ define <4 x i16> @vzext_v4i16_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i16> @llvm.vp.zext.v4i16.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i16> %v } @@ -46,7 +46,7 @@ define <4 x i32> @vzext_v4i32_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vzext.vf4 v9, v8 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -70,7 +70,7 @@ define <4 x i64> @vzext_v4i64_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: vzext.vf8 v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i8(<4 x i8> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -94,7 +94,7 @@ define <4 x i32> @vzext_v4i32_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vzext.vf2 v9, v8 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i32> @llvm.vp.zext.v4i32.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i32> %v } @@ -118,7 +118,7 @@ define <4 x i64> @vzext_v4i64_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: vzext.vf4 v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i16(<4 x i16> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -142,7 +142,7 @@ define <4 x i64> @vzext_v4i64_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32> %va, <4 x i1> shufflevector (<4 x i1> insertelement (<4 x i1> undef, i1 true, i32 0), <4 x i1> undef, <4 x i32> zeroinitializer), i32 %evl) + %v = call <4 x i64> @llvm.vp.zext.v4i64.v4i32(<4 x i32> %va, <4 x i1> splat (i1 true), i32 %evl) ret <4 x i64> %v } @@ -197,7 +197,7 @@ define <32 x i64> @vzext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl ; CHECK-NEXT: vzext.vf2 v16, v8 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) + %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll index d1cd82d9f7c1..9c4706b2bda7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll @@ -42,9 +42,7 @@ define @vp_floor_nxv1f16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -86,9 +84,7 @@ define @vp_floor_nxv2f16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -130,9 +126,7 @@ define @vp_floor_nxv4f16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -176,9 +170,7 @@ define @vp_floor_nxv8f16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +214,7 @@ define @vp_floor_nxv16f16_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -268,9 +258,7 @@ define @vp_floor_nxv32f16_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -312,9 +300,7 @@ define @vp_floor_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -356,9 +342,7 @@ define @vp_floor_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -402,9 +386,7 @@ define @vp_floor_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -448,9 +430,7 @@ define @vp_floor_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -494,9 +474,7 @@ define @vp_floor_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -538,9 +516,7 @@ define @vp_floor_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -584,9 +560,7 @@ define @vp_floor_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -630,9 +604,7 @@ define @vp_floor_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -676,9 +648,7 @@ define @vp_floor_nxv7f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -722,9 +692,7 @@ define @vp_floor_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -837,8 +805,6 @@ define @vp_floor_nxv16f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.floor.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.floor.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll index 7774e3e4775a..c61d83256c70 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll @@ -76,9 +76,7 @@ define @vfmax_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +148,7 @@ define @vfmax_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -226,9 +222,7 @@ define @vfmax_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -304,9 +298,7 @@ define @vfmax_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -408,9 +400,7 @@ define @vfmax_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -751,9 +741,7 @@ define @vfmax_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -787,9 +775,7 @@ define @vfmax_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -825,9 +811,7 @@ define @vfmax_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -863,9 +847,7 @@ define @vfmax_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -899,9 +881,7 @@ define @vfmax_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -937,9 +917,7 @@ define @vfmax_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -975,9 +953,7 @@ define @vfmax_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +1002,7 @@ define @vfmax_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vfmax.vv v8, v8, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1238,8 +1212,6 @@ define @vfmax_vv_nxv16f64_unmasked( ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv16f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv16f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll index 4e98d0581f89..bdf82f8b7135 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll @@ -76,9 +76,7 @@ define @vfmin_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +148,7 @@ define @vfmin_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -226,9 +222,7 @@ define @vfmin_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -304,9 +298,7 @@ define @vfmin_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -408,9 +400,7 @@ define @vfmin_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -751,9 +741,7 @@ define @vfmin_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -787,9 +775,7 @@ define @vfmin_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -825,9 +811,7 @@ define @vfmin_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -863,9 +847,7 @@ define @vfmin_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -899,9 +881,7 @@ define @vfmin_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -937,9 +917,7 @@ define @vfmin_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v14 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -975,9 +953,7 @@ define @vfmin_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v20 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +1002,7 @@ define @vfmin_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0 ; CHECK-NEXT: vfmin.vv v8, v8, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1238,8 +1212,6 @@ define @vfmin_vv_nxv16f64_unmasked( ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv16f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv16f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll b/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll index f773de3b518c..1d4d554d3a47 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll @@ -38,9 +38,7 @@ define @fma_true( %x, poison, i1 true, i32 0 - %true = shufflevector %head, poison, zeroinitializer - %1 = call fast @llvm.vp.fmul.nxv1f64( %x, %y, %true, i32 %vl) + %1 = call fast @llvm.vp.fmul.nxv1f64( %x, %y, splat (i1 true), i32 %vl) %2 = call fast @llvm.vp.fadd.nxv1f64( %1, %z, %m, i32 %vl) ret %2 } diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll b/llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll index 9e2a33f54f42..f8c1d5e45bc2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll @@ -258,8 +258,6 @@ define @masked_load_allones_mask(ptr %a, %ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret - %insert = insertelement poison, i1 1, i32 0 - %mask = shufflevector %insert, poison, zeroinitializer - %load = call @llvm.masked.load.nxv2i8(ptr %a, i32 1, %mask, %maskedoff) + %load = call @llvm.masked.load.nxv2i8(ptr %a, i32 1, splat (i1 1), %maskedoff) ret %load } diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll b/llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll index a2fec5ab0798..32414feab722 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll @@ -258,8 +258,6 @@ define void @masked_store_allones_mask( %val, ptr %a) nounwind ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %insert = insertelement poison, i1 1, i32 0 - %mask = shufflevector %insert, poison, zeroinitializer - call void @llvm.masked.store.v2i8.p0( %val, ptr %a, i32 1, %mask) + call void @llvm.masked.store.v2i8.p0( %val, ptr %a, i32 1, splat (i1 1)) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll index 0b236f6d3ff3..e12f1cf7603b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll @@ -206,9 +206,7 @@ define @mgather_truemask_nxv4i8( %ptrs, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4i8.nxv4p0( %ptrs, i32 1, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4i8.nxv4p0( %ptrs, i32 1, splat (i1 1), %passthru) ret %v } @@ -429,9 +427,7 @@ define @mgather_truemask_nxv4i16( %ptrs, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4i16.nxv4p0( %ptrs, i32 2, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4i16.nxv4p0( %ptrs, i32 2, splat (i1 1), %passthru) ret %v } @@ -675,9 +671,7 @@ define @mgather_truemask_nxv4i32( %ptrs, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4i32.nxv4p0( %ptrs, i32 4, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4i32.nxv4p0( %ptrs, i32 4, splat (i1 1), %passthru) ret %v } @@ -940,9 +934,7 @@ define @mgather_truemask_nxv4i64( %ptrs, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4i64.nxv4p0( %ptrs, i32 8, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4i64.nxv4p0( %ptrs, i32 8, splat (i1 1), %passthru) ret %v } @@ -1340,9 +1332,7 @@ define @mgather_truemask_nxv4f16( %ptrs, < ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4f16.nxv4p0( %ptrs, i32 2, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4f16.nxv4p0( %ptrs, i32 2, splat (i1 1), %passthru) ret %v } @@ -1542,9 +1532,7 @@ define @mgather_truemask_nxv4f32( %ptrs, ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4f32.nxv4p0( %ptrs, i32 4, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4f32.nxv4p0( %ptrs, i32 4, splat (i1 1), %passthru) ret %v } @@ -1807,9 +1795,7 @@ define @mgather_truemask_nxv4f64( %ptrs, ; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64-NEXT: vluxei64.v v8, (zero), v8 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.masked.gather.nxv4f64.nxv4p0( %ptrs, i32 8, %mtrue, %passthru) + %v = call @llvm.masked.gather.nxv4f64.nxv4p0( %ptrs, i32 8, splat (i1 1), %passthru) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll index 652e7a128a96..0e09f59b6a20 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll @@ -139,9 +139,7 @@ define void @mscatter_truemask_nxv4i8( %val, ; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV64-NEXT: vsoxei64.v v8, (zero), v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4i8.nxv4p0( %val, %ptrs, i32 1, %mtrue) + call void @llvm.masked.scatter.nxv4i8.nxv4p0( %val, %ptrs, i32 1, splat (i1 1)) ret void } @@ -300,9 +298,7 @@ define void @mscatter_truemask_nxv4i16( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4i16.nxv4p0( %val, %ptrs, i32 2, %mtrue) + call void @llvm.masked.scatter.nxv4i16.nxv4p0( %val, %ptrs, i32 2, splat (i1 1)) ret void } @@ -499,9 +495,7 @@ define void @mscatter_truemask_nxv4i32( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4i32.nxv4p0( %val, %ptrs, i32 4, %mtrue) + call void @llvm.masked.scatter.nxv4i32.nxv4p0( %val, %ptrs, i32 4, splat (i1 1)) ret void } @@ -737,9 +731,7 @@ define void @mscatter_truemask_nxv4i64( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4i64.nxv4p0( %val, %ptrs, i32 8, %mtrue) + call void @llvm.masked.scatter.nxv4i64.nxv4p0( %val, %ptrs, i32 8, splat (i1 1)) ret void } @@ -1041,9 +1033,7 @@ define void @mscatter_truemask_nxv4f16( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4f16.nxv4p0( %val, %ptrs, i32 2, %mtrue) + call void @llvm.masked.scatter.nxv4f16.nxv4p0( %val, %ptrs, i32 2, splat (i1 1)) ret void } @@ -1221,9 +1211,7 @@ define void @mscatter_truemask_nxv4f32( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4f32.nxv4p0( %val, %ptrs, i32 4, %mtrue) + call void @llvm.masked.scatter.nxv4f32.nxv4p0( %val, %ptrs, i32 4, splat (i1 1)) ret void } @@ -1459,9 +1447,7 @@ define void @mscatter_truemask_nxv4f64( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4f64.nxv4p0( %val, %ptrs, i32 8, %mtrue) + call void @llvm.masked.scatter.nxv4f64.nxv4p0( %val, %ptrs, i32 8, splat (i1 1)) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll b/llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll index f608a63d6bb9..e47517abacb4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll +++ b/llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll @@ -18,9 +18,7 @@ define @test_vloxei(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -40,9 +38,7 @@ define @test_vloxei2(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 14, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 14) %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -62,9 +58,7 @@ define @test_vloxei3(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 26, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 26) %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -87,9 +81,7 @@ define @test_vloxei4(ptr %ptr, %offset, @llvm.vp.zext.nxvi64.nxv1i8( %offset, %m, i32 %vl) - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) %vl.i64 = zext i32 %vl to i64 %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( undef, @@ -116,9 +108,7 @@ define @test_vloxei5(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i16 12, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i16 12) %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i16( undef, ptr %ptr, @@ -141,9 +131,7 @@ define @test_vloxei6(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -164,9 +152,7 @@ define @test_vloxei7(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 2, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 2) %res = call @llvm.riscv.vloxei.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -194,9 +180,7 @@ define @test_vloxei_mask(ptr %ptr, %offset, ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) %res = call @llvm.riscv.vloxei.mask.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -223,9 +207,7 @@ define @test_vluxei(ptr %ptr, %offset, i64 ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) %res = call @llvm.riscv.vluxei.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -253,9 +235,7 @@ define @test_vluxei_mask(ptr %ptr, %offset, ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) %res = call @llvm.riscv.vluxei.mask.nxv4i32.nxv4i64( undef, ptr %ptr, @@ -282,9 +262,7 @@ define void @test_vsoxei( %val, ptr %ptr, %o ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) call void @llvm.riscv.vsoxei.nxv4i32.nxv4i64( %val, ptr %ptr, @@ -311,9 +289,7 @@ define void @test_vsoxei_mask( %val, ptr %ptr, %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64( %val, ptr %ptr, @@ -340,9 +316,7 @@ define void @test_vsuxei( %val, ptr %ptr, %o ; CHECK-NEXT: ret entry: %offset.ext = zext %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) call void @llvm.riscv.vsuxei.nxv4i32.nxv4i64( %val, ptr %ptr, @@ -369,9 +343,7 @@ define void @test_vsuxei_mask( %val, ptr %ptr, %offset to - %shamt = insertelement undef, i64 4, i32 0 - %shamt.vec = shufflevector %shamt, poison, zeroinitializer - %shl = shl %offset.ext, %shamt.vec + %shl = shl %offset.ext, splat (i64 4) call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i64( %val, ptr %ptr, diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll index 126836cd9390..9ab7fdb82fd0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll @@ -86,9 +86,7 @@ define @vp_nearbyint_nxv1f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -170,9 +168,7 @@ define @vp_nearbyint_nxv2f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -256,9 +252,7 @@ define @vp_nearbyint_nxv4f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -344,9 +338,7 @@ define @vp_nearbyint_nxv8f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -432,9 +424,7 @@ define @vp_nearbyint_nxv16f16_unmasked( ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -653,9 +643,7 @@ define @vp_nearbyint_nxv1f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -697,9 +685,7 @@ define @vp_nearbyint_nxv2f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -743,9 +729,7 @@ define @vp_nearbyint_nxv4f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -789,9 +773,7 @@ define @vp_nearbyint_nxv8f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -835,9 +817,7 @@ define @vp_nearbyint_nxv16f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -879,9 +859,7 @@ define @vp_nearbyint_nxv1f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -925,9 +903,7 @@ define @vp_nearbyint_nxv2f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -971,9 +947,7 @@ define @vp_nearbyint_nxv4f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1017,9 +991,7 @@ define @vp_nearbyint_nxv7f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1063,9 +1035,7 @@ define @vp_nearbyint_nxv8f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1189,8 +1159,6 @@ define @vp_nearbyint_nxv16f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll index 04761d4e7bfc..fc5213b91e61 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll @@ -78,9 +78,7 @@ define @vp_rint_nxv1f16_unmasked( %va, i3 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -154,9 +152,7 @@ define @vp_rint_nxv2f16_unmasked( %va, i3 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +228,7 @@ define @vp_rint_nxv4f16_unmasked( %va, i3 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -312,9 +306,7 @@ define @vp_rint_nxv8f16_unmasked( %va, i3 ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -392,9 +384,7 @@ define @vp_rint_nxv16f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -598,9 +588,7 @@ define @vp_rint_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -638,9 +626,7 @@ define @vp_rint_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -680,9 +666,7 @@ define @vp_rint_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -722,9 +706,7 @@ define @vp_rint_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -764,9 +746,7 @@ define @vp_rint_nxv16f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -804,9 +784,7 @@ define @vp_rint_nxv1f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -846,9 +824,7 @@ define @vp_rint_nxv2f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -888,9 +864,7 @@ define @vp_rint_nxv4f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -930,9 +904,7 @@ define @vp_rint_nxv7f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -972,9 +944,7 @@ define @vp_rint_nxv8f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1079,8 +1049,6 @@ define @vp_rint_nxv16f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll index 16bd665dd0de..c4e472acca6e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll @@ -86,9 +86,7 @@ define @vp_round_nxv1f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -170,9 +168,7 @@ define @vp_round_nxv2f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -256,9 +252,7 @@ define @vp_round_nxv4f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -344,9 +338,7 @@ define @vp_round_nxv8f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -432,9 +424,7 @@ define @vp_round_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -654,9 +644,7 @@ define @vp_round_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -698,9 +686,7 @@ define @vp_round_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -744,9 +730,7 @@ define @vp_round_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -790,9 +774,7 @@ define @vp_round_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -836,9 +818,7 @@ define @vp_round_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -880,9 +860,7 @@ define @vp_round_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +904,7 @@ define @vp_round_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -972,9 +948,7 @@ define @vp_round_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1018,9 +992,7 @@ define @vp_round_nxv7f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1064,9 +1036,7 @@ define @vp_round_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1179,8 +1149,6 @@ define @vp_round_nxv16f64_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll index 429ddb6c71be..47edb4e64502 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll @@ -86,9 +86,7 @@ define @vp_roundeven_nxv1f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -170,9 +168,7 @@ define @vp_roundeven_nxv2f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -256,9 +252,7 @@ define @vp_roundeven_nxv4f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -344,9 +338,7 @@ define @vp_roundeven_nxv8f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -432,9 +424,7 @@ define @vp_roundeven_nxv16f16_unmasked( ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -654,9 +644,7 @@ define @vp_roundeven_nxv1f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -698,9 +686,7 @@ define @vp_roundeven_nxv2f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -744,9 +730,7 @@ define @vp_roundeven_nxv4f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -790,9 +774,7 @@ define @vp_roundeven_nxv8f32_unmasked( ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -836,9 +818,7 @@ define @vp_roundeven_nxv16f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -880,9 +860,7 @@ define @vp_roundeven_nxv1f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +904,7 @@ define @vp_roundeven_nxv2f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -972,9 +948,7 @@ define @vp_roundeven_nxv4f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1018,9 +992,7 @@ define @vp_roundeven_nxv7f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1064,9 +1036,7 @@ define @vp_roundeven_nxv8f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1179,8 +1149,6 @@ define @vp_roundeven_nxv16f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll index c854e0fb8a05..9a67eb2b53b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll @@ -86,9 +86,7 @@ define @vp_roundtozero_nxv1f16_unmasked( ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -170,9 +168,7 @@ define @vp_roundtozero_nxv2f16_unmasked( ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -256,9 +252,7 @@ define @vp_roundtozero_nxv4f16_unmasked( ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -344,9 +338,7 @@ define @vp_roundtozero_nxv8f16_unmasked( ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -432,9 +424,7 @@ define @vp_roundtozero_nxv16f16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -654,9 +644,7 @@ define @vp_roundtozero_nxv1f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -698,9 +686,7 @@ define @vp_roundtozero_nxv2f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -744,9 +730,7 @@ define @vp_roundtozero_nxv4f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -790,9 +774,7 @@ define @vp_roundtozero_nxv8f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -836,9 +818,7 @@ define @vp_roundtozero_nxv16f32_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -880,9 +860,7 @@ define @vp_roundtozero_nxv1f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +904,7 @@ define @vp_roundtozero_nxv2f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -972,9 +948,7 @@ define @vp_roundtozero_nxv4f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1018,9 +992,7 @@ define @vp_roundtozero_nxv7f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1064,9 +1036,7 @@ define @vp_roundtozero_nxv8f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -1179,8 +1149,6 @@ define @vp_roundtozero_nxv16f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll index 5f381a307099..8cefbac59ce6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll @@ -11,9 +11,7 @@ define @vpmerge_vadd( %passthru, @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %passthru, %x, %y, %m, i64 %vl, i64 1) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } declare @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(, , , , i64, i64) @@ -25,9 +23,7 @@ define @vpmerge_vsub( %passthru, @llvm.riscv.vsub.mask.nxv2i32.nxv2i32( %passthru, %x, %y, %m, i64 %vl, i64 1) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } declare @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(, , , , i64, i64) @@ -39,9 +35,7 @@ define @vpmerge_vfadd( %passthru, @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( %passthru, %x, %y, %m, i64 7, i64 %vl, i64 1) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2f32.nxv2f32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2f32.nxv2f32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } @@ -54,9 +48,7 @@ define @vpmerge_vfsub( %passthru, @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32( %passthru, %x, %y, %m, i64 7, i64 %vl, i64 1) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2f32.nxv2f32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2f32.nxv2f32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } declare @llvm.riscv.vfsub.mask.nxv2f32.nxv2f32(, , , , i64, i64, i64) @@ -68,9 +60,7 @@ define @vpmerge_vwadd( %passthru, @llvm.riscv.vwadd.mask.nxv2i32.nxv2i16.nxv2i16( %passthru, %x, %y, %m, i64 %vl, i64 1) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } declare @llvm.riscv.vwadd.mask.nxv2i32.nxv2i16.nxv2i16(, , , , i64, i64) @@ -86,9 +76,7 @@ define @vpmerge_vle( %passthru, ptr %p, %m, i64 %vl, i64 1) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } declare @llvm.riscv.vle.mask.nxv2i32(, ptr, , i64, i64) @@ -101,9 +89,7 @@ define @vpmerge_vslideup( %passthru, @llvm.riscv.vslideup.mask.nxv2i32( %passthru, %v, i64 %x, %m, i64 %vl, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } @@ -115,9 +101,7 @@ define @vpmerge_vslidedown( %passthru, @llvm.riscv.vslidedown.mask.nxv2i32( %passthru, %v, i64 %x, %m, i64 %vl, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } @@ -129,9 +113,7 @@ define @vpmerge_vslide1up( %passthru, @llvm.riscv.vslide1up.mask.nxv2i32( %passthru, %v, i32 %x, %m, i64 %vl, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } @@ -143,9 +125,7 @@ define @vpmerge_vslide1down( %passthru, @llvm.riscv.vslide1down.mask.nxv2i32( %passthru, %v, i32 %x, %m, i64 %vl, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } @@ -159,9 +139,7 @@ define @vmerge_smaller_vl_same_passthru( %p ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %a = call @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %passthru, %x, %y, %m, i64 3, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 2) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 2) ret %b } @@ -173,9 +151,7 @@ define @vmerge_larger_vl_same_passthru( %pa ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %a = call @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %passthru, %x, %y, %m, i64 2, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 3) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 3) ret %b } @@ -190,9 +166,7 @@ define @vmerge_smaller_vl_different_passthru( @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %pt1, %x, %y, %m, i64 3, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %pt2, %pt2, %a, %mask, i64 2) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %pt2, %pt2, %a, splat (i1 -1), i64 2) ret %b } @@ -207,9 +181,7 @@ define @vmerge_larger_vl_different_passthru( @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( %pt1, %x, %y, %m, i64 2, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %pt2, %pt2, %a, %mask, i64 3) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %pt2, %pt2, %a, splat (i1 -1), i64 3) ret %b } @@ -221,9 +193,7 @@ define @vmerge_smaller_vl_poison_passthru( ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %a = call @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( poison, %x, %y, %m, i64 3, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 2) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 2) ret %b } @@ -235,9 +205,7 @@ define @vmerge_larger_vl_poison_passthru( % ; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %a = call @llvm.riscv.vadd.mask.nxv2i32.nxv2i32( poison, %x, %y, %m, i64 2, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 3) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 3) ret %b } @@ -269,8 +237,6 @@ define @vpmerge_viota( %passthru, @llvm.riscv.viota.mask.nxv2i32( undef, %vm, %m, i64 %1, i64 0) - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %1) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %1) ret %b } diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll index 52bd15742ef4..31fd5bdbd31f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll @@ -19,9 +19,7 @@ define void @vpmerge_vpload_store( %passthru, ptr %p, ) into %ir.p) ; CHECK-NEXT: PseudoRET - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) store %b, ptr %p ret void @@ -40,9 +38,7 @@ define void @vpselect_vpload_store( %passthru, ptr %p, ) into %ir.p) ; CHECK-NEXT: PseudoRET - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) store %b, ptr %p ret void diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll index 7cc4a9da3d42..970581b4d80a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll @@ -14,9 +14,7 @@ define @vpmerge_vpadd( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.add.nxv2i32( %x, %y, %mask, i32 %vl) + %a = call @llvm.vp.add.nxv2i32( %x, %y, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -31,10 +29,8 @@ define @vpmerge_vpadd2( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.add.nxv2i32( %x, %y, %mask, i32 %vl) - %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", %mask, i32 %vl) + %a = call @llvm.vp.add.nxv2i32( %x, %y, splat (i1 -1), i32 %vl) + %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -46,10 +42,8 @@ define @vpmerge_vpadd3( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.add.nxv2i32( %x, %y, %mask, i32 %vl) - %b = call @llvm.vp.merge.nxv2i32( %mask, %a, %passthru, i32 %vl) + %a = call @llvm.vp.add.nxv2i32( %x, %y, splat (i1 -1), i32 %vl) + %b = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %a, %passthru, i32 %vl) ret %b } @@ -61,9 +55,7 @@ define @vpmerge_vpfadd( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fadd.nxv2f32( %x, %y, %mask, i32 %vl) + %a = call @llvm.vp.fadd.nxv2f32( %x, %y, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2f32( %m, %a, %passthru, i32 %vl) ret %b } @@ -90,9 +82,7 @@ define @vpmerge_vpfptosi( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fptosi.nxv2i16.nxv2f32( %x, %mask, i32 %vl) + %a = call @llvm.vp.fptosi.nxv2i16.nxv2f32( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i16( %m, %a, %passthru, i32 %vl) ret %b } @@ -105,9 +95,7 @@ define @vpmerge_vpsitofp( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %x, %mask, i32 %vl) + %a = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2f32( %m, %a, %passthru, i32 %vl) ret %b } @@ -120,9 +108,7 @@ define @vpmerge_vpzext( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.zext.nxv2i32.nxv2i8( %x, %mask, i32 %vl) + %a = call @llvm.vp.zext.nxv2i32.nxv2i8( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -135,9 +121,7 @@ define @vpmerge_vptrunc( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.trunc.nxv2i32.nxv2i64( %x, %mask, i32 %vl) + %a = call @llvm.vp.trunc.nxv2i32.nxv2i64( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -150,9 +134,7 @@ define @vpmerge_vpfpext( %passthru, < ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fpext.nxv2f64.nxv2f32( %x, %mask, i32 %vl) + %a = call @llvm.vp.fpext.nxv2f64.nxv2f32( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2f64( %m, %a, %passthru, i32 %vl) ret %b } @@ -165,9 +147,7 @@ define @vpmerge_vpfptrunc( %passthru, < ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fptrunc.nxv2f32.nxv2f64( %x, %mask, i32 %vl) + %a = call @llvm.vp.fptrunc.nxv2f32.nxv2f64( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2f32( %m, %a, %passthru, i32 %vl) ret %b } @@ -180,9 +160,7 @@ define @vpmerge_vpload( %passthru, ptr %p, ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -196,10 +174,8 @@ define @vpmerge_vpload2( %passthru, ptr %p, ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) - %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) + %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -212,9 +188,7 @@ define void @vpmerge_vpload_store( %passthru, ptr %p, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) %b = call @llvm.vp.merge.nxv2i32( %m, %a, %passthru, i32 %vl) store %b, ptr %p ret void @@ -304,9 +278,7 @@ define @vpmerge_viota2( %passthru, @llvm.riscv.viota.nxv2i32( undef, %vm, i64 %1) - %splat = insertelement poison, i1 -1, i32 0 - %true = shufflevector %splat, poison, zeroinitializer - %b = call @llvm.vp.merge.nxv2i32( %true, %a, %passthru, i32 %vl) + %b = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %a, %passthru, i32 %vl) ret %b } @@ -494,9 +466,7 @@ define @vpselect_vpadd( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.add.nxv2i32( %x, %y, %mask, i32 %vl) + %a = call @llvm.vp.add.nxv2i32( %x, %y, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -509,10 +479,8 @@ define @vpselect_vpadd2( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.add.nxv2i32( %x, %y, %mask, i32 %vl) - %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", %mask, i32 %vl) + %a = call @llvm.vp.add.nxv2i32( %x, %y, splat (i1 -1), i32 %vl) + %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -524,10 +492,8 @@ define @vpselect_vpadd3( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.add.nxv2i32( %x, %y, %mask, i32 %vl) - %b = call @llvm.vp.select.nxv2i32( %mask, %a, %passthru, i32 %vl) + %a = call @llvm.vp.add.nxv2i32( %x, %y, splat (i1 -1), i32 %vl) + %b = call @llvm.vp.select.nxv2i32( splat (i1 -1), %a, %passthru, i32 %vl) ret %b } @@ -538,9 +504,7 @@ define @vpselect_vpfadd( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fadd.nxv2f32( %x, %y, %mask, i32 %vl) + %a = call @llvm.vp.fadd.nxv2f32( %x, %y, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2f32( %m, %a, %passthru, i32 %vl) ret %b } @@ -565,9 +529,7 @@ define @vpselect_vpfptosi( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fptosi.nxv2i16.nxv2f32( %x, %mask, i32 %vl) + %a = call @llvm.vp.fptosi.nxv2i16.nxv2f32( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i16( %m, %a, %passthru, i32 %vl) ret %b } @@ -579,9 +541,7 @@ define @vpselect_vpsitofp( %passthru, < ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %x, %mask, i32 %vl) + %a = call @llvm.vp.sitofp.nxv2f32.nxv2i64( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2f32( %m, %a, %passthru, i32 %vl) ret %b } @@ -593,9 +553,7 @@ define @vpselect_vpzext( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.zext.nxv2i32.nxv2i8( %x, %mask, i32 %vl) + %a = call @llvm.vp.zext.nxv2i32.nxv2i8( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -607,9 +565,7 @@ define @vpselect_vptrunc( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.trunc.nxv2i32.nxv2i64( %x, %mask, i32 %vl) + %a = call @llvm.vp.trunc.nxv2i32.nxv2i64( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -621,9 +577,7 @@ define @vpselect_vpfpext( %passthru, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfwcvt.f.f.v v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fpext.nxv2f64.nxv2f32( %x, %mask, i32 %vl) + %a = call @llvm.vp.fpext.nxv2f64.nxv2f32( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2f64( %m, %a, %passthru, i32 %vl) ret %b } @@ -635,9 +589,7 @@ define @vpselect_vpfptrunc( %passthru, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.fptrunc.nxv2f32.nxv2f64( %x, %mask, i32 %vl) + %a = call @llvm.vp.fptrunc.nxv2f32.nxv2f64( %x, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2f32( %m, %a, %passthru, i32 %vl) ret %b } @@ -649,9 +601,7 @@ define @vpselect_vpload( %passthru, ptr %p, ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -664,10 +614,8 @@ define @vpselect_vpload2( %passthru, ptr %p ; CHECK-NEXT: vmseq.vv v0, v9, v10 ; CHECK-NEXT: vle32.v v8, (a0), v0.t ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) - %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) + %m = call @llvm.vp.icmp.nxv2i32( %x, %y, metadata !"eq", splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) ret %b } @@ -680,9 +628,7 @@ define void @vpselect_vpload_store( %passthru, ptr %p, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, %mask, i32 %vl) + %a = call @llvm.vp.load.nxv2i32.p0(ptr %p, splat (i1 -1), i32 %vl) %b = call @llvm.vp.select.nxv2i32( %m, %a, %passthru, i32 %vl) store %b, ptr %p ret void @@ -1052,15 +998,12 @@ define @vredsum_allones_mask( %passthru, poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.riscv.vredsum.nxv2i32.nxv2i32( %passthru, %x, %y, i64 %vl) - %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2i32.nxv2i32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } @@ -1072,15 +1015,12 @@ define @vfredusum_allones_mask( %passth ; CHECK-NEXT: vfredusum.vs v8, v9, v10 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %mask = shufflevector %splat, poison, zeroinitializer - %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( %passthru, %x, %y, i64 0, i64 %vl) - %b = call @llvm.riscv.vmerge.nxv2f32.nxv2f32( %passthru, %passthru, %a, %mask, i64 %vl) + %b = call @llvm.riscv.vmerge.nxv2f32.nxv2f32( %passthru, %passthru, %a, splat (i1 -1), i64 %vl) ret %b } diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll index bd431186f056..3aeb4e864627 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-vmerge-to-vmv.ll @@ -7,9 +7,7 @@ define @vpmerge_mf8( %x, %y ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i8 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv1i8( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %x, i32 %vl) ret %1 } @@ -19,9 +17,7 @@ define @vpmerge_mf4( %x, %y ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i8 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv2i8( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %x, i32 %vl) ret %1 } @@ -31,9 +27,7 @@ define @vpmerge_mf2( %x, %y ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i8 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv4i8( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %x, i32 %vl) ret %1 } @@ -43,9 +37,7 @@ define @vpmerge_m1( %x, %y, ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i8 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv8i8( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %x, i32 %vl) ret %1 } @@ -55,9 +47,7 @@ define @vpmerge_m2( %x, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i16 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv8i16( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %x, i32 %vl) ret %1 } @@ -67,9 +57,7 @@ define @vpmerge_m4( %x, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv8i32( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %x, i32 %vl) ret %1 } @@ -79,9 +67,7 @@ define @vpmerge_m8( %x, ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i64 0 - %allones = shufflevector %splat, poison, zeroinitializer - %1 = call @llvm.vp.merge.nxv8i64( %allones, %y, %x, i32 %vl) + %1 = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %x, i32 %vl) ret %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll index b1f1a4dceccf..7fd77c050b29 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll @@ -49,9 +49,7 @@ define @icmp_eq_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"eq", %m, i32 %evl) ret %v } @@ -61,9 +59,7 @@ define @icmp_eq_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"eq", %m, i32 %evl) ret %v } @@ -107,9 +103,7 @@ define @icmp_ne_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"ne", %m, i32 %evl) ret %v } @@ -119,9 +113,7 @@ define @icmp_ne_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"ne", %m, i32 %evl) ret %v } @@ -165,9 +157,7 @@ define @icmp_ugt_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"ugt", %m, i32 %evl) ret %v } @@ -177,9 +167,7 @@ define @icmp_ugt_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"ugt", %m, i32 %evl) ret %v } @@ -225,9 +213,7 @@ define @icmp_uge_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"uge", %m, i32 %evl) ret %v } @@ -237,9 +223,7 @@ define @icmp_uge_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"uge", %m, i32 %evl) ret %v } @@ -283,9 +267,7 @@ define @icmp_ult_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"ult", %m, i32 %evl) ret %v } @@ -295,9 +277,7 @@ define @icmp_ult_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"ult", %m, i32 %evl) ret %v } @@ -341,9 +321,7 @@ define @icmp_sgt_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"sgt", %m, i32 %evl) ret %v } @@ -353,9 +331,7 @@ define @icmp_sgt_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"sgt", %m, i32 %evl) ret %v } @@ -401,9 +377,7 @@ define @icmp_sge_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"sge", %m, i32 %evl) ret %v } @@ -413,9 +387,7 @@ define @icmp_sge_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"sge", %m, i32 %evl) ret %v } @@ -459,9 +431,7 @@ define @icmp_slt_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"slt", %m, i32 %evl) ret %v } @@ -471,9 +441,7 @@ define @icmp_slt_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"slt", %m, i32 %evl) ret %v } @@ -519,9 +487,7 @@ define @icmp_sle_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %va, %vb, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( %va, splat (i8 4), metadata !"sle", %m, i32 %evl) ret %v } @@ -531,9 +497,7 @@ define @icmp_sle_vi_swap_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i8( %vb, %va, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i8( splat (i8 4), %va, metadata !"sle", %m, i32 %evl) ret %v } @@ -665,9 +629,7 @@ define @icmp_eq_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"eq", %m, i32 %evl) ret %v } @@ -677,9 +639,7 @@ define @icmp_eq_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"eq", %m, i32 %evl) ret %v } @@ -723,9 +683,7 @@ define @icmp_ne_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"ne", %m, i32 %evl) ret %v } @@ -735,9 +693,7 @@ define @icmp_ne_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"ne", %m, i32 %evl) ret %v } @@ -781,9 +737,7 @@ define @icmp_ugt_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"ugt", %m, i32 %evl) ret %v } @@ -793,9 +747,7 @@ define @icmp_ugt_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"ugt", %m, i32 %evl) ret %v } @@ -841,9 +793,7 @@ define @icmp_uge_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"uge", %m, i32 %evl) ret %v } @@ -853,9 +803,7 @@ define @icmp_uge_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"uge", %m, i32 %evl) ret %v } @@ -899,9 +847,7 @@ define @icmp_ult_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"ult", %m, i32 %evl) ret %v } @@ -911,9 +857,7 @@ define @icmp_ult_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"ult", %m, i32 %evl) ret %v } @@ -957,9 +901,7 @@ define @icmp_sgt_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"sgt", %m, i32 %evl) ret %v } @@ -969,9 +911,7 @@ define @icmp_sgt_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"sgt", %m, i32 %evl) ret %v } @@ -1017,9 +957,7 @@ define @icmp_sge_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"sge", %m, i32 %evl) ret %v } @@ -1029,9 +967,7 @@ define @icmp_sge_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"sge", %m, i32 %evl) ret %v } @@ -1075,9 +1011,7 @@ define @icmp_slt_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"slt", %m, i32 %evl) ret %v } @@ -1087,9 +1021,7 @@ define @icmp_slt_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"slt", %m, i32 %evl) ret %v } @@ -1135,9 +1067,7 @@ define @icmp_sle_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %va, %vb, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( %va, splat (i8 4), metadata !"sle", %m, i32 %evl) ret %v } @@ -1147,9 +1077,7 @@ define @icmp_sle_vi_swap_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i8( %vb, %va, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i8( splat (i8 4), %va, metadata !"sle", %m, i32 %evl) ret %v } @@ -1312,9 +1240,7 @@ define @icmp_eq_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"eq", %m, i32 %evl) ret %v } @@ -1324,9 +1250,7 @@ define @icmp_eq_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"eq", %m, i32 %evl) ret %v } @@ -1370,9 +1294,7 @@ define @icmp_ne_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"ne", %m, i32 %evl) ret %v } @@ -1382,9 +1304,7 @@ define @icmp_ne_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"ne", %m, i32 %evl) ret %v } @@ -1428,9 +1348,7 @@ define @icmp_ugt_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"ugt", %m, i32 %evl) ret %v } @@ -1440,9 +1358,7 @@ define @icmp_ugt_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"ugt", %m, i32 %evl) ret %v } @@ -1488,9 +1404,7 @@ define @icmp_uge_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"uge", %m, i32 %evl) ret %v } @@ -1500,9 +1414,7 @@ define @icmp_uge_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"uge", %m, i32 %evl) ret %v } @@ -1546,9 +1458,7 @@ define @icmp_ult_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"ult", %m, i32 %evl) ret %v } @@ -1558,9 +1468,7 @@ define @icmp_ult_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"ult", %m, i32 %evl) ret %v } @@ -1604,9 +1512,7 @@ define @icmp_sgt_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"sgt", %m, i32 %evl) ret %v } @@ -1616,9 +1522,7 @@ define @icmp_sgt_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"sgt", %m, i32 %evl) ret %v } @@ -1664,9 +1568,7 @@ define @icmp_sge_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"sge", %m, i32 %evl) ret %v } @@ -1676,9 +1578,7 @@ define @icmp_sge_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"sge", %m, i32 %evl) ret %v } @@ -1722,9 +1622,7 @@ define @icmp_slt_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"slt", %m, i32 %evl) ret %v } @@ -1734,9 +1632,7 @@ define @icmp_slt_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"slt", %m, i32 %evl) ret %v } @@ -1782,9 +1678,7 @@ define @icmp_sle_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %va, %vb, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( %va, splat (i32 4), metadata !"sle", %m, i32 %evl) ret %v } @@ -1794,9 +1688,7 @@ define @icmp_sle_vi_swap_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i32( %vb, %va, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i32( splat (i32 4), %va, metadata !"sle", %m, i32 %evl) ret %v } @@ -1846,9 +1738,7 @@ define @icmp_eq_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"eq", %m, i32 %evl) ret %v } @@ -1859,9 +1749,7 @@ define @icmp_eq_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"eq", %m, i32 %evl) ret %v } @@ -1909,9 +1797,7 @@ define @icmp_ne_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"ne", %m, i32 %evl) ret %v } @@ -1922,9 +1808,7 @@ define @icmp_ne_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"ne", %m, i32 %evl) ret %v } @@ -1972,9 +1856,7 @@ define @icmp_ugt_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"ugt", %m, i32 %evl) ret %v } @@ -1985,9 +1867,7 @@ define @icmp_ugt_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"ugt", %m, i32 %evl) ret %v } @@ -2037,9 +1917,7 @@ define @icmp_uge_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"uge", %m, i32 %evl) ret %v } @@ -2050,9 +1928,7 @@ define @icmp_uge_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"uge", %m, i32 %evl) ret %v } @@ -2100,9 +1976,7 @@ define @icmp_ult_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"ult", %m, i32 %evl) ret %v } @@ -2113,9 +1987,7 @@ define @icmp_ult_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"ult", %m, i32 %evl) ret %v } @@ -2163,9 +2035,7 @@ define @icmp_sgt_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"sgt", %m, i32 %evl) ret %v } @@ -2176,9 +2046,7 @@ define @icmp_sgt_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"sgt", %m, i32 %evl) ret %v } @@ -2228,9 +2096,7 @@ define @icmp_sge_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"sge", %m, i32 %evl) ret %v } @@ -2241,9 +2107,7 @@ define @icmp_sge_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"sge", %m, i32 %evl) ret %v } @@ -2291,9 +2155,7 @@ define @icmp_slt_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"slt", %m, i32 %evl) ret %v } @@ -2304,9 +2166,7 @@ define @icmp_slt_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"slt", %m, i32 %evl) ret %v } @@ -2356,9 +2216,7 @@ define @icmp_sle_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %va, %vb, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( %va, splat (i32 4), metadata !"sle", %m, i32 %evl) ret %v } @@ -2369,9 +2227,7 @@ define @icmp_sle_vi_swap_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i32( %vb, %va, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i32( splat (i32 4), %va, metadata !"sle", %m, i32 %evl) ret %v } @@ -2572,9 +2428,7 @@ define @icmp_eq_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"eq", %m, i32 %evl) ret %v } @@ -2584,9 +2438,7 @@ define @icmp_eq_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"eq", %m, i32 %evl) ret %v } @@ -2658,9 +2510,7 @@ define @icmp_ne_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"ne", %m, i32 %evl) ret %v } @@ -2670,9 +2520,7 @@ define @icmp_ne_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"ne", %m, i32 %evl) ret %v } @@ -2744,9 +2592,7 @@ define @icmp_ugt_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"ugt", %m, i32 %evl) ret %v } @@ -2756,9 +2602,7 @@ define @icmp_ugt_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"ugt", %m, i32 %evl) ret %v } @@ -2832,9 +2676,7 @@ define @icmp_uge_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"uge", %m, i32 %evl) ret %v } @@ -2844,9 +2686,7 @@ define @icmp_uge_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"uge", %m, i32 %evl) ret %v } @@ -2918,9 +2758,7 @@ define @icmp_ult_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"ult", %m, i32 %evl) ret %v } @@ -2930,9 +2768,7 @@ define @icmp_ult_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"ult", %m, i32 %evl) ret %v } @@ -3004,9 +2840,7 @@ define @icmp_sgt_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"sgt", %m, i32 %evl) ret %v } @@ -3016,9 +2850,7 @@ define @icmp_sgt_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"sgt", %m, i32 %evl) ret %v } @@ -3092,9 +2924,7 @@ define @icmp_sge_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"sge", %m, i32 %evl) ret %v } @@ -3104,9 +2934,7 @@ define @icmp_sge_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"sge", %m, i32 %evl) ret %v } @@ -3178,9 +3006,7 @@ define @icmp_slt_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"slt", %m, i32 %evl) ret %v } @@ -3190,9 +3016,7 @@ define @icmp_slt_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"slt", %m, i32 %evl) ret %v } @@ -3266,9 +3090,7 @@ define @icmp_sle_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %va, %vb, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( %va, splat (i64 4), metadata !"sle", %m, i32 %evl) ret %v } @@ -3278,9 +3100,7 @@ define @icmp_sle_vi_swap_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv1i64( %vb, %va, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv1i64( splat (i64 4), %va, metadata !"sle", %m, i32 %evl) ret %v } @@ -3360,9 +3180,7 @@ define @icmp_eq_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"eq", %m, i32 %evl) ret %v } @@ -3373,9 +3191,7 @@ define @icmp_eq_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"eq", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"eq", %m, i32 %evl) ret %v } @@ -3453,9 +3269,7 @@ define @icmp_ne_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"ne", %m, i32 %evl) ret %v } @@ -3466,9 +3280,7 @@ define @icmp_ne_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"ne", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"ne", %m, i32 %evl) ret %v } @@ -3546,9 +3358,7 @@ define @icmp_ugt_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"ugt", %m, i32 %evl) ret %v } @@ -3559,9 +3369,7 @@ define @icmp_ugt_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"ugt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"ugt", %m, i32 %evl) ret %v } @@ -3641,9 +3449,7 @@ define @icmp_uge_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"uge", %m, i32 %evl) ret %v } @@ -3654,9 +3460,7 @@ define @icmp_uge_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"uge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"uge", %m, i32 %evl) ret %v } @@ -3734,9 +3538,7 @@ define @icmp_ult_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"ult", %m, i32 %evl) ret %v } @@ -3747,9 +3549,7 @@ define @icmp_ult_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"ult", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"ult", %m, i32 %evl) ret %v } @@ -3827,9 +3627,7 @@ define @icmp_sgt_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"sgt", %m, i32 %evl) ret %v } @@ -3840,9 +3638,7 @@ define @icmp_sgt_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"sgt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"sgt", %m, i32 %evl) ret %v } @@ -3922,9 +3718,7 @@ define @icmp_sge_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"sge", %m, i32 %evl) ret %v } @@ -3935,9 +3729,7 @@ define @icmp_sge_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"sge", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"sge", %m, i32 %evl) ret %v } @@ -4015,9 +3807,7 @@ define @icmp_slt_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"slt", %m, i32 %evl) ret %v } @@ -4028,9 +3818,7 @@ define @icmp_slt_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"slt", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"slt", %m, i32 %evl) ret %v } @@ -4110,9 +3898,7 @@ define @icmp_sle_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %va, %vb, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( %va, splat (i64 4), metadata !"sle", %m, i32 %evl) ret %v } @@ -4123,8 +3909,6 @@ define @icmp_sle_vi_swap_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.icmp.nxv8i64( %vb, %va, metadata !"sle", %m, i32 %evl) + %v = call @llvm.vp.icmp.nxv8i64( splat (i64 4), %va, metadata !"sle", %m, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll index 5f35a4e50a95..90ffeff9689e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll @@ -78,9 +78,7 @@ define @icmp_eq_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i8 0) ret %vc } @@ -90,9 +88,7 @@ define @icmp_eq_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i8 5) ret %vc } @@ -102,9 +98,7 @@ define @icmp_eq_iv_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %splat, %va + %vc = icmp eq splat (i8 5), %va ret %vc } @@ -148,9 +142,7 @@ define @icmp_ne_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ne %va, %splat + %vc = icmp ne %va, splat (i8 5) ret %vc } @@ -194,9 +186,7 @@ define @icmp_ugt_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ugt %va, %splat + %vc = icmp ugt %va, splat (i8 5) ret %vc } @@ -242,9 +232,7 @@ define @icmp_uge_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vmv.v.i v9, -16 ; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i8 -16) ret %vc } @@ -254,9 +242,7 @@ define @icmp_uge_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i8 15) ret %vc } @@ -266,9 +252,7 @@ define @icmp_uge_iv_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %splat, %va + %vc = icmp uge splat (i8 15), %va ret %vc } @@ -278,9 +262,7 @@ define @icmp_uge_vi_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i8 0) ret %vc } @@ -290,9 +272,7 @@ define @icmp_uge_vi_nxv8i8_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i8 1) ret %vc } @@ -302,9 +282,7 @@ define @icmp_uge_vi_nxv8i8_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i8 -15) ret %vc } @@ -314,9 +292,7 @@ define @icmp_uge_vi_nxv8i8_5( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i8 16) ret %vc } @@ -375,9 +351,7 @@ define @icmp_ult_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i8 -16) ret %vc } @@ -387,9 +361,7 @@ define @icmp_ult_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i8 -15) ret %vc } @@ -399,9 +371,7 @@ define @icmp_ult_iv_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %splat, %va + %vc = icmp ult splat (i8 -15), %va ret %vc } @@ -411,9 +381,7 @@ define @icmp_ult_vi_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i8 0) ret %vc } @@ -423,9 +391,7 @@ define @icmp_ult_vi_nxv8i8_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i8 1) ret %vc } @@ -435,9 +401,7 @@ define @icmp_ult_vi_nxv8i8_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i8 16) ret %vc } @@ -496,9 +460,7 @@ define @icmp_ule_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ule %va, %splat + %vc = icmp ule %va, splat (i8 5) ret %vc } @@ -542,9 +504,7 @@ define @icmp_sgt_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sgt %va, %splat + %vc = icmp sgt %va, splat (i8 5) ret %vc } @@ -590,9 +550,7 @@ define @icmp_sge_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vmv.v.i v9, -16 ; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i8 -16) ret %vc } @@ -602,9 +560,7 @@ define @icmp_sge_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i8 -15) ret %vc } @@ -614,9 +570,7 @@ define @icmp_sge_iv_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %splat, %va + %vc = icmp sge splat (i8 -15), %va ret %vc } @@ -626,9 +580,7 @@ define @icmp_sge_vi_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i8 0) ret %vc } @@ -638,9 +590,7 @@ define @icmp_sge_vi_nxv8i8_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i8 16) ret %vc } @@ -685,9 +635,7 @@ define @icmp_slt_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i8 -16) ret %vc } @@ -697,9 +645,7 @@ define @icmp_slt_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i8 -15) ret %vc } @@ -709,9 +655,7 @@ define @icmp_slt_iv_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %splat, %va + %vc = icmp slt splat (i8 -15), %va ret %vc } @@ -721,9 +665,7 @@ define @icmp_slt_vi_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i8 0) ret %vc } @@ -733,9 +675,7 @@ define @icmp_slt_vi_nxv8i8_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i8 16) ret %vc } @@ -780,9 +720,7 @@ define @icmp_sle_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sle %va, %splat + %vc = icmp sle %va, splat (i8 5) ret %vc } @@ -826,9 +764,7 @@ define @icmp_eq_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i16 0) ret %vc } @@ -838,9 +774,7 @@ define @icmp_eq_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i16 5) ret %vc } @@ -850,9 +784,7 @@ define @icmp_eq_iv_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %splat, %va + %vc = icmp eq splat (i16 5), %va ret %vc } @@ -896,9 +828,7 @@ define @icmp_ne_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ne %va, %splat + %vc = icmp ne %va, splat (i16 5) ret %vc } @@ -942,9 +872,7 @@ define @icmp_ugt_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ugt %va, %splat + %vc = icmp ugt %va, splat (i16 5) ret %vc } @@ -990,9 +918,7 @@ define @icmp_uge_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vmv.v.i v10, -16 ; CHECK-NEXT: vmsleu.vv v0, v10, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i16 -16) ret %vc } @@ -1002,9 +928,7 @@ define @icmp_uge_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i16 15) ret %vc } @@ -1014,9 +938,7 @@ define @icmp_uge_iv_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %splat, %va + %vc = icmp uge splat (i16 15), %va ret %vc } @@ -1026,9 +948,7 @@ define @icmp_uge_vi_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i16 0) ret %vc } @@ -1038,9 +958,7 @@ define @icmp_uge_vi_nxv8i16_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i16 1) ret %vc } @@ -1050,9 +968,7 @@ define @icmp_uge_vi_nxv8i16_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i16 -15) ret %vc } @@ -1062,9 +978,7 @@ define @icmp_uge_vi_nxv8i16_5( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i16 16) ret %vc } @@ -1109,9 +1023,7 @@ define @icmp_ult_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i16 -16) ret %vc } @@ -1121,9 +1033,7 @@ define @icmp_ult_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i16 -15) ret %vc } @@ -1133,9 +1043,7 @@ define @icmp_ult_iv_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %splat, %va + %vc = icmp ult splat (i16 -15), %va ret %vc } @@ -1145,9 +1053,7 @@ define @icmp_ult_vi_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i16 0) ret %vc } @@ -1157,9 +1063,7 @@ define @icmp_ult_vi_nxv8i16_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i16 1) ret %vc } @@ -1169,9 +1073,7 @@ define @icmp_ult_vi_nxv8i16_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i16 16) ret %vc } @@ -1216,9 +1118,7 @@ define @icmp_ule_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ule %va, %splat + %vc = icmp ule %va, splat (i16 5) ret %vc } @@ -1262,9 +1162,7 @@ define @icmp_sgt_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sgt %va, %splat + %vc = icmp sgt %va, splat (i16 5) ret %vc } @@ -1310,9 +1208,7 @@ define @icmp_sge_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vmv.v.i v10, -16 ; CHECK-NEXT: vmsle.vv v0, v10, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i16 -16) ret %vc } @@ -1322,9 +1218,7 @@ define @icmp_sge_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i16 -15) ret %vc } @@ -1334,9 +1228,7 @@ define @icmp_sge_iv_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %splat, %va + %vc = icmp sge splat (i16 -15), %va ret %vc } @@ -1346,9 +1238,7 @@ define @icmp_sge_vi_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i16 0) ret %vc } @@ -1358,9 +1248,7 @@ define @icmp_sge_vi_nxv8i16_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i16 16) ret %vc } @@ -1405,9 +1293,7 @@ define @icmp_slt_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i16 -16) ret %vc } @@ -1417,9 +1303,7 @@ define @icmp_slt_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i16 -15) ret %vc } @@ -1429,9 +1313,7 @@ define @icmp_slt_iv_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %splat, %va + %vc = icmp slt splat (i16 -15), %va ret %vc } @@ -1441,9 +1323,7 @@ define @icmp_slt_vi_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i16 0) ret %vc } @@ -1453,9 +1333,7 @@ define @icmp_slt_vi_nxv8i16_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i16 16) ret %vc } @@ -1500,9 +1378,7 @@ define @icmp_sle_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i16 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sle %va, %splat + %vc = icmp sle %va, splat (i16 5) ret %vc } @@ -1546,9 +1422,7 @@ define @icmp_eq_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i32 0) ret %vc } @@ -1558,9 +1432,7 @@ define @icmp_eq_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i32 5) ret %vc } @@ -1570,9 +1442,7 @@ define @icmp_eq_iv_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %splat, %va + %vc = icmp eq splat (i32 5), %va ret %vc } @@ -1616,9 +1486,7 @@ define @icmp_ne_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ne %va, %splat + %vc = icmp ne %va, splat (i32 5) ret %vc } @@ -1662,9 +1530,7 @@ define @icmp_ugt_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ugt %va, %splat + %vc = icmp ugt %va, splat (i32 5) ret %vc } @@ -1710,9 +1576,7 @@ define @icmp_uge_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vmv.v.i v12, -16 ; CHECK-NEXT: vmsleu.vv v0, v12, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i32 -16) ret %vc } @@ -1722,9 +1586,7 @@ define @icmp_uge_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i32 15) ret %vc } @@ -1734,9 +1596,7 @@ define @icmp_uge_iv_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %splat, %va + %vc = icmp uge splat (i32 15), %va ret %vc } @@ -1746,9 +1606,7 @@ define @icmp_uge_vi_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i32 0) ret %vc } @@ -1758,9 +1616,7 @@ define @icmp_uge_vi_nxv8i32_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i32 1) ret %vc } @@ -1770,9 +1626,7 @@ define @icmp_uge_vi_nxv8i32_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i32 -15) ret %vc } @@ -1782,9 +1636,7 @@ define @icmp_uge_vi_nxv8i32_5( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i32 16) ret %vc } @@ -1829,9 +1681,7 @@ define @icmp_ult_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i32 -16) ret %vc } @@ -1841,9 +1691,7 @@ define @icmp_ult_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i32 -15) ret %vc } @@ -1853,9 +1701,7 @@ define @icmp_ult_iv_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %splat, %va + %vc = icmp ult splat (i32 -15), %va ret %vc } @@ -1865,9 +1711,7 @@ define @icmp_ult_vi_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i32 0) ret %vc } @@ -1877,9 +1721,7 @@ define @icmp_ult_vi_nxv8i32_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i32 1) ret %vc } @@ -1889,9 +1731,7 @@ define @icmp_ult_vi_nxv8i32_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i32 16) ret %vc } @@ -1936,9 +1776,7 @@ define @icmp_ule_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ule %va, %splat + %vc = icmp ule %va, splat (i32 5) ret %vc } @@ -1982,9 +1820,7 @@ define @icmp_sgt_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sgt %va, %splat + %vc = icmp sgt %va, splat (i32 5) ret %vc } @@ -2030,9 +1866,7 @@ define @icmp_sge_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vmv.v.i v12, -16 ; CHECK-NEXT: vmsle.vv v0, v12, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i32 -16) ret %vc } @@ -2042,9 +1876,7 @@ define @icmp_sge_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i32 -15) ret %vc } @@ -2054,9 +1886,7 @@ define @icmp_sge_iv_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %splat, %va + %vc = icmp sge splat (i32 -15), %va ret %vc } @@ -2066,9 +1896,7 @@ define @icmp_sge_vi_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i32 0) ret %vc } @@ -2078,9 +1906,7 @@ define @icmp_sge_vi_nxv8i32_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i32 16) ret %vc } @@ -2125,9 +1951,7 @@ define @icmp_slt_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i32 -16) ret %vc } @@ -2137,9 +1961,7 @@ define @icmp_slt_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i32 -15) ret %vc } @@ -2149,9 +1971,7 @@ define @icmp_slt_iv_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %splat, %va + %vc = icmp slt splat (i32 -15), %va ret %vc } @@ -2161,9 +1981,7 @@ define @icmp_slt_vi_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i32 0) ret %vc } @@ -2173,9 +1991,7 @@ define @icmp_slt_vi_nxv8i32_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i32 16) ret %vc } @@ -2220,9 +2036,7 @@ define @icmp_sle_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i32 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sle %va, %splat + %vc = icmp sle %va, splat (i32 5) ret %vc } @@ -2292,9 +2106,7 @@ define @icmp_eq_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i64 0) ret %vc } @@ -2304,9 +2116,7 @@ define @icmp_eq_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %va, %splat + %vc = icmp eq %va, splat (i64 5) ret %vc } @@ -2316,9 +2126,7 @@ define @icmp_eq_iv_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp eq %splat, %va + %vc = icmp eq splat (i64 5), %va ret %vc } @@ -2388,9 +2196,7 @@ define @icmp_ne_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsne.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ne %va, %splat + %vc = icmp ne %va, splat (i64 5) ret %vc } @@ -2460,9 +2266,7 @@ define @icmp_ugt_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ugt %va, %splat + %vc = icmp ugt %va, splat (i64 5) ret %vc } @@ -2534,9 +2338,7 @@ define @icmp_uge_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vmv.v.i v16, -16 ; CHECK-NEXT: vmsleu.vv v0, v16, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i64 -16) ret %vc } @@ -2546,9 +2348,7 @@ define @icmp_uge_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 14 ; CHECK-NEXT: ret - %head = insertelement poison, i64 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i64 15) ret %vc } @@ -2558,9 +2358,7 @@ define @icmp_uge_iv_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %splat, %va + %vc = icmp uge splat (i64 15), %va ret %vc } @@ -2570,9 +2368,7 @@ define @icmp_uge_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i64 0) ret %vc } @@ -2582,9 +2378,7 @@ define @icmp_uge_vi_nxv8i64_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i64 1) ret %vc } @@ -2594,9 +2388,7 @@ define @icmp_uge_vi_nxv8i64_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i64 -15) ret %vc } @@ -2606,9 +2398,7 @@ define @icmp_uge_vi_nxv8i64_5( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp uge %va, %splat + %vc = icmp uge %va, splat (i64 16) ret %vc } @@ -2679,9 +2469,7 @@ define @icmp_ult_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsltu.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i64 -16) ret %vc } @@ -2691,9 +2479,7 @@ define @icmp_ult_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i64 -15) ret %vc } @@ -2703,9 +2489,7 @@ define @icmp_ult_iv_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgtu.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %splat, %va + %vc = icmp ult splat (i64 -15), %va ret %vc } @@ -2715,9 +2499,7 @@ define @icmp_ult_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i64 0) ret %vc } @@ -2727,9 +2509,7 @@ define @icmp_ult_vi_nxv8i64_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i64 1) ret %vc } @@ -2739,9 +2519,7 @@ define @icmp_ult_vi_nxv8i64_4( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ult %va, %splat + %vc = icmp ult %va, splat (i64 16) ret %vc } @@ -2812,9 +2590,7 @@ define @icmp_ule_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsleu.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp ule %va, %splat + %vc = icmp ule %va, splat (i64 5) ret %vc } @@ -2884,9 +2660,7 @@ define @icmp_sgt_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sgt %va, %splat + %vc = icmp sgt %va, splat (i64 5) ret %vc } @@ -2958,9 +2732,7 @@ define @icmp_sge_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vmv.v.i v16, -16 ; CHECK-NEXT: vmsle.vv v0, v16, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i64 -16) ret %vc } @@ -2970,9 +2742,7 @@ define @icmp_sge_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i64 -15) ret %vc } @@ -2982,9 +2752,7 @@ define @icmp_sge_iv_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %splat, %va + %vc = icmp sge splat (i64 -15), %va ret %vc } @@ -2994,9 +2762,7 @@ define @icmp_sge_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i64 0) ret %vc } @@ -3006,9 +2772,7 @@ define @icmp_sge_vi_nxv8i64_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sge %va, %splat + %vc = icmp sge %va, splat (i64 16) ret %vc } @@ -3079,9 +2843,7 @@ define @icmp_slt_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmslt.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i64 -16) ret %vc } @@ -3091,9 +2853,7 @@ define @icmp_slt_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -16 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i64 -15) ret %vc } @@ -3103,9 +2863,7 @@ define @icmp_slt_iv_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %splat, %va + %vc = icmp slt splat (i64 -15), %va ret %vc } @@ -3115,9 +2873,7 @@ define @icmp_slt_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i64 0) ret %vc } @@ -3127,9 +2883,7 @@ define @icmp_slt_vi_nxv8i64_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp slt %va, %splat + %vc = icmp slt %va, splat (i64 16) ret %vc } @@ -3200,9 +2954,7 @@ define @icmp_sle_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmsle.vi v0, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i64 5, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = icmp sle %va, %splat + %vc = icmp sle %va, splat (i64 5) ret %vc } @@ -3216,11 +2968,7 @@ define @icmp_eq_ii_nxv8i8() { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %heada = insertelement poison, i8 5, i32 0 - %splata = shufflevector %heada, poison, zeroinitializer - %headb = insertelement poison, i8 2, i32 0 - %splatb = shufflevector %headb, poison, zeroinitializer - %vc = icmp eq %splata, %splatb + %vc = icmp eq splat (i8 5), splat (i8 2) ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll index 5d09c39dfd6e..9046c861c336 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -1214,8 +1214,6 @@ vector.ph: ; preds = %entry %3 = shl i64 %2, 2 %n.mod.vf = urem i64 1024, %3 %n.vec = sub nsw i64 1024, %n.mod.vf - %broadcast.splatinsert = insertelement poison, i32 2, i32 0 - %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer %4 = call i64 @llvm.vscale.i64() %5 = shl i64 %4, 2 br label %vector.body @@ -1224,7 +1222,7 @@ vector.body: ; preds = %vector.body, %vecto %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ] %6 = getelementptr inbounds i32, ptr %a, i64 %index %wide.load = load , ptr %6, align 4 - %7 = ashr %wide.load, %broadcast.splat + %7 = ashr %wide.load, splat (i32 2) store %7, ptr %6, align 4 %index.next = add nuw i64 %index, %5 %8 = icmp eq i64 %index.next, %n.vec diff --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll index 8f02ca653581..eff8c26d4d06 100644 --- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll @@ -85,10 +85,8 @@ define @mul_stepvector_nxv8i8() { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i8 3, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv8i8() - %3 = mul %2, %1 + %3 = mul %2, splat (i8 3) ret %3 } @@ -100,10 +98,8 @@ define @shl_stepvector_nxv8i8() { ; CHECK-NEXT: vsll.vi v8, v8, 2 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i8 2, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv8i8() - %3 = shl %2, %1 + %3 = shl %2, splat (i8 2) ret %3 } @@ -250,10 +246,8 @@ define @mul_stepvector_nxv16i16() { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i16 3, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i16() - %3 = mul %2, %1 + %3 = mul %2, splat (i16 3) ret %3 } @@ -265,10 +259,8 @@ define @shl_stepvector_nxv16i16() { ; CHECK-NEXT: vsll.vi v8, v8, 2 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i16 2, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i16() - %3 = shl %2, %1 + %3 = shl %2, splat (i16 2) ret %3 } @@ -379,10 +371,8 @@ define @mul_stepvector_nxv16i32() { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i32 3, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i32() - %3 = mul %2, %1 + %3 = mul %2, splat (i32 3) ret %3 } @@ -394,10 +384,8 @@ define @shl_stepvector_nxv16i32() { ; CHECK-NEXT: vsll.vi v8, v8, 2 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i32 2, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i32() - %3 = shl %2, %1 + %3 = shl %2, splat (i32 2) ret %3 } @@ -484,10 +472,8 @@ define @mul_stepvector_nxv8i64() { ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i64 3, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv8i64() - %3 = mul %2, %1 + %3 = mul %2, splat (i64 3) ret %3 } @@ -520,10 +506,8 @@ define @mul_bigimm_stepvector_nxv8i64() { ; RV64-NEXT: vmul.vx v8, v8, a0 ; RV64-NEXT: ret entry: - %0 = insertelement poison, i64 33333333333, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv8i64() - %3 = mul %2, %1 + %3 = mul %2, splat (i64 33333333333) ret %3 } @@ -535,10 +519,8 @@ define @shl_stepvector_nxv8i64() { ; CHECK-NEXT: vsll.vi v8, v8, 2 ; CHECK-NEXT: ret entry: - %0 = insertelement poison, i64 2, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv8i64() - %3 = shl %2, %1 + %3 = shl %2, splat (i64 2) ret %3 } @@ -637,10 +619,8 @@ define @mul_stepvector_nxv16i64() { ; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: ret entry: - %0 = insertelement poison, i64 3, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i64() - %3 = mul %2, %1 + %3 = mul %2, splat (i64 3) ret %3 } @@ -692,10 +672,8 @@ define @mul_bigimm_stepvector_nxv16i64() { ; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: ret entry: - %0 = insertelement poison, i64 33333333333, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i64() - %3 = mul %2, %1 + %3 = mul %2, splat (i64 33333333333) ret %3 } @@ -727,10 +705,8 @@ define @shl_stepvector_nxv16i64() { ; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: ret entry: - %0 = insertelement poison, i64 2, i32 0 - %1 = shufflevector %0, poison, zeroinitializer %2 = call @llvm.experimental.stepvector.nxv16i64() - %3 = shl %2, %1 + %3 = shl %2, splat (i64 2) ret %3 } diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll index 6b584cfb22a5..7047c482c189 100644 --- a/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll @@ -206,9 +206,7 @@ define @straightline_offset_shl(ptr %p) { ; CHECK-NEXT: ret [[X]] ; %step = call @llvm.experimental.stepvector.nxv1i64() - %splat.insert = insertelement poison, i64 3, i64 0 - %splat = shufflevector %splat.insert, poison, zeroinitializer - %offset = shl %step, %splat + %offset = shl %step, splat (i64 3) %ptrs = getelementptr i32, ptr %p, %offset %x = call @llvm.masked.gather.nxv1i64.nxv1p0( %ptrs, diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll index a834630e7ebe..0e2105d5cba8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll @@ -60,9 +60,7 @@ define @strided_vpload_nxv1i8_i64_allones_mask(ptr %ptr, i64 s ; CHECK-RV64-NEXT: vsetvli zero, a2, e8, mf8, ta, ma ; CHECK-RV64-NEXT: vlse8.v v8, (a0), a1 ; CHECK-RV64-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv1i8.p0.i64(ptr %ptr, i64 %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv1i8.p0.i64(ptr %ptr, i64 %stride, splat (i1 true), i32 %evl) ret %load } @@ -84,9 +82,7 @@ define @strided_vpload_nxv1i8_allones_mask(ptr %ptr, i32 signe ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma ; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv1i8.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv1i8.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -142,9 +138,7 @@ define @strided_vpload_nxv8i8_allones_mask(ptr %ptr, i32 signe ; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma ; CHECK-NEXT: vlse8.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -178,9 +172,7 @@ define @strided_vpload_nxv2i16_allones_mask(ptr %ptr, i32 sig ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma ; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv2i16.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv2i16.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -270,9 +262,7 @@ define @strided_vpload_nxv4i32_allones_mask(ptr %ptr, i32 sig ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv4i32.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv4i32.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -316,9 +306,7 @@ define @strided_vpload_nxv1i64_allones_mask(ptr %ptr, i32 sig ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv1i64.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -388,9 +376,7 @@ define @strided_vpload_nxv2f16_allones_mask(ptr %ptr, i32 si ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma ; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv2f16.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv2f16.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -492,9 +478,7 @@ define @strided_vpload_nxv8f32_allones_mask(ptr %ptr, i32 s ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv8f32.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv8f32.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -550,9 +534,7 @@ define @strided_vpload_nxv4f64_allones_mask(ptr %ptr, i32 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.experimental.vp.strided.load.nxv4f64.p0.i32(ptr %ptr, i32 signext %stride, %b, i32 %evl) + %load = call @llvm.experimental.vp.strided.load.nxv4f64.p0.i32(ptr %ptr, i32 signext %stride, splat (i1 true), i32 %evl) ret %load } @@ -585,9 +567,7 @@ define @strided_vpload_nxv3f64_allones_mask(ptr %ptr, i32 ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma ; CHECK-NEXT: vlse64.v v8, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement poison, i1 true, i32 0 - %allones = shufflevector %one, poison, zeroinitializer - %v = call @llvm.experimental.vp.strided.load.nxv3f64.p0.i32(ptr %ptr, i32 %stride, %allones, i32 %evl) + %v = call @llvm.experimental.vp.strided.load.nxv3f64.p0.i32(ptr %ptr, i32 %stride, splat (i1 true), i32 %evl) ret %v } @@ -686,9 +666,7 @@ define @strided_load_nxv16f64_allones_mask(ptr %ptr, i64 ; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1 ; CHECK-RV64-NEXT: ret - %one = insertelement poison, i1 true, i32 0 - %allones = shufflevector %one, poison, zeroinitializer - %v = call @llvm.experimental.vp.strided.load.nxv16f64.p0.i64(ptr %ptr, i64 %stride, %allones, i32 %evl) + %v = call @llvm.experimental.vp.strided.load.nxv16f64.p0.i64(ptr %ptr, i64 %stride, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll index cf6ce89b9b5a..9378bb3d3ca6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll @@ -460,9 +460,7 @@ define void @strided_vpstore_nxv1i8_allones_mask( %val, ptr %pt ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma ; CHECK-NEXT: vsse8.v v8, (a0), a1 ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32( %val, ptr %ptr, i32 %strided, %b, i32 %evl) + call void @llvm.experimental.vp.strided.store.nxv1i8.p0.i32( %val, ptr %ptr, i32 %strided, splat (i1 true), i32 %evl) ret void } @@ -483,9 +481,7 @@ define void @strided_vpstore_nxv3f32_allones_mask( %v, ptr % ; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-NEXT: vsse32.v v8, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement poison, i1 true, i32 0 - %allones = shufflevector %one, poison, zeroinitializer - call void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32( %v, ptr %ptr, i32 %stride, %allones, i32 %evl) + call void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32( %v, ptr %ptr, i32 %stride, splat (i1 true), i32 %evl) ret void } @@ -539,9 +535,7 @@ define void @strided_store_nxv16f64_allones_mask( %v, ptr ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsse64.v v16, (a0), a1 ; CHECK-NEXT: ret - %one = insertelement poison, i1 true, i32 0 - %allones = shufflevector %one, poison, zeroinitializer - call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32( %v, ptr %ptr, i32 %stride, %allones, i32 %evl) + call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32( %v, ptr %ptr, i32 %stride, splat (i1 true), i32 %evl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll b/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll index bfbbb4b4067f..52c2cace185f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll @@ -34,12 +34,8 @@ define @test_urem_vec_even_divisor_eq0( %x) ; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret - %ins1 = insertelement poison, i16 6, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %urem = urem %x, %splat1 - %ins2 = insertelement poison, i16 0, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %cmp = icmp ne %urem, %splat2 + %urem = urem %x, splat (i16 6) + %cmp = icmp ne %urem, splat (i16 0) %ext = sext %cmp to ret %ext } @@ -70,12 +66,8 @@ define @test_urem_vec_odd_divisor_eq0( %x) ; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret - %ins1 = insertelement poison, i16 5, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %urem = urem %x, %splat1 - %ins2 = insertelement poison, i16 0, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %cmp = icmp ne %urem, %splat2 + %urem = urem %x, splat (i16 5) + %cmp = icmp ne %urem, splat (i16 0) %ext = sext %cmp to ret %ext } @@ -116,12 +108,8 @@ define @test_urem_vec_even_divisor_eq1( %x) ; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret - %ins1 = insertelement poison, i16 6, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %urem = urem %x, %splat1 - %ins2 = insertelement poison, i16 1, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %cmp = icmp ne %urem, %splat2 + %urem = urem %x, splat (i16 6) + %cmp = icmp ne %urem, splat (i16 1) %ext = sext %cmp to ret %ext } @@ -156,12 +144,8 @@ define @test_urem_vec_odd_divisor_eq1( %x) ; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmerge.vim v8, v8, -1, v0 ; RV64-NEXT: ret - %ins1 = insertelement poison, i16 5, i32 0 - %splat1 = shufflevector %ins1, poison, zeroinitializer - %urem = urem %x, %splat1 - %ins2 = insertelement poison, i16 1, i32 0 - %splat2 = shufflevector %ins2, poison, zeroinitializer - %cmp = icmp ne %urem, %splat2 + %urem = urem %x, splat (i16 5) + %cmp = icmp ne %urem, splat (i16 1) %ext = sext %cmp to ret %ext } diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll index 1cf57371455c..5b14014a252f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll @@ -12,9 +12,7 @@ define @vaaddu_vv_nxv8i8_floor( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i16 1) %ret = trunc %div to ret %ret } @@ -31,9 +29,7 @@ define @vaaddu_vx_nxv8i8_floor( %x, i8 %y) { %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i16 1) %ret = trunc %div to ret %ret } @@ -48,9 +44,7 @@ define @vaaddu_vv_nxv8i8_floor_sexti16( %x, < %xzv = sext %x to %yzv = sext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i16 1) %ret = trunc %div to ret %ret } @@ -65,9 +59,7 @@ define @vaaddu_vv_nxv8i8_floor_zexti32( %x, < %xzv = zext %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i32 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i32 1) %ret = trunc %div to ret %ret } @@ -82,9 +74,7 @@ define @vaaddu_vv_nxv8i8_floor_lshr2( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 2, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i16 2) %ret = trunc %div to ret %ret } @@ -99,9 +89,7 @@ define @vaaddu_vv_nxv8i16_floor( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i32 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i32 1) %ret = trunc %div to ret %ret } @@ -118,9 +106,7 @@ define @vaaddu_vx_nxv8i16_floor( %x, i16 %y %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i32 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i32 1) %ret = trunc %div to ret %ret } @@ -135,9 +121,7 @@ define @vaaddu_vv_nxv8i32_floor( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i64 1, i64 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i64 1) %ret = trunc %div to ret %ret } @@ -154,9 +138,7 @@ define @vaaddu_vx_nxv8i32_floor( %x, i32 %y %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i64 1, i64 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i64 1) %ret = trunc %div to ret %ret } @@ -171,9 +153,7 @@ define @vaaddu_vv_nxv8i64_floor( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i128 1, i128 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i128 1) %ret = trunc %div to ret %ret } @@ -204,9 +184,7 @@ define @vaaddu_vx_nxv8i64_floor( %x, i64 %y %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i128 1, i128 0 - %splat = shufflevector %one, poison, zeroinitializer - %div = lshr %add, %splat + %div = lshr %add, splat (i128 1) %ret = trunc %div to ret %ret } @@ -221,10 +199,8 @@ define @vaaddu_vv_nxv8i8_ceil( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i16 1) + %div = lshr %add1, splat (i16 1) %ret = trunc %div to ret %ret } @@ -241,10 +217,8 @@ define @vaaddu_vx_nxv8i8_ceil( %x, i8 %y) { %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i16 1) + %div = lshr %add1, splat (i16 1) %ret = trunc %div to ret %ret } @@ -262,10 +236,8 @@ define @vaaddu_vv_nxv8i8_ceil_sexti16( %x, %x to %yzv = sext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i16 1) + %div = lshr %add1, splat (i16 1) %ret = trunc %div to ret %ret } @@ -280,10 +252,8 @@ define @vaaddu_vv_nxv8i8_ceil_zexti32( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i32 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i32 1) + %div = lshr %add1, splat (i32 1) %ret = trunc %div to ret %ret } @@ -301,10 +271,8 @@ define @vaaddu_vv_nxv8i8_ceil_lshr2( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 2, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i16 2) + %div = lshr %add1, splat (i16 2) %ret = trunc %div to ret %ret } @@ -322,12 +290,8 @@ define @vaaddu_vv_nxv8i8_ceil_add2( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i16 2, i32 0 - %splat1 = shufflevector %one, poison, zeroinitializer - %two = insertelement poison, i16 2, i32 0 - %splat2 = shufflevector %two, poison, zeroinitializer - %add2 = add nuw nsw %add, %splat2 - %div = lshr %add2, %splat1 + %add2 = add nuw nsw %add, splat (i16 2) + %div = lshr %add2, splat (i16 2) %ret = trunc %div to ret %ret } @@ -342,10 +306,8 @@ define @vaaddu_vv_nxv8i16_ceil( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i32 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i32 1) + %div = lshr %add1, splat (i32 1) %ret = trunc %div to ret %ret } @@ -362,10 +324,8 @@ define @vaaddu_vx_nxv8i16_ceil( %x, i16 %y) %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i32 1, i32 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i32 1) + %div = lshr %add1, splat (i32 1) %ret = trunc %div to ret %ret } @@ -380,10 +340,8 @@ define @vaaddu_vv_nxv8i32_ceil( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i64 1, i64 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i64 1) + %div = lshr %add1, splat (i64 1) %ret = trunc %div to ret %ret } @@ -400,10 +358,8 @@ define @vaaddu_vx_nxv8i32_ceil( %x, i32 %y) %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i64 1, i64 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i64 1) + %div = lshr %add1, splat (i64 1) %ret = trunc %div to ret %ret } @@ -418,10 +374,8 @@ define @vaaddu_vv_nxv8i64_ceil( %x, %x to %yzv = zext %y to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i128 1, i128 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i128 1) + %div = lshr %add1, splat (i128 1) %ret = trunc %div to ret %ret } @@ -452,10 +406,8 @@ define @vaaddu_vx_nxv8i64_ceil( %x, i64 %y) %ysplat = shufflevector %yhead, poison, zeroinitializer %yzv = zext %ysplat to %add = add nuw nsw %xzv, %yzv - %one = insertelement poison, i128 1, i128 0 - %splat = shufflevector %one, poison, zeroinitializer - %add1 = add nuw nsw %add, %splat - %div = lshr %add1, %splat + %add1 = add nuw nsw %add, splat (i128 1) + %div = lshr %add1, splat (i128 1) %ret = trunc %div to ret %ret } diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll index 264cf2e8df09..27fceb0112ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll @@ -20,9 +20,7 @@ define @vadd_vx_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -32,9 +30,7 @@ define @vadd_vx_nxv1i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -45,11 +41,7 @@ define @vadd_ii_nxv1i8_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 5 ; CHECK-NEXT: ret - %heada = insertelement poison, i8 2, i32 0 - %splata = shufflevector %heada, poison, zeroinitializer - %headb = insertelement poison, i8 3, i32 0 - %splatb = shufflevector %headb, poison, zeroinitializer - %vc = add %splata, %splatb + %vc = add splat (i8 2), splat (i8 3) ret %vc } @@ -71,9 +63,7 @@ define @vadd_vx_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -83,9 +73,7 @@ define @vadd_vx_nxv2i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -107,9 +95,7 @@ define @vadd_vx_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -119,9 +105,7 @@ define @vadd_vx_nxv4i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -143,9 +127,7 @@ define @vadd_vx_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -155,9 +137,7 @@ define @vadd_vx_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -179,9 +159,7 @@ define @vadd_vx_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -191,9 +169,7 @@ define @vadd_vx_nxv16i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -215,9 +191,7 @@ define @vadd_vx_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -227,9 +201,7 @@ define @vadd_vx_nxv32i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -251,9 +223,7 @@ define @vadd_vx_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 -1) ret %vc } @@ -263,9 +233,7 @@ define @vadd_vx_nxv64i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i8 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i8 2) ret %vc } @@ -287,9 +255,7 @@ define @vadd_vx_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 -1) ret %vc } @@ -299,9 +265,7 @@ define @vadd_vx_nxv1i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i16 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 2) ret %vc } @@ -323,9 +287,7 @@ define @vadd_vx_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 -1) ret %vc } @@ -335,9 +297,7 @@ define @vadd_vx_nxv2i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i16 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 2) ret %vc } @@ -359,9 +319,7 @@ define @vadd_vx_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 -1) ret %vc } @@ -371,9 +329,7 @@ define @vadd_vx_nxv4i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i16 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 2) ret %vc } @@ -395,9 +351,7 @@ define @vadd_vx_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 -1) ret %vc } @@ -407,9 +361,7 @@ define @vadd_vx_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i16 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 2) ret %vc } @@ -431,9 +383,7 @@ define @vadd_vx_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 -1) ret %vc } @@ -443,9 +393,7 @@ define @vadd_vx_nxv16i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i16 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 2) ret %vc } @@ -467,9 +415,7 @@ define @vadd_vx_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 -1) ret %vc } @@ -479,9 +425,7 @@ define @vadd_vx_nxv32i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i16 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i16 2) ret %vc } @@ -503,9 +447,7 @@ define @vadd_vx_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 -1) ret %vc } @@ -515,9 +457,7 @@ define @vadd_vx_nxv1i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i32 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 2) ret %vc } @@ -539,9 +479,7 @@ define @vadd_vx_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 -1) ret %vc } @@ -551,9 +489,7 @@ define @vadd_vx_nxv2i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i32 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 2) ret %vc } @@ -575,9 +511,7 @@ define @vadd_vx_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 -1) ret %vc } @@ -587,9 +521,7 @@ define @vadd_vx_nxv4i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i32 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 2) ret %vc } @@ -611,9 +543,7 @@ define @vadd_vx_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 -1) ret %vc } @@ -623,9 +553,7 @@ define @vadd_vx_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i32 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 2) ret %vc } @@ -647,9 +575,7 @@ define @vadd_vx_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 -1) ret %vc } @@ -659,9 +585,7 @@ define @vadd_vx_nxv16i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i32 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i32 2) ret %vc } @@ -696,9 +620,7 @@ define @vadd_vx_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 -1) ret %vc } @@ -708,9 +630,7 @@ define @vadd_vx_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 2) ret %vc } @@ -745,9 +665,7 @@ define @vadd_vx_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 -1) ret %vc } @@ -757,9 +675,7 @@ define @vadd_vx_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 2) ret %vc } @@ -794,9 +710,7 @@ define @vadd_vx_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 -1) ret %vc } @@ -806,9 +720,7 @@ define @vadd_vx_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 2) ret %vc } @@ -843,9 +755,7 @@ define @vadd_vx_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 -1) ret %vc } @@ -855,9 +765,7 @@ define @vadd_vx_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = add %va, %splat + %vc = add %va, splat (i64 2) ret %vc } @@ -922,9 +830,7 @@ define @vadd_vi_mask_nxv8i32( %va, poison, i32 7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 7), zeroinitializer %vc = add %va, %vs ret %vc } @@ -937,9 +843,7 @@ define @vadd_vv_mask_negative0_nxv8i32( %va ; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0 ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %one = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %one + %vs = select %mask, %vb, splat (i32 1) %vc = add %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll index 8b65c1a70206..4b5e737d22eb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll @@ -36,9 +36,7 @@ define @vadd_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -74,9 +72,7 @@ define @vadd_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -86,9 +82,7 @@ define @vadd_vi_nxv1i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -98,11 +92,7 @@ define @vadd_vi_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -124,9 +114,7 @@ define @vadd_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +138,7 @@ define @vadd_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -162,9 +148,7 @@ define @vadd_vi_nxv2i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -174,11 +158,7 @@ define @vadd_vi_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -200,9 +180,7 @@ define @vadd_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -226,9 +204,7 @@ define @vadd_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -238,9 +214,7 @@ define @vadd_vi_nxv3i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv3i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -250,11 +224,7 @@ define @vadd_vi_nxv3i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv3i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -276,9 +246,7 @@ define @vadd_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -302,9 +270,7 @@ define @vadd_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -314,9 +280,7 @@ define @vadd_vi_nxv4i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -326,11 +290,7 @@ define @vadd_vi_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -352,9 +312,7 @@ define @vadd_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -378,9 +336,7 @@ define @vadd_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -390,9 +346,7 @@ define @vadd_vi_nxv8i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -402,11 +356,7 @@ define @vadd_vi_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -428,9 +378,7 @@ define @vadd_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -454,9 +402,7 @@ define @vadd_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -466,9 +412,7 @@ define @vadd_vi_nxv16i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -478,11 +422,7 @@ define @vadd_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -504,9 +444,7 @@ define @vadd_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -530,9 +468,7 @@ define @vadd_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -542,9 +478,7 @@ define @vadd_vi_nxv32i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -554,11 +488,7 @@ define @vadd_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -580,9 +510,7 @@ define @vadd_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -606,9 +534,7 @@ define @vadd_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -618,9 +544,7 @@ define @vadd_vi_nxv64i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv64i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -630,11 +554,7 @@ define @vadd_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv64i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -664,9 +584,7 @@ define @vadd_vi_nxv128i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv128i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -688,11 +606,7 @@ define @vadd_vi_nxv128i8_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv128i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -714,9 +628,7 @@ define @vadd_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -740,9 +652,7 @@ define @vadd_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -752,9 +662,7 @@ define @vadd_vi_nxv1i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -764,11 +672,7 @@ define @vadd_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -790,9 +694,7 @@ define @vadd_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -816,9 +718,7 @@ define @vadd_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -828,9 +728,7 @@ define @vadd_vi_nxv2i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -840,11 +738,7 @@ define @vadd_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -866,9 +760,7 @@ define @vadd_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -892,9 +784,7 @@ define @vadd_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -904,9 +794,7 @@ define @vadd_vi_nxv4i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -916,11 +804,7 @@ define @vadd_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -942,9 +826,7 @@ define @vadd_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -968,9 +850,7 @@ define @vadd_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -980,9 +860,7 @@ define @vadd_vi_nxv8i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -992,11 +870,7 @@ define @vadd_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1018,9 +892,7 @@ define @vadd_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1044,9 +916,7 @@ define @vadd_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1056,9 +926,7 @@ define @vadd_vi_nxv16i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1068,11 +936,7 @@ define @vadd_vi_nxv16i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1094,9 +958,7 @@ define @vadd_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1120,9 +982,7 @@ define @vadd_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1132,9 +992,7 @@ define @vadd_vi_nxv32i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1144,11 +1002,7 @@ define @vadd_vi_nxv32i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1170,9 +1024,7 @@ define @vadd_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1196,9 +1048,7 @@ define @vadd_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1208,9 +1058,7 @@ define @vadd_vi_nxv1i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1220,11 +1068,7 @@ define @vadd_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1246,9 +1090,7 @@ define @vadd_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1272,9 +1114,7 @@ define @vadd_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1284,9 +1124,7 @@ define @vadd_vi_nxv2i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1296,11 +1134,7 @@ define @vadd_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1322,9 +1156,7 @@ define @vadd_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1348,9 +1180,7 @@ define @vadd_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1360,9 +1190,7 @@ define @vadd_vi_nxv4i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1372,11 +1200,7 @@ define @vadd_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1398,9 +1222,7 @@ define @vadd_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1424,9 +1246,7 @@ define @vadd_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1436,9 +1256,7 @@ define @vadd_vi_nxv8i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1448,11 +1266,7 @@ define @vadd_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1474,9 +1288,7 @@ define @vadd_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1500,9 +1312,7 @@ define @vadd_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1512,9 +1322,7 @@ define @vadd_vi_nxv16i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1524,11 +1332,7 @@ define @vadd_vi_nxv16i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv16i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1559,9 +1363,7 @@ define @vadd_vi_nxv32i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1583,11 +1385,7 @@ define @vadd_vi_nxv32i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv32i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1621,11 +1419,9 @@ define @vadd_vi_nxv32i32_evl_nx8( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer %evl = call i32 @llvm.vscale.i32() %evl0 = mul i32 %evl, 8 - %v = call @llvm.vp.add.nxv32i32( %va, %vb, %m, i32 %evl0) + %v = call @llvm.vp.add.nxv32i32( %va, splat (i32 -1), %m, i32 %evl0) ret %v } @@ -1659,11 +1455,9 @@ define @vadd_vi_nxv32i32_evl_nx16( %va, < ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer %evl = call i32 @llvm.vscale.i32() %evl0 = mul i32 %evl, 16 - %v = call @llvm.vp.add.nxv32i32( %va, %vb, %m, i32 %evl0) + %v = call @llvm.vp.add.nxv32i32( %va, splat (i32 -1), %m, i32 %evl0) ret %v } @@ -1685,9 +1479,7 @@ define @vadd_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1739,9 +1531,7 @@ define @vadd_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1751,9 +1541,7 @@ define @vadd_vi_nxv1i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1763,11 +1551,7 @@ define @vadd_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv1i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1789,9 +1573,7 @@ define @vadd_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1843,9 +1625,7 @@ define @vadd_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1855,9 +1635,7 @@ define @vadd_vi_nxv2i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1867,11 +1645,7 @@ define @vadd_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv2i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1893,9 +1667,7 @@ define @vadd_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1947,9 +1719,7 @@ define @vadd_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1959,9 +1729,7 @@ define @vadd_vi_nxv4i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1971,11 +1739,7 @@ define @vadd_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv4i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1997,9 +1761,7 @@ define @vadd_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2051,9 +1813,7 @@ define @vadd_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2063,9 +1823,7 @@ define @vadd_vi_nxv8i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2075,10 +1833,6 @@ define @vadd_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.add.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.add.nxv8i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll index f10954bb02df..40d0d9aa9d1d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll @@ -30,9 +30,7 @@ define @vand_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -42,9 +40,7 @@ define @vand_vi_nxv1i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -55,9 +51,7 @@ define @vand_vi_nxv1i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -89,9 +83,7 @@ define @vand_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -101,9 +93,7 @@ define @vand_vi_nxv2i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -114,9 +104,7 @@ define @vand_vi_nxv2i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -148,9 +136,7 @@ define @vand_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -160,9 +146,7 @@ define @vand_vi_nxv4i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -173,9 +157,7 @@ define @vand_vi_nxv4i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -207,9 +189,7 @@ define @vand_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -219,9 +199,7 @@ define @vand_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -232,9 +210,7 @@ define @vand_vi_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -266,9 +242,7 @@ define @vand_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -278,9 +252,7 @@ define @vand_vi_nxv16i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -291,9 +263,7 @@ define @vand_vi_nxv16i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -325,9 +295,7 @@ define @vand_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -337,9 +305,7 @@ define @vand_vi_nxv32i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -350,9 +316,7 @@ define @vand_vi_nxv32i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -384,9 +348,7 @@ define @vand_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 -10) ret %vc } @@ -396,9 +358,7 @@ define @vand_vi_nxv64i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 8) ret %vc } @@ -409,9 +369,7 @@ define @vand_vi_nxv64i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i8 16) ret %vc } @@ -443,9 +401,7 @@ define @vand_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 -10) ret %vc } @@ -455,9 +411,7 @@ define @vand_vi_nxv1i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 8) ret %vc } @@ -468,9 +422,7 @@ define @vand_vi_nxv1i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 16) ret %vc } @@ -502,9 +454,7 @@ define @vand_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 -10) ret %vc } @@ -514,9 +464,7 @@ define @vand_vi_nxv2i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 8) ret %vc } @@ -527,9 +475,7 @@ define @vand_vi_nxv2i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 16) ret %vc } @@ -561,9 +507,7 @@ define @vand_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 -10) ret %vc } @@ -573,9 +517,7 @@ define @vand_vi_nxv4i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 8) ret %vc } @@ -586,9 +528,7 @@ define @vand_vi_nxv4i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 16) ret %vc } @@ -620,9 +560,7 @@ define @vand_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 -10) ret %vc } @@ -632,9 +570,7 @@ define @vand_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 8) ret %vc } @@ -645,9 +581,7 @@ define @vand_vi_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 16) ret %vc } @@ -679,9 +613,7 @@ define @vand_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 -10) ret %vc } @@ -691,9 +623,7 @@ define @vand_vi_nxv16i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 8) ret %vc } @@ -704,9 +634,7 @@ define @vand_vi_nxv16i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 16) ret %vc } @@ -738,9 +666,7 @@ define @vand_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 -10) ret %vc } @@ -750,9 +676,7 @@ define @vand_vi_nxv32i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 8) ret %vc } @@ -763,9 +687,7 @@ define @vand_vi_nxv32i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i16 16) ret %vc } @@ -797,9 +719,7 @@ define @vand_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 -10) ret %vc } @@ -809,9 +729,7 @@ define @vand_vi_nxv1i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 8) ret %vc } @@ -822,9 +740,7 @@ define @vand_vi_nxv1i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 16) ret %vc } @@ -856,9 +772,7 @@ define @vand_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 -10) ret %vc } @@ -868,9 +782,7 @@ define @vand_vi_nxv2i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 8) ret %vc } @@ -881,9 +793,7 @@ define @vand_vi_nxv2i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 16) ret %vc } @@ -915,9 +825,7 @@ define @vand_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 -10) ret %vc } @@ -927,9 +835,7 @@ define @vand_vi_nxv4i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 8) ret %vc } @@ -940,9 +846,7 @@ define @vand_vi_nxv4i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 16) ret %vc } @@ -974,9 +878,7 @@ define @vand_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 -10) ret %vc } @@ -986,9 +888,7 @@ define @vand_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 8) ret %vc } @@ -999,9 +899,7 @@ define @vand_vi_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 16) ret %vc } @@ -1033,9 +931,7 @@ define @vand_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 -10) ret %vc } @@ -1045,9 +941,7 @@ define @vand_vi_nxv16i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 8) ret %vc } @@ -1058,9 +952,7 @@ define @vand_vi_nxv16i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i32 16) ret %vc } @@ -1105,9 +997,7 @@ define @vand_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 -10) ret %vc } @@ -1117,9 +1007,7 @@ define @vand_vi_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 8) ret %vc } @@ -1130,9 +1018,7 @@ define @vand_vi_nxv1i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 16) ret %vc } @@ -1177,9 +1063,7 @@ define @vand_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 -10) ret %vc } @@ -1189,9 +1073,7 @@ define @vand_vi_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 8) ret %vc } @@ -1202,9 +1084,7 @@ define @vand_vi_nxv2i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 16) ret %vc } @@ -1249,9 +1129,7 @@ define @vand_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 -10) ret %vc } @@ -1261,9 +1139,7 @@ define @vand_vi_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 8) ret %vc } @@ -1274,9 +1150,7 @@ define @vand_vi_nxv4i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 16) ret %vc } @@ -1321,9 +1195,7 @@ define @vand_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, -10 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -10, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 -10) ret %vc } @@ -1333,9 +1205,7 @@ define @vand_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 8) ret %vc } @@ -1346,9 +1216,7 @@ define @vand_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = and %va, %splat + %vc = and %va, splat (i64 16) ret %vc } @@ -1389,9 +1257,7 @@ define @vand_vv_mask_nxv8i32( %va, poison, i32 -1, i32 0 - %allones = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %allones + %vs = select %mask, %vb, splat (i32 -1) %vc = and %va, %vs ret %vc } @@ -1402,11 +1268,9 @@ define @vand_vx_mask_nxv8i32( %va, i32 sign ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -1, i32 0 - %allones = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %allones + %vs = select %mask, %splat, splat (i32 -1) %vc = and %va, %vs ret %vc } @@ -1417,11 +1281,7 @@ define @vand_vi_mask_nxv8i32( %va, poison, i32 -1, i32 0 - %allones = shufflevector %head1, poison, zeroinitializer - %head2 = insertelement poison, i32 7, i32 0 - %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %allones + %vs = select %mask, splat (i32 7), splat (i32 -1) %vc = and %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll index 032c3a014eca..7b4a68d5867f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll @@ -36,9 +36,7 @@ define @vand_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -62,9 +60,7 @@ define @vand_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -74,9 +70,7 @@ define @vand_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -86,11 +80,7 @@ define @vand_vi_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -112,9 +102,7 @@ define @vand_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +126,7 @@ define @vand_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +136,7 @@ define @vand_vi_nxv2i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -162,11 +146,7 @@ define @vand_vi_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -188,9 +168,7 @@ define @vand_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -214,9 +192,7 @@ define @vand_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -226,9 +202,7 @@ define @vand_vi_nxv4i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -238,11 +212,7 @@ define @vand_vi_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -264,9 +234,7 @@ define @vand_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -290,9 +258,7 @@ define @vand_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -302,9 +268,7 @@ define @vand_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -314,11 +278,7 @@ define @vand_vi_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -340,9 +300,7 @@ define @vand_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -366,9 +324,7 @@ define @vand_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -378,9 +334,7 @@ define @vand_vi_nxv16i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -390,11 +344,7 @@ define @vand_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -416,9 +366,7 @@ define @vand_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -442,9 +390,7 @@ define @vand_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -454,9 +400,7 @@ define @vand_vi_nxv32i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -466,11 +410,7 @@ define @vand_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -492,9 +432,7 @@ define @vand_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -518,9 +456,7 @@ define @vand_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -530,9 +466,7 @@ define @vand_vi_nxv64i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv64i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -542,11 +476,7 @@ define @vand_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv64i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -568,9 +498,7 @@ define @vand_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -594,9 +522,7 @@ define @vand_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -606,9 +532,7 @@ define @vand_vi_nxv1i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -618,11 +542,7 @@ define @vand_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -644,9 +564,7 @@ define @vand_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -670,9 +588,7 @@ define @vand_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -682,9 +598,7 @@ define @vand_vi_nxv2i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -694,11 +608,7 @@ define @vand_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -720,9 +630,7 @@ define @vand_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -746,9 +654,7 @@ define @vand_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -758,9 +664,7 @@ define @vand_vi_nxv4i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -770,11 +674,7 @@ define @vand_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -796,9 +696,7 @@ define @vand_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -822,9 +720,7 @@ define @vand_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -834,9 +730,7 @@ define @vand_vi_nxv8i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -846,11 +740,7 @@ define @vand_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -872,9 +762,7 @@ define @vand_vv_nxv14i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv14i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv14i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -898,9 +786,7 @@ define @vand_vx_nxv14i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv14i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv14i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -910,9 +796,7 @@ define @vand_vi_nxv14i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv14i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv14i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -922,11 +806,7 @@ define @vand_vi_nxv14i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv14i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv14i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -948,9 +828,7 @@ define @vand_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -974,9 +852,7 @@ define @vand_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -986,9 +862,7 @@ define @vand_vi_nxv16i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -998,11 +872,7 @@ define @vand_vi_nxv16i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -1024,9 +894,7 @@ define @vand_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1062,9 +930,7 @@ define @vand_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1074,9 +940,7 @@ define @vand_vi_nxv32i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -1086,11 +950,7 @@ define @vand_vi_nxv32i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv32i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -1112,9 +972,7 @@ define @vand_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1138,9 +996,7 @@ define @vand_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1150,9 +1006,7 @@ define @vand_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1162,11 +1016,7 @@ define @vand_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1188,9 +1038,7 @@ define @vand_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1214,9 +1062,7 @@ define @vand_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1226,9 +1072,7 @@ define @vand_vi_nxv2i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1238,11 +1082,7 @@ define @vand_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1264,9 +1104,7 @@ define @vand_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1290,9 +1128,7 @@ define @vand_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1302,9 +1138,7 @@ define @vand_vi_nxv4i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1314,11 +1148,7 @@ define @vand_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1340,9 +1170,7 @@ define @vand_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1366,9 +1194,7 @@ define @vand_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1378,9 +1204,7 @@ define @vand_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1390,11 +1214,7 @@ define @vand_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1416,9 +1236,7 @@ define @vand_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vand.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1442,9 +1260,7 @@ define @vand_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1454,9 +1270,7 @@ define @vand_vi_nxv16i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1466,11 +1280,7 @@ define @vand_vi_nxv16i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv16i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1492,9 +1302,7 @@ define @vand_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1546,9 +1354,7 @@ define @vand_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1558,9 +1364,7 @@ define @vand_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1570,11 +1374,7 @@ define @vand_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv1i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } @@ -1596,9 +1396,7 @@ define @vand_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1650,9 +1448,7 @@ define @vand_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1662,9 +1458,7 @@ define @vand_vi_nxv2i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1674,11 +1468,7 @@ define @vand_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv2i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } @@ -1700,9 +1490,7 @@ define @vand_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1754,9 +1542,7 @@ define @vand_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1766,9 +1552,7 @@ define @vand_vi_nxv4i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1778,11 +1562,7 @@ define @vand_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv4i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } @@ -1804,9 +1584,7 @@ define @vand_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1858,9 +1636,7 @@ define @vand_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1870,9 +1646,7 @@ define @vand_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1882,10 +1656,6 @@ define @vand_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.and.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.and.nxv8i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll index f9c53c93472a..f25a3f937f1b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll @@ -17,9 +17,7 @@ define @vandn_vv_nxv1i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -37,9 +35,7 @@ define @vandn_vv_swapped_nxv1i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -97,9 +93,7 @@ define @vandn_vv_nxv2i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -117,9 +111,7 @@ define @vandn_vv_swapped_nxv2i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -177,9 +169,7 @@ define @vandn_vv_nxv4i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -197,9 +187,7 @@ define @vandn_vv_swapped_nxv4i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -257,9 +245,7 @@ define @vandn_vv_nxv8i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -277,9 +263,7 @@ define @vandn_vv_swapped_nxv8i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -337,9 +321,7 @@ define @vandn_vv_nxv16i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -357,9 +339,7 @@ define @vandn_vv_swapped_nxv16i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -417,9 +397,7 @@ define @vandn_vv_nxv32i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -437,9 +415,7 @@ define @vandn_vv_swapped_nxv32i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -497,9 +473,7 @@ define @vandn_vv_nxv64i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %a, %y ret %b } @@ -517,9 +491,7 @@ define @vandn_vv_swapped_nxv64i8( %x, poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i8 -1) %b = and %y, %a ret %b } @@ -577,9 +549,7 @@ define @vandn_vv_nxv1i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %a, %y ret %b } @@ -597,9 +567,7 @@ define @vandn_vv_swapped_nxv1i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %y, %a ret %b } @@ -657,9 +625,7 @@ define @vandn_vv_nxv2i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %a, %y ret %b } @@ -677,9 +643,7 @@ define @vandn_vv_swapped_nxv2i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %y, %a ret %b } @@ -737,9 +701,7 @@ define @vandn_vv_nxv4i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %a, %y ret %b } @@ -757,9 +719,7 @@ define @vandn_vv_swapped_nxv4i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %y, %a ret %b } @@ -817,9 +777,7 @@ define @vandn_vv_nxv8i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %a, %y ret %b } @@ -837,9 +795,7 @@ define @vandn_vv_swapped_nxv8i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %y, %a ret %b } @@ -897,9 +853,7 @@ define @vandn_vv_nxv16i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %a, %y ret %b } @@ -917,9 +871,7 @@ define @vandn_vv_swapped_nxv16i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %y, %a ret %b } @@ -977,9 +929,7 @@ define @vandn_vv_nxv32i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %a, %y ret %b } @@ -997,9 +947,7 @@ define @vandn_vv_swapped_nxv32i16( %x, poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i16 -1) %b = and %y, %a ret %b } @@ -1057,9 +1005,7 @@ define @vandn_vv_nxv1i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %a, %y ret %b } @@ -1077,9 +1023,7 @@ define @vandn_vv_swapped_nxv1i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %y, %a ret %b } @@ -1137,9 +1081,7 @@ define @vandn_vv_nxv2i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %a, %y ret %b } @@ -1157,9 +1099,7 @@ define @vandn_vv_swapped_nxv2i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %y, %a ret %b } @@ -1217,9 +1157,7 @@ define @vandn_vv_nxv4i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %a, %y ret %b } @@ -1237,9 +1175,7 @@ define @vandn_vv_swapped_nxv4i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %y, %a ret %b } @@ -1297,9 +1233,7 @@ define @vandn_vv_nxv8i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %a, %y ret %b } @@ -1317,9 +1251,7 @@ define @vandn_vv_swapped_nxv8i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %y, %a ret %b } @@ -1377,9 +1309,7 @@ define @vandn_vv_nxv16i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %a, %y ret %b } @@ -1397,9 +1327,7 @@ define @vandn_vv_swapped_nxv16i32( %x, poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i32 -1) %b = and %y, %a ret %b } @@ -1457,9 +1385,7 @@ define @vandn_vv_nxv1i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %a, %y ret %b } @@ -1477,9 +1403,7 @@ define @vandn_vv_swapped_nxv1i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %y, %a ret %b } @@ -1597,9 +1521,7 @@ define @vandn_vv_nxv2i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %a, %y ret %b } @@ -1617,9 +1539,7 @@ define @vandn_vv_swapped_nxv2i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %y, %a ret %b } @@ -1737,9 +1657,7 @@ define @vandn_vv_nxv4i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %a, %y ret %b } @@ -1757,9 +1675,7 @@ define @vandn_vv_swapped_nxv4i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %y, %a ret %b } @@ -1877,9 +1793,7 @@ define @vandn_vv_nxv8i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %a, %y ret %b } @@ -1897,9 +1811,7 @@ define @vandn_vv_swapped_nxv8i64( %x, poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %a = xor %x, %splat + %a = xor %x, splat (i64 -1) %b = and %y, %a ret %b } diff --git a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll index 4de71b6ce06f..4e60077e5db9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll @@ -48,9 +48,7 @@ define @vfsgnj_vv_nxv1f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -94,9 +92,7 @@ define @vfsgnj_vv_nxv2f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -140,9 +136,7 @@ define @vfsgnj_vv_nxv4f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -186,9 +180,7 @@ define @vfsgnj_vv_nxv8f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +224,7 @@ define @vfsgnj_vv_nxv16f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -372,9 +362,7 @@ define @vfsgnj_vv_nxv1f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -396,9 +384,7 @@ define @vfsgnj_vv_nxv2f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -420,9 +406,7 @@ define @vfsgnj_vv_nxv4f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -444,9 +428,7 @@ define @vfsgnj_vv_nxv8f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -468,9 +450,7 @@ define @vfsgnj_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -492,9 +472,7 @@ define @vfsgnj_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -516,9 +494,7 @@ define @vfsgnj_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -540,9 +516,7 @@ define @vfsgnj_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -564,8 +538,6 @@ define @vfsgnj_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsgnj.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll index 0028ac88cc4f..ef9b2104b2d2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll @@ -37,9 +37,7 @@ define @vdiv_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -48,9 +46,7 @@ define @vdiv_vi_nxv1i8_1( %va) { ; CHECK-LABEL: vdiv_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 1) ret %vc } @@ -61,9 +57,7 @@ define @vdiv_iv_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %splat, %va + %vc = sdiv splat (i8 0), %va ret %vc } @@ -100,9 +94,7 @@ define @vdiv_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -139,9 +131,7 @@ define @vdiv_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -178,9 +168,7 @@ define @vdiv_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -217,9 +205,7 @@ define @vdiv_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsrl.vi v10, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -256,9 +242,7 @@ define @vdiv_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsrl.vi v12, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -295,9 +279,7 @@ define @vdiv_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsrl.vi v16, v8, 7 ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i8 -7) ret %vc } @@ -334,9 +316,7 @@ define @vdiv_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 15 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i16 -7) ret %vc } @@ -373,9 +353,7 @@ define @vdiv_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 15 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i16 -7) ret %vc } @@ -412,9 +390,7 @@ define @vdiv_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsrl.vi v9, v8, 15 ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i16 -7) ret %vc } @@ -451,9 +427,7 @@ define @vdiv_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsrl.vi v10, v8, 15 ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i16 -7) ret %vc } @@ -490,9 +464,7 @@ define @vdiv_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsrl.vi v12, v8, 15 ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i16 -7) ret %vc } @@ -529,9 +501,7 @@ define @vdiv_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsrl.vi v16, v8, 15 ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i16 -7) ret %vc } @@ -581,9 +551,7 @@ define @vdiv_vi_nxv1i32_0( %va) { ; RV64-NEXT: vsrl.vi v9, v8, 31 ; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i32 -7) ret %vc } @@ -633,9 +601,7 @@ define @vdiv_vi_nxv2i32_0( %va) { ; RV64-NEXT: vsrl.vi v9, v8, 31 ; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i32 -7) ret %vc } @@ -685,9 +651,7 @@ define @vdiv_vi_nxv4i32_0( %va) { ; RV64-NEXT: vsrl.vi v10, v8, 31 ; RV64-NEXT: vadd.vv v8, v8, v10 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i32 -7) ret %vc } @@ -737,9 +701,7 @@ define @vdiv_vi_nxv8i32_0( %va) { ; RV64-NEXT: vsrl.vi v12, v8, 31 ; RV64-NEXT: vadd.vv v8, v8, v12 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i32 -7) ret %vc } @@ -789,9 +751,7 @@ define @vdiv_vi_nxv16i32_0( %va) { ; RV64-NEXT: vsrl.vi v16, v8, 31 ; RV64-NEXT: vadd.vv v8, v8, v16 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i32 -7) ret %vc } @@ -870,9 +830,7 @@ define @vdiv_vi_nxv1i64_0( %va) { ; RV64-V-NEXT: vsra.vi v8, v8, 1 ; RV64-V-NEXT: vadd.vv v8, v8, v9 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i64 -7) ret %vc } @@ -951,9 +909,7 @@ define @vdiv_vi_nxv2i64_0( %va) { ; RV64-V-NEXT: vsra.vi v8, v8, 1 ; RV64-V-NEXT: vadd.vv v8, v8, v10 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i64 -7) ret %vc } @@ -1032,9 +988,7 @@ define @vdiv_vi_nxv4i64_0( %va) { ; RV64-V-NEXT: vsra.vi v8, v8, 1 ; RV64-V-NEXT: vadd.vv v8, v8, v12 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i64 -7) ret %vc } @@ -1113,9 +1067,7 @@ define @vdiv_vi_nxv8i64_0( %va) { ; RV64-V-NEXT: vsra.vi v8, v8, 1 ; RV64-V-NEXT: vadd.vv v8, v8, v16 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sdiv %va, %splat + %vc = sdiv %va, splat (i64 -7) ret %vc } @@ -1127,9 +1079,7 @@ define @vdiv_vv_mask_nxv8i32( %va, poison, i32 1, i32 0 - %one = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %one + %vs = select %mask, %vb, splat (i32 1) %vc = sdiv %va, %vs ret %vc } @@ -1142,11 +1092,9 @@ define @vdiv_vx_mask_nxv8i32( %va, i32 sign ; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0 ; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 1, i32 0 - %one = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %one + %vs = select %mask, %splat, splat (i32 1) %vc = sdiv %va, %vs ret %vc } @@ -1159,11 +1107,7 @@ define @vdiv_vi_mask_nxv8i32( %va, poison, i32 1, i32 0 - %one = shufflevector %head1, poison, zeroinitializer - %head2 = insertelement poison, i32 7, i32 0 - %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %one + %vs = select %mask, splat (i32 7), splat (i32 1) %vc = sdiv %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll index fd951d5cfbff..26089706cf99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll @@ -39,9 +39,7 @@ define @vdiv_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -65,9 +63,7 @@ define @vdiv_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -89,9 +85,7 @@ define @vdiv_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -115,9 +109,7 @@ define @vdiv_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -151,9 +143,7 @@ define @vdiv_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -177,9 +167,7 @@ define @vdiv_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -201,9 +189,7 @@ define @vdiv_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -227,9 +213,7 @@ define @vdiv_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -251,9 +235,7 @@ define @vdiv_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -277,9 +259,7 @@ define @vdiv_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -301,9 +281,7 @@ define @vdiv_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -327,9 +305,7 @@ define @vdiv_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -351,9 +327,7 @@ define @vdiv_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -377,9 +351,7 @@ define @vdiv_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -401,9 +373,7 @@ define @vdiv_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -427,9 +397,7 @@ define @vdiv_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -451,9 +419,7 @@ define @vdiv_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -477,9 +443,7 @@ define @vdiv_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -501,9 +465,7 @@ define @vdiv_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -527,9 +489,7 @@ define @vdiv_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -551,9 +511,7 @@ define @vdiv_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -577,9 +535,7 @@ define @vdiv_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -601,9 +557,7 @@ define @vdiv_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -627,9 +581,7 @@ define @vdiv_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -651,9 +603,7 @@ define @vdiv_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -677,9 +627,7 @@ define @vdiv_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -701,9 +649,7 @@ define @vdiv_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -727,9 +673,7 @@ define @vdiv_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -751,9 +695,7 @@ define @vdiv_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -777,9 +719,7 @@ define @vdiv_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -801,9 +741,7 @@ define @vdiv_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -827,9 +765,7 @@ define @vdiv_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -851,9 +787,7 @@ define @vdiv_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -877,9 +811,7 @@ define @vdiv_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -901,9 +833,7 @@ define @vdiv_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vdiv.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -927,9 +857,7 @@ define @vdiv_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -951,9 +879,7 @@ define @vdiv_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1005,9 +931,7 @@ define @vdiv_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1029,9 +953,7 @@ define @vdiv_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1083,9 +1005,7 @@ define @vdiv_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1107,9 +1027,7 @@ define @vdiv_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1161,9 +1079,7 @@ define @vdiv_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1185,9 +1101,7 @@ define @vdiv_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1239,8 +1153,6 @@ define @vdiv_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sdiv.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sdiv.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll index c505cb3d1bbd..4f2fb937ca73 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll @@ -34,9 +34,7 @@ define @vdivu_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -45,9 +43,7 @@ define @vdivu_vi_nxv1i8_1( %va) { ; CHECK-LABEL: vdivu_vi_nxv1i8_1: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 1) ret %vc } @@ -58,9 +54,7 @@ define @vdivu_iv_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %splat, %va + %vc = udiv splat (i8 0), %va ret %vc } @@ -94,9 +88,7 @@ define @vdivu_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -130,9 +122,7 @@ define @vdivu_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -166,9 +156,7 @@ define @vdivu_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -202,9 +190,7 @@ define @vdivu_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -238,9 +224,7 @@ define @vdivu_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -274,9 +258,7 @@ define @vdivu_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 5 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i8 -7) ret %vc } @@ -311,9 +293,7 @@ define @vdivu_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i16 -7) ret %vc } @@ -348,9 +328,7 @@ define @vdivu_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i16 -7) ret %vc } @@ -385,9 +363,7 @@ define @vdivu_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i16 -7) ret %vc } @@ -422,9 +398,7 @@ define @vdivu_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i16 -7) ret %vc } @@ -459,9 +433,7 @@ define @vdivu_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i16 -7) ret %vc } @@ -496,9 +468,7 @@ define @vdivu_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 13 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i16 -7) ret %vc } @@ -533,9 +503,7 @@ define @vdivu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i32 -7) ret %vc } @@ -570,9 +538,7 @@ define @vdivu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i32 -7) ret %vc } @@ -607,9 +573,7 @@ define @vdivu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i32 -7) ret %vc } @@ -644,9 +608,7 @@ define @vdivu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i32 -7) ret %vc } @@ -681,9 +643,7 @@ define @vdivu_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: vsrl.vi v8, v8, 29 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i32 -7) ret %vc } @@ -757,9 +717,7 @@ define @vdivu_vi_nxv1i64_0( %va) { ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 -7) ret %vc } @@ -769,9 +727,7 @@ define @vdivu_vi_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 2) ret %vc } @@ -783,9 +739,7 @@ define @vdivu_vi_nxv1i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = udiv %va, %vc ret %vd } @@ -860,9 +814,7 @@ define @vdivu_vi_nxv2i64_0( %va) { ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 -7) ret %vc } @@ -872,9 +824,7 @@ define @vdivu_vi_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 2) ret %vc } @@ -886,9 +836,7 @@ define @vdivu_vi_nxv2i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = udiv %va, %vc ret %vd } @@ -963,9 +911,7 @@ define @vdivu_vi_nxv4i64_0( %va) { ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 -7) ret %vc } @@ -975,9 +921,7 @@ define @vdivu_vi_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 2) ret %vc } @@ -989,9 +933,7 @@ define @vdivu_vi_nxv4i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = udiv %va, %vc ret %vd } @@ -1066,9 +1008,7 @@ define @vdivu_vi_nxv8i64_0( %va) { ; RV64-V-NEXT: li a0, 61 ; RV64-V-NEXT: vsrl.vx v8, v8, a0 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 -7) ret %vc } @@ -1078,9 +1018,7 @@ define @vdivu_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = udiv %va, %splat + %vc = udiv %va, splat (i64 2) ret %vc } @@ -1092,9 +1030,7 @@ define @vdivu_vi_nxv8i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = udiv %va, %vc ret %vd } @@ -1107,9 +1043,7 @@ define @vdivu_vv_mask_nxv8i32( %va, poison, i32 1, i32 0 - %one = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %one + %vs = select %mask, %vb, splat (i32 1) %vc = udiv %va, %vs ret %vc } @@ -1122,11 +1056,9 @@ define @vdivu_vx_mask_nxv8i32( %va, i32 sig ; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0 ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 1, i32 0 - %one = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %one + %vs = select %mask, %splat, splat (i32 1) %vc = udiv %va, %vs ret %vc } @@ -1143,11 +1075,7 @@ define @vdivu_vi_mask_nxv8i32( %va, poison, i32 1, i32 0 - %one = shufflevector %head1, poison, zeroinitializer - %head2 = insertelement poison, i32 7, i32 0 - %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %one + %vs = select %mask, splat (i32 7), splat (i32 1) %vc = udiv %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll index d6ebf822fd26..f41b885a66ea 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll @@ -41,9 +41,7 @@ define @vdivu_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -67,9 +65,7 @@ define @vdivu_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -91,9 +87,7 @@ define @vdivu_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -117,9 +111,7 @@ define @vdivu_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -153,9 +145,7 @@ define @vdivu_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -179,9 +169,7 @@ define @vdivu_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -203,9 +191,7 @@ define @vdivu_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -229,9 +215,7 @@ define @vdivu_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -253,9 +237,7 @@ define @vdivu_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -279,9 +261,7 @@ define @vdivu_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -303,9 +283,7 @@ define @vdivu_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -329,9 +307,7 @@ define @vdivu_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -353,9 +329,7 @@ define @vdivu_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -379,9 +353,7 @@ define @vdivu_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -403,9 +375,7 @@ define @vdivu_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -429,9 +399,7 @@ define @vdivu_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -453,9 +421,7 @@ define @vdivu_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -479,9 +445,7 @@ define @vdivu_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -503,9 +467,7 @@ define @vdivu_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -529,9 +491,7 @@ define @vdivu_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -553,9 +513,7 @@ define @vdivu_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -579,9 +537,7 @@ define @vdivu_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -603,9 +559,7 @@ define @vdivu_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -629,9 +583,7 @@ define @vdivu_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -653,9 +605,7 @@ define @vdivu_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -679,9 +629,7 @@ define @vdivu_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -703,9 +651,7 @@ define @vdivu_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -729,9 +675,7 @@ define @vdivu_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -753,9 +697,7 @@ define @vdivu_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -779,9 +721,7 @@ define @vdivu_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -803,9 +743,7 @@ define @vdivu_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -829,9 +767,7 @@ define @vdivu_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -853,9 +789,7 @@ define @vdivu_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -879,9 +813,7 @@ define @vdivu_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -903,9 +835,7 @@ define @vdivu_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vdivu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -929,9 +859,7 @@ define @vdivu_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -953,9 +881,7 @@ define @vdivu_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1007,9 +933,7 @@ define @vdivu_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1031,9 +955,7 @@ define @vdivu_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1085,9 +1007,7 @@ define @vdivu_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1109,9 +1029,7 @@ define @vdivu_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1163,9 +1081,7 @@ define @vdivu_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1187,9 +1103,7 @@ define @vdivu_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1241,8 +1155,6 @@ define @vdivu_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.udiv.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.udiv.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll index 22f0d8bba2e6..73a59932774d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll @@ -46,9 +46,7 @@ define @vfabs_vv_nxv1f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -90,9 +88,7 @@ define @vfabs_vv_nxv2f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -134,9 +130,7 @@ define @vfabs_vv_nxv4f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -178,9 +172,7 @@ define @vfabs_vv_nxv8f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +214,7 @@ define @vfabs_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -330,9 +320,7 @@ define @vfabs_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +342,7 @@ define @vfabs_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -378,9 +364,7 @@ define @vfabs_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -402,9 +386,7 @@ define @vfabs_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -426,9 +408,7 @@ define @vfabs_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -450,9 +430,7 @@ define @vfabs_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -474,9 +452,7 @@ define @vfabs_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -498,9 +474,7 @@ define @vfabs_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -522,9 +496,7 @@ define @vfabs_vv_nxv7f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -546,9 +518,7 @@ define @vfabs_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -598,8 +568,6 @@ define @vfabs_vv_nxv16f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfabs.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll index 0651438429fd..4065b69e781a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll @@ -562,9 +562,7 @@ define @vfadd_vv_mask_nxv8f32( %va, poison, float 0.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %splat + %vs = select %mask, %vb, splat (float 0.0) %vc = fadd fast %va, %vs ret %vc } @@ -575,11 +573,9 @@ define @vfadd_vf_mask_nxv8f32( %va, flo ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vfadd.vf v8, v8, fa0, v0.t ; CHECK-NEXT: ret - %head0 = insertelement poison, float 0.0, i32 0 - %splat0 = shufflevector %head0, poison, zeroinitializer %head1 = insertelement poison, float %b, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer - %vs = select %mask, %splat1, %splat0 + %vs = select %mask, %splat1, splat (float 0.0) %vc = fadd fast %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index 4168f5cd5079..0c6a9792d7d2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -48,9 +48,7 @@ define @vfadd_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -131,9 +129,7 @@ define @vfadd_vf_nxv1f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -160,9 +156,7 @@ define @vfadd_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -206,9 +200,7 @@ define @vfadd_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv2f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv2f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -262,9 +254,7 @@ define @vfadd_vf_nxv2f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +298,7 @@ define @vfadd_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv4f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv4f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -364,9 +352,7 @@ define @vfadd_vf_nxv4f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +396,7 @@ define @vfadd_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv8f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv8f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -466,9 +450,7 @@ define @vfadd_vf_nxv8f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +494,7 @@ define @vfadd_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv16f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv16f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -568,9 +548,7 @@ define @vfadd_vf_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -806,9 +784,7 @@ define @vfadd_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -832,9 +808,7 @@ define @vfadd_vf_nxv1f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -856,9 +830,7 @@ define @vfadd_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv2f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv2f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -882,9 +854,7 @@ define @vfadd_vf_nxv2f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -906,9 +876,7 @@ define @vfadd_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv4f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv4f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -932,9 +900,7 @@ define @vfadd_vf_nxv4f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -956,9 +922,7 @@ define @vfadd_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv8f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv8f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -982,9 +946,7 @@ define @vfadd_vf_nxv8f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1006,9 +968,7 @@ define @vfadd_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv16f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv16f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1032,9 +992,7 @@ define @vfadd_vf_nxv16f32_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1056,9 +1014,7 @@ define @vfadd_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1082,9 +1038,7 @@ define @vfadd_vf_nxv1f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1106,9 +1060,7 @@ define @vfadd_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv2f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv2f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1132,9 +1084,7 @@ define @vfadd_vf_nxv2f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1156,9 +1106,7 @@ define @vfadd_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv4f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv4f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1182,9 +1130,7 @@ define @vfadd_vf_nxv4f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1218,9 +1164,7 @@ define @vfadd_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv8f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv8f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1244,8 +1188,6 @@ define @vfadd_vf_nxv8f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll index 12bfc235c0c6..be2d576597da 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll @@ -28,9 +28,7 @@ define @isnan_nxv2f16_unmasked( %x, i32 zer ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv2f16( %x, i32 3, %m, i32 %evl) ; nan + %1 = call @llvm.vp.is.fpclass.nxv2f16( %x, i32 3, splat (i1 true), i32 %evl) ; nan ret %1 } @@ -58,9 +56,7 @@ define @isnan_nxv2f32_unmasked( %x, i32 ze ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv2f32( %x, i32 639, %m, i32 %evl) + %1 = call @llvm.vp.is.fpclass.nxv2f32( %x, i32 639, splat (i1 true), i32 %evl) ret %1 } @@ -88,9 +84,7 @@ define @isnan_nxv4f32_unmasked( %x, i32 ze ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv4f32( %x, i32 3, %m, i32 %evl) ; nan + %1 = call @llvm.vp.is.fpclass.nxv4f32( %x, i32 3, splat (i1 true), i32 %evl) ; nan ret %1 } @@ -116,9 +110,7 @@ define @isnan_nxv8f32_unmasked( %x, i32 ze ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv8f32( %x, i32 2, %m, i32 %evl) + %1 = call @llvm.vp.is.fpclass.nxv8f32( %x, i32 2, splat (i1 true), i32 %evl) ret %1 } @@ -144,9 +136,7 @@ define @isnan_nxv16f32_unmasked( %x, i32 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv16f32( %x, i32 1, %m, i32 %evl) + %1 = call @llvm.vp.is.fpclass.nxv16f32( %x, i32 1, splat (i1 true), i32 %evl) ret %1 } @@ -174,9 +164,7 @@ define @isnormal_nxv2f64_unmasked( %x, i3 ; CHECK-NEXT: vand.vx v8, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv2f64( %x, i32 516, %m, i32 %evl) ; 0x204 = "inf" + %1 = call @llvm.vp.is.fpclass.nxv2f64( %x, i32 516, splat (i1 true), i32 %evl) ; 0x204 = "inf" ret %1 } @@ -202,9 +190,7 @@ define @isposinf_nxv4f64_unmasked( %x, i3 ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vmseq.vx v0, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv4f64( %x, i32 512, %m, i32 %evl) ; 0x200 = "+inf" + %1 = call @llvm.vp.is.fpclass.nxv4f64( %x, i32 512, splat (i1 true), i32 %evl) ; 0x200 = "+inf" ret %1 } @@ -228,9 +214,7 @@ define @isneginf_nxv8f64_unmasked( %x, i3 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmseq.vi v0, v8, 1 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %1 = call @llvm.vp.is.fpclass.nxv8f64( %x, i32 4, %m, i32 %evl) ; "-inf" + %1 = call @llvm.vp.is.fpclass.nxv8f64( %x, i32 4, splat (i1 true), i32 %evl) ; "-inf" ret %1 } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll index b46b6743505b..7d1d9ec1680c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll @@ -564,9 +564,7 @@ define @vfdiv_vv_mask_nxv8f32( %va, poison, float 0.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %splat + %vs = select %mask, %vb, splat (float 0.0) %vc = fdiv %va, %vs ret %vc } @@ -579,11 +577,9 @@ define @vfdiv_vf_mask_nxv8f32( %va, flo ; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head0 = insertelement poison, float 0.0, i32 0 - %splat0 = shufflevector %head0, poison, zeroinitializer %head1 = insertelement poison, float %b, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer - %vs = select %mask, %splat1, %splat0 + %vs = select %mask, %splat1, splat (float 0.0) %vc = fdiv %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 396e99bc5e4f..0775a180d5ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -48,9 +48,7 @@ define @vfdiv_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -104,9 +102,7 @@ define @vfdiv_vf_nxv1f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +146,7 @@ define @vfdiv_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -206,9 +200,7 @@ define @vfdiv_vf_nxv2f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -252,9 +244,7 @@ define @vfdiv_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +298,7 @@ define @vfdiv_vf_nxv4f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +342,7 @@ define @vfdiv_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +396,7 @@ define @vfdiv_vf_nxv8f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -456,9 +440,7 @@ define @vfdiv_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv16f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv16f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +494,7 @@ define @vfdiv_vf_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -750,9 +730,7 @@ define @vfdiv_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -776,9 +754,7 @@ define @vfdiv_vf_nxv1f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -800,9 +776,7 @@ define @vfdiv_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -826,9 +800,7 @@ define @vfdiv_vf_nxv2f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -850,9 +822,7 @@ define @vfdiv_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -876,9 +846,7 @@ define @vfdiv_vf_nxv4f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -900,9 +868,7 @@ define @vfdiv_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +892,7 @@ define @vfdiv_vf_nxv8f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -950,9 +914,7 @@ define @vfdiv_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv16f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv16f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -976,9 +938,7 @@ define @vfdiv_vf_nxv16f32_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1000,9 +960,7 @@ define @vfdiv_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +984,7 @@ define @vfdiv_vf_nxv1f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1050,9 +1006,7 @@ define @vfdiv_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1076,9 +1030,7 @@ define @vfdiv_vf_nxv2f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1100,9 +1052,7 @@ define @vfdiv_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1126,9 +1076,7 @@ define @vfdiv_vf_nxv4f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1162,9 +1110,7 @@ define @vfdiv_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfdiv.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1188,8 +1134,6 @@ define @vfdiv_vf_nxv8f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll index 1bc0ed4e7513..a0f269b59bfe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll @@ -36,12 +36,8 @@ define @test2( %a, ; CHECK-NEXT: vfadd.vf v9, v9, fa5, v0.t ; CHECK-NEXT: vfmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %elt.head1 = insertelement poison, double 2.0, i32 0 - %c1 = shufflevector %elt.head1, poison, zeroinitializer - %t = call @llvm.vp.fmul.nxv1f64( %a, %c1, %m, i32 %evl) - %elt.head2 = insertelement poison, double 4.0, i32 0 - %c2 = shufflevector %elt.head2, poison, zeroinitializer - %v = call fast @llvm.vp.fma.nxv1f64( %a, %c2, %t, %m, i32 %evl) + %t = call @llvm.vp.fmul.nxv1f64( %a, splat (double 2.0), %m, i32 %evl) + %v = call fast @llvm.vp.fma.nxv1f64( %a, splat (double 4.0), %t, %m, i32 %evl) ret %v } @@ -60,11 +56,7 @@ define @test3( %a, poison, double 2.0, i32 0 - %c1 = shufflevector %elt.head1, poison, zeroinitializer - %t = call @llvm.vp.fmul.nxv1f64( %a, %c1, %m, i32 %evl) - %elt.head2 = insertelement poison, double 4.0, i32 0 - %c2 = shufflevector %elt.head2, poison, zeroinitializer - %v = call fast @llvm.vp.fma.nxv1f64( %t, %c2, %b, %m, i32 %evl) + %t = call @llvm.vp.fmul.nxv1f64( %a, splat (double 2.0), %m, i32 %evl) + %v = call fast @llvm.vp.fma.nxv1f64( %t, splat (double 4.0), %b, %m, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll index 9ab907bfcca6..a41c26211613 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll @@ -23,9 +23,7 @@ define @vfma_vv_nxv1f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -61,9 +59,7 @@ define @vfma_vf_nxv1f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -75,9 +71,7 @@ define @vfma_vf_nxv1f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -100,9 +94,7 @@ define @vfma_vv_nxv2f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +130,7 @@ define @vfma_vf_nxv2f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -152,9 +142,7 @@ define @vfma_vf_nxv2f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -177,9 +165,7 @@ define @vfma_vv_nxv4f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -215,9 +201,7 @@ define @vfma_vf_nxv4f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -229,9 +213,7 @@ define @vfma_vf_nxv4f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -254,9 +236,7 @@ define @vfma_vv_nxv8f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -292,9 +272,7 @@ define @vfma_vf_nxv8f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -306,9 +284,7 @@ define @vfma_vf_nxv8f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -331,9 +307,7 @@ define @vfma_vv_nxv16f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -369,9 +343,7 @@ define @vfma_vf_nxv16f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -383,9 +355,7 @@ define @vfma_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +380,7 @@ define @vfma_vv_nxv32f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -448,9 +416,7 @@ define @vfma_vf_nxv32f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -462,9 +428,7 @@ define @vfma_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -487,9 +451,7 @@ define @vfma_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -525,9 +487,7 @@ define @vfma_vf_nxv1f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -539,9 +499,7 @@ define @vfma_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -564,9 +522,7 @@ define @vfma_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -602,9 +558,7 @@ define @vfma_vf_nxv2f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -616,9 +570,7 @@ define @vfma_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -641,9 +593,7 @@ define @vfma_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -679,9 +629,7 @@ define @vfma_vf_nxv4f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -693,9 +641,7 @@ define @vfma_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -718,9 +664,7 @@ define @vfma_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -756,9 +700,7 @@ define @vfma_vf_nxv8f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -770,9 +712,7 @@ define @vfma_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -797,9 +737,7 @@ define @vfma_vv_nxv16f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -835,9 +773,7 @@ define @vfma_vf_nxv16f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -849,9 +785,7 @@ define @vfma_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -874,9 +808,7 @@ define @vfma_vv_nxv1f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -912,9 +844,7 @@ define @vfma_vf_nxv1f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +856,7 @@ define @vfma_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -951,9 +879,7 @@ define @vfma_vv_nxv2f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -989,9 +915,7 @@ define @vfma_vf_nxv2f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1003,9 +927,7 @@ define @vfma_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1028,9 +950,7 @@ define @vfma_vv_nxv4f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1066,9 +986,7 @@ define @vfma_vf_nxv4f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1080,9 +998,7 @@ define @vfma_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1107,9 +1023,7 @@ define @vfma_vv_nxv7f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv7f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv7f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1134,9 +1048,7 @@ define @vfma_vv_nxv8f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1172,9 +1084,7 @@ define @vfma_vf_nxv8f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1186,9 +1096,7 @@ define @vfma_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1359,9 +1267,7 @@ define @vfma_vv_nxv16f64_unmasked( ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fma.nxv16f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1385,10 +1291,8 @@ define @vfmsub_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1426,10 +1330,8 @@ define @vfmsub_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1441,10 +1343,8 @@ define @vfmsub_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1479,11 +1379,9 @@ define @vfnmadd_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1493,11 +1391,9 @@ define @vfnmadd_vv_nxv1f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1537,11 +1433,9 @@ define @vfnmadd_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1553,11 +1447,9 @@ define @vfnmadd_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1597,11 +1489,9 @@ define @vfnmadd_vf_nxv1f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1613,11 +1503,9 @@ define @vfnmadd_vf_nxv1f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1652,11 +1540,9 @@ define @vfnmsub_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1666,11 +1552,9 @@ define @vfnmsub_vv_nxv1f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1708,10 +1592,8 @@ define @vfnmsub_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1723,10 +1605,8 @@ define @vfnmsub_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1764,10 +1644,8 @@ define @vfnmsub_vf_nxv1f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1779,10 +1657,8 @@ define @vfnmsub_vf_nxv1f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1806,10 +1682,8 @@ define @vfmsub_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1847,10 +1721,8 @@ define @vfmsub_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1862,10 +1734,8 @@ define @vfmsub_vf_nxv2f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1900,11 +1770,9 @@ define @vfnmadd_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1914,11 +1782,9 @@ define @vfnmadd_vv_nxv2f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1958,11 +1824,9 @@ define @vfnmadd_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1974,11 +1838,9 @@ define @vfnmadd_vf_nxv2f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2018,11 +1880,9 @@ define @vfnmadd_vf_nxv2f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2034,11 +1894,9 @@ define @vfnmadd_vf_nxv2f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2073,11 +1931,9 @@ define @vfnmsub_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2087,11 +1943,9 @@ define @vfnmsub_vv_nxv2f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2129,10 +1983,8 @@ define @vfnmsub_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2144,10 +1996,8 @@ define @vfnmsub_vf_nxv2f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2185,10 +2035,8 @@ define @vfnmsub_vf_nxv2f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2200,10 +2048,8 @@ define @vfnmsub_vf_nxv2f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2227,10 +2073,8 @@ define @vfmsub_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2268,10 +2112,8 @@ define @vfmsub_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2283,10 +2125,8 @@ define @vfmsub_vf_nxv4f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2321,11 +2161,9 @@ define @vfnmadd_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2335,11 +2173,9 @@ define @vfnmadd_vv_nxv4f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2379,11 +2215,9 @@ define @vfnmadd_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2395,11 +2229,9 @@ define @vfnmadd_vf_nxv4f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2439,11 +2271,9 @@ define @vfnmadd_vf_nxv4f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2455,11 +2285,9 @@ define @vfnmadd_vf_nxv4f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2494,11 +2322,9 @@ define @vfnmsub_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2508,11 +2334,9 @@ define @vfnmsub_vv_nxv4f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2550,10 +2374,8 @@ define @vfnmsub_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2565,10 +2387,8 @@ define @vfnmsub_vf_nxv4f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2606,10 +2426,8 @@ define @vfnmsub_vf_nxv4f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2621,10 +2439,8 @@ define @vfnmsub_vf_nxv4f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2648,10 +2464,8 @@ define @vfmsub_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2689,10 +2503,8 @@ define @vfmsub_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2704,10 +2516,8 @@ define @vfmsub_vf_nxv8f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2742,11 +2552,9 @@ define @vfnmadd_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2756,11 +2564,9 @@ define @vfnmadd_vv_nxv8f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2800,11 +2606,9 @@ define @vfnmadd_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2816,11 +2620,9 @@ define @vfnmadd_vf_nxv8f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2860,11 +2662,9 @@ define @vfnmadd_vf_nxv8f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2876,11 +2676,9 @@ define @vfnmadd_vf_nxv8f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2915,11 +2713,9 @@ define @vfnmsub_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2929,11 +2725,9 @@ define @vfnmsub_vv_nxv8f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2971,10 +2765,8 @@ define @vfnmsub_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2986,10 +2778,8 @@ define @vfnmsub_vf_nxv8f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3027,10 +2817,8 @@ define @vfnmsub_vf_nxv8f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3042,10 +2830,8 @@ define @vfnmsub_vf_nxv8f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3069,10 +2855,8 @@ define @vfmsub_vv_nxv16f16_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3110,10 +2894,8 @@ define @vfmsub_vf_nxv16f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3125,10 +2907,8 @@ define @vfmsub_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3163,11 +2943,9 @@ define @vfnmadd_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3177,11 +2955,9 @@ define @vfnmadd_vv_nxv16f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3221,11 +2997,9 @@ define @vfnmadd_vf_nxv16f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3237,11 +3011,9 @@ define @vfnmadd_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3281,11 +3053,9 @@ define @vfnmadd_vf_nxv16f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3297,11 +3067,9 @@ define @vfnmadd_vf_nxv16f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3336,11 +3104,9 @@ define @vfnmsub_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3350,11 +3116,9 @@ define @vfnmsub_vv_nxv16f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3392,10 +3156,8 @@ define @vfnmsub_vf_nxv16f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3407,10 +3169,8 @@ define @vfnmsub_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3448,10 +3208,8 @@ define @vfnmsub_vf_nxv16f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3463,10 +3221,8 @@ define @vfnmsub_vf_nxv16f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3492,10 +3248,8 @@ define @vfmsub_vv_nxv32f16_unmasked( %v ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3533,10 +3287,8 @@ define @vfmsub_vf_nxv32f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3548,10 +3300,8 @@ define @vfmsub_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3589,11 +3339,9 @@ define @vfnmadd_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3604,11 +3352,9 @@ define @vfnmadd_vv_nxv32f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3648,11 +3394,9 @@ define @vfnmadd_vf_nxv32f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3664,11 +3408,9 @@ define @vfnmadd_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3708,11 +3450,9 @@ define @vfnmadd_vf_nxv32f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3724,11 +3464,9 @@ define @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3766,11 +3504,9 @@ define @vfnmsub_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3781,11 +3517,9 @@ define @vfnmsub_vv_nxv32f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3823,10 +3557,8 @@ define @vfnmsub_vf_nxv32f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3838,10 +3570,8 @@ define @vfnmsub_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3879,10 +3609,8 @@ define @vfnmsub_vf_nxv32f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3894,10 +3622,8 @@ define @vfnmsub_vf_nxv32f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3921,10 +3647,8 @@ define @vfmsub_vv_nxv1f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3962,10 +3686,8 @@ define @vfmsub_vf_nxv1f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3977,10 +3699,8 @@ define @vfmsub_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4015,11 +3735,9 @@ define @vfnmadd_vv_nxv1f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4029,11 +3747,9 @@ define @vfnmadd_vv_nxv1f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4073,11 +3789,9 @@ define @vfnmadd_vf_nxv1f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4089,11 +3803,9 @@ define @vfnmadd_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4133,11 +3845,9 @@ define @vfnmadd_vf_nxv1f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4149,11 +3859,9 @@ define @vfnmadd_vf_nxv1f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4188,11 +3896,9 @@ define @vfnmsub_vv_nxv1f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4202,11 +3908,9 @@ define @vfnmsub_vv_nxv1f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4244,10 +3948,8 @@ define @vfnmsub_vf_nxv1f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4259,10 +3961,8 @@ define @vfnmsub_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4300,10 +4000,8 @@ define @vfnmsub_vf_nxv1f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4315,10 +4013,8 @@ define @vfnmsub_vf_nxv1f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4342,10 +4038,8 @@ define @vfmsub_vv_nxv2f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4383,10 +4077,8 @@ define @vfmsub_vf_nxv2f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4398,10 +4090,8 @@ define @vfmsub_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4436,11 +4126,9 @@ define @vfnmadd_vv_nxv2f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4450,11 +4138,9 @@ define @vfnmadd_vv_nxv2f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4494,11 +4180,9 @@ define @vfnmadd_vf_nxv2f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4510,11 +4194,9 @@ define @vfnmadd_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4554,11 +4236,9 @@ define @vfnmadd_vf_nxv2f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4570,11 +4250,9 @@ define @vfnmadd_vf_nxv2f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4609,11 +4287,9 @@ define @vfnmsub_vv_nxv2f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4623,11 +4299,9 @@ define @vfnmsub_vv_nxv2f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4665,10 +4339,8 @@ define @vfnmsub_vf_nxv2f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4680,10 +4352,8 @@ define @vfnmsub_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4721,10 +4391,8 @@ define @vfnmsub_vf_nxv2f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4736,10 +4404,8 @@ define @vfnmsub_vf_nxv2f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4763,10 +4429,8 @@ define @vfmsub_vv_nxv4f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4804,10 +4468,8 @@ define @vfmsub_vf_nxv4f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4819,10 +4481,8 @@ define @vfmsub_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4857,11 +4517,9 @@ define @vfnmadd_vv_nxv4f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4871,11 +4529,9 @@ define @vfnmadd_vv_nxv4f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4915,11 +4571,9 @@ define @vfnmadd_vf_nxv4f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4931,11 +4585,9 @@ define @vfnmadd_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4975,11 +4627,9 @@ define @vfnmadd_vf_nxv4f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4991,11 +4641,9 @@ define @vfnmadd_vf_nxv4f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5030,11 +4678,9 @@ define @vfnmsub_vv_nxv4f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5044,11 +4690,9 @@ define @vfnmsub_vv_nxv4f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5086,10 +4730,8 @@ define @vfnmsub_vf_nxv4f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5101,10 +4743,8 @@ define @vfnmsub_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5142,10 +4782,8 @@ define @vfnmsub_vf_nxv4f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5157,10 +4795,8 @@ define @vfnmsub_vf_nxv4f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5184,10 +4820,8 @@ define @vfmsub_vv_nxv8f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5225,10 +4859,8 @@ define @vfmsub_vf_nxv8f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5240,10 +4872,8 @@ define @vfmsub_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5278,11 +4908,9 @@ define @vfnmadd_vv_nxv8f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5292,11 +4920,9 @@ define @vfnmadd_vv_nxv8f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5336,11 +4962,9 @@ define @vfnmadd_vf_nxv8f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5352,11 +4976,9 @@ define @vfnmadd_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5396,11 +5018,9 @@ define @vfnmadd_vf_nxv8f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5412,11 +5032,9 @@ define @vfnmadd_vf_nxv8f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5451,11 +5069,9 @@ define @vfnmsub_vv_nxv8f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5465,11 +5081,9 @@ define @vfnmsub_vv_nxv8f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5507,10 +5121,8 @@ define @vfnmsub_vf_nxv8f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5522,10 +5134,8 @@ define @vfnmsub_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5563,10 +5173,8 @@ define @vfnmsub_vf_nxv8f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5578,10 +5186,8 @@ define @vfnmsub_vf_nxv8f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5607,10 +5213,8 @@ define @vfmsub_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5648,10 +5252,8 @@ define @vfmsub_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5663,10 +5265,8 @@ define @vfmsub_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5704,11 +5304,9 @@ define @vfnmadd_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5719,11 +5317,9 @@ define @vfnmadd_vv_nxv16f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5763,11 +5359,9 @@ define @vfnmadd_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5779,11 +5373,9 @@ define @vfnmadd_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5823,11 +5415,9 @@ define @vfnmadd_vf_nxv16f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5839,11 +5429,9 @@ define @vfnmadd_vf_nxv16f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5881,11 +5469,9 @@ define @vfnmsub_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5896,11 +5482,9 @@ define @vfnmsub_vv_nxv16f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5938,10 +5522,8 @@ define @vfnmsub_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5953,10 +5535,8 @@ define @vfnmsub_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5994,10 +5574,8 @@ define @vfnmsub_vf_nxv16f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6009,10 +5587,8 @@ define @vfnmsub_vf_nxv16f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6036,10 +5612,8 @@ define @vfmsub_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6077,10 +5651,8 @@ define @vfmsub_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6092,10 +5664,8 @@ define @vfmsub_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6130,11 +5700,9 @@ define @vfnmadd_vv_nxv1f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6144,11 +5712,9 @@ define @vfnmadd_vv_nxv1f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6188,11 +5754,9 @@ define @vfnmadd_vf_nxv1f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6204,11 +5768,9 @@ define @vfnmadd_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6248,11 +5810,9 @@ define @vfnmadd_vf_nxv1f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6264,11 +5824,9 @@ define @vfnmadd_vf_nxv1f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6303,11 +5861,9 @@ define @vfnmsub_vv_nxv1f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6317,11 +5873,9 @@ define @vfnmsub_vv_nxv1f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6359,10 +5913,8 @@ define @vfnmsub_vf_nxv1f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6374,10 +5926,8 @@ define @vfnmsub_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6415,10 +5965,8 @@ define @vfnmsub_vf_nxv1f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6430,10 +5978,8 @@ define @vfnmsub_vf_nxv1f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6457,10 +6003,8 @@ define @vfmsub_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6498,10 +6042,8 @@ define @vfmsub_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6513,10 +6055,8 @@ define @vfmsub_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6551,11 +6091,9 @@ define @vfnmadd_vv_nxv2f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6565,11 +6103,9 @@ define @vfnmadd_vv_nxv2f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6609,11 +6145,9 @@ define @vfnmadd_vf_nxv2f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6625,11 +6159,9 @@ define @vfnmadd_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6669,11 +6201,9 @@ define @vfnmadd_vf_nxv2f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6685,11 +6215,9 @@ define @vfnmadd_vf_nxv2f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6724,11 +6252,9 @@ define @vfnmsub_vv_nxv2f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6738,11 +6264,9 @@ define @vfnmsub_vv_nxv2f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6780,10 +6304,8 @@ define @vfnmsub_vf_nxv2f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6795,10 +6317,8 @@ define @vfnmsub_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6836,10 +6356,8 @@ define @vfnmsub_vf_nxv2f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6851,10 +6369,8 @@ define @vfnmsub_vf_nxv2f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6878,10 +6394,8 @@ define @vfmsub_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6919,10 +6433,8 @@ define @vfmsub_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6934,10 +6446,8 @@ define @vfmsub_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6972,11 +6482,9 @@ define @vfnmadd_vv_nxv4f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6986,11 +6494,9 @@ define @vfnmadd_vv_nxv4f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7030,11 +6536,9 @@ define @vfnmadd_vf_nxv4f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7046,11 +6550,9 @@ define @vfnmadd_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7090,11 +6592,9 @@ define @vfnmadd_vf_nxv4f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7106,11 +6606,9 @@ define @vfnmadd_vf_nxv4f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7145,11 +6643,9 @@ define @vfnmsub_vv_nxv4f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7159,11 +6655,9 @@ define @vfnmsub_vv_nxv4f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7201,10 +6695,8 @@ define @vfnmsub_vf_nxv4f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7216,10 +6708,8 @@ define @vfnmsub_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7257,10 +6747,8 @@ define @vfnmsub_vf_nxv4f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7272,10 +6760,8 @@ define @vfnmsub_vf_nxv4f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7301,10 +6787,8 @@ define @vfmsub_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7342,10 +6826,8 @@ define @vfmsub_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7357,10 +6839,8 @@ define @vfmsub_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7398,11 +6878,9 @@ define @vfnmadd_vv_nxv8f64_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7413,11 +6891,9 @@ define @vfnmadd_vv_nxv8f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7457,11 +6933,9 @@ define @vfnmadd_vf_nxv8f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7473,11 +6947,9 @@ define @vfnmadd_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7517,11 +6989,9 @@ define @vfnmadd_vf_nxv8f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7533,11 +7003,9 @@ define @vfnmadd_vf_nxv8f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7575,11 +7043,9 @@ define @vfnmsub_vv_nxv8f64_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7590,11 +7056,9 @@ define @vfnmsub_vv_nxv8f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7632,10 +7096,8 @@ define @vfnmsub_vf_nxv8f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7647,10 +7109,8 @@ define @vfnmsub_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7688,10 +7148,8 @@ define @vfnmsub_vf_nxv8f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7703,10 +7161,8 @@ define @vfnmsub_vf_nxv8f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll index 6f1b3986caaf..54855e6152b9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll @@ -16,9 +16,7 @@ define @vfmacc_vv_nxv1f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -30,10 +28,8 @@ define @vfmacc_vv_nxv1f16_unmasked( %a, < ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -46,9 +42,7 @@ define @vfmacc_vf_nxv1f16( %va, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -62,9 +56,7 @@ define @vfmacc_vf_nxv1f16_commute( %va, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -78,10 +70,8 @@ define @vfmacc_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -92,9 +82,7 @@ define @vfmacc_vv_nxv1f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -108,9 +96,7 @@ define @vfmacc_vf_nxv1f16_ta( %va, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -124,9 +110,7 @@ define @vfmacc_vf_nxv1f16_commute_ta( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -143,9 +127,7 @@ define @vfmacc_vv_nxv2f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -157,10 +139,8 @@ define @vfmacc_vv_nxv2f16_unmasked( %a, < ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -173,9 +153,7 @@ define @vfmacc_vf_nxv2f16( %va, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -189,9 +167,7 @@ define @vfmacc_vf_nxv2f16_commute( %va, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -205,10 +181,8 @@ define @vfmacc_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -219,9 +193,7 @@ define @vfmacc_vv_nxv2f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -235,9 +207,7 @@ define @vfmacc_vf_nxv2f16_ta( %va, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -251,9 +221,7 @@ define @vfmacc_vf_nxv2f16_commute_ta( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -270,9 +238,7 @@ define @vfmacc_vv_nxv4f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -284,10 +250,8 @@ define @vfmacc_vv_nxv4f16_unmasked( %a, < ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -300,9 +264,7 @@ define @vfmacc_vf_nxv4f16( %va, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -316,9 +278,7 @@ define @vfmacc_vf_nxv4f16_commute( %va, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -332,10 +292,8 @@ define @vfmacc_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -346,9 +304,7 @@ define @vfmacc_vv_nxv4f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -362,9 +318,7 @@ define @vfmacc_vf_nxv4f16_ta( %va, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -378,9 +332,7 @@ define @vfmacc_vf_nxv4f16_commute_ta( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -397,9 +349,7 @@ define @vfmacc_vv_nxv8f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -411,10 +361,8 @@ define @vfmacc_vv_nxv8f16_unmasked( %a, < ; CHECK-NEXT: vfmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -427,9 +375,7 @@ define @vfmacc_vf_nxv8f16( %va, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -443,9 +389,7 @@ define @vfmacc_vf_nxv8f16_commute( %va, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -459,10 +403,8 @@ define @vfmacc_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -473,9 +415,7 @@ define @vfmacc_vv_nxv8f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -489,9 +429,7 @@ define @vfmacc_vf_nxv8f16_ta( %va, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -505,9 +443,7 @@ define @vfmacc_vf_nxv8f16_commute_ta( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -524,9 +460,7 @@ define @vfmacc_vv_nxv16f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -538,10 +472,8 @@ define @vfmacc_vv_nxv16f16_unmasked( %a ; CHECK-NEXT: vfmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -554,9 +486,7 @@ define @vfmacc_vf_nxv16f16( %va, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -570,9 +500,7 @@ define @vfmacc_vf_nxv16f16_commute( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -586,10 +514,8 @@ define @vfmacc_vf_nxv16f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -600,9 +526,7 @@ define @vfmacc_vv_nxv16f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -616,9 +540,7 @@ define @vfmacc_vf_nxv16f16_ta( %va, hal ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -632,9 +554,7 @@ define @vfmacc_vf_nxv16f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -652,9 +572,7 @@ define @vfmacc_vv_nxv32f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -667,10 +585,8 @@ define @vfmacc_vv_nxv32f16_unmasked( %a ; CHECK-NEXT: vfmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -683,9 +599,7 @@ define @vfmacc_vf_nxv32f16( %va, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -699,9 +613,7 @@ define @vfmacc_vf_nxv32f16_commute( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -715,10 +627,8 @@ define @vfmacc_vf_nxv32f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -730,9 +640,7 @@ define @vfmacc_vv_nxv32f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -746,9 +654,7 @@ define @vfmacc_vf_nxv32f16_ta( %va, hal ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -762,9 +668,7 @@ define @vfmacc_vf_nxv32f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -781,9 +685,7 @@ define @vfmacc_vv_nxv1f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -795,10 +697,8 @@ define @vfmacc_vv_nxv1f32_unmasked( %a, ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -811,9 +711,7 @@ define @vfmacc_vf_nxv1f32( %va, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -827,9 +725,7 @@ define @vfmacc_vf_nxv1f32_commute( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -843,10 +739,8 @@ define @vfmacc_vf_nxv1f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -857,9 +751,7 @@ define @vfmacc_vv_nxv1f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -873,9 +765,7 @@ define @vfmacc_vf_nxv1f32_ta( %va, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -889,9 +779,7 @@ define @vfmacc_vf_nxv1f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -908,9 +796,7 @@ define @vfmacc_vv_nxv2f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -922,10 +808,8 @@ define @vfmacc_vv_nxv2f32_unmasked( %a, ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -938,9 +822,7 @@ define @vfmacc_vf_nxv2f32( %va, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -954,9 +836,7 @@ define @vfmacc_vf_nxv2f32_commute( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -970,10 +850,8 @@ define @vfmacc_vf_nxv2f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -984,9 +862,7 @@ define @vfmacc_vv_nxv2f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1000,9 +876,7 @@ define @vfmacc_vf_nxv2f32_ta( %va, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1016,9 +890,7 @@ define @vfmacc_vf_nxv2f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1035,9 +907,7 @@ define @vfmacc_vv_nxv4f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1049,10 +919,8 @@ define @vfmacc_vv_nxv4f32_unmasked( %a, ; CHECK-NEXT: vfmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1065,9 +933,7 @@ define @vfmacc_vf_nxv4f32( %va, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1081,9 +947,7 @@ define @vfmacc_vf_nxv4f32_commute( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1097,10 +961,8 @@ define @vfmacc_vf_nxv4f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1111,9 +973,7 @@ define @vfmacc_vv_nxv4f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1127,9 +987,7 @@ define @vfmacc_vf_nxv4f32_ta( %va, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1143,9 +1001,7 @@ define @vfmacc_vf_nxv4f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1162,9 +1018,7 @@ define @vfmacc_vv_nxv8f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1176,10 +1030,8 @@ define @vfmacc_vv_nxv8f32_unmasked( %a, ; CHECK-NEXT: vfmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1192,9 +1044,7 @@ define @vfmacc_vf_nxv8f32( %va, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1208,9 +1058,7 @@ define @vfmacc_vf_nxv8f32_commute( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1224,10 +1072,8 @@ define @vfmacc_vf_nxv8f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1238,9 +1084,7 @@ define @vfmacc_vv_nxv8f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1254,9 +1098,7 @@ define @vfmacc_vf_nxv8f32_ta( %va, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1270,9 +1112,7 @@ define @vfmacc_vf_nxv8f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1290,9 +1130,7 @@ define @vfmacc_vv_nxv16f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1305,10 +1143,8 @@ define @vfmacc_vv_nxv16f32_unmasked( ; CHECK-NEXT: vfmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1321,9 +1157,7 @@ define @vfmacc_vf_nxv16f32( %va, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1337,9 +1171,7 @@ define @vfmacc_vf_nxv16f32_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1353,10 +1185,8 @@ define @vfmacc_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1368,9 +1198,7 @@ define @vfmacc_vv_nxv16f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1384,9 +1212,7 @@ define @vfmacc_vf_nxv16f32_ta( %va, f ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1400,9 +1226,7 @@ define @vfmacc_vf_nxv16f32_commute_ta( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1419,9 +1243,7 @@ define @vfmacc_vv_nxv1f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1433,10 +1255,8 @@ define @vfmacc_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vfmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1449,9 +1269,7 @@ define @vfmacc_vf_nxv1f64( %va, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1465,9 +1283,7 @@ define @vfmacc_vf_nxv1f64_commute( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1481,10 +1297,8 @@ define @vfmacc_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1495,9 +1309,7 @@ define @vfmacc_vv_nxv1f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1511,9 +1323,7 @@ define @vfmacc_vf_nxv1f64_ta( %va, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1527,9 +1337,7 @@ define @vfmacc_vf_nxv1f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1546,9 +1354,7 @@ define @vfmacc_vv_nxv2f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1560,10 +1366,8 @@ define @vfmacc_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vfmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1576,9 +1380,7 @@ define @vfmacc_vf_nxv2f64( %va, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1592,9 +1394,7 @@ define @vfmacc_vf_nxv2f64_commute( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1608,10 +1408,8 @@ define @vfmacc_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1622,9 +1420,7 @@ define @vfmacc_vv_nxv2f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1638,9 +1434,7 @@ define @vfmacc_vf_nxv2f64_ta( %va, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1654,9 +1448,7 @@ define @vfmacc_vf_nxv2f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1673,9 +1465,7 @@ define @vfmacc_vv_nxv4f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1687,10 +1477,8 @@ define @vfmacc_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vfmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1703,9 +1491,7 @@ define @vfmacc_vf_nxv4f64( %va, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1719,9 +1505,7 @@ define @vfmacc_vf_nxv4f64_commute( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1735,10 +1519,8 @@ define @vfmacc_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1749,9 +1531,7 @@ define @vfmacc_vv_nxv4f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1765,9 +1545,7 @@ define @vfmacc_vf_nxv4f64_ta( %va, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1781,9 +1559,7 @@ define @vfmacc_vf_nxv4f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1801,9 +1577,7 @@ define @vfmacc_vv_nxv8f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1816,10 +1590,8 @@ define @vfmacc_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vfmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %a, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1832,9 +1604,7 @@ define @vfmacc_vf_nxv8f64( %va, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1848,9 +1618,7 @@ define @vfmacc_vf_nxv8f64_commute( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1864,10 +1632,8 @@ define @vfmacc_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1879,9 +1645,7 @@ define @vfmacc_vv_nxv8f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %a, %b, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1895,9 +1659,7 @@ define @vfmacc_vf_nxv8f64_ta( %va, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %va, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1911,9 +1673,7 @@ define @vfmacc_vf_nxv8f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %c, %allones, i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %va, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll index 72101d62567b..2c814016bc4b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll @@ -48,9 +48,7 @@ define @vfmax_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -94,9 +92,7 @@ define @vfmax_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -140,9 +136,7 @@ define @vfmax_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -186,9 +180,7 @@ define @vfmax_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +224,7 @@ define @vfmax_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -372,9 +362,7 @@ define @vfmax_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -396,9 +384,7 @@ define @vfmax_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -420,9 +406,7 @@ define @vfmax_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -444,9 +428,7 @@ define @vfmax_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -468,9 +450,7 @@ define @vfmax_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -492,9 +472,7 @@ define @vfmax_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -516,9 +494,7 @@ define @vfmax_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -540,9 +516,7 @@ define @vfmax_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -564,8 +538,6 @@ define @vfmax_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll index 15fa24a35b7d..b830d31637dc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll @@ -48,9 +48,7 @@ define @vfmin_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -94,9 +92,7 @@ define @vfmin_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -140,9 +136,7 @@ define @vfmin_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -186,9 +180,7 @@ define @vfmin_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +224,7 @@ define @vfmin_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -372,9 +362,7 @@ define @vfmin_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -396,9 +384,7 @@ define @vfmin_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -420,9 +406,7 @@ define @vfmin_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -444,9 +428,7 @@ define @vfmin_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -468,9 +450,7 @@ define @vfmin_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -492,9 +472,7 @@ define @vfmin_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -516,9 +494,7 @@ define @vfmin_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -540,9 +516,7 @@ define @vfmin_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -564,8 +538,6 @@ define @vfmin_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll index 1ce21a1c4633..f1d5562131b8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll @@ -16,10 +16,8 @@ define @vmfsac_vv_nxv1f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -31,11 +29,9 @@ define @vmfsac_vv_nxv1f16_unmasked( %a, < ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -48,10 +44,8 @@ define @vmfsac_vf_nxv1f16( %a, half %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -65,10 +59,8 @@ define @vmfsac_vf_nxv1f16_commute( %a, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -82,11 +74,9 @@ define @vmfsac_vf_nxv1f16_unmasked( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -97,10 +87,8 @@ define @vmfsac_vv_nxv1f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -114,10 +102,8 @@ define @vmfsac_vf_nxv1f16_ta( %a, half %b ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -131,10 +117,8 @@ define @vmfsac_vf_nxv1f16_commute_ta( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -151,10 +135,8 @@ define @vmfsac_vv_nxv2f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -166,11 +148,9 @@ define @vmfsac_vv_nxv2f16_unmasked( %a, < ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -183,10 +163,8 @@ define @vmfsac_vf_nxv2f16( %a, half %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -200,10 +178,8 @@ define @vmfsac_vf_nxv2f16_commute( %a, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -217,11 +193,9 @@ define @vmfsac_vf_nxv2f16_unmasked( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -232,10 +206,8 @@ define @vmfsac_vv_nxv2f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -249,10 +221,8 @@ define @vmfsac_vf_nxv2f16_ta( %a, half %b ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -266,10 +236,8 @@ define @vmfsac_vf_nxv2f16_commute_ta( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -286,10 +254,8 @@ define @vmfsac_vv_nxv4f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -301,11 +267,9 @@ define @vmfsac_vv_nxv4f16_unmasked( %a, < ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -318,10 +282,8 @@ define @vmfsac_vf_nxv4f16( %a, half %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -335,10 +297,8 @@ define @vmfsac_vf_nxv4f16_commute( %a, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -352,11 +312,9 @@ define @vmfsac_vf_nxv4f16_unmasked( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -367,10 +325,8 @@ define @vmfsac_vv_nxv4f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -384,10 +340,8 @@ define @vmfsac_vf_nxv4f16_ta( %a, half %b ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -401,10 +355,8 @@ define @vmfsac_vf_nxv4f16_commute_ta( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -421,10 +373,8 @@ define @vmfsac_vv_nxv8f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -436,11 +386,9 @@ define @vmfsac_vv_nxv8f16_unmasked( %a, < ; CHECK-NEXT: vfmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -453,10 +401,8 @@ define @vmfsac_vf_nxv8f16( %a, half %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -470,10 +416,8 @@ define @vmfsac_vf_nxv8f16_commute( %a, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -487,11 +431,9 @@ define @vmfsac_vf_nxv8f16_unmasked( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -502,10 +444,8 @@ define @vmfsac_vv_nxv8f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -519,10 +459,8 @@ define @vmfsac_vf_nxv8f16_ta( %a, half %b ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -536,10 +474,8 @@ define @vmfsac_vf_nxv8f16_commute_ta( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -556,10 +492,8 @@ define @vmfsac_vv_nxv16f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -571,11 +505,9 @@ define @vmfsac_vv_nxv16f16_unmasked( %a ; CHECK-NEXT: vfmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -588,10 +520,8 @@ define @vmfsac_vf_nxv16f16( %a, half %b ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -605,10 +535,8 @@ define @vmfsac_vf_nxv16f16_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -622,11 +550,9 @@ define @vmfsac_vf_nxv16f16_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -637,10 +563,8 @@ define @vmfsac_vv_nxv16f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -654,10 +578,8 @@ define @vmfsac_vf_nxv16f16_ta( %a, half ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -671,10 +593,8 @@ define @vmfsac_vf_nxv16f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -692,10 +612,8 @@ define @vmfsac_vv_nxv32f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -708,11 +626,9 @@ define @vmfsac_vv_nxv32f16_unmasked( %a ; CHECK-NEXT: vfmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -725,10 +641,8 @@ define @vmfsac_vf_nxv32f16( %a, half %b ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -742,10 +656,8 @@ define @vmfsac_vf_nxv32f16_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -759,11 +671,9 @@ define @vmfsac_vf_nxv32f16_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -775,10 +685,8 @@ define @vmfsac_vv_nxv32f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -792,10 +700,8 @@ define @vmfsac_vf_nxv32f16_ta( %a, half ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -809,10 +715,8 @@ define @vmfsac_vf_nxv32f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -829,10 +733,8 @@ define @vmfsac_vv_nxv1f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -844,11 +746,9 @@ define @vmfsac_vv_nxv1f32_unmasked( %a, ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -861,10 +761,8 @@ define @vmfsac_vf_nxv1f32( %a, float %b ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -878,10 +776,8 @@ define @vmfsac_vf_nxv1f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -895,11 +791,9 @@ define @vmfsac_vf_nxv1f32_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -910,10 +804,8 @@ define @vmfsac_vv_nxv1f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -927,10 +819,8 @@ define @vmfsac_vf_nxv1f32_ta( %a, float ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -944,10 +834,8 @@ define @vmfsac_vf_nxv1f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -964,10 +852,8 @@ define @vmfsac_vv_nxv2f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -979,11 +865,9 @@ define @vmfsac_vv_nxv2f32_unmasked( %a, ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -996,10 +880,8 @@ define @vmfsac_vf_nxv2f32( %a, float %b ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1013,10 +895,8 @@ define @vmfsac_vf_nxv2f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1030,11 +910,9 @@ define @vmfsac_vf_nxv2f32_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1045,10 +923,8 @@ define @vmfsac_vv_nxv2f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1062,10 +938,8 @@ define @vmfsac_vf_nxv2f32_ta( %a, float ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1079,10 +953,8 @@ define @vmfsac_vf_nxv2f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1099,10 +971,8 @@ define @vmfsac_vv_nxv4f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1114,11 +984,9 @@ define @vmfsac_vv_nxv4f32_unmasked( %a, ; CHECK-NEXT: vfmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1131,10 +999,8 @@ define @vmfsac_vf_nxv4f32( %a, float %b ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1148,10 +1014,8 @@ define @vmfsac_vf_nxv4f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1165,11 +1029,9 @@ define @vmfsac_vf_nxv4f32_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1180,10 +1042,8 @@ define @vmfsac_vv_nxv4f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1197,10 +1057,8 @@ define @vmfsac_vf_nxv4f32_ta( %a, float ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1214,10 +1072,8 @@ define @vmfsac_vf_nxv4f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1234,10 +1090,8 @@ define @vmfsac_vv_nxv8f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1249,11 +1103,9 @@ define @vmfsac_vv_nxv8f32_unmasked( %a, ; CHECK-NEXT: vfmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1266,10 +1118,8 @@ define @vmfsac_vf_nxv8f32( %a, float %b ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1283,10 +1133,8 @@ define @vmfsac_vf_nxv8f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1300,11 +1148,9 @@ define @vmfsac_vf_nxv8f32_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1315,10 +1161,8 @@ define @vmfsac_vv_nxv8f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1332,10 +1176,8 @@ define @vmfsac_vf_nxv8f32_ta( %a, float ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1349,10 +1191,8 @@ define @vmfsac_vf_nxv8f32_commute_ta( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1370,10 +1210,8 @@ define @vmfsac_vv_nxv16f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1386,11 +1224,9 @@ define @vmfsac_vv_nxv16f32_unmasked( ; CHECK-NEXT: vfmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1403,10 +1239,8 @@ define @vmfsac_vf_nxv16f32( %a, float ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1420,10 +1254,8 @@ define @vmfsac_vf_nxv16f32_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1437,11 +1269,9 @@ define @vmfsac_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1453,10 +1283,8 @@ define @vmfsac_vv_nxv16f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1470,10 +1298,8 @@ define @vmfsac_vf_nxv16f32_ta( %a, fl ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1487,10 +1313,8 @@ define @vmfsac_vf_nxv16f32_commute_ta( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1507,10 +1331,8 @@ define @vmfsac_vv_nxv1f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1522,11 +1344,9 @@ define @vmfsac_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vfmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1539,10 +1359,8 @@ define @vmfsac_vf_nxv1f64( %a, double ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1556,10 +1374,8 @@ define @vmfsac_vf_nxv1f64_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1573,11 +1389,9 @@ define @vmfsac_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1588,10 +1402,8 @@ define @vmfsac_vv_nxv1f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1605,10 +1417,8 @@ define @vmfsac_vf_nxv1f64_ta( %a, dou ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1622,10 +1432,8 @@ define @vmfsac_vf_nxv1f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1642,10 +1450,8 @@ define @vmfsac_vv_nxv2f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1657,11 +1463,9 @@ define @vmfsac_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vfmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1674,10 +1478,8 @@ define @vmfsac_vf_nxv2f64( %a, double ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1691,10 +1493,8 @@ define @vmfsac_vf_nxv2f64_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1708,11 +1508,9 @@ define @vmfsac_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1723,10 +1521,8 @@ define @vmfsac_vv_nxv2f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1740,10 +1536,8 @@ define @vmfsac_vf_nxv2f64_ta( %a, dou ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1757,10 +1551,8 @@ define @vmfsac_vf_nxv2f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1777,10 +1569,8 @@ define @vmfsac_vv_nxv4f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1792,11 +1582,9 @@ define @vmfsac_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vfmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1809,10 +1597,8 @@ define @vmfsac_vf_nxv4f64( %a, double ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1826,10 +1612,8 @@ define @vmfsac_vf_nxv4f64_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1843,11 +1627,9 @@ define @vmfsac_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1858,10 +1640,8 @@ define @vmfsac_vv_nxv4f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1875,10 +1655,8 @@ define @vmfsac_vf_nxv4f64_ta( %a, dou ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1892,10 +1670,8 @@ define @vmfsac_vf_nxv4f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1913,10 +1689,8 @@ define @vmfsac_vv_nxv8f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1929,11 +1703,9 @@ define @vmfsac_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vfmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %a, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1946,10 +1718,8 @@ define @vmfsac_vf_nxv8f64( %a, double ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1963,10 +1733,8 @@ define @vmfsac_vf_nxv8f64_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1980,11 +1748,9 @@ define @vmfsac_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %a, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1996,10 +1762,8 @@ define @vmfsac_vv_nxv8f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %a, %b, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2013,10 +1777,8 @@ define @vmfsac_vf_nxv8f64_ta( %a, dou ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %a, %vb, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %a, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2030,10 +1792,8 @@ define @vmfsac_vf_nxv8f64_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %a, %negc, %allones, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %a, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll index 518c1eacf401..f7f5e88bf871 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll @@ -564,9 +564,7 @@ define @vfmul_vv_mask_nxv8f32( %va, poison, float 0.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %splat + %vs = select %mask, %vb, splat (float 0.0) %vc = fmul %va, %vs ret %vc } @@ -579,11 +577,9 @@ define @vfmul_vf_mask_nxv8f32( %va, flo ; CHECK-NEXT: vfmerge.vfm v12, v12, fa0, v0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head0 = insertelement poison, float 0.0, i32 0 - %splat0 = shufflevector %head0, poison, zeroinitializer %head1 = insertelement poison, float %b, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer - %vs = select %mask, %splat1, %splat0 + %vs = select %mask, %splat1, splat (float 0.0) %vc = fmul %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index bb9d3cfed300..ee7a7816c5fc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -48,9 +48,7 @@ define @vfmul_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv1f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv1f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -104,9 +102,7 @@ define @vfmul_vf_nxv1f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +146,7 @@ define @vfmul_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv2f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv2f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -206,9 +200,7 @@ define @vfmul_vf_nxv2f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -252,9 +244,7 @@ define @vfmul_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv4f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv4f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +298,7 @@ define @vfmul_vf_nxv4f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +342,7 @@ define @vfmul_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv8f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv8f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +396,7 @@ define @vfmul_vf_nxv8f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -456,9 +440,7 @@ define @vfmul_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv16f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv16f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +494,7 @@ define @vfmul_vf_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -750,9 +730,7 @@ define @vfmul_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv1f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv1f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -776,9 +754,7 @@ define @vfmul_vf_nxv1f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -800,9 +776,7 @@ define @vfmul_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv2f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv2f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -826,9 +800,7 @@ define @vfmul_vf_nxv2f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -850,9 +822,7 @@ define @vfmul_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv4f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv4f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -876,9 +846,7 @@ define @vfmul_vf_nxv4f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -900,9 +868,7 @@ define @vfmul_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv8f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv8f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +892,7 @@ define @vfmul_vf_nxv8f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -950,9 +914,7 @@ define @vfmul_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv16f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv16f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -976,9 +938,7 @@ define @vfmul_vf_nxv16f32_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1000,9 +960,7 @@ define @vfmul_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv1f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv1f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +984,7 @@ define @vfmul_vf_nxv1f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1050,9 +1006,7 @@ define @vfmul_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv2f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv2f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1076,9 +1030,7 @@ define @vfmul_vf_nxv2f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1100,9 +1052,7 @@ define @vfmul_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv4f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv4f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1126,9 +1076,7 @@ define @vfmul_vf_nxv4f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1162,9 +1110,7 @@ define @vfmul_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfmul.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv8f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv8f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1188,8 +1134,6 @@ define @vfmul_vf_nxv8f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll index 582043ffb903..292f27794f37 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll @@ -23,9 +23,7 @@ define @vfma_vv_nxv1f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -61,9 +59,7 @@ define @vfma_vf_nxv1f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -75,9 +71,7 @@ define @vfma_vf_nxv1f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -100,9 +94,7 @@ define @vfma_vv_nxv2f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +130,7 @@ define @vfma_vf_nxv2f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -152,9 +142,7 @@ define @vfma_vf_nxv2f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -177,9 +165,7 @@ define @vfma_vv_nxv4f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -215,9 +201,7 @@ define @vfma_vf_nxv4f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -229,9 +213,7 @@ define @vfma_vf_nxv4f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -254,9 +236,7 @@ define @vfma_vv_nxv8f16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -292,9 +272,7 @@ define @vfma_vf_nxv8f16_unmasked( %va, ha ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -306,9 +284,7 @@ define @vfma_vf_nxv8f16_unmasked_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -331,9 +307,7 @@ define @vfma_vv_nxv16f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -369,9 +343,7 @@ define @vfma_vf_nxv16f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -383,9 +355,7 @@ define @vfma_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +380,7 @@ define @vfma_vv_nxv32f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -448,9 +416,7 @@ define @vfma_vf_nxv32f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -462,9 +428,7 @@ define @vfma_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -487,9 +451,7 @@ define @vfma_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -525,9 +487,7 @@ define @vfma_vf_nxv1f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -539,9 +499,7 @@ define @vfma_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -564,9 +522,7 @@ define @vfma_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -602,9 +558,7 @@ define @vfma_vf_nxv2f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -616,9 +570,7 @@ define @vfma_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -641,9 +593,7 @@ define @vfma_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -679,9 +629,7 @@ define @vfma_vf_nxv4f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -693,9 +641,7 @@ define @vfma_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -718,9 +664,7 @@ define @vfma_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -756,9 +700,7 @@ define @vfma_vf_nxv8f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -770,9 +712,7 @@ define @vfma_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -797,9 +737,7 @@ define @vfma_vv_nxv16f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -835,9 +773,7 @@ define @vfma_vf_nxv16f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -849,9 +785,7 @@ define @vfma_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -874,9 +808,7 @@ define @vfma_vv_nxv1f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -912,9 +844,7 @@ define @vfma_vf_nxv1f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +856,7 @@ define @vfma_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -951,9 +879,7 @@ define @vfma_vv_nxv2f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -989,9 +915,7 @@ define @vfma_vf_nxv2f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1003,9 +927,7 @@ define @vfma_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1028,9 +950,7 @@ define @vfma_vv_nxv4f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1066,9 +986,7 @@ define @vfma_vf_nxv4f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1080,9 +998,7 @@ define @vfma_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1107,9 +1023,7 @@ define @vfma_vv_nxv7f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv7f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv7f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1134,9 +1048,7 @@ define @vfma_vv_nxv8f64_unmasked( %va ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1172,9 +1084,7 @@ define @vfma_vf_nxv8f64_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %vb, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1186,9 +1096,7 @@ define @vfma_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %va, %vc, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1359,9 +1267,7 @@ define @vfma_vv_nxv16f64_unmasked( ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmuladd.nxv16f64( %va, %b, %c, %m, i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f64( %va, %b, %c, splat (i1 true), i32 %evl) ret %v } @@ -1385,10 +1291,8 @@ define @vfmsub_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1426,10 +1330,8 @@ define @vfmsub_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1441,10 +1343,8 @@ define @vfmsub_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1479,11 +1379,9 @@ define @vfnmadd_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1493,11 +1391,9 @@ define @vfnmadd_vv_nxv1f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1537,11 +1433,9 @@ define @vfnmadd_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1553,11 +1447,9 @@ define @vfnmadd_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1597,11 +1489,9 @@ define @vfnmadd_vf_nxv1f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1613,11 +1503,9 @@ define @vfnmadd_vf_nxv1f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1652,11 +1540,9 @@ define @vfnmsub_vv_nxv1f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1666,11 +1552,9 @@ define @vfnmsub_vv_nxv1f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1708,10 +1592,8 @@ define @vfnmsub_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1723,10 +1605,8 @@ define @vfnmsub_vf_nxv1f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1764,10 +1644,8 @@ define @vfnmsub_vf_nxv1f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1779,10 +1657,8 @@ define @vfnmsub_vf_nxv1f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -1806,10 +1682,8 @@ define @vfmsub_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1847,10 +1721,8 @@ define @vfmsub_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1862,10 +1734,8 @@ define @vfmsub_vf_nxv2f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1900,11 +1770,9 @@ define @vfnmadd_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1914,11 +1782,9 @@ define @vfnmadd_vv_nxv2f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -1958,11 +1824,9 @@ define @vfnmadd_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -1974,11 +1838,9 @@ define @vfnmadd_vf_nxv2f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2018,11 +1880,9 @@ define @vfnmadd_vf_nxv2f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2034,11 +1894,9 @@ define @vfnmadd_vf_nxv2f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2073,11 +1931,9 @@ define @vfnmsub_vv_nxv2f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2087,11 +1943,9 @@ define @vfnmsub_vv_nxv2f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2129,10 +1983,8 @@ define @vfnmsub_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2144,10 +1996,8 @@ define @vfnmsub_vf_nxv2f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2185,10 +2035,8 @@ define @vfnmsub_vf_nxv2f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2200,10 +2048,8 @@ define @vfnmsub_vf_nxv2f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2227,10 +2073,8 @@ define @vfmsub_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2268,10 +2112,8 @@ define @vfmsub_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2283,10 +2125,8 @@ define @vfmsub_vf_nxv4f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2321,11 +2161,9 @@ define @vfnmadd_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2335,11 +2173,9 @@ define @vfnmadd_vv_nxv4f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2379,11 +2215,9 @@ define @vfnmadd_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2395,11 +2229,9 @@ define @vfnmadd_vf_nxv4f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2439,11 +2271,9 @@ define @vfnmadd_vf_nxv4f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2455,11 +2285,9 @@ define @vfnmadd_vf_nxv4f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2494,11 +2322,9 @@ define @vfnmsub_vv_nxv4f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2508,11 +2334,9 @@ define @vfnmsub_vv_nxv4f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2550,10 +2374,8 @@ define @vfnmsub_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2565,10 +2387,8 @@ define @vfnmsub_vf_nxv4f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2606,10 +2426,8 @@ define @vfnmsub_vf_nxv4f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2621,10 +2439,8 @@ define @vfnmsub_vf_nxv4f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2648,10 +2464,8 @@ define @vfmsub_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2689,10 +2503,8 @@ define @vfmsub_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2704,10 +2516,8 @@ define @vfmsub_vf_nxv8f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2742,11 +2552,9 @@ define @vfnmadd_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2756,11 +2564,9 @@ define @vfnmadd_vv_nxv8f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2800,11 +2606,9 @@ define @vfnmadd_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2816,11 +2620,9 @@ define @vfnmadd_vf_nxv8f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2860,11 +2662,9 @@ define @vfnmadd_vf_nxv8f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2876,11 +2676,9 @@ define @vfnmadd_vf_nxv8f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -2915,11 +2713,9 @@ define @vfnmsub_vv_nxv8f16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2929,11 +2725,9 @@ define @vfnmsub_vv_nxv8f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -2971,10 +2765,8 @@ define @vfnmsub_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -2986,10 +2778,8 @@ define @vfnmsub_vf_nxv8f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3027,10 +2817,8 @@ define @vfnmsub_vf_nxv8f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3042,10 +2830,8 @@ define @vfnmsub_vf_nxv8f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3069,10 +2855,8 @@ define @vfmsub_vv_nxv16f16_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3110,10 +2894,8 @@ define @vfmsub_vf_nxv16f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3125,10 +2907,8 @@ define @vfmsub_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3163,11 +2943,9 @@ define @vfnmadd_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3177,11 +2955,9 @@ define @vfnmadd_vv_nxv16f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3221,11 +2997,9 @@ define @vfnmadd_vf_nxv16f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3237,11 +3011,9 @@ define @vfnmadd_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3281,11 +3053,9 @@ define @vfnmadd_vf_nxv16f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3297,11 +3067,9 @@ define @vfnmadd_vf_nxv16f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3336,11 +3104,9 @@ define @vfnmsub_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3350,11 +3116,9 @@ define @vfnmsub_vv_nxv16f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3392,10 +3156,8 @@ define @vfnmsub_vf_nxv16f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3407,10 +3169,8 @@ define @vfnmsub_vf_nxv16f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3448,10 +3208,8 @@ define @vfnmsub_vf_nxv16f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3463,10 +3221,8 @@ define @vfnmsub_vf_nxv16f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3492,10 +3248,8 @@ define @vfmsub_vv_nxv32f16_unmasked( %v ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3533,10 +3287,8 @@ define @vfmsub_vf_nxv32f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3548,10 +3300,8 @@ define @vfmsub_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3589,11 +3339,9 @@ define @vfnmadd_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3604,11 +3352,9 @@ define @vfnmadd_vv_nxv32f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3648,11 +3394,9 @@ define @vfnmadd_vf_nxv32f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3664,11 +3408,9 @@ define @vfnmadd_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3708,11 +3450,9 @@ define @vfnmadd_vf_nxv32f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3724,11 +3464,9 @@ define @vfnmadd_vf_nxv32f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv32f16( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv32f16( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3766,11 +3504,9 @@ define @vfnmsub_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3781,11 +3517,9 @@ define @vfnmsub_vv_nxv32f16_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv32f16( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv32f16( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3823,10 +3557,8 @@ define @vfnmsub_vf_nxv32f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3838,10 +3570,8 @@ define @vfnmsub_vf_nxv32f16_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3879,10 +3609,8 @@ define @vfnmsub_vf_nxv32f16_neg_splat_unmasked( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3894,10 +3622,8 @@ define @vfnmsub_vf_nxv32f16_neg_splat_unmasked_commute( poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv32f16( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv32f16( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv32f16( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv32f16( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -3921,10 +3647,8 @@ define @vfmsub_vv_nxv1f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -3962,10 +3686,8 @@ define @vfmsub_vf_nxv1f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -3977,10 +3699,8 @@ define @vfmsub_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4015,11 +3735,9 @@ define @vfnmadd_vv_nxv1f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4029,11 +3747,9 @@ define @vfnmadd_vv_nxv1f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4073,11 +3789,9 @@ define @vfnmadd_vf_nxv1f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4089,11 +3803,9 @@ define @vfnmadd_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4133,11 +3845,9 @@ define @vfnmadd_vf_nxv1f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4149,11 +3859,9 @@ define @vfnmadd_vf_nxv1f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4188,11 +3896,9 @@ define @vfnmsub_vv_nxv1f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4202,11 +3908,9 @@ define @vfnmsub_vv_nxv1f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4244,10 +3948,8 @@ define @vfnmsub_vf_nxv1f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4259,10 +3961,8 @@ define @vfnmsub_vf_nxv1f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4300,10 +4000,8 @@ define @vfnmsub_vf_nxv1f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4315,10 +4013,8 @@ define @vfnmsub_vf_nxv1f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4342,10 +4038,8 @@ define @vfmsub_vv_nxv2f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4383,10 +4077,8 @@ define @vfmsub_vf_nxv2f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4398,10 +4090,8 @@ define @vfmsub_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4436,11 +4126,9 @@ define @vfnmadd_vv_nxv2f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4450,11 +4138,9 @@ define @vfnmadd_vv_nxv2f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4494,11 +4180,9 @@ define @vfnmadd_vf_nxv2f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4510,11 +4194,9 @@ define @vfnmadd_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4554,11 +4236,9 @@ define @vfnmadd_vf_nxv2f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4570,11 +4250,9 @@ define @vfnmadd_vf_nxv2f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4609,11 +4287,9 @@ define @vfnmsub_vv_nxv2f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4623,11 +4299,9 @@ define @vfnmsub_vv_nxv2f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4665,10 +4339,8 @@ define @vfnmsub_vf_nxv2f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4680,10 +4352,8 @@ define @vfnmsub_vf_nxv2f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4721,10 +4391,8 @@ define @vfnmsub_vf_nxv2f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4736,10 +4404,8 @@ define @vfnmsub_vf_nxv2f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -4763,10 +4429,8 @@ define @vfmsub_vv_nxv4f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4804,10 +4468,8 @@ define @vfmsub_vf_nxv4f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4819,10 +4481,8 @@ define @vfmsub_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4857,11 +4517,9 @@ define @vfnmadd_vv_nxv4f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4871,11 +4529,9 @@ define @vfnmadd_vv_nxv4f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -4915,11 +4571,9 @@ define @vfnmadd_vf_nxv4f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4931,11 +4585,9 @@ define @vfnmadd_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4975,11 +4627,9 @@ define @vfnmadd_vf_nxv4f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -4991,11 +4641,9 @@ define @vfnmadd_vf_nxv4f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5030,11 +4678,9 @@ define @vfnmsub_vv_nxv4f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5044,11 +4690,9 @@ define @vfnmsub_vv_nxv4f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5086,10 +4730,8 @@ define @vfnmsub_vf_nxv4f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5101,10 +4743,8 @@ define @vfnmsub_vf_nxv4f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5142,10 +4782,8 @@ define @vfnmsub_vf_nxv4f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5157,10 +4795,8 @@ define @vfnmsub_vf_nxv4f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5184,10 +4820,8 @@ define @vfmsub_vv_nxv8f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5225,10 +4859,8 @@ define @vfmsub_vf_nxv8f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5240,10 +4872,8 @@ define @vfmsub_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5278,11 +4908,9 @@ define @vfnmadd_vv_nxv8f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5292,11 +4920,9 @@ define @vfnmadd_vv_nxv8f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5336,11 +4962,9 @@ define @vfnmadd_vf_nxv8f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5352,11 +4976,9 @@ define @vfnmadd_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5396,11 +5018,9 @@ define @vfnmadd_vf_nxv8f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5412,11 +5032,9 @@ define @vfnmadd_vf_nxv8f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5451,11 +5069,9 @@ define @vfnmsub_vv_nxv8f32_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5465,11 +5081,9 @@ define @vfnmsub_vv_nxv8f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5507,10 +5121,8 @@ define @vfnmsub_vf_nxv8f32_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5522,10 +5134,8 @@ define @vfnmsub_vf_nxv8f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5563,10 +5173,8 @@ define @vfnmsub_vf_nxv8f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5578,10 +5186,8 @@ define @vfnmsub_vf_nxv8f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5607,10 +5213,8 @@ define @vfmsub_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5648,10 +5252,8 @@ define @vfmsub_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5663,10 +5265,8 @@ define @vfmsub_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5704,11 +5304,9 @@ define @vfnmadd_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5719,11 +5317,9 @@ define @vfnmadd_vv_nxv16f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5763,11 +5359,9 @@ define @vfnmadd_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5779,11 +5373,9 @@ define @vfnmadd_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5823,11 +5415,9 @@ define @vfnmadd_vf_nxv16f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5839,11 +5429,9 @@ define @vfnmadd_vf_nxv16f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv16f32( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv16f32( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -5881,11 +5469,9 @@ define @vfnmsub_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5896,11 +5482,9 @@ define @vfnmsub_vv_nxv16f32_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv16f32( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv16f32( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -5938,10 +5522,8 @@ define @vfnmsub_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5953,10 +5535,8 @@ define @vfnmsub_vf_nxv16f32_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -5994,10 +5574,8 @@ define @vfnmsub_vf_nxv16f32_neg_splat_unmasked( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6009,10 +5587,8 @@ define @vfnmsub_vf_nxv16f32_neg_splat_unmasked_commute( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv16f32( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv16f32( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv16f32( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv16f32( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6036,10 +5612,8 @@ define @vfmsub_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6077,10 +5651,8 @@ define @vfmsub_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6092,10 +5664,8 @@ define @vfmsub_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6130,11 +5700,9 @@ define @vfnmadd_vv_nxv1f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6144,11 +5712,9 @@ define @vfnmadd_vv_nxv1f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6188,11 +5754,9 @@ define @vfnmadd_vf_nxv1f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6204,11 +5768,9 @@ define @vfnmadd_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6248,11 +5810,9 @@ define @vfnmadd_vf_nxv1f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6264,11 +5824,9 @@ define @vfnmadd_vf_nxv1f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv1f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv1f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6303,11 +5861,9 @@ define @vfnmsub_vv_nxv1f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6317,11 +5873,9 @@ define @vfnmsub_vv_nxv1f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv1f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv1f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6359,10 +5913,8 @@ define @vfnmsub_vf_nxv1f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6374,10 +5926,8 @@ define @vfnmsub_vf_nxv1f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6415,10 +5965,8 @@ define @vfnmsub_vf_nxv1f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6430,10 +5978,8 @@ define @vfnmsub_vf_nxv1f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv1f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv1f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv1f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv1f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6457,10 +6003,8 @@ define @vfmsub_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6498,10 +6042,8 @@ define @vfmsub_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6513,10 +6055,8 @@ define @vfmsub_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6551,11 +6091,9 @@ define @vfnmadd_vv_nxv2f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6565,11 +6103,9 @@ define @vfnmadd_vv_nxv2f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6609,11 +6145,9 @@ define @vfnmadd_vf_nxv2f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6625,11 +6159,9 @@ define @vfnmadd_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6669,11 +6201,9 @@ define @vfnmadd_vf_nxv2f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6685,11 +6215,9 @@ define @vfnmadd_vf_nxv2f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv2f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv2f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6724,11 +6252,9 @@ define @vfnmsub_vv_nxv2f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6738,11 +6264,9 @@ define @vfnmsub_vv_nxv2f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv2f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv2f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6780,10 +6304,8 @@ define @vfnmsub_vf_nxv2f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6795,10 +6317,8 @@ define @vfnmsub_vf_nxv2f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6836,10 +6356,8 @@ define @vfnmsub_vf_nxv2f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6851,10 +6369,8 @@ define @vfnmsub_vf_nxv2f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv2f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv2f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv2f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv2f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -6878,10 +6394,8 @@ define @vfmsub_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6919,10 +6433,8 @@ define @vfmsub_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6934,10 +6446,8 @@ define @vfmsub_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -6972,11 +6482,9 @@ define @vfnmadd_vv_nxv4f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -6986,11 +6494,9 @@ define @vfnmadd_vv_nxv4f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7030,11 +6536,9 @@ define @vfnmadd_vf_nxv4f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7046,11 +6550,9 @@ define @vfnmadd_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7090,11 +6592,9 @@ define @vfnmadd_vf_nxv4f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7106,11 +6606,9 @@ define @vfnmadd_vf_nxv4f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv4f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv4f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7145,11 +6643,9 @@ define @vfnmsub_vv_nxv4f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7159,11 +6655,9 @@ define @vfnmsub_vv_nxv4f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv4f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv4f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7201,10 +6695,8 @@ define @vfnmsub_vf_nxv4f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7216,10 +6708,8 @@ define @vfnmsub_vf_nxv4f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7257,10 +6747,8 @@ define @vfnmsub_vf_nxv4f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7272,10 +6760,8 @@ define @vfnmsub_vf_nxv4f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv4f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv4f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv4f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv4f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7301,10 +6787,8 @@ define @vfmsub_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfmsub.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %b, %negc, %m, i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %b, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7342,10 +6826,8 @@ define @vfmsub_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %vb, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7357,10 +6839,8 @@ define @vfmsub_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %va, %negvc, %m, i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7398,11 +6878,9 @@ define @vfnmadd_vv_nxv8f64_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7413,11 +6891,9 @@ define @vfnmadd_vv_nxv8f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7457,11 +6933,9 @@ define @vfnmadd_vf_nxv8f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %negva, %vb, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %negva, %vb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7473,11 +6947,9 @@ define @vfnmadd_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %negva, %negvc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %negva, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7517,11 +6989,9 @@ define @vfnmadd_vf_nxv8f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negvb, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negvb, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7533,11 +7003,9 @@ define @vfnmadd_vf_nxv8f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %negvc = call @llvm.vp.fneg.nxv8f64( %vc, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %negvb, %va, %negvc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %negvc = call @llvm.vp.fneg.nxv8f64( %vc, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %negvb, %va, %negvc, splat (i1 true), i32 %evl) ret %v } @@ -7575,11 +7043,9 @@ define @vfnmsub_vv_nxv8f64_unmasked( ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vfnmadd.vv v8, v16, v24 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negb, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negb, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7590,11 +7056,9 @@ define @vfnmsub_vv_nxv8f64_unmasked_commuted( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negb = call @llvm.vp.fneg.nxv8f64( %b, %m, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %negb, %va, %negc, %m, i32 %evl) + %negb = call @llvm.vp.fneg.nxv8f64( %b, splat (i1 true), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %negb, %va, %negc, splat (i1 true), i32 %evl) ret %v } @@ -7632,10 +7096,8 @@ define @vfnmsub_vf_nxv8f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %negva, %vb, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %negva, %vb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7647,10 +7109,8 @@ define @vfnmsub_vf_nxv8f64_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negva = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %negva, %vc, %m, i32 %evl) + %negva = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %vb, %negva, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7688,10 +7148,8 @@ define @vfnmsub_vf_nxv8f64_neg_splat_unmasked( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negvb, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %va, %negvb, %vc, splat (i1 true), i32 %evl) ret %v } @@ -7703,9 +7161,7 @@ define @vfnmsub_vf_nxv8f64_neg_splat_unmasked_commute( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %negvb = call @llvm.vp.fneg.nxv8f64( %vb, %m, i32 %evl) - %v = call @llvm.vp.fmuladd.nxv8f64( %negvb, %va, %vc, %m, i32 %evl) + %negvb = call @llvm.vp.fneg.nxv8f64( %vb, splat (i1 true), i32 %evl) + %v = call @llvm.vp.fmuladd.nxv8f64( %negvb, %va, %vc, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll index ef08865100f1..47a832af15e2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll @@ -46,9 +46,7 @@ define @vfneg_vv_nxv1f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -90,9 +88,7 @@ define @vfneg_vv_nxv2f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -134,9 +130,7 @@ define @vfneg_vv_nxv4f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -178,9 +172,7 @@ define @vfneg_vv_nxv8f16_unmasked( %va, i ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +214,7 @@ define @vfneg_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -330,9 +320,7 @@ define @vfneg_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +342,7 @@ define @vfneg_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -378,9 +364,7 @@ define @vfneg_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -402,9 +386,7 @@ define @vfneg_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -426,9 +408,7 @@ define @vfneg_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -450,9 +430,7 @@ define @vfneg_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -474,9 +452,7 @@ define @vfneg_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -498,9 +474,7 @@ define @vfneg_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -522,9 +496,7 @@ define @vfneg_vv_nxv7f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -546,9 +518,7 @@ define @vfneg_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -598,8 +568,6 @@ define @vfneg_vv_nxv16f64_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfneg.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll index e642e89b3dff..ee3ed603ff6d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll @@ -16,11 +16,9 @@ define @vfnmacc_vv_nxv1f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -32,12 +30,10 @@ define @vfnmacc_vv_nxv1f16_unmasked( %a, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -50,11 +46,9 @@ define @vfnmacc_vf_nxv1f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -68,11 +62,9 @@ define @vfnmacc_vf_nxv1f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -86,12 +78,10 @@ define @vfnmacc_vf_nxv1f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -102,11 +92,9 @@ define @vfnmacc_vv_nxv1f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -120,11 +108,9 @@ define @vfnmacc_vf_nxv1f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -138,11 +124,9 @@ define @vfnmacc_vf_nxv1f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -159,11 +143,9 @@ define @vfnmacc_vv_nxv2f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -175,12 +157,10 @@ define @vfnmacc_vv_nxv2f16_unmasked( %a, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -193,11 +173,9 @@ define @vfnmacc_vf_nxv2f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -211,11 +189,9 @@ define @vfnmacc_vf_nxv2f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -229,12 +205,10 @@ define @vfnmacc_vf_nxv2f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -245,11 +219,9 @@ define @vfnmacc_vv_nxv2f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -263,11 +235,9 @@ define @vfnmacc_vf_nxv2f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -281,11 +251,9 @@ define @vfnmacc_vf_nxv2f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -302,11 +270,9 @@ define @vfnmacc_vv_nxv4f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -318,12 +284,10 @@ define @vfnmacc_vv_nxv4f16_unmasked( %a, ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -336,11 +300,9 @@ define @vfnmacc_vf_nxv4f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -354,11 +316,9 @@ define @vfnmacc_vf_nxv4f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -372,12 +332,10 @@ define @vfnmacc_vf_nxv4f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -388,11 +346,9 @@ define @vfnmacc_vv_nxv4f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -406,11 +362,9 @@ define @vfnmacc_vf_nxv4f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -424,11 +378,9 @@ define @vfnmacc_vf_nxv4f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -445,11 +397,9 @@ define @vfnmacc_vv_nxv8f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -461,12 +411,10 @@ define @vfnmacc_vv_nxv8f16_unmasked( %a, ; CHECK-NEXT: vfnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -479,11 +427,9 @@ define @vfnmacc_vf_nxv8f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -497,11 +443,9 @@ define @vfnmacc_vf_nxv8f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -515,12 +459,10 @@ define @vfnmacc_vf_nxv8f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -531,11 +473,9 @@ define @vfnmacc_vv_nxv8f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -549,11 +489,9 @@ define @vfnmacc_vf_nxv8f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -567,11 +505,9 @@ define @vfnmacc_vf_nxv8f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -588,11 +524,9 @@ define @vfnmacc_vv_nxv16f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -604,12 +538,10 @@ define @vfnmacc_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vfnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -622,11 +554,9 @@ define @vfnmacc_vf_nxv16f16( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -640,11 +570,9 @@ define @vfnmacc_vf_nxv16f16_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -658,12 +586,10 @@ define @vfnmacc_vf_nxv16f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -674,11 +600,9 @@ define @vfnmacc_vv_nxv16f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -692,11 +616,9 @@ define @vfnmacc_vf_nxv16f16_ta( %a, hal ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -710,11 +632,9 @@ define @vfnmacc_vf_nxv16f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -732,11 +652,9 @@ define @vfnmacc_vv_nxv32f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -749,12 +667,10 @@ define @vfnmacc_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vfnmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -767,11 +683,9 @@ define @vfnmacc_vf_nxv32f16( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -785,11 +699,9 @@ define @vfnmacc_vf_nxv32f16_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -803,12 +715,10 @@ define @vfnmacc_vf_nxv32f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -820,11 +730,9 @@ define @vfnmacc_vv_nxv32f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -838,11 +746,9 @@ define @vfnmacc_vf_nxv32f16_ta( %a, hal ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -856,11 +762,9 @@ define @vfnmacc_vf_nxv32f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv32f16( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv32f16( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -877,11 +781,9 @@ define @vfnmacc_vv_nxv1f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -893,12 +795,10 @@ define @vfnmacc_vv_nxv1f32_unmasked( %a ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -911,11 +811,9 @@ define @vfnmacc_vf_nxv1f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -929,11 +827,9 @@ define @vfnmacc_vf_nxv1f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -947,12 +843,10 @@ define @vfnmacc_vf_nxv1f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -963,11 +857,9 @@ define @vfnmacc_vv_nxv1f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -981,11 +873,9 @@ define @vfnmacc_vf_nxv1f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -999,11 +889,9 @@ define @vfnmacc_vf_nxv1f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -1020,11 +908,9 @@ define @vfnmacc_vv_nxv2f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1036,12 +922,10 @@ define @vfnmacc_vv_nxv2f32_unmasked( %a ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1054,11 +938,9 @@ define @vfnmacc_vf_nxv2f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1072,11 +954,9 @@ define @vfnmacc_vf_nxv2f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1090,12 +970,10 @@ define @vfnmacc_vf_nxv2f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1106,11 +984,9 @@ define @vfnmacc_vv_nxv2f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1124,11 +1000,9 @@ define @vfnmacc_vf_nxv2f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1142,11 +1016,9 @@ define @vfnmacc_vf_nxv2f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1163,11 +1035,9 @@ define @vfnmacc_vv_nxv4f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1179,12 +1049,10 @@ define @vfnmacc_vv_nxv4f32_unmasked( %a ; CHECK-NEXT: vfnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1197,11 +1065,9 @@ define @vfnmacc_vf_nxv4f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1215,11 +1081,9 @@ define @vfnmacc_vf_nxv4f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1233,12 +1097,10 @@ define @vfnmacc_vf_nxv4f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1249,11 +1111,9 @@ define @vfnmacc_vv_nxv4f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1267,11 +1127,9 @@ define @vfnmacc_vf_nxv4f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1285,11 +1143,9 @@ define @vfnmacc_vf_nxv4f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1306,11 +1162,9 @@ define @vfnmacc_vv_nxv8f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1322,12 +1176,10 @@ define @vfnmacc_vv_nxv8f32_unmasked( %a ; CHECK-NEXT: vfnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1340,11 +1192,9 @@ define @vfnmacc_vf_nxv8f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1358,11 +1208,9 @@ define @vfnmacc_vf_nxv8f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1376,12 +1224,10 @@ define @vfnmacc_vf_nxv8f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1392,11 +1238,9 @@ define @vfnmacc_vv_nxv8f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1410,11 +1254,9 @@ define @vfnmacc_vf_nxv8f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1428,11 +1270,9 @@ define @vfnmacc_vf_nxv8f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1450,11 +1290,9 @@ define @vfnmacc_vv_nxv16f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1467,12 +1305,10 @@ define @vfnmacc_vv_nxv16f32_unmasked( ; CHECK-NEXT: vfnmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1485,11 +1321,9 @@ define @vfnmacc_vf_nxv16f32( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1503,11 +1337,9 @@ define @vfnmacc_vf_nxv16f32_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1521,12 +1353,10 @@ define @vfnmacc_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1538,11 +1368,9 @@ define @vfnmacc_vv_nxv16f32_ta( %a, < ; CHECK-NEXT: vfnmacc.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1556,11 +1384,9 @@ define @vfnmacc_vf_nxv16f32_ta( %a, f ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1574,11 +1400,9 @@ define @vfnmacc_vf_nxv16f32_commute_ta( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1595,11 +1419,9 @@ define @vfnmacc_vv_nxv1f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1611,12 +1433,10 @@ define @vfnmacc_vv_nxv1f64_unmasked( ; CHECK-NEXT: vfnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1629,11 +1449,9 @@ define @vfnmacc_vf_nxv1f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1647,11 +1465,9 @@ define @vfnmacc_vf_nxv1f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1665,12 +1481,10 @@ define @vfnmacc_vf_nxv1f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1681,11 +1495,9 @@ define @vfnmacc_vv_nxv1f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1699,11 +1511,9 @@ define @vfnmacc_vf_nxv1f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1717,11 +1527,9 @@ define @vfnmacc_vf_nxv1f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1738,11 +1546,9 @@ define @vfnmacc_vv_nxv2f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1754,12 +1560,10 @@ define @vfnmacc_vv_nxv2f64_unmasked( ; CHECK-NEXT: vfnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1772,11 +1576,9 @@ define @vfnmacc_vf_nxv2f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1790,11 +1592,9 @@ define @vfnmacc_vf_nxv2f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1808,12 +1608,10 @@ define @vfnmacc_vf_nxv2f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1824,11 +1622,9 @@ define @vfnmacc_vv_nxv2f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1842,11 +1638,9 @@ define @vfnmacc_vf_nxv2f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1860,11 +1654,9 @@ define @vfnmacc_vf_nxv2f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1881,11 +1673,9 @@ define @vfnmacc_vv_nxv4f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1897,12 +1687,10 @@ define @vfnmacc_vv_nxv4f64_unmasked( ; CHECK-NEXT: vfnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1915,11 +1703,9 @@ define @vfnmacc_vf_nxv4f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1933,11 +1719,9 @@ define @vfnmacc_vf_nxv4f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1951,12 +1735,10 @@ define @vfnmacc_vf_nxv4f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1967,11 +1749,9 @@ define @vfnmacc_vv_nxv4f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1985,11 +1765,9 @@ define @vfnmacc_vf_nxv4f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -2003,11 +1781,9 @@ define @vfnmacc_vf_nxv4f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -2025,11 +1801,9 @@ define @vfnmacc_vv_nxv8f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2042,12 +1816,10 @@ define @vfnmacc_vv_nxv8f64_unmasked( ; CHECK-NEXT: vfnmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -2060,11 +1832,9 @@ define @vfnmacc_vf_nxv8f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2078,11 +1848,9 @@ define @vfnmacc_vf_nxv8f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2096,12 +1864,10 @@ define @vfnmacc_vf_nxv8f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -2113,11 +1879,9 @@ define @vfnmacc_vv_nxv8f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2131,11 +1895,9 @@ define @vfnmacc_vf_nxv8f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2149,11 +1911,9 @@ define @vfnmacc_vf_nxv8f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %negc, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll index d906b6450a93..14dba24daf5f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll @@ -16,10 +16,8 @@ define @vfnmsac_vv_nxv1f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -31,11 +29,9 @@ define @vfnmsac_vv_nxv1f16_unmasked( %a, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -48,10 +44,8 @@ define @vfnmsac_vf_nxv1f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -65,10 +59,8 @@ define @vfnmsac_vf_nxv1f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -82,11 +74,9 @@ define @vfnmsac_vf_nxv1f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -97,10 +87,8 @@ define @vfnmsac_vv_nxv1f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -114,10 +102,8 @@ define @vfnmsac_vf_nxv1f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -131,10 +117,8 @@ define @vfnmsac_vf_nxv1f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f16( %m, %v, %c, i32 %evl) ret %u } @@ -151,10 +135,8 @@ define @vfnmsac_vv_nxv2f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -166,11 +148,9 @@ define @vfnmsac_vv_nxv2f16_unmasked( %a, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -183,10 +163,8 @@ define @vfnmsac_vf_nxv2f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -200,10 +178,8 @@ define @vfnmsac_vf_nxv2f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -217,11 +193,9 @@ define @vfnmsac_vf_nxv2f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -232,10 +206,8 @@ define @vfnmsac_vv_nxv2f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -249,10 +221,8 @@ define @vfnmsac_vf_nxv2f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -266,10 +236,8 @@ define @vfnmsac_vf_nxv2f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f16( %m, %v, %c, i32 %evl) ret %u } @@ -286,10 +254,8 @@ define @vfnmsac_vv_nxv4f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -301,11 +267,9 @@ define @vfnmsac_vv_nxv4f16_unmasked( %a, ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -318,10 +282,8 @@ define @vfnmsac_vf_nxv4f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -335,10 +297,8 @@ define @vfnmsac_vf_nxv4f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -352,11 +312,9 @@ define @vfnmsac_vf_nxv4f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -367,10 +325,8 @@ define @vfnmsac_vv_nxv4f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -384,10 +340,8 @@ define @vfnmsac_vf_nxv4f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -401,10 +355,8 @@ define @vfnmsac_vf_nxv4f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f16( %m, %v, %c, i32 %evl) ret %u } @@ -421,10 +373,8 @@ define @vfnmsac_vv_nxv8f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -436,11 +386,9 @@ define @vfnmsac_vv_nxv8f16_unmasked( %a, ; CHECK-NEXT: vfnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -453,10 +401,8 @@ define @vfnmsac_vf_nxv8f16( %a, half %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -470,10 +416,8 @@ define @vfnmsac_vf_nxv8f16_commute( %a, h ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -487,11 +431,9 @@ define @vfnmsac_vf_nxv8f16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -502,10 +444,8 @@ define @vfnmsac_vv_nxv8f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -519,10 +459,8 @@ define @vfnmsac_vf_nxv8f16_ta( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -536,10 +474,8 @@ define @vfnmsac_vf_nxv8f16_commute_ta( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f16( %m, %v, %c, i32 %evl) ret %u } @@ -556,10 +492,8 @@ define @vfnmsac_vv_nxv16f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -571,11 +505,9 @@ define @vfnmsac_vv_nxv16f16_unmasked( % ; CHECK-NEXT: vfnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -588,10 +520,8 @@ define @vfnmsac_vf_nxv16f16( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -605,10 +535,8 @@ define @vfnmsac_vf_nxv16f16_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -622,11 +550,9 @@ define @vfnmsac_vf_nxv16f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -637,10 +563,8 @@ define @vfnmsac_vv_nxv16f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -654,10 +578,8 @@ define @vfnmsac_vf_nxv16f16_ta( %a, hal ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -671,10 +593,8 @@ define @vfnmsac_vf_nxv16f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f16( %m, %v, %c, i32 %evl) ret %u } @@ -692,10 +612,8 @@ define @vfnmsac_vv_nxv32f16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -708,11 +626,9 @@ define @vfnmsac_vv_nxv32f16_unmasked( % ; CHECK-NEXT: vfnmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -725,10 +641,8 @@ define @vfnmsac_vf_nxv32f16( %a, half % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -742,10 +656,8 @@ define @vfnmsac_vf_nxv32f16_commute( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -759,11 +671,9 @@ define @vfnmsac_vf_nxv32f16_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32f16( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32f16( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -775,10 +685,8 @@ define @vfnmsac_vv_nxv32f16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -792,10 +700,8 @@ define @vfnmsac_vf_nxv32f16_ta( %a, hal ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -809,10 +715,8 @@ define @vfnmsac_vf_nxv32f16_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv32f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv32f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv32f16( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32f16( %m, %v, %c, i32 %evl) ret %u } @@ -829,10 +733,8 @@ define @vfnmsac_vv_nxv1f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -844,11 +746,9 @@ define @vfnmsac_vv_nxv1f32_unmasked( %a ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -861,10 +761,8 @@ define @vfnmsac_vf_nxv1f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -878,10 +776,8 @@ define @vfnmsac_vf_nxv1f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -895,11 +791,9 @@ define @vfnmsac_vf_nxv1f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -910,10 +804,8 @@ define @vfnmsac_vv_nxv1f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -927,10 +819,8 @@ define @vfnmsac_vf_nxv1f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -944,10 +834,8 @@ define @vfnmsac_vf_nxv1f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -964,10 +852,8 @@ define @vfnmsac_vv_nxv2f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -979,11 +865,9 @@ define @vfnmsac_vv_nxv2f32_unmasked( %a ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -996,10 +880,8 @@ define @vfnmsac_vf_nxv2f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1013,10 +895,8 @@ define @vfnmsac_vf_nxv2f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1030,11 +910,9 @@ define @vfnmsac_vf_nxv2f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1045,10 +923,8 @@ define @vfnmsac_vv_nxv2f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1062,10 +938,8 @@ define @vfnmsac_vf_nxv2f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1079,10 +953,8 @@ define @vfnmsac_vf_nxv2f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f32( %m, %v, %c, i32 %evl) ret %u } @@ -1099,10 +971,8 @@ define @vfnmsac_vv_nxv4f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1114,11 +984,9 @@ define @vfnmsac_vv_nxv4f32_unmasked( %a ; CHECK-NEXT: vfnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1131,10 +999,8 @@ define @vfnmsac_vf_nxv4f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1148,10 +1014,8 @@ define @vfnmsac_vf_nxv4f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1165,11 +1029,9 @@ define @vfnmsac_vf_nxv4f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1180,10 +1042,8 @@ define @vfnmsac_vv_nxv4f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1197,10 +1057,8 @@ define @vfnmsac_vf_nxv4f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1214,10 +1072,8 @@ define @vfnmsac_vf_nxv4f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f32( %m, %v, %c, i32 %evl) ret %u } @@ -1234,10 +1090,8 @@ define @vfnmsac_vv_nxv8f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1249,11 +1103,9 @@ define @vfnmsac_vv_nxv8f32_unmasked( %a ; CHECK-NEXT: vfnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1266,10 +1118,8 @@ define @vfnmsac_vf_nxv8f32( %a, float % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1283,10 +1133,8 @@ define @vfnmsac_vf_nxv8f32_commute( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1300,11 +1148,9 @@ define @vfnmsac_vf_nxv8f32_unmasked( %a ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1315,10 +1161,8 @@ define @vfnmsac_vv_nxv8f32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1332,10 +1176,8 @@ define @vfnmsac_vf_nxv8f32_ta( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1349,10 +1191,8 @@ define @vfnmsac_vf_nxv8f32_commute_ta( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f32( %m, %v, %c, i32 %evl) ret %u } @@ -1370,10 +1210,8 @@ define @vfnmsac_vv_nxv16f32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1386,11 +1224,9 @@ define @vfnmsac_vv_nxv16f32_unmasked( ; CHECK-NEXT: vfnmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1403,10 +1239,8 @@ define @vfnmsac_vf_nxv16f32( %a, floa ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1420,10 +1254,8 @@ define @vfnmsac_vf_nxv16f32_commute( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1437,11 +1269,9 @@ define @vfnmsac_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16f32( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1453,10 +1283,8 @@ define @vfnmsac_vv_nxv16f32_ta( %a, < ; CHECK-NEXT: vfnmsac.vv v24, v8, v16, v0.t ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1470,10 +1298,8 @@ define @vfnmsac_vf_nxv16f32_ta( %a, f ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1487,10 +1313,8 @@ define @vfnmsac_vf_nxv16f32_commute_ta( poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv16f32( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16f32( %m, %v, %c, i32 %evl) ret %u } @@ -1507,10 +1331,8 @@ define @vfnmsac_vv_nxv1f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1522,11 +1344,9 @@ define @vfnmsac_vv_nxv1f64_unmasked( ; CHECK-NEXT: vfnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1539,10 +1359,8 @@ define @vfnmsac_vf_nxv1f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1556,10 +1374,8 @@ define @vfnmsac_vf_nxv1f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1573,11 +1389,9 @@ define @vfnmsac_vf_nxv1f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1588,10 +1402,8 @@ define @vfnmsac_vv_nxv1f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1605,10 +1417,8 @@ define @vfnmsac_vf_nxv1f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1622,10 +1432,8 @@ define @vfnmsac_vf_nxv1f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv1f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1f64( %m, %v, %c, i32 %evl) ret %u } @@ -1642,10 +1450,8 @@ define @vfnmsac_vv_nxv2f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1657,11 +1463,9 @@ define @vfnmsac_vv_nxv2f64_unmasked( ; CHECK-NEXT: vfnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1674,10 +1478,8 @@ define @vfnmsac_vf_nxv2f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1691,10 +1493,8 @@ define @vfnmsac_vf_nxv2f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1708,11 +1508,9 @@ define @vfnmsac_vf_nxv2f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1723,10 +1521,8 @@ define @vfnmsac_vv_nxv2f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1740,10 +1536,8 @@ define @vfnmsac_vf_nxv2f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1757,10 +1551,8 @@ define @vfnmsac_vf_nxv2f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv2f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2f64( %m, %v, %c, i32 %evl) ret %u } @@ -1777,10 +1569,8 @@ define @vfnmsac_vv_nxv4f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1792,11 +1582,9 @@ define @vfnmsac_vv_nxv4f64_unmasked( ; CHECK-NEXT: vfnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1809,10 +1597,8 @@ define @vfnmsac_vf_nxv4f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1826,10 +1612,8 @@ define @vfnmsac_vf_nxv4f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1843,11 +1627,9 @@ define @vfnmsac_vf_nxv4f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1858,10 +1640,8 @@ define @vfnmsac_vv_nxv4f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1875,10 +1655,8 @@ define @vfnmsac_vf_nxv4f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1892,10 +1670,8 @@ define @vfnmsac_vf_nxv4f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv4f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4f64( %m, %v, %c, i32 %evl) ret %u } @@ -1913,10 +1689,8 @@ define @vfnmsac_vv_nxv8f64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1929,11 +1703,9 @@ define @vfnmsac_vv_nxv8f64_unmasked( ; CHECK-NEXT: vfnmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1946,10 +1718,8 @@ define @vfnmsac_vf_nxv8f64( %a, doubl ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1963,10 +1733,8 @@ define @vfnmsac_vf_nxv8f64_commute( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -1980,11 +1748,9 @@ define @vfnmsac_vf_nxv8f64_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8f64( %allones, %v, %c, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8f64( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -1996,10 +1762,8 @@ define @vfnmsac_vv_nxv8f64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %b, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2013,10 +1777,8 @@ define @vfnmsac_vf_nxv8f64_ta( %a, do ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vb, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } @@ -2030,10 +1792,8 @@ define @vfnmsac_vf_nxv8f64_commute_ta( poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %nega = call @llvm.vp.fneg.nxv8f64( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %c, %allones, i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vb, %nega, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8f64( %m, %v, %c, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll index d7bb1ad7726d..876f8d945638 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll @@ -26,9 +26,7 @@ define @vfrdiv_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -54,9 +52,7 @@ define @vfrdiv_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -82,9 +78,7 @@ define @vfrdiv_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -110,9 +104,7 @@ define @vfrdiv_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +130,7 @@ define @vfrdiv_vf_nxv16f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv16f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv16f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -166,9 +156,7 @@ define @vfrdiv_vf_nxv32f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv32f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv32f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -194,9 +182,7 @@ define @vfrdiv_vf_nxv1f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +208,7 @@ define @vfrdiv_vf_nxv2f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -250,9 +234,7 @@ define @vfrdiv_vf_nxv4f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -278,9 +260,7 @@ define @vfrdiv_vf_nxv8f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -306,9 +286,7 @@ define @vfrdiv_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv16f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv16f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -334,9 +312,7 @@ define @vfrdiv_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv1f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv1f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -362,9 +338,7 @@ define @vfrdiv_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv2f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv2f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -390,9 +364,7 @@ define @vfrdiv_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv4f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv4f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -418,8 +390,6 @@ define @vfrdiv_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv8f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv8f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll index 9e1c719e3bfa..bd941dc1a777 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll @@ -26,9 +26,7 @@ define @vfrsub_vf_nxv1f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -54,9 +52,7 @@ define @vfrsub_vf_nxv2f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -82,9 +78,7 @@ define @vfrsub_vf_nxv4f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -110,9 +104,7 @@ define @vfrsub_vf_nxv8f16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +130,7 @@ define @vfrsub_vf_nxv16f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv16f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv16f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -166,9 +156,7 @@ define @vfrsub_vf_nxv32f16_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv32f16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv32f16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -194,9 +182,7 @@ define @vfrsub_vf_nxv1f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +208,7 @@ define @vfrsub_vf_nxv2f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -250,9 +234,7 @@ define @vfrsub_vf_nxv4f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -278,9 +260,7 @@ define @vfrsub_vf_nxv8f32_unmasked( %va ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -306,9 +286,7 @@ define @vfrsub_vf_nxv16f32_unmasked( ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv16f32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv16f32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -334,9 +312,7 @@ define @vfrsub_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -362,9 +338,7 @@ define @vfrsub_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -390,9 +364,7 @@ define @vfrsub_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -418,8 +390,6 @@ define @vfrsub_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f64( %vb, %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll index b13d221e00e6..f1b7b003f539 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll @@ -46,9 +46,7 @@ define @vfsqrt_vv_nxv1f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv1f16( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv1f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -90,9 +88,7 @@ define @vfsqrt_vv_nxv2f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv2f16( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv2f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -134,9 +130,7 @@ define @vfsqrt_vv_nxv4f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv4f16( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv4f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -178,9 +172,7 @@ define @vfsqrt_vv_nxv8f16_unmasked( %va, ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv8f16( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv8f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -222,9 +214,7 @@ define @vfsqrt_vv_nxv16f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv16f16( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv16f16( %va, splat (i1 true), i32 %evl) ret %v } @@ -330,9 +320,7 @@ define @vfsqrt_vv_nxv1f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv1f32( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv1f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +342,7 @@ define @vfsqrt_vv_nxv2f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv2f32( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv2f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -378,9 +364,7 @@ define @vfsqrt_vv_nxv4f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv4f32( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv4f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -402,9 +386,7 @@ define @vfsqrt_vv_nxv8f32_unmasked( %va ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv8f32( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv8f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -426,9 +408,7 @@ define @vfsqrt_vv_nxv16f32_unmasked( ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv16f32( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv16f32( %va, splat (i1 true), i32 %evl) ret %v } @@ -450,9 +430,7 @@ define @vfsqrt_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv1f64( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv1f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -474,9 +452,7 @@ define @vfsqrt_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv2f64( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv2f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -498,9 +474,7 @@ define @vfsqrt_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv4f64( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv4f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -522,9 +496,7 @@ define @vfsqrt_vv_nxv7f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv7f64( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv7f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -546,9 +518,7 @@ define @vfsqrt_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsqrt.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv8f64( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv8f64( %va, splat (i1 true), i32 %evl) ret %v } @@ -598,8 +568,6 @@ define @vfsqrt_vv_nxv16f64_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv16f64( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv16f64( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll index b8b95ad21de6..b7941c17dab5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll @@ -562,9 +562,7 @@ define @vfsub_vv_mask_nxv8f32( %va, poison, float 0.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %splat + %vs = select %mask, %vb, splat (float 0.0) %vc = fsub fast %va, %vs ret %vc } @@ -575,11 +573,9 @@ define @vfsub_vf_mask_nxv8f32( %va, flo ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vfsub.vf v8, v8, fa0, v0.t ; CHECK-NEXT: ret - %head0 = insertelement poison, float 0.0, i32 0 - %splat0 = shufflevector %head0, poison, zeroinitializer %head1 = insertelement poison, float %b, i32 0 %splat1 = shufflevector %head1, poison, zeroinitializer - %vs = select %mask, %splat1, %splat0 + %vs = select %mask, %splat1, splat (float 0.0) %vc = fsub fast %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index 010b133e51b1..ca436e29c9de 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -48,9 +48,7 @@ define @vfsub_vv_nxv1f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -104,9 +102,7 @@ define @vfsub_vf_nxv1f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +146,7 @@ define @vfsub_vv_nxv2f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -206,9 +200,7 @@ define @vfsub_vf_nxv2f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -252,9 +244,7 @@ define @vfsub_vv_nxv4f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +298,7 @@ define @vfsub_vf_nxv4f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -354,9 +342,7 @@ define @vfsub_vv_nxv8f16_unmasked( %va, < ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -410,9 +396,7 @@ define @vfsub_vf_nxv8f16_unmasked( %va, h ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -456,9 +440,7 @@ define @vfsub_vv_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv16f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv16f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +494,7 @@ define @vfsub_vf_nxv16f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv16f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv16f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -750,9 +730,7 @@ define @vfsub_vv_nxv1f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -776,9 +754,7 @@ define @vfsub_vf_nxv1f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -800,9 +776,7 @@ define @vfsub_vv_nxv2f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -826,9 +800,7 @@ define @vfsub_vf_nxv2f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -850,9 +822,7 @@ define @vfsub_vv_nxv4f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -876,9 +846,7 @@ define @vfsub_vf_nxv4f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -900,9 +868,7 @@ define @vfsub_vv_nxv8f32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +892,7 @@ define @vfsub_vf_nxv8f32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -950,9 +914,7 @@ define @vfsub_vv_nxv16f32_unmasked( % ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv16f32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv16f32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -976,9 +938,7 @@ define @vfsub_vf_nxv16f32_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv16f32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv16f32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1000,9 +960,7 @@ define @vfsub_vv_nxv1f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +984,7 @@ define @vfsub_vf_nxv1f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv1f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv1f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1050,9 +1006,7 @@ define @vfsub_vv_nxv2f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1076,9 +1030,7 @@ define @vfsub_vf_nxv2f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv2f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv2f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1100,9 +1052,7 @@ define @vfsub_vv_nxv4f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1126,9 +1076,7 @@ define @vfsub_vf_nxv4f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv4f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv4f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1162,9 +1110,7 @@ define @vfsub_vv_nxv8f64_unmasked( %v ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vfsub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1188,8 +1134,6 @@ define @vfsub_vf_nxv8f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, double %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv8f64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv8f64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll index 8a484c7f6b77..fab76ac56458 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll @@ -51,11 +51,9 @@ define @vfmacc_vv_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmadd.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -76,11 +74,9 @@ define @vfmacc_vv_nxv1f32_tu( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -132,12 +128,10 @@ define @vfmacc_vv_nxv1f32_unmasked_tu( % ; ZVFHMIN-NEXT: vfmacc.vv v10, v11, v8 ; ZVFHMIN-NEXT: vmv1r.v v8, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -223,11 +217,9 @@ define @vfmacc_vf_nxv1f32_unmasked( %va, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -255,11 +247,9 @@ define @vfmacc_vf_nxv1f32_tu( %va, half ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %vc, i32 %evl) ret %u } @@ -288,11 +278,9 @@ define @vfmacc_vf_nxv1f32_commute_tu( %v ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vbext, %vaext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vbext, %vaext, %vc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %vc, i32 %evl) ret %u } @@ -321,12 +309,10 @@ define @vfmacc_vf_nxv1f32_unmasked_tu( % ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %vaext, %vbext, %vc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %vc, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %vc, i32 %evl) ret %u } @@ -374,11 +360,9 @@ define @vfmacc_vv_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmadd.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -434,11 +418,9 @@ define @vfmacc_vf_nxv2f32_unmasked( %va, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -488,11 +470,9 @@ define @vfmacc_vv_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: vfmadd.vv v12, v14, v10 ; ZVFHMIN-NEXT: vmv.v.v v8, v12 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -548,11 +528,9 @@ define @vfmacc_vf_nxv4f32_unmasked( %va, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -602,11 +580,9 @@ define @vfmacc_vv_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: vfmadd.vv v16, v20, v12 ; ZVFHMIN-NEXT: vmv.v.v v8, v16 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -662,11 +638,9 @@ define @vfmacc_vf_nxv8f32_unmasked( %va, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -730,11 +704,9 @@ define @vfmacc_vv_nxv16f32_unmasked( % ; ZVFHMIN-NEXT: vfmadd.vv v24, v0, v16 ; ZVFHMIN-NEXT: vmv.v.v v8, v24 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -790,11 +762,9 @@ define @vfmacc_vf_nxv16f32_unmasked( % ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -824,11 +794,9 @@ define @vfmacc_vv_nxv1f64_unmasked( %a ; CHECK-NEXT: vfwmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -856,11 +824,9 @@ define @vfmacc_vf_nxv1f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -890,11 +856,9 @@ define @vfmacc_vv_nxv2f64_unmasked( %a ; CHECK-NEXT: vfwmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -922,11 +886,9 @@ define @vfmacc_vf_nxv2f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -956,11 +918,9 @@ define @vfmacc_vv_nxv4f64_unmasked( %a ; CHECK-NEXT: vfwmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -988,11 +948,9 @@ define @vfmacc_vf_nxv4f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -1022,11 +980,9 @@ define @vfmacc_vv_nxv8f64_unmasked( %a ; CHECK-NEXT: vfwmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1054,11 +1010,9 @@ define @vfmacc_vf_nxv8f64_unmasked( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %vaext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %va, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %vb, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %vaext, %vbext, %vc, %allones, i32 %evl) + %vaext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %va, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %vb, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %vaext, %vbext, %vc, splat (i1 -1), i32 %evl) ret %v } @@ -1090,11 +1044,9 @@ define @vfmacc_vv_nxv1f64_nxv1f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1126,11 +1078,9 @@ define @vfmacc_vv_nxv2f64_nxv2f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1162,11 +1112,9 @@ define @vfmacc_vv_nxv4f64_nxv4f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1198,11 +1146,9 @@ define @vfmacc_vv_nxv8f64_nxv8f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %b, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %aext, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %aext, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1243,9 +1189,7 @@ define @vfmacc_squared_nxv1f32_unmasked( ; ZVFHMIN-NEXT: vfmadd.vv v9, v9, v10 ; ZVFHMIN-NEXT: vmv1r.v v8, v9 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %aext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %aext, %c, splat (i1 -1), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll index 92ad961999dd..4cd9b8bc2cde 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-vp.ll @@ -52,12 +52,10 @@ define @vmfsac_vv_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfmsub.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -78,12 +76,10 @@ define @vmfsac_vv_nxv1f32_tu( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %negc, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1f32( %m, %v, %c, i32 %evl) ret %u } @@ -105,13 +101,11 @@ define @vmfsac_vv_nxv1f32_unmasked_tu( % ; ZVFHMIN-NEXT: vfmsac.vv v10, v11, v8 ; ZVFHMIN-NEXT: vmv1r.v v8, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %negc, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1f32( %allones, %v, %c, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %bext, %negc, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1f32( splat (i1 -1), %v, %c, i32 %evl) ret %u } @@ -138,8 +132,6 @@ define @vmfsac_vf_nxv1f32( %a, half %b, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %m, i32 %evl) %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %m, i32 %evl) %negc = call @llvm.vp.fneg.nxv1f32( %c, %m, i32 %evl) @@ -201,12 +193,10 @@ define @vmfsac_vf_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %aext, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %aext, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -253,12 +243,10 @@ define @vmfsac_vv_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfmsub.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %aext, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %aext, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -285,8 +273,6 @@ define @vmfsac_vf_nxv2f32( %a, half %b, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %m, i32 %evl) %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, %m, i32 %evl) %negc = call @llvm.vp.fneg.nxv2f32( %c, %m, i32 %evl) @@ -348,12 +334,10 @@ define @vmfsac_vf_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %aext, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %aext, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -402,12 +386,10 @@ define @vmfsac_vv_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: vfmsub.vv v12, v14, v10 ; ZVFHMIN-NEXT: vmv.v.v v8, v12 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %aext, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %aext, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -434,8 +416,6 @@ define @vmfsac_vf_nxv4f32( %a, half %b, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %m, i32 %evl) %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, %m, i32 %evl) %negc = call @llvm.vp.fneg.nxv4f32( %c, %m, i32 %evl) @@ -497,12 +477,10 @@ define @vmfsac_vf_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %aext, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %aext, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -551,12 +529,10 @@ define @vmfsac_vv_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: vfmsub.vv v16, v20, v12 ; ZVFHMIN-NEXT: vmv.v.v v8, v16 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %aext, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %aext, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -583,8 +559,6 @@ define @vmfsac_vf_nxv8f32( %a, half %b, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %m, i32 %evl) %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, %m, i32 %evl) %negc = call @llvm.vp.fneg.nxv8f32( %c, %m, i32 %evl) @@ -646,11 +620,9 @@ define @vmfsac_vf_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %aext, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %aext, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll index 3a03f0d65273..ca0bbfd65ca2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-vp.ll @@ -52,13 +52,11 @@ define @vfnmacc_vv_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfnmadd.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -149,13 +147,11 @@ define @vfnmacc_vf_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -203,13 +199,11 @@ define @vfnmacc_vv_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfnmadd.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -300,13 +294,11 @@ define @vfnmacc_vf_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -356,13 +348,11 @@ define @vfnmacc_vv_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: vfnmadd.vv v12, v14, v10 ; ZVFHMIN-NEXT: vmv.v.v v8, v12 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -453,13 +443,11 @@ define @vfnmacc_vf_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -509,13 +497,11 @@ define @vfnmacc_vv_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: vfnmadd.vv v16, v20, v12 ; ZVFHMIN-NEXT: vmv.v.v v8, v16 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -606,13 +592,11 @@ define @vfnmacc_vf_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -676,13 +660,11 @@ define @vfnmacc_vv_nxv16f32_unmasked( ; ZVFHMIN-NEXT: vfnmadd.vv v24, v0, v16 ; ZVFHMIN-NEXT: vmv.v.v v8, v24 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv16f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -773,13 +755,11 @@ define @vfnmacc_vf_nxv16f32_unmasked( ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv16f32( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv16f32( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv16f32( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -809,13 +789,11 @@ define @vfnmacc_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vfwnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -863,13 +841,11 @@ define @vfnmacc_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -899,13 +875,11 @@ define @vfnmacc_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vfwnmacc.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -953,13 +927,11 @@ define @vfnmacc_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -989,13 +961,11 @@ define @vfnmacc_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vfwnmacc.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1043,13 +1013,11 @@ define @vfnmacc_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1079,13 +1047,11 @@ define @vfnmacc_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vfwnmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1133,13 +1099,11 @@ define @vfnmacc_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vbext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vbext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1173,13 +1137,11 @@ define @vfnmacc_vv_nxv1f64_nxv1f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv1f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f64.nxv1f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv1f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1213,13 +1175,11 @@ define @vfnmacc_vv_nxv2f64_nxv2f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv2f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f64.nxv2f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv2f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1253,13 +1213,11 @@ define @vfnmacc_vv_nxv4f64_nxv4f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv4f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f64.nxv4f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv4f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } @@ -1293,12 +1251,10 @@ define @vfnmacc_vv_nxv8f64_nxv4f16_unmasked( poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f64( %aext, %allones, i32 %evl) - %negc = call @llvm.vp.fneg.nxv8f64( %c, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %bext, %negc, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f64.nxv8f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %aext, splat (i1 -1), i32 %evl) + %negc = call @llvm.vp.fneg.nxv8f64( %c, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %bext, %negc, splat (i1 -1), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll index a8cc0ce92aa1..2797ca2eb316 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-vp.ll @@ -51,12 +51,10 @@ define @vfnmsac_vv_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfnmsub.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -144,12 +142,10 @@ define @vfnmsac_vf_nxv1f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f32( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f32.nxv1f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f32( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -196,12 +192,10 @@ define @vfnmsac_vv_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfnmsub.vv v8, v11, v10 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -289,12 +283,10 @@ define @vfnmsac_vf_nxv2f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f32( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f32.nxv2f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f32( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -343,12 +335,10 @@ define @vfnmsac_vv_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: vfnmsub.vv v12, v14, v10 ; ZVFHMIN-NEXT: vmv.v.v v8, v12 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -436,12 +426,10 @@ define @vfnmsac_vf_nxv4f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f32( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f32.nxv4f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f32( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -490,12 +478,10 @@ define @vfnmsac_vv_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: vfnmsub.vv v16, v20, v12 ; ZVFHMIN-NEXT: vmv.v.v v8, v16 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -583,12 +569,10 @@ define @vfnmsac_vf_nxv8f32_unmasked( %a, ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f32( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f32.nxv8f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f32( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -651,12 +635,10 @@ define @vfnmsac_vv_nxv16f32_unmasked( ; ZVFHMIN-NEXT: vfnmsub.vv v24, v0, v16 ; ZVFHMIN-NEXT: vmv.v.v v8, v24 ; ZVFHMIN-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv16f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -744,12 +726,10 @@ define @vfnmsac_vf_nxv16f32_unmasked( ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv16f32( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv16f32( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv16f32.nxv16f16( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv16f32( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv16f32( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -778,12 +758,10 @@ define @vfnmsac_vv_nxv1f64_unmasked( % ; CHECK-NEXT: vfwnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -828,12 +806,10 @@ define @vfnmsac_vf_nxv1f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv1f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv1f64( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv1f64.nxv1f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv1f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv1f64( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -862,12 +838,10 @@ define @vfnmsac_vv_nxv2f64_unmasked( % ; CHECK-NEXT: vfwnmsac.vv v10, v8, v9 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -912,12 +886,10 @@ define @vfnmsac_vf_nxv2f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv2f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv2f64( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv2f64.nxv2f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv2f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv2f64( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -946,12 +918,10 @@ define @vfnmsac_vv_nxv4f64_unmasked( % ; CHECK-NEXT: vfwnmsac.vv v12, v8, v10 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -996,12 +966,10 @@ define @vfnmsac_vf_nxv4f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv4f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv4f64( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv4f64.nxv4f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv4f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv4f64( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1030,12 +998,10 @@ define @vfnmsac_vv_nxv8f64_unmasked( % ; CHECK-NEXT: vfwnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, %allones, i32 %evl) - %bext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %b, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %bext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %b, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %bext, %c, splat (i1 -1), i32 %evl) ret %v } @@ -1080,11 +1046,9 @@ define @vfnmsac_vf_nxv8f64_unmasked( % ; CHECK-NEXT: ret %elt.head = insertelement poison, float %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, %allones, i32 %evl) - %vbext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %vb, %allones, i32 %evl) - %nega = call @llvm.vp.fneg.nxv8f64( %aext, %allones, i32 %evl) - %v = call @llvm.vp.fma.nxv8f64( %nega, %vbext, %c, %allones, i32 %evl) + %aext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %a, splat (i1 -1), i32 %evl) + %vbext = call @llvm.vp.fpext.nxv8f64.nxv8f32( %vb, splat (i1 -1), i32 %evl) + %nega = call @llvm.vp.fneg.nxv8f64( %aext, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.fma.nxv8f64( %nega, %vbext, %c, splat (i1 -1), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll index 797bd4125f48..5aba7ef4cc5b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll @@ -16,10 +16,8 @@ define @vmacc_vv_nxv1i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -31,11 +29,9 @@ define @vmacc_vv_nxv1i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -48,10 +44,8 @@ define @vmacc_vx_nxv1i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -65,11 +59,9 @@ define @vmacc_vx_nxv1i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -80,10 +72,8 @@ define @vmacc_vv_nxv1i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -97,10 +87,8 @@ define @vmacc_vx_nxv1i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -117,10 +105,8 @@ define @vmacc_vv_nxv2i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -132,11 +118,9 @@ define @vmacc_vv_nxv2i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -149,10 +133,8 @@ define @vmacc_vx_nxv2i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -166,11 +148,9 @@ define @vmacc_vx_nxv2i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -181,10 +161,8 @@ define @vmacc_vv_nxv2i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -198,10 +176,8 @@ define @vmacc_vx_nxv2i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -218,10 +194,8 @@ define @vmacc_vv_nxv4i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -233,11 +207,9 @@ define @vmacc_vv_nxv4i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -250,10 +222,8 @@ define @vmacc_vx_nxv4i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -267,11 +237,9 @@ define @vmacc_vx_nxv4i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -282,10 +250,8 @@ define @vmacc_vv_nxv4i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -299,10 +265,8 @@ define @vmacc_vx_nxv4i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -319,10 +283,8 @@ define @vmacc_vv_nxv8i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -334,11 +296,9 @@ define @vmacc_vv_nxv8i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -351,10 +311,8 @@ define @vmacc_vx_nxv8i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -368,11 +326,9 @@ define @vmacc_vx_nxv8i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -383,10 +339,8 @@ define @vmacc_vv_nxv8i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -400,10 +354,8 @@ define @vmacc_vx_nxv8i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -420,10 +372,8 @@ define @vmacc_vv_nxv16i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -435,11 +385,9 @@ define @vmacc_vv_nxv16i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -452,10 +400,8 @@ define @vmacc_vx_nxv16i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -469,11 +415,9 @@ define @vmacc_vx_nxv16i8_unmasked( %a, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -484,10 +428,8 @@ define @vmacc_vv_nxv16i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -501,10 +443,8 @@ define @vmacc_vx_nxv16i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -521,10 +461,8 @@ define @vmacc_vv_nxv32i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -536,11 +474,9 @@ define @vmacc_vv_nxv32i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -553,10 +489,8 @@ define @vmacc_vx_nxv32i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -570,11 +504,9 @@ define @vmacc_vx_nxv32i8_unmasked( %a, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -585,10 +517,8 @@ define @vmacc_vv_nxv32i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -602,10 +532,8 @@ define @vmacc_vx_nxv32i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -623,10 +551,8 @@ define @vmacc_vv_nxv64i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -639,11 +565,9 @@ define @vmacc_vv_nxv64i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv64i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv64i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -656,10 +580,8 @@ define @vmacc_vx_nxv64i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -673,11 +595,9 @@ define @vmacc_vx_nxv64i8_unmasked( %a, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv64i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv64i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -689,10 +609,8 @@ define @vmacc_vv_nxv64i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -706,10 +624,8 @@ define @vmacc_vx_nxv64i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -726,10 +642,8 @@ define @vmacc_vv_nxv1i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -741,11 +655,9 @@ define @vmacc_vv_nxv1i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -758,10 +670,8 @@ define @vmacc_vx_nxv1i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -775,11 +685,9 @@ define @vmacc_vx_nxv1i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -790,10 +698,8 @@ define @vmacc_vv_nxv1i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -807,10 +713,8 @@ define @vmacc_vx_nxv1i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -827,10 +731,8 @@ define @vmacc_vv_nxv2i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -842,11 +744,9 @@ define @vmacc_vv_nxv2i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -859,10 +759,8 @@ define @vmacc_vx_nxv2i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -876,11 +774,9 @@ define @vmacc_vx_nxv2i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -891,10 +787,8 @@ define @vmacc_vv_nxv2i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -908,10 +802,8 @@ define @vmacc_vx_nxv2i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -928,10 +820,8 @@ define @vmacc_vv_nxv4i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -943,11 +833,9 @@ define @vmacc_vv_nxv4i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -960,10 +848,8 @@ define @vmacc_vx_nxv4i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -977,11 +863,9 @@ define @vmacc_vx_nxv4i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -992,10 +876,8 @@ define @vmacc_vv_nxv4i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -1009,10 +891,8 @@ define @vmacc_vx_nxv4i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -1029,10 +909,8 @@ define @vmacc_vv_nxv8i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1044,11 +922,9 @@ define @vmacc_vv_nxv8i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1061,10 +937,8 @@ define @vmacc_vx_nxv8i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1078,11 +952,9 @@ define @vmacc_vx_nxv8i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1093,10 +965,8 @@ define @vmacc_vv_nxv8i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1110,10 +980,8 @@ define @vmacc_vx_nxv8i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1130,10 +998,8 @@ define @vmacc_vv_nxv16i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1145,11 +1011,9 @@ define @vmacc_vv_nxv16i16_unmasked( %a, < ; CHECK-NEXT: vmacc.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1162,10 +1026,8 @@ define @vmacc_vx_nxv16i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1179,11 +1041,9 @@ define @vmacc_vx_nxv16i16_unmasked( %a, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1194,10 +1054,8 @@ define @vmacc_vv_nxv16i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1211,10 +1069,8 @@ define @vmacc_vx_nxv16i16_ta( %a, i16 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1232,10 +1088,8 @@ define @vmacc_vv_nxv32i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1248,11 +1102,9 @@ define @vmacc_vv_nxv32i16_unmasked( %a, < ; CHECK-NEXT: vmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1265,10 +1117,8 @@ define @vmacc_vx_nxv32i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1282,11 +1132,9 @@ define @vmacc_vx_nxv32i16_unmasked( %a, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1298,10 +1146,8 @@ define @vmacc_vv_nxv32i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1315,10 +1161,8 @@ define @vmacc_vx_nxv32i16_ta( %a, i16 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1335,10 +1179,8 @@ define @vmacc_vv_nxv1i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1350,11 +1192,9 @@ define @vmacc_vv_nxv1i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1367,10 +1207,8 @@ define @vmacc_vx_nxv1i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1384,11 +1222,9 @@ define @vmacc_vx_nxv1i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1399,10 +1235,8 @@ define @vmacc_vv_nxv1i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1416,10 +1250,8 @@ define @vmacc_vx_nxv1i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1436,10 +1268,8 @@ define @vmacc_vv_nxv2i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1451,11 +1281,9 @@ define @vmacc_vv_nxv2i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1468,10 +1296,8 @@ define @vmacc_vx_nxv2i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1485,11 +1311,9 @@ define @vmacc_vx_nxv2i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1500,10 +1324,8 @@ define @vmacc_vv_nxv2i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1517,10 +1339,8 @@ define @vmacc_vx_nxv2i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1537,10 +1357,8 @@ define @vmacc_vv_nxv4i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1552,11 +1370,9 @@ define @vmacc_vv_nxv4i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1569,10 +1385,8 @@ define @vmacc_vx_nxv4i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1586,11 +1400,9 @@ define @vmacc_vx_nxv4i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1601,10 +1413,8 @@ define @vmacc_vv_nxv4i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1618,10 +1428,8 @@ define @vmacc_vx_nxv4i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1638,10 +1446,8 @@ define @vmacc_vv_nxv8i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1653,11 +1459,9 @@ define @vmacc_vv_nxv8i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1670,10 +1474,8 @@ define @vmacc_vx_nxv8i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1687,11 +1489,9 @@ define @vmacc_vx_nxv8i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1702,10 +1502,8 @@ define @vmacc_vv_nxv8i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1719,10 +1517,8 @@ define @vmacc_vx_nxv8i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1740,10 +1536,8 @@ define @vmacc_vv_nxv16i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1756,11 +1550,9 @@ define @vmacc_vv_nxv16i32_unmasked( %a, < ; CHECK-NEXT: vmacc.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1773,10 +1565,8 @@ define @vmacc_vx_nxv16i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1790,11 +1580,9 @@ define @vmacc_vx_nxv16i32_unmasked( %a, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1806,10 +1594,8 @@ define @vmacc_vv_nxv16i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1823,10 +1609,8 @@ define @vmacc_vx_nxv16i32_ta( %a, i32 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1843,10 +1627,8 @@ define @vmacc_vv_nxv1i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1858,11 +1640,9 @@ define @vmacc_vv_nxv1i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1890,10 +1670,8 @@ define @vmacc_vx_nxv1i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1922,11 +1700,9 @@ define @vmacc_vx_nxv1i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1937,10 +1713,8 @@ define @vmacc_vv_nxv1i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1969,10 +1743,8 @@ define @vmacc_vx_nxv1i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1989,10 +1761,8 @@ define @vmacc_vv_nxv2i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2004,11 +1774,9 @@ define @vmacc_vv_nxv2i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2036,10 +1804,8 @@ define @vmacc_vx_nxv2i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2068,11 +1834,9 @@ define @vmacc_vx_nxv2i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2083,10 +1847,8 @@ define @vmacc_vv_nxv2i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2115,10 +1877,8 @@ define @vmacc_vx_nxv2i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2135,10 +1895,8 @@ define @vmacc_vv_nxv4i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2150,11 +1908,9 @@ define @vmacc_vv_nxv4i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2182,10 +1938,8 @@ define @vmacc_vx_nxv4i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2214,11 +1968,9 @@ define @vmacc_vx_nxv4i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2229,10 +1981,8 @@ define @vmacc_vv_nxv4i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2261,10 +2011,8 @@ define @vmacc_vx_nxv4i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2282,10 +2030,8 @@ define @vmacc_vv_nxv8i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i64( %m, %y, %c, i32 %evl) ret %u } @@ -2298,11 +2044,9 @@ define @vmacc_vv_nxv8i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2330,10 +2074,8 @@ define @vmacc_vx_nxv8i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i64( %m, %y, %c, i32 %evl) ret %u } @@ -2362,11 +2104,9 @@ define @vmacc_vx_nxv8i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2378,10 +2118,8 @@ define @vmacc_vv_nxv8i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i64( %m, %y, %c, i32 %evl) ret %u } @@ -2410,10 +2148,8 @@ define @vmacc_vx_nxv8i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i64( %m, %y, %c, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll index 6a6d7d2a4142..0322c1ab9f63 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll @@ -17,10 +17,8 @@ define @vmadd_vv_nxv1i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i8( %m, %y, %a, i32 %evl) ret %u } @@ -33,11 +31,9 @@ define @vmadd_vv_nxv1i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -49,10 +45,8 @@ define @vmadd_vx_nxv1i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i8( %m, %y, %a, i32 %evl) ret %u } @@ -65,11 +59,9 @@ define @vmadd_vx_nxv1i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -80,10 +72,8 @@ define @vmadd_vv_nxv1i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i8( %m, %y, %a, i32 %evl) ret %u } @@ -97,10 +87,8 @@ define @vmadd_vx_nxv1i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i8( %m, %y, %a, i32 %evl) ret %u } @@ -118,10 +106,8 @@ define @vmadd_vv_nxv2i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i8( %m, %y, %a, i32 %evl) ret %u } @@ -134,11 +120,9 @@ define @vmadd_vv_nxv2i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -150,10 +134,8 @@ define @vmadd_vx_nxv2i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i8( %m, %y, %a, i32 %evl) ret %u } @@ -166,11 +148,9 @@ define @vmadd_vx_nxv2i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -181,10 +161,8 @@ define @vmadd_vv_nxv2i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i8( %m, %y, %a, i32 %evl) ret %u } @@ -198,10 +176,8 @@ define @vmadd_vx_nxv2i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i8( %m, %y, %a, i32 %evl) ret %u } @@ -219,10 +195,8 @@ define @vmadd_vv_nxv4i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i8( %m, %y, %a, i32 %evl) ret %u } @@ -235,11 +209,9 @@ define @vmadd_vv_nxv4i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -251,10 +223,8 @@ define @vmadd_vx_nxv4i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i8( %m, %y, %a, i32 %evl) ret %u } @@ -267,11 +237,9 @@ define @vmadd_vx_nxv4i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -282,10 +250,8 @@ define @vmadd_vv_nxv4i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i8( %m, %y, %a, i32 %evl) ret %u } @@ -299,10 +265,8 @@ define @vmadd_vx_nxv4i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i8( %m, %y, %a, i32 %evl) ret %u } @@ -320,10 +284,8 @@ define @vmadd_vv_nxv8i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i8( %m, %y, %a, i32 %evl) ret %u } @@ -336,11 +298,9 @@ define @vmadd_vv_nxv8i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -352,10 +312,8 @@ define @vmadd_vx_nxv8i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i8( %m, %y, %a, i32 %evl) ret %u } @@ -368,11 +326,9 @@ define @vmadd_vx_nxv8i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -383,10 +339,8 @@ define @vmadd_vv_nxv8i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i8( %m, %y, %a, i32 %evl) ret %u } @@ -400,10 +354,8 @@ define @vmadd_vx_nxv8i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i8( %m, %y, %a, i32 %evl) ret %u } @@ -421,10 +373,8 @@ define @vmadd_vv_nxv16i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i8( %m, %y, %a, i32 %evl) ret %u } @@ -437,11 +387,9 @@ define @vmadd_vv_nxv16i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -453,10 +401,8 @@ define @vmadd_vx_nxv16i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i8( %m, %y, %a, i32 %evl) ret %u } @@ -469,11 +415,9 @@ define @vmadd_vx_nxv16i8_unmasked( %a, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -484,10 +428,8 @@ define @vmadd_vv_nxv16i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i8( %m, %y, %a, i32 %evl) ret %u } @@ -501,10 +443,8 @@ define @vmadd_vx_nxv16i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i8( %m, %y, %a, i32 %evl) ret %u } @@ -522,10 +462,8 @@ define @vmadd_vv_nxv32i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i8( %m, %y, %a, i32 %evl) ret %u } @@ -538,11 +476,9 @@ define @vmadd_vv_nxv32i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -554,10 +490,8 @@ define @vmadd_vx_nxv32i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i8( %m, %y, %a, i32 %evl) ret %u } @@ -570,11 +504,9 @@ define @vmadd_vx_nxv32i8_unmasked( %a, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -585,10 +517,8 @@ define @vmadd_vv_nxv32i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i8( %m, %y, %a, i32 %evl) ret %u } @@ -602,10 +532,8 @@ define @vmadd_vx_nxv32i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i8( %m, %y, %a, i32 %evl) ret %u } @@ -624,10 +552,8 @@ define @vmadd_vv_nxv64i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv64i8( %m, %y, %a, i32 %evl) ret %u } @@ -641,11 +567,9 @@ define @vmadd_vv_nxv64i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv64i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv64i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -657,10 +581,8 @@ define @vmadd_vx_nxv64i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv64i8( %m, %y, %a, i32 %evl) ret %u } @@ -673,11 +595,9 @@ define @vmadd_vx_nxv64i8_unmasked( %a, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv64i8( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv64i8( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -689,10 +609,8 @@ define @vmadd_vv_nxv64i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv64i8( %m, %y, %a, i32 %evl) ret %u } @@ -706,10 +624,8 @@ define @vmadd_vx_nxv64i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv64i8( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv64i8( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv64i8( %m, %y, %a, i32 %evl) ret %u } @@ -727,10 +643,8 @@ define @vmadd_vv_nxv1i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i16( %m, %y, %a, i32 %evl) ret %u } @@ -743,11 +657,9 @@ define @vmadd_vv_nxv1i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -759,10 +671,8 @@ define @vmadd_vx_nxv1i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i16( %m, %y, %a, i32 %evl) ret %u } @@ -775,11 +685,9 @@ define @vmadd_vx_nxv1i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -790,10 +698,8 @@ define @vmadd_vv_nxv1i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i16( %m, %y, %a, i32 %evl) ret %u } @@ -807,10 +713,8 @@ define @vmadd_vx_nxv1i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i16( %m, %y, %a, i32 %evl) ret %u } @@ -828,10 +732,8 @@ define @vmadd_vv_nxv2i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i16( %m, %y, %a, i32 %evl) ret %u } @@ -844,11 +746,9 @@ define @vmadd_vv_nxv2i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -860,10 +760,8 @@ define @vmadd_vx_nxv2i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i16( %m, %y, %a, i32 %evl) ret %u } @@ -876,11 +774,9 @@ define @vmadd_vx_nxv2i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -891,10 +787,8 @@ define @vmadd_vv_nxv2i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i16( %m, %y, %a, i32 %evl) ret %u } @@ -908,10 +802,8 @@ define @vmadd_vx_nxv2i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i16( %m, %y, %a, i32 %evl) ret %u } @@ -929,10 +821,8 @@ define @vmadd_vv_nxv4i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i16( %m, %y, %a, i32 %evl) ret %u } @@ -945,11 +835,9 @@ define @vmadd_vv_nxv4i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -961,10 +849,8 @@ define @vmadd_vx_nxv4i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i16( %m, %y, %a, i32 %evl) ret %u } @@ -977,11 +863,9 @@ define @vmadd_vx_nxv4i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -992,10 +876,8 @@ define @vmadd_vv_nxv4i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i16( %m, %y, %a, i32 %evl) ret %u } @@ -1009,10 +891,8 @@ define @vmadd_vx_nxv4i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i16( %m, %y, %a, i32 %evl) ret %u } @@ -1030,10 +910,8 @@ define @vmadd_vv_nxv8i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i16( %m, %y, %a, i32 %evl) ret %u } @@ -1046,11 +924,9 @@ define @vmadd_vv_nxv8i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1062,10 +938,8 @@ define @vmadd_vx_nxv8i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i16( %m, %y, %a, i32 %evl) ret %u } @@ -1078,11 +952,9 @@ define @vmadd_vx_nxv8i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1093,10 +965,8 @@ define @vmadd_vv_nxv8i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i16( %m, %y, %a, i32 %evl) ret %u } @@ -1110,10 +980,8 @@ define @vmadd_vx_nxv8i16_ta( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i16( %m, %y, %a, i32 %evl) ret %u } @@ -1131,10 +999,8 @@ define @vmadd_vv_nxv16i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i16( %m, %y, %a, i32 %evl) ret %u } @@ -1147,11 +1013,9 @@ define @vmadd_vv_nxv16i16_unmasked( %a, < ; CHECK-NEXT: vsetvli zero, zero, e16, m4, tu, ma ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1163,10 +1027,8 @@ define @vmadd_vx_nxv16i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i16( %m, %y, %a, i32 %evl) ret %u } @@ -1179,11 +1041,9 @@ define @vmadd_vx_nxv16i16_unmasked( %a, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1194,10 +1054,8 @@ define @vmadd_vv_nxv16i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i16( %m, %y, %a, i32 %evl) ret %u } @@ -1211,10 +1069,8 @@ define @vmadd_vx_nxv16i16_ta( %a, i16 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i16( %m, %y, %a, i32 %evl) ret %u } @@ -1233,10 +1089,8 @@ define @vmadd_vv_nxv32i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i16( %m, %y, %a, i32 %evl) ret %u } @@ -1250,11 +1104,9 @@ define @vmadd_vv_nxv32i16_unmasked( %a, < ; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1266,10 +1118,8 @@ define @vmadd_vx_nxv32i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i16( %m, %y, %a, i32 %evl) ret %u } @@ -1282,11 +1132,9 @@ define @vmadd_vx_nxv32i16_unmasked( %a, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i16( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i16( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1298,10 +1146,8 @@ define @vmadd_vv_nxv32i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i16( %m, %y, %a, i32 %evl) ret %u } @@ -1315,10 +1161,8 @@ define @vmadd_vx_nxv32i16_ta( %a, i16 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv32i16( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv32i16( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i16( %m, %y, %a, i32 %evl) ret %u } @@ -1336,10 +1180,8 @@ define @vmadd_vv_nxv1i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i32( %m, %y, %a, i32 %evl) ret %u } @@ -1352,11 +1194,9 @@ define @vmadd_vv_nxv1i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1368,10 +1208,8 @@ define @vmadd_vx_nxv1i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i32( %m, %y, %a, i32 %evl) ret %u } @@ -1384,11 +1222,9 @@ define @vmadd_vx_nxv1i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1399,10 +1235,8 @@ define @vmadd_vv_nxv1i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i32( %m, %y, %a, i32 %evl) ret %u } @@ -1416,10 +1250,8 @@ define @vmadd_vx_nxv1i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i32( %m, %y, %a, i32 %evl) ret %u } @@ -1437,10 +1269,8 @@ define @vmadd_vv_nxv2i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i32( %m, %y, %a, i32 %evl) ret %u } @@ -1453,11 +1283,9 @@ define @vmadd_vv_nxv2i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1469,10 +1297,8 @@ define @vmadd_vx_nxv2i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i32( %m, %y, %a, i32 %evl) ret %u } @@ -1485,11 +1311,9 @@ define @vmadd_vx_nxv2i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1500,10 +1324,8 @@ define @vmadd_vv_nxv2i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i32( %m, %y, %a, i32 %evl) ret %u } @@ -1517,10 +1339,8 @@ define @vmadd_vx_nxv2i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i32( %m, %y, %a, i32 %evl) ret %u } @@ -1538,10 +1358,8 @@ define @vmadd_vv_nxv4i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i32( %m, %y, %a, i32 %evl) ret %u } @@ -1554,11 +1372,9 @@ define @vmadd_vv_nxv4i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1570,10 +1386,8 @@ define @vmadd_vx_nxv4i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i32( %m, %y, %a, i32 %evl) ret %u } @@ -1586,11 +1400,9 @@ define @vmadd_vx_nxv4i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1601,10 +1413,8 @@ define @vmadd_vv_nxv4i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i32( %m, %y, %a, i32 %evl) ret %u } @@ -1618,10 +1428,8 @@ define @vmadd_vx_nxv4i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i32( %m, %y, %a, i32 %evl) ret %u } @@ -1639,10 +1447,8 @@ define @vmadd_vv_nxv8i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i32( %m, %y, %a, i32 %evl) ret %u } @@ -1655,11 +1461,9 @@ define @vmadd_vv_nxv8i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1671,10 +1475,8 @@ define @vmadd_vx_nxv8i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i32( %m, %y, %a, i32 %evl) ret %u } @@ -1687,11 +1489,9 @@ define @vmadd_vx_nxv8i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1702,10 +1502,8 @@ define @vmadd_vv_nxv8i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i32( %m, %y, %a, i32 %evl) ret %u } @@ -1719,10 +1517,8 @@ define @vmadd_vx_nxv8i32_ta( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i32( %m, %y, %a, i32 %evl) ret %u } @@ -1741,10 +1537,8 @@ define @vmadd_vv_nxv16i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i32( %m, %y, %a, i32 %evl) ret %u } @@ -1758,11 +1552,9 @@ define @vmadd_vv_nxv16i32_unmasked( %a, < ; CHECK-NEXT: vsetvli zero, zero, e32, m8, tu, ma ; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1774,10 +1566,8 @@ define @vmadd_vx_nxv16i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i32( %m, %y, %a, i32 %evl) ret %u } @@ -1790,11 +1580,9 @@ define @vmadd_vx_nxv16i32_unmasked( %a, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i32( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i32( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1806,10 +1594,8 @@ define @vmadd_vv_nxv16i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i32( %m, %y, %a, i32 %evl) ret %u } @@ -1823,10 +1609,8 @@ define @vmadd_vx_nxv16i32_ta( %a, i32 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv16i32( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv16i32( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i32( %m, %y, %a, i32 %evl) ret %u } @@ -1844,10 +1628,8 @@ define @vmadd_vv_nxv1i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i64( %m, %y, %a, i32 %evl) ret %u } @@ -1860,11 +1642,9 @@ define @vmadd_vv_nxv1i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1892,10 +1672,8 @@ define @vmadd_vx_nxv1i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i64( %m, %y, %a, i32 %evl) ret %u } @@ -1924,11 +1702,9 @@ define @vmadd_vx_nxv1i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -1939,10 +1715,8 @@ define @vmadd_vv_nxv1i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i64( %m, %y, %a, i32 %evl) ret %u } @@ -1971,10 +1745,8 @@ define @vmadd_vx_nxv1i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv1i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv1i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i64( %m, %y, %a, i32 %evl) ret %u } @@ -1992,10 +1764,8 @@ define @vmadd_vv_nxv2i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i64( %m, %y, %a, i32 %evl) ret %u } @@ -2008,11 +1778,9 @@ define @vmadd_vv_nxv2i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -2040,10 +1808,8 @@ define @vmadd_vx_nxv2i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i64( %m, %y, %a, i32 %evl) ret %u } @@ -2072,11 +1838,9 @@ define @vmadd_vx_nxv2i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -2087,10 +1851,8 @@ define @vmadd_vv_nxv2i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i64( %m, %y, %a, i32 %evl) ret %u } @@ -2119,10 +1881,8 @@ define @vmadd_vx_nxv2i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv2i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv2i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i64( %m, %y, %a, i32 %evl) ret %u } @@ -2140,10 +1900,8 @@ define @vmadd_vv_nxv4i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i64( %m, %y, %a, i32 %evl) ret %u } @@ -2156,11 +1914,9 @@ define @vmadd_vv_nxv4i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -2188,10 +1944,8 @@ define @vmadd_vx_nxv4i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i64( %m, %y, %a, i32 %evl) ret %u } @@ -2220,11 +1974,9 @@ define @vmadd_vx_nxv4i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -2235,10 +1987,8 @@ define @vmadd_vv_nxv4i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i64( %m, %y, %a, i32 %evl) ret %u } @@ -2267,10 +2017,8 @@ define @vmadd_vx_nxv4i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv4i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv4i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i64( %m, %y, %a, i32 %evl) ret %u } @@ -2289,10 +2037,8 @@ define @vmadd_vv_nxv8i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i64( %m, %y, %a, i32 %evl) ret %u } @@ -2306,11 +2052,9 @@ define @vmadd_vv_nxv8i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -2338,10 +2082,8 @@ define @vmadd_vx_nxv8i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i64( %m, %y, %a, i32 %evl) ret %u } @@ -2370,11 +2112,9 @@ define @vmadd_vx_nxv8i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i64( %allones, %y, %a, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %a, i32 %evl) ret %u } @@ -2386,10 +2126,8 @@ define @vmadd_vv_nxv8i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i64( %m, %y, %a, i32 %evl) ret %u } @@ -2418,10 +2156,8 @@ define @vmadd_vx_nxv8i64_ta( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.add.nxv8i64( %x, %c, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.add.nxv8i64( %x, %c, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i64( %m, %y, %a, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll index d243c89958c5..91ea33733560 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll @@ -159,9 +159,7 @@ define @vmnand_vv_nxv1i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -172,9 +170,7 @@ define @vmnand_vv_nxv2i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -185,9 +181,7 @@ define @vmnand_vv_nxv4i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -198,9 +192,7 @@ define @vmnand_vv_nxv8i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -211,9 +203,7 @@ define @vmnand_vv_nxv16i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -224,9 +214,7 @@ define @vmnor_vv_nxv1i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -237,9 +225,7 @@ define @vmnor_vv_nxv2i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -250,9 +236,7 @@ define @vmnor_vv_nxv4i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -263,9 +247,7 @@ define @vmnor_vv_nxv8i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -276,9 +258,7 @@ define @vmnor_vv_nxv16i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -289,9 +269,7 @@ define @vmxnor_vv_nxv1i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -302,9 +280,7 @@ define @vmxnor_vv_nxv2i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -315,9 +291,7 @@ define @vmxnor_vv_nxv4i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -328,9 +302,7 @@ define @vmxnor_vv_nxv8i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -341,9 +313,7 @@ define @vmxnor_vv_nxv16i1( %va, %va, %vb - %head = insertelement poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vc, %splat + %not = xor %vc, splat (i1 1) ret %not } @@ -353,9 +323,7 @@ define @vmandn_vv_nxv1i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = and %va, %not ret %vc } @@ -366,9 +334,7 @@ define @vmandn_vv_nxv2i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = and %va, %not ret %vc } @@ -379,9 +345,7 @@ define @vmandn_vv_nxv4i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = and %va, %not ret %vc } @@ -392,9 +356,7 @@ define @vmandn_vv_nxv8i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = and %va, %not ret %vc } @@ -405,9 +367,7 @@ define @vmandn_vv_nxv16i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = and %va, %not ret %vc } @@ -418,9 +378,7 @@ define @vmorn_vv_nxv1i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = or %va, %not ret %vc } @@ -431,9 +389,7 @@ define @vmorn_vv_nxv2i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = or %va, %not ret %vc } @@ -444,9 +400,7 @@ define @vmorn_vv_nxv4i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = or %va, %not ret %vc } @@ -457,9 +411,7 @@ define @vmorn_vv_nxv8i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = or %va, %not ret %vc } @@ -470,9 +422,7 @@ define @vmorn_vv_nxv16i1( %va, poison, i1 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %not = xor %vb, %splat + %not = xor %vb, splat (i1 1) %vc = or %va, %not ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll index 1247f3d29c09..52720755dd5b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll @@ -33,10 +33,8 @@ define @vmax_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -71,10 +69,8 @@ define @vmax_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -109,10 +105,8 @@ define @vmax_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -147,10 +141,8 @@ define @vmax_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -185,10 +177,8 @@ define @vmax_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -223,10 +213,8 @@ define @vmax_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -261,10 +249,8 @@ define @vmax_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -299,10 +285,8 @@ define @vmax_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -337,10 +321,8 @@ define @vmax_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -375,10 +357,8 @@ define @vmax_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -413,10 +393,8 @@ define @vmax_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -451,10 +429,8 @@ define @vmax_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -489,10 +465,8 @@ define @vmax_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -527,10 +501,8 @@ define @vmax_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -565,10 +537,8 @@ define @vmax_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -603,10 +573,8 @@ define @vmax_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -641,10 +609,8 @@ define @vmax_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -679,10 +645,8 @@ define @vmax_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -730,10 +694,8 @@ define @vmax_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -781,10 +743,8 @@ define @vmax_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -832,10 +792,8 @@ define @vmax_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -883,9 +841,7 @@ define @vmax_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmax.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp sgt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp sgt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll index c69f5fdb5b71..a35fc874065a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll @@ -39,9 +39,7 @@ define @vmax_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -77,9 +75,7 @@ define @vmax_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -101,9 +97,7 @@ define @vmax_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -127,9 +121,7 @@ define @vmax_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -151,9 +143,7 @@ define @vmax_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -177,9 +167,7 @@ define @vmax_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -201,9 +189,7 @@ define @vmax_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -227,9 +213,7 @@ define @vmax_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -251,9 +235,7 @@ define @vmax_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -277,9 +259,7 @@ define @vmax_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -301,9 +281,7 @@ define @vmax_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -327,9 +305,7 @@ define @vmax_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -351,9 +327,7 @@ define @vmax_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -377,9 +351,7 @@ define @vmax_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -401,9 +373,7 @@ define @vmax_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -427,9 +397,7 @@ define @vmax_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -485,9 +453,7 @@ define @vmax_vx_nxv128i8_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv128i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -509,9 +475,7 @@ define @vmax_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -535,9 +499,7 @@ define @vmax_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -559,9 +521,7 @@ define @vmax_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -585,9 +545,7 @@ define @vmax_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -609,9 +567,7 @@ define @vmax_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -635,9 +591,7 @@ define @vmax_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -659,9 +613,7 @@ define @vmax_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -685,9 +637,7 @@ define @vmax_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -709,9 +659,7 @@ define @vmax_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -735,9 +683,7 @@ define @vmax_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -759,9 +705,7 @@ define @vmax_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -785,9 +729,7 @@ define @vmax_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -809,9 +751,7 @@ define @vmax_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -835,9 +775,7 @@ define @vmax_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -859,9 +797,7 @@ define @vmax_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -885,9 +821,7 @@ define @vmax_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -909,9 +843,7 @@ define @vmax_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -935,9 +867,7 @@ define @vmax_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -959,9 +889,7 @@ define @vmax_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -985,9 +913,7 @@ define @vmax_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1009,9 +935,7 @@ define @vmax_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vmax.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1035,9 +959,7 @@ define @vmax_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1094,9 +1016,7 @@ define @vmax_vx_nxv32i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv32i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1194,9 +1114,7 @@ define @vmax_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1248,9 +1166,7 @@ define @vmax_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1272,9 +1188,7 @@ define @vmax_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1326,9 +1240,7 @@ define @vmax_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1350,9 +1262,7 @@ define @vmax_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1404,9 +1314,7 @@ define @vmax_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1428,9 +1336,7 @@ define @vmax_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1482,8 +1388,6 @@ define @vmax_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smax.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smax.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll index a6693fad8dd5..8eb70fbc91fa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll @@ -33,10 +33,8 @@ define @vmax_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -71,10 +69,8 @@ define @vmax_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -109,10 +105,8 @@ define @vmax_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -147,10 +141,8 @@ define @vmax_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -185,10 +177,8 @@ define @vmax_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -223,10 +213,8 @@ define @vmax_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -261,10 +249,8 @@ define @vmax_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -299,10 +285,8 @@ define @vmax_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -337,10 +321,8 @@ define @vmax_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -375,10 +357,8 @@ define @vmax_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -413,10 +393,8 @@ define @vmax_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -451,10 +429,8 @@ define @vmax_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -489,10 +465,8 @@ define @vmax_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -527,10 +501,8 @@ define @vmax_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -565,10 +537,8 @@ define @vmax_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -603,10 +573,8 @@ define @vmax_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -641,10 +609,8 @@ define @vmax_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -679,10 +645,8 @@ define @vmax_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -730,10 +694,8 @@ define @vmax_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -781,10 +743,8 @@ define @vmax_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -832,10 +792,8 @@ define @vmax_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -883,10 +841,8 @@ define @vmax_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmaxu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ugt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ugt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -928,9 +884,7 @@ define @vmax_vi_mask_nxv8i32( %va, poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 -3), zeroinitializer %cmp = icmp ugt %va, %vs %vc = select %cmp, %va, %vs ret %vc diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll index a7fce573da9f..1f620a44dbbc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll @@ -41,9 +41,7 @@ define @vmaxu_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -79,9 +77,7 @@ define @vmaxu_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -103,9 +99,7 @@ define @vmaxu_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -129,9 +123,7 @@ define @vmaxu_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -153,9 +145,7 @@ define @vmaxu_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -179,9 +169,7 @@ define @vmaxu_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -203,9 +191,7 @@ define @vmaxu_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -229,9 +215,7 @@ define @vmaxu_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -253,9 +237,7 @@ define @vmaxu_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -279,9 +261,7 @@ define @vmaxu_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -303,9 +283,7 @@ define @vmaxu_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -329,9 +307,7 @@ define @vmaxu_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -353,9 +329,7 @@ define @vmaxu_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -379,9 +353,7 @@ define @vmaxu_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -403,9 +375,7 @@ define @vmaxu_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -429,9 +399,7 @@ define @vmaxu_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -487,9 +455,7 @@ define @vmaxu_vx_nxv128i8_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv128i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -511,9 +477,7 @@ define @vmaxu_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -537,9 +501,7 @@ define @vmaxu_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -561,9 +523,7 @@ define @vmaxu_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -587,9 +547,7 @@ define @vmaxu_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -611,9 +569,7 @@ define @vmaxu_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -637,9 +593,7 @@ define @vmaxu_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -661,9 +615,7 @@ define @vmaxu_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -687,9 +639,7 @@ define @vmaxu_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -711,9 +661,7 @@ define @vmaxu_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -737,9 +685,7 @@ define @vmaxu_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -761,9 +707,7 @@ define @vmaxu_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -787,9 +731,7 @@ define @vmaxu_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -811,9 +753,7 @@ define @vmaxu_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -837,9 +777,7 @@ define @vmaxu_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -861,9 +799,7 @@ define @vmaxu_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -887,9 +823,7 @@ define @vmaxu_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -911,9 +845,7 @@ define @vmaxu_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -937,9 +869,7 @@ define @vmaxu_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -961,9 +891,7 @@ define @vmaxu_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -987,9 +915,7 @@ define @vmaxu_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1011,9 +937,7 @@ define @vmaxu_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vmaxu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1037,9 +961,7 @@ define @vmaxu_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1096,9 +1018,7 @@ define @vmaxu_vx_nxv32i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv32i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1196,9 +1116,7 @@ define @vmaxu_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1250,9 +1168,7 @@ define @vmaxu_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1274,9 +1190,7 @@ define @vmaxu_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1328,9 +1242,7 @@ define @vmaxu_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1352,9 +1264,7 @@ define @vmaxu_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1406,9 +1316,7 @@ define @vmaxu_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1430,9 +1338,7 @@ define @vmaxu_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1484,8 +1390,6 @@ define @vmaxu_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umax.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umax.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll index 7405282a07b7..7f526a21deac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll @@ -33,10 +33,8 @@ define @vmin_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -71,10 +69,8 @@ define @vmin_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -109,10 +105,8 @@ define @vmin_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -147,10 +141,8 @@ define @vmin_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -185,10 +177,8 @@ define @vmin_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -223,10 +213,8 @@ define @vmin_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -261,10 +249,8 @@ define @vmin_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -299,10 +285,8 @@ define @vmin_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -337,10 +321,8 @@ define @vmin_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -375,10 +357,8 @@ define @vmin_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -413,10 +393,8 @@ define @vmin_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -451,10 +429,8 @@ define @vmin_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -489,10 +465,8 @@ define @vmin_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -527,10 +501,8 @@ define @vmin_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -565,10 +537,8 @@ define @vmin_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -603,10 +573,8 @@ define @vmin_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -641,10 +609,8 @@ define @vmin_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -679,10 +645,8 @@ define @vmin_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -730,10 +694,8 @@ define @vmin_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -781,10 +743,8 @@ define @vmin_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -832,10 +792,8 @@ define @vmin_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -883,9 +841,7 @@ define @vmin_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmin.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp slt %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp slt %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll index 95c5cda5e988..8fabf93356ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll @@ -39,9 +39,7 @@ define @vmin_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -77,9 +75,7 @@ define @vmin_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -101,9 +97,7 @@ define @vmin_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -127,9 +121,7 @@ define @vmin_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -151,9 +143,7 @@ define @vmin_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -177,9 +167,7 @@ define @vmin_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -201,9 +189,7 @@ define @vmin_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -227,9 +213,7 @@ define @vmin_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -251,9 +235,7 @@ define @vmin_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -277,9 +259,7 @@ define @vmin_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -301,9 +281,7 @@ define @vmin_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -327,9 +305,7 @@ define @vmin_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -351,9 +327,7 @@ define @vmin_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -377,9 +351,7 @@ define @vmin_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -401,9 +373,7 @@ define @vmin_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -427,9 +397,7 @@ define @vmin_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -485,9 +453,7 @@ define @vmin_vx_nxv128i8_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv128i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -509,9 +475,7 @@ define @vmin_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -535,9 +499,7 @@ define @vmin_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -559,9 +521,7 @@ define @vmin_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -585,9 +545,7 @@ define @vmin_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -609,9 +567,7 @@ define @vmin_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -635,9 +591,7 @@ define @vmin_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -659,9 +613,7 @@ define @vmin_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -685,9 +637,7 @@ define @vmin_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -709,9 +659,7 @@ define @vmin_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -735,9 +683,7 @@ define @vmin_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -759,9 +705,7 @@ define @vmin_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -785,9 +729,7 @@ define @vmin_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -809,9 +751,7 @@ define @vmin_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -835,9 +775,7 @@ define @vmin_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -859,9 +797,7 @@ define @vmin_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -885,9 +821,7 @@ define @vmin_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -909,9 +843,7 @@ define @vmin_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -935,9 +867,7 @@ define @vmin_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -959,9 +889,7 @@ define @vmin_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -985,9 +913,7 @@ define @vmin_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1009,9 +935,7 @@ define @vmin_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vmin.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1035,9 +959,7 @@ define @vmin_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1094,9 +1016,7 @@ define @vmin_vx_nxv32i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv32i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1194,9 +1114,7 @@ define @vmin_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1248,9 +1166,7 @@ define @vmin_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1272,9 +1188,7 @@ define @vmin_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1326,9 +1240,7 @@ define @vmin_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1350,9 +1262,7 @@ define @vmin_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1404,9 +1314,7 @@ define @vmin_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1428,9 +1336,7 @@ define @vmin_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1482,8 +1388,6 @@ define @vmin_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.smin.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.smin.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll index 2fbe87742a4c..d22a7dcccf0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll @@ -33,10 +33,8 @@ define @vmin_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -71,10 +69,8 @@ define @vmin_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -109,10 +105,8 @@ define @vmin_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -147,10 +141,8 @@ define @vmin_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -185,10 +177,8 @@ define @vmin_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -223,10 +213,8 @@ define @vmin_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -261,10 +249,8 @@ define @vmin_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i8 -3) + %vc = select %cmp, %va, splat (i8 -3) ret %vc } @@ -299,10 +285,8 @@ define @vmin_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -337,10 +321,8 @@ define @vmin_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -375,10 +357,8 @@ define @vmin_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -413,10 +393,8 @@ define @vmin_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -451,10 +429,8 @@ define @vmin_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -489,10 +465,8 @@ define @vmin_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i16 -3) + %vc = select %cmp, %va, splat (i16 -3) ret %vc } @@ -527,10 +501,8 @@ define @vmin_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -565,10 +537,8 @@ define @vmin_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -603,10 +573,8 @@ define @vmin_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -641,10 +609,8 @@ define @vmin_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -679,10 +645,8 @@ define @vmin_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i32 -3) + %vc = select %cmp, %va, splat (i32 -3) ret %vc } @@ -730,10 +694,8 @@ define @vmin_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -781,10 +743,8 @@ define @vmin_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -832,10 +792,8 @@ define @vmin_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -883,10 +841,8 @@ define @vmin_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vminu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %cmp = icmp ult %va, %splat - %vc = select %cmp, %va, %splat + %cmp = icmp ult %va, splat (i64 -3) + %vc = select %cmp, %va, splat (i64 -3) ret %vc } @@ -898,9 +854,7 @@ define @vmin_vv_mask_nxv8i32( %va, poison, i32 -1, i32 0 - %max = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %max + %vs = select %mask, %vb, splat (i32 -1) %cmp = icmp ult %va, %vs %vc = select %cmp, %va, %vs ret %vc @@ -914,11 +868,9 @@ define @vmin_vx_mask_nxv8i32( %va, i32 sign ; CHECK-NEXT: vmerge.vxm v12, v12, a0, v0 ; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head0 = insertelement poison, i32 -1, i32 0 - %max = shufflevector %head0, poison, zeroinitializer %head1 = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head1, poison, zeroinitializer - %vs = select %mask, %splat, %max + %vs = select %mask, %splat, splat (i32 -1) %cmp = icmp ult %va, %vs %vc = select %cmp, %va, %vs ret %vc @@ -932,11 +884,7 @@ define @vmin_vi_mask_nxv8i32( %va, poison, i32 -1, i32 0 - %max = shufflevector %head0, poison, zeroinitializer - %head1 = insertelement poison, i32 -3, i32 0 - %splat = shufflevector %head1, poison, zeroinitializer - %vs = select %mask, %splat, %max + %vs = select %mask, splat (i32 -3), splat (i32 -1) %cmp = icmp ult %va, %vs %vc = select %cmp, %va, %vs ret %vc diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll index d3d5d6ece9b4..8ec85e545a0f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll @@ -41,9 +41,7 @@ define @vminu_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -79,9 +77,7 @@ define @vminu_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -103,9 +99,7 @@ define @vminu_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -129,9 +123,7 @@ define @vminu_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -153,9 +145,7 @@ define @vminu_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -179,9 +169,7 @@ define @vminu_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -203,9 +191,7 @@ define @vminu_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -229,9 +215,7 @@ define @vminu_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -253,9 +237,7 @@ define @vminu_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -279,9 +261,7 @@ define @vminu_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -303,9 +283,7 @@ define @vminu_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -329,9 +307,7 @@ define @vminu_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -353,9 +329,7 @@ define @vminu_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -379,9 +353,7 @@ define @vminu_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -403,9 +375,7 @@ define @vminu_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -429,9 +399,7 @@ define @vminu_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -487,9 +455,7 @@ define @vminu_vx_nxv128i8_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv128i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -511,9 +477,7 @@ define @vminu_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -537,9 +501,7 @@ define @vminu_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -561,9 +523,7 @@ define @vminu_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -587,9 +547,7 @@ define @vminu_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -611,9 +569,7 @@ define @vminu_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -637,9 +593,7 @@ define @vminu_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -661,9 +615,7 @@ define @vminu_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -687,9 +639,7 @@ define @vminu_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -711,9 +661,7 @@ define @vminu_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -737,9 +685,7 @@ define @vminu_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -761,9 +707,7 @@ define @vminu_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -787,9 +731,7 @@ define @vminu_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -811,9 +753,7 @@ define @vminu_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -837,9 +777,7 @@ define @vminu_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -861,9 +799,7 @@ define @vminu_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -887,9 +823,7 @@ define @vminu_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -911,9 +845,7 @@ define @vminu_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -937,9 +869,7 @@ define @vminu_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -961,9 +891,7 @@ define @vminu_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -987,9 +915,7 @@ define @vminu_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1011,9 +937,7 @@ define @vminu_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vminu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1037,9 +961,7 @@ define @vminu_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1096,9 +1018,7 @@ define @vminu_vx_nxv32i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv32i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1196,9 +1116,7 @@ define @vminu_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1250,9 +1168,7 @@ define @vminu_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1274,9 +1190,7 @@ define @vminu_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1328,9 +1242,7 @@ define @vminu_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1352,9 +1264,7 @@ define @vminu_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1406,9 +1316,7 @@ define @vminu_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1430,9 +1338,7 @@ define @vminu_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1484,8 +1390,6 @@ define @vminu_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.umin.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.umin.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll index 3e14058210e5..1a6d5a1d0029 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll @@ -34,9 +34,7 @@ define @vmul_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -69,9 +67,7 @@ define @vmul_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -104,9 +100,7 @@ define @vmul_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -139,9 +133,7 @@ define @vmul_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -174,9 +166,7 @@ define @vmul_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -209,9 +199,7 @@ define @vmul_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -244,9 +232,7 @@ define @vmul_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i8 -7) ret %vc } @@ -279,9 +265,7 @@ define @vmul_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i16 -7) ret %vc } @@ -314,9 +298,7 @@ define @vmul_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i16 -7) ret %vc } @@ -349,9 +331,7 @@ define @vmul_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i16 -7) ret %vc } @@ -384,9 +364,7 @@ define @vmul_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i16 -7) ret %vc } @@ -419,9 +397,7 @@ define @vmul_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i16 -7) ret %vc } @@ -454,9 +430,7 @@ define @vmul_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i16 -7) ret %vc } @@ -489,9 +463,7 @@ define @vmul_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i32 -7) ret %vc } @@ -524,9 +496,7 @@ define @vmul_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i32 -7) ret %vc } @@ -559,9 +529,7 @@ define @vmul_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i32 -7) ret %vc } @@ -594,9 +562,7 @@ define @vmul_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i32 -7) ret %vc } @@ -629,9 +595,7 @@ define @vmul_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i32 -7) ret %vc } @@ -677,9 +641,7 @@ define @vmul_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 -7) ret %vc } @@ -689,9 +651,7 @@ define @vmul_vi_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 2) ret %vc } @@ -701,9 +661,7 @@ define @vmul_vi_nxv1i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 16) ret %vc } @@ -749,9 +707,7 @@ define @vmul_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 -7) ret %vc } @@ -761,9 +717,7 @@ define @vmul_vi_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 2) ret %vc } @@ -773,9 +727,7 @@ define @vmul_vi_nxv2i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 16) ret %vc } @@ -821,9 +773,7 @@ define @vmul_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 -7) ret %vc } @@ -833,9 +783,7 @@ define @vmul_vi_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 2) ret %vc } @@ -845,9 +793,7 @@ define @vmul_vi_nxv4i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 16) ret %vc } @@ -893,9 +839,7 @@ define @vmul_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmul.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 -7) ret %vc } @@ -905,9 +849,7 @@ define @vmul_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 2) ret %vc } @@ -917,9 +859,7 @@ define @vmul_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = mul %va, %splat + %vc = mul %va, splat (i64 16) ret %vc } @@ -967,9 +907,7 @@ define @vmul_vv_mask_nxv8i32( %va, poison, i32 1, i32 0 - %one = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %vb, %one + %vs = select %mask, %vb, splat (i32 1) %vc = mul %va, %vs ret %vc } @@ -980,11 +918,9 @@ define @vmul_vx_mask_nxv8i32( %va, i32 sign ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 1, i32 0 - %one = shufflevector %head1, poison, zeroinitializer %head2 = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %one + %vs = select %mask, %splat, splat (i32 1) %vc = mul %va, %vs ret %vc } @@ -996,11 +932,7 @@ define @vmul_vi_mask_nxv8i32( %va, poison, i32 1, i32 0 - %one = shufflevector %head1, poison, zeroinitializer - %head2 = insertelement poison, i32 7, i32 0 - %splat = shufflevector %head2, poison, zeroinitializer - %vs = select %mask, %splat, %one + %vs = select %mask, splat (i32 7), splat (i32 1) %vc = mul %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll index 30ff90d8aa48..24d1768da102 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll @@ -36,9 +36,7 @@ define @vmul_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -62,9 +60,7 @@ define @vmul_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -86,9 +82,7 @@ define @vmul_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -112,9 +106,7 @@ define @vmul_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -136,9 +128,7 @@ define @vmul_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -162,9 +152,7 @@ define @vmul_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -186,9 +174,7 @@ define @vmul_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -212,9 +198,7 @@ define @vmul_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -236,9 +220,7 @@ define @vmul_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -262,9 +244,7 @@ define @vmul_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -286,9 +266,7 @@ define @vmul_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -312,9 +290,7 @@ define @vmul_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -336,9 +312,7 @@ define @vmul_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -362,9 +336,7 @@ define @vmul_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -386,9 +358,7 @@ define @vmul_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -412,9 +382,7 @@ define @vmul_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -436,9 +404,7 @@ define @vmul_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -462,9 +428,7 @@ define @vmul_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -486,9 +450,7 @@ define @vmul_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +474,7 @@ define @vmul_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -536,9 +496,7 @@ define @vmul_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -562,9 +520,7 @@ define @vmul_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -586,9 +542,7 @@ define @vmul_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -612,9 +566,7 @@ define @vmul_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -636,9 +588,7 @@ define @vmul_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -662,9 +612,7 @@ define @vmul_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -686,9 +634,7 @@ define @vmul_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -712,9 +658,7 @@ define @vmul_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -736,9 +680,7 @@ define @vmul_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -762,9 +704,7 @@ define @vmul_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -786,9 +726,7 @@ define @vmul_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -812,9 +750,7 @@ define @vmul_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -836,9 +772,7 @@ define @vmul_vv_nxv7i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv7i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv7i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -862,9 +796,7 @@ define @vmul_vx_nxv7i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv7i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv7i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -886,9 +818,7 @@ define @vmul_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -912,9 +842,7 @@ define @vmul_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -936,9 +864,7 @@ define @vmul_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vmul.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -974,9 +900,7 @@ define @vmul_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -998,9 +922,7 @@ define @vmul_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1052,9 +974,7 @@ define @vmul_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1076,9 +996,7 @@ define @vmul_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1130,9 +1048,7 @@ define @vmul_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1154,9 +1070,7 @@ define @vmul_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1208,9 +1122,7 @@ define @vmul_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1232,9 +1144,7 @@ define @vmul_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1286,8 +1196,6 @@ define @vmul_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.mul.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.mul.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll index 0fda7909df31..253cfb040308 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll @@ -17,9 +17,7 @@ define @srem_eq_fold_nxv4i8( %va) { ; CHECK-NEXT: vor.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vx v0, v8, a0 ; CHECK-NEXT: ret - %head_six = insertelement poison, i8 6, i32 0 - %splat_six = shufflevector %head_six, poison, zeroinitializer - %rem = srem %va, %splat_six + %rem = srem %va, splat (i8 6) %cc = icmp eq %rem, zeroinitializer ret %cc @@ -34,9 +32,7 @@ define @vmulh_vv_nxv1i32( %va, %vb to %vd = sext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -52,9 +48,7 @@ define @vmulh_vx_nxv1i32( %va, i32 %x) { %vb = sext %splat1 to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -66,14 +60,10 @@ define @vmulh_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 -7) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -85,14 +75,10 @@ define @vmulh_vi_nxv1i32_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 16) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -106,9 +92,7 @@ define @vmulh_vv_nxv2i32( %va, %vb to %vd = sext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -124,9 +108,7 @@ define @vmulh_vx_nxv2i32( %va, i32 %x) { %vb = sext %splat1 to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -138,14 +120,10 @@ define @vmulh_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 -7) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -157,14 +135,10 @@ define @vmulh_vi_nxv2i32_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 16) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -178,9 +152,7 @@ define @vmulh_vv_nxv4i32( %va, %vb to %vd = sext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -196,9 +168,7 @@ define @vmulh_vx_nxv4i32( %va, i32 %x) { %vb = sext %splat1 to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -210,14 +180,10 @@ define @vmulh_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 -7) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -229,14 +195,10 @@ define @vmulh_vi_nxv4i32_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 16) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -250,9 +212,7 @@ define @vmulh_vv_nxv8i32( %va, %vb to %vd = sext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -268,9 +228,7 @@ define @vmulh_vx_nxv8i32( %va, i32 %x) { %vb = sext %splat1 to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -282,14 +240,10 @@ define @vmulh_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 -7) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -301,14 +255,10 @@ define @vmulh_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulh.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = sext %splat1 to + %vb = sext splat (i32 16) to %vc = sext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll index 5354c17fd2a7..3fd7f5be860c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll @@ -11,9 +11,7 @@ define @vmulhu_vv_nxv1i32( %va, %vb to %vd = zext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -29,9 +27,7 @@ define @vmulhu_vx_nxv1i32( %va, i32 %x) { %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -43,14 +39,10 @@ define @vmulhu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 -7) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -68,14 +60,10 @@ define @vmulhu_vi_nxv1i32_1( %va) { ; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 16) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -89,9 +77,7 @@ define @vmulhu_vv_nxv2i32( %va, %vb to %vd = zext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -107,9 +93,7 @@ define @vmulhu_vx_nxv2i32( %va, i32 %x) { %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -121,14 +105,10 @@ define @vmulhu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 -7) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -146,14 +126,10 @@ define @vmulhu_vi_nxv2i32_1( %va) { ; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 16) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -167,9 +143,7 @@ define @vmulhu_vv_nxv4i32( %va, %vb to %vd = zext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -185,9 +159,7 @@ define @vmulhu_vx_nxv4i32( %va, i32 %x) { %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -199,14 +171,10 @@ define @vmulhu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 -7) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -224,14 +192,10 @@ define @vmulhu_vi_nxv4i32_1( %va) { ; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 16) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -245,9 +209,7 @@ define @vmulhu_vv_nxv8i32( %va, %vb to %vd = zext %va to %ve = mul %vc, %vd - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vf = lshr %ve, %splat + %vf = lshr %ve, splat (i64 32) %vg = trunc %vf to ret %vg } @@ -263,9 +225,7 @@ define @vmulhu_vx_nxv8i32( %va, i32 %x) { %vb = zext %splat1 to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -277,14 +237,10 @@ define @vmulhu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vmulhu.vx v8, v8, a0 ; CHECK-NEXT: ret - %head1 = insertelement poison, i32 -7, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 -7) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } @@ -302,14 +258,10 @@ define @vmulhu_vi_nxv8i32_1( %va) { ; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: ret - %head1 = insertelement poison, i32 16, i32 0 - %splat1 = shufflevector %head1, poison, zeroinitializer - %vb = zext %splat1 to + %vb = zext splat (i32 16) to %vc = zext %va to %vd = mul %vb, %vc - %head2 = insertelement poison, i64 32, i32 0 - %splat2 = shufflevector %head2, poison, zeroinitializer - %ve = lshr %vd, %splat2 + %ve = lshr %vd, splat (i64 32) %vf = trunc %ve to ret %vf } diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll index 564f278372cc..f958fe815caa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll @@ -16,10 +16,8 @@ define @vnmsac_vv_nxv1i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -31,11 +29,9 @@ define @vnmsac_vv_nxv1i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -48,10 +44,8 @@ define @vnmsac_vx_nxv1i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -65,11 +59,9 @@ define @vnmsac_vx_nxv1i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -80,10 +72,8 @@ define @vnmsac_vv_nxv1i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -97,10 +87,8 @@ define @vnmsac_vx_nxv1i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i8( %m, %y, %c, i32 %evl) ret %u } @@ -117,10 +105,8 @@ define @vnmsac_vv_nxv2i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -132,11 +118,9 @@ define @vnmsac_vv_nxv2i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -149,10 +133,8 @@ define @vnmsac_vx_nxv2i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -166,11 +148,9 @@ define @vnmsac_vx_nxv2i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -181,10 +161,8 @@ define @vnmsac_vv_nxv2i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -198,10 +176,8 @@ define @vnmsac_vx_nxv2i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i8( %m, %y, %c, i32 %evl) ret %u } @@ -218,10 +194,8 @@ define @vnmsac_vv_nxv4i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -233,11 +207,9 @@ define @vnmsac_vv_nxv4i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -250,10 +222,8 @@ define @vnmsac_vx_nxv4i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -267,11 +237,9 @@ define @vnmsac_vx_nxv4i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -282,10 +250,8 @@ define @vnmsac_vv_nxv4i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -299,10 +265,8 @@ define @vnmsac_vx_nxv4i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i8( %m, %y, %c, i32 %evl) ret %u } @@ -319,10 +283,8 @@ define @vnmsac_vv_nxv8i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -334,11 +296,9 @@ define @vnmsac_vv_nxv8i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -351,10 +311,8 @@ define @vnmsac_vx_nxv8i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -368,11 +326,9 @@ define @vnmsac_vx_nxv8i8_unmasked( %a, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -383,10 +339,8 @@ define @vnmsac_vv_nxv8i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -400,10 +354,8 @@ define @vnmsac_vx_nxv8i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i8( %m, %y, %c, i32 %evl) ret %u } @@ -420,10 +372,8 @@ define @vnmsac_vv_nxv16i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -435,11 +385,9 @@ define @vnmsac_vv_nxv16i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -452,10 +400,8 @@ define @vnmsac_vx_nxv16i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -469,11 +415,9 @@ define @vnmsac_vx_nxv16i8_unmasked( %a, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -484,10 +428,8 @@ define @vnmsac_vv_nxv16i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -501,10 +443,8 @@ define @vnmsac_vx_nxv16i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i8( %m, %y, %c, i32 %evl) ret %u } @@ -521,10 +461,8 @@ define @vnmsac_vv_nxv32i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -536,11 +474,9 @@ define @vnmsac_vv_nxv32i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -553,10 +489,8 @@ define @vnmsac_vx_nxv32i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -570,11 +504,9 @@ define @vnmsac_vx_nxv32i8_unmasked( %a, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -585,10 +517,8 @@ define @vnmsac_vv_nxv32i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -602,10 +532,8 @@ define @vnmsac_vx_nxv32i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i8( %m, %y, %c, i32 %evl) ret %u } @@ -623,10 +551,8 @@ define @vnmsac_vv_nxv64i8( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv64i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv64i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -639,11 +565,9 @@ define @vnmsac_vv_nxv64i8_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv64i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv64i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv64i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv64i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -656,10 +580,8 @@ define @vnmsac_vx_nxv64i8( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv64i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv64i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -673,11 +595,9 @@ define @vnmsac_vx_nxv64i8_unmasked( %a, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv64i8( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv64i8( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv64i8( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv64i8( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -689,10 +609,8 @@ define @vnmsac_vv_nxv64i8_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv64i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv64i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -706,10 +624,8 @@ define @vnmsac_vx_nxv64i8_ta( %a, i8 %b, poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv64i8( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv64i8( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv64i8( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv64i8( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv64i8( %m, %y, %c, i32 %evl) ret %u } @@ -726,10 +642,8 @@ define @vnmsac_vv_nxv1i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -741,11 +655,9 @@ define @vnmsac_vv_nxv1i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -758,10 +670,8 @@ define @vnmsac_vx_nxv1i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -775,11 +685,9 @@ define @vnmsac_vx_nxv1i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -790,10 +698,8 @@ define @vnmsac_vv_nxv1i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -807,10 +713,8 @@ define @vnmsac_vx_nxv1i16_ta( %a, i16 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i16( %m, %y, %c, i32 %evl) ret %u } @@ -827,10 +731,8 @@ define @vnmsac_vv_nxv2i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -842,11 +744,9 @@ define @vnmsac_vv_nxv2i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -859,10 +759,8 @@ define @vnmsac_vx_nxv2i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -876,11 +774,9 @@ define @vnmsac_vx_nxv2i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -891,10 +787,8 @@ define @vnmsac_vv_nxv2i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -908,10 +802,8 @@ define @vnmsac_vx_nxv2i16_ta( %a, i16 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i16( %m, %y, %c, i32 %evl) ret %u } @@ -928,10 +820,8 @@ define @vnmsac_vv_nxv4i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -943,11 +833,9 @@ define @vnmsac_vv_nxv4i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -960,10 +848,8 @@ define @vnmsac_vx_nxv4i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -977,11 +863,9 @@ define @vnmsac_vx_nxv4i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -992,10 +876,8 @@ define @vnmsac_vv_nxv4i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -1009,10 +891,8 @@ define @vnmsac_vx_nxv4i16_ta( %a, i16 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i16( %m, %y, %c, i32 %evl) ret %u } @@ -1029,10 +909,8 @@ define @vnmsac_vv_nxv8i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1044,11 +922,9 @@ define @vnmsac_vv_nxv8i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1061,10 +937,8 @@ define @vnmsac_vx_nxv8i16( %a, i16 %b, poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1078,11 +952,9 @@ define @vnmsac_vx_nxv8i16_unmasked( %a, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1093,10 +965,8 @@ define @vnmsac_vv_nxv8i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1110,10 +980,8 @@ define @vnmsac_vx_nxv8i16_ta( %a, i16 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i16( %m, %y, %c, i32 %evl) ret %u } @@ -1130,10 +998,8 @@ define @vnmsac_vv_nxv16i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1145,11 +1011,9 @@ define @vnmsac_vv_nxv16i16_unmasked( %a, ; CHECK-NEXT: vnmsac.vv v16, v8, v12 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1162,10 +1026,8 @@ define @vnmsac_vx_nxv16i16( %a, i16 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1179,11 +1041,9 @@ define @vnmsac_vx_nxv16i16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1194,10 +1054,8 @@ define @vnmsac_vv_nxv16i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1211,10 +1069,8 @@ define @vnmsac_vx_nxv16i16_ta( %a, i16 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i16( %m, %y, %c, i32 %evl) ret %u } @@ -1232,10 +1088,8 @@ define @vnmsac_vv_nxv32i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1248,11 +1102,9 @@ define @vnmsac_vv_nxv32i16_unmasked( %a, ; CHECK-NEXT: vnmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1265,10 +1117,8 @@ define @vnmsac_vx_nxv32i16( %a, i16 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1282,11 +1132,9 @@ define @vnmsac_vx_nxv32i16_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i16( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv32i16( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i16( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv32i16( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1298,10 +1146,8 @@ define @vnmsac_vv_nxv32i16_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1315,10 +1161,8 @@ define @vnmsac_vx_nxv32i16_ta( %a, i16 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv32i16( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv32i16( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv32i16( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv32i16( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv32i16( %m, %y, %c, i32 %evl) ret %u } @@ -1335,10 +1179,8 @@ define @vnmsac_vv_nxv1i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1350,11 +1192,9 @@ define @vnmsac_vv_nxv1i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1367,10 +1207,8 @@ define @vnmsac_vx_nxv1i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1384,11 +1222,9 @@ define @vnmsac_vx_nxv1i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1399,10 +1235,8 @@ define @vnmsac_vv_nxv1i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1416,10 +1250,8 @@ define @vnmsac_vx_nxv1i32_ta( %a, i32 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i32( %m, %y, %c, i32 %evl) ret %u } @@ -1436,10 +1268,8 @@ define @vnmsac_vv_nxv2i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1451,11 +1281,9 @@ define @vnmsac_vv_nxv2i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1468,10 +1296,8 @@ define @vnmsac_vx_nxv2i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1485,11 +1311,9 @@ define @vnmsac_vx_nxv2i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1500,10 +1324,8 @@ define @vnmsac_vv_nxv2i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1517,10 +1339,8 @@ define @vnmsac_vx_nxv2i32_ta( %a, i32 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i32( %m, %y, %c, i32 %evl) ret %u } @@ -1537,10 +1357,8 @@ define @vnmsac_vv_nxv4i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1552,11 +1370,9 @@ define @vnmsac_vv_nxv4i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1569,10 +1385,8 @@ define @vnmsac_vx_nxv4i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1586,11 +1400,9 @@ define @vnmsac_vx_nxv4i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1601,10 +1413,8 @@ define @vnmsac_vv_nxv4i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1618,10 +1428,8 @@ define @vnmsac_vx_nxv4i32_ta( %a, i32 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i32( %m, %y, %c, i32 %evl) ret %u } @@ -1638,10 +1446,8 @@ define @vnmsac_vv_nxv8i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1653,11 +1459,9 @@ define @vnmsac_vv_nxv8i32_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1670,10 +1474,8 @@ define @vnmsac_vx_nxv8i32( %a, i32 %b, poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1687,11 +1489,9 @@ define @vnmsac_vx_nxv8i32_unmasked( %a, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1702,10 +1502,8 @@ define @vnmsac_vv_nxv8i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1719,10 +1517,8 @@ define @vnmsac_vx_nxv8i32_ta( %a, i32 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i32( %m, %y, %c, i32 %evl) ret %u } @@ -1740,10 +1536,8 @@ define @vnmsac_vv_nxv16i32( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1756,11 +1550,9 @@ define @vnmsac_vv_nxv16i32_unmasked( %a, ; CHECK-NEXT: vnmsac.vv v24, v8, v16 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1773,10 +1565,8 @@ define @vnmsac_vx_nxv16i32( %a, i32 %b, < ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1790,11 +1580,9 @@ define @vnmsac_vx_nxv16i32_unmasked( %a, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i32( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv16i32( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i32( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv16i32( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1806,10 +1594,8 @@ define @vnmsac_vv_nxv16i32_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1823,10 +1609,8 @@ define @vnmsac_vx_nxv16i32_ta( %a, i32 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv16i32( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv16i32( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv16i32( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv16i32( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv16i32( %m, %y, %c, i32 %evl) ret %u } @@ -1843,10 +1627,8 @@ define @vnmsac_vv_nxv1i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1858,11 +1640,9 @@ define @vnmsac_vv_nxv1i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1890,10 +1670,8 @@ define @vnmsac_vx_nxv1i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1922,11 +1700,9 @@ define @vnmsac_vx_nxv1i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv1i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv1i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -1937,10 +1713,8 @@ define @vnmsac_vv_nxv1i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1969,10 +1743,8 @@ define @vnmsac_vx_nxv1i64_ta( %a, i64 %b, < ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv1i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv1i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv1i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv1i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv1i64( %m, %y, %c, i32 %evl) ret %u } @@ -1989,10 +1761,8 @@ define @vnmsac_vv_nxv2i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2004,11 +1774,9 @@ define @vnmsac_vv_nxv2i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2036,10 +1804,8 @@ define @vnmsac_vx_nxv2i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2068,11 +1834,9 @@ define @vnmsac_vx_nxv2i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv2i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv2i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2083,10 +1847,8 @@ define @vnmsac_vv_nxv2i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2115,10 +1877,8 @@ define @vnmsac_vx_nxv2i64_ta( %a, i64 %b, < ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv2i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv2i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv2i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv2i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv2i64( %m, %y, %c, i32 %evl) ret %u } @@ -2135,10 +1895,8 @@ define @vnmsac_vv_nxv4i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2150,11 +1908,9 @@ define @vnmsac_vv_nxv4i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2182,10 +1938,8 @@ define @vnmsac_vx_nxv4i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2214,11 +1968,9 @@ define @vnmsac_vx_nxv4i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv4i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv4i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2229,10 +1981,8 @@ define @vnmsac_vv_nxv4i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2261,10 +2011,8 @@ define @vnmsac_vx_nxv4i64_ta( %a, i64 %b, < ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv4i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv4i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv4i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv4i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv4i64( %m, %y, %c, i32 %evl) ret %u } @@ -2282,10 +2030,8 @@ define @vnmsac_vv_nxv8i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i64( %m, %y, %c, i32 %evl) ret %u } @@ -2298,11 +2044,9 @@ define @vnmsac_vv_nxv8i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2330,10 +2074,8 @@ define @vnmsac_vx_nxv8i64( %a, i64 %b, poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.merge.nxv8i64( %m, %y, %c, i32 %evl) ret %u } @@ -2362,11 +2104,9 @@ define @vnmsac_vx_nxv8i64_unmasked( %a, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i64( %c, %x, %allones, i32 %evl) - %u = call @llvm.vp.merge.nxv8i64( %allones, %y, %c, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i64( %c, %x, splat (i1 -1), i32 %evl) + %u = call @llvm.vp.merge.nxv8i64( splat (i1 -1), %y, %c, i32 %evl) ret %u } @@ -2378,10 +2118,8 @@ define @vnmsac_vv_nxv8i64_ta( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %b, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %b, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i64( %m, %y, %c, i32 %evl) ret %u } @@ -2410,10 +2148,8 @@ define @vnmsac_vx_nxv8i64_ta( %a, i64 %b, < ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %x = call @llvm.vp.mul.nxv8i64( %a, %vb, %allones, i32 %evl) - %y = call @llvm.vp.sub.nxv8i64( %c, %x, %allones, i32 %evl) + %x = call @llvm.vp.mul.nxv8i64( %a, %vb, splat (i1 -1), i32 %evl) + %y = call @llvm.vp.sub.nxv8i64( %c, %x, splat (i1 -1), i32 %evl) %u = call @llvm.vp.select.nxv8i64( %m, %y, %c, i32 %evl) ret %u } diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll index 13b7a8e1991a..7b97ca3c0090 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll @@ -119,9 +119,7 @@ define @vnsra_wi_i32_nxv1i32_sext( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -192,9 +190,7 @@ define @vnsra_wi_i32_nxv2i32_sext( %va) { ; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -265,9 +261,7 @@ define @vnsra_wi_i32_nxv4i32_sext( %va) { ; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -338,9 +332,7 @@ define @vnsra_wi_i32_nxv8i32_sext( %va) { ; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -406,9 +398,7 @@ define @vnsra_wi_i32_nxv1i32_zext( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -479,9 +469,7 @@ define @vnsra_wi_i32_nxv2i32_zext( %va) { ; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -552,9 +540,7 @@ define @vnsra_wi_i32_nxv4i32_zext( %va) { ; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y @@ -625,9 +611,7 @@ define @vnsra_wi_i32_nxv8i32_zext( %va) { ; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = ashr %va, %vb %y = trunc %x to ret %y diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll index 18f743482a56..cb7a020d0b96 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-vp.ll @@ -12,10 +12,8 @@ define @vsra_vv_nxv1i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %v = call @llvm.vp.ashr.nxv1i32( %a, %bext, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.ashr.nxv1i32( %a, %bext, splat (i1 -1), i32 %evl) %vr = call @llvm.vp.trunc.nxv1i16.nxv1i32( %v, %m, i32 %evl) ret %vr } @@ -27,11 +25,9 @@ define @vsra_vv_nxv1i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %head, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %v = call @llvm.vp.ashr.nxv1i32( %a, %bext, %allones, i32 %evl) - %vr = call @llvm.vp.trunc.nxv1i16.nxv1i32( %v, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.ashr.nxv1i32( %a, %bext, splat (i1 -1), i32 %evl) + %vr = call @llvm.vp.trunc.nxv1i16.nxv1i32( %v, splat (i1 -1), i32 %evl) ret %vr } @@ -45,10 +41,8 @@ define @vsra_vv_nxv1i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, %allones, i32 %evl) - %v = call @llvm.vp.ashr.nxv1i64( %a, %bext, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.ashr.nxv1i64( %a, %bext, splat (i1 -1), i32 %evl) %vr = call @llvm.vp.trunc.nxv1i32.nxv1i64( %v, %m, i32 %evl) ret %vr } @@ -59,10 +53,8 @@ define @vsra_vv_nxv1i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, %allones, i32 %evl) - %v = call @llvm.vp.ashr.nxv1i64( %a, %bext, %allones, i32 %evl) - %vr = call @llvm.vp.trunc.nxv1i32.nxv1i64( %v, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.ashr.nxv1i64( %a, %bext, splat (i1 -1), i32 %evl) + %vr = call @llvm.vp.trunc.nxv1i32.nxv1i64( %v, splat (i1 -1), i32 %evl) ret %vr } diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll index 4c1e53cf9a01..2b912662b4b9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll @@ -119,9 +119,7 @@ define @vnsrl_wi_i32_nxv1i32_sext( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -192,9 +190,7 @@ define @vnsrl_wi_i32_nxv2i32_sext( %va) { ; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -265,9 +261,7 @@ define @vnsrl_wi_i32_nxv4i32_sext( %va) { ; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -338,9 +332,7 @@ define @vnsrl_wi_i32_nxv8i32_sext( %va) { ; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = sext %splat to + %vb = sext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -406,9 +398,7 @@ define @vnsrl_wi_i32_nxv1i32_zext( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -479,9 +469,7 @@ define @vnsrl_wi_i32_nxv2i32_zext( %va) { ; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -552,9 +540,7 @@ define @vnsrl_wi_i32_nxv4i32_zext( %va) { ; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y @@ -625,9 +611,7 @@ define @vnsrl_wi_i32_nxv8i32_zext( %va) { ; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vb = zext %splat to + %vb = zext splat (i32 15) to %x = lshr %va, %vb %y = trunc %x to ret %y diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll index 059d5bf3e095..e6e86011745b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-vp.ll @@ -12,10 +12,8 @@ define @vsra_vv_nxv1i16( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %v = call @llvm.vp.lshr.nxv1i32( %a, %bext, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.lshr.nxv1i32( %a, %bext, splat (i1 -1), i32 %evl) %vr = call @llvm.vp.trunc.nxv1i16.nxv1i32( %v, %m, i32 %evl) ret %vr } @@ -27,11 +25,9 @@ define @vsra_vv_nxv1i16_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %head, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %v = call @llvm.vp.lshr.nxv1i32( %a, %bext, %allones, i32 %evl) - %vr = call @llvm.vp.trunc.nxv1i16.nxv1i32( %v, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.lshr.nxv1i32( %a, %bext, splat (i1 -1), i32 %evl) + %vr = call @llvm.vp.trunc.nxv1i16.nxv1i32( %v, splat (i1 -1), i32 %evl) ret %vr } @@ -45,10 +41,8 @@ define @vsra_vv_nxv1i64( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, %allones, i32 %evl) - %v = call @llvm.vp.lshr.nxv1i64( %a, %bext, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.lshr.nxv1i64( %a, %bext, splat (i1 -1), i32 %evl) %vr = call @llvm.vp.trunc.nxv1i32.nxv1i64( %v, %m, i32 %evl) ret %vr } @@ -59,10 +53,8 @@ define @vsra_vv_nxv1i64_unmasked( %a, poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, %allones, i32 %evl) - %v = call @llvm.vp.lshr.nxv1i64( %a, %bext, %allones, i32 %evl) - %vr = call @llvm.vp.trunc.nxv1i32.nxv1i64( %v, %allones, i32 %evl) + %bext = call @llvm.vp.sext.nxv1i64.nxv1i32( %b, splat (i1 -1), i32 %evl) + %v = call @llvm.vp.lshr.nxv1i64( %a, %bext, splat (i1 -1), i32 %evl) + %vr = call @llvm.vp.trunc.nxv1i32.nxv1i64( %v, splat (i1 -1), i32 %evl) ret %vr } diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll index 356467698d94..fbbd71cb3544 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll @@ -20,9 +20,7 @@ define @vor_vx_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -32,9 +30,7 @@ define @vor_vx_nxv1i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -45,9 +41,7 @@ define @vor_vx_nxv1i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -69,9 +63,7 @@ define @vor_vx_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -81,9 +73,7 @@ define @vor_vx_nxv2i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -94,9 +84,7 @@ define @vor_vx_nxv2i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -118,9 +106,7 @@ define @vor_vx_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -130,9 +116,7 @@ define @vor_vx_nxv4i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -143,9 +127,7 @@ define @vor_vx_nxv4i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -167,9 +149,7 @@ define @vor_vx_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -179,9 +159,7 @@ define @vor_vx_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -192,9 +170,7 @@ define @vor_vx_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -216,9 +192,7 @@ define @vor_vx_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -228,9 +202,7 @@ define @vor_vx_nxv16i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -241,9 +213,7 @@ define @vor_vx_nxv16i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -265,9 +235,7 @@ define @vor_vx_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -277,9 +245,7 @@ define @vor_vx_nxv32i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -290,9 +256,7 @@ define @vor_vx_nxv32i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -314,9 +278,7 @@ define @vor_vx_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 -12) ret %vc } @@ -326,9 +288,7 @@ define @vor_vx_nxv64i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i8 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 15) ret %vc } @@ -339,9 +299,7 @@ define @vor_vx_nxv64i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i8 16) ret %vc } @@ -363,9 +321,7 @@ define @vor_vx_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 -12) ret %vc } @@ -375,9 +331,7 @@ define @vor_vx_nxv1i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 15) ret %vc } @@ -388,9 +342,7 @@ define @vor_vx_nxv1i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 16) ret %vc } @@ -412,9 +364,7 @@ define @vor_vx_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 -12) ret %vc } @@ -424,9 +374,7 @@ define @vor_vx_nxv2i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 15) ret %vc } @@ -437,9 +385,7 @@ define @vor_vx_nxv2i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 16) ret %vc } @@ -461,9 +407,7 @@ define @vor_vx_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 -12) ret %vc } @@ -473,9 +417,7 @@ define @vor_vx_nxv4i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 15) ret %vc } @@ -486,9 +428,7 @@ define @vor_vx_nxv4i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 16) ret %vc } @@ -510,9 +450,7 @@ define @vor_vx_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 -12) ret %vc } @@ -522,9 +460,7 @@ define @vor_vx_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 15) ret %vc } @@ -535,9 +471,7 @@ define @vor_vx_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 16) ret %vc } @@ -559,9 +493,7 @@ define @vor_vx_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 -12) ret %vc } @@ -571,9 +503,7 @@ define @vor_vx_nxv16i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 15) ret %vc } @@ -584,9 +514,7 @@ define @vor_vx_nxv16i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 16) ret %vc } @@ -608,9 +536,7 @@ define @vor_vx_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 -12) ret %vc } @@ -620,9 +546,7 @@ define @vor_vx_nxv32i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i16 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 15) ret %vc } @@ -633,9 +557,7 @@ define @vor_vx_nxv32i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i16 16) ret %vc } @@ -657,9 +579,7 @@ define @vor_vx_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 -12) ret %vc } @@ -669,9 +589,7 @@ define @vor_vx_nxv1i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 15) ret %vc } @@ -682,9 +600,7 @@ define @vor_vx_nxv1i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 16) ret %vc } @@ -706,9 +622,7 @@ define @vor_vx_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 -12) ret %vc } @@ -718,9 +632,7 @@ define @vor_vx_nxv2i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 15) ret %vc } @@ -731,9 +643,7 @@ define @vor_vx_nxv2i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 16) ret %vc } @@ -755,9 +665,7 @@ define @vor_vx_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 -12) ret %vc } @@ -767,9 +675,7 @@ define @vor_vx_nxv4i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 15) ret %vc } @@ -780,9 +686,7 @@ define @vor_vx_nxv4i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 16) ret %vc } @@ -804,9 +708,7 @@ define @vor_vx_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 -12) ret %vc } @@ -816,9 +718,7 @@ define @vor_vx_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 15) ret %vc } @@ -829,9 +729,7 @@ define @vor_vx_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 16) ret %vc } @@ -853,9 +751,7 @@ define @vor_vx_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 -12) ret %vc } @@ -865,9 +761,7 @@ define @vor_vx_nxv16i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i32 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 15) ret %vc } @@ -878,9 +772,7 @@ define @vor_vx_nxv16i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i32 16) ret %vc } @@ -915,9 +807,7 @@ define @vor_vx_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 -12) ret %vc } @@ -927,9 +817,7 @@ define @vor_vx_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 15) ret %vc } @@ -940,9 +828,7 @@ define @vor_vx_nxv1i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 16) ret %vc } @@ -977,9 +863,7 @@ define @vor_vx_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 -12) ret %vc } @@ -989,9 +873,7 @@ define @vor_vx_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 15) ret %vc } @@ -1002,9 +884,7 @@ define @vor_vx_nxv2i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 16) ret %vc } @@ -1039,9 +919,7 @@ define @vor_vx_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 -12) ret %vc } @@ -1051,9 +929,7 @@ define @vor_vx_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 15) ret %vc } @@ -1064,9 +940,7 @@ define @vor_vx_nxv4i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 16) ret %vc } @@ -1101,9 +975,7 @@ define @vor_vx_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, -12 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -12, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 -12) ret %vc } @@ -1113,9 +985,7 @@ define @vor_vx_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 15, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 15) ret %vc } @@ -1126,9 +996,7 @@ define @vor_vx_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 16) ret %vc } @@ -1139,9 +1007,7 @@ define @vor_vx_nxv8i64_3( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = or %va, %splat + %vc = or %va, splat (i64 -1) ret %vc } @@ -1206,9 +1072,7 @@ define @vor_vi_mask_nxv8i32( %va, poison, i32 7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 7), zeroinitializer %vc = or %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll index ccab5e40d450..b9388e587970 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll @@ -36,9 +36,7 @@ define @vor_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -62,9 +60,7 @@ define @vor_vx_nxv1i8_unmasked( %va, i8 %b, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -74,9 +70,7 @@ define @vor_vi_nxv1i8( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -86,11 +80,7 @@ define @vor_vi_nxv1i8_unmasked( %va, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -112,9 +102,7 @@ define @vor_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -138,9 +126,7 @@ define @vor_vx_nxv2i8_unmasked( %va, i8 %b, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -150,9 +136,7 @@ define @vor_vi_nxv2i8( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -162,11 +146,7 @@ define @vor_vi_nxv2i8_unmasked( %va, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -188,9 +168,7 @@ define @vor_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -214,9 +192,7 @@ define @vor_vx_nxv4i8_unmasked( %va, i8 %b, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -226,9 +202,7 @@ define @vor_vi_nxv4i8( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -238,11 +212,7 @@ define @vor_vi_nxv4i8_unmasked( %va, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -264,9 +234,7 @@ define @vor_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -290,9 +258,7 @@ define @vor_vx_nxv8i8_unmasked( %va, i8 %b, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -302,9 +268,7 @@ define @vor_vi_nxv8i8( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5, v0.t ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -314,11 +278,7 @@ define @vor_vi_nxv8i8_unmasked( %va, i32 zero ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -340,9 +300,7 @@ define @vor_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -366,9 +324,7 @@ define @vor_vx_nxv16i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -378,9 +334,7 @@ define @vor_vi_nxv16i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -390,11 +344,7 @@ define @vor_vi_nxv16i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -416,9 +366,7 @@ define @vor_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -442,9 +390,7 @@ define @vor_vx_nxv32i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -454,9 +400,7 @@ define @vor_vi_nxv32i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -466,11 +410,7 @@ define @vor_vi_nxv32i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -492,9 +432,7 @@ define @vor_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -518,9 +456,7 @@ define @vor_vx_nxv64i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -530,9 +466,7 @@ define @vor_vi_nxv64i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv64i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -542,11 +476,7 @@ define @vor_vi_nxv64i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv64i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -568,9 +498,7 @@ define @vor_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -594,9 +522,7 @@ define @vor_vx_nxv1i16_unmasked( %va, i16 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -606,9 +532,7 @@ define @vor_vi_nxv1i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -618,11 +542,7 @@ define @vor_vi_nxv1i16_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -644,9 +564,7 @@ define @vor_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -670,9 +588,7 @@ define @vor_vx_nxv2i16_unmasked( %va, i16 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -682,9 +598,7 @@ define @vor_vi_nxv2i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -694,11 +608,7 @@ define @vor_vi_nxv2i16_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -720,9 +630,7 @@ define @vor_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -746,9 +654,7 @@ define @vor_vx_nxv4i16_unmasked( %va, i16 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -758,9 +664,7 @@ define @vor_vi_nxv4i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -770,11 +674,7 @@ define @vor_vi_nxv4i16_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -796,9 +696,7 @@ define @vor_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -822,9 +720,7 @@ define @vor_vx_nxv8i16_unmasked( %va, i16 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -834,9 +730,7 @@ define @vor_vi_nxv8i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -846,11 +740,7 @@ define @vor_vi_nxv8i16_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -872,9 +762,7 @@ define @vor_vv_nxv16i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -898,9 +786,7 @@ define @vor_vx_nxv16i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -910,9 +796,7 @@ define @vor_vi_nxv16i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -922,11 +806,7 @@ define @vor_vi_nxv16i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -948,9 +828,7 @@ define @vor_vv_nxv32i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -974,9 +852,7 @@ define @vor_vx_nxv32i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -986,9 +862,7 @@ define @vor_vi_nxv32i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -998,11 +872,7 @@ define @vor_vi_nxv32i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv32i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -1024,9 +894,7 @@ define @vor_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1050,9 +918,7 @@ define @vor_vx_nxv1i32_unmasked( %va, i32 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1062,9 +928,7 @@ define @vor_vi_nxv1i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1074,11 +938,7 @@ define @vor_vi_nxv1i32_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1100,9 +960,7 @@ define @vor_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1138,9 +996,7 @@ define @vor_vx_nxv2i32_unmasked( %va, i32 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1152,9 +1008,7 @@ define @vor_vx_nxv2i32_unmasked_commute( %v ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -1164,9 +1018,7 @@ define @vor_vi_nxv2i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1176,11 +1028,7 @@ define @vor_vi_nxv2i32_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1202,9 +1050,7 @@ define @vor_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1228,9 +1074,7 @@ define @vor_vx_nxv4i32_unmasked( %va, i32 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1240,9 +1084,7 @@ define @vor_vi_nxv4i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1252,11 +1094,7 @@ define @vor_vi_nxv4i32_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1278,9 +1116,7 @@ define @vor_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1304,9 +1140,7 @@ define @vor_vx_nxv8i32_unmasked( %va, i32 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1316,9 +1150,7 @@ define @vor_vi_nxv8i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1328,11 +1160,7 @@ define @vor_vi_nxv8i32_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1354,9 +1182,7 @@ define @vor_vv_nxv10i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv10i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv10i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1380,9 +1206,7 @@ define @vor_vx_nxv10i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv10i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv10i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1392,9 +1216,7 @@ define @vor_vi_nxv10i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv10i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv10i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1404,11 +1226,7 @@ define @vor_vi_nxv10i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv10i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv10i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1430,9 +1248,7 @@ define @vor_vv_nxv16i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1456,9 +1272,7 @@ define @vor_vx_nxv16i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1468,9 +1282,7 @@ define @vor_vi_nxv16i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1480,11 +1292,7 @@ define @vor_vi_nxv16i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv16i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1506,9 +1314,7 @@ define @vor_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1560,9 +1366,7 @@ define @vor_vx_nxv1i64_unmasked( %va, i64 % ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1572,9 +1376,7 @@ define @vor_vi_nxv1i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1584,11 +1386,7 @@ define @vor_vi_nxv1i64_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv1i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } @@ -1610,9 +1408,7 @@ define @vor_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1664,9 +1460,7 @@ define @vor_vx_nxv2i64_unmasked( %va, i64 % ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1676,9 +1470,7 @@ define @vor_vi_nxv2i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1688,11 +1480,7 @@ define @vor_vi_nxv2i64_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv2i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } @@ -1714,9 +1502,7 @@ define @vor_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1768,9 +1554,7 @@ define @vor_vx_nxv4i64_unmasked( %va, i64 % ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1780,9 +1564,7 @@ define @vor_vi_nxv4i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1792,11 +1574,7 @@ define @vor_vi_nxv4i64_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv4i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } @@ -1818,9 +1596,7 @@ define @vor_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1872,9 +1648,7 @@ define @vor_vx_nxv8i64_unmasked( %va, i64 % ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1884,9 +1658,7 @@ define @vor_vi_nxv8i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1896,10 +1668,6 @@ define @vor_vi_nxv8i64_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vor.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.or.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.or.nxv8i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll index cc13a97ddce0..136f6e7bc999 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float-fixed-vectors.ll @@ -26,10 +26,8 @@ define <2 x double> @test_vp_reverse_v2f64(<2 x double> %src, i32 zeroext %evl) ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %dst = call <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double> %src, <2 x i1> %allones, i32 %evl) + %dst = call <2 x double> @llvm.experimental.vp.reverse.v2f64(<2 x double> %src, <2 x i1> splat (i1 1), i32 %evl) ret <2 x double> %dst } @@ -57,10 +55,8 @@ define <4 x float> @test_vp_reverse_v4f32(<4 x float> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %dst = call <4 x float> @llvm.experimental.vp.reverse.v4f32(<4 x float> %src, <4 x i1> %allones, i32 %evl) + %dst = call <4 x float> @llvm.experimental.vp.reverse.v4f32(<4 x float> %src, <4 x i1> splat (i1 1), i32 %evl) ret <4 x float> %dst } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll index adc1ca6c8586..b235990ab5dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-float.ll @@ -25,10 +25,8 @@ define @test_vp_reverse_nxv1f64( %src ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv1f64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv1f64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -56,10 +54,8 @@ define @test_vp_reverse_nxv2f32( %src, ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv2f32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv2f32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -87,10 +83,8 @@ define @test_vp_reverse_nxv2f64( %src ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv2f64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv2f64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -118,10 +112,8 @@ define @test_vp_reverse_nxv4f32( %src, ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv4f32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv4f32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -149,10 +141,8 @@ define @test_vp_reverse_nxv4f64( %src ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv4f64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv4f64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -180,10 +170,8 @@ define @test_vp_reverse_nxv8f32( %src, ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8f32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8f32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -211,10 +199,8 @@ define @test_vp_reverse_nxv8f64( %src ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8f64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8f64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -242,10 +228,8 @@ define @test_vp_reverse_nxv16f32( %sr ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv16f32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv16f32( %src, splat (i1 1), i32 %evl) ret %dst } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll index d7fc8838f430..27f16f0285e1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int-fixed-vectors.ll @@ -26,10 +26,8 @@ define <2 x i64> @test_vp_reverse_v2i64(<2 x i64> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %dst = call <2 x i64> @llvm.experimental.vp.reverse.v2i64(<2 x i64> %src, <2 x i1> %allones, i32 %evl) + %dst = call <2 x i64> @llvm.experimental.vp.reverse.v2i64(<2 x i64> %src, <2 x i1> splat (i1 1), i32 %evl) ret <2 x i64> %dst } @@ -57,10 +55,8 @@ define <4 x i32> @test_vp_reverse_v4i32(<4 x i32> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %dst = call <4 x i32> @llvm.experimental.vp.reverse.v4i32(<4 x i32> %src, <4 x i1> %allones, i32 %evl) + %dst = call <4 x i32> @llvm.experimental.vp.reverse.v4i32(<4 x i32> %src, <4 x i1> splat (i1 1), i32 %evl) ret <4 x i32> %dst } @@ -88,10 +84,8 @@ define <8 x i16> @test_vp_reverse_v8i16(<8 x i16> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> undef, i1 1, i32 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer - %dst = call <8 x i16> @llvm.experimental.vp.reverse.v8i16(<8 x i16> %src, <8 x i1> %allones, i32 %evl) + %dst = call <8 x i16> @llvm.experimental.vp.reverse.v8i16(<8 x i16> %src, <8 x i1> splat (i1 1), i32 %evl) ret <8 x i16> %dst } @@ -121,10 +115,8 @@ define <16 x i8> @test_vp_reverse_v16i8(<16 x i8> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgatherei16.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> undef, i1 1, i32 0 - %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer - %dst = call <16 x i8> @llvm.experimental.vp.reverse.v16i8(<16 x i8> %src, <16 x i1> %allones, i32 %evl) + %dst = call <16 x i8> @llvm.experimental.vp.reverse.v16i8(<16 x i8> %src, <16 x i1> splat (i1 1), i32 %evl) ret <16 x i8> %dst } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll index 47df1b005a0f..8b1660283cb7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-int.ll @@ -25,10 +25,8 @@ define @test_vp_reverse_nxv1i64( %src, i32 ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv1i64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv1i64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -56,10 +54,8 @@ define @test_vp_reverse_nxv2i32( %src, i32 ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv2i32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv2i32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -87,10 +83,8 @@ define @test_vp_reverse_nxv4i16( %src, i32 ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv4i16( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv4i16( %src, splat (i1 1), i32 %evl) ret %dst } @@ -120,10 +114,8 @@ define @test_vp_reverse_nxv8i8( %src, i32 zer ; CHECK-NEXT: vrgatherei16.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8i8( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8i8( %src, splat (i1 1), i32 %evl) ret %dst } @@ -151,10 +143,8 @@ define @test_vp_reverse_nxv2i64( %src, i32 ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv2i64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv2i64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -182,10 +172,8 @@ define @test_vp_reverse_nxv4i32( %src, i32 ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv4i32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv4i32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -213,10 +201,8 @@ define @test_vp_reverse_nxv8i16( %src, i32 ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8i16( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8i16( %src, splat (i1 1), i32 %evl) ret %dst } @@ -246,10 +232,8 @@ define @test_vp_reverse_nxv16i8( %src, i32 ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv16i8( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv16i8( %src, splat (i1 1), i32 %evl) ret %dst } @@ -277,10 +261,8 @@ define @test_vp_reverse_nxv4i64( %src, i32 ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv4i64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv4i64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -308,10 +290,8 @@ define @test_vp_reverse_nxv8i32( %src, i32 ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8i32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8i32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -339,10 +319,8 @@ define @test_vp_reverse_nxv16i16( %src, i ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv16i16( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv16i16( %src, splat (i1 1), i32 %evl) ret %dst } @@ -372,10 +350,8 @@ define @test_vp_reverse_nxv32i8( %src, i32 ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv32i8( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv32i8( %src, splat (i1 1), i32 %evl) ret %dst } @@ -403,10 +379,8 @@ define @test_vp_reverse_nxv8i64( %src, i32 ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8i64( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8i64( %src, splat (i1 1), i32 %evl) ret %dst } @@ -434,10 +408,8 @@ define @test_vp_reverse_nxv16i32( %src, i ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv16i32( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv16i32( %src, splat (i1 1), i32 %evl) ret %dst } @@ -465,10 +437,8 @@ define @test_vp_reverse_nxv32i16( %src, i ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv32i16( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv32i16( %src, splat (i1 1), i32 %evl) ret %dst } @@ -510,10 +480,8 @@ define @test_vp_reverse_nxv64i8( %src, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v24, a1 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv64i8( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv64i8( %src, splat (i1 1), i32 %evl) ret %dst } @@ -561,10 +529,8 @@ define @test_vp_reverse_nxv128i8( %src, i ; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 80 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv128i8( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv128i8( %src, splat (i1 1), i32 %evl) ret %dst } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll index fd608c858650..a30ebf2d33b5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask-fixed-vectors.ll @@ -34,10 +34,8 @@ define <2 x i1> @test_vp_reverse_v2i1(<2 x i1> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %dst = call <2 x i1> @llvm.experimental.vp.reverse.v2i1(<2 x i1> %src, <2 x i1> %allones, i32 %evl) + %dst = call <2 x i1> @llvm.experimental.vp.reverse.v2i1(<2 x i1> %src, <2 x i1> splat (i1 1), i32 %evl) ret <2 x i1> %dst } @@ -73,10 +71,8 @@ define <4 x i1> @test_vp_reverse_v4i1(<4 x i1> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %dst = call <4 x i1> @llvm.experimental.vp.reverse.v4i1(<4 x i1> %src, <4 x i1> %allones, i32 %evl) + %dst = call <4 x i1> @llvm.experimental.vp.reverse.v4i1(<4 x i1> %src, <4 x i1> splat (i1 1), i32 %evl) ret <4 x i1> %dst } @@ -112,10 +108,8 @@ define <8 x i1> @test_vp_reverse_v8i1(<8 x i1> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> undef, i1 1, i32 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer - %dst = call <8 x i1> @llvm.experimental.vp.reverse.v8i1(<8 x i1> %src, <8 x i1> %allones, i32 %evl) + %dst = call <8 x i1> @llvm.experimental.vp.reverse.v8i1(<8 x i1> %src, <8 x i1> splat (i1 1), i32 %evl) ret <8 x i1> %dst } @@ -151,10 +145,8 @@ define <16 x i1> @test_vp_reverse_v16i1(<16 x i1> %src, i32 zeroext %evl) { ; CHECK-NEXT: vrgatherei16.vv v11, v10, v8 ; CHECK-NEXT: vmsne.vi v0, v11, 0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> undef, i1 1, i32 0 - %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer - %dst = call <16 x i1> @llvm.experimental.vp.reverse.v16i1(<16 x i1> %src, <16 x i1> %allones, i32 %evl) + %dst = call <16 x i1> @llvm.experimental.vp.reverse.v16i1(<16 x i1> %src, <16 x i1> splat (i1 1), i32 %evl) ret <16 x i1> %dst } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll index 29917141fffe..ceb6a164e20d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-reverse-mask.ll @@ -33,10 +33,8 @@ define @test_vp_reverse_nxv1i1( %src, i32 zer ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv1i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv1i1( %src, splat (i1 1), i32 %evl) ret %dst } @@ -72,10 +70,8 @@ define @test_vp_reverse_nxv2i1( %src, i32 zer ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv2i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv2i1( %src, splat (i1 1), i32 %evl) ret %dst } @@ -111,10 +107,8 @@ define @test_vp_reverse_nxv4i1( %src, i32 zer ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv4i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv4i1( %src, splat (i1 1), i32 %evl) ret %dst } @@ -150,10 +144,8 @@ define @test_vp_reverse_nxv8i1( %src, i32 zer ; CHECK-NEXT: vrgatherei16.vv v11, v10, v8 ; CHECK-NEXT: vmsne.vi v0, v11, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv8i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv8i1( %src, splat (i1 1), i32 %evl) ret %dst } @@ -190,10 +182,8 @@ define @test_vp_reverse_nxv16i1( %src, i32 ; CHECK-NEXT: vrgatherei16.vv v14, v12, v8 ; CHECK-NEXT: vmsne.vi v0, v14, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv16i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv16i1( %src, splat (i1 1), i32 %evl) ret %dst } @@ -230,10 +220,8 @@ define @test_vp_reverse_nxv32i1( %src, i32 ; CHECK-NEXT: vrgatherei16.vv v20, v16, v8 ; CHECK-NEXT: vmsne.vi v0, v20, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv32i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv32i1( %src, splat (i1 1), i32 %evl) ret %dst } @@ -285,10 +273,8 @@ define @test_vp_reverse_nxv64i1( %src, i32 ; CHECK-NEXT: vslidedown.vx v8, v16, a1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %dst = call @llvm.experimental.vp.reverse.nxv64i1( %src, %allones, i32 %evl) + %dst = call @llvm.experimental.vp.reverse.nxv64i1( %src, splat (i1 1), i32 %evl) ret %dst } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-fixed-vectors.ll index f7c8c251e197..494bf46050cc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-fixed-vectors.ll @@ -19,10 +19,8 @@ define <2 x i64> @test_vp_splice_v2i64(<2 x i64> %va, <2 x i64> %vb, i32 zeroext ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 5, <2 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <2 x i64> %v } @@ -35,10 +33,8 @@ define <2 x i64> @test_vp_splice_v2i64_negative_offset(<2 x i64> %va, <2 x i64> ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 5 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 -5, <2 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <2 x i64> @llvm.experimental.vp.splice.v2i64(<2 x i64> %va, <2 x i64> %vb, i32 -5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <2 x i64> %v } @@ -64,10 +60,8 @@ define <4 x i32> @test_vp_splice_v4i32(<4 x i32> %va, <4 x i32> %vb, i32 zeroext ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 5, <4 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <4 x i32> %v } @@ -80,10 +74,8 @@ define <4 x i32> @test_vp_splice_v4i32_negative_offset(<4 x i32> %va, <4 x i32> ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 5 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 -5, <4 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 -5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <4 x i32> %v } @@ -109,10 +101,8 @@ define <8 x i16> @test_vp_splice_v8i16(<8 x i16> %va, <8 x i16> %vb, i32 zeroext ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> undef, i1 1, i32 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 5, <8 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <8 x i16> %v } @@ -125,10 +115,8 @@ define <8 x i16> @test_vp_splice_v8i16_negative_offset(<8 x i16> %va, <8 x i16> ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 5 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> undef, i1 1, i32 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 -5, <8 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <8 x i16> @llvm.experimental.vp.splice.v8i16(<8 x i16> %va, <8 x i16> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <8 x i16> %v } @@ -154,10 +142,8 @@ define <16 x i8> @test_vp_splice_v16i8(<16 x i8> %va, <16 x i8> %vb, i32 zeroext ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> undef, i1 1, i32 0 - %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 5, <16 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <16 x i8> %v } @@ -170,10 +156,8 @@ define <16 x i8> @test_vp_splice_v16i8_negative_offset(<16 x i8> %va, <16 x i8> ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 5 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> undef, i1 1, i32 0 - %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 -5, <16 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <16 x i8> @llvm.experimental.vp.splice.v16i8(<16 x i8> %va, <16 x i8> %vb, i32 -5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <16 x i8> %v } @@ -199,10 +183,8 @@ define <2 x double> @test_vp_splice_v2f64(<2 x double> %va, <2 x double> %vb, i3 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 5, <2 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <2 x double> %v } @@ -215,10 +197,8 @@ define <2 x double> @test_vp_splice_v2f64_negative_offset(<2 x double> %va, <2 x ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 5 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 -5, <2 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %va, <2 x double> %vb, i32 -5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <2 x double> %v } @@ -244,10 +224,8 @@ define <4 x float> @test_vp_splice_v4f32(<4 x float> %va, <4 x float> %vb, i32 z ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 5, <4 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <4 x float> %v } @@ -260,10 +238,8 @@ define <4 x float> @test_vp_splice_v4f32_negative_offset(<4 x float> %va, <4 x f ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 5 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 -5, <4 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <4 x float> @llvm.experimental.vp.splice.v4f32(<4 x float> %va, <4 x float> %vb, i32 -5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <4 x float> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll index 9579973aee0d..ce0ae2022885 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-fixed-vectors.ll @@ -26,10 +26,8 @@ define <2 x i1> @test_vp_splice_v2i1(<2 x i1> %va, <2 x i1> %vb, i32 zeroext %ev ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 5, <2 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <2 x i1> %v } @@ -52,10 +50,8 @@ define <2 x i1> @test_vp_splice_v2i1_negative_offset(<2 x i1> %va, <2 x i1> %vb, ; CHECK-NEXT: vslideup.vi v9, v8, 5 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <2 x i1> undef, i1 1, i32 0 - %allones = shufflevector <2 x i1> %head, <2 x i1> undef, <2 x i32> zeroinitializer - %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 -5, <2 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <2 x i1> @llvm.experimental.vp.splice.v2i1(<2 x i1> %va, <2 x i1> %vb, i32 -5, <2 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <2 x i1> %v } @@ -103,10 +99,8 @@ define <4 x i1> @test_vp_splice_v4i1(<4 x i1> %va, <4 x i1> %vb, i32 zeroext %ev ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 5, <4 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <4 x i1> %v } @@ -129,10 +123,8 @@ define <4 x i1> @test_vp_splice_v4i1_negative_offset(<4 x i1> %va, <4 x i1> %vb, ; CHECK-NEXT: vslideup.vi v9, v8, 5 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <4 x i1> undef, i1 1, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> undef, <4 x i32> zeroinitializer - %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 -5, <4 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <4 x i1> @llvm.experimental.vp.splice.v4i1(<4 x i1> %va, <4 x i1> %vb, i32 -5, <4 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <4 x i1> %v } @@ -180,10 +172,8 @@ define <8 x i1> @test_vp_splice_v8i1(<8 x i1> %va, <8 x i1> %vb, i32 zeroext %ev ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> undef, i1 1, i32 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 5, <8 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <8 x i1> %v } @@ -206,10 +196,8 @@ define <8 x i1> @test_vp_splice_v8i1_negative_offset(<8 x i1> %va, <8 x i1> %vb, ; CHECK-NEXT: vslideup.vi v9, v8, 5 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> undef, i1 1, i32 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> undef, <8 x i32> zeroinitializer - %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 -5, <8 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <8 x i1> @llvm.experimental.vp.splice.v8i1(<8 x i1> %va, <8 x i1> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <8 x i1> %v } @@ -257,10 +245,8 @@ define <16 x i1> @test_vp_splice_v16i1(<16 x i1> %va, <16 x i1> %vb, i32 zeroext ; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> undef, i1 1, i32 0 - %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer - %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 5, <16 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <16 x i1> %v } @@ -283,10 +269,8 @@ define <16 x i1> @test_vp_splice_v16i1_negative_offset(<16 x i1> %va, <16 x i1> ; CHECK-NEXT: vslideup.vi v9, v8, 5 ; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: ret - %head = insertelement <16 x i1> undef, i1 1, i32 0 - %allones = shufflevector <16 x i1> %head, <16 x i1> undef, <16 x i32> zeroinitializer - %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 -5, <16 x i1> %allones, i32 %evla, i32 %evlb) + %v = call <16 x i1> @llvm.experimental.vp.splice.v16i1(<16 x i1> %va, <16 x i1> %vb, i32 -5, <16 x i1> splat (i1 1), i32 %evla, i32 %evlb) ret <16 x i1> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll index 4eaadb3c24fb..668cff234293 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice-mask-vectors.ll @@ -29,10 +29,8 @@ define @test_vp_splice_nxv1i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv1i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv1i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -55,10 +53,8 @@ define @test_vp_splice_nxv1i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv1i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv1i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -106,10 +102,8 @@ define @test_vp_splice_nxv2i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv2i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -132,10 +126,8 @@ define @test_vp_splice_nxv2i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv2i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -183,10 +175,8 @@ define @test_vp_splice_nxv4i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv4i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv4i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -209,10 +199,8 @@ define @test_vp_splice_nxv4i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv4i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv4i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -260,10 +248,8 @@ define @test_vp_splice_nxv8i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv8i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv8i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -286,10 +272,8 @@ define @test_vp_splice_nxv8i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv8i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv8i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -337,10 +321,8 @@ define @test_vp_splice_nxv16i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv16i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv16i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -363,10 +345,8 @@ define @test_vp_splice_nxv16i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv16i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv16i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -415,10 +395,8 @@ define @test_vp_splice_nxv32i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv32i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv32i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -441,10 +419,8 @@ define @test_vp_splice_nxv32i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv32i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv32i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -493,10 +469,8 @@ define @test_vp_splice_nxv64i1( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv64i1( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv64i1( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -519,10 +493,8 @@ define @test_vp_splice_nxv64i1_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - %v = call @llvm.experimental.vp.splice.nxv64i1( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv64i1( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll index 7d85370e390b..a4f91c3e7c99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll @@ -23,10 +23,7 @@ define @test_vp_splice_nxv2i64( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv2i64( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2i64( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -39,10 +36,7 @@ define @test_vp_splice_nxv2i64_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv2i64( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2i64( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -68,10 +62,7 @@ define @test_vp_splice_nxv1i64( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv1i64( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv1i64( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -84,10 +75,7 @@ define @test_vp_splice_nxv1i64_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv1i64( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv1i64( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -113,10 +101,7 @@ define @test_vp_splice_nxv2i32( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv2i32( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2i32( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -129,10 +114,7 @@ define @test_vp_splice_nxv2i32_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv2i32( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2i32( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -158,10 +140,7 @@ define @test_vp_splice_nxv4i16( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv4i16( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv4i16( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -174,10 +153,7 @@ define @test_vp_splice_nxv4i16_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv4i16( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv4i16( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -203,10 +179,7 @@ define @test_vp_splice_nxv8i8( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv8i8( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv8i8( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -219,10 +192,7 @@ define @test_vp_splice_nxv8i8_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv8i8( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv8i8( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -248,10 +218,7 @@ define @test_vp_splice_nxv1f64( %va, ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %head = insertelement undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv1f64( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv1f64( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -264,10 +231,7 @@ define @test_vp_splice_nxv1f64_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv1f64( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv1f64( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -293,10 +257,7 @@ define @test_vp_splice_nxv2f32( %va, undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv2f32( %va, %vb, i32 5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2f32( %va, %vb, i32 5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } @@ -309,10 +270,7 @@ define @test_vp_splice_nxv2f32_negative_offset( undef, i1 1, i32 0 - %allones = shufflevector %head, undef, zeroinitializer - - %v = call @llvm.experimental.vp.splice.nxv2f32( %va, %vb, i32 -5, %allones, i32 %evla, i32 %evlb) + %v = call @llvm.experimental.vp.splice.nxv2f32( %va, %vb, i32 -5, splat (i1 1), i32 %evla, i32 %evlb) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll index a5c305d5ac82..c86fee630593 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll @@ -204,9 +204,7 @@ define @vpgather_truemask_nxv4i8( %ptrs, i32 ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv1r.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4i8.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4i8.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } @@ -500,9 +498,7 @@ define @vpgather_truemask_nxv4i16( %ptrs, i ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4i16.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4i16.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } @@ -729,9 +725,7 @@ define @vpgather_truemask_nxv4i32( %ptrs, i ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4i32.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4i32.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } @@ -988,9 +982,7 @@ define @vpgather_truemask_nxv4i64( %ptrs, i ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vluxei64.v v8, (zero), v8 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4i64.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4i64.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } @@ -1319,9 +1311,7 @@ define @vpgather_truemask_nxv4f16( %ptrs, ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4f16.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4f16.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } @@ -1506,9 +1496,7 @@ define @vpgather_truemask_nxv4f32( %ptrs, ; RV64-NEXT: vluxei64.v v12, (zero), v8 ; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4f32.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4f32.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } @@ -1765,9 +1753,7 @@ define @vpgather_truemask_nxv4f64( %ptrs ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vluxei64.v v8, (zero), v8 ; RV64-NEXT: ret - %mhead = insertelement poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %v = call @llvm.vp.gather.nxv4f64.nxv4p0( %ptrs, %mtrue, i32 %evl) + %v = call @llvm.vp.gather.nxv4f64.nxv4p0( %ptrs, splat (i1 1), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vpload.ll b/llvm/test/CodeGen/RISCV/rvv/vpload.ll index c203fcb903e5..f07c16476c56 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpload.ll @@ -22,9 +22,7 @@ define @vpload_nxv1i8_allones_mask(ptr %ptr, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv1i8.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv1i8.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -82,9 +80,7 @@ define @vpload_nxv8i8_allones_mask(ptr %ptr, i32 zeroext %evl) ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv8i8.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv8i8.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -118,9 +114,7 @@ define @vpload_nxv2i16_allones_mask(ptr %ptr, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv2i16.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv2i16.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -190,9 +184,7 @@ define @vpload_nxv4i32_allones_mask(ptr %ptr, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv4i32.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv4i32.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -226,9 +218,7 @@ define @vpload_nxv1i64_allones_mask(ptr %ptr, i32 zeroext %ev ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv1i64.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv1i64.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -298,9 +288,7 @@ define @vpload_nxv2f16_allones_mask(ptr %ptr, i32 zeroext %e ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv2f16.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv2f16.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -382,9 +370,7 @@ define @vpload_nxv8f32_allones_mask(ptr %ptr, i32 zeroext % ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv8f32.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv8f32.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } @@ -430,9 +416,7 @@ define @vpload_nxv4f64_allones_mask(ptr %ptr, i32 zeroext ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - %load = call @llvm.vp.load.nxv4f64.p0(ptr %ptr, %b, i32 %evl) + %load = call @llvm.vp.load.nxv4f64.p0(ptr %ptr, splat (i1 true), i32 %evl) ret %load } diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll index 4f67aac2d2d2..76efdda15bf7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll @@ -66,9 +66,7 @@ define @vpmerge_vi_nxv1i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv1i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv1i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -103,9 +101,7 @@ define @vpmerge_vi_nxv2i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv2i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv2i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -140,9 +136,7 @@ define @vpmerge_vi_nxv3i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv3i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv3i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -177,9 +171,7 @@ define @vpmerge_vi_nxv4i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv4i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv4i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -214,9 +206,7 @@ define @vpmerge_vi_nxv8i7( %vb, poison, i7 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv8i7( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv8i7( %m, splat (i7 2), %vb, i32 %evl) ret %v } @@ -251,9 +241,7 @@ define @vpmerge_vi_nxv8i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv8i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv8i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -288,9 +276,7 @@ define @vpmerge_vi_nxv16i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv16i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv16i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -325,9 +311,7 @@ define @vpmerge_vi_nxv32i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv32i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv32i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -362,9 +346,7 @@ define @vpmerge_vi_nxv64i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv64i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv64i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -464,9 +446,7 @@ define @vpmerge_vi_nxv128i8( %vb, poison, i8 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv128i8( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv128i8( %m, splat (i8 2), %vb, i32 %evl) ret %v } @@ -501,9 +481,7 @@ define @vpmerge_vi_nxv1i16( %vb, poison, i16 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv1i16( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv1i16( %m, splat (i16 2), %vb, i32 %evl) ret %v } @@ -538,9 +516,7 @@ define @vpmerge_vi_nxv2i16( %vb, poison, i16 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv2i16( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv2i16( %m, splat (i16 2), %vb, i32 %evl) ret %v } @@ -575,9 +551,7 @@ define @vpmerge_vi_nxv4i16( %vb, poison, i16 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv4i16( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv4i16( %m, splat (i16 2), %vb, i32 %evl) ret %v } @@ -612,9 +586,7 @@ define @vpmerge_vi_nxv8i16( %vb, poison, i16 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv8i16( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv8i16( %m, splat (i16 2), %vb, i32 %evl) ret %v } @@ -649,9 +621,7 @@ define @vpmerge_vi_nxv16i16( %vb, poison, i16 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv16i16( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv16i16( %m, splat (i16 2), %vb, i32 %evl) ret %v } @@ -686,9 +656,7 @@ define @vpmerge_vi_nxv32i16( %vb, poison, i16 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv32i16( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv32i16( %m, splat (i16 2), %vb, i32 %evl) ret %v } @@ -723,9 +691,7 @@ define @vpmerge_vi_nxv1i32( %vb, poison, i32 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv1i32( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv1i32( %m, splat (i32 2), %vb, i32 %evl) ret %v } @@ -760,9 +726,7 @@ define @vpmerge_vi_nxv2i32( %vb, poison, i32 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv2i32( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv2i32( %m, splat (i32 2), %vb, i32 %evl) ret %v } @@ -797,9 +761,7 @@ define @vpmerge_vi_nxv4i32( %vb, poison, i32 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv4i32( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv4i32( %m, splat (i32 2), %vb, i32 %evl) ret %v } @@ -834,9 +796,7 @@ define @vpmerge_vi_nxv8i32( %vb, poison, i32 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv8i32( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv8i32( %m, splat (i32 2), %vb, i32 %evl) ret %v } @@ -871,9 +831,7 @@ define @vpmerge_vi_nxv16i32( %vb, poison, i32 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv16i32( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv16i32( %m, splat (i32 2), %vb, i32 %evl) ret %v } @@ -920,9 +878,7 @@ define @vpmerge_vi_nxv1i64( %vb, poison, i64 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv1i64( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv1i64( %m, splat (i64 2), %vb, i32 %evl) ret %v } @@ -969,9 +925,7 @@ define @vpmerge_vi_nxv2i64( %vb, poison, i64 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv2i64( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv2i64( %m, splat (i64 2), %vb, i32 %evl) ret %v } @@ -1018,9 +972,7 @@ define @vpmerge_vi_nxv4i64( %vb, poison, i64 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv4i64( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv4i64( %m, splat (i64 2), %vb, i32 %evl) ret %v } @@ -1067,9 +1019,7 @@ define @vpmerge_vi_nxv8i64( %vb, poison, i64 2, i32 0 - %va = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.merge.nxv8i64( %m, %va, %vb, i32 %evl) + %v = call @llvm.vp.merge.nxv8i64( %m, splat (i64 2), %vb, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll index a907e149b167..38e4aab4deb3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll @@ -145,9 +145,7 @@ define void @vpscatter_truemask_nxv4i8( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4i8.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4i8.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } @@ -302,9 +300,7 @@ define void @vpscatter_truemask_nxv4i16( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4i16.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4i16.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } @@ -604,9 +600,7 @@ define void @vpscatter_truemask_nxv4i32( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4i32.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4i32.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } @@ -858,9 +852,7 @@ define void @vpscatter_truemask_nxv4i64( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4i64.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4i64.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } @@ -1180,9 +1172,7 @@ define void @vpscatter_truemask_nxv4f16( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4f16.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4f16.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } @@ -1361,9 +1351,7 @@ define void @vpscatter_truemask_nxv4f32( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4f32.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4f32.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } @@ -1615,9 +1603,7 @@ define void @vpscatter_truemask_nxv4f64( %val, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - call void @llvm.vp.scatter.nxv4f64.nxv4p0( %val, %ptrs, %mtrue, i32 %evl) + call void @llvm.vp.scatter.nxv4f64.nxv4p0( %val, %ptrs, splat (i1 1), i32 %evl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll index 8b27a61e243d..c12fc0497742 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll @@ -358,9 +358,7 @@ define void @vpstore_nxv1i8_allones_mask( %val, ptr %ptr, i32 z ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret - %a = insertelement poison, i1 true, i32 0 - %b = shufflevector %a, poison, zeroinitializer - call void @llvm.vp.store.nxv1i8.p0( %val, ptr %ptr, %b, i32 %evl) + call void @llvm.vp.store.nxv1i8.p0( %val, ptr %ptr, splat (i1 true), i32 %evl) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll index 1eafb3bdfed2..3a6ae5fdb210 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll @@ -39,9 +39,7 @@ define @vrem_vi_nxv1i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -93,9 +91,7 @@ define @vrem_vi_nxv2i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -147,9 +143,7 @@ define @vrem_vi_nxv4i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -201,9 +195,7 @@ define @vrem_vi_nxv8i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -255,9 +247,7 @@ define @vrem_vi_nxv16i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -309,9 +299,7 @@ define @vrem_vi_nxv32i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -363,9 +351,7 @@ define @vrem_vi_nxv64i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i8 -7) ret %vc } @@ -404,9 +390,7 @@ define @vrem_vi_nxv1i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i16 -7) ret %vc } @@ -458,9 +442,7 @@ define @vrem_vi_nxv2i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i16 -7) ret %vc } @@ -512,9 +494,7 @@ define @vrem_vi_nxv4i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i16 -7) ret %vc } @@ -566,9 +546,7 @@ define @vrem_vi_nxv8i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i16 -7) ret %vc } @@ -620,9 +598,7 @@ define @vrem_vi_nxv16i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i16 -7) ret %vc } @@ -674,9 +650,7 @@ define @vrem_vi_nxv32i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i16 -7) ret %vc } @@ -730,9 +704,7 @@ define @vrem_vi_nxv1i32_0( %va) { ; RV64-NEXT: li a0, -7 ; RV64-NEXT: vnmsac.vx v8, a0, v9 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i32 -7) ret %vc } @@ -786,9 +758,7 @@ define @vrem_vi_nxv2i32_0( %va) { ; RV64-NEXT: li a0, -7 ; RV64-NEXT: vnmsac.vx v8, a0, v9 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i32 -7) ret %vc } @@ -842,9 +812,7 @@ define @vrem_vi_nxv4i32_0( %va) { ; RV64-NEXT: li a0, -7 ; RV64-NEXT: vnmsac.vx v8, a0, v10 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i32 -7) ret %vc } @@ -898,9 +866,7 @@ define @vrem_vi_nxv8i32_0( %va) { ; RV64-NEXT: li a0, -7 ; RV64-NEXT: vnmsac.vx v8, a0, v12 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i32 -7) ret %vc } @@ -954,9 +920,7 @@ define @vrem_vi_nxv16i32_0( %va) { ; RV64-NEXT: li a0, -7 ; RV64-NEXT: vnmsac.vx v8, a0, v16 ; RV64-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i32 -7) ret %vc } @@ -1039,9 +1003,7 @@ define @vrem_vi_nxv1i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v9 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i64 -7) ret %vc } @@ -1124,9 +1086,7 @@ define @vrem_vi_nxv2i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v10 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i64 -7) ret %vc } @@ -1209,9 +1169,7 @@ define @vrem_vi_nxv4i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v12 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i64 -7) ret %vc } @@ -1294,8 +1252,6 @@ define @vrem_vi_nxv8i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v16 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = srem %va, %splat + %vc = srem %va, splat (i64 -7) ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll index 74a8fce1fcd7..cf85fd827b51 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll @@ -39,9 +39,7 @@ define @vrem_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -65,9 +63,7 @@ define @vrem_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -89,9 +85,7 @@ define @vrem_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -115,9 +109,7 @@ define @vrem_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -151,9 +143,7 @@ define @vrem_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -177,9 +167,7 @@ define @vrem_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -201,9 +189,7 @@ define @vrem_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -227,9 +213,7 @@ define @vrem_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -251,9 +235,7 @@ define @vrem_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -277,9 +259,7 @@ define @vrem_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -301,9 +281,7 @@ define @vrem_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -327,9 +305,7 @@ define @vrem_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -351,9 +327,7 @@ define @vrem_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -377,9 +351,7 @@ define @vrem_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -401,9 +373,7 @@ define @vrem_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -427,9 +397,7 @@ define @vrem_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -451,9 +419,7 @@ define @vrem_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -477,9 +443,7 @@ define @vrem_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -501,9 +465,7 @@ define @vrem_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -527,9 +489,7 @@ define @vrem_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -551,9 +511,7 @@ define @vrem_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -577,9 +535,7 @@ define @vrem_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -601,9 +557,7 @@ define @vrem_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -627,9 +581,7 @@ define @vrem_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -651,9 +603,7 @@ define @vrem_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -677,9 +627,7 @@ define @vrem_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -701,9 +649,7 @@ define @vrem_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -727,9 +673,7 @@ define @vrem_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -751,9 +695,7 @@ define @vrem_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -777,9 +719,7 @@ define @vrem_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -801,9 +741,7 @@ define @vrem_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -827,9 +765,7 @@ define @vrem_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -851,9 +787,7 @@ define @vrem_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -877,9 +811,7 @@ define @vrem_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -901,9 +833,7 @@ define @vrem_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vrem.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -927,9 +857,7 @@ define @vrem_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -951,9 +879,7 @@ define @vrem_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1005,9 +931,7 @@ define @vrem_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1029,9 +953,7 @@ define @vrem_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1083,9 +1005,7 @@ define @vrem_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1107,9 +1027,7 @@ define @vrem_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1161,9 +1079,7 @@ define @vrem_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1185,9 +1101,7 @@ define @vrem_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1239,8 +1153,6 @@ define @vrem_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.srem.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.srem.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll index 428d071cac39..ed40f5af4fa4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll @@ -36,9 +36,7 @@ define @vremu_vi_nxv1i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -74,9 +72,7 @@ define @vremu_vi_nxv2i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -112,9 +108,7 @@ define @vremu_vi_nxv4i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -150,9 +144,7 @@ define @vremu_vi_nxv8i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -188,9 +180,7 @@ define @vremu_vi_nxv16i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -226,9 +216,7 @@ define @vremu_vi_nxv32i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -264,9 +252,7 @@ define @vremu_vi_nxv64i8_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i8 -7) ret %vc } @@ -303,9 +289,7 @@ define @vremu_vi_nxv1i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i16 -7) ret %vc } @@ -342,9 +326,7 @@ define @vremu_vi_nxv2i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i16 -7) ret %vc } @@ -381,9 +363,7 @@ define @vremu_vi_nxv4i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i16 -7) ret %vc } @@ -420,9 +400,7 @@ define @vremu_vi_nxv8i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i16 -7) ret %vc } @@ -459,9 +437,7 @@ define @vremu_vi_nxv16i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i16 -7) ret %vc } @@ -498,9 +474,7 @@ define @vremu_vi_nxv32i16_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i16 -7) ret %vc } @@ -537,9 +511,7 @@ define @vremu_vi_nxv1i32_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i32 -7) ret %vc } @@ -576,9 +548,7 @@ define @vremu_vi_nxv2i32_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v9 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i32 -7) ret %vc } @@ -615,9 +585,7 @@ define @vremu_vi_nxv4i32_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v10 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i32 -7) ret %vc } @@ -654,9 +622,7 @@ define @vremu_vi_nxv8i32_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i32 -7) ret %vc } @@ -693,9 +659,7 @@ define @vremu_vi_nxv16i32_0( %va) { ; CHECK-NEXT: li a0, -7 ; CHECK-NEXT: vnmsac.vx v8, a0, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i32 -7) ret %vc } @@ -773,9 +737,7 @@ define @vremu_vi_nxv1i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v9 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 -7) ret %vc } @@ -786,9 +748,7 @@ define @vremu_vi_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 16) ret %vc } @@ -803,9 +763,7 @@ define @vremu_vi_nxv1i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = urem %va, %vc ret %vd } @@ -884,9 +842,7 @@ define @vremu_vi_nxv2i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v10 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 -7) ret %vc } @@ -897,9 +853,7 @@ define @vremu_vi_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 16) ret %vc } @@ -914,9 +868,7 @@ define @vremu_vi_nxv2i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = urem %va, %vc ret %vd } @@ -995,9 +947,7 @@ define @vremu_vi_nxv4i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v12 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 -7) ret %vc } @@ -1008,9 +958,7 @@ define @vremu_vi_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 16) ret %vc } @@ -1025,9 +973,7 @@ define @vremu_vi_nxv4i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = urem %va, %vc ret %vd } @@ -1106,9 +1052,7 @@ define @vremu_vi_nxv8i64_0( %va) { ; RV64-V-NEXT: li a0, -7 ; RV64-V-NEXT: vnmsac.vx v8, a0, v16 ; RV64-V-NEXT: ret - %head = insertelement poison, i64 -7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 -7) ret %vc } @@ -1119,9 +1063,7 @@ define @vremu_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vand.vi v8, v8, 15 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = urem %va, %splat + %vc = urem %va, splat (i64 16) ret %vc } @@ -1136,9 +1078,7 @@ define @vremu_vi_nxv8i64_2( %va, poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %splat, %vb + %vc = shl splat (i64 16), %vb %vd = urem %va, %vc ret %vd } diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll index 1be66bd74f8e..61bdd5b8d3c8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll @@ -41,9 +41,7 @@ define @vremu_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -67,9 +65,7 @@ define @vremu_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -91,9 +87,7 @@ define @vremu_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -117,9 +111,7 @@ define @vremu_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -153,9 +145,7 @@ define @vremu_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -179,9 +169,7 @@ define @vremu_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -203,9 +191,7 @@ define @vremu_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -229,9 +215,7 @@ define @vremu_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -253,9 +237,7 @@ define @vremu_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -279,9 +261,7 @@ define @vremu_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -303,9 +283,7 @@ define @vremu_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -329,9 +307,7 @@ define @vremu_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -353,9 +329,7 @@ define @vremu_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -379,9 +353,7 @@ define @vremu_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -403,9 +375,7 @@ define @vremu_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -429,9 +399,7 @@ define @vremu_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -453,9 +421,7 @@ define @vremu_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -479,9 +445,7 @@ define @vremu_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -503,9 +467,7 @@ define @vremu_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -529,9 +491,7 @@ define @vremu_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -553,9 +513,7 @@ define @vremu_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -579,9 +537,7 @@ define @vremu_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -603,9 +559,7 @@ define @vremu_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -629,9 +583,7 @@ define @vremu_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -653,9 +605,7 @@ define @vremu_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -679,9 +629,7 @@ define @vremu_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -703,9 +651,7 @@ define @vremu_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -729,9 +675,7 @@ define @vremu_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -753,9 +697,7 @@ define @vremu_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -779,9 +721,7 @@ define @vremu_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -803,9 +743,7 @@ define @vremu_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -829,9 +767,7 @@ define @vremu_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -853,9 +789,7 @@ define @vremu_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -879,9 +813,7 @@ define @vremu_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -903,9 +835,7 @@ define @vremu_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vremu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -929,9 +859,7 @@ define @vremu_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -953,9 +881,7 @@ define @vremu_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1007,9 +933,7 @@ define @vremu_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1031,9 +955,7 @@ define @vremu_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1085,9 +1007,7 @@ define @vremu_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1109,9 +1029,7 @@ define @vremu_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1163,9 +1081,7 @@ define @vremu_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1187,9 +1103,7 @@ define @vremu_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1241,8 +1155,6 @@ define @vremu_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.urem.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.urem.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll index 127d3ffd7931..e97b1f41ad3d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll @@ -20,9 +20,7 @@ define @vrsub_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -44,9 +42,7 @@ define @vrsub_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -68,9 +64,7 @@ define @vrsub_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -92,9 +86,7 @@ define @vrsub_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -116,9 +108,7 @@ define @vrsub_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -140,9 +130,7 @@ define @vrsub_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -164,9 +152,7 @@ define @vrsub_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i8 -4), %va ret %vc } @@ -188,9 +174,7 @@ define @vrsub_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i16 -4), %va ret %vc } @@ -212,9 +196,7 @@ define @vrsub_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i16 -4), %va ret %vc } @@ -236,9 +218,7 @@ define @vrsub_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i16 -4), %va ret %vc } @@ -260,9 +240,7 @@ define @vrsub_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i16 -4), %va ret %vc } @@ -284,9 +262,7 @@ define @vrsub_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i16 -4), %va ret %vc } @@ -308,9 +284,7 @@ define @vrsub_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i16 -4), %va ret %vc } @@ -332,9 +306,7 @@ define @vrsub_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i32 -4), %va ret %vc } @@ -356,9 +328,7 @@ define @vrsub_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i32 -4), %va ret %vc } @@ -380,9 +350,7 @@ define @vrsub_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i32 -4), %va ret %vc } @@ -404,9 +372,7 @@ define @vrsub_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i32 -4), %va ret %vc } @@ -428,9 +394,7 @@ define @vrsub_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i32 -4), %va ret %vc } @@ -465,9 +429,7 @@ define @vrsub_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i64 -4), %va ret %vc } @@ -502,9 +464,7 @@ define @vrsub_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i64 -4), %va ret %vc } @@ -539,9 +499,7 @@ define @vrsub_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i64 -4), %va ret %vc } @@ -576,8 +534,6 @@ define @vrsub_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, -4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %splat, %va + %vc = sub splat (i64 -4), %va ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll index a6eb4de03e1c..be372c9aa54d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll @@ -26,9 +26,7 @@ define @vrsub_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -38,9 +36,7 @@ define @vrsub_vi_nxv1i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -50,11 +46,7 @@ define @vrsub_vi_nxv1i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -80,9 +72,7 @@ define @vrsub_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -92,9 +82,7 @@ define @vrsub_vi_nxv2i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -104,11 +92,7 @@ define @vrsub_vi_nxv2i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -134,9 +118,7 @@ define @vrsub_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -146,9 +128,7 @@ define @vrsub_vi_nxv4i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -158,11 +138,7 @@ define @vrsub_vi_nxv4i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -188,9 +164,7 @@ define @vrsub_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -200,9 +174,7 @@ define @vrsub_vi_nxv8i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -212,11 +184,7 @@ define @vrsub_vi_nxv8i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -242,9 +210,7 @@ define @vrsub_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -254,9 +220,7 @@ define @vrsub_vi_nxv16i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -266,11 +230,7 @@ define @vrsub_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -296,9 +256,7 @@ define @vrsub_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +266,7 @@ define @vrsub_vi_nxv32i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -320,11 +276,7 @@ define @vrsub_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -350,9 +302,7 @@ define @vrsub_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv64i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv64i8( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -362,9 +312,7 @@ define @vrsub_vi_nxv64i8( %va, poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv64i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv64i8( splat (i8 2), %va, %m, i32 %evl) ret %v } @@ -374,11 +322,7 @@ define @vrsub_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv64i8( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv64i8( splat (i8 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -404,9 +348,7 @@ define @vrsub_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -416,9 +358,7 @@ define @vrsub_vi_nxv1i16( %va, poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i16( splat (i16 2), %va, %m, i32 %evl) ret %v } @@ -428,11 +368,7 @@ define @vrsub_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i16( splat (i16 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -458,9 +394,7 @@ define @vrsub_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -470,9 +404,7 @@ define @vrsub_vi_nxv2i16( %va, poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i16( splat (i16 2), %va, %m, i32 %evl) ret %v } @@ -482,11 +414,7 @@ define @vrsub_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i16( splat (i16 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +440,7 @@ define @vrsub_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -524,9 +450,7 @@ define @vrsub_vi_nxv4i16( %va, poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i16( splat (i16 2), %va, %m, i32 %evl) ret %v } @@ -536,11 +460,7 @@ define @vrsub_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i16( splat (i16 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -566,9 +486,7 @@ define @vrsub_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -578,9 +496,7 @@ define @vrsub_vi_nxv8i16( %va, poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i16( splat (i16 2), %va, %m, i32 %evl) ret %v } @@ -590,11 +506,7 @@ define @vrsub_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i16( splat (i16 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -620,9 +532,7 @@ define @vrsub_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -632,9 +542,7 @@ define @vrsub_vi_nxv16i16( %va, poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i16( splat (i16 2), %va, %m, i32 %evl) ret %v } @@ -644,11 +552,7 @@ define @vrsub_vi_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i16( splat (i16 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -674,9 +578,7 @@ define @vrsub_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i16( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -686,9 +588,7 @@ define @vrsub_vi_nxv32i16( %va, poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i16( splat (i16 2), %va, %m, i32 %evl) ret %v } @@ -698,11 +598,7 @@ define @vrsub_vi_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i16( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i16( splat (i16 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -728,9 +624,7 @@ define @vrsub_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -740,9 +634,7 @@ define @vrsub_vi_nxv1i32( %va, poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i32( splat (i32 2), %va, %m, i32 %evl) ret %v } @@ -752,11 +644,7 @@ define @vrsub_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i32( splat (i32 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -782,9 +670,7 @@ define @vrsub_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -794,9 +680,7 @@ define @vrsub_vi_nxv2i32( %va, poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i32( splat (i32 2), %va, %m, i32 %evl) ret %v } @@ -806,11 +690,7 @@ define @vrsub_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i32( splat (i32 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -836,9 +716,7 @@ define @vrsub_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -848,9 +726,7 @@ define @vrsub_vi_nxv4i32( %va, poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i32( splat (i32 2), %va, %m, i32 %evl) ret %v } @@ -860,11 +736,7 @@ define @vrsub_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i32( splat (i32 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -890,9 +762,7 @@ define @vrsub_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -902,9 +772,7 @@ define @vrsub_vi_nxv8i32( %va, poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i32( splat (i32 2), %va, %m, i32 %evl) ret %v } @@ -914,11 +782,7 @@ define @vrsub_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i32( splat (i32 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -944,9 +808,7 @@ define @vrsub_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i32( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -956,9 +818,7 @@ define @vrsub_vi_nxv16i32( %va, poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i32( splat (i32 2), %va, %m, i32 %evl) ret %v } @@ -968,11 +828,7 @@ define @vrsub_vi_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i32( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i32( splat (i32 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -1026,9 +882,7 @@ define @vrsub_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -1038,9 +892,7 @@ define @vrsub_vi_nxv1i64( %va, poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i64( splat (i64 2), %va, %m, i32 %evl) ret %v } @@ -1050,11 +902,7 @@ define @vrsub_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i64( splat (i64 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -1108,9 +956,7 @@ define @vrsub_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -1120,9 +966,7 @@ define @vrsub_vi_nxv2i64( %va, poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i64( splat (i64 2), %va, %m, i32 %evl) ret %v } @@ -1132,11 +976,7 @@ define @vrsub_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i64( splat (i64 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -1190,9 +1030,7 @@ define @vrsub_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -1202,9 +1040,7 @@ define @vrsub_vi_nxv4i64( %va, poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i64( splat (i64 2), %va, %m, i32 %evl) ret %v } @@ -1214,11 +1050,7 @@ define @vrsub_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i64( splat (i64 2), %va, splat (i1 true), i32 %evl) ret %v } @@ -1272,9 +1104,7 @@ define @vrsub_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i64( %vb, %va, splat (i1 true), i32 %evl) ret %v } @@ -1284,9 +1114,7 @@ define @vrsub_vi_nxv8i64( %va, poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i64( splat (i64 2), %va, %m, i32 %evl) ret %v } @@ -1296,10 +1124,6 @@ define @vrsub_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vrsub.vi v8, v8, 2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i64( %vb, %va, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i64( splat (i64 2), %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll index 38edd19096f8..6a8b80125405 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll @@ -34,9 +34,7 @@ define @sadd_nxv1i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv1i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv1i8( %va, splat (i8 5)) ret %v } @@ -70,9 +68,7 @@ define @sadd_nxv2i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv2i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv2i8( %va, splat (i8 5)) ret %v } @@ -106,9 +102,7 @@ define @sadd_nxv4i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv4i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv4i8( %va, splat (i8 5)) ret %v } @@ -142,9 +136,7 @@ define @sadd_nxv8i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv8i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv8i8( %va, splat (i8 5)) ret %v } @@ -178,9 +170,7 @@ define @sadd_nxv16i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv16i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv16i8( %va, splat (i8 5)) ret %v } @@ -214,9 +204,7 @@ define @sadd_nxv32i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv32i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv32i8( %va, splat (i8 5)) ret %v } @@ -250,9 +238,7 @@ define @sadd_nxv64i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv64i8( %va, %vb) + %v = call @llvm.sadd.sat.nxv64i8( %va, splat (i8 5)) ret %v } @@ -286,9 +272,7 @@ define @sadd_nxv1i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv1i16( %va, %vb) + %v = call @llvm.sadd.sat.nxv1i16( %va, splat (i16 5)) ret %v } @@ -322,9 +306,7 @@ define @sadd_nxv2i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv2i16( %va, %vb) + %v = call @llvm.sadd.sat.nxv2i16( %va, splat (i16 5)) ret %v } @@ -358,9 +340,7 @@ define @sadd_nxv4i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv4i16( %va, %vb) + %v = call @llvm.sadd.sat.nxv4i16( %va, splat (i16 5)) ret %v } @@ -394,9 +374,7 @@ define @sadd_nxv8i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv8i16( %va, %vb) + %v = call @llvm.sadd.sat.nxv8i16( %va, splat (i16 5)) ret %v } @@ -430,9 +408,7 @@ define @sadd_nxv16i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv16i16( %va, %vb) + %v = call @llvm.sadd.sat.nxv16i16( %va, splat (i16 5)) ret %v } @@ -466,9 +442,7 @@ define @sadd_nxv32i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv32i16( %va, %vb) + %v = call @llvm.sadd.sat.nxv32i16( %va, splat (i16 5)) ret %v } @@ -502,9 +476,7 @@ define @sadd_nxv1i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv1i32( %va, %vb) + %v = call @llvm.sadd.sat.nxv1i32( %va, splat (i32 5)) ret %v } @@ -538,9 +510,7 @@ define @sadd_nxv2i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv2i32( %va, %vb) + %v = call @llvm.sadd.sat.nxv2i32( %va, splat (i32 5)) ret %v } @@ -574,9 +544,7 @@ define @sadd_nxv4i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv4i32( %va, %vb) + %v = call @llvm.sadd.sat.nxv4i32( %va, splat (i32 5)) ret %v } @@ -610,9 +578,7 @@ define @sadd_nxv8i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv8i32( %va, %vb) + %v = call @llvm.sadd.sat.nxv8i32( %va, splat (i32 5)) ret %v } @@ -646,9 +612,7 @@ define @sadd_nxv16i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv16i32( %va, %vb) + %v = call @llvm.sadd.sat.nxv16i32( %va, splat (i32 5)) ret %v } @@ -695,9 +659,7 @@ define @sadd_nxv1i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv1i64( %va, %vb) + %v = call @llvm.sadd.sat.nxv1i64( %va, splat (i64 5)) ret %v } @@ -744,9 +706,7 @@ define @sadd_nxv2i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv2i64( %va, %vb) + %v = call @llvm.sadd.sat.nxv2i64( %va, splat (i64 5)) ret %v } @@ -793,9 +753,7 @@ define @sadd_nxv4i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv4i64( %va, %vb) + %v = call @llvm.sadd.sat.nxv4i64( %va, splat (i64 5)) ret %v } @@ -842,8 +800,6 @@ define @sadd_nxv8i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.sadd.sat.nxv8i64( %va, %vb) + %v = call @llvm.sadd.sat.nxv8i64( %va, splat (i64 5)) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll index caaeae55ed78..f9ea5143cfcb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll @@ -43,9 +43,7 @@ define @vsadd_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -81,9 +79,7 @@ define @vsadd_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -93,9 +89,7 @@ define @vsadd_vi_nxv1i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -105,11 +99,7 @@ define @vsadd_vi_nxv1i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -131,9 +121,7 @@ define @vsadd_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -157,9 +145,7 @@ define @vsadd_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -169,9 +155,7 @@ define @vsadd_vi_nxv2i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -181,11 +165,7 @@ define @vsadd_vi_nxv2i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -207,9 +187,7 @@ define @vsadd_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -233,9 +211,7 @@ define @vsadd_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -245,9 +221,7 @@ define @vsadd_vi_nxv3i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv3i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -257,11 +231,7 @@ define @vsadd_vi_nxv3i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv3i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -283,9 +253,7 @@ define @vsadd_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -309,9 +277,7 @@ define @vsadd_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -321,9 +287,7 @@ define @vsadd_vi_nxv4i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -333,11 +297,7 @@ define @vsadd_vi_nxv4i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -359,9 +319,7 @@ define @vsadd_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -385,9 +343,7 @@ define @vsadd_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -397,9 +353,7 @@ define @vsadd_vi_nxv8i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -409,11 +363,7 @@ define @vsadd_vi_nxv8i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -435,9 +385,7 @@ define @vsadd_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -461,9 +409,7 @@ define @vsadd_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -473,9 +419,7 @@ define @vsadd_vi_nxv16i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -485,11 +429,7 @@ define @vsadd_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -511,9 +451,7 @@ define @vsadd_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -537,9 +475,7 @@ define @vsadd_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -549,9 +485,7 @@ define @vsadd_vi_nxv32i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -561,11 +495,7 @@ define @vsadd_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -587,9 +517,7 @@ define @vsadd_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -613,9 +541,7 @@ define @vsadd_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -625,9 +551,7 @@ define @vsadd_vi_nxv64i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv64i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -637,11 +561,7 @@ define @vsadd_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv64i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -671,9 +591,7 @@ define @vsadd_vi_nxv128i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv128i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -695,11 +613,7 @@ define @vsadd_vi_nxv128i8_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv128i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -721,9 +635,7 @@ define @vsadd_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -747,9 +659,7 @@ define @vsadd_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -759,9 +669,7 @@ define @vsadd_vi_nxv1i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -771,11 +679,7 @@ define @vsadd_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -797,9 +701,7 @@ define @vsadd_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -823,9 +725,7 @@ define @vsadd_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -835,9 +735,7 @@ define @vsadd_vi_nxv2i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -847,11 +745,7 @@ define @vsadd_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -873,9 +767,7 @@ define @vsadd_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -899,9 +791,7 @@ define @vsadd_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -911,9 +801,7 @@ define @vsadd_vi_nxv4i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -923,11 +811,7 @@ define @vsadd_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -949,9 +833,7 @@ define @vsadd_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -975,9 +857,7 @@ define @vsadd_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -987,9 +867,7 @@ define @vsadd_vi_nxv8i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -999,11 +877,7 @@ define @vsadd_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1025,9 +899,7 @@ define @vsadd_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1051,9 +923,7 @@ define @vsadd_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1063,9 +933,7 @@ define @vsadd_vi_nxv16i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1075,11 +943,7 @@ define @vsadd_vi_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1101,9 +965,7 @@ define @vsadd_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1127,9 +989,7 @@ define @vsadd_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1139,9 +999,7 @@ define @vsadd_vi_nxv32i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1151,11 +1009,7 @@ define @vsadd_vi_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1177,9 +1031,7 @@ define @vsadd_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1203,9 +1055,7 @@ define @vsadd_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1215,9 +1065,7 @@ define @vsadd_vi_nxv1i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1227,11 +1075,7 @@ define @vsadd_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1253,9 +1097,7 @@ define @vsadd_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1279,9 +1121,7 @@ define @vsadd_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1291,9 +1131,7 @@ define @vsadd_vi_nxv2i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1303,11 +1141,7 @@ define @vsadd_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1329,9 +1163,7 @@ define @vsadd_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1355,9 +1187,7 @@ define @vsadd_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1367,9 +1197,7 @@ define @vsadd_vi_nxv4i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1379,11 +1207,7 @@ define @vsadd_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1405,9 +1229,7 @@ define @vsadd_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1431,9 +1253,7 @@ define @vsadd_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1443,9 +1263,7 @@ define @vsadd_vi_nxv8i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1455,11 +1273,7 @@ define @vsadd_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1481,9 +1295,7 @@ define @vsadd_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1507,9 +1319,7 @@ define @vsadd_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1519,9 +1329,7 @@ define @vsadd_vi_nxv16i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1531,11 +1339,7 @@ define @vsadd_vi_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv16i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1566,9 +1370,7 @@ define @vsadd_vi_nxv32i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1590,11 +1392,7 @@ define @vsadd_vi_nxv32i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv32i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1616,9 +1414,7 @@ define @vsadd_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1670,9 +1466,7 @@ define @vsadd_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1682,9 +1476,7 @@ define @vsadd_vi_nxv1i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1694,11 +1486,7 @@ define @vsadd_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv1i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1720,9 +1508,7 @@ define @vsadd_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1774,9 +1560,7 @@ define @vsadd_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1786,9 +1570,7 @@ define @vsadd_vi_nxv2i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1798,11 +1580,7 @@ define @vsadd_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv2i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1824,9 +1602,7 @@ define @vsadd_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1878,9 +1654,7 @@ define @vsadd_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1890,9 +1664,7 @@ define @vsadd_vi_nxv4i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1902,11 +1674,7 @@ define @vsadd_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv4i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1928,9 +1696,7 @@ define @vsadd_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1982,9 +1748,7 @@ define @vsadd_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1994,9 +1758,7 @@ define @vsadd_vi_nxv8i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2006,10 +1768,6 @@ define @vsadd_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sadd.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sadd.sat.nxv8i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll index ac520f891120..4fe765c34ba6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll @@ -34,9 +34,7 @@ define @uadd_nxv1i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv1i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv1i8( %va, splat (i8 8)) ret %v } @@ -70,9 +68,7 @@ define @uadd_nxv2i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv2i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv2i8( %va, splat (i8 8)) ret %v } @@ -106,9 +102,7 @@ define @uadd_nxv4i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv4i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv4i8( %va, splat (i8 8)) ret %v } @@ -142,9 +136,7 @@ define @uadd_nxv8i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv8i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv8i8( %va, splat (i8 8)) ret %v } @@ -178,9 +170,7 @@ define @uadd_nxv16i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv16i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv16i8( %va, splat (i8 8)) ret %v } @@ -214,9 +204,7 @@ define @uadd_nxv32i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv32i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv32i8( %va, splat (i8 8)) ret %v } @@ -250,9 +238,7 @@ define @uadd_nxv64i8_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv64i8( %va, %vb) + %v = call @llvm.uadd.sat.nxv64i8( %va, splat (i8 8)) ret %v } @@ -286,9 +272,7 @@ define @uadd_nxv1i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv1i16( %va, %vb) + %v = call @llvm.uadd.sat.nxv1i16( %va, splat (i16 8)) ret %v } @@ -322,9 +306,7 @@ define @uadd_nxv2i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv2i16( %va, %vb) + %v = call @llvm.uadd.sat.nxv2i16( %va, splat (i16 8)) ret %v } @@ -358,9 +340,7 @@ define @uadd_nxv4i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv4i16( %va, %vb) + %v = call @llvm.uadd.sat.nxv4i16( %va, splat (i16 8)) ret %v } @@ -394,9 +374,7 @@ define @uadd_nxv8i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv8i16( %va, %vb) + %v = call @llvm.uadd.sat.nxv8i16( %va, splat (i16 8)) ret %v } @@ -430,9 +408,7 @@ define @uadd_nxv16i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv16i16( %va, %vb) + %v = call @llvm.uadd.sat.nxv16i16( %va, splat (i16 8)) ret %v } @@ -466,9 +442,7 @@ define @uadd_nxv32i16_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv32i16( %va, %vb) + %v = call @llvm.uadd.sat.nxv32i16( %va, splat (i16 8)) ret %v } @@ -502,9 +476,7 @@ define @uadd_nxv1i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv1i32( %va, %vb) + %v = call @llvm.uadd.sat.nxv1i32( %va, splat (i32 8)) ret %v } @@ -538,9 +510,7 @@ define @uadd_nxv2i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv2i32( %va, %vb) + %v = call @llvm.uadd.sat.nxv2i32( %va, splat (i32 8)) ret %v } @@ -574,9 +544,7 @@ define @uadd_nxv4i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv4i32( %va, %vb) + %v = call @llvm.uadd.sat.nxv4i32( %va, splat (i32 8)) ret %v } @@ -610,9 +578,7 @@ define @uadd_nxv8i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv8i32( %va, %vb) + %v = call @llvm.uadd.sat.nxv8i32( %va, splat (i32 8)) ret %v } @@ -646,9 +612,7 @@ define @uadd_nxv16i32_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv16i32( %va, %vb) + %v = call @llvm.uadd.sat.nxv16i32( %va, splat (i32 8)) ret %v } @@ -695,9 +659,7 @@ define @uadd_nxv1i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv1i64( %va, %vb) + %v = call @llvm.uadd.sat.nxv1i64( %va, splat (i64 8)) ret %v } @@ -744,9 +706,7 @@ define @uadd_nxv2i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv2i64( %va, %vb) + %v = call @llvm.uadd.sat.nxv2i64( %va, splat (i64 8)) ret %v } @@ -793,9 +753,7 @@ define @uadd_nxv4i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv4i64( %va, %vb) + %v = call @llvm.uadd.sat.nxv4i64( %va, splat (i64 8)) ret %v } @@ -842,8 +800,6 @@ define @uadd_nxv8i64_vi( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, 8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 8, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.uadd.sat.nxv8i64( %va, %vb) + %v = call @llvm.uadd.sat.nxv8i64( %va, splat (i64 8)) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll index c0779e508c0a..745b93b25708 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll @@ -42,9 +42,7 @@ define @vsaddu_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -80,9 +78,7 @@ define @vsaddu_vx_nxv1i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -92,9 +88,7 @@ define @vsaddu_vi_nxv1i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -104,11 +98,7 @@ define @vsaddu_vi_nxv1i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -130,9 +120,7 @@ define @vsaddu_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -156,9 +144,7 @@ define @vsaddu_vx_nxv2i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -168,9 +154,7 @@ define @vsaddu_vi_nxv2i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -180,11 +164,7 @@ define @vsaddu_vi_nxv2i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -206,9 +186,7 @@ define @vsaddu_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +210,7 @@ define @vsaddu_vx_nxv3i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -244,9 +220,7 @@ define @vsaddu_vi_nxv3i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv3i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -256,11 +230,7 @@ define @vsaddu_vi_nxv3i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv3i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -282,9 +252,7 @@ define @vsaddu_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +276,7 @@ define @vsaddu_vx_nxv4i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -320,9 +286,7 @@ define @vsaddu_vi_nxv4i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -332,11 +296,7 @@ define @vsaddu_vi_nxv4i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -358,9 +318,7 @@ define @vsaddu_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -384,9 +342,7 @@ define @vsaddu_vx_nxv8i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -396,9 +352,7 @@ define @vsaddu_vi_nxv8i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -408,11 +362,7 @@ define @vsaddu_vi_nxv8i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -434,9 +384,7 @@ define @vsaddu_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -460,9 +408,7 @@ define @vsaddu_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -472,9 +418,7 @@ define @vsaddu_vi_nxv16i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -484,11 +428,7 @@ define @vsaddu_vi_nxv16i8_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -510,9 +450,7 @@ define @vsaddu_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -536,9 +474,7 @@ define @vsaddu_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -548,9 +484,7 @@ define @vsaddu_vi_nxv32i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -560,11 +494,7 @@ define @vsaddu_vi_nxv32i8_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -586,9 +516,7 @@ define @vsaddu_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -612,9 +540,7 @@ define @vsaddu_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -624,9 +550,7 @@ define @vsaddu_vi_nxv64i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv64i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -636,11 +560,7 @@ define @vsaddu_vi_nxv64i8_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv64i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -670,9 +590,7 @@ define @vsaddu_vi_nxv128i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv128i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -694,11 +612,7 @@ define @vsaddu_vi_nxv128i8_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv128i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -720,9 +634,7 @@ define @vsaddu_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -746,9 +658,7 @@ define @vsaddu_vx_nxv1i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -758,9 +668,7 @@ define @vsaddu_vi_nxv1i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -770,11 +678,7 @@ define @vsaddu_vi_nxv1i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -796,9 +700,7 @@ define @vsaddu_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -822,9 +724,7 @@ define @vsaddu_vx_nxv2i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -834,9 +734,7 @@ define @vsaddu_vi_nxv2i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -846,11 +744,7 @@ define @vsaddu_vi_nxv2i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -872,9 +766,7 @@ define @vsaddu_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -898,9 +790,7 @@ define @vsaddu_vx_nxv4i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -910,9 +800,7 @@ define @vsaddu_vi_nxv4i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -922,11 +810,7 @@ define @vsaddu_vi_nxv4i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -948,9 +832,7 @@ define @vsaddu_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -974,9 +856,7 @@ define @vsaddu_vx_nxv8i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -986,9 +866,7 @@ define @vsaddu_vi_nxv8i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -998,11 +876,7 @@ define @vsaddu_vi_nxv8i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1024,9 +898,7 @@ define @vsaddu_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1050,9 +922,7 @@ define @vsaddu_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1062,9 +932,7 @@ define @vsaddu_vi_nxv16i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1074,11 +942,7 @@ define @vsaddu_vi_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1100,9 +964,7 @@ define @vsaddu_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1126,9 +988,7 @@ define @vsaddu_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1138,9 +998,7 @@ define @vsaddu_vi_nxv32i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1150,11 +1008,7 @@ define @vsaddu_vi_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1176,9 +1030,7 @@ define @vsaddu_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1202,9 +1054,7 @@ define @vsaddu_vx_nxv1i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1214,9 +1064,7 @@ define @vsaddu_vi_nxv1i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1226,11 +1074,7 @@ define @vsaddu_vi_nxv1i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1252,9 +1096,7 @@ define @vsaddu_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1278,9 +1120,7 @@ define @vsaddu_vx_nxv2i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1290,9 +1130,7 @@ define @vsaddu_vi_nxv2i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1302,11 +1140,7 @@ define @vsaddu_vi_nxv2i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1328,9 +1162,7 @@ define @vsaddu_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1354,9 +1186,7 @@ define @vsaddu_vx_nxv4i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1366,9 +1196,7 @@ define @vsaddu_vi_nxv4i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1378,11 +1206,7 @@ define @vsaddu_vi_nxv4i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1404,9 +1228,7 @@ define @vsaddu_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1430,9 +1252,7 @@ define @vsaddu_vx_nxv8i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1442,9 +1262,7 @@ define @vsaddu_vi_nxv8i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1454,11 +1272,7 @@ define @vsaddu_vi_nxv8i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1480,9 +1294,7 @@ define @vsaddu_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsaddu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1506,9 +1318,7 @@ define @vsaddu_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1518,9 +1328,7 @@ define @vsaddu_vi_nxv16i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1530,11 +1338,7 @@ define @vsaddu_vi_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv16i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1565,9 +1369,7 @@ define @vsaddu_vi_nxv32i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1589,11 +1391,7 @@ define @vsaddu_vi_nxv32i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv32i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1615,9 +1413,7 @@ define @vsaddu_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1669,9 +1465,7 @@ define @vsaddu_vx_nxv1i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1681,9 +1475,7 @@ define @vsaddu_vi_nxv1i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1693,11 +1485,7 @@ define @vsaddu_vi_nxv1i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv1i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1719,9 +1507,7 @@ define @vsaddu_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1773,9 +1559,7 @@ define @vsaddu_vx_nxv2i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1785,9 +1569,7 @@ define @vsaddu_vi_nxv2i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1797,11 +1579,7 @@ define @vsaddu_vi_nxv2i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv2i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1823,9 +1601,7 @@ define @vsaddu_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1877,9 +1653,7 @@ define @vsaddu_vx_nxv4i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1889,9 +1663,7 @@ define @vsaddu_vi_nxv4i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1901,11 +1673,7 @@ define @vsaddu_vi_nxv4i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv4i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1927,9 +1695,7 @@ define @vsaddu_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1981,9 +1747,7 @@ define @vsaddu_vx_nxv8i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1993,9 +1757,7 @@ define @vsaddu_vi_nxv8i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2005,10 +1767,6 @@ define @vsaddu_vi_nxv8i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsaddu.vi v8, v8, -1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.uadd.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.uadd.sat.nxv8i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll index 17c362fc0a1a..4457c1002acc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll @@ -138,9 +138,7 @@ define @vfmerge_zv_nxv8f16( %va, poison, half zeroinitializer, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (half zeroinitializer), %va ret %vc } @@ -148,9 +146,7 @@ define @vmerge_truelhs_nxv8f16_0( %va, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %vc = select %mtrue, %va, %vb + %vc = select splat (i1 1), %va, %vb ret %vc } @@ -322,9 +318,7 @@ define @vfmerge_zv_nxv8f32( %va, poison, float zeroinitializer, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (float zeroinitializer), %va ret %vc } @@ -444,9 +438,7 @@ define @vfmerge_zv_nxv8f64( %va, poison, double zeroinitializer, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (double zeroinitializer), %va ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-int.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-int.ll index 19c7d599cb06..2715ec78bd79 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-int.ll @@ -32,9 +32,7 @@ define @vmerge_iv_nxv1i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -66,9 +64,7 @@ define @vmerge_iv_nxv2i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -100,9 +96,7 @@ define @vmerge_iv_nxv3i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -134,9 +128,7 @@ define @vmerge_iv_nxv4i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -168,9 +160,7 @@ define @vmerge_iv_nxv8i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -202,9 +192,7 @@ define @vmerge_iv_nxv16i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -236,9 +224,7 @@ define @vmerge_iv_nxv32i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -270,9 +256,7 @@ define @vmerge_iv_nxv64i8( %va, poison, i8 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i8 3), %va ret %vc } @@ -304,9 +288,7 @@ define @vmerge_iv_nxv1i16( %va, poison, i16 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i16 3), %va ret %vc } @@ -338,9 +320,7 @@ define @vmerge_iv_nxv2i16( %va, poison, i16 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i16 3), %va ret %vc } @@ -372,9 +352,7 @@ define @vmerge_iv_nxv4i16( %va, poison, i16 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i16 3), %va ret %vc } @@ -406,9 +384,7 @@ define @vmerge_iv_nxv8i16( %va, poison, i16 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i16 3), %va ret %vc } @@ -440,9 +416,7 @@ define @vmerge_iv_nxv16i16( %va, poison, i16 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i16 3), %va ret %vc } @@ -474,9 +448,7 @@ define @vmerge_iv_nxv32i16( %va, poison, i16 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i16 3), %va ret %vc } @@ -508,9 +480,7 @@ define @vmerge_iv_nxv1i32( %va, poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i32 3), %va ret %vc } @@ -542,9 +512,7 @@ define @vmerge_iv_nxv2i32( %va, poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i32 3), %va ret %vc } @@ -576,9 +544,7 @@ define @vmerge_iv_nxv4i32( %va, poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i32 3), %va ret %vc } @@ -610,9 +576,7 @@ define @vmerge_iv_nxv8i32( %va, poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i32 3), %va ret %vc } @@ -644,9 +608,7 @@ define @vmerge_iv_nxv16i32( %va, poison, i32 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i32 3), %va ret %vc } @@ -690,9 +652,7 @@ define @vmerge_iv_nxv1i64( %va, poison, i64 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i64 3), %va ret %vc } @@ -736,9 +696,7 @@ define @vmerge_iv_nxv2i64( %va, poison, i64 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i64 3), %va ret %vc } @@ -782,9 +740,7 @@ define @vmerge_iv_nxv4i64( %va, poison, i64 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i64 3), %va ret %vc } @@ -828,9 +784,7 @@ define @vmerge_iv_nxv8i64( %va, poison, i64 3, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = select %cond, %splat, %va + %vc = select %cond, splat (i64 3), %va ret %vc } @@ -838,9 +792,7 @@ define @vmerge_truelhs_nxv8i64_0( %va, poison, i1 1, i32 0 - %mtrue = shufflevector %mhead, poison, zeroinitializer - %vc = select %mtrue, %va, %vb + %vc = select splat (i1 1), %va, %vb ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll index 93f43f4578dd..5b101cf67354 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll @@ -20,9 +20,7 @@ define @vshl_vx_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -44,9 +42,7 @@ define @vshl_vx_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -68,9 +64,7 @@ define @vshl_vx_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -92,9 +86,7 @@ define @vshl_vx_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -116,9 +108,7 @@ define @vshl_vx_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -140,9 +130,7 @@ define @vshl_vx_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -164,9 +152,7 @@ define @vshl_vx_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i8 6) ret %vc } @@ -188,9 +174,7 @@ define @vshl_vx_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i16 6) ret %vc } @@ -212,9 +196,7 @@ define @vshl_vx_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i16 6) ret %vc } @@ -236,9 +218,7 @@ define @vshl_vx_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i16 6) ret %vc } @@ -260,9 +240,7 @@ define @vshl_vx_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i16 6) ret %vc } @@ -284,9 +262,7 @@ define @vshl_vx_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i16 6) ret %vc } @@ -308,9 +284,7 @@ define @vshl_vx_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i16 6) ret %vc } @@ -332,9 +306,7 @@ define @vshl_vx_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i32 31) ret %vc } @@ -356,9 +328,7 @@ define @vshl_vx_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i32 31) ret %vc } @@ -380,9 +350,7 @@ define @vshl_vx_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i32 31) ret %vc } @@ -404,9 +372,7 @@ define @vshl_vx_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i32 31) ret %vc } @@ -428,9 +394,7 @@ define @vshl_vx_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i32 31) ret %vc } @@ -452,9 +416,7 @@ define @vshl_vx_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 31) ret %vc } @@ -465,9 +427,7 @@ define @vshl_vx_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 32) ret %vc } @@ -477,9 +437,7 @@ define @vshl_vx_nxv1i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 1) ret %vc } @@ -501,9 +459,7 @@ define @vshl_vx_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 31) ret %vc } @@ -514,9 +470,7 @@ define @vshl_vx_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 32) ret %vc } @@ -526,9 +480,7 @@ define @vshl_vx_nxv2i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 1) ret %vc } @@ -550,9 +502,7 @@ define @vshl_vx_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 31) ret %vc } @@ -563,9 +513,7 @@ define @vshl_vx_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 32) ret %vc } @@ -575,9 +523,7 @@ define @vshl_vx_nxv4i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 1) ret %vc } @@ -599,9 +545,7 @@ define @vshl_vx_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 31) ret %vc } @@ -612,9 +556,7 @@ define @vshl_vx_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsll.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 32) ret %vc } @@ -624,9 +566,7 @@ define @vshl_vx_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = shl %va, %splat + %vc = shl %va, splat (i64 1) ret %vc } @@ -660,9 +600,7 @@ define @vshl_vi_mask_nxv8i32( %va, poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 31), zeroinitializer %vc = shl %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll index 9ab5218e897e..c04d5ea2da3c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll @@ -40,9 +40,7 @@ define @vsll_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -66,9 +64,7 @@ define @vsll_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -78,9 +74,7 @@ define @vsll_vi_nxv1i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -90,11 +84,7 @@ define @vsll_vi_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -116,9 +106,7 @@ define @vsll_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -142,9 +130,7 @@ define @vsll_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -154,9 +140,7 @@ define @vsll_vi_nxv2i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -166,11 +150,7 @@ define @vsll_vi_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -192,9 +172,7 @@ define @vsll_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -218,9 +196,7 @@ define @vsll_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -230,9 +206,7 @@ define @vsll_vi_nxv4i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -242,11 +216,7 @@ define @vsll_vi_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -280,9 +250,7 @@ define @vsll_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -306,9 +274,7 @@ define @vsll_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -318,9 +284,7 @@ define @vsll_vi_nxv8i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -330,11 +294,7 @@ define @vsll_vi_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -356,9 +316,7 @@ define @vsll_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -382,9 +340,7 @@ define @vsll_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -394,9 +350,7 @@ define @vsll_vi_nxv16i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -406,11 +360,7 @@ define @vsll_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -432,9 +382,7 @@ define @vsll_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -458,9 +406,7 @@ define @vsll_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -470,9 +416,7 @@ define @vsll_vi_nxv32i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -482,11 +426,7 @@ define @vsll_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -508,9 +448,7 @@ define @vsll_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -534,9 +472,7 @@ define @vsll_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -546,9 +482,7 @@ define @vsll_vi_nxv64i8( %va, poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv64i8( %va, splat (i8 3), %m, i32 %evl) ret %v } @@ -558,11 +492,7 @@ define @vsll_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv64i8( %va, splat (i8 3), splat (i1 true), i32 %evl) ret %v } @@ -584,9 +514,7 @@ define @vsll_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -610,9 +538,7 @@ define @vsll_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -622,9 +548,7 @@ define @vsll_vi_nxv1i16( %va, poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i16( %va, splat (i16 3), %m, i32 %evl) ret %v } @@ -634,11 +558,7 @@ define @vsll_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i16( %va, splat (i16 3), splat (i1 true), i32 %evl) ret %v } @@ -660,9 +580,7 @@ define @vsll_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -686,9 +604,7 @@ define @vsll_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -698,9 +614,7 @@ define @vsll_vi_nxv2i16( %va, poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i16( %va, splat (i16 3), %m, i32 %evl) ret %v } @@ -710,11 +624,7 @@ define @vsll_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i16( %va, splat (i16 3), splat (i1 true), i32 %evl) ret %v } @@ -736,9 +646,7 @@ define @vsll_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -762,9 +670,7 @@ define @vsll_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -774,9 +680,7 @@ define @vsll_vi_nxv4i16( %va, poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i16( %va, splat (i16 3), %m, i32 %evl) ret %v } @@ -786,11 +690,7 @@ define @vsll_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i16( %va, splat (i16 3), splat (i1 true), i32 %evl) ret %v } @@ -812,9 +712,7 @@ define @vsll_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -838,9 +736,7 @@ define @vsll_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -850,9 +746,7 @@ define @vsll_vi_nxv8i16( %va, poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i16( %va, splat (i16 3), %m, i32 %evl) ret %v } @@ -862,11 +756,7 @@ define @vsll_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i16( %va, splat (i16 3), splat (i1 true), i32 %evl) ret %v } @@ -888,9 +778,7 @@ define @vsll_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -914,9 +802,7 @@ define @vsll_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -926,9 +812,7 @@ define @vsll_vi_nxv16i16( %va, poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i16( %va, splat (i16 3), %m, i32 %evl) ret %v } @@ -938,11 +822,7 @@ define @vsll_vi_nxv16i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i16( %va, splat (i16 3), splat (i1 true), i32 %evl) ret %v } @@ -964,9 +844,7 @@ define @vsll_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -990,9 +868,7 @@ define @vsll_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1002,9 +878,7 @@ define @vsll_vi_nxv32i16( %va, poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i16( %va, splat (i16 3), %m, i32 %evl) ret %v } @@ -1014,11 +888,7 @@ define @vsll_vi_nxv32i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv32i16( %va, splat (i16 3), splat (i1 true), i32 %evl) ret %v } @@ -1040,9 +910,7 @@ define @vsll_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1066,9 +934,7 @@ define @vsll_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1078,9 +944,7 @@ define @vsll_vi_nxv1i32( %va, poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i32( %va, splat (i32 3), %m, i32 %evl) ret %v } @@ -1090,11 +954,7 @@ define @vsll_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i32( %va, splat (i32 3), splat (i1 true), i32 %evl) ret %v } @@ -1116,9 +976,7 @@ define @vsll_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1142,9 +1000,7 @@ define @vsll_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1154,9 +1010,7 @@ define @vsll_vi_nxv2i32( %va, poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i32( %va, splat (i32 3), %m, i32 %evl) ret %v } @@ -1166,11 +1020,7 @@ define @vsll_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i32( %va, splat (i32 3), splat (i1 true), i32 %evl) ret %v } @@ -1192,9 +1042,7 @@ define @vsll_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1218,9 +1066,7 @@ define @vsll_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1230,9 +1076,7 @@ define @vsll_vi_nxv4i32( %va, poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i32( %va, splat (i32 3), %m, i32 %evl) ret %v } @@ -1242,11 +1086,7 @@ define @vsll_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i32( %va, splat (i32 3), splat (i1 true), i32 %evl) ret %v } @@ -1268,9 +1108,7 @@ define @vsll_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1294,9 +1132,7 @@ define @vsll_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1306,9 +1142,7 @@ define @vsll_vi_nxv8i32( %va, poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i32( %va, splat (i32 3), %m, i32 %evl) ret %v } @@ -1318,11 +1152,7 @@ define @vsll_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i32( %va, splat (i32 3), splat (i1 true), i32 %evl) ret %v } @@ -1344,9 +1174,7 @@ define @vsll_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsll.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1370,9 +1198,7 @@ define @vsll_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1382,9 +1208,7 @@ define @vsll_vi_nxv16i32( %va, poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i32( %va, splat (i32 3), %m, i32 %evl) ret %v } @@ -1394,11 +1218,7 @@ define @vsll_vi_nxv16i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv16i32( %va, splat (i32 3), splat (i1 true), i32 %evl) ret %v } @@ -1420,9 +1240,7 @@ define @vsll_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1458,9 +1276,7 @@ define @vsll_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1470,9 +1286,7 @@ define @vsll_vi_nxv1i64( %va, poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i64( %va, splat (i64 3), %m, i32 %evl) ret %v } @@ -1482,11 +1296,7 @@ define @vsll_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv1i64( %va, splat (i64 3), splat (i1 true), i32 %evl) ret %v } @@ -1508,9 +1318,7 @@ define @vsll_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1546,9 +1354,7 @@ define @vsll_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1558,9 +1364,7 @@ define @vsll_vi_nxv2i64( %va, poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i64( %va, splat (i64 3), %m, i32 %evl) ret %v } @@ -1570,11 +1374,7 @@ define @vsll_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv2i64( %va, splat (i64 3), splat (i1 true), i32 %evl) ret %v } @@ -1596,9 +1396,7 @@ define @vsll_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1634,9 +1432,7 @@ define @vsll_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1646,9 +1442,7 @@ define @vsll_vi_nxv4i64( %va, poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i64( %va, splat (i64 3), %m, i32 %evl) ret %v } @@ -1658,11 +1452,7 @@ define @vsll_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv4i64( %va, splat (i64 3), splat (i1 true), i32 %evl) ret %v } @@ -1684,9 +1474,7 @@ define @vsll_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1722,9 +1510,7 @@ define @vsll_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1734,9 +1520,7 @@ define @vsll_vi_nxv8i64( %va, poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i64( %va, splat (i64 3), %m, i32 %evl) ret %v } @@ -1746,10 +1530,6 @@ define @vsll_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsll.vi v8, v8, 3 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 3, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.shl.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.shl.nxv8i64( %va, splat (i64 3), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll index bb0f26046bdb..707ef8a94432 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll @@ -25,9 +25,7 @@ define @vsplat_zero_nxv8f16() { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, half zeroinitializer, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (half zeroinitializer) } define @vsplat_nxv8f32(float %f) { @@ -47,9 +45,7 @@ define @vsplat_zero_nxv8f32() { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, float zeroinitializer, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (float zeroinitializer) } define @vsplat_nxv8f64(double %f) { @@ -69,9 +65,7 @@ define @vsplat_zero_nxv8f64() { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: ret - %head = insertelement poison, double zeroinitializer, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (double zeroinitializer) } ; Test that we fold this to a vlse with 0 stride. diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll index f462f242f068..09a713a6826c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll @@ -8,9 +8,7 @@ define @vsplat_nxv1i1_0() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 0) } define @vsplat_nxv1i1_1() { @@ -19,9 +17,7 @@ define @vsplat_nxv1i1_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 -1) } define @vsplat_nxv1i1_2(i1 %x) { @@ -58,9 +54,7 @@ define @vsplat_nxv2i1_0() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 0) } define @vsplat_nxv2i1_1() { @@ -69,9 +63,7 @@ define @vsplat_nxv2i1_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 -1) } define @vsplat_nxv2i1_2(i1 %x) { @@ -93,9 +85,7 @@ define @vsplat_nxv4i1_0() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 0) } define @vsplat_nxv4i1_1() { @@ -104,9 +94,7 @@ define @vsplat_nxv4i1_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 -1) } define @vsplat_nxv4i1_2(i1 %x) { @@ -128,9 +116,7 @@ define @vsplat_nxv8i1_0() { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 0) } define @vsplat_nxv8i1_1() { @@ -139,9 +125,7 @@ define @vsplat_nxv8i1_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 -1) } define @vsplat_nxv8i1_2(i1 %x) { @@ -163,9 +147,7 @@ define @vsplat_nxv16i1_0() { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 0) } define @vsplat_nxv16i1_1() { @@ -174,9 +156,7 @@ define @vsplat_nxv16i1_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vmset.m v0 ; CHECK-NEXT: ret - %head = insertelement poison, i1 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i1 -1) } define @vsplat_nxv16i1_2(i1 %x) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll index d428fceb6911..721d6ef26d61 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll @@ -10,9 +10,7 @@ define @vsplat_nxv8i64_1() { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i64 -1) } define @vsplat_nxv8i64_2() { @@ -21,9 +19,7 @@ define @vsplat_nxv8i64_2() { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 4 ; CHECK-NEXT: ret - %head = insertelement poison, i64 4, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i64 4) } define @vsplat_nxv8i64_3() { @@ -33,9 +29,7 @@ define @vsplat_nxv8i64_3() { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 255, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i64 255) } define @vsplat_nxv8i64_4() { @@ -61,9 +55,7 @@ define @vsplat_nxv8i64_4() { ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: ret - %head = insertelement poison, i64 4211079935, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (i64 4211079935) } define @vsplat_nxv8i64_5(i64 %a) { @@ -95,9 +87,7 @@ define @vadd_vx_nxv8i64_6( %v) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, 2 ; CHECK-NEXT: ret - %head = insertelement poison, i64 2, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vret = add %v, %splat + %vret = add %v, splat (i64 2) ret %vret } @@ -107,9 +97,7 @@ define @vadd_vx_nxv8i64_7( %v) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vi v8, v8, -1 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vret = add %v, %splat + %vret = add %v, splat (i64 -1) ret %vret } @@ -120,9 +108,7 @@ define @vadd_vx_nxv8i64_8( %v) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 255, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vret = add %v, %splat + %vret = add %v, splat (i64 255) ret %vret } @@ -142,9 +128,7 @@ define @vadd_vx_nxv8i64_9( %v) { ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret - %head = insertelement poison, i64 2063596287, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vret = add %v, %splat + %vret = add %v, splat (i64 2063596287) ret %vret } @@ -172,9 +156,7 @@ define @vadd_vx_nxv8i64_10( %v) { ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret - %head = insertelement poison, i64 4211079935, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vret = add %v, %splat + %vret = add %v, splat (i64 4211079935) ret %vret } @@ -203,9 +185,7 @@ define @vadd_vx_nxv8i64_11( %v) { ; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64V-NEXT: vadd.vx v8, v8, a0 ; RV64V-NEXT: ret - %head = insertelement poison, i64 8506047231, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vret = add %v, %splat + %vret = add %v, splat (i64 8506047231) ret %vret } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll index 59be018efb85..1047860ec8db 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll @@ -11,9 +11,7 @@ define @vsplat_f16_0p625() { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vfmv.v.f v8, fa5 ; CHECK-NEXT: ret - %head = insertelement poison, half 0.625, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (half 0.625) } define @vsplat_f32_0p75() { @@ -23,9 +21,7 @@ define @vsplat_f32_0p75() { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vfmv.v.f v8, fa5 ; CHECK-NEXT: ret - %head = insertelement poison, float 0.75, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (float 0.75) } define @vsplat_f64_neg1() { @@ -35,7 +31,5 @@ define @vsplat_f64_neg1() { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vfmv.v.f v8, fa5 ; CHECK-NEXT: ret - %head = insertelement poison, double -1.0, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - ret %splat + ret splat (double -1.0) } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll index 738e9cf805b4..7bae84142d8a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll @@ -45,9 +45,7 @@ define @vsra_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -94,9 +92,7 @@ define @vsra_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -143,9 +139,7 @@ define @vsra_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -192,9 +186,7 @@ define @vsra_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -241,9 +233,7 @@ define @vsra_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -275,9 +265,7 @@ define @vsra_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -309,9 +297,7 @@ define @vsra_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i8 6) ret %vc } @@ -358,9 +344,7 @@ define @vsra_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i16 6) ret %vc } @@ -407,9 +391,7 @@ define @vsra_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i16 6) ret %vc } @@ -456,9 +438,7 @@ define @vsra_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i16 6) ret %vc } @@ -505,9 +485,7 @@ define @vsra_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i16 6) ret %vc } @@ -554,9 +532,7 @@ define @vsra_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i16 6) ret %vc } @@ -588,9 +564,7 @@ define @vsra_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i16 6) ret %vc } @@ -622,9 +596,7 @@ define @vsra_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i32 31) ret %vc } @@ -656,9 +628,7 @@ define @vsra_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i32 31) ret %vc } @@ -690,9 +660,7 @@ define @vsra_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i32 31) ret %vc } @@ -724,9 +692,7 @@ define @vsra_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i32 31) ret %vc } @@ -758,9 +724,7 @@ define @vsra_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i32 31) ret %vc } @@ -792,9 +756,7 @@ define @vsra_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 31) ret %vc } @@ -805,9 +767,7 @@ define @vsra_vi_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 32) ret %vc } @@ -839,9 +799,7 @@ define @vsra_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 31) ret %vc } @@ -852,9 +810,7 @@ define @vsra_vi_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 32) ret %vc } @@ -886,9 +842,7 @@ define @vsra_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 31) ret %vc } @@ -899,9 +853,7 @@ define @vsra_vi_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 32) ret %vc } @@ -933,9 +885,7 @@ define @vsra_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 31) ret %vc } @@ -946,9 +896,7 @@ define @vsra_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsra.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = ashr %va, %splat + %vc = ashr %va, splat (i64 32) ret %vc } @@ -982,9 +930,7 @@ define @vsra_vi_mask_nxv8i32( %va, poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 31), zeroinitializer %vc = ashr %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll index 35100d781f05..632c4db5c5bb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll @@ -42,9 +42,7 @@ define @vsra_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -68,9 +66,7 @@ define @vsra_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -80,9 +76,7 @@ define @vsra_vi_nxv1i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -92,11 +86,7 @@ define @vsra_vi_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -118,9 +108,7 @@ define @vsra_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -144,9 +132,7 @@ define @vsra_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -156,9 +142,7 @@ define @vsra_vi_nxv2i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -168,11 +152,7 @@ define @vsra_vi_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -194,9 +174,7 @@ define @vsra_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -220,9 +198,7 @@ define @vsra_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -232,9 +208,7 @@ define @vsra_vi_nxv4i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -244,11 +218,7 @@ define @vsra_vi_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -270,9 +240,7 @@ define @vsra_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -296,9 +264,7 @@ define @vsra_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -308,9 +274,7 @@ define @vsra_vi_nxv8i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -320,11 +284,7 @@ define @vsra_vi_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -346,9 +306,7 @@ define @vsra_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -372,9 +330,7 @@ define @vsra_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -384,9 +340,7 @@ define @vsra_vi_nxv16i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -396,11 +350,7 @@ define @vsra_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -422,9 +372,7 @@ define @vsra_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -448,9 +396,7 @@ define @vsra_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -460,9 +406,7 @@ define @vsra_vi_nxv32i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -472,11 +416,7 @@ define @vsra_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -498,9 +438,7 @@ define @vsra_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -524,9 +462,7 @@ define @vsra_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -536,9 +472,7 @@ define @vsra_vi_nxv64i8( %va, poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv64i8( %va, splat (i8 5), %m, i32 %evl) ret %v } @@ -548,11 +482,7 @@ define @vsra_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv64i8( %va, splat (i8 5), splat (i1 true), i32 %evl) ret %v } @@ -574,9 +504,7 @@ define @vsra_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -600,9 +528,7 @@ define @vsra_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -612,9 +538,7 @@ define @vsra_vi_nxv1i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -624,11 +548,7 @@ define @vsra_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -650,9 +570,7 @@ define @vsra_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -676,9 +594,7 @@ define @vsra_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -688,9 +604,7 @@ define @vsra_vi_nxv2i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -700,11 +614,7 @@ define @vsra_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -726,9 +636,7 @@ define @vsra_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -752,9 +660,7 @@ define @vsra_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -764,9 +670,7 @@ define @vsra_vi_nxv4i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -776,11 +680,7 @@ define @vsra_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -802,9 +702,7 @@ define @vsra_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -828,9 +726,7 @@ define @vsra_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -840,9 +736,7 @@ define @vsra_vi_nxv8i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -852,11 +746,7 @@ define @vsra_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -878,9 +768,7 @@ define @vsra_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -904,9 +792,7 @@ define @vsra_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -916,9 +802,7 @@ define @vsra_vi_nxv16i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -928,11 +812,7 @@ define @vsra_vi_nxv16i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -954,9 +834,7 @@ define @vsra_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -980,9 +858,7 @@ define @vsra_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -992,9 +868,7 @@ define @vsra_vi_nxv32i16( %va, poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i16( %va, splat (i16 5), %m, i32 %evl) ret %v } @@ -1004,11 +878,7 @@ define @vsra_vi_nxv32i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv32i16( %va, splat (i16 5), splat (i1 true), i32 %evl) ret %v } @@ -1030,9 +900,7 @@ define @vsra_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1056,9 +924,7 @@ define @vsra_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1068,9 +934,7 @@ define @vsra_vi_nxv1i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1080,11 +944,7 @@ define @vsra_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1106,9 +966,7 @@ define @vsra_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1132,9 +990,7 @@ define @vsra_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1144,9 +1000,7 @@ define @vsra_vi_nxv2i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1156,11 +1010,7 @@ define @vsra_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1182,9 +1032,7 @@ define @vsra_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1208,9 +1056,7 @@ define @vsra_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1220,9 +1066,7 @@ define @vsra_vi_nxv4i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1232,11 +1076,7 @@ define @vsra_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1258,9 +1098,7 @@ define @vsra_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1284,9 +1122,7 @@ define @vsra_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1296,9 +1132,7 @@ define @vsra_vi_nxv8i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1308,11 +1142,7 @@ define @vsra_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1334,9 +1164,7 @@ define @vsra_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsra.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1360,9 +1188,7 @@ define @vsra_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1372,9 +1198,7 @@ define @vsra_vi_nxv16i32( %va, poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i32( %va, splat (i32 5), %m, i32 %evl) ret %v } @@ -1384,11 +1208,7 @@ define @vsra_vi_nxv16i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv16i32( %va, splat (i32 5), splat (i1 true), i32 %evl) ret %v } @@ -1410,9 +1230,7 @@ define @vsra_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1448,9 +1266,7 @@ define @vsra_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1460,9 +1276,7 @@ define @vsra_vi_nxv1i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1472,11 +1286,7 @@ define @vsra_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv1i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } @@ -1498,9 +1308,7 @@ define @vsra_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1536,9 +1344,7 @@ define @vsra_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1548,9 +1354,7 @@ define @vsra_vi_nxv2i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1560,11 +1364,7 @@ define @vsra_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv2i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } @@ -1586,9 +1386,7 @@ define @vsra_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1624,9 +1422,7 @@ define @vsra_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1636,9 +1432,7 @@ define @vsra_vi_nxv4i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1648,11 +1442,7 @@ define @vsra_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv4i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } @@ -1686,9 +1476,7 @@ define @vsra_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1724,9 +1512,7 @@ define @vsra_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1736,9 +1522,7 @@ define @vsra_vi_nxv8i64( %va, poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i64( %va, splat (i64 5), %m, i32 %evl) ret %v } @@ -1748,10 +1532,6 @@ define @vsra_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsra.vi v8, v8, 5 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 5, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ashr.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ashr.nxv8i64( %va, splat (i64 5), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll index be70b20181b1..6f4538926bef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll @@ -20,9 +20,7 @@ define @vsrl_vx_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -44,9 +42,7 @@ define @vsrl_vx_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -68,9 +64,7 @@ define @vsrl_vx_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -92,9 +86,7 @@ define @vsrl_vx_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -116,9 +108,7 @@ define @vsrl_vx_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -140,9 +130,7 @@ define @vsrl_vx_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -164,9 +152,7 @@ define @vsrl_vx_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i8 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i8 6) ret %vc } @@ -188,9 +174,7 @@ define @vsrl_vx_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i16 6) ret %vc } @@ -212,9 +196,7 @@ define @vsrl_vx_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i16 6) ret %vc } @@ -236,9 +218,7 @@ define @vsrl_vx_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i16 6) ret %vc } @@ -260,9 +240,7 @@ define @vsrl_vx_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i16 6) ret %vc } @@ -284,9 +262,7 @@ define @vsrl_vx_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i16 6) ret %vc } @@ -308,9 +284,7 @@ define @vsrl_vx_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 6 ; CHECK-NEXT: ret - %head = insertelement poison, i16 6, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i16 6) ret %vc } @@ -332,9 +306,7 @@ define @vsrl_vx_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i32 31) ret %vc } @@ -356,9 +328,7 @@ define @vsrl_vx_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i32 31) ret %vc } @@ -380,9 +350,7 @@ define @vsrl_vx_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i32 31) ret %vc } @@ -404,9 +372,7 @@ define @vsrl_vx_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i32 31) ret %vc } @@ -428,9 +394,7 @@ define @vsrl_vx_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i32 31) ret %vc } @@ -452,9 +416,7 @@ define @vsrl_vx_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 31) ret %vc } @@ -465,9 +427,7 @@ define @vsrl_vx_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 32) ret %vc } @@ -489,9 +449,7 @@ define @vsrl_vx_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 31) ret %vc } @@ -502,9 +460,7 @@ define @vsrl_vx_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 32) ret %vc } @@ -526,9 +482,7 @@ define @vsrl_vx_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 31) ret %vc } @@ -539,9 +493,7 @@ define @vsrl_vx_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 32) ret %vc } @@ -563,9 +515,7 @@ define @vsrl_vx_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 31 ; CHECK-NEXT: ret - %head = insertelement poison, i64 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 31) ret %vc } @@ -576,9 +526,7 @@ define @vsrl_vx_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 32, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = lshr %va, %splat + %vc = lshr %va, splat (i64 32) ret %vc } @@ -612,9 +560,7 @@ define @vsrl_vi_mask_nxv8i32( %va, poison, i32 31, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 31), zeroinitializer %vc = lshr %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll index 01d1f14da252..ec5b7f3faf7c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll @@ -41,9 +41,7 @@ define @vsrl_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -67,9 +65,7 @@ define @vsrl_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -79,9 +75,7 @@ define @vsrl_vi_nxv1i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -91,11 +85,7 @@ define @vsrl_vi_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -117,9 +107,7 @@ define @vsrl_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -143,9 +131,7 @@ define @vsrl_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -155,9 +141,7 @@ define @vsrl_vi_nxv2i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -167,11 +151,7 @@ define @vsrl_vi_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -193,9 +173,7 @@ define @vsrl_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -219,9 +197,7 @@ define @vsrl_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -231,9 +207,7 @@ define @vsrl_vi_nxv4i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -243,11 +217,7 @@ define @vsrl_vi_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -269,9 +239,7 @@ define @vsrl_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -295,9 +263,7 @@ define @vsrl_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -307,9 +273,7 @@ define @vsrl_vi_nxv8i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -319,11 +283,7 @@ define @vsrl_vi_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -345,9 +305,7 @@ define @vsrl_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -371,9 +329,7 @@ define @vsrl_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -383,9 +339,7 @@ define @vsrl_vi_nxv16i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -395,11 +349,7 @@ define @vsrl_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -421,9 +371,7 @@ define @vsrl_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -447,9 +395,7 @@ define @vsrl_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -459,9 +405,7 @@ define @vsrl_vi_nxv32i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -471,11 +415,7 @@ define @vsrl_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -497,9 +437,7 @@ define @vsrl_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -523,9 +461,7 @@ define @vsrl_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -535,9 +471,7 @@ define @vsrl_vi_nxv64i8( %va, poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv64i8( %va, splat (i8 4), %m, i32 %evl) ret %v } @@ -547,11 +481,7 @@ define @vsrl_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv64i8( %va, splat (i8 4), splat (i1 true), i32 %evl) ret %v } @@ -573,9 +503,7 @@ define @vsrl_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -599,9 +527,7 @@ define @vsrl_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -611,9 +537,7 @@ define @vsrl_vi_nxv1i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -623,11 +547,7 @@ define @vsrl_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -649,9 +569,7 @@ define @vsrl_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -675,9 +593,7 @@ define @vsrl_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -687,9 +603,7 @@ define @vsrl_vi_nxv2i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -699,11 +613,7 @@ define @vsrl_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -725,9 +635,7 @@ define @vsrl_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -751,9 +659,7 @@ define @vsrl_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -763,9 +669,7 @@ define @vsrl_vi_nxv4i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -775,11 +679,7 @@ define @vsrl_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -801,9 +701,7 @@ define @vsrl_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -827,9 +725,7 @@ define @vsrl_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -839,9 +735,7 @@ define @vsrl_vi_nxv8i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -851,11 +745,7 @@ define @vsrl_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -877,9 +767,7 @@ define @vsrl_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -903,9 +791,7 @@ define @vsrl_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -915,9 +801,7 @@ define @vsrl_vi_nxv16i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -927,11 +811,7 @@ define @vsrl_vi_nxv16i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -953,9 +833,7 @@ define @vsrl_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -979,9 +857,7 @@ define @vsrl_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -991,9 +867,7 @@ define @vsrl_vi_nxv32i16( %va, poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i16( %va, splat (i16 4), %m, i32 %evl) ret %v } @@ -1003,11 +877,7 @@ define @vsrl_vi_nxv32i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv32i16( %va, splat (i16 4), splat (i1 true), i32 %evl) ret %v } @@ -1029,9 +899,7 @@ define @vsrl_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1055,9 +923,7 @@ define @vsrl_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1067,9 +933,7 @@ define @vsrl_vi_nxv1i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1079,11 +943,7 @@ define @vsrl_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1105,9 +965,7 @@ define @vsrl_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1131,9 +989,7 @@ define @vsrl_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1143,9 +999,7 @@ define @vsrl_vi_nxv2i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1155,11 +1009,7 @@ define @vsrl_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1181,9 +1031,7 @@ define @vsrl_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1207,9 +1055,7 @@ define @vsrl_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1219,9 +1065,7 @@ define @vsrl_vi_nxv4i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1231,11 +1075,7 @@ define @vsrl_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1257,9 +1097,7 @@ define @vsrl_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1283,9 +1121,7 @@ define @vsrl_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1295,9 +1131,7 @@ define @vsrl_vi_nxv8i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1307,11 +1141,7 @@ define @vsrl_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1333,9 +1163,7 @@ define @vsrl_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsrl.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1359,9 +1187,7 @@ define @vsrl_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1371,9 +1197,7 @@ define @vsrl_vi_nxv16i32( %va, poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i32( %va, splat (i32 4), %m, i32 %evl) ret %v } @@ -1383,11 +1207,7 @@ define @vsrl_vi_nxv16i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv16i32( %va, splat (i32 4), splat (i1 true), i32 %evl) ret %v } @@ -1409,9 +1229,7 @@ define @vsrl_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1447,9 +1265,7 @@ define @vsrl_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1459,9 +1275,7 @@ define @vsrl_vi_nxv1i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1471,11 +1285,7 @@ define @vsrl_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv1i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } @@ -1497,9 +1307,7 @@ define @vsrl_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1535,9 +1343,7 @@ define @vsrl_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1547,9 +1353,7 @@ define @vsrl_vi_nxv2i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1559,11 +1363,7 @@ define @vsrl_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv2i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } @@ -1585,9 +1385,7 @@ define @vsrl_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1623,9 +1421,7 @@ define @vsrl_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1635,9 +1431,7 @@ define @vsrl_vi_nxv4i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1647,11 +1441,7 @@ define @vsrl_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv4i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } @@ -1685,9 +1475,7 @@ define @vsrl_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1723,9 +1511,7 @@ define @vsrl_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1735,9 +1521,7 @@ define @vsrl_vi_nxv8i64( %va, poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i64( %va, splat (i64 4), %m, i32 %evl) ret %v } @@ -1747,10 +1531,6 @@ define @vsrl_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsrl.vi v8, v8, 4 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 4, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.lshr.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.lshr.nxv8i64( %va, splat (i64 4), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll index d3289ba6e068..c043858c0294 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll @@ -35,9 +35,7 @@ define @ssub_nxv1i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv1i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv1i8( %va, splat (i8 1)) ret %v } @@ -72,9 +70,7 @@ define @ssub_nxv2i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv2i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv2i8( %va, splat (i8 1)) ret %v } @@ -109,9 +105,7 @@ define @ssub_nxv4i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv4i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv4i8( %va, splat (i8 1)) ret %v } @@ -146,9 +140,7 @@ define @ssub_nxv8i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv8i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv8i8( %va, splat (i8 1)) ret %v } @@ -183,9 +175,7 @@ define @ssub_nxv16i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv16i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv16i8( %va, splat (i8 1)) ret %v } @@ -220,9 +210,7 @@ define @ssub_nxv32i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv32i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv32i8( %va, splat (i8 1)) ret %v } @@ -257,9 +245,7 @@ define @ssub_nxv64i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv64i8( %va, %vb) + %v = call @llvm.ssub.sat.nxv64i8( %va, splat (i8 1)) ret %v } @@ -294,9 +280,7 @@ define @ssub_nxv1i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv1i16( %va, %vb) + %v = call @llvm.ssub.sat.nxv1i16( %va, splat (i16 1)) ret %v } @@ -331,9 +315,7 @@ define @ssub_nxv2i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv2i16( %va, %vb) + %v = call @llvm.ssub.sat.nxv2i16( %va, splat (i16 1)) ret %v } @@ -368,9 +350,7 @@ define @ssub_nxv4i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv4i16( %va, %vb) + %v = call @llvm.ssub.sat.nxv4i16( %va, splat (i16 1)) ret %v } @@ -405,9 +385,7 @@ define @ssub_nxv8i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv8i16( %va, %vb) + %v = call @llvm.ssub.sat.nxv8i16( %va, splat (i16 1)) ret %v } @@ -442,9 +420,7 @@ define @ssub_nxv16i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv16i16( %va, %vb) + %v = call @llvm.ssub.sat.nxv16i16( %va, splat (i16 1)) ret %v } @@ -479,9 +455,7 @@ define @ssub_nxv32i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv32i16( %va, %vb) + %v = call @llvm.ssub.sat.nxv32i16( %va, splat (i16 1)) ret %v } @@ -516,9 +490,7 @@ define @ssub_nxv1i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv1i32( %va, %vb) + %v = call @llvm.ssub.sat.nxv1i32( %va, splat (i32 1)) ret %v } @@ -553,9 +525,7 @@ define @ssub_nxv2i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv2i32( %va, %vb) + %v = call @llvm.ssub.sat.nxv2i32( %va, splat (i32 1)) ret %v } @@ -590,9 +560,7 @@ define @ssub_nxv4i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv4i32( %va, %vb) + %v = call @llvm.ssub.sat.nxv4i32( %va, splat (i32 1)) ret %v } @@ -627,9 +595,7 @@ define @ssub_nxv8i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv8i32( %va, %vb) + %v = call @llvm.ssub.sat.nxv8i32( %va, splat (i32 1)) ret %v } @@ -664,9 +630,7 @@ define @ssub_nxv16i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv16i32( %va, %vb) + %v = call @llvm.ssub.sat.nxv16i32( %va, splat (i32 1)) ret %v } @@ -714,9 +678,7 @@ define @ssub_nxv1i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv1i64( %va, %vb) + %v = call @llvm.ssub.sat.nxv1i64( %va, splat (i64 1)) ret %v } @@ -764,9 +726,7 @@ define @ssub_nxv2i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv2i64( %va, %vb) + %v = call @llvm.ssub.sat.nxv2i64( %va, splat (i64 1)) ret %v } @@ -814,9 +774,7 @@ define @ssub_nxv4i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv4i64( %va, %vb) + %v = call @llvm.ssub.sat.nxv4i64( %va, splat (i64 1)) ret %v } @@ -864,8 +822,6 @@ define @ssub_nxv8i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.ssub.sat.nxv8i64( %va, %vb) + %v = call @llvm.ssub.sat.nxv8i64( %va, splat (i64 1)) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll index 2d51a2ee44f6..b56a0f40176c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll @@ -43,9 +43,7 @@ define @vssub_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -83,9 +81,7 @@ define @vssub_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -96,9 +92,7 @@ define @vssub_vi_nxv1i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -109,11 +103,7 @@ define @vssub_vi_nxv1i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -135,9 +125,7 @@ define @vssub_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -161,9 +149,7 @@ define @vssub_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -174,9 +160,7 @@ define @vssub_vi_nxv2i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -187,11 +171,7 @@ define @vssub_vi_nxv2i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -213,9 +193,7 @@ define @vssub_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -239,9 +217,7 @@ define @vssub_vx_nxv3i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -252,9 +228,7 @@ define @vssub_vi_nxv3i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv3i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -265,11 +239,7 @@ define @vssub_vi_nxv3i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv3i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -291,9 +261,7 @@ define @vssub_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -317,9 +285,7 @@ define @vssub_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -330,9 +296,7 @@ define @vssub_vi_nxv4i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -343,11 +307,7 @@ define @vssub_vi_nxv4i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -369,9 +329,7 @@ define @vssub_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -395,9 +353,7 @@ define @vssub_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -408,9 +364,7 @@ define @vssub_vi_nxv8i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -421,11 +375,7 @@ define @vssub_vi_nxv8i8_unmasked( %va, i32 ze ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -447,9 +397,7 @@ define @vssub_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -473,9 +421,7 @@ define @vssub_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -486,9 +432,7 @@ define @vssub_vi_nxv16i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -499,11 +443,7 @@ define @vssub_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -525,9 +465,7 @@ define @vssub_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -551,9 +489,7 @@ define @vssub_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -564,9 +500,7 @@ define @vssub_vi_nxv32i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -577,11 +511,7 @@ define @vssub_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -603,9 +533,7 @@ define @vssub_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -629,9 +557,7 @@ define @vssub_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -642,9 +568,7 @@ define @vssub_vi_nxv64i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv64i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -655,11 +579,7 @@ define @vssub_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv64i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -690,9 +610,7 @@ define @vssub_vi_nxv128i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv128i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -715,11 +633,7 @@ define @vssub_vi_nxv128i8_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv128i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -741,9 +655,7 @@ define @vssub_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -767,9 +679,7 @@ define @vssub_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -780,9 +690,7 @@ define @vssub_vi_nxv1i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -793,11 +701,7 @@ define @vssub_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -819,9 +723,7 @@ define @vssub_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -845,9 +747,7 @@ define @vssub_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -858,9 +758,7 @@ define @vssub_vi_nxv2i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -871,11 +769,7 @@ define @vssub_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -897,9 +791,7 @@ define @vssub_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -923,9 +815,7 @@ define @vssub_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -936,9 +826,7 @@ define @vssub_vi_nxv4i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -949,11 +837,7 @@ define @vssub_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -975,9 +859,7 @@ define @vssub_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1001,9 +883,7 @@ define @vssub_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1014,9 +894,7 @@ define @vssub_vi_nxv8i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1027,11 +905,7 @@ define @vssub_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1053,9 +927,7 @@ define @vssub_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1079,9 +951,7 @@ define @vssub_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1092,9 +962,7 @@ define @vssub_vi_nxv16i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1105,11 +973,7 @@ define @vssub_vi_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1131,9 +995,7 @@ define @vssub_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1157,9 +1019,7 @@ define @vssub_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1170,9 +1030,7 @@ define @vssub_vi_nxv32i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1183,11 +1041,7 @@ define @vssub_vi_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1209,9 +1063,7 @@ define @vssub_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1235,9 +1087,7 @@ define @vssub_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1248,9 +1098,7 @@ define @vssub_vi_nxv1i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1261,11 +1109,7 @@ define @vssub_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1287,9 +1131,7 @@ define @vssub_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1313,9 +1155,7 @@ define @vssub_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1326,9 +1166,7 @@ define @vssub_vi_nxv2i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1339,11 +1177,7 @@ define @vssub_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1365,9 +1199,7 @@ define @vssub_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1391,9 +1223,7 @@ define @vssub_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1404,9 +1234,7 @@ define @vssub_vi_nxv4i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1417,11 +1245,7 @@ define @vssub_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1443,9 +1267,7 @@ define @vssub_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1469,9 +1291,7 @@ define @vssub_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1482,9 +1302,7 @@ define @vssub_vi_nxv8i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1495,11 +1313,7 @@ define @vssub_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1521,9 +1335,7 @@ define @vssub_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1547,9 +1359,7 @@ define @vssub_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1560,9 +1370,7 @@ define @vssub_vi_nxv16i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1573,11 +1381,7 @@ define @vssub_vi_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv16i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1609,9 +1413,7 @@ define @vssub_vi_nxv32i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1634,11 +1436,7 @@ define @vssub_vi_nxv32i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv32i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1660,9 +1458,7 @@ define @vssub_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1714,9 +1510,7 @@ define @vssub_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1727,9 +1521,7 @@ define @vssub_vi_nxv1i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1740,11 +1532,7 @@ define @vssub_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv1i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1766,9 +1554,7 @@ define @vssub_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1820,9 +1606,7 @@ define @vssub_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1833,9 +1617,7 @@ define @vssub_vi_nxv2i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1846,11 +1628,7 @@ define @vssub_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv2i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1872,9 +1650,7 @@ define @vssub_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1926,9 +1702,7 @@ define @vssub_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1939,9 +1713,7 @@ define @vssub_vi_nxv4i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1952,11 +1724,7 @@ define @vssub_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv4i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1978,9 +1746,7 @@ define @vssub_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2032,9 +1798,7 @@ define @vssub_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2045,9 +1809,7 @@ define @vssub_vi_nxv8i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2058,10 +1820,6 @@ define @vssub_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssub.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ssub.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.ssub.sat.nxv8i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll index a5b481917cae..5349548a213b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll @@ -35,9 +35,7 @@ define @usub_nxv1i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv1i8( %va, %vb) + %v = call @llvm.usub.sat.nxv1i8( %va, splat (i8 2)) ret %v } @@ -72,9 +70,7 @@ define @usub_nxv2i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv2i8( %va, %vb) + %v = call @llvm.usub.sat.nxv2i8( %va, splat (i8 2)) ret %v } @@ -109,9 +105,7 @@ define @usub_nxv4i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv4i8( %va, %vb) + %v = call @llvm.usub.sat.nxv4i8( %va, splat (i8 2)) ret %v } @@ -146,9 +140,7 @@ define @usub_nxv8i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv8i8( %va, %vb) + %v = call @llvm.usub.sat.nxv8i8( %va, splat (i8 2)) ret %v } @@ -183,9 +175,7 @@ define @usub_nxv16i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv16i8( %va, %vb) + %v = call @llvm.usub.sat.nxv16i8( %va, splat (i8 2)) ret %v } @@ -220,9 +210,7 @@ define @usub_nxv32i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv32i8( %va, %vb) + %v = call @llvm.usub.sat.nxv32i8( %va, splat (i8 2)) ret %v } @@ -257,9 +245,7 @@ define @usub_nxv64i8_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv64i8( %va, %vb) + %v = call @llvm.usub.sat.nxv64i8( %va, splat (i8 2)) ret %v } @@ -294,9 +280,7 @@ define @usub_nxv1i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv1i16( %va, %vb) + %v = call @llvm.usub.sat.nxv1i16( %va, splat (i16 2)) ret %v } @@ -331,9 +315,7 @@ define @usub_nxv2i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv2i16( %va, %vb) + %v = call @llvm.usub.sat.nxv2i16( %va, splat (i16 2)) ret %v } @@ -368,9 +350,7 @@ define @usub_nxv4i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv4i16( %va, %vb) + %v = call @llvm.usub.sat.nxv4i16( %va, splat (i16 2)) ret %v } @@ -405,9 +385,7 @@ define @usub_nxv8i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv8i16( %va, %vb) + %v = call @llvm.usub.sat.nxv8i16( %va, splat (i16 2)) ret %v } @@ -442,9 +420,7 @@ define @usub_nxv16i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv16i16( %va, %vb) + %v = call @llvm.usub.sat.nxv16i16( %va, splat (i16 2)) ret %v } @@ -479,9 +455,7 @@ define @usub_nxv32i16_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv32i16( %va, %vb) + %v = call @llvm.usub.sat.nxv32i16( %va, splat (i16 2)) ret %v } @@ -516,9 +490,7 @@ define @usub_nxv1i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv1i32( %va, %vb) + %v = call @llvm.usub.sat.nxv1i32( %va, splat (i32 2)) ret %v } @@ -553,9 +525,7 @@ define @usub_nxv2i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv2i32( %va, %vb) + %v = call @llvm.usub.sat.nxv2i32( %va, splat (i32 2)) ret %v } @@ -590,9 +560,7 @@ define @usub_nxv4i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv4i32( %va, %vb) + %v = call @llvm.usub.sat.nxv4i32( %va, splat (i32 2)) ret %v } @@ -627,9 +595,7 @@ define @usub_nxv8i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv8i32( %va, %vb) + %v = call @llvm.usub.sat.nxv8i32( %va, splat (i32 2)) ret %v } @@ -664,9 +630,7 @@ define @usub_nxv16i32_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv16i32( %va, %vb) + %v = call @llvm.usub.sat.nxv16i32( %va, splat (i32 2)) ret %v } @@ -714,9 +678,7 @@ define @usub_nxv1i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv1i64( %va, %vb) + %v = call @llvm.usub.sat.nxv1i64( %va, splat (i64 2)) ret %v } @@ -764,9 +726,7 @@ define @usub_nxv2i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv2i64( %va, %vb) + %v = call @llvm.usub.sat.nxv2i64( %va, splat (i64 2)) ret %v } @@ -814,9 +774,7 @@ define @usub_nxv4i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv4i64( %va, %vb) + %v = call @llvm.usub.sat.nxv4i64( %va, splat (i64 2)) ret %v } @@ -864,8 +822,6 @@ define @usub_nxv8i64_vi( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a0 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 2, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.usub.sat.nxv8i64( %va, %vb) + %v = call @llvm.usub.sat.nxv8i64( %va, splat (i64 2)) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll index e5589ce1a9bc..8275c3081c7c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll @@ -41,9 +41,7 @@ define @vssubu_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -81,9 +79,7 @@ define @vssubu_vx_nxv1i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -94,9 +90,7 @@ define @vssubu_vi_nxv1i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -107,11 +101,7 @@ define @vssubu_vi_nxv1i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -133,9 +123,7 @@ define @vssubu_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -159,9 +147,7 @@ define @vssubu_vx_nxv2i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -172,9 +158,7 @@ define @vssubu_vi_nxv2i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -185,11 +169,7 @@ define @vssubu_vi_nxv2i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -211,9 +191,7 @@ define @vssubu_vv_nxv3i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv3i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv3i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -237,9 +215,7 @@ define @vssubu_vx_nxv3i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv3i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -250,9 +226,7 @@ define @vssubu_vi_nxv3i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv3i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -263,11 +237,7 @@ define @vssubu_vi_nxv3i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv3i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv3i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -289,9 +259,7 @@ define @vssubu_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -315,9 +283,7 @@ define @vssubu_vx_nxv4i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -328,9 +294,7 @@ define @vssubu_vi_nxv4i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -341,11 +305,7 @@ define @vssubu_vi_nxv4i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -367,9 +327,7 @@ define @vssubu_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -393,9 +351,7 @@ define @vssubu_vx_nxv8i8_unmasked( %va, i8 %b ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -406,9 +362,7 @@ define @vssubu_vi_nxv8i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -419,11 +373,7 @@ define @vssubu_vi_nxv8i8_unmasked( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -445,9 +395,7 @@ define @vssubu_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -471,9 +419,7 @@ define @vssubu_vx_nxv16i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -484,9 +430,7 @@ define @vssubu_vi_nxv16i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -497,11 +441,7 @@ define @vssubu_vi_nxv16i8_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -523,9 +463,7 @@ define @vssubu_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -549,9 +487,7 @@ define @vssubu_vx_nxv32i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -562,9 +498,7 @@ define @vssubu_vi_nxv32i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -575,11 +509,7 @@ define @vssubu_vi_nxv32i8_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -601,9 +531,7 @@ define @vssubu_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -627,9 +555,7 @@ define @vssubu_vx_nxv64i8_unmasked( %va, i8 ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -640,9 +566,7 @@ define @vssubu_vi_nxv64i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv64i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -653,11 +577,7 @@ define @vssubu_vi_nxv64i8_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv64i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -688,9 +608,7 @@ define @vssubu_vi_nxv128i8( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv128i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -713,11 +631,7 @@ define @vssubu_vi_nxv128i8_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv128i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv128i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -739,9 +653,7 @@ define @vssubu_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -765,9 +677,7 @@ define @vssubu_vx_nxv1i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -778,9 +688,7 @@ define @vssubu_vi_nxv1i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -791,11 +699,7 @@ define @vssubu_vi_nxv1i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -817,9 +721,7 @@ define @vssubu_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -843,9 +745,7 @@ define @vssubu_vx_nxv2i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -856,9 +756,7 @@ define @vssubu_vi_nxv2i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -869,11 +767,7 @@ define @vssubu_vi_nxv2i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -895,9 +789,7 @@ define @vssubu_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -921,9 +813,7 @@ define @vssubu_vx_nxv4i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -934,9 +824,7 @@ define @vssubu_vi_nxv4i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -947,11 +835,7 @@ define @vssubu_vi_nxv4i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -973,9 +857,7 @@ define @vssubu_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -999,9 +881,7 @@ define @vssubu_vx_nxv8i16_unmasked( %va, i1 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1012,9 +892,7 @@ define @vssubu_vi_nxv8i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1025,11 +903,7 @@ define @vssubu_vi_nxv8i16_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1051,9 +925,7 @@ define @vssubu_vv_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1077,9 +949,7 @@ define @vssubu_vx_nxv16i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1090,9 +960,7 @@ define @vssubu_vi_nxv16i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1103,11 +971,7 @@ define @vssubu_vi_nxv16i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1129,9 +993,7 @@ define @vssubu_vv_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1155,9 +1017,7 @@ define @vssubu_vx_nxv32i16_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1168,9 +1028,7 @@ define @vssubu_vi_nxv32i16( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1181,11 +1039,7 @@ define @vssubu_vi_nxv32i16_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1207,9 +1061,7 @@ define @vssubu_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1233,9 +1085,7 @@ define @vssubu_vx_nxv1i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1246,9 +1096,7 @@ define @vssubu_vi_nxv1i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1259,11 +1107,7 @@ define @vssubu_vi_nxv1i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1285,9 +1129,7 @@ define @vssubu_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1311,9 +1153,7 @@ define @vssubu_vx_nxv2i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1324,9 +1164,7 @@ define @vssubu_vi_nxv2i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1337,11 +1175,7 @@ define @vssubu_vi_nxv2i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1363,9 +1197,7 @@ define @vssubu_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1389,9 +1221,7 @@ define @vssubu_vx_nxv4i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1402,9 +1232,7 @@ define @vssubu_vi_nxv4i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1415,11 +1243,7 @@ define @vssubu_vi_nxv4i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1441,9 +1265,7 @@ define @vssubu_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1467,9 +1289,7 @@ define @vssubu_vx_nxv8i32_unmasked( %va, i3 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1480,9 +1300,7 @@ define @vssubu_vi_nxv8i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1493,11 +1311,7 @@ define @vssubu_vi_nxv8i32_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1519,9 +1333,7 @@ define @vssubu_vv_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssubu.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1545,9 +1357,7 @@ define @vssubu_vx_nxv16i32_unmasked( %va, ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1558,9 +1368,7 @@ define @vssubu_vi_nxv16i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1571,11 +1379,7 @@ define @vssubu_vi_nxv16i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv16i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1607,9 +1411,7 @@ define @vssubu_vi_nxv32i32( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1632,11 +1434,7 @@ define @vssubu_vi_nxv32i32_unmasked( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a2 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv32i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv32i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1658,9 +1456,7 @@ define @vssubu_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1712,9 +1508,7 @@ define @vssubu_vx_nxv1i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1725,9 +1519,7 @@ define @vssubu_vi_nxv1i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1738,11 +1530,7 @@ define @vssubu_vi_nxv1i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv1i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1764,9 +1552,7 @@ define @vssubu_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1818,9 +1604,7 @@ define @vssubu_vx_nxv2i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1831,9 +1615,7 @@ define @vssubu_vi_nxv2i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1844,11 +1626,7 @@ define @vssubu_vi_nxv2i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv2i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1870,9 +1648,7 @@ define @vssubu_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1924,9 +1700,7 @@ define @vssubu_vx_nxv4i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1937,9 +1711,7 @@ define @vssubu_vi_nxv4i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -1950,11 +1722,7 @@ define @vssubu_vi_nxv4i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv4i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -1976,9 +1744,7 @@ define @vssubu_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2030,9 +1796,7 @@ define @vssubu_vx_nxv8i64_unmasked( %va, i6 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2043,9 +1807,7 @@ define @vssubu_vi_nxv8i64( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2056,10 +1818,6 @@ define @vssubu_vi_nxv8i64_unmasked( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssubu.vx v8, v8, a1 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.usub.sat.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.usub.sat.nxv8i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll index 5ab028ffc3de..b7f404c8e5ac 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll @@ -31,9 +31,7 @@ define @vsub_vx_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -44,11 +42,7 @@ define @vsub_ii_nxv1i8_1() { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v8, -1 ; CHECK-NEXT: ret - %heada = insertelement poison, i8 2, i32 0 - %splata = shufflevector %heada, poison, zeroinitializer - %headb = insertelement poison, i8 3, i32 0 - %splatb = shufflevector %headb, poison, zeroinitializer - %vc = sub %splata, %splatb + %vc = sub splat (i8 2), splat (i8 3) ret %vc } @@ -81,9 +75,7 @@ define @vsub_vx_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -116,9 +108,7 @@ define @vsub_vx_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -151,9 +141,7 @@ define @vsub_vx_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -186,9 +174,7 @@ define @vsub_vx_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -221,9 +207,7 @@ define @vsub_vx_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -256,9 +240,7 @@ define @vsub_vx_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i8 1) ret %vc } @@ -291,9 +273,7 @@ define @vsub_vx_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i16 1) ret %vc } @@ -326,9 +306,7 @@ define @vsub_vx_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i16 1) ret %vc } @@ -361,9 +339,7 @@ define @vsub_vx_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i16 1) ret %vc } @@ -396,9 +372,7 @@ define @vsub_vx_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i16 1) ret %vc } @@ -431,9 +405,7 @@ define @vsub_vx_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i16 1) ret %vc } @@ -466,9 +438,7 @@ define @vsub_vx_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i16 1) ret %vc } @@ -501,9 +471,7 @@ define @vsub_vx_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i32 1) ret %vc } @@ -536,9 +504,7 @@ define @vsub_vx_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i32 1) ret %vc } @@ -571,9 +537,7 @@ define @vsub_vx_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i32 1) ret %vc } @@ -606,9 +570,7 @@ define @vsub_vx_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i32 1) ret %vc } @@ -641,9 +603,7 @@ define @vsub_vx_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i32 1) ret %vc } @@ -689,9 +649,7 @@ define @vsub_vx_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i64 1) ret %vc } @@ -737,9 +695,7 @@ define @vsub_vx_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i64 1) ret %vc } @@ -785,9 +741,7 @@ define @vsub_vx_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i64 1) ret %vc } @@ -833,9 +787,7 @@ define @vsub_vx_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsub.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = sub %va, %splat + %vc = sub %va, splat (i64 1) ret %vc } @@ -902,9 +854,7 @@ define @vsub_vi_mask_nxv8i32( %va, poison, i32 7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 7), zeroinitializer %vc = sub %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll index f424c6c3aed9..a2b9285fedea 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll @@ -36,9 +36,7 @@ define @vsub_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -62,9 +60,7 @@ define @vsub_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -86,9 +82,7 @@ define @vsub_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -112,9 +106,7 @@ define @vsub_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -136,9 +128,7 @@ define @vsub_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -162,9 +152,7 @@ define @vsub_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -186,9 +174,7 @@ define @vsub_vv_nxv5i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv5i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv5i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -212,9 +198,7 @@ define @vsub_vx_nxv5i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv5i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv5i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -236,9 +220,7 @@ define @vsub_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -262,9 +244,7 @@ define @vsub_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -286,9 +266,7 @@ define @vsub_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -312,9 +290,7 @@ define @vsub_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -336,9 +312,7 @@ define @vsub_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -362,9 +336,7 @@ define @vsub_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -386,9 +358,7 @@ define @vsub_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -412,9 +382,7 @@ define @vsub_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -436,9 +404,7 @@ define @vsub_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -462,9 +428,7 @@ define @vsub_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -486,9 +450,7 @@ define @vsub_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -512,9 +474,7 @@ define @vsub_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -536,9 +496,7 @@ define @vsub_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -562,9 +520,7 @@ define @vsub_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -586,9 +542,7 @@ define @vsub_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -612,9 +566,7 @@ define @vsub_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -636,9 +588,7 @@ define @vsub_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -662,9 +612,7 @@ define @vsub_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -686,9 +634,7 @@ define @vsub_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -712,9 +658,7 @@ define @vsub_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -736,9 +680,7 @@ define @vsub_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -762,9 +704,7 @@ define @vsub_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -786,9 +726,7 @@ define @vsub_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -812,9 +750,7 @@ define @vsub_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -836,9 +772,7 @@ define @vsub_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -862,9 +796,7 @@ define @vsub_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -886,9 +818,7 @@ define @vsub_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -912,9 +842,7 @@ define @vsub_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -936,9 +864,7 @@ define @vsub_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsub.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -962,9 +888,7 @@ define @vsub_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -986,9 +910,7 @@ define @vsub_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1040,9 +962,7 @@ define @vsub_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1064,9 +984,7 @@ define @vsub_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1118,9 +1036,7 @@ define @vsub_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1142,9 +1058,7 @@ define @vsub_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1196,9 +1110,7 @@ define @vsub_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1220,9 +1132,7 @@ define @vsub_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1274,8 +1184,6 @@ define @vsub_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sub.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.sub.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll index 66e6883dd1d3..5dd01c654eff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll @@ -1406,7 +1406,7 @@ define @vwaddu_vv_disjoint_or_add( %x.i8, %x.i8 to - %x.shl = shl %x.i16, shufflevector( insertelement( poison, i16 8, i32 0), poison, zeroinitializer) + %x.shl = shl %x.i16, splat (i16 8) %x.i32 = zext %x.shl to %y.i32 = zext %y.i8 to %add = add %x.i32, %y.i32 diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll index f5cf4acd592c..02bc8d273115 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-vp.ll @@ -17,12 +17,10 @@ define @vwmacc_vv_nxv1i32_unmasked_tu( %a, ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %b, %c, i32 zeroext %evl) { - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.sext.nxv1i32.nxv1i16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, %allones, i32 %evl) - %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, %allones, i32 %evl) - %ret = call @llvm.vp.merge.nxv1i32( %allones, %cadd, %c, i32 %evl) + %aext = call @llvm.vp.sext.nxv1i32.nxv1i16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, splat (i1 -1), i32 %evl) + %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, splat (i1 -1), i32 %evl) + %ret = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %cadd, %c, i32 %evl) ret %ret } diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll index 72ef25ee9c31..486a5b09b677 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-vp.ll @@ -18,13 +18,11 @@ define @vwmacc_vv_nxv1i32_unmasked_tu( %a, ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %b, %c, i32 zeroext %evl) { - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.sext.nxv1i32.nxv1i16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.zext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, %allones, i32 %evl) - %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, %allones, i32 %evl) - %ret = call @llvm.vp.merge.nxv1i32( %allones, %cadd, %c, i32 %evl) + %aext = call @llvm.vp.sext.nxv1i32.nxv1i16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.zext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, splat (i1 -1), i32 %evl) + %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, splat (i1 -1), i32 %evl) + %ret = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %cadd, %c, i32 %evl) ret %ret } @@ -36,12 +34,10 @@ define @vwmacc_vv_nxv1i32_commute_unmasked_tu( %b, %c, i32 zeroext %evl) { - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.zext.nxv1i32.nxv1i16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, %allones, i32 %evl) - %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, %allones, i32 %evl) - %ret = call @llvm.vp.merge.nxv1i32( %allones, %cadd, %c, i32 %evl) + %aext = call @llvm.vp.zext.nxv1i32.nxv1i16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.sext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, splat (i1 -1), i32 %evl) + %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, splat (i1 -1), i32 %evl) + %ret = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %cadd, %c, i32 %evl) ret %ret } diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll index 74dcb92b7cd6..125270be4fc8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-vp.ll @@ -17,12 +17,10 @@ define @vwmacc_vv_nxv1i32_unmasked_tu( %a, ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret %b, %c, i32 zeroext %evl) { - %splat = insertelement poison, i1 -1, i32 0 - %allones = shufflevector %splat, poison, zeroinitializer - %aext = call @llvm.vp.zext.nxv1i32.nxv1i16( %a, %allones, i32 %evl) - %bext = call @llvm.vp.zext.nxv1i32.nxv1i16( %b, %allones, i32 %evl) - %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, %allones, i32 %evl) - %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, %allones, i32 %evl) - %ret = call @llvm.vp.merge.nxv1i32( %allones, %cadd, %c, i32 %evl) + %aext = call @llvm.vp.zext.nxv1i32.nxv1i16( %a, splat (i1 -1), i32 %evl) + %bext = call @llvm.vp.zext.nxv1i32.nxv1i16( %b, splat (i1 -1), i32 %evl) + %abmul = call @llvm.vp.mul.nxv1i32( %aext, %bext, splat (i1 -1), i32 %evl) + %cadd = call @llvm.vp.add.nxv1i32( %abmul, %c, splat (i1 -1), i32 %evl) + %ret = call @llvm.vp.merge.nxv1i32( splat (i1 -1), %cadd, %c, i32 %evl) ret %ret } diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll index e8c4f1fed6ef..3f10b10675ca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll @@ -30,9 +30,7 @@ define @vxor_vi_nxv1i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -42,9 +40,7 @@ define @vxor_vi_nxv1i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -55,9 +51,7 @@ define @vxor_vi_nxv1i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -89,9 +83,7 @@ define @vxor_vi_nxv2i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -101,9 +93,7 @@ define @vxor_vi_nxv2i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -114,9 +104,7 @@ define @vxor_vi_nxv2i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -148,9 +136,7 @@ define @vxor_vi_nxv4i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -160,9 +146,7 @@ define @vxor_vi_nxv4i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -173,9 +157,7 @@ define @vxor_vi_nxv4i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -207,9 +189,7 @@ define @vxor_vi_nxv8i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -219,9 +199,7 @@ define @vxor_vi_nxv8i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -232,9 +210,7 @@ define @vxor_vi_nxv8i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -266,9 +242,7 @@ define @vxor_vi_nxv16i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -278,9 +252,7 @@ define @vxor_vi_nxv16i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -291,9 +263,7 @@ define @vxor_vi_nxv16i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -325,9 +295,7 @@ define @vxor_vi_nxv32i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -337,9 +305,7 @@ define @vxor_vi_nxv32i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -350,9 +316,7 @@ define @vxor_vi_nxv32i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -384,9 +348,7 @@ define @vxor_vi_nxv64i8_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 -1) ret %vc } @@ -396,9 +358,7 @@ define @vxor_vi_nxv64i8_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i8 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 8) ret %vc } @@ -409,9 +369,7 @@ define @vxor_vi_nxv64i8_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i8 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i8 16) ret %vc } @@ -443,9 +401,7 @@ define @vxor_vi_nxv1i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 -1) ret %vc } @@ -455,9 +411,7 @@ define @vxor_vi_nxv1i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 8) ret %vc } @@ -468,9 +422,7 @@ define @vxor_vi_nxv1i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 16) ret %vc } @@ -502,9 +454,7 @@ define @vxor_vi_nxv2i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 -1) ret %vc } @@ -514,9 +464,7 @@ define @vxor_vi_nxv2i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 8) ret %vc } @@ -527,9 +475,7 @@ define @vxor_vi_nxv2i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 16) ret %vc } @@ -561,9 +507,7 @@ define @vxor_vi_nxv4i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 -1) ret %vc } @@ -573,9 +517,7 @@ define @vxor_vi_nxv4i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 8) ret %vc } @@ -586,9 +528,7 @@ define @vxor_vi_nxv4i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 16) ret %vc } @@ -620,9 +560,7 @@ define @vxor_vi_nxv8i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 -1) ret %vc } @@ -632,9 +570,7 @@ define @vxor_vi_nxv8i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 8) ret %vc } @@ -645,9 +581,7 @@ define @vxor_vi_nxv8i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 16) ret %vc } @@ -679,9 +613,7 @@ define @vxor_vi_nxv16i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 -1) ret %vc } @@ -691,9 +623,7 @@ define @vxor_vi_nxv16i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 8) ret %vc } @@ -704,9 +634,7 @@ define @vxor_vi_nxv16i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 16) ret %vc } @@ -738,9 +666,7 @@ define @vxor_vi_nxv32i16_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 -1) ret %vc } @@ -750,9 +676,7 @@ define @vxor_vi_nxv32i16_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i16 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 8) ret %vc } @@ -763,9 +687,7 @@ define @vxor_vi_nxv32i16_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i16 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i16 16) ret %vc } @@ -797,9 +719,7 @@ define @vxor_vi_nxv1i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 -1) ret %vc } @@ -809,9 +729,7 @@ define @vxor_vi_nxv1i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 8) ret %vc } @@ -822,9 +740,7 @@ define @vxor_vi_nxv1i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 16) ret %vc } @@ -856,9 +772,7 @@ define @vxor_vi_nxv2i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 -1) ret %vc } @@ -868,9 +782,7 @@ define @vxor_vi_nxv2i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 8) ret %vc } @@ -881,9 +793,7 @@ define @vxor_vi_nxv2i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 16) ret %vc } @@ -915,9 +825,7 @@ define @vxor_vi_nxv4i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 -1) ret %vc } @@ -927,9 +835,7 @@ define @vxor_vi_nxv4i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 8) ret %vc } @@ -940,9 +846,7 @@ define @vxor_vi_nxv4i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 16) ret %vc } @@ -974,9 +878,7 @@ define @vxor_vi_nxv8i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 -1) ret %vc } @@ -986,9 +888,7 @@ define @vxor_vi_nxv8i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 8) ret %vc } @@ -999,9 +899,7 @@ define @vxor_vi_nxv8i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 16) ret %vc } @@ -1033,9 +931,7 @@ define @vxor_vi_nxv16i32_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 -1) ret %vc } @@ -1045,9 +941,7 @@ define @vxor_vi_nxv16i32_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i32 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 8) ret %vc } @@ -1058,9 +952,7 @@ define @vxor_vi_nxv16i32_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i32 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i32 16) ret %vc } @@ -1105,9 +997,7 @@ define @vxor_vi_nxv1i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 -1) ret %vc } @@ -1117,9 +1007,7 @@ define @vxor_vi_nxv1i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 8) ret %vc } @@ -1130,9 +1018,7 @@ define @vxor_vi_nxv1i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 16) ret %vc } @@ -1177,9 +1063,7 @@ define @vxor_vi_nxv2i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 -1) ret %vc } @@ -1189,9 +1073,7 @@ define @vxor_vi_nxv2i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 8) ret %vc } @@ -1202,9 +1084,7 @@ define @vxor_vi_nxv2i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 16) ret %vc } @@ -1249,9 +1129,7 @@ define @vxor_vi_nxv4i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 -1) ret %vc } @@ -1261,9 +1139,7 @@ define @vxor_vi_nxv4i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 8) ret %vc } @@ -1274,9 +1150,7 @@ define @vxor_vi_nxv4i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 16) ret %vc } @@ -1321,9 +1195,7 @@ define @vxor_vi_nxv8i64_0( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 -1, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 -1) ret %vc } @@ -1333,9 +1205,7 @@ define @vxor_vi_nxv8i64_1( %va) { ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 8 ; CHECK-NEXT: ret - %head = insertelement poison, i64 8, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 8) ret %vc } @@ -1346,9 +1216,7 @@ define @vxor_vi_nxv8i64_2( %va) { ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vxor.vx v8, v8, a0 ; CHECK-NEXT: ret - %head = insertelement poison, i64 16, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vc = xor %va, %splat + %vc = xor %va, splat (i64 16) ret %vc } @@ -1413,9 +1281,7 @@ define @vxor_vi_mask_nxv8i32( %va, poison, i32 7, i32 0 - %splat = shufflevector %head, poison, zeroinitializer - %vs = select %mask, %splat, zeroinitializer + %vs = select %mask, splat (i32 7), zeroinitializer %vc = xor %va, %vs ret %vc } diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll index 96b86ff6179d..f2235b4fdc94 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll @@ -36,9 +36,7 @@ define @vxor_vv_nxv1i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -62,9 +60,7 @@ define @vxor_vx_nxv1i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -74,9 +70,7 @@ define @vxor_vi_nxv1i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -86,11 +80,7 @@ define @vxor_vi_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -100,9 +90,7 @@ define @vxor_vi_nxv1i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -112,11 +100,7 @@ define @vxor_vi_nxv1i8_unmasked_1( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -138,9 +122,7 @@ define @vxor_vv_nxv2i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -164,9 +146,7 @@ define @vxor_vx_nxv2i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -176,9 +156,7 @@ define @vxor_vi_nxv2i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -188,11 +166,7 @@ define @vxor_vi_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -202,9 +176,7 @@ define @vxor_vi_nxv2i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -214,11 +186,7 @@ define @vxor_vi_nxv2i8_unmasked_1( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -240,9 +208,7 @@ define @vxor_vv_nxv4i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -266,9 +232,7 @@ define @vxor_vx_nxv4i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -278,9 +242,7 @@ define @vxor_vi_nxv4i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -290,11 +252,7 @@ define @vxor_vi_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -304,9 +262,7 @@ define @vxor_vi_nxv4i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -316,11 +272,7 @@ define @vxor_vi_nxv4i8_unmasked_1( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -342,9 +294,7 @@ define @vxor_vv_nxv8i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -368,9 +318,7 @@ define @vxor_vx_nxv8i8_unmasked( %va, i8 %b, ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -380,9 +328,7 @@ define @vxor_vi_nxv8i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -392,11 +338,7 @@ define @vxor_vi_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -406,9 +348,7 @@ define @vxor_vi_nxv8i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -418,11 +358,7 @@ define @vxor_vi_nxv8i8_unmasked_1( %va, i32 z ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -444,9 +380,7 @@ define @vxor_vv_nxv15i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv15i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv15i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -470,9 +404,7 @@ define @vxor_vx_nxv15i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv15i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv15i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -482,9 +414,7 @@ define @vxor_vi_nxv15i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv15i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv15i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -494,11 +424,7 @@ define @vxor_vi_nxv15i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv15i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv15i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -508,9 +434,7 @@ define @vxor_vi_nxv15i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv15i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv15i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -520,11 +444,7 @@ define @vxor_vi_nxv15i8_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv15i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv15i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -546,9 +466,7 @@ define @vxor_vv_nxv16i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -572,9 +490,7 @@ define @vxor_vx_nxv16i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -584,9 +500,7 @@ define @vxor_vi_nxv16i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -596,11 +510,7 @@ define @vxor_vi_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -610,9 +520,7 @@ define @vxor_vi_nxv16i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -622,11 +530,7 @@ define @vxor_vi_nxv16i8_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -648,9 +552,7 @@ define @vxor_vv_nxv32i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -674,9 +576,7 @@ define @vxor_vx_nxv32i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -686,9 +586,7 @@ define @vxor_vi_nxv32i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -698,11 +596,7 @@ define @vxor_vi_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -712,9 +606,7 @@ define @vxor_vi_nxv32i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -724,11 +616,7 @@ define @vxor_vi_nxv32i8_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -750,9 +638,7 @@ define @vxor_vv_nxv64i8_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv64i8( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv64i8( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -776,9 +662,7 @@ define @vxor_vx_nxv64i8_unmasked( %va, i8 % ; CHECK-NEXT: ret %elt.head = insertelement poison, i8 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv64i8( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -788,9 +672,7 @@ define @vxor_vi_nxv64i8( %va, poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv64i8( %va, splat (i8 7), %m, i32 %evl) ret %v } @@ -800,11 +682,7 @@ define @vxor_vi_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv64i8( %va, splat (i8 7), splat (i1 true), i32 %evl) ret %v } @@ -814,9 +692,7 @@ define @vxor_vi_nxv64i8_1( %va, poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv64i8( %va, splat (i8 -1), %m, i32 %evl) ret %v } @@ -826,11 +702,7 @@ define @vxor_vi_nxv64i8_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i8 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv64i8( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv64i8( %va, splat (i8 -1), splat (i1 true), i32 %evl) ret %v } @@ -852,9 +724,7 @@ define @vxor_vv_nxv1i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -890,9 +760,7 @@ define @vxor_vx_nxv1i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -902,9 +770,7 @@ define @vxor_vi_nxv1i16( %va, poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i16( %va, splat (i16 7), %m, i32 %evl) ret %v } @@ -914,11 +780,7 @@ define @vxor_vi_nxv1i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i16( %va, splat (i16 7), splat (i1 true), i32 %evl) ret %v } @@ -928,9 +790,7 @@ define @vxor_vi_nxv1i16_1( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -940,11 +800,7 @@ define @vxor_vi_nxv1i16_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -966,9 +822,7 @@ define @vxor_vv_nxv2i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -992,9 +846,7 @@ define @vxor_vx_nxv2i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1004,9 +856,7 @@ define @vxor_vi_nxv2i16( %va, poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i16( %va, splat (i16 7), %m, i32 %evl) ret %v } @@ -1016,11 +866,7 @@ define @vxor_vi_nxv2i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i16( %va, splat (i16 7), splat (i1 true), i32 %evl) ret %v } @@ -1030,9 +876,7 @@ define @vxor_vi_nxv2i16_1( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1042,11 +886,7 @@ define @vxor_vi_nxv2i16_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1068,9 +908,7 @@ define @vxor_vv_nxv4i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1094,9 +932,7 @@ define @vxor_vx_nxv4i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1106,9 +942,7 @@ define @vxor_vi_nxv4i16( %va, poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i16( %va, splat (i16 7), %m, i32 %evl) ret %v } @@ -1118,11 +952,7 @@ define @vxor_vi_nxv4i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i16( %va, splat (i16 7), splat (i1 true), i32 %evl) ret %v } @@ -1132,9 +962,7 @@ define @vxor_vi_nxv4i16_1( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1144,11 +972,7 @@ define @vxor_vi_nxv4i16_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1170,9 +994,7 @@ define @vxor_vv_nxv8i16_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1196,9 +1018,7 @@ define @vxor_vx_nxv8i16_unmasked( %va, i16 ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1208,9 +1028,7 @@ define @vxor_vi_nxv8i16( %va, poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i16( %va, splat (i16 7), %m, i32 %evl) ret %v } @@ -1220,11 +1038,7 @@ define @vxor_vi_nxv8i16_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i16( %va, splat (i16 7), splat (i1 true), i32 %evl) ret %v } @@ -1234,9 +1048,7 @@ define @vxor_vi_nxv8i16_1( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1246,11 +1058,7 @@ define @vxor_vi_nxv8i16_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1272,9 +1080,7 @@ define @vxor_vv_nxv16i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v12 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1298,9 +1104,7 @@ define @vxor_vx_nxv16i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1310,9 +1114,7 @@ define @vxor_vi_nxv16i16( %va, poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i16( %va, splat (i16 7), %m, i32 %evl) ret %v } @@ -1322,11 +1124,7 @@ define @vxor_vi_nxv16i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i16( %va, splat (i16 7), splat (i1 true), i32 %evl) ret %v } @@ -1336,9 +1134,7 @@ define @vxor_vi_nxv16i16_1( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1348,11 +1144,7 @@ define @vxor_vi_nxv16i16_unmasked_1( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1374,9 +1166,7 @@ define @vxor_vv_nxv32i16_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1400,9 +1190,7 @@ define @vxor_vx_nxv32i16_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i16 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i16( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1412,9 +1200,7 @@ define @vxor_vi_nxv32i16( %va, poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i16( %va, splat (i16 7), %m, i32 %evl) ret %v } @@ -1424,11 +1210,7 @@ define @vxor_vi_nxv32i16_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i16( %va, splat (i16 7), splat (i1 true), i32 %evl) ret %v } @@ -1438,9 +1220,7 @@ define @vxor_vi_nxv32i16_1( %va, poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i16( %va, splat (i16 -1), %m, i32 %evl) ret %v } @@ -1450,11 +1230,7 @@ define @vxor_vi_nxv32i16_unmasked_1( %va, ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i16 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv32i16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv32i16( %va, splat (i16 -1), splat (i1 true), i32 %evl) ret %v } @@ -1476,9 +1252,7 @@ define @vxor_vv_nxv1i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1502,9 +1276,7 @@ define @vxor_vx_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1514,9 +1286,7 @@ define @vxor_vi_nxv1i32( %va, poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i32( %va, splat (i32 7), %m, i32 %evl) ret %v } @@ -1526,11 +1296,7 @@ define @vxor_vi_nxv1i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i32( %va, splat (i32 7), splat (i1 true), i32 %evl) ret %v } @@ -1540,9 +1306,7 @@ define @vxor_vi_nxv1i32_1( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1552,11 +1316,7 @@ define @vxor_vi_nxv1i32_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1578,9 +1338,7 @@ define @vxor_vv_nxv2i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1604,9 +1362,7 @@ define @vxor_vx_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1616,9 +1372,7 @@ define @vxor_vi_nxv2i32( %va, poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i32( %va, splat (i32 7), %m, i32 %evl) ret %v } @@ -1628,11 +1382,7 @@ define @vxor_vi_nxv2i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i32( %va, splat (i32 7), splat (i1 true), i32 %evl) ret %v } @@ -1642,9 +1392,7 @@ define @vxor_vi_nxv2i32_1( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1654,11 +1402,7 @@ define @vxor_vi_nxv2i32_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1680,9 +1424,7 @@ define @vxor_vv_nxv4i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1706,9 +1448,7 @@ define @vxor_vx_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1718,9 +1458,7 @@ define @vxor_vi_nxv4i32( %va, poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i32( %va, splat (i32 7), %m, i32 %evl) ret %v } @@ -1730,11 +1468,7 @@ define @vxor_vi_nxv4i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i32( %va, splat (i32 7), splat (i1 true), i32 %evl) ret %v } @@ -1744,9 +1478,7 @@ define @vxor_vi_nxv4i32_1( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1756,11 +1488,7 @@ define @vxor_vi_nxv4i32_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1782,9 +1510,7 @@ define @vxor_vv_nxv8i32_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1808,9 +1534,7 @@ define @vxor_vx_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1820,9 +1544,7 @@ define @vxor_vi_nxv8i32( %va, poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i32( %va, splat (i32 7), %m, i32 %evl) ret %v } @@ -1832,11 +1554,7 @@ define @vxor_vi_nxv8i32_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i32( %va, splat (i32 7), splat (i1 true), i32 %evl) ret %v } @@ -1846,9 +1564,7 @@ define @vxor_vi_nxv8i32_1( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1858,11 +1574,7 @@ define @vxor_vi_nxv8i32_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1884,9 +1596,7 @@ define @vxor_vv_nxv16i32_unmasked( %va, < ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vxor.vv v8, v8, v16 ; CHECK-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i32( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i32( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -1910,9 +1620,7 @@ define @vxor_vx_nxv16i32_unmasked( %va, i ; CHECK-NEXT: ret %elt.head = insertelement poison, i32 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i32( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -1922,9 +1630,7 @@ define @vxor_vi_nxv16i32( %va, poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i32( %va, splat (i32 7), %m, i32 %evl) ret %v } @@ -1934,11 +1640,7 @@ define @vxor_vi_nxv16i32_unmasked( %va, i ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i32( %va, splat (i32 7), splat (i1 true), i32 %evl) ret %v } @@ -1948,9 +1650,7 @@ define @vxor_vi_nxv16i32_1( %va, poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i32( %va, splat (i32 -1), %m, i32 %evl) ret %v } @@ -1960,11 +1660,7 @@ define @vxor_vi_nxv16i32_unmasked_1( %va, ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i32 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv16i32( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv16i32( %va, splat (i32 -1), splat (i1 true), i32 %evl) ret %v } @@ -1986,9 +1682,7 @@ define @vxor_vv_nxv1i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2040,9 +1734,7 @@ define @vxor_vx_nxv1i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2052,9 +1744,7 @@ define @vxor_vi_nxv1i64( %va, poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i64( %va, splat (i64 7), %m, i32 %evl) ret %v } @@ -2064,11 +1754,7 @@ define @vxor_vi_nxv1i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i64( %va, splat (i64 7), splat (i1 true), i32 %evl) ret %v } @@ -2078,9 +1764,7 @@ define @vxor_vi_nxv1i64_1( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2090,11 +1774,7 @@ define @vxor_vi_nxv1i64_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv1i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv1i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -2116,9 +1796,7 @@ define @vxor_vv_nxv2i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2170,9 +1848,7 @@ define @vxor_vx_nxv2i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2182,9 +1858,7 @@ define @vxor_vi_nxv2i64( %va, poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i64( %va, splat (i64 7), %m, i32 %evl) ret %v } @@ -2194,11 +1868,7 @@ define @vxor_vi_nxv2i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i64( %va, splat (i64 7), splat (i1 true), i32 %evl) ret %v } @@ -2208,9 +1878,7 @@ define @vxor_vi_nxv2i64_1( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2220,11 +1888,7 @@ define @vxor_vi_nxv2i64_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv2i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv2i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -2246,9 +1910,7 @@ define @vxor_vv_nxv4i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2300,9 +1962,7 @@ define @vxor_vx_nxv4i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2312,9 +1972,7 @@ define @vxor_vi_nxv4i64( %va, poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i64( %va, splat (i64 7), %m, i32 %evl) ret %v } @@ -2324,11 +1982,7 @@ define @vxor_vi_nxv4i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i64( %va, splat (i64 7), splat (i1 true), i32 %evl) ret %v } @@ -2338,9 +1992,7 @@ define @vxor_vi_nxv4i64_1( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2350,11 +2002,7 @@ define @vxor_vi_nxv4i64_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv4i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv4i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } @@ -2376,9 +2024,7 @@ define @vxor_vv_nxv8i64_unmasked( %va, poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i64( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i64( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -2430,9 +2076,7 @@ define @vxor_vx_nxv8i64_unmasked( %va, i64 ; RV64-NEXT: ret %elt.head = insertelement poison, i64 %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i64( %va, %vb, splat (i1 true), i32 %evl) ret %v } @@ -2442,9 +2086,7 @@ define @vxor_vi_nxv8i64( %va, poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i64( %va, splat (i64 7), %m, i32 %evl) ret %v } @@ -2454,11 +2096,7 @@ define @vxor_vi_nxv8i64_unmasked( %va, i32 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vxor.vi v8, v8, 7 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 7, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i64( %va, splat (i64 7), splat (i1 true), i32 %evl) ret %v } @@ -2468,9 +2106,7 @@ define @vxor_vi_nxv8i64_1( %va, poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i64( %va, splat (i64 -1), %m, i32 %evl) ret %v } @@ -2480,10 +2116,6 @@ define @vxor_vi_nxv8i64_unmasked_1( %va, i3 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vnot.v v8, v8 ; CHECK-NEXT: ret - %elt.head = insertelement poison, i64 -1, i32 0 - %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.xor.nxv8i64( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.xor.nxv8i64( %va, splat (i64 -1), splat (i1 true), i32 %evl) ret %v } -- GitLab From 0f20b9b92f5333a90cf7cd19d7ec2e27ee3eac06 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 9 Apr 2024 16:04:10 +0800 Subject: [PATCH 253/695] [RISCV] Don't require mask or VL to be the same in combineBinOp_VLToVWBinOp_VL (#87997) In NodeExtensionHelper we keep track of the VL and mask of the operand being extended and check that they are the same as the root node's. However for the nodes that we support, none of them have a passthru operand with the exception of RISCV::VMV_V_X_VL, but we check that it's passthru is undef anyway. So it's safe to just discard the extend node's VL and mask and just use the root's instead. (This is the same type of reasoning we use to treat any vmset_vl as an all ones mask) This allows us to match some more cases where we mix VP/non-VP/VL nodes, but these don't seem to appear in practice. The main benefit from this would be to simplify the code. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 54 ++----------------- llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll | 58 +++++++++++++++++++++ 2 files changed, 62 insertions(+), 50 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index b426f1a7b379..c9727a3e5a8d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13552,7 +13552,7 @@ enum ExtKind : uint8_t { ZExt = 1 << 0, SExt = 1 << 1, FPExt = 1 << 2 }; /// NodeExtensionHelper for `a` and one for `b`. /// /// This class abstracts away how the extension is materialized and -/// how its Mask, VL, number of users affect the combines. +/// how its number of users affect the combines. /// /// In particular: /// - VWADD_W is conceptually == add(op0, sext(op1)) @@ -13576,15 +13576,6 @@ struct NodeExtensionHelper { /// This boolean captures whether we care if this operand would still be /// around after the folding happens. bool EnforceOneUse; - /// Records if this operand's mask needs to match the mask of the operation - /// that it will fold into. - bool CheckMask; - /// Value of the Mask for this operand. - /// It may be SDValue(). - SDValue Mask; - /// Value of the vector length operand. - /// It may be SDValue(). - SDValue VL; /// Original value that this NodeExtensionHelper represents. SDValue OrigOperand; @@ -13789,8 +13780,10 @@ struct NodeExtensionHelper { SupportsSExt = false; SupportsFPExt = false; EnforceOneUse = true; - CheckMask = true; unsigned Opc = OrigOperand.getOpcode(); + // For the nodes we handle below, we end up using their inputs directly: see + // getSource(). However since they either don't have a passthru or we check + // that their passthru is undef, we can safely ignore their mask and VL. switch (Opc) { case ISD::ZERO_EXTEND: case ISD::SIGN_EXTEND: { @@ -13806,32 +13799,21 @@ struct NodeExtensionHelper { SupportsZExt = Opc == ISD::ZERO_EXTEND; SupportsSExt = Opc == ISD::SIGN_EXTEND; - - SDLoc DL(Root); - std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget); break; } case RISCVISD::VZEXT_VL: SupportsZExt = true; - Mask = OrigOperand.getOperand(1); - VL = OrigOperand.getOperand(2); break; case RISCVISD::VSEXT_VL: SupportsSExt = true; - Mask = OrigOperand.getOperand(1); - VL = OrigOperand.getOperand(2); break; case RISCVISD::FP_EXTEND_VL: SupportsFPExt = true; - Mask = OrigOperand.getOperand(1); - VL = OrigOperand.getOperand(2); break; case RISCVISD::VMV_V_X_VL: { // Historically, we didn't care about splat values not disappearing during // combines. EnforceOneUse = false; - CheckMask = false; - VL = OrigOperand.getOperand(2); // The operand is a splat of a scalar. @@ -13930,8 +13912,6 @@ struct NodeExtensionHelper { Opc == RISCVISD::VWADD_W_VL || Opc == RISCVISD::VWSUB_W_VL; SupportsFPExt = Opc == RISCVISD::VFWADD_W_VL || Opc == RISCVISD::VFWSUB_W_VL; - std::tie(Mask, VL) = getMaskAndVL(Root, DAG, Subtarget); - CheckMask = true; // There's no existing extension here, so we don't have to worry about // making sure it gets removed. EnforceOneUse = false; @@ -13944,16 +13924,6 @@ struct NodeExtensionHelper { } } - /// Check if this operand is compatible with the given vector length \p VL. - bool isVLCompatible(SDValue VL) const { - return this->VL != SDValue() && this->VL == VL; - } - - /// Check if this operand is compatible with the given \p Mask. - bool isMaskCompatible(SDValue Mask) const { - return !CheckMask || (this->Mask != SDValue() && this->Mask == Mask); - } - /// Helper function to get the Mask and VL from \p Root. static std::pair getMaskAndVL(const SDNode *Root, SelectionDAG &DAG, @@ -13973,13 +13943,6 @@ struct NodeExtensionHelper { } } - /// Check if the Mask and VL of this operand are compatible with \p Root. - bool areVLAndMaskCompatible(SDNode *Root, SelectionDAG &DAG, - const RISCVSubtarget &Subtarget) const { - auto [Mask, VL] = getMaskAndVL(Root, DAG, Subtarget); - return isMaskCompatible(Mask) && isVLCompatible(VL); - } - /// Helper function to check if \p N is commutative with respect to the /// foldings that are supported by this class. static bool isCommutative(const SDNode *N) { @@ -14079,9 +14042,6 @@ canFoldToVWWithSameExtensionImpl(SDNode *Root, const NodeExtensionHelper &LHS, const NodeExtensionHelper &RHS, uint8_t AllowExtMask, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - if (!LHS.areVLAndMaskCompatible(Root, DAG, Subtarget) || - !RHS.areVLAndMaskCompatible(Root, DAG, Subtarget)) - return std::nullopt; if ((AllowExtMask & ExtKind::ZExt) && LHS.SupportsZExt && RHS.SupportsZExt) return CombineResult(NodeExtensionHelper::getZExtOpcode(Root->getOpcode()), Root, LHS, /*LHSExt=*/{ExtKind::ZExt}, RHS, @@ -14120,9 +14080,6 @@ static std::optional canFoldToVW_W(SDNode *Root, const NodeExtensionHelper &LHS, const NodeExtensionHelper &RHS, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - if (!RHS.areVLAndMaskCompatible(Root, DAG, Subtarget)) - return std::nullopt; - if (RHS.SupportsFPExt) return CombineResult( NodeExtensionHelper::getWOpcode(Root->getOpcode(), ExtKind::FPExt), @@ -14190,9 +14147,6 @@ canFoldToVW_SU(SDNode *Root, const NodeExtensionHelper &LHS, if (!LHS.SupportsSExt || !RHS.SupportsZExt) return std::nullopt; - if (!LHS.areVLAndMaskCompatible(Root, DAG, Subtarget) || - !RHS.areVLAndMaskCompatible(Root, DAG, Subtarget)) - return std::nullopt; return CombineResult(NodeExtensionHelper::getSUOpcode(Root->getOpcode()), Root, LHS, /*LHSExt=*/{ExtKind::SExt}, RHS, /*RHSExt=*/{ExtKind::ZExt}); diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll index a0b7726d3cb5..433f5d2717e4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-vp.ll @@ -41,3 +41,61 @@ declare @llvm.vp.sext.nxv2i32.nxv2i8(, @llvm.vp.zext.nxv2i32.nxv2i8(, , i32) declare @llvm.vp.add.nxv2i32(, , , i32) declare @llvm.vp.merge.nxv2i32(, , , i32) + +define @vwadd_vv_vpnxv2i32_vpnxv2i16_vpnxv2i16( %x, %y, %m, i32 signext %evl) { +; CHECK-LABEL: vwadd_vv_vpnxv2i32_vpnxv2i16_vpnxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 32 +; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 +; CHECK-NEXT: ret + %x.sext = call @llvm.vp.sext.nxv2i32.nxv2i16( %x, %m, i32 %evl) + %y.sext = call @llvm.vp.sext.nxv2i32.nxv2i16( %y, %m, i32 %evl) + %add = call @llvm.vp.add.nxv2i32( %x.sext, %y.sext, %m, i32 %evl) + ret %add +} + +define @vwadd_vv_vpnxv2i32_vpnxv2i16_nxv2i16( %x, %y, %m, i32 signext %evl) { +; CHECK-LABEL: vwadd_vv_vpnxv2i32_vpnxv2i16_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 32 +; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 +; CHECK-NEXT: ret + %x.sext = call @llvm.vp.sext.nxv2i32.nxv2i16( %x, %m, i32 %evl) + %y.sext = sext %y to + %add = call @llvm.vp.add.nxv2i32( %x.sext, %y.sext, %m, i32 %evl) + ret %add +} + +define @vwadd_vv_vpnxv2i32_nxv2i16_nxv2i16( %x, %y, %m, i32 signext %evl) { +; CHECK-LABEL: vwadd_vv_vpnxv2i32_nxv2i16_nxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 32 +; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmv1r.v v8, v10 +; CHECK-NEXT: ret + %x.sext = sext %x to + %y.sext = sext %y to + %add = call @llvm.vp.add.nxv2i32( %x.sext, %y.sext, %m, i32 %evl) + ret %add +} + +define @vwadd_vv_nxv2i32_vpnxv2i16_vpnxv2i16( %x, %y, %m, i32 signext %evl) { +; CHECK-LABEL: vwadd_vv_nxv2i32_vpnxv2i16_vpnxv2i16: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9 +; CHECK-NEXT: vmv1r.v v8, v10 +; CHECK-NEXT: ret + %x.sext = call @llvm.vp.sext.nxv2i32.nxv2i16( %x, %m, i32 %evl) + %y.sext = call @llvm.vp.sext.nxv2i32.nxv2i16( %y, %m, i32 %evl) + %add = add %x.sext, %y.sext + ret %add +} -- GitLab From 9c660362c4fb05c0198b9d3ed65b2344706129bd Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 9 Apr 2024 16:10:35 +0800 Subject: [PATCH 254/695] [RISCV] Support vwsll in combineBinOp_VLToVWBinOp_VL (#87620) If the subtarget has +zvbb then we can attempt folding shl and shl_vl to vwsll nodes. There are few test cases where we still don't pick up the vwsll: - For fixed vector vwsll.vi on RV32, see the FIXME for VMV_V_X_VL in fillUpExtensionSupport for support implicit sign extension - For scalable vector vwsll.vi we need to support ISD::SPLAT_VECTOR, see #87249 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 46 +++++++++++--- .../CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll | 61 +++++++++---------- llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll | 33 ++++------ 3 files changed, 77 insertions(+), 63 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index c9727a3e5a8d..80cc41b458ca 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13543,6 +13543,7 @@ enum ExtKind : uint8_t { ZExt = 1 << 0, SExt = 1 << 1, FPExt = 1 << 2 }; /// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w /// sub | sub_vl -> vwsub(u) | vwsub(u)_w /// mul | mul_vl -> vwmul(u) | vwmul_su +/// shl | shl_vl -> vwsll /// fadd -> vfwadd | vfwadd_w /// fsub -> vfwsub | vfwsub_w /// fmul -> vfwmul @@ -13712,6 +13713,9 @@ struct NodeExtensionHelper { case ISD::MUL: case RISCVISD::MUL_VL: return RISCVISD::VWMULU_VL; + case ISD::SHL: + case RISCVISD::SHL_VL: + return RISCVISD::VWSLL_VL; default: llvm_unreachable("Unexpected opcode"); } @@ -13853,7 +13857,8 @@ struct NodeExtensionHelper { } /// Check if \p Root supports any extension folding combines. - static bool isSupportedRoot(const SDNode *Root) { + static bool isSupportedRoot(const SDNode *Root, + const RISCVSubtarget &Subtarget) { switch (Root->getOpcode()) { case ISD::ADD: case ISD::SUB: @@ -13879,6 +13884,11 @@ struct NodeExtensionHelper { case RISCVISD::VFWADD_W_VL: case RISCVISD::VFWSUB_W_VL: return true; + case ISD::SHL: + return Root->getValueType(0).isScalableVector() && + Subtarget.hasStdExtZvbb(); + case RISCVISD::SHL_VL: + return Subtarget.hasStdExtZvbb(); default: return false; } @@ -13887,8 +13897,9 @@ struct NodeExtensionHelper { /// Build a NodeExtensionHelper for \p Root.getOperand(\p OperandIdx). NodeExtensionHelper(SDNode *Root, unsigned OperandIdx, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - assert(isSupportedRoot(Root) && "Trying to build an helper with an " - "unsupported root"); + assert(isSupportedRoot(Root, Subtarget) && + "Trying to build an helper with an " + "unsupported root"); assert(OperandIdx < 2 && "Requesting something else than LHS or RHS"); assert(DAG.getTargetLoweringInfo().isTypeLegal(Root->getValueType(0))); OrigOperand = Root->getOperand(OperandIdx); @@ -13928,12 +13939,13 @@ struct NodeExtensionHelper { static std::pair getMaskAndVL(const SDNode *Root, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { - assert(isSupportedRoot(Root) && "Unexpected root"); + assert(isSupportedRoot(Root, Subtarget) && "Unexpected root"); switch (Root->getOpcode()) { case ISD::ADD: case ISD::SUB: case ISD::MUL: - case ISD::OR: { + case ISD::OR: + case ISD::SHL: { SDLoc DL(Root); MVT VT = Root->getSimpleValueType(0); return getDefaultScalableVLOps(VT, DL, DAG, Subtarget); @@ -13964,6 +13976,8 @@ struct NodeExtensionHelper { case RISCVISD::VWSUBU_W_VL: case RISCVISD::FSUB_VL: case RISCVISD::VFWSUB_W_VL: + case ISD::SHL: + case RISCVISD::SHL_VL: return false; default: llvm_unreachable("Unexpected opcode"); @@ -14017,6 +14031,7 @@ struct CombineResult { case ISD::SUB: case ISD::MUL: case ISD::OR: + case ISD::SHL: Merge = DAG.getUNDEF(Root->getValueType(0)); break; } @@ -14178,6 +14193,11 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) { // mul -> vwmulsu Strategies.push_back(canFoldToVW_SU); break; + case ISD::SHL: + case RISCVISD::SHL_VL: + // shl -> vwsll + Strategies.push_back(canFoldToVWWithZEXT); + break; case RISCVISD::VWADD_W_VL: case RISCVISD::VWSUB_W_VL: // vwadd_w|vwsub_w -> vwadd|vwsub @@ -14205,6 +14225,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) { /// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w /// sub | sub_vl -> vwsub(u) | vwsub(u)_w /// mul | mul_vl -> vwmul(u) | vwmul_su +/// shl | shl_vl -> vwsll /// fadd_vl -> vfwadd | vfwadd_w /// fsub_vl -> vfwsub | vfwsub_w /// fmul_vl -> vfwmul @@ -14219,7 +14240,7 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N, if (DCI.isBeforeLegalize()) return SDValue(); - if (!NodeExtensionHelper::isSupportedRoot(N)) + if (!NodeExtensionHelper::isSupportedRoot(N, Subtarget)) return SDValue(); SmallVector Worklist; @@ -14230,7 +14251,7 @@ static SDValue combineBinOp_VLToVWBinOp_VL(SDNode *N, while (!Worklist.empty()) { SDNode *Root = Worklist.pop_back_val(); - if (!NodeExtensionHelper::isSupportedRoot(Root)) + if (!NodeExtensionHelper::isSupportedRoot(Root, Subtarget)) return SDValue(); NodeExtensionHelper LHS(N, 0, DAG, Subtarget); @@ -16325,9 +16346,12 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, VPSN->getMemOperand(), IndexType); break; } + case RISCVISD::SHL_VL: + if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget)) + return V; + [[fallthrough]]; case RISCVISD::SRA_VL: - case RISCVISD::SRL_VL: - case RISCVISD::SHL_VL: { + case RISCVISD::SRL_VL: { SDValue ShAmt = N->getOperand(1); if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) { // We don't need the upper 32 bits of a 64-bit element for a shift amount. @@ -16347,6 +16371,10 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, [[fallthrough]]; case ISD::SRL: case ISD::SHL: { + if (N->getOpcode() == ISD::SHL) { + if (SDValue V = combineBinOp_VLToVWBinOp_VL(N, DCI, Subtarget)) + return V; + } SDValue ShAmt = N->getOperand(1); if (ShAmt.getOpcode() == RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL) { // We don't need the upper 32 bits of a 64-bit element for a shift amount. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll index 59b3d752cc20..af67b9920ed1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll @@ -111,8 +111,7 @@ define <4 x i64> @vwsll_vx_i32_v4i64_zext(<4 x i32> %a, i32 %b) { ; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_zext: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i32> poison, i32 %b, i32 0 @@ -371,8 +370,7 @@ define <8 x i32> @vwsll_vx_i16_v8i32_zext(<8 x i16> %a, i16 %b) { ; CHECK-ZVBB-LABEL: vwsll_vx_i16_v8i32_zext: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <8 x i16> poison, i16 %b, i32 0 @@ -642,8 +640,7 @@ define <16 x i16> @vwsll_vx_i8_v16i16_zext(<16 x i8> %a, i8 %b) { ; CHECK-ZVBB-LABEL: vwsll_vx_i8_v16i16_zext: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 16, e8, m1, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vwsll.vv v10, v8, v9 +; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: ret %head = insertelement <16 x i8> poison, i8 %b, i32 0 @@ -710,10 +707,10 @@ define <4 x i64> @vwsll_vv_v4i64_v4i8_zext(<4 x i8> %a, <4 x i8> %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vv_v4i64_v4i8_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9 +; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11 ; CHECK-ZVBB-NEXT: ret %x = zext <4 x i8> %a to <4 x i64> %y = zext <4 x i8> %b to <4 x i64> @@ -784,11 +781,8 @@ define <4 x i64> @vwsll_vx_i32_v4i64_v4i8_zext(<4 x i8> %a, i32 %b) { ; CHECK-ZVBB-LABEL: vwsll_vx_i32_v4i64_v4i8_zext: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i32> poison, i32 %b, i32 0 %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer @@ -839,12 +833,9 @@ define <4 x i64> @vwsll_vx_i16_v4i64_v4i8_zext(<4 x i8> %a, i16 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i16_v4i64_v4i8_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i16> poison, i16 %b, i32 0 %splat = shufflevector <4 x i16> %head, <4 x i16> poison, <4 x i32> zeroinitializer @@ -895,12 +886,9 @@ define <4 x i64> @vwsll_vx_i8_v4i64_v4i8_zext(<4 x i8> %a, i8 %b) { ; ; CHECK-ZVBB-LABEL: vwsll_vx_i8_v4i64_v4i8_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 ; CHECK-ZVBB-NEXT: ret %head = insertelement <4 x i8> poison, i8 %b, i32 0 %splat = shufflevector <4 x i8> %head, <4 x i8> poison, <4 x i32> zeroinitializer @@ -918,12 +906,19 @@ define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) { ; CHECK-NEXT: vsll.vi v8, v10, 2 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2 -; CHECK-ZVBB-NEXT: ret +; CHECK-ZVBB-RV32-LABEL: vwsll_vi_v4i64_v4i8: +; CHECK-ZVBB-RV32: # %bb.0: +; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma +; CHECK-ZVBB-RV32-NEXT: vzext.vf8 v10, v8 +; CHECK-ZVBB-RV32-NEXT: vsll.vi v8, v10, 2 +; CHECK-ZVBB-RV32-NEXT: ret +; +; CHECK-ZVBB-RV64-LABEL: vwsll_vi_v4i64_v4i8: +; CHECK-ZVBB-RV64: # %bb.0: +; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-ZVBB-RV64-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-RV64-NEXT: vwsll.vi v8, v10, 2 +; CHECK-ZVBB-RV64-NEXT: ret %x = zext <4 x i8> %a to <4 x i64> %z = shl <4 x i64> %x, splat (i64 2) ret <4 x i64> %z diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll index 082de2e7bf77..72fc9c918f22 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll @@ -665,10 +665,10 @@ define @vwsll_vv_nxv2i64_nxv2i8_zext( %a, %a to %y = zext %b to @@ -739,11 +739,8 @@ define @vwsll_vx_i32_nxv2i64_nxv2i8_zext( %a ; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext: ; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 ; CHECK-ZVBB-NEXT: ret %head = insertelement poison, i32 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -794,12 +791,9 @@ define @vwsll_vx_i16_nxv2i64_nxv2i8_zext( %a ; ; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 ; CHECK-ZVBB-NEXT: ret %head = insertelement poison, i16 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer @@ -850,12 +844,9 @@ define @vwsll_vx_i8_nxv2i64_nxv2i8_zext( %a, ; ; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext: ; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma -; CHECK-ZVBB-NEXT: vmv.v.x v9, a0 -; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9 -; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12 +; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8 +; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0 ; CHECK-ZVBB-NEXT: ret %head = insertelement poison, i8 %b, i32 0 %splat = shufflevector %head, poison, zeroinitializer -- GitLab From 9c58f3a234a5eb24db97290d1abc71f8bf181c3a Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 9 Apr 2024 09:10:45 +0100 Subject: [PATCH 255/695] [AMDGPU] Fix implicit $vcc operands after parsing MIR (#87781) MIParser checks that implicit operands match the instruction definition, so they have to be $vcc even in wave32 mode. Use the mirFileLoaded hook to fix them after MIParser's checks, converting them to $vcc_lo which is what that rest of CodeGen expects. This is all just extending the fixImplicitOperands hack which was introduced with GFX10, but at least it makes it possible to write a MIR test which creates the same instructions that normal CodeGen would generate. --- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 11 ++ llvm/lib/Target/AMDGPU/GCNSubtarget.h | 2 + .../test/CodeGen/AMDGPU/dpp_combine_gfx11.mir | 27 ++-- ...ask-pre-ra-non-empty-but-used-interval.mir | 8 +- ...imize-negated-cond-exec-masking-wave32.mir | 34 ++--- .../AMDGPU/sgpr-spill-overlap-wwm-reserve.mir | 2 +- ...lower-i1-copies-order-of-phi-incomings.mir | 2 +- .../test/CodeGen/AMDGPU/verify-vopd-gfx12.mir | 2 +- llvm/test/CodeGen/AMDGPU/verify-vopd.mir | 2 +- llvm/test/CodeGen/AMDGPU/vopc_dpp.mir | 4 +- llvm/test/CodeGen/AMDGPU/vopd-combine.mir | 129 ++++++++++-------- 11 files changed, 130 insertions(+), 93 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index fa77b94fc22d..8f0eae362eca 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -642,6 +642,17 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, Policy.ShouldTrackLaneMasks = true; } +void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const { + if (isWave32()) { + // Fix implicit $vcc operands after MIParser has verified that they match + // the instruction definitions. + for (auto &MBB : MF) { + for (auto &MI : MBB) + InstrInfo.fixImplicitOperands(MI); + } + } +} + bool GCNSubtarget::hasMadF16() const { return InstrInfo.pseudoToMCOpcode(AMDGPU::V_MAD_F16_e64) != -1; } diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index 4da10beabe31..e24a18a2842f 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -923,6 +923,8 @@ public: void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override; + void mirFileLoaded(MachineFunction &MF) const override; + unsigned getMaxNumUserSGPRs() const { return AMDGPU::getMaxNumUserSGPRs(*this); } diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir index c48231f3851a..29621a047741 100644 --- a/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir @@ -586,7 +586,7 @@ name: dpp_reg_sequence_both_combined tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 @@ -606,12 +606,12 @@ body: | # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec # GCN: %5:vreg_64 = REG_SEQUENCE undef %3:vgpr_32, %subreg.sub0, %4, %subreg.sub1 # GCN: %6:vgpr_32 = V_ADD_U32_dpp %8, %1.sub0, %2, 1, 15, 15, 1, implicit $exec -# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec +# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec name: dpp_reg_sequence_first_combined tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 @@ -636,7 +636,7 @@ name: dpp_reg_sequence_second_combined tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 @@ -656,12 +656,12 @@ body: | # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1 # GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec -# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec +# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec name: dpp_reg_sequence_none_combined tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 @@ -683,12 +683,12 @@ body: | # GCN: S_BRANCH %bb.1 # GCN: bb.1: # GCN: %6:vgpr_32 = V_ADD_U32_e32 %5.sub0, %2, implicit $exec -# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec +# GCN: %7:vgpr_32 = V_ADDC_U32_e32 %5.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec name: dpp_reg_sequence_exec_changed tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 @@ -699,6 +699,7 @@ body: | S_BRANCH %bb.1 bb.1: + liveins: $vcc_lo %6:vgpr_32 = V_ADD_U32_e32 %4.sub0, %5, implicit $exec %7:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %5, implicit-def $vcc, implicit $vcc, implicit $exec ... @@ -712,12 +713,12 @@ body: | # GCN: %5:vreg_64 = REG_SEQUENCE %3, %subreg.sub0, %4, %subreg.sub1 # GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1 # GCN: %7:vgpr_32 = V_ADD_U32_e32 %6.sub0, %2, implicit $exec -# GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc, implicit $vcc, implicit $exec +# GCN: %8:vgpr_32 = V_ADDC_U32_e32 %6.sub1, %2, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec name: dpp_reg_sequence_subreg tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 @@ -782,6 +783,7 @@ name: dpp64_add64_impdef tracksRegLiveness: true body: | bb.0: + liveins: $vcc_lo %0:vreg_64 = IMPLICIT_DEF %1:vreg_64 = IMPLICIT_DEF %2:vreg_64 = V_MOV_B64_DPP_PSEUDO %1:vreg_64, %0:vreg_64, 1, 15, 15, 1, implicit $exec @@ -796,6 +798,7 @@ name: dpp64_add64_undef tracksRegLiveness: true body: | bb.0: + liveins: $vcc_lo %2:vreg_64 = V_MOV_B64_DPP_PSEUDO undef %1:vreg_64, undef %0:vreg_64, 1, 15, 15, 1, implicit $exec %5:vgpr_32 = V_ADD_U32_e32 %2.sub0, undef %4:vgpr_32, implicit $exec %6:vgpr_32 = V_ADDC_U32_e32 %2.sub1, undef %4, implicit-def $vcc, implicit $vcc, implicit $exec @@ -860,12 +863,12 @@ body: | # GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence # GCN: %5:vgpr_32 = V_ADD_U32_e32 %4.sub0, %4.sub0, implicit $exec -# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec +# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc_lo, implicit $vcc_lo, implicit $exec name: dont_combine_more_than_one_operand_dpp_reg_sequence tracksRegLiveness: true body: | bb.0: - liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vcc_lo %0:vreg_64 = COPY $vgpr0_vgpr1 %1:vreg_64 = COPY $vgpr2_vgpr3 %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir index 2e8219f99f1d..9607889c7179 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-non-empty-but-used-interval.mir @@ -39,19 +39,19 @@ body: | S_CMP_EQ_U32 %15, undef %15, implicit-def $scc %19:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed undef $scc %20:sreg_32 = IMPLICIT_DEF - dead $vcc_lo = COPY undef %20 + $vcc_lo = COPY undef %20 S_CBRANCH_VCCNZ %bb.3, implicit $vcc S_BRANCH %bb.3 bb.3: - dead $vcc_lo = S_AND_B32 $exec_lo, undef %19, implicit-def dead $scc + $vcc_lo = S_AND_B32 $exec_lo, undef %19, implicit-def dead $scc S_CBRANCH_VCCNZ %bb.6, implicit $vcc S_BRANCH %bb.4 bb.4: %21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %19, implicit $exec %22:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, undef %21, implicit $exec - dead $vcc_lo = S_AND_B32 $exec_lo, undef %22, implicit-def dead $scc + $vcc_lo = S_AND_B32 $exec_lo, undef %22, implicit-def dead $scc S_CBRANCH_VCCNZ %bb.7, implicit $vcc S_BRANCH %bb.5 @@ -174,7 +174,7 @@ body: | S_BRANCH %bb.20 bb.28: - dead $vcc_lo = S_AND_B32 $exec_lo, %22, implicit-def dead $scc + $vcc_lo = S_AND_B32 $exec_lo, %22, implicit-def dead $scc S_CBRANCH_VCCNZ %bb.29, implicit $vcc S_BRANCH %bb.29 diff --git a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir index e680eb2845f8..116c04dea8b0 100644 --- a/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir +++ b/llvm/test/CodeGen/AMDGPU/optimize-negated-cond-exec-masking-wave32.mir @@ -4,7 +4,7 @@ # GCN: name: negated_cond_vop2 # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop2 body: | @@ -26,7 +26,7 @@ body: | # GCN: name: negated_cond_vop3 # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3 body: | @@ -48,10 +48,10 @@ body: | # GCN: name: negated_cond_vop2_redef_vcc1 # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec -# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec +# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc_lo, implicit $exec # GCN-NEXT: $vcc_lo = COPY $sgpr0 # GCN-NEXT: $vcc_lo = S_AND_B32 $exec_lo, $vcc_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop2_redef_vcc1 body: | @@ -77,7 +77,7 @@ body: | # GCN-NEXT: dead %3:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec # GCN-NEXT: %2:sgpr_32 = COPY $sgpr0 # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_redef_cmp body: | @@ -99,7 +99,7 @@ body: | # GCN: name: negated_cond_undef_vcc # GCN: $vcc_lo = S_AND_B32 $exec_lo, undef $vcc_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_undef_vcc body: | @@ -118,7 +118,7 @@ body: | # GCN: name: negated_cond_vop3_imp_vcc # GCN: $vcc_lo = IMPLICIT_DEF # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_imp_vcc body: | @@ -140,7 +140,7 @@ body: | # GCN: name: negated_cond_vop2_imp_vcc # GCN: $vcc_lo = IMPLICIT_DEF # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, $vcc_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop2_imp_vcc body: | @@ -165,7 +165,7 @@ body: | # GCN-NEXT: %1:vgpr_32 = COPY $vgpr0 # GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1, 1, implicit $exec # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_redef_sel body: | @@ -189,7 +189,7 @@ body: | # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop2_used_sel body: | @@ -212,10 +212,10 @@ body: | # GCN: name: negated_cond_vop2_used_vcc # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec -# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec +# GCN-NEXT: V_CMP_NE_U32_e32 1, %1, implicit-def $vcc_lo, implicit $exec # GCN-NEXT: $sgpr0_sgpr1 = COPY $vcc # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop2_used_vcc body: | @@ -241,7 +241,7 @@ body: | # GCN-NEXT: %1.sub0:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec # GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_sel_wrong_subreg1 body: | @@ -267,7 +267,7 @@ body: | # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub1, 1, implicit $exec # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_sel_wrong_subreg2 body: | @@ -291,7 +291,7 @@ body: | # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_sel_right_subreg1 body: | @@ -315,7 +315,7 @@ body: | # GCN: %0:sgpr_32 = IMPLICIT_DEF # GCN-NEXT: %1.sub1:vreg_64 = IMPLICIT_DEF # GCN-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, %0, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_sel_right_subreg2 body: | @@ -341,7 +341,7 @@ body: | # GCN-NEXT: %1.sub2_sub3:vreg_128 = IMPLICIT_DEF # GCN-NEXT: %2:sgpr_32 = V_CMP_NE_U32_e64 %1.sub2, 1, implicit $exec # GCN-NEXT: $vcc_lo = S_AND_B32 %2, $exec_lo, implicit-def dead $scc -# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc +# GCN-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc_lo --- name: negated_cond_vop3_sel_subreg_overlap body: | diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir index 6a2532147f88..f8e7cb397b47 100644 --- a/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir @@ -118,7 +118,7 @@ body: | ; GCN-NEXT: successors: %bb.2(0x80000000) ; GCN-NEXT: liveins: $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GCN-NEXT: {{ $}} - ; GCN-NEXT: KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99_sgpr100_sgpr101_sgpr102_sgpr103 + ; GCN-NEXT: KILL implicit-def $vcc_lo, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit-def $sgpr32_sgpr33_sgpr34_sgpr35_sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51_sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59_sgpr60_sgpr61_sgpr62_sgpr63, implicit-def $sgpr64_sgpr65_sgpr66_sgpr67_sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75_sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83_sgpr84_sgpr85_sgpr86_sgpr87_sgpr88_sgpr89_sgpr90_sgpr91_sgpr92_sgpr93_sgpr94_sgpr95, implicit-def $sgpr96_sgpr97_sgpr98_sgpr99_sgpr100_sgpr101_sgpr102_sgpr103 ; GCN-NEXT: {{ $}} ; GCN-NEXT: bb.2: ; GCN-NEXT: successors: %bb.3(0x80000000) diff --git a/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir b/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir index 695beab8dd24..ecbd47a9e8d0 100644 --- a/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir +++ b/llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir @@ -68,7 +68,7 @@ body: | ; GCN-NEXT: [[PHI4:%[0-9]+]]:sreg_32 = PHI [[S_OR_B32_]], %bb.1, [[S_OR_B32_1]], %bb.2 ; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec ; GCN-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 4 - ; GCN-NEXT: [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[PHI3]], killed [[S_MOV_B64_]], implicit-def dead $vcc, implicit $exec + ; GCN-NEXT: [[V_ADD_U:%[0-9]+]]:vreg_64 = V_ADD_U64_PSEUDO [[PHI3]], killed [[S_MOV_B64_]], implicit-def dead $vcc_lo, implicit $exec ; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 1 ; GCN-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = nsw S_ADD_I32 [[PHI2]], killed [[S_MOV_B32_3]], implicit-def dead $scc ; GCN-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sreg_32 = S_MOV_B32 9 diff --git a/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir b/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir index 39822d8754f6..6614d8f9c4b0 100644 --- a/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir +++ b/llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir @@ -1,7 +1,7 @@ # RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s # GFX12-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction *** -# GFX12-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo +# GFX12-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc_lo, implicit $vcc_lo --- name: vopd_cndmask_2sgpr body: | diff --git a/llvm/test/CodeGen/AMDGPU/verify-vopd.mir b/llvm/test/CodeGen/AMDGPU/verify-vopd.mir index 9bcc766466af..374f89895719 100644 --- a/llvm/test/CodeGen/AMDGPU/verify-vopd.mir +++ b/llvm/test/CodeGen/AMDGPU/verify-vopd.mir @@ -1,7 +1,7 @@ # RUN: not --crash llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -check-prefix=GFX11-ERR %s # GFX11-ERR: *** Bad machine code: VOP* instruction violates constant bus restriction *** -# GFX11-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc, implicit $vcc_lo +# GFX11-ERR: $vgpr2, $vgpr3 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $sgpr0, $vgpr0, $sgpr1, $vgpr1, implicit $exec, implicit $mode, implicit $vcc_lo, implicit $vcc_lo --- name: vopd_cndmask_2sgpr body: | diff --git a/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir b/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir index feba06789f7f..123893674ff5 100644 --- a/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir +++ b/llvm/test/CodeGen/AMDGPU/vopc_dpp.mir @@ -18,7 +18,7 @@ body: | ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: V_CMP_LT_F32_e32_dpp 0, [[COPY1]], 0, [[COPY]], 1, 15, 15, 1, implicit-def $vcc, implicit $mode, implicit $exec ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec - ; GCN-NEXT: V_CMPX_EQ_I16_t16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc, implicit $mode, implicit $exec + ; GCN-NEXT: V_CMPX_EQ_I16_t16_nosdst_e64 [[V_MOV_B32_dpp]], [[COPY]], implicit-def $exec, implicit-def $vcc_lo, implicit $mode, implicit $exec ; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64_dpp 0, [[COPY1]], [[COPY]], 1, 15, 15, 1, implicit $exec ; GCN-NEXT: [[V_CMP_GE_F16_t16_e64_dpp:%[0-9]+]]:sgpr_32 = V_CMP_GE_F16_t16_e64_dpp 1, [[COPY1]], 0, [[COPY]], 1, 1, 15, 15, 1, implicit $mode, implicit $exec ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 15, 1, implicit $exec @@ -89,7 +89,7 @@ body: | ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[COPY1]], 1, 15, 14, 1, implicit $exec - ; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, [[V_MOV_B32_dpp]], [[COPY]], implicit-def $vcc, implicit $mode, implicit $exec + ; GCN-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sgpr_32 = V_CMP_CLASS_F16_t16_e64 0, [[V_MOV_B32_dpp]], [[COPY]], implicit-def $vcc_lo, implicit $mode, implicit $exec ; GCN-NEXT: [[V_MOV_B32_dpp1:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[V_MOV_B32_e32_]], [[COPY1]], 1, 13, 15, 1, implicit $exec ; GCN-NEXT: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sgpr_32 = V_CMP_GE_F32_e64 1, [[V_MOV_B32_dpp1]], 0, [[COPY]], 1, implicit $mode, implicit $exec %0:vgpr_32 = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/vopd-combine.mir b/llvm/test/CodeGen/AMDGPU/vopd-combine.mir index 3c1da043bcd6..63bef40c3474 100644 --- a/llvm/test/CodeGen/AMDGPU/vopd-combine.mir +++ b/llvm/test/CodeGen/AMDGPU/vopd-combine.mir @@ -135,42 +135,49 @@ name: vopd_cndmask tracksRegLiveness: true body: | bb.0: + liveins: $vcc_lo ; SCHED-LABEL: name: vopd_cndmask - ; SCHED: $vgpr2 = IMPLICIT_DEF + ; SCHED: liveins: $vcc_lo + ; SCHED-NEXT: {{ $}} + ; SCHED-NEXT: $vgpr2 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr0 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr1 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF ; SCHED-NEXT: $sgpr20 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 $sgpr20, killed $vgpr1, killed $vgpr2, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc - ; SCHED-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr5 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo + ; SCHED-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo ; ; PAIR-GFX11-LABEL: name: vopd_cndmask - ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF + ; PAIR-GFX11: liveins: $vcc_lo + ; PAIR-GFX11-NEXT: {{ $}} + ; PAIR-GFX11-NEXT: $vgpr2 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $sgpr20 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX11-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX11-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx11 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX11-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; PAIR-GFX11-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX11-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo ; ; PAIR-GFX12-LABEL: name: vopd_cndmask - ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF + ; PAIR-GFX12: liveins: $vcc_lo + ; PAIR-GFX12-NEXT: {{ $}} + ; PAIR-GFX12-NEXT: $vgpr2 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $sgpr20 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr4 = V_FMAMK_F32 $sgpr20, 12345, $vgpr3, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx12 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX12-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX12-NEXT: $vgpr2, $vgpr5 = V_DUAL_FMAC_F32_e32_X_CNDMASK_B32_e32_gfx12 $sgpr20, killed $vgpr1, killed $vgpr2, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX12-NEXT: $vgpr7 = V_CNDMASK_B32_e32 killed $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; PAIR-GFX12-NEXT: $vgpr6 = V_ADD_F32_e32 $sgpr20, $vgpr3, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX12-NEXT: $vgpr9 = V_CNDMASK_B32_e32 killed $sgpr20, killed $vgpr3, implicit $mode, implicit $exec, implicit killed $vcc_lo $vgpr0 = IMPLICIT_DEF $vgpr1 = IMPLICIT_DEF $vgpr2 = IMPLICIT_DEF @@ -417,9 +424,12 @@ name: vopd_schedule_unconstrained tracksRegLiveness: true body: | bb.0: + liveins: $vcc_lo ; SCHED-LABEL: name: vopd_schedule_unconstrained - ; SCHED: $vgpr2 = IMPLICIT_DEF + ; SCHED: liveins: $vcc_lo + ; SCHED-NEXT: {{ $}} + ; SCHED-NEXT: $vgpr2 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr0 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr1 = IMPLICIT_DEF @@ -429,16 +439,18 @@ body: | ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc - ; SCHED-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo + ; SCHED-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr17 = V_MUL_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr10 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc - ; SCHED-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr10 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo + ; SCHED-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo ; SCHED-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec ; ; PAIR-GFX11-LABEL: name: vopd_schedule_unconstrained - ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF + ; PAIR-GFX11: liveins: $vcc_lo + ; PAIR-GFX11-NEXT: {{ $}} + ; PAIR-GFX11-NEXT: $vgpr2 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF @@ -446,15 +458,17 @@ body: | ; PAIR-GFX11-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX11-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX11-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX11-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX11-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX11-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx11 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo ; PAIR-GFX11-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec ; ; PAIR-GFX12-LABEL: name: vopd_schedule_unconstrained - ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF + ; PAIR-GFX12: liveins: $vcc_lo + ; PAIR-GFX12-NEXT: {{ $}} + ; PAIR-GFX12-NEXT: $vgpr2 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF @@ -462,10 +476,10 @@ body: | ; PAIR-GFX12-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX12-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX12-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx12 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX12-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX12-NEXT: $vgpr12, $vgpr19 = V_DUAL_ADD_F32_e32_X_CNDMASK_B32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX12-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX12-NEXT: $vgpr17, $vgpr10 = V_DUAL_MUL_F32_e32_X_CNDMASK_B32_e32_gfx12 killed $vgpr0, $vgpr0, $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX12-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo ; PAIR-GFX12-NEXT: $vgpr16 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr14 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec $vgpr0 = IMPLICIT_DEF @@ -496,9 +510,12 @@ name: vopd_schedule_unconstrained_2 tracksRegLiveness: true body: | bb.0: + liveins: $vcc_lo ; SCHED-LABEL: name: vopd_schedule_unconstrained_2 - ; SCHED: $vgpr2 = IMPLICIT_DEF + ; SCHED: liveins: $vcc_lo + ; SCHED-NEXT: {{ $}} + ; SCHED-NEXT: $vgpr2 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr3 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr0 = IMPLICIT_DEF ; SCHED-NEXT: $vgpr1 = IMPLICIT_DEF @@ -510,28 +527,30 @@ body: | ; SCHED-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr4 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr29 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc - ; SCHED-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr29 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo + ; SCHED-NEXT: $vgpr19 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr20 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr20, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc - ; SCHED-NEXT: $vgpr10 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo + ; SCHED-NEXT: $vgpr10 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr17 = V_MUL_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr11 = V_CNDMASK_B32_e32 $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr12 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr37 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr37 = V_CNDMASK_B32_e32 $vgpr0, killed $vgpr3, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr14 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr21 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr24 = V_MUL_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo ; SCHED-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; SCHED-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; SCHED-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo ; SCHED-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; SCHED-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec ; ; PAIR-GFX11-LABEL: name: vopd_schedule_unconstrained_2 - ; PAIR-GFX11: $vgpr2 = IMPLICIT_DEF + ; PAIR-GFX11: liveins: $vcc_lo + ; PAIR-GFX11-NEXT: {{ $}} + ; PAIR-GFX11-NEXT: $vgpr2 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr3 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr0 = IMPLICIT_DEF ; PAIR-GFX11-NEXT: $vgpr1 = IMPLICIT_DEF @@ -540,23 +559,25 @@ body: | ; PAIR-GFX11-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX11-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX11-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec + ; PAIR-GFX11-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx11 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX11-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx11 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec + ; PAIR-GFX11-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX11-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec + ; PAIR-GFX11-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx11 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec + ; PAIR-GFX11-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx11 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx11 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX11-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo ; PAIR-GFX11-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; PAIR-GFX11-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX11-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo ; PAIR-GFX11-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX11-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec ; ; PAIR-GFX12-LABEL: name: vopd_schedule_unconstrained_2 - ; PAIR-GFX12: $vgpr2 = IMPLICIT_DEF + ; PAIR-GFX12: liveins: $vcc_lo + ; PAIR-GFX12-NEXT: {{ $}} + ; PAIR-GFX12-NEXT: $vgpr2 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr3 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr0 = IMPLICIT_DEF ; PAIR-GFX12-NEXT: $vgpr1 = IMPLICIT_DEF @@ -565,18 +586,18 @@ body: | ; PAIR-GFX12-NEXT: $vgpr3, $vgpr6 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr2 = V_FMAC_F32_e32 10, $vgpr1, killed $vgpr2, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX12-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx12 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc - ; PAIR-GFX12-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx12 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx12 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec + ; PAIR-GFX12-NEXT: $vgpr4, $vgpr29 = V_DUAL_SUB_F32_e32_X_CNDMASK_B32_e32_gfx12 $vgpr1, $vgpr1, $vgpr0, $vgpr3, implicit $mode, implicit $exec, implicit $vcc, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX12-NEXT: $vgpr19, $vgpr20 = V_DUAL_CNDMASK_B32_e32_X_FMAC_F32_e32_gfx12 $vgpr0, $vgpr3, 10, $vgpr1, killed $vgpr20, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec + ; PAIR-GFX12-NEXT: $vgpr15 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo + ; PAIR-GFX12-NEXT: $vgpr10, $vgpr17 = V_DUAL_CNDMASK_B32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr2, $vgpr0, $vgpr0, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec + ; PAIR-GFX12-NEXT: $vgpr11, $vgpr12 = V_DUAL_CNDMASK_B32_e32_X_ADD_F32_e32_gfx12 $vgpr0, $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec + ; PAIR-GFX12-NEXT: $vgpr37, $vgpr14 = V_DUAL_CNDMASK_B32_e32_X_SUB_F32_e32_gfx12 $vgpr0, killed $vgpr3, $vgpr1, $vgpr1, implicit $vcc, implicit $exec, implicit $mode, implicit $mode, implicit $exec, implicit $vcc_lo, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr20 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr21, $vgpr24 = V_DUAL_SUB_F32_e32_X_MUL_F32_e32_gfx12 $vgpr1, $vgpr1, killed $vgpr0, $vgpr0, implicit $mode, implicit $exec, implicit $mode, implicit $exec, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX12-NEXT: $vgpr28 = V_CNDMASK_B32_e32 $vgpr1, $vgpr2, implicit $mode, implicit $exec, implicit $vcc_lo ; PAIR-GFX12-NEXT: $vgpr22 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr31 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec - ; PAIR-GFX12-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit $vcc + ; PAIR-GFX12-NEXT: $vgpr33 = V_CNDMASK_B32_e32 $vgpr1, killed $vgpr2, implicit $mode, implicit $exec, implicit killed $vcc_lo ; PAIR-GFX12-NEXT: $vgpr34 = V_SUB_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec ; PAIR-GFX12-NEXT: $vgpr32 = V_SUB_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec $vgpr0 = IMPLICIT_DEF -- GitLab From 9430a4b9d272b050869958d5f0e7ef9fd9db2643 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 9 Apr 2024 09:32:34 +0100 Subject: [PATCH 256/695] [VPlan] Use getEdgeMask when constructing VPBlendRecipe (NFCI). After 2d0d65b3babe, block-in and edge masks are create up-front. Only retrieve the cached edge-mask here. --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 9e22dce38477..fd54faf17ca3 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -8226,7 +8226,7 @@ VPBlendRecipe *VPRecipeBuilder::tryToBlend(PHINode *Phi, for (unsigned In = 0; In < NumIncoming; In++) { OperandsWithMask.push_back(Operands[In]); VPValue *EdgeMask = - createEdgeMask(Phi->getIncomingBlock(In), Phi->getParent()); + getEdgeMask(Phi->getIncomingBlock(In), Phi->getParent()); if (!EdgeMask) { assert(In == 0 && "Both null and non-null edge masks found"); assert(all_equal(Operands) && -- GitLab From a4558a4a53eda8d170bbd2c358d383bb0a13f91f Mon Sep 17 00:00:00 2001 From: Qiu Chaofan Date: Tue, 9 Apr 2024 16:43:49 +0800 Subject: [PATCH 257/695] [PowerPC] Implement 32-bit expansion for rldimi (#86783) rldimi is 64-bit instruction, due to backward compatibility, it needs to be expanded into series of rotate and masking in 32-bit environment. In the future, we may improve bit permutation selector and remove such direct codegen. --- clang/lib/CodeGen/CGBuiltin.cpp | 10 ++ clang/lib/Sema/SemaChecking.cpp | 1 - .../PowerPC/builtins-ppc-xlcompat-error.c | 6 - llvm/include/llvm/IR/IntrinsicsPowerPC.td | 7 +- llvm/test/CodeGen/PowerPC/rldimi.ll | 154 ++++++++++++++++++ 5 files changed, 167 insertions(+), 11 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index df7502b8def5..c052367d2878 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -17288,6 +17288,16 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, Value *Op1 = EmitScalarExpr(E->getArg(1)); Value *Op2 = EmitScalarExpr(E->getArg(2)); Value *Op3 = EmitScalarExpr(E->getArg(3)); + // rldimi is 64-bit instruction, expand the intrinsic before isel to + // leverage peephole and avoid legalization efforts. + if (BuiltinID == PPC::BI__builtin_ppc_rldimi && + !getTarget().getTriple().isPPC64()) { + Function *F = CGM.getIntrinsic(Intrinsic::fshl, Op0->getType()); + Op2 = Builder.CreateZExt(Op2, Int64Ty); + Value *Shift = Builder.CreateCall(F, {Op0, Op0, Op2}); + return Builder.CreateOr(Builder.CreateAnd(Shift, Op3), + Builder.CreateAnd(Op1, Builder.CreateNot(Op3))); + } return Builder.CreateCall( CGM.getIntrinsic(BuiltinID == PPC::BI__builtin_ppc_rldimi ? Intrinsic::ppc_rldimi diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index f4746647b965..b84a779b7189 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -5232,7 +5232,6 @@ static bool isPPC_64Builtin(unsigned BuiltinID) { case PPC::BI__builtin_ppc_fetch_and_andlp: case PPC::BI__builtin_ppc_fetch_and_orlp: case PPC::BI__builtin_ppc_fetch_and_swaplp: - case PPC::BI__builtin_ppc_rldimi: return true; } return false; diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-error.c b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-error.c index 272e0222dc9e..f7f357df62af 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-error.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-error.c @@ -24,7 +24,6 @@ void test_trap(void) { __tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid range [1, 31]}} } -#ifdef __PPC64__ void test_builtin_ppc_rldimi() { unsigned int shift; unsigned long long mask; @@ -33,7 +32,6 @@ void test_builtin_ppc_rldimi() { res = __builtin_ppc_rldimi(ull, ull, 63, 0xFFFF000000000F00); // expected-error {{argument 3 value should represent a contiguous bit field}} res = __builtin_ppc_rldimi(ull, ull, 64, 0xFFFF000000000000); // expected-error {{argument value 64 is outside the valid range [0, 63]}} } -#endif void test_builtin_ppc_rlwimi() { unsigned int shift; @@ -86,10 +84,6 @@ void testalignx(const void *pointer, unsigned int alignment) { } #ifndef __PPC64__ -unsigned long long testrldimi32() { - return __rldimi(ull, ui, 3, 0x7ffff8ULL); //expected-error {{this builtin is only available on 64-bit targets}} -} - long long testbpermd(long long bit_selector, long long source) { return __bpermd(bit_selector, source); //expected-error {{this builtin is only available on 64-bit targets}} } diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index ee9a04241ac2..aff1fc7f085c 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -182,10 +182,6 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_fctuwz : ClangBuiltin<"__builtin_ppc_fctuwz">, DefaultAttrsIntrinsic<[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>; - def int_ppc_rldimi - : ClangBuiltin<"__builtin_ppc_rldimi">, - DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], - [IntrNoMem, ImmArg>, ImmArg>]>; def int_ppc_rlwimi : ClangBuiltin<"__builtin_ppc_rlwimi">, DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], @@ -194,6 +190,9 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". : ClangBuiltin<"__builtin_ppc_rlwnm">, DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem, ImmArg>]>; + def int_ppc_rldimi + : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], + [IntrNoMem, ImmArg>, ImmArg>]>; // XL compatible select functions // TODO: Add llvm_f128_ty support. diff --git a/llvm/test/CodeGen/PowerPC/rldimi.ll b/llvm/test/CodeGen/PowerPC/rldimi.ll index 78ea9aa862f2..4ce015849d9e 100644 --- a/llvm/test/CodeGen/PowerPC/rldimi.ll +++ b/llvm/test/CodeGen/PowerPC/rldimi.ll @@ -139,4 +139,158 @@ define i64 @rldimi11(i64 %a, i64 %b) { ret i64 %r } +define i64 @rldimi12(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi12: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 20 +; CHECK-NEXT: rldimi 4, 3, 44, 31 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 0, i64 18446726490113441791) + ret i64 %r +} + +define i64 @rldimi13(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi13: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 62 +; CHECK-NEXT: rldimi 4, 3, 32, 2 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 30, i64 4611686014132420608) + ret i64 %r +} + +define i64 @rldimi14(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi14: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 23 +; CHECK-NEXT: rldimi 4, 3, 53, 0 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18437736874454810624) ; mb=0, me=10 + ret i64 %r +} + +define i64 @rldimi15(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi15: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 36 +; CHECK-NEXT: rldimi 4, 3, 40, 10 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18013298997854208) ; mb=10, me=23 + ret i64 %r +} + +define i64 @rldimi16(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi16: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 57 +; CHECK-NEXT: rldimi 4, 3, 19, 10 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18014398508957696) ; mb=10, me=44 + ret i64 %r +} + +define i64 @rldimi17(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi17: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 43 +; CHECK-NEXT: rldimi 4, 3, 33, 25 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 541165879296) ; mb=25, me=30 + ret i64 %r +} + +define i64 @rldimi18(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi18: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 57 +; CHECK-NEXT: rldimi 4, 3, 19, 25 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 549755289600) ; mb=25, me=44 + ret i64 %r +} + +define i64 @rldimi19(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi19: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 57 +; CHECK-NEXT: rldimi 4, 3, 19, 33 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 2146959360) ; mb=33, me=44 + ret i64 %r +} + +define i64 @rldimi20(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi20: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 23 +; CHECK-NEXT: rldimi 4, 3, 53, 15 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18438299824408231935) ; mb=15, me=10 + ret i64 %r +} + +define i64 @rldimi21(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi21: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 23 +; CHECK-NEXT: rldimi 4, 3, 53, 25 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18437737424210624511) ; mb=25, me=10 + ret i64 %r +} + +define i64 @rldimi22(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi22: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 34 +; CHECK-NEXT: rldimi 4, 3, 42, 25 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18446740225418854399) ; mb=25, me=21 + ret i64 %r +} + +define i64 @rldimi23(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi23: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 23 +; CHECK-NEXT: rldimi 4, 3, 53, 44 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18437736874455859199) ; mb=44, me=10 + ret i64 %r +} + +define i64 @rldimi24(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi24: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 38 +; CHECK-NEXT: rldimi 4, 3, 38, 44 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18446743798832693247) ; mb=44, me=25 + ret i64 %r +} + +define i64 @rldimi25(i64 %a, i64 %b) { +; CHECK-LABEL: rldimi25: +; CHECK: # %bb.0: +; CHECK-NEXT: rotldi 3, 3, 48 +; CHECK-NEXT: rldimi 4, 3, 28, 44 +; CHECK-NEXT: mr 3, 4 +; CHECK-NEXT: blr + %r = call i64 @llvm.ppc.rldimi(i64 %a, i64 %b, i32 12, i64 18446744073442164735) ; mb=44, me=35 + ret i64 %r +} + declare i64 @llvm.ppc.rldimi(i64, i64, i32 immarg, i64 immarg) -- GitLab From db080605124db107e4f58cd285941a0c498675b1 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 8 Apr 2024 17:56:52 +0100 Subject: [PATCH 258/695] Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC. --- llvm/lib/Object/GOFFObjectFile.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Object/GOFFObjectFile.cpp b/llvm/lib/Object/GOFFObjectFile.cpp index 550aebfe0670..3b8704f28fdb 100644 --- a/llvm/lib/Object/GOFFObjectFile.cpp +++ b/llvm/lib/Object/GOFFObjectFile.cpp @@ -511,7 +511,7 @@ uint64_t GOFFObjectFile::getSectionAlignment(DataRefImpl Sec) const { const uint8_t *EsdRecord = getSectionEdEsdRecord(Sec); GOFF::ESDAlignment Pow2Alignment; ESDRecord::getAlignment(EsdRecord, Pow2Alignment); - return 1 << static_cast(Pow2Alignment); + return 1ULL << static_cast(Pow2Alignment); } bool GOFFObjectFile::isSectionText(DataRefImpl Sec) const { -- GitLab From 4ae33c52f794dbd64924dd006570cdc409c297bc Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 09:53:56 +0100 Subject: [PATCH 259/695] Fix MSVC "switch statement contains 'default' but no 'case' labels" warning. NFC. --- clang/lib/Sema/SemaOpenACC.cpp | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index f520b9bfe811..2ba1e49b5739 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -39,14 +39,11 @@ bool diagnoseConstructAppertainment(SemaOpenACC &S, OpenACCDirectiveKind K, bool doesClauseApplyToDirective(OpenACCDirectiveKind DirectiveKind, OpenACCClauseKind ClauseKind) { - switch (ClauseKind) { - // FIXME: For each clause as we implement them, we can add the - // 'legalization' list here. - default: - // Do nothing so we can go to the 'unimplemented' diagnostic instead. - return true; - } - llvm_unreachable("Invalid clause kind"); + // FIXME: For each clause as we implement them, we can add the + // 'legalization' list here. + + // Do nothing so we can go to the 'unimplemented' diagnostic instead. + return true; } } // namespace -- GitLab From 24e8c6a09b7d226dbe706aeae7aebf479a1e5087 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 9 Apr 2024 17:15:15 +0800 Subject: [PATCH 260/695] [RISCV] Convert remaining constant splats in tests to use splat shorthand. NFC (#88099) This follows on from #87616, but includes the tests with codegen differences. These are presumably due to the fact that the splat is now a constant expression. They don't seem to affect anything that we were specifically testing for. --- .../RISCV/rvv/fixed-vectors-masked-gather.ll | 2283 ++++------------- .../RISCV/rvv/fixed-vectors-masked-scatter.ll | 494 +--- .../RISCV/rvv/fixed-vectors-vadd-vp.ll | 24 +- .../RISCV/rvv/fixed-vectors-vmax-vp.ll | 12 +- .../RISCV/rvv/fixed-vectors-vmaxu-vp.ll | 12 +- .../RISCV/rvv/fixed-vectors-vmin-vp.ll | 12 +- .../RISCV/rvv/fixed-vectors-vminu-vp.ll | 12 +- .../RISCV/rvv/fixed-vectors-vsadd-vp.ll | 24 +- .../RISCV/rvv/fixed-vectors-vsaddu-vp.ll | 24 +- .../RISCV/rvv/fixed-vectors-vssub-vp.ll | 24 +- .../RISCV/rvv/fixed-vectors-vssubu-vp.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/rint-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll | 16 +- 28 files changed, 726 insertions(+), 2387 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index 6ff283b9c807..9fbc22221f99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -518,55 +518,20 @@ define <4 x i8> @mgather_truemask_v4i8(<4 x ptr> %ptrs, <4 x i8> %passthru) { ; ; RV64ZVE32F-LABEL: mgather_truemask_v4i8: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a1, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB9_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB9_6 -; RV64ZVE32F-NEXT: .LBB9_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB9_7 -; RV64ZVE32F-NEXT: .LBB9_3: # %else5 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: bnez a1, .LBB9_8 -; RV64ZVE32F-NEXT: .LBB9_4: # %else8 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB9_5: # %cond.load -; RV64ZVE32F-NEXT: ld a2, 0(a0) -; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v8, a2 -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB9_2 -; RV64ZVE32F-NEXT: .LBB9_6: # %cond.load1 -; RV64ZVE32F-NEXT: ld a2, 8(a0) -; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB9_3 -; RV64ZVE32F-NEXT: .LBB9_7: # %cond.load4 +; RV64ZVE32F-NEXT: ld a1, 8(a0) ; RV64ZVE32F-NEXT: ld a2, 16(a0) +; RV64ZVE32F-NEXT: ld a3, 24(a0) +; RV64ZVE32F-NEXT: ld a0, 0(a0) +; RV64ZVE32F-NEXT: lbu a1, 0(a1) ; RV64ZVE32F-NEXT: lbu a2, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e8, mf4, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: beqz a1, .LBB9_4 -; RV64ZVE32F-NEXT: .LBB9_8: # %cond.load7 -; RV64ZVE32F-NEXT: ld a0, 24(a0) -; RV64ZVE32F-NEXT: lbu a0, 0(a0) +; RV64ZVE32F-NEXT: lbu a3, 0(a3) ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 +; RV64ZVE32F-NEXT: vlse8.v v8, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %mtrue, <4 x i8> %passthru) + %v = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> splat (i1 1), <4 x i8> %passthru) ret <4 x i8> %v } @@ -1242,55 +1207,20 @@ define <4 x i16> @mgather_truemask_v4i16(<4 x ptr> %ptrs, <4 x i16> %passthru) { ; ; RV64ZVE32F-LABEL: mgather_truemask_v4i16: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a1, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB20_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB20_6 -; RV64ZVE32F-NEXT: .LBB20_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB20_7 -; RV64ZVE32F-NEXT: .LBB20_3: # %else5 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: bnez a1, .LBB20_8 -; RV64ZVE32F-NEXT: .LBB20_4: # %else8 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB20_5: # %cond.load -; RV64ZVE32F-NEXT: ld a2, 0(a0) -; RV64ZVE32F-NEXT: lh a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v8, a2 -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB20_2 -; RV64ZVE32F-NEXT: .LBB20_6: # %cond.load1 -; RV64ZVE32F-NEXT: ld a2, 8(a0) -; RV64ZVE32F-NEXT: lh a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB20_3 -; RV64ZVE32F-NEXT: .LBB20_7: # %cond.load4 +; RV64ZVE32F-NEXT: ld a1, 8(a0) ; RV64ZVE32F-NEXT: ld a2, 16(a0) +; RV64ZVE32F-NEXT: ld a3, 24(a0) +; RV64ZVE32F-NEXT: ld a0, 0(a0) +; RV64ZVE32F-NEXT: lh a1, 0(a1) ; RV64ZVE32F-NEXT: lh a2, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, mf2, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: beqz a1, .LBB20_4 -; RV64ZVE32F-NEXT: .LBB20_8: # %cond.load7 -; RV64ZVE32F-NEXT: ld a0, 24(a0) -; RV64ZVE32F-NEXT: lh a0, 0(a0) +; RV64ZVE32F-NEXT: lh a3, 0(a3) ; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> %mtrue, <4 x i16> %passthru) + %v = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1), <4 x i16> %passthru) ret <4 x i16> %v } @@ -2326,55 +2256,20 @@ define <4 x i32> @mgather_truemask_v4i32(<4 x ptr> %ptrs, <4 x i32> %passthru) { ; ; RV64ZVE32F-LABEL: mgather_truemask_v4i32: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a1, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB32_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB32_6 -; RV64ZVE32F-NEXT: .LBB32_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB32_7 -; RV64ZVE32F-NEXT: .LBB32_3: # %else5 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: bnez a1, .LBB32_8 -; RV64ZVE32F-NEXT: .LBB32_4: # %else8 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB32_5: # %cond.load -; RV64ZVE32F-NEXT: ld a2, 0(a0) -; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v8, a2 -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB32_2 -; RV64ZVE32F-NEXT: .LBB32_6: # %cond.load1 -; RV64ZVE32F-NEXT: ld a2, 8(a0) -; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB32_3 -; RV64ZVE32F-NEXT: .LBB32_7: # %cond.load4 +; RV64ZVE32F-NEXT: ld a1, 8(a0) ; RV64ZVE32F-NEXT: ld a2, 16(a0) +; RV64ZVE32F-NEXT: ld a3, 24(a0) +; RV64ZVE32F-NEXT: ld a0, 0(a0) +; RV64ZVE32F-NEXT: lw a1, 0(a1) ; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: beqz a1, .LBB32_4 -; RV64ZVE32F-NEXT: .LBB32_8: # %cond.load7 -; RV64ZVE32F-NEXT: ld a0, 24(a0) -; RV64ZVE32F-NEXT: lw a0, 0(a0) +; RV64ZVE32F-NEXT: lw a3, 0(a3) ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 +; RV64ZVE32F-NEXT: vlse32.v v8, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mtrue, <4 x i32> %passthru) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1), <4 x i32> %passthru) ret <4 x i32> %v } @@ -3839,117 +3734,48 @@ define <4 x i64> @mgather_truemask_v4i64(<4 x ptr> %ptrs, <4 x i64> %passthru) { ; ; RV32ZVE32F-LABEL: mgather_truemask_v4i64: ; RV32ZVE32F: # %bb.0: -; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV32ZVE32F-NEXT: vmset.m v9 -; RV32ZVE32F-NEXT: vmv.x.s a6, v9 -; RV32ZVE32F-NEXT: bnez zero, .LBB45_5 -; RV32ZVE32F-NEXT: # %bb.1: # %cond.load -; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV32ZVE32F-NEXT: vmv.x.s a3, v8 -; RV32ZVE32F-NEXT: lw a2, 4(a3) -; RV32ZVE32F-NEXT: lw a3, 0(a3) -; RV32ZVE32F-NEXT: andi a4, a6, 2 -; RV32ZVE32F-NEXT: bnez a4, .LBB45_6 -; RV32ZVE32F-NEXT: .LBB45_2: -; RV32ZVE32F-NEXT: lw a4, 12(a1) -; RV32ZVE32F-NEXT: lw a5, 8(a1) -; RV32ZVE32F-NEXT: andi a7, a6, 4 -; RV32ZVE32F-NEXT: bnez a7, .LBB45_7 -; RV32ZVE32F-NEXT: .LBB45_3: -; RV32ZVE32F-NEXT: lw a7, 20(a1) -; RV32ZVE32F-NEXT: lw t0, 16(a1) -; RV32ZVE32F-NEXT: andi a6, a6, 8 -; RV32ZVE32F-NEXT: bnez a6, .LBB45_8 -; RV32ZVE32F-NEXT: .LBB45_4: -; RV32ZVE32F-NEXT: lw a6, 28(a1) -; RV32ZVE32F-NEXT: lw a1, 24(a1) -; RV32ZVE32F-NEXT: j .LBB45_9 -; RV32ZVE32F-NEXT: .LBB45_5: -; RV32ZVE32F-NEXT: lw a2, 4(a1) -; RV32ZVE32F-NEXT: lw a3, 0(a1) -; RV32ZVE32F-NEXT: andi a4, a6, 2 -; RV32ZVE32F-NEXT: beqz a4, .LBB45_2 -; RV32ZVE32F-NEXT: .LBB45_6: # %cond.load1 ; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a1, v8 +; RV32ZVE32F-NEXT: lw a2, 0(a1) +; RV32ZVE32F-NEXT: lw a1, 4(a1) ; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV32ZVE32F-NEXT: vmv.x.s a5, v9 -; RV32ZVE32F-NEXT: lw a4, 4(a5) -; RV32ZVE32F-NEXT: lw a5, 0(a5) -; RV32ZVE32F-NEXT: andi a7, a6, 4 -; RV32ZVE32F-NEXT: beqz a7, .LBB45_3 -; RV32ZVE32F-NEXT: .LBB45_7: # %cond.load4 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a3, v9 +; RV32ZVE32F-NEXT: lw a4, 0(a3) +; RV32ZVE32F-NEXT: lw a3, 4(a3) ; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV32ZVE32F-NEXT: vmv.x.s t0, v9 -; RV32ZVE32F-NEXT: lw a7, 4(t0) -; RV32ZVE32F-NEXT: lw t0, 0(t0) -; RV32ZVE32F-NEXT: andi a6, a6, 8 -; RV32ZVE32F-NEXT: beqz a6, .LBB45_4 -; RV32ZVE32F-NEXT: .LBB45_8: # %cond.load7 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a5, v9 +; RV32ZVE32F-NEXT: lw a6, 0(a5) +; RV32ZVE32F-NEXT: lw a5, 4(a5) ; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 3 -; RV32ZVE32F-NEXT: vmv.x.s a1, v8 -; RV32ZVE32F-NEXT: lw a6, 4(a1) -; RV32ZVE32F-NEXT: lw a1, 0(a1) -; RV32ZVE32F-NEXT: .LBB45_9: # %else8 -; RV32ZVE32F-NEXT: sw a3, 0(a0) -; RV32ZVE32F-NEXT: sw a2, 4(a0) -; RV32ZVE32F-NEXT: sw a5, 8(a0) -; RV32ZVE32F-NEXT: sw a4, 12(a0) -; RV32ZVE32F-NEXT: sw t0, 16(a0) -; RV32ZVE32F-NEXT: sw a7, 20(a0) -; RV32ZVE32F-NEXT: sw a1, 24(a0) -; RV32ZVE32F-NEXT: sw a6, 28(a0) +; RV32ZVE32F-NEXT: vmv.x.s a7, v8 +; RV32ZVE32F-NEXT: lw t0, 4(a7) +; RV32ZVE32F-NEXT: lw a7, 0(a7) +; RV32ZVE32F-NEXT: sw a1, 4(a0) +; RV32ZVE32F-NEXT: sw a2, 0(a0) +; RV32ZVE32F-NEXT: sw t0, 28(a0) +; RV32ZVE32F-NEXT: sw a7, 24(a0) +; RV32ZVE32F-NEXT: sw a5, 20(a0) +; RV32ZVE32F-NEXT: sw a6, 16(a0) +; RV32ZVE32F-NEXT: sw a3, 12(a0) +; RV32ZVE32F-NEXT: sw a4, 8(a0) ; RV32ZVE32F-NEXT: ret ; ; RV64ZVE32F-LABEL: mgather_truemask_v4i64: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a5, v8 -; RV64ZVE32F-NEXT: bnez zero, .LBB45_5 -; RV64ZVE32F-NEXT: # %bb.1: # %cond.load -; RV64ZVE32F-NEXT: ld a3, 0(a1) -; RV64ZVE32F-NEXT: ld a3, 0(a3) -; RV64ZVE32F-NEXT: andi a4, a5, 2 -; RV64ZVE32F-NEXT: bnez a4, .LBB45_6 -; RV64ZVE32F-NEXT: .LBB45_2: -; RV64ZVE32F-NEXT: ld a4, 8(a2) -; RV64ZVE32F-NEXT: andi a6, a5, 4 -; RV64ZVE32F-NEXT: bnez a6, .LBB45_7 -; RV64ZVE32F-NEXT: .LBB45_3: -; RV64ZVE32F-NEXT: ld a6, 16(a2) -; RV64ZVE32F-NEXT: andi a5, a5, 8 -; RV64ZVE32F-NEXT: bnez a5, .LBB45_8 -; RV64ZVE32F-NEXT: .LBB45_4: -; RV64ZVE32F-NEXT: ld a1, 24(a2) -; RV64ZVE32F-NEXT: j .LBB45_9 -; RV64ZVE32F-NEXT: .LBB45_5: -; RV64ZVE32F-NEXT: ld a3, 0(a2) -; RV64ZVE32F-NEXT: andi a4, a5, 2 -; RV64ZVE32F-NEXT: beqz a4, .LBB45_2 -; RV64ZVE32F-NEXT: .LBB45_6: # %cond.load1 +; RV64ZVE32F-NEXT: ld a2, 24(a1) +; RV64ZVE32F-NEXT: ld a3, 16(a1) ; RV64ZVE32F-NEXT: ld a4, 8(a1) +; RV64ZVE32F-NEXT: ld a1, 0(a1) +; RV64ZVE32F-NEXT: ld a2, 0(a2) +; RV64ZVE32F-NEXT: ld a3, 0(a3) ; RV64ZVE32F-NEXT: ld a4, 0(a4) -; RV64ZVE32F-NEXT: andi a6, a5, 4 -; RV64ZVE32F-NEXT: beqz a6, .LBB45_3 -; RV64ZVE32F-NEXT: .LBB45_7: # %cond.load4 -; RV64ZVE32F-NEXT: ld a6, 16(a1) -; RV64ZVE32F-NEXT: ld a6, 0(a6) -; RV64ZVE32F-NEXT: andi a5, a5, 8 -; RV64ZVE32F-NEXT: beqz a5, .LBB45_4 -; RV64ZVE32F-NEXT: .LBB45_8: # %cond.load7 -; RV64ZVE32F-NEXT: ld a1, 24(a1) ; RV64ZVE32F-NEXT: ld a1, 0(a1) -; RV64ZVE32F-NEXT: .LBB45_9: # %else8 -; RV64ZVE32F-NEXT: sd a3, 0(a0) +; RV64ZVE32F-NEXT: sd a2, 24(a0) +; RV64ZVE32F-NEXT: sd a3, 16(a0) ; RV64ZVE32F-NEXT: sd a4, 8(a0) -; RV64ZVE32F-NEXT: sd a6, 16(a0) -; RV64ZVE32F-NEXT: sd a1, 24(a0) +; RV64ZVE32F-NEXT: sd a1, 0(a0) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> %mtrue, <4 x i64> %passthru) + %v = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1), <4 x i64> %passthru) ret <4 x i64> %v } @@ -7190,55 +7016,20 @@ define <4 x half> @mgather_truemask_v4f16(<4 x ptr> %ptrs, <4 x half> %passthru) ; ; RV64ZVE32F-LABEL: mgather_truemask_v4f16: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a1, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB61_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB61_6 -; RV64ZVE32F-NEXT: .LBB61_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB61_7 -; RV64ZVE32F-NEXT: .LBB61_3: # %else5 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: bnez a1, .LBB61_8 -; RV64ZVE32F-NEXT: .LBB61_4: # %else8 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB61_5: # %cond.load -; RV64ZVE32F-NEXT: ld a2, 0(a0) -; RV64ZVE32F-NEXT: flh fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5 -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB61_2 -; RV64ZVE32F-NEXT: .LBB61_6: # %cond.load1 -; RV64ZVE32F-NEXT: ld a2, 8(a0) -; RV64ZVE32F-NEXT: flh fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB61_3 -; RV64ZVE32F-NEXT: .LBB61_7: # %cond.load4 +; RV64ZVE32F-NEXT: ld a1, 8(a0) ; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: flh fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, mf2, tu, ma -; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: beqz a1, .LBB61_4 -; RV64ZVE32F-NEXT: .LBB61_8: # %cond.load7 -; RV64ZVE32F-NEXT: ld a0, 24(a0) -; RV64ZVE32F-NEXT: flh fa5, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 24(a0) +; RV64ZVE32F-NEXT: ld a0, 0(a0) +; RV64ZVE32F-NEXT: flh fa5, 0(a1) +; RV64ZVE32F-NEXT: flh fa4, 0(a2) +; RV64ZVE32F-NEXT: flh fa3, 0(a3) ; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa5 +; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa4 +; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa3 ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> %mtrue, <4 x half> %passthru) + %v = call <4 x half> @llvm.masked.gather.v4f16.v4p0(<4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1), <4 x half> %passthru) ret <4 x half> %v } @@ -8148,55 +7939,20 @@ define <4 x float> @mgather_truemask_v4f32(<4 x ptr> %ptrs, <4 x float> %passthr ; ; RV64ZVE32F-LABEL: mgather_truemask_v4f32: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a1, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB71_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB71_6 -; RV64ZVE32F-NEXT: .LBB71_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB71_7 -; RV64ZVE32F-NEXT: .LBB71_3: # %else5 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: bnez a1, .LBB71_8 -; RV64ZVE32F-NEXT: .LBB71_4: # %else8 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB71_5: # %cond.load -; RV64ZVE32F-NEXT: ld a2, 0(a0) -; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, tu, ma -; RV64ZVE32F-NEXT: vfmv.s.f v8, fa5 -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB71_2 -; RV64ZVE32F-NEXT: .LBB71_6: # %cond.load1 -; RV64ZVE32F-NEXT: ld a2, 8(a0) -; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB71_3 -; RV64ZVE32F-NEXT: .LBB71_7: # %cond.load4 +; RV64ZVE32F-NEXT: ld a1, 8(a0) ; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma -; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: beqz a1, .LBB71_4 -; RV64ZVE32F-NEXT: .LBB71_8: # %cond.load7 -; RV64ZVE32F-NEXT: ld a0, 24(a0) -; RV64ZVE32F-NEXT: flw fa5, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 24(a0) +; RV64ZVE32F-NEXT: ld a0, 0(a0) +; RV64ZVE32F-NEXT: flw fa5, 0(a1) +; RV64ZVE32F-NEXT: flw fa4, 0(a2) +; RV64ZVE32F-NEXT: flw fa3, 0(a3) ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV64ZVE32F-NEXT: vfmv.s.f v9, fa5 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 +; RV64ZVE32F-NEXT: vlse32.v v8, (a0), zero +; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa5 +; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa4 +; RV64ZVE32F-NEXT: vfslide1down.vf v8, v8, fa3 ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mtrue, <4 x float> %passthru) + %v = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1), <4 x float> %passthru) ret <4 x float> %v } @@ -9627,95 +9383,40 @@ define <4 x double> @mgather_truemask_v4f64(<4 x ptr> %ptrs, <4 x double> %passt ; ; RV32ZVE32F-LABEL: mgather_truemask_v4f64: ; RV32ZVE32F: # %bb.0: -; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV32ZVE32F-NEXT: vmset.m v9 -; RV32ZVE32F-NEXT: vmv.x.s a1, v9 -; RV32ZVE32F-NEXT: beqz zero, .LBB84_6 -; RV32ZVE32F-NEXT: # %bb.1: # %else -; RV32ZVE32F-NEXT: andi a2, a1, 2 -; RV32ZVE32F-NEXT: bnez a2, .LBB84_7 -; RV32ZVE32F-NEXT: .LBB84_2: # %else2 -; RV32ZVE32F-NEXT: andi a2, a1, 4 -; RV32ZVE32F-NEXT: bnez a2, .LBB84_8 -; RV32ZVE32F-NEXT: .LBB84_3: # %else5 -; RV32ZVE32F-NEXT: andi a1, a1, 8 -; RV32ZVE32F-NEXT: beqz a1, .LBB84_5 -; RV32ZVE32F-NEXT: .LBB84_4: # %cond.load7 ; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a1, v8 +; RV32ZVE32F-NEXT: fld fa5, 0(a1) +; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 2 +; RV32ZVE32F-NEXT: vmv.x.s a1, v9 +; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 1 +; RV32ZVE32F-NEXT: fld fa4, 0(a1) ; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: fld fa3, 0(a1) -; RV32ZVE32F-NEXT: .LBB84_5: # %else8 -; RV32ZVE32F-NEXT: fsd fa0, 0(a0) -; RV32ZVE32F-NEXT: fsd fa1, 8(a0) -; RV32ZVE32F-NEXT: fsd fa2, 16(a0) +; RV32ZVE32F-NEXT: vmv.x.s a1, v9 +; RV32ZVE32F-NEXT: fld fa2, 0(a1) +; RV32ZVE32F-NEXT: fsd fa5, 0(a0) ; RV32ZVE32F-NEXT: fsd fa3, 24(a0) +; RV32ZVE32F-NEXT: fsd fa4, 16(a0) +; RV32ZVE32F-NEXT: fsd fa2, 8(a0) ; RV32ZVE32F-NEXT: ret -; RV32ZVE32F-NEXT: .LBB84_6: # %cond.load -; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV32ZVE32F-NEXT: vmv.x.s a2, v8 -; RV32ZVE32F-NEXT: fld fa0, 0(a2) -; RV32ZVE32F-NEXT: andi a2, a1, 2 -; RV32ZVE32F-NEXT: beqz a2, .LBB84_2 -; RV32ZVE32F-NEXT: .LBB84_7: # %cond.load1 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV32ZVE32F-NEXT: vmv.x.s a2, v9 -; RV32ZVE32F-NEXT: fld fa1, 0(a2) -; RV32ZVE32F-NEXT: andi a2, a1, 4 -; RV32ZVE32F-NEXT: beqz a2, .LBB84_3 -; RV32ZVE32F-NEXT: .LBB84_8: # %cond.load4 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV32ZVE32F-NEXT: vmv.x.s a2, v9 -; RV32ZVE32F-NEXT: fld fa2, 0(a2) -; RV32ZVE32F-NEXT: andi a1, a1, 8 -; RV32ZVE32F-NEXT: bnez a1, .LBB84_4 -; RV32ZVE32F-NEXT: j .LBB84_5 ; ; RV64ZVE32F-LABEL: mgather_truemask_v4f64: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a2, v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB84_6 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a3, a2, 2 -; RV64ZVE32F-NEXT: bnez a3, .LBB84_7 -; RV64ZVE32F-NEXT: .LBB84_2: # %else2 -; RV64ZVE32F-NEXT: andi a3, a2, 4 -; RV64ZVE32F-NEXT: bnez a3, .LBB84_8 -; RV64ZVE32F-NEXT: .LBB84_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a2, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB84_5 -; RV64ZVE32F-NEXT: .LBB84_4: # %cond.load7 -; RV64ZVE32F-NEXT: ld a1, 24(a1) -; RV64ZVE32F-NEXT: fld fa3, 0(a1) -; RV64ZVE32F-NEXT: .LBB84_5: # %else8 -; RV64ZVE32F-NEXT: fsd fa0, 0(a0) -; RV64ZVE32F-NEXT: fsd fa1, 8(a0) -; RV64ZVE32F-NEXT: fsd fa2, 16(a0) -; RV64ZVE32F-NEXT: fsd fa3, 24(a0) -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB84_6: # %cond.load -; RV64ZVE32F-NEXT: ld a3, 0(a1) -; RV64ZVE32F-NEXT: fld fa0, 0(a3) -; RV64ZVE32F-NEXT: andi a3, a2, 2 -; RV64ZVE32F-NEXT: beqz a3, .LBB84_2 -; RV64ZVE32F-NEXT: .LBB84_7: # %cond.load1 -; RV64ZVE32F-NEXT: ld a3, 8(a1) -; RV64ZVE32F-NEXT: fld fa1, 0(a3) -; RV64ZVE32F-NEXT: andi a3, a2, 4 -; RV64ZVE32F-NEXT: beqz a3, .LBB84_3 -; RV64ZVE32F-NEXT: .LBB84_8: # %cond.load4 +; RV64ZVE32F-NEXT: ld a2, 24(a1) ; RV64ZVE32F-NEXT: ld a3, 16(a1) -; RV64ZVE32F-NEXT: fld fa2, 0(a3) -; RV64ZVE32F-NEXT: andi a2, a2, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB84_4 -; RV64ZVE32F-NEXT: j .LBB84_5 - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> %mtrue, <4 x double> %passthru) +; RV64ZVE32F-NEXT: ld a4, 8(a1) +; RV64ZVE32F-NEXT: ld a1, 0(a1) +; RV64ZVE32F-NEXT: fld fa5, 0(a2) +; RV64ZVE32F-NEXT: fld fa4, 0(a3) +; RV64ZVE32F-NEXT: fld fa3, 0(a4) +; RV64ZVE32F-NEXT: fld fa2, 0(a1) +; RV64ZVE32F-NEXT: fsd fa5, 24(a0) +; RV64ZVE32F-NEXT: fsd fa4, 16(a0) +; RV64ZVE32F-NEXT: fsd fa3, 8(a0) +; RV64ZVE32F-NEXT: fsd fa2, 0(a0) +; RV64ZVE32F-NEXT: ret + %v = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1), <4 x double> %passthru) ret <4 x double> %v } @@ -12885,10 +12586,8 @@ define <4 x i32> @mgather_unit_stride_load(ptr %base) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i32, ptr %base, <4 x i32> - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -12899,10 +12598,8 @@ define <4 x i32> @mgather_unit_stride_load_with_offset(ptr %base) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i32, ptr %base, <4 x i32> - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -12912,10 +12609,8 @@ define <4 x i32> @mgather_unit_stride_load_narrow_idx(ptr %base) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i32, ptr %base, <4 x i8> - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -12925,10 +12620,8 @@ define <4 x i32> @mgather_unit_stride_load_wide_idx(ptr %base) { ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i32, ptr %base, <4 x i128> - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -12959,51 +12652,15 @@ define <4 x i32> @mgather_narrow_edge_case(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_narrow_edge_case: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB106_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB106_6 -; RV64ZVE32F-NEXT: .LBB106_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB106_7 -; RV64ZVE32F-NEXT: .LBB106_3: # %else5 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: bnez a1, .LBB106_8 -; RV64ZVE32F-NEXT: .LBB106_4: # %else8 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB106_5: # %cond.load -; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV64ZVE32F-NEXT: vlse32.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB106_2 -; RV64ZVE32F-NEXT: .LBB106_6: # %cond.load1 -; RV64ZVE32F-NEXT: lw a2, -512(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB106_3 -; RV64ZVE32F-NEXT: .LBB106_7: # %cond.load4 -; RV64ZVE32F-NEXT: lw a2, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a1, a1, 8 -; RV64ZVE32F-NEXT: beqz a1, .LBB106_4 -; RV64ZVE32F-NEXT: .LBB106_8: # %cond.load7 -; RV64ZVE32F-NEXT: lw a0, -512(a0) +; RV64ZVE32F-NEXT: addi a1, a0, -512 +; RV64ZVE32F-NEXT: lw a0, 0(a0) ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 +; RV64ZVE32F-NEXT: vlse32.v v8, (a1), zero +; RV64ZVE32F-NEXT: vmv.v.i v0, 5 +; RV64ZVE32F-NEXT: vmerge.vxm v8, v8, a0, v0 ; RV64ZVE32F-NEXT: ret - %head = insertelement <4 x i1> poison, i1 true, i32 0 - %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer %ptrs = getelementptr inbounds i32, ptr %base, <4 x i8> - %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %allones, <4 x i32> poison) + %v = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %v } @@ -13011,404 +12668,198 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV32-LABEL: mgather_strided_unaligned: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; RV32-NEXT: vmset.m v8 -; RV32-NEXT: vid.v v10 -; RV32-NEXT: vsll.vi v10, v10, 2 -; RV32-NEXT: vadd.vx v10, v10, a0 -; RV32-NEXT: vsetvli zero, zero, e8, mf2, ta, ma +; RV32-NEXT: vid.v v8 +; RV32-NEXT: vsll.vi v8, v8, 2 +; RV32-NEXT: vadd.vx v8, v8, a0 ; RV32-NEXT: vmv.x.s a0, v8 -; RV32-NEXT: # implicit-def: $v8 -; RV32-NEXT: beqz zero, .LBB107_9 -; RV32-NEXT: # %bb.1: # %else -; RV32-NEXT: andi a1, a0, 2 -; RV32-NEXT: bnez a1, .LBB107_10 -; RV32-NEXT: .LBB107_2: # %else2 -; RV32-NEXT: andi a1, a0, 4 -; RV32-NEXT: bnez a1, .LBB107_11 -; RV32-NEXT: .LBB107_3: # %else5 -; RV32-NEXT: andi a1, a0, 8 -; RV32-NEXT: bnez a1, .LBB107_12 -; RV32-NEXT: .LBB107_4: # %else8 -; RV32-NEXT: andi a1, a0, 16 -; RV32-NEXT: bnez a1, .LBB107_13 -; RV32-NEXT: .LBB107_5: # %else11 -; RV32-NEXT: andi a1, a0, 32 -; RV32-NEXT: bnez a1, .LBB107_14 -; RV32-NEXT: .LBB107_6: # %else14 -; RV32-NEXT: andi a1, a0, 64 -; RV32-NEXT: bnez a1, .LBB107_15 -; RV32-NEXT: .LBB107_7: # %else17 -; RV32-NEXT: andi a0, a0, -128 -; RV32-NEXT: bnez a0, .LBB107_16 -; RV32-NEXT: .LBB107_8: # %else20 -; RV32-NEXT: ret -; RV32-NEXT: .LBB107_9: # %cond.load -; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV32-NEXT: vmv.x.s a1, v10 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV32-NEXT: vmv.v.x v8, a1 -; RV32-NEXT: andi a1, a0, 2 -; RV32-NEXT: beqz a1, .LBB107_2 -; RV32-NEXT: .LBB107_10: # %cond.load1 -; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV32-NEXT: vslidedown.vi v9, v10, 1 -; RV32-NEXT: vmv.x.s a1, v9 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vmv.s.x v9, a1 -; RV32-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v9, 1 -; RV32-NEXT: andi a1, a0, 4 -; RV32-NEXT: beqz a1, .LBB107_3 -; RV32-NEXT: .LBB107_11: # %cond.load4 -; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV32-NEXT: vslidedown.vi v9, v10, 2 -; RV32-NEXT: vmv.x.s a1, v9 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vmv.s.x v9, a1 -; RV32-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v9, 2 -; RV32-NEXT: andi a1, a0, 8 -; RV32-NEXT: beqz a1, .LBB107_4 -; RV32-NEXT: .LBB107_12: # %cond.load7 +; RV32-NEXT: lbu a1, 0(a0) +; RV32-NEXT: lbu a0, 1(a0) ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV32-NEXT: vslidedown.vi v9, v10, 3 -; RV32-NEXT: vmv.x.s a1, v9 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vmv.s.x v9, a1 -; RV32-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v9, 3 -; RV32-NEXT: andi a1, a0, 16 -; RV32-NEXT: beqz a1, .LBB107_5 -; RV32-NEXT: .LBB107_13: # %cond.load10 -; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma -; RV32-NEXT: vslidedown.vi v12, v10, 4 -; RV32-NEXT: vmv.x.s a1, v12 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vmv.s.x v9, a1 -; RV32-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v9, 4 -; RV32-NEXT: andi a1, a0, 32 -; RV32-NEXT: beqz a1, .LBB107_6 -; RV32-NEXT: .LBB107_14: # %cond.load13 -; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma -; RV32-NEXT: vslidedown.vi v12, v10, 5 -; RV32-NEXT: vmv.x.s a1, v12 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vmv.s.x v9, a1 -; RV32-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v9, 5 -; RV32-NEXT: andi a1, a0, 64 -; RV32-NEXT: beqz a1, .LBB107_7 -; RV32-NEXT: .LBB107_15: # %cond.load16 -; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma -; RV32-NEXT: vslidedown.vi v12, v10, 6 -; RV32-NEXT: vmv.x.s a1, v12 -; RV32-NEXT: lbu a2, 1(a1) -; RV32-NEXT: lbu a1, 0(a1) -; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a1, a2, a1 -; RV32-NEXT: vmv.s.x v9, a1 -; RV32-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV32-NEXT: vslideup.vi v8, v9, 6 -; RV32-NEXT: andi a0, a0, -128 -; RV32-NEXT: beqz a0, .LBB107_8 -; RV32-NEXT: .LBB107_16: # %cond.load19 -; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma -; RV32-NEXT: vslidedown.vi v10, v10, 7 -; RV32-NEXT: vmv.x.s a0, v10 -; RV32-NEXT: lbu a1, 1(a0) -; RV32-NEXT: lbu a0, 0(a0) +; RV32-NEXT: vslidedown.vi v10, v8, 1 +; RV32-NEXT: vmv.x.s a2, v10 +; RV32-NEXT: lbu a3, 1(a2) +; RV32-NEXT: lbu a2, 0(a2) +; RV32-NEXT: slli a0, a0, 8 +; RV32-NEXT: or a0, a0, a1 +; RV32-NEXT: slli a3, a3, 8 +; RV32-NEXT: or a2, a3, a2 +; RV32-NEXT: vslidedown.vi v10, v8, 2 +; RV32-NEXT: vmv.x.s a1, v10 +; RV32-NEXT: lbu a3, 0(a1) +; RV32-NEXT: lbu a1, 1(a1) +; RV32-NEXT: vslidedown.vi v10, v8, 3 +; RV32-NEXT: vmv.x.s a4, v10 +; RV32-NEXT: lbu a5, 1(a4) +; RV32-NEXT: lbu a4, 0(a4) ; RV32-NEXT: slli a1, a1, 8 -; RV32-NEXT: or a0, a1, a0 -; RV32-NEXT: vmv.s.x v9, a0 -; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV32-NEXT: vslideup.vi v8, v9, 7 +; RV32-NEXT: or a1, a1, a3 +; RV32-NEXT: slli a5, a5, 8 +; RV32-NEXT: or a4, a5, a4 +; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma +; RV32-NEXT: vslidedown.vi v10, v8, 4 +; RV32-NEXT: vmv.x.s a3, v10 +; RV32-NEXT: lbu a5, 0(a3) +; RV32-NEXT: lbu a3, 1(a3) +; RV32-NEXT: vslidedown.vi v10, v8, 5 +; RV32-NEXT: vmv.x.s a6, v10 +; RV32-NEXT: lbu a7, 1(a6) +; RV32-NEXT: lbu a6, 0(a6) +; RV32-NEXT: slli a3, a3, 8 +; RV32-NEXT: or a3, a3, a5 +; RV32-NEXT: slli a7, a7, 8 +; RV32-NEXT: or a5, a7, a6 +; RV32-NEXT: vslidedown.vi v10, v8, 6 +; RV32-NEXT: vmv.x.s a6, v10 +; RV32-NEXT: lbu a7, 0(a6) +; RV32-NEXT: lbu a6, 1(a6) +; RV32-NEXT: vslidedown.vi v8, v8, 7 +; RV32-NEXT: vmv.x.s t0, v8 +; RV32-NEXT: lbu t1, 1(t0) +; RV32-NEXT: lbu t0, 0(t0) +; RV32-NEXT: slli a6, a6, 8 +; RV32-NEXT: or a6, a6, a7 +; RV32-NEXT: slli t1, t1, 8 +; RV32-NEXT: or a7, t1, t0 +; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV32-NEXT: vmv.v.x v8, a0 +; RV32-NEXT: vslide1down.vx v8, v8, a2 +; RV32-NEXT: vslide1down.vx v8, v8, a1 +; RV32-NEXT: vslide1down.vx v9, v8, a4 +; RV32-NEXT: vmv.v.x v8, a3 +; RV32-NEXT: vslide1down.vx v8, v8, a5 +; RV32-NEXT: vslide1down.vx v8, v8, a6 +; RV32-NEXT: vmv.v.i v0, 15 +; RV32-NEXT: vslide1down.vx v8, v8, a7 +; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV32-NEXT: ret ; ; RV64V-LABEL: mgather_strided_unaligned: ; RV64V: # %bb.0: -; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; RV64V-NEXT: vmset.m v8 -; RV64V-NEXT: vid.v v12 -; RV64V-NEXT: vsll.vi v12, v12, 2 -; RV64V-NEXT: vadd.vx v12, v12, a0 -; RV64V-NEXT: vsetvli zero, zero, e8, mf2, ta, ma -; RV64V-NEXT: vmv.x.s a0, v8 -; RV64V-NEXT: # implicit-def: $v8 -; RV64V-NEXT: beqz zero, .LBB107_11 -; RV64V-NEXT: # %bb.1: # %else -; RV64V-NEXT: andi a1, a0, 2 -; RV64V-NEXT: bnez a1, .LBB107_12 -; RV64V-NEXT: .LBB107_2: # %else2 -; RV64V-NEXT: andi a1, a0, 4 -; RV64V-NEXT: bnez a1, .LBB107_13 -; RV64V-NEXT: .LBB107_3: # %else5 -; RV64V-NEXT: andi a1, a0, 8 -; RV64V-NEXT: beqz a1, .LBB107_5 -; RV64V-NEXT: .LBB107_4: # %cond.load7 -; RV64V-NEXT: vsetivli zero, 1, e64, m2, ta, ma -; RV64V-NEXT: vslidedown.vi v10, v12, 3 -; RV64V-NEXT: vmv.x.s a1, v10 -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) -; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vmv.s.x v9, a1 -; RV64V-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64V-NEXT: vslideup.vi v8, v9, 3 -; RV64V-NEXT: .LBB107_5: # %else8 -; RV64V-NEXT: addi sp, sp, -320 -; RV64V-NEXT: .cfi_def_cfa_offset 320 -; RV64V-NEXT: sd ra, 312(sp) # 8-byte Folded Spill -; RV64V-NEXT: sd s0, 304(sp) # 8-byte Folded Spill +; RV64V-NEXT: addi sp, sp, -128 +; RV64V-NEXT: .cfi_def_cfa_offset 128 +; RV64V-NEXT: sd ra, 120(sp) # 8-byte Folded Spill +; RV64V-NEXT: sd s0, 112(sp) # 8-byte Folded Spill ; RV64V-NEXT: .cfi_offset ra, -8 ; RV64V-NEXT: .cfi_offset s0, -16 -; RV64V-NEXT: addi s0, sp, 320 +; RV64V-NEXT: addi s0, sp, 128 ; RV64V-NEXT: .cfi_def_cfa s0, 0 ; RV64V-NEXT: andi sp, sp, -64 -; RV64V-NEXT: andi a1, a0, 16 -; RV64V-NEXT: bnez a1, .LBB107_14 -; RV64V-NEXT: # %bb.6: # %else11 -; RV64V-NEXT: andi a1, a0, 32 -; RV64V-NEXT: bnez a1, .LBB107_15 -; RV64V-NEXT: .LBB107_7: # %else14 -; RV64V-NEXT: andi a1, a0, 64 -; RV64V-NEXT: bnez a1, .LBB107_16 -; RV64V-NEXT: .LBB107_8: # %else17 -; RV64V-NEXT: andi a0, a0, -128 -; RV64V-NEXT: beqz a0, .LBB107_10 -; RV64V-NEXT: .LBB107_9: # %cond.load19 -; RV64V-NEXT: mv a0, sp ; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; RV64V-NEXT: vse64.v v12, (a0) -; RV64V-NEXT: ld a0, 56(sp) -; RV64V-NEXT: lbu a1, 1(a0) -; RV64V-NEXT: lbu a0, 0(a0) -; RV64V-NEXT: slli a1, a1, 8 -; RV64V-NEXT: or a0, a1, a0 -; RV64V-NEXT: vmv.s.x v9, a0 -; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64V-NEXT: vslideup.vi v8, v9, 7 -; RV64V-NEXT: .LBB107_10: # %else20 -; RV64V-NEXT: addi sp, s0, -320 -; RV64V-NEXT: ld ra, 312(sp) # 8-byte Folded Reload -; RV64V-NEXT: ld s0, 304(sp) # 8-byte Folded Reload -; RV64V-NEXT: addi sp, sp, 320 -; RV64V-NEXT: ret -; RV64V-NEXT: .LBB107_11: # %cond.load -; RV64V-NEXT: vsetvli zero, zero, e64, m4, ta, ma -; RV64V-NEXT: vmv.x.s a1, v12 -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) -; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64V-NEXT: vmv.v.x v8, a1 -; RV64V-NEXT: andi a1, a0, 2 -; RV64V-NEXT: beqz a1, .LBB107_2 -; RV64V-NEXT: .LBB107_12: # %cond.load1 +; RV64V-NEXT: vid.v v8 +; RV64V-NEXT: vsll.vi v8, v8, 2 +; RV64V-NEXT: vadd.vx v8, v8, a0 +; RV64V-NEXT: vmv.x.s a0, v8 +; RV64V-NEXT: lbu a1, 0(a0) +; RV64V-NEXT: lbu a0, 1(a0) ; RV64V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; RV64V-NEXT: vslidedown.vi v9, v12, 1 -; RV64V-NEXT: vmv.x.s a1, v9 -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) -; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vmv.s.x v9, a1 -; RV64V-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64V-NEXT: vslideup.vi v8, v9, 1 -; RV64V-NEXT: andi a1, a0, 4 -; RV64V-NEXT: beqz a1, .LBB107_3 -; RV64V-NEXT: .LBB107_13: # %cond.load4 +; RV64V-NEXT: vslidedown.vi v12, v8, 1 +; RV64V-NEXT: vmv.x.s a2, v12 +; RV64V-NEXT: lbu a3, 1(a2) +; RV64V-NEXT: lbu a2, 0(a2) +; RV64V-NEXT: slli a0, a0, 8 +; RV64V-NEXT: or a0, a0, a1 +; RV64V-NEXT: slli a1, a3, 8 +; RV64V-NEXT: or a1, a1, a2 ; RV64V-NEXT: vsetivli zero, 1, e64, m2, ta, ma -; RV64V-NEXT: vslidedown.vi v10, v12, 2 -; RV64V-NEXT: vmv.x.s a1, v10 -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) -; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vmv.s.x v9, a1 -; RV64V-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64V-NEXT: vslideup.vi v8, v9, 2 -; RV64V-NEXT: andi a1, a0, 8 -; RV64V-NEXT: bnez a1, .LBB107_4 -; RV64V-NEXT: j .LBB107_5 -; RV64V-NEXT: .LBB107_14: # %cond.load10 -; RV64V-NEXT: addi a1, sp, 192 -; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; RV64V-NEXT: vse64.v v12, (a1) -; RV64V-NEXT: ld a1, 224(sp) -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) -; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vmv.s.x v9, a1 -; RV64V-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64V-NEXT: vslideup.vi v8, v9, 4 -; RV64V-NEXT: andi a1, a0, 32 -; RV64V-NEXT: beqz a1, .LBB107_7 -; RV64V-NEXT: .LBB107_15: # %cond.load13 -; RV64V-NEXT: addi a1, sp, 128 -; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; RV64V-NEXT: vse64.v v12, (a1) -; RV64V-NEXT: ld a1, 168(sp) -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) -; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vmv.s.x v9, a1 -; RV64V-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64V-NEXT: vslideup.vi v8, v9, 5 -; RV64V-NEXT: andi a1, a0, 64 -; RV64V-NEXT: beqz a1, .LBB107_8 -; RV64V-NEXT: .LBB107_16: # %cond.load16 -; RV64V-NEXT: addi a1, sp, 64 -; RV64V-NEXT: vsetivli zero, 8, e64, m4, ta, ma -; RV64V-NEXT: vse64.v v12, (a1) -; RV64V-NEXT: ld a1, 112(sp) -; RV64V-NEXT: lbu a2, 1(a1) -; RV64V-NEXT: lbu a1, 0(a1) +; RV64V-NEXT: vslidedown.vi v12, v8, 2 +; RV64V-NEXT: vmv.x.s a2, v12 +; RV64V-NEXT: lbu a3, 0(a2) +; RV64V-NEXT: lbu a2, 1(a2) +; RV64V-NEXT: vslidedown.vi v12, v8, 3 +; RV64V-NEXT: vmv.x.s a4, v12 +; RV64V-NEXT: lbu a5, 0(a4) +; RV64V-NEXT: lbu a4, 1(a4) +; RV64V-NEXT: mv a6, sp +; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64V-NEXT: vse64.v v8, (a6) +; RV64V-NEXT: ld a6, 32(sp) ; RV64V-NEXT: slli a2, a2, 8 -; RV64V-NEXT: or a1, a2, a1 -; RV64V-NEXT: vmv.s.x v9, a1 -; RV64V-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64V-NEXT: vslideup.vi v8, v9, 6 -; RV64V-NEXT: andi a0, a0, -128 -; RV64V-NEXT: bnez a0, .LBB107_9 -; RV64V-NEXT: j .LBB107_10 +; RV64V-NEXT: or a2, a2, a3 +; RV64V-NEXT: slli a4, a4, 8 +; RV64V-NEXT: lbu a3, 1(a6) +; RV64V-NEXT: ld a7, 40(sp) +; RV64V-NEXT: lbu a6, 0(a6) +; RV64V-NEXT: or a4, a4, a5 +; RV64V-NEXT: slli a3, a3, 8 +; RV64V-NEXT: lbu a5, 1(a7) +; RV64V-NEXT: or a3, a3, a6 +; RV64V-NEXT: lbu a6, 0(a7) +; RV64V-NEXT: ld a7, 48(sp) +; RV64V-NEXT: slli a5, a5, 8 +; RV64V-NEXT: ld t0, 56(sp) +; RV64V-NEXT: or a5, a5, a6 +; RV64V-NEXT: lbu a6, 1(a7) +; RV64V-NEXT: lbu a7, 0(a7) +; RV64V-NEXT: lbu t1, 1(t0) +; RV64V-NEXT: lbu t0, 0(t0) +; RV64V-NEXT: slli a6, a6, 8 +; RV64V-NEXT: or a6, a6, a7 +; RV64V-NEXT: slli t1, t1, 8 +; RV64V-NEXT: or a7, t1, t0 +; RV64V-NEXT: vmv.v.x v8, a0 +; RV64V-NEXT: vslide1down.vx v8, v8, a1 +; RV64V-NEXT: vslide1down.vx v8, v8, a2 +; RV64V-NEXT: vslide1down.vx v9, v8, a4 +; RV64V-NEXT: vmv.v.x v8, a3 +; RV64V-NEXT: vslide1down.vx v8, v8, a5 +; RV64V-NEXT: vslide1down.vx v8, v8, a6 +; RV64V-NEXT: vmv.v.i v0, 15 +; RV64V-NEXT: vslide1down.vx v8, v8, a7 +; RV64V-NEXT: vslidedown.vi v8, v9, 4, v0.t +; RV64V-NEXT: addi sp, s0, -128 +; RV64V-NEXT: ld ra, 120(sp) # 8-byte Folded Reload +; RV64V-NEXT: ld s0, 112(sp) # 8-byte Folded Reload +; RV64V-NEXT: addi sp, sp, 128 +; RV64V-NEXT: ret ; ; RV64ZVE32F-LABEL: mgather_strided_unaligned: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB107_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB107_10 -; RV64ZVE32F-NEXT: .LBB107_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB107_11 -; RV64ZVE32F-NEXT: .LBB107_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB107_12 -; RV64ZVE32F-NEXT: .LBB107_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB107_13 -; RV64ZVE32F-NEXT: .LBB107_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB107_14 -; RV64ZVE32F-NEXT: .LBB107_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB107_15 -; RV64ZVE32F-NEXT: .LBB107_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB107_16 -; RV64ZVE32F-NEXT: .LBB107_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB107_9: # %cond.load -; RV64ZVE32F-NEXT: lbu a2, 1(a0) -; RV64ZVE32F-NEXT: lbu a3, 0(a0) -; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.v.x v8, a2 -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB107_2 -; RV64ZVE32F-NEXT: .LBB107_10: # %cond.load1 -; RV64ZVE32F-NEXT: lbu a2, 5(a0) -; RV64ZVE32F-NEXT: lbu a3, 4(a0) -; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB107_3 -; RV64ZVE32F-NEXT: .LBB107_11: # %cond.load4 +; RV64ZVE32F-NEXT: lbu a1, 1(a0) +; RV64ZVE32F-NEXT: lbu a2, 0(a0) +; RV64ZVE32F-NEXT: lbu a3, 5(a0) +; RV64ZVE32F-NEXT: lbu a4, 4(a0) +; RV64ZVE32F-NEXT: slli a1, a1, 8 +; RV64ZVE32F-NEXT: or a1, a1, a2 +; RV64ZVE32F-NEXT: slli a3, a3, 8 +; RV64ZVE32F-NEXT: or a3, a3, a4 ; RV64ZVE32F-NEXT: lbu a2, 9(a0) -; RV64ZVE32F-NEXT: lbu a3, 8(a0) -; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB107_4 -; RV64ZVE32F-NEXT: .LBB107_12: # %cond.load7 -; RV64ZVE32F-NEXT: lbu a2, 13(a0) -; RV64ZVE32F-NEXT: lbu a3, 12(a0) -; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB107_5 -; RV64ZVE32F-NEXT: .LBB107_13: # %cond.load10 -; RV64ZVE32F-NEXT: lbu a2, 17(a0) -; RV64ZVE32F-NEXT: lbu a3, 16(a0) -; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB107_6 -; RV64ZVE32F-NEXT: .LBB107_14: # %cond.load13 -; RV64ZVE32F-NEXT: lbu a2, 21(a0) -; RV64ZVE32F-NEXT: lbu a3, 20(a0) -; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB107_7 -; RV64ZVE32F-NEXT: .LBB107_15: # %cond.load16 -; RV64ZVE32F-NEXT: lbu a2, 25(a0) -; RV64ZVE32F-NEXT: lbu a3, 24(a0) +; RV64ZVE32F-NEXT: lbu a4, 8(a0) +; RV64ZVE32F-NEXT: lbu a5, 13(a0) +; RV64ZVE32F-NEXT: lbu a6, 12(a0) ; RV64ZVE32F-NEXT: slli a2, a2, 8 -; RV64ZVE32F-NEXT: or a2, a2, a3 -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB107_8 -; RV64ZVE32F-NEXT: .LBB107_16: # %cond.load19 -; RV64ZVE32F-NEXT: lbu a1, 29(a0) +; RV64ZVE32F-NEXT: or a2, a2, a4 +; RV64ZVE32F-NEXT: slli a5, a5, 8 +; RV64ZVE32F-NEXT: or a4, a5, a6 +; RV64ZVE32F-NEXT: lbu a5, 17(a0) +; RV64ZVE32F-NEXT: lbu a6, 16(a0) +; RV64ZVE32F-NEXT: lbu a7, 21(a0) +; RV64ZVE32F-NEXT: lbu t0, 20(a0) +; RV64ZVE32F-NEXT: slli a5, a5, 8 +; RV64ZVE32F-NEXT: or a5, a5, a6 +; RV64ZVE32F-NEXT: slli a7, a7, 8 +; RV64ZVE32F-NEXT: or a6, a7, t0 +; RV64ZVE32F-NEXT: lbu a7, 25(a0) +; RV64ZVE32F-NEXT: lbu t0, 24(a0) +; RV64ZVE32F-NEXT: lbu t1, 29(a0) ; RV64ZVE32F-NEXT: lbu a0, 28(a0) -; RV64ZVE32F-NEXT: slli a1, a1, 8 -; RV64ZVE32F-NEXT: or a0, a1, a0 -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: slli a7, a7, 8 +; RV64ZVE32F-NEXT: or a7, a7, t0 +; RV64ZVE32F-NEXT: slli t1, t1, 8 +; RV64ZVE32F-NEXT: or a0, t1, a0 +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vmv.v.x v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v9, v8, a4 +; RV64ZVE32F-NEXT: vmv.v.x v8, a5 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 1, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -13430,91 +12881,27 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_strided_2xSEW: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB108_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB108_10 -; RV64ZVE32F-NEXT: .LBB108_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB108_11 -; RV64ZVE32F-NEXT: .LBB108_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB108_12 -; RV64ZVE32F-NEXT: .LBB108_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB108_13 -; RV64ZVE32F-NEXT: .LBB108_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB108_14 -; RV64ZVE32F-NEXT: .LBB108_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB108_15 -; RV64ZVE32F-NEXT: .LBB108_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB108_16 -; RV64ZVE32F-NEXT: .LBB108_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB108_9: # %cond.load -; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB108_2 -; RV64ZVE32F-NEXT: .LBB108_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB108_3 -; RV64ZVE32F-NEXT: .LBB108_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 2(a0) ; RV64ZVE32F-NEXT: lh a2, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB108_4 -; RV64ZVE32F-NEXT: .LBB108_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 10(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB108_5 -; RV64ZVE32F-NEXT: .LBB108_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 16(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB108_6 -; RV64ZVE32F-NEXT: .LBB108_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB108_7 -; RV64ZVE32F-NEXT: .LBB108_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 24(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB108_8 -; RV64ZVE32F-NEXT: .LBB108_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 26(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 10(a0) +; RV64ZVE32F-NEXT: lh a4, 18(a0) +; RV64ZVE32F-NEXT: lh a5, 24(a0) +; RV64ZVE32F-NEXT: lh a6, 26(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 16 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -13538,92 +12925,28 @@ define <8 x i16> @mgather_strided_2xSEW_with_offset(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_strided_2xSEW_with_offset: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB109_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB109_10 -; RV64ZVE32F-NEXT: .LBB109_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB109_11 -; RV64ZVE32F-NEXT: .LBB109_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB109_12 -; RV64ZVE32F-NEXT: .LBB109_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB109_13 -; RV64ZVE32F-NEXT: .LBB109_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB109_14 -; RV64ZVE32F-NEXT: .LBB109_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB109_15 -; RV64ZVE32F-NEXT: .LBB109_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB109_16 -; RV64ZVE32F-NEXT: .LBB109_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB109_9: # %cond.load -; RV64ZVE32F-NEXT: addi a2, a0, 4 -; RV64ZVE32F-NEXT: vlse16.v v8, (a2), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB109_2 -; RV64ZVE32F-NEXT: .LBB109_10: # %cond.load1 +; RV64ZVE32F-NEXT: addi a1, a0, 4 ; RV64ZVE32F-NEXT: lh a2, 6(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB109_3 -; RV64ZVE32F-NEXT: .LBB109_11: # %cond.load4 -; RV64ZVE32F-NEXT: lh a2, 12(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB109_4 -; RV64ZVE32F-NEXT: .LBB109_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 14(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB109_5 -; RV64ZVE32F-NEXT: .LBB109_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB109_6 -; RV64ZVE32F-NEXT: .LBB109_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 22(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB109_7 -; RV64ZVE32F-NEXT: .LBB109_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 28(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB109_8 -; RV64ZVE32F-NEXT: .LBB109_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 30(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 12(a0) +; RV64ZVE32F-NEXT: lh a4, 14(a0) +; RV64ZVE32F-NEXT: lh a5, 22(a0) +; RV64ZVE32F-NEXT: lh a6, 28(a0) +; RV64ZVE32F-NEXT: lh a7, 30(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a1), zero +; RV64ZVE32F-NEXT: addi a0, a0, 20 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -13647,201 +12970,73 @@ define <8 x i16> @mgather_reverse_unit_strided_2xSEW(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_reverse_unit_strided_2xSEW: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB110_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB110_10 -; RV64ZVE32F-NEXT: .LBB110_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB110_11 -; RV64ZVE32F-NEXT: .LBB110_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB110_12 -; RV64ZVE32F-NEXT: .LBB110_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB110_13 -; RV64ZVE32F-NEXT: .LBB110_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB110_14 -; RV64ZVE32F-NEXT: .LBB110_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB110_15 -; RV64ZVE32F-NEXT: .LBB110_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB110_16 -; RV64ZVE32F-NEXT: .LBB110_8: # %else20 +; RV64ZVE32F-NEXT: addi a1, a0, 28 +; RV64ZVE32F-NEXT: lh a2, 30(a0) +; RV64ZVE32F-NEXT: lh a3, 24(a0) +; RV64ZVE32F-NEXT: lh a4, 26(a0) +; RV64ZVE32F-NEXT: lh a5, 22(a0) +; RV64ZVE32F-NEXT: lh a6, 16(a0) +; RV64ZVE32F-NEXT: lh a7, 18(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a1), zero +; RV64ZVE32F-NEXT: addi a0, a0, 20 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB110_9: # %cond.load -; RV64ZVE32F-NEXT: addi a2, a0, 28 -; RV64ZVE32F-NEXT: vlse16.v v8, (a2), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB110_2 -; RV64ZVE32F-NEXT: .LBB110_10: # %cond.load1 + %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) + ret <8 x i16> %v +} + +; TODO: Recognize as strided load with SEW=32 +define <8 x i16> @mgather_reverse_strided_2xSEW(ptr %base) { +; RV32-LABEL: mgather_reverse_strided_2xSEW: +; RV32: # %bb.0: +; RV32-NEXT: addi a0, a0, 28 +; RV32-NEXT: li a1, -8 +; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; RV32-NEXT: vlse32.v v8, (a0), a1 +; RV32-NEXT: ret +; +; RV64V-LABEL: mgather_reverse_strided_2xSEW: +; RV64V: # %bb.0: +; RV64V-NEXT: addi a0, a0, 28 +; RV64V-NEXT: li a1, -8 +; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; RV64V-NEXT: vlse32.v v8, (a0), a1 +; RV64V-NEXT: ret +; +; RV64ZVE32F-LABEL: mgather_reverse_strided_2xSEW: +; RV64ZVE32F: # %bb.0: +; RV64ZVE32F-NEXT: addi a1, a0, 28 ; RV64ZVE32F-NEXT: lh a2, 30(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB110_3 -; RV64ZVE32F-NEXT: .LBB110_11: # %cond.load4 -; RV64ZVE32F-NEXT: lh a2, 24(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB110_4 -; RV64ZVE32F-NEXT: .LBB110_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 26(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB110_5 -; RV64ZVE32F-NEXT: .LBB110_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB110_6 -; RV64ZVE32F-NEXT: .LBB110_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 22(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB110_7 -; RV64ZVE32F-NEXT: .LBB110_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 16(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB110_8 -; RV64ZVE32F-NEXT: .LBB110_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 -; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) - ret <8 x i16> %v -} - -; TODO: Recognize as strided load with SEW=32 -define <8 x i16> @mgather_reverse_strided_2xSEW(ptr %base) { -; RV32-LABEL: mgather_reverse_strided_2xSEW: -; RV32: # %bb.0: -; RV32-NEXT: addi a0, a0, 28 -; RV32-NEXT: li a1, -8 -; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV32-NEXT: vlse32.v v8, (a0), a1 -; RV32-NEXT: ret -; -; RV64V-LABEL: mgather_reverse_strided_2xSEW: -; RV64V: # %bb.0: -; RV64V-NEXT: addi a0, a0, 28 -; RV64V-NEXT: li a1, -8 -; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV64V-NEXT: vlse32.v v8, (a0), a1 -; RV64V-NEXT: ret -; -; RV64ZVE32F-LABEL: mgather_reverse_strided_2xSEW: -; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB111_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB111_10 -; RV64ZVE32F-NEXT: .LBB111_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB111_11 -; RV64ZVE32F-NEXT: .LBB111_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB111_12 -; RV64ZVE32F-NEXT: .LBB111_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB111_13 -; RV64ZVE32F-NEXT: .LBB111_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB111_14 -; RV64ZVE32F-NEXT: .LBB111_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB111_15 -; RV64ZVE32F-NEXT: .LBB111_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB111_16 -; RV64ZVE32F-NEXT: .LBB111_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB111_9: # %cond.load -; RV64ZVE32F-NEXT: addi a2, a0, 28 -; RV64ZVE32F-NEXT: vlse16.v v8, (a2), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB111_2 -; RV64ZVE32F-NEXT: .LBB111_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 30(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB111_3 -; RV64ZVE32F-NEXT: .LBB111_11: # %cond.load4 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB111_4 -; RV64ZVE32F-NEXT: .LBB111_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 22(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB111_5 -; RV64ZVE32F-NEXT: .LBB111_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 12(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB111_6 -; RV64ZVE32F-NEXT: .LBB111_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 14(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB111_7 -; RV64ZVE32F-NEXT: .LBB111_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB111_8 -; RV64ZVE32F-NEXT: .LBB111_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 20(a0) +; RV64ZVE32F-NEXT: lh a4, 22(a0) +; RV64ZVE32F-NEXT: lh a5, 14(a0) +; RV64ZVE32F-NEXT: lh a6, 4(a0) +; RV64ZVE32F-NEXT: lh a7, 6(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a1), zero +; RV64ZVE32F-NEXT: addi a0, a0, 12 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -13864,91 +13059,27 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_gather_2xSEW: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB112_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB112_10 -; RV64ZVE32F-NEXT: .LBB112_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB112_11 -; RV64ZVE32F-NEXT: .LBB112_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB112_12 -; RV64ZVE32F-NEXT: .LBB112_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB112_13 -; RV64ZVE32F-NEXT: .LBB112_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB112_14 -; RV64ZVE32F-NEXT: .LBB112_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB112_15 -; RV64ZVE32F-NEXT: .LBB112_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB112_16 -; RV64ZVE32F-NEXT: .LBB112_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB112_9: # %cond.load -; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB112_2 -; RV64ZVE32F-NEXT: .LBB112_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB112_3 -; RV64ZVE32F-NEXT: .LBB112_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 2(a0) ; RV64ZVE32F-NEXT: lh a2, 16(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB112_4 -; RV64ZVE32F-NEXT: .LBB112_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB112_5 -; RV64ZVE32F-NEXT: .LBB112_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB112_6 -; RV64ZVE32F-NEXT: .LBB112_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 10(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB112_7 -; RV64ZVE32F-NEXT: .LBB112_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB112_8 -; RV64ZVE32F-NEXT: .LBB112_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 18(a0) +; RV64ZVE32F-NEXT: lh a4, 10(a0) +; RV64ZVE32F-NEXT: lh a5, 4(a0) +; RV64ZVE32F-NEXT: lh a6, 6(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 8 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -13974,91 +13105,27 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_gather_2xSEW_unaligned: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB113_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB113_10 -; RV64ZVE32F-NEXT: .LBB113_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB113_11 -; RV64ZVE32F-NEXT: .LBB113_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB113_12 -; RV64ZVE32F-NEXT: .LBB113_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB113_13 -; RV64ZVE32F-NEXT: .LBB113_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB113_14 -; RV64ZVE32F-NEXT: .LBB113_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB113_15 -; RV64ZVE32F-NEXT: .LBB113_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB113_16 -; RV64ZVE32F-NEXT: .LBB113_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB113_9: # %cond.load -; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB113_2 -; RV64ZVE32F-NEXT: .LBB113_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB113_3 -; RV64ZVE32F-NEXT: .LBB113_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 2(a0) ; RV64ZVE32F-NEXT: lh a2, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB113_4 -; RV64ZVE32F-NEXT: .LBB113_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB113_5 -; RV64ZVE32F-NEXT: .LBB113_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB113_6 -; RV64ZVE32F-NEXT: .LBB113_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 10(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB113_7 -; RV64ZVE32F-NEXT: .LBB113_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB113_8 -; RV64ZVE32F-NEXT: .LBB113_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 20(a0) +; RV64ZVE32F-NEXT: lh a4, 10(a0) +; RV64ZVE32F-NEXT: lh a5, 4(a0) +; RV64ZVE32F-NEXT: lh a6, 6(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 8 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -14085,92 +13152,27 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned2(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_gather_2xSEW_unaligned2: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB114_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB114_10 -; RV64ZVE32F-NEXT: .LBB114_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB114_11 -; RV64ZVE32F-NEXT: .LBB114_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB114_12 -; RV64ZVE32F-NEXT: .LBB114_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB114_13 -; RV64ZVE32F-NEXT: .LBB114_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB114_14 -; RV64ZVE32F-NEXT: .LBB114_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB114_15 -; RV64ZVE32F-NEXT: .LBB114_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB114_16 -; RV64ZVE32F-NEXT: .LBB114_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB114_9: # %cond.load -; RV64ZVE32F-NEXT: addi a2, a0, 2 -; RV64ZVE32F-NEXT: vlse16.v v8, (a2), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB114_2 -; RV64ZVE32F-NEXT: .LBB114_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB114_3 -; RV64ZVE32F-NEXT: .LBB114_11: # %cond.load4 -; RV64ZVE32F-NEXT: lh a2, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB114_4 -; RV64ZVE32F-NEXT: .LBB114_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB114_5 -; RV64ZVE32F-NEXT: .LBB114_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB114_6 -; RV64ZVE32F-NEXT: .LBB114_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 10(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB114_7 -; RV64ZVE32F-NEXT: .LBB114_15: # %cond.load16 +; RV64ZVE32F-NEXT: addi a1, a0, 2 ; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB114_8 -; RV64ZVE32F-NEXT: .LBB114_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 18(a0) +; RV64ZVE32F-NEXT: lh a4, 20(a0) +; RV64ZVE32F-NEXT: lh a5, 10(a0) +; RV64ZVE32F-NEXT: lh a6, 6(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a1), zero +; RV64ZVE32F-NEXT: addi a0, a0, 8 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -14200,91 +13202,27 @@ define <8 x i16> @mgather_gather_4xSEW(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_gather_4xSEW: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB115_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB115_10 -; RV64ZVE32F-NEXT: .LBB115_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB115_11 -; RV64ZVE32F-NEXT: .LBB115_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB115_12 -; RV64ZVE32F-NEXT: .LBB115_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB115_13 -; RV64ZVE32F-NEXT: .LBB115_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB115_14 -; RV64ZVE32F-NEXT: .LBB115_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB115_15 -; RV64ZVE32F-NEXT: .LBB115_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB115_16 -; RV64ZVE32F-NEXT: .LBB115_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB115_9: # %cond.load -; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB115_2 -; RV64ZVE32F-NEXT: .LBB115_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB115_3 -; RV64ZVE32F-NEXT: .LBB115_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 2(a0) ; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB115_4 -; RV64ZVE32F-NEXT: .LBB115_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB115_5 -; RV64ZVE32F-NEXT: .LBB115_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 16(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB115_6 -; RV64ZVE32F-NEXT: .LBB115_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB115_7 -; RV64ZVE32F-NEXT: .LBB115_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB115_8 -; RV64ZVE32F-NEXT: .LBB115_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 22(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 6(a0) +; RV64ZVE32F-NEXT: lh a4, 18(a0) +; RV64ZVE32F-NEXT: lh a5, 20(a0) +; RV64ZVE32F-NEXT: lh a6, 22(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 16 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 8, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -14311,91 +13249,27 @@ define <8 x i16> @mgather_gather_4xSEW_partial_align(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_gather_4xSEW_partial_align: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB116_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB116_10 -; RV64ZVE32F-NEXT: .LBB116_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB116_11 -; RV64ZVE32F-NEXT: .LBB116_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB116_12 -; RV64ZVE32F-NEXT: .LBB116_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB116_13 -; RV64ZVE32F-NEXT: .LBB116_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB116_14 -; RV64ZVE32F-NEXT: .LBB116_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB116_15 -; RV64ZVE32F-NEXT: .LBB116_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB116_16 -; RV64ZVE32F-NEXT: .LBB116_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB116_9: # %cond.load -; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB116_2 -; RV64ZVE32F-NEXT: .LBB116_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB116_3 -; RV64ZVE32F-NEXT: .LBB116_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 2(a0) ; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB116_4 -; RV64ZVE32F-NEXT: .LBB116_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB116_5 -; RV64ZVE32F-NEXT: .LBB116_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 16(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB116_6 -; RV64ZVE32F-NEXT: .LBB116_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 18(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB116_7 -; RV64ZVE32F-NEXT: .LBB116_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 20(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB116_8 -; RV64ZVE32F-NEXT: .LBB116_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 22(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 6(a0) +; RV64ZVE32F-NEXT: lh a4, 18(a0) +; RV64ZVE32F-NEXT: lh a5, 20(a0) +; RV64ZVE32F-NEXT: lh a6, 22(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 16 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -14407,10 +13281,8 @@ define <8 x i16> @mgather_shuffle_reverse(ptr %base) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vlse16.v v8, (a0), a1 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -14433,92 +13305,27 @@ define <8 x i16> @mgather_shuffle_rotate(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_shuffle_rotate: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB118_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB118_10 -; RV64ZVE32F-NEXT: .LBB118_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB118_11 -; RV64ZVE32F-NEXT: .LBB118_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB118_12 -; RV64ZVE32F-NEXT: .LBB118_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB118_13 -; RV64ZVE32F-NEXT: .LBB118_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB118_14 -; RV64ZVE32F-NEXT: .LBB118_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB118_15 -; RV64ZVE32F-NEXT: .LBB118_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB118_16 -; RV64ZVE32F-NEXT: .LBB118_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB118_9: # %cond.load -; RV64ZVE32F-NEXT: addi a2, a0, 8 -; RV64ZVE32F-NEXT: vlse16.v v8, (a2), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB118_2 -; RV64ZVE32F-NEXT: .LBB118_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 10(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB118_3 -; RV64ZVE32F-NEXT: .LBB118_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 10(a0) ; RV64ZVE32F-NEXT: lh a2, 12(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB118_4 -; RV64ZVE32F-NEXT: .LBB118_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 14(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB118_5 -; RV64ZVE32F-NEXT: .LBB118_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB118_6 -; RV64ZVE32F-NEXT: .LBB118_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB118_7 -; RV64ZVE32F-NEXT: .LBB118_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB118_8 -; RV64ZVE32F-NEXT: .LBB118_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 14(a0) +; RV64ZVE32F-NEXT: lh a4, 2(a0) +; RV64ZVE32F-NEXT: lh a5, 4(a0) +; RV64ZVE32F-NEXT: lh a6, 6(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 8 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -14545,91 +13352,27 @@ define <8 x i16> @mgather_shuffle_vrgather(ptr %base) { ; ; RV64ZVE32F-LABEL: mgather_shuffle_vrgather: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a1, v8 -; RV64ZVE32F-NEXT: # implicit-def: $v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB119_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB119_10 -; RV64ZVE32F-NEXT: .LBB119_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB119_11 -; RV64ZVE32F-NEXT: .LBB119_3: # %else5 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB119_12 -; RV64ZVE32F-NEXT: .LBB119_4: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB119_13 -; RV64ZVE32F-NEXT: .LBB119_5: # %else11 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB119_14 -; RV64ZVE32F-NEXT: .LBB119_6: # %else14 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB119_15 -; RV64ZVE32F-NEXT: .LBB119_7: # %else17 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB119_16 -; RV64ZVE32F-NEXT: .LBB119_8: # %else20 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB119_9: # %cond.load -; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB119_2 -; RV64ZVE32F-NEXT: .LBB119_10: # %cond.load1 -; RV64ZVE32F-NEXT: lh a2, 4(a0) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB119_3 -; RV64ZVE32F-NEXT: .LBB119_11: # %cond.load4 +; RV64ZVE32F-NEXT: lh a1, 4(a0) ; RV64ZVE32F-NEXT: lh a2, 6(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 3, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB119_4 -; RV64ZVE32F-NEXT: .LBB119_12: # %cond.load7 -; RV64ZVE32F-NEXT: lh a2, 2(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB119_5 -; RV64ZVE32F-NEXT: .LBB119_13: # %cond.load10 -; RV64ZVE32F-NEXT: lh a2, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 5, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 4 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB119_6 -; RV64ZVE32F-NEXT: .LBB119_14: # %cond.load13 -; RV64ZVE32F-NEXT: lh a2, 10(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 6, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 5 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB119_7 -; RV64ZVE32F-NEXT: .LBB119_15: # %cond.load16 -; RV64ZVE32F-NEXT: lh a2, 12(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 7, e16, m1, tu, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a2 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 6 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB119_8 -; RV64ZVE32F-NEXT: .LBB119_16: # %cond.load19 -; RV64ZVE32F-NEXT: lh a0, 14(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vmv.s.x v9, a0 -; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 7 +; RV64ZVE32F-NEXT: lh a3, 2(a0) +; RV64ZVE32F-NEXT: lh a4, 10(a0) +; RV64ZVE32F-NEXT: lh a5, 12(a0) +; RV64ZVE32F-NEXT: lh a6, 14(a0) +; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu +; RV64ZVE32F-NEXT: vlse16.v v8, (a0), zero +; RV64ZVE32F-NEXT: addi a0, a0, 8 +; RV64ZVE32F-NEXT: vlse16.v v9, (a0), zero +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> %allones, <8 x i16> poison) + %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> %ptrs, i32 4, <8 x i1> splat (i1 true), <8 x i16> poison) ret <8 x i16> %v } @@ -15076,7 +13819,7 @@ define <32 x i64> @mgather_strided_split(ptr %base) { ; RV64ZVE32F-NEXT: addi sp, sp, 144 ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i64, ptr %base, <32 x i64> - %x = call <32 x i64> @llvm.masked.gather.v32i64.v32p0(<32 x ptr> %ptrs, i32 8, <32 x i1> shufflevector(<32 x i1> insertelement(<32 x i1> poison, i1 true, i32 0), <32 x i1> poison, <32 x i32> zeroinitializer), <32 x i64> poison) + %x = call <32 x i64> @llvm.masked.gather.v32i64.v32p0(<32 x ptr> %ptrs, i32 8, <32 x i1> splat (i1 true), <32 x i64> poison) ret <32 x i64> %x } @@ -15119,7 +13862,7 @@ define <4 x i32> @masked_gather_widen_sew_negative_stride(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0 ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr i32, ptr %base, <4 x i64> - %x = call <4 x i32> @llvm.masked.gather.v4i32.v32p0(<4 x ptr> %ptrs, i32 8, <4 x i1> shufflevector(<4 x i1> insertelement(<4 x i1> poison, i1 true, i32 0), <4 x i1> poison, <4 x i32> zeroinitializer), <4 x i32> poison) + %x = call <4 x i32> @llvm.masked.gather.v4i32.v32p0(<4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 true), <4 x i32> poison) ret <4 x i32> %x } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll index b2ff47145563..aa815e18ac10 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -336,49 +336,19 @@ define void @mscatter_truemask_v4i8(<4 x i8> %val, <4 x ptr> %ptrs) { ; RV64ZVE32F-LABEL: mscatter_truemask_v4i8: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: ld a1, 24(a0) -; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: ld a4, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a3, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB6_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB6_6 -; RV64ZVE32F-NEXT: .LBB6_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB6_7 -; RV64ZVE32F-NEXT: .LBB6_3: # %else4 -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: bnez a3, .LBB6_8 -; RV64ZVE32F-NEXT: .LBB6_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB6_5: # %cond.store -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma -; RV64ZVE32F-NEXT: vse8.v v8, (a0) -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB6_2 -; RV64ZVE32F-NEXT: .LBB6_6: # %cond.store1 +; RV64ZVE32F-NEXT: ld a2, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 8(a0) ; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; RV64ZVE32F-NEXT: vse8.v v8, (a2) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV64ZVE32F-NEXT: vse8.v v9, (a4) -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB6_3 -; RV64ZVE32F-NEXT: .LBB6_7: # %cond.store3 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; RV64ZVE32F-NEXT: vse8.v v9, (a0) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: vse8.v v9, (a2) -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: beqz a3, .LBB6_4 -; RV64ZVE32F-NEXT: .LBB6_8: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma +; RV64ZVE32F-NEXT: vse8.v v9, (a3) ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV64ZVE32F-NEXT: vse8.v v8, (a1) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> splat (i1 1)) ret void } @@ -883,49 +853,19 @@ define void @mscatter_truemask_v4i16(<4 x i16> %val, <4 x ptr> %ptrs) { ; RV64ZVE32F-LABEL: mscatter_truemask_v4i16: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: ld a1, 24(a0) -; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: ld a4, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a3, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB15_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB15_6 -; RV64ZVE32F-NEXT: .LBB15_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB15_7 -; RV64ZVE32F-NEXT: .LBB15_3: # %else4 -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: bnez a3, .LBB15_8 -; RV64ZVE32F-NEXT: .LBB15_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB15_5: # %cond.store -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: vse16.v v8, (a0) -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB15_2 -; RV64ZVE32F-NEXT: .LBB15_6: # %cond.store1 +; RV64ZVE32F-NEXT: ld a2, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 8(a0) ; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32F-NEXT: vse16.v v8, (a2) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV64ZVE32F-NEXT: vse16.v v9, (a4) -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB15_3 -; RV64ZVE32F-NEXT: .LBB15_7: # %cond.store3 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a0) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: beqz a3, .LBB15_4 -; RV64ZVE32F-NEXT: .LBB15_8: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a3) ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV64ZVE32F-NEXT: vse16.v v8, (a1) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1)) ret void } @@ -1788,49 +1728,19 @@ define void @mscatter_truemask_v4i32(<4 x i32> %val, <4 x ptr> %ptrs) { ; RV64ZVE32F-LABEL: mscatter_truemask_v4i32: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: ld a1, 24(a0) -; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: ld a4, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a3, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB26_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB26_6 -; RV64ZVE32F-NEXT: .LBB26_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB26_7 -; RV64ZVE32F-NEXT: .LBB26_3: # %else4 -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: bnez a3, .LBB26_8 -; RV64ZVE32F-NEXT: .LBB26_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB26_5: # %cond.store -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV64ZVE32F-NEXT: vse32.v v8, (a0) -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB26_2 -; RV64ZVE32F-NEXT: .LBB26_6: # %cond.store1 +; RV64ZVE32F-NEXT: ld a2, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 8(a0) ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vse32.v v8, (a2) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV64ZVE32F-NEXT: vse32.v v9, (a4) -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB26_3 -; RV64ZVE32F-NEXT: .LBB26_7: # %cond.store3 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vse32.v v9, (a0) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: vse32.v v9, (a2) -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: beqz a3, .LBB26_4 -; RV64ZVE32F-NEXT: .LBB26_8: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vse32.v v9, (a3) ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV64ZVE32F-NEXT: vse32.v v8, (a1) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1)) ret void } @@ -3163,50 +3073,22 @@ define void @mscatter_truemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs) { ; RV32ZVE32F-NEXT: lw a2, 24(a0) ; RV32ZVE32F-NEXT: lw a3, 20(a0) ; RV32ZVE32F-NEXT: lw a4, 16(a0) -; RV32ZVE32F-NEXT: lw a7, 12(a0) +; RV32ZVE32F-NEXT: lw a5, 12(a0) ; RV32ZVE32F-NEXT: lw a6, 8(a0) -; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV32ZVE32F-NEXT: vmset.m v9 -; RV32ZVE32F-NEXT: vmv.x.s a5, v9 -; RV32ZVE32F-NEXT: beqz zero, .LBB39_5 -; RV32ZVE32F-NEXT: # %bb.1: # %else -; RV32ZVE32F-NEXT: andi a0, a5, 2 -; RV32ZVE32F-NEXT: bnez a0, .LBB39_6 -; RV32ZVE32F-NEXT: .LBB39_2: # %else2 -; RV32ZVE32F-NEXT: andi a0, a5, 4 -; RV32ZVE32F-NEXT: bnez a0, .LBB39_7 -; RV32ZVE32F-NEXT: .LBB39_3: # %else4 -; RV32ZVE32F-NEXT: andi a5, a5, 8 -; RV32ZVE32F-NEXT: bnez a5, .LBB39_8 -; RV32ZVE32F-NEXT: .LBB39_4: # %else6 -; RV32ZVE32F-NEXT: ret -; RV32ZVE32F-NEXT: .LBB39_5: # %cond.store -; RV32ZVE32F-NEXT: lw t0, 4(a0) -; RV32ZVE32F-NEXT: lw a0, 0(a0) -; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV32ZVE32F-NEXT: vmv.x.s t1, v8 -; RV32ZVE32F-NEXT: sw t0, 4(t1) -; RV32ZVE32F-NEXT: sw a0, 0(t1) -; RV32ZVE32F-NEXT: andi a0, a5, 2 -; RV32ZVE32F-NEXT: beqz a0, .LBB39_2 -; RV32ZVE32F-NEXT: .LBB39_6: # %cond.store1 +; RV32ZVE32F-NEXT: lw a7, 0(a0) +; RV32ZVE32F-NEXT: lw a0, 4(a0) ; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s t0, v8 +; RV32ZVE32F-NEXT: sw a7, 0(t0) +; RV32ZVE32F-NEXT: sw a0, 4(t0) ; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV32ZVE32F-NEXT: vmv.x.s a0, v9 -; RV32ZVE32F-NEXT: sw a7, 4(a0) ; RV32ZVE32F-NEXT: sw a6, 0(a0) -; RV32ZVE32F-NEXT: andi a0, a5, 4 -; RV32ZVE32F-NEXT: beqz a0, .LBB39_3 -; RV32ZVE32F-NEXT: .LBB39_7: # %cond.store3 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: sw a5, 4(a0) ; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 2 ; RV32ZVE32F-NEXT: vmv.x.s a0, v9 ; RV32ZVE32F-NEXT: sw a4, 0(a0) ; RV32ZVE32F-NEXT: sw a3, 4(a0) -; RV32ZVE32F-NEXT: andi a5, a5, 8 -; RV32ZVE32F-NEXT: beqz a5, .LBB39_4 -; RV32ZVE32F-NEXT: .LBB39_8: # %cond.store5 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vmv.x.s a0, v8 ; RV32ZVE32F-NEXT: sw a2, 0(a0) @@ -3216,46 +3098,19 @@ define void @mscatter_truemask_v4i64(<4 x i64> %val, <4 x ptr> %ptrs) { ; RV64ZVE32F-LABEL: mscatter_truemask_v4i64: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: ld a2, 24(a1) -; RV64ZVE32F-NEXT: ld a4, 16(a1) -; RV64ZVE32F-NEXT: ld a7, 8(a1) -; RV64ZVE32F-NEXT: ld a3, 24(a0) -; RV64ZVE32F-NEXT: ld a5, 16(a0) -; RV64ZVE32F-NEXT: ld t0, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a6, v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB39_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a6, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB39_6 -; RV64ZVE32F-NEXT: .LBB39_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a6, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB39_7 -; RV64ZVE32F-NEXT: .LBB39_3: # %else4 -; RV64ZVE32F-NEXT: andi a0, a6, 8 -; RV64ZVE32F-NEXT: bnez a0, .LBB39_8 -; RV64ZVE32F-NEXT: .LBB39_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB39_5: # %cond.store +; RV64ZVE32F-NEXT: ld a3, 16(a1) +; RV64ZVE32F-NEXT: ld a4, 8(a1) ; RV64ZVE32F-NEXT: ld a1, 0(a1) -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: sd a0, 0(a1) -; RV64ZVE32F-NEXT: andi a0, a6, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB39_2 -; RV64ZVE32F-NEXT: .LBB39_6: # %cond.store1 -; RV64ZVE32F-NEXT: sd t0, 0(a7) -; RV64ZVE32F-NEXT: andi a0, a6, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB39_3 -; RV64ZVE32F-NEXT: .LBB39_7: # %cond.store3 -; RV64ZVE32F-NEXT: sd a5, 0(a4) -; RV64ZVE32F-NEXT: andi a0, a6, 8 -; RV64ZVE32F-NEXT: beqz a0, .LBB39_4 -; RV64ZVE32F-NEXT: .LBB39_8: # %cond.store5 -; RV64ZVE32F-NEXT: sd a3, 0(a2) +; RV64ZVE32F-NEXT: ld a5, 0(a0) +; RV64ZVE32F-NEXT: ld a6, 8(a0) +; RV64ZVE32F-NEXT: ld a7, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 24(a0) +; RV64ZVE32F-NEXT: sd a5, 0(a1) +; RV64ZVE32F-NEXT: sd a6, 0(a4) +; RV64ZVE32F-NEXT: sd a7, 0(a3) +; RV64ZVE32F-NEXT: sd a0, 0(a2) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1)) ret void } @@ -6168,49 +6023,19 @@ define void @mscatter_truemask_v4f16(<4 x half> %val, <4 x ptr> %ptrs) { ; RV64ZVE32F-LABEL: mscatter_truemask_v4f16: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: ld a1, 24(a0) -; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: ld a4, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a3, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB55_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB55_6 -; RV64ZVE32F-NEXT: .LBB55_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB55_7 -; RV64ZVE32F-NEXT: .LBB55_3: # %else4 -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: bnez a3, .LBB55_8 -; RV64ZVE32F-NEXT: .LBB55_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB55_5: # %cond.store -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: vse16.v v8, (a0) -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB55_2 -; RV64ZVE32F-NEXT: .LBB55_6: # %cond.store1 +; RV64ZVE32F-NEXT: ld a2, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 8(a0) ; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32F-NEXT: vse16.v v8, (a2) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV64ZVE32F-NEXT: vse16.v v9, (a4) -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB55_3 -; RV64ZVE32F-NEXT: .LBB55_7: # %cond.store3 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a0) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: beqz a3, .LBB55_4 -; RV64ZVE32F-NEXT: .LBB55_8: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a3) ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV64ZVE32F-NEXT: vse16.v v8, (a1) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> %val, <4 x ptr> %ptrs, i32 2, <4 x i1> splat (i1 1)) ret void } @@ -7020,49 +6845,19 @@ define void @mscatter_truemask_v4f32(<4 x float> %val, <4 x ptr> %ptrs) { ; RV64ZVE32F-LABEL: mscatter_truemask_v4f32: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: ld a1, 24(a0) -; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: ld a4, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a3, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB65_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB65_6 -; RV64ZVE32F-NEXT: .LBB65_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB65_7 -; RV64ZVE32F-NEXT: .LBB65_3: # %else4 -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: bnez a3, .LBB65_8 -; RV64ZVE32F-NEXT: .LBB65_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB65_5: # %cond.store -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma -; RV64ZVE32F-NEXT: vse32.v v8, (a0) -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB65_2 -; RV64ZVE32F-NEXT: .LBB65_6: # %cond.store1 +; RV64ZVE32F-NEXT: ld a2, 0(a0) +; RV64ZVE32F-NEXT: ld a3, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 8(a0) ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vse32.v v8, (a2) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV64ZVE32F-NEXT: vse32.v v9, (a4) -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB65_3 -; RV64ZVE32F-NEXT: .LBB65_7: # %cond.store3 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vse32.v v9, (a0) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: vse32.v v9, (a2) -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: beqz a3, .LBB65_4 -; RV64ZVE32F-NEXT: .LBB65_8: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vse32.v v9, (a3) ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV64ZVE32F-NEXT: vse32.v v8, (a1) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> %val, <4 x ptr> %ptrs, i32 4, <4 x i1> splat (i1 1)) ret void } @@ -8368,43 +8163,15 @@ define void @mscatter_truemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs) { ; ; RV32ZVE32F-LABEL: mscatter_truemask_v4f64: ; RV32ZVE32F: # %bb.0: -; RV32ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV32ZVE32F-NEXT: vmset.m v9 -; RV32ZVE32F-NEXT: vmv.x.s a0, v9 -; RV32ZVE32F-NEXT: beqz zero, .LBB78_5 -; RV32ZVE32F-NEXT: # %bb.1: # %else -; RV32ZVE32F-NEXT: andi a1, a0, 2 -; RV32ZVE32F-NEXT: bnez a1, .LBB78_6 -; RV32ZVE32F-NEXT: .LBB78_2: # %else2 -; RV32ZVE32F-NEXT: andi a1, a0, 4 -; RV32ZVE32F-NEXT: bnez a1, .LBB78_7 -; RV32ZVE32F-NEXT: .LBB78_3: # %else4 -; RV32ZVE32F-NEXT: andi a0, a0, 8 -; RV32ZVE32F-NEXT: bnez a0, .LBB78_8 -; RV32ZVE32F-NEXT: .LBB78_4: # %else6 -; RV32ZVE32F-NEXT: ret -; RV32ZVE32F-NEXT: .LBB78_5: # %cond.store -; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; RV32ZVE32F-NEXT: vmv.x.s a1, v8 -; RV32ZVE32F-NEXT: fsd fa0, 0(a1) -; RV32ZVE32F-NEXT: andi a1, a0, 2 -; RV32ZVE32F-NEXT: beqz a1, .LBB78_2 -; RV32ZVE32F-NEXT: .LBB78_6: # %cond.store1 ; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a0, v8 +; RV32ZVE32F-NEXT: fsd fa0, 0(a0) ; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV32ZVE32F-NEXT: vmv.x.s a1, v9 -; RV32ZVE32F-NEXT: fsd fa1, 0(a1) -; RV32ZVE32F-NEXT: andi a1, a0, 4 -; RV32ZVE32F-NEXT: beqz a1, .LBB78_3 -; RV32ZVE32F-NEXT: .LBB78_7: # %cond.store3 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a0, v9 +; RV32ZVE32F-NEXT: fsd fa1, 0(a0) ; RV32ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV32ZVE32F-NEXT: vmv.x.s a1, v9 -; RV32ZVE32F-NEXT: fsd fa2, 0(a1) -; RV32ZVE32F-NEXT: andi a0, a0, 8 -; RV32ZVE32F-NEXT: beqz a0, .LBB78_4 -; RV32ZVE32F-NEXT: .LBB78_8: # %cond.store5 -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; RV32ZVE32F-NEXT: vmv.x.s a0, v9 +; RV32ZVE32F-NEXT: fsd fa2, 0(a0) ; RV32ZVE32F-NEXT: vslidedown.vi v8, v8, 3 ; RV32ZVE32F-NEXT: vmv.x.s a0, v8 ; RV32ZVE32F-NEXT: fsd fa3, 0(a0) @@ -8412,43 +8179,16 @@ define void @mscatter_truemask_v4f64(<4 x double> %val, <4 x ptr> %ptrs) { ; ; RV64ZVE32F-LABEL: mscatter_truemask_v4f64: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: ld a1, 24(a0) -; RV64ZVE32F-NEXT: ld a2, 16(a0) -; RV64ZVE32F-NEXT: ld a4, 8(a0) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v8 -; RV64ZVE32F-NEXT: vmv.x.s a3, v8 -; RV64ZVE32F-NEXT: beqz zero, .LBB78_5 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: bnez a0, .LBB78_6 -; RV64ZVE32F-NEXT: .LBB78_2: # %else2 -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: bnez a0, .LBB78_7 -; RV64ZVE32F-NEXT: .LBB78_3: # %else4 -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: bnez a3, .LBB78_8 -; RV64ZVE32F-NEXT: .LBB78_4: # %else6 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB78_5: # %cond.store -; RV64ZVE32F-NEXT: ld a0, 0(a0) -; RV64ZVE32F-NEXT: fsd fa0, 0(a0) -; RV64ZVE32F-NEXT: andi a0, a3, 2 -; RV64ZVE32F-NEXT: beqz a0, .LBB78_2 -; RV64ZVE32F-NEXT: .LBB78_6: # %cond.store1 -; RV64ZVE32F-NEXT: fsd fa1, 0(a4) -; RV64ZVE32F-NEXT: andi a0, a3, 4 -; RV64ZVE32F-NEXT: beqz a0, .LBB78_3 -; RV64ZVE32F-NEXT: .LBB78_7: # %cond.store3 -; RV64ZVE32F-NEXT: fsd fa2, 0(a2) -; RV64ZVE32F-NEXT: andi a3, a3, 8 -; RV64ZVE32F-NEXT: beqz a3, .LBB78_4 -; RV64ZVE32F-NEXT: .LBB78_8: # %cond.store5 -; RV64ZVE32F-NEXT: fsd fa3, 0(a1) +; RV64ZVE32F-NEXT: ld a1, 0(a0) +; RV64ZVE32F-NEXT: ld a2, 8(a0) +; RV64ZVE32F-NEXT: ld a3, 16(a0) +; RV64ZVE32F-NEXT: ld a0, 24(a0) +; RV64ZVE32F-NEXT: fsd fa0, 0(a1) +; RV64ZVE32F-NEXT: fsd fa1, 0(a2) +; RV64ZVE32F-NEXT: fsd fa2, 0(a3) +; RV64ZVE32F-NEXT: fsd fa3, 0(a0) ; RV64ZVE32F-NEXT: ret - %mhead = insertelement <4 x i1> poison, i1 1, i32 0 - %mtrue = shufflevector <4 x i1> %mhead, <4 x i1> poison, <4 x i32> zeroinitializer - call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> %mtrue) + call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %val, <4 x ptr> %ptrs, i32 8, <4 x i1> splat (i1 1)) ret void } @@ -11344,10 +11084,8 @@ define void @mscatter_unit_stride(<8 x i16> %val, ptr %base) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %allones) + call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true)) ret void } @@ -11358,10 +11096,8 @@ define void @mscatter_unit_stride_with_offset(<8 x i16> %val, ptr %base) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %allones) + call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true)) ret void } @@ -11373,10 +11109,8 @@ define void @mscatter_shuffle_reverse(<8 x i16> %val, ptr %base) { ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsse16.v v8, (a0), a1 ; CHECK-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %allones) + call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true)) ret void } @@ -11399,89 +11133,31 @@ define void @mscatter_shuffle_rotate(<8 x i16> %val, ptr %base) { ; ; RV64ZVE32F-LABEL: mscatter_shuffle_rotate: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma -; RV64ZVE32F-NEXT: vmset.m v9 -; RV64ZVE32F-NEXT: vmv.x.s a1, v9 -; RV64ZVE32F-NEXT: beqz zero, .LBB96_9 -; RV64ZVE32F-NEXT: # %bb.1: # %else -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: bnez a2, .LBB96_10 -; RV64ZVE32F-NEXT: .LBB96_2: # %else2 -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: bnez a2, .LBB96_11 -; RV64ZVE32F-NEXT: .LBB96_3: # %else4 -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: bnez a2, .LBB96_12 -; RV64ZVE32F-NEXT: .LBB96_4: # %else6 -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: bnez a2, .LBB96_13 -; RV64ZVE32F-NEXT: .LBB96_5: # %else8 -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: bnez a2, .LBB96_14 -; RV64ZVE32F-NEXT: .LBB96_6: # %else10 -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: bnez a2, .LBB96_15 -; RV64ZVE32F-NEXT: .LBB96_7: # %else12 -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: bnez a1, .LBB96_16 -; RV64ZVE32F-NEXT: .LBB96_8: # %else14 -; RV64ZVE32F-NEXT: ret -; RV64ZVE32F-NEXT: .LBB96_9: # %cond.store -; RV64ZVE32F-NEXT: addi a2, a0, 8 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma -; RV64ZVE32F-NEXT: vse16.v v8, (a2) -; RV64ZVE32F-NEXT: andi a2, a1, 2 -; RV64ZVE32F-NEXT: beqz a2, .LBB96_2 -; RV64ZVE32F-NEXT: .LBB96_10: # %cond.store1 -; RV64ZVE32F-NEXT: addi a2, a0, 10 +; RV64ZVE32F-NEXT: addi a1, a0, 6 +; RV64ZVE32F-NEXT: addi a2, a0, 4 +; RV64ZVE32F-NEXT: addi a3, a0, 2 +; RV64ZVE32F-NEXT: addi a4, a0, 14 +; RV64ZVE32F-NEXT: addi a5, a0, 12 +; RV64ZVE32F-NEXT: addi a6, a0, 10 +; RV64ZVE32F-NEXT: addi a7, a0, 8 ; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vse16.v v8, (a7) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 -; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a2, a1, 4 -; RV64ZVE32F-NEXT: beqz a2, .LBB96_3 -; RV64ZVE32F-NEXT: .LBB96_11: # %cond.store3 -; RV64ZVE32F-NEXT: addi a2, a0, 12 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a6) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a2, a1, 8 -; RV64ZVE32F-NEXT: beqz a2, .LBB96_4 -; RV64ZVE32F-NEXT: .LBB96_12: # %cond.store5 -; RV64ZVE32F-NEXT: addi a2, a0, 14 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a5) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 3 -; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a2, a1, 16 -; RV64ZVE32F-NEXT: beqz a2, .LBB96_5 -; RV64ZVE32F-NEXT: .LBB96_13: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a4) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 4 ; RV64ZVE32F-NEXT: vse16.v v9, (a0) -; RV64ZVE32F-NEXT: andi a2, a1, 32 -; RV64ZVE32F-NEXT: beqz a2, .LBB96_6 -; RV64ZVE32F-NEXT: .LBB96_14: # %cond.store9 -; RV64ZVE32F-NEXT: addi a2, a0, 2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 5 -; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a2, a1, 64 -; RV64ZVE32F-NEXT: beqz a2, .LBB96_7 -; RV64ZVE32F-NEXT: .LBB96_15: # %cond.store11 -; RV64ZVE32F-NEXT: addi a2, a0, 4 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vse16.v v9, (a3) ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 6 ; RV64ZVE32F-NEXT: vse16.v v9, (a2) -; RV64ZVE32F-NEXT: andi a1, a1, -128 -; RV64ZVE32F-NEXT: beqz a1, .LBB96_8 -; RV64ZVE32F-NEXT: .LBB96_16: # %cond.store13 -; RV64ZVE32F-NEXT: addi a0, a0, 6 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7 -; RV64ZVE32F-NEXT: vse16.v v8, (a0) +; RV64ZVE32F-NEXT: vse16.v v8, (a1) ; RV64ZVE32F-NEXT: ret - %head = insertelement <8 x i1> poison, i1 true, i16 0 - %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> - call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> %allones) + call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> %val, <8 x ptr> %ptrs, i32 2, <8 x i1> splat (i1 true)) ret void } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll index 45215480166e..2c62cbd583d0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll @@ -1349,16 +1349,16 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vadd_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB108_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB108_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vadd.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1390,24 +1390,22 @@ define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV32-LABEL: vadd_vi_v32i64_unmasked: ; RV32: # %bb.0: -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB109_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB109_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: addi a1, a0, -16 @@ -1435,11 +1433,7 @@ define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vadd.vi v16, v16, -1 ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll index 3042d9dd1cbb..3db44e87109b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll @@ -1022,16 +1022,16 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vmax_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB74_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB74_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vmax.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1064,8 +1064,6 @@ define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmax.vx v16, v16, a2, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.smax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.smax.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll index 36a9e6d42fec..c97c2232715f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll @@ -1021,16 +1021,16 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV32-LABEL: vmaxu_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB74_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB74_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vmaxu.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1063,8 +1063,6 @@ define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmaxu.vx v16, v16, a2, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll index 8a6dccd76e9b..eaa19110a2a2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll @@ -1022,16 +1022,16 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV32-LABEL: vmin_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB74_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB74_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vmin.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1064,8 +1064,6 @@ define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmin.vx v16, v16, a2, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.smin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.smin.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll index a56514c70bb0..48175e5b905b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll @@ -1021,16 +1021,16 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV32-LABEL: vminu_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB74_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB74_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vminu.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1063,8 +1063,6 @@ define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vminu.vx v16, v16, a2, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll index 348b301ef255..291629de6dcf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll @@ -1362,16 +1362,16 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV32-LABEL: vsadd_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB108_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB108_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsadd.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1403,24 +1403,22 @@ define <32 x i64> @vsadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vsadd.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV32-LABEL: vsadd_vi_v32i64_unmasked: ; RV32: # %bb.0: -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB109_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB109_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsadd.vv v8, v8, v24 ; RV32-NEXT: addi a1, a0, -16 @@ -1448,11 +1446,7 @@ define <32 x i64> @vsadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsadd.vi v16, v16, -1 ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.sadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll index 658481746671..d38ee1148e89 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll @@ -1358,16 +1358,16 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e ; RV32-LABEL: vsaddu_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB108_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB108_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsaddu.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1399,24 +1399,22 @@ define <32 x i64> @vsaddu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vsaddu.vi v16, v16, -1, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV32-LABEL: vsaddu_vi_v32i64_unmasked: ; RV32: # %bb.0: -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB109_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB109_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsaddu.vv v8, v8, v24 ; RV32-NEXT: addi a1, a0, -16 @@ -1444,11 +1442,7 @@ define <32 x i64> @vsaddu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsaddu.vi v16, v16, -1 ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.uadd.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll index 586fef71796e..2caa2ff41a7d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll @@ -1402,16 +1402,16 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV32-LABEL: vssub_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB108_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB108_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vssub.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1444,24 +1444,22 @@ define <32 x i64> @vssub_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %ev ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vssub.vx v16, v16, a2, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV32-LABEL: vssub_vi_v32i64_unmasked: ; RV32: # %bb.0: -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB109_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB109_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vssub.vv v8, v8, v24 ; RV32-NEXT: addi a1, a0, -16 @@ -1490,11 +1488,7 @@ define <32 x i64> @vssub_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vssub.vx v16, v16, a2 ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.ssub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll index 5374e44bf9e8..6313f31bc1a6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll @@ -1397,16 +1397,16 @@ define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e ; RV32-LABEL: vssubu_vx_v32i64: ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma -; RV32-NEXT: vslidedown.vi v7, v0, 2 -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 +; RV32-NEXT: vslidedown.vi v7, v0, 2 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB108_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB108_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vssubu.vv v8, v8, v24, v0.t ; RV32-NEXT: addi a1, a0, -16 @@ -1439,24 +1439,22 @@ define <32 x i64> @vssubu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %e ; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vssubu.vx v16, v16, a2, v0.t ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> %m, i32 %evl) ret <32 x i64> %v } define <32 x i64> @vssubu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV32-LABEL: vssubu_vi_v32i64_unmasked: ; RV32: # %bb.0: -; RV32-NEXT: li a1, 32 -; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a2, 16 -; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: mv a1, a0 ; RV32-NEXT: bltu a0, a2, .LBB109_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: li a1, 16 ; RV32-NEXT: .LBB109_2: +; RV32-NEXT: li a2, 32 +; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma +; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vssubu.vv v8, v8, v24 ; RV32-NEXT: addi a1, a0, -16 @@ -1485,11 +1483,7 @@ define <32 x i64> @vssubu_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vssubu.vx v16, v16, a2 ; RV64-NEXT: ret - %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 - %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer - %head = insertelement <32 x i1> poison, i1 true, i32 0 - %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) + %v = call <32 x i64> @llvm.vp.usub.sat.v32i64(<32 x i64> %va, <32 x i64> splat (i64 -1), <32 x i1> splat (i1 true), i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll index c61d83256c70..b78b8663eac9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll @@ -616,8 +616,6 @@ define @vfmax_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 5 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -625,6 +623,8 @@ define @vfmax_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -705,9 +705,7 @@ define @vfmax_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maximum.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maximum.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll index bdf82f8b7135..69c76152910e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll @@ -616,8 +616,6 @@ define @vfmin_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 5 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -625,6 +623,8 @@ define @vfmin_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v7, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -705,9 +705,7 @@ define @vfmin_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minimum.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minimum.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll index 9ab7fdb82fd0..8bc233428265 100644 --- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll @@ -544,8 +544,6 @@ define @vp_nearbyint_nxv32f16_unmasked( ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -553,6 +551,8 @@ define @vp_nearbyint_nxv32f16_unmasked( ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -599,9 +599,7 @@ define @vp_nearbyint_nxv32f16_unmasked( ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.nearbyint.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.nearbyint.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll index fc5213b91e61..f934127f978d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll @@ -497,8 +497,6 @@ define @vp_rint_nxv32f16_unmasked( %va, ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -506,6 +504,8 @@ define @vp_rint_nxv32f16_unmasked( %va, ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -548,9 +548,7 @@ define @vp_rint_nxv32f16_unmasked( %va, ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.rint.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.rint.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll index c4e472acca6e..eb4994914fad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll @@ -545,8 +545,6 @@ define @vp_round_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -554,6 +552,8 @@ define @vp_round_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -600,9 +600,7 @@ define @vp_round_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.round.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.round.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll index 47edb4e64502..f366a2922d07 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll @@ -545,8 +545,6 @@ define @vp_roundeven_nxv32f16_unmasked( ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -554,6 +552,8 @@ define @vp_roundeven_nxv32f16_unmasked( ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -600,9 +600,7 @@ define @vp_roundeven_nxv32f16_unmasked( ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundeven.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundeven.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll index 9a67eb2b53b2..79c940bdf089 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll @@ -545,8 +545,6 @@ define @vp_roundtozero_nxv32f16_unmasked( @vp_roundtozero_nxv32f16_unmasked( @vp_roundtozero_nxv32f16_unmasked( poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.roundtozero.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.roundtozero.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll index 4e60077e5db9..939a45e15c10 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll @@ -301,8 +301,6 @@ define @vfsgnj_vv_nxv32f16_unmasked( %v ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -310,6 +308,8 @@ define @vfsgnj_vv_nxv32f16_unmasked( %v ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -338,9 +338,7 @@ define @vfsgnj_vv_nxv32f16_unmasked( %v ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.copysign.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.copysign.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll index 73a59932774d..df2bc523cd7a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll @@ -269,8 +269,6 @@ define @vfabs_vv_nxv32f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfabs_vv_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -278,6 +276,8 @@ define @vfabs_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -296,9 +296,7 @@ define @vfabs_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fabs.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fabs.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index 0c6a9792d7d2..c69a7bc5cece 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -625,8 +625,6 @@ define @vfadd_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -634,6 +632,8 @@ define @vfadd_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -662,9 +662,7 @@ define @vfadd_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv32f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv32f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -730,8 +728,6 @@ define @vfadd_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -739,6 +735,8 @@ define @vfadd_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -760,9 +758,7 @@ define @vfadd_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fadd.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fadd.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 0775a180d5ae..3ad17e85570a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -571,8 +571,6 @@ define @vfdiv_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -580,6 +578,8 @@ define @vfdiv_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -608,9 +608,7 @@ define @vfdiv_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv32f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv32f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -676,8 +674,6 @@ define @vfdiv_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -685,6 +681,8 @@ define @vfdiv_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -706,9 +704,7 @@ define @vfdiv_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fdiv.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fdiv.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll index 2c814016bc4b..7556b3ace5c6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll @@ -301,8 +301,6 @@ define @vfmax_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -310,6 +308,8 @@ define @vfmax_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -338,9 +338,7 @@ define @vfmax_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.maxnum.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.maxnum.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll index b830d31637dc..755c66537612 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll @@ -301,8 +301,6 @@ define @vfmin_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -310,6 +308,8 @@ define @vfmin_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -338,9 +338,7 @@ define @vfmin_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.minnum.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.minnum.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index ee7a7816c5fc..30d5919238cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -571,8 +571,6 @@ define @vfmul_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -580,6 +578,8 @@ define @vfmul_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -608,9 +608,7 @@ define @vfmul_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv32f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv32f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -676,8 +674,6 @@ define @vfmul_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -685,6 +681,8 @@ define @vfmul_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -706,9 +704,7 @@ define @vfmul_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fmul.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fmul.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll index 47a832af15e2..1db5fa1720a2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll @@ -269,8 +269,6 @@ define @vfneg_vv_nxv32f16_unmasked( %va ; ; ZVFHMIN-LABEL: vfneg_vv_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -278,6 +276,8 @@ define @vfneg_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -296,9 +296,7 @@ define @vfneg_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fneg.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.fneg.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll index f1b7b003f539..d6caad15e40a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll @@ -269,8 +269,6 @@ define @vfsqrt_vv_nxv32f16_unmasked( %v ; ; ZVFHMIN-LABEL: vfsqrt_vv_nxv32f16_unmasked: ; ZVFHMIN: # %bb.0: -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -278,6 +276,8 @@ define @vfsqrt_vv_nxv32f16_unmasked( %v ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -296,9 +296,7 @@ define @vfsqrt_vv_nxv32f16_unmasked( %v ; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.sqrt.nxv32f16( %va, %m, i32 %evl) + %v = call @llvm.vp.sqrt.nxv32f16( %va, splat (i1 true), i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index ca436e29c9de..2eae18d7cc49 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -571,8 +571,6 @@ define @vfsub_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: slli a1, a1, 3 ; ZVFHMIN-NEXT: sub sp, sp, a1 ; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -580,6 +578,8 @@ define @vfsub_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v24 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -608,9 +608,7 @@ define @vfsub_vv_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: add sp, sp, a0 ; ZVFHMIN-NEXT: addi sp, sp, 16 ; ZVFHMIN-NEXT: ret - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv32f16( %va, %b, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv32f16( %va, %b, splat (i1 true), i32 %evl) ret %v } @@ -676,8 +674,6 @@ define @vfsub_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: vfmv.v.f v16, fa5 ; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFHMIN-NEXT: vfncvt.f.f.w v4, v16 -; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma -; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: csrr a2, vlenb ; ZVFHMIN-NEXT: slli a1, a2, 1 ; ZVFHMIN-NEXT: sub a3, a0, a1 @@ -685,6 +681,8 @@ define @vfsub_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: addi a4, a4, -1 ; ZVFHMIN-NEXT: and a3, a4, a3 ; ZVFHMIN-NEXT: srli a2, a2, 2 +; ZVFHMIN-NEXT: vsetvli a4, zero, e8, m4, ta, ma +; ZVFHMIN-NEXT: vmset.m v16 ; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2 ; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma @@ -706,9 +704,7 @@ define @vfsub_vf_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: ret %elt.head = insertelement poison, half %b, i32 0 %vb = shufflevector %elt.head, poison, zeroinitializer - %head = insertelement poison, i1 true, i32 0 - %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.fsub.nxv32f16( %va, %vb, %m, i32 %evl) + %v = call @llvm.vp.fsub.nxv32f16( %va, %vb, splat (i1 true), i32 %evl) ret %v } -- GitLab From 45aec9a0b54e6d87abf75e960c96f59408edc706 Mon Sep 17 00:00:00 2001 From: Chuanqi Xu Date: Tue, 9 Apr 2024 17:49:11 +0800 Subject: [PATCH 261/695] [NFC] [Serialization] Remove redundant hasPendingBody member The hasPendingBody member is redundant with the PendingBodies.count(Decl*) method. This patch removes the redundant hasPendingBody member and the corresponding InterestingDecl struct. --- clang/include/clang/Serialization/ASTReader.h | 16 +------------- clang/lib/Serialization/ASTReaderDecl.cpp | 21 ++++++------------- 2 files changed, 7 insertions(+), 30 deletions(-) diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h index 370d8037a4da..1911252b34cd 100644 --- a/clang/include/clang/Serialization/ASTReader.h +++ b/clang/include/clang/Serialization/ASTReader.h @@ -1089,27 +1089,13 @@ private: /// the last time we loaded information about this identifier. llvm::DenseMap IdentifierGeneration; - class InterestingDecl { - Decl *D; - bool DeclHasPendingBody; - - public: - InterestingDecl(Decl *D, bool HasBody) - : D(D), DeclHasPendingBody(HasBody) {} - - Decl *getDecl() { return D; } - - /// Whether the declaration has a pending body. - bool hasPendingBody() { return DeclHasPendingBody; } - }; - /// Contains declarations and definitions that could be /// "interesting" to the ASTConsumer, when we get that AST consumer. /// /// "Interesting" declarations are those that have data that may /// need to be emitted, such as inline function definitions or /// Objective-C protocols. - std::deque PotentiallyInterestingDecls; + std::deque PotentiallyInterestingDecls; /// The list of deduced function types that we have not yet read, because /// they might contain a deduced return type that refers to a local type diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp index a22f760408c6..78448855fba0 100644 --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -94,8 +94,6 @@ namespace clang { GlobalDeclID NamedDeclForTagDecl = 0; IdentifierInfo *TypedefNameForLinkage = nullptr; - bool HasPendingBody = false; - ///A flag to carry the information for a decl from the entity is /// used. We use it to delay the marking of the canonical decl as used until /// the entire declaration is deserialized and merged. @@ -314,9 +312,6 @@ namespace clang { static void markIncompleteDeclChainImpl(Redeclarable *D); static void markIncompleteDeclChainImpl(...); - /// Determine whether this declaration has a pending body. - bool hasPendingBody() const { return HasPendingBody; } - void ReadFunctionDefinition(FunctionDecl *FD); void Visit(Decl *D); @@ -541,7 +536,6 @@ void ASTDeclReader::ReadFunctionDefinition(FunctionDecl *FD) { } // Store the offset of the body so we can lazily load it later. Reader.PendingBodies[FD] = GetCurrentCursorOffset(); - HasPendingBody = true; } void ASTDeclReader::Visit(Decl *D) { @@ -1164,7 +1158,6 @@ void ASTDeclReader::VisitObjCMethodDecl(ObjCMethodDecl *MD) { // Load the body on-demand. Most clients won't care, because method // definitions rarely show up in headers. Reader.PendingBodies[MD] = GetCurrentCursorOffset(); - HasPendingBody = true; } MD->setSelfDecl(readDeclAs()); MD->setCmdDecl(readDeclAs()); @@ -4156,8 +4149,7 @@ Decl *ASTReader::ReadDeclRecord(DeclID ID) { // AST consumer might need to know about, queue it. // We don't pass it to the consumer immediately because we may be in recursive // loading, and some declarations may still be initializing. - PotentiallyInterestingDecls.push_back( - InterestingDecl(D, Reader.hasPendingBody())); + PotentiallyInterestingDecls.push_back(D); return D; } @@ -4179,10 +4171,10 @@ void ASTReader::PassInterestingDeclsToConsumer() { EagerlyDeserializedDecls.clear(); while (!PotentiallyInterestingDecls.empty()) { - InterestingDecl D = PotentiallyInterestingDecls.front(); + Decl *D = PotentiallyInterestingDecls.front(); PotentiallyInterestingDecls.pop_front(); - if (isConsumerInterestedIn(getContext(), D.getDecl(), D.hasPendingBody())) - PassInterestingDeclToConsumer(D.getDecl()); + if (isConsumerInterestedIn(getContext(), D, PendingBodies.count(D))) + PassInterestingDeclToConsumer(D); } } @@ -4239,9 +4231,8 @@ void ASTReader::loadDeclUpdateRecords(PendingUpdateRecord &Record) { // We might have made this declaration interesting. If so, remember that // we need to hand it off to the consumer. if (!WasInteresting && - isConsumerInterestedIn(getContext(), D, Reader.hasPendingBody())) { - PotentiallyInterestingDecls.push_back( - InterestingDecl(D, Reader.hasPendingBody())); + isConsumerInterestedIn(getContext(), D, PendingBodies.count(D))) { + PotentiallyInterestingDecls.push_back(D); WasInteresting = true; } } -- GitLab From 0bbe953aa3289a32cd816647820c8676bb3a61bc Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 11:06:18 +0100 Subject: [PATCH 262/695] [X86] Fold extract_subvector(cvtps2dq(x),c) -> cvtps2dq(extract_subvector(x,c)) Help unblock #83402 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++++++ llvm/test/CodeGen/X86/vector-half-conversions.ll | 6 ++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f24e0fc25fac..d4d7b2959663 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -56158,6 +56158,13 @@ static SDValue combineEXTRACT_SUBVECTOR(SDNode *N, SelectionDAG &DAG, return DAG.getNode(X86ISD::VFPEXT, DL, VT, InVec.getOperand(0)); } } + // v4i32 CVTPS2DQ(v4f32). + if (InOpcode == ISD::FP_TO_SINT && VT == MVT::v4i32) { + SDValue Src = InVec.getOperand(0); + if (Src.getValueType().getScalarType() == MVT::f32) + return DAG.getNode(InOpcode, DL, VT, + extractSubVector(Src, IdxVal, DAG, DL, SizeInBits)); + } if (IdxVal == 0 && (ISD::isExtOpcode(InOpcode) || ISD::isExtVecInRegOpcode(InOpcode)) && (SizeInBits == 128 || SizeInBits == 256) && diff --git a/llvm/test/CodeGen/X86/vector-half-conversions.ll b/llvm/test/CodeGen/X86/vector-half-conversions.ll index 563cf0165013..a360cf8ca83d 100644 --- a/llvm/test/CodeGen/X86/vector-half-conversions.ll +++ b/llvm/test/CodeGen/X86/vector-half-conversions.ll @@ -5025,16 +5025,14 @@ define <4 x i32> @fptosi_4f16_to_4i32(<4 x half> %a) nounwind { ; F16C-LABEL: fptosi_4f16_to_4i32: ; F16C: # %bb.0: ; F16C-NEXT: vcvtph2ps %xmm0, %ymm0 -; F16C-NEXT: vcvttps2dq %ymm0, %ymm0 -; F16C-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 +; F16C-NEXT: vcvttps2dq %xmm0, %xmm0 ; F16C-NEXT: vzeroupper ; F16C-NEXT: retq ; ; AVX512-LABEL: fptosi_4f16_to_4i32: ; AVX512: # %bb.0: ; AVX512-NEXT: vcvtph2ps %xmm0, %ymm0 -; AVX512-NEXT: vcvttps2dq %ymm0, %ymm0 -; AVX512-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 +; AVX512-NEXT: vcvttps2dq %xmm0, %xmm0 ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %cvt = fptosi <4 x half> %a to <4 x i32> -- GitLab From c83698367125703827f1b739393f006c399cb213 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 9 Apr 2024 11:14:05 +0100 Subject: [PATCH 263/695] [VPlan] Remove unused first mask op from VPBlendRecipe. (#87770) VPBlendRecipe does not use the first mask operand. Removing it allows VPlan-based DCE to remove unused mask computations. This also fixes #87410, where unused Not VPInstructions are considered having only their first lane demanded, but some of their operands providing a vector value due to other users. Fixes https://github.com/llvm/llvm-project/issues/87410 PR: https://github.com/llvm/llvm-project/pull/87770 --- .../Transforms/Vectorize/LoopVectorize.cpp | 4 + llvm/lib/Transforms/Vectorize/VPlan.h | 21 +- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 2 + .../AArch64/sve-tail-folding-reductions.ll | 2 - .../Transforms/LoopVectorize/RISCV/divrem.ll | 15 -- .../RISCV/select-cmp-reduction.ll | 2 - .../LoopVectorize/RISCV/uniform-load-store.ll | 3 - .../X86/drop-poison-generating-flags.ll | 1 - .../X86/imprecise-through-phis.ll | 6 - .../LoopVectorize/X86/load-deref-pred.ll | 74 -------- .../LoopVectorize/X86/x86-predication.ll | 4 - .../LoopVectorize/if-pred-non-void.ll | 3 - .../Transforms/LoopVectorize/if-reduction.ll | 1 - .../LoopVectorize/load-deref-pred-align.ll | 2 - .../LoopVectorize/reduction-small-size.ll | 1 - .../LoopVectorize/select-cmp-predicated.ll | 3 - .../LoopVectorize/single-value-blend-phis.ll | 4 - .../Transforms/LoopVectorize/uniform-blend.ll | 3 - .../unused-blend-mask-for-first-operand.ll | 179 ++++++++++++++++++ .../LoopVectorize/vplan-printing.ll | 8 +- .../vplan-sink-scalars-and-merge.ll | 6 +- .../Transforms/Vectorize/VPlanTest.cpp | 10 +- 22 files changed, 209 insertions(+), 145 deletions(-) create mode 100644 llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index fd54faf17ca3..5535cc55e932 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -8221,6 +8221,8 @@ VPBlendRecipe *VPRecipeBuilder::tryToBlend(PHINode *Phi, // builder. At this point we generate the predication tree. There may be // duplications since this is a simple recursive scan, but future // optimizations will clean it up. + // TODO: At the moment the first mask is always skipped, but it would be + // better to skip the most expensive mask. SmallVector OperandsWithMask; for (unsigned In = 0; In < NumIncoming; In++) { @@ -8233,6 +8235,8 @@ VPBlendRecipe *VPRecipeBuilder::tryToBlend(PHINode *Phi, "Distinct incoming values with one having a full mask"); break; } + if (In == 0) + continue; OperandsWithMask.push_back(EdgeMask); } return new VPBlendRecipe(Phi, OperandsWithMask); diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 5f6334b974cf..5dc905a3c407 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -1932,14 +1932,12 @@ public: class VPBlendRecipe : public VPSingleDefRecipe { public: /// The blend operation is a User of the incoming values and of their - /// respective masks, ordered [I0, M0, I1, M1, ...]. Note that a single value - /// might be incoming with a full mask for which there is no VPValue. + /// respective masks, ordered [I0, I1, M1, I2, M2, ...]. Note that the first + /// incoming value does not have a mask associated. VPBlendRecipe(PHINode *Phi, ArrayRef Operands) : VPSingleDefRecipe(VPDef::VPBlendSC, Operands, Phi, Phi->getDebugLoc()) { - assert(Operands.size() > 0 && - ((Operands.size() == 1) || (Operands.size() % 2 == 0)) && - "Expected either a single incoming value or a positive even number " - "of operands"); + assert((Operands.size() + 1) % 2 == 0 && + "Expected an odd number of operands"); } VPRecipeBase *clone() override { @@ -1949,15 +1947,20 @@ public: VP_CLASSOF_IMPL(VPDef::VPBlendSC) - /// Return the number of incoming values, taking into account that a single + /// Return the number of incoming values, taking into account that the first /// incoming value has no mask. unsigned getNumIncomingValues() const { return (getNumOperands() + 1) / 2; } /// Return incoming value number \p Idx. - VPValue *getIncomingValue(unsigned Idx) const { return getOperand(Idx * 2); } + VPValue *getIncomingValue(unsigned Idx) const { + return Idx == 0 ? getOperand(0) : getOperand(Idx * 2 - 1); + } /// Return mask number \p Idx. - VPValue *getMask(unsigned Idx) const { return getOperand(Idx * 2 + 1); } + VPValue *getMask(unsigned Idx) const { + assert(Idx > 0 && "First index has no mask associated."); + return getOperand(Idx * 2); + } /// Generate the phi/select nodes. void execute(VPTransformState &State) override; diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 2438e4dae3eb..625319954e9b 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -1513,6 +1513,8 @@ void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent, for (unsigned I = 0, E = getNumIncomingValues(); I < E; ++I) { O << " "; getIncomingValue(I)->printAsOperand(O, SlotTracker); + if (I == 0) + continue; O << "/"; getMask(I)->printAsOperand(O, SlotTracker); } diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll index 9dcc751db7cf..c544d2a92e63 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-reductions.ll @@ -304,8 +304,6 @@ define i32 @cond_xor_reduction(ptr noalias %a, ptr noalias %cond, i64 %N) #0 { ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP14]], i32 0 ; CHECK-NEXT: [[WIDE_MASKED_LOAD1:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP16]], i32 4, [[TMP15]], poison) ; CHECK-NEXT: [[TMP17:%.*]] = xor [[VEC_PHI]], [[WIDE_MASKED_LOAD1]] -; CHECK-NEXT: [[TMP18:%.*]] = xor [[TMP13]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) -; CHECK-NEXT: [[TMP19:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP18]], zeroinitializer ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP15]], [[TMP17]], [[VEC_PHI]] ; CHECK-NEXT: [[TMP20]] = select [[ACTIVE_LANE_MASK]], [[PREDPHI]], [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP22]] diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll b/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll index dcd78aa7f1e3..7ca1b5395dd0 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll @@ -449,7 +449,6 @@ define void @predicated_udiv(ptr noalias nocapture %a, i64 %v, i64 %n) { ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne [[BROADCAST_SPLAT]], zeroinitializer ; CHECK-NEXT: [[TMP10:%.*]] = select [[TMP9]], [[BROADCAST_SPLAT]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP11:%.*]] = udiv [[WIDE_LOAD]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP9]], [[TMP11]], [[WIDE_LOAD]] ; CHECK-NEXT: store [[PREDPHI]], ptr [[TMP8]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] @@ -502,8 +501,6 @@ define void @predicated_udiv(ptr noalias nocapture %a, i64 %v, i64 %n) { ; FIXED-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[BROADCAST_SPLAT]], <4 x i64> ; FIXED-NEXT: [[TMP10:%.*]] = udiv <4 x i64> [[WIDE_LOAD]], [[TMP8]] ; FIXED-NEXT: [[TMP11:%.*]] = udiv <4 x i64> [[WIDE_LOAD1]], [[TMP9]] -; FIXED-NEXT: [[TMP12:%.*]] = xor <4 x i1> [[TMP6]], -; FIXED-NEXT: [[TMP13:%.*]] = xor <4 x i1> [[TMP7]], ; FIXED-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP10]], <4 x i64> [[WIDE_LOAD]] ; FIXED-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP11]], <4 x i64> [[WIDE_LOAD1]] ; FIXED-NEXT: store <4 x i64> [[PREDPHI]], ptr [[TMP4]], align 8 @@ -583,7 +580,6 @@ define void @predicated_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) { ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne [[BROADCAST_SPLAT]], zeroinitializer ; CHECK-NEXT: [[TMP10:%.*]] = select [[TMP9]], [[BROADCAST_SPLAT]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP11:%.*]] = sdiv [[WIDE_LOAD]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP9]], [[TMP11]], [[WIDE_LOAD]] ; CHECK-NEXT: store [[PREDPHI]], ptr [[TMP8]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] @@ -636,8 +632,6 @@ define void @predicated_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) { ; FIXED-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[BROADCAST_SPLAT]], <4 x i64> ; FIXED-NEXT: [[TMP10:%.*]] = sdiv <4 x i64> [[WIDE_LOAD]], [[TMP8]] ; FIXED-NEXT: [[TMP11:%.*]] = sdiv <4 x i64> [[WIDE_LOAD1]], [[TMP9]] -; FIXED-NEXT: [[TMP12:%.*]] = xor <4 x i1> [[TMP6]], -; FIXED-NEXT: [[TMP13:%.*]] = xor <4 x i1> [[TMP7]], ; FIXED-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP10]], <4 x i64> [[WIDE_LOAD]] ; FIXED-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP11]], <4 x i64> [[WIDE_LOAD1]] ; FIXED-NEXT: store <4 x i64> [[PREDPHI]], ptr [[TMP4]], align 8 @@ -714,7 +708,6 @@ define void @predicated_udiv_by_constant(ptr noalias nocapture %a, i64 %n) { ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP8]], align 8 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i64 42, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP10:%.*]] = udiv [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i64 27, i64 0), poison, zeroinitializer) -; CHECK-NEXT: [[TMP11:%.*]] = xor [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP9]], [[TMP10]], [[WIDE_LOAD]] ; CHECK-NEXT: store [[PREDPHI]], ptr [[TMP8]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] @@ -763,8 +756,6 @@ define void @predicated_udiv_by_constant(ptr noalias nocapture %a, i64 %n) { ; FIXED-NEXT: [[TMP7:%.*]] = icmp ne <4 x i64> [[WIDE_LOAD1]], ; FIXED-NEXT: [[TMP8:%.*]] = udiv <4 x i64> [[WIDE_LOAD]], ; FIXED-NEXT: [[TMP9:%.*]] = udiv <4 x i64> [[WIDE_LOAD1]], -; FIXED-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP6]], -; FIXED-NEXT: [[TMP11:%.*]] = xor <4 x i1> [[TMP7]], ; FIXED-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP8]], <4 x i64> [[WIDE_LOAD]] ; FIXED-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP9]], <4 x i64> [[WIDE_LOAD1]] ; FIXED-NEXT: store <4 x i64> [[PREDPHI]], ptr [[TMP4]], align 8 @@ -841,7 +832,6 @@ define void @predicated_sdiv_by_constant(ptr noalias nocapture %a, i64 %n) { ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP8]], align 8 ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i64 42, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP10:%.*]] = sdiv [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i64 27, i64 0), poison, zeroinitializer) -; CHECK-NEXT: [[TMP11:%.*]] = xor [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP9]], [[TMP10]], [[WIDE_LOAD]] ; CHECK-NEXT: store [[PREDPHI]], ptr [[TMP8]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] @@ -890,8 +880,6 @@ define void @predicated_sdiv_by_constant(ptr noalias nocapture %a, i64 %n) { ; FIXED-NEXT: [[TMP7:%.*]] = icmp ne <4 x i64> [[WIDE_LOAD1]], ; FIXED-NEXT: [[TMP8:%.*]] = sdiv <4 x i64> [[WIDE_LOAD]], ; FIXED-NEXT: [[TMP9:%.*]] = sdiv <4 x i64> [[WIDE_LOAD1]], -; FIXED-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP6]], -; FIXED-NEXT: [[TMP11:%.*]] = xor <4 x i1> [[TMP7]], ; FIXED-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[TMP8]], <4 x i64> [[WIDE_LOAD]] ; FIXED-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP7]], <4 x i64> [[TMP9]], <4 x i64> [[WIDE_LOAD1]] ; FIXED-NEXT: store <4 x i64> [[PREDPHI]], ptr [[TMP4]], align 8 @@ -969,7 +957,6 @@ define void @predicated_sdiv_by_minus_one(ptr noalias nocapture %a, i64 %n) { ; CHECK-NEXT: [[TMP9:%.*]] = icmp ne [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i8 -128, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP10:%.*]] = select [[TMP9]], shufflevector ( insertelement ( poison, i8 -1, i64 0), poison, zeroinitializer), shufflevector ( insertelement ( poison, i8 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP11:%.*]] = sdiv [[WIDE_LOAD]], [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = xor [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[PREDPHI:%.*]] = select [[TMP9]], [[TMP11]], [[WIDE_LOAD]] ; CHECK-NEXT: store [[PREDPHI]], ptr [[TMP8]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP5]] @@ -1020,8 +1007,6 @@ define void @predicated_sdiv_by_minus_one(ptr noalias nocapture %a, i64 %n) { ; FIXED-NEXT: [[TMP9:%.*]] = select <32 x i1> [[TMP7]], <32 x i8> , <32 x i8> ; FIXED-NEXT: [[TMP10:%.*]] = sdiv <32 x i8> [[WIDE_LOAD]], [[TMP8]] ; FIXED-NEXT: [[TMP11:%.*]] = sdiv <32 x i8> [[WIDE_LOAD1]], [[TMP9]] -; FIXED-NEXT: [[TMP12:%.*]] = xor <32 x i1> [[TMP6]], -; FIXED-NEXT: [[TMP13:%.*]] = xor <32 x i1> [[TMP7]], ; FIXED-NEXT: [[PREDPHI:%.*]] = select <32 x i1> [[TMP6]], <32 x i8> [[TMP10]], <32 x i8> [[WIDE_LOAD]] ; FIXED-NEXT: [[PREDPHI2:%.*]] = select <32 x i1> [[TMP7]], <32 x i8> [[TMP11]], <32 x i8> [[WIDE_LOAD1]] ; FIXED-NEXT: store <32 x i8> [[PREDPHI]], ptr [[TMP4]], align 1 diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll index a235da069b32..2b58acbfe9cc 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/select-cmp-reduction.ll @@ -402,7 +402,6 @@ define i32 @pred_select_const_i32_from_icmp(ptr noalias nocapture readonly %src1 ; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP6]], i32 4, <4 x i1> [[TMP4]], <4 x i32> poison) ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq <4 x i32> [[WIDE_MASKED_LOAD]], ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i1> [[VEC_PHI]], [[TMP8]] -; CHECK-NEXT: [[TMP10:%.*]] = xor <4 x i1> [[TMP4]], ; CHECK-NEXT: [[PREDPHI]] = select <4 x i1> [[TMP4]], <4 x i1> [[TMP9]], <4 x i1> [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] @@ -434,7 +433,6 @@ define i32 @pred_select_const_i32_from_icmp(ptr noalias nocapture readonly %src1 ; SCALABLE-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP10]], i32 4, [[TMP8]], poison) ; SCALABLE-NEXT: [[TMP12:%.*]] = icmp eq [[WIDE_MASKED_LOAD]], shufflevector ( insertelement ( poison, i32 2, i64 0), poison, zeroinitializer) ; SCALABLE-NEXT: [[TMP13:%.*]] = or [[VEC_PHI]], [[TMP12]] -; SCALABLE-NEXT: [[TMP14:%.*]] = xor [[TMP8]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; SCALABLE-NEXT: [[PREDPHI]] = select [[TMP8]], [[TMP13]], [[VEC_PHI]] ; SCALABLE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP16]] ; SCALABLE-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll index dcfa9bb105b6..1ce4cb928e80 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll @@ -346,7 +346,6 @@ define void @conditional_uniform_load(ptr noalias nocapture %a, ptr noalias noca ; SCALABLE-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 0 ; SCALABLE-NEXT: [[TMP11:%.*]] = icmp ugt [[VEC_IND]], shufflevector ( insertelement ( poison, i64 10, i64 0), poison, zeroinitializer) ; SCALABLE-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv2i64.nxv2p0( [[BROADCAST_SPLAT]], i32 8, [[TMP11]], poison) -; SCALABLE-NEXT: [[TMP12:%.*]] = xor [[TMP11]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) ; SCALABLE-NEXT: [[PREDPHI:%.*]] = select [[TMP11]], [[WIDE_MASKED_GATHER]], zeroinitializer ; SCALABLE-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP10]] ; SCALABLE-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP13]], i32 0 @@ -395,8 +394,6 @@ define void @conditional_uniform_load(ptr noalias nocapture %a, ptr noalias noca ; FIXEDLEN-NEXT: [[TMP3:%.*]] = icmp ugt <4 x i64> [[STEP_ADD]], ; FIXEDLEN-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> [[BROADCAST_SPLAT]], i32 8, <4 x i1> [[TMP2]], <4 x i64> poison) ; FIXEDLEN-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> [[BROADCAST_SPLAT]], i32 8, <4 x i1> [[TMP3]], <4 x i64> poison) -; FIXEDLEN-NEXT: [[TMP4:%.*]] = xor <4 x i1> [[TMP2]], -; FIXEDLEN-NEXT: [[TMP5:%.*]] = xor <4 x i1> [[TMP3]], ; FIXEDLEN-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP2]], <4 x i64> [[WIDE_MASKED_GATHER]], <4 x i64> zeroinitializer ; FIXEDLEN-NEXT: [[PREDPHI3:%.*]] = select <4 x i1> [[TMP3]], <4 x i64> [[WIDE_MASKED_GATHER2]], <4 x i64> zeroinitializer ; FIXEDLEN-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[TMP0]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll index 5944d9036b0a..fcc3864a7aeb 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll @@ -579,7 +579,6 @@ define void @Bgep_inbounds_unconditionally_due_to_store(ptr noalias %B, ptr read ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr float, ptr %B, i64 [[TMP0]] -; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP3]], ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[TMP4]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x float>, ptr [[TMP5]], align 4 ; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[WIDE_LOAD2]], diff --git a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll index 87f525fbce17..09fad39062a5 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll @@ -84,8 +84,6 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; SSE-NEXT: [[WIDE_LOAD2:%.*]] = load <2 x double>, ptr [[TMP5]], align 8 ; SSE-NEXT: [[TMP6:%.*]] = fcmp fast une <2 x double> [[WIDE_LOAD]], ; SSE-NEXT: [[TMP7:%.*]] = fcmp fast une <2 x double> [[WIDE_LOAD2]], -; SSE-NEXT: [[TMP8:%.*]] = xor <2 x i1> [[TMP6]], -; SSE-NEXT: [[TMP9:%.*]] = xor <2 x i1> [[TMP7]], ; SSE-NEXT: [[TMP10:%.*]] = fadd fast <2 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; SSE-NEXT: [[TMP11:%.*]] = fadd fast <2 x double> [[VEC_PHI1]], [[WIDE_LOAD2]] ; SSE-NEXT: [[PREDPHI]] = select <2 x i1> [[TMP6]], <2 x double> [[TMP10]], <2 x double> [[VEC_PHI]] @@ -153,10 +151,6 @@ define double @sumIfVector(ptr nocapture readonly %arr) { ; AVX-NEXT: [[TMP13:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD4]], ; AVX-NEXT: [[TMP14:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD5]], ; AVX-NEXT: [[TMP15:%.*]] = fcmp fast une <4 x double> [[WIDE_LOAD6]], -; AVX-NEXT: [[TMP16:%.*]] = xor <4 x i1> [[TMP12]], -; AVX-NEXT: [[TMP17:%.*]] = xor <4 x i1> [[TMP13]], -; AVX-NEXT: [[TMP18:%.*]] = xor <4 x i1> [[TMP14]], -; AVX-NEXT: [[TMP19:%.*]] = xor <4 x i1> [[TMP15]], ; AVX-NEXT: [[TMP20:%.*]] = fadd fast <4 x double> [[VEC_PHI]], [[WIDE_LOAD]] ; AVX-NEXT: [[TMP21:%.*]] = fadd fast <4 x double> [[VEC_PHI1]], [[WIDE_LOAD4]] ; AVX-NEXT: [[TMP22:%.*]] = fadd fast <4 x double> [[VEC_PHI2]], [[WIDE_LOAD5]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll b/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll index 91b8e149487a..8be359af9e6a 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll @@ -54,10 +54,6 @@ define i32 @test_explicit_pred(i64 %len) { ; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP13]], align 4 ; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP14]], align 4 ; CHECK-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4 -; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i1> [[TMP4]], -; CHECK-NEXT: [[TMP17:%.*]] = xor <4 x i1> [[TMP5]], -; CHECK-NEXT: [[TMP18:%.*]] = xor <4 x i1> [[TMP6]], -; CHECK-NEXT: [[TMP19:%.*]] = xor <4 x i1> [[TMP7]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP4]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI10:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[WIDE_LOAD7]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI11:%.*]] = select <4 x i1> [[TMP6]], <4 x i32> [[WIDE_LOAD8]], <4 x i32> zeroinitializer @@ -214,10 +210,6 @@ define i32 @test_explicit_pred_generic(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP69]], align 4 ; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4 ; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4 -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_LOAD5]], <4 x i32> zeroinitializer @@ -398,10 +390,6 @@ define i32 @test_invariant_address(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[TMP93:%.*]] = insertelement <4 x i32> [[TMP92]], i32 [[TMP89]], i32 1 ; CHECK-NEXT: [[TMP94:%.*]] = insertelement <4 x i32> [[TMP93]], i32 [[TMP90]], i32 2 ; CHECK-NEXT: [[TMP95:%.*]] = insertelement <4 x i32> [[TMP94]], i32 [[TMP91]], i32 3 -; CHECK-NEXT: [[TMP96:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP97:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP98:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP99:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP71]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP79]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer @@ -689,10 +677,6 @@ define i32 @test_step_narrower_than_access(i64 %len, ptr %test_base) { ; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE33]] ; CHECK: pred.load.continue33: ; CHECK-NEXT: [[TMP143:%.*]] = phi <4 x i32> [ [[TMP138]], [[PRED_LOAD_CONTINUE31]] ], [ [[TMP142]], [[PRED_LOAD_IF32]] ] -; CHECK-NEXT: [[TMP144:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP145:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP146:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP147:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP83]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI34:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI35:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP123]], <4 x i32> zeroinitializer @@ -855,10 +839,6 @@ define i32 @test_max_trip_count(i64 %len, ptr %test_base, i64 %n) { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP48]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP56]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP72]], i32 4, <4 x i1> [[TMP64]], <4 x i32> poison) -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP40]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP48]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP56]], -; CHECK-NEXT: [[TMP76:%.*]] = xor <4 x i1> [[TMP64]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP40]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP48]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP56]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -1022,10 +1002,6 @@ define i32 @test_non_zero_start(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP69]], align 4 ; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4 ; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4 -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_LOAD5]], <4 x i32> zeroinitializer @@ -1270,10 +1246,6 @@ define i32 @test_non_unit_stride(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 ; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 ; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 -; CHECK-NEXT: [[TMP112:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP113:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP114:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP115:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer @@ -1430,10 +1402,6 @@ define i32 @neg_off_by_many(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -1590,10 +1558,6 @@ define i32 @neg_off_by_one_iteration(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -1750,10 +1714,6 @@ define i32 @neg_off_by_one_byte(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -1919,10 +1879,6 @@ define i32 @test_constant_max(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP70]], align 4 ; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP71]], align 4 ; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP72]], align 4 -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP40]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP48]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP56]], -; CHECK-NEXT: [[TMP76:%.*]] = xor <4 x i1> [[TMP64]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP40]], <4 x i32> [[WIDE_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP48]], <4 x i32> [[WIDE_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP56]], <4 x i32> [[WIDE_LOAD5]], <4 x i32> zeroinitializer @@ -2087,10 +2043,6 @@ define i32 @test_allocsize(i64 %len, ptr %test_base) nofree nosync { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -2248,10 +2200,6 @@ define i32 @test_allocsize_array(i64 %len, ptr %test_base) nofree nosync { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -2419,10 +2367,6 @@ define i32 @test_allocsize_cond_deref(i1 %allzero, ptr %test_base) { ; CHECK-NEXT: [[WIDE_MASKED_LOAD4:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP69]], i32 4, <4 x i1> [[TMP47]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP70]], i32 4, <4 x i1> [[TMP55]], <4 x i32> poison) ; CHECK-NEXT: [[WIDE_MASKED_LOAD6:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[TMP71]], i32 4, <4 x i1> [[TMP63]], <4 x i32> poison) -; CHECK-NEXT: [[TMP72:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP73:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP74:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP75:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[WIDE_MASKED_LOAD]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI7:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[WIDE_MASKED_LOAD4]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI8:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[WIDE_MASKED_LOAD5]], <4 x i32> zeroinitializer @@ -2624,10 +2568,6 @@ define i32 @test_stride_three(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 ; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 ; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 -; CHECK-NEXT: [[TMP112:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP113:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP114:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP115:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer @@ -2763,8 +2703,6 @@ define i32 @test_non_unit_stride_four(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i32> [[TMP52]], i32 [[TMP49]], i32 1 ; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> [[TMP53]], i32 [[TMP50]], i32 2 ; CHECK-NEXT: [[TMP55:%.*]] = insertelement <4 x i32> [[TMP54]], i32 [[TMP51]], i32 3 -; CHECK-NEXT: [[TMP56:%.*]] = xor <4 x i1> [[TMP23]], -; CHECK-NEXT: [[TMP57:%.*]] = xor <4 x i1> [[TMP31]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP23]], <4 x i32> [[TMP47]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI2:%.*]] = select <4 x i1> [[TMP31]], <4 x i32> [[TMP55]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP58]] = add <4 x i32> [[VEC_PHI]], [[PREDPHI]] @@ -2952,10 +2890,6 @@ define i32 @test_non_unit_stride_five(i64 %len, ptr %test_base) { ; CHECK-NEXT: [[TMP109:%.*]] = insertelement <4 x i32> [[TMP108]], i32 [[TMP105]], i32 1 ; CHECK-NEXT: [[TMP110:%.*]] = insertelement <4 x i32> [[TMP109]], i32 [[TMP106]], i32 2 ; CHECK-NEXT: [[TMP111:%.*]] = insertelement <4 x i32> [[TMP110]], i32 [[TMP107]], i32 3 -; CHECK-NEXT: [[TMP112:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP113:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP114:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP115:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP87]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP95]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer @@ -3245,10 +3179,6 @@ define i32 @neg_test_non_unit_stride_off_by_four_bytes(i64 %len, ptr %test_base) ; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE33]] ; CHECK: pred.load.continue33: ; CHECK-NEXT: [[TMP143:%.*]] = phi <4 x i32> [ [[TMP138]], [[PRED_LOAD_CONTINUE31]] ], [ [[TMP142]], [[PRED_LOAD_IF32]] ] -; CHECK-NEXT: [[TMP144:%.*]] = xor <4 x i1> [[TMP39]], -; CHECK-NEXT: [[TMP145:%.*]] = xor <4 x i1> [[TMP47]], -; CHECK-NEXT: [[TMP146:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP147:%.*]] = xor <4 x i1> [[TMP63]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP39]], <4 x i32> [[TMP83]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI34:%.*]] = select <4 x i1> [[TMP47]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI35:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP123]], <4 x i32> zeroinitializer @@ -3459,10 +3389,6 @@ define i32 @test_non_unit_stride_with_first_iteration_step_access(i64 %len, ptr ; CHECK-NEXT: [[TMP125:%.*]] = insertelement <4 x i32> [[TMP124]], i32 [[TMP121]], i32 1 ; CHECK-NEXT: [[TMP126:%.*]] = insertelement <4 x i32> [[TMP125]], i32 [[TMP122]], i32 2 ; CHECK-NEXT: [[TMP127:%.*]] = insertelement <4 x i32> [[TMP126]], i32 [[TMP123]], i32 3 -; CHECK-NEXT: [[TMP128:%.*]] = xor <4 x i1> [[TMP55]], -; CHECK-NEXT: [[TMP129:%.*]] = xor <4 x i1> [[TMP63]], -; CHECK-NEXT: [[TMP130:%.*]] = xor <4 x i1> [[TMP71]], -; CHECK-NEXT: [[TMP131:%.*]] = xor <4 x i1> [[TMP79]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP55]], <4 x i32> [[TMP103]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI4:%.*]] = select <4 x i1> [[TMP63]], <4 x i32> [[TMP111]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[PREDPHI5:%.*]] = select <4 x i1> [[TMP71]], <4 x i32> [[TMP119]], <4 x i32> zeroinitializer diff --git a/llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll b/llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll index 91355728133d..86eba22d35a3 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/x86-predication.ll @@ -44,7 +44,6 @@ define i32 @predicated_sdiv_masked_load(ptr %a, ptr %b, i32 %x, i1 %c) { ; CHECK: pred.sdiv.continue2: ; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x i32> [ [[TMP9]], [[PRED_SDIV_CONTINUE]] ], [ [[TMP13]], [[PRED_SDIV_IF1]] ] ; CHECK-NEXT: [[TMP15:%.*]] = add nsw <2 x i32> [[TMP14]], [[WIDE_LOAD]] -; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[BROADCAST_SPLAT]], <2 x i32> [[TMP15]], <2 x i32> [[WIDE_LOAD]] ; CHECK-NEXT: [[TMP17]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 @@ -144,7 +143,6 @@ define i32 @predicated_sdiv_masked_load(ptr %a, ptr %b, i32 %x, i1 %c) { ; SINK-GATHER: pred.sdiv.continue14: ; SINK-GATHER-NEXT: [[TMP44:%.*]] = phi <8 x i32> [ [[TMP39]], [[PRED_SDIV_CONTINUE12]] ], [ [[TMP43]], [[PRED_SDIV_IF13]] ] ; SINK-GATHER-NEXT: [[TMP45:%.*]] = add nsw <8 x i32> [[TMP44]], [[WIDE_LOAD]] -; SINK-GATHER-NEXT: [[TMP46:%.*]] = xor <8 x i1> [[BROADCAST_SPLAT]], ; SINK-GATHER-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[BROADCAST_SPLAT]], <8 x i32> [[TMP45]], <8 x i32> [[WIDE_LOAD]] ; SINK-GATHER-NEXT: [[TMP47]] = add <8 x i32> [[VEC_PHI]], [[PREDPHI]] ; SINK-GATHER-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 @@ -254,7 +252,6 @@ define i32 @scalarize_and_sink_gather(ptr %a, i1 %c, i32 %x, i64 %n) { ; CHECK: pred.udiv.continue2: ; CHECK-NEXT: [[TMP15:%.*]] = phi i32 [ poison, [[PRED_UDIV_CONTINUE]] ], [ [[TMP12]], [[PRED_UDIV_IF1]] ] ; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i32> [ [[TMP8]], [[PRED_UDIV_CONTINUE]] ], [ [[TMP14]], [[PRED_UDIV_IF1]] ] -; CHECK-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[BROADCAST_SPLAT]], <2 x i32> [[TMP16]], <2 x i32> [[BROADCAST_SPLAT4]] ; CHECK-NEXT: [[TMP18]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 @@ -403,7 +400,6 @@ define i32 @scalarize_and_sink_gather(ptr %a, i1 %c, i32 %x, i64 %n) { ; SINK-GATHER: pred.udiv.continue14: ; SINK-GATHER-NEXT: [[TMP63:%.*]] = phi i32 [ poison, [[PRED_UDIV_CONTINUE12]] ], [ [[TMP60]], [[PRED_UDIV_IF13]] ] ; SINK-GATHER-NEXT: [[TMP64:%.*]] = phi <8 x i32> [ [[TMP56]], [[PRED_UDIV_CONTINUE12]] ], [ [[TMP62]], [[PRED_UDIV_IF13]] ] -; SINK-GATHER-NEXT: [[TMP65:%.*]] = xor <8 x i1> [[BROADCAST_SPLAT]], ; SINK-GATHER-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[BROADCAST_SPLAT]], <8 x i32> [[TMP64]], <8 x i32> [[BROADCAST_SPLAT16]] ; SINK-GATHER-NEXT: [[TMP66]] = add <8 x i32> [[VEC_PHI]], [[PREDPHI]] ; SINK-GATHER-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 diff --git a/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll b/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll index 7e0727348b01..692615a49ad9 100644 --- a/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll +++ b/llvm/test/Transforms/LoopVectorize/if-pred-non-void.ll @@ -791,7 +791,6 @@ define i32 @predicated_udiv_scalarized_operand(ptr %a, i1 %c, i32 %x, i64 %n) { ; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE2]] ; CHECK: pred.udiv.continue2: ; CHECK-NEXT: [[TMP16:%.*]] = phi <2 x i32> [ [[TMP9]], [[PRED_UDIV_CONTINUE]] ], [ [[TMP15]], [[PRED_UDIV_IF1]] ] -; CHECK-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[BROADCAST_SPLAT]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[BROADCAST_SPLAT]], <2 x i32> [[TMP16]], <2 x i32> [[WIDE_LOAD]] ; CHECK-NEXT: [[TMP18]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 @@ -858,8 +857,6 @@ define i32 @predicated_udiv_scalarized_operand(ptr %a, i1 %c, i32 %x, i64 %n) { ; UNROLL-NO-VF-NEXT: br label [[PRED_UDIV_CONTINUE3]] ; UNROLL-NO-VF: pred.udiv.continue3: ; UNROLL-NO-VF-NEXT: [[TMP11:%.*]] = phi i32 [ poison, [[PRED_UDIV_CONTINUE]] ], [ [[TMP10]], [[PRED_UDIV_IF2]] ] -; UNROLL-NO-VF-NEXT: [[TMP12:%.*]] = xor i1 [[C]], true -; UNROLL-NO-VF-NEXT: [[TMP13:%.*]] = xor i1 [[C]], true ; UNROLL-NO-VF-NEXT: [[PREDPHI:%.*]] = select i1 [[C]], i32 [[TMP8]], i32 [[TMP4]] ; UNROLL-NO-VF-NEXT: [[PREDPHI4:%.*]] = select i1 [[C]], i32 [[TMP11]], i32 [[TMP5]] ; UNROLL-NO-VF-NEXT: [[TMP14]] = add i32 [[VEC_PHI]], [[PREDPHI]] diff --git a/llvm/test/Transforms/LoopVectorize/if-reduction.ll b/llvm/test/Transforms/LoopVectorize/if-reduction.ll index d5a26e97eec3..e9761a60fd6e 100644 --- a/llvm/test/Transforms/LoopVectorize/if-reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/if-reduction.ll @@ -612,7 +612,6 @@ for.end: ; preds = %for.body, %entry ; CHECK: %[[C22:.*]] = select <4 x i1> %[[C11]], <4 x i1> %[[C21]], <4 x i1> zeroinitializer ; CHECK-DAG: %[[M1:.*]] = fmul fast <4 x float> %[[V0]], %[[V0]], %[[C11]], <4 x i1> %[[C2]], <4 x i1> zeroinitializer ; CHECK: %[[S1:.*]] = select <4 x i1> %[[C22]], <4 x float> %[[M1]], <4 x float> %[[M2]] ; CHECK: %[[S2:.*]] = select <4 x i1> %[[C1]], <4 x float> %[[V0]], <4 x float> %[[S1]] ; CHECK: fadd fast <4 x float> %[[S2]], diff --git a/llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll b/llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll index ba98391e0b0c..8d4be05a4390 100644 --- a/llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll +++ b/llvm/test/Transforms/LoopVectorize/load-deref-pred-align.ll @@ -42,7 +42,6 @@ define i16 @test_access_size_not_multiple_of_align(i64 %len, ptr %test_base) { ; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE2]] ; CHECK: pred.load.continue2: ; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x i16> [ [[TMP8]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP13]], [[PRED_LOAD_IF1]] ] -; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i1> [[TMP3]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i16> [[TMP14]], <2 x i16> zeroinitializer ; CHECK-NEXT: [[TMP16]] = add <2 x i16> [[VEC_PHI]], [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 @@ -140,7 +139,6 @@ define i32 @test_access_size_multiple_of_align_but_offset_by_1(i64 %len, ptr %te ; CHECK-NEXT: br label [[PRED_LOAD_CONTINUE2]] ; CHECK: pred.load.continue2: ; CHECK-NEXT: [[TMP14:%.*]] = phi <2 x i32> [ [[TMP8]], [[PRED_LOAD_CONTINUE]] ], [ [[TMP13]], [[PRED_LOAD_IF1]] ] -; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i1> [[TMP3]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP14]], <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP16]] = add <2 x i32> [[VEC_PHI]], [[PREDPHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 diff --git a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll index 2a58748d8fb6..337e1592a830 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction-small-size.ll @@ -95,7 +95,6 @@ define i8 @PR34687_no_undef(i1 %c, i32 %x, i32 %n) { ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP6:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i32> [[BROADCAST_SPLAT2]], <4 x i32> ; CHECK-NEXT: [[TMP1:%.*]] = sdiv <4 x i32> , [[TMP0]] -; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i1> [[BROADCAST_SPLAT]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[BROADCAST_SPLAT]], <4 x i32> [[TMP1]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP3:%.*]] = and <4 x i32> [[VEC_PHI]], ; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP3]], [[PREDPHI]] diff --git a/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll b/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll index cedc769b811f..6a9f83a9e0aa 100644 --- a/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll +++ b/llvm/test/Transforms/LoopVectorize/select-cmp-predicated.ll @@ -27,7 +27,6 @@ define i32 @pred_select_const_i32_from_icmp(ptr noalias nocapture readonly %src1 ; CHECK-VF2IC1-NEXT: [[TMP15:%.*]] = phi <2 x i32> [ [[TMP9]], %pred.load.continue ], [ [[TMP14]], %pred.load.if1 ] ; CHECK-VF2IC1-NEXT: [[TMP16:%.*]] = icmp eq <2 x i32> [[TMP15]], ; CHECK-VF2IC1-NEXT: [[TMP17:%.*]] = or <2 x i1> [[VEC_PHI]], [[TMP16]] -; CHECK-VF2IC1-NEXT: [[TMP18:%.*]] = xor <2 x i1> [[TMP4]], ; CHECK-VF2IC1-NEXT: [[PREDPHI]] = select <2 x i1> [[TMP4]], <2 x i1> [[TMP17]], <2 x i1> [[VEC_PHI]] ; CHECK-VF2IC1: br i1 {{%.*}}, label %middle.block, label %vector.body ; CHECK-VF2IC1: middle.block: @@ -82,8 +81,6 @@ define i32 @pred_select_const_i32_from_icmp(ptr noalias nocapture readonly %src1 ; CHECK-VF1IC2-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP11]], 2 ; CHECK-VF1IC2-NEXT: [[TMP14:%.*]] = or i1 [[VEC_PHI]], [[TMP12]] ; CHECK-VF1IC2-NEXT: [[TMP15:%.*]] = or i1 [[VEC_PHI2]], [[TMP13]] -; CHECK-VF1IC2-NEXT: [[TMP16:%.*]] = xor i1 [[TMP4]], true -; CHECK-VF1IC2-NEXT: [[TMP17:%.*]] = xor i1 [[TMP5]], true ; CHECK-VF1IC2-NEXT: [[PREDPHI]] = select i1 [[TMP4]], i1 [[TMP14]], i1 [[VEC_PHI]] ; CHECK-VF1IC2-NEXT: [[PREDPHI5]] = select i1 [[TMP5]], i1 [[TMP15]], i1 [[VEC_PHI2]] ; CHECK-VF1IC2: br i1 {{%.*}}, label %middle.block, label %vector.body diff --git a/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll b/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll index 3bf9e5b5dd03..7f8ad1db456c 100644 --- a/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll +++ b/llvm/test/Transforms/LoopVectorize/single-value-blend-phis.ll @@ -24,7 +24,6 @@ define void @single_incoming_phi_no_blend_mask(i64 %a, i64 %b) { ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i16>, ptr [[TMP4]], align 1 ; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt <2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP6:%.*]] = xor <2 x i1> [[TMP5]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP5]], <2 x i16> , <2 x i16> [[WIDE_LOAD]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP2]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i16, ptr [[TMP7]], i32 0 @@ -114,7 +113,6 @@ define void @single_incoming_phi_with_blend_mask(i64 %a, i64 %b) { ; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP3]], <2 x i1> [[TMP6]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = xor <2 x i1> [[TMP6]], ; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP3]], <2 x i1> [[TMP8]], <2 x i1> zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = xor <2 x i1> [[TMP3]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP9]], <2 x i16> [[WIDE_LOAD]], <2 x i16> zeroinitializer ; CHECK-NEXT: [[PREDPHI1:%.*]] = select <2 x i1> [[TMP10]], <2 x i16> , <2 x i16> [[PREDPHI]] ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP2]] @@ -198,7 +196,6 @@ define void @multiple_incoming_phi_with_blend_mask(i64 %a, ptr noalias %dst) { ; CHECK-NEXT: [[VEC_IND3:%.*]] = phi <2 x i16> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT4:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP2:%.*]] = xor <2 x i1> [[TMP1]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP1]], <2 x i16> [[VEC_IND3]], <2 x i16> [[VEC_IND1]] ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i16> [[PREDPHI]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [32 x i16], ptr @src, i16 0, i16 [[TMP3]] @@ -309,7 +306,6 @@ define void @single_incoming_needs_predication(i64 %a, i64 %b) { ; CHECK-NEXT: [[TMP19:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> [[TMP15]], <2 x i1> zeroinitializer ; CHECK-NEXT: [[TMP17:%.*]] = xor <2 x i1> [[TMP15]], ; CHECK-NEXT: [[TMP18:%.*]] = select <2 x i1> [[TMP2]], <2 x i1> [[TMP17]], <2 x i1> zeroinitializer -; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i1> [[TMP2]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <2 x i1> [[TMP18]], <2 x i16> [[TMP14]], <2 x i16> zeroinitializer ; CHECK-NEXT: [[PREDPHI3:%.*]] = select <2 x i1> [[TMP19]], <2 x i16> , <2 x i16> [[PREDPHI]] ; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP1]] diff --git a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll index c21b4d45e9a0..71eed3b2985d 100644 --- a/llvm/test/Transforms/LoopVectorize/uniform-blend.ll +++ b/llvm/test/Transforms/LoopVectorize/uniform-blend.ll @@ -14,7 +14,6 @@ define void @blend_uniform_iv_trunc(i1 %c) { ; CHECK-NEXT: [[TMP2:%.*]] = add i16 [[TMP1]], 0 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP2]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT1]], <4 x i16> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i1> [[MASK1]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[MASK1]], <4 x i16> [[BROADCAST_SPLAT2]], <4 x i16> undef ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[PREDPHI]], i32 0 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i16 [[TMP4]] @@ -58,7 +57,6 @@ define void @blend_uniform_iv(i1 %c) { ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[TMP0]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i1> [[MASK1]], ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[MASK1]], <4 x i64> [[BROADCAST_SPLAT2]], <4 x i64> undef ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[PREDPHI]], i32 0 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP2]] @@ -104,7 +102,6 @@ define void @blend_chain_iv(i1 %c) { ; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[MASK1]], <4 x i1> [[TMP4]], <4 x i1> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i1> [[TMP6]], [[TMP5]] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_IND]], <4 x i64> undef -; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[MASK1]], ; CHECK-NEXT: [[PREDPHI1:%.*]] = select <4 x i1> [[TMP8]], <4 x i64> [[PREDPHI]], <4 x i64> undef ; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i64> [[PREDPHI1]], i32 0 ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [32 x i16], ptr @dst, i16 0, i64 [[TMP9]] diff --git a/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll b/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll new file mode 100644 index 000000000000..c622925510dd --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/unused-blend-mask-for-first-operand.ll @@ -0,0 +1,179 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s + +target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" + +; Test cases for https://github.com/llvm/llvm-project/issues/87410. +define void @test_not_first_lane_only_constant(ptr %A, ptr noalias %B) { +; CHECK-LABEL: define void @test_not_first_lane_only_constant( +; CHECK-SAME: ptr [[A:%.*]], ptr noalias [[B:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x ptr> poison, ptr [[B]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x ptr> [[BROADCAST_SPLATINSERT3]], <4 x ptr> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 +; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[A]], i16 [[TMP0]] +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> zeroinitializer, <4 x ptr> poison, <4 x ptr> [[BROADCAST_SPLAT4]] +; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x ptr> [[PREDPHI]], i32 0 +; CHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[TMP12]], align 2 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i16> poison, i16 [[TMP13]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT5]], <4 x i16> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i32 0 +; CHECK-NEXT: store <4 x i16> [[BROADCAST_SPLAT6]], ptr [[TMP2]], align 2 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 +; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] +; CHECK: loop.header: +; CHECK-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i16, ptr [[A]], i16 [[IV]] +; CHECK-NEXT: br i1 false, label [[LOOP_LATCH]], label [[ELSE_1:%.*]] +; CHECK: else.1: +; CHECK-NEXT: br i1 false, label [[THEN_2:%.*]], label [[ELSE_2:%.*]] +; CHECK: then.2: +; CHECK-NEXT: br label [[ELSE_2]] +; CHECK: else.2: +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: loop.latch: +; CHECK-NEXT: [[MERGE:%.*]] = phi ptr [ [[B]], [[ELSE_2]] ], [ poison, [[LOOP_HEADER]] ] +; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[MERGE]], align 2 +; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1 +; CHECK-NEXT: store i16 [[L]], ptr [[GEP_A]], align 2 +; CHECK-NEXT: [[C_2:%.*]] = icmp eq i16 [[IV_NEXT]], 1000 +; CHECK-NEXT: br i1 [[C_2]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %iv = phi i16 [ 0, %entry ], [ %iv.next, %loop.latch ] + %gep.A = getelementptr inbounds i16, ptr %A, i16 %iv + br i1 false, label %loop.latch, label %else.1 + +else.1: + br i1 false, label %then.2, label %else.2 + +then.2: + br label %else.2 + +else.2: + br label %loop.latch + +loop.latch: + %merge = phi ptr [ %B, %else.2 ], [ poison, %loop.header ] + %l = load i16, ptr %merge, align 2 + %iv.next = add i16 %iv, 1 + store i16 %l, ptr %gep.A + %c.2 = icmp eq i16 %iv.next, 1000 + br i1 %c.2, label %exit, label %loop.header + +exit: + ret void +} + +define void @test_not_first_lane_only_wide_compare(ptr %A, ptr noalias %B, i16 %x, i16 %y) { +; CHECK-LABEL: define void @test_not_first_lane_only_wide_compare( +; CHECK-SAME: ptr [[A:%.*]], ptr noalias [[B:%.*]], i16 [[X:%.*]], i16 [[Y:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[X]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <4 x ptr> poison, ptr [[B]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <4 x ptr> [[BROADCAST_SPLATINSERT3]], <4 x ptr> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16 +; CHECK-NEXT: [[TMP0:%.*]] = add i16 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[A]], i16 [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i16, ptr [[TMP1]], i32 0 +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i16>, ptr [[TMP2]], align 2 +; CHECK-NEXT: [[TMP5:%.*]] = icmp ult <4 x i16> [[WIDE_LOAD]], [[BROADCAST_SPLAT2]] +; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP5]], <4 x ptr> poison, <4 x ptr> [[BROADCAST_SPLAT4]] +; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x ptr> [[PREDPHI]], i32 0 +; CHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[TMP12]], align 2 +; CHECK-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement <4 x i16> poison, i16 [[TMP13]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT5]], <4 x i16> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: store <4 x i16> [[BROADCAST_SPLAT6]], ptr [[TMP2]], align 2 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 +; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i16 [ 1000, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] +; CHECK: loop.header: +; CHECK-NEXT: [[IV:%.*]] = phi i16 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i16, ptr [[A]], i16 [[IV]] +; CHECK-NEXT: [[L_0:%.*]] = load i16, ptr [[GEP_A]], align 2 +; CHECK-NEXT: [[C_0:%.*]] = icmp ult i16 [[L_0]], [[X]] +; CHECK-NEXT: br i1 [[C_0]], label [[LOOP_LATCH]], label [[ELSE_1:%.*]] +; CHECK: else.1: +; CHECK-NEXT: [[C_1:%.*]] = icmp ult i16 [[L_0]], [[Y]] +; CHECK-NEXT: br i1 [[C_1]], label [[THEN_2:%.*]], label [[ELSE_2:%.*]] +; CHECK: then.2: +; CHECK-NEXT: br label [[ELSE_2]] +; CHECK: else.2: +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: loop.latch: +; CHECK-NEXT: [[MERGE:%.*]] = phi ptr [ [[B]], [[ELSE_2]] ], [ poison, [[LOOP_HEADER]] ] +; CHECK-NEXT: [[L:%.*]] = load i16, ptr [[MERGE]], align 2 +; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1 +; CHECK-NEXT: store i16 [[L]], ptr [[GEP_A]], align 2 +; CHECK-NEXT: [[C_2:%.*]] = icmp eq i16 [[IV_NEXT]], 1000 +; CHECK-NEXT: br i1 [[C_2]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %iv = phi i16 [ 0, %entry ], [ %iv.next, %loop.latch ] + %gep.A = getelementptr inbounds i16, ptr %A, i16 %iv + %l.0 = load i16, ptr %gep.A + %c.0 = icmp ult i16 %l.0, %x + br i1 %c.0, label %loop.latch, label %else.1 + +else.1: + %c.1 = icmp ult i16 %l.0, %y + br i1 %c.1, label %then.2, label %else.2 + +then.2: + br label %else.2 + +else.2: + br label %loop.latch + +loop.latch: + %merge = phi ptr [ %B, %else.2 ], [ poison, %loop.header ] + %l = load i16, ptr %merge, align 2 + %iv.next = add i16 %iv, 1 + store i16 %l, ptr %gep.A + %c.2 = icmp eq i16 %iv.next, 1000 + br i1 %c.2, label %exit, label %loop.header + +exit: + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} +;. diff --git a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll index 89178953010f..7056bbe6ba1b 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-printing.ll @@ -246,8 +246,7 @@ define void @print_replicate_predicated_phi(i64 %n, ptr %x) { ; CHECK-NEXT: Successor(s): if.then.0 ; CHECK-EMPTY: ; CHECK-NEXT: if.then.0: -; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%cmp> -; CHECK-NEXT: BLEND ir<%d> = ir<0>/vp<[[NOT]]> vp<[[PRED]]>/ir<%cmp> +; CHECK-NEXT: BLEND ir<%d> = ir<0> vp<[[PRED]]>/ir<%cmp> ; CHECK-NEXT: CLONE ir<%idx> = getelementptr ir<%x>, vp<[[STEPS]]> ; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = vector-pointer ir<%idx> ; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%d> @@ -455,7 +454,7 @@ define void @debug_loc_vpinstruction(ptr nocapture %asd, ptr nocapture %bsd) !db ; CHECK-NEXT: if.then.0: ; CHECK-NEXT: EMIT vp<[[NOT2:%.+]]> = not ir<%cmp2> ; CHECK-NEXT: EMIT vp<[[SEL2:%.+]]> = select vp<[[NOT1]]>, vp<[[NOT2]]>, ir -; CHECK-NEXT: BLEND ir<%ysd.0> = vp<[[PHI]]>/vp<[[OR1]]> ir<%psd>/vp<[[SEL2]]> +; CHECK-NEXT: BLEND ir<%ysd.0> = vp<[[PHI]]> ir<%psd>/vp<[[SEL2]]> ; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer ir<%isd> ; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%ysd.0> ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]> @@ -748,8 +747,7 @@ define void @print_call_flags(ptr readonly %src, ptr noalias %dest, i64 %n) { ; CHECK-EMPTY: ; CHECK-NEXT: if.then.1: ; CHECK-NEXT: WIDEN ir<%fadd> = fadd vp<[[PHI1]]>, vp<[[PHI2]]> -; CHECK-NEXT: EMIT vp<[[NOT_COND:%.+]]> = not ir<%ifcond> -; CHECK-NEXT: BLEND ir<%st.value> = ir<%ld.value>/vp<[[NOT_COND]]> ir<%fadd>/ir<%ifcond> +; CHECK-NEXT: BLEND ir<%st.value> = ir<%ld.value> ir<%fadd>/ir<%ifcond> ; CHECK-NEXT: CLONE ir<%st.addr> = getelementptr inbounds ir<%dest>, vp<[[STEPS]]> ; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = vector-pointer ir<%st.addr> ; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%st.value> diff --git a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll index 89b3a6da16c1..0cacb02dc489 100644 --- a/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll +++ b/llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll @@ -364,7 +364,7 @@ define void @pred_cfg1(i32 %k, i32 %j) { ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.1> ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]>, vp<[[NOT]]>, ir ; CHECK-NEXT: EMIT vp<[[OR:%.+]]> = or vp<[[MASK2]]>, vp<[[MASK3]]> -; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> +; CHECK-NEXT: BLEND ir<%p> = ir<0> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: ; CHECK-NEXT: pred.store: { @@ -465,7 +465,7 @@ define void @pred_cfg2(i32 %k, i32 %j) { ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.0> ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]>, vp<[[NOT]]>, ir ; CHECK-NEXT: EMIT vp<[[OR:%.+]]> = or vp<[[MASK2]]>, vp<[[MASK3]]> -; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> +; CHECK-NEXT: BLEND ir<%p> = ir<0> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[MASK4:%.+]]> = select vp<[[OR]]>, ir<%c.1>, ir ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: @@ -573,7 +573,7 @@ define void @pred_cfg3(i32 %k, i32 %j) { ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.0> ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]>, vp<[[NOT]]>, ir ; CHECK-NEXT: EMIT vp<[[MASK4:%.+]]> = or vp<[[MASK2]]>, vp<[[MASK3]]> -; CHECK-NEXT: BLEND ir<%p> = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]> +; CHECK-NEXT: BLEND ir<%p> = ir<0> vp<[[PRED]]>/vp<[[MASK2]]> ; CHECK-NEXT: EMIT vp<[[MASK5:%.+]]> = select vp<[[MASK4]]>, ir<%c.0>, ir ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp index 78d809296d4c..73687846e281 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp @@ -972,11 +972,13 @@ TEST(VPRecipeTest, CastVPBlendRecipeToVPUser) { IntegerType *Int32 = IntegerType::get(C, 32); auto *Phi = PHINode::Create(Int32, 1); - VPValue Op1; - VPValue Op2; + VPValue I1; + VPValue I2; + VPValue M2; SmallVector Args; - Args.push_back(&Op1); - Args.push_back(&Op2); + Args.push_back(&I1); + Args.push_back(&I2); + Args.push_back(&M2); VPBlendRecipe Recipe(Phi, Args); EXPECT_TRUE(isa(&Recipe)); VPRecipeBase *BaseR = &Recipe; -- GitLab From 321f8312b98620131ebb3b71fe15c0d6b2267488 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 9 Apr 2024 10:24:03 +0200 Subject: [PATCH 264/695] [clang][Interp] Diagnose comparisons with weak pointers --- clang/lib/AST/Interp/Interp.h | 12 ++++++++++++ clang/test/AST/Interp/weak.cpp | 15 +++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 clang/test/AST/Interp/weak.cpp diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 3dc223f97a8c..2c733c90f5f2 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -801,6 +801,18 @@ inline bool CmpHelperEQ(InterpState &S, CodePtr OpPC, CompareFn Fn) { return true; } + for (const auto &P : {LHS, RHS}) { + if (P.isZero()) + continue; + if (const ValueDecl *VD = P.getDeclDesc()->asValueDecl(); + VD && VD->isWeak()) { + const SourceInfo &Loc = S.Current->getSource(OpPC); + S.FFDiag(Loc, diag::note_constexpr_pointer_weak_comparison) + << P.toDiagnosticString(S.getCtx()); + return false; + } + } + if (!Pointer::hasSameBase(LHS, RHS)) { S.Stk.push(BoolT::from(Fn(ComparisonCategoryResult::Unordered))); return true; diff --git a/clang/test/AST/Interp/weak.cpp b/clang/test/AST/Interp/weak.cpp new file mode 100644 index 000000000000..d4aac3ff764d --- /dev/null +++ b/clang/test/AST/Interp/weak.cpp @@ -0,0 +1,15 @@ +// RUN: %clang_cc1 -std=c++20 -fexperimental-new-constant-interpreter -verify=expected,both %s +// RUN: %clang_cc1 -std=c++20 -verify=ref,both %s + + + + +/// FIXME: The new interpreter also emits the "address of weak declaration" note in the pointer-to-bool case. + +[[gnu::weak]] extern int a; +int ha[(bool)&a]; // both-warning {{variable length arrays in C++ are a Clang extension}} \ + // expected-note {{comparison against address of weak declaration}} \ + // both-error {{variable length array declaration not allowed at file scope}} +int ha2[&a == nullptr]; // both-warning {{variable length arrays in C++ are a Clang extension}} \ + // both-note {{comparison against address of weak declaration '&a' can only be performed at runtime}} \ + // both-error {{variable length array declaration not allowed at file scope}} -- GitLab From 5d7d6ad663f80fbc6161da1175476bb663301c46 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 9 Apr 2024 11:58:57 +0200 Subject: [PATCH 265/695] [clang][Interp] Add toAPValue unittests --- clang/unittests/AST/Interp/CMakeLists.txt | 1 + clang/unittests/AST/Interp/toAPValue.cpp | 90 +++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 clang/unittests/AST/Interp/toAPValue.cpp diff --git a/clang/unittests/AST/Interp/CMakeLists.txt b/clang/unittests/AST/Interp/CMakeLists.txt index 8fa5c85064db..ea727cdd4412 100644 --- a/clang/unittests/AST/Interp/CMakeLists.txt +++ b/clang/unittests/AST/Interp/CMakeLists.txt @@ -1,5 +1,6 @@ add_clang_unittest(InterpTests Descriptor.cpp + toAPValue.cpp ) clang_target_link_libraries(InterpTests diff --git a/clang/unittests/AST/Interp/toAPValue.cpp b/clang/unittests/AST/Interp/toAPValue.cpp new file mode 100644 index 000000000000..d0dfb40d5149 --- /dev/null +++ b/clang/unittests/AST/Interp/toAPValue.cpp @@ -0,0 +1,90 @@ +#include "../../../lib/AST/Interp/Context.h" +#include "../../../lib/AST/Interp/Descriptor.h" +#include "../../../lib/AST/Interp/Program.h" +#include "clang/AST/ASTContext.h" +#include "clang/AST/Decl.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" +#include "clang/Tooling/Tooling.h" +#include "gtest/gtest.h" + +using namespace clang; +using namespace clang::interp; +using namespace clang::ast_matchers; + +/// Test the various toAPValue implementations. +TEST(ToAPValue, Pointers) { + constexpr char Code[] = + "struct A { bool a; bool z; };\n" + "struct S {\n" + " A a[3];\n" + "};\n" + "constexpr S d = {{{true, false}, {false, true}, {false, false}}};\n" + "constexpr const bool *b = &d.a[1].z;\n"; + + auto AST = tooling::buildASTFromCodeWithArgs( + Code, {"-fexperimental-new-constant-interpreter"}); + + auto &Ctx = AST->getASTContext().getInterpContext(); + Program &Prog = Ctx.getProgram(); + + auto getDecl = [&](const char *Name) -> const ValueDecl * { + auto Nodes = + match(valueDecl(hasName(Name)).bind("var"), AST->getASTContext()); + assert(Nodes.size() == 1); + const auto *D = Nodes[0].getNodeAs("var"); + assert(D); + return D; + }; + auto getGlobalPtr = [&](const char *Name) -> Pointer { + const VarDecl *D = cast(getDecl(Name)); + return Prog.getPtrGlobal(*Prog.getGlobal(D)); + }; + + const Pointer &GP = getGlobalPtr("b"); + const Pointer &P = GP.deref(); + ASSERT_TRUE(P.isLive()); + APValue A = P.toAPValue(); + ASSERT_TRUE(A.isLValue()); + ASSERT_TRUE(A.hasLValuePath()); + const auto &Path = A.getLValuePath(); + ASSERT_EQ(Path.size(), 3u); + ASSERT_EQ(A.getLValueBase(), getDecl("d")); +} + +TEST(ToAPValue, FunctionPointers) { + constexpr char Code[] = " constexpr bool foo() { return true; }\n" + " constexpr bool (*func)() = foo;\n"; + + auto AST = tooling::buildASTFromCodeWithArgs( + Code, {"-fexperimental-new-constant-interpreter"}); + + auto &Ctx = AST->getASTContext().getInterpContext(); + Program &Prog = Ctx.getProgram(); + + auto getDecl = [&](const char *Name) -> const ValueDecl * { + auto Nodes = + match(valueDecl(hasName(Name)).bind("var"), AST->getASTContext()); + assert(Nodes.size() == 1); + const auto *D = Nodes[0].getNodeAs("var"); + assert(D); + return D; + }; + + auto getGlobalPtr = [&](const char *Name) -> Pointer { + const VarDecl *D = cast(getDecl(Name)); + return Prog.getPtrGlobal(*Prog.getGlobal(D)); + }; + + const Pointer &GP = getGlobalPtr("func"); + const FunctionPointer &FP = GP.deref(); + ASSERT_FALSE(FP.isZero()); + APValue A = FP.toAPValue(); + ASSERT_TRUE(A.hasValue()); + ASSERT_TRUE(A.isLValue()); + ASSERT_TRUE(A.hasLValuePath()); + const auto &Path = A.getLValuePath(); + ASSERT_EQ(Path.size(), 0u); + ASSERT_FALSE(A.getLValueBase().isNull()); + ASSERT_EQ(A.getLValueBase().dyn_cast(), getDecl("foo")); +} -- GitLab From 8795822f6ae2e82e23f7fd87a84d6d273e6c04ac Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Tue, 9 Apr 2024 12:19:53 +0100 Subject: [PATCH 266/695] [NFC][LLVM][CodeGen] Refactor SVE unpredicated binop isel patterns. (#84045) Create PatFrags for fadd, fmul, fsub, mul, smulh and umulh so that a single set of patterns can be used. Patch then removes unused classes and some redundant whitespace. --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 39 ++++++++++++++----- llvm/lib/Target/AArch64/SVEInstrFormats.td | 35 +++-------------- 2 files changed, 35 insertions(+), 39 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index dd5e11c0f5e3..a519d81362a7 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -487,6 +487,27 @@ def AArch64fmaxnm_m1 : VSelectCommPredOrPassthruPatFrags; def AArch64fmax_m1 : VSelectCommPredOrPassthruPatFrags; +def AArch64fadd : PatFrags<(ops node:$op1, node:$op2), + [(fadd node:$op1, node:$op2), + (AArch64fadd_p (SVEAllActive), node:$op1, node:$op2)]>; + +def AArch64fmul : PatFrags<(ops node:$op1, node:$op2), + [(fmul node:$op1, node:$op2), + (AArch64fmul_p (SVEAllActive), node:$op1, node:$op2)]>; + +def AArch64fsub : PatFrags<(ops node:$op1, node:$op2), + [(fsub node:$op1, node:$op2), + (AArch64fsub_p (SVEAllActive), node:$op1, node:$op2)]>; + +def AArch64mul : PatFrag<(ops node:$op1, node:$op2), + (AArch64mul_p (SVEAnyPredicate), node:$op1, node:$op2)>; + +def AArch64smulh : PatFrag<(ops node:$op1, node:$op2), + (AArch64smulh_p (SVEAnyPredicate), node:$op1, node:$op2)>; + +def AArch64umulh : PatFrag<(ops node:$op1, node:$op2), + (AArch64umulh_p (SVEAnyPredicate), node:$op1, node:$op2)>; + let Predicates = [HasSVE] in { def RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr", int_aarch64_sve_rdffr_z>; def RDFFRS_PPz : sve_int_rdffr_pred<0b1, "rdffrs">; @@ -705,9 +726,9 @@ let Predicates = [HasSVEorSME, UseExperimentalZeroingPseudos] in { } // End HasSVEorSME, UseExperimentalZeroingPseudos let Predicates = [HasSVEorSME] in { - defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd", fadd, AArch64fadd_p>; - defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub", fsub, AArch64fsub_p>; - defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", fmul, AArch64fmul_p>; + defm FADD_ZZZ : sve_fp_3op_u_zd<0b000, "fadd", AArch64fadd>; + defm FSUB_ZZZ : sve_fp_3op_u_zd<0b001, "fsub", AArch64fsub>; + defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul", AArch64fmul>; } // End HasSVEorSME let Predicates = [HasSVE] in { @@ -3402,9 +3423,9 @@ let Predicates = [HasSVE2orSME] in { defm SQRDMULH_ZZZ : sve2_int_mul<0b101, "sqrdmulh", int_aarch64_sve_sqrdmulh>; // SVE2 integer multiply vectors (unpredicated) - defm MUL_ZZZ : sve2_int_mul<0b000, "mul", null_frag, AArch64mul_p>; - defm SMULH_ZZZ : sve2_int_mul<0b010, "smulh", null_frag, AArch64smulh_p>; - defm UMULH_ZZZ : sve2_int_mul<0b011, "umulh", null_frag, AArch64umulh_p>; + defm MUL_ZZZ : sve2_int_mul<0b000, "mul", AArch64mul>; + defm SMULH_ZZZ : sve2_int_mul<0b010, "smulh", AArch64smulh>; + defm UMULH_ZZZ : sve2_int_mul<0b011, "umulh", AArch64umulh>; defm PMUL_ZZZ : sve2_int_mul_single<0b001, "pmul", int_aarch64_sve_pmul>; // SVE2 complex integer dot product (indexed) @@ -4059,9 +4080,9 @@ defm BFADD_ZPmZZ : sve2p1_bf_2op_p_zds<0b0000, "bfadd", "BFADD_ZPZZ", AArch64fad defm BFSUB_ZPmZZ : sve2p1_bf_2op_p_zds<0b0001, "bfsub", "BFSUB_ZPZZ", AArch64fsub_m1, DestructiveBinaryComm>; defm BFMUL_ZPmZZ : sve2p1_bf_2op_p_zds<0b0010, "bfmul", "BFMUL_ZPZZ", AArch64fmul_m1, DestructiveBinaryComm>; -defm BFADD_ZZZ : sve2p1_bf_3op_u_zd<0b000, "bfadd", fadd, AArch64fadd_p>; -defm BFSUB_ZZZ : sve2p1_bf_3op_u_zd<0b001, "bfsub", fsub, AArch64fsub_p>; -defm BFMUL_ZZZ : sve2p1_bf_3op_u_zd<0b010, "bfmul", fmul, AArch64fmul_p>; +defm BFADD_ZZZ : sve2p1_bf_3op_u_zd<0b000, "bfadd", AArch64fadd>; +defm BFSUB_ZZZ : sve2p1_bf_3op_u_zd<0b001, "bfsub", AArch64fsub>; +defm BFMUL_ZZZ : sve2p1_bf_3op_u_zd<0b010, "bfmul", AArch64fmul>; defm BFADD_ZPZZ : sve2p1_bf_bin_pred_zds; defm BFSUB_ZPZZ : sve2p1_bf_bin_pred_zds; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 1e76d58669da..ee8292fdd883 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -477,12 +477,6 @@ class SVE_2_Op_Pred_All_Active_Pt; -class SVE_2_Op_Pred_Any_Predicate -: Pat<(vtd (op (pt (SVEAnyPredicate)), vt1:$Op1, vt2:$Op2)), - (inst $Op1, $Op2)>; - class SVE_3_Op_Pat : Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)), @@ -550,11 +544,6 @@ class SVE_3_Op_Pat_Shift_Imm_SelZero -: Pat<(vtd (op vt1:$Op1)), - (inst (IMPLICIT_DEF), (ptrue 31), $Op1)>; - class SVE_2_Op_AllActive_Pat : Pat<(vtd (op vt1:$Op1, vt2:$Op2)), @@ -2278,8 +2267,7 @@ class sve_fp_3op_u_zd sz, bits<3> opc, string asm, ZPRRegOp zprty> let mayRaiseFPException = 1; } -multiclass sve_fp_3op_u_zd opc, string asm, SDPatternOperator op, - SDPatternOperator predicated_op = null_frag> { +multiclass sve_fp_3op_u_zd opc, string asm, SDPatternOperator op> { def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16>; def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32>; def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64>; @@ -2287,18 +2275,12 @@ multiclass sve_fp_3op_u_zd opc, string asm, SDPatternOperator op, def : SVE_2_Op_Pat(NAME # _H)>; def : SVE_2_Op_Pat(NAME # _S)>; def : SVE_2_Op_Pat(NAME # _D)>; - - def : SVE_2_Op_Pred_All_Active(NAME # _H)>; - def : SVE_2_Op_Pred_All_Active(NAME # _S)>; - def : SVE_2_Op_Pred_All_Active(NAME # _D)>; } -multiclass sve2p1_bf_3op_u_zd opc1, string asm, SDPatternOperator op, - SDPatternOperator predicated_op = null_frag> { - def NAME : sve_fp_3op_u_zd<0b00, opc1, asm, ZPR16>; - def : SVE_2_Op_Pat(NAME)>; +multiclass sve2p1_bf_3op_u_zd opc, string asm, SDPatternOperator op> { + def NAME : sve_fp_3op_u_zd<0b00, opc, asm, ZPR16>; - def : SVE_2_Op_Pred_All_Active(NAME)>; + def : SVE_2_Op_Pat(NAME)>; } multiclass sve_fp_3op_u_zd_ftsmul opc, string asm, SDPatternOperator op> { @@ -3684,8 +3666,7 @@ class sve2_int_mul sz, bits<3> opc, string asm, ZPRRegOp zprty> let hasSideEffects = 0; } -multiclass sve2_int_mul opc, string asm, SDPatternOperator op, - SDPatternOperator op_pred = null_frag> { +multiclass sve2_int_mul opc, string asm, SDPatternOperator op> { def _B : sve2_int_mul<0b00, opc, asm, ZPR8>; def _H : sve2_int_mul<0b01, opc, asm, ZPR16>; def _S : sve2_int_mul<0b10, opc, asm, ZPR32>; @@ -3695,11 +3676,6 @@ multiclass sve2_int_mul opc, string asm, SDPatternOperator op, def : SVE_2_Op_Pat(NAME # _H)>; def : SVE_2_Op_Pat(NAME # _S)>; def : SVE_2_Op_Pat(NAME # _D)>; - - def : SVE_2_Op_Pred_Any_Predicate(NAME # _B)>; - def : SVE_2_Op_Pred_Any_Predicate(NAME # _H)>; - def : SVE_2_Op_Pred_Any_Predicate(NAME # _S)>; - def : SVE_2_Op_Pred_Any_Predicate(NAME # _D)>; } multiclass sve2_int_mul_single opc, string asm, SDPatternOperator op> { @@ -4934,7 +4910,6 @@ multiclass sve2_int_bitwise_ternary_op opc, string asm, SDPatternOperato def : SVE_3_Op_Pat(NAME)>; def : SVE_3_Op_Pat(NAME)>; - def : SVE_3_Op_BSP_Pat(NAME)>; def : SVE_3_Op_BSP_Pat(NAME)>; def : SVE_3_Op_BSP_Pat(NAME)>; -- GitLab From 040e0d4fa45f3606fb584c2923dd111cca675feb Mon Sep 17 00:00:00 2001 From: Mats Petersson Date: Tue, 9 Apr 2024 12:54:24 +0100 Subject: [PATCH 267/695] [flang]Accept directive inside type definition (#87804) Some applications have alignment directives for members inside types. This allows those to be present, but generally getting ignored [with a warning] later on in the processing. This is just to allow the compilation to complete. --- flang/include/flang/Parser/parse-tree.h | 3 ++- flang/lib/Parser/Fortran-parsers.cpp | 3 ++- flang/test/Parser/compiler-directives.f90 | 4 ++++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index 26b2e5f4e34b..be59e3912a36 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -1097,7 +1097,8 @@ struct ProcComponentDefStmt { // R736 component-def-stmt -> data-component-def-stmt | proc-component-def-stmt struct ComponentDefStmt { UNION_CLASS_BOILERPLATE(ComponentDefStmt); - std::variant, ErrorRecovery // , TypeParamDefStmt -- PGI accidental extension, not enabled > u; diff --git a/flang/lib/Parser/Fortran-parsers.cpp b/flang/lib/Parser/Fortran-parsers.cpp index 21185694227d..5186d3baa54c 100644 --- a/flang/lib/Parser/Fortran-parsers.cpp +++ b/flang/lib/Parser/Fortran-parsers.cpp @@ -437,7 +437,8 @@ TYPE_PARSER(construct(name, maybe("=" >> scalarIntConstantExpr))) TYPE_PARSER(recovery( withMessage("expected component definition"_err_en_US, first(construct(Parser{}), - construct(Parser{}))), + construct(Parser{}), + construct(indirect(compilerDirective)))), construct(inStmtErrorRecovery))) // R737 data-component-def-stmt -> diff --git a/flang/test/Parser/compiler-directives.f90 b/flang/test/Parser/compiler-directives.f90 index 67e8d5b292aa..d4c99ae12f14 100644 --- a/flang/test/Parser/compiler-directives.f90 +++ b/flang/test/Parser/compiler-directives.f90 @@ -23,4 +23,8 @@ module m !dir$ optimize : 1 !dir$ loop count (10000) !dir$ loop count (1, 500, 5000, 10000) + type stuff + real(8), allocatable :: d(:) + !dir$ align : 1024 :: d + end type stuff end -- GitLab From bf0b21aa685264c65a2d7fd4a8b86e3c42dfd729 Mon Sep 17 00:00:00 2001 From: Hirofumi Nakamura Date: Tue, 9 Apr 2024 21:17:01 +0900 Subject: [PATCH 268/695] [clang-format] Remove trailing newlines in TableGen formatting test. (#87983) --- clang/unittests/Format/FormatTestTableGen.cpp | 103 +++++++++--------- 1 file changed, 51 insertions(+), 52 deletions(-) diff --git a/clang/unittests/Format/FormatTestTableGen.cpp b/clang/unittests/Format/FormatTestTableGen.cpp index d235c85c8eaa..79b6961b00b4 100644 --- a/clang/unittests/Format/FormatTestTableGen.cpp +++ b/clang/unittests/Format/FormatTestTableGen.cpp @@ -72,7 +72,7 @@ TEST_F(FormatTestTableGen, LiteralsAndIdentifiers) { " let 0startID = $TokVarName;\n" " let 0xstartInteger = 0x42;\n" " let someIdentifier = $TokVarName;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, BangOperators) { @@ -101,22 +101,22 @@ TEST_F(FormatTestTableGen, BangOperators) { " \"zerozero\",\n" " true: // default\n" " \"positivepositive\");\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, Include) { - verifyFormat("include \"test/IncludeFile.h\"\n"); + verifyFormat("include \"test/IncludeFile.h\""); } TEST_F(FormatTestTableGen, Types) { - verifyFormat("def Types : list, bits<3>, list> {}\n"); + verifyFormat("def Types : list, bits<3>, list> {}"); } TEST_F(FormatTestTableGen, SimpleValue1_SingleLiterals) { verifyFormat("def SimpleValue {\n" " let Integer = 42;\n" " let String = \"some string\";\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, SimpleValue1_MultilineString) { @@ -129,7 +129,7 @@ TEST_F(FormatTestTableGen, SimpleValue1_MultilineString) { "delimited by \\[{ and }\\]. It can break across lines and the line " "breaks are retained in the string. \n" "(https://llvm.org/docs/TableGen/ProgRef.html#grammar-token-TokCode)}];\n" - "}\n"; + "}"; StringRef DefWithCodeMessedUp = "def SimpleValueCode { let \n" "Code= \n" @@ -139,7 +139,7 @@ TEST_F(FormatTestTableGen, SimpleValue1_MultilineString) { "breaks are retained in the string. \n" "(https://llvm.org/docs/TableGen/ProgRef.html#grammar-token-TokCode)}] \n" " ; \n" - " } \n"; + " } "; verifyFormat(DefWithCode, DefWithCodeMessedUp); } @@ -147,15 +147,15 @@ TEST_F(FormatTestTableGen, SimpleValue2) { verifyFormat("def SimpleValue2 {\n" " let True = true;\n" " let False = false;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, SimpleValue3) { - verifyFormat("class SimpleValue3 { int Question = ?; }\n"); + verifyFormat("class SimpleValue3 { int Question = ?; }"); } TEST_F(FormatTestTableGen, SimpleValue4) { - verifyFormat("def SimpleValue4 { let ValueList = {1, 2, 3}; }\n"); + verifyFormat("def SimpleValue4 { let ValueList = {1, 2, 3}; }"); } TEST_F(FormatTestTableGen, SimpleValue5) { @@ -166,7 +166,7 @@ TEST_F(FormatTestTableGen, SimpleValue5) { " list>;\n" " let SquareBitsListWithType = [ {1, 2},\n" " {3, 4} ]>>;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, SimpleValue6) { @@ -184,15 +184,15 @@ TEST_F(FormatTestTableGen, SimpleValue6) { " );\n" " let DAGArgBang = (!cast(\"Some\") i32:$src1,\n" " i32:$src2);\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, SimpleValue7) { - verifyFormat("def SimpleValue7 { let Identifier = SimpleValue; }\n"); + verifyFormat("def SimpleValue7 { let Identifier = SimpleValue; }"); } TEST_F(FormatTestTableGen, SimpleValue8) { - verifyFormat("def SimpleValue8 { let Class = SimpleValue3<3>; }\n"); + verifyFormat("def SimpleValue8 { let Class = SimpleValue3<3>; }"); } TEST_F(FormatTestTableGen, ValueSuffix) { @@ -203,19 +203,18 @@ TEST_F(FormatTestTableGen, ValueSuffix) { " let Slice1 = value[1, ];\n" " let Slice2 = value[4...7, 17, 2...3, 4];\n" " let Field = value.field;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, PasteOperator) { - verifyFormat( - "def Paste#\"Operator\" { string Paste = \"Paste\"#operator; }\n"); + verifyFormat("def Paste#\"Operator\" { string Paste = \"Paste\"#operator; }"); verifyFormat("def [\"Traring\", \"Paste\"]# {\n" " string X = Traring#;\n" " string Y = List<\"Operator\">#;\n" " string Z = [\"Traring\", \"Paste\", \"Traring\", \"Paste\",\n" " \"Traring\", \"Paste\"]#;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, ClassDefinition) { @@ -229,9 +228,9 @@ TEST_F(FormatTestTableGen, ClassDefinition) { " defvar Item6 = 6;\n" " let Item7 = ?;\n" " assert !ge(x, 0), \"Assert7\";\n" - "}\n"); + "}"); - verifyFormat("class FPFormat val> { bits<3> Value = val; }\n"); + verifyFormat("class FPFormat val> { bits<3> Value = val; }"); } TEST_F(FormatTestTableGen, Def) { @@ -240,18 +239,18 @@ TEST_F(FormatTestTableGen, Def) { " let Item2{1, 3...4} = {1, 2};\n" " defvar Item3 = (ops nodty:$node1, nodty:$node2);\n" " assert !le(Item2, 0), \"Assert4\";\n" - "}\n"); + "}"); - verifyFormat("class FPFormat val> { bits<3> Value = val; }\n"); + verifyFormat("class FPFormat val> { bits<3> Value = val; }"); - verifyFormat("def NotFP : FPFormat<0>;\n"); + verifyFormat("def NotFP : FPFormat<0>;"); } TEST_F(FormatTestTableGen, Let) { verifyFormat("let x = 1, y = value,\n" " z = !and(!gt(!add(1, 2), !sub(3, 4)), !isa($x)) in {\n" " class Class1 : Parent { let Item1 = z; }\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, MultiClass) { @@ -287,7 +286,7 @@ TEST_F(FormatTestTableGen, MultiClass) { " }\n" " }\n" " }\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, MultiClassesWithPasteOperator) { @@ -297,25 +296,25 @@ TEST_F(FormatTestTableGen, MultiClassesWithPasteOperator) { " def : Def#x;\n" " def : Def#y;\n" "}\n" - "multiclass MultiClass2 { def : Def#x; }\n"); + "multiclass MultiClass2 { def : Def#x; }"); } TEST_F(FormatTestTableGen, Defm) { - verifyFormat("defm : Multiclass<0>;\n"); + verifyFormat("defm : Multiclass<0>;"); - verifyFormat("defm Defm1 : Multiclass<1>;\n"); + verifyFormat("defm Defm1 : Multiclass<1>;"); } TEST_F(FormatTestTableGen, Defset) { verifyFormat("defset list DefSet1 = {\n" " def Def1 : Class<1>;\n" " def Def2 : Class<2>;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, Defvar) { verifyFormat("defvar DefVar1 = !cond(!ge(!size(PaseOperator.Paste), 1): 1,\n" - " true: 0);\n"); + " true: 0);"); } TEST_F(FormatTestTableGen, ForEach) { @@ -325,21 +324,21 @@ TEST_F(FormatTestTableGen, ForEach) { " (!if(!lt(x, i),\n" " !shl(!mul(x, i), !size(\"string\")),\n" " !size(!strconcat(\"a\", \"b\", \"c\"))))>;\n" - "}\n"); + "}"); } -TEST_F(FormatTestTableGen, Dump) { verifyFormat("dump \"Dump\";\n"); } +TEST_F(FormatTestTableGen, Dump) { verifyFormat("dump \"Dump\";"); } TEST_F(FormatTestTableGen, If) { verifyFormat("if !gt(x, 0) then {\n" " def : IfThen;\n" "} else {\n" " def : IfElse;\n" - "}\n"); + "}"); } TEST_F(FormatTestTableGen, Assert) { - verifyFormat("assert !le(DefVar1, 0), \"Assert1\";\n"); + verifyFormat("assert !le(DefVar1, 0), \"Assert1\";"); } TEST_F(FormatTestTableGen, DAGArgBreakElements) { @@ -349,7 +348,7 @@ TEST_F(FormatTestTableGen, DAGArgBreakElements) { ASSERT_EQ(Style.TableGenBreakInsideDAGArg, FormatStyle::DAS_DontBreak); verifyFormat("def Def : Parent {\n" " let dagarg = (ins a:$src1, aa:$src2, aaa:$src3)\n" - "}\n", + "}", Style); // This option forces to break inside the DAGArg. Style.TableGenBreakInsideDAGArg = FormatStyle::DAS_BreakElements; @@ -357,13 +356,13 @@ TEST_F(FormatTestTableGen, DAGArgBreakElements) { " let dagarg = (ins a:$src1,\n" " aa:$src2,\n" " aaa:$src3);\n" - "}\n", + "}", Style); verifyFormat("def Def : Parent {\n" " let dagarg = (other a:$src1,\n" " aa:$src2,\n" " aaa:$src3);\n" - "}\n", + "}", Style); // Then, limit the DAGArg operator only to "ins". Style.TableGenBreakingDAGArgOperators = {"ins"}; @@ -371,11 +370,11 @@ TEST_F(FormatTestTableGen, DAGArgBreakElements) { " let dagarg = (ins a:$src1,\n" " aa:$src2,\n" " aaa:$src3);\n" - "}\n", + "}", Style); verifyFormat("def Def : Parent {\n" " let dagarg = (other a:$src1, aa:$src2, aaa:$src3)\n" - "}\n", + "}", Style); } @@ -385,7 +384,7 @@ TEST_F(FormatTestTableGen, DAGArgBreakAll) { // By default, the DAGArg does not have a break inside. verifyFormat("def Def : Parent {\n" " let dagarg = (ins a:$src1, aa:$src2, aaa:$src3)\n" - "}\n", + "}", Style); // This option forces to break inside the DAGArg. Style.TableGenBreakInsideDAGArg = FormatStyle::DAS_BreakAll; @@ -395,7 +394,7 @@ TEST_F(FormatTestTableGen, DAGArgBreakAll) { " aa:$src2,\n" " aaa:$src3\n" " );\n" - "}\n", + "}", Style); verifyFormat("def Def : Parent {\n" " let dagarg = (other\n" @@ -403,7 +402,7 @@ TEST_F(FormatTestTableGen, DAGArgBreakAll) { " aa:$src2,\n" " aaa:$src3\n" " );\n" - "}\n", + "}", Style); // Then, limit the DAGArg operator only to "ins". Style.TableGenBreakingDAGArgOperators = {"ins"}; @@ -413,11 +412,11 @@ TEST_F(FormatTestTableGen, DAGArgBreakAll) { " aa:$src2,\n" " aaa:$src3\n" " );\n" - "}\n", + "}", Style); verifyFormat("def Def : Parent {\n" " let dagarg = (other a:$src1, aa:$src2, aaa:$src3);\n" - "}\n", + "}", Style); } @@ -432,11 +431,11 @@ TEST_F(FormatTestTableGen, DAGArgAlignment) { " aa:$src2,\n" " aaa:$src3\n" " )\n" - "}\n", + "}", Style); verifyFormat("def Def : Parent {\n" " let dagarg = (not a:$src1, aa:$src2, aaa:$src2)\n" - "}\n", + "}", Style); Style.AlignConsecutiveTableGenBreakingDAGArgColons.Enabled = true; verifyFormat("def Def : Parent {\n" @@ -445,11 +444,11 @@ TEST_F(FormatTestTableGen, DAGArgAlignment) { " aa :$src2,\n" " aaa:$src3\n" " )\n" - "}\n", + "}", Style); verifyFormat("def Def : Parent {\n" " let dagarg = (not a:$src1, aa:$src2, aaa:$src2)\n" - "}\n", + "}", Style); } @@ -458,12 +457,12 @@ TEST_F(FormatTestTableGen, CondOperatorAlignment) { Style.ColumnLimit = 60; verifyFormat("let CondOpe1 = !cond(!eq(size, 1): 1,\n" " !eq(size, 16): 1,\n" - " true: 0);\n", + " true: 0);", Style); Style.AlignConsecutiveTableGenCondOperatorColons.Enabled = true; verifyFormat("let CondOpe1 = !cond(!eq(size, 1) : 1,\n" " !eq(size, 16): 1,\n" - " true : 0);\n", + " true : 0);", Style); } @@ -472,12 +471,12 @@ TEST_F(FormatTestTableGen, DefAlignment) { Style.ColumnLimit = 60; verifyFormat("def Def : Parent {}\n" "def DefDef : Parent {}\n" - "def DefDefDef : Parent {}\n", + "def DefDefDef : Parent {}", Style); Style.AlignConsecutiveTableGenDefinitionColons.Enabled = true; verifyFormat("def Def : Parent {}\n" "def DefDef : Parent {}\n" - "def DefDefDef : Parent {}\n", + "def DefDefDef : Parent {}", Style); } -- GitLab From 4023329bbfab5f2abc5c035aad05820724a484cf Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 12:33:47 +0100 Subject: [PATCH 269/695] [X86] collectConcatOps - add ability to recurse through insert_subvector chains Allows us to match insert_subvector(insert_subvector(undef, insert_subvector(insert_subvector(undef, x, 0), y, 1), 0), 0), insert_subvector(insert_subvector(undef, z, 0), w, 1), 2) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 16 +- .../vector-interleaved-store-i16-stride-4.ll | 849 ++++++++---------- .../vector-interleaved-store-i8-stride-8.ll | 786 +++++++--------- 3 files changed, 707 insertions(+), 944 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d4d7b2959663..5405c2921e51 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3992,7 +3992,6 @@ static bool collectConcatOps(SDNode *N, SmallVectorImpl &Ops, EVT VT = Src.getValueType(); EVT SubVT = Sub.getValueType(); - // TODO - Handle more general insert_subvector chains. if (VT.getSizeInBits() == (SubVT.getSizeInBits() * 2)) { // insert_subvector(undef, x, lo) if (Idx == 0 && Src.isUndef()) { @@ -4005,8 +4004,19 @@ static bool collectConcatOps(SDNode *N, SmallVectorImpl &Ops, if (Src.getOpcode() == ISD::INSERT_SUBVECTOR && Src.getOperand(1).getValueType() == SubVT && isNullConstant(Src.getOperand(2))) { - Ops.push_back(Src.getOperand(1)); - Ops.push_back(Sub); + // Attempt to recurse into inner (matching) concats. + SDValue Lo = Src.getOperand(1); + SDValue Hi = Sub; + SmallVector LoOps, HiOps; + if (collectConcatOps(Lo.getNode(), LoOps, DAG) && + collectConcatOps(Hi.getNode(), HiOps, DAG) && + LoOps.size() == HiOps.size()) { + Ops.append(LoOps); + Ops.append(HiOps); + return true; + } + Ops.push_back(Lo); + Ops.push_back(Hi); return true; } // insert_subvector(x, extract_subvector(x, lo), hi) diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll index 68b180ef5256..f054c7edfff1 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll @@ -1589,104 +1589,81 @@ define void @store_i16_stride4_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; ; AVX512-LABEL: store_i16_stride4_vf32: ; AVX512: # %bb.0: -; AVX512-NEXT: vmovdqa (%rcx), %xmm0 -; AVX512-NEXT: vmovdqa 16(%rcx), %xmm2 -; AVX512-NEXT: vmovdqa 32(%rcx), %xmm9 -; AVX512-NEXT: vmovdqa 48(%rcx), %xmm5 -; AVX512-NEXT: vmovdqa (%rdx), %xmm1 -; AVX512-NEXT: vmovdqa 16(%rdx), %xmm3 -; AVX512-NEXT: vmovdqa 32(%rdx), %xmm10 -; AVX512-NEXT: vmovdqa 48(%rdx), %xmm6 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm7 = xmm4[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm7, %ymm4 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 -; AVX512-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm13 -; AVX512-NEXT: vmovdqa (%rsi), %xmm2 -; AVX512-NEXT: vmovdqa 16(%rsi), %xmm4 -; AVX512-NEXT: vmovdqa 32(%rsi), %xmm11 -; AVX512-NEXT: vmovdqa 48(%rsi), %xmm7 -; AVX512-NEXT: vmovdqa (%rdi), %xmm3 -; AVX512-NEXT: vmovdqa 16(%rdi), %xmm14 -; AVX512-NEXT: vmovdqa 32(%rdi), %xmm12 -; AVX512-NEXT: vmovdqa 48(%rdi), %xmm8 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm4[4],xmm14[5],xmm4[5],xmm14[6],xmm4[6],xmm14[7],xmm4[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm15[0],zero,xmm15[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm4 = xmm14[0],xmm4[0],xmm14[1],xmm4[1],xmm14[2],xmm4[2],xmm14[3],xmm4[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm14 = xmm4[0],zero,xmm4[1],zero +; AVX512-NEXT: vmovdqa (%rsi), %xmm0 +; AVX512-NEXT: vmovdqa 16(%rsi), %xmm1 +; AVX512-NEXT: vmovdqa 32(%rsi), %xmm10 +; AVX512-NEXT: vmovdqa 48(%rsi), %xmm6 +; AVX512-NEXT: vmovdqa (%rdi), %xmm2 +; AVX512-NEXT: vmovdqa 16(%rdi), %xmm3 +; AVX512-NEXT: vmovdqa 32(%rdi), %xmm11 +; AVX512-NEXT: vmovdqa 48(%rdi), %xmm7 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm4[0],zero,xmm4[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm14, %ymm4 -; AVX512-NEXT: vinserti64x4 $1, %ymm15, %zmm4, %zmm4 +; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] +; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm1 +; AVX512-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1 +; AVX512-NEXT: vmovdqa (%rcx), %xmm3 +; AVX512-NEXT: vmovdqa 16(%rcx), %xmm5 +; AVX512-NEXT: vmovdqa 32(%rcx), %xmm12 +; AVX512-NEXT: vmovdqa 48(%rcx), %xmm8 +; AVX512-NEXT: vmovdqa (%rdx), %xmm4 +; AVX512-NEXT: vmovdqa 16(%rdx), %xmm13 +; AVX512-NEXT: vmovdqa 32(%rdx), %xmm14 +; AVX512-NEXT: vmovdqa 48(%rdx), %xmm9 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm13[4],xmm5[4],xmm13[5],xmm5[5],xmm13[6],xmm5[6],xmm13[7],xmm5[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm13[0],xmm5[0],xmm13[1],xmm5[1],xmm13[2],xmm5[2],xmm13[3],xmm5[3] +; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm5 = [0,0,1,1,2,2,3,3,16,16,17,17,18,18,19,19] +; AVX512-NEXT: vpermt2d %zmm15, %zmm5, %zmm13 ; AVX512-NEXT: movw $-21846, %ax # imm = 0xAAAA ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovdqa32 %zmm13, %zmm4 {%k1} -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm10[4],xmm9[4],xmm10[5],xmm9[5],xmm10[6],xmm9[6],xmm10[7],xmm9[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm14 = xmm13[0,0,1,1] +; AVX512-NEXT: vmovdqa32 %zmm13, %zmm1 {%k1} +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm13[0],zero,xmm13[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm13, %ymm14, %ymm13 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm10 = xmm9[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm9, %ymm10, %ymm9 -; AVX512-NEXT: vinserti64x4 $1, %ymm13, %zmm9, %zmm9 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm13 = xmm10[0],zero,xmm10[1],zero +; AVX512-NEXT: vinserti128 $1, %xmm13, %ymm15, %ymm13 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm11 = xmm10[0],zero,xmm10[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm10 = xmm10[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm10, %ymm13, %ymm10 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm11 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3] +; AVX512-NEXT: vinserti128 $1, %xmm10, %ymm11, %ymm10 +; AVX512-NEXT: vinserti64x4 $1, %ymm13, %zmm10, %zmm10 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm11 = xmm14[4],xmm12[4],xmm14[5],xmm12[5],xmm14[6],xmm12[6],xmm14[7],xmm12[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm14[0],xmm12[0],xmm14[1],xmm12[1],xmm14[2],xmm12[2],xmm14[3],xmm12[3] +; AVX512-NEXT: vpermt2d %zmm11, %zmm5, %zmm12 +; AVX512-NEXT: vmovdqa32 %zmm12, %zmm10 {%k1} +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm11 = xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7] ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm12 = xmm11[0],zero,xmm11[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm11 = xmm11[2,2,3,3] ; AVX512-NEXT: vinserti128 $1, %xmm11, %ymm12, %ymm11 -; AVX512-NEXT: vinserti64x4 $1, %ymm10, %zmm11, %zmm10 -; AVX512-NEXT: vmovdqa32 %zmm9, %zmm10 {%k1} -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm6[4],xmm5[4],xmm6[5],xmm5[5],xmm6[6],xmm5[6],xmm6[7],xmm5[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm11 = xmm9[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm9, %ymm11, %ymm9 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm5[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512-NEXT: vinserti64x4 $1, %ymm9, %zmm5, %zmm5 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm8[4],xmm7[4],xmm8[5],xmm7[5],xmm8[6],xmm7[6],xmm8[7],xmm7[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm9 = xmm6[0],zero,xmm6[1],zero +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm6[0],zero,xmm6[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm6, %ymm9, %ymm6 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3] +; AVX512-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6 +; AVX512-NEXT: vinserti64x4 $1, %ymm11, %zmm6, %zmm6 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm9[4],xmm8[4],xmm9[5],xmm8[5],xmm9[6],xmm8[6],xmm9[7],xmm8[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3] +; AVX512-NEXT: vpermt2d %zmm7, %zmm5, %zmm8 +; AVX512-NEXT: vmovdqa32 %zmm8, %zmm6 {%k1} +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm8 = xmm7[0],zero,xmm7[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3] ; AVX512-NEXT: vinserti128 $1, %xmm7, %ymm8, %ymm7 -; AVX512-NEXT: vinserti64x4 $1, %ymm6, %zmm7, %zmm6 -; AVX512-NEXT: vmovdqa32 %zmm5, %zmm6 {%k1} -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm7 = xmm5[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm5, %ymm7, %ymm5 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,0,1,1] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 -; AVX512-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm1[0],zero,xmm1[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm5, %ymm1 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm2[0],zero,xmm2[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 -; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1 -; AVX512-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} -; AVX512-NEXT: vmovdqa64 %zmm1, (%r8) +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0 +; AVX512-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm0 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; AVX512-NEXT: vpermt2d %zmm2, %zmm5, %zmm3 +; AVX512-NEXT: vmovdqa32 %zmm3, %zmm0 {%k1} +; AVX512-NEXT: vmovdqa64 %zmm0, (%r8) ; AVX512-NEXT: vmovdqa64 %zmm6, 192(%r8) ; AVX512-NEXT: vmovdqa64 %zmm10, 128(%r8) -; AVX512-NEXT: vmovdqa64 %zmm4, 64(%r8) +; AVX512-NEXT: vmovdqa64 %zmm1, 64(%r8) ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq ; @@ -1772,100 +1749,81 @@ define void @store_i16_stride4_vf32(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; ; AVX512DQ-LABEL: store_i16_stride4_vf32: ; AVX512DQ: # %bb.0: -; AVX512DQ-NEXT: vmovdqa (%rsi), %xmm1 -; AVX512DQ-NEXT: vmovdqa 16(%rsi), %xmm0 -; AVX512DQ-NEXT: vmovdqa 32(%rsi), %xmm7 -; AVX512DQ-NEXT: vmovdqa 48(%rsi), %xmm5 +; AVX512DQ-NEXT: vmovdqa (%rsi), %xmm0 +; AVX512DQ-NEXT: vmovdqa 16(%rsi), %xmm1 +; AVX512DQ-NEXT: vmovdqa 32(%rsi), %xmm10 +; AVX512DQ-NEXT: vmovdqa 48(%rsi), %xmm6 ; AVX512DQ-NEXT: vmovdqa (%rdi), %xmm2 ; AVX512DQ-NEXT: vmovdqa 16(%rdi), %xmm3 -; AVX512DQ-NEXT: vmovdqa 32(%rdi), %xmm10 -; AVX512DQ-NEXT: vmovdqa 48(%rdi), %xmm6 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm8 = xmm4[0],zero,xmm4[1],zero +; AVX512DQ-NEXT: vmovdqa 32(%rdi), %xmm11 +; AVX512DQ-NEXT: vmovdqa 48(%rdi), %xmm7 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm4[0],zero,xmm4[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm4, %ymm8, %ymm4 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm0 +; AVX512DQ-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm1, %ymm3, %ymm1 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm4, %zmm1, %zmm1 ; AVX512DQ-NEXT: vmovdqa (%rcx), %xmm3 -; AVX512DQ-NEXT: vmovdqa 16(%rcx), %xmm13 -; AVX512DQ-NEXT: vmovdqa 32(%rcx), %xmm11 +; AVX512DQ-NEXT: vmovdqa 16(%rcx), %xmm5 +; AVX512DQ-NEXT: vmovdqa 32(%rcx), %xmm12 ; AVX512DQ-NEXT: vmovdqa 48(%rcx), %xmm8 ; AVX512DQ-NEXT: vmovdqa (%rdx), %xmm4 -; AVX512DQ-NEXT: vmovdqa 16(%rdx), %xmm14 -; AVX512DQ-NEXT: vmovdqa 32(%rdx), %xmm12 +; AVX512DQ-NEXT: vmovdqa 16(%rdx), %xmm13 +; AVX512DQ-NEXT: vmovdqa 32(%rdx), %xmm14 ; AVX512DQ-NEXT: vmovdqa 48(%rdx), %xmm9 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm16 = xmm15[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm14 = xmm13[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm13, %ymm14, %ymm13 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm13[4],xmm5[4],xmm13[5],xmm5[5],xmm13[6],xmm5[6],xmm13[7],xmm5[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm13[0],xmm5[0],xmm13[1],xmm5[1],xmm13[2],xmm5[2],xmm13[3],xmm5[3] +; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm5 = [0,0,1,1,2,2,3,3,16,16,17,17,18,18,19,19] +; AVX512DQ-NEXT: vpermt2d %zmm15, %zmm5, %zmm13 ; AVX512DQ-NEXT: movw $-21846, %ax # imm = 0xAAAA ; AVX512DQ-NEXT: kmovw %eax, %k1 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm15, %zmm13, %zmm0 {%k1} -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm10[4],xmm7[4],xmm10[5],xmm7[5],xmm10[6],xmm7[6],xmm10[7],xmm7[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm14 = xmm13[0],zero,xmm13[1],zero +; AVX512DQ-NEXT: vmovdqa32 %zmm13, %zmm1 {%k1} +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm13[0],zero,xmm13[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm13, %ymm14, %ymm13 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm7 = xmm10[0],xmm7[0],xmm10[1],xmm7[1],xmm10[2],xmm7[2],xmm10[3],xmm7[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm10 = xmm7[0],zero,xmm7[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm7, %ymm10, %ymm7 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm13, %zmm7, %zmm7 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm10[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm10 = xmm10[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm10, %ymm13, %ymm10 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm11 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm12 = xmm11[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm11 = xmm11[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm11, %ymm12, %ymm11 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm10, %zmm11, %zmm7 {%k1} -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm10 = xmm6[4],xmm5[4],xmm6[5],xmm5[5],xmm6[6],xmm5[6],xmm6[7],xmm5[7] +; AVX512DQ-NEXT: vinserti128 $1, %xmm13, %ymm15, %ymm13 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm10 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3] ; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm11 = xmm10[0],zero,xmm10[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm10 = xmm10[2,2,3,3] ; AVX512DQ-NEXT: vinserti128 $1, %xmm10, %ymm11, %ymm10 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm5[0],zero,xmm5[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm10, %zmm5, %zmm5 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm9[4],xmm8[4],xmm9[5],xmm8[5],xmm9[6],xmm8[6],xmm9[7],xmm8[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm10 = xmm6[0,0,1,1] +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm13, %zmm10, %zmm10 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm11 = xmm14[4],xmm12[4],xmm14[5],xmm12[5],xmm14[6],xmm12[6],xmm14[7],xmm12[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm12 = xmm14[0],xmm12[0],xmm14[1],xmm12[1],xmm14[2],xmm12[2],xmm14[3],xmm12[3] +; AVX512DQ-NEXT: vpermt2d %zmm11, %zmm5, %zmm12 +; AVX512DQ-NEXT: vmovdqa32 %zmm12, %zmm10 {%k1} +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm11 = xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm12 = xmm11[0],zero,xmm11[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm11 = xmm11[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm11, %ymm12, %ymm11 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm6[0],zero,xmm6[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm10, %ymm6 +; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm11, %zmm6, %zmm6 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm9[4],xmm8[4],xmm9[5],xmm8[5],xmm9[6],xmm8[6],xmm9[7],xmm8[7] ; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm9 = xmm8[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm8, %ymm9, %ymm8 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm6, %zmm8, %zmm5 {%k1} -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm8 = xmm6[0],zero,xmm6[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm8, %ymm6 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm6, %zmm1, %zmm1 +; AVX512DQ-NEXT: vpermt2d %zmm7, %zmm5, %zmm8 +; AVX512DQ-NEXT: vmovdqa32 %zmm8, %zmm6 {%k1} +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm7 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm8 = xmm7[0],zero,xmm7[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm7 = xmm7[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm7, %ymm8, %ymm7 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm7, %zmm0, %zmm0 ; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm2[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2 ; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm2, %zmm3, %zmm1 {%k1} -; AVX512DQ-NEXT: vmovdqa64 %zmm1, (%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm5, 192(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm7, 128(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm0, 64(%r8) +; AVX512DQ-NEXT: vpermt2d %zmm2, %zmm5, %zmm3 +; AVX512DQ-NEXT: vmovdqa32 %zmm3, %zmm0 {%k1} +; AVX512DQ-NEXT: vmovdqa64 %zmm0, (%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm6, 192(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm10, 128(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm1, 64(%r8) ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; @@ -3112,201 +3070,155 @@ define void @store_i16_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; ; AVX512-LABEL: store_i16_stride4_vf64: ; AVX512: # %bb.0: -; AVX512-NEXT: vmovdqa64 (%rcx), %xmm20 -; AVX512-NEXT: vmovdqa 16(%rcx), %xmm2 -; AVX512-NEXT: vmovdqa 32(%rcx), %xmm10 -; AVX512-NEXT: vmovdqa 48(%rcx), %xmm5 -; AVX512-NEXT: vmovdqa (%rdx), %xmm1 -; AVX512-NEXT: vmovdqa 16(%rdx), %xmm3 -; AVX512-NEXT: vmovdqa 32(%rdx), %xmm11 -; AVX512-NEXT: vmovdqa 48(%rdx), %xmm6 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm7 = xmm4[0,0,1,1] +; AVX512-NEXT: vmovdqa64 (%rsi), %xmm19 +; AVX512-NEXT: vmovdqa 16(%rsi), %xmm0 +; AVX512-NEXT: vmovdqa 32(%rsi), %xmm11 +; AVX512-NEXT: vmovdqa 48(%rsi), %xmm6 +; AVX512-NEXT: vmovdqa64 (%rdi), %xmm20 +; AVX512-NEXT: vmovdqa 16(%rdi), %xmm3 +; AVX512-NEXT: vmovdqa 32(%rdi), %xmm12 +; AVX512-NEXT: vmovdqa 48(%rdi), %xmm7 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm4[0],zero,xmm4[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm7, %ymm4 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[1],xmm2[1],xmm3[2],xmm2[2],xmm3[3],xmm2[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 -; AVX512-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm9 -; AVX512-NEXT: vmovdqa (%rsi), %xmm2 -; AVX512-NEXT: vmovdqa 16(%rsi), %xmm3 -; AVX512-NEXT: vmovdqa 32(%rsi), %xmm12 -; AVX512-NEXT: vmovdqa 48(%rsi), %xmm7 -; AVX512-NEXT: vmovdqa (%rdi), %xmm4 -; AVX512-NEXT: vmovdqa 16(%rdi), %xmm14 -; AVX512-NEXT: vmovdqa 32(%rdi), %xmm13 -; AVX512-NEXT: vmovdqa 48(%rdi), %xmm8 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm3[4],xmm14[5],xmm3[5],xmm14[6],xmm3[6],xmm14[7],xmm3[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm15[0],zero,xmm15[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm14[0],xmm3[0],xmm14[1],xmm3[1],xmm14[2],xmm3[2],xmm14[3],xmm3[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm14 = xmm3[0],zero,xmm3[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm14, %ymm3 -; AVX512-NEXT: vinserti64x4 $1, %ymm15, %zmm3, %zmm17 +; AVX512-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0 +; AVX512-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm18 +; AVX512-NEXT: vmovdqa (%rcx), %xmm3 +; AVX512-NEXT: vmovdqa 16(%rcx), %xmm5 +; AVX512-NEXT: vmovdqa 32(%rcx), %xmm13 +; AVX512-NEXT: vmovdqa 48(%rcx), %xmm9 +; AVX512-NEXT: vmovdqa (%rdx), %xmm4 +; AVX512-NEXT: vmovdqa 16(%rdx), %xmm8 +; AVX512-NEXT: vmovdqa 32(%rdx), %xmm14 +; AVX512-NEXT: vmovdqa 48(%rdx), %xmm10 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm8[4],xmm5[4],xmm8[5],xmm5[5],xmm8[6],xmm5[6],xmm8[7],xmm5[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm8[0],xmm5[0],xmm8[1],xmm5[1],xmm8[2],xmm5[2],xmm8[3],xmm5[3] +; AVX512-NEXT: vpmovsxbd {{.*#+}} zmm5 = [0,0,1,1,2,2,3,3,16,16,17,17,18,18,19,19] +; AVX512-NEXT: vpermt2d %zmm15, %zmm5, %zmm8 ; AVX512-NEXT: movw $-21846, %ax # imm = 0xAAAA ; AVX512-NEXT: kmovw %eax, %k1 -; AVX512-NEXT: vmovdqa32 %zmm9, %zmm17 {%k1} -; AVX512-NEXT: vmovdqa 96(%rcx), %xmm9 -; AVX512-NEXT: vmovdqa 96(%rdx), %xmm14 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm9[4],xmm14[5],xmm9[5],xmm14[6],xmm9[6],xmm14[7],xmm9[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm16 = xmm15[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm14[0],xmm9[0],xmm14[1],xmm9[1],xmm14[2],xmm9[2],xmm14[3],xmm9[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm14 = xmm9[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm9, %ymm14, %ymm9 -; AVX512-NEXT: vinserti64x4 $1, %ymm15, %zmm9, %zmm14 -; AVX512-NEXT: vmovdqa 96(%rsi), %xmm9 +; AVX512-NEXT: vmovdqa32 %zmm8, %zmm18 {%k1} +; AVX512-NEXT: vmovdqa 96(%rsi), %xmm8 ; AVX512-NEXT: vmovdqa 96(%rdi), %xmm15 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm9[4],xmm15[5],xmm9[5],xmm15[6],xmm9[6],xmm15[7],xmm9[7] +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7] ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm0[0],zero,xmm0[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; AVX512-NEXT: vinserti32x4 $1, %xmm0, %ymm16, %ymm0 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm15[0],xmm9[0],xmm15[1],xmm9[1],xmm15[2],xmm9[2],xmm15[3],xmm9[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm9[0],zero,xmm9[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm9, %ymm15, %ymm9 -; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm9, %zmm18 -; AVX512-NEXT: vmovdqa32 %zmm14, %zmm18 {%k1} -; AVX512-NEXT: vmovdqa 112(%rcx), %xmm0 -; AVX512-NEXT: vmovdqa 112(%rdx), %xmm14 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm14[4],xmm0[4],xmm14[5],xmm0[5],xmm14[6],xmm0[6],xmm14[7],xmm0[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm16 = xmm15[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm14[0],xmm0[0],xmm14[1],xmm0[1],xmm14[2],xmm0[2],xmm14[3],xmm0[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm14 = xmm0[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm14, %ymm0 -; AVX512-NEXT: vinserti64x4 $1, %ymm15, %zmm0, %zmm0 -; AVX512-NEXT: vmovdqa 112(%rsi), %xmm14 -; AVX512-NEXT: vmovdqa 112(%rdi), %xmm15 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm3[0],zero,xmm3[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm3, %ymm16, %ymm3 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm14 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm14[0],zero,xmm14[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm14 = xmm14[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm14, %ymm15, %ymm14 -; AVX512-NEXT: vinserti64x4 $1, %ymm3, %zmm14, %zmm19 -; AVX512-NEXT: vmovdqa32 %zmm0, %zmm19 {%k1} -; AVX512-NEXT: vmovdqa 64(%rcx), %xmm0 -; AVX512-NEXT: vmovdqa 64(%rdx), %xmm3 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm16 = xmm15[0,0,1,1] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm8[0],zero,xmm8[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[2,2,3,3] +; AVX512-NEXT: vinserti128 $1, %xmm8, %ymm15, %ymm8 +; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm8, %zmm8 +; AVX512-NEXT: vmovdqa 96(%rcx), %xmm0 +; AVX512-NEXT: vmovdqa 96(%rdx), %xmm15 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm15[4],xmm0[4],xmm15[5],xmm0[5],xmm15[6],xmm0[6],xmm15[7],xmm0[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm0[0],xmm15[1],xmm0[1],xmm15[2],xmm0[2],xmm15[3],xmm0[3] +; AVX512-NEXT: vpermt2d %zmm1, %zmm5, %zmm0 +; AVX512-NEXT: vmovdqa32 %zmm0, %zmm8 {%k1} +; AVX512-NEXT: vmovdqa 112(%rsi), %xmm0 +; AVX512-NEXT: vmovdqa 112(%rdi), %xmm1 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm15[0],zero,xmm15[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] ; AVX512-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[0,0,1,1] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0 -; AVX512-NEXT: vinserti64x4 $1, %ymm15, %zmm0, %zmm0 -; AVX512-NEXT: vmovdqa 64(%rsi), %xmm3 -; AVX512-NEXT: vmovdqa 64(%rdi), %xmm15 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm15[4],xmm3[4],xmm15[5],xmm3[5],xmm15[6],xmm3[6],xmm15[7],xmm3[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm9[0],zero,xmm9[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm9, %ymm16, %ymm9 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm15[0],xmm3[0],xmm15[1],xmm3[1],xmm15[2],xmm3[2],xmm15[3],xmm3[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm3[0],zero,xmm3[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm15, %ymm3 -; AVX512-NEXT: vinserti64x4 $1, %ymm9, %zmm3, %zmm15 +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512-NEXT: vinserti64x4 $1, %ymm15, %zmm0, %zmm15 +; AVX512-NEXT: vmovdqa 112(%rcx), %xmm0 +; AVX512-NEXT: vmovdqa 112(%rdx), %xmm1 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512-NEXT: vpermt2d %zmm2, %zmm5, %zmm0 ; AVX512-NEXT: vmovdqa32 %zmm0, %zmm15 {%k1} -; AVX512-NEXT: vmovdqa 80(%rcx), %xmm0 -; AVX512-NEXT: vmovdqa 80(%rdx), %xmm3 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm9 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm16 = xmm9[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm9, %ymm16, %ymm9 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[0,0,1,1] +; AVX512-NEXT: vmovdqa 64(%rsi), %xmm0 +; AVX512-NEXT: vmovdqa 64(%rdi), %xmm1 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm2[0],zero,xmm2[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] +; AVX512-NEXT: vinserti32x4 $1, %xmm2, %ymm16, %ymm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0 -; AVX512-NEXT: vinserti64x4 $1, %ymm9, %zmm0, %zmm0 -; AVX512-NEXT: vmovdqa 80(%rsi), %xmm3 -; AVX512-NEXT: vmovdqa 80(%rdi), %xmm9 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm14 = xmm9[4],xmm3[4],xmm9[5],xmm3[5],xmm9[6],xmm3[6],xmm9[7],xmm3[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm14[0],zero,xmm14[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm14 = xmm14[2,2,3,3] -; AVX512-NEXT: vinserti32x4 $1, %xmm14, %ymm16, %ymm14 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm9[0],xmm3[0],xmm9[1],xmm3[1],xmm9[2],xmm3[2],xmm9[3],xmm3[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm9 = xmm3[0],zero,xmm3[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm9, %ymm3 -; AVX512-NEXT: vinserti64x4 $1, %ymm14, %zmm3, %zmm16 +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm16 +; AVX512-NEXT: vmovdqa 64(%rcx), %xmm0 +; AVX512-NEXT: vmovdqa 64(%rdx), %xmm1 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512-NEXT: vpermt2d %zmm2, %zmm5, %zmm0 ; AVX512-NEXT: vmovdqa32 %zmm0, %zmm16 {%k1} -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm3[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm9, %ymm3 -; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm0 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm3 = xmm13[4],xmm12[4],xmm13[5],xmm12[5],xmm13[6],xmm12[6],xmm13[7],xmm12[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm9 = xmm3[0],zero,xmm3[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm3, %ymm9, %ymm3 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm9 = xmm13[0],xmm12[0],xmm13[1],xmm12[1],xmm13[2],xmm12[2],xmm13[3],xmm12[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm10 = xmm9[0],zero,xmm9[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm9[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm9, %ymm10, %ymm9 -; AVX512-NEXT: vinserti64x4 $1, %ymm3, %zmm9, %zmm3 -; AVX512-NEXT: vmovdqa32 %zmm0, %zmm3 {%k1} -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm6[4],xmm5[4],xmm6[5],xmm5[5],xmm6[6],xmm5[6],xmm6[7],xmm5[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm9 = xmm0[0,0,1,1] +; AVX512-NEXT: vmovdqa 80(%rsi), %xmm0 +; AVX512-NEXT: vmovdqa 80(%rdi), %xmm1 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm17 = xmm2[0],zero,xmm2[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] +; AVX512-NEXT: vinserti32x4 $1, %xmm2, %ymm17, %ymm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm9, %ymm0 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm6[0],xmm5[0],xmm6[1],xmm5[1],xmm6[2],xmm5[2],xmm6[3],xmm5[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm5[0,0,1,1] -; AVX512-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm5, %zmm0 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm8[4],xmm7[4],xmm8[5],xmm7[5],xmm8[6],xmm7[6],xmm8[7],xmm7[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm5[0],zero,xmm5[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm6[0],zero,xmm6[1],zero -; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6 -; AVX512-NEXT: vinserti64x4 $1, %ymm5, %zmm6, %zmm5 -; AVX512-NEXT: vmovdqa32 %zmm0, %zmm5 {%k1} -; AVX512-NEXT: vmovdqa64 %xmm20, %xmm7 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm1[4],xmm7[4],xmm1[5],xmm7[5],xmm1[6],xmm7[6],xmm1[7],xmm7[7] -; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm0[0,0,1,1] +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm17 +; AVX512-NEXT: vmovdqa 80(%rcx), %xmm0 +; AVX512-NEXT: vmovdqa 80(%rdx), %xmm1 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512-NEXT: vpermt2d %zmm2, %zmm5, %zmm0 +; AVX512-NEXT: vmovdqa32 %zmm0, %zmm17 {%k1} +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm1[0],xmm7[0],xmm1[1],xmm7[1],xmm1[2],xmm7[2],xmm1[3],xmm7[3] -; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm1[0,0,1,1] +; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm6, %ymm1 +; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 -; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm1[0],zero,xmm1[1],zero +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3] +; AVX512-NEXT: vpermt2d %zmm1, %zmm5, %zmm2 +; AVX512-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1} +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm6, %ymm1 -; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm4[0],xmm2[0],xmm4[1],xmm2[1],xmm4[2],xmm2[2],xmm4[3],xmm2[3] -; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm2[0],zero,xmm2[1],zero +; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm2[0],zero,xmm2[1],zero ; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] -; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm4, %ymm2 +; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1 -; AVX512-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1} -; AVX512-NEXT: vmovdqa64 %zmm1, (%r8) -; AVX512-NEXT: vmovdqa64 %zmm5, 192(%r8) -; AVX512-NEXT: vmovdqa64 %zmm3, 128(%r8) -; AVX512-NEXT: vmovdqa64 %zmm16, 320(%r8) -; AVX512-NEXT: vmovdqa64 %zmm15, 256(%r8) -; AVX512-NEXT: vmovdqa64 %zmm19, 448(%r8) -; AVX512-NEXT: vmovdqa64 %zmm18, 384(%r8) -; AVX512-NEXT: vmovdqa64 %zmm17, 64(%r8) +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm10[4],xmm9[4],xmm10[5],xmm9[5],xmm10[6],xmm9[6],xmm10[7],xmm9[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3] +; AVX512-NEXT: vpermt2d %zmm2, %zmm5, %zmm6 +; AVX512-NEXT: vmovdqa32 %zmm6, %zmm1 {%k1} +; AVX512-NEXT: vmovdqa64 %xmm19, %xmm7 +; AVX512-NEXT: vmovdqa64 %xmm20, %xmm9 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm7[4],xmm9[5],xmm7[5],xmm9[6],xmm7[6],xmm9[7],xmm7[7] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm2[0],zero,xmm2[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] +; AVX512-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2 +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm9[0],xmm7[0],xmm9[1],xmm7[1],xmm9[2],xmm7[2],xmm9[3],xmm7[3] +; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm6[0],zero,xmm6[1],zero +; AVX512-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] +; AVX512-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6 +; AVX512-NEXT: vinserti64x4 $1, %ymm2, %zmm6, %zmm2 +; AVX512-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] +; AVX512-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] +; AVX512-NEXT: vpermt2d %zmm6, %zmm5, %zmm3 +; AVX512-NEXT: vmovdqa32 %zmm3, %zmm2 {%k1} +; AVX512-NEXT: vmovdqa64 %zmm2, (%r8) +; AVX512-NEXT: vmovdqa64 %zmm1, 192(%r8) +; AVX512-NEXT: vmovdqa64 %zmm0, 128(%r8) +; AVX512-NEXT: vmovdqa64 %zmm17, 320(%r8) +; AVX512-NEXT: vmovdqa64 %zmm16, 256(%r8) +; AVX512-NEXT: vmovdqa64 %zmm15, 448(%r8) +; AVX512-NEXT: vmovdqa64 %zmm8, 384(%r8) +; AVX512-NEXT: vmovdqa64 %zmm18, 64(%r8) ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq ; @@ -3466,192 +3378,155 @@ define void @store_i16_stride4_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.ve ; ; AVX512DQ-LABEL: store_i16_stride4_vf64: ; AVX512DQ: # %bb.0: -; AVX512DQ-NEXT: vmovdqa (%rsi), %xmm1 +; AVX512DQ-NEXT: vmovdqa64 (%rsi), %xmm19 ; AVX512DQ-NEXT: vmovdqa 16(%rsi), %xmm0 -; AVX512DQ-NEXT: vmovdqa 32(%rsi), %xmm10 -; AVX512DQ-NEXT: vmovdqa 48(%rsi), %xmm5 -; AVX512DQ-NEXT: vmovdqa (%rdi), %xmm2 +; AVX512DQ-NEXT: vmovdqa 32(%rsi), %xmm11 +; AVX512DQ-NEXT: vmovdqa 48(%rsi), %xmm6 +; AVX512DQ-NEXT: vmovdqa64 (%rdi), %xmm20 ; AVX512DQ-NEXT: vmovdqa 16(%rdi), %xmm3 -; AVX512DQ-NEXT: vmovdqa 32(%rdi), %xmm11 +; AVX512DQ-NEXT: vmovdqa 32(%rdi), %xmm12 ; AVX512DQ-NEXT: vmovdqa 48(%rdi), %xmm7 ; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm4 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm4[0],zero,xmm4[1],zero +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm5 = xmm4[0],zero,xmm4[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm4, %ymm6, %ymm4 +; AVX512DQ-NEXT: vinserti128 $1, %xmm4, %ymm5, %ymm4 ; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3] ; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm3, %ymm0 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm17 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm4, %zmm0, %zmm18 ; AVX512DQ-NEXT: vmovdqa (%rcx), %xmm3 -; AVX512DQ-NEXT: vmovdqa 16(%rcx), %xmm6 -; AVX512DQ-NEXT: vmovdqa 32(%rcx), %xmm12 -; AVX512DQ-NEXT: vmovdqa 48(%rcx), %xmm8 +; AVX512DQ-NEXT: vmovdqa 16(%rcx), %xmm5 +; AVX512DQ-NEXT: vmovdqa 32(%rcx), %xmm13 +; AVX512DQ-NEXT: vmovdqa 48(%rcx), %xmm9 ; AVX512DQ-NEXT: vmovdqa (%rdx), %xmm4 -; AVX512DQ-NEXT: vmovdqa 16(%rdx), %xmm13 +; AVX512DQ-NEXT: vmovdqa 16(%rdx), %xmm8 ; AVX512DQ-NEXT: vmovdqa 32(%rdx), %xmm14 -; AVX512DQ-NEXT: vmovdqa 48(%rdx), %xmm9 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm13[4],xmm6[4],xmm13[5],xmm6[5],xmm13[6],xmm6[6],xmm13[7],xmm6[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm16 = xmm15[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm13[0],xmm6[0],xmm13[1],xmm6[1],xmm13[2],xmm6[2],xmm13[3],xmm6[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm6[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm13, %ymm6 +; AVX512DQ-NEXT: vmovdqa 48(%rdx), %xmm10 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm8[4],xmm5[4],xmm8[5],xmm5[5],xmm8[6],xmm5[6],xmm8[7],xmm5[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm8[0],xmm5[0],xmm8[1],xmm5[1],xmm8[2],xmm5[2],xmm8[3],xmm5[3] +; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm5 = [0,0,1,1,2,2,3,3,16,16,17,17,18,18,19,19] +; AVX512DQ-NEXT: vpermt2d %zmm15, %zmm5, %zmm8 ; AVX512DQ-NEXT: movw $-21846, %ax # imm = 0xAAAA ; AVX512DQ-NEXT: kmovw %eax, %k1 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm15, %zmm6, %zmm17 {%k1} -; AVX512DQ-NEXT: vmovdqa 96(%rsi), %xmm6 -; AVX512DQ-NEXT: vmovdqa 96(%rdi), %xmm13 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm13[4],xmm6[4],xmm13[5],xmm6[5],xmm13[6],xmm6[6],xmm13[7],xmm6[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm15[0],zero,xmm15[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm13[0],xmm6[0],xmm13[1],xmm6[1],xmm13[2],xmm6[2],xmm13[3],xmm6[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm13 = xmm6[0],zero,xmm6[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm13, %ymm6 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm15, %zmm6, %zmm18 -; AVX512DQ-NEXT: vmovdqa 96(%rcx), %xmm13 -; AVX512DQ-NEXT: vmovdqa 96(%rdx), %xmm15 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm13[4],xmm15[5],xmm13[5],xmm15[6],xmm13[6],xmm15[7],xmm13[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm16 = xmm0[0,0,1,1] +; AVX512DQ-NEXT: vmovdqa32 %zmm8, %zmm18 {%k1} +; AVX512DQ-NEXT: vmovdqa 96(%rsi), %xmm8 +; AVX512DQ-NEXT: vmovdqa 96(%rdi), %xmm15 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] ; AVX512DQ-NEXT: vinserti32x4 $1, %xmm0, %ymm16, %ymm0 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm13 = xmm15[0],xmm13[0],xmm15[1],xmm13[1],xmm15[2],xmm13[2],xmm15[3],xmm13[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm13[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm13, %ymm15, %ymm13 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm0, %zmm13, %zmm18 {%k1} +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm8 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm15 = xmm8[0],zero,xmm8[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm8 = xmm8[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm8, %ymm15, %ymm8 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm8, %zmm8 +; AVX512DQ-NEXT: vmovdqa 96(%rcx), %xmm0 +; AVX512DQ-NEXT: vmovdqa 96(%rdx), %xmm15 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm15[4],xmm0[4],xmm15[5],xmm0[5],xmm15[6],xmm0[6],xmm15[7],xmm0[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm0[0],xmm15[1],xmm0[1],xmm15[2],xmm0[2],xmm15[3],xmm0[3] +; AVX512DQ-NEXT: vpermt2d %zmm1, %zmm5, %zmm0 +; AVX512DQ-NEXT: vmovdqa32 %zmm0, %zmm8 {%k1} ; AVX512DQ-NEXT: vmovdqa 112(%rsi), %xmm0 -; AVX512DQ-NEXT: vmovdqa 112(%rdi), %xmm13 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm13[4],xmm0[4],xmm13[5],xmm0[5],xmm13[6],xmm0[6],xmm13[7],xmm0[7] +; AVX512DQ-NEXT: vmovdqa 112(%rdi), %xmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] ; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm15[0],zero,xmm15[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] ; AVX512DQ-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm13[0],xmm0[0],xmm13[1],xmm0[1],xmm13[2],xmm0[2],xmm13[3],xmm0[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm13 = xmm0[0],zero,xmm0[1],zero +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm13, %ymm0 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm15, %zmm0, %zmm19 +; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm15, %zmm0, %zmm15 ; AVX512DQ-NEXT: vmovdqa 112(%rcx), %xmm0 -; AVX512DQ-NEXT: vmovdqa 112(%rdx), %xmm15 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm15[4],xmm0[4],xmm15[5],xmm0[5],xmm15[6],xmm0[6],xmm15[7],xmm0[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm16 = xmm6[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm6, %ymm16, %ymm6 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm15[0],xmm0[0],xmm15[1],xmm0[1],xmm15[2],xmm0[2],xmm15[3],xmm0[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm0[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm15, %ymm0 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm6, %zmm0, %zmm19 {%k1} +; AVX512DQ-NEXT: vmovdqa 112(%rdx), %xmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512DQ-NEXT: vpermt2d %zmm2, %zmm5, %zmm0 +; AVX512DQ-NEXT: vmovdqa32 %zmm0, %zmm15 {%k1} ; AVX512DQ-NEXT: vmovdqa 64(%rsi), %xmm0 -; AVX512DQ-NEXT: vmovdqa 64(%rdi), %xmm6 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm15 = xmm6[4],xmm0[4],xmm6[5],xmm0[5],xmm6[6],xmm0[6],xmm6[7],xmm0[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm15[0],zero,xmm15[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm15 = xmm15[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm15, %ymm16, %ymm15 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm6[0],xmm0[0],xmm6[1],xmm0[1],xmm6[2],xmm0[2],xmm6[3],xmm0[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero +; AVX512DQ-NEXT: vmovdqa 64(%rdi), %xmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm2[0],zero,xmm2[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] +; AVX512DQ-NEXT: vinserti32x4 $1, %xmm2, %ymm16, %ymm2 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm15, %zmm0, %zmm15 +; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm16 ; AVX512DQ-NEXT: vmovdqa 64(%rcx), %xmm0 -; AVX512DQ-NEXT: vmovdqa 64(%rdx), %xmm6 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm6[4],xmm0[4],xmm6[5],xmm0[5],xmm6[6],xmm0[6],xmm6[7],xmm0[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm16 = xmm13[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm13, %ymm16, %ymm13 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm6[0],xmm0[0],xmm6[1],xmm0[1],xmm6[2],xmm0[2],xmm6[3],xmm0[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm0[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm13, %zmm0, %zmm15 {%k1} +; AVX512DQ-NEXT: vmovdqa 64(%rdx), %xmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512DQ-NEXT: vpermt2d %zmm2, %zmm5, %zmm0 +; AVX512DQ-NEXT: vmovdqa32 %zmm0, %zmm16 {%k1} ; AVX512DQ-NEXT: vmovdqa 80(%rsi), %xmm0 -; AVX512DQ-NEXT: vmovdqa 80(%rdi), %xmm6 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm6[4],xmm0[4],xmm6[5],xmm0[5],xmm6[6],xmm0[6],xmm6[7],xmm0[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm16 = xmm13[0],zero,xmm13[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm13, %ymm16, %ymm13 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm6[0],xmm0[0],xmm6[1],xmm0[1],xmm6[2],xmm0[2],xmm6[3],xmm0[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero +; AVX512DQ-NEXT: vmovdqa 80(%rdi), %xmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm17 = xmm2[0],zero,xmm2[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] +; AVX512DQ-NEXT: vinserti32x4 $1, %xmm2, %ymm17, %ymm2 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm13, %zmm0, %zmm16 +; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm17 ; AVX512DQ-NEXT: vmovdqa 80(%rcx), %xmm0 -; AVX512DQ-NEXT: vmovdqa 80(%rdx), %xmm6 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm13 = xmm6[4],xmm0[4],xmm6[5],xmm0[5],xmm6[6],xmm0[6],xmm6[7],xmm0[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm20 = xmm13[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm13 = xmm13[2,2,3,3] -; AVX512DQ-NEXT: vinserti32x4 $1, %xmm13, %ymm20, %ymm13 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm6[0],xmm0[0],xmm6[1],xmm0[1],xmm6[2],xmm0[2],xmm6[3],xmm0[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm0[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm13, %zmm0, %zmm16 {%k1} -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm10 = xmm6[0],zero,xmm6[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm10, %ymm6 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm6, %zmm10 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm14[4],xmm12[4],xmm14[5],xmm12[5],xmm14[6],xmm12[6],xmm14[7],xmm12[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm0[0,0,1,1] +; AVX512DQ-NEXT: vmovdqa 80(%rdx), %xmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX512DQ-NEXT: vpermt2d %zmm2, %zmm5, %zmm0 +; AVX512DQ-NEXT: vmovdqa32 %zmm0, %zmm17 {%k1} +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm12[4],xmm11[4],xmm12[5],xmm11[5],xmm12[6],xmm11[6],xmm12[7],xmm11[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm14[0],xmm12[0],xmm14[1],xmm12[1],xmm14[2],xmm12[2],xmm14[3],xmm12[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm11 = xmm6[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm11, %ymm6 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm0, %zmm6, %zmm10 {%k1} -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm0[0],zero,xmm0[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm6, %ymm0 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm5 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm5[0],zero,xmm5[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm5, %zmm0 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm9[4],xmm8[4],xmm9[5],xmm8[5],xmm9[6],xmm8[6],xmm9[7],xmm8[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm5[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm9[0],xmm8[0],xmm9[1],xmm8[1],xmm9[2],xmm8[2],xmm9[3],xmm8[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm7 = xmm6[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm5, %zmm6, %zmm0 {%k1} -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm5 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7] -; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm5[0],zero,xmm5[1],zero -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm5, %ymm6, %ymm5 -; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm12[0],xmm11[0],xmm12[1],xmm11[1],xmm12[2],xmm11[2],xmm12[3],xmm11[3] ; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] ; AVX512DQ-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 -; AVX512DQ-NEXT: vinserti64x4 $1, %ymm5, %zmm1, %zmm1 -; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[0,0,1,1] +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3] +; AVX512DQ-NEXT: vpermt2d %zmm1, %zmm5, %zmm2 +; AVX512DQ-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1} +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm2 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm2[0],zero,xmm2[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm10[4],xmm9[4],xmm10[5],xmm9[5],xmm10[6],xmm9[6],xmm10[7],xmm9[7] +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm10[0],xmm9[0],xmm10[1],xmm9[1],xmm10[2],xmm9[2],xmm10[3],xmm9[3] +; AVX512DQ-NEXT: vpermt2d %zmm2, %zmm5, %zmm6 +; AVX512DQ-NEXT: vmovdqa32 %zmm6, %zmm1 {%k1} +; AVX512DQ-NEXT: vmovdqa64 %xmm19, %xmm7 +; AVX512DQ-NEXT: vmovdqa64 %xmm20, %xmm9 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm9[4],xmm7[4],xmm9[5],xmm7[5],xmm9[6],xmm7[6],xmm9[7],xmm7[7] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm6 = xmm2[0],zero,xmm2[1],zero ; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm5, %ymm2 +; AVX512DQ-NEXT: vinserti128 $1, %xmm2, %ymm6, %ymm2 +; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm6 = xmm9[0],xmm7[0],xmm9[1],xmm7[1],xmm9[2],xmm7[2],xmm9[3],xmm7[3] +; AVX512DQ-NEXT: vpmovzxdq {{.*#+}} xmm7 = xmm6[0],zero,xmm6[1],zero +; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm6 = xmm6[2,2,3,3] +; AVX512DQ-NEXT: vinserti128 $1, %xmm6, %ymm7, %ymm6 +; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm6, %zmm2 +; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} xmm6 = xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] ; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[0,0,1,1] -; AVX512DQ-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,2,3,3] -; AVX512DQ-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3 -; AVX512DQ-NEXT: vinserti32x8 $1, %ymm2, %zmm3, %zmm1 {%k1} -; AVX512DQ-NEXT: vmovdqa64 %zmm1, (%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm0, 192(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm10, 128(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm16, 320(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm15, 256(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm19, 448(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm18, 384(%r8) -; AVX512DQ-NEXT: vmovdqa64 %zmm17, 64(%r8) +; AVX512DQ-NEXT: vpermt2d %zmm6, %zmm5, %zmm3 +; AVX512DQ-NEXT: vmovdqa32 %zmm3, %zmm2 {%k1} +; AVX512DQ-NEXT: vmovdqa64 %zmm2, (%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm1, 192(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm0, 128(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm17, 320(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm16, 256(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm15, 448(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm8, 384(%r8) +; AVX512DQ-NEXT: vmovdqa64 %zmm18, 64(%r8) ; AVX512DQ-NEXT: vzeroupper ; AVX512DQ-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll index d8fd21f4877f..a343df8428fb 100644 --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll @@ -1151,24 +1151,25 @@ define void @store_i8_stride8_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp ; AVX512BW-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0] ; AVX512BW-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2 ; AVX512BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; AVX512BW-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm1 ; AVX512BW-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512BW-NEXT: vpshufb {{.*#+}} zmm1 = zmm0[0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u,u,u] +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm3 = zmm0[0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u,u,u] ; AVX512BW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[2,3,0,1,6,7,4,5] ; AVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u,u,u,u,u] ; AVX512BW-NEXT: movl $287445282, %ecx # imm = 0x11221122 ; AVX512BW-NEXT: kmovd %ecx, %k1 -; AVX512BW-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1} -; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm2[2,3,0,1,2,3,0,1] -; AVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[u,u,u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u] -; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3,0,1,2,3] -; AVX512BW-NEXT: vpshufb {{.*#+}} zmm2 = zmm2[u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63] +; AVX512BW-NEXT: vmovdqu16 %zmm0, %zmm3 {%k1} +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[4,5,6,7,4,5,6,7] +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63] +; AVX512BW-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm2[2,3,0,1,2,3,0,1] +; AVX512BW-NEXT: vpshufb {{.*#+}} zmm1 = zmm1[u,u,u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u] ; AVX512BW-NEXT: movl $1149781128, %ecx # imm = 0x44884488 ; AVX512BW-NEXT: kmovd %ecx, %k1 -; AVX512BW-NEXT: vmovdqu16 %zmm0, %zmm2 {%k1} +; AVX512BW-NEXT: vmovdqu16 %zmm1, %zmm0 {%k1} ; AVX512BW-NEXT: movw $-21846, %cx # imm = 0xAAAA ; AVX512BW-NEXT: kmovd %ecx, %k1 -; AVX512BW-NEXT: vmovdqa32 %zmm2, %zmm1 {%k1} -; AVX512BW-NEXT: vmovdqa64 %zmm1, (%rax) +; AVX512BW-NEXT: vmovdqa32 %zmm0, %zmm3 {%k1} +; AVX512BW-NEXT: vmovdqa64 %zmm3, (%rax) ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq ; @@ -1224,24 +1225,25 @@ define void @store_i8_stride8_vf8(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vecp ; AVX512DQ-BW-NEXT: vpunpcklqdq {{.*#+}} xmm3 = xmm4[0],xmm3[0] ; AVX512DQ-BW-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2 ; AVX512DQ-BW-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 +; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm1 ; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm1 = zmm0[0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u,u,u] +; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm3 = zmm0[0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u,u,u] ; AVX512DQ-BW-NEXT: vpermq {{.*#+}} zmm0 = zmm0[2,3,0,1,6,7,4,5] ; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u,u,u,u,u] ; AVX512DQ-BW-NEXT: movl $287445282, %ecx # imm = 0x11221122 ; AVX512DQ-BW-NEXT: kmovd %ecx, %k1 -; AVX512DQ-BW-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1} -; AVX512DQ-BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm2[2,3,0,1,2,3,0,1] -; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[u,u,u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u] -; AVX512DQ-BW-NEXT: vshufi64x2 {{.*#+}} zmm2 = zmm2[0,1,2,3,0,1,2,3] -; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm2 = zmm2[u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63] +; AVX512DQ-BW-NEXT: vmovdqu16 %zmm0, %zmm3 {%k1} +; AVX512DQ-BW-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm1[4,5,6,7,4,5,6,7] +; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm0 = zmm0[u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,u,u,u,u,54,62,u,u,u,u,u,u,55,63] +; AVX512DQ-BW-NEXT: vshufi64x2 {{.*#+}} zmm1 = zmm2[2,3,0,1,2,3,0,1] +; AVX512DQ-BW-NEXT: vpshufb {{.*#+}} zmm1 = zmm1[u,u,u,u,u,u,0,8,u,u,u,u,u,u,1,9,u,u,u,u,18,26,u,u,u,u,u,u,19,27,u,u,u,u,u,u,u,u,36,44,u,u,u,u,u,u,37,45,u,u,u,u,54,62,u,u,u,u,u,u,55,63,u,u] ; AVX512DQ-BW-NEXT: movl $1149781128, %ecx # imm = 0x44884488 ; AVX512DQ-BW-NEXT: kmovd %ecx, %k1 -; AVX512DQ-BW-NEXT: vmovdqu16 %zmm0, %zmm2 {%k1} +; AVX512DQ-BW-NEXT: vmovdqu16 %zmm1, %zmm0 {%k1} ; AVX512DQ-BW-NEXT: movw $-21846, %cx # imm = 0xAAAA ; AVX512DQ-BW-NEXT: kmovd %ecx, %k1 -; AVX512DQ-BW-NEXT: vmovdqa32 %zmm2, %zmm1 {%k1} -; AVX512DQ-BW-NEXT: vmovdqa64 %zmm1, (%rax) +; AVX512DQ-BW-NEXT: vmovdqa32 %zmm0, %zmm3 {%k1} +; AVX512DQ-BW-NEXT: vmovdqa64 %zmm3, (%rax) ; AVX512DQ-BW-NEXT: vzeroupper ; AVX512DQ-BW-NEXT: retq ; @@ -8870,234 +8872,172 @@ define void @store_i8_stride8_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512BW-FCP: # %bb.0: ; AVX512BW-FCP-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512BW-FCP-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512BW-FCP-NEXT: vmovdqa (%r10), %xmm0 -; AVX512BW-FCP-NEXT: vmovdqa 16(%r10), %xmm14 -; AVX512BW-FCP-NEXT: vmovdqa64 32(%r10), %xmm18 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%r10), %xmm17 -; AVX512BW-FCP-NEXT: vmovdqa (%rax), %xmm1 -; AVX512BW-FCP-NEXT: vmovdqa 16(%rax), %xmm15 -; AVX512BW-FCP-NEXT: vmovdqa64 32(%rax), %xmm19 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%rax), %xmm20 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm2, %ymm2, %ymm2 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm2, %zmm2, %zmm3 -; AVX512BW-FCP-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,0,1,0,1,0,1,8,9,10,11,4,5,2,3,0,1,4,5,0,1,4,5,8,9,10,11,4,5,6,7,0,1,2,3,8,9,8,9,8,9,8,9,12,13,10,11,0,1,2,3,8,9,12,13,8,9,12,13,12,13,14,15] -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm3, %zmm6 -; AVX512BW-FCP-NEXT: vmovdqa (%r9), %xmm3 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%r9), %xmm21 -; AVX512BW-FCP-NEXT: vmovdqa (%r8), %xmm4 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%r8), %xmm22 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm5, %ymm5, %ymm5 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm5, %zmm5, %zmm7 -; AVX512BW-FCP-NEXT: vmovdqa64 {{.*#+}} zmm5 = [0,1,2,3,0,1,2,3,8,9,10,11,2,3,6,7,4,5,2,3,4,5,2,3,8,9,10,11,6,7,6,7,0,1,2,3,8,9,10,11,8,9,10,11,10,11,14,15,0,1,2,3,12,13,10,11,12,13,10,11,14,15,14,15] -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm7, %zmm16 -; AVX512BW-FCP-NEXT: movl $-2004318072, %eax # imm = 0x88888888 -; AVX512BW-FCP-NEXT: kmovd %eax, %k1 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm6, %zmm16 {%k1} -; AVX512BW-FCP-NEXT: vmovdqa (%rcx), %xmm6 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%rcx), %xmm23 +; AVX512BW-FCP-NEXT: vmovdqa (%rsi), %xmm0 +; AVX512BW-FCP-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512BW-FCP-NEXT: vmovdqa64 32(%rsi), %xmm20 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%rsi), %xmm17 +; AVX512BW-FCP-NEXT: vmovdqa (%rdi), %xmm2 +; AVX512BW-FCP-NEXT: vmovdqa64 32(%rdi), %xmm21 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%rdi), %xmm18 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] +; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm3 +; AVX512BW-FCP-NEXT: vpmovsxwq {{.*#+}} ymm4 = [2312,2826,3340,3854] +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm3, %ymm3 +; AVX512BW-FCP-NEXT: vpmovsxwq {{.*#+}} xmm5 = [1284,1798] +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm0, %xmm6 +; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm6, %ymm0, %ymm0 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm1 +; AVX512BW-FCP-NEXT: vmovdqa (%rcx), %xmm3 +; AVX512BW-FCP-NEXT: vmovdqa64 32(%rcx), %xmm22 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%rcx), %xmm19 ; AVX512BW-FCP-NEXT: vmovdqa (%rdx), %xmm7 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm7[8],xmm6[8],xmm7[9],xmm6[9],xmm7[10],xmm6[10],xmm7[11],xmm6[11],xmm7[12],xmm6[12],xmm7[13],xmm6[13],xmm7[14],xmm6[14],xmm7[15],xmm6[15] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm8, %ymm8, %ymm8 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm8, %zmm8, %zmm8 -; AVX512BW-FCP-NEXT: vmovdqa64 {{.*#+}} zmm9 = [0,1,0,1,4,5,2,3,4,5,2,3,12,13,14,15,0,1,4,5,4,5,6,7,4,5,6,7,12,13,14,15,8,9,8,9,4,5,6,7,12,13,10,11,12,13,10,11,8,9,12,13,4,5,6,7,12,13,14,15,12,13,14,15] -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm8, %zmm24 -; AVX512BW-FCP-NEXT: vmovdqa (%rsi), %xmm10 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%rsi), %xmm25 -; AVX512BW-FCP-NEXT: vmovdqa (%rdi), %xmm11 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%rdi), %xmm28 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm11[8],xmm10[8],xmm11[9],xmm10[9],xmm11[10],xmm10[10],xmm11[11],xmm10[11],xmm11[12],xmm10[12],xmm11[13],xmm10[13],xmm11[14],xmm10[14],xmm11[15],xmm10[15] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm8, %ymm8, %ymm13 -; AVX512BW-FCP-NEXT: vpmovsxwq {{.*#+}} ymm12 = [2312,2826,3340,3854] -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm13, %ymm26 -; AVX512BW-FCP-NEXT: vpmovsxwq {{.*#+}} xmm13 = [1284,1798] -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm8, %xmm27 -; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm8 = xmm8[0],zero,zero,zero,xmm8[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm27, %ymm8, %ymm8 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm26, %zmm8, %zmm8 -; AVX512BW-FCP-NEXT: movl $572662306, %eax # imm = 0x22222222 -; AVX512BW-FCP-NEXT: kmovd %eax, %k2 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm24, %zmm8 {%k2} -; AVX512BW-FCP-NEXT: movw $-21846, %ax # imm = 0xAAAA -; AVX512BW-FCP-NEXT: kmovd %eax, %k3 -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm16, %zmm8 {%k3} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm20[0],xmm17[0],xmm20[1],xmm17[1],xmm20[2],xmm17[2],xmm20[3],xmm17[3],xmm20[4],xmm17[4],xmm20[5],xmm17[5],xmm20[6],xmm17[6],xmm20[7],xmm17[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm16, %ymm16, %ymm16 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm16, %zmm16, %zmm16 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm16, %zmm16 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm22[0],xmm21[0],xmm22[1],xmm21[1],xmm22[2],xmm21[2],xmm22[3],xmm21[3],xmm22[4],xmm21[4],xmm22[5],xmm21[5],xmm22[6],xmm21[6],xmm22[7],xmm21[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm24, %ymm24, %ymm24 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm24, %zmm24, %zmm24 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm24, %zmm24 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm16, %zmm24 {%k1} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm28[0],xmm25[0],xmm28[1],xmm25[1],xmm28[2],xmm25[2],xmm28[3],xmm25[3],xmm28[4],xmm25[4],xmm28[5],xmm25[5],xmm28[6],xmm25[6],xmm28[7],xmm25[7] -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm16, %xmm26 -; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm27 = xmm16[0],zero,zero,zero,xmm16[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm26, %ymm27, %ymm26 -; AVX512BW-FCP-NEXT: vmovdqa64 48(%rdx), %xmm30 -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm16, %ymm16, %ymm16 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm16, %ymm16 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm16, %zmm26, %zmm16 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm26 = xmm30[0],xmm23[0],xmm30[1],xmm23[1],xmm30[2],xmm23[2],xmm30[3],xmm23[3],xmm30[4],xmm23[4],xmm30[5],xmm23[5],xmm30[6],xmm23[6],xmm30[7],xmm23[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm26, %ymm26, %ymm26 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm26, %zmm26, %zmm26 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm26, %zmm26 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm26, %zmm16 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa64 32(%r9), %xmm26 -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm24, %zmm16 {%k3} -; AVX512BW-FCP-NEXT: vmovdqa64 32(%r8), %xmm27 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm20[8],xmm17[8],xmm20[9],xmm17[9],xmm20[10],xmm17[10],xmm20[11],xmm17[11],xmm20[12],xmm17[12],xmm20[13],xmm17[13],xmm20[14],xmm17[14],xmm20[15],xmm17[15] -; AVX512BW-FCP-NEXT: vmovdqa64 32(%rcx), %xmm24 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm22[8],xmm21[8],xmm22[9],xmm21[9],xmm22[10],xmm21[10],xmm22[11],xmm21[11],xmm22[12],xmm21[12],xmm22[13],xmm21[13],xmm22[14],xmm21[14],xmm22[15],xmm21[15] -; AVX512BW-FCP-NEXT: vmovdqa64 32(%rsi), %xmm21 +; AVX512BW-FCP-NEXT: vmovdqa64 32(%rdx), %xmm23 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%rdx), %xmm24 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm7[8],xmm3[8],xmm7[9],xmm3[9],xmm7[10],xmm3[10],xmm7[11],xmm3[11],xmm7[12],xmm3[12],xmm7[13],xmm3[13],xmm7[14],xmm3[14],xmm7[15],xmm3[15] +; AVX512BW-FCP-NEXT: vpmovsxbw {{.*#+}} zmm8 = [0,0,2,1,2,1,6,7,0,2,2,3,2,3,6,7,4,4,2,3,6,5,6,5,4,6,2,3,6,7,6,7] +; AVX512BW-FCP-NEXT: movl $572662306, %r11d # imm = 0x22222222 +; AVX512BW-FCP-NEXT: kmovd %r11d, %k1 +; AVX512BW-FCP-NEXT: vpermw %zmm6, %zmm8, %zmm1 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa (%r10), %xmm6 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%r10), %xmm25 +; AVX512BW-FCP-NEXT: vmovdqa (%rax), %xmm9 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%rax), %xmm26 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm15 = xmm9[8],xmm6[8],xmm9[9],xmm6[9],xmm9[10],xmm6[10],xmm9[11],xmm6[11],xmm9[12],xmm6[12],xmm9[13],xmm6[13],xmm9[14],xmm6[14],xmm9[15],xmm6[15] +; AVX512BW-FCP-NEXT: vmovdqa (%r9), %xmm10 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%r9), %xmm27 +; AVX512BW-FCP-NEXT: vmovdqa (%r8), %xmm11 +; AVX512BW-FCP-NEXT: vmovdqa64 48(%r8), %xmm28 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm12 = xmm11[8],xmm10[8],xmm11[9],xmm10[9],xmm11[10],xmm10[10],xmm11[11],xmm10[11],xmm11[12],xmm10[12],xmm11[13],xmm10[13],xmm11[14],xmm10[14],xmm11[15],xmm10[15] +; AVX512BW-FCP-NEXT: vpmovsxbw {{.*#+}} zmm13 = [0,1,0,1,4,5,1,3,2,1,2,1,4,5,3,3,0,1,4,5,4,5,5,7,0,1,6,5,6,5,7,7] +; AVX512BW-FCP-NEXT: vpermw %zmm12, %zmm13, %zmm12 +; AVX512BW-FCP-NEXT: vpmovsxbw {{.*#+}} zmm14 = [0,0,0,0,4,5,2,1,0,2,0,2,4,5,2,3,0,1,4,4,4,4,6,5,0,1,4,6,4,6,6,7] +; AVX512BW-FCP-NEXT: movl $-2004318072, %r11d # imm = 0x88888888 +; AVX512BW-FCP-NEXT: kmovd %r11d, %k2 +; AVX512BW-FCP-NEXT: vpermw %zmm15, %zmm14, %zmm12 {%k2} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm18[0],xmm17[0],xmm18[1],xmm17[1],xmm18[2],xmm17[2],xmm18[3],xmm17[3],xmm18[4],xmm17[4],xmm18[5],xmm17[5],xmm18[6],xmm17[6],xmm18[7],xmm17[7] +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm15, %ymm15, %ymm16 +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm16, %ymm16 +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm15, %xmm29 +; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm15 = xmm15[0],zero,zero,zero,xmm15[1],zero,zero,zero +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm29, %ymm15, %ymm15 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm16, %zmm15, %zmm15 +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm24[0],xmm19[0],xmm24[1],xmm19[1],xmm24[2],xmm19[2],xmm24[3],xmm19[3],xmm24[4],xmm19[4],xmm24[5],xmm19[5],xmm24[6],xmm19[6],xmm24[7],xmm19[7] +; AVX512BW-FCP-NEXT: vpermw %zmm16, %zmm8, %zmm15 {%k1} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm29 = xmm26[0],xmm25[0],xmm26[1],xmm25[1],xmm26[2],xmm25[2],xmm26[3],xmm25[3],xmm26[4],xmm25[4],xmm26[5],xmm25[5],xmm26[6],xmm25[6],xmm26[7],xmm25[7] +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm28[0],xmm27[0],xmm28[1],xmm27[1],xmm28[2],xmm27[2],xmm28[3],xmm27[3],xmm28[4],xmm27[4],xmm28[5],xmm27[5],xmm28[6],xmm27[6],xmm28[7],xmm27[7] +; AVX512BW-FCP-NEXT: vpermw %zmm16, %zmm13, %zmm16 +; AVX512BW-FCP-NEXT: vpermw %zmm29, %zmm14, %zmm16 {%k2} +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm18[8],xmm17[8],xmm18[9],xmm17[9],xmm18[10],xmm17[10],xmm18[11],xmm17[11],xmm18[12],xmm17[12],xmm18[13],xmm17[13],xmm18[14],xmm17[14],xmm18[15],xmm17[15] +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm17, %xmm18 +; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm29 = xmm17[0],zero,zero,zero,xmm17[1],zero,zero,zero +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm29, %ymm18 +; AVX512BW-FCP-NEXT: vmovdqa64 32(%r10), %xmm29 ; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm17, %ymm17, %ymm17 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm17, %zmm17, %zmm17 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm17, %zmm17 -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm20, %ymm20, %ymm20 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm20, %zmm20 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm20, %zmm20 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm17, %zmm20 {%k1} -; AVX512BW-FCP-NEXT: vmovdqa64 32(%rdi), %xmm29 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm30[8],xmm23[8],xmm30[9],xmm23[9],xmm30[10],xmm23[10],xmm30[11],xmm23[11],xmm30[12],xmm23[12],xmm30[13],xmm23[13],xmm30[14],xmm23[14],xmm30[15],xmm23[15] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm17, %ymm17, %ymm17 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm17, %zmm17, %zmm17 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm17, %zmm22 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm28[8],xmm25[8],xmm28[9],xmm25[9],xmm28[10],xmm25[10],xmm28[11],xmm25[11],xmm28[12],xmm25[12],xmm28[13],xmm25[13],xmm28[14],xmm25[14],xmm28[15],xmm25[15] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm17, %ymm17, %ymm23 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm23, %ymm23 -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm17, %xmm25 -; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm17 = xmm17[0],zero,zero,zero,xmm17[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm25, %ymm17, %ymm17 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm23, %zmm17, %zmm17 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm22, %zmm17 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm20, %zmm17 {%k3} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm20 = xmm19[0],xmm18[0],xmm19[1],xmm18[1],xmm19[2],xmm18[2],xmm19[3],xmm18[3],xmm19[4],xmm18[4],xmm19[5],xmm18[5],xmm19[6],xmm18[6],xmm19[7],xmm18[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm20, %ymm20, %ymm20 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm20, %zmm20 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm20, %zmm20 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm22 = xmm27[0],xmm26[0],xmm27[1],xmm26[1],xmm27[2],xmm26[2],xmm27[3],xmm26[3],xmm27[4],xmm26[4],xmm27[5],xmm26[5],xmm27[6],xmm26[6],xmm27[7],xmm26[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm22, %ymm22, %ymm22 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm22, %zmm22, %zmm22 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm22, %zmm22 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm20, %zmm22 {%k1} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm20 = xmm29[0],xmm21[0],xmm29[1],xmm21[1],xmm29[2],xmm21[2],xmm29[3],xmm21[3],xmm29[4],xmm21[4],xmm29[5],xmm21[5],xmm29[6],xmm21[6],xmm29[7],xmm21[7] -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm20, %xmm23 +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm17, %ymm17 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm17 +; AVX512BW-FCP-NEXT: vmovdqa64 32(%rax), %xmm30 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm24[8],xmm19[8],xmm24[9],xmm19[9],xmm24[10],xmm19[10],xmm24[11],xmm19[11],xmm24[12],xmm19[12],xmm24[13],xmm19[13],xmm24[14],xmm19[14],xmm24[15],xmm19[15] +; AVX512BW-FCP-NEXT: vmovdqa64 32(%r9), %xmm31 +; AVX512BW-FCP-NEXT: vpermw %zmm18, %zmm8, %zmm17 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa 32(%r8), %xmm0 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm19 = xmm26[8],xmm25[8],xmm26[9],xmm25[9],xmm26[10],xmm25[10],xmm26[11],xmm25[11],xmm26[12],xmm25[12],xmm26[13],xmm25[13],xmm26[14],xmm25[14],xmm26[15],xmm25[15] +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm28[8],xmm27[8],xmm28[9],xmm27[9],xmm28[10],xmm27[10],xmm28[11],xmm27[11],xmm28[12],xmm27[12],xmm28[13],xmm27[13],xmm28[14],xmm27[14],xmm28[15],xmm27[15] +; AVX512BW-FCP-NEXT: vpermw %zmm18, %zmm13, %zmm18 +; AVX512BW-FCP-NEXT: vpermw %zmm19, %zmm14, %zmm18 {%k2} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm21[0],xmm20[0],xmm21[1],xmm20[1],xmm21[2],xmm20[2],xmm21[3],xmm20[3],xmm21[4],xmm20[4],xmm21[5],xmm20[5],xmm21[6],xmm20[6],xmm21[7],xmm20[7] +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm19, %ymm19, %ymm24 +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm24, %ymm24 +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm19, %xmm25 +; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm19 = xmm19[0],zero,zero,zero,xmm19[1],zero,zero,zero +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm25, %ymm19, %ymm19 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm24, %zmm19, %zmm19 +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm23[0],xmm22[0],xmm23[1],xmm22[1],xmm23[2],xmm22[2],xmm23[3],xmm22[3],xmm23[4],xmm22[4],xmm23[5],xmm22[5],xmm23[6],xmm22[6],xmm23[7],xmm22[7] +; AVX512BW-FCP-NEXT: vpermw %zmm24, %zmm8, %zmm19 {%k1} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm25 = xmm30[0],xmm29[0],xmm30[1],xmm29[1],xmm30[2],xmm29[2],xmm30[3],xmm29[3],xmm30[4],xmm29[4],xmm30[5],xmm29[5],xmm30[6],xmm29[6],xmm30[7],xmm29[7] +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm0[0],xmm31[0],xmm0[1],xmm31[1],xmm0[2],xmm31[2],xmm0[3],xmm31[3],xmm0[4],xmm31[4],xmm0[5],xmm31[5],xmm0[6],xmm31[6],xmm0[7],xmm31[7] +; AVX512BW-FCP-NEXT: vpermw %zmm24, %zmm13, %zmm24 +; AVX512BW-FCP-NEXT: vpermw %zmm25, %zmm14, %zmm24 {%k2} +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm21[8],xmm20[8],xmm21[9],xmm20[9],xmm21[10],xmm20[10],xmm21[11],xmm20[11],xmm21[12],xmm20[12],xmm21[13],xmm20[13],xmm21[14],xmm20[14],xmm21[15],xmm20[15] +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm20, %xmm21 ; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm25 = xmm20[0],zero,zero,zero,xmm20[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm23, %ymm25, %ymm23 -; AVX512BW-FCP-NEXT: vmovdqa64 32(%rdx), %xmm28 +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm21, %ymm25, %ymm21 ; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm20, %ymm20, %ymm20 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm20, %ymm20 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm23, %zmm20 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm23 = xmm28[0],xmm24[0],xmm28[1],xmm24[1],xmm28[2],xmm24[2],xmm28[3],xmm24[3],xmm28[4],xmm24[4],xmm28[5],xmm24[5],xmm28[6],xmm24[6],xmm28[7],xmm24[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm23, %ymm23, %ymm23 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm23, %zmm23, %zmm23 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm23, %zmm23 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm23, %zmm20 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa64 16(%r9), %xmm23 -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm22, %zmm20 {%k3} -; AVX512BW-FCP-NEXT: vmovdqa64 16(%r8), %xmm25 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm19[8],xmm18[8],xmm19[9],xmm18[9],xmm19[10],xmm18[10],xmm19[11],xmm18[11],xmm19[12],xmm18[12],xmm19[13],xmm18[13],xmm19[14],xmm18[14],xmm19[15],xmm18[15] -; AVX512BW-FCP-NEXT: vmovdqa64 16(%rcx), %xmm19 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm26 = xmm27[8],xmm26[8],xmm27[9],xmm26[9],xmm27[10],xmm26[10],xmm27[11],xmm26[11],xmm27[12],xmm26[12],xmm27[13],xmm26[13],xmm27[14],xmm26[14],xmm27[15],xmm26[15] -; AVX512BW-FCP-NEXT: vmovdqa64 16(%rsi), %xmm22 -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm18, %ymm18 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm18, %zmm18, %zmm18 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm18, %zmm18 -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm26, %ymm26, %ymm26 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm26, %zmm26, %zmm26 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm26, %zmm27 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm18, %zmm27 {%k1} -; AVX512BW-FCP-NEXT: vmovdqa64 16(%rdi), %xmm26 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm28[8],xmm24[8],xmm28[9],xmm24[9],xmm28[10],xmm24[10],xmm28[11],xmm24[11],xmm28[12],xmm24[12],xmm28[13],xmm24[13],xmm28[14],xmm24[14],xmm28[15],xmm24[15] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm18, %ymm18 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm18, %zmm18, %zmm18 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm18, %zmm24 -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm29[8],xmm21[8],xmm29[9],xmm21[9],xmm29[10],xmm21[10],xmm29[11],xmm21[11],xmm29[12],xmm21[12],xmm29[13],xmm21[13],xmm29[14],xmm21[14],xmm29[15],xmm21[15] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm18, %ymm21 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm21, %ymm21 -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm18, %xmm28 -; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm18 = xmm18[0],zero,zero,zero,xmm18[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm28, %ymm18, %ymm18 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm21, %zmm18, %zmm18 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm24, %zmm18 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm27, %zmm18 {%k3} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm21 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm21, %ymm21, %ymm21 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm21, %zmm21, %zmm21 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm21, %zmm21 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm25[0],xmm23[0],xmm25[1],xmm23[1],xmm25[2],xmm23[2],xmm25[3],xmm23[3],xmm25[4],xmm23[4],xmm25[5],xmm23[5],xmm25[6],xmm23[6],xmm25[7],xmm23[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm24, %ymm24, %ymm24 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm24, %zmm24, %zmm24 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm24, %zmm24 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm21, %zmm24 {%k1} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm21 = xmm26[0],xmm22[0],xmm26[1],xmm22[1],xmm26[2],xmm22[2],xmm26[3],xmm22[3],xmm26[4],xmm22[4],xmm26[5],xmm22[5],xmm26[6],xmm22[6],xmm26[7],xmm22[7] -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm21, %xmm27 -; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm28 = xmm21[0],zero,zero,zero,xmm21[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm27, %ymm28, %ymm27 -; AVX512BW-FCP-NEXT: vmovdqa64 16(%rdx), %xmm28 -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm21, %ymm21, %ymm21 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm21, %ymm21 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm21, %zmm27, %zmm21 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm27 = xmm28[0],xmm19[0],xmm28[1],xmm19[1],xmm28[2],xmm19[2],xmm28[3],xmm19[3],xmm28[4],xmm19[4],xmm28[5],xmm19[5],xmm28[6],xmm19[6],xmm28[7],xmm19[7] -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm27, %ymm27, %ymm27 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm27, %zmm27, %zmm27 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm27, %zmm27 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm27, %zmm21 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm24, %zmm21 {%k3} -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm15[8],xmm14[8],xmm15[9],xmm14[9],xmm15[10],xmm14[10],xmm15[11],xmm14[11],xmm15[12],xmm14[12],xmm15[13],xmm14[13],xmm15[14],xmm14[14],xmm15[15],xmm14[15] -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm15 = xmm25[8],xmm23[8],xmm25[9],xmm23[9],xmm25[10],xmm23[10],xmm25[11],xmm23[11],xmm25[12],xmm23[12],xmm25[13],xmm23[13],xmm25[14],xmm23[14],xmm25[15],xmm23[15] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm14, %ymm14, %ymm14 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm14, %zmm14, %zmm14 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm14, %zmm14 -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm15, %ymm15, %ymm15 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm15, %zmm15, %zmm15 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm15, %zmm15 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm14, %zmm15 {%k1} -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm28[8],xmm19[8],xmm28[9],xmm19[9],xmm28[10],xmm19[10],xmm28[11],xmm19[11],xmm28[12],xmm19[12],xmm28[13],xmm19[13],xmm28[14],xmm19[14],xmm28[15],xmm19[15] -; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm19 = xmm26[8],xmm22[8],xmm26[9],xmm22[9],xmm26[10],xmm22[10],xmm26[11],xmm22[11],xmm26[12],xmm22[12],xmm26[13],xmm22[13],xmm26[14],xmm22[14],xmm26[15],xmm22[15] -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm19, %xmm22 -; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm23 = xmm19[0],zero,zero,zero,xmm19[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm22, %ymm23, %ymm22 -; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm19, %ymm19, %ymm19 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm19, %ymm19 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm19, %zmm22, %zmm19 -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm14, %ymm14, %ymm14 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm14, %zmm14, %zmm14 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm14, %zmm14 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm14, %zmm19 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm15, %zmm19 {%k3} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm20, %ymm20 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm21, %zmm20 +; AVX512BW-FCP-NEXT: vmovdqa64 16(%rsi), %xmm25 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm21 = xmm23[8],xmm22[8],xmm23[9],xmm22[9],xmm23[10],xmm22[10],xmm23[11],xmm22[11],xmm23[12],xmm22[12],xmm23[13],xmm22[13],xmm23[14],xmm22[14],xmm23[15],xmm22[15] +; AVX512BW-FCP-NEXT: vmovdqa64 16(%rdi), %xmm23 +; AVX512BW-FCP-NEXT: vpermw %zmm21, %zmm8, %zmm20 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa64 16(%rcx), %xmm26 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm30[8],xmm29[8],xmm30[9],xmm29[9],xmm30[10],xmm29[10],xmm30[11],xmm29[11],xmm30[12],xmm29[12],xmm30[13],xmm29[13],xmm30[14],xmm29[14],xmm30[15],xmm29[15] +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm31[8],xmm0[9],xmm31[9],xmm0[10],xmm31[10],xmm0[11],xmm31[11],xmm0[12],xmm31[12],xmm0[13],xmm31[13],xmm0[14],xmm31[14],xmm0[15],xmm31[15] +; AVX512BW-FCP-NEXT: vpermw %zmm0, %zmm13, %zmm21 +; AVX512BW-FCP-NEXT: vpermw %zmm22, %zmm14, %zmm21 {%k2} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm23[0],xmm25[0],xmm23[1],xmm25[1],xmm23[2],xmm25[2],xmm23[3],xmm25[3],xmm23[4],xmm25[4],xmm23[5],xmm25[5],xmm23[6],xmm25[6],xmm23[7],xmm25[7] +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm0, %xmm22 +; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm27 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm22, %ymm27, %ymm22 +; AVX512BW-FCP-NEXT: vmovdqa64 16(%rdx), %xmm27 ; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512BW-FCP-NEXT: vpshufb %zmm2, %zmm0, %zmm0 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1 -; AVX512BW-FCP-NEXT: vpshufb %zmm5, %zmm1, %zmm1 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1} -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3],xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7] +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm0, %ymm0 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm22, %zmm22 +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm27[0],xmm26[0],xmm27[1],xmm26[1],xmm27[2],xmm26[2],xmm27[3],xmm26[3],xmm27[4],xmm26[4],xmm27[5],xmm26[5],xmm27[6],xmm26[6],xmm27[7],xmm26[7] +; AVX512BW-FCP-NEXT: vpermw %zmm0, %zmm8, %zmm22 {%k1} +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm23[8],xmm25[8],xmm23[9],xmm25[9],xmm23[10],xmm25[10],xmm23[11],xmm25[11],xmm23[12],xmm25[12],xmm23[13],xmm25[13],xmm23[14],xmm25[14],xmm23[15],xmm25[15] +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm0, %xmm23 +; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm25 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm23, %ymm25, %ymm23 ; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512BW-FCP-NEXT: vpshufb %zmm9, %zmm0, %zmm0 -; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm2, %ymm2, %ymm3 -; AVX512BW-FCP-NEXT: vpshufb %ymm12, %ymm3, %ymm3 -; AVX512BW-FCP-NEXT: vpshufb %xmm13, %xmm2, %xmm4 +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm0, %ymm0 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm23, %zmm0 +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm23 = xmm27[8],xmm26[8],xmm27[9],xmm26[9],xmm27[10],xmm26[10],xmm27[11],xmm26[11],xmm27[12],xmm26[12],xmm27[13],xmm26[13],xmm27[14],xmm26[14],xmm27[15],xmm26[15] +; AVX512BW-FCP-NEXT: vpermw %zmm23, %zmm8, %zmm0 {%k1} +; AVX512BW-FCP-NEXT: vpunpcklbw {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload +; AVX512BW-FCP-NEXT: # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1],xmm2[2],mem[2],xmm2[3],mem[3],xmm2[4],mem[4],xmm2[5],mem[5],xmm2[6],mem[6],xmm2[7],mem[7] +; AVX512BW-FCP-NEXT: vinserti32x4 $1, %xmm2, %ymm2, %ymm23 +; AVX512BW-FCP-NEXT: vpshufb %ymm4, %ymm23, %ymm4 +; AVX512BW-FCP-NEXT: vmovdqa64 16(%r10), %xmm23 +; AVX512BW-FCP-NEXT: vpshufb %xmm5, %xmm2, %xmm5 ; AVX512BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero -; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm4, %ymm2, %ymm2 -; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512BW-FCP-NEXT: vmovdqu16 %zmm0, %zmm2 {%k2} -; AVX512BW-FCP-NEXT: vmovdqa32 %zmm1, %zmm2 {%k3} +; AVX512BW-FCP-NEXT: vinserti128 $1, %xmm5, %ymm2, %ymm2 +; AVX512BW-FCP-NEXT: vmovdqa 16(%rax), %xmm5 +; AVX512BW-FCP-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm2 +; AVX512BW-FCP-NEXT: vmovdqa 16(%r9), %xmm4 +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm7[0],xmm3[0],xmm7[1],xmm3[1],xmm7[2],xmm3[2],xmm7[3],xmm3[3],xmm7[4],xmm3[4],xmm7[5],xmm3[5],xmm7[6],xmm3[6],xmm7[7],xmm3[7] +; AVX512BW-FCP-NEXT: vmovdqa 16(%r8), %xmm7 +; AVX512BW-FCP-NEXT: vpermw %zmm3, %zmm8, %zmm2 {%k1} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm5[0],xmm23[0],xmm5[1],xmm23[1],xmm5[2],xmm23[2],xmm5[3],xmm23[3],xmm5[4],xmm23[4],xmm5[5],xmm23[5],xmm5[6],xmm23[6],xmm5[7],xmm23[7] +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm7[0],xmm4[0],xmm7[1],xmm4[1],xmm7[2],xmm4[2],xmm7[3],xmm4[3],xmm7[4],xmm4[4],xmm7[5],xmm4[5],xmm7[6],xmm4[6],xmm7[7],xmm4[7] +; AVX512BW-FCP-NEXT: vpermw %zmm8, %zmm13, %zmm8 +; AVX512BW-FCP-NEXT: vpermw %zmm3, %zmm14, %zmm8 {%k2} +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm5[8],xmm23[8],xmm5[9],xmm23[9],xmm5[10],xmm23[10],xmm5[11],xmm23[11],xmm5[12],xmm23[12],xmm5[13],xmm23[13],xmm5[14],xmm23[14],xmm5[15],xmm23[15] +; AVX512BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm7[8],xmm4[8],xmm7[9],xmm4[9],xmm7[10],xmm4[10],xmm7[11],xmm4[11],xmm7[12],xmm4[12],xmm7[13],xmm4[13],xmm7[14],xmm4[14],xmm7[15],xmm4[15] +; AVX512BW-FCP-NEXT: vpermw %zmm4, %zmm13, %zmm4 +; AVX512BW-FCP-NEXT: vpermw %zmm3, %zmm14, %zmm4 {%k2} +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm9[0],xmm6[0],xmm9[1],xmm6[1],xmm9[2],xmm6[2],xmm9[3],xmm6[3],xmm9[4],xmm6[4],xmm9[5],xmm6[5],xmm9[6],xmm6[6],xmm9[7],xmm6[7] +; AVX512BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] +; AVX512BW-FCP-NEXT: vpermw %zmm5, %zmm13, %zmm5 +; AVX512BW-FCP-NEXT: vpermw %zmm3, %zmm14, %zmm5 {%k2} +; AVX512BW-FCP-NEXT: movw $-21846, %ax # imm = 0xAAAA +; AVX512BW-FCP-NEXT: kmovd %eax, %k1 +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm12, %zmm1 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm16, %zmm15 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm18, %zmm17 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm24, %zmm19 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm21, %zmm20 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm8, %zmm22 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm4, %zmm0 {%k1} +; AVX512BW-FCP-NEXT: vmovdqa32 %zmm5, %zmm2 {%k1} ; AVX512BW-FCP-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512BW-FCP-NEXT: vmovdqa64 %zmm2, (%rax) -; AVX512BW-FCP-NEXT: vmovdqa64 %zmm19, 192(%rax) -; AVX512BW-FCP-NEXT: vmovdqa64 %zmm21, 128(%rax) -; AVX512BW-FCP-NEXT: vmovdqa64 %zmm18, 320(%rax) -; AVX512BW-FCP-NEXT: vmovdqa64 %zmm20, 256(%rax) +; AVX512BW-FCP-NEXT: vmovdqa64 %zmm0, 192(%rax) +; AVX512BW-FCP-NEXT: vmovdqa64 %zmm22, 128(%rax) +; AVX512BW-FCP-NEXT: vmovdqa64 %zmm20, 320(%rax) +; AVX512BW-FCP-NEXT: vmovdqa64 %zmm19, 256(%rax) ; AVX512BW-FCP-NEXT: vmovdqa64 %zmm17, 448(%rax) -; AVX512BW-FCP-NEXT: vmovdqa64 %zmm16, 384(%rax) -; AVX512BW-FCP-NEXT: vmovdqa64 %zmm8, 64(%rax) +; AVX512BW-FCP-NEXT: vmovdqa64 %zmm15, 384(%rax) +; AVX512BW-FCP-NEXT: vmovdqa64 %zmm1, 64(%rax) ; AVX512BW-FCP-NEXT: vzeroupper ; AVX512BW-FCP-NEXT: retq ; @@ -9336,234 +9276,172 @@ define void @store_i8_stride8_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec ; AVX512DQ-BW-FCP: # %bb.0: ; AVX512DQ-BW-FCP-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512DQ-BW-FCP-NEXT: movq {{[0-9]+}}(%rsp), %r10 -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%r10), %xmm0 -; AVX512DQ-BW-FCP-NEXT: vmovdqa 16(%r10), %xmm14 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%r10), %xmm18 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%r10), %xmm17 -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rax), %xmm1 -; AVX512DQ-BW-FCP-NEXT: vmovdqa 16(%rax), %xmm15 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rax), %xmm19 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rax), %xmm20 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm2, %ymm2, %ymm2 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm2, %zmm2, %zmm3 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,0,1,0,1,0,1,8,9,10,11,4,5,2,3,0,1,4,5,0,1,4,5,8,9,10,11,4,5,6,7,0,1,2,3,8,9,8,9,8,9,8,9,12,13,10,11,0,1,2,3,8,9,12,13,8,9,12,13,12,13,14,15] -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm3, %zmm6 -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%r9), %xmm3 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%r9), %xmm21 -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%r8), %xmm4 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%r8), %xmm22 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm5 = xmm4[8],xmm3[8],xmm4[9],xmm3[9],xmm4[10],xmm3[10],xmm4[11],xmm3[11],xmm4[12],xmm3[12],xmm4[13],xmm3[13],xmm4[14],xmm3[14],xmm4[15],xmm3[15] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm5, %ymm5, %ymm5 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm5, %zmm5, %zmm7 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 {{.*#+}} zmm5 = [0,1,2,3,0,1,2,3,8,9,10,11,2,3,6,7,4,5,2,3,4,5,2,3,8,9,10,11,6,7,6,7,0,1,2,3,8,9,10,11,8,9,10,11,10,11,14,15,0,1,2,3,12,13,10,11,12,13,10,11,14,15,14,15] -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm7, %zmm16 -; AVX512DQ-BW-FCP-NEXT: movl $-2004318072, %eax # imm = 0x88888888 -; AVX512DQ-BW-FCP-NEXT: kmovd %eax, %k1 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm6, %zmm16 {%k1} -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rcx), %xmm6 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rcx), %xmm23 +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rsi), %xmm0 +; AVX512DQ-BW-FCP-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rsi), %xmm20 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rsi), %xmm17 +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rdi), %xmm2 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rdi), %xmm21 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rdi), %xmm18 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] +; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm3 +; AVX512DQ-BW-FCP-NEXT: vpmovsxwq {{.*#+}} ymm4 = [2312,2826,3340,3854] +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm3, %ymm3 +; AVX512DQ-BW-FCP-NEXT: vpmovsxwq {{.*#+}} xmm5 = [1284,1798] +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm0, %xmm6 +; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm6, %ymm0, %ymm0 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm1 +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rcx), %xmm3 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rcx), %xmm22 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rcx), %xmm19 ; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rdx), %xmm7 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm7[8],xmm6[8],xmm7[9],xmm6[9],xmm7[10],xmm6[10],xmm7[11],xmm6[11],xmm7[12],xmm6[12],xmm7[13],xmm6[13],xmm7[14],xmm6[14],xmm7[15],xmm6[15] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm8, %ymm8, %ymm8 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm8, %zmm8, %zmm8 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 {{.*#+}} zmm9 = [0,1,0,1,4,5,2,3,4,5,2,3,12,13,14,15,0,1,4,5,4,5,6,7,4,5,6,7,12,13,14,15,8,9,8,9,4,5,6,7,12,13,10,11,12,13,10,11,8,9,12,13,4,5,6,7,12,13,14,15,12,13,14,15] -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm8, %zmm24 -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rsi), %xmm10 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rsi), %xmm25 -; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rdi), %xmm11 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rdi), %xmm28 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm8 = xmm11[8],xmm10[8],xmm11[9],xmm10[9],xmm11[10],xmm10[10],xmm11[11],xmm10[11],xmm11[12],xmm10[12],xmm11[13],xmm10[13],xmm11[14],xmm10[14],xmm11[15],xmm10[15] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm8, %ymm8, %ymm13 -; AVX512DQ-BW-FCP-NEXT: vpmovsxwq {{.*#+}} ymm12 = [2312,2826,3340,3854] -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm13, %ymm26 -; AVX512DQ-BW-FCP-NEXT: vpmovsxwq {{.*#+}} xmm13 = [1284,1798] -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm8, %xmm27 -; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm8 = xmm8[0],zero,zero,zero,xmm8[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm27, %ymm8, %ymm8 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm26, %zmm8, %zmm8 -; AVX512DQ-BW-FCP-NEXT: movl $572662306, %eax # imm = 0x22222222 -; AVX512DQ-BW-FCP-NEXT: kmovd %eax, %k2 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm24, %zmm8 {%k2} -; AVX512DQ-BW-FCP-NEXT: movw $-21846, %ax # imm = 0xAAAA -; AVX512DQ-BW-FCP-NEXT: kmovd %eax, %k3 -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm16, %zmm8 {%k3} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm20[0],xmm17[0],xmm20[1],xmm17[1],xmm20[2],xmm17[2],xmm20[3],xmm17[3],xmm20[4],xmm17[4],xmm20[5],xmm17[5],xmm20[6],xmm17[6],xmm20[7],xmm17[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm16, %ymm16, %ymm16 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm16, %zmm16, %zmm16 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm16, %zmm16 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm22[0],xmm21[0],xmm22[1],xmm21[1],xmm22[2],xmm21[2],xmm22[3],xmm21[3],xmm22[4],xmm21[4],xmm22[5],xmm21[5],xmm22[6],xmm21[6],xmm22[7],xmm21[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm24, %ymm24, %ymm24 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm24, %zmm24, %zmm24 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm24, %zmm24 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm16, %zmm24 {%k1} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm28[0],xmm25[0],xmm28[1],xmm25[1],xmm28[2],xmm25[2],xmm28[3],xmm25[3],xmm28[4],xmm25[4],xmm28[5],xmm25[5],xmm28[6],xmm25[6],xmm28[7],xmm25[7] -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm16, %xmm26 -; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm27 = xmm16[0],zero,zero,zero,xmm16[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm26, %ymm27, %ymm26 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rdx), %xmm30 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm16, %ymm16, %ymm16 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm16, %ymm16 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm16, %zmm26, %zmm16 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm26 = xmm30[0],xmm23[0],xmm30[1],xmm23[1],xmm30[2],xmm23[2],xmm30[3],xmm23[3],xmm30[4],xmm23[4],xmm30[5],xmm23[5],xmm30[6],xmm23[6],xmm30[7],xmm23[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm26, %ymm26, %ymm26 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm26, %zmm26, %zmm26 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm26, %zmm26 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm26, %zmm16 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%r9), %xmm26 -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm24, %zmm16 {%k3} -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%r8), %xmm27 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm20[8],xmm17[8],xmm20[9],xmm17[9],xmm20[10],xmm17[10],xmm20[11],xmm17[11],xmm20[12],xmm17[12],xmm20[13],xmm17[13],xmm20[14],xmm17[14],xmm20[15],xmm17[15] -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rcx), %xmm24 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm22[8],xmm21[8],xmm22[9],xmm21[9],xmm22[10],xmm21[10],xmm22[11],xmm21[11],xmm22[12],xmm21[12],xmm22[13],xmm21[13],xmm22[14],xmm21[14],xmm22[15],xmm21[15] -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rsi), %xmm21 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm17, %ymm17, %ymm17 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm17, %zmm17, %zmm17 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm17, %zmm17 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm20, %ymm20, %ymm20 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm20, %zmm20 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm20, %zmm20 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm17, %zmm20 {%k1} -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rdi), %xmm29 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm30[8],xmm23[8],xmm30[9],xmm23[9],xmm30[10],xmm23[10],xmm30[11],xmm23[11],xmm30[12],xmm23[12],xmm30[13],xmm23[13],xmm30[14],xmm23[14],xmm30[15],xmm23[15] +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rdx), %xmm23 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rdx), %xmm24 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm6 = xmm7[8],xmm3[8],xmm7[9],xmm3[9],xmm7[10],xmm3[10],xmm7[11],xmm3[11],xmm7[12],xmm3[12],xmm7[13],xmm3[13],xmm7[14],xmm3[14],xmm7[15],xmm3[15] +; AVX512DQ-BW-FCP-NEXT: vpmovsxbw {{.*#+}} zmm8 = [0,0,2,1,2,1,6,7,0,2,2,3,2,3,6,7,4,4,2,3,6,5,6,5,4,6,2,3,6,7,6,7] +; AVX512DQ-BW-FCP-NEXT: movl $572662306, %r11d # imm = 0x22222222 +; AVX512DQ-BW-FCP-NEXT: kmovd %r11d, %k1 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm6, %zmm8, %zmm1 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%r10), %xmm6 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%r10), %xmm25 +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%rax), %xmm9 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%rax), %xmm26 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm15 = xmm9[8],xmm6[8],xmm9[9],xmm6[9],xmm9[10],xmm6[10],xmm9[11],xmm6[11],xmm9[12],xmm6[12],xmm9[13],xmm6[13],xmm9[14],xmm6[14],xmm9[15],xmm6[15] +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%r9), %xmm10 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%r9), %xmm27 +; AVX512DQ-BW-FCP-NEXT: vmovdqa (%r8), %xmm11 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 48(%r8), %xmm28 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm12 = xmm11[8],xmm10[8],xmm11[9],xmm10[9],xmm11[10],xmm10[10],xmm11[11],xmm10[11],xmm11[12],xmm10[12],xmm11[13],xmm10[13],xmm11[14],xmm10[14],xmm11[15],xmm10[15] +; AVX512DQ-BW-FCP-NEXT: vpmovsxbw {{.*#+}} zmm13 = [0,1,0,1,4,5,1,3,2,1,2,1,4,5,3,3,0,1,4,5,4,5,5,7,0,1,6,5,6,5,7,7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm12, %zmm13, %zmm12 +; AVX512DQ-BW-FCP-NEXT: vpmovsxbw {{.*#+}} zmm14 = [0,0,0,0,4,5,2,1,0,2,0,2,4,5,2,3,0,1,4,4,4,4,6,5,0,1,4,6,4,6,6,7] +; AVX512DQ-BW-FCP-NEXT: movl $-2004318072, %r11d # imm = 0x88888888 +; AVX512DQ-BW-FCP-NEXT: kmovd %r11d, %k2 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm15, %zmm14, %zmm12 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm15 = xmm18[0],xmm17[0],xmm18[1],xmm17[1],xmm18[2],xmm17[2],xmm18[3],xmm17[3],xmm18[4],xmm17[4],xmm18[5],xmm17[5],xmm18[6],xmm17[6],xmm18[7],xmm17[7] +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm15, %ymm15, %ymm16 +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm16, %ymm16 +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm15, %xmm29 +; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm15 = xmm15[0],zero,zero,zero,xmm15[1],zero,zero,zero +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm29, %ymm15, %ymm15 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm16, %zmm15, %zmm15 +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm24[0],xmm19[0],xmm24[1],xmm19[1],xmm24[2],xmm19[2],xmm24[3],xmm19[3],xmm24[4],xmm19[4],xmm24[5],xmm19[5],xmm24[6],xmm19[6],xmm24[7],xmm19[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm16, %zmm8, %zmm15 {%k1} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm29 = xmm26[0],xmm25[0],xmm26[1],xmm25[1],xmm26[2],xmm25[2],xmm26[3],xmm25[3],xmm26[4],xmm25[4],xmm26[5],xmm25[5],xmm26[6],xmm25[6],xmm26[7],xmm25[7] +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm16 = xmm28[0],xmm27[0],xmm28[1],xmm27[1],xmm28[2],xmm27[2],xmm28[3],xmm27[3],xmm28[4],xmm27[4],xmm28[5],xmm27[5],xmm28[6],xmm27[6],xmm28[7],xmm27[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm16, %zmm13, %zmm16 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm29, %zmm14, %zmm16 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm18[8],xmm17[8],xmm18[9],xmm17[9],xmm18[10],xmm17[10],xmm18[11],xmm17[11],xmm18[12],xmm17[12],xmm18[13],xmm17[13],xmm18[14],xmm17[14],xmm18[15],xmm17[15] +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm17, %xmm18 +; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm29 = xmm17[0],zero,zero,zero,xmm17[1],zero,zero,zero +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm29, %ymm18 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%r10), %xmm29 ; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm17, %ymm17, %ymm17 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm17, %zmm17, %zmm17 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm17, %zmm22 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm17 = xmm28[8],xmm25[8],xmm28[9],xmm25[9],xmm28[10],xmm25[10],xmm28[11],xmm25[11],xmm28[12],xmm25[12],xmm28[13],xmm25[13],xmm28[14],xmm25[14],xmm28[15],xmm25[15] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm17, %ymm17, %ymm23 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm23, %ymm23 -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm17, %xmm25 -; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm17 = xmm17[0],zero,zero,zero,xmm17[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm25, %ymm17, %ymm17 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm23, %zmm17, %zmm17 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm22, %zmm17 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm20, %zmm17 {%k3} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm20 = xmm19[0],xmm18[0],xmm19[1],xmm18[1],xmm19[2],xmm18[2],xmm19[3],xmm18[3],xmm19[4],xmm18[4],xmm19[5],xmm18[5],xmm19[6],xmm18[6],xmm19[7],xmm18[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm20, %ymm20, %ymm20 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm20, %zmm20 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm20, %zmm20 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm22 = xmm27[0],xmm26[0],xmm27[1],xmm26[1],xmm27[2],xmm26[2],xmm27[3],xmm26[3],xmm27[4],xmm26[4],xmm27[5],xmm26[5],xmm27[6],xmm26[6],xmm27[7],xmm26[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm22, %ymm22, %ymm22 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm22, %zmm22, %zmm22 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm22, %zmm22 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm20, %zmm22 {%k1} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm20 = xmm29[0],xmm21[0],xmm29[1],xmm21[1],xmm29[2],xmm21[2],xmm29[3],xmm21[3],xmm29[4],xmm21[4],xmm29[5],xmm21[5],xmm29[6],xmm21[6],xmm29[7],xmm21[7] -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm20, %xmm23 +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm17, %ymm17 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm17, %zmm18, %zmm17 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rax), %xmm30 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm24[8],xmm19[8],xmm24[9],xmm19[9],xmm24[10],xmm19[10],xmm24[11],xmm19[11],xmm24[12],xmm19[12],xmm24[13],xmm19[13],xmm24[14],xmm19[14],xmm24[15],xmm19[15] +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%r9), %xmm31 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm18, %zmm8, %zmm17 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa 32(%r8), %xmm0 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm19 = xmm26[8],xmm25[8],xmm26[9],xmm25[9],xmm26[10],xmm25[10],xmm26[11],xmm25[11],xmm26[12],xmm25[12],xmm26[13],xmm25[13],xmm26[14],xmm25[14],xmm26[15],xmm25[15] +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm28[8],xmm27[8],xmm28[9],xmm27[9],xmm28[10],xmm27[10],xmm28[11],xmm27[11],xmm28[12],xmm27[12],xmm28[13],xmm27[13],xmm28[14],xmm27[14],xmm28[15],xmm27[15] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm18, %zmm13, %zmm18 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm19, %zmm14, %zmm18 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm19 = xmm21[0],xmm20[0],xmm21[1],xmm20[1],xmm21[2],xmm20[2],xmm21[3],xmm20[3],xmm21[4],xmm20[4],xmm21[5],xmm20[5],xmm21[6],xmm20[6],xmm21[7],xmm20[7] +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm19, %ymm19, %ymm24 +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm24, %ymm24 +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm19, %xmm25 +; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm19 = xmm19[0],zero,zero,zero,xmm19[1],zero,zero,zero +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm25, %ymm19, %ymm19 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm24, %zmm19, %zmm19 +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm23[0],xmm22[0],xmm23[1],xmm22[1],xmm23[2],xmm22[2],xmm23[3],xmm22[3],xmm23[4],xmm22[4],xmm23[5],xmm22[5],xmm23[6],xmm22[6],xmm23[7],xmm22[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm24, %zmm8, %zmm19 {%k1} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm25 = xmm30[0],xmm29[0],xmm30[1],xmm29[1],xmm30[2],xmm29[2],xmm30[3],xmm29[3],xmm30[4],xmm29[4],xmm30[5],xmm29[5],xmm30[6],xmm29[6],xmm30[7],xmm29[7] +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm0[0],xmm31[0],xmm0[1],xmm31[1],xmm0[2],xmm31[2],xmm0[3],xmm31[3],xmm0[4],xmm31[4],xmm0[5],xmm31[5],xmm0[6],xmm31[6],xmm0[7],xmm31[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm24, %zmm13, %zmm24 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm25, %zmm14, %zmm24 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm20 = xmm21[8],xmm20[8],xmm21[9],xmm20[9],xmm21[10],xmm20[10],xmm21[11],xmm20[11],xmm21[12],xmm20[12],xmm21[13],xmm20[13],xmm21[14],xmm20[14],xmm21[15],xmm20[15] +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm20, %xmm21 ; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm25 = xmm20[0],zero,zero,zero,xmm20[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm23, %ymm25, %ymm23 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 32(%rdx), %xmm28 +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm21, %ymm25, %ymm21 ; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm20, %ymm20, %ymm20 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm20, %ymm20 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm23, %zmm20 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm23 = xmm28[0],xmm24[0],xmm28[1],xmm24[1],xmm28[2],xmm24[2],xmm28[3],xmm24[3],xmm28[4],xmm24[4],xmm28[5],xmm24[5],xmm28[6],xmm24[6],xmm28[7],xmm24[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm23, %ymm23, %ymm23 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm23, %zmm23, %zmm23 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm23, %zmm23 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm23, %zmm20 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%r9), %xmm23 -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm22, %zmm20 {%k3} -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%r8), %xmm25 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm19[8],xmm18[8],xmm19[9],xmm18[9],xmm19[10],xmm18[10],xmm19[11],xmm18[11],xmm19[12],xmm18[12],xmm19[13],xmm18[13],xmm19[14],xmm18[14],xmm19[15],xmm18[15] -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rcx), %xmm19 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm26 = xmm27[8],xmm26[8],xmm27[9],xmm26[9],xmm27[10],xmm26[10],xmm27[11],xmm26[11],xmm27[12],xmm26[12],xmm27[13],xmm26[13],xmm27[14],xmm26[14],xmm27[15],xmm26[15] -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rsi), %xmm22 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm18, %ymm18 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm18, %zmm18, %zmm18 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm18, %zmm18 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm26, %ymm26, %ymm26 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm26, %zmm26, %zmm26 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm26, %zmm27 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm18, %zmm27 {%k1} -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rdi), %xmm26 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm28[8],xmm24[8],xmm28[9],xmm24[9],xmm28[10],xmm24[10],xmm28[11],xmm24[11],xmm28[12],xmm24[12],xmm28[13],xmm24[13],xmm28[14],xmm24[14],xmm28[15],xmm24[15] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm18, %ymm18 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm18, %zmm18, %zmm18 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm18, %zmm24 -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm18 = xmm29[8],xmm21[8],xmm29[9],xmm21[9],xmm29[10],xmm21[10],xmm29[11],xmm21[11],xmm29[12],xmm21[12],xmm29[13],xmm21[13],xmm29[14],xmm21[14],xmm29[15],xmm21[15] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm18, %ymm18, %ymm21 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm21, %ymm21 -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm18, %xmm28 -; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm18 = xmm18[0],zero,zero,zero,xmm18[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm28, %ymm18, %ymm18 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm21, %zmm18, %zmm18 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm24, %zmm18 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm27, %zmm18 {%k3} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm21 = xmm15[0],xmm14[0],xmm15[1],xmm14[1],xmm15[2],xmm14[2],xmm15[3],xmm14[3],xmm15[4],xmm14[4],xmm15[5],xmm14[5],xmm15[6],xmm14[6],xmm15[7],xmm14[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm21, %ymm21, %ymm21 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm21, %zmm21, %zmm21 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm21, %zmm21 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm24 = xmm25[0],xmm23[0],xmm25[1],xmm23[1],xmm25[2],xmm23[2],xmm25[3],xmm23[3],xmm25[4],xmm23[4],xmm25[5],xmm23[5],xmm25[6],xmm23[6],xmm25[7],xmm23[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm24, %ymm24, %ymm24 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm24, %zmm24, %zmm24 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm24, %zmm24 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm21, %zmm24 {%k1} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm21 = xmm26[0],xmm22[0],xmm26[1],xmm22[1],xmm26[2],xmm22[2],xmm26[3],xmm22[3],xmm26[4],xmm22[4],xmm26[5],xmm22[5],xmm26[6],xmm22[6],xmm26[7],xmm22[7] -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm21, %xmm27 -; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm28 = xmm21[0],zero,zero,zero,xmm21[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm27, %ymm28, %ymm27 -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rdx), %xmm28 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm21, %ymm21, %ymm21 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm21, %ymm21 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm21, %zmm27, %zmm21 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm27 = xmm28[0],xmm19[0],xmm28[1],xmm19[1],xmm28[2],xmm19[2],xmm28[3],xmm19[3],xmm28[4],xmm19[4],xmm28[5],xmm19[5],xmm28[6],xmm19[6],xmm28[7],xmm19[7] -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm27, %ymm27, %ymm27 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm27, %zmm27, %zmm27 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm27, %zmm27 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm27, %zmm21 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm24, %zmm21 {%k3} -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm15[8],xmm14[8],xmm15[9],xmm14[9],xmm15[10],xmm14[10],xmm15[11],xmm14[11],xmm15[12],xmm14[12],xmm15[13],xmm14[13],xmm15[14],xmm14[14],xmm15[15],xmm14[15] -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm15 = xmm25[8],xmm23[8],xmm25[9],xmm23[9],xmm25[10],xmm23[10],xmm25[11],xmm23[11],xmm25[12],xmm23[12],xmm25[13],xmm23[13],xmm25[14],xmm23[14],xmm25[15],xmm23[15] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm14, %ymm14, %ymm14 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm14, %zmm14, %zmm14 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm14, %zmm14 -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm15, %ymm15, %ymm15 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm15, %zmm15, %zmm15 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm15, %zmm15 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm14, %zmm15 {%k1} -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm14 = xmm28[8],xmm19[8],xmm28[9],xmm19[9],xmm28[10],xmm19[10],xmm28[11],xmm19[11],xmm28[12],xmm19[12],xmm28[13],xmm19[13],xmm28[14],xmm19[14],xmm28[15],xmm19[15] -; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm19 = xmm26[8],xmm22[8],xmm26[9],xmm22[9],xmm26[10],xmm22[10],xmm26[11],xmm22[11],xmm26[12],xmm22[12],xmm26[13],xmm22[13],xmm26[14],xmm22[14],xmm26[15],xmm22[15] -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm19, %xmm22 -; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm23 = xmm19[0],zero,zero,zero,xmm19[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm22, %ymm23, %ymm22 -; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm19, %ymm19, %ymm19 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm19, %ymm19 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm19, %zmm22, %zmm19 -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm14, %ymm14, %ymm14 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm14, %zmm14, %zmm14 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm14, %zmm14 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm14, %zmm19 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm15, %zmm19 {%k3} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm20, %ymm20 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm20, %zmm21, %zmm20 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rsi), %xmm25 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm21 = xmm23[8],xmm22[8],xmm23[9],xmm22[9],xmm23[10],xmm22[10],xmm23[11],xmm22[11],xmm23[12],xmm22[12],xmm23[13],xmm22[13],xmm23[14],xmm22[14],xmm23[15],xmm22[15] +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rdi), %xmm23 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm21, %zmm8, %zmm20 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rcx), %xmm26 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm22 = xmm30[8],xmm29[8],xmm30[9],xmm29[9],xmm30[10],xmm29[10],xmm30[11],xmm29[11],xmm30[12],xmm29[12],xmm30[13],xmm29[13],xmm30[14],xmm29[14],xmm30[15],xmm29[15] +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8],xmm31[8],xmm0[9],xmm31[9],xmm0[10],xmm31[10],xmm0[11],xmm31[11],xmm0[12],xmm31[12],xmm0[13],xmm31[13],xmm0[14],xmm31[14],xmm0[15],xmm31[15] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm0, %zmm13, %zmm21 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm22, %zmm14, %zmm21 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm23[0],xmm25[0],xmm23[1],xmm25[1],xmm23[2],xmm25[2],xmm23[3],xmm25[3],xmm23[4],xmm25[4],xmm23[5],xmm25[5],xmm23[6],xmm25[6],xmm23[7],xmm25[7] +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm0, %xmm22 +; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm27 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm22, %ymm27, %ymm22 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%rdx), %xmm27 ; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm2, %zmm0, %zmm0 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm1, %ymm1, %ymm1 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm5, %zmm1, %zmm1 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1} -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm7[0],xmm6[0],xmm7[1],xmm6[1],xmm7[2],xmm6[2],xmm7[3],xmm6[3],xmm7[4],xmm6[4],xmm7[5],xmm6[5],xmm7[6],xmm6[6],xmm7[7],xmm6[7] +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm0, %ymm0 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm22, %zmm22 +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm27[0],xmm26[0],xmm27[1],xmm26[1],xmm27[2],xmm26[2],xmm27[3],xmm26[3],xmm27[4],xmm26[4],xmm27[5],xmm26[5],xmm27[6],xmm26[6],xmm27[7],xmm26[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm0, %zmm8, %zmm22 {%k1} +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm23[8],xmm25[8],xmm23[9],xmm25[9],xmm23[10],xmm25[10],xmm23[11],xmm25[11],xmm23[12],xmm25[12],xmm23[13],xmm25[13],xmm23[14],xmm25[14],xmm23[15],xmm25[15] +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm0, %xmm23 +; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm25 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm23, %ymm25, %ymm23 ; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm0, %zmm0 -; AVX512DQ-BW-FCP-NEXT: vpshufb %zmm9, %zmm0, %zmm0 -; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm2 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm2, %ymm2, %ymm3 -; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm12, %ymm3, %ymm3 -; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm13, %xmm2, %xmm4 +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm0, %ymm0 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm0, %zmm23, %zmm0 +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm23 = xmm27[8],xmm26[8],xmm27[9],xmm26[9],xmm27[10],xmm26[10],xmm27[11],xmm26[11],xmm27[12],xmm26[12],xmm27[13],xmm26[13],xmm27[14],xmm26[14],xmm27[15],xmm26[15] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm23, %zmm8, %zmm0 {%k1} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{[-0-9]+}}(%r{{[sb]}}p), %xmm2, %xmm2 # 16-byte Folded Reload +; AVX512DQ-BW-FCP-NEXT: # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1],xmm2[2],mem[2],xmm2[3],mem[3],xmm2[4],mem[4],xmm2[5],mem[5],xmm2[6],mem[6],xmm2[7],mem[7] +; AVX512DQ-BW-FCP-NEXT: vinserti32x4 $1, %xmm2, %ymm2, %ymm23 +; AVX512DQ-BW-FCP-NEXT: vpshufb %ymm4, %ymm23, %ymm4 +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 16(%r10), %xmm23 +; AVX512DQ-BW-FCP-NEXT: vpshufb %xmm5, %xmm2, %xmm5 ; AVX512DQ-BW-FCP-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero -; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm4, %ymm2, %ymm2 -; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2 -; AVX512DQ-BW-FCP-NEXT: vmovdqu16 %zmm0, %zmm2 {%k2} -; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm1, %zmm2 {%k3} +; AVX512DQ-BW-FCP-NEXT: vinserti128 $1, %xmm5, %ymm2, %ymm2 +; AVX512DQ-BW-FCP-NEXT: vmovdqa 16(%rax), %xmm5 +; AVX512DQ-BW-FCP-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm2 +; AVX512DQ-BW-FCP-NEXT: vmovdqa 16(%r9), %xmm4 +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm7[0],xmm3[0],xmm7[1],xmm3[1],xmm7[2],xmm3[2],xmm7[3],xmm3[3],xmm7[4],xmm3[4],xmm7[5],xmm3[5],xmm7[6],xmm3[6],xmm7[7],xmm3[7] +; AVX512DQ-BW-FCP-NEXT: vmovdqa 16(%r8), %xmm7 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm3, %zmm8, %zmm2 {%k1} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm5[0],xmm23[0],xmm5[1],xmm23[1],xmm5[2],xmm23[2],xmm5[3],xmm23[3],xmm5[4],xmm23[4],xmm5[5],xmm23[5],xmm5[6],xmm23[6],xmm5[7],xmm23[7] +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm8 = xmm7[0],xmm4[0],xmm7[1],xmm4[1],xmm7[2],xmm4[2],xmm7[3],xmm4[3],xmm7[4],xmm4[4],xmm7[5],xmm4[5],xmm7[6],xmm4[6],xmm7[7],xmm4[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm8, %zmm13, %zmm8 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm3, %zmm14, %zmm8 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm5[8],xmm23[8],xmm5[9],xmm23[9],xmm5[10],xmm23[10],xmm5[11],xmm23[11],xmm5[12],xmm23[12],xmm5[13],xmm23[13],xmm5[14],xmm23[14],xmm5[15],xmm23[15] +; AVX512DQ-BW-FCP-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm7[8],xmm4[8],xmm7[9],xmm4[9],xmm7[10],xmm4[10],xmm7[11],xmm4[11],xmm7[12],xmm4[12],xmm7[13],xmm4[13],xmm7[14],xmm4[14],xmm7[15],xmm4[15] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm4, %zmm13, %zmm4 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm3, %zmm14, %zmm4 {%k2} +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm9[0],xmm6[0],xmm9[1],xmm6[1],xmm9[2],xmm6[2],xmm9[3],xmm6[3],xmm9[4],xmm6[4],xmm9[5],xmm6[5],xmm9[6],xmm6[6],xmm9[7],xmm6[7] +; AVX512DQ-BW-FCP-NEXT: vpunpcklbw {{.*#+}} xmm5 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm5, %zmm13, %zmm5 +; AVX512DQ-BW-FCP-NEXT: vpermw %zmm3, %zmm14, %zmm5 {%k2} +; AVX512DQ-BW-FCP-NEXT: movw $-21846, %ax # imm = 0xAAAA +; AVX512DQ-BW-FCP-NEXT: kmovd %eax, %k1 +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm12, %zmm1 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm16, %zmm15 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm18, %zmm17 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm24, %zmm19 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm21, %zmm20 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm8, %zmm22 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm4, %zmm0 {%k1} +; AVX512DQ-BW-FCP-NEXT: vmovdqa32 %zmm5, %zmm2 {%k1} ; AVX512DQ-BW-FCP-NEXT: movq {{[0-9]+}}(%rsp), %rax ; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm2, (%rax) -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm19, 192(%rax) -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm21, 128(%rax) -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm18, 320(%rax) -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm20, 256(%rax) +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm0, 192(%rax) +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm22, 128(%rax) +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm20, 320(%rax) +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm19, 256(%rax) ; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm17, 448(%rax) -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm16, 384(%rax) -; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm8, 64(%rax) +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm15, 384(%rax) +; AVX512DQ-BW-FCP-NEXT: vmovdqa64 %zmm1, 64(%rax) ; AVX512DQ-BW-FCP-NEXT: vzeroupper ; AVX512DQ-BW-FCP-NEXT: retq %in.vec0 = load <64 x i8>, ptr %in.vecptr0, align 64 -- GitLab From 866a1bc814b4d4cb9aa3890eae56ffa05431741d Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 13:01:26 +0100 Subject: [PATCH 270/695] [X86] Add test coverage for #88030 --- llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll | 856 ++++++++++++++++++ 1 file changed, 856 insertions(+) diff --git a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll index 14a0626ff0ea..3f2220f1a4c4 100644 --- a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll +++ b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll @@ -652,3 +652,859 @@ define void @trunc_v2i64_to_v2i8(ptr %L, ptr %S) nounwind { store <2 x i8> %strided.vec, ptr %S ret void } + +; PR88030 - Select sub-elements and truncate + +define <16 x i8> @evenelts_v32i16_shuffle_v16i16_to_v16i8(<32 x i16> %n2) nounwind { +; SSE2-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; SSE2: # %bb.0: +; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,0,255,0,255,0,255,0] +; SSE2-NEXT: pand %xmm4, %xmm3 +; SSE2-NEXT: pand %xmm4, %xmm2 +; SSE2-NEXT: packuswb %xmm3, %xmm2 +; SSE2-NEXT: pand %xmm4, %xmm1 +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: packuswb %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE42-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; SSE42: # %bb.0: +; SSE42-NEXT: movq {{.*#+}} xmm4 = [0,0,0,0,0,4,8,12,0,0,0,0,0,0,0,0] +; SSE42-NEXT: pshufb %xmm4, %xmm3 +; SSE42-NEXT: pshufb %xmm4, %xmm2 +; SSE42-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE42-NEXT: movd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] +; SSE42-NEXT: pshufb %xmm3, %xmm1 +; SSE42-NEXT: pshufb %xmm3, %xmm0 +; SSE42-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] +; SSE42-NEXT: retq +; +; AVX1-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [0,4,8,12,0,4,8,12,0,4,8,12,0,4,8,12] +; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vmovd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-SLOW-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX2-SLOW: # %bb.0: +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-SLOW-NEXT: vpbroadcastd {{.*#+}} xmm3 = [0,4,8,12,0,4,8,12,0,4,8,12,0,4,8,12] +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-SLOW-NEXT: vmovd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX2-SLOW-NEXT: vzeroupper +; AVX2-SLOW-NEXT: retq +; +; AVX2-FAST-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX2-FAST: # %bb.0: +; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-FAST-NEXT: vpbroadcastd {{.*#+}} xmm3 = [0,4,8,12,0,4,8,12,0,4,8,12,0,4,8,12] +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-FAST-NEXT: vmovd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX2-FAST-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX2-FAST-NEXT: vzeroupper +; AVX2-FAST-NEXT: retq +; +; AVX512-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX512: # %bb.0: +; AVX512-NEXT: vpmovdb %zmm0, %xmm0 +; AVX512-NEXT: vzeroupper +; AVX512-NEXT: retq + %n0 = bitcast <32 x i16> %n2 to <64 x i8> + %p = shufflevector <64 x i8> %n0, <64 x i8> poison, <16 x i32> + ret <16 x i8> %p +} + +define <16 x i8> @oddelts_v32i16_shuffle_v16i16_to_v16i8(<32 x i16> %n2) nounwind { +; SSE2-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; SSE2: # %bb.0: +; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[3,1,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,5,6,7] +; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: pand %xmm4, %xmm3 +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,1,2,0] +; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,7,6,5,4] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,1,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,5,6,7] +; SSE2-NEXT: pand %xmm4, %xmm2 +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] +; SSE2-NEXT: packuswb %xmm3, %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[3,1,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,5,6,7] +; SSE2-NEXT: pand %xmm4, %xmm1 +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,0] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,7,6,5,4] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,1,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,5,6,7] +; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3] +; SSE2-NEXT: retq +; +; SSE42-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; SSE42: # %bb.0: +; SSE42-NEXT: movq {{.*#+}} xmm4 = [0,0,0,0,2,6,10,14,0,0,0,0,0,0,0,0] +; SSE42-NEXT: pshufb %xmm4, %xmm3 +; SSE42-NEXT: pshufb %xmm4, %xmm2 +; SSE42-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE42-NEXT: movd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] +; SSE42-NEXT: pshufb %xmm3, %xmm1 +; SSE42-NEXT: pshufb %xmm3, %xmm0 +; SSE42-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] +; SSE42-NEXT: retq +; +; AVX1-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX1: # %bb.0: +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX1-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 +; AVX1-NEXT: vmovd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7] +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-SLOW-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX2-SLOW: # %bb.0: +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-SLOW-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-SLOW-NEXT: vmovd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX2-SLOW-NEXT: vzeroupper +; AVX2-SLOW-NEXT: retq +; +; AVX2-FAST-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX2-FAST: # %bb.0: +; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-FAST-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-FAST-NEXT: vmovd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX2-FAST-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX2-FAST-NEXT: vzeroupper +; AVX2-FAST-NEXT: retq +; +; AVX512F-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX512F: # %bb.0: +; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX512F-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX512F-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX512F-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX512F-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX512F-NEXT: vpmovdb %zmm0, %xmm0 +; AVX512F-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; AVX512VL-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX512VL-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX512VL-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX512VL-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX512VL-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX512VL-NEXT: vpmovdb %ymm0, %xmm0 +; AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq +; +; AVX512BW-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; AVX512BW-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX512BW-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX512BW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX512BW-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX512BW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX512BW-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX512BW-NEXT: vpmovdb %zmm0, %xmm0 +; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %n0 = bitcast <32 x i16> %n2 to <64 x i8> + %p = shufflevector <64 x i8> %n0, <64 x i8> poison, <16 x i32> + ret <16 x i8> %p +} + +define <16 x i8> @evenelts_v32i16_trunc_v16i16_to_v16i8(<32 x i16> %n2) nounwind { +; SSE2-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; SSE2: # %bb.0: +; SSE2-NEXT: pushq %rbp +; SSE2-NEXT: pushq %r14 +; SSE2-NEXT: pushq %rbx +; SSE2-NEXT: pextrw $2, %xmm0, %eax +; SSE2-NEXT: pextrw $4, %xmm0, %ecx +; SSE2-NEXT: pextrw $6, %xmm0, %edx +; SSE2-NEXT: pextrw $2, %xmm1, %esi +; SSE2-NEXT: pextrw $4, %xmm1, %edi +; SSE2-NEXT: pextrw $6, %xmm1, %r8d +; SSE2-NEXT: pextrw $2, %xmm2, %r9d +; SSE2-NEXT: pextrw $4, %xmm2, %r10d +; SSE2-NEXT: pextrw $6, %xmm2, %r11d +; SSE2-NEXT: pextrw $2, %xmm3, %ebx +; SSE2-NEXT: pextrw $4, %xmm3, %ebp +; SSE2-NEXT: pextrw $6, %xmm3, %r14d +; SSE2-NEXT: movd %r14d, %xmm4 +; SSE2-NEXT: movd %ebp, %xmm5 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3],xmm5[4],xmm4[4],xmm5[5],xmm4[5],xmm5[6],xmm4[6],xmm5[7],xmm4[7] +; SSE2-NEXT: movd %ebx, %xmm4 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3],xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] +; SSE2-NEXT: movd %r11d, %xmm4 +; SSE2-NEXT: movd %r10d, %xmm5 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3],xmm5[4],xmm4[4],xmm5[5],xmm4[5],xmm5[6],xmm4[6],xmm5[7],xmm4[7] +; SSE2-NEXT: movd %r9d, %xmm4 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm5[0],xmm2[1],xmm5[1],xmm2[2],xmm5[2],xmm2[3],xmm5[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE2-NEXT: movd %r8d, %xmm3 +; SSE2-NEXT: movd %edi, %xmm4 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] +; SSE2-NEXT: movd %esi, %xmm3 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3],xmm1[4],xmm3[4],xmm1[5],xmm3[5],xmm1[6],xmm3[6],xmm1[7],xmm3[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3] +; SSE2-NEXT: movd %edx, %xmm3 +; SSE2-NEXT: movd %ecx, %xmm4 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3],xmm4[4],xmm3[4],xmm4[5],xmm3[5],xmm4[6],xmm3[6],xmm4[7],xmm3[7] +; SSE2-NEXT: movd %eax, %xmm3 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; SSE2-NEXT: popq %rbx +; SSE2-NEXT: popq %r14 +; SSE2-NEXT: popq %rbp +; SSE2-NEXT: retq +; +; SSE42-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; SSE42: # %bb.0: +; SSE42-NEXT: pushq %rbp +; SSE42-NEXT: pushq %r14 +; SSE42-NEXT: pushq %rbx +; SSE42-NEXT: pextrw $6, %xmm3, %eax +; SSE42-NEXT: pextrw $4, %xmm3, %ecx +; SSE42-NEXT: pextrw $2, %xmm3, %edx +; SSE42-NEXT: movd %xmm3, %esi +; SSE42-NEXT: pextrw $6, %xmm2, %edi +; SSE42-NEXT: pextrw $4, %xmm2, %r8d +; SSE42-NEXT: pextrw $2, %xmm2, %r9d +; SSE42-NEXT: movd %xmm2, %r10d +; SSE42-NEXT: pextrw $6, %xmm1, %r11d +; SSE42-NEXT: pextrw $4, %xmm1, %ebx +; SSE42-NEXT: pextrw $2, %xmm1, %ebp +; SSE42-NEXT: movd %xmm1, %r14d +; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] +; SSE42-NEXT: pinsrb $4, %r14d, %xmm0 +; SSE42-NEXT: pinsrb $5, %ebp, %xmm0 +; SSE42-NEXT: pinsrb $6, %ebx, %xmm0 +; SSE42-NEXT: pinsrb $7, %r11d, %xmm0 +; SSE42-NEXT: pinsrb $8, %r10d, %xmm0 +; SSE42-NEXT: pinsrb $9, %r9d, %xmm0 +; SSE42-NEXT: pinsrb $10, %r8d, %xmm0 +; SSE42-NEXT: pinsrb $11, %edi, %xmm0 +; SSE42-NEXT: pinsrb $12, %esi, %xmm0 +; SSE42-NEXT: pinsrb $13, %edx, %xmm0 +; SSE42-NEXT: pinsrb $14, %ecx, %xmm0 +; SSE42-NEXT: pinsrb $15, %eax, %xmm0 +; SSE42-NEXT: popq %rbx +; SSE42-NEXT: popq %r14 +; SSE42-NEXT: popq %rbp +; SSE42-NEXT: retq +; +; AVX1-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX1: # %bb.0: +; AVX1-NEXT: pushq %rbp +; AVX1-NEXT: pushq %r14 +; AVX1-NEXT: pushq %rbx +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpextrw $6, %xmm2, %eax +; AVX1-NEXT: vpextrw $4, %xmm2, %ecx +; AVX1-NEXT: vpextrw $2, %xmm2, %edx +; AVX1-NEXT: vmovd %xmm2, %esi +; AVX1-NEXT: vpextrw $6, %xmm1, %edi +; AVX1-NEXT: vpextrw $4, %xmm1, %r8d +; AVX1-NEXT: vpextrw $2, %xmm1, %r9d +; AVX1-NEXT: vmovd %xmm1, %r10d +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpextrw $6, %xmm1, %r11d +; AVX1-NEXT: vpextrw $4, %xmm1, %ebx +; AVX1-NEXT: vpextrw $2, %xmm1, %ebp +; AVX1-NEXT: vmovd %xmm1, %r14d +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX1-NEXT: popq %rbx +; AVX1-NEXT: popq %r14 +; AVX1-NEXT: popq %rbp +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-SLOW-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX2-SLOW: # %bb.0: +; AVX2-SLOW-NEXT: pushq %rbp +; AVX2-SLOW-NEXT: pushq %r14 +; AVX2-SLOW-NEXT: pushq %rbx +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-SLOW-NEXT: vpextrw $6, %xmm2, %eax +; AVX2-SLOW-NEXT: vpextrw $4, %xmm2, %ecx +; AVX2-SLOW-NEXT: vpextrw $2, %xmm2, %edx +; AVX2-SLOW-NEXT: vmovd %xmm2, %esi +; AVX2-SLOW-NEXT: vpextrw $6, %xmm1, %edi +; AVX2-SLOW-NEXT: vpextrw $4, %xmm1, %r8d +; AVX2-SLOW-NEXT: vpextrw $2, %xmm1, %r9d +; AVX2-SLOW-NEXT: vmovd %xmm1, %r10d +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-SLOW-NEXT: vpextrw $6, %xmm1, %r11d +; AVX2-SLOW-NEXT: vpextrw $4, %xmm1, %ebx +; AVX2-SLOW-NEXT: vpextrw $2, %xmm1, %ebp +; AVX2-SLOW-NEXT: vmovd %xmm1, %r14d +; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX2-SLOW-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: popq %rbx +; AVX2-SLOW-NEXT: popq %r14 +; AVX2-SLOW-NEXT: popq %rbp +; AVX2-SLOW-NEXT: vzeroupper +; AVX2-SLOW-NEXT: retq +; +; AVX2-FAST-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX2-FAST: # %bb.0: +; AVX2-FAST-NEXT: pushq %rbp +; AVX2-FAST-NEXT: pushq %r14 +; AVX2-FAST-NEXT: pushq %rbx +; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-FAST-NEXT: vpextrw $6, %xmm2, %eax +; AVX2-FAST-NEXT: vpextrw $4, %xmm2, %ecx +; AVX2-FAST-NEXT: vpextrw $2, %xmm2, %edx +; AVX2-FAST-NEXT: vmovd %xmm2, %esi +; AVX2-FAST-NEXT: vpextrw $6, %xmm1, %edi +; AVX2-FAST-NEXT: vpextrw $4, %xmm1, %r8d +; AVX2-FAST-NEXT: vpextrw $2, %xmm1, %r9d +; AVX2-FAST-NEXT: vmovd %xmm1, %r10d +; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-FAST-NEXT: vpextrw $6, %xmm1, %r11d +; AVX2-FAST-NEXT: vpextrw $4, %xmm1, %ebx +; AVX2-FAST-NEXT: vpextrw $2, %xmm1, %ebp +; AVX2-FAST-NEXT: vmovd %xmm1, %r14d +; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX2-FAST-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX2-FAST-NEXT: popq %rbx +; AVX2-FAST-NEXT: popq %r14 +; AVX2-FAST-NEXT: popq %rbp +; AVX2-FAST-NEXT: vzeroupper +; AVX2-FAST-NEXT: retq +; +; AVX512F-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512F: # %bb.0: +; AVX512F-NEXT: pushq %rbp +; AVX512F-NEXT: pushq %rbx +; AVX512F-NEXT: vpmovdb %zmm0, %xmm1 +; AVX512F-NEXT: vextracti32x4 $3, %zmm0, %xmm2 +; AVX512F-NEXT: vpextrw $6, %xmm2, %eax +; AVX512F-NEXT: vpextrw $4, %xmm2, %ecx +; AVX512F-NEXT: vpextrw $2, %xmm2, %edx +; AVX512F-NEXT: vmovd %xmm2, %esi +; AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm2 +; AVX512F-NEXT: vpextrw $6, %xmm2, %edi +; AVX512F-NEXT: vpextrw $4, %xmm2, %r8d +; AVX512F-NEXT: vpextrw $2, %xmm2, %r9d +; AVX512F-NEXT: vmovd %xmm2, %r10d +; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX512F-NEXT: vpextrw $6, %xmm0, %r11d +; AVX512F-NEXT: vpextrw $4, %xmm0, %ebx +; AVX512F-NEXT: vpextrw $2, %xmm0, %ebp +; AVX512F-NEXT: vpinsrb $5, %ebp, %xmm1, %xmm0 +; AVX512F-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512F-NEXT: popq %rbx +; AVX512F-NEXT: popq %rbp +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: pushq %rbp +; AVX512VL-NEXT: pushq %r14 +; AVX512VL-NEXT: pushq %rbx +; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm1 +; AVX512VL-NEXT: vpextrw $6, %xmm1, %eax +; AVX512VL-NEXT: vpextrw $4, %xmm1, %ecx +; AVX512VL-NEXT: vpextrw $2, %xmm1, %edx +; AVX512VL-NEXT: vmovd %xmm1, %esi +; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm1 +; AVX512VL-NEXT: vpextrw $6, %xmm1, %edi +; AVX512VL-NEXT: vpextrw $4, %xmm1, %r8d +; AVX512VL-NEXT: vpextrw $2, %xmm1, %r9d +; AVX512VL-NEXT: vmovd %xmm1, %r10d +; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX512VL-NEXT: vpextrw $6, %xmm1, %r11d +; AVX512VL-NEXT: vpextrw $4, %xmm1, %ebx +; AVX512VL-NEXT: vpextrw $2, %xmm1, %ebp +; AVX512VL-NEXT: vmovd %xmm1, %r14d +; AVX512VL-NEXT: vpmovdb %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512VL-NEXT: popq %rbx +; AVX512VL-NEXT: popq %r14 +; AVX512VL-NEXT: popq %rbp +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq +; +; AVX512BW-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: pushq %rbp +; AVX512BW-NEXT: pushq %rbx +; AVX512BW-NEXT: vpmovdb %zmm0, %xmm1 +; AVX512BW-NEXT: vextracti32x4 $3, %zmm0, %xmm2 +; AVX512BW-NEXT: vpextrw $6, %xmm2, %eax +; AVX512BW-NEXT: vpextrw $4, %xmm2, %ecx +; AVX512BW-NEXT: vpextrw $2, %xmm2, %edx +; AVX512BW-NEXT: vmovd %xmm2, %esi +; AVX512BW-NEXT: vextracti32x4 $2, %zmm0, %xmm2 +; AVX512BW-NEXT: vpextrw $6, %xmm2, %edi +; AVX512BW-NEXT: vpextrw $4, %xmm2, %r8d +; AVX512BW-NEXT: vpextrw $2, %xmm2, %r9d +; AVX512BW-NEXT: vmovd %xmm2, %r10d +; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm0 +; AVX512BW-NEXT: vpextrw $6, %xmm0, %r11d +; AVX512BW-NEXT: vpextrw $4, %xmm0, %ebx +; AVX512BW-NEXT: vpextrw $2, %xmm0, %ebp +; AVX512BW-NEXT: vpinsrb $5, %ebp, %xmm1, %xmm0 +; AVX512BW-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512BW-NEXT: popq %rbx +; AVX512BW-NEXT: popq %rbp +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %n0 = shufflevector <32 x i16> %n2, <32 x i16> poison, <16 x i32> + %n1 = trunc <16 x i16> %n0 to <16 x i8> + ret <16 x i8> %n1 +} + +define <16 x i8> @oddelts_v32i16_trunc_v16i16_to_v16i8(<32 x i16> %n2) nounwind { +; SSE2-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; SSE2: # %bb.0: +; SSE2-NEXT: pextrw $7, %xmm3, %eax +; SSE2-NEXT: movd %eax, %xmm4 +; SSE2-NEXT: pextrw $5, %xmm3, %eax +; SSE2-NEXT: movd %eax, %xmm5 +; SSE2-NEXT: pextrw $3, %xmm3, %eax +; SSE2-NEXT: movd %eax, %xmm6 +; SSE2-NEXT: pextrw $1, %xmm3, %eax +; SSE2-NEXT: movd %eax, %xmm3 +; SSE2-NEXT: pextrw $7, %xmm2, %eax +; SSE2-NEXT: movd %eax, %xmm7 +; SSE2-NEXT: pextrw $5, %xmm2, %eax +; SSE2-NEXT: movd %eax, %xmm8 +; SSE2-NEXT: pextrw $3, %xmm2, %eax +; SSE2-NEXT: movd %eax, %xmm9 +; SSE2-NEXT: pextrw $1, %xmm2, %eax +; SSE2-NEXT: movd %eax, %xmm2 +; SSE2-NEXT: pextrw $7, %xmm1, %eax +; SSE2-NEXT: movd %eax, %xmm10 +; SSE2-NEXT: pextrw $5, %xmm1, %eax +; SSE2-NEXT: movd %eax, %xmm11 +; SSE2-NEXT: pextrw $3, %xmm1, %eax +; SSE2-NEXT: movd %eax, %xmm12 +; SSE2-NEXT: pextrw $1, %xmm1, %eax +; SSE2-NEXT: movd %eax, %xmm1 +; SSE2-NEXT: pextrw $7, %xmm0, %eax +; SSE2-NEXT: movd %eax, %xmm13 +; SSE2-NEXT: pextrw $5, %xmm0, %eax +; SSE2-NEXT: movd %eax, %xmm14 +; SSE2-NEXT: pextrw $3, %xmm0, %eax +; SSE2-NEXT: movd %eax, %xmm15 +; SSE2-NEXT: pextrw $1, %xmm0, %eax +; SSE2-NEXT: movd %eax, %xmm0 +; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm4[0],xmm5[1],xmm4[1],xmm5[2],xmm4[2],xmm5[3],xmm4[3],xmm5[4],xmm4[4],xmm5[5],xmm4[5],xmm5[6],xmm4[6],xmm5[7],xmm4[7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm6[0],xmm3[1],xmm6[1],xmm3[2],xmm6[2],xmm3[3],xmm6[3],xmm3[4],xmm6[4],xmm3[5],xmm6[5],xmm3[6],xmm6[6],xmm3[7],xmm6[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm5[0],xmm3[1],xmm5[1],xmm3[2],xmm5[2],xmm3[3],xmm5[3] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm8 = xmm8[0],xmm7[0],xmm8[1],xmm7[1],xmm8[2],xmm7[2],xmm8[3],xmm7[3],xmm8[4],xmm7[4],xmm8[5],xmm7[5],xmm8[6],xmm7[6],xmm8[7],xmm7[7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm9[0],xmm2[1],xmm9[1],xmm2[2],xmm9[2],xmm2[3],xmm9[3],xmm2[4],xmm9[4],xmm2[5],xmm9[5],xmm2[6],xmm9[6],xmm2[7],xmm9[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm8[0],xmm2[1],xmm8[1],xmm2[2],xmm8[2],xmm2[3],xmm8[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm11 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm12[0],xmm1[1],xmm12[1],xmm1[2],xmm12[2],xmm1[3],xmm12[3],xmm1[4],xmm12[4],xmm1[5],xmm12[5],xmm1[6],xmm12[6],xmm1[7],xmm12[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm11[0],xmm1[1],xmm11[1],xmm1[2],xmm11[2],xmm1[3],xmm11[3] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm14 = xmm14[0],xmm13[0],xmm14[1],xmm13[1],xmm14[2],xmm13[2],xmm14[3],xmm13[3],xmm14[4],xmm13[4],xmm14[5],xmm13[5],xmm14[6],xmm13[6],xmm14[7],xmm13[7] +; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm15[0],xmm0[1],xmm15[1],xmm0[2],xmm15[2],xmm0[3],xmm15[3],xmm0[4],xmm15[4],xmm0[5],xmm15[5],xmm0[6],xmm15[6],xmm0[7],xmm15[7] +; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm14[0],xmm0[1],xmm14[1],xmm0[2],xmm14[2],xmm0[3],xmm14[3] +; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] +; SSE2-NEXT: retq +; +; SSE42-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; SSE42: # %bb.0: +; SSE42-NEXT: pushq %rbp +; SSE42-NEXT: pushq %r14 +; SSE42-NEXT: pushq %rbx +; SSE42-NEXT: pextrw $7, %xmm3, %eax +; SSE42-NEXT: pextrw $5, %xmm3, %ecx +; SSE42-NEXT: pextrw $3, %xmm3, %edx +; SSE42-NEXT: pextrw $1, %xmm3, %esi +; SSE42-NEXT: pextrw $7, %xmm2, %edi +; SSE42-NEXT: pextrw $5, %xmm2, %r8d +; SSE42-NEXT: pextrw $3, %xmm2, %r9d +; SSE42-NEXT: pextrw $1, %xmm2, %r10d +; SSE42-NEXT: pextrw $7, %xmm1, %r11d +; SSE42-NEXT: pextrw $5, %xmm1, %ebx +; SSE42-NEXT: pextrw $3, %xmm1, %ebp +; SSE42-NEXT: pextrw $1, %xmm1, %r14d +; SSE42-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; SSE42-NEXT: pinsrb $4, %r14d, %xmm0 +; SSE42-NEXT: pinsrb $5, %ebp, %xmm0 +; SSE42-NEXT: pinsrb $6, %ebx, %xmm0 +; SSE42-NEXT: pinsrb $7, %r11d, %xmm0 +; SSE42-NEXT: pinsrb $8, %r10d, %xmm0 +; SSE42-NEXT: pinsrb $9, %r9d, %xmm0 +; SSE42-NEXT: pinsrb $10, %r8d, %xmm0 +; SSE42-NEXT: pinsrb $11, %edi, %xmm0 +; SSE42-NEXT: pinsrb $12, %esi, %xmm0 +; SSE42-NEXT: pinsrb $13, %edx, %xmm0 +; SSE42-NEXT: pinsrb $14, %ecx, %xmm0 +; SSE42-NEXT: pinsrb $15, %eax, %xmm0 +; SSE42-NEXT: popq %rbx +; SSE42-NEXT: popq %r14 +; SSE42-NEXT: popq %rbp +; SSE42-NEXT: retq +; +; AVX1-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX1: # %bb.0: +; AVX1-NEXT: pushq %rbp +; AVX1-NEXT: pushq %r14 +; AVX1-NEXT: pushq %rbx +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 +; AVX1-NEXT: vpextrw $7, %xmm2, %eax +; AVX1-NEXT: vpextrw $5, %xmm2, %ecx +; AVX1-NEXT: vpextrw $3, %xmm2, %edx +; AVX1-NEXT: vpextrw $1, %xmm2, %esi +; AVX1-NEXT: vpextrw $7, %xmm1, %edi +; AVX1-NEXT: vpextrw $5, %xmm1, %r8d +; AVX1-NEXT: vpextrw $3, %xmm1, %r9d +; AVX1-NEXT: vpextrw $1, %xmm1, %r10d +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vpextrw $7, %xmm1, %r11d +; AVX1-NEXT: vpextrw $5, %xmm1, %ebx +; AVX1-NEXT: vpextrw $3, %xmm1, %ebp +; AVX1-NEXT: vpextrw $1, %xmm1, %r14d +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX1-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX1-NEXT: popq %rbx +; AVX1-NEXT: popq %r14 +; AVX1-NEXT: popq %rbp +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-SLOW-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX2-SLOW: # %bb.0: +; AVX2-SLOW-NEXT: pushq %rbp +; AVX2-SLOW-NEXT: pushq %r14 +; AVX2-SLOW-NEXT: pushq %rbx +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-SLOW-NEXT: vpextrw $7, %xmm2, %eax +; AVX2-SLOW-NEXT: vpextrw $5, %xmm2, %ecx +; AVX2-SLOW-NEXT: vpextrw $3, %xmm2, %edx +; AVX2-SLOW-NEXT: vpextrw $1, %xmm2, %esi +; AVX2-SLOW-NEXT: vpextrw $7, %xmm1, %edi +; AVX2-SLOW-NEXT: vpextrw $5, %xmm1, %r8d +; AVX2-SLOW-NEXT: vpextrw $3, %xmm1, %r9d +; AVX2-SLOW-NEXT: vpextrw $1, %xmm1, %r10d +; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-SLOW-NEXT: vpextrw $7, %xmm1, %r11d +; AVX2-SLOW-NEXT: vpextrw $5, %xmm1, %ebx +; AVX2-SLOW-NEXT: vpextrw $3, %xmm1, %ebp +; AVX2-SLOW-NEXT: vpextrw $1, %xmm1, %r14d +; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX2-SLOW-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX2-SLOW-NEXT: popq %rbx +; AVX2-SLOW-NEXT: popq %r14 +; AVX2-SLOW-NEXT: popq %rbp +; AVX2-SLOW-NEXT: vzeroupper +; AVX2-SLOW-NEXT: retq +; +; AVX2-FAST-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX2-FAST: # %bb.0: +; AVX2-FAST-NEXT: pushq %rbp +; AVX2-FAST-NEXT: pushq %r14 +; AVX2-FAST-NEXT: pushq %rbx +; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-FAST-NEXT: vpextrw $7, %xmm2, %eax +; AVX2-FAST-NEXT: vpextrw $5, %xmm2, %ecx +; AVX2-FAST-NEXT: vpextrw $3, %xmm2, %edx +; AVX2-FAST-NEXT: vpextrw $1, %xmm2, %esi +; AVX2-FAST-NEXT: vpextrw $7, %xmm1, %edi +; AVX2-FAST-NEXT: vpextrw $5, %xmm1, %r8d +; AVX2-FAST-NEXT: vpextrw $3, %xmm1, %r9d +; AVX2-FAST-NEXT: vpextrw $1, %xmm1, %r10d +; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-FAST-NEXT: vpextrw $7, %xmm1, %r11d +; AVX2-FAST-NEXT: vpextrw $5, %xmm1, %ebx +; AVX2-FAST-NEXT: vpextrw $3, %xmm1, %ebp +; AVX2-FAST-NEXT: vpextrw $1, %xmm1, %r14d +; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX2-FAST-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX2-FAST-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX2-FAST-NEXT: popq %rbx +; AVX2-FAST-NEXT: popq %r14 +; AVX2-FAST-NEXT: popq %rbp +; AVX2-FAST-NEXT: vzeroupper +; AVX2-FAST-NEXT: retq +; +; AVX512F-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512F: # %bb.0: +; AVX512F-NEXT: pushq %rbp +; AVX512F-NEXT: pushq %r14 +; AVX512F-NEXT: pushq %rbx +; AVX512F-NEXT: vextracti32x4 $3, %zmm0, %xmm1 +; AVX512F-NEXT: vpextrw $7, %xmm1, %eax +; AVX512F-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512F-NEXT: vpextrw $3, %xmm1, %edx +; AVX512F-NEXT: vpextrw $1, %xmm1, %esi +; AVX512F-NEXT: vextracti32x4 $2, %zmm0, %xmm1 +; AVX512F-NEXT: vpextrw $7, %xmm1, %edi +; AVX512F-NEXT: vpextrw $5, %xmm1, %r8d +; AVX512F-NEXT: vpextrw $3, %xmm1, %r9d +; AVX512F-NEXT: vpextrw $1, %xmm1, %r10d +; AVX512F-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX512F-NEXT: vpextrw $7, %xmm1, %r11d +; AVX512F-NEXT: vpextrw $5, %xmm1, %ebx +; AVX512F-NEXT: vpextrw $3, %xmm1, %ebp +; AVX512F-NEXT: vpextrw $1, %xmm1, %r14d +; AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512F-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512F-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512F-NEXT: popq %rbx +; AVX512F-NEXT: popq %r14 +; AVX512F-NEXT: popq %rbp +; AVX512F-NEXT: vzeroupper +; AVX512F-NEXT: retq +; +; AVX512VL-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512VL: # %bb.0: +; AVX512VL-NEXT: pushq %rbp +; AVX512VL-NEXT: pushq %r14 +; AVX512VL-NEXT: pushq %rbx +; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm1 +; AVX512VL-NEXT: vpextrw $7, %xmm1, %eax +; AVX512VL-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512VL-NEXT: vpextrw $3, %xmm1, %edx +; AVX512VL-NEXT: vpextrw $1, %xmm1, %esi +; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm1 +; AVX512VL-NEXT: vpextrw $7, %xmm1, %edi +; AVX512VL-NEXT: vpextrw $5, %xmm1, %r8d +; AVX512VL-NEXT: vpextrw $3, %xmm1, %r9d +; AVX512VL-NEXT: vpextrw $1, %xmm1, %r10d +; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX512VL-NEXT: vpextrw $7, %xmm1, %r11d +; AVX512VL-NEXT: vpextrw $5, %xmm1, %ebx +; AVX512VL-NEXT: vpextrw $3, %xmm1, %ebp +; AVX512VL-NEXT: vpextrw $1, %xmm1, %r14d +; AVX512VL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512VL-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512VL-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512VL-NEXT: popq %rbx +; AVX512VL-NEXT: popq %r14 +; AVX512VL-NEXT: popq %rbp +; AVX512VL-NEXT: vzeroupper +; AVX512VL-NEXT: retq +; +; AVX512BW-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512BW: # %bb.0: +; AVX512BW-NEXT: pushq %rbp +; AVX512BW-NEXT: pushq %r14 +; AVX512BW-NEXT: pushq %rbx +; AVX512BW-NEXT: vextracti32x4 $3, %zmm0, %xmm1 +; AVX512BW-NEXT: vpextrw $7, %xmm1, %eax +; AVX512BW-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512BW-NEXT: vpextrw $3, %xmm1, %edx +; AVX512BW-NEXT: vpextrw $1, %xmm1, %esi +; AVX512BW-NEXT: vextracti32x4 $2, %zmm0, %xmm1 +; AVX512BW-NEXT: vpextrw $7, %xmm1, %edi +; AVX512BW-NEXT: vpextrw $5, %xmm1, %r8d +; AVX512BW-NEXT: vpextrw $3, %xmm1, %r9d +; AVX512BW-NEXT: vpextrw $1, %xmm1, %r10d +; AVX512BW-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX512BW-NEXT: vpextrw $7, %xmm1, %r11d +; AVX512BW-NEXT: vpextrw $5, %xmm1, %ebx +; AVX512BW-NEXT: vpextrw $3, %xmm1, %ebp +; AVX512BW-NEXT: vpextrw $1, %xmm1, %r14d +; AVX512BW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512BW-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512BW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512BW-NEXT: popq %rbx +; AVX512BW-NEXT: popq %r14 +; AVX512BW-NEXT: popq %rbp +; AVX512BW-NEXT: vzeroupper +; AVX512BW-NEXT: retq + %n0 = shufflevector <32 x i16> %n2, <32 x i16> poison, <16 x i32> + %n1 = trunc <16 x i16> %n0 to <16 x i8> + ret <16 x i8> %n1 +} -- GitLab From 4657ab1c968e486e9f45329daa07340ebcf3bffd Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Tue, 9 Apr 2024 08:31:52 -0400 Subject: [PATCH 271/695] [Clang][Sema] Fix crash when 'this' is used in a dependent class scope function template specialization that instantiates to a static member function (#87541) This patch fixes a crash that happens when '`this`' is referenced (implicitly or explicitly) in a dependent class scope function template specialization that instantiates to a static member function. For example: ``` template struct A { template static void f(); template<> void f() { this; // causes crash during instantiation } }; template struct A; ``` This happens because during instantiation of the function body, `Sema::getCurrentThisType` will return a null `QualType` which we rebuild the `CXXThisExpr` with. A similar problem exists for implicit class member access expressions in such contexts (which shouldn't really happen within templates anyways per [class.mfct.non.static] p2, but changing that is non-trivial). This patch fixes the crash by building `UnresolvedLookupExpr`s instead of `MemberExpr`s for these implicit member accesses, which will then be correctly rebuilt as `MemberExpr`s during instantiation. --- clang/docs/ReleaseNotes.rst | 2 + clang/include/clang/Sema/Sema.h | 8 +++- clang/lib/Sema/SemaExpr.cpp | 5 ++- clang/lib/Sema/SemaExprCXX.cpp | 44 +++++++++++++------ clang/lib/Sema/SemaExprMember.cpp | 42 +++++++++++++----- .../lib/Sema/SemaTemplateInstantiateDecl.cpp | 8 ++++ clang/lib/Sema/TreeTransform.h | 7 +-- ...ms-function-specialization-class-scope.cpp | 44 +++++++++++++++++-- 8 files changed, 124 insertions(+), 36 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 8d9ccf789d9c..30cedbe774be 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -507,6 +507,8 @@ Bug Fixes to C++ Support - Fix an issue caused by not handling invalid cases when substituting into the parameter mapping of a constraint. Fixes (#GH86757). - Fixed a bug that prevented member function templates of class templates declared with a deduced return type from being explicitly specialized for a given implicit instantiation of the class template. +- Fixed a crash when ``this`` is used in a dependent class scope function template specialization + that instantiates to a static member function. - Fix crash when inheriting from a cv-qualified type. Fixes: (`#35603 `_) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 9769d3690066..f311f9f37434 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -5439,7 +5439,8 @@ public: ExprResult BuildDeclarationNameExpr(const CXXScopeSpec &SS, LookupResult &R, bool NeedsADL, - bool AcceptInvalidDecl = false); + bool AcceptInvalidDecl = false, + bool NeedUnresolved = false); ExprResult BuildDeclarationNameExpr( const CXXScopeSpec &SS, const DeclarationNameInfo &NameInfo, NamedDecl *D, NamedDecl *FoundD = nullptr, @@ -6591,7 +6592,10 @@ public: SourceLocation RParenLoc); //// ActOnCXXThis - Parse 'this' pointer. - ExprResult ActOnCXXThis(SourceLocation loc); + ExprResult ActOnCXXThis(SourceLocation Loc); + + /// Check whether the type of 'this' is valid in the current context. + bool CheckCXXThisType(SourceLocation Loc, QualType Type); /// Build a CXXThisExpr and mark it referenced in the current context. Expr *BuildCXXThisExpr(SourceLocation Loc, QualType Type, bool IsImplicit); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 8db4fffeecfe..7b91bbe0b205 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -3442,10 +3442,11 @@ static bool ShouldLookupResultBeMultiVersionOverload(const LookupResult &R) { ExprResult Sema::BuildDeclarationNameExpr(const CXXScopeSpec &SS, LookupResult &R, bool NeedsADL, - bool AcceptInvalidDecl) { + bool AcceptInvalidDecl, + bool NeedUnresolved) { // If this is a single, fully-resolved result and we don't need ADL, // just build an ordinary singleton decl ref. - if (!NeedsADL && R.isSingleResult() && + if (!NeedUnresolved && !NeedsADL && R.isSingleResult() && !R.getAsSingle() && !ShouldLookupResultBeMultiVersionOverload(R)) return BuildDeclarationNameExpr(SS, R.getLookupNameInfo(), R.getFoundDecl(), diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index dee6b658cd00..9ba414324019 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -1415,26 +1415,42 @@ bool Sema::CheckCXXThisCapture(SourceLocation Loc, const bool Explicit, } ExprResult Sema::ActOnCXXThis(SourceLocation Loc) { - /// C++ 9.3.2: In the body of a non-static member function, the keyword this - /// is a non-lvalue expression whose value is the address of the object for - /// which the function is called. + // C++20 [expr.prim.this]p1: + // The keyword this names a pointer to the object for which an + // implicit object member function is invoked or a non-static + // data member's initializer is evaluated. QualType ThisTy = getCurrentThisType(); - if (ThisTy.isNull()) { - DeclContext *DC = getFunctionLevelDeclContext(); + if (CheckCXXThisType(Loc, ThisTy)) + return ExprError(); - if (const auto *Method = dyn_cast(DC); - Method && Method->isExplicitObjectMemberFunction()) { - return Diag(Loc, diag::err_invalid_this_use) << 1; - } + return BuildCXXThisExpr(Loc, ThisTy, /*IsImplicit=*/false); +} - if (isLambdaCallWithExplicitObjectParameter(CurContext)) - return Diag(Loc, diag::err_invalid_this_use) << 1; +bool Sema::CheckCXXThisType(SourceLocation Loc, QualType Type) { + if (!Type.isNull()) + return false; - return Diag(Loc, diag::err_invalid_this_use) << 0; + // C++20 [expr.prim.this]p3: + // If a declaration declares a member function or member function template + // of a class X, the expression this is a prvalue of type + // "pointer to cv-qualifier-seq X" wherever X is the current class between + // the optional cv-qualifier-seq and the end of the function-definition, + // member-declarator, or declarator. It shall not appear within the + // declaration of either a static member function or an explicit object + // member function of the current class (although its type and value + // category are defined within such member functions as they are within + // an implicit object member function). + DeclContext *DC = getFunctionLevelDeclContext(); + if (const auto *Method = dyn_cast(DC); + Method && Method->isExplicitObjectMemberFunction()) { + Diag(Loc, diag::err_invalid_this_use) << 1; + } else if (isLambdaCallWithExplicitObjectParameter(CurContext)) { + Diag(Loc, diag::err_invalid_this_use) << 1; + } else { + Diag(Loc, diag::err_invalid_this_use) << 0; } - - return BuildCXXThisExpr(Loc, ThisTy, /*IsImplicit=*/false); + return true; } Expr *Sema::BuildCXXThisExpr(SourceLocation Loc, QualType Type, diff --git a/clang/lib/Sema/SemaExprMember.cpp b/clang/lib/Sema/SemaExprMember.cpp index 32998ae60eaf..8cd2288d279c 100644 --- a/clang/lib/Sema/SemaExprMember.cpp +++ b/clang/lib/Sema/SemaExprMember.cpp @@ -61,6 +61,10 @@ enum IMAKind { /// The reference is a contextually-permitted abstract member reference. IMA_Abstract, + /// Whether the context is static is dependent on the enclosing template (i.e. + /// in a dependent class scope explicit specialization). + IMA_Dependent, + /// The reference may be to an unresolved using declaration and the /// context is not an instance method. IMA_Unresolved_StaticOrExplicitContext, @@ -91,10 +95,18 @@ static IMAKind ClassifyImplicitMemberAccess(Sema &SemaRef, DeclContext *DC = SemaRef.getFunctionLevelDeclContext(); - bool isStaticOrExplicitContext = - SemaRef.CXXThisTypeOverride.isNull() && - (!isa(DC) || cast(DC)->isStatic() || - cast(DC)->isExplicitObjectMemberFunction()); + bool couldInstantiateToStatic = false; + bool isStaticOrExplicitContext = SemaRef.CXXThisTypeOverride.isNull(); + + if (auto *MD = dyn_cast(DC)) { + if (MD->isImplicitObjectMemberFunction()) { + isStaticOrExplicitContext = false; + // A dependent class scope function template explicit specialization + // that is neither declared 'static' nor with an explicit object + // parameter could instantiate to a static or non-static member function. + couldInstantiateToStatic = MD->getDependentSpecializationInfo(); + } + } if (R.isUnresolvableResult()) return isStaticOrExplicitContext ? IMA_Unresolved_StaticOrExplicitContext @@ -123,6 +135,9 @@ static IMAKind ClassifyImplicitMemberAccess(Sema &SemaRef, if (Classes.empty()) return IMA_Static; + if (couldInstantiateToStatic) + return IMA_Dependent; + // C++11 [expr.prim.general]p12: // An id-expression that denotes a non-static data member or non-static // member function of a class can only be used: @@ -268,27 +283,30 @@ ExprResult Sema::BuildPossibleImplicitMemberExpr( const CXXScopeSpec &SS, SourceLocation TemplateKWLoc, LookupResult &R, const TemplateArgumentListInfo *TemplateArgs, const Scope *S, UnresolvedLookupExpr *AsULE) { - switch (ClassifyImplicitMemberAccess(*this, R)) { + switch (IMAKind Classification = ClassifyImplicitMemberAccess(*this, R)) { case IMA_Instance: - return BuildImplicitMemberExpr(SS, TemplateKWLoc, R, TemplateArgs, true, S); - case IMA_Mixed: case IMA_Mixed_Unrelated: case IMA_Unresolved: - return BuildImplicitMemberExpr(SS, TemplateKWLoc, R, TemplateArgs, false, - S); - + return BuildImplicitMemberExpr( + SS, TemplateKWLoc, R, TemplateArgs, + /*IsKnownInstance=*/Classification == IMA_Instance, S); case IMA_Field_Uneval_Context: Diag(R.getNameLoc(), diag::warn_cxx98_compat_non_static_member_use) << R.getLookupNameInfo().getName(); [[fallthrough]]; case IMA_Static: case IMA_Abstract: + case IMA_Dependent: case IMA_Mixed_StaticOrExplicitContext: case IMA_Unresolved_StaticOrExplicitContext: if (TemplateArgs || TemplateKWLoc.isValid()) - return BuildTemplateIdExpr(SS, TemplateKWLoc, R, false, TemplateArgs); - return AsULE ? AsULE : BuildDeclarationNameExpr(SS, R, false); + return BuildTemplateIdExpr(SS, TemplateKWLoc, R, /*RequiresADL=*/false, + TemplateArgs); + return AsULE ? AsULE + : BuildDeclarationNameExpr( + SS, R, /*NeedsADL=*/false, /*AcceptInvalidDecl=*/false, + /*NeedUnresolved=*/Classification == IMA_Dependent); case IMA_Error_StaticOrExplicitContext: case IMA_Error_Unrelated: diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp index 127a432367b9..8248b10814fe 100644 --- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp @@ -5093,6 +5093,14 @@ void Sema::InstantiateFunctionDefinition(SourceLocation PointOfInstantiation, EnterExpressionEvaluationContext EvalContext( *this, Sema::ExpressionEvaluationContext::PotentiallyEvaluated); + Qualifiers ThisTypeQuals; + CXXRecordDecl *ThisContext = nullptr; + if (CXXMethodDecl *Method = dyn_cast(Function)) { + ThisContext = Method->getParent(); + ThisTypeQuals = Method->getMethodQualifiers(); + } + CXXThisScopeRAII ThisScope(*this, ThisContext, ThisTypeQuals); + // Introduce a new scope where local variable instantiations will be // recorded, unless we're actually a member function within a local // class, in which case we need to merge our results with the parent diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index ab97b375f516..6ebca07eaa4f 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -3307,12 +3307,13 @@ public: /// Build a new C++ "this" expression. /// - /// By default, builds a new "this" expression without performing any - /// semantic analysis. Subclasses may override this routine to provide - /// different behavior. + /// By default, performs semantic analysis to build a new "this" expression. + /// Subclasses may override this routine to provide different behavior. ExprResult RebuildCXXThisExpr(SourceLocation ThisLoc, QualType ThisType, bool isImplicit) { + if (getSema().CheckCXXThisType(ThisLoc, ThisType)) + return ExprError(); return getSema().BuildCXXThisExpr(ThisLoc, ThisType, isImplicit); } diff --git a/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp b/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp index dcab9bfaeabc..6977623a0816 100644 --- a/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp +++ b/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp @@ -1,7 +1,6 @@ -// RUN: %clang_cc1 -fms-extensions -fsyntax-only -verify %s -// RUN: %clang_cc1 -fms-extensions -fdelayed-template-parsing -fsyntax-only -verify %s +// RUN: %clang_cc1 -fms-extensions -fsyntax-only -Wno-unused-value -verify %s +// RUN: %clang_cc1 -fms-extensions -fdelayed-template-parsing -fsyntax-only -Wno-unused-value -verify %s -// expected-no-diagnostics class A { public: template A(U p) {} @@ -76,3 +75,42 @@ struct S { int f<0>(int); }; } + +namespace UsesThis { + template + struct A { + int x; + + template + static void f(); + + template<> + void f() { + this->x; // expected-error {{invalid use of 'this' outside of a non-static member function}} + x; // expected-error {{invalid use of member 'x' in static member function}} + A::x; // expected-error {{invalid use of member 'x' in static member function}} + +x; // expected-error {{invalid use of member 'x' in static member function}} + +A::x; // expected-error {{invalid use of member 'x' in static member function}} + } + + template + void g(); + + template<> + void g() { + this->x; + x; + A::x; + +x; + +A::x; + } + + template + static auto h() -> A*; + + template<> + auto h() -> decltype(this); // expected-error {{'this' cannot be used in a static member function declaration}} + }; + + template struct A; // expected-note 2{{in instantiation of}} +} -- GitLab From 6528f103663af2f08474c16a1bb9ca0f1c2ad31d Mon Sep 17 00:00:00 2001 From: Sergio Afonso Date: Tue, 9 Apr 2024 13:40:18 +0100 Subject: [PATCH 272/695] [MLIR][OpenMP] Group clause operands into structures and use them to define simplified op builders (#86797) This patch introduces a set of composable structures grouping the MLIR operands associated to each OpenMP clause. This makes it easier to keep the MLIR representation for the same clause consistent throughout all operations that accept it. The relevant clause operand structures are grouped into per-operation structures using a mixin pattern and used to define new operation constructors. These constructors can be used to avoid having to get the order of a possibly large list of operands right. Missing clauses are documented as TODOs, as well as operands which are part of the relevant operation's operand structure but cannot be attached to the associated operation yet, due to missing op arguments to its MLIR definition. A follow-up patch will update Flang lowering to make use of these structures, simplifying the passing of information from clause processing to operation-generating functions and also simplifying the creation of operations through the use of the new operation constructors. --- .../Dialect/OpenMP/OpenMPClauseOperands.h | 300 ++++++++++++++++++ .../mlir/Dialect/OpenMP/OpenMPDialect.h | 7 +- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 72 ++++- mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 226 ++++++++++++- 4 files changed, 595 insertions(+), 10 deletions(-) create mode 100644 mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h new file mode 100644 index 000000000000..6454076f7593 --- /dev/null +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h @@ -0,0 +1,300 @@ +//===-- OpenMPClauseOperands.h ----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares the structures defining MLIR operands associated with each +// OpenMP clause, and structures grouping the appropriate operands for each +// construct. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_DIALECT_OPENMP_OPENMPCLAUSEOPERANDS_H_ +#define MLIR_DIALECT_OPENMP_OPENMPCLAUSEOPERANDS_H_ + +#include "mlir/IR/BuiltinAttributes.h" +#include "llvm/ADT/SmallVector.h" + +#include "mlir/Dialect/OpenMP/OpenMPOpsEnums.h.inc" + +#define GET_ATTRDEF_CLASSES +#include "mlir/Dialect/OpenMP/OpenMPOpsAttributes.h.inc" + +namespace mlir { +namespace omp { + +//===----------------------------------------------------------------------===// +// Mixin structures defining MLIR operands associated with each OpenMP clause. +//===----------------------------------------------------------------------===// + +struct AlignedClauseOps { + llvm::SmallVector alignedVars; + llvm::SmallVector alignmentAttrs; +}; + +struct AllocateClauseOps { + llvm::SmallVector allocatorVars, allocateVars; +}; + +struct CollapseClauseOps { + llvm::SmallVector loopLBVar, loopUBVar, loopStepVar; +}; + +struct CopyprivateClauseOps { + llvm::SmallVector copyprivateVars; + llvm::SmallVector copyprivateFuncs; +}; + +struct DependClauseOps { + llvm::SmallVector dependTypeAttrs; + llvm::SmallVector dependVars; +}; + +struct DeviceClauseOps { + Value deviceVar; +}; + +struct DeviceTypeClauseOps { + // The default capture type. + DeclareTargetDeviceType deviceType = DeclareTargetDeviceType::any; +}; + +struct DistScheduleClauseOps { + UnitAttr distScheduleStaticAttr; + Value distScheduleChunkSizeVar; +}; + +struct DoacrossClauseOps { + llvm::SmallVector doacrossVectorVars; + ClauseDependAttr doacrossDependTypeAttr; + IntegerAttr doacrossNumLoopsAttr; +}; + +struct FinalClauseOps { + Value finalVar; +}; + +struct GrainsizeClauseOps { + Value grainsizeVar; +}; + +struct HintClauseOps { + IntegerAttr hintAttr; +}; + +struct IfClauseOps { + Value ifVar; +}; + +struct InReductionClauseOps { + llvm::SmallVector inReductionVars; + llvm::SmallVector inReductionDeclSymbols; +}; + +struct LinearClauseOps { + llvm::SmallVector linearVars, linearStepVars; +}; + +struct LoopRelatedOps { + UnitAttr loopInclusiveAttr; +}; + +struct MapClauseOps { + llvm::SmallVector mapVars; +}; + +struct MergeableClauseOps { + UnitAttr mergeableAttr; +}; + +struct NameClauseOps { + StringAttr nameAttr; +}; + +struct NogroupClauseOps { + UnitAttr nogroupAttr; +}; + +struct NontemporalClauseOps { + llvm::SmallVector nontemporalVars; +}; + +struct NowaitClauseOps { + UnitAttr nowaitAttr; +}; + +struct NumTasksClauseOps { + Value numTasksVar; +}; + +struct NumTeamsClauseOps { + Value numTeamsLowerVar, numTeamsUpperVar; +}; + +struct NumThreadsClauseOps { + Value numThreadsVar; +}; + +struct OrderClauseOps { + ClauseOrderKindAttr orderAttr; +}; + +struct OrderedClauseOps { + IntegerAttr orderedAttr; +}; + +struct ParallelizationLevelClauseOps { + UnitAttr parLevelSimdAttr; +}; + +struct PriorityClauseOps { + Value priorityVar; +}; + +struct PrivateClauseOps { + // SSA values that correspond to "original" values being privatized. + // They refer to the SSA value outside the OpenMP region from which a clone is + // created inside the region. + llvm::SmallVector privateVars; + // The list of symbols referring to delayed privatizer ops (i.e. `omp.private` + // ops). + llvm::SmallVector privatizers; +}; + +struct ProcBindClauseOps { + ClauseProcBindKindAttr procBindKindAttr; +}; + +struct ReductionClauseOps { + llvm::SmallVector reductionVars; + llvm::SmallVector reductionDeclSymbols; + UnitAttr reductionByRefAttr; +}; + +struct SafelenClauseOps { + IntegerAttr safelenAttr; +}; + +struct ScheduleClauseOps { + ClauseScheduleKindAttr scheduleValAttr; + ScheduleModifierAttr scheduleModAttr; + Value scheduleChunkVar; + UnitAttr scheduleSimdAttr; +}; + +struct SimdlenClauseOps { + IntegerAttr simdlenAttr; +}; + +struct TaskReductionClauseOps { + llvm::SmallVector taskReductionVars; + llvm::SmallVector taskReductionDeclSymbols; +}; + +struct ThreadLimitClauseOps { + Value threadLimitVar; +}; + +struct UntiedClauseOps { + UnitAttr untiedAttr; +}; + +struct UseDeviceClauseOps { + llvm::SmallVector useDevicePtrVars, useDeviceAddrVars; +}; + +//===----------------------------------------------------------------------===// +// Structures defining clause operands associated with each OpenMP leaf +// construct. +// +// These mirror the arguments expected by the corresponding OpenMP MLIR ops. +//===----------------------------------------------------------------------===// + +namespace detail { +template +struct Clauses : public Mixins... {}; +} // namespace detail + +using CriticalClauseOps = detail::Clauses; + +// TODO `indirect` clause. +using DeclareTargetClauseOps = detail::Clauses; + +using DistributeClauseOps = + detail::Clauses; + +// TODO `filter` clause. +using MaskedClauseOps = detail::Clauses<>; + +using OrderedOpClauseOps = detail::Clauses; + +using OrderedRegionClauseOps = detail::Clauses; + +using ParallelClauseOps = + detail::Clauses; + +using SectionsClauseOps = detail::Clauses; + +// TODO `linear` clause. +using SimdLoopClauseOps = + detail::Clauses; + +using SingleClauseOps = detail::Clauses; + +// TODO `defaultmap`, `has_device_addr`, `is_device_ptr`, `uses_allocators` +// clauses. +using TargetClauseOps = + detail::Clauses; + +using TargetDataClauseOps = detail::Clauses; + +using TargetEnterExitUpdateDataClauseOps = + detail::Clauses; + +// TODO `affinity`, `detach` clauses. +using TaskClauseOps = + detail::Clauses; + +using TaskgroupClauseOps = + detail::Clauses; + +using TaskloopClauseOps = + detail::Clauses; + +using TaskwaitClauseOps = detail::Clauses; + +using TeamsClauseOps = + detail::Clauses; + +using WsloopClauseOps = + detail::Clauses; + +} // namespace omp +} // namespace mlir + +#endif // MLIR_DIALECT_OPENMP_OPENMPCLAUSEOPERANDS_H_ diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h b/mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h index 23509c5b6070..c656bdc87097 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPDialect.h @@ -26,11 +26,10 @@ #include "mlir/Dialect/OpenMP/OpenMPOpsTypes.h.inc" #include "mlir/Dialect/OpenMP/OpenMPOpsDialect.h.inc" -#include "mlir/Dialect/OpenMP/OpenMPOpsEnums.h.inc" -#include "mlir/Dialect/OpenMP/OpenMPTypeInterfaces.h.inc" -#define GET_ATTRDEF_CLASSES -#include "mlir/Dialect/OpenMP/OpenMPOpsAttributes.h.inc" +#include "mlir/Dialect/OpenMP/OpenMPClauseOperands.h" + +#include "mlir/Dialect/OpenMP/OpenMPTypeInterfaces.h.inc" #include "mlir/Dialect/OpenMP/OpenMPInterfaces.h" diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index 457451886e14..a38a82f9cc60 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -287,7 +287,8 @@ def ParallelOp : OpenMP_Op<"parallel", [ let regions = (region AnyRegion:$region); let builders = [ - OpBuilder<(ins CArg<"ArrayRef", "{}">:$attributes)> + OpBuilder<(ins CArg<"ArrayRef", "{}">:$attributes)>, + OpBuilder<(ins CArg<"const ParallelClauseOps &">:$clauses)> ]; let extraClassDeclaration = [{ /// Returns the number of reduction variables. @@ -362,6 +363,10 @@ def TeamsOp : OpenMP_Op<"teams", [ let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const TeamsClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist( `num_teams` `(` ( $num_teams_lower^ `:` type($num_teams_lower) )? `to` @@ -451,6 +456,10 @@ def SectionsOp : OpenMP_Op<"sections", [AttrSizedOperandSegments, let regions = (region SizedRegion<1>:$region); + let builders = [ + OpBuilder<(ins CArg<"const SectionsClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist( `reduction` `(` custom( @@ -495,6 +504,10 @@ def SingleOp : OpenMP_Op<"single", [AttrSizedOperandSegments]> { let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const SingleClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`allocate` `(` custom( @@ -601,6 +614,7 @@ def WsloopOp : OpenMP_Op<"wsloop", [AttrSizedOperandSegments, OpBuilder<(ins "ValueRange":$lowerBound, "ValueRange":$upperBound, "ValueRange":$step, CArg<"ArrayRef", "{}">:$attributes)>, + OpBuilder<(ins CArg<"const WsloopClauseOps &">:$clauses)> ]; let regions = (region AnyRegion:$region); @@ -698,6 +712,11 @@ def SimdLoopOp : OpenMP_Op<"simdloop", [AttrSizedOperandSegments, ); let regions = (region AnyRegion:$region); + + let builders = [ + OpBuilder<(ins CArg<"const SimdLoopClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`aligned` `(` custom($aligned_vars, type($aligned_vars), @@ -781,6 +800,10 @@ def DistributeOp : OpenMP_Op<"distribute", [AttrSizedOperandSegments, let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const DistributeClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`dist_schedule_static` $dist_schedule_static |`chunk_size` `(` $chunk_size `:` type($chunk_size) `)` @@ -883,6 +906,9 @@ def TaskOp : OpenMP_Op<"task", [AttrSizedOperandSegments, Variadic:$allocate_vars, Variadic:$allocators_vars); let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const TaskClauseOps &">:$clauses)> + ]; let assemblyFormat = [{ oilist(`if` `(` $if_expr `)` |`final` `(` $final_expr `)` @@ -1037,6 +1063,10 @@ def TaskloopOp : OpenMP_Op<"taskloop", [AttrSizedOperandSegments, let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const TaskloopClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`if` `(` $if_expr `)` |`final` `(` $final_expr `)` @@ -1106,6 +1136,10 @@ def TaskgroupOp : OpenMP_Op<"taskgroup", [AttrSizedOperandSegments, let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const TaskgroupClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`task_reduction` `(` custom( @@ -1432,6 +1466,10 @@ def TargetDataOp: OpenMP_Op<"target_data", [AttrSizedOperandSegments, let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const TargetDataClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`if` `(` $if_expr `:` type($if_expr) `)` | `device` `(` $device `:` type($device) `)` @@ -1486,6 +1524,10 @@ def TargetEnterDataOp: OpenMP_Op<"target_enter_data", UnitAttr:$nowait, Variadic:$map_operands); + let builders = [ + OpBuilder<(ins CArg<"const TargetEnterExitUpdateDataClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`if` `(` $if_expr `:` type($if_expr) `)` | `device` `(` $device `:` type($device) `)` @@ -1540,6 +1582,10 @@ def TargetExitDataOp: OpenMP_Op<"target_exit_data", UnitAttr:$nowait, Variadic:$map_operands); + let builders = [ + OpBuilder<(ins CArg<"const TargetEnterExitUpdateDataClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`if` `(` $if_expr `:` type($if_expr) `)` | `device` `(` $device `:` type($device) `)` @@ -1596,6 +1642,10 @@ def TargetUpdateOp: OpenMP_Op<"target_update", [AttrSizedOperandSegments, UnitAttr:$nowait, Variadic:$map_operands); + let builders = [ + OpBuilder<(ins CArg<"const TargetEnterExitUpdateDataClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist(`if` `(` $if_expr `:` type($if_expr) `)` | `device` `(` $device `:` type($device) `)` @@ -1649,6 +1699,10 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const TargetClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ oilist( `if` `(` $if_expr `)` | `device` `(` $device `:` type($device) `)` @@ -1693,6 +1747,10 @@ def CriticalDeclareOp : OpenMP_Op<"critical.declare", [Symbol]> { let arguments = (ins SymbolNameAttr:$sym_name, DefaultValuedAttr:$hint_val); + let builders = [ + OpBuilder<(ins CArg<"const CriticalClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ $sym_name oilist(`hint` `(` custom($hint_val) `)`) attr-dict @@ -1773,6 +1831,10 @@ def OrderedOp : OpenMP_Op<"ordered"> { ConfinedAttr, [IntMinValue<0>]>:$num_loops_val, Variadic:$depend_vec_vars); + let builders = [ + OpBuilder<(ins CArg<"const OrderedOpClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ ( `depend_type` `` $depend_type_val^ )? ( `depend_vec` `(` $depend_vec_vars^ `:` type($depend_vec_vars) `)` )? @@ -1797,6 +1859,10 @@ def OrderedRegionOp : OpenMP_Op<"ordered.region"> { let regions = (region AnyRegion:$region); + let builders = [ + OpBuilder<(ins CArg<"const OrderedRegionClauseOps &">:$clauses)> + ]; + let assemblyFormat = [{ ( `simd` $simd^ )? $region attr-dict}]; let hasVerifier = 1; } @@ -1812,6 +1878,10 @@ def TaskwaitOp : OpenMP_Op<"taskwait"> { of the current task. }]; + let builders = [ + OpBuilder<(ins CArg<"const TaskwaitClauseOps &">:$clauses)> + ]; + let assemblyFormat = "attr-dict"; } diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index a04343154a4d..543655338db8 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -41,6 +41,11 @@ using namespace mlir; using namespace mlir::omp; +static ArrayAttr makeArrayAttr(MLIRContext *context, + llvm::ArrayRef attrs) { + return attrs.empty() ? nullptr : ArrayAttr::get(context, attrs); +} + namespace { struct MemRefPointerLikeModel : public PointerLikeType::ExternalModel static LogicalResult verifyPrivateVarList(OpType &op) { auto privateVars = op.getPrivateVars(); @@ -1280,6 +1364,17 @@ static bool opInGlobalImplicitParallelRegion(Operation *op) { return true; } +void TeamsOp::build(OpBuilder &builder, OperationState &state, + const TeamsClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: reductionByRefAttr, privateVars, privatizers. + TeamsOp::build(builder, state, clauses.numTeamsLowerVar, + clauses.numTeamsUpperVar, clauses.ifVar, + clauses.threadLimitVar, clauses.allocateVars, + clauses.allocatorVars, clauses.reductionVars, + makeArrayAttr(ctx, clauses.reductionDeclSymbols)); +} + LogicalResult TeamsOp::verify() { // Check parent region // TODO If nested inside of a target region, also check that it does not @@ -1312,9 +1407,19 @@ LogicalResult TeamsOp::verify() { } //===----------------------------------------------------------------------===// -// Verifier for SectionsOp +// SectionsOp //===----------------------------------------------------------------------===// +void SectionsOp::build(OpBuilder &builder, OperationState &state, + const SectionsClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: reductionByRefAttr, privateVars, privatizers. + SectionsOp::build(builder, state, clauses.reductionVars, + makeArrayAttr(ctx, clauses.reductionDeclSymbols), + clauses.allocateVars, clauses.allocatorVars, + clauses.nowaitAttr); +} + LogicalResult SectionsOp::verify() { if (getAllocateVars().size() != getAllocatorsVars().size()) return emitError( @@ -1334,6 +1439,20 @@ LogicalResult SectionsOp::verifyRegions() { return success(); } +//===----------------------------------------------------------------------===// +// SingleOp +//===----------------------------------------------------------------------===// + +void SingleOp::build(OpBuilder &builder, OperationState &state, + const SingleClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: privateVars, privatizers. + SingleOp::build(builder, state, clauses.allocateVars, clauses.allocatorVars, + clauses.copyprivateVars, + makeArrayAttr(ctx, clauses.copyprivateFuncs), + clauses.nowaitAttr); +} + LogicalResult SingleOp::verify() { // Check for allocate clause restrictions if (getAllocateVars().size() != getAllocatorsVars().size()) @@ -1481,9 +1600,21 @@ void printLoopControl(OpAsmPrinter &p, Operation *op, Region ®ion, } //===----------------------------------------------------------------------===// -// Verifier for Simd construct [2.9.3.1] +// Simd construct [2.9.3.1] //===----------------------------------------------------------------------===// +void SimdLoopOp::build(OpBuilder &builder, OperationState &state, + const SimdLoopClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: privateVars, reductionByRefAttr, reductionVars, + // privatizers, reductionDeclSymbols. + SimdLoopOp::build( + builder, state, clauses.loopLBVar, clauses.loopUBVar, clauses.loopStepVar, + clauses.alignedVars, makeArrayAttr(ctx, clauses.alignmentAttrs), + clauses.ifVar, clauses.nontemporalVars, clauses.orderAttr, + clauses.simdlenAttr, clauses.safelenAttr, clauses.loopInclusiveAttr); +} + LogicalResult SimdLoopOp::verify() { if (this->getLowerBound().empty()) { return emitOpError() << "empty lowerbound for simd loop operation"; @@ -1504,9 +1635,17 @@ LogicalResult SimdLoopOp::verify() { } //===----------------------------------------------------------------------===// -// Verifier for Distribute construct [2.9.4.1] +// Distribute construct [2.9.4.1] //===----------------------------------------------------------------------===// +void DistributeOp::build(OpBuilder &builder, OperationState &state, + const DistributeClauseOps &clauses) { + // TODO Store clauses in op: privateVars, privatizers. + DistributeOp::build(builder, state, clauses.distScheduleStaticAttr, + clauses.distScheduleChunkSizeVar, clauses.allocateVars, + clauses.allocatorVars, clauses.orderAttr); +} + LogicalResult DistributeOp::verify() { if (this->getChunkSize() && !this->getDistScheduleStatic()) return emitOpError() << "chunk size set without " @@ -1630,6 +1769,19 @@ LogicalResult ReductionOp::verify() { //===----------------------------------------------------------------------===// // TaskOp //===----------------------------------------------------------------------===// + +void TaskOp::build(OpBuilder &builder, OperationState &state, + const TaskClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: privateVars, privatizers. + TaskOp::build( + builder, state, clauses.ifVar, clauses.finalVar, clauses.untiedAttr, + clauses.mergeableAttr, clauses.inReductionVars, + makeArrayAttr(ctx, clauses.inReductionDeclSymbols), clauses.priorityVar, + makeArrayAttr(ctx, clauses.dependTypeAttrs), clauses.dependVars, + clauses.allocateVars, clauses.allocatorVars); +} + LogicalResult TaskOp::verify() { LogicalResult verifyDependVars = verifyDependVarList(*this, getDepends(), getDependVars()); @@ -1642,6 +1794,15 @@ LogicalResult TaskOp::verify() { //===----------------------------------------------------------------------===// // TaskgroupOp //===----------------------------------------------------------------------===// + +void TaskgroupOp::build(OpBuilder &builder, OperationState &state, + const TaskgroupClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + TaskgroupOp::build(builder, state, clauses.taskReductionVars, + makeArrayAttr(ctx, clauses.taskReductionDeclSymbols), + clauses.allocateVars, clauses.allocatorVars); +} + LogicalResult TaskgroupOp::verify() { return verifyReductionVarList(*this, getTaskReductions(), getTaskReductionVars()); @@ -1650,6 +1811,21 @@ LogicalResult TaskgroupOp::verify() { //===----------------------------------------------------------------------===// // TaskloopOp //===----------------------------------------------------------------------===// + +void TaskloopOp::build(OpBuilder &builder, OperationState &state, + const TaskloopClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: reductionByRefAttr, privateVars, privatizers. + TaskloopOp::build( + builder, state, clauses.loopLBVar, clauses.loopUBVar, clauses.loopStepVar, + clauses.loopInclusiveAttr, clauses.ifVar, clauses.finalVar, + clauses.untiedAttr, clauses.mergeableAttr, clauses.inReductionVars, + makeArrayAttr(ctx, clauses.inReductionDeclSymbols), clauses.reductionVars, + makeArrayAttr(ctx, clauses.reductionDeclSymbols), clauses.priorityVar, + clauses.allocateVars, clauses.allocatorVars, clauses.grainsizeVar, + clauses.numTasksVar, clauses.nogroupAttr); +} + SmallVector TaskloopOp::getAllReductionVars() { SmallVector allReductionNvars(getInReductionVars().begin(), getInReductionVars().end()); @@ -1703,14 +1879,33 @@ void WsloopOp::build(OpBuilder &builder, OperationState &state, state.addAttributes(attributes); } +void WsloopOp::build(OpBuilder &builder, OperationState &state, + const WsloopClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO Store clauses in op: allocateVars, allocatorVars, privateVars, + // privatizers. + WsloopOp::build( + builder, state, clauses.loopLBVar, clauses.loopUBVar, clauses.loopStepVar, + clauses.linearVars, clauses.linearStepVars, clauses.reductionVars, + makeArrayAttr(ctx, clauses.reductionDeclSymbols), clauses.scheduleValAttr, + clauses.scheduleChunkVar, clauses.scheduleModAttr, + clauses.scheduleSimdAttr, clauses.nowaitAttr, clauses.reductionByRefAttr, + clauses.orderedAttr, clauses.orderAttr, clauses.loopInclusiveAttr); +} + LogicalResult WsloopOp::verify() { return verifyReductionVarList(*this, getReductions(), getReductionVars()); } //===----------------------------------------------------------------------===// -// Verifier for critical construct (2.17.1) +// Critical construct (2.17.1) //===----------------------------------------------------------------------===// +void CriticalDeclareOp::build(OpBuilder &builder, OperationState &state, + const CriticalClauseOps &clauses) { + CriticalDeclareOp::build(builder, state, clauses.nameAttr, clauses.hintAttr); +} + LogicalResult CriticalDeclareOp::verify() { return verifySynchronizationHint(*this, getHintVal()); } @@ -1730,9 +1925,15 @@ LogicalResult CriticalOp::verifySymbolUses(SymbolTableCollection &symbolTable) { } //===----------------------------------------------------------------------===// -// Verifier for ordered construct +// Ordered construct //===----------------------------------------------------------------------===// +void OrderedOp::build(OpBuilder &builder, OperationState &state, + const OrderedOpClauseOps &clauses) { + OrderedOp::build(builder, state, clauses.doacrossDependTypeAttr, + clauses.doacrossNumLoopsAttr, clauses.doacrossVectorVars); +} + LogicalResult OrderedOp::verify() { auto container = (*this)->getParentOfType(); if (!container || !container.getOrderedValAttr() || @@ -1749,6 +1950,11 @@ LogicalResult OrderedOp::verify() { return success(); } +void OrderedRegionOp::build(OpBuilder &builder, OperationState &state, + const OrderedRegionClauseOps &clauses) { + OrderedRegionOp::build(builder, state, clauses.parLevelSimdAttr); +} + LogicalResult OrderedRegionOp::verify() { // TODO: The code generation for ordered simd directive is not supported yet. if (getSimd()) @@ -1765,6 +1971,16 @@ LogicalResult OrderedRegionOp::verify() { return success(); } +//===----------------------------------------------------------------------===// +// TaskwaitOp +//===----------------------------------------------------------------------===// + +void TaskwaitOp::build(OpBuilder &builder, OperationState &state, + const TaskwaitClauseOps &clauses) { + // TODO Store clauses in op: dependTypeAttrs, dependVars, nowaitAttr. + TaskwaitOp::build(builder, state); +} + //===----------------------------------------------------------------------===// // Verifier for AtomicReadOp //===----------------------------------------------------------------------===// -- GitLab From a4cf479cdf08093b69177dd9adf32eebf3632dc3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 13:43:52 +0100 Subject: [PATCH 273/695] [X86] shuffle-vs-trunc-128.ll - add BWVL-ONLY/VBMI/VBMI-FAST/VBMI-SLOW check prefixes to recover missing test checks It is VERY annoying that update_llc_test_checks.py silently fails instead of correctly warning when this happens :( --- llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll | 157 +++++++++++++++++- 1 file changed, 153 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll index 3f2220f1a4c4..e7a1fdbd2910 100644 --- a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll +++ b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll @@ -10,10 +10,10 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512VL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BW -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi,+avx512vl,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi,+avx512vl,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL,AVX512BWVL-ONLY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL,AVX512BWVL-ONLY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi,+avx512vl,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL,AVX512VBMI,AVX512VBMI-FAST +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi,+avx512vl,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512BWVL,AVX512VBMI,AVX512VBMI-SLOW ; PR31551 ; Pairs of shufflevector:trunc functions with functional equivalence. @@ -870,6 +870,29 @@ define <16 x i8> @oddelts_v32i16_shuffle_v16i16_to_v16i8(<32 x i16> %n2) nounwin ; AVX512BW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq +; +; AVX512BWVL-ONLY-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX512BWVL-ONLY: # %bb.0: +; AVX512BWVL-ONLY-NEXT: vextracti64x4 $1, %zmm0, %ymm1 +; AVX512BWVL-ONLY-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX512BWVL-ONLY-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX512BWVL-ONLY-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX512BWVL-ONLY-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX512BWVL-ONLY-NEXT: vpsrld $16, %ymm0, %ymm0 +; AVX512BWVL-ONLY-NEXT: vpmovdb %ymm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX512BWVL-ONLY-NEXT: vzeroupper +; AVX512BWVL-ONLY-NEXT: retq +; +; AVX512VBMI-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX512VBMI: # %bb.0: +; AVX512VBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [2,6,10,14,18,22,26,30,34,38,42,46,50,54,58,62] +; AVX512VBMI-NEXT: vextracti64x4 $1, %zmm0, %ymm2 +; AVX512VBMI-NEXT: vpermt2b %ymm2, %ymm1, %ymm0 +; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 +; AVX512VBMI-NEXT: vzeroupper +; AVX512VBMI-NEXT: retq %n0 = bitcast <32 x i16> %n2 to <64 x i8> %p = shufflevector <64 x i8> %n0, <64 x i8> poison, <16 x i32> ret <16 x i8> %p @@ -1182,6 +1205,71 @@ define <16 x i8> @evenelts_v32i16_trunc_v16i16_to_v16i8(<32 x i16> %n2) nounwind ; AVX512BW-NEXT: popq %rbp ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq +; +; AVX512BWVL-ONLY-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512BWVL-ONLY: # %bb.0: +; AVX512BWVL-ONLY-NEXT: pushq %rbp +; AVX512BWVL-ONLY-NEXT: pushq %r14 +; AVX512BWVL-ONLY-NEXT: pushq %rbx +; AVX512BWVL-ONLY-NEXT: vextracti32x4 $3, %zmm0, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpextrw $6, %xmm1, %eax +; AVX512BWVL-ONLY-NEXT: vpextrw $4, %xmm1, %ecx +; AVX512BWVL-ONLY-NEXT: vpextrw $2, %xmm1, %edx +; AVX512BWVL-ONLY-NEXT: vmovd %xmm1, %esi +; AVX512BWVL-ONLY-NEXT: vextracti32x4 $2, %zmm0, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpextrw $6, %xmm1, %edi +; AVX512BWVL-ONLY-NEXT: vpextrw $4, %xmm1, %r8d +; AVX512BWVL-ONLY-NEXT: vpextrw $2, %xmm1, %r9d +; AVX512BWVL-ONLY-NEXT: vmovd %xmm1, %r10d +; AVX512BWVL-ONLY-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpextrw $6, %xmm1, %r11d +; AVX512BWVL-ONLY-NEXT: vpextrw $4, %xmm1, %ebx +; AVX512BWVL-ONLY-NEXT: vpextrw $2, %xmm1, %ebp +; AVX512BWVL-ONLY-NEXT: vmovd %xmm1, %r14d +; AVX512BWVL-ONLY-NEXT: vpmovdb %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: popq %rbx +; AVX512BWVL-ONLY-NEXT: popq %r14 +; AVX512BWVL-ONLY-NEXT: popq %rbp +; AVX512BWVL-ONLY-NEXT: vzeroupper +; AVX512BWVL-ONLY-NEXT: retq +; +; AVX512VBMI-FAST-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512VBMI-FAST: # %bb.0: +; AVX512VBMI-FAST-NEXT: vmovdqa {{.*#+}} xmm1 = [0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,79] +; AVX512VBMI-FAST-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512VBMI-FAST-NEXT: vpermi2b %zmm2, %zmm0, %zmm1 +; AVX512VBMI-FAST-NEXT: vextracti32x4 $3, %zmm0, %xmm0 +; AVX512VBMI-FAST-NEXT: vpextrw $6, %xmm0, %eax +; AVX512VBMI-FAST-NEXT: vpinsrb $15, %eax, %xmm1, %xmm0 +; AVX512VBMI-FAST-NEXT: vzeroupper +; AVX512VBMI-FAST-NEXT: retq +; +; AVX512VBMI-SLOW-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512VBMI-SLOW: # %bb.0: +; AVX512VBMI-SLOW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,4,8,12,16,20,24,28,32,36,40,44,48,77,78,79] +; AVX512VBMI-SLOW-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512VBMI-SLOW-NEXT: vpermi2b %zmm2, %zmm0, %zmm1 +; AVX512VBMI-SLOW-NEXT: vextracti32x4 $3, %zmm0, %xmm0 +; AVX512VBMI-SLOW-NEXT: vpextrw $6, %xmm0, %eax +; AVX512VBMI-SLOW-NEXT: vpextrw $4, %xmm0, %ecx +; AVX512VBMI-SLOW-NEXT: vpextrw $2, %xmm0, %edx +; AVX512VBMI-SLOW-NEXT: vpinsrb $13, %edx, %xmm1, %xmm0 +; AVX512VBMI-SLOW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512VBMI-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512VBMI-SLOW-NEXT: vzeroupper +; AVX512VBMI-SLOW-NEXT: retq %n0 = shufflevector <32 x i16> %n2, <32 x i16> poison, <16 x i32> %n1 = trunc <16 x i16> %n0 to <16 x i8> ret <16 x i8> %n1 @@ -1504,6 +1592,67 @@ define <16 x i8> @oddelts_v32i16_trunc_v16i16_to_v16i8(<32 x i16> %n2) nounwind ; AVX512BW-NEXT: popq %rbp ; AVX512BW-NEXT: vzeroupper ; AVX512BW-NEXT: retq +; +; AVX512BWVL-ONLY-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512BWVL-ONLY: # %bb.0: +; AVX512BWVL-ONLY-NEXT: pushq %rbp +; AVX512BWVL-ONLY-NEXT: pushq %r14 +; AVX512BWVL-ONLY-NEXT: pushq %rbx +; AVX512BWVL-ONLY-NEXT: vextracti32x4 $3, %zmm0, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpextrw $7, %xmm1, %eax +; AVX512BWVL-ONLY-NEXT: vpextrw $5, %xmm1, %ecx +; AVX512BWVL-ONLY-NEXT: vpextrw $3, %xmm1, %edx +; AVX512BWVL-ONLY-NEXT: vpextrw $1, %xmm1, %esi +; AVX512BWVL-ONLY-NEXT: vextracti32x4 $2, %zmm0, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpextrw $7, %xmm1, %edi +; AVX512BWVL-ONLY-NEXT: vpextrw $5, %xmm1, %r8d +; AVX512BWVL-ONLY-NEXT: vpextrw $3, %xmm1, %r9d +; AVX512BWVL-ONLY-NEXT: vpextrw $1, %xmm1, %r10d +; AVX512BWVL-ONLY-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX512BWVL-ONLY-NEXT: vpextrw $7, %xmm1, %r11d +; AVX512BWVL-ONLY-NEXT: vpextrw $5, %xmm1, %ebx +; AVX512BWVL-ONLY-NEXT: vpextrw $3, %xmm1, %ebp +; AVX512BWVL-ONLY-NEXT: vpextrw $1, %xmm1, %r14d +; AVX512BWVL-ONLY-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX512BWVL-ONLY-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512BWVL-ONLY-NEXT: popq %rbx +; AVX512BWVL-ONLY-NEXT: popq %r14 +; AVX512BWVL-ONLY-NEXT: popq %rbp +; AVX512BWVL-ONLY-NEXT: vzeroupper +; AVX512BWVL-ONLY-NEXT: retq +; +; AVX512VBMI-FAST-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512VBMI-FAST: # %bb.0: +; AVX512VBMI-FAST-NEXT: vmovdqa {{.*#+}} xmm1 = [2,6,10,14,18,22,26,30,34,38,42,46,50,54,58,62] +; AVX512VBMI-FAST-NEXT: vpermb %zmm0, %zmm1, %zmm0 +; AVX512VBMI-FAST-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 +; AVX512VBMI-FAST-NEXT: vzeroupper +; AVX512VBMI-FAST-NEXT: retq +; +; AVX512VBMI-SLOW-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX512VBMI-SLOW: # %bb.0: +; AVX512VBMI-SLOW-NEXT: vmovdqa {{.*#+}} xmm1 = [2,6,10,14,18,22,26,30,34,38,42,46,50,u,u,u] +; AVX512VBMI-SLOW-NEXT: vpermb %zmm0, %zmm1, %zmm1 +; AVX512VBMI-SLOW-NEXT: vextracti32x4 $3, %zmm0, %xmm0 +; AVX512VBMI-SLOW-NEXT: vpextrw $7, %xmm0, %eax +; AVX512VBMI-SLOW-NEXT: vpextrw $5, %xmm0, %ecx +; AVX512VBMI-SLOW-NEXT: vpextrw $3, %xmm0, %edx +; AVX512VBMI-SLOW-NEXT: vpinsrb $13, %edx, %xmm1, %xmm0 +; AVX512VBMI-SLOW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX512VBMI-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX512VBMI-SLOW-NEXT: vzeroupper +; AVX512VBMI-SLOW-NEXT: retq %n0 = shufflevector <32 x i16> %n2, <32 x i16> poison, <16 x i32> %n1 = trunc <16 x i16> %n0 to <16 x i8> ret <16 x i8> %n1 -- GitLab From 38824f285f1459cb890337d2df1a3cafd3fd109d Mon Sep 17 00:00:00 2001 From: Sirraide Date: Tue, 9 Apr 2024 14:52:52 +0200 Subject: [PATCH 274/695] [Clang] [Sema] Fix dependence of DREs in lambdas with an explicit object parameter (#84473) This fixes some problems wrt dependence of captures in lambdas with an explicit object parameter. [temp.dep.expr] states that > An id-expression is type-dependent if [...] its terminal name is > - associated by name lookup with an entity captured by copy > ([expr.prim.lambda.capture]) in a lambda-expression that has > an explicit object parameter whose type is dependent [dcl.fct]. There were several issues with our implementation of this: 1. we were treating by-reference captures as dependent rather than by-value captures; 2. tree transform wasn't checking whether referring to such a by-value capture should make a DRE dependent; 3. when checking whether a DRE refers to such a by-value capture, we were only looking at the immediately enclosing lambda, and not at any parent lambdas; 4. we also forgot to check for implicit by-value captures; 5. lastly, we were attempting to determine whether a lambda has an explicit object parameter by checking the `LambdaScopeInfo`'s `ExplicitObjectParameter`, but it seems that that simply wasn't set (yet) by the time we got to the check. All of these should be fixed now. This fixes #70604, #79754, #84163, #84425, #86054, #86398, and #86399. --- clang/docs/ReleaseNotes.rst | 3 + clang/include/clang/AST/ExprCXX.h | 10 + clang/include/clang/AST/Stmt.h | 5 + clang/lib/AST/ComputeDependence.cpp | 10 + clang/lib/AST/StmtProfile.cpp | 1 + clang/lib/AST/TextNodeDumper.cpp | 7 +- clang/lib/Sema/SemaExpr.cpp | 44 +++-- clang/lib/Sema/SemaExprCXX.cpp | 36 ++++ clang/lib/Sema/TreeTransform.h | 18 +- clang/lib/Serialization/ASTReaderStmt.cpp | 1 + clang/lib/Serialization/ASTWriterStmt.cpp | 1 + clang/test/CodeGenCXX/cxx2b-deducing-this.cpp | 73 ++++++++ clang/test/PCH/cxx23-deducing-this-lambda.cpp | 35 ++++ clang/test/SemaCXX/cxx2b-deducing-this.cpp | 176 ++++++++++++++++++ 14 files changed, 403 insertions(+), 17 deletions(-) create mode 100644 clang/test/PCH/cxx23-deducing-this-lambda.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 30cedbe774be..5708e691d084 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -513,6 +513,9 @@ Bug Fixes to C++ Support - Fix crash when inheriting from a cv-qualified type. Fixes: (`#35603 `_) - Fix a crash when the using enum declaration uses an anonymous enumeration. Fixes (#GH86790). +- Clang now correctly tracks type dependence of by-value captures in lambdas with an explicit + object parameter. + Fixes (#GH70604), (#GH79754), (#GH84163), (#GH84425), (#GH86054), (#GH86398), and (#GH86399). Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h index 6003b866c9f5..7eb99a75e1fc 100644 --- a/clang/include/clang/AST/ExprCXX.h +++ b/clang/include/clang/AST/ExprCXX.h @@ -1149,6 +1149,7 @@ class CXXThisExpr : public Expr { CXXThisExpr(SourceLocation L, QualType Ty, bool IsImplicit, ExprValueKind VK) : Expr(CXXThisExprClass, Ty, VK, OK_Ordinary) { CXXThisExprBits.IsImplicit = IsImplicit; + CXXThisExprBits.CapturedByCopyInLambdaWithExplicitObjectParameter = false; CXXThisExprBits.Loc = L; setDependence(computeDependence(this)); } @@ -1170,6 +1171,15 @@ public: bool isImplicit() const { return CXXThisExprBits.IsImplicit; } void setImplicit(bool I) { CXXThisExprBits.IsImplicit = I; } + bool isCapturedByCopyInLambdaWithExplicitObjectParameter() const { + return CXXThisExprBits.CapturedByCopyInLambdaWithExplicitObjectParameter; + } + + void setCapturedByCopyInLambdaWithExplicitObjectParameter(bool Set) { + CXXThisExprBits.CapturedByCopyInLambdaWithExplicitObjectParameter = Set; + setDependence(computeDependence(this)); + } + static bool classof(const Stmt *T) { return T->getStmtClass() == CXXThisExprClass; } diff --git a/clang/include/clang/AST/Stmt.h b/clang/include/clang/AST/Stmt.h index 8892518d58e8..1b9c92310477 100644 --- a/clang/include/clang/AST/Stmt.h +++ b/clang/include/clang/AST/Stmt.h @@ -784,6 +784,11 @@ protected: LLVM_PREFERRED_TYPE(bool) unsigned IsImplicit : 1; + /// Whether there is a lambda with an explicit object parameter that + /// captures this "this" by copy. + LLVM_PREFERRED_TYPE(bool) + unsigned CapturedByCopyInLambdaWithExplicitObjectParameter : 1; + /// The location of the "this". SourceLocation Loc; }; diff --git a/clang/lib/AST/ComputeDependence.cpp b/clang/lib/AST/ComputeDependence.cpp index 86b77b49a0fb..5ec3013fabba 100644 --- a/clang/lib/AST/ComputeDependence.cpp +++ b/clang/lib/AST/ComputeDependence.cpp @@ -310,6 +310,16 @@ ExprDependence clang::computeDependence(CXXThisExpr *E) { // 'this' is type-dependent if the class type of the enclosing // member function is dependent (C++ [temp.dep.expr]p2) auto D = toExprDependenceForImpliedType(E->getType()->getDependence()); + + // If a lambda with an explicit object parameter captures '*this', then + // 'this' now refers to the captured copy of lambda, and if the lambda + // is type-dependent, so is the object and thus 'this'. + // + // Note: The standard does not mention this case explicitly, but we need + // to do this so we can mark NSDM accesses as dependent. + if (E->isCapturedByCopyInLambdaWithExplicitObjectParameter()) + D |= ExprDependence::Type; + assert(!(D & ExprDependence::UnexpandedPack)); return D; } diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index d68547f444c5..bec8bc71f555 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -2011,6 +2011,7 @@ void StmtProfiler::VisitMSPropertySubscriptExpr( void StmtProfiler::VisitCXXThisExpr(const CXXThisExpr *S) { VisitExpr(S); ID.AddBoolean(S->isImplicit()); + ID.AddBoolean(S->isCapturedByCopyInLambdaWithExplicitObjectParameter()); } void StmtProfiler::VisitCXXThrowExpr(const CXXThrowExpr *S) { diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index f498de637434..431f5d8bdb2b 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -1194,8 +1194,11 @@ void TextNodeDumper::VisitDeclRefExpr(const DeclRefExpr *Node) { case NOUR_Constant: OS << " non_odr_use_constant"; break; case NOUR_Discarded: OS << " non_odr_use_discarded"; break; } - if (Node->refersToEnclosingVariableOrCapture()) + if (Node->isCapturedByCopyInLambdaWithExplicitObjectParameter()) + OS << " dependent_capture"; + else if (Node->refersToEnclosingVariableOrCapture()) OS << " refers_to_enclosing_variable_or_capture"; + if (Node->isImmediateEscalating()) OS << " immediate-escalating"; } @@ -1351,6 +1354,8 @@ void TextNodeDumper::VisitCXXBoolLiteralExpr(const CXXBoolLiteralExpr *Node) { void TextNodeDumper::VisitCXXThisExpr(const CXXThisExpr *Node) { if (Node->isImplicit()) OS << " implicit"; + if (Node->isCapturedByCopyInLambdaWithExplicitObjectParameter()) + OS << " dependent_capture"; OS << " this"; } diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 7b91bbe0b205..bd221763b319 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -20720,20 +20720,42 @@ void Sema::MarkVariableReferenced(SourceLocation Loc, VarDecl *Var) { static void FixDependencyOfIdExpressionsInLambdaWithDependentObjectParameter( Sema &SemaRef, ValueDecl *D, Expr *E) { auto *ID = dyn_cast(E); - if (!ID || ID->isTypeDependent()) + if (!ID || ID->isTypeDependent() || !ID->refersToEnclosingVariableOrCapture()) return; + // If any enclosing lambda with a dependent explicit object parameter either + // explicitly captures the variable by value, or has a capture default of '=' + // and does not capture the variable by reference, then the type of the DRE + // is dependent on the type of that lambda's explicit object parameter. auto IsDependent = [&]() { - const LambdaScopeInfo *LSI = SemaRef.getCurLambda(); - if (!LSI) - return false; - if (!LSI->ExplicitObjectParameter || - !LSI->ExplicitObjectParameter->getType()->isDependentType()) - return false; - if (!LSI->CaptureMap.count(D)) - return false; - const Capture &Cap = LSI->getCapture(D); - return !Cap.isCopyCapture(); + for (auto *Scope : llvm::reverse(SemaRef.FunctionScopes)) { + auto *LSI = dyn_cast(Scope); + if (!LSI) + continue; + + if (LSI->Lambda && !LSI->Lambda->Encloses(SemaRef.CurContext) && + LSI->AfterParameterList) + return false; + + const auto *MD = LSI->CallOperator; + if (MD->getType().isNull()) + continue; + + const auto *Ty = cast(MD->getType()); + if (!Ty || !MD->isExplicitObjectMemberFunction() || + !Ty->getParamType(0)->isDependentType()) + continue; + + if (auto *C = LSI->CaptureMap.count(D) ? &LSI->getCapture(D) : nullptr) { + if (C->isCopyCapture()) + return true; + continue; + } + + if (LSI->ImpCaptureStyle == LambdaScopeInfo::ImpCap_LambdaByval) + return true; + } + return false; }(); ID->setCapturedByCopyInLambdaWithExplicitObjectParameter( diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 9ba414324019..80c01b14379c 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -1462,6 +1462,42 @@ Expr *Sema::BuildCXXThisExpr(SourceLocation Loc, QualType Type, void Sema::MarkThisReferenced(CXXThisExpr *This) { CheckCXXThisCapture(This->getExprLoc()); + if (This->isTypeDependent()) + return; + + // Check if 'this' is captured by value in a lambda with a dependent explicit + // object parameter, and mark it as type-dependent as well if so. + auto IsDependent = [&]() { + for (auto *Scope : llvm::reverse(FunctionScopes)) { + auto *LSI = dyn_cast(Scope); + if (!LSI) + continue; + + if (LSI->Lambda && !LSI->Lambda->Encloses(CurContext) && + LSI->AfterParameterList) + return false; + + // If this lambda captures 'this' by value, then 'this' is dependent iff + // this lambda has a dependent explicit object parameter. If we can't + // determine whether it does (e.g. because the CXXMethodDecl's type is + // null), assume it doesn't. + if (LSI->isCXXThisCaptured()) { + if (!LSI->getCXXThisCapture().isCopyCapture()) + continue; + + const auto *MD = LSI->CallOperator; + if (MD->getType().isNull()) + return false; + + const auto *Ty = cast(MD->getType()); + return Ty && MD->isExplicitObjectMemberFunction() && + Ty->getParamType(0)->isDependentType(); + } + } + return false; + }(); + + This->setCapturedByCopyInLambdaWithExplicitObjectParameter(IsDependent); } bool Sema::isThisOutsideMemberFunctionBody(QualType BaseType) { diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 6ebca07eaa4f..13d7b00430d5 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -11178,8 +11178,8 @@ TreeTransform::TransformDeclRefExpr(DeclRefExpr *E) { } if (!getDerived().AlwaysRebuild() && - QualifierLoc == E->getQualifierLoc() && - ND == E->getDecl() && + !E->isCapturedByCopyInLambdaWithExplicitObjectParameter() && + QualifierLoc == E->getQualifierLoc() && ND == E->getDecl() && Found == E->getFoundDecl() && NameInfo.getName() == E->getDecl()->getDeclName() && !E->hasExplicitTemplateArgs()) { @@ -12642,9 +12642,17 @@ TreeTransform::TransformCXXThisExpr(CXXThisExpr *E) { // // In other contexts, the type of `this` may be overrided // for type deduction, so we need to recompute it. - QualType T = getSema().getCurLambda() ? - getDerived().TransformType(E->getType()) - : getSema().getCurrentThisType(); + // + // Always recompute the type if we're in the body of a lambda, and + // 'this' is dependent on a lambda's explicit object parameter. + QualType T = [&]() { + auto &S = getSema(); + if (E->isCapturedByCopyInLambdaWithExplicitObjectParameter()) + return S.getCurrentThisType(); + if (S.getCurLambda()) + return getDerived().TransformType(E->getType()); + return S.getCurrentThisType(); + }(); if (!getDerived().AlwaysRebuild() && T == E->getType()) { // Mark it referenced in the new context regardless. diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp index f0984c3e4696..3ddb15b10f48 100644 --- a/clang/lib/Serialization/ASTReaderStmt.cpp +++ b/clang/lib/Serialization/ASTReaderStmt.cpp @@ -1841,6 +1841,7 @@ void ASTStmtReader::VisitCXXThisExpr(CXXThisExpr *E) { VisitExpr(E); E->setLocation(readSourceLocation()); E->setImplicit(Record.readInt()); + E->setCapturedByCopyInLambdaWithExplicitObjectParameter(Record.readInt()); } void ASTStmtReader::VisitCXXThrowExpr(CXXThrowExpr *E) { diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp index 0651614e2ce5..ddee5db2b69e 100644 --- a/clang/lib/Serialization/ASTWriterStmt.cpp +++ b/clang/lib/Serialization/ASTWriterStmt.cpp @@ -1839,6 +1839,7 @@ void ASTStmtWriter::VisitCXXThisExpr(CXXThisExpr *E) { VisitExpr(E); Record.AddSourceLocation(E->getLocation()); Record.push_back(E->isImplicit()); + Record.push_back(E->isCapturedByCopyInLambdaWithExplicitObjectParameter()); Code = serialization::EXPR_CXX_THIS; } diff --git a/clang/test/CodeGenCXX/cxx2b-deducing-this.cpp b/clang/test/CodeGenCXX/cxx2b-deducing-this.cpp index de8c124c050e..b755e80db35a 100644 --- a/clang/test/CodeGenCXX/cxx2b-deducing-this.cpp +++ b/clang/test/CodeGenCXX/cxx2b-deducing-this.cpp @@ -109,3 +109,76 @@ void test_temporary() { //CHECK: %ref.tmp = alloca %struct.MaterializedTemporary, align 1 //CHECK: call void @_ZN21MaterializedTemporaryC1Ev(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp){{.*}} //CHECK invoke void @_ZNH21MaterializedTemporary3fooEOS_(ptr noundef nonnull align 1 dereferenceable(1) %ref.tmp){{.*}} + +namespace GH86399 { +volatile int a = 0; +struct function { + function& operator=(function const&) { + a = 1; + return *this; + } +}; + +void f() { + function list; + + //CHECK-LABEL: define internal void @"_ZZN7GH863991f{{.*}}"(ptr %{{.*}}) + //CHECK: call {{.*}} @_ZN7GH863998functionaSERKS0_ + //CHECK-NEXT: ret void + [&list](this auto self) { + list = function{}; + }(); +} +} + +namespace GH84163 { +// Just check that this doesn't crash (we were previously not instantiating +// everything that needs instantiating in here). +template struct S {}; + +void a() { + int x; + const auto l = [&x](this auto&) { S q; }; + l(); +} +} + +namespace GH84425 { +// As above. +void do_thing(int x) { + auto second = [&](this auto const& self, int b) -> int { + if (x) return x; + else return self(x); + }; + + second(1); +} + +void do_thing2(int x) { + auto second = [&](this auto const& self) { + if (true) return x; + else return x; + }; + + second(); +} +} + +namespace GH79754 { +// As above. +void f() { + int x; + [&x](this auto&&) {return x;}(); +} +} + +namespace GH70604 { +auto dothing(int num) +{ + auto fun = [&num](this auto&& self) -> void { + auto copy = num; + }; + + fun(); +} +} diff --git a/clang/test/PCH/cxx23-deducing-this-lambda.cpp b/clang/test/PCH/cxx23-deducing-this-lambda.cpp new file mode 100644 index 000000000000..21b4bf0d633f --- /dev/null +++ b/clang/test/PCH/cxx23-deducing-this-lambda.cpp @@ -0,0 +1,35 @@ +// RUN: %clang_cc1 -emit-pch -std=c++23 -o %t %s +// RUN: %clang_cc1 -include-pch %t -verify -fsyntax-only -DTEST -std=c++23 %s + +// Test that dependence of 'this' and DREs due to by-value capture by a +// lambda with an explicit object parameter is serialised/deserialised +// properly. + +#ifndef HEADER +#define HEADER +struct S { + int x; + auto f() { + return [*this] (this auto&&) { + int y; + x = 42; + + const auto l = [y] (this auto&&) { y = 42; }; + l(); + }; + } +}; +#endif + +// expected-error@* {{read-only variable is not assignable}} +// expected-error@* {{cannot assign to a variable captured by copy in a non-mutable lambda}} +// expected-note@* 2 {{in instantiation of}} + +#ifdef TEST +void f() { + const auto l = S{}.f(); + l(); // expected-note {{in instantiation of}} +} +#endif + + diff --git a/clang/test/SemaCXX/cxx2b-deducing-this.cpp b/clang/test/SemaCXX/cxx2b-deducing-this.cpp index b8ddb9ad3000..c14c971afd23 100644 --- a/clang/test/SemaCXX/cxx2b-deducing-this.cpp +++ b/clang/test/SemaCXX/cxx2b-deducing-this.cpp @@ -200,6 +200,118 @@ void TestMutationInLambda() { [i = 0](this auto){ i++; }(); [i = 0](this const auto&){ i++; }(); // expected-error@-1 {{cannot assign to a variable captured by copy in a non-mutable lambda}} + // expected-note@-2 {{in instantiation of}} + + int x; + const auto l1 = [x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + const auto l2 = [=](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + + const auto l3 = [&x](this auto&) { + const auto l3a = [x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l3a(); // expected-note {{in instantiation of}} + }; + + const auto l4 = [&x](this auto&) { + const auto l4a = [=](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l4a(); // expected-note {{in instantiation of}} + }; + + const auto l5 = [x](this auto&) { + const auto l5a = [x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l5a(); // expected-note {{in instantiation of}} + }; + + const auto l6 = [=](this auto&) { + const auto l6a = [=](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l6a(); // expected-note {{in instantiation of}} + }; + + const auto l7 = [x](this auto&) { + const auto l7a = [=](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l7a(); // expected-note {{in instantiation of}} + }; + + const auto l8 = [=](this auto&) { + const auto l8a = [x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l8a(); // expected-note {{in instantiation of}} + }; + + const auto l9 = [&](this auto&) { + const auto l9a = [x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l9a(); // expected-note {{in instantiation of}} + }; + + const auto l10 = [&](this auto&) { + const auto l10a = [=](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + l10a(); // expected-note {{in instantiation of}} + }; + + const auto l11 = [x](this auto&) { + const auto l11a = [&x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} expected-note {{while substituting}} + l11a(); + }; + + const auto l12 = [x](this auto&) { + const auto l12a = [&](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} expected-note {{while substituting}} + l12a(); + }; + + const auto l13 = [=](this auto&) { + const auto l13a = [&x](this auto&) { x = 42; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} expected-note {{while substituting}} + l13a(); + }; + + struct S { + int x; + auto f() { + return [*this] (this auto&&) { + x = 42; // expected-error {{read-only variable is not assignable}} + [*this] () mutable { x = 42; } (); + [*this] (this auto&&) { x = 42; } (); + [*this] () { x = 42; } (); // expected-error {{read-only variable is not assignable}} + const auto l = [*this] (this auto&&) { x = 42; }; // expected-error {{read-only variable is not assignable}} + l(); // expected-note {{in instantiation of}} + + struct T { + int x; + auto g() { + return [&] (this auto&&) { + x = 42; + const auto l = [*this] (this auto&&) { x = 42; }; // expected-error {{read-only variable is not assignable}} + l(); // expected-note {{in instantiation of}} + }; + } + }; + + const auto l2 = T{}.g(); + l2(); // expected-note {{in instantiation of}} + }; + } + }; + + const auto l14 = S{}.f(); + + l1(); // expected-note {{in instantiation of}} + l2(); // expected-note {{in instantiation of}} + l3(); // expected-note {{in instantiation of}} + l4(); // expected-note {{in instantiation of}} + l5(); // expected-note {{in instantiation of}} + l6(); // expected-note {{in instantiation of}} + l7(); // expected-note {{in instantiation of}} + l8(); // expected-note {{in instantiation of}} + l9(); // expected-note {{in instantiation of}} + l10(); // expected-note {{in instantiation of}} + l11(); // expected-note {{in instantiation of}} + l12(); // expected-note {{in instantiation of}} + l13(); // expected-note {{in instantiation of}} + l14(); // expected-note 3 {{in instantiation of}} + + { + const auto l1 = [&x](this auto&) { x = 42; }; + const auto l2 = [&](this auto&) { x = 42; }; + l1(); + l2(); + } } struct Over_Call_Func_Example { @@ -650,3 +762,67 @@ int bug() { S{}.f(0); } } + +namespace GH84163 { +struct S { + int x; + + auto foo() { + return [*this](this auto&&) { + x = 10; // expected-error {{read-only variable is not assignable}} + }; + } +}; + +int f() { + S s{ 5 }; + const auto l = s.foo(); + l(); // expected-note {{in instantiation of}} + + const auto g = [x = 10](this auto&& self) { x = 20; }; // expected-error {{cannot assign to a variable captured by copy in a non-mutable lambda}} + g(); // expected-note {{in instantiation of}} +} +} + +namespace GH86054 { +template +struct unique_lock { + unique_lock(M&) {} +}; +int f() { + struct mutex {} cursor_guard; + [&cursor_guard](this auto self) { + unique_lock a(cursor_guard); + }(); +} +} + +namespace GH86398 { +struct function {}; // expected-note 2 {{not viable}} +int f() { + function list; + [&list](this auto self) { + list = self; // expected-error {{no viable overloaded '='}} + }(); // expected-note {{in instantiation of}} +} + +struct function2 { + function2& operator=(function2 const&) = delete; // expected-note {{candidate function not viable}} +}; +int g() { + function2 list; + [&list](this auto self) { + list = self; // expected-error {{no viable overloaded '='}} + }(); // expected-note {{in instantiation of}} +} + +struct function3 { + function3& operator=(function3 const&) = delete; // expected-note {{has been explicitly deleted}} +}; +int h() { + function3 list; + [&list](this auto self) { + list = function3{}; // expected-error {{selected deleted operator '='}} + }(); +} +} -- GitLab From 961d91abd375100a498807a5a0da8003a2878284 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 14:11:02 +0100 Subject: [PATCH 275/695] [X86] shuffle-vs-trunc-128.ll - add common AVX2 check prefix --- llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll | 322 ++++++------------ 1 file changed, 107 insertions(+), 215 deletions(-) diff --git a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll index e7a1fdbd2910..aea76f694a0f 100644 --- a/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll +++ b/llvm/test/CodeGen/X86/shuffle-vs-trunc-128.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2-SLOW -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2-FAST -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2-FAST +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-SLOW +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512F ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512VL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX512,AVX512VL @@ -697,37 +697,21 @@ define <16 x i8> @evenelts_v32i16_shuffle_v16i16_to_v16i8(<32 x i16> %n2) nounwi ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; -; AVX2-SLOW-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: -; AVX2-SLOW: # %bb.0: -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-SLOW-NEXT: vpbroadcastd {{.*#+}} xmm3 = [0,4,8,12,0,4,8,12,0,4,8,12,0,4,8,12] -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm1, %xmm1 -; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm2 -; AVX2-SLOW-NEXT: vmovd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; AVX2-SLOW-NEXT: vzeroupper -; AVX2-SLOW-NEXT: retq -; -; AVX2-FAST-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: -; AVX2-FAST: # %bb.0: -; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-FAST-NEXT: vpbroadcastd {{.*#+}} xmm3 = [0,4,8,12,0,4,8,12,0,4,8,12,0,4,8,12] -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 -; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm2 -; AVX2-FAST-NEXT: vmovd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; AVX2-FAST-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; AVX2-FAST-NEXT: vzeroupper -; AVX2-FAST-NEXT: retq +; AVX2-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX2: # %bb.0: +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [0,4,8,12,0,4,8,12,0,4,8,12,0,4,8,12] +; AVX2-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-NEXT: vmovd {{.*#+}} xmm3 = [0,4,8,12,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX2-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq ; ; AVX512-LABEL: evenelts_v32i16_shuffle_v16i16_to_v16i8: ; AVX512: # %bb.0: @@ -797,37 +781,21 @@ define <16 x i8> @oddelts_v32i16_shuffle_v16i16_to_v16i8(<32 x i16> %n2) nounwin ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; -; AVX2-SLOW-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: -; AVX2-SLOW: # %bb.0: -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-SLOW-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm1, %xmm1 -; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm2 -; AVX2-SLOW-NEXT: vmovd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-SLOW-NEXT: vpshufb %xmm3, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; AVX2-SLOW-NEXT: vzeroupper -; AVX2-SLOW-NEXT: retq -; -; AVX2-FAST-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: -; AVX2-FAST: # %bb.0: -; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-FAST-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm1, %xmm1 -; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm2 -; AVX2-FAST-NEXT: vmovd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm2, %xmm2 -; AVX2-FAST-NEXT: vpshufb %xmm3, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; AVX2-FAST-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; AVX2-FAST-NEXT: vzeroupper -; AVX2-FAST-NEXT: retq +; AVX2-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: +; AVX2: # %bb.0: +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2,6,10,14,2,6,10,14,2,6,10,14,2,6,10,14] +; AVX2-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 +; AVX2-NEXT: vmovd {{.*#+}} xmm3 = [2,6,10,14,0,0,0,0,0,0,0,0,0,0,0,0] +; AVX2-NEXT: vpshufb %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq ; ; AVX512F-LABEL: oddelts_v32i16_shuffle_v16i16_to_v16i8: ; AVX512F: # %bb.0: @@ -1021,81 +989,43 @@ define <16 x i8> @evenelts_v32i16_trunc_v16i16_to_v16i8(<32 x i16> %n2) nounwind ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; -; AVX2-SLOW-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: -; AVX2-SLOW: # %bb.0: -; AVX2-SLOW-NEXT: pushq %rbp -; AVX2-SLOW-NEXT: pushq %r14 -; AVX2-SLOW-NEXT: pushq %rbx -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-SLOW-NEXT: vpextrw $6, %xmm2, %eax -; AVX2-SLOW-NEXT: vpextrw $4, %xmm2, %ecx -; AVX2-SLOW-NEXT: vpextrw $2, %xmm2, %edx -; AVX2-SLOW-NEXT: vmovd %xmm2, %esi -; AVX2-SLOW-NEXT: vpextrw $6, %xmm1, %edi -; AVX2-SLOW-NEXT: vpextrw $4, %xmm1, %r8d -; AVX2-SLOW-NEXT: vpextrw $2, %xmm1, %r9d -; AVX2-SLOW-NEXT: vmovd %xmm1, %r10d -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-SLOW-NEXT: vpextrw $6, %xmm1, %r11d -; AVX2-SLOW-NEXT: vpextrw $4, %xmm1, %ebx -; AVX2-SLOW-NEXT: vpextrw $2, %xmm1, %ebp -; AVX2-SLOW-NEXT: vmovd %xmm1, %r14d -; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX2-SLOW-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: popq %rbx -; AVX2-SLOW-NEXT: popq %r14 -; AVX2-SLOW-NEXT: popq %rbp -; AVX2-SLOW-NEXT: vzeroupper -; AVX2-SLOW-NEXT: retq -; -; AVX2-FAST-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: -; AVX2-FAST: # %bb.0: -; AVX2-FAST-NEXT: pushq %rbp -; AVX2-FAST-NEXT: pushq %r14 -; AVX2-FAST-NEXT: pushq %rbx -; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-FAST-NEXT: vpextrw $6, %xmm2, %eax -; AVX2-FAST-NEXT: vpextrw $4, %xmm2, %ecx -; AVX2-FAST-NEXT: vpextrw $2, %xmm2, %edx -; AVX2-FAST-NEXT: vmovd %xmm2, %esi -; AVX2-FAST-NEXT: vpextrw $6, %xmm1, %edi -; AVX2-FAST-NEXT: vpextrw $4, %xmm1, %r8d -; AVX2-FAST-NEXT: vpextrw $2, %xmm1, %r9d -; AVX2-FAST-NEXT: vmovd %xmm1, %r10d -; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-FAST-NEXT: vpextrw $6, %xmm1, %r11d -; AVX2-FAST-NEXT: vpextrw $4, %xmm1, %ebx -; AVX2-FAST-NEXT: vpextrw $2, %xmm1, %ebp -; AVX2-FAST-NEXT: vmovd %xmm1, %r14d -; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX2-FAST-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 -; AVX2-FAST-NEXT: popq %rbx -; AVX2-FAST-NEXT: popq %r14 -; AVX2-FAST-NEXT: popq %rbp -; AVX2-FAST-NEXT: vzeroupper -; AVX2-FAST-NEXT: retq +; AVX2-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpextrw $6, %xmm2, %eax +; AVX2-NEXT: vpextrw $4, %xmm2, %ecx +; AVX2-NEXT: vpextrw $2, %xmm2, %edx +; AVX2-NEXT: vmovd %xmm2, %esi +; AVX2-NEXT: vpextrw $6, %xmm1, %edi +; AVX2-NEXT: vpextrw $4, %xmm1, %r8d +; AVX2-NEXT: vpextrw $2, %xmm1, %r9d +; AVX2-NEXT: vmovd %xmm1, %r10d +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpextrw $6, %xmm1, %r11d +; AVX2-NEXT: vpextrw $4, %xmm1, %ebx +; AVX2-NEXT: vpextrw $2, %xmm1, %ebp +; AVX2-NEXT: vmovd %xmm1, %r14d +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq ; ; AVX512F-LABEL: evenelts_v32i16_trunc_v16i16_to_v16i8: ; AVX512F: # %bb.0: @@ -1400,81 +1330,43 @@ define <16 x i8> @oddelts_v32i16_trunc_v16i16_to_v16i8(<32 x i16> %n2) nounwind ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; -; AVX2-SLOW-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: -; AVX2-SLOW: # %bb.0: -; AVX2-SLOW-NEXT: pushq %rbp -; AVX2-SLOW-NEXT: pushq %r14 -; AVX2-SLOW-NEXT: pushq %rbx -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-SLOW-NEXT: vpextrw $7, %xmm2, %eax -; AVX2-SLOW-NEXT: vpextrw $5, %xmm2, %ecx -; AVX2-SLOW-NEXT: vpextrw $3, %xmm2, %edx -; AVX2-SLOW-NEXT: vpextrw $1, %xmm2, %esi -; AVX2-SLOW-NEXT: vpextrw $7, %xmm1, %edi -; AVX2-SLOW-NEXT: vpextrw $5, %xmm1, %r8d -; AVX2-SLOW-NEXT: vpextrw $3, %xmm1, %r9d -; AVX2-SLOW-NEXT: vpextrw $1, %xmm1, %r10d -; AVX2-SLOW-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-SLOW-NEXT: vpextrw $7, %xmm1, %r11d -; AVX2-SLOW-NEXT: vpextrw $5, %xmm1, %ebx -; AVX2-SLOW-NEXT: vpextrw $3, %xmm1, %ebp -; AVX2-SLOW-NEXT: vpextrw $1, %xmm1, %r14d -; AVX2-SLOW-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX2-SLOW-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 -; AVX2-SLOW-NEXT: popq %rbx -; AVX2-SLOW-NEXT: popq %r14 -; AVX2-SLOW-NEXT: popq %rbp -; AVX2-SLOW-NEXT: vzeroupper -; AVX2-SLOW-NEXT: retq -; -; AVX2-FAST-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: -; AVX2-FAST: # %bb.0: -; AVX2-FAST-NEXT: pushq %rbp -; AVX2-FAST-NEXT: pushq %r14 -; AVX2-FAST-NEXT: pushq %rbx -; AVX2-FAST-NEXT: vextracti128 $1, %ymm1, %xmm2 -; AVX2-FAST-NEXT: vpextrw $7, %xmm2, %eax -; AVX2-FAST-NEXT: vpextrw $5, %xmm2, %ecx -; AVX2-FAST-NEXT: vpextrw $3, %xmm2, %edx -; AVX2-FAST-NEXT: vpextrw $1, %xmm2, %esi -; AVX2-FAST-NEXT: vpextrw $7, %xmm1, %edi -; AVX2-FAST-NEXT: vpextrw $5, %xmm1, %r8d -; AVX2-FAST-NEXT: vpextrw $3, %xmm1, %r9d -; AVX2-FAST-NEXT: vpextrw $1, %xmm1, %r10d -; AVX2-FAST-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-FAST-NEXT: vpextrw $7, %xmm1, %r11d -; AVX2-FAST-NEXT: vpextrw $5, %xmm1, %ebx -; AVX2-FAST-NEXT: vpextrw $3, %xmm1, %ebp -; AVX2-FAST-NEXT: vpextrw $1, %xmm1, %r14d -; AVX2-FAST-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] -; AVX2-FAST-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 -; AVX2-FAST-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 -; AVX2-FAST-NEXT: popq %rbx -; AVX2-FAST-NEXT: popq %r14 -; AVX2-FAST-NEXT: popq %rbp -; AVX2-FAST-NEXT: vzeroupper -; AVX2-FAST-NEXT: retq +; AVX2-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: +; AVX2: # %bb.0: +; AVX2-NEXT: pushq %rbp +; AVX2-NEXT: pushq %r14 +; AVX2-NEXT: pushq %rbx +; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2 +; AVX2-NEXT: vpextrw $7, %xmm2, %eax +; AVX2-NEXT: vpextrw $5, %xmm2, %ecx +; AVX2-NEXT: vpextrw $3, %xmm2, %edx +; AVX2-NEXT: vpextrw $1, %xmm2, %esi +; AVX2-NEXT: vpextrw $7, %xmm1, %edi +; AVX2-NEXT: vpextrw $5, %xmm1, %r8d +; AVX2-NEXT: vpextrw $3, %xmm1, %r9d +; AVX2-NEXT: vpextrw $1, %xmm1, %r10d +; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 +; AVX2-NEXT: vpextrw $7, %xmm1, %r11d +; AVX2-NEXT: vpextrw $5, %xmm1, %ebx +; AVX2-NEXT: vpextrw $3, %xmm1, %ebp +; AVX2-NEXT: vpextrw $1, %xmm1, %r14d +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,6,10,14,u,u,u,u,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpinsrb $4, %r14d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $5, %ebp, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $6, %ebx, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $7, %r11d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $8, %r10d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $9, %r9d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $10, %r8d, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $11, %edi, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $13, %edx, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0 +; AVX2-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0 +; AVX2-NEXT: popq %rbx +; AVX2-NEXT: popq %r14 +; AVX2-NEXT: popq %rbp +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq ; ; AVX512F-LABEL: oddelts_v32i16_trunc_v16i16_to_v16i8: ; AVX512F: # %bb.0: -- GitLab From 6f6336858e4588ebd113ebcc930f6384a4edca54 Mon Sep 17 00:00:00 2001 From: Billy Zhu Date: Tue, 9 Apr 2024 06:18:07 -0700 Subject: [PATCH 276/695] [MLIR][LLVM] Add DebugNameTableKind to DICompileUnit (#87974) Add the DebugNameTableKind field to DICompileUnit, along with its importer & exporter. --- .../Transforms/AddDebugFoundation.cpp | 2 +- mlir/include/mlir-c/Dialect/LLVM.h | 10 +++++++++- .../mlir/Dialect/LLVMIR/LLVMAttrDefs.td | 14 ++++++++++++- mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td | 20 +++++++++++++++++++ mlir/lib/CAPI/Dialect/LLVM.cpp | 6 ++++-- .../Transforms/DIScopeForLLVMFuncOp.cpp | 4 ++-- mlir/lib/Target/LLVMIR/DebugImporter.cpp | 6 +++++- mlir/lib/Target/LLVMIR/DebugTranslation.cpp | 5 ++++- mlir/test/CAPI/llvm.c | 6 +++--- mlir/test/Target/LLVMIR/Import/debug-info.ll | 4 ++-- mlir/test/Target/LLVMIR/llvmir-debug.mlir | 5 +++-- 11 files changed, 66 insertions(+), 16 deletions(-) diff --git a/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp b/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp index 7a6f58066722..678fbf6a7d23 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp @@ -65,7 +65,7 @@ void AddDebugFoundationPass::runOnOperation() { mlir::LLVM::DIFileAttr fileAttr = getFileAttr(inputFilePath); mlir::StringAttr producer = mlir::StringAttr::get(context, "Flang"); mlir::LLVM::DICompileUnitAttr cuAttr = mlir::LLVM::DICompileUnitAttr::get( - context, mlir::DistinctAttr::create(mlir::UnitAttr::get(context)), + mlir::DistinctAttr::create(mlir::UnitAttr::get(context)), llvm::dwarf::getLanguage("DW_LANG_Fortran95"), fileAttr, producer, /*isOptimized=*/false, mlir::LLVM::DIEmissionKind::LineTablesOnly); diff --git a/mlir/include/mlir-c/Dialect/LLVM.h b/mlir/include/mlir-c/Dialect/LLVM.h index 4f1d646f5bc8..bd9b7dd26f5e 100644 --- a/mlir/include/mlir-c/Dialect/LLVM.h +++ b/mlir/include/mlir-c/Dialect/LLVM.h @@ -257,11 +257,19 @@ enum MlirLLVMDIEmissionKind { }; typedef enum MlirLLVMDIEmissionKind MlirLLVMDIEmissionKind; +enum MlirLLVMDINameTableKind { + MlirLLVMDINameTableKindDefault = 0, + MlirLLVMDINameTableKindGNU = 1, + MlirLLVMDINameTableKindNone = 2, + MlirLLVMDINameTableKindApple = 3, +}; +typedef enum MlirLLVMDINameTableKind MlirLLVMDINameTableKind; + /// Creates a LLVM DICompileUnit attribute. MLIR_CAPI_EXPORTED MlirAttribute mlirLLVMDICompileUnitAttrGet( MlirContext ctx, MlirAttribute id, unsigned int sourceLanguage, MlirAttribute file, MlirAttribute producer, bool isOptimized, - MlirLLVMDIEmissionKind emissionKind); + MlirLLVMDIEmissionKind emissionKind, MlirLLVMDINameTableKind nameTableKind); /// Creates a LLVM DIFlags attribute. MLIR_CAPI_EXPORTED MlirAttribute mlirLLVMDIFlagsAttrGet(MlirContext ctx, diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td index 91bd3702f93b..cc849cb7c978 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td @@ -350,8 +350,20 @@ def LLVM_DICompileUnitAttr : LLVM_Attr<"DICompileUnit", "di_compile_unit", "DIFileAttr":$file, OptionalParameter<"StringAttr">:$producer, "bool":$isOptimized, - "DIEmissionKind":$emissionKind + "DIEmissionKind":$emissionKind, + OptionalParameter<"DINameTableKind">:$nameTableKind ); + let builders = [ + AttrBuilderWithInferredContext<(ins + "DistinctAttr":$id, "unsigned":$sourceLanguage, "DIFileAttr":$file, + "StringAttr":$producer, "bool":$isOptimized, + "DIEmissionKind":$emissionKind, + CArg<"DINameTableKind", "DINameTableKind::Default">:$nameTableKind + ), [{ + return $_get(id.getContext(), id, sourceLanguage, file, producer, + isOptimized, emissionKind, nameTableKind); + }]> + ]; let assemblyFormat = "`<` struct(params) `>`"; } diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td index 04d797031245..a93964abcb42 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMEnums.td @@ -393,6 +393,26 @@ def DIFlags : I32BitEnumAttr< let printBitEnumPrimaryGroups = 1; } +//===----------------------------------------------------------------------===// +// DINameTableKind +//===----------------------------------------------------------------------===// + +def LLVM_DINameTableDefault : I64EnumAttrCase<"Default", 0>; +def LLVM_DINameTableGNU : I64EnumAttrCase<"GNU", 1>; +def LLVM_DINameTableNone : I64EnumAttrCase<"None", 2>; +def LLVM_DINameTableApple : I64EnumAttrCase<"Apple", 3>; + +def LLVM_DINameTableKind : I64EnumAttr< + "DINameTableKind", + "LLVM debug name table kind", [ + LLVM_DINameTableDefault, + LLVM_DINameTableGNU, + LLVM_DINameTableNone, + LLVM_DINameTableApple, + ]> { + let cppNamespace = "::mlir::LLVM"; +} + //===----------------------------------------------------------------------===// // DISubprogramFlags //===----------------------------------------------------------------------===// diff --git a/mlir/lib/CAPI/Dialect/LLVM.cpp b/mlir/lib/CAPI/Dialect/LLVM.cpp index 71f2b73dd73b..4669c40f843d 100644 --- a/mlir/lib/CAPI/Dialect/LLVM.cpp +++ b/mlir/lib/CAPI/Dialect/LLVM.cpp @@ -206,11 +206,13 @@ MlirAttribute mlirLLVMDICompileUnitAttrGet(MlirContext ctx, MlirAttribute id, unsigned int sourceLanguage, MlirAttribute file, MlirAttribute producer, bool isOptimized, - MlirLLVMDIEmissionKind emissionKind) { + MlirLLVMDIEmissionKind emissionKind, + MlirLLVMDINameTableKind nameTableKind) { return wrap(DICompileUnitAttr::get( unwrap(ctx), cast(unwrap(id)), sourceLanguage, cast(unwrap(file)), cast(unwrap(producer)), - isOptimized, DIEmissionKind(emissionKind))); + isOptimized, DIEmissionKind(emissionKind), + DINameTableKind(nameTableKind))); } MlirAttribute mlirLLVMDIFlagsAttrGet(MlirContext ctx, uint64_t value) { diff --git a/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp b/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp index 2960cc6220d9..395ff6ed1e48 100644 --- a/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp +++ b/mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp @@ -115,8 +115,8 @@ struct DIScopeForLLVMFuncOp } compileUnitAttr = LLVM::DICompileUnitAttr::get( - context, DistinctAttr::create(UnitAttr::get(context)), - llvm::dwarf::DW_LANG_C, fileAttr, StringAttr::get(context, "MLIR"), + DistinctAttr::create(UnitAttr::get(context)), llvm::dwarf::DW_LANG_C, + fileAttr, StringAttr::get(context, "MLIR"), /*isOptimized=*/true, LLVM::DIEmissionKind::LineTablesOnly); } diff --git a/mlir/lib/Target/LLVMIR/DebugImporter.cpp b/mlir/lib/Target/LLVMIR/DebugImporter.cpp index aa8c307ba2ce..4a4e1d1ecdd8 100644 --- a/mlir/lib/Target/LLVMIR/DebugImporter.cpp +++ b/mlir/lib/Target/LLVMIR/DebugImporter.cpp @@ -56,10 +56,14 @@ DIBasicTypeAttr DebugImporter::translateImpl(llvm::DIBasicType *node) { DICompileUnitAttr DebugImporter::translateImpl(llvm::DICompileUnit *node) { std::optional emissionKind = symbolizeDIEmissionKind(node->getEmissionKind()); + std::optional nameTableKind = symbolizeDINameTableKind( + static_cast< + std::underlying_type_t>( + node->getNameTableKind())); return DICompileUnitAttr::get( context, getOrCreateDistinctID(node), node->getSourceLanguage(), translate(node->getFile()), getStringAttrOrNull(node->getRawProducer()), - node->isOptimized(), emissionKind.value()); + node->isOptimized(), emissionKind.value(), nameTableKind.value()); } DICompositeTypeAttr DebugImporter::translateImpl(llvm::DICompositeType *node) { diff --git a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp index f6e05e25ace6..46e2e7f2ba5d 100644 --- a/mlir/lib/Target/LLVMIR/DebugTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/DebugTranslation.cpp @@ -104,7 +104,10 @@ llvm::DICompileUnit *DebugTranslation::translateImpl(DICompileUnitAttr attr) { attr.getIsOptimized(), /*Flags=*/"", /*RV=*/0, /*SplitName=*/{}, static_cast( - attr.getEmissionKind())); + attr.getEmissionKind()), + 0, true, false, + static_cast( + attr.getNameTableKind())); } /// Returns a new `DINodeT` that is either distinct or not, depending on diff --git a/mlir/test/CAPI/llvm.c b/mlir/test/CAPI/llvm.c index 9c3c7da46c4c..25f900e521cf 100644 --- a/mlir/test/CAPI/llvm.c +++ b/mlir/test/CAPI/llvm.c @@ -264,9 +264,9 @@ static void testDebugInfoAttributes(MlirContext ctx) { // CHECK: #llvm.di_file<"foo" in "bar"> mlirAttributeDump(file); - MlirAttribute compile_unit = - mlirLLVMDICompileUnitAttrGet(ctx, id, LLVMDWARFSourceLanguageC99, file, - foo, false, MlirLLVMDIEmissionKindFull); + MlirAttribute compile_unit = mlirLLVMDICompileUnitAttrGet( + ctx, id, LLVMDWARFSourceLanguageC99, file, foo, false, + MlirLLVMDIEmissionKindFull, MlirLLVMDINameTableKindDefault); // CHECK: #llvm.di_compile_unit<{{.*}}> mlirAttributeDump(compile_unit); diff --git a/mlir/test/Target/LLVMIR/Import/debug-info.ll b/mlir/test/Target/LLVMIR/Import/debug-info.ll index e2ef94617dd7..245cf300d2c1 100644 --- a/mlir/test/Target/LLVMIR/Import/debug-info.ll +++ b/mlir/test/Target/LLVMIR/Import/debug-info.ll @@ -197,7 +197,7 @@ define void @composite_type() !dbg !3 { ; // ----- ; CHECK-DAG: #[[FILE:.+]] = #llvm.di_file<"debug-info.ll" in "/"> -; CHECK-DAG: #[[CU:.+]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[FILE]], isOptimized = false, emissionKind = None> +; CHECK-DAG: #[[CU:.+]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_C, file = #[[FILE]], isOptimized = false, emissionKind = None, nameTableKind = None> ; Verify an empty subroutine types list is supported. ; CHECK-DAG: #[[SP_TYPE:.+]] = #llvm.di_subroutine_type ; CHECK-DAG: #[[SP:.+]] = #llvm.di_subprogram, compileUnit = #[[CU]], scope = #[[FILE]], name = "subprogram", linkageName = "subprogram", file = #[[FILE]], line = 42, scopeLine = 42, subprogramFlags = Definition, type = #[[SP_TYPE]]> @@ -209,7 +209,7 @@ define void @subprogram() !dbg !3 { !llvm.dbg.cu = !{!1} !llvm.module.flags = !{!0} !0 = !{i32 2, !"Debug Info Version", i32 3} -!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2) +!1 = distinct !DICompileUnit(language: DW_LANG_C, file: !2, nameTableKind: None) !2 = !DIFile(filename: "debug-info.ll", directory: "/") !3 = distinct !DISubprogram(name: "subprogram", linkageName: "subprogram", scope: !2, file: !2, line: 42, scopeLine: 42, spFlags: DISPFlagDefinition, unit: !1, type: !4) !4 = !DISubroutineType(cc: DW_CC_normal, types: !5) diff --git a/mlir/test/Target/LLVMIR/llvmir-debug.mlir b/mlir/test/Target/LLVMIR/llvmir-debug.mlir index c4ca0e83f81e..f4c18bf6bd53 100644 --- a/mlir/test/Target/LLVMIR/llvmir-debug.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-debug.mlir @@ -37,7 +37,8 @@ llvm.func @func_no_debug() { > #cu = #llvm.di_compile_unit< id = distinct[0]<>, sourceLanguage = DW_LANG_C, file = #file, - producer = "MLIR", isOptimized = true, emissionKind = Full + producer = "MLIR", isOptimized = true, emissionKind = Full, + nameTableKind = None > #composite = #llvm.di_composite_type< tag = DW_TAG_structure_type, name = "composite", file = #file, @@ -127,7 +128,7 @@ llvm.func @empty_types() { llvm.return } loc(fused<#sp1>["foo.mlir":2:1]) -// CHECK: ![[CU_LOC:.*]] = distinct !DICompileUnit(language: DW_LANG_C, file: ![[CU_FILE_LOC:.*]], producer: "MLIR", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) +// CHECK: ![[CU_LOC:.*]] = distinct !DICompileUnit(language: DW_LANG_C, file: ![[CU_FILE_LOC:.*]], producer: "MLIR", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, nameTableKind: None) // CHECK: ![[CU_FILE_LOC]] = !DIFile(filename: "foo.mlir", directory: "/test/") // CHECK: ![[FUNC_LOC]] = distinct !DISubprogram(name: "func_with_debug", linkageName: "func_with_debug", scope: ![[NESTED_NAMESPACE:.*]], file: ![[CU_FILE_LOC]], line: 3, type: ![[FUNC_TYPE:.*]], scopeLine: 3, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: ![[CU_LOC]]) -- GitLab From 1e44d9ac5e9d1ff8baa99fd5495477f3f2f1abe6 Mon Sep 17 00:00:00 2001 From: Natalie Chouinard Date: Tue, 9 Apr 2024 09:41:47 -0400 Subject: [PATCH 277/695] [SPIR-V] Map llvm.{min,max}num to GL::N{Min,Max} (#88009) SPIR-V intsruction selection was mapping the LLVM float min/max intrinsics to FMin and FMax respectively for GL/Vulkan environments, which does not match the intrinsics' documented treatment of NaN operands. This patch switches the mapping to the correctly matched NMin and NMax operations. Fixes #87072 --- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 4 ++-- llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll | 7 +++---- llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll | 7 +++---- 3 files changed, 8 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 49749b563453..45a70da7f869 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -432,10 +432,10 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg, case TargetOpcode::G_FMINNUM: case TargetOpcode::G_FMINIMUM: - return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::FMin); + return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::NMin); case TargetOpcode::G_FMAXNUM: case TargetOpcode::G_FMAXIMUM: - return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::FMax); + return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::NMax); case TargetOpcode::G_FCOPYSIGN: return selectExtInst(ResVReg, ResType, I, CL::copysign); diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll index 48e916581f9f..159d4ac19c8c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll @@ -1,25 +1,24 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This need to be NMax: See https://github.com/llvm/llvm-project/issues/87072 ; CHECK: OpExtInstImport "GLSL.std.450" define noundef half @test_fmax_half(half noundef %a, half noundef %b) { entry: -; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMax %[[#]] %[[#]] +; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMax %[[#]] %[[#]] %0 = call half @llvm.maxnum.f16(half %a, half %b) ret half %0 } define noundef float @test_fmax_float(float noundef %a, float noundef %b) { entry: -; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMax %[[#]] %[[#]] +; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMax %[[#]] %[[#]] %0 = call float @llvm.maxnum.f32(float %a, float %b) ret float %0 } define noundef double @test_fmax_double(double noundef %a, double noundef %b) { entry: -; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMax %[[#]] %[[#]] +; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMax %[[#]] %[[#]] %0 = call double @llvm.maxnum.f64(double %a, double %b) ret double %0 } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll index 5bfd69c972a3..15946b5038ee 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll @@ -1,27 +1,26 @@ ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; TODO: This need to be NMin: See https://github.com/llvm/llvm-project/issues/87072 ; CHECK: OpExtInstImport "GLSL.std.450" ; CHECK: OpMemoryModel Logical GLSL450 define noundef half @test_fmax_half(half noundef %a, half noundef %b) { entry: -; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMin %[[#]] %[[#]] +; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMin %[[#]] %[[#]] %0 = call half @llvm.minnum.f16(half %a, half %b) ret half %0 } define noundef float @test_fmax_float(float noundef %a, float noundef %b) { entry: -; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMin %[[#]] %[[#]] +; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMin %[[#]] %[[#]] %0 = call float @llvm.minnum.f32(float %a, float %b) ret float %0 } define noundef double @test_fmax_double(double noundef %a, double noundef %b) { entry: -; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] FMin %[[#]] %[[#]] +; CHECK: %[[#]] = OpExtInst %[[#]] %[[#]] NMin %[[#]] %[[#]] %0 = call double @llvm.minnum.f64(double %a, double %b) ret double %0 } -- GitLab From 0c92f8646a765174b68797ad3c0842215c77752f Mon Sep 17 00:00:00 2001 From: Charalampos Mitrodimas Date: Tue, 9 Apr 2024 16:47:11 +0300 Subject: [PATCH 278/695] [clang] Disable missing definition warning on pure virtual functions (#74510) Warning '-Wundefined-func-template' incorrectly indicates that no definition is available for a pure virtual function. However, a definition is not needed for a pure virtual function. Fixes #74016 --- clang/docs/ReleaseNotes.rst | 4 ++ clang/lib/Sema/SemaExpr.cpp | 6 +- .../instantiate-pure-virtual-function.cpp | 67 +++++++++++++++++++ 3 files changed, 75 insertions(+), 2 deletions(-) create mode 100644 clang/test/SemaTemplate/instantiate-pure-virtual-function.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5708e691d084..5a39fe32f758 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -353,6 +353,10 @@ Improvements to Clang's time-trace Bug Fixes in This Version ------------------------- +- Clang's ``-Wundefined-func-template`` no longer warns on pure virtual + functions. + (`#74016 `_) + - Fixed missing warnings when comparing mismatched enumeration constants in C (`#29217 `). diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index bd221763b319..45acbf197ea6 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -18982,8 +18982,10 @@ void Sema::MarkFunctionReferenced(SourceLocation Loc, FunctionDecl *Func, // Note that we skip the implicit instantiation of templates that are only // used in unused default arguments or by recursive calls to themselves. // This is formally non-conforming, but seems reasonable in practice. - bool NeedDefinition = !IsRecursiveCall && (OdrUse == OdrUseContext::Used || - NeededForConstantEvaluation); + bool NeedDefinition = + !IsRecursiveCall && + (OdrUse == OdrUseContext::Used || + (NeededForConstantEvaluation && !Func->isPureVirtual())); // C++14 [temp.expl.spec]p6: // If a template [...] is explicitly specialized then that specialization diff --git a/clang/test/SemaTemplate/instantiate-pure-virtual-function.cpp b/clang/test/SemaTemplate/instantiate-pure-virtual-function.cpp new file mode 100644 index 000000000000..caec42b6b77f --- /dev/null +++ b/clang/test/SemaTemplate/instantiate-pure-virtual-function.cpp @@ -0,0 +1,67 @@ +// RUN: %clang_cc1 -fsyntax-only -verify -Wundefined-func-template %s + +namespace GH74016 { + template class B { + public: + constexpr void foo(const T &) { bar(1); } + virtual constexpr void bar(unsigned int) = 0; + }; + + template class D : public B { + public: + constexpr void bar(unsigned int) override {} + }; + + void test() { + auto t = D(); + t.foo(0); + } +}; + +namespace call_pure_virtual_function_from_virtual { + template class B { + public: + const void foo(const T &) { B::bar(1); } // expected-warning {{instantiation of function 'call_pure_virtual_function_from_virtual::B::bar' required here, but no definition is available}} + // expected-note@-1 {{add an explicit instantiation declaration to suppress this warning if 'call_pure_virtual_function_from_virtual::B::bar' is explicitly instantiated in another translation unit}} + virtual const void bar(unsigned int) = 0; // expected-note {{forward declaration of template entity is here}} + }; + + template class D : public B { + public: + const void bar(unsigned int) override {} + }; + + void test() { + auto t = D(); + t.foo(0); // expected-note {{in instantiation of member function 'call_pure_virtual_function_from_virtual::B::foo' requested here}} + } +}; + +namespace non_pure_virtual_function { + template class B { + public: + constexpr void foo(const T &) { bar(1); } + + virtual constexpr void bar(unsigned int); // expected-warning {{inline function 'non_pure_virtual_function::B::bar' is not defined}} + // expected-note@-1 {{forward declaration of template entity is here}} + // expected-note@-2 {{forward declaration of template entity is here}} + // expected-note@-3 {{forward declaration of template entity is here}} + }; + + template class D : public B { // expected-warning {{instantiation of function 'non_pure_virtual_function::B::bar' required here, but no definition is available}} +// expected-warning@-1 {{instantiation of function 'non_pure_virtual_function::B::bar' required here, but no definition is available}} +// expected-warning@-2 {{instantiation of function 'non_pure_virtual_function::B::bar' required here, but no definition is available}} +// expected-note@-3 {{add an explicit instantiation declaration to suppress this warning if 'non_pure_virtual_function::B::bar' is explicitly instantiated in another translation unit}} +// expected-note@-4 {{add an explicit instantiation declaration to suppress this warning if 'non_pure_virtual_function::B::bar' is explicitly instantiated in another translation unit}} +// expected-note@-5 {{add an explicit instantiation declaration to suppress this warning if 'non_pure_virtual_function::B::bar' is explicitly instantiated in another translation unit}} +// expected-note@-6 {{used here}} + + public: + constexpr void bar(unsigned int) override { } + }; + + void test() { + auto t = D(); + t.foo(0); + } +}; -- GitLab From d022f6b8ff94bb13d12d39f23a3c3e7836e90756 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 8 Apr 2024 15:26:54 -0500 Subject: [PATCH 279/695] [Libomp] Place generated OpenMP headers into build resource directory (#88007) Summary: These headers are a part of the compiler's resource directory once installed. However, they are currently placed in the binary directory temporarily. This makes it more difficult to use the compiler out of the build directory and will cause issues when moving to `liboffload`. This patch changes the logic to write these instead to the copmiler's resource directory inside of the build tree. NOTE: This doesn't change the Fortran headers, I don't know enough about those and it won't use the same directory. --- clang/test/Headers/Inputs/include/stdint.h | 8 +++++++ openmp/runtime/src/CMakeLists.txt | 26 ++++++++++++++-------- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/clang/test/Headers/Inputs/include/stdint.h b/clang/test/Headers/Inputs/include/stdint.h index 5bf26a7b67b0..67b27b8dfc7b 100644 --- a/clang/test/Headers/Inputs/include/stdint.h +++ b/clang/test/Headers/Inputs/include/stdint.h @@ -16,4 +16,12 @@ typedef unsigned __INTPTR_TYPE__ uintptr_t; #error Every target should have __INTPTR_TYPE__ #endif +#ifdef __INTPTR_MAX__ +#define INTPTR_MAX __INTPTR_MAX__ +#endif + +#ifdef __UINTPTR_MAX__ +#define UINTPTR_MAX __UINTPTR_MAX__ +#endif + #endif /* STDINT_H */ diff --git a/openmp/runtime/src/CMakeLists.txt b/openmp/runtime/src/CMakeLists.txt index f05bcabb4417..701c35150f30 100644 --- a/openmp/runtime/src/CMakeLists.txt +++ b/openmp/runtime/src/CMakeLists.txt @@ -10,12 +10,19 @@ include(ExtendPath) +# The generated headers will be placed in clang's resource directory if present. +if(OPENMP_STANDALONE_BUILD OR NOT LLVM_RUNTIMES_BUILD) + set(LIBOMP_HEADERS_INTDIR ${CMAKE_CURRENT_BINARY_DIR}) +else() + set(LIBOMP_HEADERS_INTDIR ${LLVM_BINARY_DIR}/${LIBOMP_HEADERS_INSTALL_PATH}) +endif() + # Configure omp.h, kmp_config.h and omp-tools.h if necessary -configure_file(${LIBOMP_INC_DIR}/omp.h.var omp.h @ONLY) -configure_file(${LIBOMP_INC_DIR}/ompx.h.var ompx.h @ONLY) -configure_file(kmp_config.h.cmake kmp_config.h @ONLY) +configure_file(${LIBOMP_INC_DIR}/omp.h.var ${LIBOMP_HEADERS_INTDIR}/omp.h @ONLY) +configure_file(${LIBOMP_INC_DIR}/ompx.h.var ${LIBOMP_HEADERS_INTDIR}/ompx.h @ONLY) +configure_file(kmp_config.h.cmake ${LIBOMP_HEADERS_INTDIR}/kmp_config.h @ONLY) if(${LIBOMP_OMPT_SUPPORT}) - configure_file(${LIBOMP_INC_DIR}/omp-tools.h.var omp-tools.h @ONLY) + configure_file(${LIBOMP_INC_DIR}/omp-tools.h.var ${LIBOMP_HEADERS_INTDIR}/omp-tools.h @ONLY) endif() # Generate message catalog files: kmp_i18n_id.inc and kmp_i18n_default.inc @@ -48,6 +55,7 @@ include_directories( ${LIBOMP_SRC_DIR}/i18n ${LIBOMP_INC_DIR} ${LIBOMP_SRC_DIR}/thirdparty/ittnotify + ${LIBOMP_HEADERS_INTDIR} ) # Building with time profiling support requires LLVM directory includes. @@ -419,15 +427,15 @@ else() endif() install( FILES - ${CMAKE_CURRENT_BINARY_DIR}/omp.h - ${CMAKE_CURRENT_BINARY_DIR}/ompx.h + ${LIBOMP_HEADERS_INTDIR}/omp.h + ${LIBOMP_HEADERS_INTDIR}/ompx.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} ) if(${LIBOMP_OMPT_SUPPORT}) - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) + install(FILES ${LIBOMP_HEADERS_INTDIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH}) # install under legacy name ompt.h - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} RENAME ompt.h) - set(LIBOMP_OMP_TOOLS_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR} PARENT_SCOPE) + install(FILES ${LIBOMP_HEADERS_INTDIR}/omp-tools.h DESTINATION ${LIBOMP_HEADERS_INSTALL_PATH} RENAME ompt.h) + set(LIBOMP_OMP_TOOLS_INCLUDE_DIR ${LIBOMP_HEADERS_INTDIR} PARENT_SCOPE) endif() if(${BUILD_FORTRAN_MODULES}) set (destination ${LIBOMP_HEADERS_INSTALL_PATH}) -- GitLab From 2875e2448c147d8a2335882819acdd4c8eb97ea6 Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Tue, 9 Apr 2024 06:59:31 -0700 Subject: [PATCH 280/695] Update __cpp_concepts macro (#87998) After discussion with a few others, and seeing the state of our concepts support, I believe it is worth trying to see if we can update this for Clang19. The forcing function is that libstdc++'s `` header is guarded by this macro, so we need to update it to support that. --- clang/docs/ReleaseNotes.rst | 4 ++++ clang/lib/Frontend/InitPreprocessor.cpp | 5 +---- clang/test/Lexer/cxx-features.cpp | 2 +- clang/www/cxx_status.html | 12 ++---------- 4 files changed, 8 insertions(+), 15 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5a39fe32f758..9349cc788e5f 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -110,6 +110,10 @@ C++20 Feature Support templates (`P1814R0 `_). (#GH54051). +- We have sufficient confidence and experience with the concepts implementation + to update the ``__cpp_concepts`` macro to `202002L`. This enables + ```` from libstdc++ to work correctly with Clang. + C++23 Feature Support ^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index 48ad92063bd4..84069e96f414 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -720,10 +720,7 @@ static void InitializeCPlusPlusFeatureTestMacros(const LangOptions &LangOpts, if (LangOpts.CPlusPlus20) { Builder.defineMacro("__cpp_aggregate_paren_init", "201902L"); - // P0848 is implemented, but we're still waiting for other concepts - // issues to be addressed before bumping __cpp_concepts up to 202002L. - // Refer to the discussion of this at https://reviews.llvm.org/D128619. - Builder.defineMacro("__cpp_concepts", "201907L"); + Builder.defineMacro("__cpp_concepts", "202002"); Builder.defineMacro("__cpp_conditional_explicit", "201806L"); Builder.defineMacro("__cpp_consteval", "202211L"); Builder.defineMacro("__cpp_constexpr_dynamic_alloc", "201907L"); diff --git a/clang/test/Lexer/cxx-features.cpp b/clang/test/Lexer/cxx-features.cpp index 9496746c6fd6..1de32498cd34 100644 --- a/clang/test/Lexer/cxx-features.cpp +++ b/clang/test/Lexer/cxx-features.cpp @@ -85,7 +85,7 @@ #error "wrong value for __cpp_char8_t" #endif -#if check(concepts, 0, 0, 0, 0, 201907, 201907, 201907) +#if check(concepts, 0, 0, 0, 0, 202002, 202002, 202002) #error "wrong value for __cpp_concepts" #endif diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index c1d95dadbb27..130148c7420f 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -544,16 +544,8 @@ C++23, informally referred to as C++26.

P0848R3 - -
- Clang 16 (Partial) - Because of other concepts implementation deficits, the __cpp_concepts macro is not yet set to 202002L. - Also, the related defect reports DR1496 and - DR1734 are not yet implemented. Accordingly, deleted - special member functions are treated as eligible even though they shouldn't be. -
- - + Clang 19 + P1616R1 Clang 10 -- GitLab From 3f71d29e2370912ccc0384adce640c554561edd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Tue, 9 Apr 2024 15:49:36 +0200 Subject: [PATCH 281/695] [clang][Interp] Handle __unaligned in alignof expressions --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 3 +++ clang/test/AST/Interp/ms.cpp | 2 ++ 2 files changed, 5 insertions(+) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 50e86d947364..a1ce65751483 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -1084,6 +1084,9 @@ static CharUnits AlignOfType(QualType T, const ASTContext &ASTCtx, if (const auto *Ref = T->getAs()) T = Ref->getPointeeType(); + if (T.getQualifiers().hasUnaligned()) + return CharUnits::One(); + // __alignof is defined to return the preferred alignment. // Before 8, clang returned the preferred alignment for alignof and // _Alignof as well. diff --git a/clang/test/AST/Interp/ms.cpp b/clang/test/AST/Interp/ms.cpp index 99716e90c7a1..fe5ed219946e 100644 --- a/clang/test/AST/Interp/ms.cpp +++ b/clang/test/AST/Interp/ms.cpp @@ -6,3 +6,5 @@ /// Used to assert because the two parameters to _rotl do not have the same type. static_assert(_rotl(0x01, 5) == 32); + +static_assert(alignof(__unaligned int) == 1, ""); -- GitLab From 23b058cb7f2da7778eb66dbe44d5e60390264e4b Mon Sep 17 00:00:00 2001 From: Vyacheslav Levytskyy Date: Tue, 9 Apr 2024 16:15:44 +0200 Subject: [PATCH 282/695] [SPIR-V] Re-implement switch and improve validation of forward calls (#87823) This PR fixes issue https://github.com/llvm/llvm-project/issues/87763 and preserves valid CFG in cases when previous scheme failed to generate valid code for a switch statement. The PR hardens one existing test case and adds one more test case as a validation of a new switch generation. Tests are passing spirv-val now. This PR also improves validation of forward calls. --- llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp | 10 +- llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 35 ++- llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 7 +- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 17 +- llvm/lib/Target/SPIRV/SPIRVISelLowering.h | 4 + llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 223 +++++------------- .../SPIRV/branching/OpSwitchUnreachable.ll | 5 +- .../SPIRV/branching/switch-range-check.ll | 73 ++++++ 8 files changed, 189 insertions(+), 185 deletions(-) create mode 100644 llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp index 4eee8062f282..1de4616fd5b7 100644 --- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp @@ -43,6 +43,8 @@ using namespace llvm; namespace { class SPIRVAsmPrinter : public AsmPrinter { + unsigned NLabels = 0; + public: explicit SPIRVAsmPrinter(TargetMachine &TM, std::unique_ptr Streamer) @@ -109,10 +111,9 @@ void SPIRVAsmPrinter::emitEndOfAsmFile(Module &M) { uint32_t DecSPIRVVersion = ST->getSPIRVVersion(); uint32_t Major = DecSPIRVVersion / 10; uint32_t Minor = DecSPIRVVersion - Major * 10; - // TODO: calculate Bound more carefully from maximum used register number, - // accounting for generated OpLabels and other related instructions if - // needed. - unsigned Bound = 2 * (ST->getBound() + 1); + // Bound is an approximation that accounts for the maximum used register + // number and number of generated OpLabels + unsigned Bound = 2 * (ST->getBound() + 1) + NLabels; bool FlagToRestore = OutStreamer->getUseAssemblerInfoForParsing(); OutStreamer->setUseAssemblerInfoForParsing(true); if (MCAssembler *Asm = OutStreamer->getAssemblerPtr()) @@ -158,6 +159,7 @@ void SPIRVAsmPrinter::emitOpLabel(const MachineBasicBlock &MBB) { LabelInst.setOpcode(SPIRV::OpLabel); LabelInst.addOperand(MCOperand::createReg(MAI->getOrCreateMBBRegister(MBB))); outputMCInst(LabelInst); + ++NLabels; } void SPIRVAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp index b341fcb41d03..e8ce5a35b457 100644 --- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp @@ -460,15 +460,36 @@ void SPIRVEmitIntrinsics::preprocessCompositeConstants(IRBuilder<> &B) { } Instruction *SPIRVEmitIntrinsics::visitSwitchInst(SwitchInst &I) { - IRBuilder<> B(I.getParent()); + BasicBlock *ParentBB = I.getParent(); + IRBuilder<> B(ParentBB); + B.SetInsertPoint(&I); SmallVector Args; - for (auto &Op : I.operands()) - if (Op.get()->getType()->isSized()) + SmallVector BBCases; + for (auto &Op : I.operands()) { + if (Op.get()->getType()->isSized()) { Args.push_back(Op); - B.SetInsertPoint(&I); - B.CreateIntrinsic(Intrinsic::spv_switch, {I.getOperand(0)->getType()}, - {Args}); - return &I; + } else if (BasicBlock *BB = dyn_cast(Op.get())) { + BBCases.push_back(BB); + Args.push_back(BlockAddress::get(BB->getParent(), BB)); + } else { + report_fatal_error("Unexpected switch operand"); + } + } + CallInst *NewI = B.CreateIntrinsic(Intrinsic::spv_switch, + {I.getOperand(0)->getType()}, {Args}); + // remove switch to avoid its unneeded and undesirable unwrap into branches + // and conditions + I.replaceAllUsesWith(NewI); + I.eraseFromParent(); + // insert artificial and temporary instruction to preserve valid CFG, + // it will be removed after IR translation pass + B.SetInsertPoint(ParentBB); + IndirectBrInst *BrI = B.CreateIndirectBr( + Constant::getNullValue(PointerType::getUnqual(ParentBB->getContext())), + BBCases.size()); + for (BasicBlock *BBCase : BBCases) + BrI->addDestination(BBCase); + return BrI; } Instruction *SPIRVEmitIntrinsics::visitGetElementPtrInst(GetElementPtrInst &I) { diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h index ac799374adce..37f575e884ef 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h +++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h @@ -284,7 +284,12 @@ public: // Return the VReg holding the result of the given OpTypeXXX instruction. Register getSPIRVTypeID(const SPIRVType *SpirvType) const; - void setCurrentFunc(MachineFunction &MF) { CurMF = &MF; } + // Return previous value of the current machine function + MachineFunction *setCurrentFunc(MachineFunction &MF) { + MachineFunction *Ret = CurMF; + CurMF = &MF; + return Ret; + } // Whether the given VReg has an OpTypeXXX instruction mapped to it with the // given opcode (e.g. OpTypeFloat). diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp index d450078d793f..8db54c74f236 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp @@ -160,12 +160,15 @@ void validateFunCallMachineDef(const SPIRVSubtarget &STI, : nullptr; if (DefElemType) { const Type *DefElemTy = GR.getTypeForSPIRVType(DefElemType); - // Switch GR context to the call site instead of the (default) definition - // side - GR.setCurrentFunc(*FunCall.getParent()->getParent()); + // validatePtrTypes() works in the context if the call site + // When we process historical records about forward calls + // we need to switch context to the (forward) call site and + // then restore it back to the current machine function. + MachineFunction *CurMF = + GR.setCurrentFunc(*FunCall.getParent()->getParent()); validatePtrTypes(STI, CallMRI, GR, FunCall, OpIdx, DefElemType, DefElemTy); - GR.setCurrentFunc(*FunDef->getParent()->getParent()); + GR.setCurrentFunc(*CurMF); } } } @@ -215,6 +218,11 @@ void validateAccessChain(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI, // TODO: the logic of inserting additional bitcast's is to be moved // to pre-IRTranslation passes eventually void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const { + // finalizeLowering() is called twice (see GlobalISel/InstructionSelect.cpp) + // We'd like to avoid the needless second processing pass. + if (ProcessedMF.find(&MF) != ProcessedMF.end()) + return; + MachineRegisterInfo *MRI = &MF.getRegInfo(); SPIRVGlobalRegistry &GR = *STI.getSPIRVGlobalRegistry(); GR.setCurrentFunc(MF); @@ -302,5 +310,6 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const { } } } + ProcessedMF.insert(&MF); TargetLowering::finalizeLowering(MF); } diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h index b01571bfc1ee..8c1de7d97d1a 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.h +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.h @@ -16,6 +16,7 @@ #include "SPIRVGlobalRegistry.h" #include "llvm/CodeGen/TargetLowering.h" +#include namespace llvm { class SPIRVSubtarget; @@ -23,6 +24,9 @@ class SPIRVSubtarget; class SPIRVTargetLowering : public TargetLowering { const SPIRVSubtarget &STI; + // Record of already processed machine functions + mutable std::set ProcessedMF; + public: explicit SPIRVTargetLowering(const TargetMachine &TM, const SPIRVSubtarget &ST) diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index b133f0ae85de..7e155a36aadb 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -438,186 +438,75 @@ static void processInstrsWithTypeFolding(MachineFunction &MF, } } +// Find basic blocks of the switch and replace registers in spv_switch() by its +// MBB equivalent. static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB) { - // Before IRTranslator pass, calls to spv_switch intrinsic are inserted before - // each switch instruction. IRTranslator lowers switches to G_ICMP + G_BRCOND - // + G_BR triples. A switch with two cases may be transformed to this MIR - // sequence: - // - // intrinsic(@llvm.spv.switch), %CmpReg, %Const0, %Const1 - // %Dst0 = G_ICMP intpred(eq), %CmpReg, %Const0 - // G_BRCOND %Dst0, %bb.2 - // G_BR %bb.5 - // bb.5.entry: - // %Dst1 = G_ICMP intpred(eq), %CmpReg, %Const1 - // G_BRCOND %Dst1, %bb.3 - // G_BR %bb.4 - // bb.2.sw.bb: - // ... - // bb.3.sw.bb1: - // ... - // bb.4.sw.epilog: - // ... - // - // Sometimes (in case of range-compare switches), additional G_SUBs - // instructions are inserted before G_ICMPs. Those need to be additionally - // processed. - // - // This function modifies spv_switch call's operands to include destination - // MBBs (default and for each constant value). - // - // At the end, the function removes redundant [G_SUB] + G_ICMP + G_BRCOND + - // G_BR sequences. - - MachineRegisterInfo &MRI = MF.getRegInfo(); - - // Collect spv_switches and G_ICMPs across all MBBs in MF. - std::vector RelevantInsts; - - // Collect redundant MIs from [G_SUB] + G_ICMP + G_BRCOND + G_BR sequences. - // After updating spv_switches, the instructions can be removed. - std::vector PostUpdateArtifacts; - - // Temporary set of compare registers. G_SUBs and G_ICMPs relating to - // spv_switch use these registers. - DenseSet CompareRegs; + DenseMap BB2MBB; + SmallVector>> + Switches; for (MachineBasicBlock &MBB : MF) { + MachineRegisterInfo &MRI = MF.getRegInfo(); + BB2MBB[MBB.getBasicBlock()] = &MBB; for (MachineInstr &MI : MBB) { + if (!isSpvIntrinsic(MI, Intrinsic::spv_switch)) + continue; // Calls to spv_switch intrinsics representing IR switches. - if (isSpvIntrinsic(MI, Intrinsic::spv_switch)) { - assert(MI.getOperand(1).isReg()); - CompareRegs.insert(MI.getOperand(1).getReg()); - RelevantInsts.push_back(&MI); - } - - // G_SUBs coming from range-compare switch lowering. G_SUBs are found - // after spv_switch but before G_ICMP. - if (MI.getOpcode() == TargetOpcode::G_SUB && MI.getOperand(1).isReg() && - CompareRegs.contains(MI.getOperand(1).getReg())) { - assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg()); - Register Dst = MI.getOperand(0).getReg(); - CompareRegs.insert(Dst); - PostUpdateArtifacts.push_back(&MI); - } - - // G_ICMPs relating to switches. - if (MI.getOpcode() == TargetOpcode::G_ICMP && MI.getOperand(2).isReg() && - CompareRegs.contains(MI.getOperand(2).getReg())) { - Register Dst = MI.getOperand(0).getReg(); - RelevantInsts.push_back(&MI); - PostUpdateArtifacts.push_back(&MI); - MachineInstr *CBr = MRI.use_begin(Dst)->getParent(); - assert(CBr->getOpcode() == SPIRV::G_BRCOND); - PostUpdateArtifacts.push_back(CBr); - MachineInstr *Br = CBr->getNextNode(); - assert(Br->getOpcode() == SPIRV::G_BR); - PostUpdateArtifacts.push_back(Br); + SmallVector NewOps; + for (unsigned i = 2; i < MI.getNumOperands(); ++i) { + Register Reg = MI.getOperand(i).getReg(); + if (i % 2 == 1) { + MachineInstr *ConstInstr = getDefInstrMaybeConstant(Reg, &MRI); + NewOps.push_back(ConstInstr); + } else { + MachineInstr *BuildMBB = MRI.getVRegDef(Reg); + assert(BuildMBB && + BuildMBB->getOpcode() == TargetOpcode::G_BLOCK_ADDR && + BuildMBB->getOperand(1).isBlockAddress() && + BuildMBB->getOperand(1).getBlockAddress()); + NewOps.push_back(BuildMBB); + } } + Switches.push_back(std::make_pair(&MI, NewOps)); } } - // Update each spv_switch with destination MBBs. - for (auto i = RelevantInsts.begin(); i != RelevantInsts.end(); i++) { - if (!isSpvIntrinsic(**i, Intrinsic::spv_switch)) - continue; - - // Currently considered spv_switch. - MachineInstr *Switch = *i; - // Set the first successor as default MBB to support empty switches. - MachineBasicBlock *DefaultMBB = *Switch->getParent()->succ_begin(); - // Container for mapping values to MMBs. - SmallDenseMap ValuesToMBBs; - - // Walk all G_ICMPs to collect ValuesToMBBs. Start at currently considered - // spv_switch (i) and break at any spv_switch with the same compare - // register (indicating we are back at the same scope). - Register CompareReg = Switch->getOperand(1).getReg(); - for (auto j = i + 1; j != RelevantInsts.end(); j++) { - if (isSpvIntrinsic(**j, Intrinsic::spv_switch) && - (*j)->getOperand(1).getReg() == CompareReg) - break; - - if (!((*j)->getOpcode() == TargetOpcode::G_ICMP && - (*j)->getOperand(2).getReg() == CompareReg)) - continue; - - MachineInstr *ICMP = *j; - Register Dst = ICMP->getOperand(0).getReg(); - MachineOperand &PredOp = ICMP->getOperand(1); - const auto CC = static_cast(PredOp.getPredicate()); - (void)CC; - assert((CC == CmpInst::ICMP_EQ || CC == CmpInst::ICMP_ULE) && - MRI.hasOneUse(Dst) && MRI.hasOneDef(CompareReg)); - uint64_t Value = getIConstVal(ICMP->getOperand(3).getReg(), &MRI); - MachineInstr *CBr = MRI.use_begin(Dst)->getParent(); - assert(CBr->getOpcode() == SPIRV::G_BRCOND && CBr->getOperand(1).isMBB()); - MachineBasicBlock *MBB = CBr->getOperand(1).getMBB(); - - // Map switch case Value to target MBB. - ValuesToMBBs[Value] = MBB; - - // Add target MBB as successor to the switch's MBB. - Switch->getParent()->addSuccessor(MBB); - - // The next MI is always G_BR to either the next case or the default. - MachineInstr *NextMI = CBr->getNextNode(); - assert(NextMI->getOpcode() == SPIRV::G_BR && - NextMI->getOperand(0).isMBB()); - MachineBasicBlock *NextMBB = NextMI->getOperand(0).getMBB(); - // Default MBB does not begin with G_ICMP using spv_switch compare - // register. - if (NextMBB->front().getOpcode() != SPIRV::G_ICMP || - (NextMBB->front().getOperand(2).isReg() && - NextMBB->front().getOperand(2).getReg() != CompareReg)) { - // Set default MBB and add it as successor to the switch's MBB. - DefaultMBB = NextMBB; - Switch->getParent()->addSuccessor(DefaultMBB); + SmallPtrSet ToEraseMI; + for (auto &SwIt : Switches) { + MachineInstr &MI = *SwIt.first; + SmallVector &Ins = SwIt.second; + SmallVector NewOps; + for (unsigned i = 0; i < Ins.size(); ++i) { + if (Ins[i]->getOpcode() == TargetOpcode::G_BLOCK_ADDR) { + BasicBlock *CaseBB = + Ins[i]->getOperand(1).getBlockAddress()->getBasicBlock(); + auto It = BB2MBB.find(CaseBB); + if (It == BB2MBB.end()) + report_fatal_error("cannot find a machine basic block by a basic " + "block in a switch statement"); + NewOps.push_back(MachineOperand::CreateMBB(It->second)); + MI.getParent()->addSuccessor(It->second); + ToEraseMI.insert(Ins[i]); + } else { + NewOps.push_back( + MachineOperand::CreateCImm(Ins[i]->getOperand(1).getCImm())); } } - - // Modify considered spv_switch operands using collected Values and - // MBBs. - SmallVector Values; - SmallVector MBBs; - for (unsigned k = 2; k < Switch->getNumExplicitOperands(); k++) { - Register CReg = Switch->getOperand(k).getReg(); - uint64_t Val = getIConstVal(CReg, &MRI); - MachineInstr *ConstInstr = getDefInstrMaybeConstant(CReg, &MRI); - if (!ValuesToMBBs[Val]) - continue; - - Values.push_back(ConstInstr->getOperand(1).getCImm()); - MBBs.push_back(ValuesToMBBs[Val]); - } - - for (unsigned k = Switch->getNumExplicitOperands() - 1; k > 1; k--) - Switch->removeOperand(k); - - Switch->addOperand(MachineOperand::CreateMBB(DefaultMBB)); - for (unsigned k = 0; k < Values.size(); k++) { - Switch->addOperand(MachineOperand::CreateCImm(Values[k])); - Switch->addOperand(MachineOperand::CreateMBB(MBBs[k])); - } - } - - for (MachineInstr *MI : PostUpdateArtifacts) { - MachineBasicBlock *ParentMBB = MI->getParent(); - MI->eraseFromParent(); - // If G_ICMP + G_BRCOND + G_BR were the only MIs in MBB, erase this MBB. It - // can be safely assumed, there are no breaks or phis directing into this - // MBB. However, we need to remove this MBB from the CFG graph. MBBs must be - // erased top-down. - if (ParentMBB->empty()) { - while (!ParentMBB->pred_empty()) - (*ParentMBB->pred_begin())->removeSuccessor(ParentMBB); - - while (!ParentMBB->succ_empty()) - ParentMBB->removeSuccessor(ParentMBB->succ_begin()); - - ParentMBB->eraseFromParent(); + for (unsigned i = MI.getNumOperands() - 1; i > 1; --i) + MI.removeOperand(i); + for (auto &MO : NewOps) + MI.addOperand(MO); + if (MachineInstr *Next = MI.getNextNode()) { + if (isSpvIntrinsic(*Next, Intrinsic::spv_track_constant)) { + ToEraseMI.insert(Next); + Next = MI.getNextNode(); + } + if (Next && Next->getOpcode() == TargetOpcode::G_BRINDIRECT) + ToEraseMI.insert(Next); } } + for (MachineInstr *BlockAddrI : ToEraseMI) + BlockAddrI->eraseFromParent(); } static bool isImplicitFallthrough(MachineBasicBlock &MBB) { diff --git a/llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll b/llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll index e73efbeade70..6eb36e5756ec 100644 --- a/llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll +++ b/llvm/test/CodeGen/SPIRV/branching/OpSwitchUnreachable.ll @@ -1,8 +1,9 @@ ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} define void @test_switch_with_unreachable_block(i1 %a) { %value = zext i1 %a to i32 -; CHECK-SPIRV: OpSwitch %[[#]] %[[#REACHABLE:]] +; CHECK-SPIRV: OpSwitch %[[#]] %[[#UNREACHABLE:]] 0 %[[#REACHABLE:]] 1 %[[#REACHABLE:]] switch i32 %value, label %unreachable [ i32 0, label %reachable i32 1, label %reachable @@ -13,7 +14,7 @@ reachable: ; CHECK-SPIRV-NEXT: OpReturn ret void -; CHECK-SPIRV: %[[#]] = OpLabel +; CHECK-SPIRV: %[[#UNREACHABLE]] = OpLabel ; CHECK-SPIRV-NEXT: OpUnreachable unreachable: unreachable diff --git a/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll b/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll new file mode 100644 index 000000000000..85a4d4db089c --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/branching/switch-range-check.ll @@ -0,0 +1,73 @@ +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: %[[#Var:]] = OpPhi +; CHECK: OpSwitch %[[#Var]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] [[#]] %[[#]] +; CHECK-COUNT-11: OpBranch +; CHECK-NOT: OpBranch + +define spir_func void @foo(i64 noundef %addr, i64 noundef %as) { +entry: + %src = inttoptr i64 %as to ptr addrspace(4) + %val = load i8, ptr addrspace(4) %src + %cmp = icmp sgt i8 %val, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + %add.ptr = getelementptr inbounds i8, ptr addrspace(4) %src, i64 1 + %cond = load i8, ptr addrspace(4) %add.ptr + br label %if.end + +if.end: + %swval = phi i8 [ %cond, %if.then ], [ %val, %entry ] + switch i8 %swval, label %sw.default [ + i8 -127, label %sw.epilog + i8 -126, label %sw.bb3 + i8 -125, label %sw.bb4 + i8 -111, label %sw.bb5 + i8 -110, label %sw.bb6 + i8 -109, label %sw.bb7 + i8 -15, label %sw.bb8 + i8 -14, label %sw.bb8 + i8 -13, label %sw.bb8 + i8 -124, label %sw.bb9 + i8 -95, label %sw.bb10 + i8 -123, label %sw.bb11 + ] + +sw.bb3: + br label %sw.epilog + +sw.bb4: + br label %sw.epilog + +sw.bb5: + br label %sw.epilog + +sw.bb6: + br label %sw.epilog + +sw.bb7: + br label %sw.epilog + +sw.bb8: + br label %sw.epilog + +sw.bb9: + br label %sw.epilog + +sw.bb10: + br label %sw.epilog + +sw.bb11: + br label %sw.epilog + +sw.default: + br label %sw.epilog + +sw.epilog: + br label %exit + +exit: + ret void +} -- GitLab From e47fd09f8eece712707f9611992cf6cfcd66605e Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Tue, 9 Apr 2024 07:29:10 -0700 Subject: [PATCH 283/695] [RISCV] Use shNadd for scalable stack offsets (#88062) If we need to multiply VLENB by 2, 4, or 8 and add it to the stack pointer, we can do so with a shNadd instead of separate shift and add instructions. --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 19 +- .../CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll | 238 +++++++++++++----- 2 files changed, 195 insertions(+), 62 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 426a8b66b2e1..46e79272d60e 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -204,10 +204,21 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB, uint32_t NumOfVReg = ScalableValue / 8; BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), ScratchReg) .setMIFlag(Flag); - TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag); - BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) - .addReg(SrcReg).addReg(ScratchReg, RegState::Kill) - .setMIFlag(Flag); + + if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() && + (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) { + unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD : + (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD); + BuildMI(MBB, II, DL, TII->get(Opc), DestReg) + .addReg(ScratchReg, RegState::Kill) + .addReg(SrcReg, getKillRegState(KillSrcReg)) + .setMIFlag(Flag); + } else { + TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag); + BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) + .addReg(SrcReg).addReg(ScratchReg, RegState::Kill) + .setMIFlag(Flag); + } SrcReg = DestReg; KillSrcReg = true; } diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll index 466ab085b266..90794820ddd8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll @@ -7,29 +7,67 @@ ; RUN: | FileCheck %s --check-prefixes=CHECK,NOMUL define void @lmul1() nounwind { -; CHECK-LABEL: lmul1: -; CHECK: # %bb.0: -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 1 -; CHECK-NEXT: sub sp, sp, a0 -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 1 -; CHECK-NEXT: add sp, sp, a0 -; CHECK-NEXT: ret +; NOZBA-LABEL: lmul1: +; NOZBA: # %bb.0: +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 1 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 1 +; NOZBA-NEXT: add sp, sp, a0 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: lmul1: +; ZBA: # %bb.0: +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 1 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: sh1add sp, a0, sp +; ZBA-NEXT: ret +; +; NOMUL-LABEL: lmul1: +; NOMUL: # %bb.0: +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 1 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 1 +; NOMUL-NEXT: add sp, sp, a0 +; NOMUL-NEXT: ret %v = alloca ret void } define void @lmul2() nounwind { -; CHECK-LABEL: lmul2: -; CHECK: # %bb.0: -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 1 -; CHECK-NEXT: sub sp, sp, a0 -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 1 -; CHECK-NEXT: add sp, sp, a0 -; CHECK-NEXT: ret +; NOZBA-LABEL: lmul2: +; NOZBA: # %bb.0: +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 1 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 1 +; NOZBA-NEXT: add sp, sp, a0 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: lmul2: +; ZBA: # %bb.0: +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 1 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: sh1add sp, a0, sp +; ZBA-NEXT: ret +; +; NOMUL-LABEL: lmul2: +; NOMUL: # %bb.0: +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 1 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 1 +; NOMUL-NEXT: add sp, sp, a0 +; NOMUL-NEXT: ret %v = alloca ret void } @@ -75,15 +113,34 @@ define void @lmul8() nounwind { } define void @lmul1_and_2() nounwind { -; CHECK-LABEL: lmul1_and_2: -; CHECK: # %bb.0: -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: sub sp, sp, a0 -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: add sp, sp, a0 -; CHECK-NEXT: ret +; NOZBA-LABEL: lmul1_and_2: +; NOZBA: # %bb.0: +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: add sp, sp, a0 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: lmul1_and_2: +; ZBA: # %bb.0: +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 2 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: sh2add sp, a0, sp +; ZBA-NEXT: ret +; +; NOMUL-LABEL: lmul1_and_2: +; NOMUL: # %bb.0: +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: add sp, sp, a0 +; NOMUL-NEXT: ret %v1 = alloca %v2 = alloca ret void @@ -132,15 +189,34 @@ define void @lmul1_and_4() nounwind { } define void @lmul2_and_1() nounwind { -; CHECK-LABEL: lmul2_and_1: -; CHECK: # %bb.0: -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: sub sp, sp, a0 -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: add sp, sp, a0 -; CHECK-NEXT: ret +; NOZBA-LABEL: lmul2_and_1: +; NOZBA: # %bb.0: +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: add sp, sp, a0 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: lmul2_and_1: +; ZBA: # %bb.0: +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 2 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: sh2add sp, a0, sp +; ZBA-NEXT: ret +; +; NOMUL-LABEL: lmul2_and_1: +; NOMUL: # %bb.0: +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: add sp, sp, a0 +; NOMUL-NEXT: ret %v1 = alloca %v2 = alloca ret void @@ -273,19 +349,46 @@ define void @lmul4_and_2_x2_1() nounwind { define void @gpr_and_lmul1_and_2() nounwind { -; CHECK-LABEL: gpr_and_lmul1_and_2: -; CHECK: # %bb.0: -; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: sub sp, sp, a0 -; CHECK-NEXT: li a0, 3 -; CHECK-NEXT: sd a0, 8(sp) -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: add sp, sp, a0 -; CHECK-NEXT: addi sp, sp, 16 -; CHECK-NEXT: ret +; NOZBA-LABEL: gpr_and_lmul1_and_2: +; NOZBA: # %bb.0: +; NOZBA-NEXT: addi sp, sp, -16 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: li a0, 3 +; NOZBA-NEXT: sd a0, 8(sp) +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: add sp, sp, a0 +; NOZBA-NEXT: addi sp, sp, 16 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: gpr_and_lmul1_and_2: +; ZBA: # %bb.0: +; ZBA-NEXT: addi sp, sp, -16 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 2 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: li a0, 3 +; ZBA-NEXT: sd a0, 8(sp) +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: sh2add sp, a0, sp +; ZBA-NEXT: addi sp, sp, 16 +; ZBA-NEXT: ret +; +; NOMUL-LABEL: gpr_and_lmul1_and_2: +; NOMUL: # %bb.0: +; NOMUL-NEXT: addi sp, sp, -16 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: li a0, 3 +; NOMUL-NEXT: sd a0, 8(sp) +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: add sp, sp, a0 +; NOMUL-NEXT: addi sp, sp, 16 +; NOMUL-NEXT: ret %x1 = alloca i64 %v1 = alloca %v2 = alloca @@ -396,15 +499,34 @@ define void @lmul_1_2_4_8_x2_1() nounwind { } define void @masks() nounwind { -; CHECK-LABEL: masks: -; CHECK: # %bb.0: -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: sub sp, sp, a0 -; CHECK-NEXT: csrr a0, vlenb -; CHECK-NEXT: slli a0, a0, 2 -; CHECK-NEXT: add sp, sp, a0 -; CHECK-NEXT: ret +; NOZBA-LABEL: masks: +; NOZBA: # %bb.0: +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: slli a0, a0, 2 +; NOZBA-NEXT: add sp, sp, a0 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: masks: +; ZBA: # %bb.0: +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 2 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: sh2add sp, a0, sp +; ZBA-NEXT: ret +; +; NOMUL-LABEL: masks: +; NOMUL: # %bb.0: +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 2 +; NOMUL-NEXT: add sp, sp, a0 +; NOMUL-NEXT: ret %v1 = alloca %v2 = alloca %v4 = alloca -- GitLab From 5278594d7ef8c6814578f2f600016fef5ad058c9 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Tue, 9 Apr 2024 10:38:54 -0400 Subject: [PATCH 284/695] Add a diagnostic group for tentative array definitions This diagnostic is one of the ones that GCC also does not have a warning group for, but a user requested adding a group to control selectively turning off this diagnostic. So this adds the diagnostic to a new group, -Wtentative-definition-array Fixes #87766 --- clang/docs/ReleaseNotes.rst | 5 +++++ clang/include/clang/Basic/DiagnosticSemaKinds.td | 3 ++- clang/test/Misc/warning-flags.c | 3 +-- clang/test/Sema/tentative-array-decl.c | 5 +++++ 4 files changed, 13 insertions(+), 3 deletions(-) create mode 100644 clang/test/Sema/tentative-array-decl.c diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 9349cc788e5f..f96cebbde3d8 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -352,6 +352,11 @@ Improvements to Clang's diagnostics (with initializer) entirely consist the condition expression of a if/while/for construct but are not actually used in the body of the if/while/for construct. Fixes #GH41447 +- Clang emits a diagnostic when a tentative array definition is assumed to have + a single element, but that diagnostic was never given a diagnostic group. + Added the ``-Wtentative-definition-array`` warning group to cover this. + Fixes #GH87766 + Improvements to Clang's time-trace ---------------------------------- diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 4fbbc42273ba..1c068f6cdb42 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -7142,7 +7142,8 @@ def ext_typecheck_decl_incomplete_type : ExtWarn< def err_tentative_def_incomplete_type : Error< "tentative definition has type %0 that is never completed">; def warn_tentative_incomplete_array : Warning< - "tentative array definition assumed to have one element">; + "tentative array definition assumed to have one element">, + InGroup>; def err_typecheck_incomplete_array_needs_initializer : Error< "definition of variable with array type needs an explicit size " "or an initializer">; diff --git a/clang/test/Misc/warning-flags.c b/clang/test/Misc/warning-flags.c index bb3c7d816d2f..dd73331913c6 100644 --- a/clang/test/Misc/warning-flags.c +++ b/clang/test/Misc/warning-flags.c @@ -18,7 +18,7 @@ This test serves two purposes: The list of warnings below should NEVER grow. It should gradually shrink to 0. -CHECK: Warnings without flags (67): +CHECK: Warnings without flags (66): CHECK-NEXT: ext_expected_semi_decl_list CHECK-NEXT: ext_explicit_specialization_storage_class @@ -80,7 +80,6 @@ CHECK-NEXT: warn_register_objc_catch_parm CHECK-NEXT: warn_related_result_type_compatibility_class CHECK-NEXT: warn_related_result_type_compatibility_protocol CHECK-NEXT: warn_template_export_unsupported -CHECK-NEXT: warn_tentative_incomplete_array CHECK-NEXT: warn_typecheck_function_qualifiers CHECK-NEXT: warn_undef_interface CHECK-NEXT: warn_undef_interface_suggest diff --git a/clang/test/Sema/tentative-array-decl.c b/clang/test/Sema/tentative-array-decl.c new file mode 100644 index 000000000000..77ede14c0be2 --- /dev/null +++ b/clang/test/Sema/tentative-array-decl.c @@ -0,0 +1,5 @@ +// RUN: %clang_cc1 -verify %s +// RUN: %clang_cc1 -verify=good -Wno-tentative-definition-array %s +// good-no-diagnostics + +int foo[]; // expected-warning {{tentative array definition assumed to have one element}} -- GitLab From 3bfd5c64240c1a812c596dd2bcd480b7607155de Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 9 Apr 2024 15:42:51 +0100 Subject: [PATCH 285/695] [TTI] getCommonMaskedMemoryOpCost - consistently use getScalarizationOverhead instead of ExtractElement costs for address/mask extraction. (#87771) These aren't unknown extraction indices, we will be extracting every address/mask element in sequence. --- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 28 +- .../Analysis/CostModel/AArch64/masked_ldst.ll | 36 +- .../CostModel/AArch64/mem-op-cost-model.ll | 48 +- .../Analysis/CostModel/AArch64/sve-gather.ll | 6 +- .../CostModel/AArch64/sve-intrinsics.ll | 8 +- .../CostModel/RISCV/fixed-vector-gather.ll | 12 +- .../CostModel/RISCV/fixed-vector-scatter.ll | 12 +- .../Analysis/CostModel/RISCV/masked_ldst.ll | 8 +- .../CostModel/RISCV/rvv-intrinsics.ll | 16 +- .../CostModel/X86/intrinsic-cost-kinds.ll | 12 +- .../X86/masked-intrinsic-codesize.ll | 606 ++++++++++-------- .../CostModel/X86/masked-intrinsic-latency.ll | 606 ++++++++++-------- .../X86/masked-intrinsic-sizelatency.ll | 606 ++++++++++-------- .../LoopVectorize/AArch64/masked-op-cost.ll | 4 +- 14 files changed, 1084 insertions(+), 924 deletions(-) diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index 42d8f74fd427..2a5638dd1d3c 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -224,16 +224,16 @@ private: // First, compute the cost of the individual memory operations. InstructionCost AddrExtractCost = IsGatherScatter - ? getVectorInstrCost( - Instruction::ExtractElement, + ? getScalarizationOverhead( FixedVectorType::get( PointerType::get(VT->getElementType(), 0), VF), - CostKind, -1, nullptr, nullptr) + /*Insert=*/false, /*Extract=*/true, CostKind) : 0; - InstructionCost LoadCost = - VF * - (AddrExtractCost + getMemoryOpCost(Opcode, VT->getElementType(), - Alignment, AddressSpace, CostKind)); + + // The cost of the scalar loads/stores. + InstructionCost MemoryOpCost = + VF * getMemoryOpCost(Opcode, VT->getElementType(), Alignment, + AddressSpace, CostKind); // Next, compute the cost of packing the result in a vector. InstructionCost PackingCost = @@ -249,16 +249,14 @@ private: // operations accurately is quite difficult and the current solution // provides a very rough estimate only. ConditionalCost = - VF * - (getVectorInstrCost( - Instruction::ExtractElement, - FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), VF), - CostKind, -1, nullptr, nullptr) + - getCFInstrCost(Instruction::Br, CostKind) + - getCFInstrCost(Instruction::PHI, CostKind)); + getScalarizationOverhead( + FixedVectorType::get(Type::getInt1Ty(DataTy->getContext()), VF), + /*Insert=*/false, /*Extract=*/true, CostKind) + + VF * (getCFInstrCost(Instruction::Br, CostKind) + + getCFInstrCost(Instruction::PHI, CostKind)); } - return LoadCost + PackingCost + ConditionalCost; + return AddrExtractCost + MemoryOpCost + PackingCost + ConditionalCost; } protected: diff --git a/llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll b/llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll index 652d36c01a77..f5ca6a22b60a 100644 --- a/llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll +++ b/llvm/test/Analysis/CostModel/AArch64/masked_ldst.ll @@ -5,24 +5,24 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" define void @fixed() { ; CHECK-LABEL: 'fixed' -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2i8 = call <2 x i8> @llvm.masked.load.v2i8.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i8> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i8 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i8> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i8 = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr undef, i32 8, <8 x i1> undef, <8 x i8> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %v16i8 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr undef, i32 8, <16 x i1> undef, <16 x i8> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2i16 = call <2 x i16> @llvm.masked.load.v2i16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i16> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i16 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i16> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v8i16 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x i16> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2i32 = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i32> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i32 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i32> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2i64 = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f16 = call <2 x half> @llvm.masked.load.v2f16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %v4f16 = call <4 x half> @llvm.masked.load.v4f16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %v8f16 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f32 = call <2 x float> @llvm.masked.load.v2f32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %v4f32 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %v2f64 = call <2 x double> @llvm.masked.load.v2f64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v4i64 = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 184 for instruction: %v32f16 = call <32 x half> @llvm.masked.load.v32f16.p0(ptr undef, i32 8, <32 x i1> undef, <32 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v2i8 = call <2 x i8> @llvm.masked.load.v2i8.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i8> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v4i8 = call <4 x i8> @llvm.masked.load.v4i8.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i8> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v8i8 = call <8 x i8> @llvm.masked.load.v8i8.p0(ptr undef, i32 8, <8 x i1> undef, <8 x i8> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v16i8 = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr undef, i32 8, <16 x i1> undef, <16 x i8> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v2i16 = call <2 x i16> @llvm.masked.load.v2i16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i16> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v4i16 = call <4 x i16> @llvm.masked.load.v4i16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i16> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v8i16 = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x i16> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v2i32 = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i32> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v4i32 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i32> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v2i64 = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i64> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2f16 = call <2 x half> @llvm.masked.load.v2f16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v4f16 = call <4 x half> @llvm.masked.load.v4f16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %v8f16 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2f32 = call <2 x float> @llvm.masked.load.v2f32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v4f32 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v2f64 = call <2 x double> @llvm.masked.load.v2f64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v4i64 = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i64> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %v32f16 = call <32 x half> @llvm.masked.load.v32f16.p0(ptr undef, i32 8, <32 x i1> undef, <32 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; entry: diff --git a/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll b/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll index bf8458ba56e8..521a0900c844 100644 --- a/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll +++ b/llvm/test/Analysis/CostModel/AArch64/mem-op-cost-model.ll @@ -190,11 +190,11 @@ declare <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr>, i32 immarg, <4 x i1>, define <4 x i8> @gather_load_4xi8_constant_mask(<4 x ptr> %ptrs) { ; CHECK: gather_load_4xi8_constant_mask ; CHECK-NEON-LABEL: 'gather_load_4xi8_constant_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i8> undef) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i8> undef) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %lv ; ; CHECK-SVE-128-LABEL: 'gather_load_4xi8_constant_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i8> undef) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i8> undef) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %lv ; ; CHECK-SVE-256-LABEL: 'gather_load_4xi8_constant_mask' @@ -212,11 +212,11 @@ define <4 x i8> @gather_load_4xi8_constant_mask(<4 x ptr> %ptrs) { define <4 x i8> @gather_load_4xi8_variable_mask(<4 x ptr> %ptrs, <4 x i1> %cond) { ; CHECK: gather_load_4xi8_variable_mask ; CHECK-NEON-LABEL: 'gather_load_4xi8_variable_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i8> undef) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i8> undef) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %lv ; ; CHECK-SVE-128-LABEL: 'gather_load_4xi8_variable_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i8> undef) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %lv = call <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i8> undef) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i8> %lv ; ; CHECK-SVE-256-LABEL: 'gather_load_4xi8_variable_mask' @@ -235,11 +235,11 @@ declare void @llvm.masked.scatter.v4i8.v4p0(<4 x i8>, <4 x ptr>, i32 immarg, <4 define void @scatter_store_4xi8_constant_mask(<4 x i8> %val, <4 x ptr> %ptrs) { ; CHECK: scatter_store_4xi8_constant_mask ; CHECK-NEON-LABEL: 'scatter_store_4xi8_constant_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'scatter_store_4xi8_constant_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'scatter_store_4xi8_constant_mask' @@ -257,11 +257,11 @@ define void @scatter_store_4xi8_constant_mask(<4 x i8> %val, <4 x ptr> %ptrs) { define void @scatter_store_4xi8_variable_mask(<4 x i8> %val, <4 x ptr> %ptrs, <4 x i1> %cond) { ; CHECK: scatter_store_4xi8_variable_mask ; CHECK-NEON-LABEL: 'scatter_store_4xi8_variable_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'scatter_store_4xi8_variable_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v4i8.v4p0(<4 x i8> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'scatter_store_4xi8_variable_mask' @@ -280,11 +280,11 @@ declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32 immarg, <4 x i1> define <4 x i32> @gather_load_4xi32_constant_mask(<4 x ptr> %ptrs) { ; CHECK: gather_load_4xi32_constant_mask ; CHECK-NEON-LABEL: 'gather_load_4xi32_constant_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i32> undef) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i32> undef) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %lv ; ; CHECK-SVE-128-LABEL: 'gather_load_4xi32_constant_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i32> undef) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> , <4 x i32> undef) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %lv ; ; CHECK-SVE-256-LABEL: 'gather_load_4xi32_constant_mask' @@ -302,11 +302,11 @@ define <4 x i32> @gather_load_4xi32_constant_mask(<4 x ptr> %ptrs) { define <4 x i32> @gather_load_4xi32_variable_mask(<4 x ptr> %ptrs, <4 x i1> %cond) { ; CHECK: gather_load_4xi32_variable_mask ; CHECK-NEON-LABEL: 'gather_load_4xi32_variable_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i32> undef) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i32> undef) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %lv ; ; CHECK-SVE-128-LABEL: 'gather_load_4xi32_variable_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i32> undef) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %lv = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 1, <4 x i1> %cond, <4 x i32> undef) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %lv ; ; CHECK-SVE-256-LABEL: 'gather_load_4xi32_variable_mask' @@ -325,11 +325,11 @@ declare void @llvm.masked.scatter.v4i32.v4p0(<4 x i32>, <4 x ptr>, i32 immarg, < define void @scatter_store_4xi32_constant_mask(<4 x i32> %val, <4 x ptr> %ptrs) { ; CHECK: scatter_store_4xi32_constant_mask ; CHECK-NEON-LABEL: 'scatter_store_4xi32_constant_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'scatter_store_4xi32_constant_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> ) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'scatter_store_4xi32_constant_mask' @@ -347,11 +347,11 @@ define void @scatter_store_4xi32_constant_mask(<4 x i32> %val, <4 x ptr> %ptrs) define void @scatter_store_4xi32_variable_mask(<4 x i32> %val, <4 x ptr> %ptrs, <4 x i1> %cond) { ; CHECK: scatter_store_4xi32_variable_mask ; CHECK-NEON-LABEL: 'scatter_store_4xi32_variable_mask' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'scatter_store_4xi32_variable_mask' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %val, <4 x ptr> %ptrs, i32 1, <4 x i1> %cond) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'scatter_store_4xi32_variable_mask' @@ -370,11 +370,11 @@ declare <256 x i16> @llvm.masked.gather.v256i16.v256p0(<256 x ptr>, i32, <256 x define void @sve_gather_vls(<256 x i1> %v256i1mask) { ; CHECK-LABEL: 'sve_scatter_vls' ; CHECK-NEON-LABEL: 'sve_gather_vls' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %res.v256i16 = call <256 x i16> @llvm.masked.gather.v256i16.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x i16> zeroinitializer) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2304 for instruction: %res.v256i16 = call <256 x i16> @llvm.masked.gather.v256i16.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x i16> zeroinitializer) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'sve_gather_vls' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: %res.v256i16 = call <256 x i16> @llvm.masked.gather.v256i16.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x i16> zeroinitializer) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 2304 for instruction: %res.v256i16 = call <256 x i16> @llvm.masked.gather.v256i16.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x i16> zeroinitializer) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'sve_gather_vls' @@ -394,11 +394,11 @@ declare <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr>, i32, <256 define void @sve_gather_vls_float(<256 x i1> %v256i1mask) { ; CHECK-LABEL: 'sve_gather_vls_float' ; CHECK-NEON-LABEL: 'sve_gather_vls_float' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1664 for instruction: %res.v256f32 = call <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x float> zeroinitializer) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2176 for instruction: %res.v256f32 = call <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x float> zeroinitializer) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'sve_gather_vls_float' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 1664 for instruction: %res.v256f32 = call <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x float> zeroinitializer) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 2176 for instruction: %res.v256f32 = call <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> undef, i32 0, <256 x i1> %v256i1mask, <256 x float> zeroinitializer) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'sve_gather_vls_float' @@ -418,11 +418,11 @@ declare void @llvm.masked.scatter.v256i8.v256p0(<256 x i8>, <256 x ptr>, i32, <2 define void @sve_scatter_vls(<256 x i1> %v256i1mask){ ; CHECK-LABEL: 'sve_scatter_vls' ; CHECK-NEON-LABEL: 'sve_scatter_vls' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: call void @llvm.masked.scatter.v256i8.v256p0(<256 x i8> undef, <256 x ptr> undef, i32 0, <256 x i1> %v256i1mask) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 2304 for instruction: call void @llvm.masked.scatter.v256i8.v256p0(<256 x i8> undef, <256 x ptr> undef, i32 0, <256 x i1> %v256i1mask) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'sve_scatter_vls' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 1792 for instruction: call void @llvm.masked.scatter.v256i8.v256p0(<256 x i8> undef, <256 x ptr> undef, i32 0, <256 x i1> %v256i1mask) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 2304 for instruction: call void @llvm.masked.scatter.v256i8.v256p0(<256 x i8> undef, <256 x ptr> undef, i32 0, <256 x i1> %v256i1mask) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'sve_scatter_vls' @@ -442,11 +442,11 @@ declare void @llvm.masked.scatter.v512f16.v512p0(<512 x half>, <512 x ptr>, i32, define void @sve_scatter_vls_float(<512 x i1> %v512i1mask){ ; CHECK-LABEL: 'sve_scatter_vls_float' ; CHECK-NEON-LABEL: 'sve_scatter_vls_float' -; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 3456 for instruction: call void @llvm.masked.scatter.v512f16.v512p0(<512 x half> undef, <512 x ptr> undef, i32 0, <512 x i1> %v512i1mask) +; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 4480 for instruction: call void @llvm.masked.scatter.v512f16.v512p0(<512 x half> undef, <512 x ptr> undef, i32 0, <512 x i1> %v512i1mask) ; CHECK-NEON-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-128-LABEL: 'sve_scatter_vls_float' -; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 3456 for instruction: call void @llvm.masked.scatter.v512f16.v512p0(<512 x half> undef, <512 x ptr> undef, i32 0, <512 x i1> %v512i1mask) +; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 4480 for instruction: call void @llvm.masked.scatter.v512f16.v512p0(<512 x half> undef, <512 x ptr> undef, i32 0, <512 x i1> %v512i1mask) ; CHECK-SVE-128-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; CHECK-SVE-256-LABEL: 'sve_scatter_vls_float' diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll b/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll index c05339d89d35..a9c18e20c1f5 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-gather.ll @@ -107,15 +107,15 @@ define void @masked_gathers_no_vscale_range() #2 { define <2 x i128> @masked_gather_v1i128(<2 x ptr> %ld, <2 x i1> %masks, <2 x i128> %passthru) #3 { ; CHECK-LABEL: 'masked_gather_v1i128' -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i128> %res ; ; CHECK-VSCALE-2-LABEL: 'masked_gather_v1i128' -; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) +; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i128> %res ; ; CHECK-VSCALE-1-LABEL: 'masked_gather_v1i128' -; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) +; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) ; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i128> %res ; %res = call <2 x i128> @llvm.masked.gather.v2i128.v2p0(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x i128> %passthru) diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll index 937c383aedc7..8d5535e2a82f 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll @@ -829,7 +829,7 @@ define @masked_gather_nxv8i32( %ld, @masked_gather_v4i32(<4 x ptr> %ld, <4 x i1> %masks, <4 x i32> %passthru) { ; CHECK-LABEL: 'masked_gather_v4i32' -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ld, i32 0, <4 x i1> %masks, <4 x i32> %passthru) +; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ld, i32 0, <4 x i1> %masks, <4 x i32> %passthru) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res ; ; TYPE_BASED_ONLY-LABEL: 'masked_gather_v4i32' @@ -842,7 +842,7 @@ define <4 x i32> @masked_gather_v4i32(<4 x ptr> %ld, <4 x i1> %masks, <4 x i32> define <1 x i128> @masked_gather_v1i128(<1 x ptr> %ld, <1 x i1> %masks, <1 x i128> %passthru) { ; CHECK-LABEL: 'masked_gather_v1i128' -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <1 x i128> @llvm.masked.gather.v1i128.v1p0(<1 x ptr> %ld, i32 0, <1 x i1> %masks, <1 x i128> %passthru) +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %res = call <1 x i128> @llvm.masked.gather.v1i128.v1p0(<1 x ptr> %ld, i32 0, <1 x i1> %masks, <1 x i128> %passthru) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <1 x i128> %res ; ; TYPE_BASED_ONLY-LABEL: 'masked_gather_v1i128' @@ -883,7 +883,7 @@ define void @masked_scatter_nxv8i32( %data, define void @masked_scatter_v4i32(<4 x i32> %data, <4 x ptr> %ptrs, <4 x i1> %masks) { ; CHECK-LABEL: 'masked_scatter_v4i32' -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %data, <4 x ptr> %ptrs, i32 0, <4 x i1> %masks) +; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %data, <4 x ptr> %ptrs, i32 0, <4 x i1> %masks) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; TYPE_BASED_ONLY-LABEL: 'masked_scatter_v4i32' @@ -897,7 +897,7 @@ define void @masked_scatter_v4i32(<4 x i32> %data, <4 x ptr> %ptrs, <4 x i1> %ma define void @masked_scatter_v1i128(<1 x i128> %data, <1 x ptr> %ptrs, <1 x i1> %masks) { ; CHECK-LABEL: 'masked_scatter_v1i128' -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v1i128.v1p0(<1 x i128> %data, <1 x ptr> %ptrs, i32 0, <1 x i1> %masks) +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v1i128.v1p0(<1 x i128> %data, <1 x ptr> %ptrs, i32 0, <1 x i1> %masks) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; TYPE_BASED_ONLY-LABEL: 'masked_scatter_v1i128' diff --git a/llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll b/llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll index 510d33b8d903..ec7eb81d98bf 100644 --- a/llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll +++ b/llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll @@ -44,33 +44,33 @@ define i32 @masked_gather() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1I8 = call <1 x i8> @llvm.masked.gather.v1i8.v1p0(<1 x ptr> undef, i32 1, <1 x i1> undef, <1 x i8> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64.u = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 2, <8 x i1> undef, <8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64.u = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 2, <4 x i1> undef, <4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2F64.u = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 2, <2 x i1> undef, <2 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64.u = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 2, <2 x i1> undef, <2 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64.u = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 2, <1 x i1> undef, <1 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32.u = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 2, <16 x i1> undef, <16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F32.u = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 2, <8 x i1> undef, <8 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F32.u = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 2, <4 x i1> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2F32.u = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 2, <2 x i1> undef, <2 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32.u = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 2, <2 x i1> undef, <2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F32.u = call <1 x float> @llvm.masked.gather.v1f32.v1p0(<1 x ptr> undef, i32 2, <1 x i1> undef, <1 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32F16.u = call <32 x half> @llvm.masked.gather.v32f16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> undef, <32 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F16.u = call <16 x half> @llvm.masked.gather.v16f16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> undef, <16 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F16.u = call <8 x half> @llvm.masked.gather.v8f16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> undef, <8 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F16.u = call <4 x half> @llvm.masked.gather.v4f16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> undef, <4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2F16.u = call <2 x half> @llvm.masked.gather.v2f16.v2p0(<2 x ptr> undef, i32 1, <2 x i1> undef, <2 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F16.u = call <2 x half> @llvm.masked.gather.v2f16.v2p0(<2 x ptr> undef, i32 1, <2 x i1> undef, <2 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F16.u = call <1 x half> @llvm.masked.gather.v1f16.v1p0(<1 x ptr> undef, i32 1, <1 x i1> undef, <1 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8I64.u = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 4, <8 x i1> undef, <8 x i64> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4I64.u = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 4, <4 x i1> undef, <4 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I64.u = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 4, <2 x i1> undef, <2 x i64> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2I64.u = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 4, <2 x i1> undef, <2 x i64> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64.u = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 4, <1 x i1> undef, <1 x i64> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16I32.u = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> undef, <16 x i32> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8I32.u = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> undef, <8 x i32> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4I32.u = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> undef, <4 x i32> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I32.u = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> undef, <2 x i32> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2I32.u = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> undef, <2 x i32> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I32.u = call <1 x i32> @llvm.masked.gather.v1i32.v1p0(<1 x ptr> undef, i32 1, <1 x i1> undef, <1 x i32> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32I16.u = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> undef, <32 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16I16.u = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> undef, <16 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8I16.u = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> undef, <8 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4I16.u = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> undef, <4 x i16> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2I16.u = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> undef, i32 1, <2 x i1> undef, <2 x i16> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2I16.u = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> undef, i32 1, <2 x i1> undef, <2 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I16.u = call <1 x i16> @llvm.masked.gather.v1i16.v1p0(<1 x ptr> undef, i32 1, <1 x i1> undef, <1 x i16> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 0 ; diff --git a/llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll b/llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll index caa5138287f2..6da9d8d73cbd 100644 --- a/llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll +++ b/llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll @@ -44,33 +44,33 @@ define i32 @masked_scatter() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1i8.v1p0(<1 x i8> undef, <1 x ptr> undef, i32 1, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 2, <8 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 2, <4 x i1> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 2, <2 x i1> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 2, <2 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 2, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 2, <16 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 2, <8 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 2, <4 x i1> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 2, <2 x i1> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 2, <2 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f32.v1p0(<1 x float> undef, <1 x ptr> undef, i32 2, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: call void @llvm.masked.scatter.v32f16.v32p0(<32 x half> undef, <32 x ptr> undef, i32 1, <32 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v16f16.v16p0(<16 x half> undef, <16 x ptr> undef, i32 1, <16 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: call void @llvm.masked.scatter.v8f16.v8p0(<8 x half> undef, <8 x ptr> undef, i32 1, <8 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4f16.v4p0(<4 x half> undef, <4 x ptr> undef, i32 1, <4 x i1> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v2f16.v2p0(<2 x half> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f16.v2p0(<2 x half> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f16.v1p0(<1 x half> undef, <1 x ptr> undef, i32 1, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i32.v1p0(<1 x i32> undef, <1 x ptr> undef, i32 1, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v2i16.v2p0(<2 x i16> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2i16.v2p0(<2 x i16> undef, <2 x ptr> undef, i32 1, <2 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i16.v1p0(<1 x i16> undef, <1 x ptr> undef, i32 1, <1 x i1> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 0 ; diff --git a/llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll b/llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll index 387e6e43bb34..31bbc8b02a19 100644 --- a/llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll +++ b/llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll @@ -13,14 +13,14 @@ define void @fixed() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32 = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i32> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i32> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64 = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v2f16 = call <2 x half> @llvm.masked.load.v2f16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v4f16 = call <4 x half> @llvm.masked.load.v4f16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v8f16 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %v2f16 = call <2 x half> @llvm.masked.load.v2f16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v4f16 = call <4 x half> @llvm.masked.load.v4f16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 55 for instruction: %v8f16 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = call <2 x float> @llvm.masked.load.v2f32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f32 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64 = call <2 x double> @llvm.masked.load.v2f64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %v32f16 = call <32 x half> @llvm.masked.load.v32f16.p0(ptr undef, i32 8, <32 x i1> undef, <32 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 287 for instruction: %v32f16 = call <32 x half> @llvm.masked.load.v32f16.p0(ptr undef, i32 8, <32 x i1> undef, <32 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; entry: diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll index f308c535d158..a23ea00dbaa7 100644 --- a/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll @@ -500,10 +500,10 @@ define void @strided_load() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t10.a = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i64(ptr align 8 undef, i64 undef, <4 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t13.a = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64.p0.i64(ptr align 8 undef, i64 undef, <8 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %t15.a = call <16 x i64> @llvm.experimental.vp.strided.load.v16i64.p0.i64(ptr align 8 undef, i64 undef, <16 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %t8 = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i64(ptr undef, i64 undef, <2 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %t10 = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i64(ptr undef, i64 undef, <4 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %t13 = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64.p0.i64(ptr undef, i64 undef, <8 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %t15 = call <16 x i64> @llvm.experimental.vp.strided.load.v16i64.p0.i64(ptr undef, i64 undef, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t8 = call <2 x i64> @llvm.experimental.vp.strided.load.v2i64.p0.i64(ptr undef, i64 undef, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %t10 = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i64(ptr undef, i64 undef, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %t13 = call <8 x i64> @llvm.experimental.vp.strided.load.v8i64.p0.i64(ptr undef, i64 undef, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %t15 = call <16 x i64> @llvm.experimental.vp.strided.load.v16i64.p0.i64(ptr undef, i64 undef, <16 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %t17 = call @llvm.experimental.vp.strided.load.nxv2i8.p0.i64(ptr undef, i64 undef, undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %t19 = call @llvm.experimental.vp.strided.load.nxv4i8.p0.i64(ptr undef, i64 undef, undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %t21 = call @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr undef, i64 undef, undef, i32 undef) @@ -543,10 +543,10 @@ define void @strided_store() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.experimental.vp.strided.store.v4i8.p0.i64(<4 x i8> undef, ptr undef, i64 undef, <4 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.experimental.vp.strided.store.v8i8.p0.i64(<8 x i8> undef, ptr undef, i64 undef, <8 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.experimental.vp.strided.store.v16i8.p0.i64(<16 x i8> undef, ptr undef, i64 undef, <16 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.experimental.vp.strided.store.v2i64.p0.i64(<2 x i64> undef, ptr undef, i64 undef, <2 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.experimental.vp.strided.store.v4i64.p0.i64(<4 x i64> undef, ptr undef, i64 undef, <4 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: call void @llvm.experimental.vp.strided.store.v8i64.p0.i64(<8 x i64> undef, ptr undef, i64 undef, <8 x i1> undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 63 for instruction: call void @llvm.experimental.vp.strided.store.v16i64.p0.i64(<16 x i64> undef, ptr undef, i64 undef, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.experimental.vp.strided.store.v2i64.p0.i64(<2 x i64> undef, ptr undef, i64 undef, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.experimental.vp.strided.store.v4i64.p0.i64(<4 x i64> undef, ptr undef, i64 undef, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.experimental.vp.strided.store.v8i64.p0.i64(<8 x i64> undef, ptr undef, i64 undef, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 78 for instruction: call void @llvm.experimental.vp.strided.store.v16i64.p0.i64(<16 x i64> undef, ptr undef, i64 undef, <16 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.experimental.vp.strided.store.v2i64.p0.i64(<2 x i64> undef, ptr align 8 undef, i64 undef, <2 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.experimental.vp.strided.store.v4i64.p0.i64(<4 x i64> undef, ptr align 8 undef, i64 undef, <4 x i1> undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.experimental.vp.strided.store.v8i64.p0.i64(<8 x i64> undef, ptr align 8 undef, i64 undef, <8 x i1> undef, i32 undef) diff --git a/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll b/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll index 10786e1f7a4a..cda9744a8d6b 100644 --- a/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll +++ b/llvm/test/Analysis/CostModel/X86/intrinsic-cost-kinds.ll @@ -314,15 +314,15 @@ define void @maskedgather(<16 x ptr> %va, <16 x i1> %vb, <16 x float> %vc) { ; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; LATE-LABEL: 'maskedgather' -; LATE-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) +; LATE-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'maskedgather' -; SIZE-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) +; SIZE-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'maskedgather' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %v = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %va, i32 1, <16 x i1> %vb, <16 x float> %vc) @@ -335,15 +335,15 @@ define void @maskedscatter(<16 x float> %va, <16 x ptr> %vb, <16 x i1> %vc) { ; THRU-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; LATE-LABEL: 'maskedscatter' -; LATE-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) +; LATE-NEXT: Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) ; LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE-LABEL: 'maskedscatter' -; SIZE-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) +; SIZE-NEXT: Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SIZE_LATE-LABEL: 'maskedscatter' -; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) +; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) ; SIZE_LATE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> %va, <16 x ptr> %vb, i32 1, <16 x i1> %vc) diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll index d97c3d550efd..827e503fe7b1 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-codesize.ll @@ -732,118 +732,118 @@ define i32 @masked_store(<1 x i1> %m1, <2 x i1> %m2, <3 x i1> %m3, <4 x i1> %m4, define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8, <16 x i1> %m16, <32 x i1> %m32, <64 x i1> %m64) { ; SSE2-LABEL: 'masked_gather' -; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 380 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SSE42-LABEL: 'masked_gather' -; SSE42-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; AVX1-LABEL: 'masked_gather' -; AVX1-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 278 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; AVX2-LABEL: 'masked_gather' -; AVX2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 276 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 138 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKL-LABEL: 'masked_gather' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) @@ -851,53 +851,53 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 276 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 138 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_gather' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 163 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 323 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 347 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 173 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 86 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_gather' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) @@ -905,19 +905,19 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 163 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 323 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 347 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 173 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 86 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) @@ -955,118 +955,172 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8, <16 x i1> %m16, <32 x i1> %m32, <64 x i1> %m64) { ; SSE2-LABEL: 'masked_scatter' -; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 380 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SSE2-NEXT: Cost Model: Found an estimated cost of 190 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE2-NEXT: Cost Model: Found an estimated cost of 95 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 384 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SSE2-NEXT: Cost Model: Found an estimated cost of 192 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE2-NEXT: Cost Model: Found an estimated cost of 96 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SSE42-LABEL: 'masked_scatter' -; SSE42-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 320 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 31 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 260 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; -; AVX-LABEL: 'masked_scatter' -; AVX-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; AVX-NEXT: Cost Model: Found an estimated cost of 78 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 42 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; AVX-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 162 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; AVX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 322 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; AVX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; AVX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; AVX1-LABEL: 'masked_scatter' +; AVX1-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 140 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX1-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 278 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; AVX1-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX1-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; +; AVX2-LABEL: 'masked_scatter' +; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX2-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 276 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; AVX2-NEXT: Cost Model: Found an estimated cost of 138 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX2-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; +; SKL-LABEL: 'masked_scatter' +; SKL-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKL-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKL-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 276 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SKL-NEXT: Cost Model: Found an estimated cost of 138 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKL-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_scatter' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 163 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; KNL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; KNL-NEXT: Cost Model: Found an estimated cost of 323 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; KNL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; KNL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; KNL-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 347 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; KNL-NEXT: Cost Model: Found an estimated cost of 173 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; KNL-NEXT: Cost Model: Found an estimated cost of 86 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_scatter' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) @@ -1074,19 +1128,19 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 163 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SKX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SKX-NEXT: Cost Model: Found an estimated cost of 323 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SKX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SKX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 347 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SKX-NEXT: Cost Model: Found an estimated cost of 173 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKX-NEXT: Cost Model: Found an estimated cost of 86 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) @@ -1734,19 +1788,19 @@ define <2 x i32> @test8(<2 x i32> %trigger, ptr %addr, <2 x i32> %dst) { define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x double> %src0) { ; SSE2-LABEL: 'test_gather_2f64' -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SSE42-LABEL: 'test_gather_2f64' -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX1-LABEL: 'test_gather_2f64' -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX2-LABEL: 'test_gather_2f64' -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SKL-LABEL: 'test_gather_2f64' @@ -1763,19 +1817,19 @@ define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x doub define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %src0) { ; SSE2-LABEL: 'test_gather_4i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SSE42-LABEL: 'test_gather_4i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX1-LABEL: 'test_gather_4i32' -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX2-LABEL: 'test_gather_4i32' -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32' @@ -1783,7 +1837,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32' -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32' @@ -1796,7 +1850,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) { ; SSE2-LABEL: 'test_gather_4i32_const_mask' -; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SSE42-LABEL: 'test_gather_4i32_const_mask' @@ -1804,11 +1858,11 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX1-LABEL: 'test_gather_4i32_const_mask' -; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX2-LABEL: 'test_gather_4i32_const_mask' -; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32_const_mask' @@ -1816,7 +1870,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32_const_mask' -; KNL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; KNL-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32_const_mask' @@ -1831,7 +1885,7 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_const_mask' @@ -1843,13 +1897,13 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; AVX1-LABEL: 'test_gather_16f32_const_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_const_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_const_mask' @@ -1875,25 +1929,25 @@ define <16 x float> @test_gather_16f32_var_mask(ptr %base, <16 x i32> %ind, <16 ; SSE2-LABEL: 'test_gather_16f32_var_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_var_mask' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX1-LABEL: 'test_gather_16f32_var_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_var_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_var_mask' @@ -1919,25 +1973,25 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> ; SSE2-LABEL: 'test_gather_16f32_ra_var_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_ra_var_mask' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX1-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_ra_var_mask' @@ -1965,7 +2019,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_const_mask2' @@ -1981,7 +2035,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_const_mask2' @@ -1989,7 +2043,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_const_mask2' @@ -2024,7 +2078,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_16i32' @@ -2032,7 +2086,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX1-LABEL: 'test_scatter_16i32' @@ -2040,7 +2094,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX1-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX2-LABEL: 'test_scatter_16i32' @@ -2048,7 +2102,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX2-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKL-LABEL: 'test_scatter_16i32' @@ -2056,7 +2110,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SKL-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SKL-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_16i32' @@ -2078,15 +2132,15 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { ; SSE2-LABEL: 'test_scatter_8i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_8i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX-LABEL: 'test_scatter_8i32' -; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; AVX-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_8i32' @@ -2099,19 +2153,19 @@ define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { define void @test_scatter_4i32(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; SSE2-LABEL: 'test_scatter_4i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_4i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX-LABEL: 'test_scatter_4i32' -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; AVX-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; KNL-LABEL: 'test_scatter_4i32' -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKX-LABEL: 'test_scatter_4i32' @@ -2126,25 +2180,25 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SSE2-LABEL: 'test_gather_4f32' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SSE42-LABEL: 'test_gather_4f32' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX1-LABEL: 'test_gather_4f32' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX2-LABEL: 'test_gather_4f32' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKL-LABEL: 'test_gather_4f32' @@ -2156,7 +2210,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; KNL-LABEL: 'test_gather_4f32' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; KNL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKX-LABEL: 'test_gather_4f32' @@ -2176,7 +2230,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SSE2-LABEL: 'test_gather_4f32_const_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SSE42-LABEL: 'test_gather_4f32_const_mask' @@ -2188,13 +2242,13 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; AVX1-LABEL: 'test_gather_4f32_const_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX2-LABEL: 'test_gather_4f32_const_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKL-LABEL: 'test_gather_4f32_const_mask' @@ -2206,7 +2260,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; KNL-LABEL: 'test_gather_4f32_const_mask' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; KNL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; KNL-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKX-LABEL: 'test_gather_4f32_const_mask' diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll index 416005b4f5f4..8ca572ada8b7 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-latency.ll @@ -732,118 +732,118 @@ define i32 @masked_store(<1 x i1> %m1, <2 x i1> %m2, <3 x i1> %m3, <4 x i1> %m4, define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8, <16 x i1> %m16, <32 x i1> %m32, <64 x i1> %m64) { ; SSE2-LABEL: 'masked_gather' -; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 380 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SSE42-LABEL: 'masked_gather' -; SSE42-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; AVX1-LABEL: 'masked_gather' -; AVX1-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 278 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; AVX2-LABEL: 'masked_gather' -; AVX2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 276 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 138 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKL-LABEL: 'masked_gather' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) @@ -851,53 +851,53 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 276 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 138 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_gather' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 163 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 323 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 347 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 173 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 86 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_gather' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) @@ -905,19 +905,19 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 163 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 323 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 347 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 173 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 86 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) @@ -955,118 +955,172 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8, <16 x i1> %m16, <32 x i1> %m32, <64 x i1> %m64) { ; SSE2-LABEL: 'masked_scatter' -; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 380 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SSE2-NEXT: Cost Model: Found an estimated cost of 190 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE2-NEXT: Cost Model: Found an estimated cost of 95 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 384 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SSE2-NEXT: Cost Model: Found an estimated cost of 192 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE2-NEXT: Cost Model: Found an estimated cost of 96 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SSE42-LABEL: 'masked_scatter' -; SSE42-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 320 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 31 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 260 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; -; AVX-LABEL: 'masked_scatter' -; AVX-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; AVX-NEXT: Cost Model: Found an estimated cost of 78 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 42 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; AVX-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 162 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; AVX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 322 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; AVX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; AVX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; AVX1-LABEL: 'masked_scatter' +; AVX1-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 140 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX1-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 278 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; AVX1-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX1-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; +; AVX2-LABEL: 'masked_scatter' +; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX2-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 276 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; AVX2-NEXT: Cost Model: Found an estimated cost of 138 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX2-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; +; SKL-LABEL: 'masked_scatter' +; SKL-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKL-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKL-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 276 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SKL-NEXT: Cost Model: Found an estimated cost of 138 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKL-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_scatter' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 163 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; KNL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; KNL-NEXT: Cost Model: Found an estimated cost of 323 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; KNL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; KNL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; KNL-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 347 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; KNL-NEXT: Cost Model: Found an estimated cost of 173 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; KNL-NEXT: Cost Model: Found an estimated cost of 86 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_scatter' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) @@ -1074,19 +1128,19 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 163 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SKX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SKX-NEXT: Cost Model: Found an estimated cost of 323 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SKX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SKX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 347 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SKX-NEXT: Cost Model: Found an estimated cost of 173 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKX-NEXT: Cost Model: Found an estimated cost of 86 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) @@ -1734,19 +1788,19 @@ define <2 x i32> @test8(<2 x i32> %trigger, ptr %addr, <2 x i32> %dst) { define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x double> %src0) { ; SSE2-LABEL: 'test_gather_2f64' -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SSE42-LABEL: 'test_gather_2f64' -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX1-LABEL: 'test_gather_2f64' -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX2-LABEL: 'test_gather_2f64' -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SKL-LABEL: 'test_gather_2f64' @@ -1763,19 +1817,19 @@ define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x doub define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %src0) { ; SSE2-LABEL: 'test_gather_4i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SSE42-LABEL: 'test_gather_4i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX1-LABEL: 'test_gather_4i32' -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX2-LABEL: 'test_gather_4i32' -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32' @@ -1783,7 +1837,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32' -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32' @@ -1796,7 +1850,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) { ; SSE2-LABEL: 'test_gather_4i32_const_mask' -; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SSE42-LABEL: 'test_gather_4i32_const_mask' @@ -1804,11 +1858,11 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX1-LABEL: 'test_gather_4i32_const_mask' -; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX2-LABEL: 'test_gather_4i32_const_mask' -; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32_const_mask' @@ -1816,7 +1870,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32_const_mask' -; KNL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; KNL-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32_const_mask' @@ -1831,7 +1885,7 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_const_mask' @@ -1843,13 +1897,13 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; AVX1-LABEL: 'test_gather_16f32_const_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_const_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_const_mask' @@ -1875,25 +1929,25 @@ define <16 x float> @test_gather_16f32_var_mask(ptr %base, <16 x i32> %ind, <16 ; SSE2-LABEL: 'test_gather_16f32_var_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_var_mask' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX1-LABEL: 'test_gather_16f32_var_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_var_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_var_mask' @@ -1919,25 +1973,25 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> ; SSE2-LABEL: 'test_gather_16f32_ra_var_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_ra_var_mask' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX1-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_ra_var_mask' @@ -1965,7 +2019,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_const_mask2' @@ -1981,7 +2035,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_const_mask2' @@ -1989,7 +2043,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_const_mask2' @@ -2024,7 +2078,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_16i32' @@ -2032,7 +2086,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX1-LABEL: 'test_scatter_16i32' @@ -2040,7 +2094,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX1-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX2-LABEL: 'test_scatter_16i32' @@ -2048,7 +2102,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX2-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKL-LABEL: 'test_scatter_16i32' @@ -2056,7 +2110,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SKL-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SKL-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_16i32' @@ -2078,15 +2132,15 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { ; SSE2-LABEL: 'test_scatter_8i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_8i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX-LABEL: 'test_scatter_8i32' -; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; AVX-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_8i32' @@ -2099,19 +2153,19 @@ define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { define void @test_scatter_4i32(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; SSE2-LABEL: 'test_scatter_4i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_4i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX-LABEL: 'test_scatter_4i32' -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; AVX-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; KNL-LABEL: 'test_scatter_4i32' -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKX-LABEL: 'test_scatter_4i32' @@ -2126,25 +2180,25 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SSE2-LABEL: 'test_gather_4f32' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SSE42-LABEL: 'test_gather_4f32' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX1-LABEL: 'test_gather_4f32' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX2-LABEL: 'test_gather_4f32' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKL-LABEL: 'test_gather_4f32' @@ -2156,7 +2210,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; KNL-LABEL: 'test_gather_4f32' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; KNL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKX-LABEL: 'test_gather_4f32' @@ -2176,7 +2230,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SSE2-LABEL: 'test_gather_4f32_const_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SSE42-LABEL: 'test_gather_4f32_const_mask' @@ -2188,13 +2242,13 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; AVX1-LABEL: 'test_gather_4f32_const_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX2-LABEL: 'test_gather_4f32_const_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKL-LABEL: 'test_gather_4f32_const_mask' @@ -2206,7 +2260,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; KNL-LABEL: 'test_gather_4f32_const_mask' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; KNL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; KNL-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKX-LABEL: 'test_gather_4f32_const_mask' diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll index b460df341b44..07583d268c8a 100644 --- a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll +++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-sizelatency.ll @@ -732,118 +732,118 @@ define i32 @masked_store(<1 x i1> %m1, <2 x i1> %m2, <3 x i1> %m3, <4 x i1> %m4, define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8, <16 x i1> %m16, <32 x i1> %m32, <64 x i1> %m64) { ; SSE2-LABEL: 'masked_gather' -; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 380 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 384 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SSE42-LABEL: 'masked_gather' -; SSE42-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 260 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; AVX1-LABEL: 'masked_gather' -; AVX1-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; AVX1-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 140 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 278 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; AVX2-LABEL: 'masked_gather' -; AVX2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 82 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; AVX2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 276 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 138 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKL-LABEL: 'masked_gather' ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) @@ -851,53 +851,53 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 162 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 322 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SKL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 276 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 138 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 69 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_gather' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 163 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 323 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 347 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 173 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 86 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_gather' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x double> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x double> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x float> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x float> undef) @@ -905,19 +905,19 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i64> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0(<1 x ptr> undef, i32 1, <1 x i1> %m1, <1 x i64> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i32> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> undef, i32 1, <2 x i1> %m2, <2 x i32> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 163 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 323 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0(<4 x ptr> undef, i32 1, <4 x i1> %m4, <4 x i16> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 347 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0(<64 x ptr> undef, i32 1, <64 x i1> %m64, <64 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 173 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0(<32 x ptr> undef, i32 1, <32 x i1> %m32, <32 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 86 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0(<16 x ptr> undef, i32 1, <16 x i1> %m16, <16 x i8> undef) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x i8> undef) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0(<8 x ptr> undef, i32 1, <8 x i1> %m8, <8 x double> undef) @@ -955,118 +955,172 @@ define i32 @masked_gather(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8 define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m8, <16 x i1> %m16, <32 x i1> %m32, <64 x i1> %m64) { ; SSE2-LABEL: 'masked_scatter' -; SSE2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE2-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE2-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE2-NEXT: Cost Model: Found an estimated cost of 380 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SSE2-NEXT: Cost Model: Found an estimated cost of 190 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE2-NEXT: Cost Model: Found an estimated cost of 95 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 45 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE2-NEXT: Cost Model: Found an estimated cost of 162 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE2-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE2-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE2-NEXT: Cost Model: Found an estimated cost of 384 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SSE2-NEXT: Cost Model: Found an estimated cost of 192 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE2-NEXT: Cost Model: Found an estimated cost of 96 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE2-NEXT: Cost Model: Found an estimated cost of 48 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SSE42-LABEL: 'masked_scatter' -; SSE42-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SSE42-NEXT: Cost Model: Found an estimated cost of 320 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SSE42-NEXT: Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 31 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SSE42-NEXT: Cost Model: Found an estimated cost of 260 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SSE42-NEXT: Cost Model: Found an estimated cost of 130 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; -; AVX-LABEL: 'masked_scatter' -; AVX-NEXT: Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; AVX-NEXT: Cost Model: Found an estimated cost of 78 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 42 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) -; AVX-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; AVX-NEXT: Cost Model: Found an estimated cost of 162 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; AVX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; AVX-NEXT: Cost Model: Found an estimated cost of 322 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; AVX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; AVX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; AVX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; AVX1-LABEL: 'masked_scatter' +; AVX1-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX1-NEXT: Cost Model: Found an estimated cost of 140 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX1-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX1-NEXT: Cost Model: Found an estimated cost of 278 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; AVX1-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX1-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX1-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; +; AVX2-LABEL: 'masked_scatter' +; AVX2-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; AVX2-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX2-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; AVX2-NEXT: Cost Model: Found an estimated cost of 276 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; AVX2-NEXT: Cost Model: Found an estimated cost of 138 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; AVX2-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; AVX2-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 +; +; SKL-LABEL: 'masked_scatter' +; SKL-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKL-NEXT: Cost Model: Found an estimated cost of 67 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 34 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKL-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) +; SKL-NEXT: Cost Model: Found an estimated cost of 139 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKL-NEXT: Cost Model: Found an estimated cost of 70 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKL-NEXT: Cost Model: Found an estimated cost of 276 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SKL-NEXT: Cost Model: Found an estimated cost of 138 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKL-NEXT: Cost Model: Found an estimated cost of 69 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKL-NEXT: Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; KNL-LABEL: 'masked_scatter' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f32.v2p0(<2 x float> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; KNL-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; KNL-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; KNL-NEXT: Cost Model: Found an estimated cost of 163 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; KNL-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; KNL-NEXT: Cost Model: Found an estimated cost of 323 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; KNL-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; KNL-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; KNL-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; KNL-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; KNL-NEXT: Cost Model: Found an estimated cost of 347 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; KNL-NEXT: Cost Model: Found an estimated cost of 173 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; KNL-NEXT: Cost Model: Found an estimated cost of 86 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; KNL-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; ; SKX-LABEL: 'masked_scatter' ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1f64.v1p0(<1 x double> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16f32.v16p0(<16 x float> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4f32.v4p0(<4 x float> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) @@ -1074,19 +1128,19 @@ define i32 @masked_scatter(<1 x i1> %m1, <2 x i1> %m2, <4 x i1> %m4, <8 x i1> %m ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i64.v8p0(<8 x i64> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i64.v4p0(<4 x i64> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i64.v2p0(<2 x i64> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) +; SKX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v1i64.v1p0(<1 x i64> undef, <1 x ptr> undef, i32 1, <1 x i1> %m1) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) ; SKX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v2i32.v2p0(<2 x i32> undef, <2 x ptr> undef, i32 1, <2 x i1> %m2) -; SKX-NEXT: Cost Model: Found an estimated cost of 163 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SKX-NEXT: Cost Model: Found an estimated cost of 81 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) -; SKX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) -; SKX-NEXT: Cost Model: Found an estimated cost of 323 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) -; SKX-NEXT: Cost Model: Found an estimated cost of 161 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) -; SKX-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) -; SKX-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 175 for instruction: call void @llvm.masked.scatter.v32i16.v32p0(<32 x i16> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKX-NEXT: Cost Model: Found an estimated cost of 87 for instruction: call void @llvm.masked.scatter.v16i16.v16p0(<16 x i16> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i16.v8p0(<8 x i16> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) +; SKX-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i16.v4p0(<4 x i16> undef, <4 x ptr> undef, i32 1, <4 x i1> %m4) +; SKX-NEXT: Cost Model: Found an estimated cost of 347 for instruction: call void @llvm.masked.scatter.v64i8.v64p0(<64 x i8> undef, <64 x ptr> undef, i32 1, <64 x i1> %m64) +; SKX-NEXT: Cost Model: Found an estimated cost of 173 for instruction: call void @llvm.masked.scatter.v32i8.v32p0(<32 x i8> undef, <32 x ptr> undef, i32 1, <32 x i1> %m32) +; SKX-NEXT: Cost Model: Found an estimated cost of 86 for instruction: call void @llvm.masked.scatter.v16i8.v16p0(<16 x i8> undef, <16 x ptr> undef, i32 1, <16 x i1> %m16) +; SKX-NEXT: Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.scatter.v8i8.v8p0(<8 x i8> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) ; SKX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret i32 0 ; call void @llvm.masked.scatter.v8f64.v8p0(<8 x double> undef, <8 x ptr> undef, i32 1, <8 x i1> %m8) @@ -1734,19 +1788,19 @@ define <2 x i32> @test8(<2 x i32> %trigger, ptr %addr, <2 x i32> %dst) { define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x double> %src0) { ; SSE2-LABEL: 'test_gather_2f64' -; SSE2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SSE42-LABEL: 'test_gather_2f64' -; SSE42-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; SSE42-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX1-LABEL: 'test_gather_2f64' -; AVX1-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; AVX2-LABEL: 'test_gather_2f64' -; AVX2-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <2 x double> %res ; ; SKL-LABEL: 'test_gather_2f64' @@ -1763,19 +1817,19 @@ define <2 x double> @test_gather_2f64(<2 x ptr> %ptrs, <2 x i1> %mask, <2 x doub define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %src0) { ; SSE2-LABEL: 'test_gather_4i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SSE42-LABEL: 'test_gather_4i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX1-LABEL: 'test_gather_4i32' -; AVX1-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX2-LABEL: 'test_gather_4i32' -; AVX2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32' @@ -1783,7 +1837,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32' -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32' @@ -1796,7 +1850,7 @@ define <4 x i32> @test_gather_4i32(<4 x ptr> %ptrs, <4 x i1> %mask, <4 x i32> %s define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) { ; SSE2-LABEL: 'test_gather_4i32_const_mask' -; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SSE42-LABEL: 'test_gather_4i32_const_mask' @@ -1804,11 +1858,11 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX1-LABEL: 'test_gather_4i32_const_mask' -; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; AVX1-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; AVX2-LABEL: 'test_gather_4i32_const_mask' -; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; AVX2-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKL-LABEL: 'test_gather_4i32_const_mask' @@ -1816,7 +1870,7 @@ define <4 x i32> @test_gather_4i32_const_mask(<4 x ptr> %ptrs, <4 x i32> %src0) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; KNL-LABEL: 'test_gather_4i32_const_mask' -; KNL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) +; KNL-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> , <4 x i32> %src0) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x i32> %res ; ; SKX-LABEL: 'test_gather_4i32_const_mask' @@ -1831,7 +1885,7 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; SSE2-LABEL: 'test_gather_16f32_const_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_const_mask' @@ -1843,13 +1897,13 @@ define <16 x float> @test_gather_16f32_const_mask(ptr %base, <16 x i32> %ind) { ; AVX1-LABEL: 'test_gather_16f32_const_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_const_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> , <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_const_mask' @@ -1875,25 +1929,25 @@ define <16 x float> @test_gather_16f32_var_mask(ptr %base, <16 x i32> %ind, <16 ; SSE2-LABEL: 'test_gather_16f32_var_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_var_mask' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX1-LABEL: 'test_gather_16f32_var_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_var_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %base, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_var_mask' @@ -1919,25 +1973,25 @@ define <16 x float> @test_gather_16f32_ra_var_mask(<16 x ptr> %ptrs, <16 x i32> ; SSE2-LABEL: 'test_gather_16f32_ra_var_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 77 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_ra_var_mask' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 61 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX1-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_ra_var_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x ptr> %ptrs, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 78 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 67 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_ra_var_mask' @@ -1965,7 +2019,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SSE42-LABEL: 'test_gather_16f32_const_mask2' @@ -1981,7 +2035,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; AVX2-LABEL: 'test_gather_16f32_const_mask2' @@ -1989,7 +2043,7 @@ define <16 x float> @test_gather_16f32_const_mask2(ptr %base, <16 x i32> %ind) { ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x ptr> %broadcast.splat, <16 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %gep.random, i32 4, <16 x i1> , <16 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <16 x float> %res ; ; SKL-LABEL: 'test_gather_16f32_const_mask2' @@ -2024,7 +2078,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SSE2-NEXT: Cost Model: Found an estimated cost of 92 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 93 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_16i32' @@ -2032,7 +2086,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SSE42-NEXT: Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 65 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX1-LABEL: 'test_scatter_16i32' @@ -2040,7 +2094,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX1-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX1-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX2-LABEL: 'test_scatter_16i32' @@ -2048,7 +2102,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; AVX2-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; AVX2-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKL-LABEL: 'test_scatter_16i32' @@ -2056,7 +2110,7 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x ptr> %broadcast.splatinsert, <16 x ptr> undef, <16 x i32> zeroinitializer ; SKL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x ptr> %broadcast.splat, <16 x i32> %ind ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1> -; SKL-NEXT: Cost Model: Found an estimated cost of 82 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) +; SKL-NEXT: Cost Model: Found an estimated cost of 71 for instruction: call void @llvm.masked.scatter.v16i32.v16p0(<16 x i32> %val, <16 x ptr> %gep.random, i32 4, <16 x i1> %imask) ; SKL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_16i32' @@ -2078,15 +2132,15 @@ define void @test_scatter_16i32(ptr %base, <16 x i32> %ind, i16 %mask, <16 x i32 define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { ; SSE2-LABEL: 'test_scatter_8i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_8i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 33 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX-LABEL: 'test_scatter_8i32' -; AVX-NEXT: Cost Model: Found an estimated cost of 41 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) +; AVX-NEXT: Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %a1, <8 x ptr> %ptr, i32 4, <8 x i1> %mask) ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX512-LABEL: 'test_scatter_8i32' @@ -2099,19 +2153,19 @@ define void @test_scatter_8i32(<8 x i32>%a1, <8 x ptr> %ptr, <8 x i1>%mask) { define void @test_scatter_4i32(<4 x i32>%a1, <4 x ptr> %ptr, <4 x i1>%mask) { ; SSE2-LABEL: 'test_scatter_4i32' -; SSE2-NEXT: Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SSE2-NEXT: Cost Model: Found an estimated cost of 24 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SSE42-LABEL: 'test_scatter_4i32' -; SSE42-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; SSE42-NEXT: Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; AVX-LABEL: 'test_scatter_4i32' -; AVX-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; AVX-NEXT: Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; KNL-LABEL: 'test_scatter_4i32' -; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) +; KNL-NEXT: Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.scatter.v4i32.v4p0(<4 x i32> %a1, <4 x ptr> %ptr, i32 4, <4 x i1> %mask) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; ; SKX-LABEL: 'test_scatter_4i32' @@ -2126,25 +2180,25 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; SSE2-LABEL: 'test_gather_4f32' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SSE42-LABEL: 'test_gather_4f32' ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE42-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE42-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; SSE42-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX1-LABEL: 'test_gather_4f32' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX2-LABEL: 'test_gather_4f32' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 17 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKL-LABEL: 'test_gather_4f32' @@ -2156,7 +2210,7 @@ define <4 x float> @test_gather_4f32(ptr %ptr, <4 x i32> %ind, <4 x i1>%mask) { ; KNL-LABEL: 'test_gather_4f32' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; KNL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; KNL-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKX-LABEL: 'test_gather_4f32' @@ -2176,7 +2230,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; SSE2-LABEL: 'test_gather_4f32_const_mask' ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; SSE2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; SSE2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; SSE2-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SSE42-LABEL: 'test_gather_4f32_const_mask' @@ -2188,13 +2242,13 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; AVX1-LABEL: 'test_gather_4f32_const_mask' ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX1-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; AVX1-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; AVX1-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; AVX2-LABEL: 'test_gather_4f32_const_mask' ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; AVX2-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; AVX2-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; AVX2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKL-LABEL: 'test_gather_4f32_const_mask' @@ -2206,7 +2260,7 @@ define <4 x float> @test_gather_4f32_const_mask(ptr %ptr, <4 x i32> %ind) { ; KNL-LABEL: 'test_gather_4f32_const_mask' ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64> ; KNL-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, ptr %ptr, <4 x i64> %sext_ind -; KNL-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) +; KNL-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0(<4 x ptr> %gep.v, i32 4, <4 x i1> , <4 x float> undef) ; KNL-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret <4 x float> %res ; ; SKX-LABEL: 'test_gather_4f32_const_mask' diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll index 37ac570aa06c..9969f881063c 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll @@ -5,8 +5,8 @@ target triple = "aarch64-unknown-linux-gnu" ; CHECK-COST: Checking a loop in 'fixed_width' -; CHECK-COST: Found an estimated cost of 12 for VF 2 For instruction: store i32 2, ptr %arrayidx1, align 4 -; CHECK-COST: Found an estimated cost of 24 for VF 4 For instruction: store i32 2, ptr %arrayidx1, align 4 +; CHECK-COST: Found an estimated cost of 14 for VF 2 For instruction: store i32 2, ptr %arrayidx1, align 4 +; CHECK-COST: Found an estimated cost of 28 for VF 4 For instruction: store i32 2, ptr %arrayidx1, align 4 ; CHECK-COST: Selecting VF: 1. ; We should decide this loop is not worth vectorising using fixed width vectors -- GitLab From c8917048e3aa2be03b6588b817730abdbce23c85 Mon Sep 17 00:00:00 2001 From: Jakub Mazurkiewicz Date: Tue, 9 Apr 2024 17:10:20 +0200 Subject: [PATCH 286/695] [libc++] Implement `bind_back` (#81055) Implement `std::bind_back` function from P2387R3 "Pipe support for user-defined range adaptors". --- libcxx/docs/FeatureTestMacroTable.rst | 4 +- libcxx/docs/Status/Cxx23.rst | 1 + libcxx/docs/Status/Cxx23Papers.csv | 2 +- libcxx/include/__functional/bind_back.h | 14 + libcxx/include/functional | 6 + libcxx/include/version | 7 +- libcxx/modules/std/functional.inc | 4 +- .../functional.version.compile.pass.cpp | 33 +- .../version.version.compile.pass.cpp | 33 +- .../func.bind.partial/bind_back.pass.cpp | 381 ++++++++++++++++++ .../func.bind.partial/bind_back.verify.cpp | 85 ++++ .../func.bind.partial/types.h | 43 ++ .../func.bind_front/bind_front.pass.cpp | 30 +- .../generate_feature_test_macro_components.py | 3 +- 14 files changed, 582 insertions(+), 64 deletions(-) create mode 100644 libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.pass.cpp create mode 100644 libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp create mode 100644 libcxx/test/std/utilities/function.objects/func.bind.partial/types.h diff --git a/libcxx/docs/FeatureTestMacroTable.rst b/libcxx/docs/FeatureTestMacroTable.rst index 014ac1c31e63..3197d2cd1b27 100644 --- a/libcxx/docs/FeatureTestMacroTable.rst +++ b/libcxx/docs/FeatureTestMacroTable.rst @@ -308,7 +308,7 @@ Status ---------------------------------------------------------- ----------------- ``__cpp_lib_associative_heterogeneous_erasure`` *unimplemented* ---------------------------------------------------------- ----------------- - ``__cpp_lib_bind_back`` *unimplemented* + ``__cpp_lib_bind_back`` ``202202L`` ---------------------------------------------------------- ----------------- ``__cpp_lib_byteswap`` ``202110L`` ---------------------------------------------------------- ----------------- @@ -398,8 +398,6 @@ Status ---------------------------------------------------------- ----------------- ``__cpp_lib_atomic_min_max`` *unimplemented* ---------------------------------------------------------- ----------------- - ``__cpp_lib_bind_back`` *unimplemented* - ---------------------------------------------------------- ----------------- ``__cpp_lib_bind_front`` ``202306L`` ---------------------------------------------------------- ----------------- ``__cpp_lib_bitset`` ``202306L`` diff --git a/libcxx/docs/Status/Cxx23.rst b/libcxx/docs/Status/Cxx23.rst index 23d30c8128d7..b19ff4fdc0f7 100644 --- a/libcxx/docs/Status/Cxx23.rst +++ b/libcxx/docs/Status/Cxx23.rst @@ -43,6 +43,7 @@ Paper Status .. [#note-P0533R9] P0533R9: ``isfinite``, ``isinf``, ``isnan`` and ``isnormal`` are implemented. .. [#note-P1413R3] P1413R3: ``std::aligned_storage_t`` and ``std::aligned_union_t`` are marked deprecated, but clang doesn't issue a diagnostic for deprecated using template declarations. + .. [#note-P2387R3] P2387R3: ``bind_back`` only .. [#note-P2520R0] P2520R0: Libc++ implemented this paper as a DR in C++20 as well. .. [#note-P2711R1] P2711R1: ``join_with_view`` hasn't been done yet since this type isn't implemented yet. .. [#note-P2770R0] P2770R0: ``join_with_view`` hasn't been done yet since this type isn't implemented yet. diff --git a/libcxx/docs/Status/Cxx23Papers.csv b/libcxx/docs/Status/Cxx23Papers.csv index 80547c5c1f3f..065db97a0b0b 100644 --- a/libcxx/docs/Status/Cxx23Papers.csv +++ b/libcxx/docs/Status/Cxx23Papers.csv @@ -45,7 +45,7 @@ "`P1413R3 `__","LWG","Deprecate ``std::aligned_storage`` and ``std::aligned_union``","February 2022","|Complete| [#note-P1413R3]_","" "`P2255R2 `__","LWG","A type trait to detect reference binding to temporary","February 2022","","" "`P2273R3 `__","LWG","Making ``std::unique_ptr`` constexpr","February 2022","|Complete|","16.0" -"`P2387R3 `__","LWG","Pipe support for user-defined range adaptors","February 2022","","","|ranges|" +"`P2387R3 `__","LWG","Pipe support for user-defined range adaptors","February 2022","|Partial| [#note-P2387R3]_","","|ranges|" "`P2440R1 `__","LWG","``ranges::iota``, ``ranges::shift_left`` and ``ranges::shift_right``","February 2022","","","|ranges|" "`P2441R2 `__","LWG","``views::join_with``","February 2022","|In Progress|","","|ranges|" "`P2442R1 `__","LWG","Windowing range adaptors: ``views::chunk`` and ``views::slide``","February 2022","","","|ranges|" diff --git a/libcxx/include/__functional/bind_back.h b/libcxx/include/__functional/bind_back.h index ce26d3b70630..3c42d4769e8a 100644 --- a/libcxx/include/__functional/bind_back.h +++ b/libcxx/include/__functional/bind_back.h @@ -62,6 +62,20 @@ _LIBCPP_HIDE_FROM_ABI constexpr auto __bind_back(_Fn&& __f, _Args&&... __args) n std::forward<_Fn>(__f), std::forward_as_tuple(std::forward<_Args>(__args)...)); } +# if _LIBCPP_STD_VER >= 23 +template +_LIBCPP_HIDE_FROM_ABI constexpr auto bind_back(_Fn&& __f, _Args&&... __args) { + static_assert(is_constructible_v, _Fn>, "bind_back requires decay_t to be constructible from F"); + static_assert(is_move_constructible_v>, "bind_back requires decay_t to be move constructible"); + static_assert((is_constructible_v, _Args> && ...), + "bind_back requires all decay_t to be constructible from respective Args"); + static_assert((is_move_constructible_v> && ...), + "bind_back requires all decay_t to be move constructible"); + return __bind_back_t, tuple...>>( + std::forward<_Fn>(__f), std::forward_as_tuple(std::forward<_Args>(__args)...)); +} +# endif // _LIBCPP_STD_VER >= 23 + #endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/functional b/libcxx/include/functional index a2774a48bda0..a2476c93ad1b 100644 --- a/libcxx/include/functional +++ b/libcxx/include/functional @@ -207,6 +207,12 @@ binary_negate not2(const Predicate& pred); template constexpr unspecified not_fn(F&& f); // C++17, constexpr in C++20 +// [func.bind.partial], function templates bind_front and bind_back +template + constexpr unspecified bind_front(F&&, Args&&...); // C++20 +template + constexpr unspecified bind_back(F&&, Args&&...); // C++23 + template struct is_bind_expression; template struct is_placeholder; diff --git a/libcxx/include/version b/libcxx/include/version index 90dc1b279c6c..0ed77345baa7 100644 --- a/libcxx/include/version +++ b/libcxx/include/version @@ -41,8 +41,7 @@ __cpp_lib_atomic_shared_ptr 201711L __cpp_lib_atomic_value_initialization 201911L __cpp_lib_atomic_wait 201907L __cpp_lib_barrier 201907L -__cpp_lib_bind_back 202306L - 202202L // C++23 +__cpp_lib_bind_back 202202L __cpp_lib_bind_front 202306L 201907L // C++20 __cpp_lib_bit_cast 201806L @@ -449,7 +448,7 @@ __cpp_lib_within_lifetime 202306L # define __cpp_lib_adaptor_iterator_pair_constructor 202106L # define __cpp_lib_allocate_at_least 202302L // # define __cpp_lib_associative_heterogeneous_erasure 202110L -// # define __cpp_lib_bind_back 202202L +# define __cpp_lib_bind_back 202202L # define __cpp_lib_byteswap 202110L # define __cpp_lib_constexpr_bitset 202207L # define __cpp_lib_constexpr_charconv 202207L @@ -498,8 +497,6 @@ __cpp_lib_within_lifetime 202306L #if _LIBCPP_STD_VER >= 26 // # define __cpp_lib_associative_heterogeneous_insertion 202306L // # define __cpp_lib_atomic_min_max 202403L -# undef __cpp_lib_bind_back -// # define __cpp_lib_bind_back 202306L # undef __cpp_lib_bind_front # define __cpp_lib_bind_front 202306L # define __cpp_lib_bitset 202306L diff --git a/libcxx/modules/std/functional.inc b/libcxx/modules/std/functional.inc index 1148944a9d2f..ddc7d023ee6d 100644 --- a/libcxx/modules/std/functional.inc +++ b/libcxx/modules/std/functional.inc @@ -56,8 +56,10 @@ export namespace std { using std::not_fn; // [func.bind.partial], function templates bind_front and bind_back - // using std::bind_back; using std::bind_front; +#if _LIBCPP_STD_VER >= 23 + using std::bind_back; +#endif // [func.bind], bind using std::is_bind_expression; diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp index fa4d9baa2837..aeb09a30b425 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.compile.pass.cpp @@ -17,7 +17,6 @@ /* Constant Value __cpp_lib_bind_back 202202L [C++23] - 202306L [C++26] __cpp_lib_bind_front 201907L [C++20] 202306L [C++26] __cpp_lib_boyer_moore_searcher 201603L [C++17] @@ -337,17 +336,11 @@ #elif TEST_STD_VER == 23 -# if !defined(_LIBCPP_VERSION) -# ifndef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should be defined in c++23" -# endif -# if __cpp_lib_bind_back != 202202L -# error "__cpp_lib_bind_back should have the value 202202L in c++23" -# endif -# else // _LIBCPP_VERSION -# ifdef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should not be defined because it is unimplemented in libc++!" -# endif +# ifndef __cpp_lib_bind_back +# error "__cpp_lib_bind_back should be defined in c++23" +# endif +# if __cpp_lib_bind_back != 202202L +# error "__cpp_lib_bind_back should have the value 202202L in c++23" # endif # ifndef __cpp_lib_bind_front @@ -447,17 +440,11 @@ #elif TEST_STD_VER > 23 -# if !defined(_LIBCPP_VERSION) -# ifndef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should be defined in c++26" -# endif -# if __cpp_lib_bind_back != 202306L -# error "__cpp_lib_bind_back should have the value 202306L in c++26" -# endif -# else // _LIBCPP_VERSION -# ifdef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should not be defined because it is unimplemented in libc++!" -# endif +# ifndef __cpp_lib_bind_back +# error "__cpp_lib_bind_back should be defined in c++26" +# endif +# if __cpp_lib_bind_back != 202202L +# error "__cpp_lib_bind_back should have the value 202202L in c++26" # endif # ifndef __cpp_lib_bind_front diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp index 5055786c2d45..3ec548f56cea 100644 --- a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp @@ -39,7 +39,6 @@ __cpp_lib_atomic_wait 201907L [C++20] __cpp_lib_barrier 201907L [C++20] __cpp_lib_bind_back 202202L [C++23] - 202306L [C++26] __cpp_lib_bind_front 201907L [C++20] 202306L [C++26] __cpp_lib_bit_cast 201806L [C++20] @@ -4605,17 +4604,11 @@ # endif # endif -# if !defined(_LIBCPP_VERSION) -# ifndef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should be defined in c++23" -# endif -# if __cpp_lib_bind_back != 202202L -# error "__cpp_lib_bind_back should have the value 202202L in c++23" -# endif -# else // _LIBCPP_VERSION -# ifdef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should not be defined because it is unimplemented in libc++!" -# endif +# ifndef __cpp_lib_bind_back +# error "__cpp_lib_bind_back should be defined in c++23" +# endif +# if __cpp_lib_bind_back != 202202L +# error "__cpp_lib_bind_back should have the value 202202L in c++23" # endif # ifndef __cpp_lib_bind_front @@ -6240,17 +6233,11 @@ # endif # endif -# if !defined(_LIBCPP_VERSION) -# ifndef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should be defined in c++26" -# endif -# if __cpp_lib_bind_back != 202306L -# error "__cpp_lib_bind_back should have the value 202306L in c++26" -# endif -# else // _LIBCPP_VERSION -# ifdef __cpp_lib_bind_back -# error "__cpp_lib_bind_back should not be defined because it is unimplemented in libc++!" -# endif +# ifndef __cpp_lib_bind_back +# error "__cpp_lib_bind_back should be defined in c++26" +# endif +# if __cpp_lib_bind_back != 202202L +# error "__cpp_lib_bind_back should have the value 202202L in c++26" # endif # ifndef __cpp_lib_bind_front diff --git a/libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.pass.cpp b/libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.pass.cpp new file mode 100644 index 000000000000..01a96348d50c --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.pass.cpp @@ -0,0 +1,381 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 + +// + +// template +// constexpr unspecified bind_back(F&& f, Args&&... args); + +#include + +#include +#include +#include +#include + +#include "callable_types.h" +#include "types.h" + +constexpr void test_basic_bindings() { + { // Bind arguments, call without arguments + { + auto f = std::bind_back(MakeTuple{}); + assert(f() == std::make_tuple()); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}); + assert(f() == std::make_tuple(Elem<1>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}); + assert(f() == std::make_tuple(Elem<1>{}, Elem<2>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}, Elem<3>{}); + assert(f() == std::make_tuple(Elem<1>{}, Elem<2>{}, Elem<3>{})); + } + } + + { // Bind no arguments, call with arguments + { + auto f = std::bind_back(MakeTuple{}); + assert(f(Elem<1>{}) == std::make_tuple(Elem<1>{})); + } + { + auto f = std::bind_back(MakeTuple{}); + assert(f(Elem<1>{}, Elem<2>{}) == std::make_tuple(Elem<1>{}, Elem<2>{})); + } + { + auto f = std::bind_back(MakeTuple{}); + assert(f(Elem<1>{}, Elem<2>{}, Elem<3>{}) == std::make_tuple(Elem<1>{}, Elem<2>{}, Elem<3>{})); + } + } + + { // Bind arguments, call with arguments + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}); + assert(f(Elem<10>{}) == std::make_tuple(Elem<10>{}, Elem<1>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}); + assert(f(Elem<10>{}) == std::make_tuple(Elem<10>{}, Elem<1>{}, Elem<2>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}, Elem<3>{}); + assert(f(Elem<10>{}) == std::make_tuple(Elem<10>{}, Elem<1>{}, Elem<2>{}, Elem<3>{})); + } + + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}); + assert(f(Elem<10>{}, Elem<11>{}) == std::make_tuple(Elem<10>{}, Elem<11>{}, Elem<1>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}); + assert(f(Elem<10>{}, Elem<11>{}) == std::make_tuple(Elem<10>{}, Elem<11>{}, Elem<1>{}, Elem<2>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}, Elem<3>{}); + assert(f(Elem<10>{}, Elem<11>{}) == std::make_tuple(Elem<10>{}, Elem<11>{}, Elem<1>{}, Elem<2>{}, Elem<3>{})); + } + { + auto f = std::bind_back(MakeTuple{}, Elem<1>{}, Elem<2>{}, Elem<3>{}); + assert(f(Elem<10>{}, Elem<11>{}, Elem<12>{}) == + std::make_tuple(Elem<10>{}, Elem<11>{}, Elem<12>{}, Elem<1>{}, Elem<2>{}, Elem<3>{})); + } + } + + { // Basic tests with fundamental types + int n = 2; + int m = 1; + int sum = 0; + auto add = [](int x, int y) { return x + y; }; + auto add_n = [](int a, int b, int c, int d, int e, int f) { return a + b + c + d + e + f; }; + auto add_ref = [&](int x, int y) -> int& { return sum = x + y; }; + auto add_rref = [&](int x, int y) -> int&& { return std::move(sum = x + y); }; + + auto a = std::bind_back(add, m, n); + assert(a() == 3); + + auto b = std::bind_back(add_n, m, n, m, m, m, m); + assert(b() == 7); + + auto c = std::bind_back(add_n, n, m); + assert(c(1, 1, 1, 1) == 7); + + auto d = std::bind_back(add_ref, n, m); + std::same_as decltype(auto) dresult(d()); + assert(dresult == 3); + + auto e = std::bind_back(add_rref, n, m); + std::same_as decltype(auto) eresult(e()); + assert(eresult == 3); + + auto f = std::bind_back(add, n); + assert(f(3) == 5); + + auto g = std::bind_back(add, n, 1); + assert(g() == 3); + + auto h = std::bind_back(add_n, 1, 1, 1); + assert(h(2, 2, 2) == 9); + + auto i = std::bind_back(add_ref, n); + std::same_as decltype(auto) iresult(i(5)); + assert(iresult == 7); + + auto j = std::bind_back(add_rref, m); + std::same_as decltype(auto) jresult(j(4)); + assert(jresult == 5); + } +} + +constexpr void test_edge_cases() { + { // Make sure we don't treat std::reference_wrapper specially. + auto sub = [](std::reference_wrapper a, std::reference_wrapper b) { return a.get() - b.get(); }; + + int i = 1; + int j = 2; + auto f = std::bind_back(sub, std::ref(i)); + assert(f(std::ref(j)) == 1); + } + + { // Make sure we can call a function that's a pointer to a member function. + struct MemberFunction { + constexpr int foo(int x, int y) { return x * y; } + }; + + MemberFunction value; + auto fn = std::bind_back(&MemberFunction::foo, 2, 3); + assert(fn(value) == 6); + } + + { // Make sure we can call a function that's a pointer to a member object. + struct MemberObject { + int obj; + }; + + MemberObject value{.obj = 3}; + auto fn = std::bind_back(&MemberObject::obj); + assert(fn(value) == 3); + } +} + +constexpr void test_passing_arguments() { + { // Make sure that we copy the bound arguments into the unspecified-type. + auto add = [](int x, int y) { return x + y; }; + int n = 2; + auto f = std::bind_back(add, n, 1); + n = 100; + assert(f() == 3); + } + + { // Make sure we pass the bound arguments to the function object + // with the right value category. + { + auto was_copied = [](CopyMoveInfo info) { return info.copy_kind == CopyMoveInfo::copy; }; + CopyMoveInfo info; + auto f = std::bind_back(was_copied, info); + assert(f()); + } + + { + auto was_moved = [](CopyMoveInfo info) { return info.copy_kind == CopyMoveInfo::move; }; + CopyMoveInfo info; + auto f = std::bind_back(was_moved, info); + assert(std::move(f)()); + } + } +} + +constexpr void test_function_objects() { + { // Make sure we call the correctly cv-ref qualified operator() + // based on the value category of the bind_back unspecified-type. + struct X { + constexpr int operator()() & { return 1; } + constexpr int operator()() const& { return 2; } + constexpr int operator()() && { return 3; } + constexpr int operator()() const&& { return 4; } + }; + + auto f = std::bind_back(X{}); + using F = decltype(f); + assert(static_cast(f)() == 1); + assert(static_cast(f)() == 2); + assert(static_cast(f)() == 3); + assert(static_cast(f)() == 4); + } + + // Make sure the `bind_back` unspecified-type does not model invocable + // when the call would select a differently-qualified operator(). + // + // For example, if the call to `operator()() &` is ill-formed, the call to the unspecified-type + // should be ill-formed and not fall back to the `operator()() const&` overload. + { // Make sure we delete the & overload when the underlying call isn't valid. + { + struct X { + void operator()() & = delete; + void operator()() const&; + void operator()() &&; + void operator()() const&&; + }; + + using F = decltype(std::bind_back(X{})); + static_assert(!std::invocable); + static_assert(std::invocable); + static_assert(std::invocable); + static_assert(std::invocable); + } + + // There's no way to make sure we delete the const& overload when the underlying call isn't valid, + // so we can't check this one. + + { // Make sure we delete the && overload when the underlying call isn't valid. + struct X { + void operator()() &; + void operator()() const&; + void operator()() && = delete; + void operator()() const&&; + }; + + using F = decltype(std::bind_back(X{})); + static_assert(std::invocable); + static_assert(std::invocable); + static_assert(!std::invocable); + static_assert(std::invocable); + } + + { // Make sure we delete the const&& overload when the underlying call isn't valid. + struct X { + void operator()() &; + void operator()() const&; + void operator()() &&; + void operator()() const&& = delete; + }; + + using F = decltype(std::bind_back(X{})); + static_assert(std::invocable); + static_assert(std::invocable); + static_assert(std::invocable); + static_assert(!std::invocable); + } + } + + { // Extra value category tests + struct X {}; + + { + struct Y { + void operator()(X&&) const&; + void operator()(X&&) && = delete; + }; + + using F = decltype(std::bind_back(Y{})); + static_assert(std::invocable); + static_assert(!std::invocable); + } + + { + struct Y { + void operator()(const X&) const; + void operator()(X&&) const = delete; + }; + + using F = decltype(std::bind_back(Y{}, X{})); + static_assert(std::invocable); + static_assert(!std::invocable); + } + } +} + +constexpr void test_return_type() { + { // Test properties of the constructor of the unspecified-type returned by bind_back. + { // Test move constructor when function is move only. + MoveOnlyCallable value(true); + auto f = std::bind_back(std::move(value), 1); + assert(f()); + assert(f(1, 2, 3)); + + auto f1 = std::move(f); + assert(!f()); + assert(f1()); + assert(f1(1, 2, 3)); + + using F = decltype(f); + static_assert(std::is_move_constructible::value); + static_assert(!std::is_copy_constructible::value); + static_assert(!std::is_move_assignable::value); + static_assert(!std::is_copy_assignable::value); + } + + { // Test move constructor when function is copyable but not assignable. + CopyCallable value(true); + auto f = std::bind_back(value, 1); + assert(f()); + assert(f(1, 2, 3)); + + auto f1 = std::move(f); + assert(!f()); + assert(f1()); + assert(f1(1, 2, 3)); + + auto f2 = std::bind_back(std::move(value), 1); + assert(f1()); + assert(f2()); + assert(f2(1, 2, 3)); + + using F = decltype(f); + static_assert(std::is_move_constructible::value); + static_assert(std::is_copy_constructible::value); + static_assert(!std::is_move_assignable::value); + static_assert(!std::is_copy_assignable::value); + } + + { // Test constructors when function is copy assignable. + using F = decltype(std::bind_back(std::declval(), 1)); + static_assert(std::is_move_constructible::value); + static_assert(std::is_copy_constructible::value); + static_assert(std::is_move_assignable::value); + static_assert(std::is_copy_assignable::value); + } + + { // Test constructors when function is move assignable only. + using F = decltype(std::bind_back(std::declval(), 1)); + static_assert(std::is_move_constructible::value); + static_assert(!std::is_copy_constructible::value); + static_assert(std::is_move_assignable::value); + static_assert(!std::is_copy_assignable::value); + } + } + + { // Make sure bind_back's unspecified type's operator() is SFINAE-friendly. + using F = decltype(std::bind_back(std::declval(), 1)); + static_assert(!std::is_invocable::value); + static_assert(std::is_invocable::value); + static_assert(!std::is_invocable::value); + static_assert(!std::is_invocable::value); + } +} + +constexpr bool test() { + test_basic_bindings(); + test_edge_cases(); + test_passing_arguments(); + test_function_objects(); + test_return_type(); + + return true; +} + +int main(int, char**) { + test(); + static_assert(test()); + + return 0; +} diff --git a/libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp b/libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp new file mode 100644 index 000000000000..eb100c15f580 --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/func.bind.partial/bind_back.verify.cpp @@ -0,0 +1,85 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 + +// + +// template +// constexpr unspecified bind_back(F&& f, Args&&... args); + +#include + +#include "types.h" + +constexpr int pass(int n) { return n; } + +void test() { + { // Test calling constexpr function from non-constexpr `bind_back` result + auto f1 = std::bind_back(pass, 1); + static_assert(f1() == 1); // expected-error {{static assertion expression is not an integral constant expression}} + } + + { // Test calling `bind_back` with template function + auto f1 = std::bind_back(do_nothing, 2); + // expected-error@-1 {{no matching function for call to 'bind_back'}} + } + + { // Mandates: is_constructible_v, F> + struct F { + F() = default; + F(const F&) = default; + F(F&) = delete; + + void operator()() {} + }; + + F f; + auto f1 = std::bind_back(f); + // expected-error-re@*:* {{static assertion failed{{.*}}bind_back requires decay_t to be constructible from F}} + } + + { // Mandates: is_move_constructible_v> + struct F { + F() = default; + F(const F&) = default; + F(F&&) = delete; + + void operator()() {} + }; + + F f; + auto f1 = std::bind_back(f); + // expected-error-re@*:* {{static assertion failed{{.*}}bind_back requires decay_t to be move constructible}} + } + + { // Mandates: (is_constructible_v, Args> && ...) + struct Arg { + Arg() = default; + Arg(const Arg&) = default; + Arg(Arg&) = delete; + }; + + Arg x; + auto f = std::bind_back([](const Arg&) {}, x); + // expected-error-re@*:* {{static assertion failed{{.*}}bind_back requires all decay_t to be constructible from respective Args}} + // expected-error@*:* {{no matching constructor for initialization}} + } + + { // Mandates: (is_move_constructible_v> && ...) + struct Arg { + Arg() = default; + Arg(const Arg&) = default; + Arg(Arg&&) = delete; + }; + + Arg x; + auto f = std::bind_back([](Arg&) {}, x); + // expected-error-re@*:* {{static assertion failed{{.*}}bind_back requires all decay_t to be move constructible}} + } +} diff --git a/libcxx/test/std/utilities/function.objects/func.bind.partial/types.h b/libcxx/test/std/utilities/function.objects/func.bind.partial/types.h new file mode 100644 index 000000000000..76ed4d478baa --- /dev/null +++ b/libcxx/test/std/utilities/function.objects/func.bind.partial/types.h @@ -0,0 +1,43 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef TEST_STD_UTILITIES_FUNCTION_OBJECTS_FUNC_BIND_PARTIAL_TYPES_H +#define TEST_STD_UTILITIES_FUNCTION_OBJECTS_FUNC_BIND_PARTIAL_TYPES_H + +#include +#include + +struct MakeTuple { + template + constexpr auto operator()(Args&&... args) const { + return std::make_tuple(std::forward(args)...); + } +}; + +template +struct Elem { + template + constexpr bool operator==(const Elem&) const { + return X == Y; + } +}; + +struct CopyMoveInfo { + enum { none, copy, move } copy_kind; + + constexpr CopyMoveInfo() : copy_kind(none) {} + constexpr CopyMoveInfo(const CopyMoveInfo&) : copy_kind(copy) {} + constexpr CopyMoveInfo(CopyMoveInfo&&) : copy_kind(move) {} +}; + +template +T do_nothing(T t) { + return t; +} + +#endif // TEST_STD_UTILITIES_FUNCTION_OBJECTS_FUNC_BIND_PARTIAL_TYPES_H diff --git a/libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.pass.cpp b/libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.pass.cpp index 6eb4e4a46e82..0dee6a95f60a 100644 --- a/libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.bind_front/bind_front.pass.cpp @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -142,12 +143,13 @@ constexpr bool test() { // Basic tests with fundamental types { - int n = 2; - int m = 1; - auto add = [](int x, int y) { return x + y; }; - auto addN = [](int a, int b, int c, int d, int e, int f) { - return a + b + c + d + e + f; - }; + int n = 2; + int m = 1; + int sum = 0; + auto add = [](int x, int y) { return x + y; }; + auto addN = [](int a, int b, int c, int d, int e, int f) { return a + b + c + d + e + f; }; + auto add_ref = [&](int x, int y) -> int& { return sum = x + y; }; + auto add_rref = [&](int x, int y) -> int&& { return std::move(sum = x + y); }; auto a = std::bind_front(add, m, n); assert(a() == 3); @@ -158,6 +160,14 @@ constexpr bool test() { auto c = std::bind_front(addN, n, m); assert(c(1, 1, 1, 1) == 7); + auto d = std::bind_front(add_ref, n, m); + std::same_as decltype(auto) dresult(d()); + assert(dresult == 3); + + auto e = std::bind_front(add_rref, n, m); + std::same_as decltype(auto) eresult(e()); + assert(eresult == 3); + auto f = std::bind_front(add, n); assert(f(3) == 5); @@ -166,6 +176,14 @@ constexpr bool test() { auto h = std::bind_front(addN, 1, 1, 1); assert(h(2, 2, 2) == 9); + + auto i = std::bind_front(add_ref, n); + std::same_as decltype(auto) iresult(i(5)); + assert(iresult == 7); + + auto j = std::bind_front(add_rref, m); + std::same_as decltype(auto) jresult(j(4)); + assert(jresult == 5); } // Make sure we don't treat std::reference_wrapper specially. diff --git a/libcxx/utils/generate_feature_test_macro_components.py b/libcxx/utils/generate_feature_test_macro_components.py index 759e49055be5..f2b8d55c0e11 100755 --- a/libcxx/utils/generate_feature_test_macro_components.py +++ b/libcxx/utils/generate_feature_test_macro_components.py @@ -211,10 +211,9 @@ feature_test_macros = [ "name": "__cpp_lib_bind_back", "values": { "c++23": 202202, - "c++26": 202306, # P2714R1 Bind front and back to NTTP callables + # "c++26": 202306, # P2714R1 Bind front and back to NTTP callables }, "headers": ["functional"], - "unimplemented": True, }, { "name": "__cpp_lib_bind_front", -- GitLab From fb8dbd1fb67ef4d1417f279df7f9a99b29468527 Mon Sep 17 00:00:00 2001 From: Sam Tebbs Date: Tue, 9 Apr 2024 16:17:27 +0100 Subject: [PATCH 287/695] [AArch64] Remove copy in SVE/SME predicate spill and fill (#81716) 7dc20ab introduced an extra COPY when spilling and filling a PNR register, which can't be elided as the input (PNR predicate) and output (PPR predicate) register classes differ. The patch adds a new register class that covers both PPR and PNR so that STR_PXI and LDR_PXI can take either of them, removing the need for the copy. --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 37 +++++----------- .../lib/Target/AArch64/AArch64RegisterInfo.td | 34 +++++++++----- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 +----- .../AArch64/AsmParser/AArch64AsmParser.cpp | 44 +++++++++++++++++-- .../Disassembler/AArch64Disassembler.cpp | 15 +++++++ llvm/lib/Target/AArch64/SMEInstrFormats.td | 15 +------ llvm/lib/Target/AArch64/SVEInstrFormats.td | 12 ++--- .../AArch64/GlobalISel/regbank-inlineasm.mir | 8 ++-- .../emit_fneg_with_non_register_operand.mir | 8 ++-- .../CodeGen/AArch64/peephole-insvigpr.mir | 4 +- llvm/test/CodeGen/AArch64/spillfill-sve.mir | 12 +++-- llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s | 2 +- 12 files changed, 115 insertions(+), 90 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 22687b0e31c2..9783b3321946 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -4807,29 +4807,20 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, if (AArch64::FPR8RegClass.hasSubClassEq(RC)) Opc = AArch64::STRBui; break; - case 2: + case 2: { + bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC); if (AArch64::FPR16RegClass.hasSubClassEq(RC)) Opc = AArch64::STRHui; - else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { + else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVEorSME() && "Unexpected register store without SVE store instructions"); - Opc = AArch64::STR_PXI; - StackID = TargetStackID::ScalableVector; - } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) { - assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) && + assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) && "Unexpected register store without SVE2p1 or SME2"); - if (SrcReg.isVirtual()) { - auto NewSrcReg = - MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass); - BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg) - .addReg(SrcReg); - SrcReg = NewSrcReg; - } else - SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0; Opc = AArch64::STR_PXI; StackID = TargetStackID::ScalableVector; } break; + } case 4: if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { Opc = AArch64::STRWui; @@ -4990,26 +4981,22 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, if (AArch64::FPR8RegClass.hasSubClassEq(RC)) Opc = AArch64::LDRBui; break; - case 2: + case 2: { + bool IsPNR = AArch64::PNRRegClass.hasSubClassEq(RC); if (AArch64::FPR16RegClass.hasSubClassEq(RC)) Opc = AArch64::LDRHui; - else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { + else if (IsPNR || AArch64::PPRRegClass.hasSubClassEq(RC)) { assert(Subtarget.hasSVEorSME() && "Unexpected register load without SVE load instructions"); - Opc = AArch64::LDR_PXI; - StackID = TargetStackID::ScalableVector; - } else if (AArch64::PNRRegClass.hasSubClassEq(RC)) { - assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) && + assert((!IsPNR || Subtarget.hasSVE2p1() || Subtarget.hasSME2()) && "Unexpected register load without SVE2p1 or SME2"); - PNRReg = DestReg; - if (DestReg.isVirtual()) - DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass); - else - DestReg = (DestReg - AArch64::PN0) + AArch64::P0; + if (IsPNR) + PNRReg = DestReg; Opc = AArch64::LDR_PXI; StackID = TargetStackID::ScalableVector; } break; + } case 4: if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { Opc = AArch64::LDRWui; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td index fef1748021b0..80d0f9c57f4b 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -953,17 +953,6 @@ class PNRAsmOperand: AsmOperandClass { let ParserMethod = "tryParseSVEPredicateVector"; } -let RenderMethod = "addPNRasPPRRegOperands" in { - def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>; - def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>; -} - -class PNRasPPRRegOp : SVERegOp {} - -def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>; -def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>; - def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>; def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>; def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>; @@ -1004,6 +993,29 @@ let Namespace = "AArch64" in { def psub1 : SubRegIndex<16, -1>; } +class PPRorPNRClass : RegisterClass< + "AArch64", + [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16, + (add PPR, PNR)> { + let Size = 16; +} + +class PPRorPNRAsmOperand: AsmOperandClass { + let Name = "SVE" # name # "Reg"; + let PredicateMethod = "isSVEPredicateOrPredicateAsCounterRegOfWidth<" + # Width # ", " # "AArch64::" + # RegClass # "RegClassID>"; + let DiagnosticType = "InvalidSVE" # name # "Reg"; + let RenderMethod = "addPPRorPNRRegOperands"; + let ParserMethod = "tryParseSVEPredicateOrPredicateAsCounterVector"; +} + +def PPRorPNR : PPRorPNRClass; +def PPRorPNRAsmOp8 : PPRorPNRAsmOperand<"PPRorPNRB", "PPRorPNR", 8>; +def PPRorPNRAsmOpAny : PPRorPNRAsmOperand<"PPRorPNRAny", "PPRorPNR", 0>; +def PPRorPNRAny : PPRRegOp<"", PPRorPNRAsmOpAny, ElementSizeNone, PPRorPNR>; +def PPRorPNR8 : PPRRegOp<"b", PPRorPNRAsmOp8, ElementSizeB, PPRorPNR>; + // Pairs of SVE predicate vector registers. def PSeqPairs : RegisterTuples<[psub0, psub1], [(rotl PPR, 0), (rotl PPR, 1)]>; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index a519d81362a7..9c747198c12d 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -4034,20 +4034,10 @@ let Predicates = [HasSVEorSME] in { // Aliases for existing SVE instructions for which predicate-as-counter are // accepted as an operand to the instruction -def : InstAlias<"ldr $Pt, [$Rn, $imm9, mul vl]", - (LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>; -def : InstAlias<"ldr $Pt, [$Rn]", - (LDR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>; - -def : InstAlias<"str $Pt, [$Rn, $imm9, mul vl]", - (STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), 0>; -def : InstAlias<"str $Pt, [$Rn]", - (STR_PXI PNRasPPRAny:$Pt, GPR64sp:$Rn, 0), 0>; - def : InstAlias<"mov $Pd, $Pn", - (ORR_PPzPP PNRasPPR8:$Pd, PNRasPPR8:$Pn, PNRasPPR8:$Pn, PNRasPPR8:$Pn), 0>; + (ORR_PPzPP PPRorPNR8:$Pd, PPRorPNR8:$Pn, PPRorPNR8:$Pn, PPRorPNR8:$Pn), 0>; -def : InstAlias<"pfalse\t$Pd", (PFALSE PNRasPPR8:$Pd), 0>; +def : InstAlias<"pfalse\t$Pd", (PFALSE PPRorPNR8:$Pd), 0>; } diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 21643ebb4138..a3b966aa6155 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -276,6 +276,8 @@ private: ParseStatus tryParseSVEDataVector(OperandVector &Operands); template ParseStatus tryParseSVEPredicateVector(OperandVector &Operands); + ParseStatus + tryParseSVEPredicateOrPredicateAsCounterVector(OperandVector &Operands); template ParseStatus tryParseVectorList(OperandVector &Operands, bool ExpectMatch = false); @@ -1241,6 +1243,7 @@ public: case AArch64::PPR_p8to15RegClassID: case AArch64::PNRRegClassID: case AArch64::PNR_p8to15RegClassID: + case AArch64::PPRorPNRRegClassID: RK = RegKind::SVEPredicateAsCounter; break; default: @@ -1264,6 +1267,7 @@ public: case AArch64::PPR_p8to15RegClassID: case AArch64::PNRRegClassID: case AArch64::PNR_p8to15RegClassID: + case AArch64::PPRorPNRRegClassID: RK = RegKind::SVEPredicateVector; break; default: @@ -1290,6 +1294,20 @@ public: return DiagnosticPredicateTy::NearMatch; } + template + DiagnosticPredicate isSVEPredicateOrPredicateAsCounterRegOfWidth() const { + if (Kind != k_Register || (Reg.Kind != RegKind::SVEPredicateAsCounter && + Reg.Kind != RegKind::SVEPredicateVector)) + return DiagnosticPredicateTy::NoMatch; + + if ((isSVEPredicateAsCounterReg() || + isSVEPredicateVectorRegOfWidth()) && + Reg.ElementWidth == ElementWidth) + return DiagnosticPredicateTy::Match; + + return DiagnosticPredicateTy::NearMatch; + } + template DiagnosticPredicate isSVEPredicateAsCounterRegOfWidth() const { if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateAsCounter) @@ -1770,6 +1788,15 @@ public: Inst.addOperand(MCOperand::createReg(AArch64::Z0 + getReg() - Base)); } + void addPPRorPNRRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + unsigned Reg = getReg(); + // Normalise to PPR + if (Reg >= AArch64::PN0 && Reg <= AArch64::PN15) + Reg = Reg - AArch64::PN0 + AArch64::P0; + Inst.addOperand(MCOperand::createReg(Reg)); + } + void addPNRasPPRRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand( @@ -4167,6 +4194,15 @@ ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg, return ParseStatus::NoMatch; } +ParseStatus AArch64AsmParser::tryParseSVEPredicateOrPredicateAsCounterVector( + OperandVector &Operands) { + ParseStatus Status = + tryParseSVEPredicateVector(Operands); + if (!Status.isSuccess()) + Status = tryParseSVEPredicateVector(Operands); + return Status; +} + /// tryParseSVEPredicateVector - Parse a SVE predicate register operand. template ParseStatus @@ -6019,6 +6055,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, return Error(Loc, "Invalid restricted vector register, expected z0.d..z15.d"); case Match_InvalidSVEPattern: return Error(Loc, "invalid predicate pattern"); + case Match_InvalidSVEPPRorPNRAnyReg: + case Match_InvalidSVEPPRorPNRBReg: case Match_InvalidSVEPredicateAnyReg: case Match_InvalidSVEPredicateBReg: case Match_InvalidSVEPredicateHReg: @@ -6131,9 +6169,6 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode, case Match_AddSubLSLImm3ShiftLarge: return Error(Loc, "expected 'lsl' with optional integer in range [0, 7]"); - case Match_InvalidSVEPNRasPPRPredicateBReg: - return Error(Loc, - "Expected predicate-as-counter register name with .B suffix"); default: llvm_unreachable("unexpected error code!"); } @@ -6653,6 +6688,8 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidZPR_4b16: case Match_InvalidZPR_4b32: case Match_InvalidZPR_4b64: + case Match_InvalidSVEPPRorPNRAnyReg: + case Match_InvalidSVEPPRorPNRBReg: case Match_InvalidSVEPredicateAnyReg: case Match_InvalidSVEPattern: case Match_InvalidSVEVecLenSpecifier: @@ -6714,7 +6751,6 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidSVEVectorListStrided4x16: case Match_InvalidSVEVectorListStrided4x32: case Match_InvalidSVEVectorListStrided4x64: - case Match_InvalidSVEPNRasPPRPredicateBReg: case Match_MSR: case Match_MRS: { if (ErrorInfo >= Operands.size()) diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index a21b4b77166e..ddb875e73ff5 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -143,6 +143,9 @@ DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder); +static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Addr, + const MCDisassembler *Decoder); static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder); @@ -741,6 +744,18 @@ static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, return Success; } +static DecodeStatus DecodePPRorPNRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Addr, + const MCDisassembler *Decoder) { + if (RegNo > 15) + return Fail; + + unsigned Register = + AArch64MCRegisterClasses[AArch64::PPRorPNRRegClassID].getRegister(RegNo); + Inst.addOperand(MCOperand::createReg(Register)); + return Success; +} + static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 44d9a8ac7cb6..3363aab4b093 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -1301,7 +1301,7 @@ multiclass sve2_clamp { } class sve2_int_perm_sel_p - : I<(outs PPRAny:$Pd), (ins PPRAny:$Pn, ppr_ty:$Pm, + : I<(outs PPRorPNRAny:$Pd), (ins PPRorPNRAny:$Pn, ppr_ty:$Pm, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), asm, "\t$Pd, $Pn, $Pm[$Rv, $imm]", "", []>, Sched<[]> { @@ -1345,19 +1345,6 @@ multiclass sve2_int_perm_sel_p { let Inst{20-18} = 0b000; } - def : InstAlias(NAME # _B) PNRasPPRAny:$Pd, - PNRasPPRAny:$Pn, PPR8:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm), 0>; - def : InstAlias(NAME # _H) PNRasPPRAny:$Pd, - PNRasPPRAny:$Pn, PPR16:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm), 0>; - def : InstAlias(NAME # _S) PNRasPPRAny:$Pd, - PNRasPPRAny:$Pn, PPR32:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm), 0>; - def : InstAlias(NAME # _D) PNRasPPRAny:$Pd, - PNRasPPRAny:$Pn, PPR64:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm), 0>; - def : Pat<(nxv16i1 (op (nxv16i1 PPRAny:$Pn), (nxv16i1 PPR8:$Pm), MatrixIndexGPR32Op12_15:$idx)), (!cast(NAME # _B) $Pn, $Pm, $idx, 0)>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index ee8292fdd883..fb0c6188edb3 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -729,7 +729,7 @@ let hasNoSchedulingInfo = 1 in { //===----------------------------------------------------------------------===// class sve_int_pfalse opc, string asm> -: I<(outs PPR8:$Pd), (ins), +: I<(outs PPRorPNR8:$Pd), (ins), asm, "\t$Pd", "", []>, Sched<[]> { @@ -1837,7 +1837,7 @@ multiclass sve_int_sel_vvv { //===----------------------------------------------------------------------===// class sve_int_pred_log opc, string asm> -: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm), +: I<(outs PPRorPNR8:$Pd), (ins PPRorPNRAny:$Pg, PPRorPNR8:$Pn, PPRorPNR8:$Pm), asm, "\t$Pd, $Pg/z, $Pn, $Pm", "", []>, Sched<[]> { @@ -6664,7 +6664,7 @@ multiclass sve_mem_z_spill { } class sve_mem_p_spill -: I<(outs), (ins PPRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), +: I<(outs), (ins PPRorPNRAny:$Pt, GPR64sp:$Rn, simm9:$imm9), asm, "\t$Pt, [$Rn, $imm9, mul vl]", "", []>, Sched<[]> { @@ -6687,7 +6687,7 @@ multiclass sve_mem_p_spill { def NAME : sve_mem_p_spill; def : InstAlias(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; + (!cast(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>; } //===----------------------------------------------------------------------===// @@ -7833,7 +7833,7 @@ multiclass sve_mem_z_fill { } class sve_mem_p_fill -: I<(outs PPRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), +: I<(outs PPRorPNRAny:$Pt), (ins GPR64sp:$Rn, simm9:$imm9), asm, "\t$Pt, [$Rn, $imm9, mul vl]", "", []>, Sched<[]> { @@ -7856,7 +7856,7 @@ multiclass sve_mem_p_fill { def NAME : sve_mem_p_fill; def : InstAlias(NAME) PPRAny:$Pt, GPR64sp:$Rn, 0), 1>; + (!cast(NAME) PPRorPNRAny:$Pt, GPR64sp:$Rn, 0), 1>; } class sve2_mem_gldnt_vs_base opc, dag iops, string asm, diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir index e77fac19e0a7..2ffb78568068 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir @@ -57,11 +57,11 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: inlineasm_virt_reg_output - ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0 + ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0 ; CHECK-NEXT: $w0 = COPY [[COPY]](s32) ; CHECK-NEXT: RET_ReallyLR implicit $w0 - INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common + INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common %1:_(s32) = COPY %0 $w0 = COPY %1(s32) RET_ReallyLR implicit $w0 @@ -75,12 +75,12 @@ tracksRegLiveness: true body: | bb.1: ; CHECK-LABEL: name: inlineasm_virt_mixed_types - ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:PPR2_with_psub_in_PNR_3b_and_PPR2_with_psub1_in_PPR_p8to15 */, def %0, 2162698 /* regdef:WSeqPairsClass */, def %1 + ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0, {{[0-9]+}} /* regdef:FPR64 */, def %1 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1 ; CHECK-NEXT: $d0 = COPY [[COPY1]](s64) ; CHECK-NEXT: RET_ReallyLR implicit $d0 - INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1310730 /* regdef:GPR32common */, def %0:gpr32common, 2162698 /* regdef:FPR64 */, def %1:fpr64 + INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 1769482 /* regdef:GPR32common */, def %0:gpr32common, 2621450 /* regdef:FPR64 */, def %1:fpr64 %3:_(s32) = COPY %0 %4:_(s64) = COPY %1 $d0 = COPY %4(s64) diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir index 92fb053b0db7..2be7aba2a3df 100644 --- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir +++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir @@ -91,10 +91,10 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c ; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c) - ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3) + ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3) ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2 ; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c) - ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3) + ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3) ; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2 ; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr ; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv @@ -111,10 +111,10 @@ body: | %6:gpr64common = LOADgot target-flags(aarch64-got) @c %3:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c) - INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3) + INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3) %0:fpr64 = COPY %2 %5:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c) - INLINEASM &"", 1 /* sideeffect attdialect */, 2359306 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3) + INLINEASM &"", 1 /* sideeffect attdialect */, 2621450 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3) %7:fpr64 = FNEGDr %2 nofpexcept FCMPDrr %4, killed %7, implicit-def $nzcv, implicit $fpcr Bcc 1, %bb.2, implicit $nzcv diff --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir index 65148344096c..5dd29cf39c0e 100644 --- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir +++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir @@ -487,7 +487,7 @@ body: | ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]] - ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, {{[0-9]+}} /* regdef:WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15 */, def %1, 262158 /* mem:m */, killed [[COPY1]] + ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2621450 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]] ; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF @@ -505,7 +505,7 @@ body: | %0:gpr64common = COPY $x0 %2:gpr64all = IMPLICIT_DEF %3:gpr64sp = COPY %2 - INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2359306 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3 + INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 2621450 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3 %4:fpr128 = MOVIv2d_ns 0 %5:fpr64 = COPY %4.dsub %7:fpr128 = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AArch64/spillfill-sve.mir b/llvm/test/CodeGen/AArch64/spillfill-sve.mir index ef7d55a1c239..11cf388e3853 100644 --- a/llvm/test/CodeGen/AArch64/spillfill-sve.mir +++ b/llvm/test/CodeGen/AArch64/spillfill-sve.mir @@ -1,5 +1,5 @@ # RUN: llc -mtriple=aarch64-linux-gnu -run-pass=greedy %s -o - | FileCheck %s -# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy -stop-after=aarch64-expand-pseudo %s -o - | FileCheck %s --check-prefix=EXPAND +# RUN: llc -mtriple=aarch64-linux-gnu -start-before=greedy -stop-after=aarch64-expand-pseudo -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=EXPAND --- | ; ModuleID = '' source_filename = "" @@ -173,8 +173,8 @@ body: | ; CHECK-NEXT: stack-id: scalable-vector, callee-saved-register: '' ; EXPAND-LABEL: name: spills_fills_stack_id_pnr - ; EXPAND: STR_PXI $p0, $sp, 7 - ; EXPAND: $p0 = LDR_PXI $sp, 7, implicit-def $pn0 + ; EXPAND: STR_PXI $pn0, $sp, 7 + ; EXPAND: $pn0 = LDR_PXI $sp, 7, implicit-def $pn0 %0:pnr = COPY $pn0 @@ -213,11 +213,9 @@ body: | ; EXPAND-LABEL: name: spills_fills_stack_id_virtreg_pnr ; EXPAND: renamable $pn8 = WHILEGE_CXX_B - ; EXPAND: $p0 = ORR_PPzPP $p8, $p8, killed $p8 - ; EXPAND: STR_PXI killed renamable $p0, $sp, 7 + ; EXPAND: STR_PXI killed renamable $pn8, $sp, 7 ; - ; EXPAND: renamable $p0 = LDR_PXI $sp, 7 - ; EXPAND: $p8 = ORR_PPzPP $p0, $p0, killed $p0, implicit-def $pn8 + ; EXPAND: renamable $pn8 = LDR_PXI $sp, 7 ; EXPAND: $p0 = PEXT_PCI_B killed renamable $pn8, 0 diff --git a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s index f4d95c5910d8..e44453b4c326 100644 --- a/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s @@ -17,6 +17,6 @@ pfalse pn16.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: pfalse pn5.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Expected predicate-as-counter register name with .B suffix +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register // CHECK-NEXT: pfalse pn5.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -- GitLab From 93f0880869419ffa3c7bb66b178f2453ea9d2bed Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Tue, 9 Apr 2024 15:22:05 +0000 Subject: [PATCH 288/695] [bazel][clang] Remove gen-clang-*-left-list attributes from tablegen For both 9391ff8c86007562d40c240ea082b7c0cbf35947 and a30662fc2acdd73ca1a9217716299a4676999fb4. --- utils/bazel/llvm-project-overlay/clang/BUILD.bazel | 8 -------- 1 file changed, 8 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index a69894ea7a40..2c3c39e5b53d 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -736,14 +736,6 @@ gentbl( "-gen-clang-attr-impl", "include/clang/AST/AttrImpl.inc", ), - ( - "-gen-clang-attr-can-print-left-list", - "include/clang/Basic/AttrLeftSideCanPrintList.inc", - ), - ( - "-gen-clang-attr-must-print-left-list", - "include/clang/Basic/AttrLeftSideMustPrintList.inc", - ), ], tblgen = ":clang-tblgen", td_file = "include/clang/Basic/Attr.td", -- GitLab From 568ec1340c1260c36a490d10c38366ed00f63209 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Tue, 9 Apr 2024 08:25:41 -0700 Subject: [PATCH 289/695] [memprof] Use structured binding (NFC) (#88096) --- llvm/lib/ProfileData/InstrProfWriter.cpp | 8 ++++---- llvm/lib/ProfileData/RawMemProfReader.cpp | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp index 1e0159dd1e6f..7c56cde3e6ce 100644 --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -433,9 +433,9 @@ static uint64_t writeMemProfRecords( RecordWriter->Schema = Schema; OnDiskChainedHashTableGenerator RecordTableGenerator; - for (auto &I : MemProfRecordData) { + for (auto &[GUID, Record] : MemProfRecordData) { // Insert the key (func hash) and value (memprof record). - RecordTableGenerator.insert(I.first, I.second, *RecordWriter.get()); + RecordTableGenerator.insert(GUID, Record, *RecordWriter.get()); } // Release the memory of this MapVector as it is no longer needed. MemProfRecordData.clear(); @@ -453,9 +453,9 @@ static uint64_t writeMemProfFrames( auto FrameWriter = std::make_unique(); OnDiskChainedHashTableGenerator FrameTableGenerator; - for (auto &I : MemProfFrameData) { + for (auto &[FrameId, Frame] : MemProfFrameData) { // Insert the key (frame id) and value (frame contents). - FrameTableGenerator.insert(I.first, I.second); + FrameTableGenerator.insert(FrameId, Frame); } // Release the memory of this MapVector as it is no longer needed. MemProfFrameData.clear(); diff --git a/llvm/lib/ProfileData/RawMemProfReader.cpp b/llvm/lib/ProfileData/RawMemProfReader.cpp index 5dc1ff897815..e93fbc72f54e 100644 --- a/llvm/lib/ProfileData/RawMemProfReader.cpp +++ b/llvm/lib/ProfileData/RawMemProfReader.cpp @@ -614,11 +614,11 @@ Error RawMemProfReader::readRawProfile( // Read in the MemInfoBlocks. Merge them based on stack id - we assume that // raw profiles in the same binary file are from the same process so the // stackdepot ids are the same. - for (const auto &Value : readMemInfoBlocks(Next + Header->MIBOffset)) { - if (CallstackProfileData.count(Value.first)) { - CallstackProfileData[Value.first].Merge(Value.second); + for (const auto &[Id, MIB] : readMemInfoBlocks(Next + Header->MIBOffset)) { + if (CallstackProfileData.count(Id)) { + CallstackProfileData[Id].Merge(MIB); } else { - CallstackProfileData[Value.first] = Value.second; + CallstackProfileData[Id] = MIB; } } -- GitLab From e280407a4865542c4bb6cfa148edbe1ea67023d6 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 9 Apr 2024 11:27:40 -0400 Subject: [PATCH 290/695] [libc++] Add test coverage for our implementation of LWG4031 (#87508) This was actually already implemented in the initial version of std::expected, but this patch adds test coverage and makes it more explicit that we intend to make these functions noexcept. --- libcxx/docs/Status/Cxx2cIssues.csv | 2 +- .../include/__expected/bad_expected_access.h | 12 +-- ...compile.pass.cpp => base.compile.pass.cpp} | 17 ++-- .../expected.bad/void-specialization.pass.cpp | 83 +++++++++++++++++++ .../expected/expected.bad/what.pass.cpp | 35 ++++++++ 5 files changed, 130 insertions(+), 19 deletions(-) rename libcxx/test/std/utilities/expected/expected.bad/{what.noexcept.compile.pass.cpp => base.compile.pass.cpp} (56%) create mode 100644 libcxx/test/std/utilities/expected/expected.bad/void-specialization.pass.cpp create mode 100644 libcxx/test/std/utilities/expected/expected.bad/what.pass.cpp diff --git a/libcxx/docs/Status/Cxx2cIssues.csv b/libcxx/docs/Status/Cxx2cIssues.csv index 8a4bf2ef6216..b402fb835bc1 100644 --- a/libcxx/docs/Status/Cxx2cIssues.csv +++ b/libcxx/docs/Status/Cxx2cIssues.csv @@ -52,7 +52,7 @@ "`4023 `__","Preconditions of ``std::basic_streambuf::setg/setp``","Tokyo March 2024","","","" "`4025 `__","Move assignment operator of ``std::expected`` should not be conditionally deleted","Tokyo March 2024","","","" "`4030 `__","Clarify whether arithmetic expressions in ``[numeric.sat.func]`` are mathematical or C++","Tokyo March 2024","|Nothing To Do|","","" -"`4031 `__","``bad_expected_access`` member functions should be ``noexcept``","Tokyo March 2024","","","" +"`4031 `__","``bad_expected_access`` member functions should be ``noexcept``","Tokyo March 2024","|Complete|","16.0","" "`4035 `__","``single_view`` should provide ``empty``","Tokyo March 2024","","","|ranges|" "`4036 `__","``__alignof_is_defined`` is only implicitly specified in C++ and not yet deprecated","Tokyo March 2024","","","" "`4037 `__","Static data members of ``ctype_base`` are not yet required to be usable in constant expressions","Tokyo March 2024","","","" diff --git a/libcxx/include/__expected/bad_expected_access.h b/libcxx/include/__expected/bad_expected_access.h index 585b4ec9a053..9d490307b680 100644 --- a/libcxx/include/__expected/bad_expected_access.h +++ b/libcxx/include/__expected/bad_expected_access.h @@ -32,12 +32,12 @@ _LIBCPP_CLANG_DIAGNOSTIC_IGNORED("-Wweak-vtables") template <> class bad_expected_access : public exception { protected: - _LIBCPP_HIDE_FROM_ABI bad_expected_access() noexcept = default; - _LIBCPP_HIDE_FROM_ABI bad_expected_access(const bad_expected_access&) = default; - _LIBCPP_HIDE_FROM_ABI bad_expected_access(bad_expected_access&&) = default; - _LIBCPP_HIDE_FROM_ABI bad_expected_access& operator=(const bad_expected_access&) = default; - _LIBCPP_HIDE_FROM_ABI bad_expected_access& operator=(bad_expected_access&&) = default; - _LIBCPP_HIDE_FROM_ABI_VIRTUAL ~bad_expected_access() override = default; + _LIBCPP_HIDE_FROM_ABI bad_expected_access() noexcept = default; + _LIBCPP_HIDE_FROM_ABI bad_expected_access(const bad_expected_access&) noexcept = default; + _LIBCPP_HIDE_FROM_ABI bad_expected_access(bad_expected_access&&) noexcept = default; + _LIBCPP_HIDE_FROM_ABI bad_expected_access& operator=(const bad_expected_access&) noexcept = default; + _LIBCPP_HIDE_FROM_ABI bad_expected_access& operator=(bad_expected_access&&) noexcept = default; + _LIBCPP_HIDE_FROM_ABI_VIRTUAL ~bad_expected_access() override = default; public: // The way this has been designed (by using a class template below) means that we'll already diff --git a/libcxx/test/std/utilities/expected/expected.bad/what.noexcept.compile.pass.cpp b/libcxx/test/std/utilities/expected/expected.bad/base.compile.pass.cpp similarity index 56% rename from libcxx/test/std/utilities/expected/expected.bad/what.noexcept.compile.pass.cpp rename to libcxx/test/std/utilities/expected/expected.bad/base.compile.pass.cpp index e6d050b2129d..545215a3b161 100644 --- a/libcxx/test/std/utilities/expected/expected.bad/what.noexcept.compile.pass.cpp +++ b/libcxx/test/std/utilities/expected/expected.bad/base.compile.pass.cpp @@ -7,19 +7,12 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 -// const char* what() const noexcept override; +// Make sure std::bad_expected_access inherits from std::bad_expected_access. #include -#include +#include -template -concept WhatNoexcept = - requires(const T& t) { - { t.what() } noexcept; - }; +struct Foo {}; -struct foo{}; - -static_assert(!WhatNoexcept); -static_assert(WhatNoexcept>); -static_assert(WhatNoexcept>); +static_assert(std::is_base_of_v, std::bad_expected_access>); +static_assert(std::is_base_of_v, std::bad_expected_access>); diff --git a/libcxx/test/std/utilities/expected/expected.bad/void-specialization.pass.cpp b/libcxx/test/std/utilities/expected/expected.bad/void-specialization.pass.cpp new file mode 100644 index 000000000000..092e1153103c --- /dev/null +++ b/libcxx/test/std/utilities/expected/expected.bad/void-specialization.pass.cpp @@ -0,0 +1,83 @@ +//===----------------------------------------------------------------------===// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 + +// template<> +// class bad_expected_access : public exception { +// protected: +// bad_expected_access() noexcept; +// bad_expected_access(const bad_expected_access&) noexcept; +// bad_expected_access(bad_expected_access&&) noexcept; +// bad_expected_access& operator=(const bad_expected_access&) noexcept; +// bad_expected_access& operator=(bad_expected_access&&) noexcept; +// ~bad_expected_access(); +// +// public: +// const char* what() const noexcept override; +// }; + +#include +#include +#include +#include +#include + +#include "test_macros.h" + +struct Inherit : std::bad_expected_access {}; + +int main(int, char**) { + // base class + static_assert(std::is_base_of_v>); + + // default constructor + { + Inherit exc; + ASSERT_NOEXCEPT(Inherit()); + } + + // copy constructor + { + Inherit exc; + Inherit copy(exc); + ASSERT_NOEXCEPT(Inherit(exc)); + } + + // move constructor + { + Inherit exc; + Inherit copy(std::move(exc)); + ASSERT_NOEXCEPT(Inherit(std::move(exc))); + } + + // copy assignment + { + Inherit exc; + Inherit copy; + [[maybe_unused]] Inherit& result = (copy = exc); + ASSERT_NOEXCEPT(copy = exc); + } + + // move assignment + { + Inherit exc; + Inherit copy; + [[maybe_unused]] Inherit& result = (copy = std::move(exc)); + ASSERT_NOEXCEPT(copy = std::move(exc)); + } + + // what() + { + Inherit exc; + char const* what = exc.what(); + assert(what != nullptr); + ASSERT_NOEXCEPT(exc.what()); + } + + return 0; +} diff --git a/libcxx/test/std/utilities/expected/expected.bad/what.pass.cpp b/libcxx/test/std/utilities/expected/expected.bad/what.pass.cpp new file mode 100644 index 000000000000..bc5e356161a7 --- /dev/null +++ b/libcxx/test/std/utilities/expected/expected.bad/what.pass.cpp @@ -0,0 +1,35 @@ +//===----------------------------------------------------------------------===// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 + +// const char* what() const noexcept override; + +#include +#include +#include + +#include "test_macros.h" + +struct Foo {}; + +int main(int, char**) { + { + std::bad_expected_access const exc(99); + char const* what = exc.what(); + assert(what != nullptr); + ASSERT_NOEXCEPT(exc.what()); + } + { + std::bad_expected_access const exc(Foo{}); + char const* what = exc.what(); + assert(what != nullptr); + ASSERT_NOEXCEPT(exc.what()); + } + + return 0; +} -- GitLab From 4ac2721e51131b3a160fee5ae0fcbd695d090e86 Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 9 Apr 2024 16:36:08 +0100 Subject: [PATCH 291/695] [AArch64] Add costs for ST3 and ST4 instructions, modelled as store(shuffle). (#87934) This tries to add some costs for the shuffle in a ST3/ST4 instruction, which are represented in LLVM IR as store(interleaving shuffle). In order to detect the store, it needs to add a CxtI context instruction to check the users of the shuffle. LD3 and LD4 are added, LD2 should be a zip1 shuffle, which will be added in another patch. It should help fix some of the regressions from #87510. --- .../llvm/Analysis/TargetTransformInfo.h | 26 +++++------ .../llvm/Analysis/TargetTransformInfoImpl.h | 44 +++++++++++-------- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 3 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 6 +-- .../AArch64/AArch64TargetTransformInfo.cpp | 28 ++++++++---- .../AArch64/AArch64TargetTransformInfo.h | 3 +- .../AMDGPU/AMDGPUTargetTransformInfo.cpp | 3 +- .../Target/AMDGPU/AMDGPUTargetTransformInfo.h | 3 +- .../lib/Target/ARM/ARMTargetTransformInfo.cpp | 3 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 3 +- .../Hexagon/HexagonTargetTransformInfo.cpp | 3 +- .../Hexagon/HexagonTargetTransformInfo.h | 3 +- .../Target/PowerPC/PPCTargetTransformInfo.cpp | 3 +- .../Target/PowerPC/PPCTargetTransformInfo.h | 3 +- .../Target/RISCV/RISCVTargetTransformInfo.cpp | 3 +- .../Target/RISCV/RISCVTargetTransformInfo.h | 3 +- .../SystemZ/SystemZTargetTransformInfo.cpp | 10 ++--- .../SystemZ/SystemZTargetTransformInfo.h | 3 +- .../lib/Target/X86/X86TargetTransformInfo.cpp | 10 ++--- llvm/lib/Target/X86/X86TargetTransformInfo.h | 3 +- .../Transforms/Vectorize/VectorCombine.cpp | 5 ++- .../CostModel/AArch64/shuffle-store.ll | 42 +++++++++--------- 22 files changed, 121 insertions(+), 92 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index fa9392b86c15..58c69ac93976 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1291,12 +1291,11 @@ public: /// passed through \p Args, which helps improve the cost estimation in some /// cases, like in broadcast loads. /// NOTE: For subvector extractions Tp represents the source type. - InstructionCost - getShuffleCost(ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask = std::nullopt, - TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, - int Index = 0, VectorType *SubTp = nullptr, - ArrayRef Args = std::nullopt) const; + InstructionCost getShuffleCost( + ShuffleKind Kind, VectorType *Tp, ArrayRef Mask = std::nullopt, + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, int Index = 0, + VectorType *SubTp = nullptr, ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr) const; /// Represents a hint about the context in which a cast is used. /// @@ -2008,11 +2007,10 @@ public: const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const = 0; - virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, - int Index, VectorType *SubTp, - ArrayRef Args) = 0; + virtual InstructionCost + getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args, const Instruction *CxtI) = 0; virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH, TTI::TargetCostKind CostKind, @@ -2647,8 +2645,10 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args) override { - return Impl.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args); + ArrayRef Args, + const Instruction *CxtI) override { + return Impl.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args, + CxtI); } InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH, diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 63c2ef8912b2..5b40e4971406 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -579,10 +579,12 @@ public: return InstructionCost::getInvalid(); } - InstructionCost - getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef Mask, - TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt) const { + InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, + ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, + VectorType *SubTp, + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr) const { return 1; } @@ -1341,13 +1343,13 @@ public: if (Shuffle->isExtractSubvectorMask(SubIndex)) return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy, Mask, CostKind, SubIndex, VecTy, - Operands); + Operands, Shuffle); if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) return TargetTTI->getShuffleCost( TTI::SK_InsertSubvector, VecTy, Mask, CostKind, SubIndex, FixedVectorType::get(VecTy->getScalarType(), NumSubElts), - Operands); + Operands, Shuffle); int ReplicationFactor, VF; if (Shuffle->isReplicationMask(ReplicationFactor, VF)) { @@ -1374,7 +1376,7 @@ public: return TargetTTI->getShuffleCost( IsUnary ? TTI::SK_PermuteSingleSrc : TTI::SK_PermuteTwoSrc, VecTy, - AdjustMask, CostKind, 0, nullptr); + AdjustMask, CostKind, 0, nullptr, {}, Shuffle); } // Narrowing shuffle - perform shuffle at original wider width and @@ -1383,13 +1385,13 @@ public: InstructionCost ShuffleCost = TargetTTI->getShuffleCost( IsUnary ? TTI::SK_PermuteSingleSrc : TTI::SK_PermuteTwoSrc, - VecSrcTy, AdjustMask, CostKind, 0, nullptr); + VecSrcTy, AdjustMask, CostKind, 0, nullptr, {}, Shuffle); SmallVector ExtractMask(Mask.size()); std::iota(ExtractMask.begin(), ExtractMask.end(), 0); - return ShuffleCost + TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, - VecSrcTy, ExtractMask, - CostKind, 0, VecTy); + return ShuffleCost + TargetTTI->getShuffleCost( + TTI::SK_ExtractSubvector, VecSrcTy, + ExtractMask, CostKind, 0, VecTy, {}, Shuffle); } if (Shuffle->isIdentity()) @@ -1397,35 +1399,39 @@ public: if (Shuffle->isReverse()) return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy, Mask, CostKind, - 0, nullptr, Operands); + 0, nullptr, Operands, Shuffle); if (Shuffle->isSelect()) return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy, Mask, CostKind, - 0, nullptr, Operands); + 0, nullptr, Operands, Shuffle); if (Shuffle->isTranspose()) return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy, Mask, - CostKind, 0, nullptr, Operands); + CostKind, 0, nullptr, Operands, + Shuffle); if (Shuffle->isZeroEltSplat()) return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy, Mask, - CostKind, 0, nullptr, Operands); + CostKind, 0, nullptr, Operands, + Shuffle); if (Shuffle->isSingleSource()) return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy, Mask, - CostKind, 0, nullptr, Operands); + CostKind, 0, nullptr, Operands, + Shuffle); if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex)) return TargetTTI->getShuffleCost( TTI::SK_InsertSubvector, VecTy, Mask, CostKind, SubIndex, - FixedVectorType::get(VecTy->getScalarType(), NumSubElts), Operands); + FixedVectorType::get(VecTy->getScalarType(), NumSubElts), Operands, + Shuffle); if (Shuffle->isSplice(SubIndex)) return TargetTTI->getShuffleCost(TTI::SK_Splice, VecTy, Mask, CostKind, - SubIndex, nullptr, Operands); + SubIndex, nullptr, Operands, Shuffle); return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy, Mask, - CostKind, 0, nullptr, Operands); + CostKind, 0, nullptr, Operands, Shuffle); } case Instruction::ExtractElement: { auto *EEI = dyn_cast(U); diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index 2a5638dd1d3c..06a19c75cf87 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -1018,7 +1018,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt) { + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr) { switch (improveShuffleKindFromMask(Kind, Mask, Tp, Index, SubTp)) { case TTI::SK_Broadcast: if (auto *FVT = dyn_cast(Tp)) diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 5f933b458784..33c899fe8899 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -916,9 +916,9 @@ InstructionCost TargetTransformInfo::getAltInstrCost( InstructionCost TargetTransformInfo::getShuffleCost( ShuffleKind Kind, VectorType *Ty, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args) const { - InstructionCost Cost = - TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind, Index, SubTp, Args); + ArrayRef Args, const Instruction *CxtI) const { + InstructionCost Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, CostKind, + Index, SubTp, Args, CxtI); assert(Cost >= 0 && "TTI should not produce negative costs!"); return Cost; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index ee7137b92445..fc48338628b3 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -3815,18 +3815,29 @@ InstructionCost AArch64TTIImpl::getSpliceCost(VectorType *Tp, int Index) { return LegalizationCost * LT.first; } -InstructionCost AArch64TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, - VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, - int Index, VectorType *SubTp, - ArrayRef Args) { +InstructionCost AArch64TTIImpl::getShuffleCost( + TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args, const Instruction *CxtI) { std::pair LT = getTypeLegalizationCost(Tp); + // If we have a Mask, and the LT is being legalized somehow, split the Mask // into smaller vectors and sum the cost of each shuffle. if (!Mask.empty() && isa(Tp) && LT.second.isVector() && Tp->getScalarSizeInBits() == LT.second.getScalarSizeInBits() && Mask.size() > LT.second.getVectorNumElements() && !Index && !SubTp) { + + // Check for ST3/ST4 instructions, which are represented in llvm IR as + // store(interleaving-shuffle). The shuffle cost could potentially be free, + // but we model it with a cost of LT.first so that LD3/LD3 have a higher + // cost than just the store. + if (CxtI && CxtI->hasOneUse() && isa(*CxtI->user_begin()) && + (ShuffleVectorInst::isInterleaveMask( + Mask, 4, Tp->getElementCount().getKnownMinValue() * 2) || + ShuffleVectorInst::isInterleaveMask( + Mask, 3, Tp->getElementCount().getKnownMinValue() * 2))) + return LT.first; + unsigned TpNumElts = Mask.size(); unsigned LTNumElts = LT.second.getVectorNumElements(); unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; @@ -3874,7 +3885,7 @@ InstructionCost AArch64TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, if (NumSources <= 2) Cost += getShuffleCost(NumSources <= 1 ? TTI::SK_PermuteSingleSrc : TTI::SK_PermuteTwoSrc, - NTp, NMask, CostKind, 0, nullptr, Args); + NTp, NMask, CostKind, 0, nullptr, Args, CxtI); else if (any_of(enumerate(NMask), [&](const auto &ME) { return ME.value() % LTNumElts == ME.index(); })) @@ -4055,7 +4066,8 @@ InstructionCost AArch64TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, // Restore optimal kind. if (IsExtractSubvector) Kind = TTI::SK_ExtractSubvector; - return BaseT::getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp); + return BaseT::getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args, + CxtI); } static bool containsDecreasingPointers(Loop *TheLoop, diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index de39dea2be43..dba384481f6a 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -393,7 +393,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp index 31077dbc0b2c..84320d296a03 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp @@ -1127,7 +1127,8 @@ InstructionCost GCNTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *VT, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args) { + ArrayRef Args, + const Instruction *CxtI) { Kind = improveShuffleKindFromMask(Kind, Mask, VT, Index, SubTp); // Treat extractsubvector as single op permutation. bool IsExtractSubvector = Kind == TTI::SK_ExtractSubvector; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index cd8e9fd10bbf..0dab3a982779 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -234,7 +234,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); bool areInlineCompatible(const Function *Caller, const Function *Callee) const; diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 3be894ad3bef..ee87f7f0e555 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -1212,7 +1212,8 @@ InstructionCost ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args) { + ArrayRef Args, + const Instruction *CxtI) { Kind = improveShuffleKindFromMask(Kind, Mask, Tp, Index, SubTp); // Treat extractsubvector as single op permutation. bool IsExtractSubvector = Kind == TTI::SK_ExtractSubvector; diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index bb4b321b5300..04b32194f806 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -220,7 +220,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index 458b8717256f..f47fcff5d602 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -230,7 +230,8 @@ InstructionCost HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, - ArrayRef Args) { + ArrayRef Args, + const Instruction *CxtI) { return 1; } diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index fdb34f308e64..9689f2f5bb86 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -122,7 +122,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 57e1019adb74..3fa35efc2d15 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -607,7 +607,8 @@ InstructionCost PPCTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, - ArrayRef Args) { + ArrayRef Args, + const Instruction *CxtI) { InstructionCost CostFactor = vectorCostAdjustmentFactor(Instruction::ShuffleVector, Tp, nullptr); diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index c3ade9968c33..36006dd7df73 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -112,7 +112,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, Type *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index aeec06313c75..55637b8ea47f 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -329,7 +329,8 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args) { + ArrayRef Args, + const Instruction *CxtI) { Kind = improveShuffleKindFromMask(Kind, Mask, Tp, Index, SubTp); std::pair LT = getTypeLegalizationCost(Tp); diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index c0169ea1ad53..e0c0e6517b6f 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -146,7 +146,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind); diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp index 5bdbaf47064d..17e534f405c0 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp @@ -601,12 +601,10 @@ InstructionCost SystemZTTIImpl::getArithmeticInstrCost( Args, CxtI); } -InstructionCost SystemZTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, - VectorType *Tp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, - int Index, VectorType *SubTp, - ArrayRef Args) { +InstructionCost SystemZTTIImpl::getShuffleCost( + TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args, const Instruction *CxtI) { Kind = improveShuffleKindFromMask(Kind, Mask, Tp, Index, SubTp); if (ST->hasVector()) { unsigned NumVectors = getNumVectorRegs(Tp); diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index 2cccdf6d17da..1d824d353d8f 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -95,7 +95,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); unsigned getVectorTruncCost(Type *SrcTy, Type *DstTy); unsigned getVectorBitmaskConversionCost(Type *SrcTy, Type *DstTy); unsigned getBoolVecToIntConversionCost(unsigned Opcode, Type *Dst, diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 5d1810b5bc2c..b466624e1334 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -1468,12 +1468,10 @@ X86TTIImpl::getAltInstrCost(VectorType *VecTy, unsigned Opcode0, return InstructionCost::getInvalid(); } -InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind, - VectorType *BaseTp, - ArrayRef Mask, - TTI::TargetCostKind CostKind, - int Index, VectorType *SubTp, - ArrayRef Args) { +InstructionCost X86TTIImpl::getShuffleCost( + TTI::ShuffleKind Kind, VectorType *BaseTp, ArrayRef Mask, + TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, + ArrayRef Args, const Instruction *CxtI) { // 64-bit packed float vectors (v2f32) are widened to type v4f32. // 64-bit packed integer vectors (v2i32) are widened to type v4i32. std::pair LT = getTypeLegalizationCost(BaseTp); diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 985b00438ce8..8ef9b4f86ffd 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -150,7 +150,8 @@ public: ArrayRef Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, - ArrayRef Args = std::nullopt); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr); InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 61e3f0ff55f7..633b46e2dc8b 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1478,8 +1478,9 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { TTI::CastContextHint::None, CostKind) + TTI.getCastInstrCost(C1->getOpcode(), CastDstTy, CastSrcTy, TTI::CastContextHint::None, CostKind); - OldCost += TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, - CastDstTy, Mask, CostKind); + OldCost += + TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, CastDstTy, Mask, + CostKind, 0, nullptr, std::nullopt, &I); InstructionCost NewCost = TTI.getShuffleCost( TargetTransformInfo::SK_PermuteTwoSrc, CastSrcTy, Mask, CostKind); diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll index ebf913ece3a9..12de334574f5 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll @@ -85,33 +85,33 @@ define void @vst3(ptr %p) { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <6 x i8> %v8i8, ptr %p, align 8 ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <12 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <12 x i8> %v16i8, ptr %p, align 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <24 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <24 x i8> %v32i8, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 45 for instruction: %v64i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v64i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <48 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <48 x i8> %v64i8, ptr %p, align 64 ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <6 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <6 x i16> %v8i16, ptr %p, align 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <12 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <12 x i16> %v16i16, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <24 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <24 x i16> %v32i16, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 42 for instruction: %v64i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v64i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <48 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <48 x i16> %v64i16, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <6 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <6 x i32> %v8i32, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <12 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <12 x i32> %v16i32, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <24 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <24 x i32> %v32i32, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v64i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v64i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <48 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <48 x i32> %v64i32, ptr %p, align 256 -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <6 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i64 = shufflevector <4 x i64> undef, <4 x i64> undef, <6 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <6 x i64> %v8i64, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <12 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <12 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <12 x i64> %v16i64, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <24 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v32i64 = shufflevector <16 x i64> undef, <16 x i64> undef, <24 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <24 x i64> %v32i64, ptr %p, align 256 -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v64i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <48 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v64i64 = shufflevector <32 x i64> undef, <32 x i64> undef, <48 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: store <48 x i64> %v64i64, ptr %p, align 512 ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; @@ -161,25 +161,25 @@ define void @vst4(ptr %p) { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> %v16i8, ptr %p, align 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8 = shufflevector <32 x i8> undef, <32 x i8> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v64i8 = shufflevector <64 x i8> undef, <64 x i8> undef, <64 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <64 x i8> %v64i8, ptr %p, align 64 ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> %v8i16, ptr %p, align 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i16 = shufflevector <32 x i16> undef, <32 x i16> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v64i16 = shufflevector <64 x i16> undef, <64 x i16> undef, <64 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <64 x i16> %v64i16, ptr %p, align 128 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v8i32 = shufflevector <8 x i32> undef, <8 x i32> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <8 x i32> %v8i32, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v16i32 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <16 x i32> %v16i32, ptr %p, align 64 -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v32i32 = shufflevector <32 x i32> undef, <32 x i32> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: store <32 x i32> %v32i32, ptr %p, align 128 -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %v64i32 = shufflevector <64 x i32> undef, <64 x i32> undef, <64 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: store <64 x i32> %v64i32, ptr %p, align 256 ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v8i64 = shufflevector <8 x i64> undef, <8 x i64> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <8 x i64> %v8i64, ptr %p, align 64 -- GitLab From e8e67957fa48fd7611adccef1a0449b83649c9f4 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 9 Apr 2024 08:23:40 -0700 Subject: [PATCH 292/695] [SLP]Fix PR88123: use vectorized operands consistently. Need to use vectorized operands, not the vecop of the extractelement instructions, to avoid false detection of the extra vector operand in the extractelements shuffling. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 8 ++--- .../X86/extractelement-vecop-vectorized.ll | 32 +++++++++++++++++++ 2 files changed, 36 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/extractelement-vecop-vectorized.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index e2be6e0fa366..da2b61ea6a63 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -11755,8 +11755,8 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { VecOp = TE->VectorizedValue; if (!Vec1) { Vec1 = VecOp; - } else if (Vec1 != EI->getVectorOperand()) { - assert((!Vec2 || Vec2 == EI->getVectorOperand()) && + } else if (Vec1 != VecOp) { + assert((!Vec2 || Vec2 == VecOp) && "Expected only 1 or 2 vectors shuffle."); Vec2 = VecOp; } @@ -11796,8 +11796,8 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { VecMask.assign(VecMask.size(), PoisonMaskElem); copy(SubMask, std::next(VecMask.begin(), I * SliceSize)); if (TEs.size() == 1) { - IsUsedInExpr &= - FindReusedSplat(VecMask, TEs.front()->getVectorFactor(), I, SliceSize); + IsUsedInExpr &= FindReusedSplat( + VecMask, TEs.front()->getVectorFactor(), I, SliceSize); ShuffleBuilder.add(*TEs.front(), VecMask); if (TEs.front()->VectorizedValue) IsNonPoisoned &= diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractelement-vecop-vectorized.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-vecop-vectorized.ll new file mode 100644 index 000000000000..a7dbe7d0b43f --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/extractelement-vecop-vectorized.ll @@ -0,0 +1,32 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt --passes=slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux -mattr=+avx512vl | FileCheck %s + +define i32 @test() { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: br label [[TMP1:%.*]] +; CHECK: 1: +; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x double> [ zeroinitializer, [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[TMP1]] ] +; CHECK-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x double> [[TMP2]]) +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> poison, <8 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <8 x double> zeroinitializer, <8 x double> [[TMP4]], <4 x i32> +; CHECK-NEXT: [[TMP6]] = shufflevector <4 x double> [[TMP5]], <4 x double> , <4 x i32> +; CHECK-NEXT: br label [[TMP1]] +; + br label %1 + +1: + %.i489 = phi double [ 0.000000e+00, %0 ], [ 0.000000e+00, %1 ] + %.i1102 = phi double [ 0.000000e+00, %0 ], [ %.i1110, %1 ] + %.i4105 = phi double [ 0.000000e+00, %0 ], [ %.i4113, %1 ] + %.i14525 = call double @llvm.fma.f64(double 0.000000e+00, double 0.000000e+00, double %.i1102) + %.i24526 = call double @llvm.fma.f64(double 0.000000e+00, double 0.000000e+00, double %.i489) + %.i44529 = call double @llvm.fma.f64(double 0.000000e+00, double 0.000000e+00, double %.i4105) + %.upto16034 = insertelement <8 x double> zeroinitializer, double %.i14525, i64 1 + %.upto26035 = insertelement <8 x double> %.upto16034, double %.i24526, i64 2 + %.upto36036 = insertelement <8 x double> %.upto26035, double %.i14525, i64 3 + %.upto46037 = insertelement <8 x double> %.upto36036, double %.i44529, i64 0 + %.i1110 = extractelement <8 x double> %.upto46037, i64 0 + %.i4113 = extractelement <8 x double> zeroinitializer, i64 0 + br label %1 +} -- GitLab From 8a8ab8f70cbb5507d1aa55efcd9c6e61ad4e891c Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 9 Apr 2024 11:55:17 -0400 Subject: [PATCH 293/695] [lit][ci] Publish lit wheels (#88072) Add wheel publishing in addition to existing source distribution publishing of lit. Fixes #63369. This also uses the exact fix proposed by @EFord36 in #63369. Signed-off-by: Schuyler Eldridge --- .github/workflows/release-lit.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/release-lit.yml b/.github/workflows/release-lit.yml index 36b0b6edd518..0316ba406041 100644 --- a/.github/workflows/release-lit.yml +++ b/.github/workflows/release-lit.yml @@ -58,7 +58,7 @@ jobs: cd llvm/utils/lit # Remove 'dev' suffix from lit version. sed -i 's/ + "dev"//g' lit/__init__.py - python3 setup.py sdist + python3 setup.py sdist bdist_wheel - name: Upload lit to test.pypi.org uses: pypa/gh-action-pypi-publish@release/v1 -- GitLab From 4bb5d48584818646a31a1ba4bfbbd658b7dfbe67 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 9 Apr 2024 10:08:26 -0400 Subject: [PATCH 294/695] [clang][NFC] Fix CUDA clang-cl tests - Add '--' argument to prevent interpreting intput files as options starting with '/'. Fix test failure after 2921a0928c71f4ee652a2478283e47ab5ffebf58. --- clang/test/Driver/cuda-external-tools.cu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/Driver/cuda-external-tools.cu b/clang/test/Driver/cuda-external-tools.cu index d9564d026b4f..9ada0cf8595d 100644 --- a/clang/test/Driver/cuda-external-tools.cu +++ b/clang/test/Driver/cuda-external-tools.cu @@ -89,7 +89,7 @@ // Check -Xcuda-ptxas with clang-cl // RUN: %clang_cl -### -c -Xcuda-ptxas -foo1 \ // RUN: --offload-arch=sm_35 --cuda-path=%S/Inputs/CUDA/usr/local/cuda \ -// RUN: -Xcuda-ptxas -foo2 %s 2>&1 \ +// RUN: -Xcuda-ptxas -foo2 -- %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHECK,SM35,PTXAS-EXTRA %s // MacOS spot-checks -- GitLab From 614a5780347ff0c8f82b8867660ea7fb4d9fdccb Mon Sep 17 00:00:00 2001 From: Peter Lafreniere Date: Tue, 9 Apr 2024 12:07:26 -0400 Subject: [PATCH 295/695] [M68k] Add support for bitwise NOT instruction (#88049) Currently the bitwise NOT instruction is not recognized. Add support for using NOT on data registers. This is a partial implementation that puts NOT at the same level of support as NEG currently enjoys. Using not rather than eori cuts the length of the encoded instruction in half or in thirds, leading to a reduction of 4-10 cycles per instruction, on the original 68000. This change includes tests for both bitwise and arithmetic negation. --- llvm/lib/Target/M68k/M68kInstrArithmetic.td | 20 ++++- llvm/test/CodeGen/M68k/Arith/unary.ll | 86 +++++++++++++++++++ llvm/test/CodeGen/M68k/Atomics/rmw.ll | 2 +- llvm/test/MC/Disassembler/M68k/arithmetic.txt | 6 ++ llvm/test/MC/M68k/Arith/Classes/MxNOT.s | 11 +++ 5 files changed, 121 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/M68k/Arith/unary.ll create mode 100644 llvm/test/MC/M68k/Arith/Classes/MxNOT.s diff --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td index 3532e56e7417..e2d4e49ddf27 100644 --- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td +++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td @@ -15,8 +15,8 @@ /// ADD [~] ADDA [~] ADDI [~] ADDQ [ ] ADDX [~] /// CLR [ ] CMP [~] CMPA [~] CMPI [~] CMPM [ ] /// CMP2 [ ] DIVS/DIVU [~] DIVSL/DIVUL [ ] EXT [~] EXTB [ ] -/// MULS/MULU [~] NEG [~] NEGX [~] SUB [~] SUBA [~] -/// SUBI [~] SUBQ [ ] SUBX [~] +/// MULS/MULU [~] NEG [~] NEGX [~] NOT [~] SUB [~] +/// SUBA [~] SUBI [~] SUBQ [ ] SUBX [~] /// /// Map: /// @@ -769,7 +769,7 @@ def : Pat<(mulhu i16:$dst, Mxi16immSExt16:$opd), //===----------------------------------------------------------------------===// -// NEG/NEGX +// NEG/NEGX/NOT //===----------------------------------------------------------------------===// /// ------------+------------+------+---------+--------- @@ -809,12 +809,26 @@ class MxNegX_D } } +class MxNot_D + : MxInst<(outs TYPE.ROp:$dst), (ins TYPE.ROp:$src), + "not."#TYPE.Prefix#"\t$dst", + [(set TYPE.VT:$dst, (not TYPE.VT:$src))]> { + let Inst = (descend 0b01000110, + /*SIZE*/!cast("MxEncSize"#TYPE.Size).Value, + //MODE without last bit + 0b00, + //REGISTER prefixed by D/A bit + (operand "$dst", 4) + ); +} + } // let Constraints } // let Defs = [CCR] foreach S = [8, 16, 32] in { def NEG#S#d : MxNeg_D("MxType"#S#"d")>; def NEGX#S#d : MxNegX_D("MxType"#S#"d")>; + def NOT#S#d : MxNot_D("MxType"#S#"d")>; } def : Pat<(MxSub 0, i8 :$src), (NEG8d MxDRD8 :$src)>; diff --git a/llvm/test/CodeGen/M68k/Arith/unary.ll b/llvm/test/CodeGen/M68k/Arith/unary.ll new file mode 100644 index 000000000000..a28ac7328d26 --- /dev/null +++ b/llvm/test/CodeGen/M68k/Arith/unary.ll @@ -0,0 +1,86 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out ";*\.cfi_*" +; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s + +define i64 @notll(i64 %x) { +; CHECK-LABEL: notll: +; CHECK: ; %bb.0: +; CHECK: move.l (4,%sp), %d0 +; CHECK: not.l %d0 +; CHECK: move.l (8,%sp), %d1 +; CHECK: not.l %d1 +; CHECK: rts + %not = xor i64 %x, -1 + ret i64 %not +} + +define i32 @notl(i32 %x) { +; CHECK-LABEL: notl: +; CHECK: ; %bb.0: +; CHECK: move.l (4,%sp), %d0 +; CHECK: not.l %d0 +; CHECK: rts + %not = xor i32 %x, -1 + ret i32 %not +} + +define i16 @nots(i16 %x) { +; CHECK-LABEL: nots: +; CHECK: ; %bb.0: +; CHECK: move.w (6,%sp), %d0 +; CHECK: not.w %d0 +; CHECK: rts + %not = xor i16 %x, -1 + ret i16 %not +} + +define i8 @notb(i8 %x) { +; CHECK-LABEL: notb: +; CHECK: ; %bb.0: +; CHECK: move.b (7,%sp), %d0 +; CHECK: not.b %d0 +; CHECK: rts + %not = xor i8 %x, -1 + ret i8 %not +} + +define i64 @negll(i64 %x) { +; CHECK-LABEL: negll: +; CHECK: ; %bb.0: +; CHECK: move.l (4,%sp), %d0 +; CHECK: move.l (8,%sp), %d1 +; CHECK: neg.l %d1 +; CHECK: negx.l %d0 +; CHECK: rts + %neg = sub i64 0, %x + ret i64 %neg +} + +define i32 @negl(i32 %x) { +; CHECK-LABEL: negl: +; CHECK: ; %bb.0: +; CHECK: move.l (4,%sp), %d0 +; CHECK: neg.l %d0 +; CHECK: rts + %neg = sub i32 0, %x + ret i32 %neg +} + +define i16 @negs(i16 %x) { +; CHECK-LABEL: negs: +; CHECK: ; %bb.0: +; CHECK: move.w (6,%sp), %d0 +; CHECK: neg.w %d0 +; CHECK: rts + %neg = sub i16 0, %x + ret i16 %neg +} + +define i8 @negb(i8 %x) { +; CHECK-LABEL: negb: +; CHECK: ; %bb.0: +; CHECK: move.b (7,%sp), %d0 +; CHECK: neg.b %d0 +; CHECK: rts + %neg = sub i8 0, %x + ret i8 %neg +} diff --git a/llvm/test/CodeGen/M68k/Atomics/rmw.ll b/llvm/test/CodeGen/M68k/Atomics/rmw.ll index b589e7751d80..1036a0a8ba3d 100644 --- a/llvm/test/CodeGen/M68k/Atomics/rmw.ll +++ b/llvm/test/CodeGen/M68k/Atomics/rmw.ll @@ -237,7 +237,7 @@ define i16 @atmoicrmw_nand_i16(i16 %val, ptr %ptr) { ; ATOMIC-NEXT: ; =>This Inner Loop Header: Depth=1 ; ATOMIC-NEXT: move.w %d2, %d3 ; ATOMIC-NEXT: and.w %d0, %d3 -; ATOMIC-NEXT: eori.w #-1, %d3 +; ATOMIC-NEXT: not.w %d3 ; ATOMIC-NEXT: cas.w %d1, %d3, (%a0) ; ATOMIC-NEXT: move.w %d1, %d3 ; ATOMIC-NEXT: sub.w %d2, %d3 diff --git a/llvm/test/MC/Disassembler/M68k/arithmetic.txt b/llvm/test/MC/Disassembler/M68k/arithmetic.txt index 007a789b3bf0..8142024940c6 100644 --- a/llvm/test/MC/Disassembler/M68k/arithmetic.txt +++ b/llvm/test/MC/Disassembler/M68k/arithmetic.txt @@ -89,6 +89,12 @@ # CHECK: negx.l %a2 0x40 0x8a +# CHECK: not.l %d5 +0x46 0x85 + +# CHECK: not.b %d1 +0x46 0x01 + # CHECK: or.w (18,%a4,%a0), %d3 0x86 0x74 0x88 0x12 diff --git a/llvm/test/MC/M68k/Arith/Classes/MxNOT.s b/llvm/test/MC/M68k/Arith/Classes/MxNOT.s new file mode 100644 index 000000000000..93b473334d7b --- /dev/null +++ b/llvm/test/MC/M68k/Arith/Classes/MxNOT.s @@ -0,0 +1,11 @@ +; RUN: llvm-mc -triple=m68k -show-encoding %s | FileCheck %s + +; CHECK: not.b %d0 +; CHECK-SAME: encoding: [0x46,0x00] +not.b %d0 +; CHECK: not.w %d0 +; CHECK-SAME: encoding: [0x46,0x40] +not.w %d0 +; CHECK: not.l %d0 +; CHECK-SAME: encoding: [0x46,0x80] +not.l %d0 -- GitLab From 71ffc1f0ea1c64d475d9248ea7c68dfec16ee1ab Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Tue, 9 Apr 2024 11:07:36 -0500 Subject: [PATCH 296/695] [libc] Initialize rand for fma tests (#88055) Summary: The GPU build will have some random garbage here since we do not support initializers for the underlying implementation. Manually set the seed to 1. --- libc/test/src/math/CMakeLists.txt | 2 ++ libc/test/src/math/FmaTest.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/libc/test/src/math/CMakeLists.txt b/libc/test/src/math/CMakeLists.txt index 274018e59da5..55119868bdaa 100644 --- a/libc/test/src/math/CMakeLists.txt +++ b/libc/test/src/math/CMakeLists.txt @@ -1271,6 +1271,7 @@ add_fp_unittest( DEPENDS libc.src.math.fmaf libc.src.stdlib.rand + libc.src.stdlib.srand libc.src.__support.FPUtil.fp_bits FLAGS FMA_OPT__ONLY @@ -1286,6 +1287,7 @@ add_fp_unittest( DEPENDS libc.src.math.fma libc.src.stdlib.rand + libc.src.stdlib.srand libc.src.__support.FPUtil.fp_bits ) diff --git a/libc/test/src/math/FmaTest.h b/libc/test/src/math/FmaTest.h index a3b1c9bb8f9b..76bd221fcb1f 100644 --- a/libc/test/src/math/FmaTest.h +++ b/libc/test/src/math/FmaTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/stdlib/rand.h" +#include "src/stdlib/srand.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -76,6 +77,7 @@ public: void test_subnormal_range(Func func) { constexpr StorageType COUNT = 100'001; constexpr StorageType STEP = (MAX_SUBNORMAL - MIN_SUBNORMAL) / COUNT; + LIBC_NAMESPACE::srand(1); for (StorageType v = MIN_SUBNORMAL, w = MAX_SUBNORMAL; v <= MAX_SUBNORMAL && w >= MIN_SUBNORMAL; v += STEP, w -= STEP) { T x = FPBits(get_random_bit_pattern()).get_val(), y = FPBits(v).get_val(), @@ -89,6 +91,7 @@ public: void test_normal_range(Func func) { constexpr StorageType COUNT = 100'001; constexpr StorageType STEP = (MAX_NORMAL - MIN_NORMAL) / COUNT; + LIBC_NAMESPACE::srand(1); for (StorageType v = MIN_NORMAL, w = MAX_NORMAL; v <= MAX_NORMAL && w >= MIN_NORMAL; v += STEP, w -= STEP) { T x = FPBits(v).get_val(), y = FPBits(w).get_val(), -- GitLab From f0e79d9152b04845e60fc97ca6a4e7760202afbb Mon Sep 17 00:00:00 2001 From: David Green Date: Tue, 9 Apr 2024 17:16:14 +0100 Subject: [PATCH 297/695] [AArch64] Add a cost for identity shuffles. These are mostly handled at a higher level when costing shuffles, but some masks can end up being identity or concat masks which we can treat as free. --- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 8 ++++++++ llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index fc48338628b3..20150d738675 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -3924,6 +3924,14 @@ InstructionCost AArch64TTIImpl::getShuffleCost( all_of(Mask, [](int E) { return E < 8; })) return getPerfectShuffleCost(Mask); + // Check for identity masks, which we can treat as free. + if (!Mask.empty() && LT.second.isFixedLengthVector() && + (Kind == TTI::SK_PermuteTwoSrc || Kind == TTI::SK_PermuteSingleSrc) && + all_of(enumerate(Mask), [](const auto &M) { + return M.value() < 0 || M.value() == (int)M.index(); + })) + return 0; + if (Kind == TTI::SK_Broadcast || Kind == TTI::SK_Transpose || Kind == TTI::SK_Select || Kind == TTI::SK_PermuteSingleSrc || Kind == TTI::SK_Reverse || Kind == TTI::SK_Splice) { diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll index aec181ec8d24..d469ce630593 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll @@ -106,7 +106,7 @@ define void @insert_subvec() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_2_2 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16_2_3 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %v8i16_2_05 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16i16_4_0 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_4_0 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_4_1 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_4_2 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i16_4_3 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> -- GitLab From 3009228a09dbfe04e0911fc19813ec72d389bc45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Halkenh=C3=A4user?= Date: Tue, 9 Apr 2024 18:18:21 +0200 Subject: [PATCH 298/695] [clang][UBSan] Remove rigid metadata checks for `ubsan-bitfield-conversion` (#88116) Follow-up to discussion: https://github.com/llvm/llvm-project/pull/87761 As discussed after landing the original PR: Since fails could happen w.r.t. checking `!6`, these checks should be removed. --- clang/test/CodeGen/ubsan-bitfield-conversion.c | 8 ++++---- .../CodeGenCXX/ubsan-bitfield-conversion.cpp | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/clang/test/CodeGen/ubsan-bitfield-conversion.c b/clang/test/CodeGen/ubsan-bitfield-conversion.c index ea9bdd7da6bc..61d7634f9a33 100644 --- a/clang/test/CodeGen/ubsan-bitfield-conversion.c +++ b/clang/test/CodeGen/ubsan-bitfield-conversion.c @@ -17,7 +17,7 @@ void foo1(int x) { // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } @@ -29,7 +29,7 @@ void foo2(int x) { // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 6 // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 6 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } @@ -42,7 +42,7 @@ void foo3() { // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } @@ -55,7 +55,7 @@ void foo4(int x) { // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } \ No newline at end of file diff --git a/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp b/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp index 92f6e247c5f5..c0248871ddc2 100644 --- a/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp +++ b/clang/test/CodeGenCXX/ubsan-bitfield-conversion.cpp @@ -23,14 +23,14 @@ void foo1(int x) { // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize c.a = x; // CHECK: store i8 %{{.*}} // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } @@ -42,13 +42,13 @@ void foo2(int x) { // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 6 // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 6 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize c.b = x; // CHECK: store i8 %{{.*}} // CHECK-BITFIELD-CONVERSION: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 6 // CHECK-BITFIELD-CONVERSION-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 6 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } @@ -61,14 +61,14 @@ void foo3() { // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize c.a++; // CHECK: store i8 %{{.*}} // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } @@ -81,14 +81,14 @@ void foo4(int x) { // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize c.a += x; // CHECK: store i8 %{{.*}} // CHECK-NEXT: [[BFRESULTSHL:%.*]] = shl i8 {{.*}}, 5 // CHECK-NEXT: [[BFRESULTASHR:%.*]] = ashr i8 [[BFRESULTSHL]], 5 // CHECK-NEXT: [[BFRESULTCAST:%.*]] = sext i8 [[BFRESULTASHR]] to i32 // CHECK-BITFIELD-CONVERSION: call void @__ubsan_handle_implicit_conversion - // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize !6 + // CHECK-BITFIELD-CONVERSION-NEXT: br label %[[CONT:.*]], !nosanitize // CHECK-BITFIELD-CONVERSION: [[CONT]]: // CHECK-NEXT: ret void } \ No newline at end of file -- GitLab From 5601e35f620eccdebab988bed4b9677b29366b79 Mon Sep 17 00:00:00 2001 From: Alexander Richardson Date: Tue, 9 Apr 2024 09:23:38 -0700 Subject: [PATCH 299/695] [memprof] Use COMPILER_RT_TEST_COMPILER Unlike the other compiler-rt unit tests MemProf was not using the `generate_compiler_rt_tests()` helper that ensures the test is compiled using the test compiler (generally the Clang binary built earlier). This was exposed by https://github.com/llvm/llvm-project/pull/83088 because it started adding Clang-specific flags to COMPILER_RT_UNITTEST_CFLAGS if the compiler ID matched "Clang". This change should fix the buildbots that compile compiler-rt using a GCC compiler with LLVM_ENABLE_PROJECTS=compiler-rt. Reviewed By: vitalybuka Pull Request: https://github.com/llvm/llvm-project/pull/88074 --- compiler-rt/lib/memprof/tests/CMakeLists.txt | 54 ++++++++++++-------- 1 file changed, 34 insertions(+), 20 deletions(-) diff --git a/compiler-rt/lib/memprof/tests/CMakeLists.txt b/compiler-rt/lib/memprof/tests/CMakeLists.txt index f812bd1f86ff..dc19ac5cd49a 100644 --- a/compiler-rt/lib/memprof/tests/CMakeLists.txt +++ b/compiler-rt/lib/memprof/tests/CMakeLists.txt @@ -41,33 +41,47 @@ if(NOT WIN32) list(APPEND MEMPROF_UNITTEST_LINK_FLAGS -pthread) endif() +set(MEMPROF_UNITTEST_DEPS) +if (TARGET cxx-headers OR HAVE_LIBCXX) + list(APPEND MEMPROF_UNITTEST_DEPS cxx-headers) +endif() + set(MEMPROF_UNITTEST_LINK_LIBRARIES ${COMPILER_RT_UNWINDER_LINK_LIBS} ${SANITIZER_TEST_CXX_LIBRARIES}) -list(APPEND MEMPROF_UNITTEST_LINK_LIBRARIES "dl") - -if(COMPILER_RT_DEFAULT_TARGET_ARCH IN_LIST MEMPROF_SUPPORTED_ARCH) - # MemProf unit tests are only run on the host machine. - set(arch ${COMPILER_RT_DEFAULT_TARGET_ARCH}) +append_list_if(COMPILER_RT_HAS_LIBDL -ldl MEMPROF_UNITTEST_LINK_LIBRARIES) - add_executable(MemProfUnitTests - ${MEMPROF_UNITTESTS} - ${COMPILER_RT_GTEST_SOURCE} - ${COMPILER_RT_GMOCK_SOURCE} - ${MEMPROF_SOURCES} +# Adds memprof tests for each architecture. +macro(add_memprof_tests_for_arch arch) + set(MEMPROF_TEST_RUNTIME_OBJECTS $ $ $ $ - $) - set_target_compile_flags(MemProfUnitTests ${MEMPROF_UNITTEST_CFLAGS}) - set_target_link_flags(MemProfUnitTests ${MEMPROF_UNITTEST_LINK_FLAGS}) - target_link_libraries(MemProfUnitTests ${MEMPROF_UNITTEST_LINK_LIBRARIES}) - - if (TARGET cxx-headers OR HAVE_LIBCXX) - add_dependencies(MemProfUnitTests cxx-headers) - endif() + $ + ) + set(MEMPROF_TEST_RUNTIME RTMemProfTest.${arch}) + add_library(${MEMPROF_TEST_RUNTIME} STATIC ${MEMPROF_TEST_RUNTIME_OBJECTS}) + set_target_properties(${MEMPROF_TEST_RUNTIME} PROPERTIES + ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + FOLDER "Compiler-RT Runtime tests") + set(MEMPROF_TEST_OBJECTS) + generate_compiler_rt_tests(MEMPROF_TEST_OBJECTS + MemProfUnitTests "MemProf-${arch}-UnitTest" ${arch} + RUNTIME ${MEMPROF_TEST_RUNTIME} + DEPS ${MEMPROF_UNITTEST_DEPS} + SOURCES ${MEMPROF_UNITTESTS} ${MEMPROF_SOURCES} ${COMPILER_RT_GTEST_SOURCE} + COMPILE_DEPS ${MEMPROF_UNIT_TEST_HEADERS} + CFLAGS ${MEMPROF_UNITTEST_CFLAGS} + LINK_FLAGS ${MEMPROF_UNITTEST_LINK_FLAGS} ${MEMPROF_UNITTEST_LINK_LIBRARIES}) +endmacro() - set_target_properties(MemProfUnitTests PROPERTIES - RUNTIME_OUTPUT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}) +# MemProf unit tests testsuite. +add_custom_target(MemProfUnitTests) +set_target_properties(MemProfUnitTests PROPERTIES FOLDER "Compiler-RT Tests") +if(COMPILER_RT_CAN_EXECUTE_TESTS AND COMPILER_RT_DEFAULT_TARGET_ARCH IN_LIST MEMPROF_SUPPORTED_ARCH) + # MemProf unit tests are only run on the host machine. + foreach(arch ${COMPILER_RT_DEFAULT_TARGET_ARCH}) + add_memprof_tests_for_arch(${arch}) + endforeach() endif() -- GitLab From 528943f1535b925ce175afb2438cec79513cfc2b Mon Sep 17 00:00:00 2001 From: Dinar Temirbulatov Date: Tue, 9 Apr 2024 17:27:46 +0100 Subject: [PATCH 300/695] [AArch64][SME] Allow memory operations lowering to custom SME functions. (#79263) This change allows to lower memcpy, memset, memmove to custom SME version provided by LibRT. --- .../AArch64/AArch64SelectionDAGInfo.cpp | 87 +++++- .../Target/AArch64/AArch64SelectionDAGInfo.h | 5 + .../AArch64/Utils/AArch64SMEAttributes.cpp | 3 + .../streaming-compatible-memory-ops.ll | 289 ++++++++++++++++++ 4 files changed, 380 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/streaming-compatible-memory-ops.ll diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp index 9e43f206efcf..19ef6f4fb32e 100644 --- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp @@ -15,6 +15,12 @@ using namespace llvm; #define DEBUG_TYPE "aarch64-selectiondag-info" +static cl::opt + LowerToSMERoutines("aarch64-lower-to-sme-routines", cl::Hidden, + cl::desc("Enable AArch64 SME memory operations " + "to lower to librt functions"), + cl::init(true)); + SDValue AArch64SelectionDAGInfo::EmitMOPS(AArch64ISD::NodeType SDOpcode, SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, @@ -76,15 +82,79 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(AArch64ISD::NodeType SDOpcode, } } +SDValue AArch64SelectionDAGInfo::EmitStreamingCompatibleMemLibCall( + SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, + SDValue Size, RTLIB::Libcall LC) const { + const AArch64Subtarget &STI = + DAG.getMachineFunction().getSubtarget(); + const AArch64TargetLowering *TLI = STI.getTargetLowering(); + SDValue Symbol; + TargetLowering::ArgListEntry DstEntry; + DstEntry.Ty = PointerType::getUnqual(*DAG.getContext()); + DstEntry.Node = Dst; + TargetLowering::ArgListTy Args; + Args.push_back(DstEntry); + EVT PointerVT = TLI->getPointerTy(DAG.getDataLayout()); + + switch (LC) { + case RTLIB::MEMCPY: { + TargetLowering::ArgListEntry Entry; + Entry.Ty = PointerType::getUnqual(*DAG.getContext()); + Symbol = DAG.getExternalSymbol("__arm_sc_memcpy", PointerVT); + Entry.Node = Src; + Args.push_back(Entry); + break; + } + case RTLIB::MEMMOVE: { + TargetLowering::ArgListEntry Entry; + Entry.Ty = PointerType::getUnqual(*DAG.getContext()); + Symbol = DAG.getExternalSymbol("__arm_sc_memmove", PointerVT); + Entry.Node = Src; + Args.push_back(Entry); + break; + } + case RTLIB::MEMSET: { + TargetLowering::ArgListEntry Entry; + Entry.Ty = Type::getInt32Ty(*DAG.getContext()); + Symbol = DAG.getExternalSymbol("__arm_sc_memset", PointerVT); + Src = DAG.getZExtOrTrunc(Src, DL, MVT::i32); + Entry.Node = Src; + Args.push_back(Entry); + break; + } + default: + return SDValue(); + } + + TargetLowering::ArgListEntry SizeEntry; + SizeEntry.Node = Size; + SizeEntry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); + Args.push_back(SizeEntry); + assert(Symbol->getOpcode() == ISD::ExternalSymbol && + "Function name is not set"); + + TargetLowering::CallLoweringInfo CLI(DAG); + PointerType *RetTy = PointerType::getUnqual(*DAG.getContext()); + CLI.setDebugLoc(DL).setChain(Chain).setLibCallee( + TLI->getLibcallCallingConv(LC), RetTy, Symbol, std::move(Args)); + return TLI->LowerCallTo(CLI).second; +} + SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { const AArch64Subtarget &STI = DAG.getMachineFunction().getSubtarget(); + if (STI.hasMOPS()) return EmitMOPS(AArch64ISD::MOPS_MEMCOPY, DAG, DL, Chain, Dst, Src, Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo); + + SMEAttrs Attrs(DAG.getMachineFunction().getFunction()); + if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) + return EmitStreamingCompatibleMemLibCall(DAG, DL, Chain, Dst, Src, Size, + RTLIB::MEMCPY); return SDValue(); } @@ -95,10 +165,14 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemset( const AArch64Subtarget &STI = DAG.getMachineFunction().getSubtarget(); - if (STI.hasMOPS()) { + if (STI.hasMOPS()) return EmitMOPS(AArch64ISD::MOPS_MEMSET, DAG, dl, Chain, Dst, Src, Size, Alignment, isVolatile, DstPtrInfo, MachinePointerInfo{}); - } + + SMEAttrs Attrs(DAG.getMachineFunction().getFunction()); + if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) + return EmitStreamingCompatibleMemLibCall(DAG, dl, Chain, Dst, Src, Size, + RTLIB::MEMSET); return SDValue(); } @@ -108,10 +182,15 @@ SDValue AArch64SelectionDAGInfo::EmitTargetCodeForMemmove( MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const { const AArch64Subtarget &STI = DAG.getMachineFunction().getSubtarget(); - if (STI.hasMOPS()) { + + if (STI.hasMOPS()) return EmitMOPS(AArch64ISD::MOPS_MEMMOVE, DAG, dl, Chain, Dst, Src, Size, Alignment, isVolatile, DstPtrInfo, SrcPtrInfo); - } + + SMEAttrs Attrs(DAG.getMachineFunction().getFunction()); + if (LowerToSMERoutines && !Attrs.hasNonStreamingInterfaceAndBody()) + return EmitStreamingCompatibleMemLibCall(DAG, dl, Chain, Dst, Src, Size, + RTLIB::MEMMOVE); return SDValue(); } diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h index 73f93724d6fc..514de4477863 100644 --- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h +++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h @@ -47,6 +47,11 @@ public: SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo DstPtrInfo, bool ZeroData) const override; + + SDValue EmitStreamingCompatibleMemLibCall(SelectionDAG &DAG, const SDLoc &DL, + SDValue Chain, SDValue Dst, + SDValue Src, SDValue Size, + RTLIB::Libcall LC) const; }; } diff --git a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp index d399e0ac0794..015ca4cb92b2 100644 --- a/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp +++ b/llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp @@ -53,6 +53,9 @@ SMEAttrs::SMEAttrs(StringRef FuncName) : Bitmask(0) { if (FuncName == "__arm_tpidr2_restore") Bitmask |= SMEAttrs::SM_Compatible | encodeZAState(StateValue::In) | SMEAttrs::SME_ABI_Routine; + if (FuncName == "__arm_sc_memcpy" || FuncName == "__arm_sc_memset" || + FuncName == "__arm_sc_memmove" || FuncName == "__arm_sc_memchr") + Bitmask |= SMEAttrs::SM_Compatible; } SMEAttrs::SMEAttrs(const AttributeList &Attrs) { diff --git a/llvm/test/CodeGen/AArch64/streaming-compatible-memory-ops.ll b/llvm/test/CodeGen/AArch64/streaming-compatible-memory-ops.ll new file mode 100644 index 000000000000..c39894c27d9d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/streaming-compatible-memory-ops.ll @@ -0,0 +1,289 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs -aarch64-lower-to-sme-routines=false < %s | FileCheck %s -check-prefixes=CHECK-NO-SME-ROUTINES +; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -mattr=+mops -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK-MOPS + +@dst = global [512 x i8] zeroinitializer, align 1 +@src = global [512 x i8] zeroinitializer, align 1 + +define void @se_memcpy(i64 noundef %n) "aarch64_pstate_sm_enabled" nounwind { +; CHECK-LABEL: se_memcpy: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: adrp x0, :got:dst +; CHECK-NEXT: adrp x1, :got:src +; CHECK-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NEXT: bl __arm_sc_memcpy +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +; +; CHECK-NO-SME-ROUTINES-LABEL: se_memcpy: +; CHECK-NO-SME-ROUTINES: // %bb.0: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: mov x2, x0 +; CHECK-NO-SME-ROUTINES-NEXT: adrp x0, :got:dst +; CHECK-NO-SME-ROUTINES-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: adrp x1, :got:src +; CHECK-NO-SME-ROUTINES-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: str x30, [sp, #64] // 8-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NO-SME-ROUTINES-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NO-SME-ROUTINES-NEXT: smstop sm +; CHECK-NO-SME-ROUTINES-NEXT: bl memcpy +; CHECK-NO-SME-ROUTINES-NEXT: smstart sm +; CHECK-NO-SME-ROUTINES-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ret +; +; CHECK-MOPS-LABEL: se_memcpy: +; CHECK-MOPS: // %bb.0: // %entry +; CHECK-MOPS-NEXT: adrp x8, :got:src +; CHECK-MOPS-NEXT: adrp x9, :got:dst +; CHECK-MOPS-NEXT: ldr x8, [x8, :got_lo12:src] +; CHECK-MOPS-NEXT: ldr x9, [x9, :got_lo12:dst] +; CHECK-MOPS-NEXT: cpyfp [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpyfm [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpyfe [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: ret +entry: + tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 @dst, ptr nonnull align 1 @src, i64 %n, i1 false) + ret void +} + +define void @se_memset(i64 noundef %n) "aarch64_pstate_sm_enabled" nounwind { +; CHECK-LABEL: se_memset: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: adrp x0, :got:dst +; CHECK-NEXT: mov w1, #2 // =0x2 +; CHECK-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NEXT: bl __arm_sc_memset +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +; +; CHECK-NO-SME-ROUTINES-LABEL: se_memset: +; CHECK-NO-SME-ROUTINES: // %bb.0: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: mov x2, x0 +; CHECK-NO-SME-ROUTINES-NEXT: adrp x0, :got:dst +; CHECK-NO-SME-ROUTINES-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: str x30, [sp, #64] // 8-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NO-SME-ROUTINES-NEXT: smstop sm +; CHECK-NO-SME-ROUTINES-NEXT: mov w1, #2 // =0x2 +; CHECK-NO-SME-ROUTINES-NEXT: bl memset +; CHECK-NO-SME-ROUTINES-NEXT: smstart sm +; CHECK-NO-SME-ROUTINES-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ret +; +; CHECK-MOPS-LABEL: se_memset: +; CHECK-MOPS: // %bb.0: // %entry +; CHECK-MOPS-NEXT: adrp x8, :got:dst +; CHECK-MOPS-NEXT: mov w9, #2 // =0x2 +; CHECK-MOPS-NEXT: ldr x8, [x8, :got_lo12:dst] +; CHECK-MOPS-NEXT: setp [x8]!, x0!, x9 +; CHECK-MOPS-NEXT: setm [x8]!, x0!, x9 +; CHECK-MOPS-NEXT: sete [x8]!, x0!, x9 +; CHECK-MOPS-NEXT: ret +entry: + tail call void @llvm.memset.p0.i64(ptr align 1 @dst, i8 2, i64 %n, i1 false) + ret void +} + +define void @se_memmove(i64 noundef %n) "aarch64_pstate_sm_enabled" nounwind { +; CHECK-LABEL: se_memmove: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: adrp x0, :got:dst +; CHECK-NEXT: adrp x1, :got:src +; CHECK-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NEXT: bl __arm_sc_memmove +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +; +; CHECK-NO-SME-ROUTINES-LABEL: se_memmove: +; CHECK-NO-SME-ROUTINES: // %bb.0: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: mov x2, x0 +; CHECK-NO-SME-ROUTINES-NEXT: adrp x0, :got:dst +; CHECK-NO-SME-ROUTINES-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: adrp x1, :got:src +; CHECK-NO-SME-ROUTINES-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: str x30, [sp, #64] // 8-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NO-SME-ROUTINES-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NO-SME-ROUTINES-NEXT: smstop sm +; CHECK-NO-SME-ROUTINES-NEXT: bl memmove +; CHECK-NO-SME-ROUTINES-NEXT: smstart sm +; CHECK-NO-SME-ROUTINES-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ret +; +; CHECK-MOPS-LABEL: se_memmove: +; CHECK-MOPS: // %bb.0: // %entry +; CHECK-MOPS-NEXT: adrp x8, :got:src +; CHECK-MOPS-NEXT: adrp x9, :got:dst +; CHECK-MOPS-NEXT: ldr x8, [x8, :got_lo12:src] +; CHECK-MOPS-NEXT: ldr x9, [x9, :got_lo12:dst] +; CHECK-MOPS-NEXT: cpyp [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpym [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpye [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: ret +entry: + tail call void @llvm.memmove.p0.p0.i64(ptr align 1 @dst, ptr nonnull align 1 @src, i64 %n, i1 false) + ret void +} + +define void @sc_memcpy(i64 noundef %n) "aarch64_pstate_sm_compatible" nounwind { +; CHECK-LABEL: sc_memcpy: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: adrp x0, :got:dst +; CHECK-NEXT: adrp x1, :got:src +; CHECK-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NEXT: bl __arm_sc_memcpy +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret +; +; CHECK-NO-SME-ROUTINES-LABEL: sc_memcpy: +; CHECK-NO-SME-ROUTINES: // %bb.0: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: mov x2, x0 +; CHECK-NO-SME-ROUTINES-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp x30, x19, [sp, #64] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: bl __arm_sme_state +; CHECK-NO-SME-ROUTINES-NEXT: adrp x8, :got:dst +; CHECK-NO-SME-ROUTINES-NEXT: adrp x1, :got:src +; CHECK-NO-SME-ROUTINES-NEXT: and x19, x0, #0x1 +; CHECK-NO-SME-ROUTINES-NEXT: ldr x8, [x8, :got_lo12:dst] +; CHECK-NO-SME-ROUTINES-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NO-SME-ROUTINES-NEXT: tbz w19, #0, .LBB3_2 +; CHECK-NO-SME-ROUTINES-NEXT: // %bb.1: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: smstop sm +; CHECK-NO-SME-ROUTINES-NEXT: .LBB3_2: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: mov x0, x8 +; CHECK-NO-SME-ROUTINES-NEXT: bl memcpy +; CHECK-NO-SME-ROUTINES-NEXT: tbz w19, #0, .LBB3_4 +; CHECK-NO-SME-ROUTINES-NEXT: // %bb.3: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: smstart sm +; CHECK-NO-SME-ROUTINES-NEXT: .LBB3_4: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: ldp x30, x19, [sp, #64] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ret +; +; CHECK-MOPS-LABEL: sc_memcpy: +; CHECK-MOPS: // %bb.0: // %entry +; CHECK-MOPS-NEXT: adrp x8, :got:src +; CHECK-MOPS-NEXT: adrp x9, :got:dst +; CHECK-MOPS-NEXT: ldr x8, [x8, :got_lo12:src] +; CHECK-MOPS-NEXT: ldr x9, [x9, :got_lo12:dst] +; CHECK-MOPS-NEXT: cpyfp [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpyfm [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpyfe [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: ret +entry: + tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 @dst, ptr nonnull align 1 @src, i64 %n, i1 false) + ret void +} + +define void @sb_memcpy(i64 noundef %n) "aarch64_pstate_sm_body" nounwind { +; CHECK-LABEL: sb_memcpy: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill +; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: mov x2, x0 +; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill +; CHECK-NEXT: smstart sm +; CHECK-NEXT: adrp x0, :got:dst +; CHECK-NEXT: adrp x1, :got:src +; CHECK-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NEXT: bl __arm_sc_memcpy +; CHECK-NEXT: smstop sm +; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload +; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload +; CHECK-NEXT: ret +; +; CHECK-NO-SME-ROUTINES-LABEL: sb_memcpy: +; CHECK-NO-SME-ROUTINES: // %bb.0: // %entry +; CHECK-NO-SME-ROUTINES-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: mov x2, x0 +; CHECK-NO-SME-ROUTINES-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: str x30, [sp, #64] // 8-byte Folded Spill +; CHECK-NO-SME-ROUTINES-NEXT: smstart sm +; CHECK-NO-SME-ROUTINES-NEXT: adrp x0, :got:dst +; CHECK-NO-SME-ROUTINES-NEXT: adrp x1, :got:src +; CHECK-NO-SME-ROUTINES-NEXT: ldr x0, [x0, :got_lo12:dst] +; CHECK-NO-SME-ROUTINES-NEXT: ldr x1, [x1, :got_lo12:src] +; CHECK-NO-SME-ROUTINES-NEXT: smstop sm +; CHECK-NO-SME-ROUTINES-NEXT: bl memcpy +; CHECK-NO-SME-ROUTINES-NEXT: smstart sm +; CHECK-NO-SME-ROUTINES-NEXT: smstop sm +; CHECK-NO-SME-ROUTINES-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldr x30, [sp, #64] // 8-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload +; CHECK-NO-SME-ROUTINES-NEXT: ret +; +; CHECK-MOPS-LABEL: sb_memcpy: +; CHECK-MOPS: // %bb.0: // %entry +; CHECK-MOPS-NEXT: stp d15, d14, [sp, #-64]! // 16-byte Folded Spill +; CHECK-MOPS-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill +; CHECK-MOPS-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill +; CHECK-MOPS-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill +; CHECK-MOPS-NEXT: smstart sm +; CHECK-MOPS-NEXT: adrp x8, :got:src +; CHECK-MOPS-NEXT: adrp x9, :got:dst +; CHECK-MOPS-NEXT: ldr x8, [x8, :got_lo12:src] +; CHECK-MOPS-NEXT: ldr x9, [x9, :got_lo12:dst] +; CHECK-MOPS-NEXT: cpyfp [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpyfm [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: cpyfe [x9]!, [x8]!, x0! +; CHECK-MOPS-NEXT: smstop sm +; CHECK-MOPS-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload +; CHECK-MOPS-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload +; CHECK-MOPS-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload +; CHECK-MOPS-NEXT: ldp d15, d14, [sp], #64 // 16-byte Folded Reload +; CHECK-MOPS-NEXT: ret +entry: + tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 @dst, ptr nonnull align 1 @src, i64 %n, i1 false) + ret void +} + +declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg) +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg) +declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg) -- GitLab From bab0507ff2679d2bbfa34921eeed4ff1cadbe7e2 Mon Sep 17 00:00:00 2001 From: ChiaHungDuan Date: Tue, 9 Apr 2024 09:30:11 -0700 Subject: [PATCH 301/695] [scudo] Add EnableContiguousRegions mode (#85149) This releases the requirement that we need to preserve the memory for all regions at the beginning. It needs a huge amount of contiguous pages and which may be a challenge in certain cases. Therefore, adding a new flag, EnableContiguousRegions, to indicate whether we want to allocate all the regions next to each other. Note that once the EnableContiguousRegions is disabled, EnableRandomOffset becomes irrelevant because the base of each region is already random. --- .../lib/scudo/standalone/allocator_config.def | 7 +- compiler-rt/lib/scudo/standalone/primary64.h | 117 ++++++++++++------ .../scudo/standalone/tests/primary_test.cpp | 1 + 3 files changed, 83 insertions(+), 42 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/allocator_config.def b/compiler-rt/lib/scudo/standalone/allocator_config.def index c50aadad2d63..9691a007eed5 100644 --- a/compiler-rt/lib/scudo/standalone/allocator_config.def +++ b/compiler-rt/lib/scudo/standalone/allocator_config.def @@ -87,9 +87,14 @@ PRIMARY_REQUIRED(const s32, MaxReleaseToOsIntervalMs) // PRIMARY_OPTIONAL(TYPE, NAME, DEFAULT) // // Indicates support for offsetting the start of a region by a random number of -// pages. Only used with primary64. +// pages. This is only used if `EnableContiguousRegions` is enabled. PRIMARY_OPTIONAL(const bool, EnableRandomOffset, false) +// When `EnableContiguousRegions` is true, all regions will be be arranged in +// adjacency. This will reduce the fragmentation caused by region allocations +// but may require a huge amount of contiguous pages at initialization. +PRIMARY_OPTIONAL(const bool, EnableContiguousRegions, true) + // PRIMARY_OPTIONAL_TYPE(NAME, DEFAULT) // // Use condition variable to shorten the waiting time of refillment of diff --git a/compiler-rt/lib/scudo/standalone/primary64.h b/compiler-rt/lib/scudo/standalone/primary64.h index abce4bff321c..61d57976ae43 100644 --- a/compiler-rt/lib/scudo/standalone/primary64.h +++ b/compiler-rt/lib/scudo/standalone/primary64.h @@ -117,40 +117,30 @@ public: SmallerBlockReleasePageDelta = PagesInGroup * (1 + MinSizeClass / 16U) / 100; - // Reserve the space required for the Primary. - CHECK(ReservedMemory.create(/*Addr=*/0U, PrimarySize, - "scudo:primary_reserve")); - PrimaryBase = ReservedMemory.getBase(); - DCHECK_NE(PrimaryBase, 0U); - u32 Seed; const u64 Time = getMonotonicTimeFast(); if (!getRandom(reinterpret_cast(&Seed), sizeof(Seed))) - Seed = static_cast(Time ^ (PrimaryBase >> 12)); + Seed = static_cast(Time ^ (reinterpret_cast(&Seed) >> 12)); - for (uptr I = 0; I < NumClasses; I++) { - RegionInfo *Region = getRegionInfo(I); + for (uptr I = 0; I < NumClasses; I++) + getRegionInfo(I)->RandState = getRandomU32(&Seed); - // The actual start of a region is offset by a random number of pages - // when PrimaryEnableRandomOffset is set. - Region->RegionBeg = (PrimaryBase + (I << RegionSizeLog)) + - (Config::getEnableRandomOffset() - ? ((getRandomModN(&Seed, 16) + 1) * PageSize) - : 0); - Region->RandState = getRandomU32(&Seed); - // Releasing small blocks is expensive, set a higher threshold to avoid - // frequent page releases. - if (isSmallBlock(getSizeByClassId(I))) - Region->TryReleaseThreshold = PageSize * SmallerBlockReleasePageDelta; - else - Region->TryReleaseThreshold = PageSize; - Region->ReleaseInfo.LastReleaseAtNs = Time; + if (Config::getEnableContiguousRegions()) { + ReservedMemoryT ReservedMemory = {}; + // Reserve the space required for the Primary. + CHECK(ReservedMemory.create(/*Addr=*/0U, RegionSize * NumClasses, + "scudo:primary_reserve")); + const uptr PrimaryBase = ReservedMemory.getBase(); + + for (uptr I = 0; I < NumClasses; I++) { + MemMapT RegionMemMap = ReservedMemory.dispatch( + PrimaryBase + (I << RegionSizeLog), RegionSize); + RegionInfo *Region = getRegionInfo(I); - Region->MemMapInfo.MemMap = ReservedMemory.dispatch( - PrimaryBase + (I << RegionSizeLog), RegionSize); - CHECK(Region->MemMapInfo.MemMap.isAllocated()); + initRegion(Region, I, RegionMemMap, Config::getEnableRandomOffset()); + } + shuffle(RegionInfoArray, NumClasses, &Seed); } - shuffle(RegionInfoArray, NumClasses, &Seed); // The binding should be done after region shuffling so that it won't bind // the FLLock from the wrong region. @@ -160,14 +150,17 @@ public: setOption(Option::ReleaseInterval, static_cast(ReleaseToOsInterval)); } - void unmapTestOnly() NO_THREAD_SAFETY_ANALYSIS { + void unmapTestOnly() { for (uptr I = 0; I < NumClasses; I++) { RegionInfo *Region = getRegionInfo(I); + { + ScopedLock ML(Region->MMLock); + MemMapT MemMap = Region->MemMapInfo.MemMap; + if (MemMap.isAllocated()) + MemMap.unmap(MemMap.getBase(), MemMap.getCapacity()); + } *Region = {}; } - if (PrimaryBase) - ReservedMemory.release(); - PrimaryBase = 0U; } // When all blocks are freed, it has to be the same size as `AllocatedUser`. @@ -251,9 +244,10 @@ public: } const bool RegionIsExhausted = Region->Exhausted; - if (!RegionIsExhausted) + if (!RegionIsExhausted) { PopCount = populateFreeListAndPopBlocks(C, ClassId, Region, ToArray, MaxBlockCount); + } ReportRegionExhausted = !RegionIsExhausted && Region->Exhausted; break; } @@ -514,7 +508,6 @@ public: private: static const uptr RegionSize = 1UL << RegionSizeLog; static const uptr NumClasses = SizeClassMap::NumClasses; - static const uptr PrimarySize = RegionSize * NumClasses; static const uptr MapSizeIncrement = Config::getMapSizeIncrement(); // Fill at most this number of batches from the newly map'd memory. @@ -570,9 +563,14 @@ private: } uptr getRegionBaseByClassId(uptr ClassId) { - return roundDown(getRegionInfo(ClassId)->RegionBeg - PrimaryBase, - RegionSize) + - PrimaryBase; + RegionInfo *Region = getRegionInfo(ClassId); + Region->MMLock.assertHeld(); + + if (!Config::getEnableContiguousRegions() && + !Region->MemMapInfo.MemMap.isAllocated()) { + return 0U; + } + return Region->MemMapInfo.MemMap.getBase(); } static CompactPtrT compactPtrInternal(uptr Base, uptr Ptr) { @@ -602,6 +600,30 @@ private: return BlockSize > PageSize; } + ALWAYS_INLINE void initRegion(RegionInfo *Region, uptr ClassId, + MemMapT MemMap, bool EnableRandomOffset) + REQUIRES(Region->MMLock) { + DCHECK(!Region->MemMapInfo.MemMap.isAllocated()); + DCHECK(MemMap.isAllocated()); + + const uptr PageSize = getPageSizeCached(); + + Region->MemMapInfo.MemMap = MemMap; + + Region->RegionBeg = MemMap.getBase(); + if (EnableRandomOffset) { + Region->RegionBeg += + (getRandomModN(&Region->RandState, 16) + 1) * PageSize; + } + + // Releasing small blocks is expensive, set a higher threshold to avoid + // frequent page releases. + if (isSmallBlock(getSizeByClassId(ClassId))) + Region->TryReleaseThreshold = PageSize * SmallerBlockReleasePageDelta; + else + Region->TryReleaseThreshold = PageSize; + } + void pushBatchClassBlocks(RegionInfo *Region, CompactPtrT *Array, u32 Size) REQUIRES(Region->FLLock) { DCHECK_EQ(Region, getRegionInfo(SizeClassMap::BatchClassId)); @@ -989,9 +1011,26 @@ private: CompactPtrT *ToArray, const u16 MaxBlockCount) REQUIRES(Region->MMLock) EXCLUDES(Region->FLLock) { + if (!Config::getEnableContiguousRegions() && + !Region->MemMapInfo.MemMap.isAllocated()) { + ReservedMemoryT ReservedMemory; + if (UNLIKELY(!ReservedMemory.create(/*Addr=*/0U, RegionSize, + "scudo:primary_reserve", + MAP_ALLOWNOMEM))) { + Printf("Can't reserve pages for size class %zu.\n", + getSizeByClassId(ClassId)); + Region->Exhausted = true; + return 0U; + } + initRegion(Region, ClassId, + ReservedMemory.dispatch(ReservedMemory.getBase(), + ReservedMemory.getCapacity()), + /*EnableRandomOffset=*/false); + } + + DCHECK(Region->MemMapInfo.MemMap.isAllocated()); const uptr Size = getSizeByClassId(ClassId); const u16 MaxCount = CacheT::getMaxCached(Size); - const uptr RegionBeg = Region->RegionBeg; const uptr MappedUser = Region->MemMapInfo.MappedUser; const uptr TotalUserBytes = @@ -1683,10 +1722,6 @@ private: Region->FLLockCV.notifyAll(Region->FLLock); } - // TODO: `PrimaryBase` can be obtained from ReservedMemory. This needs to be - // deprecated. - uptr PrimaryBase = 0; - ReservedMemoryT ReservedMemory = {}; // The minimum size of pushed blocks that we will try to release the pages in // that size class. uptr SmallerBlockReleasePageDelta = 0; diff --git a/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp b/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp index 683ce3e59659..1cf3bb51db0e 100644 --- a/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp @@ -90,6 +90,7 @@ template struct TestConfig3 { static const scudo::s32 MaxReleaseToOsIntervalMs = INT32_MAX; typedef scudo::uptr CompactPtrT; static const scudo::uptr CompactPtrScale = 0; + static const bool EnableContiguousRegions = false; static const bool EnableRandomOffset = true; static const scudo::uptr MapSizeIncrement = 1UL << 18; }; -- GitLab From b1a278dd874d6135780fc824c6aa263c52d7aadd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Tue, 9 Apr 2024 09:44:55 -0700 Subject: [PATCH 302/695] [flang][cuda] Add a proper TODO for allocate statement for cuda var (#88034) Allocate statement for variable with CUDA attributes need to allocate memory on the device and not the host. Add a proper TODO so we keep track of work to be done for it. --- flang/include/flang/Semantics/tools.h | 10 ++++++++++ flang/lib/Lower/Allocatable.cpp | 3 +++ 2 files changed, 13 insertions(+) diff --git a/flang/include/flang/Semantics/tools.h b/flang/include/flang/Semantics/tools.h index f0eb82eebefa..da10969ebc70 100644 --- a/flang/include/flang/Semantics/tools.h +++ b/flang/include/flang/Semantics/tools.h @@ -212,6 +212,16 @@ inline bool IsCUDADeviceContext(const Scope *scope) { return false; } +inline bool HasCUDAAttr(const Symbol &sym) { + if (const auto *details{ + sym.GetUltimate().detailsIf()}) { + if (details->cudaDataAttr()) { + return true; + } + } + return false; +} + const Scope *FindCUDADeviceContext(const Scope *); std::optional GetCUDADataAttr(const Symbol *); diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index 09180518ea41..42e78fc96e44 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -379,6 +379,9 @@ private: } void lowerAllocation(const Allocation &alloc) { + if (Fortran::semantics::HasCUDAAttr(alloc.getSymbol())) + TODO(loc, "Allocation of variable with CUDA attributes"); + fir::MutableBoxValue boxAddr = genMutableBoxValue(converter, loc, alloc.getAllocObj()); -- GitLab From 9e418c94cd1393408d201f215be8631d1f41e857 Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 9 Apr 2024 12:50:18 -0400 Subject: [PATCH 303/695] [ADT] Use `adl_*` wrappers across STLExtras (#87936) Update the remaining uses of `std::begin`/`end` functions to `adl_beging`/`end`. This is to make the behavior all the utility functions consistent, rather than trying to fix a specific usecase. --- llvm/include/llvm/ADT/STLExtras.h | 49 +++++++++++++++---------------- 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index 08a708e5c587..f906f7acfc1c 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -320,7 +320,8 @@ public: /// Returns true if the given container only contains a single element. template bool hasSingleElement(ContainerTy &&C) { - auto B = std::begin(C), E = std::end(C); + auto B = adl_begin(C); + auto E = adl_end(C); return B != E && std::next(B) == E; } @@ -375,8 +376,7 @@ inline mapped_iterator map_iterator(ItTy I, FuncTy F) { template auto map_range(ContainerTy &&C, FuncTy F) { - return make_range(map_iterator(std::begin(C), F), - map_iterator(std::end(C), F)); + return make_range(map_iterator(adl_begin(C), F), map_iterator(adl_end(C), F)); } /// A base type of mapped iterator, that is useful for building derived @@ -572,11 +572,11 @@ iterator_range, PredicateT>> make_filter_range(RangeT &&Range, PredicateT Pred) { using FilterIteratorT = filter_iterator, PredicateT>; - return make_range( - FilterIteratorT(std::begin(std::forward(Range)), - std::end(std::forward(Range)), Pred), - FilterIteratorT(std::end(std::forward(Range)), - std::end(std::forward(Range)), Pred)); + return make_range(FilterIteratorT(adl_begin(std::forward(Range)), + adl_end(std::forward(Range)), Pred), + FilterIteratorT(adl_end(std::forward(Range)), + adl_end(std::forward(Range)), + Pred)); } /// A pseudo-iterator adaptor that is designed to implement "early increment" @@ -656,8 +656,8 @@ iterator_range>> make_early_inc_range(RangeT &&Range) { using EarlyIncIteratorT = early_inc_iterator_impl>; - return make_range(EarlyIncIteratorT(std::begin(std::forward(Range))), - EarlyIncIteratorT(std::end(std::forward(Range)))); + return make_range(EarlyIncIteratorT(adl_begin(std::forward(Range))), + EarlyIncIteratorT(adl_end(std::forward(Range)))); } // Forward declarations required by zip_shortest/zip_equal/zip_first/zip_longest @@ -1097,8 +1097,8 @@ public: /// We need the full range to know how to switch between each of the /// iterators. template - explicit concat_iterator(RangeTs &&... Ranges) - : Begins(std::begin(Ranges)...), Ends(std::end(Ranges)...) {} + explicit concat_iterator(RangeTs &&...Ranges) + : Begins(adl_begin(Ranges)...), Ends(adl_end(Ranges)...) {} using BaseT::operator++; @@ -1127,13 +1127,12 @@ template class concat_range { public: using iterator = concat_iterator()))...>; + decltype(adl_begin(std::declval()))...>; private: std::tuple Ranges; - template - iterator begin_impl(std::index_sequence) { + template iterator begin_impl(std::index_sequence) { return iterator(std::get(Ranges)...); } template @@ -1141,12 +1140,12 @@ private: return iterator(std::get(Ranges)...); } template iterator end_impl(std::index_sequence) { - return iterator(make_range(std::end(std::get(Ranges)), - std::end(std::get(Ranges)))...); + return iterator(make_range(adl_end(std::get(Ranges)), + adl_end(std::get(Ranges)))...); } template iterator end_impl(std::index_sequence) const { - return iterator(make_range(std::end(std::get(Ranges)), - std::end(std::get(Ranges)))...); + return iterator(make_range(adl_end(std::get(Ranges)), + adl_end(std::get(Ranges)))...); } public: @@ -1420,7 +1419,7 @@ public: /// Given a container of pairs, return a range over the first elements. template auto make_first_range(ContainerTy &&c) { - using EltTy = decltype((*std::begin(c))); + using EltTy = decltype((*adl_begin(c))); return llvm::map_range(std::forward(c), [](EltTy elt) -> typename detail::first_or_second_type< EltTy, decltype((elt.first))>::type { @@ -1430,7 +1429,7 @@ template auto make_first_range(ContainerTy &&c) { /// Given a container of pairs, return a range over the second elements. template auto make_second_range(ContainerTy &&c) { - using EltTy = decltype((*std::begin(c))); + using EltTy = decltype((*adl_begin(c))); return llvm::map_range( std::forward(c), [](EltTy elt) -> @@ -2106,7 +2105,7 @@ template> void replace(Container &Cont, typename Container::iterator ContIt, typename Container::iterator ContEnd, Range R) { - replace(Cont, ContIt, ContEnd, R.begin(), R.end()); + replace(Cont, ContIt, ContEnd, adl_begin(R), adl_begin(R)); } /// An STL-style algorithm similar to std::for_each that applies a second @@ -2519,19 +2518,19 @@ bool hasNItemsOrLess( /// Returns true if the given container has exactly N items template bool hasNItems(ContainerTy &&C, unsigned N) { - return hasNItems(std::begin(C), std::end(C), N); + return hasNItems(adl_begin(C), adl_end(C), N); } /// Returns true if the given container has N or more items template bool hasNItemsOrMore(ContainerTy &&C, unsigned N) { - return hasNItemsOrMore(std::begin(C), std::end(C), N); + return hasNItemsOrMore(adl_begin(C), adl_end(C), N); } /// Returns true if the given container has N or less items template bool hasNItemsOrLess(ContainerTy &&C, unsigned N) { - return hasNItemsOrLess(std::begin(C), std::end(C), N); + return hasNItemsOrLess(adl_begin(C), adl_end(C), N); } /// Returns a raw pointer that represents the same address as the argument. -- GitLab From 49561181bdc8698aa28ee2a46d2faa4cf6767bbe Mon Sep 17 00:00:00 2001 From: Job Henandez Lara Date: Tue, 9 Apr 2024 09:55:10 -0700 Subject: [PATCH 304/695] [libc] Add proxy header for fenv.h macro constants. #87863 (#87896) Hello, this addresses #87863. --- libc/hdr/CMakeLists.txt | 9 ++++++ libc/hdr/fenv_macros.h | 22 +++++++++++++++ libc/src/__support/FPUtil/CMakeLists.txt | 3 +- libc/src/__support/FPUtil/aarch64/FEnvImpl.h | 1 + .../FPUtil/aarch64/fenv_darwin_impl.h | 1 + libc/src/__support/FPUtil/arm/FEnvImpl.h | 2 +- .../__support/FPUtil/generic/CMakeLists.txt | 1 - libc/src/__support/FPUtil/riscv/FEnvImpl.h | 1 + libc/src/__support/FPUtil/rounding_mode.h | 3 +- libc/src/fenv/CMakeLists.txt | 28 +++++++++---------- libc/src/fenv/feholdexcept.cpp | 1 - libc/src/fenv/fesetexceptflag.cpp | 1 - libc/test/UnitTest/RoundingModeUtils.cpp | 2 +- .../__support/FPUtil/rounding_mode_test.cpp | 2 +- libc/test/src/fenv/CMakeLists.txt | 2 +- .../test/src/fenv/enabled_exceptions_test.cpp | 2 +- libc/test/src/fenv/exception_status_test.cpp | 2 +- libc/test/src/fenv/feclearexcept_test.cpp | 2 +- libc/test/src/fenv/feenableexcept_test.cpp | 2 +- libc/test/src/fenv/rounding_mode_test.cpp | 2 +- libc/test/src/math/RIntTest.h | 2 +- libc/test/src/math/smoke/NextTowardTest.h | 2 +- libc/test/src/math/smoke/RIntTest.h | 2 +- libc/utils/MPFRWrapper/MPFRUtils.cpp | 1 - .../llvm-project-overlay/libc/BUILD.bazel | 6 ++++ .../libc/test/UnitTest/BUILD.bazel | 1 + .../test/src/__support/FPUtil/BUILD.bazel | 1 + .../libc/test/src/fenv/BUILD.bazel | 5 ++++ .../libc/test/src/math/smoke/BUILD.bazel | 1 + 29 files changed, 77 insertions(+), 33 deletions(-) create mode 100644 libc/hdr/fenv_macros.h diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 1d3eb9d5240a..4ca7db5e98d6 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -31,3 +31,12 @@ add_proxy_header_library( libc.include.llvm-libc-macros.math_macros libc.include.math ) + +add_proxy_header_library( + fenv_macros + HDRS + fenv_macros.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-macros.fenv_macros + libc.incude.fenv +) diff --git a/libc/hdr/fenv_macros.h b/libc/hdr/fenv_macros.h new file mode 100644 index 000000000000..1ad28cc278a9 --- /dev/null +++ b/libc/hdr/fenv_macros.h @@ -0,0 +1,22 @@ +//===-- Definition of macros from fenv.h ----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_HDR_FENV_MACROS_H +#define LLVM_LIBC_HDR_FENV_MACROS_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-macros/fenv-macros.h" + +#else // Overlay mode + +#include + +#endif // LLVM_LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_FENV_MACROS_H diff --git a/libc/src/__support/FPUtil/CMakeLists.txt b/libc/src/__support/FPUtil/CMakeLists.txt index c75a7cd7e097..0b5ea8368943 100644 --- a/libc/src/__support/FPUtil/CMakeLists.txt +++ b/libc/src/__support/FPUtil/CMakeLists.txt @@ -4,6 +4,7 @@ add_header_library( FEnvImpl.h DEPENDS libc.include.fenv + libc.hdr.fenv_macros libc.hdr.math_macros libc.src.__support.macros.attributes libc.src.errno.errno @@ -14,7 +15,7 @@ add_header_library( HDRS rounding_mode.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.macros.attributes libc.src.__support.macros.properties.architectures libc.src.__support.macros.sanitizer diff --git a/libc/src/__support/FPUtil/aarch64/FEnvImpl.h b/libc/src/__support/FPUtil/aarch64/FEnvImpl.h index e0eec17e038c..4b593cdd8cc4 100644 --- a/libc/src/__support/FPUtil/aarch64/FEnvImpl.h +++ b/libc/src/__support/FPUtil/aarch64/FEnvImpl.h @@ -20,6 +20,7 @@ #include #include +#include "hdr/fenv_macros.h" #include "src/__support/FPUtil/FPBits.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h b/libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h index fd915373020e..773d6bfe9f89 100644 --- a/libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h +++ b/libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h @@ -20,6 +20,7 @@ #include #include +#include "hdr/fenv_macros.h" #include "src/__support/FPUtil/FPBits.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/__support/FPUtil/arm/FEnvImpl.h b/libc/src/__support/FPUtil/arm/FEnvImpl.h index ac4673cf20f6..ddb0edcf8278 100644 --- a/libc/src/__support/FPUtil/arm/FEnvImpl.h +++ b/libc/src/__support/FPUtil/arm/FEnvImpl.h @@ -9,9 +9,9 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_ARM_FENVIMPL_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_ARM_FENVIMPL_H +#include "hdr/fenv_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/macros/attributes.h" // For LIBC_INLINE - #include #include diff --git a/libc/src/__support/FPUtil/generic/CMakeLists.txt b/libc/src/__support/FPUtil/generic/CMakeLists.txt index 17b1fffea82e..09eede157096 100644 --- a/libc/src/__support/FPUtil/generic/CMakeLists.txt +++ b/libc/src/__support/FPUtil/generic/CMakeLists.txt @@ -4,7 +4,6 @@ add_header_library( sqrt.h sqrt_80_bit_long_double.h DEPENDS - libc.include.fenv libc.src.__support.common libc.src.__support.CPP.bit libc.src.__support.CPP.type_traits diff --git a/libc/src/__support/FPUtil/riscv/FEnvImpl.h b/libc/src/__support/FPUtil/riscv/FEnvImpl.h index b73c4798b053..a5224330f339 100644 --- a/libc/src/__support/FPUtil/riscv/FEnvImpl.h +++ b/libc/src/__support/FPUtil/riscv/FEnvImpl.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_RISCV_FENVIMPL_H +#include "hdr/fenv_macros.h" #include "src/__support/FPUtil/FPBits.h" #include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM #include "src/__support/macros/config.h" // For LIBC_INLINE diff --git a/libc/src/__support/FPUtil/rounding_mode.h b/libc/src/__support/FPUtil/rounding_mode.h index 91a5b9c50e7c..aa5e00fa560b 100644 --- a/libc/src/__support/FPUtil/rounding_mode.h +++ b/libc/src/__support/FPUtil/rounding_mode.h @@ -9,10 +9,9 @@ #ifndef LLVM_LIBC_SRC___SUPPORT_FPUTIL_ROUNDING_MODE_H #define LLVM_LIBC_SRC___SUPPORT_FPUTIL_ROUNDING_MODE_H +#include "hdr/fenv_macros.h" #include "src/__support/macros/attributes.h" // LIBC_INLINE -#include - namespace LIBC_NAMESPACE::fputil { // Quick free-standing test whether fegetround() == FE_UPWARD. diff --git a/libc/src/fenv/CMakeLists.txt b/libc/src/fenv/CMakeLists.txt index d2f90d3d007a..5dcf21de04f1 100644 --- a/libc/src/fenv/CMakeLists.txt +++ b/libc/src/fenv/CMakeLists.txt @@ -18,7 +18,7 @@ add_entrypoint_object( HDRS fesetround.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -31,7 +31,7 @@ add_entrypoint_object( HDRS feclearexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -44,7 +44,7 @@ add_entrypoint_object( HDRS feraiseexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -57,7 +57,7 @@ add_entrypoint_object( HDRS fetestexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -70,7 +70,7 @@ add_entrypoint_object( HDRS fegetenv.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -83,7 +83,7 @@ add_entrypoint_object( HDRS fesetenv.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -96,7 +96,7 @@ add_entrypoint_object( HDRS fegetexceptflag.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -109,7 +109,7 @@ add_entrypoint_object( HDRS fesetexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -122,7 +122,7 @@ add_entrypoint_object( HDRS fesetexceptflag.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -135,7 +135,7 @@ add_entrypoint_object( HDRS feholdexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -148,7 +148,7 @@ add_entrypoint_object( HDRS feupdateenv.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -161,7 +161,7 @@ add_entrypoint_object( HDRS feenableexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -174,7 +174,7 @@ add_entrypoint_object( HDRS fedisableexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 @@ -187,7 +187,7 @@ add_entrypoint_object( HDRS fegetexcept.h DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.__support.FPUtil.fenv_impl COMPILE_OPTIONS -O2 diff --git a/libc/src/fenv/feholdexcept.cpp b/libc/src/fenv/feholdexcept.cpp index 3c73b1f42177..f264c5ae251d 100644 --- a/libc/src/fenv/feholdexcept.cpp +++ b/libc/src/fenv/feholdexcept.cpp @@ -9,7 +9,6 @@ #include "src/fenv/feholdexcept.h" #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/common.h" - #include namespace LIBC_NAMESPACE { diff --git a/libc/src/fenv/fesetexceptflag.cpp b/libc/src/fenv/fesetexceptflag.cpp index 2fe7cb571a8d..3ff8e270dc0a 100644 --- a/libc/src/fenv/fesetexceptflag.cpp +++ b/libc/src/fenv/fesetexceptflag.cpp @@ -9,7 +9,6 @@ #include "src/fenv/fesetexceptflag.h" #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/common.h" - #include namespace LIBC_NAMESPACE { diff --git a/libc/test/UnitTest/RoundingModeUtils.cpp b/libc/test/UnitTest/RoundingModeUtils.cpp index c8f32f81e713..cb34c5eab421 100644 --- a/libc/test/UnitTest/RoundingModeUtils.cpp +++ b/libc/test/UnitTest/RoundingModeUtils.cpp @@ -10,7 +10,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/rounding_mode.h" -#include +#include "hdr/fenv_macros.h" namespace LIBC_NAMESPACE { namespace fputil { diff --git a/libc/test/src/__support/FPUtil/rounding_mode_test.cpp b/libc/test/src/__support/FPUtil/rounding_mode_test.cpp index 8077a5aab7af..5d62bc8c9ae9 100644 --- a/libc/test/src/__support/FPUtil/rounding_mode_test.cpp +++ b/libc/test/src/__support/FPUtil/rounding_mode_test.cpp @@ -10,7 +10,7 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include +#include "hdr/fenv_macros.h" using LIBC_NAMESPACE::testing::mpfr::ForceRoundingMode; using LIBC_NAMESPACE::testing::mpfr::RoundingMode; diff --git a/libc/test/src/fenv/CMakeLists.txt b/libc/test/src/fenv/CMakeLists.txt index 7e456b9a922f..577735599dc0 100644 --- a/libc/test/src/fenv/CMakeLists.txt +++ b/libc/test/src/fenv/CMakeLists.txt @@ -118,7 +118,7 @@ if (NOT (LLVM_USE_SANITIZER OR (${LIBC_TARGET_OS} STREQUAL "windows") SRCS feholdexcept_test.cpp DEPENDS - libc.include.fenv + libc.hdr.fenv_macros libc.src.fenv.feholdexcept libc.src.__support.FPUtil.fenv_impl LINK_LIBRARIES diff --git a/libc/test/src/fenv/enabled_exceptions_test.cpp b/libc/test/src/fenv/enabled_exceptions_test.cpp index 8bc2454faf9e..53440b704ca7 100644 --- a/libc/test/src/fenv/enabled_exceptions_test.cpp +++ b/libc/test/src/fenv/enabled_exceptions_test.cpp @@ -15,7 +15,7 @@ #include "test/UnitTest/FPExceptMatcher.h" #include "test/UnitTest/Test.h" -#include +#include "hdr/fenv_macros.h" #include // This test enables an exception and verifies that raising that exception diff --git a/libc/test/src/fenv/exception_status_test.cpp b/libc/test/src/fenv/exception_status_test.cpp index cf0fd1fe1af3..a7000020b1a3 100644 --- a/libc/test/src/fenv/exception_status_test.cpp +++ b/libc/test/src/fenv/exception_status_test.cpp @@ -15,7 +15,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "test/UnitTest/Test.h" -#include +#include "hdr/fenv_macros.h" TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { // This test raises a set of exceptions and checks that the exception diff --git a/libc/test/src/fenv/feclearexcept_test.cpp b/libc/test/src/fenv/feclearexcept_test.cpp index fa3e856d1ba2..bb42d9070358 100644 --- a/libc/test/src/fenv/feclearexcept_test.cpp +++ b/libc/test/src/fenv/feclearexcept_test.cpp @@ -11,7 +11,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "test/UnitTest/Test.h" -#include +#include "hdr/fenv_macros.h" #include TEST(LlvmLibcFEnvTest, ClearTest) { diff --git a/libc/test/src/fenv/feenableexcept_test.cpp b/libc/test/src/fenv/feenableexcept_test.cpp index 41c1945368ed..aeb4f955fd69 100644 --- a/libc/test/src/fenv/feenableexcept_test.cpp +++ b/libc/test/src/fenv/feenableexcept_test.cpp @@ -13,7 +13,7 @@ #include "test/UnitTest/Test.h" -#include +#include "hdr/fenv_macros.h" TEST(LlvmLibcFEnvTest, EnableTest) { #if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \ diff --git a/libc/test/src/fenv/rounding_mode_test.cpp b/libc/test/src/fenv/rounding_mode_test.cpp index 4560160e8e2e..ec2e27ecc818 100644 --- a/libc/test/src/fenv/rounding_mode_test.cpp +++ b/libc/test/src/fenv/rounding_mode_test.cpp @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" -#include +#include "hdr/fenv_macros.h" TEST(LlvmLibcRoundingModeTest, SetAndGet) { struct ResetDefaultRoundingMode { diff --git a/libc/test/src/math/RIntTest.h b/libc/test/src/math/RIntTest.h index 5be34bece54b..c706ff18f186 100644 --- a/libc/test/src/math/RIntTest.h +++ b/libc/test/src/math/RIntTest.h @@ -15,8 +15,8 @@ #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" +#include "hdr/fenv_macros.h" #include "hdr/math_macros.h" -#include #include namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/math/smoke/NextTowardTest.h b/libc/test/src/math/smoke/NextTowardTest.h index d97aea96d837..b6c1c8d1797d 100644 --- a/libc/test/src/math/smoke/NextTowardTest.h +++ b/libc/test/src/math/smoke/NextTowardTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_NEXTTOWARDTEST_H #define LLVM_LIBC_TEST_SRC_MATH_NEXTTOWARDTEST_H +#include "hdr/fenv_macros.h" #include "hdr/math_macros.h" #include "src/__support/CPP/bit.h" #include "src/__support/CPP/type_traits.h" @@ -16,7 +17,6 @@ #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -#include #define ASSERT_FP_EQ_WITH_EXCEPTION(result, expected, expected_exception) \ ASSERT_FP_EQ(result, expected); \ diff --git a/libc/test/src/math/smoke/RIntTest.h b/libc/test/src/math/smoke/RIntTest.h index 73c3428047e9..cbed9a3b10ba 100644 --- a/libc/test/src/math/smoke/RIntTest.h +++ b/libc/test/src/math/smoke/RIntTest.h @@ -14,8 +14,8 @@ #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" +#include "hdr/fenv_macros.h" #include "hdr/math_macros.h" -#include #include static constexpr int ROUNDING_MODES[4] = {FE_UPWARD, FE_DOWNWARD, FE_TOWARDZERO, diff --git a/libc/utils/MPFRWrapper/MPFRUtils.cpp b/libc/utils/MPFRWrapper/MPFRUtils.cpp index 91a623ddfa12..18a8ac044a9b 100644 --- a/libc/utils/MPFRWrapper/MPFRUtils.cpp +++ b/libc/utils/MPFRWrapper/MPFRUtils.cpp @@ -15,7 +15,6 @@ #include "test/UnitTest/FPMatcher.h" #include "hdr/math_macros.h" -#include #include #include diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index e8d8320a42e9..ee9f5b8bd83d 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -113,6 +113,11 @@ libc_support_library( hdrs = ["hdr/math_macros.h"], ) +libc_support_library( + name = "hdr_fenv_macros", + hdrs = ["hdr/fenv_macros.h"], +) + ############################### Support libraries ############################## libc_support_library( @@ -751,6 +756,7 @@ libc_support_library( hdrs = ["src/__support/FPUtil/rounding_mode.h"], deps = [ ":__support_macros_attributes", + ":hdr_fenv_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel index 2fc7e36aebb4..82c015a7eeda 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel @@ -86,6 +86,7 @@ libc_support_library( "//libc:__support_fputil_fpbits_str", "//libc:__support_fputil_rounding_mode", "//libc:hdr_math_macros", + "//libc:hdr_fenv_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel index 132c146b507b..ff3b035f64ad 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel @@ -41,5 +41,6 @@ libc_test( "//libc:__support_fputil_rounding_mode", "//libc:__support_uint128", "//libc/utils/MPFRWrapper:mpfr_wrapper", + "//libc:hdr_fenv_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel index 2a268ae227fb..bce1dd786a85 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel @@ -21,6 +21,7 @@ libc_test( ], deps = [ "//libc:__support_fputil_fenv_impl", + "//libc:hdr_fenv_macros", ], ) @@ -31,6 +32,7 @@ libc_test( "//libc:fegetround", "//libc:fesetround", ], + deps = ["//libc:hdr_fenv_macros"], ) libc_test( @@ -47,6 +49,7 @@ libc_test( "//libc:__support_fputil_fenv_impl", "//libc:__support_macros_properties_architectures", "//libc/test/UnitTest:fp_test_helpers", + "//libc:hdr_fenv_macros", ], ) @@ -85,6 +88,7 @@ libc_test( ], deps = [ "//libc:__support_fputil_fenv_impl", + "//libc:hdr_fenv_macros", ], ) @@ -99,6 +103,7 @@ libc_test( deps = [ "//libc:__support_common", "//libc:__support_macros_properties_architectures", + "//libc:hdr_fenv_macros", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel index f16bce32fe98..7d4b9978db3f 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel @@ -105,6 +105,7 @@ math_test( math_test( name = "rintf128", hdrs = ["RIntTest.h"], + deps = ["//libc:hdr_fenv_macros"], ) math_test( -- GitLab From 8d6469b0e02c4c7bd1d496972c63ed3e2de0e077 Mon Sep 17 00:00:00 2001 From: xiaoleis-nv <99947620+xiaoleis-nv@users.noreply.github.com> Date: Wed, 10 Apr 2024 01:04:25 +0800 Subject: [PATCH 305/695] [mlir][vector] Add lower-vector-multi-reduction pass (#87333) This MR adds the `lower-vector-multi-reduction` pass to lower the vector.multi_reduction operation. While the Transform Dialect includes an operation, `transform.apply_patterns.vector.lower_multi_reduction`, intended for a similar purpose, its utility is limited to projects that have adopted the Transform Dialect. Recognizing that not all projects are equipped to integrate this dialect, the proposed pass serves as a vital standalone alternative. It ensures that projects solely dependent on the traditional pass infrastructure can also benefit from the optimized lowering of `multi_reduction` operation. --------- Co-authored-by: Xiaolei Shi --- .../mlir/Dialect/Vector/Transforms/Passes.h | 6 +++ .../mlir/Dialect/Vector/Transforms/Passes.td | 18 ++++++++ .../Transforms/LowerVectorMultiReduction.cpp | 40 +++++++++++++++++ .../vector-multi-reduction-pass-lowering.mlir | 45 +++++++++++++++++++ 4 files changed, 109 insertions(+) create mode 100644 mlir/test/Dialect/Vector/vector-multi-reduction-pass-lowering.mlir diff --git a/mlir/include/mlir/Dialect/Vector/Transforms/Passes.h b/mlir/include/mlir/Dialect/Vector/Transforms/Passes.h index bf89b01e2b60..911402551e14 100644 --- a/mlir/include/mlir/Dialect/Vector/Transforms/Passes.h +++ b/mlir/include/mlir/Dialect/Vector/Transforms/Passes.h @@ -9,6 +9,7 @@ #ifndef MLIR_DIALECT_VECTOR_TRANSFORMS_PASSES_H_ #define MLIR_DIALECT_VECTOR_TRANSFORMS_PASSES_H_ +#include "mlir/Dialect/Vector/Transforms/VectorTransforms.h" #include "mlir/Pass/Pass.h" namespace mlir { @@ -22,6 +23,11 @@ std::unique_ptr createVectorBufferizePass(); /// Creates an instance of the `vector.mask` lowering pass. std::unique_ptr createLowerVectorMaskPass(); +/// Creates an instance of the `vector.multi_reduction` lowering pass. +std::unique_ptr createLowerVectorMultiReductionPass( + VectorMultiReductionLowering option = + VectorMultiReductionLowering::InnerParallel); + //===----------------------------------------------------------------------===// // Registration //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/Vector/Transforms/Passes.td b/mlir/include/mlir/Dialect/Vector/Transforms/Passes.td index 4911a61ab3c2..31a0b3b2f0c5 100644 --- a/mlir/include/mlir/Dialect/Vector/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/Vector/Transforms/Passes.td @@ -21,4 +21,22 @@ def LowerVectorMaskPass : Pass<"lower-vector-mask", "func::FuncOp"> { let constructor = "mlir::vector::createLowerVectorMaskPass()"; } +def LowerVectorMultiReduction : Pass<"lower-vector-multi-reduction", "func::FuncOp"> { + let summary = "Lower 'vector.multi_reduction' operations"; + let constructor = "mlir::vector::createLowerVectorMultiReductionPass()"; + let options = [ + Option<"loweringStrategy", "lowering-strategy", "mlir::vector::VectorMultiReductionLowering", + /*default=*/"mlir::vector::VectorMultiReductionLowering::InnerParallel", + "Select the strategy to control how multi_reduction is lowered.", + [{::llvm::cl::values( + clEnumValN(mlir::vector::VectorMultiReductionLowering::InnerParallel, + "inner-parallel", + "Lower multi_reduction into outer-reduction and inner-parallel ops."), + clEnumValN(mlir::vector::VectorMultiReductionLowering::InnerReduction, + "inner-reduction", + "Lower multi_reduction into outer-parallel and inner-reduction ops.") + )}]> + ]; +} + #endif // MLIR_DIALECT_VECTOR_TRANSFORMS_PASSES diff --git a/mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp b/mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp index bed2c2496719..2f21c50c6347 100644 --- a/mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/LowerVectorMultiReduction.cpp @@ -12,9 +12,19 @@ //===----------------------------------------------------------------------===// #include "mlir/Dialect/Arith/IR/Arith.h" +#include "mlir/Dialect/Func/IR/FuncOps.h" #include "mlir/Dialect/Vector/Transforms/LoweringPatterns.h" +#include "mlir/Dialect/Vector/Transforms/Passes.h" #include "mlir/IR/Builders.h" #include "mlir/IR/TypeUtilities.h" +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" + +namespace mlir { +namespace vector { +#define GEN_PASS_DEF_LOWERVECTORMULTIREDUCTION +#include "mlir/Dialect/Vector/Transforms/Passes.h.inc" +} // namespace vector +} // namespace mlir #define DEBUG_TYPE "vector-multi-reduction" @@ -461,6 +471,31 @@ struct OneDimMultiReductionToTwoDim return success(); } }; + +struct LowerVectorMultiReductionPass + : public vector::impl::LowerVectorMultiReductionBase< + LowerVectorMultiReductionPass> { + LowerVectorMultiReductionPass(vector::VectorMultiReductionLowering option) { + this->loweringStrategy = option; + } + + void runOnOperation() override { + Operation *op = getOperation(); + MLIRContext *context = op->getContext(); + + RewritePatternSet loweringPatterns(context); + populateVectorMultiReductionLoweringPatterns(loweringPatterns, + this->loweringStrategy); + + if (failed(applyPatternsAndFoldGreedily(op, std::move(loweringPatterns)))) + signalPassFailure(); + } + + void getDependentDialects(DialectRegistry ®istry) const override { + registry.insert(); + } +}; + } // namespace void mlir::vector::populateVectorMultiReductionLoweringPatterns( @@ -476,3 +511,8 @@ void mlir::vector::populateVectorMultiReductionLoweringPatterns( patterns.add(patterns.getContext(), benefit); } + +std::unique_ptr vector::createLowerVectorMultiReductionPass( + vector::VectorMultiReductionLowering option) { + return std::make_unique(option); +} diff --git a/mlir/test/Dialect/Vector/vector-multi-reduction-pass-lowering.mlir b/mlir/test/Dialect/Vector/vector-multi-reduction-pass-lowering.mlir new file mode 100644 index 000000000000..4cb6fba9b691 --- /dev/null +++ b/mlir/test/Dialect/Vector/vector-multi-reduction-pass-lowering.mlir @@ -0,0 +1,45 @@ +// RUN: mlir-opt -lower-vector-multi-reduction="lowering-strategy=inner-reduction" -split-input-file %s | FileCheck %s --check-prefixes=ALL,INNER-REDUCTION +// RUN: mlir-opt -lower-vector-multi-reduction="lowering-strategy=inner-parallel" -split-input-file %s | FileCheck %s --check-prefixes=ALL,INNER-PARALLEL +// RUN: mlir-opt -lower-vector-multi-reduction -split-input-file %s | FileCheck %s --check-prefixes=ALL,INNER-PARALLEL + +func.func @vector_multi_reduction(%arg0: vector<2x4xf32>, %acc: vector<2xf32>) -> vector<2xf32> { + %0 = vector.multi_reduction , %arg0, %acc [1] : vector<2x4xf32> to vector<2xf32> + return %0 : vector<2xf32> +} +// ALL-LABEL: func @vector_multi_reduction +// ALL-SAME: %[[INPUT:.+]]: vector<2x4xf32>, %[[ACC:.*]]: vector<2xf32>) +// INNER-REDUCTION-DAG: %[[RESULT_VEC_0:.+]] = arith.constant dense<{{.*}}> : vector<2xf32> +// INNER-REDUCTION-DAG: %[[C0:.+]] = arith.constant 0 : index +// INNER-REDUCTION-DAG: %[[C1:.+]] = arith.constant 1 : index +// INNER-REDUCTION: %[[V0:.+]] = vector.extract %[[INPUT]][0] +// INNER-REDUCTION: %[[ACC0:.+]] = vector.extract %[[ACC]][0] +// INNER-REDUCTION: %[[RV0:.+]] = vector.reduction , %[[V0]], %[[ACC0]] : vector<4xf32> into f32 +// INNER-REDUCTION: %[[RESULT_VEC_1:.+]] = vector.insertelement %[[RV0:.+]], %[[RESULT_VEC_0]][%[[C0]] : index] : vector<2xf32> +// INNER-REDUCTION: %[[V1:.+]] = vector.extract %[[INPUT]][1] +// INNER-REDUCTION: %[[ACC1:.+]] = vector.extract %[[ACC]][1] +// INNER-REDUCTION: %[[RV1:.+]] = vector.reduction , %[[V1]], %[[ACC1]] : vector<4xf32> into f32 +// INNER-REDUCTION: %[[RESULT_VEC:.+]] = vector.insertelement %[[RV1:.+]], %[[RESULT_VEC_1]][%[[C1]] : index] : vector<2xf32> +// INNER-REDUCTION: return %[[RESULT_VEC]] + +// INNER-PARALLEL: %[[TRANSPOSED:.+]] = vector.transpose %[[INPUT]], [1, 0] : vector<2x4xf32> to vector<4x2xf32> +// INNER-PARALLEL: %[[V0:.+]] = vector.extract %[[TRANSPOSED]][0] : vector<2xf32> from vector<4x2xf32> +// INNER-PARALLEL: %[[RV0:.+]] = arith.mulf %[[V0]], %[[ACC]] : vector<2xf32> +// INNER-PARALLEL: %[[V1:.+]] = vector.extract %[[TRANSPOSED]][1] : vector<2xf32> from vector<4x2xf32> +// INNER-PARALLEL: %[[RV01:.+]] = arith.mulf %[[V1]], %[[RV0]] : vector<2xf32> +// INNER-PARALLEL: %[[V2:.+]] = vector.extract %[[TRANSPOSED]][2] : vector<2xf32> from vector<4x2xf32> +// INNER-PARALLEL: %[[RV012:.+]] = arith.mulf %[[V2]], %[[RV01]] : vector<2xf32> +// INNER-PARALLEL: %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<2xf32> from vector<4x2xf32> +// INNER-PARALLEL: %[[RESULT_VEC:.+]] = arith.mulf %[[V3]], %[[RV012]] : vector<2xf32> +// INNER-PARALLEL: return %[[RESULT_VEC]] : vector<2xf32> + +// ----- + +func.func @vector_multi_reduction_parallel_middle(%arg0: vector<3x4x5xf32>, %acc: vector<4xf32>) -> vector<4xf32> { + %0 = vector.multi_reduction , %arg0, %acc [0, 2] : vector<3x4x5xf32> to vector<4xf32> + return %0 : vector<4xf32> +} + +// ALL-LABEL: func @vector_multi_reduction_parallel_middle +// ALL-SAME: %[[INPUT:.+]]: vector<3x4x5xf32>, %[[ACC:.+]]: vector<4xf32> +// INNER-REDUCTION: vector.transpose %[[INPUT]], [1, 0, 2] : vector<3x4x5xf32> to vector<4x3x5xf32> +// INNER-PARALLEL: vector.transpose %[[INPUT]], [0, 2, 1] : vector<3x4x5xf32> to vector<3x5x4xf32> -- GitLab From 1381645ab675d1edcc0eaa0b72729b9f3f02a82d Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Apr 2024 19:08:40 +0200 Subject: [PATCH 306/695] [libc++][format] adds a basic fuzzer test. (#87883) This adds an initial fuzzer. Different formatting arguments will execute different code paths. This will be tested by different fuzzer tests. The code is based on a sample provided by Louis. --- .../libcxx/fuzzing/format_no_args.pass.cpp | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 libcxx/test/libcxx/fuzzing/format_no_args.pass.cpp diff --git a/libcxx/test/libcxx/fuzzing/format_no_args.pass.cpp b/libcxx/test/libcxx/fuzzing/format_no_args.pass.cpp new file mode 100644 index 000000000000..2faf27eda98c --- /dev/null +++ b/libcxx/test/libcxx/fuzzing/format_no_args.pass.cpp @@ -0,0 +1,30 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: no-exceptions + +// UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME + +// XFAIL: availability-fp_to_chars-missing + +#include +#include +#include + +#include "fuzz.h" + +extern "C" int LLVMFuzzerTestOneInput(const std::uint8_t* data, std::size_t size) { + try { + [[maybe_unused]] auto result = std::vformat(std::string_view{(const char*)(data), size}, std::make_format_args()); + } catch (std::format_error const&) { + // If the fuzzing input isn't a valid thing we can format and we detect it, it's okay. We are looking for crashes. + return 0; + } + return 0; +} -- GitLab From eea3bd3954e3a38ae0997f1af558b9deea301c3a Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Apr 2024 19:12:04 +0200 Subject: [PATCH 307/695] [libc++][TZDB] Fixes relative path resolving. (#87882) The path /etc/localtime is a symlink. This symlink can be a relative path. This fixes resolving a relative symlink. Since the path used is hard-coded based on the user's system there is no good way to test this. Fixes: https://github.com/llvm/llvm-project/issues/87872 --- libcxx/src/tzdb.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/libcxx/src/tzdb.cpp b/libcxx/src/tzdb.cpp index 2c82a4a4317a..9d06eb920e5c 100644 --- a/libcxx/src/tzdb.cpp +++ b/libcxx/src/tzdb.cpp @@ -717,8 +717,12 @@ void __init_tzdb(tzdb& __tzdb, __tz::__rules_storage_type& __rules) { std::__throw_runtime_error("tzdb: the path '/etc/localtime' is not a symlink"); filesystem::path __tz = filesystem::read_symlink(__path); - string __name = filesystem::relative(__tz, "/usr/share/zoneinfo/"); + // The path may be a relative path, in that case convert it to an absolute + // path based on the proper initial directory. + if (__tz.is_relative()) + __tz = filesystem::canonical("/etc" / __tz); + string __name = filesystem::relative(__tz, "/usr/share/zoneinfo/"); if (const time_zone* __result = tzdb.__locate_zone(__name)) return __result; -- GitLab From cf6feff56b06b9110095ba6e20c609c9d1dfcfd3 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Apr 2024 19:13:02 +0200 Subject: [PATCH 308/695] [libc++] Avoids using ENODATA. (#86165) This macro is deprecated in C++26. Fixes https://github.com/llvm/llvm-project/issues/81360 --------- Co-authored-by: Louis Dionne --- libcxx/docs/ReleaseNotes/19.rst | 5 ++++- libcxx/src/random.cpp | 4 +--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index eaba5c8d0456..399693f4f3e0 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -117,7 +117,10 @@ TODO ABI Affecting Changes --------------------- -TODO + +- The optional POSIX macro ``ENODATA`` has been deprecated in C++ and POSIX 2017. The + ``random_device`` could throw a ``system_error`` with this value. It now + throws ``ENOMSG``. Build System Changes diff --git a/libcxx/src/random.cpp b/libcxx/src/random.cpp index 93590af310e5..14c6f4473d70 100644 --- a/libcxx/src/random.cpp +++ b/libcxx/src/random.cpp @@ -79,10 +79,8 @@ unsigned random_device::operator()() { char* p = reinterpret_cast(&r); while (n > 0) { ssize_t s = read(__f_, p, n); - _LIBCPP_SUPPRESS_DEPRECATED_PUSH if (s == 0) - __throw_system_error(ENODATA, "random_device got EOF"); // TODO ENODATA -> ENOMSG - _LIBCPP_SUPPRESS_DEPRECATED_POP + __throw_system_error(ENOMSG, "random_device got EOF"); if (s == -1) { if (errno != EINTR) __throw_system_error(errno, "random_device got an unexpected error"); -- GitLab From 59e66c515a475bc53db011f3ccca0d2831314443 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Tue, 9 Apr 2024 19:20:06 +0200 Subject: [PATCH 309/695] [libc++][format] Switches to Unicode 15.1. (#86543) In addition to changes in the tables the extended grapheme clustering algorithm has been overhauled. Before I considered a separate state machine to implement the rules. With the new rule GB9c this became more attractive and the design has changed. This change initially had quite an impact on the performance. By making the state machine persistent the performance was improved greatly. Note it is still slower than before due to the larger Unicode tables. Before -------------------------------------------------------------------- Benchmark Time CPU Iterations -------------------------------------------------------------------- BM_ascii_text 1891 ns 1889 ns 369504 BM_unicode_text 106642 ns 106397 ns 6576 BM_cyrillic_text 73420 ns 73277 ns 9445 BM_japanese_text 62485 ns 62387 ns 11153 BM_emoji_text 1895 ns 1893 ns 369525 BM_ascii_text 2015 ns 2013 ns 346887 BM_unicode_text 92119 ns 92017 ns 7598 BM_cyrillic_text 62637 ns 62568 ns 11117 BM_japanese_text 53850 ns 53785 ns 12803 BM_emoji_text 2016 ns 2014 ns 347325 After -------------------------------------------------------------------- Benchmark Time CPU Iterations -------------------------------------------------------------------- BM_ascii_text 1906 ns 1904 ns 369409 BM_unicode_text 265462 ns 265175 ns 2628 BM_cyrillic_text 181063 ns 180865 ns 3871 BM_japanese_text 130927 ns 130789 ns 5324 BM_emoji_text 1892 ns 1890 ns 370537 BM_ascii_text 2038 ns 2035 ns 343689 BM_unicode_text 277603 ns 277282 ns 2526 BM_cyrillic_text 188558 ns 188339 ns 3727 BM_japanese_text 133084 ns 132943 ns 5262 BM_emoji_text 2012 ns 2010 ns 348015 Persistent -------------------------------------------------------------------- Benchmark Time CPU Iterations -------------------------------------------------------------------- BM_ascii_text 1904 ns 1899 ns 367472 BM_unicode_text 133609 ns 133287 ns 5246 BM_cyrillic_text 90185 ns 89941 ns 7796 BM_japanese_text 75137 ns 74946 ns 9316 BM_emoji_text 1906 ns 1901 ns 368081 BM_ascii_text 2703 ns 2696 ns 259153 BM_unicode_text 131497 ns 131168 ns 5341 BM_cyrillic_text 87071 ns 86840 ns 8076 BM_japanese_text 72279 ns 72099 ns 9682 BM_emoji_text 2021 ns 2016 ns 346767 --- libcxx/docs/ReleaseNotes/19.rst | 3 + libcxx/include/CMakeLists.txt | 1 + .../include/__format/escaped_output_table.h | 11 +- .../__format/indic_conjunct_break_table.h | 350 ++ libcxx/include/__format/unicode.h | 313 +- .../include/__format/width_estimation_table.h | 7 +- libcxx/include/libcxx.imp | 1 + libcxx/include/module.modulemap | 2 + .../extended_grapheme_cluster.h | 2163 ++++++- .../extended_grapheme_cluster.pass.cpp | 15 + libcxx/utils/CMakeLists.txt | 8 + .../data/unicode/DerivedCoreProperties.txt | 277 +- .../data/unicode/DerivedGeneralCategory.txt | 22 +- libcxx/utils/data/unicode/EastAsianWidth.txt | 5170 +++++++++-------- .../data/unicode/GraphemeBreakProperty.txt | 6 +- .../utils/data/unicode/GraphemeBreakTest.txt | 727 ++- libcxx/utils/data/unicode/emoji-data.txt | 10 +- ...enerate_extended_grapheme_cluster_table.py | 25 +- .../generate_indic_conjunct_break_table.py | 309 + 19 files changed, 6412 insertions(+), 3008 deletions(-) create mode 100644 libcxx/include/__format/indic_conjunct_break_table.h create mode 100755 libcxx/utils/generate_indic_conjunct_break_table.py diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 399693f4f3e0..81c05b9112bd 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -56,6 +56,7 @@ Improvements and New Features resulting in a performance increase of up to 1400x. - The ``std::mismatch`` algorithm has been optimized for integral types, which can lead up to 40x performance improvements. + - The ``std::ranges::minmax`` algorithm has been optimized for integral types, resulting in a performance increase of up to 100x. @@ -64,6 +65,8 @@ Improvements and New Features - The ``_LIBCPP_ENABLE_CXX26_REMOVED_WSTRING_CONVERT`` macro has been added to make the declarations in ```` available. +- The formatting library is updated to Unicode 15.1.0. + Deprecations and Removals ------------------------- diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index 097a41d4c417..3cbca9ff4bd1 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -395,6 +395,7 @@ set(files __format/formatter_pointer.h __format/formatter_string.h __format/formatter_tuple.h + __format/indic_conjunct_break_table.h __format/parser_std_format_spec.h __format/range_default_formatter.h __format/range_formatter.h diff --git a/libcxx/include/__format/escaped_output_table.h b/libcxx/include/__format/escaped_output_table.h index e9f4a6e4f63f..b194f9431c3b 100644 --- a/libcxx/include/__format/escaped_output_table.h +++ b/libcxx/include/__format/escaped_output_table.h @@ -110,7 +110,7 @@ namespace __escaped_output_table { /// - bits [0, 10] The size of the range, allowing 2048 elements. /// - bits [11, 31] The lower bound code point of the range. The upper bound of /// the range is lower bound + size. -_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[893] = { +_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[894] = { 0x00000020, 0x0003f821, 0x00056800, @@ -464,14 +464,14 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[893] = { 0x0174d000, 0x0177a00b, 0x017eb019, - 0x017fe004, + 0x01800000, 0x01815005, 0x01820000, 0x0184b803, 0x01880004, 0x01898000, 0x018c7800, - 0x018f200b, + 0x018f200a, 0x0190f800, 0x05246802, 0x05263808, @@ -1000,8 +1000,9 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[893] = { 0x15b9d005, 0x15c0f001, 0x1675100d, - 0x175f0fff, - 0x179f0c1e, + 0x175f080e, + 0x1772f7ff, + 0x17b2f1a1, 0x17d0f5e1, 0x189a5804}; diff --git a/libcxx/include/__format/indic_conjunct_break_table.h b/libcxx/include/__format/indic_conjunct_break_table.h new file mode 100644 index 000000000000..44521d27498c --- /dev/null +++ b/libcxx/include/__format/indic_conjunct_break_table.h @@ -0,0 +1,350 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// WARNING, this entire header is generated by +// utils/generate_indic_conjunct_break_table.py +// DO NOT MODIFY! + +// UNICODE, INC. LICENSE AGREEMENT - DATA FILES AND SOFTWARE +// +// See Terms of Use +// for definitions of Unicode Inc.'s Data Files and Software. +// +// NOTICE TO USER: Carefully read the following legal agreement. +// BY DOWNLOADING, INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S +// DATA FILES ("DATA FILES"), AND/OR SOFTWARE ("SOFTWARE"), +// YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO BE BOUND BY, ALL OF THE +// TERMS AND CONDITIONS OF THIS AGREEMENT. +// IF YOU DO NOT AGREE, DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE +// THE DATA FILES OR SOFTWARE. +// +// COPYRIGHT AND PERMISSION NOTICE +// +// Copyright (c) 1991-2022 Unicode, Inc. All rights reserved. +// Distributed under the Terms of Use in https://www.unicode.org/copyright.html. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of the Unicode data files and any associated documentation +// (the "Data Files") or Unicode software and any associated documentation +// (the "Software") to deal in the Data Files or Software +// without restriction, including without limitation the rights to use, +// copy, modify, merge, publish, distribute, and/or sell copies of +// the Data Files or Software, and to permit persons to whom the Data Files +// or Software are furnished to do so, provided that either +// (a) this copyright and permission notice appear with all copies +// of the Data Files or Software, or +// (b) this copyright and permission notice appear in associated +// Documentation. +// +// THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF +// ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT OF THIRD PARTY RIGHTS. +// IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS +// NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL +// DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +// DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +// TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +// PERFORMANCE OF THE DATA FILES OR SOFTWARE. +// +// Except as contained in this notice, the name of a copyright holder +// shall not be used in advertising or otherwise to promote the sale, +// use or other dealings in these Data Files or Software without prior +// written authorization of the copyright holder. + +#ifndef _LIBCPP___FORMAT_INDIC_CONJUNCT_BREAK_TABLE_H +#define _LIBCPP___FORMAT_INDIC_CONJUNCT_BREAK_TABLE_H + +#include <__algorithm/ranges_upper_bound.h> +#include <__config> +#include <__iterator/access.h> +#include +#include + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +_LIBCPP_BEGIN_NAMESPACE_STD + +#if _LIBCPP_STD_VER >= 20 + +namespace __indic_conjunct_break { + +enum class __property : uint8_t { + // Values generated from the data files. + __Consonant, + __Extend, + __Linker, + + // The code unit has none of above properties. + __none +}; + +/// The entries of the indic conjunct break property table. +/// +/// The data is generated from +/// - https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt +/// +/// The data has 3 values +/// - bits [0, 1] The property. One of the values generated from the datafiles +/// of \ref __property +/// - bits [2, 10] The size of the range. +/// - bits [11, 31] The lower bound code point of the range. The upper bound of +/// the range is lower bound + size. +/// +/// The 9 bits for the size allow a maximum range of 512 elements. Some ranges +/// in the Unicode tables are larger. They are stored in multiple consecutive +/// ranges in the data table. An alternative would be to store the sizes in a +/// separate 16-bit value. The original MSVC STL code had such an approach, but +/// this approach uses less space for the data and is about 4% faster in the +/// following benchmark. +/// libcxx/benchmarks/std_format_spec_string_unicode.bench.cpp +// clang-format off +_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[201] = { + 0x00180139, + 0x001a807d, + 0x00241811, + 0x002c88b1, + 0x002df801, + 0x002e0805, + 0x002e2005, + 0x002e3801, + 0x00308029, + 0x00325851, + 0x00338001, + 0x0036b019, + 0x0036f815, + 0x00373805, + 0x0037500d, + 0x00388801, + 0x00398069, + 0x003f5821, + 0x003fe801, + 0x0040b00d, + 0x0040d821, + 0x00412809, + 0x00414811, + 0x0042c809, + 0x0044c01d, + 0x0046505d, + 0x00471871, + 0x0048a890, + 0x0049e001, + 0x004a6802, + 0x004a880d, + 0x004ac01c, + 0x004bc01c, + 0x004ca84c, + 0x004d5018, + 0x004d9000, + 0x004db00c, + 0x004de001, + 0x004e6802, + 0x004ee004, + 0x004ef800, + 0x004f8004, + 0x004ff001, + 0x0051e001, + 0x0054a84c, + 0x00555018, + 0x00559004, + 0x0055a810, + 0x0055e001, + 0x00566802, + 0x0057c800, + 0x0058a84c, + 0x00595018, + 0x00599004, + 0x0059a810, + 0x0059e001, + 0x005a6802, + 0x005ae004, + 0x005af800, + 0x005b8800, + 0x0060a84c, + 0x0061503c, + 0x0061e001, + 0x00626802, + 0x0062a805, + 0x0062c008, + 0x0065e001, + 0x0068a894, + 0x0069d805, + 0x006a6802, + 0x0071c009, + 0x0072400d, + 0x0075c009, + 0x0076400d, + 0x0078c005, + 0x0079a801, + 0x0079b801, + 0x0079c801, + 0x007b8805, + 0x007ba001, + 0x007bd00d, + 0x007c0001, + 0x007c1009, + 0x007c3005, + 0x007e3001, + 0x0081b801, + 0x0081c805, + 0x00846801, + 0x009ae809, + 0x00b8a001, + 0x00be9001, + 0x00bee801, + 0x00c54801, + 0x00c9c809, + 0x00d0b805, + 0x00d30001, + 0x00d3a81d, + 0x00d3f801, + 0x00d58035, + 0x00d5f83d, + 0x00d9a001, + 0x00db5821, + 0x00dd5801, + 0x00df3001, + 0x00e1b801, + 0x00e68009, + 0x00e6a031, + 0x00e71019, + 0x00e76801, + 0x00e7a001, + 0x00e7c005, + 0x00ee00fd, + 0x01006801, + 0x01068031, + 0x01070801, + 0x0107282d, + 0x01677809, + 0x016bf801, + 0x016f007d, + 0x01815015, + 0x0184c805, + 0x05337801, + 0x0533a025, + 0x0534f005, + 0x05378005, + 0x05416001, + 0x05470045, + 0x05495809, + 0x054d9801, + 0x05558001, + 0x05559009, + 0x0555b805, + 0x0555f005, + 0x05560801, + 0x0557b001, + 0x055f6801, + 0x07d8f001, + 0x07f1003d, + 0x080fe801, + 0x08170001, + 0x081bb011, + 0x08506801, + 0x08507801, + 0x0851c009, + 0x0851f801, + 0x08572805, + 0x0869200d, + 0x08755805, + 0x0877e809, + 0x087a3029, + 0x087c100d, + 0x08838001, + 0x0883f801, + 0x0885d001, + 0x08880009, + 0x08899805, + 0x088b9801, + 0x088e5001, + 0x0891b001, + 0x08974805, + 0x0899d805, + 0x089b3019, + 0x089b8011, + 0x08a23001, + 0x08a2f001, + 0x08a61801, + 0x08ae0001, + 0x08b5b801, + 0x08b95801, + 0x08c1d001, + 0x08c9f001, + 0x08ca1801, + 0x08d1a001, + 0x08d23801, + 0x08d4c801, + 0x08ea1001, + 0x08ea2005, + 0x08ecb801, + 0x08fa1001, + 0x0b578011, + 0x0b598019, + 0x0de4f001, + 0x0e8b2801, + 0x0e8b3809, + 0x0e8b7011, + 0x0e8bd81d, + 0x0e8c2819, + 0x0e8d500d, + 0x0e921009, + 0x0f000019, + 0x0f004041, + 0x0f00d819, + 0x0f011805, + 0x0f013011, + 0x0f047801, + 0x0f098019, + 0x0f157001, + 0x0f17600d, + 0x0f27600d, + 0x0f468019, + 0x0f4a2019}; +// clang-format on + +/// Returns the indic conjuct break property of a code point. +[[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr __property __get_property(const char32_t __code_point) noexcept { + // The algorithm searches for the upper bound of the range and, when found, + // steps back one entry. This algorithm is used since the code point can be + // anywhere in the range. After a lower bound is found the next step is to + // compare whether the code unit is indeed in the range. + // + // Since the entry contains a code unit, size, and property the code point + // being sought needs to be adjusted. Just shifting the code point to the + // proper position doesn't work; suppose an entry has property 0, size 1, + // and lower bound 3. This results in the entry 0x1810. + // When searching for code point 3 it will search for 0x1800, find 0x1810 + // and moves to the previous entry. Thus the lower bound value will never + // be found. + // The simple solution is to set the bits belonging to the property and + // size. Then the upper bound for code point 3 will return the entry after + // 0x1810. After moving to the previous entry the algorithm arrives at the + // correct entry. + ptrdiff_t __i = std::ranges::upper_bound(__entries, (__code_point << 11) | 0x7ffu) - __entries; + if (__i == 0) + return __property::__none; + + --__i; + uint32_t __upper_bound = (__entries[__i] >> 11) + ((__entries[__i] >> 2) & 0b1'1111'1111); + if (__code_point <= __upper_bound) + return static_cast<__property>(__entries[__i] & 0b11); + + return __property::__none; +} + +} // namespace __indic_conjunct_break + +#endif //_LIBCPP_STD_VER >= 20 + +_LIBCPP_END_NAMESPACE_STD + +#endif // _LIBCPP___FORMAT_INDIC_CONJUNCT_BREAK_TABLE_H diff --git a/libcxx/include/__format/unicode.h b/libcxx/include/__format/unicode.h index 40067ca3448b..de7d0fea1df5 100644 --- a/libcxx/include/__format/unicode.h +++ b/libcxx/include/__format/unicode.h @@ -15,8 +15,10 @@ #include <__concepts/same_as.h> #include <__config> #include <__format/extended_grapheme_cluster_table.h> +#include <__format/indic_conjunct_break_table.h> #include <__iterator/concepts.h> #include <__iterator/readable_traits.h> // iter_value_t +#include <__utility/unreachable.h> #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) @@ -292,84 +294,231 @@ private: }; # endif // _LIBCPP_HAS_NO_WIDE_CHARACTERS -_LIBCPP_HIDE_FROM_ABI constexpr bool __at_extended_grapheme_cluster_break( - bool& __ri_break_allowed, - bool __has_extened_pictographic, - __extended_grapheme_custer_property_boundary::__property __prev, - __extended_grapheme_custer_property_boundary::__property __next) { - using __extended_grapheme_custer_property_boundary::__property; +// State machine to implement the Extended Grapheme Cluster Boundary +// +// The exact rules may change between Unicode versions. +// This implements the extended rules see +// https://www.unicode.org/reports/tr29/#Grapheme_Cluster_Boundaries +class __extended_grapheme_cluster_break { + using __EGC_property = __extended_grapheme_custer_property_boundary::__property; + using __inCB_property = __indic_conjunct_break::__property; - __has_extened_pictographic |= __prev == __property::__Extended_Pictographic; +public: + _LIBCPP_HIDE_FROM_ABI constexpr explicit __extended_grapheme_cluster_break(char32_t __first_code_point) + : __prev_code_point_(__first_code_point), + __prev_property_(__extended_grapheme_custer_property_boundary::__get_property(__first_code_point)) { + // Initializes the active rule. + if (__prev_property_ == __EGC_property::__Extended_Pictographic) + __active_rule_ = __rule::__GB11_emoji; + else if (__prev_property_ == __EGC_property::__Regional_Indicator) + __active_rule_ = __rule::__GB12_GB13_regional_indicator; + else if (__indic_conjunct_break::__get_property(__first_code_point) == __inCB_property::__Consonant) + __active_rule_ = __rule::__GB9c_indic_conjunct_break; + } - // https://www.unicode.org/reports/tr29/tr29-39.html#Grapheme_Cluster_Boundary_Rules + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool operator()(char32_t __next_code_point) { + __EGC_property __next_property = __extended_grapheme_custer_property_boundary::__get_property(__next_code_point); + bool __result = __evaluate(__next_code_point, __next_property); + __prev_code_point_ = __next_code_point; + __prev_property_ = __next_property; + return __result; + } - // *** Break at the start and end of text, unless the text is empty. *** + // The code point whose break propery are considered during the next + // evaluation cyle. + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr char32_t __current_code_point() const { return __prev_code_point_; } - _LIBCPP_ASSERT_INTERNAL(__prev != __property::__sot, "should be handled in the constructor"); // GB1 - _LIBCPP_ASSERT_INTERNAL(__prev != __property::__eot, "should be handled by our caller"); // GB2 +private: + // The naming of the identifiers matches the Unicode standard. + // NOLINTBEGIN(readability-identifier-naming) + + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool + __evaluate(char32_t __next_code_point, __EGC_property __next_property) { + switch (__active_rule_) { + case __rule::__none: + return __evaluate_none(__next_code_point, __next_property); + case __rule::__GB9c_indic_conjunct_break: + return __evaluate_GB9c_indic_conjunct_break(__next_code_point, __next_property); + case __rule::__GB11_emoji: + return __evaluate_GB11_emoji(__next_code_point, __next_property); + case __rule::__GB12_GB13_regional_indicator: + return __evaluate_GB12_GB13_regional_indicator(__next_code_point, __next_property); + } + __libcpp_unreachable(); + } - // *** Do not break between a CR and LF. Otherwise, break before and after controls. *** - if (__prev == __property::__CR && __next == __property::__LF) // GB3 - return false; + _LIBCPP_HIDE_FROM_ABI constexpr bool __evaluate_none(char32_t __next_code_point, __EGC_property __next_property) { + // *** Break at the start and end of text, unless the text is empty. *** - if (__prev == __property::__Control || __prev == __property::__CR || __prev == __property::__LF) // GB4 - return true; + _LIBCPP_ASSERT_INTERNAL(__prev_property_ != __EGC_property::__sot, "should be handled in the constructor"); // GB1 + _LIBCPP_ASSERT_INTERNAL(__prev_property_ != __EGC_property::__eot, "should be handled by our caller"); // GB2 - if (__next == __property::__Control || __next == __property::__CR || __next == __property::__LF) // GB5 - return true; + // *** Do not break between a CR and LF. Otherwise, break before and after controls. *** + if (__prev_property_ == __EGC_property::__CR && __next_property == __EGC_property::__LF) // GB3 + return false; - // *** Do not break Hangul syllable sequences. *** - if (__prev == __property::__L && (__next == __property::__L || __next == __property::__V || - __next == __property::__LV || __next == __property::__LVT)) // GB6 - return false; + if (__prev_property_ == __EGC_property::__Control || __prev_property_ == __EGC_property::__CR || + __prev_property_ == __EGC_property::__LF) // GB4 + return true; - if ((__prev == __property::__LV || __prev == __property::__V) && - (__next == __property::__V || __next == __property::__T)) // GB7 - return false; + if (__next_property == __EGC_property::__Control || __next_property == __EGC_property::__CR || + __next_property == __EGC_property::__LF) // GB5 + return true; - if ((__prev == __property::__LVT || __prev == __property::__T) && __next == __property::__T) // GB8 - return false; + // *** Do not break Hangul syllable sequences. *** + if (__prev_property_ == __EGC_property::__L && + (__next_property == __EGC_property::__L || __next_property == __EGC_property::__V || + __next_property == __EGC_property::__LV || __next_property == __EGC_property::__LVT)) // GB6 + return false; - // *** Do not break before extending characters or ZWJ. *** - if (__next == __property::__Extend || __next == __property::__ZWJ) - return false; // GB9 + if ((__prev_property_ == __EGC_property::__LV || __prev_property_ == __EGC_property::__V) && + (__next_property == __EGC_property::__V || __next_property == __EGC_property::__T)) // GB7 + return false; - // *** Do not break before SpacingMarks, or after Prepend characters. *** - if (__next == __property::__SpacingMark) // GB9a - return false; + if ((__prev_property_ == __EGC_property::__LVT || __prev_property_ == __EGC_property::__T) && + __next_property == __EGC_property::__T) // GB8 + return false; - if (__prev == __property::__Prepend) // GB9b - return false; + // *** Do not break before extending characters or ZWJ. *** + if (__next_property == __EGC_property::__Extend || __next_property == __EGC_property::__ZWJ) + return false; // GB9 - // *** Do not break within emoji modifier sequences or emoji zwj sequences. *** + // *** Do not break before SpacingMarks, or after Prepend characters. *** + if (__next_property == __EGC_property::__SpacingMark) // GB9a + return false; - // GB11 \p{Extended_Pictographic} Extend* ZWJ x \p{Extended_Pictographic} - // - // Note that several parts of this rule are matched by GB9: Any x (Extend | ZWJ) - // - \p{Extended_Pictographic} x Extend - // - Extend x Extend - // - \p{Extended_Pictographic} x ZWJ - // - Extend x ZWJ - // - // So the only case left to test is - // - \p{Extended_Pictographic}' x ZWJ x \p{Extended_Pictographic} - // where \p{Extended_Pictographic}' is stored in __has_extened_pictographic - if (__has_extened_pictographic && __prev == __property::__ZWJ && __next == __property::__Extended_Pictographic) - return false; + if (__prev_property_ == __EGC_property::__Prepend) // GB9b + return false; - // *** Do not break within emoji flag sequences *** + // *** Do not break within certain combinations with Indic_Conjunct_Break (InCB)=Linker. *** + if (__indic_conjunct_break::__get_property(__next_code_point) == __inCB_property::__Consonant) { + __active_rule_ = __rule::__GB9c_indic_conjunct_break; + __GB9c_indic_conjunct_break_state_ = __GB9c_indic_conjunct_break_state::__Consonant; + return true; + } + + // *** Do not break within emoji modifier sequences or emoji zwj sequences. *** + if (__next_property == __EGC_property::__Extended_Pictographic) { + __active_rule_ = __rule::__GB11_emoji; + __GB11_emoji_state_ = __GB11_emoji_state::__Extended_Pictographic; + return true; + } + + // *** Do not break within emoji flag sequences *** - // That is, do not break between regional indicator (RI) symbols if there - // is an odd number of RI characters before the break point. + // That is, do not break between regional indicator (RI) symbols if there + // is an odd number of RI characters before the break point. + if (__next_property == __EGC_property::__Regional_Indicator) { // GB12 + GB13 + __active_rule_ = __rule::__GB12_GB13_regional_indicator; + return true; + } - if (__prev == __property::__Regional_Indicator && __next == __property::__Regional_Indicator) { // GB12 + GB13 - __ri_break_allowed = !__ri_break_allowed; - return __ri_break_allowed; + // *** Otherwise, break everywhere. *** + return true; // GB999 } - // *** Otherwise, break everywhere. *** - return true; // GB999 -} + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool + __evaluate_GB9c_indic_conjunct_break(char32_t __next_code_point, __EGC_property __next_property) { + __inCB_property __break = __indic_conjunct_break::__get_property(__next_code_point); + if (__break == __inCB_property::__none) { + __active_rule_ = __rule::__none; + return __evaluate_none(__next_code_point, __next_property); + } + + switch (__GB9c_indic_conjunct_break_state_) { + case __GB9c_indic_conjunct_break_state::__Consonant: + if (__break == __inCB_property::__Extend) { + return false; + } + if (__break == __inCB_property::__Linker) { + __GB9c_indic_conjunct_break_state_ = __GB9c_indic_conjunct_break_state::__Linker; + return false; + } + __active_rule_ = __rule::__none; + return __evaluate_none(__next_code_point, __next_property); + + case __GB9c_indic_conjunct_break_state::__Linker: + if (__break == __inCB_property::__Extend) { + return false; + } + if (__break == __inCB_property::__Linker) { + return false; + } + if (__break == __inCB_property::__Consonant) { + __GB9c_indic_conjunct_break_state_ = __GB9c_indic_conjunct_break_state::__Consonant; + return false; + } + __active_rule_ = __rule::__none; + return __evaluate_none(__next_code_point, __next_property); + } + __libcpp_unreachable(); + } + + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool + __evaluate_GB11_emoji(char32_t __next_code_point, __EGC_property __next_property) { + switch (__GB11_emoji_state_) { + case __GB11_emoji_state::__Extended_Pictographic: + if (__next_property == __EGC_property::__Extend) { + __GB11_emoji_state_ = __GB11_emoji_state::__Extend; + return false; + } + [[fallthrough]]; + case __GB11_emoji_state::__Extend: + if (__next_property == __EGC_property::__ZWJ) { + __GB11_emoji_state_ = __GB11_emoji_state::__ZWJ; + return false; + } + if (__next_property == __EGC_property::__Extend) + return false; + __active_rule_ = __rule::__none; + return __evaluate_none(__next_code_point, __next_property); + + case __GB11_emoji_state::__ZWJ: + if (__next_property == __EGC_property::__Extended_Pictographic) { + __GB11_emoji_state_ = __GB11_emoji_state::__Extended_Pictographic; + return false; + } + __active_rule_ = __rule::__none; + return __evaluate_none(__next_code_point, __next_property); + } + __libcpp_unreachable(); + } + + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool + __evaluate_GB12_GB13_regional_indicator(char32_t __next_code_point, __EGC_property __next_property) { + __active_rule_ = __rule::__none; + if (__next_property == __EGC_property::__Regional_Indicator) + return false; + return __evaluate_none(__next_code_point, __next_property); + } + + char32_t __prev_code_point_; + __EGC_property __prev_property_; + + enum class __rule { + __none, + __GB9c_indic_conjunct_break, + __GB11_emoji, + __GB12_GB13_regional_indicator, + }; + __rule __active_rule_ = __rule::__none; + + enum class __GB11_emoji_state { + __Extended_Pictographic, + __Extend, + __ZWJ, + }; + __GB11_emoji_state __GB11_emoji_state_ = __GB11_emoji_state::__Extended_Pictographic; + + enum class __GB9c_indic_conjunct_break_state { + __Consonant, + __Linker, + }; + + __GB9c_indic_conjunct_break_state __GB9c_indic_conjunct_break_state_ = __GB9c_indic_conjunct_break_state::__Consonant; + + // NOLINTEND(readability-identifier-naming) +}; /// Helper class to extract an extended grapheme cluster from a Unicode character range. /// @@ -382,9 +531,7 @@ class __extended_grapheme_cluster_view { public: _LIBCPP_HIDE_FROM_ABI constexpr explicit __extended_grapheme_cluster_view(_Iterator __first, _Iterator __last) - : __code_point_view_(__first, __last), - __next_code_point_(__code_point_view_.__consume().__code_point), - __next_prop_(__extended_grapheme_custer_property_boundary::__get_property(__next_code_point_)) {} + : __code_point_view_(__first, __last), __at_break_(__code_point_view_.__consume().__code_point) {} struct __cluster { /// The first code point of the extended grapheme cluster. @@ -400,44 +547,20 @@ public: _Iterator __last_; }; - _LIBCPP_HIDE_FROM_ABI constexpr __cluster __consume() { - _LIBCPP_ASSERT_INTERNAL(__next_prop_ != __extended_grapheme_custer_property_boundary::__property::__eot, - "can't move beyond the end of input"); - - char32_t __code_point = __next_code_point_; - if (!__code_point_view_.__at_end()) - return {__code_point, __get_break()}; - - __next_prop_ = __extended_grapheme_custer_property_boundary::__property::__eot; - return {__code_point, __code_point_view_.__position()}; + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr __cluster __consume() { + char32_t __code_point = __at_break_.__current_code_point(); + _Iterator __position = __code_point_view_.__position(); + while (!__code_point_view_.__at_end()) { + if (__at_break_(__code_point_view_.__consume().__code_point)) + break; + __position = __code_point_view_.__position(); + } + return {__code_point, __position}; } private: __code_point_view<_CharT> __code_point_view_; - - char32_t __next_code_point_; - __extended_grapheme_custer_property_boundary::__property __next_prop_; - - _LIBCPP_HIDE_FROM_ABI constexpr _Iterator __get_break() { - bool __ri_break_allowed = true; - bool __has_extened_pictographic = false; - while (true) { - _Iterator __result = __code_point_view_.__position(); - __extended_grapheme_custer_property_boundary::__property __prev = __next_prop_; - if (__code_point_view_.__at_end()) { - __next_prop_ = __extended_grapheme_custer_property_boundary::__property::__eot; - return __result; - } - __next_code_point_ = __code_point_view_.__consume().__code_point; - __next_prop_ = __extended_grapheme_custer_property_boundary::__get_property(__next_code_point_); - - __has_extened_pictographic |= - __prev == __extended_grapheme_custer_property_boundary::__property::__Extended_Pictographic; - - if (__at_extended_grapheme_cluster_break(__ri_break_allowed, __has_extened_pictographic, __prev, __next_prop_)) - return __result; - } - } + __extended_grapheme_cluster_break __at_break_; }; template diff --git a/libcxx/include/__format/width_estimation_table.h b/libcxx/include/__format/width_estimation_table.h index 6309483367f1..c9a9f6719c61 100644 --- a/libcxx/include/__format/width_estimation_table.h +++ b/libcxx/include/__format/width_estimation_table.h @@ -119,7 +119,7 @@ namespace __width_estimation_table { /// - bits [0, 13] The size of the range, allowing 16384 elements. /// - bits [14, 31] The lower bound code point of the range. The upper bound of /// the range is lower bound + size. -_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[108] = { +_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[107] = { 0x0440005f /* 00001100 - 0000115f [ 96] */, // 0x08c68001 /* 0000231a - 0000231b [ 2] */, // 0x08ca4001 /* 00002329 - 0000232a [ 2] */, // @@ -158,14 +158,13 @@ _LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[108] = { 0x0ba00019 /* 00002e80 - 00002e99 [ 26] */, // 0x0ba6c058 /* 00002e9b - 00002ef3 [ 89] */, // 0x0bc000d5 /* 00002f00 - 00002fd5 [ 214] */, // - 0x0bfc000b /* 00002ff0 - 00002ffb [ 12] */, // - 0x0c00003e /* 00003000 - 0000303e [ 63] */, // + 0x0bfc004e /* 00002ff0 - 0000303e [ 79] */, // 0x0c104055 /* 00003041 - 00003096 [ 86] */, // 0x0c264066 /* 00003099 - 000030ff [ 103] */, // 0x0c41402a /* 00003105 - 0000312f [ 43] */, // 0x0c4c405d /* 00003131 - 0000318e [ 94] */, // 0x0c640053 /* 00003190 - 000031e3 [ 84] */, // - 0x0c7c002e /* 000031f0 - 0000321e [ 47] */, // + 0x0c7bc02f /* 000031ef - 0000321e [ 48] */, // 0x0c880027 /* 00003220 - 00003247 [ 40] */, // 0x0c943fff /* 00003250 - 0000724f [16384] */, // 0x1c94323c /* 00007250 - 0000a48c [12861] */, // diff --git a/libcxx/include/libcxx.imp b/libcxx/include/libcxx.imp index 607f63e6d822..a79e8fedbdac 100644 --- a/libcxx/include/libcxx.imp +++ b/libcxx/include/libcxx.imp @@ -389,6 +389,7 @@ { include: [ "<__format/formatter_pointer.h>", "private", "", "public" ] }, { include: [ "<__format/formatter_string.h>", "private", "", "public" ] }, { include: [ "<__format/formatter_tuple.h>", "private", "", "public" ] }, + { include: [ "<__format/indic_conjunct_break_table.h>", "private", "", "public" ] }, { include: [ "<__format/parser_std_format_spec.h>", "private", "", "public" ] }, { include: [ "<__format/range_default_formatter.h>", "private", "", "public" ] }, { include: [ "<__format/range_formatter.h>", "private", "", "public" ] }, diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index ed45a1b18338..e1637907b3ec 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -1339,12 +1339,14 @@ module std_private_format_formatter_output [system] { header "__f module std_private_format_formatter_pointer [system] { header "__format/formatter_pointer.h" } module std_private_format_formatter_string [system] { header "__format/formatter_string.h" } module std_private_format_formatter_tuple [system] { header "__format/formatter_tuple.h" } +module std_private_format_indic_conjunct_break_table [system] { header "__format/indic_conjunct_break_table.h" } module std_private_format_parser_std_format_spec [system] { header "__format/parser_std_format_spec.h" } module std_private_format_range_default_formatter [system] { header "__format/range_default_formatter.h" } module std_private_format_range_formatter [system] { header "__format/range_formatter.h" } module std_private_format_unicode [system] { header "__format/unicode.h" export std_private_format_extended_grapheme_cluster_table + export std_private_format_indic_conjunct_break_table } module std_private_format_width_estimation_table [system] { header "__format/width_estimation_table.h" } module std_private_format_write_escaped [system] { header "__format/write_escaped.h" } diff --git a/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h b/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h index 204dcacb1152..eb7500a828cc 100644 --- a/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h +++ b/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.h @@ -82,7 +82,7 @@ struct data { }; /// The data for UTF-8. -std::array, 602> data_utf8 = {{ +std::array, 1187> data_utf8 = {{ {"\U00000020\U00000020", {32, 32}, {1, 2}}, {"\U00000020\U00000308\U00000020", {32, 32}, {3, 4}}, {"\U00000020\U0000000d", {32, 13}, {1, 2}}, @@ -97,8 +97,8 @@ std::array, 602> data_utf8 = {{ {"\U00000020\U00000308\U0001f1e6", {32, 127462}, {3, 7}}, {"\U00000020\U00000600", {32, 1536}, {1, 3}}, {"\U00000020\U00000308\U00000600", {32, 1536}, {3, 5}}, - {"\U00000020\U00000903", {32}, {4}}, - {"\U00000020\U00000308\U00000903", {32}, {6}}, + {"\U00000020\U00000a03", {32}, {4}}, + {"\U00000020\U00000308\U00000a03", {32}, {6}}, {"\U00000020\U00001100", {32, 4352}, {1, 4}}, {"\U00000020\U00000308\U00001100", {32, 4352}, {3, 6}}, {"\U00000020\U00001160", {32, 4448}, {1, 4}}, @@ -109,10 +109,24 @@ std::array, 602> data_utf8 = {{ {"\U00000020\U00000308\U0000ac00", {32, 44032}, {3, 6}}, {"\U00000020\U0000ac01", {32, 44033}, {1, 4}}, {"\U00000020\U00000308\U0000ac01", {32, 44033}, {3, 6}}, + {"\U00000020\U00000900", {32}, {4}}, + {"\U00000020\U00000308\U00000900", {32}, {6}}, + {"\U00000020\U00000903", {32}, {4}}, + {"\U00000020\U00000308\U00000903", {32}, {6}}, + {"\U00000020\U00000904", {32, 2308}, {1, 4}}, + {"\U00000020\U00000308\U00000904", {32, 2308}, {3, 6}}, + {"\U00000020\U00000d4e", {32, 3406}, {1, 4}}, + {"\U00000020\U00000308\U00000d4e", {32, 3406}, {3, 6}}, + {"\U00000020\U00000915", {32, 2325}, {1, 4}}, + {"\U00000020\U00000308\U00000915", {32, 2325}, {3, 6}}, {"\U00000020\U0000231a", {32, 8986}, {1, 4}}, {"\U00000020\U00000308\U0000231a", {32, 8986}, {3, 6}}, {"\U00000020\U00000300", {32}, {3}}, {"\U00000020\U00000308\U00000300", {32}, {5}}, + {"\U00000020\U0000093c", {32}, {4}}, + {"\U00000020\U00000308\U0000093c", {32}, {6}}, + {"\U00000020\U0000094d", {32}, {4}}, + {"\U00000020\U00000308\U0000094d", {32}, {6}}, {"\U00000020\U0000200d", {32}, {4}}, {"\U00000020\U00000308\U0000200d", {32}, {6}}, {"\U00000020\U00000378", {32, 888}, {1, 3}}, @@ -131,8 +145,8 @@ std::array, 602> data_utf8 = {{ {"\U0000000d\U00000308\U0001f1e6", {13, 776, 127462}, {1, 3, 7}}, {"\U0000000d\U00000600", {13, 1536}, {1, 3}}, {"\U0000000d\U00000308\U00000600", {13, 776, 1536}, {1, 3, 5}}, - {"\U0000000d\U00000903", {13, 2307}, {1, 4}}, - {"\U0000000d\U00000308\U00000903", {13, 776}, {1, 6}}, + {"\U0000000d\U00000a03", {13, 2563}, {1, 4}}, + {"\U0000000d\U00000308\U00000a03", {13, 776}, {1, 6}}, {"\U0000000d\U00001100", {13, 4352}, {1, 4}}, {"\U0000000d\U00000308\U00001100", {13, 776, 4352}, {1, 3, 6}}, {"\U0000000d\U00001160", {13, 4448}, {1, 4}}, @@ -143,10 +157,24 @@ std::array, 602> data_utf8 = {{ {"\U0000000d\U00000308\U0000ac00", {13, 776, 44032}, {1, 3, 6}}, {"\U0000000d\U0000ac01", {13, 44033}, {1, 4}}, {"\U0000000d\U00000308\U0000ac01", {13, 776, 44033}, {1, 3, 6}}, + {"\U0000000d\U00000900", {13, 2304}, {1, 4}}, + {"\U0000000d\U00000308\U00000900", {13, 776}, {1, 6}}, + {"\U0000000d\U00000903", {13, 2307}, {1, 4}}, + {"\U0000000d\U00000308\U00000903", {13, 776}, {1, 6}}, + {"\U0000000d\U00000904", {13, 2308}, {1, 4}}, + {"\U0000000d\U00000308\U00000904", {13, 776, 2308}, {1, 3, 6}}, + {"\U0000000d\U00000d4e", {13, 3406}, {1, 4}}, + {"\U0000000d\U00000308\U00000d4e", {13, 776, 3406}, {1, 3, 6}}, + {"\U0000000d\U00000915", {13, 2325}, {1, 4}}, + {"\U0000000d\U00000308\U00000915", {13, 776, 2325}, {1, 3, 6}}, {"\U0000000d\U0000231a", {13, 8986}, {1, 4}}, {"\U0000000d\U00000308\U0000231a", {13, 776, 8986}, {1, 3, 6}}, {"\U0000000d\U00000300", {13, 768}, {1, 3}}, {"\U0000000d\U00000308\U00000300", {13, 776}, {1, 5}}, + {"\U0000000d\U0000093c", {13, 2364}, {1, 4}}, + {"\U0000000d\U00000308\U0000093c", {13, 776}, {1, 6}}, + {"\U0000000d\U0000094d", {13, 2381}, {1, 4}}, + {"\U0000000d\U00000308\U0000094d", {13, 776}, {1, 6}}, {"\U0000000d\U0000200d", {13, 8205}, {1, 4}}, {"\U0000000d\U00000308\U0000200d", {13, 776}, {1, 6}}, {"\U0000000d\U00000378", {13, 888}, {1, 3}}, @@ -165,8 +193,8 @@ std::array, 602> data_utf8 = {{ {"\U0000000a\U00000308\U0001f1e6", {10, 776, 127462}, {1, 3, 7}}, {"\U0000000a\U00000600", {10, 1536}, {1, 3}}, {"\U0000000a\U00000308\U00000600", {10, 776, 1536}, {1, 3, 5}}, - {"\U0000000a\U00000903", {10, 2307}, {1, 4}}, - {"\U0000000a\U00000308\U00000903", {10, 776}, {1, 6}}, + {"\U0000000a\U00000a03", {10, 2563}, {1, 4}}, + {"\U0000000a\U00000308\U00000a03", {10, 776}, {1, 6}}, {"\U0000000a\U00001100", {10, 4352}, {1, 4}}, {"\U0000000a\U00000308\U00001100", {10, 776, 4352}, {1, 3, 6}}, {"\U0000000a\U00001160", {10, 4448}, {1, 4}}, @@ -177,10 +205,24 @@ std::array, 602> data_utf8 = {{ {"\U0000000a\U00000308\U0000ac00", {10, 776, 44032}, {1, 3, 6}}, {"\U0000000a\U0000ac01", {10, 44033}, {1, 4}}, {"\U0000000a\U00000308\U0000ac01", {10, 776, 44033}, {1, 3, 6}}, + {"\U0000000a\U00000900", {10, 2304}, {1, 4}}, + {"\U0000000a\U00000308\U00000900", {10, 776}, {1, 6}}, + {"\U0000000a\U00000903", {10, 2307}, {1, 4}}, + {"\U0000000a\U00000308\U00000903", {10, 776}, {1, 6}}, + {"\U0000000a\U00000904", {10, 2308}, {1, 4}}, + {"\U0000000a\U00000308\U00000904", {10, 776, 2308}, {1, 3, 6}}, + {"\U0000000a\U00000d4e", {10, 3406}, {1, 4}}, + {"\U0000000a\U00000308\U00000d4e", {10, 776, 3406}, {1, 3, 6}}, + {"\U0000000a\U00000915", {10, 2325}, {1, 4}}, + {"\U0000000a\U00000308\U00000915", {10, 776, 2325}, {1, 3, 6}}, {"\U0000000a\U0000231a", {10, 8986}, {1, 4}}, {"\U0000000a\U00000308\U0000231a", {10, 776, 8986}, {1, 3, 6}}, {"\U0000000a\U00000300", {10, 768}, {1, 3}}, {"\U0000000a\U00000308\U00000300", {10, 776}, {1, 5}}, + {"\U0000000a\U0000093c", {10, 2364}, {1, 4}}, + {"\U0000000a\U00000308\U0000093c", {10, 776}, {1, 6}}, + {"\U0000000a\U0000094d", {10, 2381}, {1, 4}}, + {"\U0000000a\U00000308\U0000094d", {10, 776}, {1, 6}}, {"\U0000000a\U0000200d", {10, 8205}, {1, 4}}, {"\U0000000a\U00000308\U0000200d", {10, 776}, {1, 6}}, {"\U0000000a\U00000378", {10, 888}, {1, 3}}, @@ -199,8 +241,8 @@ std::array, 602> data_utf8 = {{ {"\U00000001\U00000308\U0001f1e6", {1, 776, 127462}, {1, 3, 7}}, {"\U00000001\U00000600", {1, 1536}, {1, 3}}, {"\U00000001\U00000308\U00000600", {1, 776, 1536}, {1, 3, 5}}, - {"\U00000001\U00000903", {1, 2307}, {1, 4}}, - {"\U00000001\U00000308\U00000903", {1, 776}, {1, 6}}, + {"\U00000001\U00000a03", {1, 2563}, {1, 4}}, + {"\U00000001\U00000308\U00000a03", {1, 776}, {1, 6}}, {"\U00000001\U00001100", {1, 4352}, {1, 4}}, {"\U00000001\U00000308\U00001100", {1, 776, 4352}, {1, 3, 6}}, {"\U00000001\U00001160", {1, 4448}, {1, 4}}, @@ -211,10 +253,24 @@ std::array, 602> data_utf8 = {{ {"\U00000001\U00000308\U0000ac00", {1, 776, 44032}, {1, 3, 6}}, {"\U00000001\U0000ac01", {1, 44033}, {1, 4}}, {"\U00000001\U00000308\U0000ac01", {1, 776, 44033}, {1, 3, 6}}, + {"\U00000001\U00000900", {1, 2304}, {1, 4}}, + {"\U00000001\U00000308\U00000900", {1, 776}, {1, 6}}, + {"\U00000001\U00000903", {1, 2307}, {1, 4}}, + {"\U00000001\U00000308\U00000903", {1, 776}, {1, 6}}, + {"\U00000001\U00000904", {1, 2308}, {1, 4}}, + {"\U00000001\U00000308\U00000904", {1, 776, 2308}, {1, 3, 6}}, + {"\U00000001\U00000d4e", {1, 3406}, {1, 4}}, + {"\U00000001\U00000308\U00000d4e", {1, 776, 3406}, {1, 3, 6}}, + {"\U00000001\U00000915", {1, 2325}, {1, 4}}, + {"\U00000001\U00000308\U00000915", {1, 776, 2325}, {1, 3, 6}}, {"\U00000001\U0000231a", {1, 8986}, {1, 4}}, {"\U00000001\U00000308\U0000231a", {1, 776, 8986}, {1, 3, 6}}, {"\U00000001\U00000300", {1, 768}, {1, 3}}, {"\U00000001\U00000308\U00000300", {1, 776}, {1, 5}}, + {"\U00000001\U0000093c", {1, 2364}, {1, 4}}, + {"\U00000001\U00000308\U0000093c", {1, 776}, {1, 6}}, + {"\U00000001\U0000094d", {1, 2381}, {1, 4}}, + {"\U00000001\U00000308\U0000094d", {1, 776}, {1, 6}}, {"\U00000001\U0000200d", {1, 8205}, {1, 4}}, {"\U00000001\U00000308\U0000200d", {1, 776}, {1, 6}}, {"\U00000001\U00000378", {1, 888}, {1, 3}}, @@ -233,8 +289,8 @@ std::array, 602> data_utf8 = {{ {"\U0000034f\U00000308\U0001f1e6", {847, 127462}, {4, 8}}, {"\U0000034f\U00000600", {847, 1536}, {2, 4}}, {"\U0000034f\U00000308\U00000600", {847, 1536}, {4, 6}}, - {"\U0000034f\U00000903", {847}, {5}}, - {"\U0000034f\U00000308\U00000903", {847}, {7}}, + {"\U0000034f\U00000a03", {847}, {5}}, + {"\U0000034f\U00000308\U00000a03", {847}, {7}}, {"\U0000034f\U00001100", {847, 4352}, {2, 5}}, {"\U0000034f\U00000308\U00001100", {847, 4352}, {4, 7}}, {"\U0000034f\U00001160", {847, 4448}, {2, 5}}, @@ -245,10 +301,24 @@ std::array, 602> data_utf8 = {{ {"\U0000034f\U00000308\U0000ac00", {847, 44032}, {4, 7}}, {"\U0000034f\U0000ac01", {847, 44033}, {2, 5}}, {"\U0000034f\U00000308\U0000ac01", {847, 44033}, {4, 7}}, + {"\U0000034f\U00000900", {847}, {5}}, + {"\U0000034f\U00000308\U00000900", {847}, {7}}, + {"\U0000034f\U00000903", {847}, {5}}, + {"\U0000034f\U00000308\U00000903", {847}, {7}}, + {"\U0000034f\U00000904", {847, 2308}, {2, 5}}, + {"\U0000034f\U00000308\U00000904", {847, 2308}, {4, 7}}, + {"\U0000034f\U00000d4e", {847, 3406}, {2, 5}}, + {"\U0000034f\U00000308\U00000d4e", {847, 3406}, {4, 7}}, + {"\U0000034f\U00000915", {847, 2325}, {2, 5}}, + {"\U0000034f\U00000308\U00000915", {847, 2325}, {4, 7}}, {"\U0000034f\U0000231a", {847, 8986}, {2, 5}}, {"\U0000034f\U00000308\U0000231a", {847, 8986}, {4, 7}}, {"\U0000034f\U00000300", {847}, {4}}, {"\U0000034f\U00000308\U00000300", {847}, {6}}, + {"\U0000034f\U0000093c", {847}, {5}}, + {"\U0000034f\U00000308\U0000093c", {847}, {7}}, + {"\U0000034f\U0000094d", {847}, {5}}, + {"\U0000034f\U00000308\U0000094d", {847}, {7}}, {"\U0000034f\U0000200d", {847}, {5}}, {"\U0000034f\U00000308\U0000200d", {847}, {7}}, {"\U0000034f\U00000378", {847, 888}, {2, 4}}, @@ -267,8 +337,8 @@ std::array, 602> data_utf8 = {{ {"\U0001f1e6\U00000308\U0001f1e6", {127462, 127462}, {6, 10}}, {"\U0001f1e6\U00000600", {127462, 1536}, {4, 6}}, {"\U0001f1e6\U00000308\U00000600", {127462, 1536}, {6, 8}}, - {"\U0001f1e6\U00000903", {127462}, {7}}, - {"\U0001f1e6\U00000308\U00000903", {127462}, {9}}, + {"\U0001f1e6\U00000a03", {127462}, {7}}, + {"\U0001f1e6\U00000308\U00000a03", {127462}, {9}}, {"\U0001f1e6\U00001100", {127462, 4352}, {4, 7}}, {"\U0001f1e6\U00000308\U00001100", {127462, 4352}, {6, 9}}, {"\U0001f1e6\U00001160", {127462, 4448}, {4, 7}}, @@ -279,10 +349,24 @@ std::array, 602> data_utf8 = {{ {"\U0001f1e6\U00000308\U0000ac00", {127462, 44032}, {6, 9}}, {"\U0001f1e6\U0000ac01", {127462, 44033}, {4, 7}}, {"\U0001f1e6\U00000308\U0000ac01", {127462, 44033}, {6, 9}}, + {"\U0001f1e6\U00000900", {127462}, {7}}, + {"\U0001f1e6\U00000308\U00000900", {127462}, {9}}, + {"\U0001f1e6\U00000903", {127462}, {7}}, + {"\U0001f1e6\U00000308\U00000903", {127462}, {9}}, + {"\U0001f1e6\U00000904", {127462, 2308}, {4, 7}}, + {"\U0001f1e6\U00000308\U00000904", {127462, 2308}, {6, 9}}, + {"\U0001f1e6\U00000d4e", {127462, 3406}, {4, 7}}, + {"\U0001f1e6\U00000308\U00000d4e", {127462, 3406}, {6, 9}}, + {"\U0001f1e6\U00000915", {127462, 2325}, {4, 7}}, + {"\U0001f1e6\U00000308\U00000915", {127462, 2325}, {6, 9}}, {"\U0001f1e6\U0000231a", {127462, 8986}, {4, 7}}, {"\U0001f1e6\U00000308\U0000231a", {127462, 8986}, {6, 9}}, {"\U0001f1e6\U00000300", {127462}, {6}}, {"\U0001f1e6\U00000308\U00000300", {127462}, {8}}, + {"\U0001f1e6\U0000093c", {127462}, {7}}, + {"\U0001f1e6\U00000308\U0000093c", {127462}, {9}}, + {"\U0001f1e6\U0000094d", {127462}, {7}}, + {"\U0001f1e6\U00000308\U0000094d", {127462}, {9}}, {"\U0001f1e6\U0000200d", {127462}, {7}}, {"\U0001f1e6\U00000308\U0000200d", {127462}, {9}}, {"\U0001f1e6\U00000378", {127462, 888}, {4, 6}}, @@ -301,8 +385,8 @@ std::array, 602> data_utf8 = {{ {"\U00000600\U00000308\U0001f1e6", {1536, 127462}, {4, 8}}, {"\U00000600\U00000600", {1536}, {4}}, {"\U00000600\U00000308\U00000600", {1536, 1536}, {4, 6}}, - {"\U00000600\U00000903", {1536}, {5}}, - {"\U00000600\U00000308\U00000903", {1536}, {7}}, + {"\U00000600\U00000a03", {1536}, {5}}, + {"\U00000600\U00000308\U00000a03", {1536}, {7}}, {"\U00000600\U00001100", {1536}, {5}}, {"\U00000600\U00000308\U00001100", {1536, 4352}, {4, 7}}, {"\U00000600\U00001160", {1536}, {5}}, @@ -313,48 +397,76 @@ std::array, 602> data_utf8 = {{ {"\U00000600\U00000308\U0000ac00", {1536, 44032}, {4, 7}}, {"\U00000600\U0000ac01", {1536}, {5}}, {"\U00000600\U00000308\U0000ac01", {1536, 44033}, {4, 7}}, + {"\U00000600\U00000900", {1536}, {5}}, + {"\U00000600\U00000308\U00000900", {1536}, {7}}, + {"\U00000600\U00000903", {1536}, {5}}, + {"\U00000600\U00000308\U00000903", {1536}, {7}}, + {"\U00000600\U00000904", {1536}, {5}}, + {"\U00000600\U00000308\U00000904", {1536, 2308}, {4, 7}}, + {"\U00000600\U00000d4e", {1536}, {5}}, + {"\U00000600\U00000308\U00000d4e", {1536, 3406}, {4, 7}}, + {"\U00000600\U00000915", {1536}, {5}}, + {"\U00000600\U00000308\U00000915", {1536, 2325}, {4, 7}}, {"\U00000600\U0000231a", {1536}, {5}}, {"\U00000600\U00000308\U0000231a", {1536, 8986}, {4, 7}}, {"\U00000600\U00000300", {1536}, {4}}, {"\U00000600\U00000308\U00000300", {1536}, {6}}, + {"\U00000600\U0000093c", {1536}, {5}}, + {"\U00000600\U00000308\U0000093c", {1536}, {7}}, + {"\U00000600\U0000094d", {1536}, {5}}, + {"\U00000600\U00000308\U0000094d", {1536}, {7}}, {"\U00000600\U0000200d", {1536}, {5}}, {"\U00000600\U00000308\U0000200d", {1536}, {7}}, {"\U00000600\U00000378", {1536}, {4}}, {"\U00000600\U00000308\U00000378", {1536, 888}, {4, 6}}, - {"\U00000903\U00000020", {2307, 32}, {3, 4}}, - {"\U00000903\U00000308\U00000020", {2307, 32}, {5, 6}}, - {"\U00000903\U0000000d", {2307, 13}, {3, 4}}, - {"\U00000903\U00000308\U0000000d", {2307, 13}, {5, 6}}, - {"\U00000903\U0000000a", {2307, 10}, {3, 4}}, - {"\U00000903\U00000308\U0000000a", {2307, 10}, {5, 6}}, - {"\U00000903\U00000001", {2307, 1}, {3, 4}}, - {"\U00000903\U00000308\U00000001", {2307, 1}, {5, 6}}, - {"\U00000903\U0000034f", {2307}, {5}}, - {"\U00000903\U00000308\U0000034f", {2307}, {7}}, - {"\U00000903\U0001f1e6", {2307, 127462}, {3, 7}}, - {"\U00000903\U00000308\U0001f1e6", {2307, 127462}, {5, 9}}, - {"\U00000903\U00000600", {2307, 1536}, {3, 5}}, - {"\U00000903\U00000308\U00000600", {2307, 1536}, {5, 7}}, - {"\U00000903\U00000903", {2307}, {6}}, - {"\U00000903\U00000308\U00000903", {2307}, {8}}, - {"\U00000903\U00001100", {2307, 4352}, {3, 6}}, - {"\U00000903\U00000308\U00001100", {2307, 4352}, {5, 8}}, - {"\U00000903\U00001160", {2307, 4448}, {3, 6}}, - {"\U00000903\U00000308\U00001160", {2307, 4448}, {5, 8}}, - {"\U00000903\U000011a8", {2307, 4520}, {3, 6}}, - {"\U00000903\U00000308\U000011a8", {2307, 4520}, {5, 8}}, - {"\U00000903\U0000ac00", {2307, 44032}, {3, 6}}, - {"\U00000903\U00000308\U0000ac00", {2307, 44032}, {5, 8}}, - {"\U00000903\U0000ac01", {2307, 44033}, {3, 6}}, - {"\U00000903\U00000308\U0000ac01", {2307, 44033}, {5, 8}}, - {"\U00000903\U0000231a", {2307, 8986}, {3, 6}}, - {"\U00000903\U00000308\U0000231a", {2307, 8986}, {5, 8}}, - {"\U00000903\U00000300", {2307}, {5}}, - {"\U00000903\U00000308\U00000300", {2307}, {7}}, - {"\U00000903\U0000200d", {2307}, {6}}, - {"\U00000903\U00000308\U0000200d", {2307}, {8}}, - {"\U00000903\U00000378", {2307, 888}, {3, 5}}, - {"\U00000903\U00000308\U00000378", {2307, 888}, {5, 7}}, + {"\U00000a03\U00000020", {2563, 32}, {3, 4}}, + {"\U00000a03\U00000308\U00000020", {2563, 32}, {5, 6}}, + {"\U00000a03\U0000000d", {2563, 13}, {3, 4}}, + {"\U00000a03\U00000308\U0000000d", {2563, 13}, {5, 6}}, + {"\U00000a03\U0000000a", {2563, 10}, {3, 4}}, + {"\U00000a03\U00000308\U0000000a", {2563, 10}, {5, 6}}, + {"\U00000a03\U00000001", {2563, 1}, {3, 4}}, + {"\U00000a03\U00000308\U00000001", {2563, 1}, {5, 6}}, + {"\U00000a03\U0000034f", {2563}, {5}}, + {"\U00000a03\U00000308\U0000034f", {2563}, {7}}, + {"\U00000a03\U0001f1e6", {2563, 127462}, {3, 7}}, + {"\U00000a03\U00000308\U0001f1e6", {2563, 127462}, {5, 9}}, + {"\U00000a03\U00000600", {2563, 1536}, {3, 5}}, + {"\U00000a03\U00000308\U00000600", {2563, 1536}, {5, 7}}, + {"\U00000a03\U00000a03", {2563}, {6}}, + {"\U00000a03\U00000308\U00000a03", {2563}, {8}}, + {"\U00000a03\U00001100", {2563, 4352}, {3, 6}}, + {"\U00000a03\U00000308\U00001100", {2563, 4352}, {5, 8}}, + {"\U00000a03\U00001160", {2563, 4448}, {3, 6}}, + {"\U00000a03\U00000308\U00001160", {2563, 4448}, {5, 8}}, + {"\U00000a03\U000011a8", {2563, 4520}, {3, 6}}, + {"\U00000a03\U00000308\U000011a8", {2563, 4520}, {5, 8}}, + {"\U00000a03\U0000ac00", {2563, 44032}, {3, 6}}, + {"\U00000a03\U00000308\U0000ac00", {2563, 44032}, {5, 8}}, + {"\U00000a03\U0000ac01", {2563, 44033}, {3, 6}}, + {"\U00000a03\U00000308\U0000ac01", {2563, 44033}, {5, 8}}, + {"\U00000a03\U00000900", {2563}, {6}}, + {"\U00000a03\U00000308\U00000900", {2563}, {8}}, + {"\U00000a03\U00000903", {2563}, {6}}, + {"\U00000a03\U00000308\U00000903", {2563}, {8}}, + {"\U00000a03\U00000904", {2563, 2308}, {3, 6}}, + {"\U00000a03\U00000308\U00000904", {2563, 2308}, {5, 8}}, + {"\U00000a03\U00000d4e", {2563, 3406}, {3, 6}}, + {"\U00000a03\U00000308\U00000d4e", {2563, 3406}, {5, 8}}, + {"\U00000a03\U00000915", {2563, 2325}, {3, 6}}, + {"\U00000a03\U00000308\U00000915", {2563, 2325}, {5, 8}}, + {"\U00000a03\U0000231a", {2563, 8986}, {3, 6}}, + {"\U00000a03\U00000308\U0000231a", {2563, 8986}, {5, 8}}, + {"\U00000a03\U00000300", {2563}, {5}}, + {"\U00000a03\U00000308\U00000300", {2563}, {7}}, + {"\U00000a03\U0000093c", {2563}, {6}}, + {"\U00000a03\U00000308\U0000093c", {2563}, {8}}, + {"\U00000a03\U0000094d", {2563}, {6}}, + {"\U00000a03\U00000308\U0000094d", {2563}, {8}}, + {"\U00000a03\U0000200d", {2563}, {6}}, + {"\U00000a03\U00000308\U0000200d", {2563}, {8}}, + {"\U00000a03\U00000378", {2563, 888}, {3, 5}}, + {"\U00000a03\U00000308\U00000378", {2563, 888}, {5, 7}}, {"\U00001100\U00000020", {4352, 32}, {3, 4}}, {"\U00001100\U00000308\U00000020", {4352, 32}, {5, 6}}, {"\U00001100\U0000000d", {4352, 13}, {3, 4}}, @@ -369,8 +481,8 @@ std::array, 602> data_utf8 = {{ {"\U00001100\U00000308\U0001f1e6", {4352, 127462}, {5, 9}}, {"\U00001100\U00000600", {4352, 1536}, {3, 5}}, {"\U00001100\U00000308\U00000600", {4352, 1536}, {5, 7}}, - {"\U00001100\U00000903", {4352}, {6}}, - {"\U00001100\U00000308\U00000903", {4352}, {8}}, + {"\U00001100\U00000a03", {4352}, {6}}, + {"\U00001100\U00000308\U00000a03", {4352}, {8}}, {"\U00001100\U00001100", {4352}, {6}}, {"\U00001100\U00000308\U00001100", {4352, 4352}, {5, 8}}, {"\U00001100\U00001160", {4352}, {6}}, @@ -381,10 +493,24 @@ std::array, 602> data_utf8 = {{ {"\U00001100\U00000308\U0000ac00", {4352, 44032}, {5, 8}}, {"\U00001100\U0000ac01", {4352}, {6}}, {"\U00001100\U00000308\U0000ac01", {4352, 44033}, {5, 8}}, + {"\U00001100\U00000900", {4352}, {6}}, + {"\U00001100\U00000308\U00000900", {4352}, {8}}, + {"\U00001100\U00000903", {4352}, {6}}, + {"\U00001100\U00000308\U00000903", {4352}, {8}}, + {"\U00001100\U00000904", {4352, 2308}, {3, 6}}, + {"\U00001100\U00000308\U00000904", {4352, 2308}, {5, 8}}, + {"\U00001100\U00000d4e", {4352, 3406}, {3, 6}}, + {"\U00001100\U00000308\U00000d4e", {4352, 3406}, {5, 8}}, + {"\U00001100\U00000915", {4352, 2325}, {3, 6}}, + {"\U00001100\U00000308\U00000915", {4352, 2325}, {5, 8}}, {"\U00001100\U0000231a", {4352, 8986}, {3, 6}}, {"\U00001100\U00000308\U0000231a", {4352, 8986}, {5, 8}}, {"\U00001100\U00000300", {4352}, {5}}, {"\U00001100\U00000308\U00000300", {4352}, {7}}, + {"\U00001100\U0000093c", {4352}, {6}}, + {"\U00001100\U00000308\U0000093c", {4352}, {8}}, + {"\U00001100\U0000094d", {4352}, {6}}, + {"\U00001100\U00000308\U0000094d", {4352}, {8}}, {"\U00001100\U0000200d", {4352}, {6}}, {"\U00001100\U00000308\U0000200d", {4352}, {8}}, {"\U00001100\U00000378", {4352, 888}, {3, 5}}, @@ -403,8 +529,8 @@ std::array, 602> data_utf8 = {{ {"\U00001160\U00000308\U0001f1e6", {4448, 127462}, {5, 9}}, {"\U00001160\U00000600", {4448, 1536}, {3, 5}}, {"\U00001160\U00000308\U00000600", {4448, 1536}, {5, 7}}, - {"\U00001160\U00000903", {4448}, {6}}, - {"\U00001160\U00000308\U00000903", {4448}, {8}}, + {"\U00001160\U00000a03", {4448}, {6}}, + {"\U00001160\U00000308\U00000a03", {4448}, {8}}, {"\U00001160\U00001100", {4448, 4352}, {3, 6}}, {"\U00001160\U00000308\U00001100", {4448, 4352}, {5, 8}}, {"\U00001160\U00001160", {4448}, {6}}, @@ -415,10 +541,24 @@ std::array, 602> data_utf8 = {{ {"\U00001160\U00000308\U0000ac00", {4448, 44032}, {5, 8}}, {"\U00001160\U0000ac01", {4448, 44033}, {3, 6}}, {"\U00001160\U00000308\U0000ac01", {4448, 44033}, {5, 8}}, + {"\U00001160\U00000900", {4448}, {6}}, + {"\U00001160\U00000308\U00000900", {4448}, {8}}, + {"\U00001160\U00000903", {4448}, {6}}, + {"\U00001160\U00000308\U00000903", {4448}, {8}}, + {"\U00001160\U00000904", {4448, 2308}, {3, 6}}, + {"\U00001160\U00000308\U00000904", {4448, 2308}, {5, 8}}, + {"\U00001160\U00000d4e", {4448, 3406}, {3, 6}}, + {"\U00001160\U00000308\U00000d4e", {4448, 3406}, {5, 8}}, + {"\U00001160\U00000915", {4448, 2325}, {3, 6}}, + {"\U00001160\U00000308\U00000915", {4448, 2325}, {5, 8}}, {"\U00001160\U0000231a", {4448, 8986}, {3, 6}}, {"\U00001160\U00000308\U0000231a", {4448, 8986}, {5, 8}}, {"\U00001160\U00000300", {4448}, {5}}, {"\U00001160\U00000308\U00000300", {4448}, {7}}, + {"\U00001160\U0000093c", {4448}, {6}}, + {"\U00001160\U00000308\U0000093c", {4448}, {8}}, + {"\U00001160\U0000094d", {4448}, {6}}, + {"\U00001160\U00000308\U0000094d", {4448}, {8}}, {"\U00001160\U0000200d", {4448}, {6}}, {"\U00001160\U00000308\U0000200d", {4448}, {8}}, {"\U00001160\U00000378", {4448, 888}, {3, 5}}, @@ -437,8 +577,8 @@ std::array, 602> data_utf8 = {{ {"\U000011a8\U00000308\U0001f1e6", {4520, 127462}, {5, 9}}, {"\U000011a8\U00000600", {4520, 1536}, {3, 5}}, {"\U000011a8\U00000308\U00000600", {4520, 1536}, {5, 7}}, - {"\U000011a8\U00000903", {4520}, {6}}, - {"\U000011a8\U00000308\U00000903", {4520}, {8}}, + {"\U000011a8\U00000a03", {4520}, {6}}, + {"\U000011a8\U00000308\U00000a03", {4520}, {8}}, {"\U000011a8\U00001100", {4520, 4352}, {3, 6}}, {"\U000011a8\U00000308\U00001100", {4520, 4352}, {5, 8}}, {"\U000011a8\U00001160", {4520, 4448}, {3, 6}}, @@ -449,10 +589,24 @@ std::array, 602> data_utf8 = {{ {"\U000011a8\U00000308\U0000ac00", {4520, 44032}, {5, 8}}, {"\U000011a8\U0000ac01", {4520, 44033}, {3, 6}}, {"\U000011a8\U00000308\U0000ac01", {4520, 44033}, {5, 8}}, + {"\U000011a8\U00000900", {4520}, {6}}, + {"\U000011a8\U00000308\U00000900", {4520}, {8}}, + {"\U000011a8\U00000903", {4520}, {6}}, + {"\U000011a8\U00000308\U00000903", {4520}, {8}}, + {"\U000011a8\U00000904", {4520, 2308}, {3, 6}}, + {"\U000011a8\U00000308\U00000904", {4520, 2308}, {5, 8}}, + {"\U000011a8\U00000d4e", {4520, 3406}, {3, 6}}, + {"\U000011a8\U00000308\U00000d4e", {4520, 3406}, {5, 8}}, + {"\U000011a8\U00000915", {4520, 2325}, {3, 6}}, + {"\U000011a8\U00000308\U00000915", {4520, 2325}, {5, 8}}, {"\U000011a8\U0000231a", {4520, 8986}, {3, 6}}, {"\U000011a8\U00000308\U0000231a", {4520, 8986}, {5, 8}}, {"\U000011a8\U00000300", {4520}, {5}}, {"\U000011a8\U00000308\U00000300", {4520}, {7}}, + {"\U000011a8\U0000093c", {4520}, {6}}, + {"\U000011a8\U00000308\U0000093c", {4520}, {8}}, + {"\U000011a8\U0000094d", {4520}, {6}}, + {"\U000011a8\U00000308\U0000094d", {4520}, {8}}, {"\U000011a8\U0000200d", {4520}, {6}}, {"\U000011a8\U00000308\U0000200d", {4520}, {8}}, {"\U000011a8\U00000378", {4520, 888}, {3, 5}}, @@ -471,8 +625,8 @@ std::array, 602> data_utf8 = {{ {"\U0000ac00\U00000308\U0001f1e6", {44032, 127462}, {5, 9}}, {"\U0000ac00\U00000600", {44032, 1536}, {3, 5}}, {"\U0000ac00\U00000308\U00000600", {44032, 1536}, {5, 7}}, - {"\U0000ac00\U00000903", {44032}, {6}}, - {"\U0000ac00\U00000308\U00000903", {44032}, {8}}, + {"\U0000ac00\U00000a03", {44032}, {6}}, + {"\U0000ac00\U00000308\U00000a03", {44032}, {8}}, {"\U0000ac00\U00001100", {44032, 4352}, {3, 6}}, {"\U0000ac00\U00000308\U00001100", {44032, 4352}, {5, 8}}, {"\U0000ac00\U00001160", {44032}, {6}}, @@ -483,10 +637,24 @@ std::array, 602> data_utf8 = {{ {"\U0000ac00\U00000308\U0000ac00", {44032, 44032}, {5, 8}}, {"\U0000ac00\U0000ac01", {44032, 44033}, {3, 6}}, {"\U0000ac00\U00000308\U0000ac01", {44032, 44033}, {5, 8}}, + {"\U0000ac00\U00000900", {44032}, {6}}, + {"\U0000ac00\U00000308\U00000900", {44032}, {8}}, + {"\U0000ac00\U00000903", {44032}, {6}}, + {"\U0000ac00\U00000308\U00000903", {44032}, {8}}, + {"\U0000ac00\U00000904", {44032, 2308}, {3, 6}}, + {"\U0000ac00\U00000308\U00000904", {44032, 2308}, {5, 8}}, + {"\U0000ac00\U00000d4e", {44032, 3406}, {3, 6}}, + {"\U0000ac00\U00000308\U00000d4e", {44032, 3406}, {5, 8}}, + {"\U0000ac00\U00000915", {44032, 2325}, {3, 6}}, + {"\U0000ac00\U00000308\U00000915", {44032, 2325}, {5, 8}}, {"\U0000ac00\U0000231a", {44032, 8986}, {3, 6}}, {"\U0000ac00\U00000308\U0000231a", {44032, 8986}, {5, 8}}, {"\U0000ac00\U00000300", {44032}, {5}}, {"\U0000ac00\U00000308\U00000300", {44032}, {7}}, + {"\U0000ac00\U0000093c", {44032}, {6}}, + {"\U0000ac00\U00000308\U0000093c", {44032}, {8}}, + {"\U0000ac00\U0000094d", {44032}, {6}}, + {"\U0000ac00\U00000308\U0000094d", {44032}, {8}}, {"\U0000ac00\U0000200d", {44032}, {6}}, {"\U0000ac00\U00000308\U0000200d", {44032}, {8}}, {"\U0000ac00\U00000378", {44032, 888}, {3, 5}}, @@ -505,8 +673,8 @@ std::array, 602> data_utf8 = {{ {"\U0000ac01\U00000308\U0001f1e6", {44033, 127462}, {5, 9}}, {"\U0000ac01\U00000600", {44033, 1536}, {3, 5}}, {"\U0000ac01\U00000308\U00000600", {44033, 1536}, {5, 7}}, - {"\U0000ac01\U00000903", {44033}, {6}}, - {"\U0000ac01\U00000308\U00000903", {44033}, {8}}, + {"\U0000ac01\U00000a03", {44033}, {6}}, + {"\U0000ac01\U00000308\U00000a03", {44033}, {8}}, {"\U0000ac01\U00001100", {44033, 4352}, {3, 6}}, {"\U0000ac01\U00000308\U00001100", {44033, 4352}, {5, 8}}, {"\U0000ac01\U00001160", {44033, 4448}, {3, 6}}, @@ -517,14 +685,268 @@ std::array, 602> data_utf8 = {{ {"\U0000ac01\U00000308\U0000ac00", {44033, 44032}, {5, 8}}, {"\U0000ac01\U0000ac01", {44033, 44033}, {3, 6}}, {"\U0000ac01\U00000308\U0000ac01", {44033, 44033}, {5, 8}}, + {"\U0000ac01\U00000900", {44033}, {6}}, + {"\U0000ac01\U00000308\U00000900", {44033}, {8}}, + {"\U0000ac01\U00000903", {44033}, {6}}, + {"\U0000ac01\U00000308\U00000903", {44033}, {8}}, + {"\U0000ac01\U00000904", {44033, 2308}, {3, 6}}, + {"\U0000ac01\U00000308\U00000904", {44033, 2308}, {5, 8}}, + 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{"\U0000231a\U0000ac01", {8986, 44033}, {3, 6}}, {"\U0000231a\U00000308\U0000ac01", {8986, 44033}, {5, 8}}, + {"\U0000231a\U00000900", {8986}, {6}}, + {"\U0000231a\U00000308\U00000900", {8986}, {8}}, + {"\U0000231a\U00000903", {8986}, {6}}, + {"\U0000231a\U00000308\U00000903", {8986}, {8}}, + {"\U0000231a\U00000904", {8986, 2308}, {3, 6}}, + {"\U0000231a\U00000308\U00000904", {8986, 2308}, {5, 8}}, + {"\U0000231a\U00000d4e", {8986, 3406}, {3, 6}}, + {"\U0000231a\U00000308\U00000d4e", {8986, 3406}, {5, 8}}, + {"\U0000231a\U00000915", {8986, 2325}, {3, 6}}, + {"\U0000231a\U00000308\U00000915", {8986, 2325}, {5, 8}}, {"\U0000231a\U0000231a", {8986, 8986}, {3, 6}}, {"\U0000231a\U00000308\U0000231a", {8986, 8986}, {5, 8}}, {"\U0000231a\U00000300", {8986}, {5}}, {"\U0000231a\U00000308\U00000300", {8986}, {7}}, + {"\U0000231a\U0000093c", {8986}, {6}}, + {"\U0000231a\U00000308\U0000093c", {8986}, {8}}, + {"\U0000231a\U0000094d", {8986}, {6}}, + {"\U0000231a\U00000308\U0000094d", {8986}, {8}}, {"\U0000231a\U0000200d", {8986}, {6}}, {"\U0000231a\U00000308\U0000200d", {8986}, {8}}, {"\U0000231a\U00000378", {8986, 888}, {3, 5}}, @@ -573,8 +1009,8 @@ std::array, 602> data_utf8 = {{ {"\U00000300\U00000308\U0001f1e6", {768, 127462}, {4, 8}}, {"\U00000300\U00000600", {768, 1536}, {2, 4}}, {"\U00000300\U00000308\U00000600", {768, 1536}, {4, 6}}, - {"\U00000300\U00000903", {768}, {5}}, - {"\U00000300\U00000308\U00000903", {768}, {7}}, + {"\U00000300\U00000a03", {768}, {5}}, + {"\U00000300\U00000308\U00000a03", {768}, {7}}, {"\U00000300\U00001100", {768, 4352}, {2, 5}}, {"\U00000300\U00000308\U00001100", {768, 4352}, {4, 7}}, {"\U00000300\U00001160", {768, 4448}, {2, 5}}, @@ -585,14 +1021,124 @@ std::array, 602> data_utf8 = {{ {"\U00000300\U00000308\U0000ac00", {768, 44032}, {4, 7}}, {"\U00000300\U0000ac01", {768, 44033}, {2, 5}}, {"\U00000300\U00000308\U0000ac01", {768, 44033}, {4, 7}}, + {"\U00000300\U00000900", {768}, {5}}, + {"\U00000300\U00000308\U00000900", {768}, {7}}, + {"\U00000300\U00000903", {768}, {5}}, + {"\U00000300\U00000308\U00000903", {768}, {7}}, + {"\U00000300\U00000904", {768, 2308}, {2, 5}}, + {"\U00000300\U00000308\U00000904", {768, 2308}, {4, 7}}, + {"\U00000300\U00000d4e", {768, 3406}, {2, 5}}, + {"\U00000300\U00000308\U00000d4e", {768, 3406}, {4, 7}}, + {"\U00000300\U00000915", {768, 2325}, {2, 5}}, + {"\U00000300\U00000308\U00000915", {768, 2325}, {4, 7}}, {"\U00000300\U0000231a", {768, 8986}, {2, 5}}, {"\U00000300\U00000308\U0000231a", {768, 8986}, {4, 7}}, {"\U00000300\U00000300", {768}, {4}}, {"\U00000300\U00000308\U00000300", {768}, {6}}, + {"\U00000300\U0000093c", {768}, {5}}, + {"\U00000300\U00000308\U0000093c", {768}, {7}}, + {"\U00000300\U0000094d", {768}, {5}}, + {"\U00000300\U00000308\U0000094d", {768}, {7}}, {"\U00000300\U0000200d", {768}, {5}}, {"\U00000300\U00000308\U0000200d", {768}, {7}}, {"\U00000300\U00000378", {768, 888}, {2, 4}}, {"\U00000300\U00000308\U00000378", {768, 888}, {4, 6}}, + {"\U0000093c\U00000020", {2364, 32}, {3, 4}}, + {"\U0000093c\U00000308\U00000020", {2364, 32}, {5, 6}}, + {"\U0000093c\U0000000d", {2364, 13}, {3, 4}}, + {"\U0000093c\U00000308\U0000000d", {2364, 13}, {5, 6}}, + {"\U0000093c\U0000000a", {2364, 10}, {3, 4}}, + {"\U0000093c\U00000308\U0000000a", {2364, 10}, {5, 6}}, + {"\U0000093c\U00000001", {2364, 1}, {3, 4}}, + {"\U0000093c\U00000308\U00000001", {2364, 1}, {5, 6}}, + {"\U0000093c\U0000034f", {2364}, {5}}, + {"\U0000093c\U00000308\U0000034f", {2364}, {7}}, + {"\U0000093c\U0001f1e6", {2364, 127462}, {3, 7}}, + {"\U0000093c\U00000308\U0001f1e6", {2364, 127462}, {5, 9}}, + {"\U0000093c\U00000600", {2364, 1536}, {3, 5}}, + {"\U0000093c\U00000308\U00000600", {2364, 1536}, {5, 7}}, + {"\U0000093c\U00000a03", {2364}, {6}}, + {"\U0000093c\U00000308\U00000a03", {2364}, {8}}, + {"\U0000093c\U00001100", {2364, 4352}, {3, 6}}, + {"\U0000093c\U00000308\U00001100", {2364, 4352}, {5, 8}}, + {"\U0000093c\U00001160", {2364, 4448}, {3, 6}}, + {"\U0000093c\U00000308\U00001160", {2364, 4448}, {5, 8}}, + {"\U0000093c\U000011a8", {2364, 4520}, {3, 6}}, + {"\U0000093c\U00000308\U000011a8", {2364, 4520}, {5, 8}}, + {"\U0000093c\U0000ac00", {2364, 44032}, {3, 6}}, + {"\U0000093c\U00000308\U0000ac00", {2364, 44032}, {5, 8}}, + {"\U0000093c\U0000ac01", {2364, 44033}, {3, 6}}, + {"\U0000093c\U00000308\U0000ac01", {2364, 44033}, {5, 8}}, + {"\U0000093c\U00000900", {2364}, {6}}, + {"\U0000093c\U00000308\U00000900", {2364}, {8}}, + {"\U0000093c\U00000903", {2364}, {6}}, + {"\U0000093c\U00000308\U00000903", {2364}, {8}}, + {"\U0000093c\U00000904", {2364, 2308}, {3, 6}}, + {"\U0000093c\U00000308\U00000904", {2364, 2308}, {5, 8}}, + {"\U0000093c\U00000d4e", {2364, 3406}, {3, 6}}, + {"\U0000093c\U00000308\U00000d4e", {2364, 3406}, {5, 8}}, + {"\U0000093c\U00000915", {2364, 2325}, {3, 6}}, + {"\U0000093c\U00000308\U00000915", {2364, 2325}, {5, 8}}, + {"\U0000093c\U0000231a", {2364, 8986}, {3, 6}}, + {"\U0000093c\U00000308\U0000231a", {2364, 8986}, {5, 8}}, + {"\U0000093c\U00000300", {2364}, {5}}, + {"\U0000093c\U00000308\U00000300", {2364}, {7}}, + {"\U0000093c\U0000093c", {2364}, {6}}, + {"\U0000093c\U00000308\U0000093c", {2364}, {8}}, + {"\U0000093c\U0000094d", {2364}, {6}}, + {"\U0000093c\U00000308\U0000094d", {2364}, {8}}, + {"\U0000093c\U0000200d", {2364}, {6}}, + {"\U0000093c\U00000308\U0000200d", {2364}, {8}}, + {"\U0000093c\U00000378", {2364, 888}, {3, 5}}, + {"\U0000093c\U00000308\U00000378", {2364, 888}, {5, 7}}, + {"\U0000094d\U00000020", {2381, 32}, {3, 4}}, + {"\U0000094d\U00000308\U00000020", {2381, 32}, {5, 6}}, + {"\U0000094d\U0000000d", {2381, 13}, {3, 4}}, + {"\U0000094d\U00000308\U0000000d", {2381, 13}, {5, 6}}, + {"\U0000094d\U0000000a", {2381, 10}, {3, 4}}, + {"\U0000094d\U00000308\U0000000a", {2381, 10}, {5, 6}}, + {"\U0000094d\U00000001", {2381, 1}, {3, 4}}, + {"\U0000094d\U00000308\U00000001", {2381, 1}, {5, 6}}, + {"\U0000094d\U0000034f", {2381}, {5}}, + {"\U0000094d\U00000308\U0000034f", {2381}, {7}}, + {"\U0000094d\U0001f1e6", {2381, 127462}, {3, 7}}, + {"\U0000094d\U00000308\U0001f1e6", {2381, 127462}, {5, 9}}, + {"\U0000094d\U00000600", {2381, 1536}, {3, 5}}, + {"\U0000094d\U00000308\U00000600", {2381, 1536}, {5, 7}}, + {"\U0000094d\U00000a03", {2381}, {6}}, + {"\U0000094d\U00000308\U00000a03", {2381}, {8}}, + {"\U0000094d\U00001100", {2381, 4352}, {3, 6}}, + {"\U0000094d\U00000308\U00001100", {2381, 4352}, {5, 8}}, + {"\U0000094d\U00001160", {2381, 4448}, {3, 6}}, + {"\U0000094d\U00000308\U00001160", {2381, 4448}, {5, 8}}, + {"\U0000094d\U000011a8", {2381, 4520}, {3, 6}}, + {"\U0000094d\U00000308\U000011a8", {2381, 4520}, {5, 8}}, + {"\U0000094d\U0000ac00", {2381, 44032}, {3, 6}}, + {"\U0000094d\U00000308\U0000ac00", {2381, 44032}, {5, 8}}, + {"\U0000094d\U0000ac01", {2381, 44033}, {3, 6}}, + {"\U0000094d\U00000308\U0000ac01", {2381, 44033}, {5, 8}}, + {"\U0000094d\U00000900", {2381}, {6}}, + {"\U0000094d\U00000308\U00000900", {2381}, {8}}, + {"\U0000094d\U00000903", {2381}, {6}}, + {"\U0000094d\U00000308\U00000903", {2381}, {8}}, + {"\U0000094d\U00000904", {2381, 2308}, {3, 6}}, + {"\U0000094d\U00000308\U00000904", {2381, 2308}, {5, 8}}, + {"\U0000094d\U00000d4e", {2381, 3406}, {3, 6}}, + {"\U0000094d\U00000308\U00000d4e", {2381, 3406}, {5, 8}}, + {"\U0000094d\U00000915", {2381, 2325}, {3, 6}}, + {"\U0000094d\U00000308\U00000915", {2381, 2325}, {5, 8}}, + {"\U0000094d\U0000231a", {2381, 8986}, {3, 6}}, + {"\U0000094d\U00000308\U0000231a", {2381, 8986}, {5, 8}}, + {"\U0000094d\U00000300", {2381}, {5}}, + {"\U0000094d\U00000308\U00000300", {2381}, {7}}, + {"\U0000094d\U0000093c", {2381}, {6}}, + {"\U0000094d\U00000308\U0000093c", {2381}, {8}}, + {"\U0000094d\U0000094d", {2381}, {6}}, + {"\U0000094d\U00000308\U0000094d", {2381}, {8}}, + {"\U0000094d\U0000200d", {2381}, {6}}, + {"\U0000094d\U00000308\U0000200d", {2381}, {8}}, + {"\U0000094d\U00000378", {2381, 888}, {3, 5}}, + {"\U0000094d\U00000308\U00000378", {2381, 888}, {5, 7}}, {"\U0000200d\U00000020", {8205, 32}, {3, 4}}, {"\U0000200d\U00000308\U00000020", {8205, 32}, {5, 6}}, {"\U0000200d\U0000000d", {8205, 13}, {3, 4}}, @@ -607,8 +1153,8 @@ std::array, 602> data_utf8 = {{ {"\U0000200d\U00000308\U0001f1e6", {8205, 127462}, {5, 9}}, {"\U0000200d\U00000600", {8205, 1536}, {3, 5}}, {"\U0000200d\U00000308\U00000600", {8205, 1536}, {5, 7}}, - {"\U0000200d\U00000903", {8205}, {6}}, - {"\U0000200d\U00000308\U00000903", {8205}, {8}}, + {"\U0000200d\U00000a03", {8205}, {6}}, + {"\U0000200d\U00000308\U00000a03", {8205}, {8}}, {"\U0000200d\U00001100", {8205, 4352}, {3, 6}}, {"\U0000200d\U00000308\U00001100", {8205, 4352}, {5, 8}}, {"\U0000200d\U00001160", {8205, 4448}, {3, 6}}, @@ -619,10 +1165,24 @@ std::array, 602> data_utf8 = {{ {"\U0000200d\U00000308\U0000ac00", {8205, 44032}, {5, 8}}, {"\U0000200d\U0000ac01", {8205, 44033}, {3, 6}}, {"\U0000200d\U00000308\U0000ac01", {8205, 44033}, {5, 8}}, + {"\U0000200d\U00000900", {8205}, {6}}, + {"\U0000200d\U00000308\U00000900", {8205}, {8}}, + {"\U0000200d\U00000903", {8205}, {6}}, + {"\U0000200d\U00000308\U00000903", {8205}, {8}}, + {"\U0000200d\U00000904", {8205, 2308}, {3, 6}}, + {"\U0000200d\U00000308\U00000904", {8205, 2308}, {5, 8}}, + {"\U0000200d\U00000d4e", {8205, 3406}, {3, 6}}, + {"\U0000200d\U00000308\U00000d4e", {8205, 3406}, {5, 8}}, + {"\U0000200d\U00000915", {8205, 2325}, {3, 6}}, + {"\U0000200d\U00000308\U00000915", {8205, 2325}, {5, 8}}, {"\U0000200d\U0000231a", {8205, 8986}, {3, 6}}, {"\U0000200d\U00000308\U0000231a", {8205, 8986}, {5, 8}}, {"\U0000200d\U00000300", {8205}, {5}}, {"\U0000200d\U00000308\U00000300", {8205}, {7}}, + {"\U0000200d\U0000093c", {8205}, {6}}, + {"\U0000200d\U00000308\U0000093c", {8205}, {8}}, + {"\U0000200d\U0000094d", {8205}, {6}}, + {"\U0000200d\U00000308\U0000094d", {8205}, {8}}, {"\U0000200d\U0000200d", {8205}, {6}}, {"\U0000200d\U00000308\U0000200d", {8205}, {8}}, {"\U0000200d\U00000378", {8205, 888}, {3, 5}}, @@ -641,8 +1201,8 @@ std::array, 602> data_utf8 = {{ {"\U00000378\U00000308\U0001f1e6", {888, 127462}, {4, 8}}, {"\U00000378\U00000600", {888, 1536}, {2, 4}}, {"\U00000378\U00000308\U00000600", {888, 1536}, {4, 6}}, - {"\U00000378\U00000903", {888}, {5}}, - {"\U00000378\U00000308\U00000903", {888}, {7}}, + {"\U00000378\U00000a03", {888}, {5}}, + {"\U00000378\U00000308\U00000a03", {888}, {7}}, {"\U00000378\U00001100", {888, 4352}, {2, 5}}, {"\U00000378\U00000308\U00001100", {888, 4352}, {4, 7}}, {"\U00000378\U00001160", {888, 4448}, {2, 5}}, @@ -653,10 +1213,24 @@ std::array, 602> data_utf8 = {{ {"\U00000378\U00000308\U0000ac00", {888, 44032}, {4, 7}}, {"\U00000378\U0000ac01", {888, 44033}, {2, 5}}, {"\U00000378\U00000308\U0000ac01", {888, 44033}, {4, 7}}, + {"\U00000378\U00000900", {888}, {5}}, + {"\U00000378\U00000308\U00000900", {888}, {7}}, + {"\U00000378\U00000903", {888}, {5}}, + {"\U00000378\U00000308\U00000903", {888}, {7}}, + {"\U00000378\U00000904", {888, 2308}, {2, 5}}, + {"\U00000378\U00000308\U00000904", {888, 2308}, {4, 7}}, + {"\U00000378\U00000d4e", {888, 3406}, {2, 5}}, + {"\U00000378\U00000308\U00000d4e", {888, 3406}, {4, 7}}, + {"\U00000378\U00000915", {888, 2325}, {2, 5}}, + {"\U00000378\U00000308\U00000915", {888, 2325}, {4, 7}}, {"\U00000378\U0000231a", {888, 8986}, {2, 5}}, {"\U00000378\U00000308\U0000231a", {888, 8986}, {4, 7}}, {"\U00000378\U00000300", {888}, {4}}, {"\U00000378\U00000308\U00000300", {888}, {6}}, + {"\U00000378\U0000093c", {888}, {5}}, + {"\U00000378\U00000308\U0000093c", {888}, {7}}, + {"\U00000378\U0000094d", {888}, {5}}, + {"\U00000378\U00000308\U0000094d", {888}, {7}}, {"\U00000378\U0000200d", {888}, {5}}, {"\U00000378\U00000308\U0000200d", {888}, {7}}, {"\U00000378\U00000378", {888, 888}, {2, 4}}, @@ -684,7 +1258,18 @@ std::array, 602> data_utf8 = {{ {"\U0001f6d1\U0000200d\U0001f6d1", {128721}, {11}}, {"\U00000061\U0000200d\U0001f6d1", {97, 128721}, {4, 8}}, {"\U00002701\U0000200d\U00002701", {9985}, {9}}, - {"\U00000061\U0000200d\U00002701", {97, 9985}, {4, 7}}}}; + {"\U00000061\U0000200d\U00002701", {97, 9985}, {4, 7}}, + {"\U00000915\U00000924", {2325, 2340}, {3, 6}}, + {"\U00000915\U0000094d\U00000924", {2325}, {9}}, + {"\U00000915\U0000094d\U0000094d\U00000924", {2325}, {12}}, + {"\U00000915\U0000094d\U0000200d\U00000924", {2325}, {12}}, + {"\U00000915\U0000093c\U0000200d\U0000094d\U00000924", {2325}, {15}}, + {"\U00000915\U0000093c\U0000094d\U0000200d\U00000924", {2325}, {15}}, + {"\U00000915\U0000094d\U00000924\U0000094d\U0000092f", {2325}, {15}}, + {"\U00000915\U0000094d\U00000061", {2325, 97}, {6, 7}}, + {"\U00000061\U0000094d\U00000924", {97, 2340}, {4, 7}}, + {"\U0000003f\U0000094d\U00000924", {63, 2340}, {4, 7}}, + {"\U00000915\U0000094d\U0000094d\U00000924", {2325}, {12}}}}; /// The data for UTF-16. /// @@ -692,7 +1277,7 @@ std::array, 602> data_utf8 = {{ /// since the size of the code units differ the breaks can contain different /// values. #ifndef TEST_HAS_NO_WIDE_CHARACTERS -std::array, 602> data_utf16 = {{ +std::array, 1187> data_utf16 = {{ {L"\U00000020\U00000020", {32, 32}, {1, 2}}, {L"\U00000020\U00000308\U00000020", {32, 32}, {2, 3}}, {L"\U00000020\U0000000d", {32, 13}, {1, 2}}, @@ -707,8 +1292,8 @@ std::array, 602> data_utf16 = {{ {L"\U00000020\U00000308\U0001f1e6", {32, 127462}, {2, 4}}, {L"\U00000020\U00000600", {32, 1536}, {1, 2}}, {L"\U00000020\U00000308\U00000600", {32, 1536}, {2, 3}}, - {L"\U00000020\U00000903", {32}, {2}}, - {L"\U00000020\U00000308\U00000903", {32}, {3}}, + {L"\U00000020\U00000a03", {32}, {2}}, + {L"\U00000020\U00000308\U00000a03", {32}, {3}}, {L"\U00000020\U00001100", {32, 4352}, {1, 2}}, {L"\U00000020\U00000308\U00001100", {32, 4352}, {2, 3}}, {L"\U00000020\U00001160", {32, 4448}, {1, 2}}, @@ -719,10 +1304,24 @@ std::array, 602> data_utf16 = {{ {L"\U00000020\U00000308\U0000ac00", {32, 44032}, {2, 3}}, {L"\U00000020\U0000ac01", {32, 44033}, {1, 2}}, {L"\U00000020\U00000308\U0000ac01", {32, 44033}, {2, 3}}, + {L"\U00000020\U00000900", {32}, {2}}, + {L"\U00000020\U00000308\U00000900", {32}, {3}}, + {L"\U00000020\U00000903", {32}, {2}}, + {L"\U00000020\U00000308\U00000903", {32}, {3}}, + {L"\U00000020\U00000904", {32, 2308}, {1, 2}}, + {L"\U00000020\U00000308\U00000904", {32, 2308}, {2, 3}}, + {L"\U00000020\U00000d4e", {32, 3406}, {1, 2}}, + {L"\U00000020\U00000308\U00000d4e", {32, 3406}, {2, 3}}, + {L"\U00000020\U00000915", {32, 2325}, {1, 2}}, + {L"\U00000020\U00000308\U00000915", {32, 2325}, {2, 3}}, {L"\U00000020\U0000231a", {32, 8986}, {1, 2}}, {L"\U00000020\U00000308\U0000231a", {32, 8986}, {2, 3}}, {L"\U00000020\U00000300", {32}, {2}}, {L"\U00000020\U00000308\U00000300", {32}, {3}}, + {L"\U00000020\U0000093c", {32}, {2}}, + {L"\U00000020\U00000308\U0000093c", {32}, {3}}, + {L"\U00000020\U0000094d", {32}, {2}}, + {L"\U00000020\U00000308\U0000094d", {32}, {3}}, {L"\U00000020\U0000200d", {32}, {2}}, {L"\U00000020\U00000308\U0000200d", {32}, {3}}, {L"\U00000020\U00000378", {32, 888}, {1, 2}}, @@ -741,8 +1340,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000000d\U00000308\U0001f1e6", {13, 776, 127462}, {1, 2, 4}}, {L"\U0000000d\U00000600", {13, 1536}, {1, 2}}, {L"\U0000000d\U00000308\U00000600", {13, 776, 1536}, {1, 2, 3}}, - {L"\U0000000d\U00000903", {13, 2307}, {1, 2}}, - {L"\U0000000d\U00000308\U00000903", {13, 776}, {1, 3}}, + {L"\U0000000d\U00000a03", {13, 2563}, {1, 2}}, + {L"\U0000000d\U00000308\U00000a03", {13, 776}, {1, 3}}, {L"\U0000000d\U00001100", {13, 4352}, {1, 2}}, {L"\U0000000d\U00000308\U00001100", {13, 776, 4352}, {1, 2, 3}}, {L"\U0000000d\U00001160", {13, 4448}, {1, 2}}, @@ -753,10 +1352,24 @@ std::array, 602> data_utf16 = {{ {L"\U0000000d\U00000308\U0000ac00", {13, 776, 44032}, {1, 2, 3}}, {L"\U0000000d\U0000ac01", {13, 44033}, {1, 2}}, {L"\U0000000d\U00000308\U0000ac01", {13, 776, 44033}, {1, 2, 3}}, + {L"\U0000000d\U00000900", {13, 2304}, {1, 2}}, + {L"\U0000000d\U00000308\U00000900", {13, 776}, {1, 3}}, + {L"\U0000000d\U00000903", {13, 2307}, {1, 2}}, + {L"\U0000000d\U00000308\U00000903", {13, 776}, {1, 3}}, + {L"\U0000000d\U00000904", {13, 2308}, {1, 2}}, + {L"\U0000000d\U00000308\U00000904", {13, 776, 2308}, {1, 2, 3}}, + {L"\U0000000d\U00000d4e", {13, 3406}, {1, 2}}, + {L"\U0000000d\U00000308\U00000d4e", {13, 776, 3406}, {1, 2, 3}}, + {L"\U0000000d\U00000915", {13, 2325}, {1, 2}}, + {L"\U0000000d\U00000308\U00000915", {13, 776, 2325}, {1, 2, 3}}, {L"\U0000000d\U0000231a", {13, 8986}, {1, 2}}, {L"\U0000000d\U00000308\U0000231a", {13, 776, 8986}, {1, 2, 3}}, {L"\U0000000d\U00000300", {13, 768}, {1, 2}}, {L"\U0000000d\U00000308\U00000300", {13, 776}, {1, 3}}, + {L"\U0000000d\U0000093c", {13, 2364}, {1, 2}}, + {L"\U0000000d\U00000308\U0000093c", {13, 776}, {1, 3}}, + {L"\U0000000d\U0000094d", {13, 2381}, {1, 2}}, + {L"\U0000000d\U00000308\U0000094d", {13, 776}, {1, 3}}, {L"\U0000000d\U0000200d", {13, 8205}, {1, 2}}, {L"\U0000000d\U00000308\U0000200d", {13, 776}, {1, 3}}, {L"\U0000000d\U00000378", {13, 888}, {1, 2}}, @@ -775,8 +1388,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000000a\U00000308\U0001f1e6", {10, 776, 127462}, {1, 2, 4}}, {L"\U0000000a\U00000600", {10, 1536}, {1, 2}}, {L"\U0000000a\U00000308\U00000600", {10, 776, 1536}, {1, 2, 3}}, - {L"\U0000000a\U00000903", {10, 2307}, {1, 2}}, - {L"\U0000000a\U00000308\U00000903", {10, 776}, {1, 3}}, + {L"\U0000000a\U00000a03", {10, 2563}, {1, 2}}, + {L"\U0000000a\U00000308\U00000a03", {10, 776}, {1, 3}}, {L"\U0000000a\U00001100", {10, 4352}, {1, 2}}, {L"\U0000000a\U00000308\U00001100", {10, 776, 4352}, {1, 2, 3}}, {L"\U0000000a\U00001160", {10, 4448}, {1, 2}}, @@ -787,10 +1400,24 @@ std::array, 602> data_utf16 = {{ {L"\U0000000a\U00000308\U0000ac00", {10, 776, 44032}, {1, 2, 3}}, {L"\U0000000a\U0000ac01", {10, 44033}, {1, 2}}, {L"\U0000000a\U00000308\U0000ac01", {10, 776, 44033}, {1, 2, 3}}, + {L"\U0000000a\U00000900", {10, 2304}, {1, 2}}, + {L"\U0000000a\U00000308\U00000900", {10, 776}, {1, 3}}, + {L"\U0000000a\U00000903", {10, 2307}, {1, 2}}, + {L"\U0000000a\U00000308\U00000903", {10, 776}, {1, 3}}, + {L"\U0000000a\U00000904", {10, 2308}, {1, 2}}, + {L"\U0000000a\U00000308\U00000904", {10, 776, 2308}, {1, 2, 3}}, + {L"\U0000000a\U00000d4e", {10, 3406}, {1, 2}}, + {L"\U0000000a\U00000308\U00000d4e", {10, 776, 3406}, {1, 2, 3}}, + {L"\U0000000a\U00000915", {10, 2325}, {1, 2}}, + {L"\U0000000a\U00000308\U00000915", {10, 776, 2325}, {1, 2, 3}}, {L"\U0000000a\U0000231a", {10, 8986}, {1, 2}}, {L"\U0000000a\U00000308\U0000231a", {10, 776, 8986}, {1, 2, 3}}, {L"\U0000000a\U00000300", {10, 768}, {1, 2}}, {L"\U0000000a\U00000308\U00000300", {10, 776}, {1, 3}}, + {L"\U0000000a\U0000093c", {10, 2364}, {1, 2}}, + {L"\U0000000a\U00000308\U0000093c", {10, 776}, {1, 3}}, + {L"\U0000000a\U0000094d", {10, 2381}, {1, 2}}, + {L"\U0000000a\U00000308\U0000094d", {10, 776}, {1, 3}}, {L"\U0000000a\U0000200d", {10, 8205}, {1, 2}}, {L"\U0000000a\U00000308\U0000200d", {10, 776}, {1, 3}}, {L"\U0000000a\U00000378", {10, 888}, {1, 2}}, @@ -809,8 +1436,8 @@ std::array, 602> data_utf16 = {{ {L"\U00000001\U00000308\U0001f1e6", {1, 776, 127462}, {1, 2, 4}}, {L"\U00000001\U00000600", {1, 1536}, {1, 2}}, {L"\U00000001\U00000308\U00000600", {1, 776, 1536}, {1, 2, 3}}, - {L"\U00000001\U00000903", {1, 2307}, {1, 2}}, - {L"\U00000001\U00000308\U00000903", {1, 776}, {1, 3}}, + {L"\U00000001\U00000a03", {1, 2563}, {1, 2}}, + {L"\U00000001\U00000308\U00000a03", {1, 776}, {1, 3}}, {L"\U00000001\U00001100", {1, 4352}, {1, 2}}, {L"\U00000001\U00000308\U00001100", {1, 776, 4352}, {1, 2, 3}}, {L"\U00000001\U00001160", {1, 4448}, {1, 2}}, @@ -821,10 +1448,24 @@ std::array, 602> data_utf16 = {{ {L"\U00000001\U00000308\U0000ac00", {1, 776, 44032}, {1, 2, 3}}, {L"\U00000001\U0000ac01", {1, 44033}, {1, 2}}, {L"\U00000001\U00000308\U0000ac01", {1, 776, 44033}, {1, 2, 3}}, + {L"\U00000001\U00000900", {1, 2304}, {1, 2}}, + {L"\U00000001\U00000308\U00000900", {1, 776}, {1, 3}}, + {L"\U00000001\U00000903", {1, 2307}, {1, 2}}, + {L"\U00000001\U00000308\U00000903", {1, 776}, {1, 3}}, + {L"\U00000001\U00000904", {1, 2308}, {1, 2}}, + {L"\U00000001\U00000308\U00000904", {1, 776, 2308}, {1, 2, 3}}, + {L"\U00000001\U00000d4e", {1, 3406}, {1, 2}}, + {L"\U00000001\U00000308\U00000d4e", {1, 776, 3406}, {1, 2, 3}}, + {L"\U00000001\U00000915", {1, 2325}, {1, 2}}, + {L"\U00000001\U00000308\U00000915", {1, 776, 2325}, {1, 2, 3}}, {L"\U00000001\U0000231a", {1, 8986}, {1, 2}}, {L"\U00000001\U00000308\U0000231a", {1, 776, 8986}, {1, 2, 3}}, {L"\U00000001\U00000300", {1, 768}, {1, 2}}, {L"\U00000001\U00000308\U00000300", {1, 776}, {1, 3}}, + {L"\U00000001\U0000093c", {1, 2364}, {1, 2}}, + {L"\U00000001\U00000308\U0000093c", {1, 776}, {1, 3}}, + {L"\U00000001\U0000094d", {1, 2381}, {1, 2}}, + {L"\U00000001\U00000308\U0000094d", {1, 776}, {1, 3}}, {L"\U00000001\U0000200d", {1, 8205}, {1, 2}}, {L"\U00000001\U00000308\U0000200d", {1, 776}, {1, 3}}, {L"\U00000001\U00000378", {1, 888}, {1, 2}}, @@ -843,8 +1484,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000034f\U00000308\U0001f1e6", {847, 127462}, {2, 4}}, {L"\U0000034f\U00000600", {847, 1536}, {1, 2}}, {L"\U0000034f\U00000308\U00000600", {847, 1536}, {2, 3}}, - {L"\U0000034f\U00000903", {847}, {2}}, - {L"\U0000034f\U00000308\U00000903", {847}, {3}}, + {L"\U0000034f\U00000a03", {847}, {2}}, + {L"\U0000034f\U00000308\U00000a03", {847}, {3}}, {L"\U0000034f\U00001100", {847, 4352}, {1, 2}}, {L"\U0000034f\U00000308\U00001100", {847, 4352}, {2, 3}}, {L"\U0000034f\U00001160", {847, 4448}, {1, 2}}, @@ -855,10 +1496,24 @@ std::array, 602> data_utf16 = {{ {L"\U0000034f\U00000308\U0000ac00", {847, 44032}, {2, 3}}, {L"\U0000034f\U0000ac01", {847, 44033}, {1, 2}}, {L"\U0000034f\U00000308\U0000ac01", {847, 44033}, {2, 3}}, + {L"\U0000034f\U00000900", {847}, {2}}, + {L"\U0000034f\U00000308\U00000900", {847}, {3}}, + {L"\U0000034f\U00000903", {847}, {2}}, + {L"\U0000034f\U00000308\U00000903", {847}, {3}}, + {L"\U0000034f\U00000904", {847, 2308}, {1, 2}}, + {L"\U0000034f\U00000308\U00000904", {847, 2308}, {2, 3}}, + {L"\U0000034f\U00000d4e", {847, 3406}, {1, 2}}, + {L"\U0000034f\U00000308\U00000d4e", {847, 3406}, {2, 3}}, + {L"\U0000034f\U00000915", {847, 2325}, {1, 2}}, + {L"\U0000034f\U00000308\U00000915", {847, 2325}, {2, 3}}, {L"\U0000034f\U0000231a", {847, 8986}, {1, 2}}, {L"\U0000034f\U00000308\U0000231a", {847, 8986}, {2, 3}}, {L"\U0000034f\U00000300", {847}, {2}}, {L"\U0000034f\U00000308\U00000300", {847}, {3}}, + {L"\U0000034f\U0000093c", {847}, {2}}, + {L"\U0000034f\U00000308\U0000093c", {847}, {3}}, + {L"\U0000034f\U0000094d", {847}, {2}}, + {L"\U0000034f\U00000308\U0000094d", {847}, {3}}, {L"\U0000034f\U0000200d", {847}, {2}}, {L"\U0000034f\U00000308\U0000200d", {847}, {3}}, {L"\U0000034f\U00000378", {847, 888}, {1, 2}}, @@ -877,8 +1532,8 @@ std::array, 602> data_utf16 = {{ {L"\U0001f1e6\U00000308\U0001f1e6", {127462, 127462}, {3, 5}}, {L"\U0001f1e6\U00000600", {127462, 1536}, {2, 3}}, {L"\U0001f1e6\U00000308\U00000600", {127462, 1536}, {3, 4}}, - {L"\U0001f1e6\U00000903", {127462}, {3}}, - {L"\U0001f1e6\U00000308\U00000903", {127462}, {4}}, + {L"\U0001f1e6\U00000a03", {127462}, {3}}, + {L"\U0001f1e6\U00000308\U00000a03", {127462}, {4}}, {L"\U0001f1e6\U00001100", {127462, 4352}, {2, 3}}, {L"\U0001f1e6\U00000308\U00001100", {127462, 4352}, {3, 4}}, {L"\U0001f1e6\U00001160", {127462, 4448}, {2, 3}}, @@ -889,10 +1544,24 @@ std::array, 602> data_utf16 = {{ {L"\U0001f1e6\U00000308\U0000ac00", {127462, 44032}, {3, 4}}, {L"\U0001f1e6\U0000ac01", {127462, 44033}, {2, 3}}, {L"\U0001f1e6\U00000308\U0000ac01", {127462, 44033}, {3, 4}}, + {L"\U0001f1e6\U00000900", {127462}, {3}}, + {L"\U0001f1e6\U00000308\U00000900", {127462}, {4}}, + {L"\U0001f1e6\U00000903", {127462}, {3}}, + {L"\U0001f1e6\U00000308\U00000903", {127462}, {4}}, + {L"\U0001f1e6\U00000904", {127462, 2308}, {2, 3}}, + {L"\U0001f1e6\U00000308\U00000904", {127462, 2308}, {3, 4}}, + {L"\U0001f1e6\U00000d4e", {127462, 3406}, {2, 3}}, + {L"\U0001f1e6\U00000308\U00000d4e", {127462, 3406}, {3, 4}}, + {L"\U0001f1e6\U00000915", {127462, 2325}, {2, 3}}, + {L"\U0001f1e6\U00000308\U00000915", {127462, 2325}, {3, 4}}, {L"\U0001f1e6\U0000231a", {127462, 8986}, {2, 3}}, {L"\U0001f1e6\U00000308\U0000231a", {127462, 8986}, {3, 4}}, {L"\U0001f1e6\U00000300", {127462}, {3}}, {L"\U0001f1e6\U00000308\U00000300", {127462}, {4}}, + {L"\U0001f1e6\U0000093c", {127462}, {3}}, + {L"\U0001f1e6\U00000308\U0000093c", {127462}, {4}}, + {L"\U0001f1e6\U0000094d", {127462}, {3}}, + {L"\U0001f1e6\U00000308\U0000094d", {127462}, {4}}, {L"\U0001f1e6\U0000200d", {127462}, {3}}, {L"\U0001f1e6\U00000308\U0000200d", {127462}, {4}}, {L"\U0001f1e6\U00000378", {127462, 888}, {2, 3}}, @@ -911,8 +1580,8 @@ std::array, 602> data_utf16 = {{ {L"\U00000600\U00000308\U0001f1e6", {1536, 127462}, {2, 4}}, {L"\U00000600\U00000600", {1536}, {2}}, {L"\U00000600\U00000308\U00000600", {1536, 1536}, {2, 3}}, - {L"\U00000600\U00000903", {1536}, {2}}, - {L"\U00000600\U00000308\U00000903", {1536}, {3}}, + {L"\U00000600\U00000a03", {1536}, {2}}, + {L"\U00000600\U00000308\U00000a03", {1536}, {3}}, {L"\U00000600\U00001100", {1536}, {2}}, {L"\U00000600\U00000308\U00001100", {1536, 4352}, {2, 3}}, {L"\U00000600\U00001160", {1536}, {2}}, @@ -923,48 +1592,76 @@ std::array, 602> data_utf16 = {{ {L"\U00000600\U00000308\U0000ac00", {1536, 44032}, {2, 3}}, {L"\U00000600\U0000ac01", {1536}, {2}}, {L"\U00000600\U00000308\U0000ac01", {1536, 44033}, {2, 3}}, + {L"\U00000600\U00000900", {1536}, {2}}, + {L"\U00000600\U00000308\U00000900", {1536}, {3}}, + {L"\U00000600\U00000903", {1536}, {2}}, + {L"\U00000600\U00000308\U00000903", {1536}, {3}}, + {L"\U00000600\U00000904", {1536}, {2}}, + {L"\U00000600\U00000308\U00000904", {1536, 2308}, {2, 3}}, + {L"\U00000600\U00000d4e", {1536}, {2}}, + {L"\U00000600\U00000308\U00000d4e", {1536, 3406}, {2, 3}}, + {L"\U00000600\U00000915", {1536}, {2}}, + {L"\U00000600\U00000308\U00000915", {1536, 2325}, {2, 3}}, {L"\U00000600\U0000231a", {1536}, {2}}, {L"\U00000600\U00000308\U0000231a", {1536, 8986}, {2, 3}}, {L"\U00000600\U00000300", {1536}, {2}}, {L"\U00000600\U00000308\U00000300", {1536}, {3}}, + {L"\U00000600\U0000093c", {1536}, {2}}, + {L"\U00000600\U00000308\U0000093c", {1536}, {3}}, + {L"\U00000600\U0000094d", {1536}, {2}}, + {L"\U00000600\U00000308\U0000094d", {1536}, {3}}, {L"\U00000600\U0000200d", {1536}, {2}}, {L"\U00000600\U00000308\U0000200d", {1536}, {3}}, {L"\U00000600\U00000378", {1536}, {2}}, {L"\U00000600\U00000308\U00000378", {1536, 888}, {2, 3}}, - {L"\U00000903\U00000020", {2307, 32}, {1, 2}}, - {L"\U00000903\U00000308\U00000020", {2307, 32}, {2, 3}}, - {L"\U00000903\U0000000d", {2307, 13}, {1, 2}}, - {L"\U00000903\U00000308\U0000000d", {2307, 13}, {2, 3}}, - {L"\U00000903\U0000000a", {2307, 10}, {1, 2}}, - {L"\U00000903\U00000308\U0000000a", {2307, 10}, {2, 3}}, - {L"\U00000903\U00000001", {2307, 1}, {1, 2}}, - {L"\U00000903\U00000308\U00000001", {2307, 1}, {2, 3}}, - {L"\U00000903\U0000034f", {2307}, {2}}, - {L"\U00000903\U00000308\U0000034f", {2307}, {3}}, - {L"\U00000903\U0001f1e6", {2307, 127462}, {1, 3}}, - {L"\U00000903\U00000308\U0001f1e6", {2307, 127462}, {2, 4}}, - {L"\U00000903\U00000600", {2307, 1536}, {1, 2}}, - {L"\U00000903\U00000308\U00000600", {2307, 1536}, {2, 3}}, - {L"\U00000903\U00000903", {2307}, {2}}, - {L"\U00000903\U00000308\U00000903", {2307}, {3}}, - {L"\U00000903\U00001100", {2307, 4352}, {1, 2}}, - {L"\U00000903\U00000308\U00001100", {2307, 4352}, {2, 3}}, - {L"\U00000903\U00001160", {2307, 4448}, {1, 2}}, - {L"\U00000903\U00000308\U00001160", {2307, 4448}, {2, 3}}, - {L"\U00000903\U000011a8", {2307, 4520}, {1, 2}}, - {L"\U00000903\U00000308\U000011a8", {2307, 4520}, {2, 3}}, - {L"\U00000903\U0000ac00", {2307, 44032}, {1, 2}}, - {L"\U00000903\U00000308\U0000ac00", {2307, 44032}, {2, 3}}, - {L"\U00000903\U0000ac01", {2307, 44033}, {1, 2}}, - {L"\U00000903\U00000308\U0000ac01", {2307, 44033}, {2, 3}}, - {L"\U00000903\U0000231a", {2307, 8986}, {1, 2}}, - {L"\U00000903\U00000308\U0000231a", {2307, 8986}, {2, 3}}, - {L"\U00000903\U00000300", {2307}, {2}}, - {L"\U00000903\U00000308\U00000300", {2307}, {3}}, - {L"\U00000903\U0000200d", {2307}, {2}}, - {L"\U00000903\U00000308\U0000200d", {2307}, {3}}, - {L"\U00000903\U00000378", {2307, 888}, {1, 2}}, - {L"\U00000903\U00000308\U00000378", {2307, 888}, {2, 3}}, + {L"\U00000a03\U00000020", {2563, 32}, {1, 2}}, + {L"\U00000a03\U00000308\U00000020", {2563, 32}, {2, 3}}, + {L"\U00000a03\U0000000d", {2563, 13}, {1, 2}}, + {L"\U00000a03\U00000308\U0000000d", {2563, 13}, {2, 3}}, + {L"\U00000a03\U0000000a", {2563, 10}, {1, 2}}, + {L"\U00000a03\U00000308\U0000000a", {2563, 10}, {2, 3}}, + {L"\U00000a03\U00000001", {2563, 1}, {1, 2}}, + {L"\U00000a03\U00000308\U00000001", {2563, 1}, {2, 3}}, + {L"\U00000a03\U0000034f", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000034f", {2563}, {3}}, + {L"\U00000a03\U0001f1e6", {2563, 127462}, {1, 3}}, + {L"\U00000a03\U00000308\U0001f1e6", {2563, 127462}, {2, 4}}, + {L"\U00000a03\U00000600", {2563, 1536}, {1, 2}}, + {L"\U00000a03\U00000308\U00000600", {2563, 1536}, {2, 3}}, + {L"\U00000a03\U00000a03", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000a03", {2563}, {3}}, + {L"\U00000a03\U00001100", {2563, 4352}, {1, 2}}, + {L"\U00000a03\U00000308\U00001100", {2563, 4352}, {2, 3}}, + {L"\U00000a03\U00001160", {2563, 4448}, {1, 2}}, + {L"\U00000a03\U00000308\U00001160", {2563, 4448}, {2, 3}}, + {L"\U00000a03\U000011a8", {2563, 4520}, {1, 2}}, + {L"\U00000a03\U00000308\U000011a8", {2563, 4520}, {2, 3}}, + {L"\U00000a03\U0000ac00", {2563, 44032}, {1, 2}}, + {L"\U00000a03\U00000308\U0000ac00", {2563, 44032}, {2, 3}}, + {L"\U00000a03\U0000ac01", {2563, 44033}, {1, 2}}, + {L"\U00000a03\U00000308\U0000ac01", {2563, 44033}, {2, 3}}, + {L"\U00000a03\U00000900", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000900", {2563}, {3}}, + {L"\U00000a03\U00000903", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000903", {2563}, {3}}, + {L"\U00000a03\U00000904", {2563, 2308}, {1, 2}}, + {L"\U00000a03\U00000308\U00000904", {2563, 2308}, {2, 3}}, + {L"\U00000a03\U00000d4e", {2563, 3406}, {1, 2}}, + {L"\U00000a03\U00000308\U00000d4e", {2563, 3406}, {2, 3}}, + {L"\U00000a03\U00000915", {2563, 2325}, {1, 2}}, + {L"\U00000a03\U00000308\U00000915", {2563, 2325}, {2, 3}}, + {L"\U00000a03\U0000231a", {2563, 8986}, {1, 2}}, + {L"\U00000a03\U00000308\U0000231a", {2563, 8986}, {2, 3}}, + {L"\U00000a03\U00000300", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000300", {2563}, {3}}, + {L"\U00000a03\U0000093c", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000093c", {2563}, {3}}, + {L"\U00000a03\U0000094d", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000094d", {2563}, {3}}, + {L"\U00000a03\U0000200d", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000200d", {2563}, {3}}, + {L"\U00000a03\U00000378", {2563, 888}, {1, 2}}, + {L"\U00000a03\U00000308\U00000378", {2563, 888}, {2, 3}}, {L"\U00001100\U00000020", {4352, 32}, {1, 2}}, {L"\U00001100\U00000308\U00000020", {4352, 32}, {2, 3}}, {L"\U00001100\U0000000d", {4352, 13}, {1, 2}}, @@ -979,8 +1676,8 @@ std::array, 602> data_utf16 = {{ {L"\U00001100\U00000308\U0001f1e6", {4352, 127462}, {2, 4}}, {L"\U00001100\U00000600", {4352, 1536}, {1, 2}}, {L"\U00001100\U00000308\U00000600", {4352, 1536}, {2, 3}}, - {L"\U00001100\U00000903", {4352}, {2}}, - {L"\U00001100\U00000308\U00000903", {4352}, {3}}, + {L"\U00001100\U00000a03", {4352}, {2}}, + {L"\U00001100\U00000308\U00000a03", {4352}, {3}}, {L"\U00001100\U00001100", {4352}, {2}}, {L"\U00001100\U00000308\U00001100", {4352, 4352}, {2, 3}}, {L"\U00001100\U00001160", {4352}, {2}}, @@ -991,10 +1688,24 @@ std::array, 602> data_utf16 = {{ {L"\U00001100\U00000308\U0000ac00", {4352, 44032}, {2, 3}}, {L"\U00001100\U0000ac01", {4352}, {2}}, {L"\U00001100\U00000308\U0000ac01", {4352, 44033}, {2, 3}}, + {L"\U00001100\U00000900", {4352}, {2}}, + {L"\U00001100\U00000308\U00000900", {4352}, {3}}, + {L"\U00001100\U00000903", {4352}, {2}}, + {L"\U00001100\U00000308\U00000903", {4352}, {3}}, + {L"\U00001100\U00000904", {4352, 2308}, {1, 2}}, + {L"\U00001100\U00000308\U00000904", {4352, 2308}, {2, 3}}, + {L"\U00001100\U00000d4e", {4352, 3406}, {1, 2}}, + {L"\U00001100\U00000308\U00000d4e", {4352, 3406}, {2, 3}}, + {L"\U00001100\U00000915", {4352, 2325}, {1, 2}}, + {L"\U00001100\U00000308\U00000915", {4352, 2325}, {2, 3}}, {L"\U00001100\U0000231a", {4352, 8986}, {1, 2}}, {L"\U00001100\U00000308\U0000231a", {4352, 8986}, {2, 3}}, {L"\U00001100\U00000300", {4352}, {2}}, {L"\U00001100\U00000308\U00000300", {4352}, {3}}, + {L"\U00001100\U0000093c", {4352}, {2}}, + {L"\U00001100\U00000308\U0000093c", {4352}, {3}}, + {L"\U00001100\U0000094d", {4352}, {2}}, + {L"\U00001100\U00000308\U0000094d", {4352}, {3}}, {L"\U00001100\U0000200d", {4352}, {2}}, {L"\U00001100\U00000308\U0000200d", {4352}, {3}}, {L"\U00001100\U00000378", {4352, 888}, {1, 2}}, @@ -1013,8 +1724,8 @@ std::array, 602> data_utf16 = {{ {L"\U00001160\U00000308\U0001f1e6", {4448, 127462}, {2, 4}}, {L"\U00001160\U00000600", {4448, 1536}, {1, 2}}, {L"\U00001160\U00000308\U00000600", {4448, 1536}, {2, 3}}, - {L"\U00001160\U00000903", {4448}, {2}}, - {L"\U00001160\U00000308\U00000903", {4448}, {3}}, + {L"\U00001160\U00000a03", {4448}, {2}}, + {L"\U00001160\U00000308\U00000a03", {4448}, {3}}, {L"\U00001160\U00001100", {4448, 4352}, {1, 2}}, {L"\U00001160\U00000308\U00001100", {4448, 4352}, {2, 3}}, {L"\U00001160\U00001160", {4448}, {2}}, @@ -1025,10 +1736,24 @@ std::array, 602> data_utf16 = {{ {L"\U00001160\U00000308\U0000ac00", {4448, 44032}, {2, 3}}, {L"\U00001160\U0000ac01", {4448, 44033}, {1, 2}}, {L"\U00001160\U00000308\U0000ac01", {4448, 44033}, {2, 3}}, + {L"\U00001160\U00000900", {4448}, {2}}, + {L"\U00001160\U00000308\U00000900", {4448}, {3}}, + {L"\U00001160\U00000903", {4448}, {2}}, + {L"\U00001160\U00000308\U00000903", {4448}, {3}}, + {L"\U00001160\U00000904", {4448, 2308}, {1, 2}}, + {L"\U00001160\U00000308\U00000904", {4448, 2308}, {2, 3}}, + {L"\U00001160\U00000d4e", {4448, 3406}, {1, 2}}, + {L"\U00001160\U00000308\U00000d4e", {4448, 3406}, {2, 3}}, + {L"\U00001160\U00000915", {4448, 2325}, {1, 2}}, + {L"\U00001160\U00000308\U00000915", {4448, 2325}, {2, 3}}, {L"\U00001160\U0000231a", {4448, 8986}, {1, 2}}, {L"\U00001160\U00000308\U0000231a", {4448, 8986}, {2, 3}}, {L"\U00001160\U00000300", {4448}, {2}}, {L"\U00001160\U00000308\U00000300", {4448}, {3}}, + {L"\U00001160\U0000093c", {4448}, {2}}, + {L"\U00001160\U00000308\U0000093c", {4448}, {3}}, + {L"\U00001160\U0000094d", {4448}, {2}}, + {L"\U00001160\U00000308\U0000094d", {4448}, {3}}, {L"\U00001160\U0000200d", {4448}, {2}}, {L"\U00001160\U00000308\U0000200d", {4448}, {3}}, {L"\U00001160\U00000378", {4448, 888}, {1, 2}}, @@ -1047,8 +1772,8 @@ std::array, 602> data_utf16 = {{ {L"\U000011a8\U00000308\U0001f1e6", {4520, 127462}, {2, 4}}, {L"\U000011a8\U00000600", {4520, 1536}, {1, 2}}, {L"\U000011a8\U00000308\U00000600", {4520, 1536}, {2, 3}}, - {L"\U000011a8\U00000903", {4520}, {2}}, - {L"\U000011a8\U00000308\U00000903", {4520}, {3}}, + {L"\U000011a8\U00000a03", {4520}, {2}}, + {L"\U000011a8\U00000308\U00000a03", {4520}, {3}}, {L"\U000011a8\U00001100", {4520, 4352}, {1, 2}}, {L"\U000011a8\U00000308\U00001100", {4520, 4352}, {2, 3}}, {L"\U000011a8\U00001160", {4520, 4448}, {1, 2}}, @@ -1059,10 +1784,24 @@ std::array, 602> data_utf16 = {{ {L"\U000011a8\U00000308\U0000ac00", {4520, 44032}, {2, 3}}, {L"\U000011a8\U0000ac01", {4520, 44033}, {1, 2}}, {L"\U000011a8\U00000308\U0000ac01", {4520, 44033}, {2, 3}}, + {L"\U000011a8\U00000900", {4520}, {2}}, + {L"\U000011a8\U00000308\U00000900", {4520}, {3}}, + {L"\U000011a8\U00000903", {4520}, {2}}, + {L"\U000011a8\U00000308\U00000903", {4520}, {3}}, + {L"\U000011a8\U00000904", {4520, 2308}, {1, 2}}, + {L"\U000011a8\U00000308\U00000904", {4520, 2308}, {2, 3}}, + {L"\U000011a8\U00000d4e", {4520, 3406}, {1, 2}}, + {L"\U000011a8\U00000308\U00000d4e", {4520, 3406}, {2, 3}}, + {L"\U000011a8\U00000915", {4520, 2325}, {1, 2}}, + {L"\U000011a8\U00000308\U00000915", {4520, 2325}, {2, 3}}, {L"\U000011a8\U0000231a", {4520, 8986}, {1, 2}}, {L"\U000011a8\U00000308\U0000231a", {4520, 8986}, {2, 3}}, {L"\U000011a8\U00000300", {4520}, {2}}, {L"\U000011a8\U00000308\U00000300", {4520}, {3}}, + {L"\U000011a8\U0000093c", {4520}, {2}}, + {L"\U000011a8\U00000308\U0000093c", {4520}, {3}}, + {L"\U000011a8\U0000094d", {4520}, {2}}, + {L"\U000011a8\U00000308\U0000094d", {4520}, {3}}, {L"\U000011a8\U0000200d", {4520}, {2}}, {L"\U000011a8\U00000308\U0000200d", {4520}, {3}}, {L"\U000011a8\U00000378", {4520, 888}, {1, 2}}, @@ -1081,8 +1820,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000ac00\U00000308\U0001f1e6", {44032, 127462}, {2, 4}}, {L"\U0000ac00\U00000600", {44032, 1536}, {1, 2}}, {L"\U0000ac00\U00000308\U00000600", {44032, 1536}, {2, 3}}, - {L"\U0000ac00\U00000903", {44032}, {2}}, - {L"\U0000ac00\U00000308\U00000903", {44032}, {3}}, + {L"\U0000ac00\U00000a03", {44032}, {2}}, + {L"\U0000ac00\U00000308\U00000a03", {44032}, {3}}, {L"\U0000ac00\U00001100", {44032, 4352}, {1, 2}}, {L"\U0000ac00\U00000308\U00001100", {44032, 4352}, {2, 3}}, {L"\U0000ac00\U00001160", {44032}, {2}}, @@ -1093,10 +1832,24 @@ std::array, 602> data_utf16 = {{ {L"\U0000ac00\U00000308\U0000ac00", {44032, 44032}, {2, 3}}, {L"\U0000ac00\U0000ac01", {44032, 44033}, {1, 2}}, {L"\U0000ac00\U00000308\U0000ac01", {44032, 44033}, {2, 3}}, + {L"\U0000ac00\U00000900", {44032}, {2}}, + {L"\U0000ac00\U00000308\U00000900", {44032}, {3}}, + {L"\U0000ac00\U00000903", {44032}, {2}}, + {L"\U0000ac00\U00000308\U00000903", {44032}, {3}}, + {L"\U0000ac00\U00000904", {44032, 2308}, {1, 2}}, + {L"\U0000ac00\U00000308\U00000904", {44032, 2308}, {2, 3}}, + {L"\U0000ac00\U00000d4e", {44032, 3406}, {1, 2}}, + {L"\U0000ac00\U00000308\U00000d4e", {44032, 3406}, {2, 3}}, + {L"\U0000ac00\U00000915", {44032, 2325}, {1, 2}}, + {L"\U0000ac00\U00000308\U00000915", {44032, 2325}, {2, 3}}, {L"\U0000ac00\U0000231a", {44032, 8986}, {1, 2}}, {L"\U0000ac00\U00000308\U0000231a", {44032, 8986}, {2, 3}}, {L"\U0000ac00\U00000300", {44032}, {2}}, {L"\U0000ac00\U00000308\U00000300", {44032}, {3}}, + {L"\U0000ac00\U0000093c", {44032}, {2}}, + {L"\U0000ac00\U00000308\U0000093c", {44032}, {3}}, + {L"\U0000ac00\U0000094d", {44032}, {2}}, + {L"\U0000ac00\U00000308\U0000094d", {44032}, {3}}, {L"\U0000ac00\U0000200d", {44032}, {2}}, {L"\U0000ac00\U00000308\U0000200d", {44032}, {3}}, {L"\U0000ac00\U00000378", {44032, 888}, {1, 2}}, @@ -1115,8 +1868,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000ac01\U00000308\U0001f1e6", {44033, 127462}, {2, 4}}, {L"\U0000ac01\U00000600", {44033, 1536}, {1, 2}}, {L"\U0000ac01\U00000308\U00000600", {44033, 1536}, {2, 3}}, - {L"\U0000ac01\U00000903", {44033}, {2}}, - {L"\U0000ac01\U00000308\U00000903", {44033}, {3}}, + {L"\U0000ac01\U00000a03", {44033}, {2}}, + {L"\U0000ac01\U00000308\U00000a03", {44033}, {3}}, {L"\U0000ac01\U00001100", {44033, 4352}, {1, 2}}, {L"\U0000ac01\U00000308\U00001100", {44033, 4352}, {2, 3}}, {L"\U0000ac01\U00001160", {44033, 4448}, {1, 2}}, @@ -1127,14 +1880,268 @@ std::array, 602> data_utf16 = {{ {L"\U0000ac01\U00000308\U0000ac00", {44033, 44032}, {2, 3}}, {L"\U0000ac01\U0000ac01", {44033, 44033}, {1, 2}}, {L"\U0000ac01\U00000308\U0000ac01", {44033, 44033}, {2, 3}}, + {L"\U0000ac01\U00000900", {44033}, {2}}, + {L"\U0000ac01\U00000308\U00000900", {44033}, {3}}, + {L"\U0000ac01\U00000903", {44033}, {2}}, + {L"\U0000ac01\U00000308\U00000903", {44033}, {3}}, + {L"\U0000ac01\U00000904", {44033, 2308}, {1, 2}}, + {L"\U0000ac01\U00000308\U00000904", {44033, 2308}, {2, 3}}, + {L"\U0000ac01\U00000d4e", {44033, 3406}, {1, 2}}, + {L"\U0000ac01\U00000308\U00000d4e", {44033, 3406}, {2, 3}}, + {L"\U0000ac01\U00000915", {44033, 2325}, {1, 2}}, + {L"\U0000ac01\U00000308\U00000915", {44033, 2325}, {2, 3}}, {L"\U0000ac01\U0000231a", {44033, 8986}, {1, 2}}, {L"\U0000ac01\U00000308\U0000231a", {44033, 8986}, {2, 3}}, {L"\U0000ac01\U00000300", {44033}, {2}}, {L"\U0000ac01\U00000308\U00000300", {44033}, {3}}, + {L"\U0000ac01\U0000093c", {44033}, {2}}, + {L"\U0000ac01\U00000308\U0000093c", {44033}, {3}}, + {L"\U0000ac01\U0000094d", {44033}, {2}}, + {L"\U0000ac01\U00000308\U0000094d", {44033}, {3}}, {L"\U0000ac01\U0000200d", {44033}, {2}}, {L"\U0000ac01\U00000308\U0000200d", {44033}, {3}}, {L"\U0000ac01\U00000378", {44033, 888}, {1, 2}}, {L"\U0000ac01\U00000308\U00000378", {44033, 888}, {2, 3}}, + {L"\U00000900\U00000020", {2304, 32}, {1, 2}}, + {L"\U00000900\U00000308\U00000020", {2304, 32}, {2, 3}}, + {L"\U00000900\U0000000d", {2304, 13}, {1, 2}}, + {L"\U00000900\U00000308\U0000000d", {2304, 13}, {2, 3}}, + {L"\U00000900\U0000000a", {2304, 10}, {1, 2}}, + {L"\U00000900\U00000308\U0000000a", {2304, 10}, {2, 3}}, + {L"\U00000900\U00000001", {2304, 1}, {1, 2}}, + {L"\U00000900\U00000308\U00000001", {2304, 1}, {2, 3}}, + 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{2325, 1}, {1, 2}}, + {L"\U00000915\U00000308\U00000001", {2325, 1}, {2, 3}}, + {L"\U00000915\U0000034f", {2325}, {2}}, + {L"\U00000915\U00000308\U0000034f", {2325}, {3}}, + {L"\U00000915\U0001f1e6", {2325, 127462}, {1, 3}}, + {L"\U00000915\U00000308\U0001f1e6", {2325, 127462}, {2, 4}}, + {L"\U00000915\U00000600", {2325, 1536}, {1, 2}}, + {L"\U00000915\U00000308\U00000600", {2325, 1536}, {2, 3}}, + {L"\U00000915\U00000a03", {2325}, {2}}, + {L"\U00000915\U00000308\U00000a03", {2325}, {3}}, + {L"\U00000915\U00001100", {2325, 4352}, {1, 2}}, + {L"\U00000915\U00000308\U00001100", {2325, 4352}, {2, 3}}, + {L"\U00000915\U00001160", {2325, 4448}, {1, 2}}, + {L"\U00000915\U00000308\U00001160", {2325, 4448}, {2, 3}}, + {L"\U00000915\U000011a8", {2325, 4520}, {1, 2}}, + {L"\U00000915\U00000308\U000011a8", {2325, 4520}, {2, 3}}, + {L"\U00000915\U0000ac00", {2325, 44032}, {1, 2}}, + {L"\U00000915\U00000308\U0000ac00", {2325, 44032}, {2, 3}}, + {L"\U00000915\U0000ac01", {2325, 44033}, {1, 2}}, + {L"\U00000915\U00000308\U0000ac01", {2325, 44033}, {2, 3}}, + {L"\U00000915\U00000900", {2325}, {2}}, + {L"\U00000915\U00000308\U00000900", {2325}, {3}}, + {L"\U00000915\U00000903", {2325}, {2}}, + {L"\U00000915\U00000308\U00000903", {2325}, {3}}, + {L"\U00000915\U00000904", {2325, 2308}, {1, 2}}, + {L"\U00000915\U00000308\U00000904", {2325, 2308}, {2, 3}}, + {L"\U00000915\U00000d4e", {2325, 3406}, {1, 2}}, + {L"\U00000915\U00000308\U00000d4e", {2325, 3406}, {2, 3}}, + {L"\U00000915\U00000915", {2325, 2325}, {1, 2}}, + {L"\U00000915\U00000308\U00000915", {2325, 2325}, {2, 3}}, + {L"\U00000915\U0000231a", {2325, 8986}, {1, 2}}, + {L"\U00000915\U00000308\U0000231a", {2325, 8986}, {2, 3}}, + {L"\U00000915\U00000300", {2325}, {2}}, + {L"\U00000915\U00000308\U00000300", {2325}, {3}}, + {L"\U00000915\U0000093c", {2325}, {2}}, + {L"\U00000915\U00000308\U0000093c", {2325}, {3}}, + {L"\U00000915\U0000094d", {2325}, {2}}, + {L"\U00000915\U00000308\U0000094d", {2325}, {3}}, + {L"\U00000915\U0000200d", {2325}, {2}}, + {L"\U00000915\U00000308\U0000200d", {2325}, {3}}, + {L"\U00000915\U00000378", {2325, 888}, {1, 2}}, + {L"\U00000915\U00000308\U00000378", {2325, 888}, {2, 3}}, {L"\U0000231a\U00000020", {8986, 32}, {1, 2}}, {L"\U0000231a\U00000308\U00000020", {8986, 32}, {2, 3}}, {L"\U0000231a\U0000000d", {8986, 13}, {1, 2}}, @@ -1149,8 +2156,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000231a\U00000308\U0001f1e6", {8986, 127462}, {2, 4}}, {L"\U0000231a\U00000600", {8986, 1536}, {1, 2}}, {L"\U0000231a\U00000308\U00000600", {8986, 1536}, {2, 3}}, - {L"\U0000231a\U00000903", {8986}, {2}}, - {L"\U0000231a\U00000308\U00000903", {8986}, {3}}, + {L"\U0000231a\U00000a03", {8986}, {2}}, + {L"\U0000231a\U00000308\U00000a03", {8986}, {3}}, {L"\U0000231a\U00001100", {8986, 4352}, {1, 2}}, {L"\U0000231a\U00000308\U00001100", {8986, 4352}, {2, 3}}, {L"\U0000231a\U00001160", {8986, 4448}, {1, 2}}, @@ -1161,10 +2168,24 @@ std::array, 602> data_utf16 = {{ {L"\U0000231a\U00000308\U0000ac00", {8986, 44032}, {2, 3}}, {L"\U0000231a\U0000ac01", {8986, 44033}, {1, 2}}, {L"\U0000231a\U00000308\U0000ac01", {8986, 44033}, {2, 3}}, + {L"\U0000231a\U00000900", {8986}, {2}}, + {L"\U0000231a\U00000308\U00000900", {8986}, {3}}, + {L"\U0000231a\U00000903", {8986}, {2}}, + {L"\U0000231a\U00000308\U00000903", {8986}, {3}}, + {L"\U0000231a\U00000904", {8986, 2308}, {1, 2}}, + {L"\U0000231a\U00000308\U00000904", {8986, 2308}, {2, 3}}, + {L"\U0000231a\U00000d4e", {8986, 3406}, {1, 2}}, + {L"\U0000231a\U00000308\U00000d4e", {8986, 3406}, {2, 3}}, + {L"\U0000231a\U00000915", {8986, 2325}, {1, 2}}, + {L"\U0000231a\U00000308\U00000915", {8986, 2325}, {2, 3}}, {L"\U0000231a\U0000231a", {8986, 8986}, {1, 2}}, {L"\U0000231a\U00000308\U0000231a", {8986, 8986}, {2, 3}}, {L"\U0000231a\U00000300", {8986}, {2}}, {L"\U0000231a\U00000308\U00000300", {8986}, {3}}, + {L"\U0000231a\U0000093c", {8986}, {2}}, + {L"\U0000231a\U00000308\U0000093c", {8986}, {3}}, + {L"\U0000231a\U0000094d", {8986}, {2}}, + {L"\U0000231a\U00000308\U0000094d", {8986}, {3}}, {L"\U0000231a\U0000200d", {8986}, {2}}, {L"\U0000231a\U00000308\U0000200d", {8986}, {3}}, {L"\U0000231a\U00000378", {8986, 888}, {1, 2}}, @@ -1183,8 +2204,8 @@ std::array, 602> data_utf16 = {{ {L"\U00000300\U00000308\U0001f1e6", {768, 127462}, {2, 4}}, {L"\U00000300\U00000600", {768, 1536}, {1, 2}}, {L"\U00000300\U00000308\U00000600", {768, 1536}, {2, 3}}, - {L"\U00000300\U00000903", {768}, {2}}, - {L"\U00000300\U00000308\U00000903", {768}, {3}}, + {L"\U00000300\U00000a03", {768}, {2}}, + {L"\U00000300\U00000308\U00000a03", {768}, {3}}, {L"\U00000300\U00001100", {768, 4352}, {1, 2}}, {L"\U00000300\U00000308\U00001100", {768, 4352}, {2, 3}}, {L"\U00000300\U00001160", {768, 4448}, {1, 2}}, @@ -1195,14 +2216,124 @@ std::array, 602> data_utf16 = {{ {L"\U00000300\U00000308\U0000ac00", {768, 44032}, {2, 3}}, {L"\U00000300\U0000ac01", {768, 44033}, {1, 2}}, {L"\U00000300\U00000308\U0000ac01", {768, 44033}, {2, 3}}, + {L"\U00000300\U00000900", {768}, {2}}, + {L"\U00000300\U00000308\U00000900", {768}, {3}}, + {L"\U00000300\U00000903", {768}, {2}}, + {L"\U00000300\U00000308\U00000903", {768}, {3}}, + {L"\U00000300\U00000904", {768, 2308}, {1, 2}}, + {L"\U00000300\U00000308\U00000904", {768, 2308}, {2, 3}}, + {L"\U00000300\U00000d4e", {768, 3406}, {1, 2}}, + {L"\U00000300\U00000308\U00000d4e", {768, 3406}, {2, 3}}, + {L"\U00000300\U00000915", {768, 2325}, {1, 2}}, + {L"\U00000300\U00000308\U00000915", {768, 2325}, {2, 3}}, {L"\U00000300\U0000231a", {768, 8986}, {1, 2}}, {L"\U00000300\U00000308\U0000231a", {768, 8986}, {2, 3}}, {L"\U00000300\U00000300", {768}, {2}}, {L"\U00000300\U00000308\U00000300", {768}, {3}}, + {L"\U00000300\U0000093c", {768}, {2}}, + {L"\U00000300\U00000308\U0000093c", {768}, {3}}, + {L"\U00000300\U0000094d", {768}, {2}}, + {L"\U00000300\U00000308\U0000094d", {768}, {3}}, {L"\U00000300\U0000200d", {768}, {2}}, {L"\U00000300\U00000308\U0000200d", {768}, {3}}, {L"\U00000300\U00000378", {768, 888}, {1, 2}}, {L"\U00000300\U00000308\U00000378", {768, 888}, {2, 3}}, + {L"\U0000093c\U00000020", {2364, 32}, {1, 2}}, + {L"\U0000093c\U00000308\U00000020", {2364, 32}, {2, 3}}, + {L"\U0000093c\U0000000d", {2364, 13}, {1, 2}}, + {L"\U0000093c\U00000308\U0000000d", {2364, 13}, {2, 3}}, + {L"\U0000093c\U0000000a", {2364, 10}, {1, 2}}, + {L"\U0000093c\U00000308\U0000000a", {2364, 10}, {2, 3}}, + {L"\U0000093c\U00000001", {2364, 1}, {1, 2}}, + {L"\U0000093c\U00000308\U00000001", {2364, 1}, {2, 3}}, + {L"\U0000093c\U0000034f", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000034f", {2364}, {3}}, + {L"\U0000093c\U0001f1e6", {2364, 127462}, {1, 3}}, + {L"\U0000093c\U00000308\U0001f1e6", {2364, 127462}, {2, 4}}, + {L"\U0000093c\U00000600", {2364, 1536}, {1, 2}}, + {L"\U0000093c\U00000308\U00000600", {2364, 1536}, {2, 3}}, + {L"\U0000093c\U00000a03", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000a03", {2364}, {3}}, + {L"\U0000093c\U00001100", {2364, 4352}, {1, 2}}, + {L"\U0000093c\U00000308\U00001100", {2364, 4352}, {2, 3}}, + {L"\U0000093c\U00001160", {2364, 4448}, {1, 2}}, + {L"\U0000093c\U00000308\U00001160", {2364, 4448}, {2, 3}}, + {L"\U0000093c\U000011a8", {2364, 4520}, {1, 2}}, + {L"\U0000093c\U00000308\U000011a8", {2364, 4520}, {2, 3}}, + {L"\U0000093c\U0000ac00", {2364, 44032}, {1, 2}}, + {L"\U0000093c\U00000308\U0000ac00", {2364, 44032}, {2, 3}}, + {L"\U0000093c\U0000ac01", {2364, 44033}, {1, 2}}, + {L"\U0000093c\U00000308\U0000ac01", {2364, 44033}, {2, 3}}, + {L"\U0000093c\U00000900", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000900", {2364}, {3}}, + {L"\U0000093c\U00000903", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000903", {2364}, {3}}, + {L"\U0000093c\U00000904", {2364, 2308}, {1, 2}}, + {L"\U0000093c\U00000308\U00000904", {2364, 2308}, {2, 3}}, + {L"\U0000093c\U00000d4e", {2364, 3406}, {1, 2}}, + {L"\U0000093c\U00000308\U00000d4e", {2364, 3406}, {2, 3}}, + {L"\U0000093c\U00000915", {2364, 2325}, {1, 2}}, + {L"\U0000093c\U00000308\U00000915", {2364, 2325}, {2, 3}}, + {L"\U0000093c\U0000231a", {2364, 8986}, {1, 2}}, + {L"\U0000093c\U00000308\U0000231a", {2364, 8986}, {2, 3}}, + {L"\U0000093c\U00000300", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000300", {2364}, {3}}, + {L"\U0000093c\U0000093c", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000093c", {2364}, {3}}, + {L"\U0000093c\U0000094d", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000094d", {2364}, {3}}, + {L"\U0000093c\U0000200d", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000200d", {2364}, {3}}, + {L"\U0000093c\U00000378", {2364, 888}, {1, 2}}, + {L"\U0000093c\U00000308\U00000378", {2364, 888}, {2, 3}}, + {L"\U0000094d\U00000020", {2381, 32}, {1, 2}}, + {L"\U0000094d\U00000308\U00000020", {2381, 32}, {2, 3}}, + {L"\U0000094d\U0000000d", {2381, 13}, {1, 2}}, + {L"\U0000094d\U00000308\U0000000d", {2381, 13}, {2, 3}}, + {L"\U0000094d\U0000000a", {2381, 10}, {1, 2}}, + {L"\U0000094d\U00000308\U0000000a", {2381, 10}, {2, 3}}, + {L"\U0000094d\U00000001", {2381, 1}, {1, 2}}, + {L"\U0000094d\U00000308\U00000001", {2381, 1}, {2, 3}}, + {L"\U0000094d\U0000034f", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000034f", {2381}, {3}}, + {L"\U0000094d\U0001f1e6", {2381, 127462}, {1, 3}}, + {L"\U0000094d\U00000308\U0001f1e6", {2381, 127462}, {2, 4}}, + {L"\U0000094d\U00000600", {2381, 1536}, {1, 2}}, + {L"\U0000094d\U00000308\U00000600", {2381, 1536}, {2, 3}}, + {L"\U0000094d\U00000a03", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000a03", {2381}, {3}}, + {L"\U0000094d\U00001100", {2381, 4352}, {1, 2}}, + {L"\U0000094d\U00000308\U00001100", {2381, 4352}, {2, 3}}, + {L"\U0000094d\U00001160", {2381, 4448}, {1, 2}}, + {L"\U0000094d\U00000308\U00001160", {2381, 4448}, {2, 3}}, + {L"\U0000094d\U000011a8", {2381, 4520}, {1, 2}}, + {L"\U0000094d\U00000308\U000011a8", {2381, 4520}, {2, 3}}, + {L"\U0000094d\U0000ac00", {2381, 44032}, {1, 2}}, + {L"\U0000094d\U00000308\U0000ac00", {2381, 44032}, {2, 3}}, + {L"\U0000094d\U0000ac01", {2381, 44033}, {1, 2}}, + {L"\U0000094d\U00000308\U0000ac01", {2381, 44033}, {2, 3}}, + {L"\U0000094d\U00000900", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000900", {2381}, {3}}, + {L"\U0000094d\U00000903", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000903", {2381}, {3}}, + {L"\U0000094d\U00000904", {2381, 2308}, {1, 2}}, + {L"\U0000094d\U00000308\U00000904", {2381, 2308}, {2, 3}}, + {L"\U0000094d\U00000d4e", {2381, 3406}, {1, 2}}, + {L"\U0000094d\U00000308\U00000d4e", {2381, 3406}, {2, 3}}, + {L"\U0000094d\U00000915", {2381, 2325}, {1, 2}}, + {L"\U0000094d\U00000308\U00000915", {2381, 2325}, {2, 3}}, + {L"\U0000094d\U0000231a", {2381, 8986}, {1, 2}}, + {L"\U0000094d\U00000308\U0000231a", {2381, 8986}, {2, 3}}, + {L"\U0000094d\U00000300", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000300", {2381}, {3}}, + {L"\U0000094d\U0000093c", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000093c", {2381}, {3}}, + {L"\U0000094d\U0000094d", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000094d", {2381}, {3}}, + {L"\U0000094d\U0000200d", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000200d", {2381}, {3}}, + {L"\U0000094d\U00000378", {2381, 888}, {1, 2}}, + {L"\U0000094d\U00000308\U00000378", {2381, 888}, {2, 3}}, {L"\U0000200d\U00000020", {8205, 32}, {1, 2}}, {L"\U0000200d\U00000308\U00000020", {8205, 32}, {2, 3}}, {L"\U0000200d\U0000000d", {8205, 13}, {1, 2}}, @@ -1217,8 +2348,8 @@ std::array, 602> data_utf16 = {{ {L"\U0000200d\U00000308\U0001f1e6", {8205, 127462}, {2, 4}}, {L"\U0000200d\U00000600", {8205, 1536}, {1, 2}}, {L"\U0000200d\U00000308\U00000600", {8205, 1536}, {2, 3}}, - {L"\U0000200d\U00000903", {8205}, {2}}, - {L"\U0000200d\U00000308\U00000903", {8205}, {3}}, + {L"\U0000200d\U00000a03", {8205}, {2}}, + {L"\U0000200d\U00000308\U00000a03", {8205}, {3}}, {L"\U0000200d\U00001100", {8205, 4352}, {1, 2}}, {L"\U0000200d\U00000308\U00001100", {8205, 4352}, {2, 3}}, {L"\U0000200d\U00001160", {8205, 4448}, {1, 2}}, @@ -1229,10 +2360,24 @@ std::array, 602> data_utf16 = {{ {L"\U0000200d\U00000308\U0000ac00", {8205, 44032}, {2, 3}}, {L"\U0000200d\U0000ac01", {8205, 44033}, {1, 2}}, {L"\U0000200d\U00000308\U0000ac01", {8205, 44033}, {2, 3}}, + {L"\U0000200d\U00000900", {8205}, {2}}, + {L"\U0000200d\U00000308\U00000900", {8205}, {3}}, + {L"\U0000200d\U00000903", {8205}, {2}}, + {L"\U0000200d\U00000308\U00000903", {8205}, {3}}, + {L"\U0000200d\U00000904", {8205, 2308}, {1, 2}}, + {L"\U0000200d\U00000308\U00000904", {8205, 2308}, {2, 3}}, + {L"\U0000200d\U00000d4e", {8205, 3406}, {1, 2}}, + {L"\U0000200d\U00000308\U00000d4e", {8205, 3406}, {2, 3}}, + {L"\U0000200d\U00000915", {8205, 2325}, {1, 2}}, + {L"\U0000200d\U00000308\U00000915", {8205, 2325}, {2, 3}}, {L"\U0000200d\U0000231a", {8205, 8986}, {1, 2}}, {L"\U0000200d\U00000308\U0000231a", {8205, 8986}, {2, 3}}, {L"\U0000200d\U00000300", {8205}, {2}}, {L"\U0000200d\U00000308\U00000300", {8205}, {3}}, + {L"\U0000200d\U0000093c", {8205}, {2}}, + {L"\U0000200d\U00000308\U0000093c", {8205}, {3}}, + {L"\U0000200d\U0000094d", {8205}, {2}}, + {L"\U0000200d\U00000308\U0000094d", {8205}, {3}}, {L"\U0000200d\U0000200d", {8205}, {2}}, {L"\U0000200d\U00000308\U0000200d", {8205}, {3}}, {L"\U0000200d\U00000378", {8205, 888}, {1, 2}}, @@ -1251,8 +2396,8 @@ std::array, 602> data_utf16 = {{ {L"\U00000378\U00000308\U0001f1e6", {888, 127462}, {2, 4}}, {L"\U00000378\U00000600", {888, 1536}, {1, 2}}, {L"\U00000378\U00000308\U00000600", {888, 1536}, {2, 3}}, - {L"\U00000378\U00000903", {888}, {2}}, - {L"\U00000378\U00000308\U00000903", {888}, {3}}, + {L"\U00000378\U00000a03", {888}, {2}}, + {L"\U00000378\U00000308\U00000a03", {888}, {3}}, {L"\U00000378\U00001100", {888, 4352}, {1, 2}}, {L"\U00000378\U00000308\U00001100", {888, 4352}, {2, 3}}, {L"\U00000378\U00001160", {888, 4448}, {1, 2}}, @@ -1263,10 +2408,24 @@ std::array, 602> data_utf16 = {{ {L"\U00000378\U00000308\U0000ac00", {888, 44032}, {2, 3}}, {L"\U00000378\U0000ac01", {888, 44033}, {1, 2}}, {L"\U00000378\U00000308\U0000ac01", {888, 44033}, {2, 3}}, + {L"\U00000378\U00000900", {888}, {2}}, + {L"\U00000378\U00000308\U00000900", {888}, {3}}, + {L"\U00000378\U00000903", {888}, {2}}, + {L"\U00000378\U00000308\U00000903", {888}, {3}}, + {L"\U00000378\U00000904", {888, 2308}, {1, 2}}, + {L"\U00000378\U00000308\U00000904", {888, 2308}, {2, 3}}, + {L"\U00000378\U00000d4e", {888, 3406}, {1, 2}}, + {L"\U00000378\U00000308\U00000d4e", {888, 3406}, {2, 3}}, + {L"\U00000378\U00000915", {888, 2325}, {1, 2}}, + {L"\U00000378\U00000308\U00000915", {888, 2325}, {2, 3}}, {L"\U00000378\U0000231a", {888, 8986}, {1, 2}}, {L"\U00000378\U00000308\U0000231a", {888, 8986}, {2, 3}}, {L"\U00000378\U00000300", {888}, {2}}, {L"\U00000378\U00000308\U00000300", {888}, {3}}, + {L"\U00000378\U0000093c", {888}, {2}}, + {L"\U00000378\U00000308\U0000093c", {888}, {3}}, + {L"\U00000378\U0000094d", {888}, {2}}, + {L"\U00000378\U00000308\U0000094d", {888}, {3}}, {L"\U00000378\U0000200d", {888}, {2}}, {L"\U00000378\U00000308\U0000200d", {888}, {3}}, {L"\U00000378\U00000378", {888, 888}, {1, 2}}, @@ -1294,14 +2453,25 @@ std::array, 602> data_utf16 = {{ {L"\U0001f6d1\U0000200d\U0001f6d1", {128721}, {5}}, {L"\U00000061\U0000200d\U0001f6d1", {97, 128721}, {2, 4}}, {L"\U00002701\U0000200d\U00002701", {9985}, {3}}, - {L"\U00000061\U0000200d\U00002701", {97, 9985}, {2, 3}}}}; + {L"\U00000061\U0000200d\U00002701", {97, 9985}, {2, 3}}, + {L"\U00000915\U00000924", {2325, 2340}, {1, 2}}, + {L"\U00000915\U0000094d\U00000924", {2325}, {3}}, + {L"\U00000915\U0000094d\U0000094d\U00000924", {2325}, {4}}, + {L"\U00000915\U0000094d\U0000200d\U00000924", {2325}, {4}}, + {L"\U00000915\U0000093c\U0000200d\U0000094d\U00000924", {2325}, {5}}, + {L"\U00000915\U0000093c\U0000094d\U0000200d\U00000924", {2325}, {5}}, + {L"\U00000915\U0000094d\U00000924\U0000094d\U0000092f", {2325}, {5}}, + {L"\U00000915\U0000094d\U00000061", {2325, 97}, {2, 3}}, + {L"\U00000061\U0000094d\U00000924", {97, 2340}, {2, 3}}, + {L"\U0000003f\U0000094d\U00000924", {63, 2340}, {2, 3}}, + {L"\U00000915\U0000094d\U0000094d\U00000924", {2325}, {4}}}}; /// The data for UTF-8. /// /// Note that most of the data for the UTF-16 and UTF-32 are identical. However /// since the size of the code units differ the breaks can contain different /// values. -std::array, 602> data_utf32 = {{ +std::array, 1187> data_utf32 = {{ {L"\U00000020\U00000020", {32, 32}, {1, 2}}, {L"\U00000020\U00000308\U00000020", {32, 32}, {2, 3}}, {L"\U00000020\U0000000d", {32, 13}, {1, 2}}, @@ -1316,8 +2486,8 @@ std::array, 602> data_utf32 = {{ {L"\U00000020\U00000308\U0001f1e6", {32, 127462}, {2, 3}}, {L"\U00000020\U00000600", {32, 1536}, {1, 2}}, {L"\U00000020\U00000308\U00000600", {32, 1536}, {2, 3}}, - {L"\U00000020\U00000903", {32}, {2}}, - {L"\U00000020\U00000308\U00000903", {32}, {3}}, + {L"\U00000020\U00000a03", {32}, {2}}, + {L"\U00000020\U00000308\U00000a03", {32}, {3}}, {L"\U00000020\U00001100", {32, 4352}, {1, 2}}, {L"\U00000020\U00000308\U00001100", {32, 4352}, {2, 3}}, {L"\U00000020\U00001160", {32, 4448}, {1, 2}}, @@ -1328,10 +2498,24 @@ std::array, 602> data_utf32 = {{ {L"\U00000020\U00000308\U0000ac00", {32, 44032}, {2, 3}}, {L"\U00000020\U0000ac01", {32, 44033}, {1, 2}}, {L"\U00000020\U00000308\U0000ac01", {32, 44033}, {2, 3}}, + {L"\U00000020\U00000900", {32}, {2}}, + {L"\U00000020\U00000308\U00000900", {32}, {3}}, + {L"\U00000020\U00000903", {32}, {2}}, + {L"\U00000020\U00000308\U00000903", {32}, {3}}, + {L"\U00000020\U00000904", {32, 2308}, {1, 2}}, + {L"\U00000020\U00000308\U00000904", {32, 2308}, {2, 3}}, + {L"\U00000020\U00000d4e", {32, 3406}, {1, 2}}, + {L"\U00000020\U00000308\U00000d4e", {32, 3406}, {2, 3}}, + {L"\U00000020\U00000915", {32, 2325}, {1, 2}}, + {L"\U00000020\U00000308\U00000915", {32, 2325}, {2, 3}}, {L"\U00000020\U0000231a", {32, 8986}, {1, 2}}, {L"\U00000020\U00000308\U0000231a", {32, 8986}, {2, 3}}, {L"\U00000020\U00000300", {32}, {2}}, {L"\U00000020\U00000308\U00000300", {32}, {3}}, + {L"\U00000020\U0000093c", {32}, {2}}, + {L"\U00000020\U00000308\U0000093c", {32}, {3}}, + {L"\U00000020\U0000094d", {32}, {2}}, + {L"\U00000020\U00000308\U0000094d", {32}, {3}}, {L"\U00000020\U0000200d", {32}, {2}}, {L"\U00000020\U00000308\U0000200d", {32}, {3}}, {L"\U00000020\U00000378", {32, 888}, {1, 2}}, @@ -1350,8 +2534,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000000d\U00000308\U0001f1e6", {13, 776, 127462}, {1, 2, 3}}, {L"\U0000000d\U00000600", {13, 1536}, {1, 2}}, {L"\U0000000d\U00000308\U00000600", {13, 776, 1536}, {1, 2, 3}}, - {L"\U0000000d\U00000903", {13, 2307}, {1, 2}}, - {L"\U0000000d\U00000308\U00000903", {13, 776}, {1, 3}}, + {L"\U0000000d\U00000a03", {13, 2563}, {1, 2}}, + {L"\U0000000d\U00000308\U00000a03", {13, 776}, {1, 3}}, {L"\U0000000d\U00001100", {13, 4352}, {1, 2}}, {L"\U0000000d\U00000308\U00001100", {13, 776, 4352}, {1, 2, 3}}, {L"\U0000000d\U00001160", {13, 4448}, {1, 2}}, @@ -1362,10 +2546,24 @@ std::array, 602> data_utf32 = {{ {L"\U0000000d\U00000308\U0000ac00", {13, 776, 44032}, {1, 2, 3}}, {L"\U0000000d\U0000ac01", {13, 44033}, {1, 2}}, {L"\U0000000d\U00000308\U0000ac01", {13, 776, 44033}, {1, 2, 3}}, + {L"\U0000000d\U00000900", {13, 2304}, {1, 2}}, + {L"\U0000000d\U00000308\U00000900", {13, 776}, {1, 3}}, + {L"\U0000000d\U00000903", {13, 2307}, {1, 2}}, + {L"\U0000000d\U00000308\U00000903", {13, 776}, {1, 3}}, + {L"\U0000000d\U00000904", {13, 2308}, {1, 2}}, + {L"\U0000000d\U00000308\U00000904", {13, 776, 2308}, {1, 2, 3}}, + {L"\U0000000d\U00000d4e", {13, 3406}, {1, 2}}, + {L"\U0000000d\U00000308\U00000d4e", {13, 776, 3406}, {1, 2, 3}}, + {L"\U0000000d\U00000915", {13, 2325}, {1, 2}}, + {L"\U0000000d\U00000308\U00000915", {13, 776, 2325}, {1, 2, 3}}, {L"\U0000000d\U0000231a", {13, 8986}, {1, 2}}, {L"\U0000000d\U00000308\U0000231a", {13, 776, 8986}, {1, 2, 3}}, {L"\U0000000d\U00000300", {13, 768}, {1, 2}}, {L"\U0000000d\U00000308\U00000300", {13, 776}, {1, 3}}, + {L"\U0000000d\U0000093c", {13, 2364}, {1, 2}}, + {L"\U0000000d\U00000308\U0000093c", {13, 776}, {1, 3}}, + {L"\U0000000d\U0000094d", {13, 2381}, {1, 2}}, + {L"\U0000000d\U00000308\U0000094d", {13, 776}, {1, 3}}, {L"\U0000000d\U0000200d", {13, 8205}, {1, 2}}, {L"\U0000000d\U00000308\U0000200d", {13, 776}, {1, 3}}, {L"\U0000000d\U00000378", {13, 888}, {1, 2}}, @@ -1384,8 +2582,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000000a\U00000308\U0001f1e6", {10, 776, 127462}, {1, 2, 3}}, {L"\U0000000a\U00000600", {10, 1536}, {1, 2}}, {L"\U0000000a\U00000308\U00000600", {10, 776, 1536}, {1, 2, 3}}, - {L"\U0000000a\U00000903", {10, 2307}, {1, 2}}, - {L"\U0000000a\U00000308\U00000903", {10, 776}, {1, 3}}, + {L"\U0000000a\U00000a03", {10, 2563}, {1, 2}}, + {L"\U0000000a\U00000308\U00000a03", {10, 776}, {1, 3}}, {L"\U0000000a\U00001100", {10, 4352}, {1, 2}}, {L"\U0000000a\U00000308\U00001100", {10, 776, 4352}, {1, 2, 3}}, {L"\U0000000a\U00001160", {10, 4448}, {1, 2}}, @@ -1396,10 +2594,24 @@ std::array, 602> data_utf32 = {{ {L"\U0000000a\U00000308\U0000ac00", {10, 776, 44032}, {1, 2, 3}}, {L"\U0000000a\U0000ac01", {10, 44033}, {1, 2}}, {L"\U0000000a\U00000308\U0000ac01", {10, 776, 44033}, {1, 2, 3}}, + {L"\U0000000a\U00000900", {10, 2304}, {1, 2}}, + {L"\U0000000a\U00000308\U00000900", {10, 776}, {1, 3}}, + {L"\U0000000a\U00000903", {10, 2307}, {1, 2}}, + {L"\U0000000a\U00000308\U00000903", {10, 776}, {1, 3}}, + {L"\U0000000a\U00000904", {10, 2308}, {1, 2}}, + {L"\U0000000a\U00000308\U00000904", {10, 776, 2308}, {1, 2, 3}}, + {L"\U0000000a\U00000d4e", {10, 3406}, {1, 2}}, + {L"\U0000000a\U00000308\U00000d4e", {10, 776, 3406}, {1, 2, 3}}, + {L"\U0000000a\U00000915", {10, 2325}, {1, 2}}, + {L"\U0000000a\U00000308\U00000915", {10, 776, 2325}, {1, 2, 3}}, {L"\U0000000a\U0000231a", {10, 8986}, {1, 2}}, {L"\U0000000a\U00000308\U0000231a", {10, 776, 8986}, {1, 2, 3}}, {L"\U0000000a\U00000300", {10, 768}, {1, 2}}, {L"\U0000000a\U00000308\U00000300", {10, 776}, {1, 3}}, + {L"\U0000000a\U0000093c", {10, 2364}, {1, 2}}, + {L"\U0000000a\U00000308\U0000093c", {10, 776}, {1, 3}}, + {L"\U0000000a\U0000094d", {10, 2381}, {1, 2}}, + {L"\U0000000a\U00000308\U0000094d", {10, 776}, {1, 3}}, {L"\U0000000a\U0000200d", {10, 8205}, {1, 2}}, {L"\U0000000a\U00000308\U0000200d", {10, 776}, {1, 3}}, {L"\U0000000a\U00000378", {10, 888}, {1, 2}}, @@ -1418,8 +2630,8 @@ std::array, 602> data_utf32 = {{ {L"\U00000001\U00000308\U0001f1e6", {1, 776, 127462}, {1, 2, 3}}, {L"\U00000001\U00000600", {1, 1536}, {1, 2}}, {L"\U00000001\U00000308\U00000600", {1, 776, 1536}, {1, 2, 3}}, - {L"\U00000001\U00000903", {1, 2307}, {1, 2}}, - {L"\U00000001\U00000308\U00000903", {1, 776}, {1, 3}}, + {L"\U00000001\U00000a03", {1, 2563}, {1, 2}}, + {L"\U00000001\U00000308\U00000a03", {1, 776}, {1, 3}}, {L"\U00000001\U00001100", {1, 4352}, {1, 2}}, {L"\U00000001\U00000308\U00001100", {1, 776, 4352}, {1, 2, 3}}, {L"\U00000001\U00001160", {1, 4448}, {1, 2}}, @@ -1430,10 +2642,24 @@ std::array, 602> data_utf32 = {{ {L"\U00000001\U00000308\U0000ac00", {1, 776, 44032}, {1, 2, 3}}, {L"\U00000001\U0000ac01", {1, 44033}, {1, 2}}, {L"\U00000001\U00000308\U0000ac01", {1, 776, 44033}, {1, 2, 3}}, + {L"\U00000001\U00000900", {1, 2304}, {1, 2}}, + {L"\U00000001\U00000308\U00000900", {1, 776}, {1, 3}}, + {L"\U00000001\U00000903", {1, 2307}, {1, 2}}, + {L"\U00000001\U00000308\U00000903", {1, 776}, {1, 3}}, + {L"\U00000001\U00000904", {1, 2308}, {1, 2}}, + {L"\U00000001\U00000308\U00000904", {1, 776, 2308}, {1, 2, 3}}, + {L"\U00000001\U00000d4e", {1, 3406}, {1, 2}}, + {L"\U00000001\U00000308\U00000d4e", {1, 776, 3406}, {1, 2, 3}}, + {L"\U00000001\U00000915", {1, 2325}, {1, 2}}, + {L"\U00000001\U00000308\U00000915", {1, 776, 2325}, {1, 2, 3}}, {L"\U00000001\U0000231a", {1, 8986}, {1, 2}}, {L"\U00000001\U00000308\U0000231a", {1, 776, 8986}, {1, 2, 3}}, {L"\U00000001\U00000300", {1, 768}, {1, 2}}, {L"\U00000001\U00000308\U00000300", {1, 776}, {1, 3}}, + {L"\U00000001\U0000093c", {1, 2364}, {1, 2}}, + {L"\U00000001\U00000308\U0000093c", {1, 776}, {1, 3}}, + {L"\U00000001\U0000094d", {1, 2381}, {1, 2}}, + {L"\U00000001\U00000308\U0000094d", {1, 776}, {1, 3}}, {L"\U00000001\U0000200d", {1, 8205}, {1, 2}}, {L"\U00000001\U00000308\U0000200d", {1, 776}, {1, 3}}, {L"\U00000001\U00000378", {1, 888}, {1, 2}}, @@ -1452,8 +2678,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000034f\U00000308\U0001f1e6", {847, 127462}, {2, 3}}, {L"\U0000034f\U00000600", {847, 1536}, {1, 2}}, {L"\U0000034f\U00000308\U00000600", {847, 1536}, {2, 3}}, - {L"\U0000034f\U00000903", {847}, {2}}, - {L"\U0000034f\U00000308\U00000903", {847}, {3}}, + {L"\U0000034f\U00000a03", {847}, {2}}, + {L"\U0000034f\U00000308\U00000a03", {847}, {3}}, {L"\U0000034f\U00001100", {847, 4352}, {1, 2}}, {L"\U0000034f\U00000308\U00001100", {847, 4352}, {2, 3}}, {L"\U0000034f\U00001160", {847, 4448}, {1, 2}}, @@ -1464,10 +2690,24 @@ std::array, 602> data_utf32 = {{ {L"\U0000034f\U00000308\U0000ac00", {847, 44032}, {2, 3}}, {L"\U0000034f\U0000ac01", {847, 44033}, {1, 2}}, {L"\U0000034f\U00000308\U0000ac01", {847, 44033}, {2, 3}}, + {L"\U0000034f\U00000900", {847}, {2}}, + {L"\U0000034f\U00000308\U00000900", {847}, {3}}, + {L"\U0000034f\U00000903", {847}, {2}}, + {L"\U0000034f\U00000308\U00000903", {847}, {3}}, + {L"\U0000034f\U00000904", {847, 2308}, {1, 2}}, + {L"\U0000034f\U00000308\U00000904", {847, 2308}, {2, 3}}, + {L"\U0000034f\U00000d4e", {847, 3406}, {1, 2}}, + {L"\U0000034f\U00000308\U00000d4e", {847, 3406}, {2, 3}}, + {L"\U0000034f\U00000915", {847, 2325}, {1, 2}}, + {L"\U0000034f\U00000308\U00000915", {847, 2325}, {2, 3}}, {L"\U0000034f\U0000231a", {847, 8986}, {1, 2}}, {L"\U0000034f\U00000308\U0000231a", {847, 8986}, {2, 3}}, {L"\U0000034f\U00000300", {847}, {2}}, {L"\U0000034f\U00000308\U00000300", {847}, {3}}, + {L"\U0000034f\U0000093c", {847}, {2}}, + {L"\U0000034f\U00000308\U0000093c", {847}, {3}}, + {L"\U0000034f\U0000094d", {847}, {2}}, + {L"\U0000034f\U00000308\U0000094d", {847}, {3}}, {L"\U0000034f\U0000200d", {847}, {2}}, {L"\U0000034f\U00000308\U0000200d", {847}, {3}}, {L"\U0000034f\U00000378", {847, 888}, {1, 2}}, @@ -1486,8 +2726,8 @@ std::array, 602> data_utf32 = {{ {L"\U0001f1e6\U00000308\U0001f1e6", {127462, 127462}, {2, 3}}, {L"\U0001f1e6\U00000600", {127462, 1536}, {1, 2}}, {L"\U0001f1e6\U00000308\U00000600", {127462, 1536}, {2, 3}}, - {L"\U0001f1e6\U00000903", {127462}, {2}}, - {L"\U0001f1e6\U00000308\U00000903", {127462}, {3}}, + {L"\U0001f1e6\U00000a03", {127462}, {2}}, + {L"\U0001f1e6\U00000308\U00000a03", {127462}, {3}}, {L"\U0001f1e6\U00001100", {127462, 4352}, {1, 2}}, {L"\U0001f1e6\U00000308\U00001100", {127462, 4352}, {2, 3}}, {L"\U0001f1e6\U00001160", {127462, 4448}, {1, 2}}, @@ -1498,10 +2738,24 @@ std::array, 602> data_utf32 = {{ {L"\U0001f1e6\U00000308\U0000ac00", {127462, 44032}, {2, 3}}, {L"\U0001f1e6\U0000ac01", {127462, 44033}, {1, 2}}, {L"\U0001f1e6\U00000308\U0000ac01", {127462, 44033}, {2, 3}}, + {L"\U0001f1e6\U00000900", {127462}, {2}}, + {L"\U0001f1e6\U00000308\U00000900", {127462}, {3}}, + {L"\U0001f1e6\U00000903", {127462}, {2}}, + {L"\U0001f1e6\U00000308\U00000903", {127462}, {3}}, + {L"\U0001f1e6\U00000904", {127462, 2308}, {1, 2}}, + {L"\U0001f1e6\U00000308\U00000904", {127462, 2308}, {2, 3}}, + {L"\U0001f1e6\U00000d4e", {127462, 3406}, {1, 2}}, + {L"\U0001f1e6\U00000308\U00000d4e", {127462, 3406}, {2, 3}}, + {L"\U0001f1e6\U00000915", {127462, 2325}, {1, 2}}, + {L"\U0001f1e6\U00000308\U00000915", {127462, 2325}, {2, 3}}, {L"\U0001f1e6\U0000231a", {127462, 8986}, {1, 2}}, {L"\U0001f1e6\U00000308\U0000231a", {127462, 8986}, {2, 3}}, {L"\U0001f1e6\U00000300", {127462}, {2}}, {L"\U0001f1e6\U00000308\U00000300", {127462}, {3}}, + {L"\U0001f1e6\U0000093c", {127462}, {2}}, + {L"\U0001f1e6\U00000308\U0000093c", {127462}, {3}}, + {L"\U0001f1e6\U0000094d", {127462}, {2}}, + {L"\U0001f1e6\U00000308\U0000094d", {127462}, {3}}, {L"\U0001f1e6\U0000200d", {127462}, {2}}, {L"\U0001f1e6\U00000308\U0000200d", {127462}, {3}}, {L"\U0001f1e6\U00000378", {127462, 888}, {1, 2}}, @@ -1520,8 +2774,8 @@ std::array, 602> data_utf32 = {{ {L"\U00000600\U00000308\U0001f1e6", {1536, 127462}, {2, 3}}, {L"\U00000600\U00000600", {1536}, {2}}, {L"\U00000600\U00000308\U00000600", {1536, 1536}, {2, 3}}, - {L"\U00000600\U00000903", {1536}, {2}}, - {L"\U00000600\U00000308\U00000903", {1536}, {3}}, + {L"\U00000600\U00000a03", {1536}, {2}}, + {L"\U00000600\U00000308\U00000a03", {1536}, {3}}, {L"\U00000600\U00001100", {1536}, {2}}, {L"\U00000600\U00000308\U00001100", {1536, 4352}, {2, 3}}, {L"\U00000600\U00001160", {1536}, {2}}, @@ -1532,48 +2786,76 @@ std::array, 602> data_utf32 = {{ {L"\U00000600\U00000308\U0000ac00", {1536, 44032}, {2, 3}}, {L"\U00000600\U0000ac01", {1536}, {2}}, {L"\U00000600\U00000308\U0000ac01", {1536, 44033}, {2, 3}}, + {L"\U00000600\U00000900", {1536}, {2}}, + {L"\U00000600\U00000308\U00000900", {1536}, {3}}, + {L"\U00000600\U00000903", {1536}, {2}}, + {L"\U00000600\U00000308\U00000903", {1536}, {3}}, + {L"\U00000600\U00000904", {1536}, {2}}, + {L"\U00000600\U00000308\U00000904", {1536, 2308}, {2, 3}}, + {L"\U00000600\U00000d4e", {1536}, {2}}, + {L"\U00000600\U00000308\U00000d4e", {1536, 3406}, {2, 3}}, + {L"\U00000600\U00000915", {1536}, {2}}, + {L"\U00000600\U00000308\U00000915", {1536, 2325}, {2, 3}}, {L"\U00000600\U0000231a", {1536}, {2}}, {L"\U00000600\U00000308\U0000231a", {1536, 8986}, {2, 3}}, {L"\U00000600\U00000300", {1536}, {2}}, {L"\U00000600\U00000308\U00000300", {1536}, {3}}, + {L"\U00000600\U0000093c", {1536}, {2}}, + {L"\U00000600\U00000308\U0000093c", {1536}, {3}}, + {L"\U00000600\U0000094d", {1536}, {2}}, + {L"\U00000600\U00000308\U0000094d", {1536}, {3}}, {L"\U00000600\U0000200d", {1536}, {2}}, {L"\U00000600\U00000308\U0000200d", {1536}, {3}}, {L"\U00000600\U00000378", {1536}, {2}}, {L"\U00000600\U00000308\U00000378", {1536, 888}, {2, 3}}, - {L"\U00000903\U00000020", {2307, 32}, {1, 2}}, - {L"\U00000903\U00000308\U00000020", {2307, 32}, {2, 3}}, - {L"\U00000903\U0000000d", {2307, 13}, {1, 2}}, - {L"\U00000903\U00000308\U0000000d", {2307, 13}, {2, 3}}, - {L"\U00000903\U0000000a", {2307, 10}, {1, 2}}, - {L"\U00000903\U00000308\U0000000a", {2307, 10}, {2, 3}}, - {L"\U00000903\U00000001", {2307, 1}, {1, 2}}, - {L"\U00000903\U00000308\U00000001", {2307, 1}, {2, 3}}, - {L"\U00000903\U0000034f", {2307}, {2}}, - {L"\U00000903\U00000308\U0000034f", {2307}, {3}}, - {L"\U00000903\U0001f1e6", {2307, 127462}, {1, 2}}, - {L"\U00000903\U00000308\U0001f1e6", {2307, 127462}, {2, 3}}, - {L"\U00000903\U00000600", {2307, 1536}, {1, 2}}, - {L"\U00000903\U00000308\U00000600", {2307, 1536}, {2, 3}}, - {L"\U00000903\U00000903", {2307}, {2}}, - {L"\U00000903\U00000308\U00000903", {2307}, {3}}, - {L"\U00000903\U00001100", {2307, 4352}, {1, 2}}, - {L"\U00000903\U00000308\U00001100", {2307, 4352}, {2, 3}}, - {L"\U00000903\U00001160", {2307, 4448}, {1, 2}}, - {L"\U00000903\U00000308\U00001160", {2307, 4448}, {2, 3}}, - {L"\U00000903\U000011a8", {2307, 4520}, {1, 2}}, - {L"\U00000903\U00000308\U000011a8", {2307, 4520}, {2, 3}}, - {L"\U00000903\U0000ac00", {2307, 44032}, {1, 2}}, - {L"\U00000903\U00000308\U0000ac00", {2307, 44032}, {2, 3}}, - {L"\U00000903\U0000ac01", {2307, 44033}, {1, 2}}, - {L"\U00000903\U00000308\U0000ac01", {2307, 44033}, {2, 3}}, - {L"\U00000903\U0000231a", {2307, 8986}, {1, 2}}, - {L"\U00000903\U00000308\U0000231a", {2307, 8986}, {2, 3}}, - {L"\U00000903\U00000300", {2307}, {2}}, - {L"\U00000903\U00000308\U00000300", {2307}, {3}}, - {L"\U00000903\U0000200d", {2307}, {2}}, - {L"\U00000903\U00000308\U0000200d", {2307}, {3}}, - {L"\U00000903\U00000378", {2307, 888}, {1, 2}}, - {L"\U00000903\U00000308\U00000378", {2307, 888}, {2, 3}}, + {L"\U00000a03\U00000020", {2563, 32}, {1, 2}}, + {L"\U00000a03\U00000308\U00000020", {2563, 32}, {2, 3}}, + {L"\U00000a03\U0000000d", {2563, 13}, {1, 2}}, + {L"\U00000a03\U00000308\U0000000d", {2563, 13}, {2, 3}}, + {L"\U00000a03\U0000000a", {2563, 10}, {1, 2}}, + {L"\U00000a03\U00000308\U0000000a", {2563, 10}, {2, 3}}, + {L"\U00000a03\U00000001", {2563, 1}, {1, 2}}, + {L"\U00000a03\U00000308\U00000001", {2563, 1}, {2, 3}}, + {L"\U00000a03\U0000034f", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000034f", {2563}, {3}}, + {L"\U00000a03\U0001f1e6", {2563, 127462}, {1, 2}}, + {L"\U00000a03\U00000308\U0001f1e6", {2563, 127462}, {2, 3}}, + {L"\U00000a03\U00000600", {2563, 1536}, {1, 2}}, + {L"\U00000a03\U00000308\U00000600", {2563, 1536}, {2, 3}}, + {L"\U00000a03\U00000a03", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000a03", {2563}, {3}}, + {L"\U00000a03\U00001100", {2563, 4352}, {1, 2}}, + {L"\U00000a03\U00000308\U00001100", {2563, 4352}, {2, 3}}, + {L"\U00000a03\U00001160", {2563, 4448}, {1, 2}}, + {L"\U00000a03\U00000308\U00001160", {2563, 4448}, {2, 3}}, + {L"\U00000a03\U000011a8", {2563, 4520}, {1, 2}}, + {L"\U00000a03\U00000308\U000011a8", {2563, 4520}, {2, 3}}, + {L"\U00000a03\U0000ac00", {2563, 44032}, {1, 2}}, + {L"\U00000a03\U00000308\U0000ac00", {2563, 44032}, {2, 3}}, + {L"\U00000a03\U0000ac01", {2563, 44033}, {1, 2}}, + {L"\U00000a03\U00000308\U0000ac01", {2563, 44033}, {2, 3}}, + {L"\U00000a03\U00000900", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000900", {2563}, {3}}, + {L"\U00000a03\U00000903", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000903", {2563}, {3}}, + {L"\U00000a03\U00000904", {2563, 2308}, {1, 2}}, + {L"\U00000a03\U00000308\U00000904", {2563, 2308}, {2, 3}}, + {L"\U00000a03\U00000d4e", {2563, 3406}, {1, 2}}, + {L"\U00000a03\U00000308\U00000d4e", {2563, 3406}, {2, 3}}, + {L"\U00000a03\U00000915", {2563, 2325}, {1, 2}}, + {L"\U00000a03\U00000308\U00000915", {2563, 2325}, {2, 3}}, + {L"\U00000a03\U0000231a", {2563, 8986}, {1, 2}}, + {L"\U00000a03\U00000308\U0000231a", {2563, 8986}, {2, 3}}, + {L"\U00000a03\U00000300", {2563}, {2}}, + {L"\U00000a03\U00000308\U00000300", {2563}, {3}}, + {L"\U00000a03\U0000093c", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000093c", {2563}, {3}}, + {L"\U00000a03\U0000094d", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000094d", {2563}, {3}}, + {L"\U00000a03\U0000200d", {2563}, {2}}, + {L"\U00000a03\U00000308\U0000200d", {2563}, {3}}, + {L"\U00000a03\U00000378", {2563, 888}, {1, 2}}, + {L"\U00000a03\U00000308\U00000378", {2563, 888}, {2, 3}}, {L"\U00001100\U00000020", {4352, 32}, {1, 2}}, {L"\U00001100\U00000308\U00000020", {4352, 32}, {2, 3}}, {L"\U00001100\U0000000d", {4352, 13}, {1, 2}}, @@ -1588,8 +2870,8 @@ std::array, 602> data_utf32 = {{ {L"\U00001100\U00000308\U0001f1e6", {4352, 127462}, {2, 3}}, {L"\U00001100\U00000600", {4352, 1536}, {1, 2}}, {L"\U00001100\U00000308\U00000600", {4352, 1536}, {2, 3}}, - {L"\U00001100\U00000903", {4352}, {2}}, - {L"\U00001100\U00000308\U00000903", {4352}, {3}}, + {L"\U00001100\U00000a03", {4352}, {2}}, + {L"\U00001100\U00000308\U00000a03", {4352}, {3}}, {L"\U00001100\U00001100", {4352}, {2}}, {L"\U00001100\U00000308\U00001100", {4352, 4352}, {2, 3}}, {L"\U00001100\U00001160", {4352}, {2}}, @@ -1600,10 +2882,24 @@ std::array, 602> data_utf32 = {{ {L"\U00001100\U00000308\U0000ac00", {4352, 44032}, {2, 3}}, {L"\U00001100\U0000ac01", {4352}, {2}}, {L"\U00001100\U00000308\U0000ac01", {4352, 44033}, {2, 3}}, + {L"\U00001100\U00000900", {4352}, {2}}, + {L"\U00001100\U00000308\U00000900", {4352}, {3}}, + {L"\U00001100\U00000903", {4352}, {2}}, + {L"\U00001100\U00000308\U00000903", {4352}, {3}}, + {L"\U00001100\U00000904", {4352, 2308}, {1, 2}}, + {L"\U00001100\U00000308\U00000904", {4352, 2308}, {2, 3}}, + {L"\U00001100\U00000d4e", {4352, 3406}, {1, 2}}, + {L"\U00001100\U00000308\U00000d4e", {4352, 3406}, {2, 3}}, + {L"\U00001100\U00000915", {4352, 2325}, {1, 2}}, + {L"\U00001100\U00000308\U00000915", {4352, 2325}, {2, 3}}, {L"\U00001100\U0000231a", {4352, 8986}, {1, 2}}, {L"\U00001100\U00000308\U0000231a", {4352, 8986}, {2, 3}}, {L"\U00001100\U00000300", {4352}, {2}}, {L"\U00001100\U00000308\U00000300", {4352}, {3}}, + {L"\U00001100\U0000093c", {4352}, {2}}, + {L"\U00001100\U00000308\U0000093c", {4352}, {3}}, + {L"\U00001100\U0000094d", {4352}, {2}}, + {L"\U00001100\U00000308\U0000094d", {4352}, {3}}, {L"\U00001100\U0000200d", {4352}, {2}}, {L"\U00001100\U00000308\U0000200d", {4352}, {3}}, {L"\U00001100\U00000378", {4352, 888}, {1, 2}}, @@ -1622,8 +2918,8 @@ std::array, 602> data_utf32 = {{ {L"\U00001160\U00000308\U0001f1e6", {4448, 127462}, {2, 3}}, {L"\U00001160\U00000600", {4448, 1536}, {1, 2}}, {L"\U00001160\U00000308\U00000600", {4448, 1536}, {2, 3}}, - {L"\U00001160\U00000903", {4448}, {2}}, - {L"\U00001160\U00000308\U00000903", {4448}, {3}}, + {L"\U00001160\U00000a03", {4448}, {2}}, + {L"\U00001160\U00000308\U00000a03", {4448}, {3}}, {L"\U00001160\U00001100", {4448, 4352}, {1, 2}}, {L"\U00001160\U00000308\U00001100", {4448, 4352}, {2, 3}}, {L"\U00001160\U00001160", {4448}, {2}}, @@ -1634,10 +2930,24 @@ std::array, 602> data_utf32 = {{ {L"\U00001160\U00000308\U0000ac00", {4448, 44032}, {2, 3}}, {L"\U00001160\U0000ac01", {4448, 44033}, {1, 2}}, {L"\U00001160\U00000308\U0000ac01", {4448, 44033}, {2, 3}}, + {L"\U00001160\U00000900", {4448}, {2}}, + {L"\U00001160\U00000308\U00000900", {4448}, {3}}, + {L"\U00001160\U00000903", {4448}, {2}}, + {L"\U00001160\U00000308\U00000903", {4448}, {3}}, + {L"\U00001160\U00000904", {4448, 2308}, {1, 2}}, + {L"\U00001160\U00000308\U00000904", {4448, 2308}, {2, 3}}, + {L"\U00001160\U00000d4e", {4448, 3406}, {1, 2}}, + {L"\U00001160\U00000308\U00000d4e", {4448, 3406}, {2, 3}}, + {L"\U00001160\U00000915", {4448, 2325}, {1, 2}}, + {L"\U00001160\U00000308\U00000915", {4448, 2325}, {2, 3}}, {L"\U00001160\U0000231a", {4448, 8986}, {1, 2}}, {L"\U00001160\U00000308\U0000231a", {4448, 8986}, {2, 3}}, {L"\U00001160\U00000300", {4448}, {2}}, {L"\U00001160\U00000308\U00000300", {4448}, {3}}, + {L"\U00001160\U0000093c", {4448}, {2}}, + {L"\U00001160\U00000308\U0000093c", {4448}, {3}}, + {L"\U00001160\U0000094d", {4448}, {2}}, + {L"\U00001160\U00000308\U0000094d", {4448}, {3}}, {L"\U00001160\U0000200d", {4448}, {2}}, {L"\U00001160\U00000308\U0000200d", {4448}, {3}}, {L"\U00001160\U00000378", {4448, 888}, {1, 2}}, @@ -1656,8 +2966,8 @@ std::array, 602> data_utf32 = {{ {L"\U000011a8\U00000308\U0001f1e6", {4520, 127462}, {2, 3}}, {L"\U000011a8\U00000600", {4520, 1536}, {1, 2}}, {L"\U000011a8\U00000308\U00000600", {4520, 1536}, {2, 3}}, - {L"\U000011a8\U00000903", {4520}, {2}}, - {L"\U000011a8\U00000308\U00000903", {4520}, {3}}, + {L"\U000011a8\U00000a03", {4520}, {2}}, + {L"\U000011a8\U00000308\U00000a03", {4520}, {3}}, {L"\U000011a8\U00001100", {4520, 4352}, {1, 2}}, {L"\U000011a8\U00000308\U00001100", {4520, 4352}, {2, 3}}, {L"\U000011a8\U00001160", {4520, 4448}, {1, 2}}, @@ -1668,10 +2978,24 @@ std::array, 602> data_utf32 = {{ {L"\U000011a8\U00000308\U0000ac00", {4520, 44032}, {2, 3}}, {L"\U000011a8\U0000ac01", {4520, 44033}, {1, 2}}, {L"\U000011a8\U00000308\U0000ac01", {4520, 44033}, {2, 3}}, + {L"\U000011a8\U00000900", {4520}, {2}}, + {L"\U000011a8\U00000308\U00000900", {4520}, {3}}, + {L"\U000011a8\U00000903", {4520}, {2}}, + {L"\U000011a8\U00000308\U00000903", {4520}, {3}}, + {L"\U000011a8\U00000904", {4520, 2308}, {1, 2}}, + {L"\U000011a8\U00000308\U00000904", {4520, 2308}, {2, 3}}, + {L"\U000011a8\U00000d4e", {4520, 3406}, {1, 2}}, + {L"\U000011a8\U00000308\U00000d4e", {4520, 3406}, {2, 3}}, + {L"\U000011a8\U00000915", {4520, 2325}, {1, 2}}, + {L"\U000011a8\U00000308\U00000915", {4520, 2325}, {2, 3}}, {L"\U000011a8\U0000231a", {4520, 8986}, {1, 2}}, {L"\U000011a8\U00000308\U0000231a", {4520, 8986}, {2, 3}}, {L"\U000011a8\U00000300", {4520}, {2}}, {L"\U000011a8\U00000308\U00000300", {4520}, {3}}, + {L"\U000011a8\U0000093c", {4520}, {2}}, + {L"\U000011a8\U00000308\U0000093c", {4520}, {3}}, + {L"\U000011a8\U0000094d", {4520}, {2}}, + {L"\U000011a8\U00000308\U0000094d", {4520}, {3}}, {L"\U000011a8\U0000200d", {4520}, {2}}, {L"\U000011a8\U00000308\U0000200d", {4520}, {3}}, {L"\U000011a8\U00000378", {4520, 888}, {1, 2}}, @@ -1690,8 +3014,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000ac00\U00000308\U0001f1e6", {44032, 127462}, {2, 3}}, {L"\U0000ac00\U00000600", {44032, 1536}, {1, 2}}, {L"\U0000ac00\U00000308\U00000600", {44032, 1536}, {2, 3}}, - {L"\U0000ac00\U00000903", {44032}, {2}}, - {L"\U0000ac00\U00000308\U00000903", {44032}, {3}}, + {L"\U0000ac00\U00000a03", {44032}, {2}}, + {L"\U0000ac00\U00000308\U00000a03", {44032}, {3}}, {L"\U0000ac00\U00001100", {44032, 4352}, {1, 2}}, {L"\U0000ac00\U00000308\U00001100", {44032, 4352}, {2, 3}}, {L"\U0000ac00\U00001160", {44032}, {2}}, @@ -1702,10 +3026,24 @@ std::array, 602> data_utf32 = {{ {L"\U0000ac00\U00000308\U0000ac00", {44032, 44032}, {2, 3}}, {L"\U0000ac00\U0000ac01", {44032, 44033}, {1, 2}}, {L"\U0000ac00\U00000308\U0000ac01", {44032, 44033}, {2, 3}}, + {L"\U0000ac00\U00000900", {44032}, {2}}, + {L"\U0000ac00\U00000308\U00000900", {44032}, {3}}, + {L"\U0000ac00\U00000903", {44032}, {2}}, + {L"\U0000ac00\U00000308\U00000903", {44032}, {3}}, + {L"\U0000ac00\U00000904", {44032, 2308}, {1, 2}}, + {L"\U0000ac00\U00000308\U00000904", {44032, 2308}, {2, 3}}, + {L"\U0000ac00\U00000d4e", {44032, 3406}, {1, 2}}, + {L"\U0000ac00\U00000308\U00000d4e", {44032, 3406}, {2, 3}}, + {L"\U0000ac00\U00000915", {44032, 2325}, {1, 2}}, + {L"\U0000ac00\U00000308\U00000915", {44032, 2325}, {2, 3}}, {L"\U0000ac00\U0000231a", {44032, 8986}, {1, 2}}, {L"\U0000ac00\U00000308\U0000231a", {44032, 8986}, {2, 3}}, {L"\U0000ac00\U00000300", {44032}, {2}}, {L"\U0000ac00\U00000308\U00000300", {44032}, {3}}, + {L"\U0000ac00\U0000093c", {44032}, {2}}, + {L"\U0000ac00\U00000308\U0000093c", {44032}, {3}}, + {L"\U0000ac00\U0000094d", {44032}, {2}}, + {L"\U0000ac00\U00000308\U0000094d", {44032}, {3}}, {L"\U0000ac00\U0000200d", {44032}, {2}}, {L"\U0000ac00\U00000308\U0000200d", {44032}, {3}}, {L"\U0000ac00\U00000378", {44032, 888}, {1, 2}}, @@ -1724,8 +3062,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000ac01\U00000308\U0001f1e6", {44033, 127462}, {2, 3}}, {L"\U0000ac01\U00000600", {44033, 1536}, {1, 2}}, {L"\U0000ac01\U00000308\U00000600", {44033, 1536}, {2, 3}}, - {L"\U0000ac01\U00000903", {44033}, {2}}, - {L"\U0000ac01\U00000308\U00000903", {44033}, {3}}, + {L"\U0000ac01\U00000a03", {44033}, {2}}, + {L"\U0000ac01\U00000308\U00000a03", {44033}, {3}}, {L"\U0000ac01\U00001100", {44033, 4352}, {1, 2}}, {L"\U0000ac01\U00000308\U00001100", {44033, 4352}, {2, 3}}, {L"\U0000ac01\U00001160", {44033, 4448}, {1, 2}}, @@ -1736,14 +3074,268 @@ std::array, 602> data_utf32 = {{ {L"\U0000ac01\U00000308\U0000ac00", {44033, 44032}, {2, 3}}, {L"\U0000ac01\U0000ac01", {44033, 44033}, {1, 2}}, {L"\U0000ac01\U00000308\U0000ac01", {44033, 44033}, {2, 3}}, + {L"\U0000ac01\U00000900", {44033}, {2}}, + {L"\U0000ac01\U00000308\U00000900", {44033}, {3}}, + {L"\U0000ac01\U00000903", {44033}, {2}}, + {L"\U0000ac01\U00000308\U00000903", {44033}, {3}}, + {L"\U0000ac01\U00000904", {44033, 2308}, {1, 2}}, + {L"\U0000ac01\U00000308\U00000904", {44033, 2308}, {2, 3}}, + {L"\U0000ac01\U00000d4e", {44033, 3406}, {1, 2}}, + {L"\U0000ac01\U00000308\U00000d4e", {44033, 3406}, {2, 3}}, + {L"\U0000ac01\U00000915", {44033, 2325}, {1, 2}}, + {L"\U0000ac01\U00000308\U00000915", {44033, 2325}, {2, 3}}, {L"\U0000ac01\U0000231a", {44033, 8986}, {1, 2}}, {L"\U0000ac01\U00000308\U0000231a", {44033, 8986}, {2, 3}}, {L"\U0000ac01\U00000300", {44033}, {2}}, {L"\U0000ac01\U00000308\U00000300", {44033}, {3}}, + {L"\U0000ac01\U0000093c", {44033}, {2}}, + {L"\U0000ac01\U00000308\U0000093c", {44033}, {3}}, + {L"\U0000ac01\U0000094d", {44033}, {2}}, + {L"\U0000ac01\U00000308\U0000094d", {44033}, {3}}, {L"\U0000ac01\U0000200d", {44033}, {2}}, {L"\U0000ac01\U00000308\U0000200d", {44033}, {3}}, {L"\U0000ac01\U00000378", {44033, 888}, {1, 2}}, {L"\U0000ac01\U00000308\U00000378", {44033, 888}, {2, 3}}, + {L"\U00000900\U00000020", {2304, 32}, {1, 2}}, + {L"\U00000900\U00000308\U00000020", {2304, 32}, {2, 3}}, + {L"\U00000900\U0000000d", {2304, 13}, {1, 2}}, + {L"\U00000900\U00000308\U0000000d", {2304, 13}, {2, 3}}, + {L"\U00000900\U0000000a", {2304, 10}, {1, 2}}, + {L"\U00000900\U00000308\U0000000a", {2304, 10}, {2, 3}}, + {L"\U00000900\U00000001", {2304, 1}, {1, 2}}, + {L"\U00000900\U00000308\U00000001", {2304, 1}, {2, 3}}, + {L"\U00000900\U0000034f", {2304}, {2}}, + {L"\U00000900\U00000308\U0000034f", {2304}, {3}}, + {L"\U00000900\U0001f1e6", {2304, 127462}, {1, 2}}, + {L"\U00000900\U00000308\U0001f1e6", {2304, 127462}, {2, 3}}, + {L"\U00000900\U00000600", {2304, 1536}, {1, 2}}, + {L"\U00000900\U00000308\U00000600", {2304, 1536}, {2, 3}}, + {L"\U00000900\U00000a03", {2304}, {2}}, + {L"\U00000900\U00000308\U00000a03", {2304}, {3}}, + {L"\U00000900\U00001100", {2304, 4352}, {1, 2}}, + {L"\U00000900\U00000308\U00001100", {2304, 4352}, {2, 3}}, + {L"\U00000900\U00001160", {2304, 4448}, {1, 2}}, + {L"\U00000900\U00000308\U00001160", {2304, 4448}, {2, 3}}, + {L"\U00000900\U000011a8", {2304, 4520}, {1, 2}}, + {L"\U00000900\U00000308\U000011a8", {2304, 4520}, {2, 3}}, + {L"\U00000900\U0000ac00", {2304, 44032}, {1, 2}}, + {L"\U00000900\U00000308\U0000ac00", {2304, 44032}, {2, 3}}, + {L"\U00000900\U0000ac01", {2304, 44033}, {1, 2}}, + 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{L"\U00000903\U00000308\U00000d4e", {2307, 3406}, {2, 3}}, + {L"\U00000903\U00000915", {2307, 2325}, {1, 2}}, + {L"\U00000903\U00000308\U00000915", {2307, 2325}, {2, 3}}, + {L"\U00000903\U0000231a", {2307, 8986}, {1, 2}}, + {L"\U00000903\U00000308\U0000231a", {2307, 8986}, {2, 3}}, + {L"\U00000903\U00000300", {2307}, {2}}, + {L"\U00000903\U00000308\U00000300", {2307}, {3}}, + {L"\U00000903\U0000093c", {2307}, {2}}, + {L"\U00000903\U00000308\U0000093c", {2307}, {3}}, + {L"\U00000903\U0000094d", {2307}, {2}}, + {L"\U00000903\U00000308\U0000094d", {2307}, {3}}, + {L"\U00000903\U0000200d", {2307}, {2}}, + {L"\U00000903\U00000308\U0000200d", {2307}, {3}}, + {L"\U00000903\U00000378", {2307, 888}, {1, 2}}, + {L"\U00000903\U00000308\U00000378", {2307, 888}, {2, 3}}, + {L"\U00000904\U00000020", {2308, 32}, {1, 2}}, + {L"\U00000904\U00000308\U00000020", {2308, 32}, {2, 3}}, + {L"\U00000904\U0000000d", {2308, 13}, {1, 2}}, + {L"\U00000904\U00000308\U0000000d", {2308, 13}, {2, 3}}, + {L"\U00000904\U0000000a", {2308, 10}, {1, 2}}, + {L"\U00000904\U00000308\U0000000a", {2308, 10}, {2, 3}}, + {L"\U00000904\U00000001", {2308, 1}, {1, 2}}, + {L"\U00000904\U00000308\U00000001", {2308, 1}, {2, 3}}, + {L"\U00000904\U0000034f", {2308}, {2}}, + {L"\U00000904\U00000308\U0000034f", {2308}, {3}}, + {L"\U00000904\U0001f1e6", {2308, 127462}, {1, 2}}, + {L"\U00000904\U00000308\U0001f1e6", {2308, 127462}, {2, 3}}, + {L"\U00000904\U00000600", {2308, 1536}, {1, 2}}, + {L"\U00000904\U00000308\U00000600", {2308, 1536}, {2, 3}}, + {L"\U00000904\U00000a03", {2308}, {2}}, + {L"\U00000904\U00000308\U00000a03", {2308}, {3}}, + {L"\U00000904\U00001100", {2308, 4352}, {1, 2}}, + {L"\U00000904\U00000308\U00001100", {2308, 4352}, {2, 3}}, + {L"\U00000904\U00001160", {2308, 4448}, {1, 2}}, + {L"\U00000904\U00000308\U00001160", {2308, 4448}, {2, 3}}, + {L"\U00000904\U000011a8", {2308, 4520}, {1, 2}}, + {L"\U00000904\U00000308\U000011a8", {2308, 4520}, {2, 3}}, + {L"\U00000904\U0000ac00", {2308, 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{L"\U00000904\U00000308\U0000093c", {2308}, {3}}, + {L"\U00000904\U0000094d", {2308}, {2}}, + {L"\U00000904\U00000308\U0000094d", {2308}, {3}}, + {L"\U00000904\U0000200d", {2308}, {2}}, + {L"\U00000904\U00000308\U0000200d", {2308}, {3}}, + {L"\U00000904\U00000378", {2308, 888}, {1, 2}}, + {L"\U00000904\U00000308\U00000378", {2308, 888}, {2, 3}}, + {L"\U00000d4e\U00000020", {3406}, {2}}, + {L"\U00000d4e\U00000308\U00000020", {3406, 32}, {2, 3}}, + {L"\U00000d4e\U0000000d", {3406, 13}, {1, 2}}, + {L"\U00000d4e\U00000308\U0000000d", {3406, 13}, {2, 3}}, + {L"\U00000d4e\U0000000a", {3406, 10}, {1, 2}}, + {L"\U00000d4e\U00000308\U0000000a", {3406, 10}, {2, 3}}, + {L"\U00000d4e\U00000001", {3406, 1}, {1, 2}}, + {L"\U00000d4e\U00000308\U00000001", {3406, 1}, {2, 3}}, + {L"\U00000d4e\U0000034f", {3406}, {2}}, + {L"\U00000d4e\U00000308\U0000034f", {3406}, {3}}, + {L"\U00000d4e\U0001f1e6", {3406}, {2}}, + {L"\U00000d4e\U00000308\U0001f1e6", {3406, 127462}, {2, 3}}, + {L"\U00000d4e\U00000600", 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{L"\U00000d4e\U00000d4e", {3406}, {2}}, + {L"\U00000d4e\U00000308\U00000d4e", {3406, 3406}, {2, 3}}, + {L"\U00000d4e\U00000915", {3406}, {2}}, + {L"\U00000d4e\U00000308\U00000915", {3406, 2325}, {2, 3}}, + {L"\U00000d4e\U0000231a", {3406}, {2}}, + {L"\U00000d4e\U00000308\U0000231a", {3406, 8986}, {2, 3}}, + {L"\U00000d4e\U00000300", {3406}, {2}}, + {L"\U00000d4e\U00000308\U00000300", {3406}, {3}}, + {L"\U00000d4e\U0000093c", {3406}, {2}}, + {L"\U00000d4e\U00000308\U0000093c", {3406}, {3}}, + {L"\U00000d4e\U0000094d", {3406}, {2}}, + {L"\U00000d4e\U00000308\U0000094d", {3406}, {3}}, + {L"\U00000d4e\U0000200d", {3406}, {2}}, + {L"\U00000d4e\U00000308\U0000200d", {3406}, {3}}, + {L"\U00000d4e\U00000378", {3406}, {2}}, + {L"\U00000d4e\U00000308\U00000378", {3406, 888}, {2, 3}}, + {L"\U00000915\U00000020", {2325, 32}, {1, 2}}, + {L"\U00000915\U00000308\U00000020", {2325, 32}, {2, 3}}, + {L"\U00000915\U0000000d", {2325, 13}, {1, 2}}, + {L"\U00000915\U00000308\U0000000d", {2325, 13}, {2, 3}}, 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44032}, {1, 2}}, + {L"\U00000915\U00000308\U0000ac00", {2325, 44032}, {2, 3}}, + {L"\U00000915\U0000ac01", {2325, 44033}, {1, 2}}, + {L"\U00000915\U00000308\U0000ac01", {2325, 44033}, {2, 3}}, + {L"\U00000915\U00000900", {2325}, {2}}, + {L"\U00000915\U00000308\U00000900", {2325}, {3}}, + {L"\U00000915\U00000903", {2325}, {2}}, + {L"\U00000915\U00000308\U00000903", {2325}, {3}}, + {L"\U00000915\U00000904", {2325, 2308}, {1, 2}}, + {L"\U00000915\U00000308\U00000904", {2325, 2308}, {2, 3}}, + {L"\U00000915\U00000d4e", {2325, 3406}, {1, 2}}, + {L"\U00000915\U00000308\U00000d4e", {2325, 3406}, {2, 3}}, + {L"\U00000915\U00000915", {2325, 2325}, {1, 2}}, + {L"\U00000915\U00000308\U00000915", {2325, 2325}, {2, 3}}, + {L"\U00000915\U0000231a", {2325, 8986}, {1, 2}}, + {L"\U00000915\U00000308\U0000231a", {2325, 8986}, {2, 3}}, + {L"\U00000915\U00000300", {2325}, {2}}, + {L"\U00000915\U00000308\U00000300", {2325}, {3}}, + {L"\U00000915\U0000093c", {2325}, {2}}, + {L"\U00000915\U00000308\U0000093c", {2325}, {3}}, + {L"\U00000915\U0000094d", {2325}, {2}}, + {L"\U00000915\U00000308\U0000094d", {2325}, {3}}, + {L"\U00000915\U0000200d", {2325}, {2}}, + {L"\U00000915\U00000308\U0000200d", {2325}, {3}}, + {L"\U00000915\U00000378", {2325, 888}, {1, 2}}, + {L"\U00000915\U00000308\U00000378", {2325, 888}, {2, 3}}, {L"\U0000231a\U00000020", {8986, 32}, {1, 2}}, {L"\U0000231a\U00000308\U00000020", {8986, 32}, {2, 3}}, {L"\U0000231a\U0000000d", {8986, 13}, {1, 2}}, @@ -1758,8 +3350,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000231a\U00000308\U0001f1e6", {8986, 127462}, {2, 3}}, {L"\U0000231a\U00000600", {8986, 1536}, {1, 2}}, {L"\U0000231a\U00000308\U00000600", {8986, 1536}, {2, 3}}, - {L"\U0000231a\U00000903", {8986}, {2}}, - {L"\U0000231a\U00000308\U00000903", {8986}, {3}}, + {L"\U0000231a\U00000a03", {8986}, {2}}, + {L"\U0000231a\U00000308\U00000a03", {8986}, {3}}, {L"\U0000231a\U00001100", {8986, 4352}, {1, 2}}, {L"\U0000231a\U00000308\U00001100", {8986, 4352}, {2, 3}}, {L"\U0000231a\U00001160", {8986, 4448}, {1, 2}}, @@ -1770,10 +3362,24 @@ std::array, 602> data_utf32 = {{ {L"\U0000231a\U00000308\U0000ac00", {8986, 44032}, {2, 3}}, {L"\U0000231a\U0000ac01", {8986, 44033}, {1, 2}}, {L"\U0000231a\U00000308\U0000ac01", {8986, 44033}, {2, 3}}, + {L"\U0000231a\U00000900", {8986}, {2}}, + {L"\U0000231a\U00000308\U00000900", {8986}, {3}}, + {L"\U0000231a\U00000903", {8986}, {2}}, + {L"\U0000231a\U00000308\U00000903", {8986}, {3}}, + {L"\U0000231a\U00000904", {8986, 2308}, {1, 2}}, + {L"\U0000231a\U00000308\U00000904", {8986, 2308}, {2, 3}}, + {L"\U0000231a\U00000d4e", {8986, 3406}, {1, 2}}, + {L"\U0000231a\U00000308\U00000d4e", {8986, 3406}, {2, 3}}, + {L"\U0000231a\U00000915", {8986, 2325}, {1, 2}}, + {L"\U0000231a\U00000308\U00000915", {8986, 2325}, {2, 3}}, {L"\U0000231a\U0000231a", {8986, 8986}, {1, 2}}, {L"\U0000231a\U00000308\U0000231a", {8986, 8986}, {2, 3}}, {L"\U0000231a\U00000300", {8986}, {2}}, {L"\U0000231a\U00000308\U00000300", {8986}, {3}}, + {L"\U0000231a\U0000093c", {8986}, {2}}, + {L"\U0000231a\U00000308\U0000093c", {8986}, {3}}, + {L"\U0000231a\U0000094d", {8986}, {2}}, + {L"\U0000231a\U00000308\U0000094d", {8986}, {3}}, {L"\U0000231a\U0000200d", {8986}, {2}}, {L"\U0000231a\U00000308\U0000200d", {8986}, {3}}, {L"\U0000231a\U00000378", {8986, 888}, {1, 2}}, @@ -1792,8 +3398,8 @@ std::array, 602> data_utf32 = {{ {L"\U00000300\U00000308\U0001f1e6", {768, 127462}, {2, 3}}, {L"\U00000300\U00000600", {768, 1536}, {1, 2}}, {L"\U00000300\U00000308\U00000600", {768, 1536}, {2, 3}}, - {L"\U00000300\U00000903", {768}, {2}}, - {L"\U00000300\U00000308\U00000903", {768}, {3}}, + {L"\U00000300\U00000a03", {768}, {2}}, + {L"\U00000300\U00000308\U00000a03", {768}, {3}}, {L"\U00000300\U00001100", {768, 4352}, {1, 2}}, {L"\U00000300\U00000308\U00001100", {768, 4352}, {2, 3}}, {L"\U00000300\U00001160", {768, 4448}, {1, 2}}, @@ -1804,14 +3410,124 @@ std::array, 602> data_utf32 = {{ {L"\U00000300\U00000308\U0000ac00", {768, 44032}, {2, 3}}, {L"\U00000300\U0000ac01", {768, 44033}, {1, 2}}, {L"\U00000300\U00000308\U0000ac01", {768, 44033}, {2, 3}}, + {L"\U00000300\U00000900", {768}, {2}}, + {L"\U00000300\U00000308\U00000900", {768}, {3}}, + {L"\U00000300\U00000903", {768}, {2}}, + {L"\U00000300\U00000308\U00000903", {768}, {3}}, + {L"\U00000300\U00000904", {768, 2308}, {1, 2}}, + {L"\U00000300\U00000308\U00000904", {768, 2308}, {2, 3}}, + {L"\U00000300\U00000d4e", {768, 3406}, {1, 2}}, + {L"\U00000300\U00000308\U00000d4e", {768, 3406}, {2, 3}}, + {L"\U00000300\U00000915", {768, 2325}, {1, 2}}, + {L"\U00000300\U00000308\U00000915", {768, 2325}, {2, 3}}, {L"\U00000300\U0000231a", {768, 8986}, {1, 2}}, {L"\U00000300\U00000308\U0000231a", {768, 8986}, {2, 3}}, {L"\U00000300\U00000300", {768}, {2}}, {L"\U00000300\U00000308\U00000300", {768}, {3}}, + {L"\U00000300\U0000093c", {768}, {2}}, + {L"\U00000300\U00000308\U0000093c", {768}, {3}}, + {L"\U00000300\U0000094d", {768}, {2}}, + {L"\U00000300\U00000308\U0000094d", {768}, {3}}, {L"\U00000300\U0000200d", {768}, {2}}, {L"\U00000300\U00000308\U0000200d", {768}, {3}}, {L"\U00000300\U00000378", {768, 888}, {1, 2}}, {L"\U00000300\U00000308\U00000378", {768, 888}, {2, 3}}, + {L"\U0000093c\U00000020", {2364, 32}, {1, 2}}, + {L"\U0000093c\U00000308\U00000020", {2364, 32}, {2, 3}}, + {L"\U0000093c\U0000000d", {2364, 13}, {1, 2}}, + {L"\U0000093c\U00000308\U0000000d", {2364, 13}, {2, 3}}, + {L"\U0000093c\U0000000a", {2364, 10}, {1, 2}}, + {L"\U0000093c\U00000308\U0000000a", {2364, 10}, {2, 3}}, + {L"\U0000093c\U00000001", {2364, 1}, {1, 2}}, + {L"\U0000093c\U00000308\U00000001", {2364, 1}, {2, 3}}, + {L"\U0000093c\U0000034f", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000034f", {2364}, {3}}, + {L"\U0000093c\U0001f1e6", {2364, 127462}, {1, 2}}, + {L"\U0000093c\U00000308\U0001f1e6", {2364, 127462}, {2, 3}}, + {L"\U0000093c\U00000600", {2364, 1536}, {1, 2}}, + {L"\U0000093c\U00000308\U00000600", {2364, 1536}, {2, 3}}, + {L"\U0000093c\U00000a03", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000a03", {2364}, {3}}, + {L"\U0000093c\U00001100", {2364, 4352}, {1, 2}}, + {L"\U0000093c\U00000308\U00001100", {2364, 4352}, {2, 3}}, + {L"\U0000093c\U00001160", {2364, 4448}, {1, 2}}, + {L"\U0000093c\U00000308\U00001160", {2364, 4448}, {2, 3}}, + {L"\U0000093c\U000011a8", {2364, 4520}, {1, 2}}, + {L"\U0000093c\U00000308\U000011a8", {2364, 4520}, {2, 3}}, + {L"\U0000093c\U0000ac00", {2364, 44032}, {1, 2}}, + {L"\U0000093c\U00000308\U0000ac00", {2364, 44032}, {2, 3}}, + {L"\U0000093c\U0000ac01", {2364, 44033}, {1, 2}}, + {L"\U0000093c\U00000308\U0000ac01", {2364, 44033}, {2, 3}}, + {L"\U0000093c\U00000900", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000900", {2364}, {3}}, + {L"\U0000093c\U00000903", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000903", {2364}, {3}}, + {L"\U0000093c\U00000904", {2364, 2308}, {1, 2}}, + {L"\U0000093c\U00000308\U00000904", {2364, 2308}, {2, 3}}, + {L"\U0000093c\U00000d4e", {2364, 3406}, {1, 2}}, + {L"\U0000093c\U00000308\U00000d4e", {2364, 3406}, {2, 3}}, + {L"\U0000093c\U00000915", {2364, 2325}, {1, 2}}, + {L"\U0000093c\U00000308\U00000915", {2364, 2325}, {2, 3}}, + {L"\U0000093c\U0000231a", {2364, 8986}, {1, 2}}, + {L"\U0000093c\U00000308\U0000231a", {2364, 8986}, {2, 3}}, + {L"\U0000093c\U00000300", {2364}, {2}}, + {L"\U0000093c\U00000308\U00000300", {2364}, {3}}, + {L"\U0000093c\U0000093c", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000093c", {2364}, {3}}, + {L"\U0000093c\U0000094d", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000094d", {2364}, {3}}, + {L"\U0000093c\U0000200d", {2364}, {2}}, + {L"\U0000093c\U00000308\U0000200d", {2364}, {3}}, + {L"\U0000093c\U00000378", {2364, 888}, {1, 2}}, + {L"\U0000093c\U00000308\U00000378", {2364, 888}, {2, 3}}, + {L"\U0000094d\U00000020", {2381, 32}, {1, 2}}, + {L"\U0000094d\U00000308\U00000020", {2381, 32}, {2, 3}}, + {L"\U0000094d\U0000000d", {2381, 13}, {1, 2}}, + {L"\U0000094d\U00000308\U0000000d", {2381, 13}, {2, 3}}, + {L"\U0000094d\U0000000a", {2381, 10}, {1, 2}}, + {L"\U0000094d\U00000308\U0000000a", {2381, 10}, {2, 3}}, + {L"\U0000094d\U00000001", {2381, 1}, {1, 2}}, + {L"\U0000094d\U00000308\U00000001", {2381, 1}, {2, 3}}, + {L"\U0000094d\U0000034f", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000034f", {2381}, {3}}, + {L"\U0000094d\U0001f1e6", {2381, 127462}, {1, 2}}, + {L"\U0000094d\U00000308\U0001f1e6", {2381, 127462}, {2, 3}}, + {L"\U0000094d\U00000600", {2381, 1536}, {1, 2}}, + {L"\U0000094d\U00000308\U00000600", {2381, 1536}, {2, 3}}, + {L"\U0000094d\U00000a03", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000a03", {2381}, {3}}, + {L"\U0000094d\U00001100", {2381, 4352}, {1, 2}}, + {L"\U0000094d\U00000308\U00001100", {2381, 4352}, {2, 3}}, + {L"\U0000094d\U00001160", {2381, 4448}, {1, 2}}, + {L"\U0000094d\U00000308\U00001160", {2381, 4448}, {2, 3}}, + {L"\U0000094d\U000011a8", {2381, 4520}, {1, 2}}, + {L"\U0000094d\U00000308\U000011a8", {2381, 4520}, {2, 3}}, + {L"\U0000094d\U0000ac00", {2381, 44032}, {1, 2}}, + {L"\U0000094d\U00000308\U0000ac00", {2381, 44032}, {2, 3}}, + {L"\U0000094d\U0000ac01", {2381, 44033}, {1, 2}}, + {L"\U0000094d\U00000308\U0000ac01", {2381, 44033}, {2, 3}}, + {L"\U0000094d\U00000900", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000900", {2381}, {3}}, + {L"\U0000094d\U00000903", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000903", {2381}, {3}}, + {L"\U0000094d\U00000904", {2381, 2308}, {1, 2}}, + {L"\U0000094d\U00000308\U00000904", {2381, 2308}, {2, 3}}, + {L"\U0000094d\U00000d4e", {2381, 3406}, {1, 2}}, + {L"\U0000094d\U00000308\U00000d4e", {2381, 3406}, {2, 3}}, + {L"\U0000094d\U00000915", {2381, 2325}, {1, 2}}, + {L"\U0000094d\U00000308\U00000915", {2381, 2325}, {2, 3}}, + {L"\U0000094d\U0000231a", {2381, 8986}, {1, 2}}, + {L"\U0000094d\U00000308\U0000231a", {2381, 8986}, {2, 3}}, + {L"\U0000094d\U00000300", {2381}, {2}}, + {L"\U0000094d\U00000308\U00000300", {2381}, {3}}, + {L"\U0000094d\U0000093c", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000093c", {2381}, {3}}, + {L"\U0000094d\U0000094d", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000094d", {2381}, {3}}, + {L"\U0000094d\U0000200d", {2381}, {2}}, + {L"\U0000094d\U00000308\U0000200d", {2381}, {3}}, + {L"\U0000094d\U00000378", {2381, 888}, {1, 2}}, + {L"\U0000094d\U00000308\U00000378", {2381, 888}, {2, 3}}, {L"\U0000200d\U00000020", {8205, 32}, {1, 2}}, {L"\U0000200d\U00000308\U00000020", {8205, 32}, {2, 3}}, {L"\U0000200d\U0000000d", {8205, 13}, {1, 2}}, @@ -1826,8 +3542,8 @@ std::array, 602> data_utf32 = {{ {L"\U0000200d\U00000308\U0001f1e6", {8205, 127462}, {2, 3}}, {L"\U0000200d\U00000600", {8205, 1536}, {1, 2}}, {L"\U0000200d\U00000308\U00000600", {8205, 1536}, {2, 3}}, - {L"\U0000200d\U00000903", {8205}, {2}}, - {L"\U0000200d\U00000308\U00000903", {8205}, {3}}, + {L"\U0000200d\U00000a03", {8205}, {2}}, + {L"\U0000200d\U00000308\U00000a03", {8205}, {3}}, {L"\U0000200d\U00001100", {8205, 4352}, {1, 2}}, {L"\U0000200d\U00000308\U00001100", {8205, 4352}, {2, 3}}, {L"\U0000200d\U00001160", {8205, 4448}, {1, 2}}, @@ -1838,10 +3554,24 @@ std::array, 602> data_utf32 = {{ {L"\U0000200d\U00000308\U0000ac00", {8205, 44032}, {2, 3}}, {L"\U0000200d\U0000ac01", {8205, 44033}, {1, 2}}, {L"\U0000200d\U00000308\U0000ac01", {8205, 44033}, {2, 3}}, + {L"\U0000200d\U00000900", {8205}, {2}}, + {L"\U0000200d\U00000308\U00000900", {8205}, {3}}, + {L"\U0000200d\U00000903", {8205}, {2}}, + {L"\U0000200d\U00000308\U00000903", {8205}, {3}}, + {L"\U0000200d\U00000904", {8205, 2308}, {1, 2}}, + {L"\U0000200d\U00000308\U00000904", {8205, 2308}, {2, 3}}, + {L"\U0000200d\U00000d4e", {8205, 3406}, {1, 2}}, + {L"\U0000200d\U00000308\U00000d4e", {8205, 3406}, {2, 3}}, + {L"\U0000200d\U00000915", {8205, 2325}, {1, 2}}, + {L"\U0000200d\U00000308\U00000915", {8205, 2325}, {2, 3}}, {L"\U0000200d\U0000231a", {8205, 8986}, {1, 2}}, {L"\U0000200d\U00000308\U0000231a", {8205, 8986}, {2, 3}}, {L"\U0000200d\U00000300", {8205}, {2}}, {L"\U0000200d\U00000308\U00000300", {8205}, {3}}, + {L"\U0000200d\U0000093c", {8205}, {2}}, + {L"\U0000200d\U00000308\U0000093c", {8205}, {3}}, + {L"\U0000200d\U0000094d", {8205}, {2}}, + {L"\U0000200d\U00000308\U0000094d", {8205}, {3}}, {L"\U0000200d\U0000200d", {8205}, {2}}, {L"\U0000200d\U00000308\U0000200d", {8205}, {3}}, {L"\U0000200d\U00000378", {8205, 888}, {1, 2}}, @@ -1860,8 +3590,8 @@ std::array, 602> data_utf32 = {{ {L"\U00000378\U00000308\U0001f1e6", {888, 127462}, {2, 3}}, {L"\U00000378\U00000600", {888, 1536}, {1, 2}}, {L"\U00000378\U00000308\U00000600", {888, 1536}, {2, 3}}, - {L"\U00000378\U00000903", {888}, {2}}, - {L"\U00000378\U00000308\U00000903", {888}, {3}}, + {L"\U00000378\U00000a03", {888}, {2}}, + {L"\U00000378\U00000308\U00000a03", {888}, {3}}, {L"\U00000378\U00001100", {888, 4352}, {1, 2}}, {L"\U00000378\U00000308\U00001100", {888, 4352}, {2, 3}}, {L"\U00000378\U00001160", {888, 4448}, {1, 2}}, @@ -1872,10 +3602,24 @@ std::array, 602> data_utf32 = {{ {L"\U00000378\U00000308\U0000ac00", {888, 44032}, {2, 3}}, {L"\U00000378\U0000ac01", {888, 44033}, {1, 2}}, {L"\U00000378\U00000308\U0000ac01", {888, 44033}, {2, 3}}, + {L"\U00000378\U00000900", {888}, {2}}, + {L"\U00000378\U00000308\U00000900", {888}, {3}}, + {L"\U00000378\U00000903", {888}, {2}}, + {L"\U00000378\U00000308\U00000903", {888}, {3}}, + {L"\U00000378\U00000904", {888, 2308}, {1, 2}}, + {L"\U00000378\U00000308\U00000904", {888, 2308}, {2, 3}}, + {L"\U00000378\U00000d4e", {888, 3406}, {1, 2}}, + {L"\U00000378\U00000308\U00000d4e", {888, 3406}, {2, 3}}, + {L"\U00000378\U00000915", {888, 2325}, {1, 2}}, + {L"\U00000378\U00000308\U00000915", {888, 2325}, {2, 3}}, {L"\U00000378\U0000231a", {888, 8986}, {1, 2}}, {L"\U00000378\U00000308\U0000231a", {888, 8986}, {2, 3}}, {L"\U00000378\U00000300", {888}, {2}}, {L"\U00000378\U00000308\U00000300", {888}, {3}}, + {L"\U00000378\U0000093c", {888}, {2}}, + {L"\U00000378\U00000308\U0000093c", {888}, {3}}, + {L"\U00000378\U0000094d", {888}, {2}}, + {L"\U00000378\U00000308\U0000094d", {888}, {3}}, {L"\U00000378\U0000200d", {888}, {2}}, {L"\U00000378\U00000308\U0000200d", {888}, {3}}, {L"\U00000378\U00000378", {888, 888}, {1, 2}}, @@ -1903,7 +3647,18 @@ std::array, 602> data_utf32 = {{ {L"\U0001f6d1\U0000200d\U0001f6d1", {128721}, {3}}, {L"\U00000061\U0000200d\U0001f6d1", {97, 128721}, {2, 3}}, {L"\U00002701\U0000200d\U00002701", {9985}, {3}}, - {L"\U00000061\U0000200d\U00002701", {97, 9985}, {2, 3}}}}; + {L"\U00000061\U0000200d\U00002701", {97, 9985}, {2, 3}}, + {L"\U00000915\U00000924", {2325, 2340}, {1, 2}}, + {L"\U00000915\U0000094d\U00000924", {2325}, {3}}, + {L"\U00000915\U0000094d\U0000094d\U00000924", {2325}, {4}}, + {L"\U00000915\U0000094d\U0000200d\U00000924", {2325}, {4}}, + {L"\U00000915\U0000093c\U0000200d\U0000094d\U00000924", {2325}, {5}}, + {L"\U00000915\U0000093c\U0000094d\U0000200d\U00000924", {2325}, {5}}, + {L"\U00000915\U0000094d\U00000924\U0000094d\U0000092f", {2325}, {5}}, + {L"\U00000915\U0000094d\U00000061", {2325, 97}, {2, 3}}, + {L"\U00000061\U0000094d\U00000924", {97, 2340}, {2, 3}}, + {L"\U0000003f\U0000094d\U00000924", {63, 2340}, {2, 3}}, + {L"\U00000915\U0000094d\U0000094d\U00000924", {2325}, {4}}}}; #endif // TEST_HAS_NO_WIDE_CHARACTERS #endif // LIBCXX_TEST_STD_UTILITIES_FORMAT_FORMAT_STRING_FORMAT_STRING_STD_EXTENDED_GRAPHEME_CLUSTER_H diff --git a/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp b/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp index 5f9873b51ac0..c1fdd1f2098d 100644 --- a/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp +++ b/libcxx/test/libcxx/utilities/format/format.string/format.string.std/extended_grapheme_cluster.pass.cpp @@ -53,6 +53,21 @@ static_assert(count_entries(cluster::__property::__LVT) == 10773); static_assert(count_entries(cluster::__property::__ZWJ) == 1); static_assert(count_entries(cluster::__property::__Extended_Pictographic) == 3537); +namespace inCB = std::__indic_conjunct_break; +constexpr int count_entries(inCB::__property property) { + return std::transform_reduce( + std::begin(inCB::__entries), std::end(inCB::__entries), 0, std::plus{}, [property](auto entry) { + if (static_cast(entry & 0b11) != property) + return 0; + + return 1 + static_cast((entry >> 2) & 0b1'1111'1111); + }); +} + +static_assert(count_entries(inCB::__property::__Linker) == 6); +static_assert(count_entries(inCB::__property::__Consonant) == 240); +static_assert(count_entries(inCB::__property::__Extend) == 884); + } // namespace template diff --git a/libcxx/utils/CMakeLists.txt b/libcxx/utils/CMakeLists.txt index 19bb9851c867..7a573535e1ef 100644 --- a/libcxx/utils/CMakeLists.txt +++ b/libcxx/utils/CMakeLists.txt @@ -48,6 +48,13 @@ add_custom_target(libcxx-generate-width-estimation-table "${LIBCXX_SOURCE_DIR}/include/__format/width_estimation_table.h" COMMENT "Generate the width estimation header") +add_custom_target(libcxx-indic-conjunct-break-table + COMMAND + "${Python3_EXECUTABLE}" + "${LIBCXX_SOURCE_DIR}/utils/generate_indic_conjunct_break_table.py" + "${LIBCXX_SOURCE_DIR}/include/__format/indic_conjunct_break_table.h" + COMMENT "Generate the Indic Conjunct Break header") + add_custom_target(libcxx-generate-iwyu-mapping COMMAND "${Python3_EXECUTABLE}" @@ -63,5 +70,6 @@ add_custom_target(libcxx-generate-files libcxx-generate-extended-grapheme-cluster-tests libcxx-generate-escaped-output-table libcxx-generate-width-estimation-table + libcxx-indic-conjunct-break-table libcxx-generate-iwyu-mapping COMMENT "Create all the auto-generated files in libc++ and its tests.") diff --git a/libcxx/utils/data/unicode/DerivedCoreProperties.txt b/libcxx/utils/data/unicode/DerivedCoreProperties.txt index 8b482b5c10ae..220c55685d4b 100644 --- a/libcxx/utils/data/unicode/DerivedCoreProperties.txt +++ b/libcxx/utils/data/unicode/DerivedCoreProperties.txt @@ -1,6 +1,6 @@ -# DerivedCoreProperties-15.0.0.txt -# Date: 2022-08-05, 22:17:05 GMT -# © 2022 Unicode®, Inc. +# DerivedCoreProperties-15.1.0.txt +# Date: 2023-08-07, 15:21:24 GMT +# © 2023 Unicode®, Inc. # Unicode and the Unicode Logo are registered trademarks of Unicode, Inc. in the U.S. and other countries. # For terms of use, see https://www.unicode.org/terms_of_use.html # @@ -1397,11 +1397,12 @@ FFDA..FFDC ; Alphabetic # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANG 2B740..2B81D ; Alphabetic # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; Alphabetic # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; Alphabetic # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; Alphabetic # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; Alphabetic # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; Alphabetic # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; Alphabetic # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF -# Total code points: 137765 +# Total code points: 138387 # ================================================ @@ -6853,11 +6854,12 @@ FFDA..FFDC ; ID_Start # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGUL 2B740..2B81D ; ID_Start # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; ID_Start # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; ID_Start # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; ID_Start # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; ID_Start # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; ID_Start # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; ID_Start # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF -# Total code points: 136345 +# Total code points: 136967 # ================================================ @@ -7438,6 +7440,7 @@ FFDA..FFDC ; ID_Start # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGUL 1FE0..1FEC ; ID_Continue # L& [13] GREEK SMALL LETTER UPSILON WITH VRACHY..GREEK CAPITAL LETTER RHO WITH DASIA 1FF2..1FF4 ; ID_Continue # L& [3] GREEK SMALL LETTER OMEGA WITH VARIA AND YPOGEGRAMMENI..GREEK SMALL LETTER OMEGA WITH OXIA AND YPOGEGRAMMENI 1FF6..1FFC ; ID_Continue # L& [7] GREEK SMALL LETTER OMEGA WITH PERISPOMENI..GREEK CAPITAL LETTER OMEGA WITH PROSGEGRAMMENI +200C..200D ; ID_Continue # Cf [2] ZERO WIDTH NON-JOINER..ZERO WIDTH JOINER 203F..2040 ; ID_Continue # Pc [2] UNDERTIE..CHARACTER TIE 2054 ; ID_Continue # Pc INVERTED UNDERTIE 2071 ; ID_Continue # Lm SUPERSCRIPT LATIN SMALL LETTER I @@ -7504,6 +7507,7 @@ FFDA..FFDC ; ID_Start # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGUL 309D..309E ; ID_Continue # Lm [2] HIRAGANA ITERATION MARK..HIRAGANA VOICED ITERATION MARK 309F ; ID_Continue # Lo HIRAGANA DIGRAPH YORI 30A1..30FA ; ID_Continue # Lo [90] KATAKANA LETTER SMALL A..KATAKANA LETTER VO +30FB ; ID_Continue # Po KATAKANA MIDDLE DOT 30FC..30FE ; ID_Continue # Lm [3] KATAKANA-HIRAGANA PROLONGED SOUND MARK..KATAKANA VOICED ITERATION MARK 30FF ; ID_Continue # Lo KATAKANA DIGRAPH KOTO 3105..312F ; ID_Continue # Lo [43] BOPOMOFO LETTER B..BOPOMOFO LETTER NN @@ -7683,6 +7687,7 @@ FF10..FF19 ; ID_Continue # Nd [10] FULLWIDTH DIGIT ZERO..FULLWIDTH DIGIT NIN FF21..FF3A ; ID_Continue # L& [26] FULLWIDTH LATIN CAPITAL LETTER A..FULLWIDTH LATIN CAPITAL LETTER Z FF3F ; ID_Continue # Pc FULLWIDTH LOW LINE FF41..FF5A ; ID_Continue # L& [26] FULLWIDTH LATIN SMALL LETTER A..FULLWIDTH LATIN SMALL LETTER Z +FF65 ; ID_Continue # Po HALFWIDTH KATAKANA MIDDLE DOT FF66..FF6F ; ID_Continue # Lo [10] HALFWIDTH KATAKANA LETTER WO..HALFWIDTH KATAKANA LETTER SMALL TU FF70 ; ID_Continue # Lm HALFWIDTH KATAKANA-HIRAGANA PROLONGED SOUND MARK FF71..FF9D ; ID_Continue # Lo [45] HALFWIDTH KATAKANA LETTER A..HALFWIDTH KATAKANA LETTER N @@ -8207,12 +8212,13 @@ FFDA..FFDC ; ID_Continue # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HAN 2B740..2B81D ; ID_Continue # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; ID_Continue # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; ID_Continue # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; ID_Continue # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; ID_Continue # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; ID_Continue # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; ID_Continue # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF E0100..E01EF ; ID_Continue # Mn [240] VARIATION SELECTOR-17..VARIATION SELECTOR-256 -# Total code points: 139482 +# Total code points: 140108 # ================================================ @@ -8962,11 +8968,12 @@ FFDA..FFDC ; XID_Start # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGU 2B740..2B81D ; XID_Start # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; XID_Start # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; XID_Start # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; XID_Start # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; XID_Start # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; XID_Start # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; XID_Start # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF -# Total code points: 136322 +# Total code points: 136944 # ================================================ @@ -9543,6 +9550,7 @@ FFDA..FFDC ; XID_Start # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGU 1FE0..1FEC ; XID_Continue # L& [13] GREEK SMALL LETTER UPSILON WITH VRACHY..GREEK CAPITAL LETTER RHO WITH DASIA 1FF2..1FF4 ; XID_Continue # L& [3] GREEK SMALL LETTER OMEGA WITH VARIA AND YPOGEGRAMMENI..GREEK SMALL LETTER OMEGA WITH OXIA AND YPOGEGRAMMENI 1FF6..1FFC ; XID_Continue # L& [7] GREEK SMALL LETTER OMEGA WITH PERISPOMENI..GREEK CAPITAL LETTER OMEGA WITH PROSGEGRAMMENI +200C..200D ; XID_Continue # Cf [2] ZERO WIDTH NON-JOINER..ZERO WIDTH JOINER 203F..2040 ; XID_Continue # Pc [2] UNDERTIE..CHARACTER TIE 2054 ; XID_Continue # Pc INVERTED UNDERTIE 2071 ; XID_Continue # Lm SUPERSCRIPT LATIN SMALL LETTER I @@ -9608,6 +9616,7 @@ FFDA..FFDC ; XID_Start # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGU 309D..309E ; XID_Continue # Lm [2] HIRAGANA ITERATION MARK..HIRAGANA VOICED ITERATION MARK 309F ; XID_Continue # Lo HIRAGANA DIGRAPH YORI 30A1..30FA ; XID_Continue # Lo [90] KATAKANA LETTER SMALL A..KATAKANA LETTER VO +30FB ; XID_Continue # Po KATAKANA MIDDLE DOT 30FC..30FE ; XID_Continue # Lm [3] KATAKANA-HIRAGANA PROLONGED SOUND MARK..KATAKANA VOICED ITERATION MARK 30FF ; XID_Continue # Lo KATAKANA DIGRAPH KOTO 3105..312F ; XID_Continue # Lo [43] BOPOMOFO LETTER B..BOPOMOFO LETTER NN @@ -9793,6 +9802,7 @@ FF10..FF19 ; XID_Continue # Nd [10] FULLWIDTH DIGIT ZERO..FULLWIDTH DIGIT NI FF21..FF3A ; XID_Continue # L& [26] FULLWIDTH LATIN CAPITAL LETTER A..FULLWIDTH LATIN CAPITAL LETTER Z FF3F ; XID_Continue # Pc FULLWIDTH LOW LINE FF41..FF5A ; XID_Continue # L& [26] FULLWIDTH LATIN SMALL LETTER A..FULLWIDTH LATIN SMALL LETTER Z +FF65 ; XID_Continue # Po HALFWIDTH KATAKANA MIDDLE DOT FF66..FF6F ; XID_Continue # Lo [10] HALFWIDTH KATAKANA LETTER WO..HALFWIDTH KATAKANA LETTER SMALL TU FF70 ; XID_Continue # Lm HALFWIDTH KATAKANA-HIRAGANA PROLONGED SOUND MARK FF71..FF9D ; XID_Continue # Lo [45] HALFWIDTH KATAKANA LETTER A..HALFWIDTH KATAKANA LETTER N @@ -10317,12 +10327,13 @@ FFDA..FFDC ; XID_Continue # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HA 2B740..2B81D ; XID_Continue # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; XID_Continue # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; XID_Continue # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; XID_Continue # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; XID_Continue # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; XID_Continue # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; XID_Continue # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF E0100..E01EF ; XID_Continue # Mn [240] VARIATION SELECTOR-17..VARIATION SELECTOR-256 -# Total code points: 139463 +# Total code points: 140089 # ================================================ @@ -10335,6 +10346,15 @@ E0100..E01EF ; XID_Continue # Mn [240] VARIATION SELECTOR-17..VARIATION SELECTO # - FFF9..FFFB (Interlinear annotation format characters) # - 13430..13440 (Egyptian hieroglyph format characters) # - Prepended_Concatenation_Mark (Exceptional format characters that should be visible) +# +# There are currently no stability guarantees for DICP. However, the +# values of DICP interact with the derivation of XID_Continue +# and NFKC_CF, for which there are stability guarantees. +# Maintainers of this property should note that in the +# unlikely case that the DICP value changes for an existing character +# which is also XID_Continue=Yes, then exceptions must be put +# in place to ensure that the NFKC_CF mapping value for that +# existing character does not change. 00AD ; Default_Ignorable_Code_Point # Cf SOFT HYPHEN 034F ; Default_Ignorable_Code_Point # Mn COMBINING GRAPHEME JOINER @@ -11602,7 +11622,7 @@ E0100..E01EF ; Grapheme_Extend # Mn [240] VARIATION SELECTOR-17..VARIATION SELE 2E80..2E99 ; Grapheme_Base # So [26] CJK RADICAL REPEAT..CJK RADICAL RAP 2E9B..2EF3 ; Grapheme_Base # So [89] CJK RADICAL CHOKE..CJK RADICAL C-SIMPLIFIED TURTLE 2F00..2FD5 ; Grapheme_Base # So [214] KANGXI RADICAL ONE..KANGXI RADICAL FLUTE -2FF0..2FFB ; Grapheme_Base # So [12] IDEOGRAPHIC DESCRIPTION CHARACTER LEFT TO RIGHT..IDEOGRAPHIC DESCRIPTION CHARACTER OVERLAID +2FF0..2FFF ; Grapheme_Base # So [16] IDEOGRAPHIC DESCRIPTION CHARACTER LEFT TO RIGHT..IDEOGRAPHIC DESCRIPTION CHARACTER ROTATION 3000 ; Grapheme_Base # Zs IDEOGRAPHIC SPACE 3001..3003 ; Grapheme_Base # Po [3] IDEOGRAPHIC COMMA..DITTO MARK 3004 ; Grapheme_Base # So JAPANESE INDUSTRIAL STANDARD SYMBOL @@ -11657,6 +11677,7 @@ E0100..E01EF ; Grapheme_Extend # Mn [240] VARIATION SELECTOR-17..VARIATION SELE 3196..319F ; Grapheme_Base # So [10] IDEOGRAPHIC ANNOTATION TOP MARK..IDEOGRAPHIC ANNOTATION MAN MARK 31A0..31BF ; Grapheme_Base # Lo [32] BOPOMOFO LETTER BU..BOPOMOFO LETTER AH 31C0..31E3 ; Grapheme_Base # So [36] CJK STROKE T..CJK STROKE Q +31EF ; Grapheme_Base # So IDEOGRAPHIC DESCRIPTION CHARACTER SUBTRACTION 31F0..31FF ; Grapheme_Base # Lo [16] KATAKANA LETTER SMALL KU..KATAKANA LETTER SMALL RO 3200..321E ; Grapheme_Base # So [31] PARENTHESIZED HANGUL KIYEOK..PARENTHESIZED KOREAN CHARACTER O HU 3220..3229 ; Grapheme_Base # No [10] PARENTHESIZED IDEOGRAPH ONE..PARENTHESIZED IDEOGRAPH TEN @@ -12497,11 +12518,12 @@ FFFC..FFFD ; Grapheme_Base # So [2] OBJECT REPLACEMENT CHARACTER..REPLACEME 2B740..2B81D ; Grapheme_Base # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; Grapheme_Base # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; Grapheme_Base # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; Grapheme_Base # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; Grapheme_Base # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; Grapheme_Base # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; Grapheme_Base # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF -# Total code points: 146986 +# Total code points: 147613 # ================================================ @@ -12572,4 +12594,239 @@ ABED ; Grapheme_Link # Mn MEETEI MAYEK APUN IYEK # Total code points: 65 +# ================================================ + +# Derived Property: Indic_Conjunct_Break +# Generated from the Grapheme_Cluster_Break, Indic_Syllabic_Category, +# Canonical_Combining_Class, and Script properties as described in UAX #44: +# https://www.unicode.org/reports/tr44/. + +# All code points not explicitly listed for Indic_Conjunct_Break +# have the value None. + +# @missing: 0000..10FFFF; InCB; None + +# ================================================ + +# Indic_Conjunct_Break=Linker + +094D ; InCB; Linker # Mn DEVANAGARI SIGN VIRAMA +09CD ; InCB; Linker # Mn BENGALI SIGN VIRAMA +0ACD ; InCB; Linker # Mn GUJARATI SIGN VIRAMA +0B4D ; InCB; Linker # Mn ORIYA SIGN VIRAMA +0C4D ; InCB; Linker # Mn TELUGU SIGN VIRAMA +0D4D ; InCB; Linker # Mn MALAYALAM SIGN VIRAMA + +# Total code points: 6 + +# ================================================ + +# Indic_Conjunct_Break=Consonant + +0915..0939 ; InCB; Consonant # Lo [37] DEVANAGARI LETTER KA..DEVANAGARI LETTER HA +0958..095F ; InCB; Consonant # Lo [8] DEVANAGARI LETTER QA..DEVANAGARI LETTER YYA +0978..097F ; InCB; Consonant # Lo [8] DEVANAGARI LETTER MARWARI DDA..DEVANAGARI LETTER BBA +0995..09A8 ; InCB; Consonant # Lo [20] BENGALI LETTER KA..BENGALI LETTER NA +09AA..09B0 ; InCB; Consonant # Lo [7] BENGALI LETTER PA..BENGALI LETTER RA +09B2 ; InCB; Consonant # Lo BENGALI LETTER LA +09B6..09B9 ; InCB; Consonant # Lo [4] BENGALI LETTER SHA..BENGALI LETTER HA +09DC..09DD ; InCB; Consonant # Lo [2] BENGALI LETTER RRA..BENGALI LETTER RHA +09DF ; InCB; Consonant # Lo BENGALI LETTER YYA +09F0..09F1 ; InCB; Consonant # Lo [2] BENGALI LETTER RA WITH MIDDLE DIAGONAL..BENGALI LETTER RA WITH LOWER DIAGONAL +0A95..0AA8 ; InCB; Consonant # Lo [20] GUJARATI LETTER KA..GUJARATI LETTER NA +0AAA..0AB0 ; InCB; Consonant # Lo [7] GUJARATI LETTER PA..GUJARATI LETTER RA +0AB2..0AB3 ; InCB; Consonant # Lo [2] GUJARATI LETTER LA..GUJARATI LETTER LLA +0AB5..0AB9 ; InCB; Consonant # Lo [5] GUJARATI LETTER VA..GUJARATI LETTER HA +0AF9 ; InCB; Consonant # Lo GUJARATI LETTER ZHA +0B15..0B28 ; InCB; Consonant # Lo [20] ORIYA LETTER KA..ORIYA LETTER NA +0B2A..0B30 ; InCB; Consonant # Lo [7] ORIYA LETTER PA..ORIYA LETTER RA +0B32..0B33 ; InCB; Consonant # Lo [2] ORIYA LETTER LA..ORIYA LETTER LLA +0B35..0B39 ; InCB; Consonant # Lo [5] ORIYA LETTER VA..ORIYA LETTER HA +0B5C..0B5D ; InCB; Consonant # Lo [2] ORIYA LETTER RRA..ORIYA LETTER RHA +0B5F ; InCB; Consonant # Lo ORIYA LETTER YYA +0B71 ; InCB; Consonant # Lo ORIYA LETTER WA +0C15..0C28 ; InCB; Consonant # Lo [20] TELUGU LETTER KA..TELUGU LETTER NA +0C2A..0C39 ; InCB; Consonant # Lo [16] TELUGU LETTER PA..TELUGU LETTER HA +0C58..0C5A ; InCB; Consonant # Lo [3] TELUGU LETTER TSA..TELUGU LETTER RRRA +0D15..0D3A ; InCB; Consonant # Lo [38] MALAYALAM LETTER KA..MALAYALAM LETTER TTTA + +# Total code points: 240 + +# ================================================ + +# Indic_Conjunct_Break=Extend + +0300..034E ; InCB; Extend # Mn [79] COMBINING GRAVE ACCENT..COMBINING UPWARDS ARROW BELOW +0350..036F ; InCB; Extend # Mn [32] COMBINING RIGHT ARROWHEAD ABOVE..COMBINING LATIN SMALL LETTER X +0483..0487 ; InCB; Extend # Mn [5] COMBINING CYRILLIC TITLO..COMBINING CYRILLIC POKRYTIE +0591..05BD ; InCB; Extend # Mn [45] HEBREW ACCENT ETNAHTA..HEBREW POINT METEG +05BF ; InCB; Extend # Mn HEBREW POINT RAFE +05C1..05C2 ; InCB; Extend # Mn [2] HEBREW POINT SHIN DOT..HEBREW POINT SIN DOT +05C4..05C5 ; InCB; Extend # Mn [2] HEBREW MARK UPPER DOT..HEBREW MARK LOWER DOT +05C7 ; InCB; Extend # Mn HEBREW POINT QAMATS QATAN +0610..061A ; InCB; Extend # Mn [11] ARABIC SIGN SALLALLAHOU ALAYHE WASSALLAM..ARABIC SMALL KASRA +064B..065F ; InCB; Extend # Mn [21] ARABIC FATHATAN..ARABIC WAVY HAMZA BELOW +0670 ; InCB; Extend # Mn ARABIC LETTER SUPERSCRIPT ALEF +06D6..06DC ; InCB; Extend # Mn [7] ARABIC SMALL HIGH LIGATURE SAD WITH LAM WITH ALEF MAKSURA..ARABIC SMALL HIGH SEEN +06DF..06E4 ; InCB; Extend # Mn [6] ARABIC SMALL HIGH ROUNDED ZERO..ARABIC SMALL HIGH MADDA +06E7..06E8 ; InCB; Extend # Mn [2] ARABIC SMALL HIGH YEH..ARABIC SMALL HIGH NOON +06EA..06ED ; InCB; Extend # Mn [4] ARABIC EMPTY CENTRE LOW STOP..ARABIC SMALL LOW MEEM +0711 ; InCB; Extend # Mn SYRIAC LETTER SUPERSCRIPT ALAPH +0730..074A ; InCB; Extend # Mn [27] SYRIAC PTHAHA ABOVE..SYRIAC BARREKH +07EB..07F3 ; InCB; Extend # Mn [9] NKO COMBINING SHORT HIGH TONE..NKO COMBINING DOUBLE DOT ABOVE +07FD ; InCB; Extend # Mn NKO DANTAYALAN +0816..0819 ; InCB; Extend # Mn [4] SAMARITAN MARK IN..SAMARITAN MARK DAGESH +081B..0823 ; InCB; Extend # Mn [9] SAMARITAN MARK EPENTHETIC YUT..SAMARITAN VOWEL SIGN A +0825..0827 ; InCB; Extend # Mn [3] SAMARITAN VOWEL SIGN SHORT A..SAMARITAN VOWEL SIGN U +0829..082D ; InCB; Extend # Mn [5] SAMARITAN VOWEL SIGN LONG I..SAMARITAN MARK NEQUDAA +0859..085B ; InCB; Extend # Mn [3] MANDAIC AFFRICATION MARK..MANDAIC GEMINATION MARK +0898..089F ; InCB; Extend # Mn [8] ARABIC SMALL HIGH WORD AL-JUZ..ARABIC HALF MADDA OVER MADDA +08CA..08E1 ; InCB; Extend # Mn [24] ARABIC SMALL HIGH FARSI YEH..ARABIC SMALL HIGH SIGN SAFHA +08E3..08FF ; InCB; Extend # Mn [29] ARABIC TURNED DAMMA BELOW..ARABIC MARK SIDEWAYS NOON GHUNNA +093C ; InCB; Extend # Mn DEVANAGARI SIGN NUKTA +0951..0954 ; InCB; Extend # Mn [4] DEVANAGARI STRESS SIGN UDATTA..DEVANAGARI ACUTE ACCENT +09BC ; InCB; Extend # Mn BENGALI SIGN NUKTA +09FE ; InCB; Extend # Mn BENGALI SANDHI MARK +0A3C ; InCB; Extend # Mn GURMUKHI SIGN NUKTA +0ABC ; InCB; Extend # Mn GUJARATI SIGN NUKTA +0B3C ; InCB; Extend # Mn ORIYA SIGN NUKTA +0C3C ; InCB; Extend # Mn TELUGU SIGN NUKTA +0C55..0C56 ; InCB; Extend # Mn [2] TELUGU LENGTH MARK..TELUGU AI LENGTH MARK +0CBC ; InCB; Extend # Mn KANNADA SIGN NUKTA +0D3B..0D3C ; InCB; Extend # Mn [2] MALAYALAM SIGN VERTICAL BAR VIRAMA..MALAYALAM SIGN CIRCULAR VIRAMA +0E38..0E3A ; InCB; Extend # Mn [3] THAI CHARACTER SARA U..THAI CHARACTER PHINTHU +0E48..0E4B ; InCB; Extend # Mn [4] THAI CHARACTER MAI EK..THAI CHARACTER MAI CHATTAWA +0EB8..0EBA ; InCB; Extend # Mn [3] LAO VOWEL SIGN U..LAO SIGN PALI VIRAMA +0EC8..0ECB ; InCB; Extend # Mn [4] LAO TONE MAI EK..LAO TONE MAI CATAWA +0F18..0F19 ; InCB; Extend # Mn [2] TIBETAN ASTROLOGICAL SIGN -KHYUD PA..TIBETAN ASTROLOGICAL SIGN SDONG TSHUGS +0F35 ; InCB; Extend # Mn TIBETAN MARK NGAS BZUNG NYI ZLA +0F37 ; InCB; Extend # Mn TIBETAN MARK NGAS BZUNG SGOR RTAGS +0F39 ; InCB; Extend # Mn TIBETAN MARK TSA -PHRU +0F71..0F72 ; InCB; Extend # Mn [2] TIBETAN VOWEL SIGN AA..TIBETAN VOWEL SIGN I +0F74 ; InCB; Extend # Mn TIBETAN VOWEL SIGN U +0F7A..0F7D ; InCB; Extend # Mn [4] TIBETAN VOWEL SIGN E..TIBETAN VOWEL SIGN OO +0F80 ; InCB; Extend # Mn TIBETAN VOWEL SIGN REVERSED I +0F82..0F84 ; InCB; Extend # Mn [3] TIBETAN SIGN NYI ZLA NAA DA..TIBETAN MARK HALANTA +0F86..0F87 ; InCB; Extend # Mn [2] TIBETAN SIGN LCI RTAGS..TIBETAN SIGN YANG RTAGS +0FC6 ; InCB; Extend # Mn TIBETAN SYMBOL PADMA GDAN +1037 ; InCB; Extend # Mn MYANMAR SIGN DOT BELOW +1039..103A ; InCB; Extend # Mn [2] MYANMAR SIGN VIRAMA..MYANMAR SIGN ASAT +108D ; InCB; Extend # Mn MYANMAR SIGN SHAN COUNCIL EMPHATIC TONE +135D..135F ; InCB; Extend # Mn [3] ETHIOPIC COMBINING GEMINATION AND VOWEL LENGTH MARK..ETHIOPIC COMBINING GEMINATION MARK +1714 ; InCB; Extend # Mn TAGALOG SIGN VIRAMA +17D2 ; InCB; Extend # Mn KHMER SIGN COENG +17DD ; InCB; Extend # Mn KHMER SIGN ATTHACAN +18A9 ; InCB; Extend # Mn MONGOLIAN LETTER ALI GALI DAGALGA +1939..193B ; InCB; Extend # Mn [3] LIMBU SIGN MUKPHRENG..LIMBU SIGN SA-I +1A17..1A18 ; InCB; Extend # Mn [2] BUGINESE VOWEL SIGN I..BUGINESE VOWEL SIGN U +1A60 ; InCB; Extend # Mn TAI THAM SIGN SAKOT +1A75..1A7C ; InCB; Extend # Mn [8] TAI THAM SIGN TONE-1..TAI THAM SIGN KHUEN-LUE KARAN +1A7F ; InCB; Extend # Mn TAI THAM COMBINING CRYPTOGRAMMIC DOT +1AB0..1ABD ; InCB; Extend # Mn [14] COMBINING DOUBLED CIRCUMFLEX ACCENT..COMBINING PARENTHESES BELOW +1ABF..1ACE ; InCB; Extend # Mn [16] COMBINING LATIN SMALL LETTER W BELOW..COMBINING LATIN SMALL LETTER INSULAR T +1B34 ; InCB; Extend # Mn BALINESE SIGN REREKAN +1B6B..1B73 ; InCB; Extend # Mn [9] BALINESE MUSICAL SYMBOL COMBINING TEGEH..BALINESE MUSICAL SYMBOL COMBINING GONG +1BAB ; InCB; Extend # Mn SUNDANESE SIGN VIRAMA +1BE6 ; InCB; Extend # Mn BATAK SIGN TOMPI +1C37 ; InCB; Extend # Mn LEPCHA SIGN NUKTA +1CD0..1CD2 ; InCB; Extend # Mn [3] VEDIC TONE KARSHANA..VEDIC TONE PRENKHA +1CD4..1CE0 ; InCB; Extend # Mn [13] VEDIC SIGN YAJURVEDIC MIDLINE SVARITA..VEDIC TONE RIGVEDIC KASHMIRI INDEPENDENT SVARITA +1CE2..1CE8 ; InCB; Extend # Mn [7] VEDIC SIGN VISARGA SVARITA..VEDIC SIGN VISARGA ANUDATTA WITH TAIL +1CED ; InCB; Extend # Mn VEDIC SIGN TIRYAK +1CF4 ; InCB; Extend # Mn VEDIC TONE CANDRA ABOVE +1CF8..1CF9 ; InCB; Extend # Mn [2] VEDIC TONE RING ABOVE..VEDIC TONE DOUBLE RING ABOVE +1DC0..1DFF ; InCB; Extend # Mn [64] COMBINING DOTTED GRAVE ACCENT..COMBINING RIGHT ARROWHEAD AND DOWN ARROWHEAD BELOW +200D ; InCB; Extend # Cf ZERO WIDTH JOINER +20D0..20DC ; InCB; Extend # Mn [13] COMBINING LEFT HARPOON ABOVE..COMBINING FOUR DOTS ABOVE +20E1 ; InCB; Extend # Mn COMBINING LEFT RIGHT ARROW ABOVE +20E5..20F0 ; InCB; Extend # Mn [12] COMBINING REVERSE SOLIDUS OVERLAY..COMBINING ASTERISK ABOVE +2CEF..2CF1 ; InCB; Extend # Mn [3] COPTIC COMBINING NI ABOVE..COPTIC COMBINING SPIRITUS LENIS +2D7F ; InCB; Extend # Mn TIFINAGH CONSONANT JOINER +2DE0..2DFF ; InCB; Extend # Mn [32] COMBINING CYRILLIC LETTER BE..COMBINING CYRILLIC LETTER IOTIFIED BIG YUS +302A..302D ; InCB; Extend # Mn [4] IDEOGRAPHIC LEVEL TONE MARK..IDEOGRAPHIC ENTERING TONE MARK +302E..302F ; InCB; Extend # Mc [2] HANGUL SINGLE DOT TONE MARK..HANGUL DOUBLE DOT TONE MARK +3099..309A ; InCB; Extend # Mn [2] COMBINING KATAKANA-HIRAGANA VOICED SOUND MARK..COMBINING KATAKANA-HIRAGANA SEMI-VOICED SOUND MARK +A66F ; InCB; Extend # Mn COMBINING CYRILLIC VZMET +A674..A67D ; InCB; Extend # Mn [10] COMBINING CYRILLIC LETTER UKRAINIAN IE..COMBINING CYRILLIC PAYEROK +A69E..A69F ; InCB; Extend # Mn [2] COMBINING CYRILLIC LETTER EF..COMBINING CYRILLIC LETTER IOTIFIED E +A6F0..A6F1 ; InCB; Extend # Mn [2] BAMUM COMBINING MARK KOQNDON..BAMUM COMBINING MARK TUKWENTIS +A82C ; InCB; Extend # Mn SYLOTI NAGRI SIGN ALTERNATE HASANTA +A8E0..A8F1 ; InCB; Extend # Mn [18] COMBINING DEVANAGARI DIGIT ZERO..COMBINING DEVANAGARI SIGN AVAGRAHA +A92B..A92D ; InCB; Extend # Mn [3] KAYAH LI TONE PLOPHU..KAYAH LI TONE CALYA PLOPHU +A9B3 ; InCB; Extend # Mn JAVANESE SIGN CECAK TELU +AAB0 ; InCB; Extend # Mn TAI VIET MAI KANG +AAB2..AAB4 ; InCB; Extend # Mn [3] TAI VIET VOWEL I..TAI VIET VOWEL U +AAB7..AAB8 ; InCB; Extend # Mn [2] TAI VIET MAI KHIT..TAI VIET VOWEL IA +AABE..AABF ; InCB; Extend # Mn [2] TAI VIET VOWEL AM..TAI VIET TONE MAI EK +AAC1 ; InCB; Extend # Mn TAI VIET TONE MAI THO +AAF6 ; InCB; Extend # Mn MEETEI MAYEK VIRAMA +ABED ; InCB; Extend # Mn MEETEI MAYEK APUN IYEK +FB1E ; InCB; Extend # Mn HEBREW POINT JUDEO-SPANISH VARIKA +FE20..FE2F ; InCB; Extend # Mn [16] COMBINING LIGATURE LEFT HALF..COMBINING CYRILLIC TITLO RIGHT HALF +101FD ; InCB; Extend # Mn PHAISTOS DISC SIGN COMBINING OBLIQUE STROKE +102E0 ; InCB; Extend # Mn COPTIC EPACT THOUSANDS MARK +10376..1037A ; InCB; Extend # Mn [5] COMBINING OLD PERMIC LETTER AN..COMBINING OLD PERMIC LETTER SII +10A0D ; InCB; Extend # Mn KHAROSHTHI SIGN DOUBLE RING BELOW +10A0F ; InCB; Extend # Mn KHAROSHTHI SIGN VISARGA +10A38..10A3A ; InCB; Extend # Mn [3] KHAROSHTHI SIGN BAR ABOVE..KHAROSHTHI SIGN DOT BELOW +10A3F ; InCB; Extend # Mn KHAROSHTHI VIRAMA +10AE5..10AE6 ; InCB; Extend # Mn [2] MANICHAEAN ABBREVIATION MARK ABOVE..MANICHAEAN ABBREVIATION MARK BELOW +10D24..10D27 ; InCB; Extend # Mn [4] HANIFI ROHINGYA SIGN HARBAHAY..HANIFI ROHINGYA SIGN TASSI +10EAB..10EAC ; InCB; Extend # Mn [2] YEZIDI COMBINING HAMZA MARK..YEZIDI COMBINING MADDA MARK +10EFD..10EFF ; InCB; Extend # Mn [3] ARABIC SMALL LOW WORD SAKTA..ARABIC SMALL LOW WORD MADDA +10F46..10F50 ; InCB; Extend # Mn [11] SOGDIAN COMBINING DOT BELOW..SOGDIAN COMBINING STROKE BELOW +10F82..10F85 ; InCB; Extend # Mn [4] OLD UYGHUR COMBINING DOT ABOVE..OLD UYGHUR COMBINING TWO DOTS BELOW +11070 ; InCB; Extend # Mn BRAHMI SIGN OLD TAMIL VIRAMA +1107F ; InCB; Extend # Mn BRAHMI NUMBER JOINER +110BA ; InCB; Extend # Mn KAITHI SIGN NUKTA +11100..11102 ; InCB; Extend # Mn [3] CHAKMA SIGN CANDRABINDU..CHAKMA SIGN VISARGA +11133..11134 ; InCB; Extend # Mn [2] CHAKMA VIRAMA..CHAKMA MAAYYAA +11173 ; InCB; Extend # Mn MAHAJANI SIGN NUKTA +111CA ; InCB; Extend # Mn SHARADA SIGN NUKTA +11236 ; InCB; Extend # Mn KHOJKI SIGN NUKTA +112E9..112EA ; InCB; Extend # Mn [2] KHUDAWADI SIGN NUKTA..KHUDAWADI SIGN VIRAMA +1133B..1133C ; InCB; Extend # Mn [2] COMBINING BINDU BELOW..GRANTHA SIGN NUKTA +11366..1136C ; InCB; Extend # Mn [7] COMBINING GRANTHA DIGIT ZERO..COMBINING GRANTHA DIGIT SIX +11370..11374 ; InCB; Extend # Mn [5] COMBINING GRANTHA LETTER A..COMBINING GRANTHA LETTER PA +11446 ; InCB; Extend # Mn NEWA SIGN NUKTA +1145E ; InCB; Extend # Mn NEWA SANDHI MARK +114C3 ; InCB; Extend # Mn TIRHUTA SIGN NUKTA +115C0 ; InCB; Extend # Mn SIDDHAM SIGN NUKTA +116B7 ; InCB; Extend # Mn TAKRI SIGN NUKTA +1172B ; InCB; Extend # Mn AHOM SIGN KILLER +1183A ; InCB; Extend # Mn DOGRA SIGN NUKTA +1193E ; InCB; Extend # Mn DIVES AKURU VIRAMA +11943 ; InCB; Extend # Mn DIVES AKURU SIGN NUKTA +11A34 ; InCB; Extend # Mn ZANABAZAR SQUARE SIGN VIRAMA +11A47 ; InCB; Extend # Mn ZANABAZAR SQUARE SUBJOINER +11A99 ; InCB; Extend # Mn SOYOMBO SUBJOINER +11D42 ; InCB; Extend # Mn MASARAM GONDI SIGN NUKTA +11D44..11D45 ; InCB; Extend # Mn [2] MASARAM GONDI SIGN HALANTA..MASARAM GONDI VIRAMA +11D97 ; InCB; Extend # Mn GUNJALA GONDI VIRAMA +11F42 ; InCB; Extend # Mn KAWI CONJOINER +16AF0..16AF4 ; InCB; Extend # Mn [5] BASSA VAH COMBINING HIGH TONE..BASSA VAH COMBINING HIGH-LOW TONE +16B30..16B36 ; InCB; Extend # Mn [7] PAHAWH HMONG MARK CIM TUB..PAHAWH HMONG MARK CIM TAUM +1BC9E ; InCB; Extend # Mn DUPLOYAN DOUBLE MARK +1D165 ; InCB; Extend # Mc MUSICAL SYMBOL COMBINING STEM +1D167..1D169 ; InCB; Extend # Mn [3] MUSICAL SYMBOL COMBINING TREMOLO-1..MUSICAL SYMBOL COMBINING TREMOLO-3 +1D16E..1D172 ; InCB; Extend # Mc [5] MUSICAL SYMBOL COMBINING FLAG-1..MUSICAL SYMBOL COMBINING FLAG-5 +1D17B..1D182 ; InCB; Extend # Mn [8] MUSICAL SYMBOL COMBINING ACCENT..MUSICAL SYMBOL COMBINING LOURE +1D185..1D18B ; InCB; Extend # Mn [7] MUSICAL SYMBOL COMBINING DOIT..MUSICAL SYMBOL COMBINING TRIPLE TONGUE +1D1AA..1D1AD ; InCB; Extend # Mn [4] MUSICAL SYMBOL COMBINING DOWN BOW..MUSICAL SYMBOL COMBINING SNAP PIZZICATO +1D242..1D244 ; InCB; Extend # Mn [3] COMBINING GREEK MUSICAL TRISEME..COMBINING GREEK MUSICAL PENTASEME +1E000..1E006 ; InCB; Extend # Mn [7] COMBINING GLAGOLITIC LETTER AZU..COMBINING GLAGOLITIC LETTER ZHIVETE +1E008..1E018 ; InCB; Extend # Mn [17] COMBINING GLAGOLITIC LETTER ZEMLJA..COMBINING GLAGOLITIC LETTER HERU +1E01B..1E021 ; InCB; Extend # Mn [7] COMBINING GLAGOLITIC LETTER SHTA..COMBINING GLAGOLITIC LETTER YATI +1E023..1E024 ; InCB; Extend # Mn [2] COMBINING GLAGOLITIC LETTER YU..COMBINING GLAGOLITIC LETTER SMALL YUS +1E026..1E02A ; InCB; Extend # Mn [5] COMBINING GLAGOLITIC LETTER YO..COMBINING GLAGOLITIC LETTER FITA +1E08F ; InCB; Extend # Mn COMBINING CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I +1E130..1E136 ; InCB; Extend # Mn [7] NYIAKENG PUACHUE HMONG TONE-B..NYIAKENG PUACHUE HMONG TONE-D +1E2AE ; InCB; Extend # Mn TOTO SIGN RISING TONE +1E2EC..1E2EF ; InCB; Extend # Mn [4] WANCHO TONE TUP..WANCHO TONE KOINI +1E4EC..1E4EF ; InCB; Extend # Mn [4] NAG MUNDARI SIGN MUHOR..NAG MUNDARI SIGN SUTUH +1E8D0..1E8D6 ; InCB; Extend # Mn [7] MENDE KIKAKUI COMBINING NUMBER TEENS..MENDE KIKAKUI COMBINING NUMBER MILLIONS +1E944..1E94A ; InCB; Extend # Mn [7] ADLAM ALIF LENGTHENER..ADLAM NUKTA + +# Total code points: 884 + # EOF diff --git a/libcxx/utils/data/unicode/DerivedGeneralCategory.txt b/libcxx/utils/data/unicode/DerivedGeneralCategory.txt index c6013ef25d83..285ffa8fb83a 100644 --- a/libcxx/utils/data/unicode/DerivedGeneralCategory.txt +++ b/libcxx/utils/data/unicode/DerivedGeneralCategory.txt @@ -1,6 +1,6 @@ -# DerivedGeneralCategory-15.0.0.txt -# Date: 2022-04-26, 23:14:35 GMT -# © 2022 Unicode®, Inc. +# DerivedGeneralCategory-15.1.0.txt +# Date: 2023-07-28, 23:34:02 GMT +# © 2023 Unicode®, Inc. # Unicode and the Unicode Logo are registered trademarks of Unicode, Inc. in the U.S. and other countries. # For terms of use, see https://www.unicode.org/terms_of_use.html # @@ -284,13 +284,12 @@ 2E9A ; Cn # 2EF4..2EFF ; Cn # [12] .. 2FD6..2FEF ; Cn # [26] .. -2FFC..2FFF ; Cn # [4] .. 3040 ; Cn # 3097..3098 ; Cn # [2] .. 3100..3104 ; Cn # [5] .. 3130 ; Cn # 318F ; Cn # -31E4..31EF ; Cn # [12] .. +31E4..31EE ; Cn # [11] .. 321F ; Cn # A48D..A48F ; Cn # [3] .. A4C7..A4CF ; Cn # [9] .. @@ -713,7 +712,8 @@ FFFE..FFFF ; Cn # [2] .. 2B73A..2B73F ; Cn # [6] .. 2B81E..2B81F ; Cn # [2] .. 2CEA2..2CEAF ; Cn # [14] .. -2EBE1..2F7FF ; Cn # [3103] .. +2EBE1..2EBEF ; Cn # [15] .. +2EE5E..2F7FF ; Cn # [2466] .. 2FA1E..2FFFF ; Cn # [1506] .. 3134B..3134F ; Cn # [5] .. 323B0..E0000 ; Cn # [711761] .. @@ -723,7 +723,7 @@ E01F0..EFFFF ; Cn # [65040] .. FFFFE..FFFFF ; Cn # [2] .. 10FFFE..10FFFF; Cn # [2] .. -# Total code points: 825345 +# Total code points: 824718 # ================================================ @@ -2649,11 +2649,12 @@ FFDA..FFDC ; Lo # [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGUL LETTER I 2B740..2B81D ; Lo # [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D 2B820..2CEA1 ; Lo # [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 2CEB0..2EBE0 ; Lo # [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBF0..2EE5D ; Lo # [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D 2F800..2FA1D ; Lo # [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D 30000..3134A ; Lo # [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A 31350..323AF ; Lo # [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF -# Total code points: 131612 +# Total code points: 132234 # ================================================ @@ -4092,7 +4093,7 @@ FFE3 ; Sk # FULLWIDTH MACRON 2E80..2E99 ; So # [26] CJK RADICAL REPEAT..CJK RADICAL RAP 2E9B..2EF3 ; So # [89] CJK RADICAL CHOKE..CJK RADICAL C-SIMPLIFIED TURTLE 2F00..2FD5 ; So # [214] KANGXI RADICAL ONE..KANGXI RADICAL FLUTE -2FF0..2FFB ; So # [12] IDEOGRAPHIC DESCRIPTION CHARACTER LEFT TO RIGHT..IDEOGRAPHIC DESCRIPTION CHARACTER OVERLAID +2FF0..2FFF ; So # [16] IDEOGRAPHIC DESCRIPTION CHARACTER LEFT TO RIGHT..IDEOGRAPHIC DESCRIPTION CHARACTER ROTATION 3004 ; So # JAPANESE INDUSTRIAL STANDARD SYMBOL 3012..3013 ; So # [2] POSTAL MARK..GETA MARK 3020 ; So # POSTAL MARK FACE @@ -4101,6 +4102,7 @@ FFE3 ; Sk # FULLWIDTH MACRON 3190..3191 ; So # [2] IDEOGRAPHIC ANNOTATION LINKING MARK..IDEOGRAPHIC ANNOTATION REVERSE MARK 3196..319F ; So # [10] IDEOGRAPHIC ANNOTATION TOP MARK..IDEOGRAPHIC ANNOTATION MAN MARK 31C0..31E3 ; So # [36] CJK STROKE T..CJK STROKE Q +31EF ; So # IDEOGRAPHIC DESCRIPTION CHARACTER SUBTRACTION 3200..321E ; So # [31] PARENTHESIZED HANGUL KIYEOK..PARENTHESIZED KOREAN CHARACTER O HU 322A..3247 ; So # [30] PARENTHESIZED IDEOGRAPH MOON..CIRCLED IDEOGRAPH KOTO 3250 ; So # PARTNERSHIP SIGN @@ -4191,7 +4193,7 @@ FFFC..FFFD ; So # [2] OBJECT REPLACEMENT CHARACTER..REPLACEMENT CHARACTER 1FB00..1FB92 ; So # [147] BLOCK SEXTANT-1..UPPER HALF INVERSE MEDIUM SHADE AND LOWER HALF BLOCK 1FB94..1FBCA ; So # [55] LEFT HALF INVERSE MEDIUM SHADE AND RIGHT HALF BLOCK..WHITE UP-POINTING CHEVRON -# Total code points: 6634 +# Total code points: 6639 # ================================================ diff --git a/libcxx/utils/data/unicode/EastAsianWidth.txt b/libcxx/utils/data/unicode/EastAsianWidth.txt index 38b7076c02f7..02df4df475cb 100644 --- a/libcxx/utils/data/unicode/EastAsianWidth.txt +++ b/libcxx/utils/data/unicode/EastAsianWidth.txt @@ -1,11 +1,11 @@ -# EastAsianWidth-15.0.0.txt -# Date: 2022-05-24, 17:40:20 GMT [KW, LI] -# © 2022 Unicode®, Inc. +# EastAsianWidth-15.1.0.txt +# Date: 2023-07-28, 23:34:08 GMT +# © 2023 Unicode®, Inc. # Unicode and the Unicode Logo are registered trademarks of Unicode, Inc. in the U.S. and other countries. # For terms of use, see https://www.unicode.org/terms_of_use.html # # Unicode Character Database -# For documentation, see https://www.unicode.org/reports/tr44/ +# For documentation, see https://www.unicode.org/reports/tr44/ # # East_Asian_Width Property # @@ -30,2590 +30,2592 @@ # Character ranges are specified as for other property files in the # Unicode Character Database. # -# For legacy reasons, there are no spaces before or after the semicolon -# which separates the two fields. The comments following the number sign -# "#" list the General_Category property value or the L& alias of the -# derived value LC, the Unicode character name or names, and, in lines -# with ranges of code points, the code point count in square brackets. +# The comments following the number sign "#" list the General_Category +# property value or the L& alias of the derived value LC, the Unicode +# character name or names, and, in lines with ranges of code points, +# the code point count in square brackets. # # For more information, see UAX #11: East Asian Width, # at https://www.unicode.org/reports/tr11/ # # @missing: 0000..10FFFF; N -0000..001F;N # Cc [32] .. -0020;Na # Zs SPACE -0021..0023;Na # Po [3] EXCLAMATION MARK..NUMBER SIGN -0024;Na # Sc DOLLAR SIGN -0025..0027;Na # Po [3] PERCENT SIGN..APOSTROPHE -0028;Na # Ps LEFT PARENTHESIS -0029;Na # Pe RIGHT PARENTHESIS -002A;Na # Po ASTERISK -002B;Na # Sm PLUS SIGN -002C;Na # Po COMMA -002D;Na # Pd HYPHEN-MINUS -002E..002F;Na # Po [2] FULL STOP..SOLIDUS -0030..0039;Na # Nd [10] DIGIT ZERO..DIGIT NINE -003A..003B;Na # Po [2] COLON..SEMICOLON -003C..003E;Na # Sm [3] LESS-THAN SIGN..GREATER-THAN SIGN -003F..0040;Na # Po [2] QUESTION MARK..COMMERCIAL AT -0041..005A;Na # Lu [26] LATIN CAPITAL LETTER A..LATIN CAPITAL LETTER Z -005B;Na # Ps LEFT SQUARE BRACKET -005C;Na # Po REVERSE SOLIDUS -005D;Na # Pe RIGHT SQUARE BRACKET -005E;Na # Sk CIRCUMFLEX ACCENT -005F;Na # Pc LOW LINE -0060;Na # Sk GRAVE ACCENT -0061..007A;Na # Ll [26] LATIN SMALL LETTER A..LATIN SMALL LETTER Z -007B;Na # Ps LEFT CURLY BRACKET -007C;Na # Sm VERTICAL LINE -007D;Na # Pe RIGHT CURLY BRACKET -007E;Na # Sm TILDE -007F;N # Cc -0080..009F;N # Cc [32] .. -00A0;N # Zs NO-BREAK SPACE -00A1;A # Po INVERTED EXCLAMATION MARK -00A2..00A3;Na # Sc [2] CENT SIGN..POUND SIGN -00A4;A # Sc CURRENCY SIGN -00A5;Na # Sc YEN SIGN -00A6;Na # So BROKEN BAR -00A7;A # Po SECTION SIGN -00A8;A # Sk DIAERESIS -00A9;N # So COPYRIGHT SIGN -00AA;A # Lo FEMININE ORDINAL INDICATOR -00AB;N # Pi LEFT-POINTING DOUBLE ANGLE QUOTATION MARK -00AC;Na # Sm NOT SIGN -00AD;A # Cf SOFT HYPHEN -00AE;A # So REGISTERED SIGN -00AF;Na # Sk MACRON -00B0;A # So DEGREE SIGN -00B1;A # Sm PLUS-MINUS SIGN -00B2..00B3;A # No [2] SUPERSCRIPT TWO..SUPERSCRIPT THREE -00B4;A # Sk ACUTE ACCENT -00B5;N # Ll MICRO SIGN -00B6..00B7;A # Po [2] PILCROW SIGN..MIDDLE DOT -00B8;A # Sk CEDILLA -00B9;A # No SUPERSCRIPT ONE -00BA;A # Lo MASCULINE ORDINAL INDICATOR -00BB;N # Pf RIGHT-POINTING DOUBLE ANGLE QUOTATION MARK -00BC..00BE;A # No [3] VULGAR FRACTION ONE QUARTER..VULGAR FRACTION THREE QUARTERS -00BF;A # Po INVERTED QUESTION MARK -00C0..00C5;N # Lu [6] LATIN CAPITAL LETTER A WITH GRAVE..LATIN CAPITAL LETTER A WITH RING ABOVE -00C6;A # Lu LATIN CAPITAL LETTER AE -00C7..00CF;N # Lu [9] LATIN CAPITAL LETTER C WITH CEDILLA..LATIN CAPITAL LETTER I WITH DIAERESIS -00D0;A # Lu LATIN CAPITAL LETTER ETH -00D1..00D6;N # Lu [6] LATIN CAPITAL LETTER N WITH TILDE..LATIN CAPITAL LETTER O WITH DIAERESIS -00D7;A # Sm MULTIPLICATION SIGN -00D8;A # Lu LATIN CAPITAL LETTER O WITH STROKE -00D9..00DD;N # Lu [5] LATIN CAPITAL LETTER U WITH GRAVE..LATIN CAPITAL LETTER Y WITH ACUTE -00DE..00E1;A # L& [4] LATIN CAPITAL LETTER THORN..LATIN SMALL LETTER A WITH ACUTE -00E2..00E5;N # Ll [4] LATIN SMALL LETTER A WITH CIRCUMFLEX..LATIN SMALL LETTER A WITH RING ABOVE -00E6;A # Ll LATIN SMALL LETTER AE -00E7;N # Ll LATIN SMALL LETTER C WITH CEDILLA -00E8..00EA;A # Ll [3] LATIN SMALL LETTER E WITH GRAVE..LATIN SMALL LETTER E WITH CIRCUMFLEX -00EB;N # Ll LATIN SMALL LETTER E WITH DIAERESIS -00EC..00ED;A # Ll [2] LATIN SMALL LETTER I WITH GRAVE..LATIN SMALL LETTER I WITH ACUTE -00EE..00EF;N # Ll [2] LATIN SMALL LETTER I WITH CIRCUMFLEX..LATIN SMALL LETTER I WITH DIAERESIS -00F0;A # Ll LATIN SMALL LETTER ETH -00F1;N # Ll LATIN SMALL LETTER N WITH TILDE -00F2..00F3;A # Ll [2] LATIN SMALL LETTER O WITH GRAVE..LATIN SMALL LETTER O WITH ACUTE -00F4..00F6;N # Ll [3] LATIN SMALL LETTER O WITH CIRCUMFLEX..LATIN SMALL LETTER O WITH DIAERESIS -00F7;A # Sm DIVISION SIGN -00F8..00FA;A # Ll [3] LATIN SMALL LETTER O WITH STROKE..LATIN SMALL LETTER U WITH ACUTE -00FB;N # Ll LATIN SMALL LETTER U WITH CIRCUMFLEX -00FC;A # Ll LATIN SMALL LETTER U WITH DIAERESIS -00FD;N # Ll LATIN SMALL LETTER Y WITH ACUTE -00FE;A # Ll LATIN SMALL LETTER THORN -00FF;N # Ll LATIN SMALL LETTER Y WITH DIAERESIS -0100;N # Lu LATIN CAPITAL LETTER A WITH MACRON -0101;A # Ll LATIN SMALL LETTER A WITH MACRON -0102..0110;N # L& [15] LATIN CAPITAL LETTER A WITH BREVE..LATIN CAPITAL LETTER D WITH STROKE -0111;A # Ll LATIN SMALL LETTER D WITH STROKE -0112;N # Lu LATIN CAPITAL LETTER E WITH MACRON -0113;A # Ll LATIN SMALL LETTER E WITH MACRON -0114..011A;N # L& [7] LATIN CAPITAL LETTER E WITH BREVE..LATIN CAPITAL LETTER E WITH CARON -011B;A # Ll LATIN SMALL LETTER E WITH CARON -011C..0125;N # L& [10] LATIN CAPITAL LETTER G WITH CIRCUMFLEX..LATIN SMALL LETTER H WITH CIRCUMFLEX -0126..0127;A # L& [2] LATIN CAPITAL LETTER H WITH STROKE..LATIN SMALL LETTER H WITH STROKE -0128..012A;N # L& [3] LATIN CAPITAL LETTER I WITH TILDE..LATIN CAPITAL LETTER I WITH MACRON -012B;A # Ll LATIN SMALL LETTER I WITH MACRON -012C..0130;N # L& [5] LATIN CAPITAL LETTER I WITH BREVE..LATIN CAPITAL LETTER I WITH DOT ABOVE -0131..0133;A # L& [3] LATIN SMALL LETTER DOTLESS I..LATIN SMALL LIGATURE IJ -0134..0137;N # L& [4] LATIN CAPITAL LETTER J WITH CIRCUMFLEX..LATIN SMALL LETTER K WITH CEDILLA -0138;A # Ll LATIN SMALL LETTER KRA -0139..013E;N # L& [6] LATIN CAPITAL LETTER L WITH ACUTE..LATIN SMALL LETTER L WITH CARON -013F..0142;A # L& [4] LATIN CAPITAL LETTER L WITH MIDDLE DOT..LATIN SMALL LETTER L WITH STROKE -0143;N # Lu LATIN CAPITAL LETTER N WITH ACUTE -0144;A # Ll LATIN SMALL LETTER N WITH ACUTE -0145..0147;N # L& [3] LATIN CAPITAL LETTER N WITH CEDILLA..LATIN CAPITAL LETTER N WITH CARON -0148..014B;A # L& [4] LATIN SMALL LETTER N WITH CARON..LATIN SMALL LETTER ENG -014C;N # Lu LATIN CAPITAL LETTER O WITH MACRON -014D;A # Ll LATIN SMALL LETTER O WITH MACRON -014E..0151;N # L& [4] LATIN CAPITAL LETTER O WITH BREVE..LATIN SMALL LETTER O WITH DOUBLE ACUTE -0152..0153;A # L& [2] LATIN CAPITAL LIGATURE OE..LATIN SMALL LIGATURE OE -0154..0165;N # L& [18] LATIN CAPITAL LETTER R WITH ACUTE..LATIN SMALL LETTER T WITH CARON -0166..0167;A # L& [2] LATIN CAPITAL LETTER T WITH STROKE..LATIN SMALL LETTER T WITH STROKE -0168..016A;N # L& [3] LATIN CAPITAL LETTER U WITH TILDE..LATIN CAPITAL LETTER U WITH MACRON -016B;A # Ll LATIN SMALL LETTER U WITH MACRON -016C..017F;N # L& [20] LATIN CAPITAL LETTER U WITH BREVE..LATIN SMALL LETTER LONG S -0180..01BA;N # L& [59] LATIN SMALL LETTER B WITH STROKE..LATIN SMALL LETTER EZH WITH TAIL -01BB;N # Lo LATIN LETTER TWO WITH STROKE -01BC..01BF;N # L& [4] LATIN CAPITAL LETTER TONE FIVE..LATIN LETTER WYNN -01C0..01C3;N # Lo [4] LATIN LETTER DENTAL CLICK..LATIN LETTER RETROFLEX CLICK -01C4..01CD;N # L& [10] LATIN CAPITAL LETTER DZ WITH CARON..LATIN CAPITAL LETTER A WITH CARON -01CE;A # Ll LATIN SMALL LETTER A WITH CARON -01CF;N # Lu LATIN CAPITAL LETTER I WITH CARON -01D0;A # Ll LATIN SMALL LETTER I WITH CARON -01D1;N # Lu LATIN CAPITAL LETTER O WITH CARON -01D2;A # Ll LATIN SMALL LETTER O WITH CARON -01D3;N # Lu LATIN CAPITAL LETTER U WITH CARON -01D4;A # Ll LATIN SMALL LETTER U WITH CARON -01D5;N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND MACRON -01D6;A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND MACRON -01D7;N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND ACUTE -01D8;A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND ACUTE -01D9;N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND CARON -01DA;A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND CARON -01DB;N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND GRAVE -01DC;A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND GRAVE -01DD..024F;N # L& [115] LATIN SMALL LETTER TURNED E..LATIN SMALL LETTER Y WITH STROKE -0250;N # Ll LATIN SMALL LETTER TURNED A -0251;A # Ll LATIN SMALL LETTER ALPHA -0252..0260;N # Ll [15] LATIN SMALL LETTER TURNED ALPHA..LATIN SMALL LETTER G WITH HOOK -0261;A # Ll LATIN SMALL LETTER SCRIPT G -0262..0293;N # Ll [50] LATIN LETTER SMALL CAPITAL G..LATIN SMALL LETTER EZH WITH CURL -0294;N # Lo LATIN LETTER GLOTTAL STOP -0295..02AF;N # Ll [27] LATIN LETTER PHARYNGEAL VOICED FRICATIVE..LATIN SMALL LETTER TURNED H WITH FISHHOOK AND TAIL -02B0..02C1;N # Lm [18] MODIFIER LETTER SMALL H..MODIFIER LETTER REVERSED GLOTTAL STOP -02C2..02C3;N # Sk [2] MODIFIER LETTER LEFT ARROWHEAD..MODIFIER LETTER RIGHT ARROWHEAD -02C4;A # Sk MODIFIER LETTER UP ARROWHEAD -02C5;N # Sk MODIFIER LETTER DOWN ARROWHEAD -02C6;N # Lm MODIFIER LETTER CIRCUMFLEX ACCENT -02C7;A # Lm CARON -02C8;N # Lm MODIFIER LETTER VERTICAL LINE -02C9..02CB;A # Lm [3] MODIFIER LETTER MACRON..MODIFIER LETTER GRAVE ACCENT -02CC;N # Lm MODIFIER LETTER LOW VERTICAL LINE -02CD;A # Lm MODIFIER LETTER LOW MACRON -02CE..02CF;N # Lm [2] MODIFIER LETTER LOW GRAVE ACCENT..MODIFIER LETTER LOW ACUTE ACCENT -02D0;A # Lm MODIFIER LETTER TRIANGULAR COLON -02D1;N # Lm MODIFIER LETTER HALF TRIANGULAR COLON -02D2..02D7;N # Sk [6] MODIFIER LETTER CENTRED RIGHT HALF RING..MODIFIER LETTER MINUS SIGN -02D8..02DB;A # Sk [4] BREVE..OGONEK -02DC;N # Sk SMALL TILDE -02DD;A # Sk DOUBLE ACUTE ACCENT -02DE;N # Sk MODIFIER LETTER RHOTIC HOOK -02DF;A # Sk MODIFIER LETTER CROSS ACCENT -02E0..02E4;N # Lm [5] MODIFIER LETTER SMALL GAMMA..MODIFIER LETTER SMALL REVERSED GLOTTAL STOP -02E5..02EB;N # Sk [7] MODIFIER LETTER EXTRA-HIGH TONE BAR..MODIFIER LETTER YANG DEPARTING TONE MARK -02EC;N # Lm MODIFIER LETTER VOICING -02ED;N # Sk MODIFIER LETTER UNASPIRATED -02EE;N # Lm MODIFIER LETTER DOUBLE APOSTROPHE -02EF..02FF;N # Sk [17] MODIFIER LETTER LOW DOWN ARROWHEAD..MODIFIER LETTER LOW LEFT ARROW -0300..036F;A # Mn [112] COMBINING GRAVE ACCENT..COMBINING LATIN SMALL LETTER X -0370..0373;N # L& [4] GREEK CAPITAL LETTER HETA..GREEK SMALL LETTER ARCHAIC SAMPI -0374;N # Lm GREEK NUMERAL SIGN -0375;N # Sk GREEK LOWER NUMERAL SIGN -0376..0377;N # L& [2] GREEK CAPITAL LETTER PAMPHYLIAN DIGAMMA..GREEK SMALL LETTER PAMPHYLIAN DIGAMMA -037A;N # Lm GREEK YPOGEGRAMMENI -037B..037D;N # Ll [3] GREEK SMALL REVERSED LUNATE SIGMA SYMBOL..GREEK SMALL REVERSED DOTTED LUNATE SIGMA SYMBOL -037E;N # Po GREEK QUESTION MARK -037F;N # Lu GREEK CAPITAL LETTER YOT -0384..0385;N # Sk [2] GREEK TONOS..GREEK DIALYTIKA TONOS -0386;N # Lu GREEK CAPITAL LETTER ALPHA WITH TONOS -0387;N # Po GREEK ANO TELEIA -0388..038A;N # Lu [3] GREEK CAPITAL LETTER EPSILON WITH TONOS..GREEK CAPITAL LETTER IOTA WITH TONOS -038C;N # Lu GREEK CAPITAL LETTER OMICRON WITH TONOS -038E..0390;N # L& [3] GREEK CAPITAL LETTER UPSILON WITH TONOS..GREEK SMALL LETTER IOTA WITH DIALYTIKA AND TONOS -0391..03A1;A # Lu [17] GREEK CAPITAL LETTER ALPHA..GREEK CAPITAL LETTER RHO -03A3..03A9;A # Lu [7] GREEK CAPITAL LETTER SIGMA..GREEK CAPITAL LETTER OMEGA -03AA..03B0;N # L& [7] GREEK CAPITAL LETTER IOTA WITH DIALYTIKA..GREEK SMALL LETTER UPSILON WITH DIALYTIKA AND TONOS -03B1..03C1;A # Ll [17] GREEK SMALL LETTER ALPHA..GREEK SMALL LETTER RHO -03C2;N # Ll GREEK SMALL LETTER FINAL SIGMA -03C3..03C9;A # Ll [7] GREEK SMALL LETTER SIGMA..GREEK SMALL LETTER OMEGA -03CA..03F5;N # L& [44] GREEK SMALL LETTER IOTA WITH DIALYTIKA..GREEK LUNATE EPSILON SYMBOL -03F6;N # Sm GREEK REVERSED LUNATE EPSILON SYMBOL -03F7..03FF;N # L& [9] GREEK CAPITAL LETTER SHO..GREEK CAPITAL REVERSED DOTTED LUNATE SIGMA SYMBOL -0400;N # Lu CYRILLIC CAPITAL LETTER IE WITH GRAVE -0401;A # Lu CYRILLIC CAPITAL LETTER IO -0402..040F;N # Lu [14] CYRILLIC CAPITAL LETTER DJE..CYRILLIC CAPITAL LETTER DZHE -0410..044F;A # L& [64] CYRILLIC CAPITAL LETTER A..CYRILLIC SMALL LETTER YA -0450;N # Ll CYRILLIC SMALL LETTER IE WITH GRAVE -0451;A # Ll CYRILLIC SMALL LETTER IO -0452..0481;N # L& [48] CYRILLIC SMALL LETTER DJE..CYRILLIC SMALL LETTER KOPPA -0482;N # So CYRILLIC THOUSANDS SIGN -0483..0487;N # Mn [5] COMBINING CYRILLIC TITLO..COMBINING CYRILLIC POKRYTIE -0488..0489;N # Me [2] COMBINING CYRILLIC HUNDRED THOUSANDS SIGN..COMBINING CYRILLIC MILLIONS SIGN -048A..04FF;N # L& [118] CYRILLIC CAPITAL LETTER SHORT I WITH TAIL..CYRILLIC SMALL LETTER HA WITH STROKE -0500..052F;N # L& [48] CYRILLIC CAPITAL LETTER KOMI DE..CYRILLIC SMALL LETTER EL WITH DESCENDER -0531..0556;N # Lu [38] ARMENIAN CAPITAL LETTER AYB..ARMENIAN CAPITAL LETTER FEH -0559;N # Lm ARMENIAN MODIFIER LETTER LEFT HALF RING -055A..055F;N # Po [6] ARMENIAN APOSTROPHE..ARMENIAN ABBREVIATION MARK -0560..0588;N # Ll [41] ARMENIAN SMALL LETTER TURNED AYB..ARMENIAN SMALL LETTER YI WITH STROKE -0589;N # Po ARMENIAN FULL STOP -058A;N # Pd ARMENIAN HYPHEN -058D..058E;N # So [2] RIGHT-FACING ARMENIAN ETERNITY SIGN..LEFT-FACING ARMENIAN ETERNITY SIGN -058F;N # Sc ARMENIAN DRAM SIGN -0591..05BD;N # Mn [45] HEBREW ACCENT ETNAHTA..HEBREW POINT METEG -05BE;N # Pd HEBREW PUNCTUATION MAQAF -05BF;N # Mn HEBREW POINT RAFE -05C0;N # Po HEBREW PUNCTUATION PASEQ -05C1..05C2;N # Mn [2] HEBREW POINT SHIN DOT..HEBREW POINT SIN DOT -05C3;N # Po HEBREW PUNCTUATION SOF PASUQ -05C4..05C5;N # Mn [2] HEBREW MARK UPPER DOT..HEBREW MARK LOWER DOT -05C6;N # Po HEBREW PUNCTUATION NUN HAFUKHA -05C7;N # Mn HEBREW POINT QAMATS QATAN -05D0..05EA;N # Lo [27] HEBREW LETTER ALEF..HEBREW LETTER TAV -05EF..05F2;N # Lo [4] HEBREW YOD TRIANGLE..HEBREW LIGATURE YIDDISH DOUBLE YOD -05F3..05F4;N # Po [2] HEBREW PUNCTUATION GERESH..HEBREW PUNCTUATION GERSHAYIM -0600..0605;N # Cf [6] ARABIC NUMBER SIGN..ARABIC NUMBER MARK ABOVE -0606..0608;N # Sm [3] ARABIC-INDIC CUBE ROOT..ARABIC RAY -0609..060A;N # Po [2] ARABIC-INDIC PER MILLE SIGN..ARABIC-INDIC PER TEN THOUSAND SIGN -060B;N # Sc AFGHANI SIGN -060C..060D;N # Po [2] ARABIC COMMA..ARABIC DATE SEPARATOR -060E..060F;N # So [2] ARABIC POETIC VERSE SIGN..ARABIC SIGN MISRA -0610..061A;N # Mn [11] ARABIC SIGN SALLALLAHOU ALAYHE WASSALLAM..ARABIC SMALL KASRA -061B;N # Po ARABIC SEMICOLON -061C;N # Cf ARABIC LETTER MARK -061D..061F;N # Po [3] ARABIC END OF TEXT MARK..ARABIC QUESTION MARK -0620..063F;N # Lo [32] ARABIC LETTER KASHMIRI YEH..ARABIC LETTER FARSI YEH WITH THREE DOTS ABOVE -0640;N # Lm ARABIC TATWEEL -0641..064A;N # Lo [10] ARABIC LETTER FEH..ARABIC LETTER YEH -064B..065F;N # Mn [21] ARABIC FATHATAN..ARABIC WAVY HAMZA BELOW -0660..0669;N # Nd [10] ARABIC-INDIC DIGIT ZERO..ARABIC-INDIC DIGIT NINE -066A..066D;N # Po [4] ARABIC PERCENT SIGN..ARABIC FIVE POINTED STAR -066E..066F;N # Lo [2] ARABIC LETTER DOTLESS BEH..ARABIC LETTER DOTLESS QAF -0670;N # Mn ARABIC LETTER SUPERSCRIPT ALEF -0671..06D3;N # Lo [99] ARABIC LETTER ALEF WASLA..ARABIC LETTER YEH BARREE WITH HAMZA ABOVE -06D4;N # Po ARABIC FULL STOP -06D5;N # Lo ARABIC LETTER AE -06D6..06DC;N # Mn [7] ARABIC SMALL HIGH LIGATURE SAD WITH LAM WITH ALEF MAKSURA..ARABIC SMALL HIGH SEEN -06DD;N # Cf ARABIC END OF AYAH -06DE;N # So ARABIC START OF RUB EL HIZB -06DF..06E4;N # Mn [6] ARABIC SMALL HIGH ROUNDED ZERO..ARABIC SMALL HIGH MADDA -06E5..06E6;N # Lm [2] ARABIC SMALL WAW..ARABIC SMALL YEH -06E7..06E8;N # Mn [2] ARABIC SMALL HIGH YEH..ARABIC SMALL HIGH NOON -06E9;N # So ARABIC PLACE OF SAJDAH -06EA..06ED;N # Mn [4] ARABIC EMPTY CENTRE LOW STOP..ARABIC SMALL LOW MEEM -06EE..06EF;N # Lo [2] ARABIC LETTER DAL WITH INVERTED V..ARABIC LETTER REH WITH INVERTED V -06F0..06F9;N # Nd [10] EXTENDED ARABIC-INDIC DIGIT ZERO..EXTENDED ARABIC-INDIC DIGIT NINE -06FA..06FC;N # Lo [3] ARABIC LETTER SHEEN WITH DOT BELOW..ARABIC LETTER GHAIN WITH DOT BELOW -06FD..06FE;N # So [2] ARABIC SIGN SINDHI AMPERSAND..ARABIC SIGN SINDHI POSTPOSITION MEN -06FF;N # Lo ARABIC LETTER HEH WITH INVERTED V -0700..070D;N # Po [14] SYRIAC END OF PARAGRAPH..SYRIAC HARKLEAN ASTERISCUS -070F;N # Cf SYRIAC ABBREVIATION MARK -0710;N # Lo SYRIAC LETTER ALAPH -0711;N # Mn SYRIAC LETTER SUPERSCRIPT ALAPH -0712..072F;N # Lo [30] SYRIAC LETTER BETH..SYRIAC LETTER PERSIAN DHALATH -0730..074A;N # Mn [27] SYRIAC PTHAHA ABOVE..SYRIAC BARREKH -074D..074F;N # Lo [3] SYRIAC LETTER SOGDIAN ZHAIN..SYRIAC LETTER SOGDIAN FE -0750..077F;N # Lo [48] ARABIC LETTER BEH WITH THREE DOTS HORIZONTALLY BELOW..ARABIC LETTER KAF WITH TWO DOTS ABOVE -0780..07A5;N # Lo [38] THAANA LETTER HAA..THAANA LETTER WAAVU -07A6..07B0;N # Mn [11] THAANA ABAFILI..THAANA SUKUN -07B1;N # Lo THAANA LETTER NAA -07C0..07C9;N # Nd [10] NKO DIGIT ZERO..NKO DIGIT NINE -07CA..07EA;N # Lo [33] NKO LETTER A..NKO LETTER JONA RA -07EB..07F3;N # Mn [9] NKO COMBINING SHORT HIGH TONE..NKO COMBINING DOUBLE DOT ABOVE -07F4..07F5;N # Lm [2] NKO HIGH TONE APOSTROPHE..NKO LOW TONE APOSTROPHE -07F6;N # So NKO SYMBOL OO DENNEN -07F7..07F9;N # Po [3] NKO SYMBOL GBAKURUNEN..NKO EXCLAMATION MARK -07FA;N # Lm NKO LAJANYALAN -07FD;N # Mn NKO DANTAYALAN -07FE..07FF;N # Sc [2] NKO DOROME SIGN..NKO TAMAN SIGN -0800..0815;N # Lo [22] SAMARITAN LETTER ALAF..SAMARITAN LETTER TAAF -0816..0819;N # Mn [4] SAMARITAN MARK IN..SAMARITAN MARK DAGESH -081A;N # Lm SAMARITAN MODIFIER LETTER EPENTHETIC YUT -081B..0823;N # Mn [9] SAMARITAN MARK EPENTHETIC YUT..SAMARITAN VOWEL SIGN A -0824;N # Lm SAMARITAN MODIFIER LETTER SHORT A -0825..0827;N # Mn [3] SAMARITAN VOWEL SIGN SHORT A..SAMARITAN VOWEL SIGN U -0828;N # Lm SAMARITAN MODIFIER LETTER I -0829..082D;N # Mn [5] SAMARITAN VOWEL SIGN LONG I..SAMARITAN MARK NEQUDAA -0830..083E;N # Po [15] SAMARITAN PUNCTUATION NEQUDAA..SAMARITAN PUNCTUATION ANNAAU -0840..0858;N # Lo [25] MANDAIC LETTER HALQA..MANDAIC LETTER AIN -0859..085B;N # Mn [3] MANDAIC AFFRICATION MARK..MANDAIC GEMINATION MARK -085E;N # Po MANDAIC PUNCTUATION -0860..086A;N # Lo [11] SYRIAC LETTER MALAYALAM NGA..SYRIAC LETTER MALAYALAM SSA -0870..0887;N # Lo [24] ARABIC LETTER ALEF WITH ATTACHED FATHA..ARABIC BASELINE ROUND DOT -0888;N # Sk ARABIC RAISED ROUND DOT -0889..088E;N # Lo [6] ARABIC LETTER NOON WITH INVERTED SMALL V..ARABIC VERTICAL TAIL -0890..0891;N # Cf [2] ARABIC POUND MARK ABOVE..ARABIC PIASTRE MARK ABOVE -0898..089F;N # Mn [8] ARABIC SMALL HIGH WORD AL-JUZ..ARABIC HALF MADDA OVER MADDA -08A0..08C8;N # Lo [41] ARABIC LETTER BEH WITH SMALL V BELOW..ARABIC LETTER GRAF -08C9;N # Lm ARABIC SMALL FARSI YEH -08CA..08E1;N # Mn [24] ARABIC SMALL HIGH FARSI YEH..ARABIC SMALL HIGH SIGN SAFHA -08E2;N # Cf ARABIC DISPUTED END OF AYAH -08E3..08FF;N # Mn [29] ARABIC TURNED DAMMA BELOW..ARABIC MARK SIDEWAYS NOON GHUNNA -0900..0902;N # Mn [3] DEVANAGARI SIGN INVERTED CANDRABINDU..DEVANAGARI SIGN ANUSVARA -0903;N # Mc DEVANAGARI SIGN VISARGA -0904..0939;N # Lo [54] DEVANAGARI LETTER SHORT A..DEVANAGARI LETTER HA -093A;N # Mn DEVANAGARI VOWEL SIGN OE -093B;N # Mc DEVANAGARI VOWEL SIGN OOE -093C;N # Mn DEVANAGARI SIGN NUKTA -093D;N # Lo DEVANAGARI SIGN AVAGRAHA -093E..0940;N # Mc [3] DEVANAGARI VOWEL SIGN AA..DEVANAGARI VOWEL SIGN II -0941..0948;N # Mn [8] DEVANAGARI VOWEL SIGN U..DEVANAGARI VOWEL SIGN AI -0949..094C;N # Mc [4] DEVANAGARI VOWEL SIGN CANDRA O..DEVANAGARI VOWEL SIGN AU -094D;N # Mn DEVANAGARI SIGN VIRAMA -094E..094F;N # Mc [2] DEVANAGARI VOWEL SIGN PRISHTHAMATRA E..DEVANAGARI VOWEL SIGN AW -0950;N # Lo DEVANAGARI OM -0951..0957;N # Mn [7] DEVANAGARI STRESS SIGN UDATTA..DEVANAGARI VOWEL SIGN UUE -0958..0961;N # Lo [10] DEVANAGARI LETTER QA..DEVANAGARI LETTER VOCALIC LL -0962..0963;N # Mn [2] DEVANAGARI VOWEL SIGN VOCALIC L..DEVANAGARI VOWEL SIGN VOCALIC LL -0964..0965;N # Po [2] DEVANAGARI DANDA..DEVANAGARI DOUBLE DANDA -0966..096F;N # Nd [10] DEVANAGARI DIGIT ZERO..DEVANAGARI DIGIT NINE -0970;N # Po DEVANAGARI ABBREVIATION SIGN -0971;N # Lm DEVANAGARI SIGN HIGH SPACING DOT -0972..097F;N # Lo [14] DEVANAGARI LETTER CANDRA A..DEVANAGARI LETTER BBA -0980;N # Lo BENGALI ANJI -0981;N # Mn BENGALI SIGN CANDRABINDU -0982..0983;N # Mc [2] BENGALI SIGN ANUSVARA..BENGALI SIGN VISARGA -0985..098C;N # Lo [8] BENGALI LETTER A..BENGALI LETTER VOCALIC L -098F..0990;N # Lo [2] BENGALI LETTER E..BENGALI LETTER AI -0993..09A8;N # Lo [22] BENGALI LETTER O..BENGALI LETTER NA -09AA..09B0;N # Lo [7] BENGALI LETTER PA..BENGALI LETTER RA -09B2;N # Lo BENGALI LETTER LA -09B6..09B9;N # Lo [4] BENGALI LETTER SHA..BENGALI LETTER HA -09BC;N # Mn BENGALI SIGN NUKTA -09BD;N # Lo BENGALI SIGN AVAGRAHA -09BE..09C0;N # Mc [3] BENGALI VOWEL SIGN AA..BENGALI VOWEL SIGN II -09C1..09C4;N # Mn [4] BENGALI VOWEL SIGN U..BENGALI VOWEL SIGN VOCALIC RR -09C7..09C8;N # Mc [2] BENGALI VOWEL SIGN E..BENGALI VOWEL SIGN AI -09CB..09CC;N # Mc [2] BENGALI VOWEL SIGN O..BENGALI VOWEL SIGN AU -09CD;N # Mn BENGALI SIGN VIRAMA -09CE;N # Lo BENGALI LETTER KHANDA TA -09D7;N # Mc BENGALI AU LENGTH MARK -09DC..09DD;N # Lo [2] BENGALI LETTER RRA..BENGALI LETTER RHA -09DF..09E1;N # Lo [3] BENGALI LETTER YYA..BENGALI LETTER VOCALIC LL -09E2..09E3;N # Mn [2] BENGALI VOWEL SIGN VOCALIC L..BENGALI VOWEL SIGN VOCALIC LL -09E6..09EF;N # Nd [10] BENGALI DIGIT ZERO..BENGALI DIGIT NINE -09F0..09F1;N # Lo [2] BENGALI LETTER RA WITH MIDDLE DIAGONAL..BENGALI LETTER RA WITH LOWER DIAGONAL -09F2..09F3;N # Sc [2] BENGALI RUPEE MARK..BENGALI RUPEE SIGN -09F4..09F9;N # No [6] BENGALI CURRENCY NUMERATOR ONE..BENGALI CURRENCY DENOMINATOR SIXTEEN -09FA;N # So BENGALI ISSHAR -09FB;N # Sc BENGALI GANDA MARK -09FC;N # Lo BENGALI LETTER VEDIC ANUSVARA -09FD;N # Po BENGALI ABBREVIATION SIGN -09FE;N # Mn BENGALI SANDHI MARK -0A01..0A02;N # Mn [2] GURMUKHI SIGN ADAK BINDI..GURMUKHI SIGN BINDI -0A03;N # Mc GURMUKHI SIGN VISARGA -0A05..0A0A;N # Lo [6] GURMUKHI LETTER A..GURMUKHI LETTER UU -0A0F..0A10;N # Lo [2] GURMUKHI LETTER EE..GURMUKHI LETTER AI -0A13..0A28;N # Lo [22] GURMUKHI LETTER OO..GURMUKHI LETTER NA -0A2A..0A30;N # Lo [7] GURMUKHI LETTER PA..GURMUKHI LETTER RA -0A32..0A33;N # Lo [2] GURMUKHI LETTER LA..GURMUKHI LETTER LLA -0A35..0A36;N # Lo [2] GURMUKHI LETTER VA..GURMUKHI LETTER SHA -0A38..0A39;N # Lo [2] GURMUKHI LETTER SA..GURMUKHI LETTER HA -0A3C;N # Mn GURMUKHI SIGN NUKTA -0A3E..0A40;N # Mc [3] GURMUKHI VOWEL SIGN AA..GURMUKHI VOWEL SIGN II -0A41..0A42;N # Mn [2] GURMUKHI VOWEL SIGN U..GURMUKHI VOWEL SIGN UU -0A47..0A48;N # Mn [2] GURMUKHI VOWEL SIGN EE..GURMUKHI VOWEL SIGN AI -0A4B..0A4D;N # Mn [3] GURMUKHI VOWEL SIGN OO..GURMUKHI SIGN VIRAMA -0A51;N # Mn GURMUKHI SIGN UDAAT -0A59..0A5C;N # Lo [4] GURMUKHI LETTER KHHA..GURMUKHI LETTER RRA -0A5E;N # Lo GURMUKHI LETTER FA -0A66..0A6F;N # Nd [10] GURMUKHI DIGIT ZERO..GURMUKHI DIGIT NINE -0A70..0A71;N # Mn [2] GURMUKHI TIPPI..GURMUKHI ADDAK -0A72..0A74;N # Lo [3] GURMUKHI IRI..GURMUKHI EK ONKAR -0A75;N # Mn GURMUKHI SIGN YAKASH -0A76;N # Po GURMUKHI ABBREVIATION SIGN -0A81..0A82;N # Mn [2] GUJARATI SIGN CANDRABINDU..GUJARATI SIGN ANUSVARA -0A83;N # Mc GUJARATI SIGN VISARGA -0A85..0A8D;N # Lo [9] GUJARATI LETTER A..GUJARATI VOWEL CANDRA E -0A8F..0A91;N # Lo [3] GUJARATI LETTER E..GUJARATI VOWEL CANDRA O -0A93..0AA8;N # Lo [22] GUJARATI LETTER O..GUJARATI LETTER NA -0AAA..0AB0;N # Lo [7] GUJARATI LETTER PA..GUJARATI LETTER RA -0AB2..0AB3;N # Lo [2] GUJARATI LETTER LA..GUJARATI LETTER LLA -0AB5..0AB9;N # Lo [5] GUJARATI LETTER VA..GUJARATI LETTER HA -0ABC;N # Mn GUJARATI SIGN NUKTA -0ABD;N # Lo GUJARATI SIGN AVAGRAHA -0ABE..0AC0;N # Mc [3] GUJARATI VOWEL SIGN AA..GUJARATI VOWEL SIGN II -0AC1..0AC5;N # Mn [5] GUJARATI VOWEL SIGN U..GUJARATI VOWEL SIGN CANDRA E -0AC7..0AC8;N # Mn [2] GUJARATI VOWEL SIGN E..GUJARATI VOWEL SIGN AI -0AC9;N # Mc GUJARATI VOWEL SIGN CANDRA O -0ACB..0ACC;N # Mc [2] GUJARATI VOWEL SIGN O..GUJARATI VOWEL SIGN AU -0ACD;N # Mn GUJARATI SIGN VIRAMA -0AD0;N # Lo GUJARATI OM -0AE0..0AE1;N # Lo [2] GUJARATI LETTER VOCALIC RR..GUJARATI LETTER VOCALIC LL -0AE2..0AE3;N # Mn [2] GUJARATI VOWEL SIGN VOCALIC L..GUJARATI VOWEL SIGN VOCALIC LL -0AE6..0AEF;N # Nd [10] GUJARATI DIGIT ZERO..GUJARATI DIGIT NINE -0AF0;N # Po GUJARATI ABBREVIATION SIGN -0AF1;N # Sc GUJARATI RUPEE SIGN -0AF9;N # Lo GUJARATI LETTER ZHA -0AFA..0AFF;N # Mn [6] GUJARATI SIGN SUKUN..GUJARATI SIGN TWO-CIRCLE NUKTA ABOVE -0B01;N # Mn ORIYA SIGN CANDRABINDU -0B02..0B03;N # Mc [2] ORIYA SIGN ANUSVARA..ORIYA SIGN VISARGA -0B05..0B0C;N # Lo [8] ORIYA LETTER A..ORIYA LETTER VOCALIC L -0B0F..0B10;N # Lo [2] ORIYA LETTER E..ORIYA LETTER AI -0B13..0B28;N # Lo [22] ORIYA LETTER O..ORIYA LETTER NA -0B2A..0B30;N # Lo [7] ORIYA LETTER PA..ORIYA LETTER RA -0B32..0B33;N # Lo [2] ORIYA LETTER LA..ORIYA LETTER LLA -0B35..0B39;N # Lo [5] ORIYA LETTER VA..ORIYA LETTER HA -0B3C;N # Mn ORIYA SIGN NUKTA -0B3D;N # Lo ORIYA SIGN AVAGRAHA -0B3E;N # Mc ORIYA VOWEL SIGN AA -0B3F;N # Mn ORIYA VOWEL SIGN I -0B40;N # Mc ORIYA VOWEL SIGN II -0B41..0B44;N # Mn [4] ORIYA VOWEL SIGN U..ORIYA VOWEL SIGN VOCALIC RR -0B47..0B48;N # Mc [2] ORIYA VOWEL SIGN E..ORIYA VOWEL SIGN AI -0B4B..0B4C;N # Mc [2] ORIYA VOWEL SIGN O..ORIYA VOWEL SIGN AU -0B4D;N # Mn ORIYA SIGN VIRAMA -0B55..0B56;N # Mn [2] ORIYA SIGN OVERLINE..ORIYA AI LENGTH MARK -0B57;N # Mc ORIYA AU LENGTH MARK -0B5C..0B5D;N # Lo [2] ORIYA LETTER RRA..ORIYA LETTER RHA -0B5F..0B61;N # Lo [3] ORIYA LETTER YYA..ORIYA LETTER VOCALIC LL -0B62..0B63;N # Mn [2] ORIYA VOWEL SIGN VOCALIC L..ORIYA VOWEL SIGN VOCALIC LL -0B66..0B6F;N # Nd [10] ORIYA DIGIT ZERO..ORIYA DIGIT NINE -0B70;N # So ORIYA ISSHAR -0B71;N # Lo ORIYA LETTER WA -0B72..0B77;N # No [6] ORIYA FRACTION ONE QUARTER..ORIYA FRACTION THREE SIXTEENTHS -0B82;N # Mn TAMIL SIGN ANUSVARA -0B83;N # Lo TAMIL SIGN VISARGA -0B85..0B8A;N # Lo [6] TAMIL LETTER A..TAMIL LETTER UU -0B8E..0B90;N # Lo [3] TAMIL LETTER E..TAMIL LETTER AI -0B92..0B95;N # Lo [4] TAMIL LETTER O..TAMIL LETTER KA -0B99..0B9A;N # Lo [2] TAMIL LETTER NGA..TAMIL LETTER CA -0B9C;N # Lo TAMIL LETTER JA -0B9E..0B9F;N # Lo [2] TAMIL LETTER NYA..TAMIL LETTER TTA -0BA3..0BA4;N # Lo [2] TAMIL LETTER NNA..TAMIL LETTER TA -0BA8..0BAA;N # Lo [3] TAMIL LETTER NA..TAMIL LETTER PA -0BAE..0BB9;N # Lo [12] TAMIL LETTER MA..TAMIL LETTER HA -0BBE..0BBF;N # Mc [2] TAMIL VOWEL SIGN AA..TAMIL VOWEL SIGN I -0BC0;N # Mn TAMIL VOWEL SIGN II -0BC1..0BC2;N # Mc [2] TAMIL VOWEL SIGN U..TAMIL VOWEL SIGN UU -0BC6..0BC8;N # Mc [3] TAMIL VOWEL SIGN E..TAMIL VOWEL SIGN AI -0BCA..0BCC;N # Mc [3] TAMIL VOWEL SIGN O..TAMIL VOWEL SIGN AU -0BCD;N # Mn TAMIL SIGN VIRAMA -0BD0;N # Lo TAMIL OM -0BD7;N # Mc TAMIL AU LENGTH MARK -0BE6..0BEF;N # Nd [10] TAMIL DIGIT ZERO..TAMIL DIGIT NINE -0BF0..0BF2;N # No [3] TAMIL NUMBER TEN..TAMIL NUMBER ONE THOUSAND -0BF3..0BF8;N # So [6] TAMIL DAY SIGN..TAMIL AS ABOVE SIGN -0BF9;N # Sc TAMIL RUPEE SIGN -0BFA;N # So TAMIL NUMBER SIGN -0C00;N # Mn TELUGU SIGN COMBINING CANDRABINDU ABOVE -0C01..0C03;N # Mc [3] TELUGU SIGN CANDRABINDU..TELUGU SIGN VISARGA -0C04;N # Mn TELUGU SIGN COMBINING ANUSVARA ABOVE -0C05..0C0C;N # Lo [8] TELUGU LETTER A..TELUGU LETTER VOCALIC L -0C0E..0C10;N # Lo [3] TELUGU LETTER E..TELUGU LETTER AI -0C12..0C28;N # Lo [23] TELUGU LETTER O..TELUGU LETTER NA -0C2A..0C39;N # Lo [16] TELUGU LETTER PA..TELUGU LETTER HA -0C3C;N # Mn TELUGU SIGN NUKTA -0C3D;N # Lo TELUGU SIGN AVAGRAHA -0C3E..0C40;N # Mn [3] TELUGU VOWEL SIGN AA..TELUGU VOWEL SIGN II -0C41..0C44;N # Mc [4] TELUGU VOWEL SIGN U..TELUGU VOWEL SIGN VOCALIC RR -0C46..0C48;N # Mn [3] TELUGU VOWEL SIGN E..TELUGU VOWEL SIGN AI -0C4A..0C4D;N # Mn [4] TELUGU VOWEL SIGN O..TELUGU SIGN VIRAMA -0C55..0C56;N # Mn [2] TELUGU LENGTH MARK..TELUGU AI LENGTH MARK -0C58..0C5A;N # Lo [3] TELUGU LETTER TSA..TELUGU LETTER RRRA -0C5D;N # Lo TELUGU LETTER NAKAARA POLLU -0C60..0C61;N # Lo [2] TELUGU LETTER VOCALIC RR..TELUGU LETTER VOCALIC LL -0C62..0C63;N # Mn [2] TELUGU VOWEL SIGN VOCALIC L..TELUGU VOWEL SIGN VOCALIC LL -0C66..0C6F;N # Nd [10] TELUGU DIGIT ZERO..TELUGU DIGIT NINE -0C77;N # Po TELUGU SIGN SIDDHAM -0C78..0C7E;N # No [7] TELUGU FRACTION DIGIT ZERO FOR ODD POWERS OF FOUR..TELUGU FRACTION DIGIT THREE FOR EVEN POWERS OF FOUR -0C7F;N # So TELUGU SIGN TUUMU -0C80;N # Lo KANNADA SIGN SPACING CANDRABINDU -0C81;N # Mn KANNADA SIGN CANDRABINDU -0C82..0C83;N # Mc [2] KANNADA SIGN ANUSVARA..KANNADA SIGN VISARGA -0C84;N # Po KANNADA SIGN SIDDHAM -0C85..0C8C;N # Lo [8] KANNADA LETTER A..KANNADA LETTER VOCALIC L -0C8E..0C90;N # Lo [3] KANNADA LETTER E..KANNADA LETTER AI -0C92..0CA8;N # Lo [23] KANNADA LETTER O..KANNADA LETTER NA -0CAA..0CB3;N # Lo [10] KANNADA LETTER PA..KANNADA LETTER LLA -0CB5..0CB9;N # Lo [5] KANNADA LETTER VA..KANNADA LETTER HA -0CBC;N # Mn KANNADA SIGN NUKTA -0CBD;N # Lo KANNADA SIGN AVAGRAHA -0CBE;N # Mc KANNADA VOWEL SIGN AA -0CBF;N # Mn KANNADA VOWEL SIGN I -0CC0..0CC4;N # Mc [5] KANNADA VOWEL SIGN II..KANNADA VOWEL SIGN VOCALIC RR -0CC6;N # Mn KANNADA VOWEL SIGN E -0CC7..0CC8;N # Mc [2] KANNADA VOWEL SIGN EE..KANNADA VOWEL SIGN AI -0CCA..0CCB;N # Mc [2] KANNADA VOWEL SIGN O..KANNADA VOWEL SIGN OO -0CCC..0CCD;N # Mn [2] KANNADA VOWEL SIGN AU..KANNADA SIGN VIRAMA -0CD5..0CD6;N # Mc [2] KANNADA LENGTH MARK..KANNADA AI LENGTH MARK -0CDD..0CDE;N # Lo [2] KANNADA LETTER NAKAARA POLLU..KANNADA LETTER FA -0CE0..0CE1;N # Lo [2] KANNADA LETTER VOCALIC RR..KANNADA LETTER VOCALIC LL -0CE2..0CE3;N # Mn [2] KANNADA VOWEL SIGN VOCALIC L..KANNADA VOWEL SIGN VOCALIC LL -0CE6..0CEF;N # Nd [10] KANNADA DIGIT ZERO..KANNADA DIGIT NINE -0CF1..0CF2;N # Lo [2] KANNADA SIGN JIHVAMULIYA..KANNADA SIGN UPADHMANIYA -0CF3;N # Mc KANNADA SIGN COMBINING ANUSVARA ABOVE RIGHT -0D00..0D01;N # Mn [2] MALAYALAM SIGN COMBINING ANUSVARA ABOVE..MALAYALAM SIGN CANDRABINDU -0D02..0D03;N # Mc [2] MALAYALAM SIGN ANUSVARA..MALAYALAM SIGN VISARGA -0D04..0D0C;N # Lo [9] MALAYALAM LETTER VEDIC ANUSVARA..MALAYALAM LETTER VOCALIC L -0D0E..0D10;N # Lo [3] MALAYALAM LETTER E..MALAYALAM LETTER AI -0D12..0D3A;N # Lo [41] MALAYALAM LETTER O..MALAYALAM LETTER TTTA -0D3B..0D3C;N # Mn [2] MALAYALAM SIGN VERTICAL BAR VIRAMA..MALAYALAM SIGN CIRCULAR VIRAMA -0D3D;N # Lo MALAYALAM SIGN AVAGRAHA -0D3E..0D40;N # Mc [3] MALAYALAM VOWEL SIGN AA..MALAYALAM VOWEL SIGN II -0D41..0D44;N # Mn [4] MALAYALAM VOWEL SIGN U..MALAYALAM VOWEL SIGN VOCALIC RR -0D46..0D48;N # Mc [3] MALAYALAM VOWEL SIGN E..MALAYALAM VOWEL SIGN AI -0D4A..0D4C;N # Mc [3] MALAYALAM VOWEL SIGN O..MALAYALAM VOWEL SIGN AU -0D4D;N # Mn MALAYALAM SIGN VIRAMA -0D4E;N # Lo MALAYALAM LETTER DOT REPH -0D4F;N # So MALAYALAM SIGN PARA -0D54..0D56;N # Lo [3] MALAYALAM LETTER CHILLU M..MALAYALAM LETTER CHILLU LLL -0D57;N # Mc MALAYALAM AU LENGTH MARK -0D58..0D5E;N # No [7] MALAYALAM FRACTION ONE ONE-HUNDRED-AND-SIXTIETH..MALAYALAM FRACTION ONE FIFTH -0D5F..0D61;N # Lo [3] MALAYALAM LETTER ARCHAIC II..MALAYALAM LETTER VOCALIC LL -0D62..0D63;N # Mn [2] MALAYALAM VOWEL SIGN VOCALIC L..MALAYALAM VOWEL SIGN VOCALIC LL -0D66..0D6F;N # Nd [10] MALAYALAM DIGIT ZERO..MALAYALAM DIGIT NINE -0D70..0D78;N # No [9] MALAYALAM NUMBER TEN..MALAYALAM FRACTION THREE SIXTEENTHS -0D79;N # So MALAYALAM DATE MARK -0D7A..0D7F;N # Lo [6] MALAYALAM LETTER CHILLU NN..MALAYALAM LETTER CHILLU K -0D81;N # Mn SINHALA SIGN CANDRABINDU -0D82..0D83;N # Mc [2] SINHALA SIGN ANUSVARAYA..SINHALA SIGN VISARGAYA -0D85..0D96;N # Lo [18] SINHALA LETTER AYANNA..SINHALA LETTER AUYANNA -0D9A..0DB1;N # Lo [24] SINHALA LETTER ALPAPRAANA KAYANNA..SINHALA LETTER DANTAJA NAYANNA -0DB3..0DBB;N # Lo [9] SINHALA LETTER SANYAKA DAYANNA..SINHALA LETTER RAYANNA -0DBD;N # Lo SINHALA LETTER DANTAJA LAYANNA -0DC0..0DC6;N # Lo [7] SINHALA LETTER VAYANNA..SINHALA LETTER FAYANNA -0DCA;N # Mn SINHALA SIGN AL-LAKUNA -0DCF..0DD1;N # Mc [3] SINHALA VOWEL SIGN AELA-PILLA..SINHALA VOWEL SIGN DIGA AEDA-PILLA -0DD2..0DD4;N # Mn [3] SINHALA VOWEL SIGN KETTI IS-PILLA..SINHALA VOWEL SIGN KETTI PAA-PILLA -0DD6;N # Mn SINHALA VOWEL SIGN DIGA PAA-PILLA -0DD8..0DDF;N # Mc [8] SINHALA VOWEL SIGN GAETTA-PILLA..SINHALA VOWEL SIGN GAYANUKITTA -0DE6..0DEF;N # Nd [10] SINHALA LITH DIGIT ZERO..SINHALA LITH DIGIT NINE -0DF2..0DF3;N # Mc [2] SINHALA VOWEL SIGN DIGA GAETTA-PILLA..SINHALA VOWEL SIGN DIGA GAYANUKITTA -0DF4;N # Po SINHALA PUNCTUATION KUNDDALIYA -0E01..0E30;N # Lo [48] THAI CHARACTER KO KAI..THAI CHARACTER SARA A -0E31;N # Mn THAI CHARACTER MAI HAN-AKAT -0E32..0E33;N # Lo [2] THAI CHARACTER SARA AA..THAI CHARACTER SARA AM -0E34..0E3A;N # Mn [7] THAI CHARACTER SARA I..THAI CHARACTER PHINTHU -0E3F;N # Sc THAI CURRENCY SYMBOL BAHT -0E40..0E45;N # Lo [6] THAI CHARACTER SARA E..THAI CHARACTER LAKKHANGYAO -0E46;N # Lm THAI CHARACTER MAIYAMOK -0E47..0E4E;N # Mn [8] THAI CHARACTER MAITAIKHU..THAI CHARACTER YAMAKKAN -0E4F;N # Po THAI CHARACTER FONGMAN -0E50..0E59;N # Nd [10] THAI DIGIT ZERO..THAI DIGIT NINE -0E5A..0E5B;N # Po [2] THAI CHARACTER ANGKHANKHU..THAI CHARACTER KHOMUT -0E81..0E82;N # Lo [2] LAO LETTER KO..LAO LETTER KHO SUNG -0E84;N # Lo LAO LETTER KHO TAM -0E86..0E8A;N # Lo [5] LAO LETTER PALI GHA..LAO LETTER SO TAM -0E8C..0EA3;N # Lo [24] LAO LETTER PALI JHA..LAO LETTER LO LING -0EA5;N # Lo LAO LETTER LO LOOT -0EA7..0EB0;N # Lo [10] LAO LETTER WO..LAO VOWEL SIGN A -0EB1;N # Mn LAO VOWEL SIGN MAI KAN -0EB2..0EB3;N # Lo [2] LAO VOWEL SIGN AA..LAO VOWEL SIGN AM -0EB4..0EBC;N # Mn [9] LAO VOWEL SIGN I..LAO SEMIVOWEL SIGN LO -0EBD;N # Lo LAO SEMIVOWEL SIGN NYO -0EC0..0EC4;N # Lo [5] LAO VOWEL SIGN E..LAO VOWEL SIGN AI -0EC6;N # Lm LAO KO LA -0EC8..0ECE;N # Mn [7] LAO TONE MAI EK..LAO YAMAKKAN -0ED0..0ED9;N # Nd [10] LAO DIGIT ZERO..LAO DIGIT NINE -0EDC..0EDF;N # Lo [4] LAO HO NO..LAO LETTER KHMU NYO -0F00;N # Lo TIBETAN SYLLABLE OM -0F01..0F03;N # So [3] TIBETAN MARK GTER YIG MGO TRUNCATED A..TIBETAN MARK GTER YIG MGO -UM GTER TSHEG MA -0F04..0F12;N # Po [15] TIBETAN MARK INITIAL YIG MGO MDUN MA..TIBETAN MARK RGYA GRAM SHAD -0F13;N # So TIBETAN MARK CARET -DZUD RTAGS ME LONG CAN -0F14;N # Po TIBETAN MARK GTER TSHEG -0F15..0F17;N # So [3] TIBETAN LOGOTYPE SIGN CHAD RTAGS..TIBETAN ASTROLOGICAL SIGN SGRA GCAN -CHAR RTAGS -0F18..0F19;N # Mn [2] TIBETAN ASTROLOGICAL SIGN -KHYUD PA..TIBETAN ASTROLOGICAL SIGN SDONG TSHUGS -0F1A..0F1F;N # So [6] TIBETAN SIGN RDEL DKAR GCIG..TIBETAN SIGN RDEL DKAR RDEL NAG -0F20..0F29;N # Nd [10] TIBETAN DIGIT ZERO..TIBETAN DIGIT NINE -0F2A..0F33;N # No [10] TIBETAN DIGIT HALF ONE..TIBETAN DIGIT HALF ZERO -0F34;N # So TIBETAN MARK BSDUS RTAGS -0F35;N # Mn TIBETAN MARK NGAS BZUNG NYI ZLA -0F36;N # So TIBETAN MARK CARET -DZUD RTAGS BZHI MIG CAN -0F37;N # Mn TIBETAN MARK NGAS BZUNG SGOR RTAGS -0F38;N # So TIBETAN MARK CHE MGO -0F39;N # Mn TIBETAN MARK TSA -PHRU -0F3A;N # Ps TIBETAN MARK GUG RTAGS GYON -0F3B;N # Pe TIBETAN MARK GUG RTAGS GYAS -0F3C;N # Ps TIBETAN MARK ANG KHANG GYON -0F3D;N # Pe TIBETAN MARK ANG KHANG GYAS -0F3E..0F3F;N # Mc [2] TIBETAN SIGN YAR TSHES..TIBETAN SIGN MAR TSHES -0F40..0F47;N # Lo [8] TIBETAN LETTER KA..TIBETAN LETTER JA -0F49..0F6C;N # Lo [36] TIBETAN LETTER NYA..TIBETAN LETTER RRA -0F71..0F7E;N # Mn [14] TIBETAN VOWEL SIGN AA..TIBETAN SIGN RJES SU NGA RO -0F7F;N # Mc TIBETAN SIGN RNAM BCAD -0F80..0F84;N # Mn [5] TIBETAN VOWEL SIGN REVERSED I..TIBETAN MARK HALANTA -0F85;N # Po TIBETAN MARK PALUTA -0F86..0F87;N # Mn [2] TIBETAN SIGN LCI RTAGS..TIBETAN SIGN YANG RTAGS -0F88..0F8C;N # Lo [5] TIBETAN SIGN LCE TSA CAN..TIBETAN SIGN INVERTED MCHU CAN -0F8D..0F97;N # Mn [11] TIBETAN SUBJOINED SIGN LCE TSA CAN..TIBETAN SUBJOINED LETTER JA -0F99..0FBC;N # Mn [36] TIBETAN SUBJOINED LETTER NYA..TIBETAN SUBJOINED LETTER FIXED-FORM RA -0FBE..0FC5;N # So [8] TIBETAN KU RU KHA..TIBETAN SYMBOL RDO RJE -0FC6;N # Mn TIBETAN SYMBOL PADMA GDAN -0FC7..0FCC;N # So [6] TIBETAN SYMBOL RDO RJE RGYA GRAM..TIBETAN SYMBOL NOR BU BZHI -KHYIL -0FCE..0FCF;N # So [2] TIBETAN SIGN RDEL NAG RDEL DKAR..TIBETAN SIGN RDEL NAG GSUM -0FD0..0FD4;N # Po [5] TIBETAN MARK BSKA- SHOG GI MGO RGYAN..TIBETAN MARK CLOSING BRDA RNYING YIG MGO SGAB MA -0FD5..0FD8;N # So [4] RIGHT-FACING SVASTI SIGN..LEFT-FACING SVASTI SIGN WITH DOTS -0FD9..0FDA;N # Po [2] TIBETAN MARK LEADING MCHAN RTAGS..TIBETAN MARK TRAILING MCHAN RTAGS -1000..102A;N # Lo [43] MYANMAR LETTER KA..MYANMAR LETTER AU -102B..102C;N # Mc [2] MYANMAR VOWEL SIGN TALL AA..MYANMAR VOWEL SIGN AA -102D..1030;N # Mn [4] MYANMAR VOWEL SIGN I..MYANMAR VOWEL SIGN UU -1031;N # Mc MYANMAR VOWEL SIGN E -1032..1037;N # Mn [6] MYANMAR VOWEL SIGN AI..MYANMAR SIGN DOT BELOW -1038;N # Mc MYANMAR SIGN VISARGA -1039..103A;N # Mn [2] MYANMAR SIGN VIRAMA..MYANMAR SIGN ASAT -103B..103C;N # Mc [2] MYANMAR CONSONANT SIGN MEDIAL YA..MYANMAR CONSONANT SIGN MEDIAL RA -103D..103E;N # Mn [2] MYANMAR CONSONANT SIGN MEDIAL WA..MYANMAR CONSONANT SIGN MEDIAL HA -103F;N # Lo MYANMAR LETTER GREAT SA -1040..1049;N # Nd [10] MYANMAR DIGIT ZERO..MYANMAR DIGIT NINE -104A..104F;N # Po [6] MYANMAR SIGN LITTLE SECTION..MYANMAR SYMBOL GENITIVE -1050..1055;N # Lo [6] MYANMAR LETTER SHA..MYANMAR LETTER VOCALIC LL -1056..1057;N # Mc [2] MYANMAR VOWEL SIGN VOCALIC R..MYANMAR VOWEL SIGN VOCALIC RR -1058..1059;N # Mn [2] MYANMAR VOWEL SIGN VOCALIC L..MYANMAR VOWEL SIGN VOCALIC LL -105A..105D;N # Lo [4] MYANMAR LETTER MON NGA..MYANMAR LETTER MON BBE -105E..1060;N # Mn [3] MYANMAR CONSONANT SIGN MON MEDIAL NA..MYANMAR CONSONANT SIGN MON MEDIAL LA -1061;N # Lo MYANMAR LETTER SGAW KAREN SHA -1062..1064;N # Mc [3] MYANMAR VOWEL SIGN SGAW KAREN EU..MYANMAR TONE MARK SGAW KAREN KE PHO -1065..1066;N # Lo [2] MYANMAR LETTER WESTERN PWO KAREN THA..MYANMAR LETTER WESTERN PWO KAREN PWA -1067..106D;N # Mc [7] MYANMAR VOWEL SIGN WESTERN PWO KAREN EU..MYANMAR SIGN WESTERN PWO KAREN TONE-5 -106E..1070;N # Lo [3] MYANMAR LETTER EASTERN PWO KAREN NNA..MYANMAR LETTER EASTERN PWO KAREN GHWA -1071..1074;N # Mn [4] MYANMAR VOWEL SIGN GEBA KAREN I..MYANMAR VOWEL SIGN KAYAH EE -1075..1081;N # Lo [13] MYANMAR LETTER SHAN KA..MYANMAR LETTER SHAN HA -1082;N # Mn MYANMAR CONSONANT SIGN SHAN MEDIAL WA -1083..1084;N # Mc [2] MYANMAR VOWEL SIGN SHAN AA..MYANMAR VOWEL SIGN SHAN E -1085..1086;N # Mn [2] MYANMAR VOWEL SIGN SHAN E ABOVE..MYANMAR VOWEL SIGN SHAN FINAL Y -1087..108C;N # Mc [6] MYANMAR SIGN SHAN TONE-2..MYANMAR SIGN SHAN COUNCIL TONE-3 -108D;N # Mn MYANMAR SIGN SHAN COUNCIL EMPHATIC TONE -108E;N # Lo MYANMAR LETTER RUMAI PALAUNG FA -108F;N # Mc MYANMAR SIGN RUMAI PALAUNG TONE-5 -1090..1099;N # Nd [10] MYANMAR SHAN DIGIT ZERO..MYANMAR SHAN DIGIT NINE -109A..109C;N # Mc [3] MYANMAR SIGN KHAMTI TONE-1..MYANMAR VOWEL SIGN AITON A -109D;N # Mn MYANMAR VOWEL SIGN AITON AI -109E..109F;N # So [2] MYANMAR SYMBOL SHAN ONE..MYANMAR SYMBOL SHAN EXCLAMATION -10A0..10C5;N # Lu [38] GEORGIAN CAPITAL LETTER AN..GEORGIAN CAPITAL LETTER HOE -10C7;N # Lu GEORGIAN CAPITAL LETTER YN -10CD;N # Lu GEORGIAN CAPITAL LETTER AEN -10D0..10FA;N # Ll [43] GEORGIAN LETTER AN..GEORGIAN LETTER AIN -10FB;N # Po GEORGIAN PARAGRAPH SEPARATOR -10FC;N # Lm MODIFIER LETTER GEORGIAN NAR -10FD..10FF;N # Ll [3] GEORGIAN LETTER AEN..GEORGIAN LETTER LABIAL SIGN -1100..115F;W # Lo [96] HANGUL CHOSEONG KIYEOK..HANGUL CHOSEONG FILLER -1160..11FF;N # Lo [160] HANGUL JUNGSEONG FILLER..HANGUL JONGSEONG SSANGNIEUN -1200..1248;N # Lo [73] ETHIOPIC SYLLABLE HA..ETHIOPIC SYLLABLE QWA -124A..124D;N # Lo [4] ETHIOPIC SYLLABLE QWI..ETHIOPIC SYLLABLE QWE -1250..1256;N # Lo [7] ETHIOPIC SYLLABLE QHA..ETHIOPIC SYLLABLE QHO -1258;N # Lo ETHIOPIC SYLLABLE QHWA -125A..125D;N # Lo [4] ETHIOPIC SYLLABLE QHWI..ETHIOPIC SYLLABLE QHWE -1260..1288;N # Lo [41] ETHIOPIC SYLLABLE BA..ETHIOPIC SYLLABLE XWA -128A..128D;N # Lo [4] ETHIOPIC SYLLABLE XWI..ETHIOPIC SYLLABLE XWE -1290..12B0;N # Lo [33] ETHIOPIC SYLLABLE NA..ETHIOPIC SYLLABLE KWA -12B2..12B5;N # Lo [4] ETHIOPIC SYLLABLE KWI..ETHIOPIC SYLLABLE KWE -12B8..12BE;N # Lo [7] ETHIOPIC SYLLABLE KXA..ETHIOPIC SYLLABLE KXO -12C0;N # Lo ETHIOPIC SYLLABLE KXWA -12C2..12C5;N # Lo [4] ETHIOPIC SYLLABLE KXWI..ETHIOPIC SYLLABLE KXWE -12C8..12D6;N # Lo [15] ETHIOPIC SYLLABLE WA..ETHIOPIC SYLLABLE PHARYNGEAL O -12D8..1310;N # Lo [57] ETHIOPIC SYLLABLE ZA..ETHIOPIC SYLLABLE GWA -1312..1315;N # Lo [4] ETHIOPIC SYLLABLE GWI..ETHIOPIC SYLLABLE GWE -1318..135A;N # Lo [67] ETHIOPIC SYLLABLE GGA..ETHIOPIC SYLLABLE FYA -135D..135F;N # Mn [3] ETHIOPIC COMBINING GEMINATION AND VOWEL LENGTH MARK..ETHIOPIC COMBINING GEMINATION MARK -1360..1368;N # Po [9] ETHIOPIC SECTION MARK..ETHIOPIC PARAGRAPH SEPARATOR -1369..137C;N # No [20] ETHIOPIC DIGIT ONE..ETHIOPIC NUMBER TEN THOUSAND -1380..138F;N # Lo [16] ETHIOPIC SYLLABLE SEBATBEIT MWA..ETHIOPIC SYLLABLE PWE -1390..1399;N # So [10] ETHIOPIC TONAL MARK YIZET..ETHIOPIC TONAL MARK KURT -13A0..13F5;N # Lu [86] CHEROKEE LETTER A..CHEROKEE LETTER MV -13F8..13FD;N # Ll [6] CHEROKEE SMALL LETTER YE..CHEROKEE SMALL LETTER MV -1400;N # Pd CANADIAN SYLLABICS HYPHEN -1401..166C;N # Lo [620] CANADIAN SYLLABICS E..CANADIAN SYLLABICS CARRIER TTSA -166D;N # So CANADIAN SYLLABICS CHI SIGN -166E;N # Po CANADIAN SYLLABICS FULL STOP -166F..167F;N # Lo [17] CANADIAN SYLLABICS QAI..CANADIAN SYLLABICS BLACKFOOT W -1680;N # Zs OGHAM SPACE MARK -1681..169A;N # Lo [26] OGHAM LETTER BEITH..OGHAM LETTER PEITH -169B;N # Ps OGHAM FEATHER MARK -169C;N # Pe OGHAM REVERSED FEATHER MARK -16A0..16EA;N # Lo [75] RUNIC LETTER FEHU FEOH FE F..RUNIC LETTER X -16EB..16ED;N # Po [3] RUNIC SINGLE PUNCTUATION..RUNIC CROSS PUNCTUATION -16EE..16F0;N # Nl [3] RUNIC ARLAUG SYMBOL..RUNIC BELGTHOR SYMBOL -16F1..16F8;N # Lo [8] RUNIC LETTER K..RUNIC LETTER FRANKS CASKET AESC -1700..1711;N # Lo [18] TAGALOG LETTER A..TAGALOG LETTER HA -1712..1714;N # Mn [3] TAGALOG VOWEL SIGN I..TAGALOG SIGN VIRAMA -1715;N # Mc TAGALOG SIGN PAMUDPOD -171F;N # Lo TAGALOG LETTER ARCHAIC RA -1720..1731;N # Lo [18] HANUNOO LETTER A..HANUNOO LETTER HA -1732..1733;N # Mn [2] HANUNOO VOWEL SIGN I..HANUNOO VOWEL SIGN U -1734;N # Mc HANUNOO SIGN PAMUDPOD -1735..1736;N # Po [2] PHILIPPINE SINGLE PUNCTUATION..PHILIPPINE DOUBLE PUNCTUATION -1740..1751;N # Lo [18] BUHID LETTER A..BUHID LETTER HA -1752..1753;N # Mn [2] BUHID VOWEL SIGN I..BUHID VOWEL SIGN U -1760..176C;N # Lo [13] TAGBANWA LETTER A..TAGBANWA LETTER YA -176E..1770;N # Lo [3] TAGBANWA LETTER LA..TAGBANWA LETTER SA -1772..1773;N # Mn [2] TAGBANWA VOWEL SIGN I..TAGBANWA VOWEL SIGN U -1780..17B3;N # Lo [52] KHMER LETTER KA..KHMER INDEPENDENT VOWEL QAU -17B4..17B5;N # Mn [2] KHMER VOWEL INHERENT AQ..KHMER VOWEL INHERENT AA -17B6;N # Mc KHMER VOWEL SIGN AA -17B7..17BD;N # Mn [7] KHMER VOWEL SIGN I..KHMER VOWEL SIGN UA -17BE..17C5;N # Mc [8] KHMER VOWEL SIGN OE..KHMER VOWEL SIGN AU -17C6;N # Mn KHMER SIGN NIKAHIT -17C7..17C8;N # Mc [2] KHMER SIGN REAHMUK..KHMER SIGN YUUKALEAPINTU -17C9..17D3;N # Mn [11] KHMER SIGN MUUSIKATOAN..KHMER SIGN BATHAMASAT -17D4..17D6;N # Po [3] KHMER SIGN KHAN..KHMER SIGN CAMNUC PII KUUH -17D7;N # Lm KHMER SIGN LEK TOO -17D8..17DA;N # Po [3] KHMER SIGN BEYYAL..KHMER SIGN KOOMUUT -17DB;N # Sc KHMER CURRENCY SYMBOL RIEL -17DC;N # Lo KHMER SIGN AVAKRAHASANYA -17DD;N # Mn KHMER SIGN ATTHACAN -17E0..17E9;N # Nd [10] KHMER DIGIT ZERO..KHMER DIGIT NINE -17F0..17F9;N # No [10] KHMER SYMBOL LEK ATTAK SON..KHMER SYMBOL LEK ATTAK PRAM-BUON -1800..1805;N # Po [6] MONGOLIAN BIRGA..MONGOLIAN FOUR DOTS -1806;N # Pd MONGOLIAN TODO SOFT HYPHEN -1807..180A;N # Po [4] MONGOLIAN SIBE SYLLABLE BOUNDARY MARKER..MONGOLIAN NIRUGU -180B..180D;N # Mn [3] MONGOLIAN FREE VARIATION SELECTOR ONE..MONGOLIAN FREE VARIATION SELECTOR THREE -180E;N # Cf MONGOLIAN VOWEL SEPARATOR -180F;N # Mn MONGOLIAN FREE VARIATION SELECTOR FOUR -1810..1819;N # Nd [10] MONGOLIAN DIGIT ZERO..MONGOLIAN DIGIT NINE -1820..1842;N # Lo [35] MONGOLIAN LETTER A..MONGOLIAN LETTER CHI -1843;N # Lm MONGOLIAN LETTER TODO LONG VOWEL SIGN -1844..1878;N # Lo [53] MONGOLIAN LETTER TODO E..MONGOLIAN LETTER CHA WITH TWO DOTS -1880..1884;N # Lo [5] MONGOLIAN LETTER ALI GALI ANUSVARA ONE..MONGOLIAN LETTER ALI GALI INVERTED UBADAMA -1885..1886;N # Mn [2] MONGOLIAN LETTER ALI GALI BALUDA..MONGOLIAN LETTER ALI GALI THREE BALUDA -1887..18A8;N # Lo [34] MONGOLIAN LETTER ALI GALI A..MONGOLIAN LETTER MANCHU ALI GALI BHA -18A9;N # Mn MONGOLIAN LETTER ALI GALI DAGALGA -18AA;N # Lo MONGOLIAN LETTER MANCHU ALI GALI LHA -18B0..18F5;N # Lo [70] CANADIAN SYLLABICS OY..CANADIAN SYLLABICS CARRIER DENTAL S -1900..191E;N # Lo [31] LIMBU VOWEL-CARRIER LETTER..LIMBU LETTER TRA -1920..1922;N # Mn [3] LIMBU VOWEL SIGN A..LIMBU VOWEL SIGN U -1923..1926;N # Mc [4] LIMBU VOWEL SIGN EE..LIMBU VOWEL SIGN AU -1927..1928;N # Mn [2] LIMBU VOWEL SIGN E..LIMBU VOWEL SIGN O -1929..192B;N # Mc [3] LIMBU SUBJOINED LETTER YA..LIMBU SUBJOINED LETTER WA -1930..1931;N # Mc [2] LIMBU SMALL LETTER KA..LIMBU SMALL LETTER NGA -1932;N # Mn LIMBU SMALL LETTER ANUSVARA -1933..1938;N # Mc [6] LIMBU SMALL LETTER TA..LIMBU SMALL LETTER LA -1939..193B;N # Mn [3] LIMBU SIGN MUKPHRENG..LIMBU SIGN SA-I -1940;N # So LIMBU SIGN LOO -1944..1945;N # Po [2] LIMBU EXCLAMATION MARK..LIMBU QUESTION MARK -1946..194F;N # Nd [10] LIMBU DIGIT ZERO..LIMBU DIGIT NINE -1950..196D;N # Lo [30] TAI LE LETTER KA..TAI LE LETTER AI -1970..1974;N # Lo [5] TAI LE LETTER TONE-2..TAI LE LETTER TONE-6 -1980..19AB;N # Lo [44] NEW TAI LUE LETTER HIGH QA..NEW TAI LUE LETTER LOW SUA -19B0..19C9;N # Lo [26] NEW TAI LUE VOWEL SIGN VOWEL SHORTENER..NEW TAI LUE TONE MARK-2 -19D0..19D9;N # Nd [10] NEW TAI LUE DIGIT ZERO..NEW TAI LUE DIGIT NINE -19DA;N # No NEW TAI LUE THAM DIGIT ONE -19DE..19DF;N # So [2] NEW TAI LUE SIGN LAE..NEW TAI LUE SIGN LAEV -19E0..19FF;N # So [32] KHMER SYMBOL PATHAMASAT..KHMER SYMBOL DAP-PRAM ROC -1A00..1A16;N # Lo [23] BUGINESE LETTER KA..BUGINESE LETTER HA -1A17..1A18;N # Mn [2] BUGINESE VOWEL SIGN I..BUGINESE VOWEL SIGN U -1A19..1A1A;N # Mc [2] BUGINESE VOWEL SIGN E..BUGINESE VOWEL SIGN O -1A1B;N # Mn BUGINESE VOWEL SIGN AE -1A1E..1A1F;N # Po [2] BUGINESE PALLAWA..BUGINESE END OF SECTION -1A20..1A54;N # Lo [53] TAI THAM LETTER HIGH KA..TAI THAM LETTER GREAT SA -1A55;N # Mc TAI THAM CONSONANT SIGN MEDIAL RA -1A56;N # Mn TAI THAM CONSONANT SIGN MEDIAL LA -1A57;N # Mc TAI THAM CONSONANT SIGN LA TANG LAI -1A58..1A5E;N # Mn [7] TAI THAM SIGN MAI KANG LAI..TAI THAM CONSONANT SIGN SA -1A60;N # Mn TAI THAM SIGN SAKOT -1A61;N # Mc TAI THAM VOWEL SIGN A -1A62;N # Mn TAI THAM VOWEL SIGN MAI SAT -1A63..1A64;N # Mc [2] TAI THAM VOWEL SIGN AA..TAI THAM VOWEL SIGN TALL AA -1A65..1A6C;N # Mn [8] TAI THAM VOWEL SIGN I..TAI THAM VOWEL SIGN OA BELOW -1A6D..1A72;N # Mc [6] TAI THAM VOWEL SIGN OY..TAI THAM VOWEL SIGN THAM AI -1A73..1A7C;N # Mn [10] TAI THAM VOWEL SIGN OA ABOVE..TAI THAM SIGN KHUEN-LUE KARAN -1A7F;N # Mn TAI THAM COMBINING CRYPTOGRAMMIC DOT -1A80..1A89;N # Nd [10] TAI THAM HORA DIGIT ZERO..TAI THAM HORA DIGIT NINE -1A90..1A99;N # Nd [10] TAI THAM THAM DIGIT ZERO..TAI THAM THAM DIGIT NINE -1AA0..1AA6;N # Po [7] TAI THAM SIGN WIANG..TAI THAM SIGN REVERSED ROTATED RANA -1AA7;N # Lm TAI THAM SIGN MAI YAMOK -1AA8..1AAD;N # Po [6] TAI THAM SIGN KAAN..TAI THAM SIGN CAANG -1AB0..1ABD;N # Mn [14] COMBINING DOUBLED CIRCUMFLEX ACCENT..COMBINING PARENTHESES BELOW -1ABE;N # Me COMBINING PARENTHESES OVERLAY -1ABF..1ACE;N # Mn [16] COMBINING LATIN SMALL LETTER W BELOW..COMBINING LATIN SMALL LETTER INSULAR T -1B00..1B03;N # Mn [4] BALINESE SIGN ULU RICEM..BALINESE SIGN SURANG -1B04;N # Mc BALINESE SIGN BISAH -1B05..1B33;N # Lo [47] BALINESE LETTER AKARA..BALINESE LETTER HA -1B34;N # Mn BALINESE SIGN REREKAN -1B35;N # Mc BALINESE VOWEL SIGN TEDUNG -1B36..1B3A;N # Mn [5] BALINESE VOWEL SIGN ULU..BALINESE VOWEL SIGN RA REPA -1B3B;N # Mc BALINESE VOWEL SIGN RA REPA TEDUNG -1B3C;N # Mn BALINESE VOWEL SIGN LA LENGA -1B3D..1B41;N # Mc [5] BALINESE VOWEL SIGN LA LENGA TEDUNG..BALINESE VOWEL SIGN TALING REPA TEDUNG -1B42;N # Mn BALINESE VOWEL SIGN PEPET -1B43..1B44;N # Mc [2] BALINESE VOWEL SIGN PEPET TEDUNG..BALINESE ADEG ADEG -1B45..1B4C;N # Lo [8] BALINESE LETTER KAF SASAK..BALINESE LETTER ARCHAIC JNYA -1B50..1B59;N # Nd [10] BALINESE DIGIT ZERO..BALINESE DIGIT NINE -1B5A..1B60;N # Po [7] BALINESE PANTI..BALINESE PAMENENG -1B61..1B6A;N # So [10] BALINESE MUSICAL SYMBOL DONG..BALINESE MUSICAL SYMBOL DANG GEDE -1B6B..1B73;N # Mn [9] BALINESE MUSICAL SYMBOL COMBINING TEGEH..BALINESE MUSICAL SYMBOL COMBINING GONG -1B74..1B7C;N # So [9] BALINESE MUSICAL SYMBOL RIGHT-HAND OPEN DUG..BALINESE MUSICAL SYMBOL LEFT-HAND OPEN PING -1B7D..1B7E;N # Po [2] BALINESE PANTI LANTANG..BALINESE PAMADA LANTANG -1B80..1B81;N # Mn [2] SUNDANESE SIGN PANYECEK..SUNDANESE SIGN PANGLAYAR -1B82;N # Mc SUNDANESE SIGN PANGWISAD -1B83..1BA0;N # Lo [30] SUNDANESE LETTER A..SUNDANESE LETTER HA -1BA1;N # Mc SUNDANESE CONSONANT SIGN PAMINGKAL -1BA2..1BA5;N # Mn [4] SUNDANESE CONSONANT SIGN PANYAKRA..SUNDANESE VOWEL SIGN PANYUKU -1BA6..1BA7;N # Mc [2] SUNDANESE VOWEL SIGN PANAELAENG..SUNDANESE VOWEL SIGN PANOLONG -1BA8..1BA9;N # Mn [2] SUNDANESE VOWEL SIGN PAMEPET..SUNDANESE VOWEL SIGN PANEULEUNG -1BAA;N # Mc SUNDANESE SIGN PAMAAEH -1BAB..1BAD;N # Mn [3] SUNDANESE SIGN VIRAMA..SUNDANESE CONSONANT SIGN PASANGAN WA -1BAE..1BAF;N # Lo [2] SUNDANESE LETTER KHA..SUNDANESE LETTER SYA -1BB0..1BB9;N # Nd [10] SUNDANESE DIGIT ZERO..SUNDANESE DIGIT NINE -1BBA..1BBF;N # Lo [6] SUNDANESE AVAGRAHA..SUNDANESE LETTER FINAL M -1BC0..1BE5;N # Lo [38] BATAK LETTER A..BATAK LETTER U -1BE6;N # Mn BATAK SIGN TOMPI -1BE7;N # Mc BATAK VOWEL SIGN E -1BE8..1BE9;N # Mn [2] BATAK VOWEL SIGN PAKPAK E..BATAK VOWEL SIGN EE -1BEA..1BEC;N # Mc [3] BATAK VOWEL SIGN I..BATAK VOWEL SIGN O -1BED;N # Mn BATAK VOWEL SIGN KARO O -1BEE;N # Mc BATAK VOWEL SIGN U -1BEF..1BF1;N # Mn [3] BATAK VOWEL SIGN U FOR SIMALUNGUN SA..BATAK CONSONANT SIGN H -1BF2..1BF3;N # Mc [2] BATAK PANGOLAT..BATAK PANONGONAN -1BFC..1BFF;N # Po [4] BATAK SYMBOL BINDU NA METEK..BATAK SYMBOL BINDU PANGOLAT -1C00..1C23;N # Lo [36] LEPCHA LETTER KA..LEPCHA LETTER A -1C24..1C2B;N # Mc [8] LEPCHA SUBJOINED LETTER YA..LEPCHA VOWEL SIGN UU -1C2C..1C33;N # Mn [8] LEPCHA VOWEL SIGN E..LEPCHA CONSONANT SIGN T -1C34..1C35;N # Mc [2] LEPCHA CONSONANT SIGN NYIN-DO..LEPCHA CONSONANT SIGN KANG -1C36..1C37;N # Mn [2] LEPCHA SIGN RAN..LEPCHA SIGN NUKTA -1C3B..1C3F;N # Po [5] LEPCHA PUNCTUATION TA-ROL..LEPCHA PUNCTUATION TSHOOK -1C40..1C49;N # Nd [10] LEPCHA DIGIT ZERO..LEPCHA DIGIT NINE -1C4D..1C4F;N # Lo [3] LEPCHA LETTER TTA..LEPCHA LETTER DDA -1C50..1C59;N # Nd [10] OL CHIKI DIGIT ZERO..OL CHIKI DIGIT NINE -1C5A..1C77;N # Lo [30] OL CHIKI LETTER LA..OL CHIKI LETTER OH -1C78..1C7D;N # Lm [6] OL CHIKI MU TTUDDAG..OL CHIKI AHAD -1C7E..1C7F;N # Po [2] OL CHIKI PUNCTUATION MUCAAD..OL CHIKI PUNCTUATION DOUBLE MUCAAD -1C80..1C88;N # Ll [9] CYRILLIC SMALL LETTER ROUNDED VE..CYRILLIC SMALL LETTER UNBLENDED UK -1C90..1CBA;N # Lu [43] GEORGIAN MTAVRULI CAPITAL LETTER AN..GEORGIAN MTAVRULI CAPITAL LETTER AIN -1CBD..1CBF;N # Lu [3] GEORGIAN MTAVRULI CAPITAL LETTER AEN..GEORGIAN MTAVRULI CAPITAL LETTER LABIAL SIGN -1CC0..1CC7;N # Po [8] SUNDANESE PUNCTUATION BINDU SURYA..SUNDANESE PUNCTUATION BINDU BA SATANGA -1CD0..1CD2;N # Mn [3] VEDIC TONE KARSHANA..VEDIC TONE PRENKHA -1CD3;N # Po VEDIC SIGN NIHSHVASA -1CD4..1CE0;N # Mn [13] VEDIC SIGN YAJURVEDIC MIDLINE SVARITA..VEDIC TONE RIGVEDIC KASHMIRI INDEPENDENT SVARITA -1CE1;N # Mc VEDIC TONE ATHARVAVEDIC INDEPENDENT SVARITA -1CE2..1CE8;N # Mn [7] VEDIC SIGN VISARGA SVARITA..VEDIC SIGN VISARGA ANUDATTA WITH TAIL -1CE9..1CEC;N # Lo [4] VEDIC SIGN ANUSVARA ANTARGOMUKHA..VEDIC SIGN ANUSVARA VAMAGOMUKHA WITH TAIL -1CED;N # Mn VEDIC SIGN TIRYAK -1CEE..1CF3;N # Lo [6] VEDIC SIGN HEXIFORM LONG ANUSVARA..VEDIC SIGN ROTATED ARDHAVISARGA -1CF4;N # Mn VEDIC TONE CANDRA ABOVE -1CF5..1CF6;N # Lo [2] VEDIC SIGN JIHVAMULIYA..VEDIC SIGN UPADHMANIYA -1CF7;N # Mc VEDIC SIGN ATIKRAMA -1CF8..1CF9;N # Mn [2] VEDIC TONE RING ABOVE..VEDIC TONE DOUBLE RING ABOVE -1CFA;N # Lo VEDIC SIGN DOUBLE ANUSVARA ANTARGOMUKHA -1D00..1D2B;N # Ll [44] LATIN LETTER SMALL CAPITAL A..CYRILLIC LETTER SMALL CAPITAL EL -1D2C..1D6A;N # Lm [63] MODIFIER LETTER CAPITAL A..GREEK SUBSCRIPT SMALL LETTER CHI -1D6B..1D77;N # Ll [13] LATIN SMALL LETTER UE..LATIN SMALL LETTER TURNED G -1D78;N # Lm MODIFIER LETTER CYRILLIC EN -1D79..1D7F;N # Ll [7] LATIN SMALL LETTER INSULAR G..LATIN SMALL LETTER UPSILON WITH STROKE -1D80..1D9A;N # Ll [27] LATIN SMALL LETTER B WITH PALATAL HOOK..LATIN SMALL LETTER EZH WITH RETROFLEX HOOK -1D9B..1DBF;N # Lm [37] MODIFIER LETTER SMALL TURNED ALPHA..MODIFIER LETTER SMALL THETA -1DC0..1DFF;N # Mn [64] COMBINING DOTTED GRAVE ACCENT..COMBINING RIGHT ARROWHEAD AND DOWN ARROWHEAD BELOW -1E00..1EFF;N # L& [256] LATIN CAPITAL LETTER A WITH RING BELOW..LATIN SMALL LETTER Y WITH LOOP -1F00..1F15;N # L& [22] GREEK SMALL LETTER ALPHA WITH PSILI..GREEK SMALL LETTER EPSILON WITH DASIA AND OXIA -1F18..1F1D;N # Lu [6] GREEK CAPITAL LETTER EPSILON WITH PSILI..GREEK CAPITAL LETTER EPSILON WITH DASIA AND OXIA -1F20..1F45;N # L& [38] GREEK SMALL LETTER ETA WITH PSILI..GREEK SMALL LETTER OMICRON WITH DASIA AND OXIA -1F48..1F4D;N # Lu [6] GREEK CAPITAL LETTER OMICRON WITH PSILI..GREEK CAPITAL LETTER OMICRON WITH DASIA AND OXIA -1F50..1F57;N # Ll [8] GREEK SMALL LETTER UPSILON WITH PSILI..GREEK SMALL LETTER UPSILON WITH DASIA AND PERISPOMENI -1F59;N # Lu GREEK CAPITAL LETTER UPSILON WITH DASIA -1F5B;N # Lu GREEK CAPITAL LETTER UPSILON WITH DASIA AND VARIA -1F5D;N # Lu GREEK CAPITAL LETTER UPSILON WITH DASIA AND OXIA -1F5F..1F7D;N # L& [31] GREEK CAPITAL LETTER UPSILON WITH DASIA AND PERISPOMENI..GREEK SMALL LETTER OMEGA WITH OXIA -1F80..1FB4;N # L& [53] GREEK SMALL LETTER ALPHA WITH PSILI AND YPOGEGRAMMENI..GREEK SMALL LETTER ALPHA WITH OXIA AND YPOGEGRAMMENI -1FB6..1FBC;N # L& [7] GREEK SMALL LETTER ALPHA WITH PERISPOMENI..GREEK CAPITAL LETTER ALPHA WITH PROSGEGRAMMENI -1FBD;N # Sk GREEK KORONIS -1FBE;N # Ll GREEK PROSGEGRAMMENI -1FBF..1FC1;N # Sk [3] GREEK PSILI..GREEK DIALYTIKA AND PERISPOMENI -1FC2..1FC4;N # Ll [3] GREEK SMALL LETTER ETA WITH VARIA AND YPOGEGRAMMENI..GREEK SMALL LETTER ETA WITH OXIA AND YPOGEGRAMMENI -1FC6..1FCC;N # L& [7] GREEK SMALL LETTER ETA WITH PERISPOMENI..GREEK CAPITAL LETTER ETA WITH PROSGEGRAMMENI -1FCD..1FCF;N # Sk [3] GREEK PSILI AND VARIA..GREEK PSILI AND PERISPOMENI -1FD0..1FD3;N # Ll [4] GREEK SMALL LETTER IOTA WITH VRACHY..GREEK SMALL LETTER IOTA WITH DIALYTIKA AND OXIA -1FD6..1FDB;N # L& [6] GREEK SMALL LETTER IOTA WITH PERISPOMENI..GREEK CAPITAL LETTER IOTA WITH OXIA -1FDD..1FDF;N # Sk [3] GREEK DASIA AND VARIA..GREEK DASIA AND PERISPOMENI -1FE0..1FEC;N # L& [13] GREEK SMALL LETTER UPSILON WITH VRACHY..GREEK CAPITAL LETTER RHO WITH DASIA -1FED..1FEF;N # Sk [3] GREEK DIALYTIKA AND VARIA..GREEK VARIA -1FF2..1FF4;N # Ll [3] GREEK SMALL LETTER OMEGA WITH VARIA AND YPOGEGRAMMENI..GREEK SMALL LETTER OMEGA WITH OXIA AND YPOGEGRAMMENI -1FF6..1FFC;N # L& [7] GREEK SMALL LETTER OMEGA WITH PERISPOMENI..GREEK CAPITAL LETTER OMEGA WITH PROSGEGRAMMENI -1FFD..1FFE;N # Sk [2] GREEK OXIA..GREEK DASIA -2000..200A;N # Zs [11] EN QUAD..HAIR SPACE -200B..200F;N # Cf [5] ZERO WIDTH SPACE..RIGHT-TO-LEFT MARK -2010;A # Pd HYPHEN -2011..2012;N # Pd [2] NON-BREAKING HYPHEN..FIGURE DASH -2013..2015;A # Pd [3] EN DASH..HORIZONTAL BAR -2016;A # Po DOUBLE VERTICAL LINE -2017;N # Po DOUBLE LOW LINE -2018;A # Pi LEFT SINGLE QUOTATION MARK -2019;A # Pf RIGHT SINGLE QUOTATION MARK -201A;N # Ps SINGLE LOW-9 QUOTATION MARK -201B;N # Pi SINGLE HIGH-REVERSED-9 QUOTATION MARK -201C;A # Pi LEFT DOUBLE QUOTATION MARK -201D;A # Pf RIGHT DOUBLE QUOTATION MARK -201E;N # Ps DOUBLE LOW-9 QUOTATION MARK -201F;N # Pi DOUBLE HIGH-REVERSED-9 QUOTATION MARK -2020..2022;A # Po [3] DAGGER..BULLET -2023;N # Po TRIANGULAR BULLET -2024..2027;A # Po [4] ONE DOT LEADER..HYPHENATION POINT -2028;N # Zl LINE SEPARATOR -2029;N # Zp PARAGRAPH SEPARATOR -202A..202E;N # Cf [5] LEFT-TO-RIGHT EMBEDDING..RIGHT-TO-LEFT OVERRIDE -202F;N # Zs NARROW NO-BREAK SPACE -2030;A # Po PER MILLE SIGN -2031;N # Po PER TEN THOUSAND SIGN -2032..2033;A # Po [2] PRIME..DOUBLE PRIME -2034;N # Po TRIPLE PRIME -2035;A # Po REVERSED PRIME -2036..2038;N # Po [3] REVERSED DOUBLE PRIME..CARET -2039;N # Pi SINGLE LEFT-POINTING ANGLE QUOTATION MARK -203A;N # Pf SINGLE RIGHT-POINTING ANGLE QUOTATION MARK -203B;A # Po REFERENCE MARK -203C..203D;N # Po [2] DOUBLE EXCLAMATION MARK..INTERROBANG -203E;A # Po OVERLINE -203F..2040;N # Pc [2] UNDERTIE..CHARACTER TIE -2041..2043;N # Po [3] CARET INSERTION POINT..HYPHEN BULLET -2044;N # Sm FRACTION SLASH -2045;N # Ps LEFT SQUARE BRACKET WITH QUILL -2046;N # Pe RIGHT SQUARE BRACKET WITH QUILL -2047..2051;N # Po [11] DOUBLE QUESTION MARK..TWO ASTERISKS ALIGNED VERTICALLY -2052;N # Sm COMMERCIAL MINUS SIGN -2053;N # Po SWUNG DASH -2054;N # Pc INVERTED UNDERTIE -2055..205E;N # Po [10] FLOWER PUNCTUATION MARK..VERTICAL FOUR DOTS -205F;N # Zs MEDIUM MATHEMATICAL SPACE -2060..2064;N # Cf [5] WORD JOINER..INVISIBLE PLUS -2066..206F;N # Cf [10] LEFT-TO-RIGHT ISOLATE..NOMINAL DIGIT SHAPES -2070;N # No SUPERSCRIPT ZERO -2071;N # Lm SUPERSCRIPT LATIN SMALL LETTER I -2074;A # No SUPERSCRIPT FOUR -2075..2079;N # No [5] SUPERSCRIPT FIVE..SUPERSCRIPT NINE -207A..207C;N # Sm [3] SUPERSCRIPT PLUS SIGN..SUPERSCRIPT EQUALS SIGN -207D;N # Ps SUPERSCRIPT LEFT PARENTHESIS -207E;N # Pe SUPERSCRIPT RIGHT PARENTHESIS -207F;A # Lm SUPERSCRIPT LATIN SMALL LETTER N -2080;N # No SUBSCRIPT ZERO -2081..2084;A # No [4] SUBSCRIPT ONE..SUBSCRIPT FOUR -2085..2089;N # No [5] SUBSCRIPT FIVE..SUBSCRIPT NINE -208A..208C;N # Sm [3] SUBSCRIPT PLUS SIGN..SUBSCRIPT EQUALS SIGN -208D;N # Ps SUBSCRIPT LEFT PARENTHESIS -208E;N # Pe SUBSCRIPT RIGHT PARENTHESIS -2090..209C;N # Lm [13] LATIN SUBSCRIPT SMALL LETTER A..LATIN SUBSCRIPT SMALL LETTER T -20A0..20A8;N # Sc [9] EURO-CURRENCY SIGN..RUPEE SIGN -20A9;H # Sc WON SIGN -20AA..20AB;N # Sc [2] NEW SHEQEL SIGN..DONG SIGN -20AC;A # Sc EURO SIGN -20AD..20C0;N # Sc [20] KIP SIGN..SOM SIGN -20D0..20DC;N # Mn [13] COMBINING LEFT HARPOON ABOVE..COMBINING FOUR DOTS ABOVE -20DD..20E0;N # Me [4] COMBINING ENCLOSING CIRCLE..COMBINING ENCLOSING CIRCLE BACKSLASH -20E1;N # Mn COMBINING LEFT RIGHT ARROW ABOVE -20E2..20E4;N # Me [3] COMBINING ENCLOSING SCREEN..COMBINING ENCLOSING UPWARD POINTING TRIANGLE -20E5..20F0;N # Mn [12] COMBINING REVERSE SOLIDUS OVERLAY..COMBINING ASTERISK ABOVE -2100..2101;N # So [2] ACCOUNT OF..ADDRESSED TO THE SUBJECT -2102;N # Lu DOUBLE-STRUCK CAPITAL C -2103;A # So DEGREE CELSIUS -2104;N # So CENTRE LINE SYMBOL -2105;A # So CARE OF -2106;N # So CADA UNA -2107;N # Lu EULER CONSTANT -2108;N # So SCRUPLE -2109;A # So DEGREE FAHRENHEIT -210A..2112;N # L& [9] SCRIPT SMALL G..SCRIPT CAPITAL L -2113;A # Ll SCRIPT SMALL L -2114;N # So L B BAR SYMBOL -2115;N # Lu DOUBLE-STRUCK CAPITAL N -2116;A # So NUMERO SIGN -2117;N # So SOUND RECORDING COPYRIGHT -2118;N # Sm SCRIPT CAPITAL P -2119..211D;N # Lu [5] DOUBLE-STRUCK CAPITAL P..DOUBLE-STRUCK CAPITAL R -211E..2120;N # So [3] PRESCRIPTION TAKE..SERVICE MARK -2121..2122;A # So [2] TELEPHONE SIGN..TRADE MARK SIGN -2123;N # So VERSICLE -2124;N # Lu DOUBLE-STRUCK CAPITAL Z -2125;N # So OUNCE SIGN -2126;A # Lu OHM SIGN -2127;N # So INVERTED OHM SIGN -2128;N # Lu BLACK-LETTER CAPITAL Z -2129;N # So TURNED GREEK SMALL LETTER IOTA -212A;N # Lu KELVIN SIGN -212B;A # Lu ANGSTROM SIGN -212C..212D;N # Lu [2] SCRIPT CAPITAL B..BLACK-LETTER CAPITAL C -212E;N # So ESTIMATED SYMBOL -212F..2134;N # L& [6] SCRIPT SMALL E..SCRIPT SMALL O -2135..2138;N # Lo [4] ALEF SYMBOL..DALET SYMBOL -2139;N # Ll INFORMATION SOURCE -213A..213B;N # So [2] ROTATED CAPITAL Q..FACSIMILE SIGN -213C..213F;N # L& [4] DOUBLE-STRUCK SMALL PI..DOUBLE-STRUCK CAPITAL PI -2140..2144;N # Sm [5] DOUBLE-STRUCK N-ARY SUMMATION..TURNED SANS-SERIF CAPITAL Y -2145..2149;N # L& [5] DOUBLE-STRUCK ITALIC CAPITAL D..DOUBLE-STRUCK ITALIC SMALL J -214A;N # So PROPERTY LINE -214B;N # Sm TURNED AMPERSAND -214C..214D;N # So [2] PER SIGN..AKTIESELSKAB -214E;N # Ll TURNED SMALL F -214F;N # So SYMBOL FOR SAMARITAN SOURCE -2150..2152;N # No [3] VULGAR FRACTION ONE SEVENTH..VULGAR FRACTION ONE TENTH -2153..2154;A # No [2] VULGAR FRACTION ONE THIRD..VULGAR FRACTION TWO THIRDS -2155..215A;N # No [6] VULGAR FRACTION ONE FIFTH..VULGAR FRACTION FIVE SIXTHS -215B..215E;A # No [4] VULGAR FRACTION ONE EIGHTH..VULGAR FRACTION SEVEN EIGHTHS -215F;N # No FRACTION NUMERATOR ONE -2160..216B;A # Nl [12] ROMAN NUMERAL ONE..ROMAN NUMERAL TWELVE -216C..216F;N # Nl [4] ROMAN NUMERAL FIFTY..ROMAN NUMERAL ONE THOUSAND -2170..2179;A # Nl [10] SMALL ROMAN NUMERAL ONE..SMALL ROMAN NUMERAL TEN -217A..2182;N # Nl [9] SMALL ROMAN NUMERAL ELEVEN..ROMAN NUMERAL TEN THOUSAND -2183..2184;N # L& [2] ROMAN NUMERAL REVERSED ONE HUNDRED..LATIN SMALL LETTER REVERSED C -2185..2188;N # Nl [4] ROMAN NUMERAL SIX LATE FORM..ROMAN NUMERAL ONE HUNDRED THOUSAND -2189;A # No VULGAR FRACTION ZERO THIRDS -218A..218B;N # So [2] TURNED DIGIT TWO..TURNED DIGIT THREE -2190..2194;A # Sm [5] LEFTWARDS ARROW..LEFT RIGHT ARROW -2195..2199;A # So [5] UP DOWN ARROW..SOUTH WEST ARROW -219A..219B;N # Sm [2] LEFTWARDS ARROW WITH STROKE..RIGHTWARDS ARROW WITH STROKE -219C..219F;N # So [4] LEFTWARDS WAVE ARROW..UPWARDS TWO HEADED ARROW -21A0;N # Sm RIGHTWARDS TWO HEADED ARROW -21A1..21A2;N # So [2] DOWNWARDS TWO HEADED ARROW..LEFTWARDS ARROW WITH TAIL -21A3;N # Sm RIGHTWARDS ARROW WITH TAIL -21A4..21A5;N # So [2] LEFTWARDS ARROW FROM BAR..UPWARDS ARROW FROM BAR -21A6;N # Sm RIGHTWARDS ARROW FROM BAR -21A7..21AD;N # So [7] DOWNWARDS ARROW FROM BAR..LEFT RIGHT WAVE ARROW -21AE;N # Sm LEFT RIGHT ARROW WITH STROKE -21AF..21B7;N # So [9] DOWNWARDS ZIGZAG ARROW..CLOCKWISE TOP SEMICIRCLE ARROW -21B8..21B9;A # So [2] NORTH WEST ARROW TO LONG BAR..LEFTWARDS ARROW TO BAR OVER RIGHTWARDS ARROW TO BAR -21BA..21CD;N # So [20] ANTICLOCKWISE OPEN CIRCLE ARROW..LEFTWARDS DOUBLE ARROW WITH STROKE -21CE..21CF;N # Sm [2] LEFT RIGHT DOUBLE ARROW WITH STROKE..RIGHTWARDS DOUBLE ARROW WITH STROKE -21D0..21D1;N # So [2] LEFTWARDS DOUBLE ARROW..UPWARDS DOUBLE ARROW -21D2;A # Sm RIGHTWARDS DOUBLE ARROW -21D3;N # So DOWNWARDS DOUBLE ARROW -21D4;A # Sm LEFT RIGHT DOUBLE ARROW -21D5..21E6;N # So [18] UP DOWN DOUBLE ARROW..LEFTWARDS WHITE ARROW -21E7;A # So UPWARDS WHITE ARROW -21E8..21F3;N # So [12] RIGHTWARDS WHITE ARROW..UP DOWN WHITE ARROW -21F4..21FF;N # Sm [12] RIGHT ARROW WITH SMALL CIRCLE..LEFT RIGHT OPEN-HEADED ARROW -2200;A # Sm FOR ALL -2201;N # Sm COMPLEMENT -2202..2203;A # Sm [2] PARTIAL DIFFERENTIAL..THERE EXISTS -2204..2206;N # Sm [3] THERE DOES NOT EXIST..INCREMENT -2207..2208;A # Sm [2] NABLA..ELEMENT OF -2209..220A;N # Sm [2] NOT AN ELEMENT OF..SMALL ELEMENT OF -220B;A # Sm CONTAINS AS MEMBER -220C..220E;N # Sm [3] DOES NOT CONTAIN AS MEMBER..END OF PROOF -220F;A # Sm N-ARY PRODUCT -2210;N # Sm N-ARY COPRODUCT -2211;A # Sm N-ARY SUMMATION -2212..2214;N # Sm [3] MINUS SIGN..DOT PLUS -2215;A # Sm DIVISION SLASH -2216..2219;N # Sm [4] SET MINUS..BULLET OPERATOR -221A;A # Sm SQUARE ROOT -221B..221C;N # Sm [2] CUBE ROOT..FOURTH ROOT -221D..2220;A # Sm [4] PROPORTIONAL TO..ANGLE -2221..2222;N # Sm [2] MEASURED ANGLE..SPHERICAL ANGLE -2223;A # Sm DIVIDES -2224;N # Sm DOES NOT DIVIDE -2225;A # Sm PARALLEL TO -2226;N # Sm NOT PARALLEL TO -2227..222C;A # Sm [6] LOGICAL AND..DOUBLE INTEGRAL -222D;N # Sm TRIPLE INTEGRAL -222E;A # Sm CONTOUR INTEGRAL -222F..2233;N # Sm [5] SURFACE INTEGRAL..ANTICLOCKWISE CONTOUR INTEGRAL -2234..2237;A # Sm [4] THEREFORE..PROPORTION -2238..223B;N # Sm [4] DOT MINUS..HOMOTHETIC -223C..223D;A # Sm [2] TILDE OPERATOR..REVERSED TILDE -223E..2247;N # Sm [10] INVERTED LAZY S..NEITHER APPROXIMATELY NOR ACTUALLY EQUAL TO -2248;A # Sm ALMOST EQUAL TO -2249..224B;N # Sm [3] NOT ALMOST EQUAL TO..TRIPLE TILDE -224C;A # Sm ALL EQUAL TO -224D..2251;N # Sm [5] EQUIVALENT TO..GEOMETRICALLY EQUAL TO -2252;A # Sm APPROXIMATELY EQUAL TO OR THE IMAGE OF -2253..225F;N # Sm [13] IMAGE OF OR APPROXIMATELY EQUAL TO..QUESTIONED EQUAL TO -2260..2261;A # Sm [2] NOT EQUAL TO..IDENTICAL TO -2262..2263;N # Sm [2] NOT IDENTICAL TO..STRICTLY EQUIVALENT TO -2264..2267;A # Sm [4] LESS-THAN OR EQUAL TO..GREATER-THAN OVER EQUAL TO -2268..2269;N # Sm [2] LESS-THAN BUT NOT EQUAL TO..GREATER-THAN BUT NOT EQUAL TO -226A..226B;A # Sm [2] MUCH LESS-THAN..MUCH GREATER-THAN -226C..226D;N # Sm [2] BETWEEN..NOT EQUIVALENT TO -226E..226F;A # Sm [2] NOT LESS-THAN..NOT GREATER-THAN -2270..2281;N # Sm [18] NEITHER LESS-THAN NOR EQUAL TO..DOES NOT SUCCEED -2282..2283;A # Sm [2] SUBSET OF..SUPERSET OF -2284..2285;N # Sm [2] NOT A SUBSET OF..NOT A SUPERSET OF -2286..2287;A # Sm [2] SUBSET OF OR EQUAL TO..SUPERSET OF OR EQUAL TO -2288..2294;N # Sm [13] NEITHER A SUBSET OF NOR EQUAL TO..SQUARE CUP -2295;A # Sm CIRCLED PLUS -2296..2298;N # Sm [3] CIRCLED MINUS..CIRCLED DIVISION SLASH -2299;A # Sm CIRCLED DOT OPERATOR -229A..22A4;N # Sm [11] CIRCLED RING OPERATOR..DOWN TACK -22A5;A # Sm UP TACK -22A6..22BE;N # Sm [25] ASSERTION..RIGHT ANGLE WITH ARC -22BF;A # Sm RIGHT TRIANGLE -22C0..22FF;N # Sm [64] N-ARY LOGICAL AND..Z NOTATION BAG MEMBERSHIP -2300..2307;N # So [8] DIAMETER SIGN..WAVY LINE -2308;N # Ps LEFT CEILING -2309;N # Pe RIGHT CEILING -230A;N # Ps LEFT FLOOR -230B;N # Pe RIGHT FLOOR -230C..2311;N # So [6] BOTTOM RIGHT CROP..SQUARE LOZENGE -2312;A # So ARC -2313..2319;N # So [7] SEGMENT..TURNED NOT SIGN -231A..231B;W # So [2] WATCH..HOURGLASS -231C..231F;N # So [4] TOP LEFT CORNER..BOTTOM RIGHT CORNER -2320..2321;N # Sm [2] TOP HALF INTEGRAL..BOTTOM HALF INTEGRAL -2322..2328;N # So [7] FROWN..KEYBOARD -2329;W # Ps LEFT-POINTING ANGLE BRACKET -232A;W # Pe RIGHT-POINTING ANGLE BRACKET -232B..237B;N # So [81] ERASE TO THE LEFT..NOT CHECK MARK -237C;N # Sm RIGHT ANGLE WITH DOWNWARDS ZIGZAG ARROW -237D..239A;N # So [30] SHOULDERED OPEN BOX..CLEAR SCREEN SYMBOL -239B..23B3;N # Sm [25] LEFT PARENTHESIS UPPER HOOK..SUMMATION BOTTOM -23B4..23DB;N # So [40] TOP SQUARE BRACKET..FUSE -23DC..23E1;N # Sm [6] TOP PARENTHESIS..BOTTOM TORTOISE SHELL BRACKET -23E2..23E8;N # So [7] WHITE TRAPEZIUM..DECIMAL EXPONENT SYMBOL -23E9..23EC;W # So [4] BLACK RIGHT-POINTING DOUBLE TRIANGLE..BLACK DOWN-POINTING DOUBLE TRIANGLE -23ED..23EF;N # So [3] BLACK RIGHT-POINTING DOUBLE TRIANGLE WITH VERTICAL BAR..BLACK RIGHT-POINTING TRIANGLE WITH DOUBLE VERTICAL BAR -23F0;W # So ALARM CLOCK -23F1..23F2;N # So [2] STOPWATCH..TIMER CLOCK -23F3;W # So HOURGLASS WITH FLOWING SAND -23F4..23FF;N # So [12] BLACK MEDIUM LEFT-POINTING TRIANGLE..OBSERVER EYE SYMBOL -2400..2426;N # So [39] SYMBOL FOR NULL..SYMBOL FOR SUBSTITUTE FORM TWO -2440..244A;N # So [11] OCR HOOK..OCR DOUBLE BACKSLASH -2460..249B;A # No [60] CIRCLED DIGIT ONE..NUMBER TWENTY FULL STOP -249C..24E9;A # So [78] PARENTHESIZED LATIN SMALL LETTER A..CIRCLED LATIN SMALL LETTER Z -24EA;N # No CIRCLED DIGIT ZERO -24EB..24FF;A # No [21] NEGATIVE CIRCLED NUMBER ELEVEN..NEGATIVE CIRCLED DIGIT ZERO -2500..254B;A # So [76] BOX DRAWINGS LIGHT HORIZONTAL..BOX DRAWINGS HEAVY VERTICAL AND HORIZONTAL -254C..254F;N # So [4] BOX DRAWINGS LIGHT DOUBLE DASH HORIZONTAL..BOX DRAWINGS HEAVY DOUBLE DASH VERTICAL -2550..2573;A # So [36] BOX DRAWINGS DOUBLE HORIZONTAL..BOX DRAWINGS LIGHT DIAGONAL CROSS -2574..257F;N # So [12] BOX DRAWINGS LIGHT LEFT..BOX DRAWINGS HEAVY UP AND LIGHT DOWN -2580..258F;A # So [16] UPPER HALF BLOCK..LEFT ONE EIGHTH BLOCK -2590..2591;N # So [2] RIGHT HALF BLOCK..LIGHT SHADE -2592..2595;A # So [4] MEDIUM SHADE..RIGHT ONE EIGHTH BLOCK -2596..259F;N # So [10] QUADRANT LOWER LEFT..QUADRANT UPPER RIGHT AND LOWER LEFT AND LOWER RIGHT -25A0..25A1;A # So [2] BLACK SQUARE..WHITE SQUARE -25A2;N # So WHITE SQUARE WITH ROUNDED CORNERS -25A3..25A9;A # So [7] WHITE SQUARE CONTAINING BLACK SMALL SQUARE..SQUARE WITH DIAGONAL CROSSHATCH FILL -25AA..25B1;N # So [8] BLACK SMALL SQUARE..WHITE PARALLELOGRAM -25B2..25B3;A # So [2] BLACK UP-POINTING TRIANGLE..WHITE UP-POINTING TRIANGLE -25B4..25B5;N # So [2] BLACK UP-POINTING SMALL TRIANGLE..WHITE UP-POINTING SMALL TRIANGLE -25B6;A # So BLACK RIGHT-POINTING TRIANGLE -25B7;A # Sm WHITE RIGHT-POINTING TRIANGLE -25B8..25BB;N # So [4] BLACK RIGHT-POINTING SMALL TRIANGLE..WHITE RIGHT-POINTING POINTER -25BC..25BD;A # So [2] BLACK DOWN-POINTING TRIANGLE..WHITE DOWN-POINTING TRIANGLE -25BE..25BF;N # So [2] BLACK DOWN-POINTING SMALL TRIANGLE..WHITE DOWN-POINTING SMALL TRIANGLE -25C0;A # So BLACK LEFT-POINTING TRIANGLE -25C1;A # Sm WHITE LEFT-POINTING TRIANGLE -25C2..25C5;N # So [4] BLACK LEFT-POINTING SMALL TRIANGLE..WHITE LEFT-POINTING POINTER -25C6..25C8;A # So [3] BLACK DIAMOND..WHITE DIAMOND CONTAINING BLACK SMALL DIAMOND -25C9..25CA;N # So [2] FISHEYE..LOZENGE -25CB;A # So WHITE CIRCLE -25CC..25CD;N # So [2] DOTTED CIRCLE..CIRCLE WITH VERTICAL FILL -25CE..25D1;A # So [4] BULLSEYE..CIRCLE WITH RIGHT HALF BLACK -25D2..25E1;N # So [16] CIRCLE WITH LOWER HALF BLACK..LOWER HALF CIRCLE -25E2..25E5;A # So [4] BLACK LOWER RIGHT TRIANGLE..BLACK UPPER RIGHT TRIANGLE -25E6..25EE;N # So [9] WHITE BULLET..UP-POINTING TRIANGLE WITH RIGHT HALF BLACK -25EF;A # So LARGE CIRCLE -25F0..25F7;N # So [8] WHITE SQUARE WITH UPPER LEFT QUADRANT..WHITE CIRCLE WITH UPPER RIGHT QUADRANT -25F8..25FC;N # Sm [5] UPPER LEFT TRIANGLE..BLACK MEDIUM SQUARE -25FD..25FE;W # Sm [2] WHITE MEDIUM SMALL SQUARE..BLACK MEDIUM SMALL SQUARE -25FF;N # Sm LOWER RIGHT TRIANGLE -2600..2604;N # So [5] BLACK SUN WITH RAYS..COMET -2605..2606;A # So [2] BLACK STAR..WHITE STAR -2607..2608;N # So [2] LIGHTNING..THUNDERSTORM -2609;A # So SUN -260A..260D;N # So [4] ASCENDING NODE..OPPOSITION -260E..260F;A # So [2] BLACK TELEPHONE..WHITE TELEPHONE -2610..2613;N # So [4] BALLOT BOX..SALTIRE -2614..2615;W # So [2] UMBRELLA WITH RAIN DROPS..HOT BEVERAGE -2616..261B;N # So [6] WHITE SHOGI PIECE..BLACK RIGHT POINTING INDEX -261C;A # So WHITE LEFT POINTING INDEX -261D;N # So WHITE UP POINTING INDEX -261E;A # So WHITE RIGHT POINTING INDEX -261F..263F;N # So [33] WHITE DOWN POINTING INDEX..MERCURY -2640;A # So FEMALE SIGN -2641;N # So EARTH -2642;A # So MALE SIGN -2643..2647;N # So [5] JUPITER..PLUTO -2648..2653;W # So [12] ARIES..PISCES -2654..265F;N # So [12] WHITE CHESS KING..BLACK CHESS PAWN -2660..2661;A # So [2] BLACK SPADE SUIT..WHITE HEART SUIT -2662;N # So WHITE DIAMOND SUIT -2663..2665;A # So [3] BLACK CLUB SUIT..BLACK HEART SUIT -2666;N # So BLACK DIAMOND SUIT -2667..266A;A # So [4] WHITE CLUB SUIT..EIGHTH NOTE -266B;N # So BEAMED EIGHTH NOTES -266C..266D;A # So [2] BEAMED SIXTEENTH NOTES..MUSIC FLAT SIGN -266E;N # So MUSIC NATURAL SIGN -266F;A # Sm MUSIC SHARP SIGN -2670..267E;N # So [15] WEST SYRIAC CROSS..PERMANENT PAPER SIGN -267F;W # So WHEELCHAIR SYMBOL -2680..2692;N # So [19] DIE FACE-1..HAMMER AND PICK -2693;W # So ANCHOR -2694..269D;N # So [10] CROSSED SWORDS..OUTLINED WHITE STAR -269E..269F;A # So [2] THREE LINES CONVERGING RIGHT..THREE LINES CONVERGING LEFT -26A0;N # So WARNING SIGN -26A1;W # So HIGH VOLTAGE SIGN -26A2..26A9;N # So [8] DOUBLED FEMALE SIGN..HORIZONTAL MALE WITH STROKE SIGN -26AA..26AB;W # So [2] MEDIUM WHITE CIRCLE..MEDIUM BLACK CIRCLE -26AC..26BC;N # So [17] MEDIUM SMALL WHITE CIRCLE..SESQUIQUADRATE -26BD..26BE;W # So [2] SOCCER BALL..BASEBALL -26BF;A # So SQUARED KEY -26C0..26C3;N # So [4] WHITE DRAUGHTS MAN..BLACK DRAUGHTS KING -26C4..26C5;W # So [2] SNOWMAN WITHOUT SNOW..SUN BEHIND CLOUD -26C6..26CD;A # So [8] RAIN..DISABLED CAR -26CE;W # So OPHIUCHUS -26CF..26D3;A # So [5] PICK..CHAINS -26D4;W # So NO ENTRY -26D5..26E1;A # So [13] ALTERNATE ONE-WAY LEFT WAY TRAFFIC..RESTRICTED LEFT ENTRY-2 -26E2;N # So ASTRONOMICAL SYMBOL FOR URANUS -26E3;A # So HEAVY CIRCLE WITH STROKE AND TWO DOTS ABOVE -26E4..26E7;N # So [4] PENTAGRAM..INVERTED PENTAGRAM -26E8..26E9;A # So [2] BLACK CROSS ON SHIELD..SHINTO SHRINE -26EA;W # So CHURCH -26EB..26F1;A # So [7] CASTLE..UMBRELLA ON GROUND -26F2..26F3;W # So [2] FOUNTAIN..FLAG IN HOLE -26F4;A # So FERRY -26F5;W # So SAILBOAT -26F6..26F9;A # So [4] SQUARE FOUR CORNERS..PERSON WITH BALL -26FA;W # So TENT -26FB..26FC;A # So [2] JAPANESE BANK SYMBOL..HEADSTONE GRAVEYARD SYMBOL -26FD;W # So FUEL PUMP -26FE..26FF;A # So [2] CUP ON BLACK SQUARE..WHITE FLAG WITH HORIZONTAL MIDDLE BLACK STRIPE -2700..2704;N # So [5] BLACK SAFETY SCISSORS..WHITE SCISSORS -2705;W # So WHITE HEAVY CHECK MARK -2706..2709;N # So [4] TELEPHONE LOCATION SIGN..ENVELOPE -270A..270B;W # So [2] RAISED FIST..RAISED HAND -270C..2727;N # So [28] VICTORY HAND..WHITE FOUR POINTED STAR -2728;W # So SPARKLES -2729..273C;N # So [20] STRESS OUTLINED WHITE STAR..OPEN CENTRE TEARDROP-SPOKED ASTERISK -273D;A # So HEAVY TEARDROP-SPOKED ASTERISK -273E..274B;N # So [14] SIX PETALLED BLACK AND WHITE FLORETTE..HEAVY EIGHT TEARDROP-SPOKED PROPELLER ASTERISK -274C;W # So CROSS MARK -274D;N # So SHADOWED WHITE CIRCLE -274E;W # So NEGATIVE SQUARED CROSS MARK -274F..2752;N # So [4] LOWER RIGHT DROP-SHADOWED WHITE SQUARE..UPPER RIGHT SHADOWED WHITE SQUARE -2753..2755;W # So [3] BLACK QUESTION MARK ORNAMENT..WHITE EXCLAMATION MARK ORNAMENT -2756;N # So BLACK DIAMOND MINUS WHITE X -2757;W # So HEAVY EXCLAMATION MARK SYMBOL -2758..2767;N # So [16] LIGHT VERTICAL BAR..ROTATED FLORAL HEART BULLET -2768;N # Ps MEDIUM LEFT PARENTHESIS ORNAMENT -2769;N # Pe MEDIUM RIGHT PARENTHESIS ORNAMENT -276A;N # Ps MEDIUM FLATTENED LEFT PARENTHESIS ORNAMENT -276B;N # Pe MEDIUM FLATTENED RIGHT PARENTHESIS ORNAMENT -276C;N # Ps MEDIUM LEFT-POINTING ANGLE BRACKET ORNAMENT -276D;N # Pe MEDIUM RIGHT-POINTING ANGLE BRACKET ORNAMENT -276E;N # Ps HEAVY LEFT-POINTING ANGLE QUOTATION MARK ORNAMENT -276F;N # Pe HEAVY RIGHT-POINTING ANGLE QUOTATION MARK ORNAMENT -2770;N # Ps HEAVY LEFT-POINTING ANGLE BRACKET ORNAMENT -2771;N # Pe HEAVY RIGHT-POINTING ANGLE BRACKET ORNAMENT -2772;N # Ps LIGHT LEFT TORTOISE SHELL BRACKET ORNAMENT -2773;N # Pe LIGHT RIGHT TORTOISE SHELL BRACKET ORNAMENT -2774;N # Ps MEDIUM LEFT CURLY BRACKET ORNAMENT -2775;N # Pe MEDIUM RIGHT CURLY BRACKET ORNAMENT -2776..277F;A # No [10] DINGBAT NEGATIVE CIRCLED DIGIT ONE..DINGBAT NEGATIVE CIRCLED NUMBER TEN -2780..2793;N # No [20] DINGBAT CIRCLED SANS-SERIF DIGIT ONE..DINGBAT NEGATIVE CIRCLED SANS-SERIF NUMBER TEN -2794;N # So HEAVY WIDE-HEADED RIGHTWARDS ARROW -2795..2797;W # So [3] HEAVY PLUS SIGN..HEAVY DIVISION SIGN -2798..27AF;N # So [24] HEAVY SOUTH EAST ARROW..NOTCHED LOWER RIGHT-SHADOWED WHITE RIGHTWARDS ARROW -27B0;W # So CURLY LOOP -27B1..27BE;N # So [14] NOTCHED UPPER RIGHT-SHADOWED WHITE RIGHTWARDS ARROW..OPEN-OUTLINED RIGHTWARDS ARROW -27BF;W # So DOUBLE CURLY LOOP -27C0..27C4;N # Sm [5] THREE DIMENSIONAL ANGLE..OPEN SUPERSET -27C5;N # Ps LEFT S-SHAPED BAG DELIMITER -27C6;N # Pe RIGHT S-SHAPED BAG DELIMITER -27C7..27E5;N # Sm [31] OR WITH DOT INSIDE..WHITE SQUARE WITH RIGHTWARDS TICK -27E6;Na # Ps MATHEMATICAL LEFT WHITE SQUARE BRACKET -27E7;Na # Pe MATHEMATICAL RIGHT WHITE SQUARE BRACKET -27E8;Na # Ps MATHEMATICAL LEFT ANGLE BRACKET -27E9;Na # Pe MATHEMATICAL RIGHT ANGLE BRACKET -27EA;Na # Ps MATHEMATICAL LEFT DOUBLE ANGLE BRACKET -27EB;Na # Pe MATHEMATICAL RIGHT DOUBLE ANGLE BRACKET -27EC;Na # Ps MATHEMATICAL LEFT WHITE TORTOISE SHELL BRACKET -27ED;Na # Pe MATHEMATICAL RIGHT WHITE TORTOISE SHELL BRACKET -27EE;N # Ps MATHEMATICAL LEFT FLATTENED PARENTHESIS -27EF;N # Pe MATHEMATICAL RIGHT FLATTENED PARENTHESIS -27F0..27FF;N # Sm [16] UPWARDS QUADRUPLE ARROW..LONG RIGHTWARDS SQUIGGLE ARROW -2800..28FF;N # So [256] BRAILLE PATTERN BLANK..BRAILLE PATTERN DOTS-12345678 -2900..297F;N # Sm [128] RIGHTWARDS TWO-HEADED ARROW WITH VERTICAL STROKE..DOWN FISH TAIL -2980..2982;N # Sm [3] TRIPLE VERTICAL BAR DELIMITER..Z NOTATION TYPE COLON -2983;N # Ps LEFT WHITE CURLY BRACKET -2984;N # Pe RIGHT WHITE CURLY BRACKET -2985;Na # Ps LEFT WHITE PARENTHESIS -2986;Na # Pe RIGHT WHITE PARENTHESIS -2987;N # Ps Z NOTATION LEFT IMAGE BRACKET -2988;N # Pe Z NOTATION RIGHT IMAGE BRACKET -2989;N # Ps Z NOTATION LEFT BINDING BRACKET -298A;N # Pe Z NOTATION RIGHT BINDING BRACKET -298B;N # Ps LEFT SQUARE BRACKET WITH UNDERBAR -298C;N # Pe RIGHT SQUARE BRACKET WITH UNDERBAR -298D;N # Ps LEFT SQUARE BRACKET WITH TICK IN TOP CORNER -298E;N # Pe RIGHT SQUARE BRACKET WITH TICK IN BOTTOM CORNER -298F;N # Ps LEFT SQUARE BRACKET WITH TICK IN BOTTOM CORNER -2990;N # Pe RIGHT SQUARE BRACKET WITH TICK IN TOP CORNER -2991;N # Ps LEFT ANGLE BRACKET WITH DOT -2992;N # Pe RIGHT ANGLE BRACKET WITH DOT -2993;N # Ps LEFT ARC LESS-THAN BRACKET -2994;N # Pe RIGHT ARC GREATER-THAN BRACKET -2995;N # Ps DOUBLE LEFT ARC GREATER-THAN BRACKET -2996;N # Pe DOUBLE RIGHT ARC LESS-THAN BRACKET -2997;N # Ps LEFT BLACK TORTOISE SHELL BRACKET -2998;N # Pe RIGHT BLACK TORTOISE SHELL BRACKET -2999..29D7;N # Sm [63] DOTTED FENCE..BLACK HOURGLASS -29D8;N # Ps LEFT WIGGLY FENCE -29D9;N # Pe RIGHT WIGGLY FENCE -29DA;N # Ps LEFT DOUBLE WIGGLY FENCE -29DB;N # Pe RIGHT DOUBLE WIGGLY FENCE -29DC..29FB;N # Sm [32] INCOMPLETE INFINITY..TRIPLE PLUS -29FC;N # Ps LEFT-POINTING CURVED ANGLE BRACKET -29FD;N # Pe RIGHT-POINTING CURVED ANGLE BRACKET -29FE..29FF;N # Sm [2] TINY..MINY -2A00..2AFF;N # Sm [256] N-ARY CIRCLED DOT OPERATOR..N-ARY WHITE VERTICAL BAR -2B00..2B1A;N # So [27] NORTH EAST WHITE ARROW..DOTTED SQUARE -2B1B..2B1C;W # So [2] BLACK LARGE SQUARE..WHITE LARGE SQUARE -2B1D..2B2F;N # So [19] BLACK VERY SMALL SQUARE..WHITE VERTICAL ELLIPSE -2B30..2B44;N # Sm [21] LEFT ARROW WITH SMALL CIRCLE..RIGHTWARDS ARROW THROUGH SUPERSET -2B45..2B46;N # So [2] LEFTWARDS QUADRUPLE ARROW..RIGHTWARDS QUADRUPLE ARROW -2B47..2B4C;N # Sm [6] REVERSE TILDE OPERATOR ABOVE RIGHTWARDS ARROW..RIGHTWARDS ARROW ABOVE REVERSE TILDE OPERATOR -2B4D..2B4F;N # So [3] DOWNWARDS TRIANGLE-HEADED ZIGZAG ARROW..SHORT BACKSLANTED SOUTH ARROW -2B50;W # So WHITE MEDIUM STAR -2B51..2B54;N # So [4] BLACK SMALL STAR..WHITE RIGHT-POINTING PENTAGON -2B55;W # So HEAVY LARGE CIRCLE -2B56..2B59;A # So [4] HEAVY OVAL WITH OVAL INSIDE..HEAVY CIRCLED SALTIRE -2B5A..2B73;N # So [26] SLANTED NORTH ARROW WITH HOOKED HEAD..DOWNWARDS TRIANGLE-HEADED ARROW TO BAR -2B76..2B95;N # So [32] NORTH WEST TRIANGLE-HEADED ARROW TO BAR..RIGHTWARDS BLACK ARROW -2B97..2BFF;N # So [105] SYMBOL FOR TYPE A ELECTRONICS..HELLSCHREIBER PAUSE SYMBOL -2C00..2C5F;N # L& [96] GLAGOLITIC CAPITAL LETTER AZU..GLAGOLITIC SMALL LETTER CAUDATE CHRIVI -2C60..2C7B;N # L& [28] LATIN CAPITAL LETTER L WITH DOUBLE BAR..LATIN LETTER SMALL CAPITAL TURNED E -2C7C..2C7D;N # Lm [2] LATIN SUBSCRIPT SMALL LETTER J..MODIFIER LETTER CAPITAL V -2C7E..2C7F;N # Lu [2] LATIN CAPITAL LETTER S WITH SWASH TAIL..LATIN CAPITAL LETTER Z WITH SWASH TAIL -2C80..2CE4;N # L& [101] COPTIC CAPITAL LETTER ALFA..COPTIC SYMBOL KAI -2CE5..2CEA;N # So [6] COPTIC SYMBOL MI RO..COPTIC SYMBOL SHIMA SIMA -2CEB..2CEE;N # L& [4] COPTIC CAPITAL LETTER CRYPTOGRAMMIC SHEI..COPTIC SMALL LETTER CRYPTOGRAMMIC GANGIA -2CEF..2CF1;N # Mn [3] COPTIC COMBINING NI ABOVE..COPTIC COMBINING SPIRITUS LENIS -2CF2..2CF3;N # L& [2] COPTIC CAPITAL LETTER BOHAIRIC KHEI..COPTIC SMALL LETTER BOHAIRIC KHEI -2CF9..2CFC;N # Po [4] COPTIC OLD NUBIAN FULL STOP..COPTIC OLD NUBIAN VERSE DIVIDER -2CFD;N # No COPTIC FRACTION ONE HALF -2CFE..2CFF;N # Po [2] COPTIC FULL STOP..COPTIC MORPHOLOGICAL DIVIDER -2D00..2D25;N # Ll [38] GEORGIAN SMALL LETTER AN..GEORGIAN SMALL LETTER HOE -2D27;N # Ll GEORGIAN SMALL LETTER YN -2D2D;N # Ll GEORGIAN SMALL LETTER AEN -2D30..2D67;N # Lo [56] TIFINAGH LETTER YA..TIFINAGH LETTER YO -2D6F;N # Lm TIFINAGH MODIFIER LETTER LABIALIZATION MARK -2D70;N # Po TIFINAGH SEPARATOR MARK -2D7F;N # Mn TIFINAGH CONSONANT JOINER -2D80..2D96;N # Lo [23] ETHIOPIC SYLLABLE LOA..ETHIOPIC SYLLABLE GGWE -2DA0..2DA6;N # Lo [7] ETHIOPIC SYLLABLE SSA..ETHIOPIC SYLLABLE SSO -2DA8..2DAE;N # Lo [7] ETHIOPIC SYLLABLE CCA..ETHIOPIC SYLLABLE CCO -2DB0..2DB6;N # Lo [7] ETHIOPIC SYLLABLE ZZA..ETHIOPIC SYLLABLE ZZO -2DB8..2DBE;N # Lo [7] ETHIOPIC SYLLABLE CCHA..ETHIOPIC SYLLABLE CCHO -2DC0..2DC6;N # Lo [7] ETHIOPIC SYLLABLE QYA..ETHIOPIC SYLLABLE QYO -2DC8..2DCE;N # Lo [7] ETHIOPIC SYLLABLE KYA..ETHIOPIC SYLLABLE KYO -2DD0..2DD6;N # Lo [7] ETHIOPIC SYLLABLE XYA..ETHIOPIC SYLLABLE XYO -2DD8..2DDE;N # Lo [7] ETHIOPIC SYLLABLE GYA..ETHIOPIC SYLLABLE GYO -2DE0..2DFF;N # Mn [32] COMBINING CYRILLIC LETTER BE..COMBINING CYRILLIC LETTER IOTIFIED BIG YUS -2E00..2E01;N # Po [2] RIGHT ANGLE SUBSTITUTION MARKER..RIGHT ANGLE DOTTED SUBSTITUTION MARKER -2E02;N # Pi LEFT SUBSTITUTION BRACKET -2E03;N # Pf RIGHT SUBSTITUTION BRACKET -2E04;N # Pi LEFT DOTTED SUBSTITUTION BRACKET -2E05;N # Pf RIGHT DOTTED SUBSTITUTION BRACKET -2E06..2E08;N # Po [3] RAISED INTERPOLATION MARKER..DOTTED TRANSPOSITION MARKER -2E09;N # Pi LEFT TRANSPOSITION BRACKET -2E0A;N # Pf RIGHT TRANSPOSITION BRACKET -2E0B;N # Po RAISED SQUARE -2E0C;N # Pi LEFT RAISED OMISSION BRACKET -2E0D;N # Pf RIGHT RAISED OMISSION BRACKET -2E0E..2E16;N # Po [9] EDITORIAL CORONIS..DOTTED RIGHT-POINTING ANGLE -2E17;N # Pd DOUBLE OBLIQUE HYPHEN -2E18..2E19;N # Po [2] INVERTED INTERROBANG..PALM BRANCH -2E1A;N # Pd HYPHEN WITH DIAERESIS -2E1B;N # Po TILDE WITH RING ABOVE -2E1C;N # Pi LEFT LOW PARAPHRASE BRACKET -2E1D;N # Pf RIGHT LOW PARAPHRASE BRACKET -2E1E..2E1F;N # Po [2] TILDE WITH DOT ABOVE..TILDE WITH DOT BELOW -2E20;N # Pi LEFT VERTICAL BAR WITH QUILL -2E21;N # Pf RIGHT VERTICAL BAR WITH QUILL -2E22;N # Ps TOP LEFT HALF BRACKET -2E23;N # Pe TOP RIGHT HALF BRACKET -2E24;N # Ps BOTTOM LEFT HALF BRACKET -2E25;N # Pe BOTTOM RIGHT HALF BRACKET -2E26;N # Ps LEFT SIDEWAYS U BRACKET -2E27;N # Pe RIGHT SIDEWAYS U BRACKET -2E28;N # Ps LEFT DOUBLE PARENTHESIS -2E29;N # Pe RIGHT DOUBLE PARENTHESIS -2E2A..2E2E;N # Po [5] TWO DOTS OVER ONE DOT PUNCTUATION..REVERSED QUESTION MARK -2E2F;N # Lm VERTICAL TILDE -2E30..2E39;N # Po [10] RING POINT..TOP HALF SECTION SIGN -2E3A..2E3B;N # Pd [2] TWO-EM DASH..THREE-EM DASH -2E3C..2E3F;N # Po [4] STENOGRAPHIC FULL STOP..CAPITULUM -2E40;N # Pd DOUBLE HYPHEN -2E41;N # Po REVERSED COMMA -2E42;N # Ps DOUBLE LOW-REVERSED-9 QUOTATION MARK -2E43..2E4F;N # Po [13] DASH WITH LEFT UPTURN..CORNISH VERSE DIVIDER -2E50..2E51;N # So [2] CROSS PATTY WITH RIGHT CROSSBAR..CROSS PATTY WITH LEFT CROSSBAR -2E52..2E54;N # Po [3] TIRONIAN SIGN CAPITAL ET..MEDIEVAL QUESTION MARK -2E55;N # Ps LEFT SQUARE BRACKET WITH STROKE -2E56;N # Pe RIGHT SQUARE BRACKET WITH STROKE -2E57;N # Ps LEFT SQUARE BRACKET WITH DOUBLE STROKE -2E58;N # Pe RIGHT SQUARE BRACKET WITH DOUBLE STROKE -2E59;N # Ps TOP HALF LEFT PARENTHESIS -2E5A;N # Pe TOP HALF RIGHT PARENTHESIS -2E5B;N # Ps BOTTOM HALF LEFT PARENTHESIS -2E5C;N # Pe BOTTOM HALF RIGHT PARENTHESIS -2E5D;N # Pd OBLIQUE HYPHEN -2E80..2E99;W # So [26] CJK RADICAL REPEAT..CJK RADICAL RAP -2E9B..2EF3;W # So [89] CJK RADICAL CHOKE..CJK RADICAL C-SIMPLIFIED TURTLE -2F00..2FD5;W # So [214] KANGXI RADICAL ONE..KANGXI RADICAL FLUTE -2FF0..2FFB;W # So [12] IDEOGRAPHIC DESCRIPTION CHARACTER LEFT TO RIGHT..IDEOGRAPHIC DESCRIPTION CHARACTER OVERLAID -3000;F # Zs IDEOGRAPHIC SPACE -3001..3003;W # Po [3] IDEOGRAPHIC COMMA..DITTO MARK -3004;W # So JAPANESE INDUSTRIAL STANDARD SYMBOL -3005;W # Lm IDEOGRAPHIC ITERATION MARK -3006;W # Lo IDEOGRAPHIC CLOSING MARK -3007;W # Nl IDEOGRAPHIC NUMBER ZERO -3008;W # Ps LEFT ANGLE BRACKET -3009;W # Pe RIGHT ANGLE BRACKET -300A;W # Ps LEFT DOUBLE ANGLE BRACKET -300B;W # Pe RIGHT DOUBLE ANGLE BRACKET -300C;W # Ps LEFT CORNER BRACKET -300D;W # Pe RIGHT CORNER BRACKET -300E;W # Ps LEFT WHITE CORNER BRACKET -300F;W # Pe RIGHT WHITE CORNER BRACKET -3010;W # Ps LEFT BLACK LENTICULAR BRACKET -3011;W # Pe RIGHT BLACK LENTICULAR BRACKET -3012..3013;W # So [2] POSTAL MARK..GETA MARK -3014;W # Ps LEFT TORTOISE SHELL BRACKET -3015;W # Pe RIGHT TORTOISE SHELL BRACKET -3016;W # Ps LEFT WHITE LENTICULAR BRACKET -3017;W # Pe RIGHT WHITE LENTICULAR BRACKET -3018;W # Ps LEFT WHITE TORTOISE SHELL BRACKET -3019;W # Pe RIGHT WHITE TORTOISE SHELL BRACKET -301A;W # Ps LEFT WHITE SQUARE BRACKET -301B;W # Pe RIGHT WHITE SQUARE BRACKET -301C;W # Pd WAVE DASH -301D;W # Ps REVERSED DOUBLE PRIME QUOTATION MARK -301E..301F;W # Pe [2] DOUBLE PRIME QUOTATION MARK..LOW DOUBLE PRIME QUOTATION MARK -3020;W # So POSTAL MARK FACE -3021..3029;W # Nl [9] HANGZHOU NUMERAL ONE..HANGZHOU NUMERAL NINE -302A..302D;W # Mn [4] IDEOGRAPHIC LEVEL TONE MARK..IDEOGRAPHIC ENTERING TONE MARK -302E..302F;W # Mc [2] HANGUL SINGLE DOT TONE MARK..HANGUL DOUBLE DOT TONE MARK -3030;W # Pd WAVY DASH -3031..3035;W # Lm [5] VERTICAL KANA REPEAT MARK..VERTICAL KANA REPEAT MARK LOWER HALF -3036..3037;W # So [2] CIRCLED POSTAL MARK..IDEOGRAPHIC TELEGRAPH LINE FEED SEPARATOR SYMBOL -3038..303A;W # Nl [3] HANGZHOU NUMERAL TEN..HANGZHOU NUMERAL THIRTY -303B;W # Lm VERTICAL IDEOGRAPHIC ITERATION MARK -303C;W # Lo MASU MARK -303D;W # Po PART ALTERNATION MARK -303E;W # So IDEOGRAPHIC VARIATION INDICATOR -303F;N # So IDEOGRAPHIC HALF FILL SPACE -3041..3096;W # Lo [86] HIRAGANA LETTER SMALL A..HIRAGANA LETTER SMALL KE -3099..309A;W # Mn [2] COMBINING KATAKANA-HIRAGANA VOICED SOUND MARK..COMBINING KATAKANA-HIRAGANA SEMI-VOICED SOUND MARK -309B..309C;W # Sk [2] KATAKANA-HIRAGANA VOICED SOUND MARK..KATAKANA-HIRAGANA SEMI-VOICED SOUND MARK -309D..309E;W # Lm [2] HIRAGANA ITERATION MARK..HIRAGANA VOICED ITERATION MARK -309F;W # Lo HIRAGANA DIGRAPH YORI -30A0;W # Pd KATAKANA-HIRAGANA DOUBLE HYPHEN -30A1..30FA;W # Lo [90] KATAKANA LETTER SMALL A..KATAKANA LETTER VO -30FB;W # Po KATAKANA MIDDLE DOT -30FC..30FE;W # Lm [3] KATAKANA-HIRAGANA PROLONGED SOUND MARK..KATAKANA VOICED ITERATION MARK -30FF;W # Lo KATAKANA DIGRAPH KOTO -3105..312F;W # Lo [43] BOPOMOFO LETTER B..BOPOMOFO LETTER NN -3131..318E;W # Lo [94] HANGUL LETTER KIYEOK..HANGUL LETTER ARAEAE -3190..3191;W # So [2] IDEOGRAPHIC ANNOTATION LINKING MARK..IDEOGRAPHIC ANNOTATION REVERSE MARK -3192..3195;W # No [4] IDEOGRAPHIC ANNOTATION ONE MARK..IDEOGRAPHIC ANNOTATION FOUR MARK -3196..319F;W # So [10] IDEOGRAPHIC ANNOTATION TOP MARK..IDEOGRAPHIC ANNOTATION MAN MARK -31A0..31BF;W # Lo [32] BOPOMOFO LETTER BU..BOPOMOFO LETTER AH -31C0..31E3;W # So [36] CJK STROKE T..CJK STROKE Q -31F0..31FF;W # Lo [16] KATAKANA LETTER SMALL KU..KATAKANA LETTER SMALL RO -3200..321E;W # So [31] PARENTHESIZED HANGUL KIYEOK..PARENTHESIZED KOREAN CHARACTER O HU -3220..3229;W # No [10] PARENTHESIZED IDEOGRAPH ONE..PARENTHESIZED IDEOGRAPH TEN -322A..3247;W # So [30] PARENTHESIZED IDEOGRAPH MOON..CIRCLED IDEOGRAPH KOTO -3248..324F;A # No [8] CIRCLED NUMBER TEN ON BLACK SQUARE..CIRCLED NUMBER EIGHTY ON BLACK SQUARE -3250;W # So PARTNERSHIP SIGN -3251..325F;W # No [15] CIRCLED NUMBER TWENTY ONE..CIRCLED NUMBER THIRTY FIVE -3260..327F;W # So [32] CIRCLED HANGUL KIYEOK..KOREAN STANDARD SYMBOL -3280..3289;W # No [10] CIRCLED IDEOGRAPH ONE..CIRCLED IDEOGRAPH TEN -328A..32B0;W # So [39] CIRCLED IDEOGRAPH MOON..CIRCLED IDEOGRAPH NIGHT -32B1..32BF;W # No [15] CIRCLED NUMBER THIRTY SIX..CIRCLED NUMBER FIFTY -32C0..32FF;W # So [64] IDEOGRAPHIC TELEGRAPH SYMBOL FOR JANUARY..SQUARE ERA NAME REIWA -3300..33FF;W # So [256] SQUARE APAATO..SQUARE GAL -3400..4DBF;W # Lo [6592] CJK UNIFIED IDEOGRAPH-3400..CJK UNIFIED IDEOGRAPH-4DBF -4DC0..4DFF;N # So [64] HEXAGRAM FOR THE CREATIVE HEAVEN..HEXAGRAM FOR BEFORE COMPLETION -4E00..9FFF;W # Lo [20992] CJK UNIFIED IDEOGRAPH-4E00..CJK UNIFIED IDEOGRAPH-9FFF -A000..A014;W # Lo [21] YI SYLLABLE IT..YI SYLLABLE E -A015;W # Lm YI SYLLABLE WU -A016..A48C;W # Lo [1143] YI SYLLABLE BIT..YI SYLLABLE YYR -A490..A4C6;W # So [55] YI RADICAL QOT..YI RADICAL KE -A4D0..A4F7;N # Lo [40] LISU LETTER BA..LISU LETTER OE -A4F8..A4FD;N # Lm [6] LISU LETTER TONE MYA TI..LISU LETTER TONE MYA JEU -A4FE..A4FF;N # Po [2] LISU PUNCTUATION COMMA..LISU PUNCTUATION FULL STOP -A500..A60B;N # Lo [268] VAI SYLLABLE EE..VAI SYLLABLE NG -A60C;N # Lm VAI SYLLABLE LENGTHENER -A60D..A60F;N # Po [3] VAI COMMA..VAI QUESTION MARK -A610..A61F;N # Lo [16] VAI SYLLABLE NDOLE FA..VAI SYMBOL JONG -A620..A629;N # Nd [10] VAI DIGIT ZERO..VAI DIGIT NINE -A62A..A62B;N # Lo [2] VAI SYLLABLE NDOLE MA..VAI SYLLABLE NDOLE DO -A640..A66D;N # L& [46] CYRILLIC CAPITAL LETTER ZEMLYA..CYRILLIC SMALL LETTER DOUBLE MONOCULAR O -A66E;N # Lo CYRILLIC LETTER MULTIOCULAR O -A66F;N # Mn COMBINING CYRILLIC VZMET -A670..A672;N # Me [3] COMBINING CYRILLIC TEN MILLIONS SIGN..COMBINING CYRILLIC THOUSAND MILLIONS SIGN -A673;N # Po SLAVONIC ASTERISK -A674..A67D;N # Mn [10] COMBINING CYRILLIC LETTER UKRAINIAN IE..COMBINING CYRILLIC PAYEROK -A67E;N # Po CYRILLIC KAVYKA -A67F;N # Lm CYRILLIC PAYEROK -A680..A69B;N # L& [28] CYRILLIC CAPITAL LETTER DWE..CYRILLIC SMALL LETTER CROSSED O -A69C..A69D;N # Lm [2] MODIFIER LETTER CYRILLIC HARD SIGN..MODIFIER LETTER CYRILLIC SOFT SIGN -A69E..A69F;N # Mn [2] COMBINING CYRILLIC LETTER EF..COMBINING CYRILLIC LETTER IOTIFIED E -A6A0..A6E5;N # Lo [70] BAMUM LETTER A..BAMUM LETTER KI -A6E6..A6EF;N # Nl [10] BAMUM LETTER MO..BAMUM LETTER KOGHOM -A6F0..A6F1;N # Mn [2] BAMUM COMBINING MARK KOQNDON..BAMUM COMBINING MARK TUKWENTIS -A6F2..A6F7;N # Po [6] BAMUM NJAEMLI..BAMUM QUESTION MARK -A700..A716;N # Sk [23] MODIFIER LETTER CHINESE TONE YIN PING..MODIFIER LETTER EXTRA-LOW LEFT-STEM TONE BAR -A717..A71F;N # Lm [9] MODIFIER LETTER DOT VERTICAL BAR..MODIFIER LETTER LOW INVERTED EXCLAMATION MARK -A720..A721;N # Sk [2] MODIFIER LETTER STRESS AND HIGH TONE..MODIFIER LETTER STRESS AND LOW TONE -A722..A76F;N # L& [78] LATIN CAPITAL LETTER EGYPTOLOGICAL ALEF..LATIN SMALL LETTER CON -A770;N # Lm MODIFIER LETTER US -A771..A787;N # L& [23] LATIN SMALL LETTER DUM..LATIN SMALL LETTER INSULAR T -A788;N # Lm MODIFIER LETTER LOW CIRCUMFLEX ACCENT -A789..A78A;N # Sk [2] MODIFIER LETTER COLON..MODIFIER LETTER SHORT EQUALS SIGN -A78B..A78E;N # L& [4] LATIN CAPITAL LETTER SALTILLO..LATIN SMALL LETTER L WITH RETROFLEX HOOK AND BELT -A78F;N # Lo LATIN LETTER SINOLOGICAL DOT -A790..A7CA;N # L& [59] LATIN CAPITAL LETTER N WITH DESCENDER..LATIN SMALL LETTER S WITH SHORT STROKE OVERLAY -A7D0..A7D1;N # L& [2] LATIN CAPITAL LETTER CLOSED INSULAR G..LATIN SMALL LETTER CLOSED INSULAR G -A7D3;N # Ll LATIN SMALL LETTER DOUBLE THORN -A7D5..A7D9;N # L& [5] LATIN SMALL LETTER DOUBLE WYNN..LATIN SMALL LETTER SIGMOID S -A7F2..A7F4;N # Lm [3] MODIFIER LETTER CAPITAL C..MODIFIER LETTER CAPITAL Q -A7F5..A7F6;N # L& [2] LATIN CAPITAL LETTER REVERSED HALF H..LATIN SMALL LETTER REVERSED HALF H -A7F7;N # Lo LATIN EPIGRAPHIC LETTER SIDEWAYS I -A7F8..A7F9;N # Lm [2] MODIFIER LETTER CAPITAL H WITH STROKE..MODIFIER LETTER SMALL LIGATURE OE -A7FA;N # Ll LATIN LETTER SMALL CAPITAL TURNED M -A7FB..A7FF;N # Lo [5] LATIN EPIGRAPHIC LETTER REVERSED F..LATIN EPIGRAPHIC LETTER ARCHAIC M -A800..A801;N # Lo [2] SYLOTI NAGRI LETTER A..SYLOTI NAGRI LETTER I -A802;N # Mn SYLOTI NAGRI SIGN DVISVARA -A803..A805;N # Lo [3] SYLOTI NAGRI LETTER U..SYLOTI NAGRI LETTER O -A806;N # Mn SYLOTI NAGRI SIGN HASANTA -A807..A80A;N # Lo [4] SYLOTI NAGRI LETTER KO..SYLOTI NAGRI LETTER GHO -A80B;N # Mn SYLOTI NAGRI SIGN ANUSVARA -A80C..A822;N # Lo [23] SYLOTI NAGRI LETTER CO..SYLOTI NAGRI LETTER HO -A823..A824;N # Mc [2] SYLOTI NAGRI VOWEL SIGN A..SYLOTI NAGRI VOWEL SIGN I -A825..A826;N # Mn [2] SYLOTI NAGRI VOWEL SIGN U..SYLOTI NAGRI VOWEL SIGN E -A827;N # Mc SYLOTI NAGRI VOWEL SIGN OO -A828..A82B;N # So [4] SYLOTI NAGRI POETRY MARK-1..SYLOTI NAGRI POETRY MARK-4 -A82C;N # Mn SYLOTI NAGRI SIGN ALTERNATE HASANTA -A830..A835;N # No [6] NORTH INDIC FRACTION ONE QUARTER..NORTH INDIC FRACTION THREE SIXTEENTHS -A836..A837;N # So [2] NORTH INDIC QUARTER MARK..NORTH INDIC PLACEHOLDER MARK -A838;N # Sc NORTH INDIC RUPEE MARK -A839;N # So NORTH INDIC QUANTITY MARK -A840..A873;N # Lo [52] PHAGS-PA LETTER KA..PHAGS-PA LETTER CANDRABINDU -A874..A877;N # Po [4] PHAGS-PA SINGLE HEAD MARK..PHAGS-PA MARK DOUBLE SHAD -A880..A881;N # Mc [2] SAURASHTRA SIGN ANUSVARA..SAURASHTRA SIGN VISARGA -A882..A8B3;N # Lo [50] SAURASHTRA LETTER A..SAURASHTRA LETTER LLA -A8B4..A8C3;N # Mc [16] SAURASHTRA CONSONANT SIGN HAARU..SAURASHTRA VOWEL SIGN AU -A8C4..A8C5;N # Mn [2] SAURASHTRA SIGN VIRAMA..SAURASHTRA SIGN CANDRABINDU -A8CE..A8CF;N # Po [2] SAURASHTRA DANDA..SAURASHTRA DOUBLE DANDA -A8D0..A8D9;N # Nd [10] SAURASHTRA DIGIT ZERO..SAURASHTRA DIGIT NINE -A8E0..A8F1;N # Mn [18] COMBINING DEVANAGARI DIGIT ZERO..COMBINING DEVANAGARI SIGN AVAGRAHA -A8F2..A8F7;N # Lo [6] DEVANAGARI SIGN SPACING CANDRABINDU..DEVANAGARI SIGN CANDRABINDU AVAGRAHA -A8F8..A8FA;N # Po [3] DEVANAGARI SIGN PUSHPIKA..DEVANAGARI CARET -A8FB;N # Lo DEVANAGARI HEADSTROKE -A8FC;N # Po DEVANAGARI SIGN SIDDHAM -A8FD..A8FE;N # Lo [2] DEVANAGARI JAIN OM..DEVANAGARI LETTER AY -A8FF;N # Mn DEVANAGARI VOWEL SIGN AY -A900..A909;N # Nd [10] KAYAH LI DIGIT ZERO..KAYAH LI DIGIT NINE -A90A..A925;N # Lo [28] KAYAH LI LETTER KA..KAYAH LI LETTER OO -A926..A92D;N # Mn [8] KAYAH LI VOWEL UE..KAYAH LI TONE CALYA PLOPHU -A92E..A92F;N # Po [2] KAYAH LI SIGN CWI..KAYAH LI SIGN SHYA -A930..A946;N # Lo [23] REJANG LETTER KA..REJANG LETTER A -A947..A951;N # Mn [11] REJANG VOWEL SIGN I..REJANG CONSONANT SIGN R -A952..A953;N # Mc [2] REJANG CONSONANT SIGN H..REJANG VIRAMA -A95F;N # Po REJANG SECTION MARK -A960..A97C;W # Lo [29] HANGUL CHOSEONG TIKEUT-MIEUM..HANGUL CHOSEONG SSANGYEORINHIEUH -A980..A982;N # Mn [3] JAVANESE SIGN PANYANGGA..JAVANESE SIGN LAYAR -A983;N # Mc JAVANESE SIGN WIGNYAN -A984..A9B2;N # Lo [47] JAVANESE LETTER A..JAVANESE LETTER HA -A9B3;N # Mn JAVANESE SIGN CECAK TELU -A9B4..A9B5;N # Mc [2] JAVANESE VOWEL SIGN TARUNG..JAVANESE VOWEL SIGN TOLONG -A9B6..A9B9;N # Mn [4] JAVANESE VOWEL SIGN WULU..JAVANESE VOWEL SIGN SUKU MENDUT -A9BA..A9BB;N # Mc [2] JAVANESE VOWEL SIGN TALING..JAVANESE VOWEL SIGN DIRGA MURE -A9BC..A9BD;N # Mn [2] JAVANESE VOWEL SIGN PEPET..JAVANESE CONSONANT SIGN KERET -A9BE..A9C0;N # Mc [3] JAVANESE CONSONANT SIGN PENGKAL..JAVANESE PANGKON -A9C1..A9CD;N # Po [13] JAVANESE LEFT RERENGGAN..JAVANESE TURNED PADA PISELEH -A9CF;N # Lm JAVANESE PANGRANGKEP -A9D0..A9D9;N # Nd [10] JAVANESE DIGIT ZERO..JAVANESE DIGIT NINE -A9DE..A9DF;N # Po [2] JAVANESE PADA TIRTA TUMETES..JAVANESE PADA ISEN-ISEN -A9E0..A9E4;N # Lo [5] MYANMAR LETTER SHAN GHA..MYANMAR LETTER SHAN BHA -A9E5;N # Mn MYANMAR SIGN SHAN SAW -A9E6;N # Lm MYANMAR MODIFIER LETTER SHAN REDUPLICATION -A9E7..A9EF;N # Lo [9] MYANMAR LETTER TAI LAING NYA..MYANMAR LETTER TAI LAING NNA -A9F0..A9F9;N # Nd [10] MYANMAR TAI LAING DIGIT ZERO..MYANMAR TAI LAING DIGIT NINE -A9FA..A9FE;N # Lo [5] MYANMAR LETTER TAI LAING LLA..MYANMAR LETTER TAI LAING BHA -AA00..AA28;N # Lo [41] CHAM LETTER A..CHAM LETTER HA -AA29..AA2E;N # Mn [6] CHAM VOWEL SIGN AA..CHAM VOWEL SIGN OE -AA2F..AA30;N # Mc [2] CHAM VOWEL SIGN O..CHAM VOWEL SIGN AI -AA31..AA32;N # Mn [2] CHAM VOWEL SIGN AU..CHAM VOWEL SIGN UE -AA33..AA34;N # Mc [2] CHAM CONSONANT SIGN YA..CHAM CONSONANT SIGN RA -AA35..AA36;N # Mn [2] CHAM CONSONANT SIGN LA..CHAM CONSONANT SIGN WA -AA40..AA42;N # Lo [3] CHAM LETTER FINAL K..CHAM LETTER FINAL NG -AA43;N # Mn CHAM CONSONANT SIGN FINAL NG -AA44..AA4B;N # Lo [8] CHAM LETTER FINAL CH..CHAM LETTER FINAL SS -AA4C;N # Mn CHAM CONSONANT SIGN FINAL M -AA4D;N # Mc CHAM CONSONANT SIGN FINAL H -AA50..AA59;N # Nd [10] CHAM DIGIT ZERO..CHAM DIGIT NINE -AA5C..AA5F;N # Po [4] CHAM PUNCTUATION SPIRAL..CHAM PUNCTUATION TRIPLE DANDA -AA60..AA6F;N # Lo [16] MYANMAR LETTER KHAMTI GA..MYANMAR LETTER KHAMTI FA -AA70;N # Lm MYANMAR MODIFIER LETTER KHAMTI REDUPLICATION -AA71..AA76;N # Lo [6] MYANMAR LETTER KHAMTI XA..MYANMAR LOGOGRAM KHAMTI HM -AA77..AA79;N # So [3] MYANMAR SYMBOL AITON EXCLAMATION..MYANMAR SYMBOL AITON TWO -AA7A;N # Lo MYANMAR LETTER AITON RA -AA7B;N # Mc MYANMAR SIGN PAO KAREN TONE -AA7C;N # Mn MYANMAR SIGN TAI LAING TONE-2 -AA7D;N # Mc MYANMAR SIGN TAI LAING TONE-5 -AA7E..AA7F;N # Lo [2] MYANMAR LETTER SHWE PALAUNG CHA..MYANMAR LETTER SHWE PALAUNG SHA -AA80..AAAF;N # Lo [48] TAI VIET LETTER LOW KO..TAI VIET LETTER HIGH O -AAB0;N # Mn TAI VIET MAI KANG -AAB1;N # Lo TAI VIET VOWEL AA -AAB2..AAB4;N # Mn [3] TAI VIET VOWEL I..TAI VIET VOWEL U -AAB5..AAB6;N # Lo [2] TAI VIET VOWEL E..TAI VIET VOWEL O -AAB7..AAB8;N # Mn [2] TAI VIET MAI KHIT..TAI VIET VOWEL IA -AAB9..AABD;N # Lo [5] TAI VIET VOWEL UEA..TAI VIET VOWEL AN -AABE..AABF;N # Mn [2] TAI VIET VOWEL AM..TAI VIET TONE MAI EK -AAC0;N # Lo TAI VIET TONE MAI NUENG -AAC1;N # Mn TAI VIET TONE MAI THO -AAC2;N # Lo TAI VIET TONE MAI SONG -AADB..AADC;N # Lo [2] TAI VIET SYMBOL KON..TAI VIET SYMBOL NUENG -AADD;N # Lm TAI VIET SYMBOL SAM -AADE..AADF;N # Po [2] TAI VIET SYMBOL HO HOI..TAI VIET SYMBOL KOI KOI -AAE0..AAEA;N # Lo [11] MEETEI MAYEK LETTER E..MEETEI MAYEK LETTER SSA -AAEB;N # Mc MEETEI MAYEK VOWEL SIGN II -AAEC..AAED;N # Mn [2] MEETEI MAYEK VOWEL SIGN UU..MEETEI MAYEK VOWEL SIGN AAI -AAEE..AAEF;N # Mc [2] MEETEI MAYEK VOWEL SIGN AU..MEETEI MAYEK VOWEL SIGN AAU -AAF0..AAF1;N # Po [2] MEETEI MAYEK CHEIKHAN..MEETEI MAYEK AHANG KHUDAM -AAF2;N # Lo MEETEI MAYEK ANJI -AAF3..AAF4;N # Lm [2] MEETEI MAYEK SYLLABLE REPETITION MARK..MEETEI MAYEK WORD REPETITION MARK -AAF5;N # Mc MEETEI MAYEK VOWEL SIGN VISARGA -AAF6;N # Mn MEETEI MAYEK VIRAMA -AB01..AB06;N # Lo [6] ETHIOPIC SYLLABLE TTHU..ETHIOPIC SYLLABLE TTHO -AB09..AB0E;N # Lo [6] ETHIOPIC SYLLABLE DDHU..ETHIOPIC SYLLABLE DDHO -AB11..AB16;N # Lo [6] ETHIOPIC SYLLABLE DZU..ETHIOPIC SYLLABLE DZO -AB20..AB26;N # Lo [7] ETHIOPIC SYLLABLE CCHHA..ETHIOPIC SYLLABLE CCHHO -AB28..AB2E;N # Lo [7] ETHIOPIC SYLLABLE BBA..ETHIOPIC SYLLABLE BBO -AB30..AB5A;N # Ll [43] LATIN SMALL LETTER BARRED ALPHA..LATIN SMALL LETTER Y WITH SHORT RIGHT LEG -AB5B;N # Sk MODIFIER BREVE WITH INVERTED BREVE -AB5C..AB5F;N # Lm [4] MODIFIER LETTER SMALL HENG..MODIFIER LETTER SMALL U WITH LEFT HOOK -AB60..AB68;N # Ll [9] LATIN SMALL LETTER SAKHA YAT..LATIN SMALL LETTER TURNED R WITH MIDDLE TILDE -AB69;N # Lm MODIFIER LETTER SMALL TURNED W -AB6A..AB6B;N # Sk [2] MODIFIER LETTER LEFT TACK..MODIFIER LETTER RIGHT TACK -AB70..ABBF;N # Ll [80] CHEROKEE SMALL LETTER A..CHEROKEE SMALL LETTER YA -ABC0..ABE2;N # Lo [35] MEETEI MAYEK LETTER KOK..MEETEI MAYEK LETTER I LONSUM -ABE3..ABE4;N # Mc [2] MEETEI MAYEK VOWEL SIGN ONAP..MEETEI MAYEK VOWEL SIGN INAP -ABE5;N # Mn MEETEI MAYEK VOWEL SIGN ANAP -ABE6..ABE7;N # Mc [2] MEETEI MAYEK VOWEL SIGN YENAP..MEETEI MAYEK VOWEL SIGN SOUNAP -ABE8;N # Mn MEETEI MAYEK VOWEL SIGN UNAP -ABE9..ABEA;N # Mc [2] MEETEI MAYEK VOWEL SIGN CHEINAP..MEETEI MAYEK VOWEL SIGN NUNG -ABEB;N # Po MEETEI MAYEK CHEIKHEI -ABEC;N # Mc MEETEI MAYEK LUM IYEK -ABED;N # Mn MEETEI MAYEK APUN IYEK -ABF0..ABF9;N # Nd [10] MEETEI MAYEK DIGIT ZERO..MEETEI MAYEK DIGIT NINE -AC00..D7A3;W # Lo [11172] HANGUL SYLLABLE GA..HANGUL SYLLABLE HIH -D7B0..D7C6;N # Lo [23] HANGUL JUNGSEONG O-YEO..HANGUL JUNGSEONG ARAEA-E -D7CB..D7FB;N # Lo [49] HANGUL JONGSEONG NIEUN-RIEUL..HANGUL JONGSEONG PHIEUPH-THIEUTH -D800..DB7F;N # Cs [896] .. -DB80..DBFF;N # Cs [128] .. -DC00..DFFF;N # Cs [1024] .. -E000..F8FF;A # Co [6400] .. -F900..FA6D;W # Lo [366] CJK COMPATIBILITY IDEOGRAPH-F900..CJK COMPATIBILITY IDEOGRAPH-FA6D -FA6E..FA6F;W # Cn [2] .. -FA70..FAD9;W # Lo [106] CJK COMPATIBILITY IDEOGRAPH-FA70..CJK COMPATIBILITY IDEOGRAPH-FAD9 -FADA..FAFF;W # Cn [38] .. -FB00..FB06;N # Ll [7] LATIN SMALL LIGATURE FF..LATIN SMALL LIGATURE ST -FB13..FB17;N # Ll [5] ARMENIAN SMALL LIGATURE MEN NOW..ARMENIAN SMALL LIGATURE MEN XEH -FB1D;N # Lo HEBREW LETTER YOD WITH HIRIQ -FB1E;N # Mn HEBREW POINT JUDEO-SPANISH VARIKA -FB1F..FB28;N # Lo [10] HEBREW LIGATURE YIDDISH YOD YOD PATAH..HEBREW LETTER WIDE TAV -FB29;N # Sm HEBREW LETTER ALTERNATIVE PLUS SIGN -FB2A..FB36;N # Lo [13] HEBREW LETTER SHIN WITH SHIN DOT..HEBREW LETTER ZAYIN WITH DAGESH -FB38..FB3C;N # Lo [5] HEBREW LETTER TET WITH DAGESH..HEBREW LETTER LAMED WITH DAGESH -FB3E;N # Lo HEBREW LETTER MEM WITH DAGESH -FB40..FB41;N # Lo [2] HEBREW LETTER NUN WITH DAGESH..HEBREW LETTER SAMEKH WITH DAGESH -FB43..FB44;N # Lo [2] HEBREW LETTER FINAL PE WITH DAGESH..HEBREW LETTER PE WITH DAGESH -FB46..FB4F;N # Lo [10] HEBREW LETTER TSADI WITH DAGESH..HEBREW LIGATURE ALEF LAMED -FB50..FBB1;N # Lo [98] ARABIC LETTER ALEF WASLA ISOLATED FORM..ARABIC LETTER YEH BARREE WITH HAMZA ABOVE FINAL FORM -FBB2..FBC2;N # Sk [17] ARABIC SYMBOL DOT ABOVE..ARABIC SYMBOL WASLA ABOVE -FBD3..FD3D;N # Lo [363] ARABIC LETTER NG ISOLATED FORM..ARABIC LIGATURE ALEF WITH FATHATAN ISOLATED FORM -FD3E;N # Pe ORNATE LEFT PARENTHESIS -FD3F;N # Ps ORNATE RIGHT PARENTHESIS -FD40..FD4F;N # So [16] ARABIC LIGATURE RAHIMAHU ALLAAH..ARABIC LIGATURE RAHIMAHUM ALLAAH -FD50..FD8F;N # Lo [64] ARABIC LIGATURE TEH WITH JEEM WITH MEEM INITIAL FORM..ARABIC LIGATURE MEEM WITH KHAH WITH MEEM INITIAL FORM -FD92..FDC7;N # Lo [54] ARABIC LIGATURE MEEM WITH JEEM WITH KHAH INITIAL FORM..ARABIC LIGATURE NOON WITH JEEM WITH YEH FINAL FORM -FDCF;N # So ARABIC LIGATURE SALAAMUHU ALAYNAA -FDF0..FDFB;N # Lo [12] ARABIC LIGATURE SALLA USED AS KORANIC STOP SIGN ISOLATED FORM..ARABIC LIGATURE JALLAJALALOUHOU -FDFC;N # Sc RIAL SIGN -FDFD..FDFF;N # So [3] ARABIC LIGATURE BISMILLAH AR-RAHMAN AR-RAHEEM..ARABIC LIGATURE AZZA WA JALL -FE00..FE0F;A # Mn [16] VARIATION SELECTOR-1..VARIATION SELECTOR-16 -FE10..FE16;W # Po [7] PRESENTATION FORM FOR VERTICAL COMMA..PRESENTATION FORM FOR VERTICAL QUESTION MARK -FE17;W # Ps PRESENTATION FORM FOR VERTICAL LEFT WHITE LENTICULAR BRACKET -FE18;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT WHITE LENTICULAR BRAKCET -FE19;W # Po PRESENTATION FORM FOR VERTICAL HORIZONTAL ELLIPSIS -FE20..FE2F;N # Mn [16] COMBINING LIGATURE LEFT HALF..COMBINING CYRILLIC TITLO RIGHT HALF -FE30;W # Po PRESENTATION FORM FOR VERTICAL TWO DOT LEADER -FE31..FE32;W # Pd [2] PRESENTATION FORM FOR VERTICAL EM DASH..PRESENTATION FORM FOR VERTICAL EN DASH -FE33..FE34;W # Pc [2] PRESENTATION FORM FOR VERTICAL LOW LINE..PRESENTATION FORM FOR VERTICAL WAVY LOW LINE -FE35;W # Ps PRESENTATION FORM FOR VERTICAL LEFT PARENTHESIS -FE36;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT PARENTHESIS -FE37;W # Ps PRESENTATION FORM FOR VERTICAL LEFT CURLY BRACKET -FE38;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT CURLY BRACKET -FE39;W # Ps PRESENTATION FORM FOR VERTICAL LEFT TORTOISE SHELL BRACKET -FE3A;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT TORTOISE SHELL BRACKET -FE3B;W # Ps PRESENTATION FORM FOR VERTICAL LEFT BLACK LENTICULAR BRACKET -FE3C;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT BLACK LENTICULAR BRACKET -FE3D;W # Ps PRESENTATION FORM FOR VERTICAL LEFT DOUBLE ANGLE BRACKET -FE3E;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT DOUBLE ANGLE BRACKET -FE3F;W # Ps PRESENTATION FORM FOR VERTICAL LEFT ANGLE BRACKET -FE40;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT ANGLE BRACKET -FE41;W # Ps PRESENTATION FORM FOR VERTICAL LEFT CORNER BRACKET -FE42;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT CORNER BRACKET -FE43;W # Ps PRESENTATION FORM FOR VERTICAL LEFT WHITE CORNER BRACKET -FE44;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT WHITE CORNER BRACKET -FE45..FE46;W # Po [2] SESAME DOT..WHITE SESAME DOT -FE47;W # Ps PRESENTATION FORM FOR VERTICAL LEFT SQUARE BRACKET -FE48;W # Pe PRESENTATION FORM FOR VERTICAL RIGHT SQUARE BRACKET -FE49..FE4C;W # Po [4] DASHED OVERLINE..DOUBLE WAVY OVERLINE -FE4D..FE4F;W # Pc [3] DASHED LOW LINE..WAVY LOW LINE -FE50..FE52;W # Po [3] SMALL COMMA..SMALL FULL STOP -FE54..FE57;W # Po [4] SMALL SEMICOLON..SMALL EXCLAMATION MARK -FE58;W # Pd SMALL EM DASH -FE59;W # Ps SMALL LEFT PARENTHESIS -FE5A;W # Pe SMALL RIGHT PARENTHESIS -FE5B;W # Ps SMALL LEFT CURLY BRACKET -FE5C;W # Pe SMALL RIGHT CURLY BRACKET -FE5D;W # Ps SMALL LEFT TORTOISE SHELL BRACKET -FE5E;W # Pe SMALL RIGHT TORTOISE SHELL BRACKET -FE5F..FE61;W # Po [3] SMALL NUMBER SIGN..SMALL ASTERISK -FE62;W # Sm SMALL PLUS SIGN -FE63;W # Pd SMALL HYPHEN-MINUS -FE64..FE66;W # Sm [3] SMALL LESS-THAN SIGN..SMALL EQUALS SIGN -FE68;W # Po SMALL REVERSE SOLIDUS -FE69;W # Sc SMALL DOLLAR SIGN -FE6A..FE6B;W # Po [2] SMALL PERCENT SIGN..SMALL COMMERCIAL AT -FE70..FE74;N # Lo [5] ARABIC FATHATAN ISOLATED FORM..ARABIC KASRATAN ISOLATED FORM -FE76..FEFC;N # Lo [135] ARABIC FATHA ISOLATED FORM..ARABIC LIGATURE LAM WITH ALEF FINAL FORM -FEFF;N # Cf ZERO WIDTH NO-BREAK SPACE -FF01..FF03;F # Po [3] FULLWIDTH EXCLAMATION MARK..FULLWIDTH NUMBER SIGN -FF04;F # Sc FULLWIDTH DOLLAR SIGN -FF05..FF07;F # Po [3] FULLWIDTH PERCENT SIGN..FULLWIDTH APOSTROPHE -FF08;F # Ps FULLWIDTH LEFT PARENTHESIS -FF09;F # Pe FULLWIDTH RIGHT PARENTHESIS -FF0A;F # Po FULLWIDTH ASTERISK -FF0B;F # Sm FULLWIDTH PLUS SIGN -FF0C;F # Po FULLWIDTH COMMA -FF0D;F # Pd FULLWIDTH HYPHEN-MINUS -FF0E..FF0F;F # Po [2] FULLWIDTH FULL STOP..FULLWIDTH SOLIDUS -FF10..FF19;F # Nd [10] FULLWIDTH DIGIT ZERO..FULLWIDTH DIGIT NINE -FF1A..FF1B;F # Po [2] FULLWIDTH COLON..FULLWIDTH SEMICOLON -FF1C..FF1E;F # Sm [3] FULLWIDTH LESS-THAN SIGN..FULLWIDTH GREATER-THAN SIGN -FF1F..FF20;F # Po [2] FULLWIDTH QUESTION MARK..FULLWIDTH COMMERCIAL AT -FF21..FF3A;F # Lu [26] FULLWIDTH LATIN CAPITAL LETTER A..FULLWIDTH LATIN CAPITAL LETTER Z -FF3B;F # Ps FULLWIDTH LEFT SQUARE BRACKET -FF3C;F # Po FULLWIDTH REVERSE SOLIDUS -FF3D;F # Pe FULLWIDTH RIGHT SQUARE BRACKET -FF3E;F # Sk FULLWIDTH CIRCUMFLEX ACCENT -FF3F;F # Pc FULLWIDTH LOW LINE -FF40;F # Sk FULLWIDTH GRAVE ACCENT -FF41..FF5A;F # Ll [26] FULLWIDTH LATIN SMALL LETTER A..FULLWIDTH LATIN SMALL LETTER Z -FF5B;F # Ps FULLWIDTH LEFT CURLY BRACKET -FF5C;F # Sm FULLWIDTH VERTICAL LINE -FF5D;F # Pe FULLWIDTH RIGHT CURLY BRACKET -FF5E;F # Sm FULLWIDTH TILDE -FF5F;F # Ps FULLWIDTH LEFT WHITE PARENTHESIS -FF60;F # Pe FULLWIDTH RIGHT WHITE PARENTHESIS -FF61;H # Po HALFWIDTH IDEOGRAPHIC FULL STOP -FF62;H # Ps HALFWIDTH LEFT CORNER BRACKET -FF63;H # Pe HALFWIDTH RIGHT CORNER BRACKET -FF64..FF65;H # Po [2] HALFWIDTH IDEOGRAPHIC COMMA..HALFWIDTH KATAKANA MIDDLE DOT -FF66..FF6F;H # Lo [10] HALFWIDTH KATAKANA LETTER WO..HALFWIDTH KATAKANA LETTER SMALL TU -FF70;H # Lm HALFWIDTH KATAKANA-HIRAGANA PROLONGED SOUND MARK -FF71..FF9D;H # Lo [45] HALFWIDTH KATAKANA LETTER A..HALFWIDTH KATAKANA LETTER N -FF9E..FF9F;H # Lm [2] HALFWIDTH KATAKANA VOICED SOUND MARK..HALFWIDTH KATAKANA SEMI-VOICED SOUND MARK -FFA0..FFBE;H # Lo [31] HALFWIDTH HANGUL FILLER..HALFWIDTH HANGUL LETTER HIEUH -FFC2..FFC7;H # Lo [6] HALFWIDTH HANGUL LETTER A..HALFWIDTH HANGUL LETTER E -FFCA..FFCF;H # Lo [6] HALFWIDTH HANGUL LETTER YEO..HALFWIDTH HANGUL LETTER OE -FFD2..FFD7;H # Lo [6] HALFWIDTH HANGUL LETTER YO..HALFWIDTH HANGUL LETTER YU -FFDA..FFDC;H # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGUL LETTER I -FFE0..FFE1;F # Sc [2] FULLWIDTH CENT SIGN..FULLWIDTH POUND SIGN -FFE2;F # Sm FULLWIDTH NOT SIGN -FFE3;F # Sk FULLWIDTH MACRON -FFE4;F # So FULLWIDTH BROKEN BAR -FFE5..FFE6;F # Sc [2] FULLWIDTH YEN SIGN..FULLWIDTH WON SIGN -FFE8;H # So HALFWIDTH FORMS LIGHT VERTICAL -FFE9..FFEC;H # Sm [4] HALFWIDTH LEFTWARDS ARROW..HALFWIDTH DOWNWARDS ARROW -FFED..FFEE;H # So [2] HALFWIDTH BLACK SQUARE..HALFWIDTH WHITE CIRCLE -FFF9..FFFB;N # Cf [3] INTERLINEAR ANNOTATION ANCHOR..INTERLINEAR ANNOTATION TERMINATOR -FFFC;N # So OBJECT REPLACEMENT CHARACTER -FFFD;A # So REPLACEMENT CHARACTER -10000..1000B;N # Lo [12] LINEAR B SYLLABLE B008 A..LINEAR B SYLLABLE B046 JE -1000D..10026;N # Lo [26] LINEAR B SYLLABLE B036 JO..LINEAR B SYLLABLE B032 QO -10028..1003A;N # Lo [19] LINEAR B SYLLABLE B060 RA..LINEAR B SYLLABLE B042 WO -1003C..1003D;N # Lo [2] LINEAR B SYLLABLE B017 ZA..LINEAR B SYLLABLE B074 ZE -1003F..1004D;N # Lo [15] LINEAR B SYLLABLE B020 ZO..LINEAR B SYLLABLE B091 TWO -10050..1005D;N # Lo [14] LINEAR B SYMBOL B018..LINEAR B SYMBOL B089 -10080..100FA;N # Lo [123] LINEAR B IDEOGRAM B100 MAN..LINEAR B IDEOGRAM VESSEL B305 -10100..10102;N # Po [3] AEGEAN WORD SEPARATOR LINE..AEGEAN CHECK MARK -10107..10133;N # No [45] AEGEAN NUMBER ONE..AEGEAN NUMBER NINETY THOUSAND -10137..1013F;N # So [9] AEGEAN WEIGHT BASE UNIT..AEGEAN MEASURE THIRD SUBUNIT -10140..10174;N # Nl [53] GREEK ACROPHONIC ATTIC ONE QUARTER..GREEK ACROPHONIC STRATIAN FIFTY MNAS -10175..10178;N # No [4] GREEK ONE HALF SIGN..GREEK THREE QUARTERS SIGN -10179..10189;N # So [17] GREEK YEAR SIGN..GREEK TRYBLION BASE SIGN -1018A..1018B;N # No [2] GREEK ZERO SIGN..GREEK ONE QUARTER SIGN -1018C..1018E;N # So [3] GREEK SINUSOID SIGN..NOMISMA SIGN -10190..1019C;N # So [13] ROMAN SEXTANS SIGN..ASCIA SYMBOL -101A0;N # So GREEK SYMBOL TAU RHO -101D0..101FC;N # So [45] PHAISTOS DISC SIGN PEDESTRIAN..PHAISTOS DISC SIGN WAVY BAND -101FD;N # Mn PHAISTOS DISC SIGN COMBINING OBLIQUE STROKE -10280..1029C;N # Lo [29] LYCIAN LETTER A..LYCIAN LETTER X -102A0..102D0;N # Lo [49] CARIAN LETTER A..CARIAN LETTER UUU3 -102E0;N # Mn COPTIC EPACT THOUSANDS MARK -102E1..102FB;N # No [27] COPTIC EPACT DIGIT ONE..COPTIC EPACT NUMBER NINE HUNDRED -10300..1031F;N # Lo [32] OLD ITALIC LETTER A..OLD ITALIC LETTER ESS -10320..10323;N # No [4] OLD ITALIC NUMERAL ONE..OLD ITALIC NUMERAL FIFTY -1032D..1032F;N # Lo [3] OLD ITALIC LETTER YE..OLD ITALIC LETTER SOUTHERN TSE -10330..10340;N # Lo [17] GOTHIC LETTER AHSA..GOTHIC LETTER PAIRTHRA -10341;N # Nl GOTHIC LETTER NINETY -10342..10349;N # Lo [8] GOTHIC LETTER RAIDA..GOTHIC LETTER OTHAL -1034A;N # Nl GOTHIC LETTER NINE HUNDRED -10350..10375;N # Lo [38] OLD PERMIC LETTER AN..OLD PERMIC LETTER IA -10376..1037A;N # Mn [5] COMBINING OLD PERMIC LETTER AN..COMBINING OLD PERMIC LETTER SII -10380..1039D;N # Lo [30] UGARITIC LETTER ALPA..UGARITIC LETTER SSU -1039F;N # Po UGARITIC WORD DIVIDER -103A0..103C3;N # Lo [36] OLD PERSIAN SIGN A..OLD PERSIAN SIGN HA -103C8..103CF;N # Lo [8] OLD PERSIAN SIGN AURAMAZDAA..OLD PERSIAN SIGN BUUMISH -103D0;N # Po OLD PERSIAN WORD DIVIDER -103D1..103D5;N # Nl [5] OLD PERSIAN NUMBER ONE..OLD PERSIAN NUMBER HUNDRED -10400..1044F;N # L& [80] DESERET CAPITAL LETTER LONG I..DESERET SMALL LETTER EW -10450..1047F;N # Lo [48] SHAVIAN LETTER PEEP..SHAVIAN LETTER YEW -10480..1049D;N # Lo [30] OSMANYA LETTER ALEF..OSMANYA LETTER OO -104A0..104A9;N # Nd [10] OSMANYA DIGIT ZERO..OSMANYA DIGIT NINE -104B0..104D3;N # Lu [36] OSAGE CAPITAL LETTER A..OSAGE CAPITAL LETTER ZHA -104D8..104FB;N # Ll [36] OSAGE SMALL LETTER A..OSAGE SMALL LETTER ZHA -10500..10527;N # Lo [40] ELBASAN LETTER A..ELBASAN LETTER KHE -10530..10563;N # Lo [52] CAUCASIAN ALBANIAN LETTER ALT..CAUCASIAN ALBANIAN LETTER KIW -1056F;N # Po CAUCASIAN ALBANIAN CITATION MARK -10570..1057A;N # Lu [11] VITHKUQI CAPITAL LETTER A..VITHKUQI CAPITAL LETTER GA -1057C..1058A;N # Lu [15] VITHKUQI CAPITAL LETTER HA..VITHKUQI CAPITAL LETTER RE -1058C..10592;N # Lu [7] VITHKUQI CAPITAL LETTER SE..VITHKUQI CAPITAL LETTER XE -10594..10595;N # Lu [2] VITHKUQI CAPITAL LETTER Y..VITHKUQI CAPITAL LETTER ZE -10597..105A1;N # Ll [11] VITHKUQI SMALL LETTER A..VITHKUQI SMALL LETTER GA -105A3..105B1;N # Ll [15] VITHKUQI SMALL LETTER HA..VITHKUQI SMALL LETTER RE -105B3..105B9;N # Ll [7] VITHKUQI SMALL LETTER SE..VITHKUQI SMALL LETTER XE -105BB..105BC;N # Ll [2] VITHKUQI SMALL LETTER Y..VITHKUQI SMALL LETTER ZE -10600..10736;N # Lo [311] LINEAR A SIGN AB001..LINEAR A SIGN A664 -10740..10755;N # Lo [22] LINEAR A SIGN A701 A..LINEAR A SIGN A732 JE -10760..10767;N # Lo [8] LINEAR A SIGN A800..LINEAR A SIGN A807 -10780..10785;N # Lm [6] MODIFIER LETTER SMALL CAPITAL AA..MODIFIER LETTER SMALL B WITH HOOK -10787..107B0;N # Lm [42] MODIFIER LETTER SMALL DZ DIGRAPH..MODIFIER LETTER SMALL V WITH RIGHT HOOK -107B2..107BA;N # Lm [9] MODIFIER LETTER SMALL CAPITAL Y..MODIFIER LETTER SMALL S WITH CURL -10800..10805;N # Lo [6] CYPRIOT SYLLABLE A..CYPRIOT SYLLABLE JA -10808;N # Lo CYPRIOT SYLLABLE JO -1080A..10835;N # Lo [44] CYPRIOT SYLLABLE KA..CYPRIOT SYLLABLE WO -10837..10838;N # Lo [2] CYPRIOT SYLLABLE XA..CYPRIOT SYLLABLE XE -1083C;N # Lo CYPRIOT SYLLABLE ZA -1083F;N # Lo CYPRIOT SYLLABLE ZO -10840..10855;N # Lo [22] IMPERIAL ARAMAIC LETTER ALEPH..IMPERIAL ARAMAIC LETTER TAW -10857;N # Po IMPERIAL ARAMAIC SECTION SIGN -10858..1085F;N # No [8] IMPERIAL ARAMAIC NUMBER ONE..IMPERIAL ARAMAIC NUMBER TEN THOUSAND -10860..10876;N # Lo [23] PALMYRENE LETTER ALEPH..PALMYRENE LETTER TAW -10877..10878;N # So [2] PALMYRENE LEFT-POINTING FLEURON..PALMYRENE RIGHT-POINTING FLEURON -10879..1087F;N # No [7] PALMYRENE NUMBER ONE..PALMYRENE NUMBER TWENTY -10880..1089E;N # Lo [31] NABATAEAN LETTER FINAL ALEPH..NABATAEAN LETTER TAW -108A7..108AF;N # No [9] NABATAEAN NUMBER ONE..NABATAEAN NUMBER ONE HUNDRED -108E0..108F2;N # Lo [19] HATRAN LETTER ALEPH..HATRAN LETTER QOPH -108F4..108F5;N # Lo [2] HATRAN LETTER SHIN..HATRAN LETTER TAW -108FB..108FF;N # No [5] HATRAN NUMBER ONE..HATRAN NUMBER ONE HUNDRED -10900..10915;N # Lo [22] PHOENICIAN LETTER ALF..PHOENICIAN LETTER TAU -10916..1091B;N # No [6] PHOENICIAN NUMBER ONE..PHOENICIAN NUMBER THREE -1091F;N # Po PHOENICIAN WORD SEPARATOR -10920..10939;N # Lo [26] LYDIAN LETTER A..LYDIAN LETTER C -1093F;N # Po LYDIAN TRIANGULAR MARK -10980..1099F;N # Lo [32] MEROITIC HIEROGLYPHIC LETTER A..MEROITIC HIEROGLYPHIC SYMBOL VIDJ-2 -109A0..109B7;N # Lo [24] MEROITIC CURSIVE LETTER A..MEROITIC CURSIVE LETTER DA -109BC..109BD;N # No [2] MEROITIC CURSIVE FRACTION ELEVEN TWELFTHS..MEROITIC CURSIVE FRACTION ONE HALF -109BE..109BF;N # Lo [2] MEROITIC CURSIVE LOGOGRAM RMT..MEROITIC CURSIVE LOGOGRAM IMN -109C0..109CF;N # No [16] MEROITIC CURSIVE NUMBER ONE..MEROITIC CURSIVE NUMBER SEVENTY -109D2..109FF;N # No [46] MEROITIC CURSIVE NUMBER ONE HUNDRED..MEROITIC CURSIVE FRACTION TEN TWELFTHS -10A00;N # Lo KHAROSHTHI LETTER A -10A01..10A03;N # Mn [3] KHAROSHTHI VOWEL SIGN I..KHAROSHTHI VOWEL SIGN VOCALIC R -10A05..10A06;N # Mn [2] KHAROSHTHI VOWEL SIGN E..KHAROSHTHI VOWEL SIGN O -10A0C..10A0F;N # Mn [4] KHAROSHTHI VOWEL LENGTH MARK..KHAROSHTHI SIGN VISARGA -10A10..10A13;N # Lo [4] KHAROSHTHI LETTER KA..KHAROSHTHI LETTER GHA -10A15..10A17;N # Lo [3] KHAROSHTHI LETTER CA..KHAROSHTHI LETTER JA -10A19..10A35;N # Lo [29] KHAROSHTHI LETTER NYA..KHAROSHTHI LETTER VHA -10A38..10A3A;N # Mn [3] KHAROSHTHI SIGN BAR ABOVE..KHAROSHTHI SIGN DOT BELOW -10A3F;N # Mn KHAROSHTHI VIRAMA -10A40..10A48;N # No [9] KHAROSHTHI DIGIT ONE..KHAROSHTHI FRACTION ONE HALF -10A50..10A58;N # Po [9] KHAROSHTHI PUNCTUATION DOT..KHAROSHTHI PUNCTUATION LINES -10A60..10A7C;N # Lo [29] OLD SOUTH ARABIAN LETTER HE..OLD SOUTH ARABIAN LETTER THETH -10A7D..10A7E;N # No [2] OLD SOUTH ARABIAN NUMBER ONE..OLD SOUTH ARABIAN NUMBER FIFTY -10A7F;N # Po OLD SOUTH ARABIAN NUMERIC INDICATOR -10A80..10A9C;N # Lo [29] OLD NORTH ARABIAN LETTER HEH..OLD NORTH ARABIAN LETTER ZAH -10A9D..10A9F;N # No [3] OLD NORTH ARABIAN NUMBER ONE..OLD NORTH ARABIAN NUMBER TWENTY -10AC0..10AC7;N # Lo [8] MANICHAEAN LETTER ALEPH..MANICHAEAN LETTER WAW -10AC8;N # So MANICHAEAN SIGN UD -10AC9..10AE4;N # Lo [28] MANICHAEAN LETTER ZAYIN..MANICHAEAN LETTER TAW -10AE5..10AE6;N # Mn [2] MANICHAEAN ABBREVIATION MARK ABOVE..MANICHAEAN ABBREVIATION MARK BELOW -10AEB..10AEF;N # No [5] MANICHAEAN NUMBER ONE..MANICHAEAN NUMBER ONE HUNDRED -10AF0..10AF6;N # Po [7] MANICHAEAN PUNCTUATION STAR..MANICHAEAN PUNCTUATION LINE FILLER -10B00..10B35;N # Lo [54] AVESTAN LETTER A..AVESTAN LETTER HE -10B39..10B3F;N # Po [7] AVESTAN ABBREVIATION MARK..LARGE ONE RING OVER TWO RINGS PUNCTUATION -10B40..10B55;N # Lo [22] INSCRIPTIONAL PARTHIAN LETTER ALEPH..INSCRIPTIONAL PARTHIAN LETTER TAW -10B58..10B5F;N # No [8] INSCRIPTIONAL PARTHIAN NUMBER ONE..INSCRIPTIONAL PARTHIAN NUMBER ONE THOUSAND -10B60..10B72;N # Lo [19] INSCRIPTIONAL PAHLAVI LETTER ALEPH..INSCRIPTIONAL PAHLAVI LETTER TAW -10B78..10B7F;N # No [8] INSCRIPTIONAL PAHLAVI NUMBER ONE..INSCRIPTIONAL PAHLAVI NUMBER ONE THOUSAND -10B80..10B91;N # Lo [18] PSALTER PAHLAVI LETTER ALEPH..PSALTER PAHLAVI LETTER TAW -10B99..10B9C;N # Po [4] PSALTER PAHLAVI SECTION MARK..PSALTER PAHLAVI FOUR DOTS WITH DOT -10BA9..10BAF;N # No [7] PSALTER PAHLAVI NUMBER ONE..PSALTER PAHLAVI NUMBER ONE HUNDRED -10C00..10C48;N # Lo [73] OLD TURKIC LETTER ORKHON A..OLD TURKIC LETTER ORKHON BASH -10C80..10CB2;N # Lu [51] OLD HUNGARIAN CAPITAL LETTER A..OLD HUNGARIAN CAPITAL LETTER US -10CC0..10CF2;N # Ll [51] OLD HUNGARIAN SMALL LETTER A..OLD HUNGARIAN SMALL LETTER US -10CFA..10CFF;N # No [6] OLD HUNGARIAN NUMBER ONE..OLD HUNGARIAN NUMBER ONE THOUSAND -10D00..10D23;N # Lo [36] HANIFI ROHINGYA LETTER A..HANIFI ROHINGYA MARK NA KHONNA -10D24..10D27;N # Mn [4] HANIFI ROHINGYA SIGN HARBAHAY..HANIFI ROHINGYA SIGN TASSI -10D30..10D39;N # Nd [10] HANIFI ROHINGYA DIGIT ZERO..HANIFI ROHINGYA DIGIT NINE -10E60..10E7E;N # No [31] RUMI DIGIT ONE..RUMI FRACTION TWO THIRDS -10E80..10EA9;N # Lo [42] YEZIDI LETTER ELIF..YEZIDI LETTER ET -10EAB..10EAC;N # Mn [2] YEZIDI COMBINING HAMZA MARK..YEZIDI COMBINING MADDA MARK -10EAD;N # Pd YEZIDI HYPHENATION MARK -10EB0..10EB1;N # Lo [2] YEZIDI LETTER LAM WITH DOT ABOVE..YEZIDI LETTER YOT WITH CIRCUMFLEX ABOVE -10EFD..10EFF;N # Mn [3] ARABIC SMALL LOW WORD SAKTA..ARABIC SMALL LOW WORD MADDA -10F00..10F1C;N # Lo [29] OLD SOGDIAN LETTER ALEPH..OLD SOGDIAN LETTER FINAL TAW WITH VERTICAL TAIL -10F1D..10F26;N # No [10] OLD SOGDIAN NUMBER ONE..OLD SOGDIAN FRACTION ONE HALF -10F27;N # Lo OLD SOGDIAN LIGATURE AYIN-DALETH -10F30..10F45;N # Lo [22] SOGDIAN LETTER ALEPH..SOGDIAN INDEPENDENT SHIN -10F46..10F50;N # Mn [11] SOGDIAN COMBINING DOT BELOW..SOGDIAN COMBINING STROKE BELOW -10F51..10F54;N # No [4] SOGDIAN NUMBER ONE..SOGDIAN NUMBER ONE HUNDRED -10F55..10F59;N # Po [5] SOGDIAN PUNCTUATION TWO VERTICAL BARS..SOGDIAN PUNCTUATION HALF CIRCLE WITH DOT -10F70..10F81;N # Lo [18] OLD UYGHUR LETTER ALEPH..OLD UYGHUR LETTER LESH -10F82..10F85;N # Mn [4] OLD UYGHUR COMBINING DOT ABOVE..OLD UYGHUR COMBINING TWO DOTS BELOW -10F86..10F89;N # Po [4] OLD UYGHUR PUNCTUATION BAR..OLD UYGHUR PUNCTUATION FOUR DOTS -10FB0..10FC4;N # Lo [21] CHORASMIAN LETTER ALEPH..CHORASMIAN LETTER TAW -10FC5..10FCB;N # No [7] CHORASMIAN NUMBER ONE..CHORASMIAN NUMBER ONE HUNDRED -10FE0..10FF6;N # Lo [23] ELYMAIC LETTER ALEPH..ELYMAIC LIGATURE ZAYIN-YODH -11000;N # Mc BRAHMI SIGN CANDRABINDU -11001;N # Mn BRAHMI SIGN ANUSVARA -11002;N # Mc BRAHMI SIGN VISARGA -11003..11037;N # Lo [53] BRAHMI SIGN JIHVAMULIYA..BRAHMI LETTER OLD TAMIL NNNA -11038..11046;N # Mn [15] BRAHMI VOWEL SIGN AA..BRAHMI VIRAMA -11047..1104D;N # Po [7] BRAHMI DANDA..BRAHMI PUNCTUATION LOTUS -11052..11065;N # No [20] BRAHMI NUMBER ONE..BRAHMI NUMBER ONE THOUSAND -11066..1106F;N # Nd [10] BRAHMI DIGIT ZERO..BRAHMI DIGIT NINE -11070;N # Mn BRAHMI SIGN OLD TAMIL VIRAMA -11071..11072;N # Lo [2] BRAHMI LETTER OLD TAMIL SHORT E..BRAHMI LETTER OLD TAMIL SHORT O -11073..11074;N # Mn [2] BRAHMI VOWEL SIGN OLD TAMIL SHORT E..BRAHMI VOWEL SIGN OLD TAMIL SHORT O -11075;N # Lo BRAHMI LETTER OLD TAMIL LLA -1107F;N # Mn BRAHMI NUMBER JOINER -11080..11081;N # Mn [2] KAITHI SIGN CANDRABINDU..KAITHI SIGN ANUSVARA -11082;N # Mc KAITHI SIGN VISARGA -11083..110AF;N # Lo [45] KAITHI LETTER A..KAITHI LETTER HA -110B0..110B2;N # Mc [3] KAITHI VOWEL SIGN AA..KAITHI VOWEL SIGN II -110B3..110B6;N # Mn [4] KAITHI VOWEL SIGN U..KAITHI VOWEL SIGN AI -110B7..110B8;N # Mc [2] KAITHI VOWEL SIGN O..KAITHI VOWEL SIGN AU -110B9..110BA;N # Mn [2] KAITHI SIGN VIRAMA..KAITHI SIGN NUKTA -110BB..110BC;N # Po [2] KAITHI ABBREVIATION SIGN..KAITHI ENUMERATION SIGN -110BD;N # Cf KAITHI NUMBER SIGN -110BE..110C1;N # Po [4] KAITHI SECTION MARK..KAITHI DOUBLE DANDA -110C2;N # Mn KAITHI VOWEL SIGN VOCALIC R -110CD;N # Cf KAITHI NUMBER SIGN ABOVE -110D0..110E8;N # Lo [25] SORA SOMPENG LETTER SAH..SORA SOMPENG LETTER MAE -110F0..110F9;N # Nd [10] SORA SOMPENG DIGIT ZERO..SORA SOMPENG DIGIT NINE -11100..11102;N # Mn [3] CHAKMA SIGN CANDRABINDU..CHAKMA SIGN VISARGA -11103..11126;N # Lo [36] CHAKMA LETTER AA..CHAKMA LETTER HAA -11127..1112B;N # Mn [5] CHAKMA VOWEL SIGN A..CHAKMA VOWEL SIGN UU -1112C;N # Mc CHAKMA VOWEL SIGN E -1112D..11134;N # Mn [8] CHAKMA VOWEL SIGN AI..CHAKMA MAAYYAA -11136..1113F;N # Nd [10] CHAKMA DIGIT ZERO..CHAKMA DIGIT NINE -11140..11143;N # Po [4] CHAKMA SECTION MARK..CHAKMA QUESTION MARK -11144;N # Lo CHAKMA LETTER LHAA -11145..11146;N # Mc [2] CHAKMA VOWEL SIGN AA..CHAKMA VOWEL SIGN EI -11147;N # Lo CHAKMA LETTER VAA -11150..11172;N # Lo [35] MAHAJANI LETTER A..MAHAJANI LETTER RRA -11173;N # Mn MAHAJANI SIGN NUKTA -11174..11175;N # Po [2] MAHAJANI ABBREVIATION SIGN..MAHAJANI SECTION MARK -11176;N # Lo MAHAJANI LIGATURE SHRI -11180..11181;N # Mn [2] SHARADA SIGN CANDRABINDU..SHARADA SIGN ANUSVARA -11182;N # Mc SHARADA SIGN VISARGA -11183..111B2;N # Lo [48] SHARADA LETTER A..SHARADA LETTER HA -111B3..111B5;N # Mc [3] SHARADA VOWEL SIGN AA..SHARADA VOWEL SIGN II -111B6..111BE;N # Mn [9] SHARADA VOWEL SIGN U..SHARADA VOWEL SIGN O -111BF..111C0;N # Mc [2] SHARADA VOWEL SIGN AU..SHARADA SIGN VIRAMA -111C1..111C4;N # Lo [4] SHARADA SIGN AVAGRAHA..SHARADA OM -111C5..111C8;N # Po [4] SHARADA DANDA..SHARADA SEPARATOR -111C9..111CC;N # Mn [4] SHARADA SANDHI MARK..SHARADA EXTRA SHORT VOWEL MARK -111CD;N # Po SHARADA SUTRA MARK -111CE;N # Mc SHARADA VOWEL SIGN PRISHTHAMATRA E -111CF;N # Mn SHARADA SIGN INVERTED CANDRABINDU -111D0..111D9;N # Nd [10] SHARADA DIGIT ZERO..SHARADA DIGIT NINE -111DA;N # Lo SHARADA EKAM -111DB;N # Po SHARADA SIGN SIDDHAM -111DC;N # Lo SHARADA HEADSTROKE -111DD..111DF;N # Po [3] SHARADA CONTINUATION SIGN..SHARADA SECTION MARK-2 -111E1..111F4;N # No [20] SINHALA ARCHAIC DIGIT ONE..SINHALA ARCHAIC NUMBER ONE THOUSAND -11200..11211;N # Lo [18] KHOJKI LETTER A..KHOJKI LETTER JJA -11213..1122B;N # Lo [25] KHOJKI LETTER NYA..KHOJKI LETTER LLA -1122C..1122E;N # Mc [3] KHOJKI VOWEL SIGN AA..KHOJKI VOWEL SIGN II -1122F..11231;N # Mn [3] KHOJKI VOWEL SIGN U..KHOJKI VOWEL SIGN AI -11232..11233;N # Mc [2] KHOJKI VOWEL SIGN O..KHOJKI VOWEL SIGN AU -11234;N # Mn KHOJKI SIGN ANUSVARA -11235;N # Mc KHOJKI SIGN VIRAMA -11236..11237;N # Mn [2] KHOJKI SIGN NUKTA..KHOJKI SIGN SHADDA -11238..1123D;N # Po [6] KHOJKI DANDA..KHOJKI ABBREVIATION SIGN -1123E;N # Mn KHOJKI SIGN SUKUN -1123F..11240;N # Lo [2] KHOJKI LETTER QA..KHOJKI LETTER SHORT I -11241;N # Mn KHOJKI VOWEL SIGN VOCALIC R -11280..11286;N # Lo [7] MULTANI LETTER A..MULTANI LETTER GA -11288;N # Lo MULTANI LETTER GHA -1128A..1128D;N # Lo [4] MULTANI LETTER CA..MULTANI LETTER JJA -1128F..1129D;N # Lo [15] MULTANI LETTER NYA..MULTANI LETTER BA -1129F..112A8;N # Lo [10] MULTANI LETTER BHA..MULTANI LETTER RHA -112A9;N # Po MULTANI SECTION MARK -112B0..112DE;N # Lo [47] KHUDAWADI LETTER A..KHUDAWADI LETTER HA -112DF;N # Mn KHUDAWADI SIGN ANUSVARA -112E0..112E2;N # Mc [3] KHUDAWADI VOWEL SIGN AA..KHUDAWADI VOWEL SIGN II -112E3..112EA;N # Mn [8] KHUDAWADI VOWEL SIGN U..KHUDAWADI SIGN VIRAMA -112F0..112F9;N # Nd [10] KHUDAWADI DIGIT ZERO..KHUDAWADI DIGIT NINE -11300..11301;N # Mn [2] GRANTHA SIGN COMBINING ANUSVARA ABOVE..GRANTHA SIGN CANDRABINDU -11302..11303;N # Mc [2] GRANTHA SIGN ANUSVARA..GRANTHA SIGN VISARGA -11305..1130C;N # Lo [8] GRANTHA LETTER A..GRANTHA LETTER VOCALIC L -1130F..11310;N # Lo [2] GRANTHA LETTER EE..GRANTHA LETTER AI -11313..11328;N # Lo [22] GRANTHA LETTER OO..GRANTHA LETTER NA -1132A..11330;N # Lo [7] GRANTHA LETTER PA..GRANTHA LETTER RA -11332..11333;N # Lo [2] GRANTHA LETTER LA..GRANTHA LETTER LLA -11335..11339;N # Lo [5] GRANTHA LETTER VA..GRANTHA LETTER HA -1133B..1133C;N # Mn [2] COMBINING BINDU BELOW..GRANTHA SIGN NUKTA -1133D;N # Lo GRANTHA SIGN AVAGRAHA -1133E..1133F;N # Mc [2] GRANTHA VOWEL SIGN AA..GRANTHA VOWEL SIGN I -11340;N # Mn GRANTHA VOWEL SIGN II -11341..11344;N # Mc [4] GRANTHA VOWEL SIGN U..GRANTHA VOWEL SIGN VOCALIC RR -11347..11348;N # Mc [2] GRANTHA VOWEL SIGN EE..GRANTHA VOWEL SIGN AI -1134B..1134D;N # Mc [3] GRANTHA VOWEL SIGN OO..GRANTHA SIGN VIRAMA -11350;N # Lo GRANTHA OM -11357;N # Mc GRANTHA AU LENGTH MARK -1135D..11361;N # Lo [5] GRANTHA SIGN PLUTA..GRANTHA LETTER VOCALIC LL -11362..11363;N # Mc [2] GRANTHA VOWEL SIGN VOCALIC L..GRANTHA VOWEL SIGN VOCALIC LL -11366..1136C;N # Mn [7] COMBINING GRANTHA DIGIT ZERO..COMBINING GRANTHA DIGIT SIX -11370..11374;N # Mn [5] COMBINING GRANTHA LETTER A..COMBINING GRANTHA LETTER PA -11400..11434;N # Lo [53] NEWA LETTER A..NEWA LETTER HA -11435..11437;N # Mc [3] NEWA VOWEL SIGN AA..NEWA VOWEL SIGN II -11438..1143F;N # Mn [8] NEWA VOWEL SIGN U..NEWA VOWEL SIGN AI -11440..11441;N # Mc [2] NEWA VOWEL SIGN O..NEWA VOWEL SIGN AU -11442..11444;N # Mn [3] NEWA SIGN VIRAMA..NEWA SIGN ANUSVARA -11445;N # Mc NEWA SIGN VISARGA -11446;N # Mn NEWA SIGN NUKTA -11447..1144A;N # Lo [4] NEWA SIGN AVAGRAHA..NEWA SIDDHI -1144B..1144F;N # Po [5] NEWA DANDA..NEWA ABBREVIATION SIGN -11450..11459;N # Nd [10] NEWA DIGIT ZERO..NEWA DIGIT NINE -1145A..1145B;N # Po [2] NEWA DOUBLE COMMA..NEWA PLACEHOLDER MARK -1145D;N # Po NEWA INSERTION SIGN -1145E;N # Mn NEWA SANDHI MARK -1145F..11461;N # Lo [3] NEWA LETTER VEDIC ANUSVARA..NEWA SIGN UPADHMANIYA -11480..114AF;N # Lo [48] TIRHUTA ANJI..TIRHUTA LETTER HA -114B0..114B2;N # Mc [3] TIRHUTA VOWEL SIGN AA..TIRHUTA VOWEL SIGN II -114B3..114B8;N # Mn [6] TIRHUTA VOWEL SIGN U..TIRHUTA VOWEL SIGN VOCALIC LL -114B9;N # Mc TIRHUTA VOWEL SIGN E -114BA;N # Mn TIRHUTA VOWEL SIGN SHORT E -114BB..114BE;N # Mc [4] TIRHUTA VOWEL SIGN AI..TIRHUTA VOWEL SIGN AU -114BF..114C0;N # Mn [2] TIRHUTA SIGN CANDRABINDU..TIRHUTA SIGN ANUSVARA -114C1;N # Mc TIRHUTA SIGN VISARGA -114C2..114C3;N # Mn [2] TIRHUTA SIGN VIRAMA..TIRHUTA SIGN NUKTA -114C4..114C5;N # Lo [2] TIRHUTA SIGN AVAGRAHA..TIRHUTA GVANG -114C6;N # Po TIRHUTA ABBREVIATION SIGN -114C7;N # Lo TIRHUTA OM -114D0..114D9;N # Nd [10] TIRHUTA DIGIT ZERO..TIRHUTA DIGIT NINE -11580..115AE;N # Lo [47] SIDDHAM LETTER A..SIDDHAM LETTER HA -115AF..115B1;N # Mc [3] SIDDHAM VOWEL SIGN AA..SIDDHAM VOWEL SIGN II -115B2..115B5;N # Mn [4] SIDDHAM VOWEL SIGN U..SIDDHAM VOWEL SIGN VOCALIC RR -115B8..115BB;N # Mc [4] SIDDHAM VOWEL SIGN E..SIDDHAM VOWEL SIGN AU -115BC..115BD;N # Mn [2] SIDDHAM SIGN CANDRABINDU..SIDDHAM SIGN ANUSVARA -115BE;N # Mc SIDDHAM SIGN VISARGA -115BF..115C0;N # Mn [2] SIDDHAM SIGN VIRAMA..SIDDHAM SIGN NUKTA -115C1..115D7;N # Po [23] SIDDHAM SIGN SIDDHAM..SIDDHAM SECTION MARK WITH CIRCLES AND FOUR ENCLOSURES -115D8..115DB;N # Lo [4] SIDDHAM LETTER THREE-CIRCLE ALTERNATE I..SIDDHAM LETTER ALTERNATE U -115DC..115DD;N # Mn [2] SIDDHAM VOWEL SIGN ALTERNATE U..SIDDHAM VOWEL SIGN ALTERNATE UU -11600..1162F;N # Lo [48] MODI LETTER A..MODI LETTER LLA -11630..11632;N # Mc [3] MODI VOWEL SIGN AA..MODI VOWEL SIGN II -11633..1163A;N # Mn [8] MODI VOWEL SIGN U..MODI VOWEL SIGN AI -1163B..1163C;N # Mc [2] MODI VOWEL SIGN O..MODI VOWEL SIGN AU -1163D;N # Mn MODI SIGN ANUSVARA -1163E;N # Mc MODI SIGN VISARGA -1163F..11640;N # Mn [2] MODI SIGN VIRAMA..MODI SIGN ARDHACANDRA -11641..11643;N # Po [3] MODI DANDA..MODI ABBREVIATION SIGN -11644;N # Lo MODI SIGN HUVA -11650..11659;N # Nd [10] MODI DIGIT ZERO..MODI DIGIT NINE -11660..1166C;N # Po [13] MONGOLIAN BIRGA WITH ORNAMENT..MONGOLIAN TURNED SWIRL BIRGA WITH DOUBLE ORNAMENT -11680..116AA;N # Lo [43] TAKRI LETTER A..TAKRI LETTER RRA -116AB;N # Mn TAKRI SIGN ANUSVARA -116AC;N # Mc TAKRI SIGN VISARGA -116AD;N # Mn TAKRI VOWEL SIGN AA -116AE..116AF;N # Mc [2] TAKRI VOWEL SIGN I..TAKRI VOWEL SIGN II -116B0..116B5;N # Mn [6] TAKRI VOWEL SIGN U..TAKRI VOWEL SIGN AU -116B6;N # Mc TAKRI SIGN VIRAMA -116B7;N # Mn TAKRI SIGN NUKTA -116B8;N # Lo TAKRI LETTER ARCHAIC KHA -116B9;N # Po TAKRI ABBREVIATION SIGN -116C0..116C9;N # Nd [10] TAKRI DIGIT ZERO..TAKRI DIGIT NINE -11700..1171A;N # Lo [27] AHOM LETTER KA..AHOM LETTER ALTERNATE BA -1171D..1171F;N # Mn [3] AHOM CONSONANT SIGN MEDIAL LA..AHOM CONSONANT SIGN MEDIAL LIGATING RA -11720..11721;N # Mc [2] AHOM VOWEL SIGN A..AHOM VOWEL SIGN AA -11722..11725;N # Mn [4] AHOM VOWEL SIGN I..AHOM VOWEL SIGN UU -11726;N # Mc AHOM VOWEL SIGN E -11727..1172B;N # Mn [5] AHOM VOWEL SIGN AW..AHOM SIGN KILLER -11730..11739;N # Nd [10] AHOM DIGIT ZERO..AHOM DIGIT NINE -1173A..1173B;N # No [2] AHOM NUMBER TEN..AHOM NUMBER TWENTY -1173C..1173E;N # Po [3] AHOM SIGN SMALL SECTION..AHOM SIGN RULAI -1173F;N # So AHOM SYMBOL VI -11740..11746;N # Lo [7] AHOM LETTER CA..AHOM LETTER LLA -11800..1182B;N # Lo [44] DOGRA LETTER A..DOGRA LETTER RRA -1182C..1182E;N # Mc [3] DOGRA VOWEL SIGN AA..DOGRA VOWEL SIGN II -1182F..11837;N # Mn [9] DOGRA VOWEL SIGN U..DOGRA SIGN ANUSVARA -11838;N # Mc DOGRA SIGN VISARGA -11839..1183A;N # Mn [2] DOGRA SIGN VIRAMA..DOGRA SIGN NUKTA -1183B;N # Po DOGRA ABBREVIATION SIGN -118A0..118DF;N # L& [64] WARANG CITI CAPITAL LETTER NGAA..WARANG CITI SMALL LETTER VIYO -118E0..118E9;N # Nd [10] WARANG CITI DIGIT ZERO..WARANG CITI DIGIT NINE -118EA..118F2;N # No [9] WARANG CITI NUMBER TEN..WARANG CITI NUMBER NINETY -118FF;N # Lo WARANG CITI OM -11900..11906;N # Lo [7] DIVES AKURU LETTER A..DIVES AKURU LETTER E -11909;N # Lo DIVES AKURU LETTER O -1190C..11913;N # Lo [8] DIVES AKURU LETTER KA..DIVES AKURU LETTER JA -11915..11916;N # Lo [2] DIVES AKURU LETTER NYA..DIVES AKURU LETTER TTA -11918..1192F;N # Lo [24] DIVES AKURU LETTER DDA..DIVES AKURU LETTER ZA -11930..11935;N # Mc [6] DIVES AKURU VOWEL SIGN AA..DIVES AKURU VOWEL SIGN E -11937..11938;N # Mc [2] DIVES AKURU VOWEL SIGN AI..DIVES AKURU VOWEL SIGN O -1193B..1193C;N # Mn [2] DIVES AKURU SIGN ANUSVARA..DIVES AKURU SIGN CANDRABINDU -1193D;N # Mc DIVES AKURU SIGN HALANTA -1193E;N # Mn DIVES AKURU VIRAMA -1193F;N # Lo DIVES AKURU PREFIXED NASAL SIGN -11940;N # Mc DIVES AKURU MEDIAL YA -11941;N # Lo DIVES AKURU INITIAL RA -11942;N # Mc DIVES AKURU MEDIAL RA -11943;N # Mn DIVES AKURU SIGN NUKTA -11944..11946;N # Po [3] DIVES AKURU DOUBLE DANDA..DIVES AKURU END OF TEXT MARK -11950..11959;N # Nd [10] DIVES AKURU DIGIT ZERO..DIVES AKURU DIGIT NINE -119A0..119A7;N # Lo [8] NANDINAGARI LETTER A..NANDINAGARI LETTER VOCALIC RR -119AA..119D0;N # Lo [39] NANDINAGARI LETTER E..NANDINAGARI LETTER RRA -119D1..119D3;N # Mc [3] NANDINAGARI VOWEL SIGN AA..NANDINAGARI VOWEL SIGN II -119D4..119D7;N # Mn [4] NANDINAGARI VOWEL SIGN U..NANDINAGARI VOWEL SIGN VOCALIC RR -119DA..119DB;N # Mn [2] NANDINAGARI VOWEL SIGN E..NANDINAGARI VOWEL SIGN AI -119DC..119DF;N # Mc [4] NANDINAGARI VOWEL SIGN O..NANDINAGARI SIGN VISARGA -119E0;N # Mn NANDINAGARI SIGN VIRAMA -119E1;N # Lo NANDINAGARI SIGN AVAGRAHA -119E2;N # Po NANDINAGARI SIGN SIDDHAM -119E3;N # Lo NANDINAGARI HEADSTROKE -119E4;N # Mc NANDINAGARI VOWEL SIGN PRISHTHAMATRA E -11A00;N # Lo ZANABAZAR SQUARE LETTER A -11A01..11A0A;N # Mn [10] ZANABAZAR SQUARE VOWEL SIGN I..ZANABAZAR SQUARE VOWEL LENGTH MARK -11A0B..11A32;N # Lo [40] ZANABAZAR SQUARE LETTER KA..ZANABAZAR SQUARE LETTER KSSA -11A33..11A38;N # Mn [6] ZANABAZAR SQUARE FINAL CONSONANT MARK..ZANABAZAR SQUARE SIGN ANUSVARA -11A39;N # Mc ZANABAZAR SQUARE SIGN VISARGA -11A3A;N # Lo ZANABAZAR SQUARE CLUSTER-INITIAL LETTER RA -11A3B..11A3E;N # Mn [4] ZANABAZAR SQUARE CLUSTER-FINAL LETTER YA..ZANABAZAR SQUARE CLUSTER-FINAL LETTER VA -11A3F..11A46;N # Po [8] ZANABAZAR SQUARE INITIAL HEAD MARK..ZANABAZAR SQUARE CLOSING DOUBLE-LINED HEAD MARK -11A47;N # Mn ZANABAZAR SQUARE SUBJOINER -11A50;N # Lo SOYOMBO LETTER A -11A51..11A56;N # Mn [6] SOYOMBO VOWEL SIGN I..SOYOMBO VOWEL SIGN OE -11A57..11A58;N # Mc [2] SOYOMBO VOWEL SIGN AI..SOYOMBO VOWEL SIGN AU -11A59..11A5B;N # Mn [3] SOYOMBO VOWEL SIGN VOCALIC R..SOYOMBO VOWEL LENGTH MARK -11A5C..11A89;N # Lo [46] SOYOMBO LETTER KA..SOYOMBO CLUSTER-INITIAL LETTER SA -11A8A..11A96;N # Mn [13] SOYOMBO FINAL CONSONANT SIGN G..SOYOMBO SIGN ANUSVARA -11A97;N # Mc SOYOMBO SIGN VISARGA -11A98..11A99;N # Mn [2] SOYOMBO GEMINATION MARK..SOYOMBO SUBJOINER -11A9A..11A9C;N # Po [3] SOYOMBO MARK TSHEG..SOYOMBO MARK DOUBLE SHAD -11A9D;N # Lo SOYOMBO MARK PLUTA -11A9E..11AA2;N # Po [5] SOYOMBO HEAD MARK WITH MOON AND SUN AND TRIPLE FLAME..SOYOMBO TERMINAL MARK-2 -11AB0..11ABF;N # Lo [16] CANADIAN SYLLABICS NATTILIK HI..CANADIAN SYLLABICS SPA -11AC0..11AF8;N # Lo [57] PAU CIN HAU LETTER PA..PAU CIN HAU GLOTTAL STOP FINAL -11B00..11B09;N # Po [10] DEVANAGARI HEAD MARK..DEVANAGARI SIGN MINDU -11C00..11C08;N # Lo [9] BHAIKSUKI LETTER A..BHAIKSUKI LETTER VOCALIC L -11C0A..11C2E;N # Lo [37] BHAIKSUKI LETTER E..BHAIKSUKI LETTER HA -11C2F;N # Mc BHAIKSUKI VOWEL SIGN AA -11C30..11C36;N # Mn [7] BHAIKSUKI VOWEL SIGN I..BHAIKSUKI VOWEL SIGN VOCALIC L -11C38..11C3D;N # Mn [6] BHAIKSUKI VOWEL SIGN E..BHAIKSUKI SIGN ANUSVARA -11C3E;N # Mc BHAIKSUKI SIGN VISARGA -11C3F;N # Mn BHAIKSUKI SIGN VIRAMA -11C40;N # Lo BHAIKSUKI SIGN AVAGRAHA -11C41..11C45;N # Po [5] BHAIKSUKI DANDA..BHAIKSUKI GAP FILLER-2 -11C50..11C59;N # Nd [10] BHAIKSUKI DIGIT ZERO..BHAIKSUKI DIGIT NINE -11C5A..11C6C;N # No [19] BHAIKSUKI NUMBER ONE..BHAIKSUKI HUNDREDS UNIT MARK -11C70..11C71;N # Po [2] MARCHEN HEAD MARK..MARCHEN MARK SHAD -11C72..11C8F;N # Lo [30] MARCHEN LETTER KA..MARCHEN LETTER A -11C92..11CA7;N # Mn [22] MARCHEN SUBJOINED LETTER KA..MARCHEN SUBJOINED LETTER ZA -11CA9;N # Mc MARCHEN SUBJOINED LETTER YA -11CAA..11CB0;N # Mn [7] MARCHEN SUBJOINED LETTER RA..MARCHEN VOWEL SIGN AA -11CB1;N # Mc MARCHEN VOWEL SIGN I -11CB2..11CB3;N # Mn [2] MARCHEN VOWEL SIGN U..MARCHEN VOWEL SIGN E -11CB4;N # Mc MARCHEN VOWEL SIGN O -11CB5..11CB6;N # Mn [2] MARCHEN SIGN ANUSVARA..MARCHEN SIGN CANDRABINDU -11D00..11D06;N # Lo [7] MASARAM GONDI LETTER A..MASARAM GONDI LETTER E -11D08..11D09;N # Lo [2] MASARAM GONDI LETTER AI..MASARAM GONDI LETTER O -11D0B..11D30;N # Lo [38] MASARAM GONDI LETTER AU..MASARAM GONDI LETTER TRA -11D31..11D36;N # Mn [6] MASARAM GONDI VOWEL SIGN AA..MASARAM GONDI VOWEL SIGN VOCALIC R -11D3A;N # Mn MASARAM GONDI VOWEL SIGN E -11D3C..11D3D;N # Mn [2] MASARAM GONDI VOWEL SIGN AI..MASARAM GONDI VOWEL SIGN O -11D3F..11D45;N # Mn [7] MASARAM GONDI VOWEL SIGN AU..MASARAM GONDI VIRAMA -11D46;N # Lo MASARAM GONDI REPHA -11D47;N # Mn MASARAM GONDI RA-KARA -11D50..11D59;N # Nd [10] MASARAM GONDI DIGIT ZERO..MASARAM GONDI DIGIT NINE -11D60..11D65;N # Lo [6] GUNJALA GONDI LETTER A..GUNJALA GONDI LETTER UU -11D67..11D68;N # Lo [2] GUNJALA GONDI LETTER EE..GUNJALA GONDI LETTER AI -11D6A..11D89;N # Lo [32] GUNJALA GONDI LETTER OO..GUNJALA GONDI LETTER SA -11D8A..11D8E;N # Mc [5] GUNJALA GONDI VOWEL SIGN AA..GUNJALA GONDI VOWEL SIGN UU -11D90..11D91;N # Mn [2] GUNJALA GONDI VOWEL SIGN EE..GUNJALA GONDI VOWEL SIGN AI -11D93..11D94;N # Mc [2] GUNJALA GONDI VOWEL SIGN OO..GUNJALA GONDI VOWEL SIGN AU -11D95;N # Mn GUNJALA GONDI SIGN ANUSVARA -11D96;N # Mc GUNJALA GONDI SIGN VISARGA -11D97;N # Mn GUNJALA GONDI VIRAMA -11D98;N # Lo GUNJALA GONDI OM -11DA0..11DA9;N # Nd [10] GUNJALA GONDI DIGIT ZERO..GUNJALA GONDI DIGIT NINE -11EE0..11EF2;N # Lo [19] MAKASAR LETTER KA..MAKASAR ANGKA -11EF3..11EF4;N # Mn [2] MAKASAR VOWEL SIGN I..MAKASAR VOWEL SIGN U -11EF5..11EF6;N # Mc [2] MAKASAR VOWEL SIGN E..MAKASAR VOWEL SIGN O -11EF7..11EF8;N # Po [2] MAKASAR PASSIMBANG..MAKASAR END OF SECTION -11F00..11F01;N # Mn [2] KAWI SIGN CANDRABINDU..KAWI SIGN ANUSVARA -11F02;N # Lo KAWI SIGN REPHA -11F03;N # Mc KAWI SIGN VISARGA -11F04..11F10;N # Lo [13] KAWI LETTER A..KAWI LETTER O -11F12..11F33;N # Lo [34] KAWI LETTER KA..KAWI LETTER JNYA -11F34..11F35;N # Mc [2] KAWI VOWEL SIGN AA..KAWI VOWEL SIGN ALTERNATE AA -11F36..11F3A;N # Mn [5] KAWI VOWEL SIGN I..KAWI VOWEL SIGN VOCALIC R -11F3E..11F3F;N # Mc [2] KAWI VOWEL SIGN E..KAWI VOWEL SIGN AI -11F40;N # Mn KAWI VOWEL SIGN EU -11F41;N # Mc KAWI SIGN KILLER -11F42;N # Mn KAWI CONJOINER -11F43..11F4F;N # Po [13] KAWI DANDA..KAWI PUNCTUATION CLOSING SPIRAL -11F50..11F59;N # Nd [10] KAWI DIGIT ZERO..KAWI DIGIT NINE -11FB0;N # Lo LISU LETTER YHA -11FC0..11FD4;N # No [21] TAMIL FRACTION ONE THREE-HUNDRED-AND-TWENTIETH..TAMIL FRACTION DOWNSCALING FACTOR KIIZH -11FD5..11FDC;N # So [8] TAMIL SIGN NEL..TAMIL SIGN MUKKURUNI -11FDD..11FE0;N # Sc [4] TAMIL SIGN KAACU..TAMIL SIGN VARAAKAN -11FE1..11FF1;N # So [17] TAMIL SIGN PAARAM..TAMIL SIGN VAKAIYARAA -11FFF;N # Po TAMIL PUNCTUATION END OF TEXT -12000..12399;N # Lo [922] CUNEIFORM SIGN A..CUNEIFORM SIGN U U -12400..1246E;N # Nl [111] CUNEIFORM NUMERIC SIGN TWO ASH..CUNEIFORM NUMERIC SIGN NINE U VARIANT FORM -12470..12474;N # Po [5] CUNEIFORM PUNCTUATION SIGN OLD ASSYRIAN WORD DIVIDER..CUNEIFORM PUNCTUATION SIGN DIAGONAL QUADCOLON -12480..12543;N # Lo [196] CUNEIFORM SIGN AB TIMES NUN TENU..CUNEIFORM SIGN ZU5 TIMES THREE DISH TENU -12F90..12FF0;N # Lo [97] CYPRO-MINOAN SIGN CM001..CYPRO-MINOAN SIGN CM114 -12FF1..12FF2;N # Po [2] CYPRO-MINOAN SIGN CM301..CYPRO-MINOAN SIGN CM302 -13000..1342F;N # Lo [1072] EGYPTIAN HIEROGLYPH A001..EGYPTIAN HIEROGLYPH V011D -13430..1343F;N # Cf [16] EGYPTIAN HIEROGLYPH VERTICAL JOINER..EGYPTIAN HIEROGLYPH END WALLED ENCLOSURE -13440;N # Mn EGYPTIAN HIEROGLYPH MIRROR HORIZONTALLY -13441..13446;N # Lo [6] EGYPTIAN HIEROGLYPH FULL BLANK..EGYPTIAN HIEROGLYPH WIDE LOST SIGN -13447..13455;N # Mn [15] EGYPTIAN HIEROGLYPH MODIFIER DAMAGED AT TOP START..EGYPTIAN HIEROGLYPH MODIFIER DAMAGED -14400..14646;N # Lo [583] ANATOLIAN HIEROGLYPH A001..ANATOLIAN HIEROGLYPH A530 -16800..16A38;N # Lo [569] BAMUM LETTER PHASE-A NGKUE MFON..BAMUM LETTER PHASE-F VUEQ -16A40..16A5E;N # Lo [31] MRO LETTER TA..MRO LETTER TEK -16A60..16A69;N # Nd [10] MRO DIGIT ZERO..MRO DIGIT NINE -16A6E..16A6F;N # Po [2] MRO DANDA..MRO DOUBLE DANDA -16A70..16ABE;N # Lo [79] TANGSA LETTER OZ..TANGSA LETTER ZA -16AC0..16AC9;N # Nd [10] TANGSA DIGIT ZERO..TANGSA DIGIT NINE -16AD0..16AED;N # Lo [30] BASSA VAH LETTER ENNI..BASSA VAH LETTER I -16AF0..16AF4;N # Mn [5] BASSA VAH COMBINING HIGH TONE..BASSA VAH COMBINING HIGH-LOW TONE -16AF5;N # Po BASSA VAH FULL STOP -16B00..16B2F;N # Lo [48] PAHAWH HMONG VOWEL KEEB..PAHAWH HMONG CONSONANT CAU -16B30..16B36;N # Mn [7] PAHAWH HMONG MARK CIM TUB..PAHAWH HMONG MARK CIM TAUM -16B37..16B3B;N # Po [5] PAHAWH HMONG SIGN VOS THOM..PAHAWH HMONG SIGN VOS FEEM -16B3C..16B3F;N # So [4] PAHAWH HMONG SIGN XYEEM NTXIV..PAHAWH HMONG SIGN XYEEM FAIB -16B40..16B43;N # Lm [4] PAHAWH HMONG SIGN VOS SEEV..PAHAWH HMONG SIGN IB YAM -16B44;N # Po PAHAWH HMONG SIGN XAUS -16B45;N # So PAHAWH HMONG SIGN CIM TSOV ROG -16B50..16B59;N # Nd [10] PAHAWH HMONG DIGIT ZERO..PAHAWH HMONG DIGIT NINE -16B5B..16B61;N # No [7] PAHAWH HMONG NUMBER TENS..PAHAWH HMONG NUMBER TRILLIONS -16B63..16B77;N # Lo [21] PAHAWH HMONG SIGN VOS LUB..PAHAWH HMONG SIGN CIM NRES TOS -16B7D..16B8F;N # Lo [19] PAHAWH HMONG CLAN SIGN TSHEEJ..PAHAWH HMONG CLAN SIGN VWJ -16E40..16E7F;N # L& [64] MEDEFAIDRIN CAPITAL LETTER M..MEDEFAIDRIN SMALL LETTER Y -16E80..16E96;N # No [23] MEDEFAIDRIN DIGIT ZERO..MEDEFAIDRIN DIGIT THREE ALTERNATE FORM -16E97..16E9A;N # Po [4] MEDEFAIDRIN COMMA..MEDEFAIDRIN EXCLAMATION OH -16F00..16F4A;N # Lo [75] MIAO LETTER PA..MIAO LETTER RTE -16F4F;N # Mn MIAO SIGN CONSONANT MODIFIER BAR -16F50;N # Lo MIAO LETTER NASALIZATION -16F51..16F87;N # Mc [55] MIAO SIGN ASPIRATION..MIAO VOWEL SIGN UI -16F8F..16F92;N # Mn [4] MIAO TONE RIGHT..MIAO TONE BELOW -16F93..16F9F;N # Lm [13] MIAO LETTER TONE-2..MIAO LETTER REFORMED TONE-8 -16FE0..16FE1;W # Lm [2] TANGUT ITERATION MARK..NUSHU ITERATION MARK -16FE2;W # Po OLD CHINESE HOOK MARK -16FE3;W # Lm OLD CHINESE ITERATION MARK -16FE4;W # Mn KHITAN SMALL SCRIPT FILLER -16FF0..16FF1;W # Mc [2] VIETNAMESE ALTERNATE READING MARK CA..VIETNAMESE ALTERNATE READING MARK NHAY -17000..187F7;W # Lo [6136] TANGUT IDEOGRAPH-17000..TANGUT IDEOGRAPH-187F7 -18800..18AFF;W # Lo [768] TANGUT COMPONENT-001..TANGUT COMPONENT-768 -18B00..18CD5;W # Lo [470] KHITAN SMALL SCRIPT CHARACTER-18B00..KHITAN SMALL SCRIPT CHARACTER-18CD5 -18D00..18D08;W # Lo [9] TANGUT IDEOGRAPH-18D00..TANGUT IDEOGRAPH-18D08 -1AFF0..1AFF3;W # Lm [4] KATAKANA LETTER MINNAN TONE-2..KATAKANA LETTER MINNAN TONE-5 -1AFF5..1AFFB;W # Lm [7] KATAKANA LETTER MINNAN TONE-7..KATAKANA LETTER MINNAN NASALIZED TONE-5 -1AFFD..1AFFE;W # Lm [2] KATAKANA LETTER MINNAN NASALIZED TONE-7..KATAKANA LETTER MINNAN NASALIZED TONE-8 -1B000..1B0FF;W # Lo [256] KATAKANA LETTER ARCHAIC E..HENTAIGANA LETTER RE-2 -1B100..1B122;W # Lo [35] HENTAIGANA LETTER RE-3..KATAKANA LETTER ARCHAIC WU -1B132;W # Lo HIRAGANA LETTER SMALL KO -1B150..1B152;W # Lo [3] HIRAGANA LETTER SMALL WI..HIRAGANA LETTER SMALL WO -1B155;W # Lo KATAKANA LETTER SMALL KO -1B164..1B167;W # Lo [4] KATAKANA LETTER SMALL WI..KATAKANA LETTER SMALL N -1B170..1B2FB;W # Lo [396] NUSHU CHARACTER-1B170..NUSHU CHARACTER-1B2FB -1BC00..1BC6A;N # Lo [107] DUPLOYAN LETTER H..DUPLOYAN LETTER VOCALIC M -1BC70..1BC7C;N # Lo [13] DUPLOYAN AFFIX LEFT HORIZONTAL SECANT..DUPLOYAN AFFIX ATTACHED TANGENT HOOK -1BC80..1BC88;N # Lo [9] DUPLOYAN AFFIX HIGH ACUTE..DUPLOYAN AFFIX HIGH VERTICAL -1BC90..1BC99;N # Lo [10] DUPLOYAN AFFIX LOW ACUTE..DUPLOYAN AFFIX LOW ARROW -1BC9C;N # So DUPLOYAN SIGN O WITH CROSS -1BC9D..1BC9E;N # Mn [2] DUPLOYAN THICK LETTER SELECTOR..DUPLOYAN DOUBLE MARK -1BC9F;N # Po DUPLOYAN PUNCTUATION CHINOOK FULL STOP -1BCA0..1BCA3;N # Cf [4] SHORTHAND FORMAT LETTER OVERLAP..SHORTHAND FORMAT UP STEP -1CF00..1CF2D;N # Mn [46] ZNAMENNY COMBINING MARK GORAZDO NIZKO S KRYZHEM ON LEFT..ZNAMENNY COMBINING MARK KRYZH ON LEFT -1CF30..1CF46;N # Mn [23] ZNAMENNY COMBINING TONAL RANGE MARK MRACHNO..ZNAMENNY PRIZNAK MODIFIER ROG -1CF50..1CFC3;N # So [116] ZNAMENNY NEUME KRYUK..ZNAMENNY NEUME PAUK -1D000..1D0F5;N # So [246] BYZANTINE MUSICAL SYMBOL PSILI..BYZANTINE MUSICAL SYMBOL GORGON NEO KATO -1D100..1D126;N # So [39] MUSICAL SYMBOL SINGLE BARLINE..MUSICAL SYMBOL DRUM CLEF-2 -1D129..1D164;N # So [60] MUSICAL SYMBOL MULTIPLE MEASURE REST..MUSICAL SYMBOL ONE HUNDRED TWENTY-EIGHTH NOTE -1D165..1D166;N # Mc [2] MUSICAL SYMBOL COMBINING STEM..MUSICAL SYMBOL COMBINING SPRECHGESANG STEM -1D167..1D169;N # Mn [3] MUSICAL SYMBOL COMBINING TREMOLO-1..MUSICAL SYMBOL COMBINING TREMOLO-3 -1D16A..1D16C;N # So [3] MUSICAL SYMBOL FINGERED TREMOLO-1..MUSICAL SYMBOL FINGERED TREMOLO-3 -1D16D..1D172;N # Mc [6] MUSICAL SYMBOL COMBINING AUGMENTATION DOT..MUSICAL SYMBOL COMBINING FLAG-5 -1D173..1D17A;N # Cf [8] MUSICAL SYMBOL BEGIN BEAM..MUSICAL SYMBOL END PHRASE -1D17B..1D182;N # Mn [8] MUSICAL SYMBOL COMBINING ACCENT..MUSICAL SYMBOL COMBINING LOURE -1D183..1D184;N # So [2] MUSICAL SYMBOL ARPEGGIATO UP..MUSICAL SYMBOL ARPEGGIATO DOWN -1D185..1D18B;N # Mn [7] MUSICAL SYMBOL COMBINING DOIT..MUSICAL SYMBOL COMBINING TRIPLE TONGUE -1D18C..1D1A9;N # So [30] MUSICAL SYMBOL RINFORZANDO..MUSICAL SYMBOL DEGREE SLASH -1D1AA..1D1AD;N # Mn [4] MUSICAL SYMBOL COMBINING DOWN BOW..MUSICAL SYMBOL COMBINING SNAP PIZZICATO -1D1AE..1D1EA;N # So [61] MUSICAL SYMBOL PEDAL MARK..MUSICAL SYMBOL KORON -1D200..1D241;N # So [66] GREEK VOCAL NOTATION SYMBOL-1..GREEK INSTRUMENTAL NOTATION SYMBOL-54 -1D242..1D244;N # Mn [3] COMBINING GREEK MUSICAL TRISEME..COMBINING GREEK MUSICAL PENTASEME -1D245;N # So GREEK MUSICAL LEIMMA -1D2C0..1D2D3;N # No [20] KAKTOVIK NUMERAL ZERO..KAKTOVIK NUMERAL NINETEEN -1D2E0..1D2F3;N # No [20] MAYAN NUMERAL ZERO..MAYAN NUMERAL NINETEEN -1D300..1D356;N # So [87] MONOGRAM FOR EARTH..TETRAGRAM FOR FOSTERING -1D360..1D378;N # No [25] COUNTING ROD UNIT DIGIT ONE..TALLY MARK FIVE -1D400..1D454;N # L& [85] MATHEMATICAL BOLD CAPITAL A..MATHEMATICAL ITALIC SMALL G -1D456..1D49C;N # L& [71] MATHEMATICAL ITALIC SMALL I..MATHEMATICAL SCRIPT CAPITAL A -1D49E..1D49F;N # Lu [2] MATHEMATICAL SCRIPT CAPITAL C..MATHEMATICAL SCRIPT CAPITAL D -1D4A2;N # Lu MATHEMATICAL SCRIPT CAPITAL G -1D4A5..1D4A6;N # Lu [2] MATHEMATICAL SCRIPT CAPITAL J..MATHEMATICAL SCRIPT CAPITAL K -1D4A9..1D4AC;N # Lu [4] MATHEMATICAL SCRIPT CAPITAL N..MATHEMATICAL SCRIPT CAPITAL Q -1D4AE..1D4B9;N # L& [12] MATHEMATICAL SCRIPT CAPITAL S..MATHEMATICAL SCRIPT SMALL D -1D4BB;N # Ll MATHEMATICAL SCRIPT SMALL F -1D4BD..1D4C3;N # Ll [7] MATHEMATICAL SCRIPT SMALL H..MATHEMATICAL SCRIPT SMALL N -1D4C5..1D505;N # L& [65] MATHEMATICAL SCRIPT SMALL P..MATHEMATICAL FRAKTUR CAPITAL B -1D507..1D50A;N # Lu [4] MATHEMATICAL FRAKTUR CAPITAL D..MATHEMATICAL FRAKTUR CAPITAL G -1D50D..1D514;N # Lu [8] MATHEMATICAL FRAKTUR CAPITAL J..MATHEMATICAL FRAKTUR CAPITAL Q -1D516..1D51C;N # Lu [7] MATHEMATICAL FRAKTUR CAPITAL S..MATHEMATICAL FRAKTUR CAPITAL Y -1D51E..1D539;N # L& [28] MATHEMATICAL FRAKTUR SMALL A..MATHEMATICAL DOUBLE-STRUCK CAPITAL B -1D53B..1D53E;N # Lu [4] MATHEMATICAL DOUBLE-STRUCK CAPITAL D..MATHEMATICAL DOUBLE-STRUCK CAPITAL G -1D540..1D544;N # Lu [5] MATHEMATICAL DOUBLE-STRUCK CAPITAL I..MATHEMATICAL DOUBLE-STRUCK CAPITAL M -1D546;N # Lu MATHEMATICAL DOUBLE-STRUCK CAPITAL O -1D54A..1D550;N # Lu [7] MATHEMATICAL DOUBLE-STRUCK CAPITAL S..MATHEMATICAL DOUBLE-STRUCK CAPITAL Y -1D552..1D6A5;N # L& [340] MATHEMATICAL DOUBLE-STRUCK SMALL A..MATHEMATICAL ITALIC SMALL DOTLESS J -1D6A8..1D6C0;N # Lu [25] MATHEMATICAL BOLD CAPITAL ALPHA..MATHEMATICAL BOLD CAPITAL OMEGA -1D6C1;N # Sm MATHEMATICAL BOLD NABLA -1D6C2..1D6DA;N # Ll [25] MATHEMATICAL BOLD SMALL ALPHA..MATHEMATICAL BOLD SMALL OMEGA -1D6DB;N # Sm MATHEMATICAL BOLD PARTIAL DIFFERENTIAL -1D6DC..1D6FA;N # L& [31] MATHEMATICAL BOLD EPSILON SYMBOL..MATHEMATICAL ITALIC CAPITAL OMEGA -1D6FB;N # Sm MATHEMATICAL ITALIC NABLA -1D6FC..1D714;N # Ll [25] MATHEMATICAL ITALIC SMALL ALPHA..MATHEMATICAL ITALIC SMALL OMEGA -1D715;N # Sm MATHEMATICAL ITALIC PARTIAL DIFFERENTIAL -1D716..1D734;N # L& [31] MATHEMATICAL ITALIC EPSILON SYMBOL..MATHEMATICAL BOLD ITALIC CAPITAL OMEGA -1D735;N # Sm MATHEMATICAL BOLD ITALIC NABLA -1D736..1D74E;N # Ll [25] MATHEMATICAL BOLD ITALIC SMALL ALPHA..MATHEMATICAL BOLD ITALIC SMALL OMEGA -1D74F;N # Sm MATHEMATICAL BOLD ITALIC PARTIAL DIFFERENTIAL -1D750..1D76E;N # L& [31] MATHEMATICAL BOLD ITALIC EPSILON SYMBOL..MATHEMATICAL SANS-SERIF BOLD CAPITAL OMEGA -1D76F;N # Sm MATHEMATICAL SANS-SERIF BOLD NABLA -1D770..1D788;N # Ll [25] MATHEMATICAL SANS-SERIF BOLD SMALL ALPHA..MATHEMATICAL SANS-SERIF BOLD SMALL OMEGA -1D789;N # Sm MATHEMATICAL SANS-SERIF BOLD PARTIAL DIFFERENTIAL -1D78A..1D7A8;N # L& [31] MATHEMATICAL SANS-SERIF BOLD EPSILON SYMBOL..MATHEMATICAL SANS-SERIF BOLD ITALIC CAPITAL OMEGA -1D7A9;N # Sm MATHEMATICAL SANS-SERIF BOLD ITALIC NABLA -1D7AA..1D7C2;N # Ll [25] MATHEMATICAL SANS-SERIF BOLD ITALIC SMALL ALPHA..MATHEMATICAL SANS-SERIF BOLD ITALIC SMALL OMEGA -1D7C3;N # Sm MATHEMATICAL SANS-SERIF BOLD ITALIC PARTIAL DIFFERENTIAL -1D7C4..1D7CB;N # L& [8] MATHEMATICAL SANS-SERIF BOLD ITALIC EPSILON SYMBOL..MATHEMATICAL BOLD SMALL DIGAMMA -1D7CE..1D7FF;N # Nd [50] MATHEMATICAL BOLD DIGIT ZERO..MATHEMATICAL MONOSPACE DIGIT NINE -1D800..1D9FF;N # So [512] SIGNWRITING HAND-FIST INDEX..SIGNWRITING HEAD -1DA00..1DA36;N # Mn [55] SIGNWRITING HEAD RIM..SIGNWRITING AIR SUCKING IN -1DA37..1DA3A;N # So [4] SIGNWRITING AIR BLOW SMALL ROTATIONS..SIGNWRITING BREATH EXHALE -1DA3B..1DA6C;N # Mn [50] SIGNWRITING MOUTH CLOSED NEUTRAL..SIGNWRITING EXCITEMENT -1DA6D..1DA74;N # So [8] SIGNWRITING SHOULDER HIP SPINE..SIGNWRITING TORSO-FLOORPLANE TWISTING -1DA75;N # Mn SIGNWRITING UPPER BODY TILTING FROM HIP JOINTS -1DA76..1DA83;N # So [14] SIGNWRITING LIMB COMBINATION..SIGNWRITING LOCATION DEPTH -1DA84;N # Mn SIGNWRITING LOCATION HEAD NECK -1DA85..1DA86;N # So [2] SIGNWRITING LOCATION TORSO..SIGNWRITING LOCATION LIMBS DIGITS -1DA87..1DA8B;N # Po [5] SIGNWRITING COMMA..SIGNWRITING PARENTHESIS -1DA9B..1DA9F;N # Mn [5] SIGNWRITING FILL MODIFIER-2..SIGNWRITING FILL MODIFIER-6 -1DAA1..1DAAF;N # Mn [15] SIGNWRITING ROTATION MODIFIER-2..SIGNWRITING ROTATION MODIFIER-16 -1DF00..1DF09;N # Ll [10] LATIN SMALL LETTER FENG DIGRAPH WITH TRILL..LATIN SMALL LETTER T WITH HOOK AND RETROFLEX HOOK -1DF0A;N # Lo LATIN LETTER RETROFLEX CLICK WITH RETROFLEX HOOK -1DF0B..1DF1E;N # Ll [20] LATIN SMALL LETTER ESH WITH DOUBLE BAR..LATIN SMALL LETTER S WITH CURL -1DF25..1DF2A;N # Ll [6] LATIN SMALL LETTER D WITH MID-HEIGHT LEFT HOOK..LATIN SMALL LETTER T WITH MID-HEIGHT LEFT HOOK -1E000..1E006;N # Mn [7] COMBINING GLAGOLITIC LETTER AZU..COMBINING GLAGOLITIC LETTER ZHIVETE -1E008..1E018;N # Mn [17] COMBINING GLAGOLITIC LETTER ZEMLJA..COMBINING GLAGOLITIC LETTER HERU -1E01B..1E021;N # Mn [7] COMBINING GLAGOLITIC LETTER SHTA..COMBINING GLAGOLITIC LETTER YATI -1E023..1E024;N # Mn [2] COMBINING GLAGOLITIC LETTER YU..COMBINING GLAGOLITIC LETTER SMALL YUS -1E026..1E02A;N # Mn [5] COMBINING GLAGOLITIC LETTER YO..COMBINING GLAGOLITIC LETTER FITA -1E030..1E06D;N # Lm [62] MODIFIER LETTER CYRILLIC SMALL A..MODIFIER LETTER CYRILLIC SMALL STRAIGHT U WITH STROKE -1E08F;N # Mn COMBINING CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I -1E100..1E12C;N # Lo [45] NYIAKENG PUACHUE HMONG LETTER MA..NYIAKENG PUACHUE HMONG LETTER W -1E130..1E136;N # Mn [7] NYIAKENG PUACHUE HMONG TONE-B..NYIAKENG PUACHUE HMONG TONE-D -1E137..1E13D;N # Lm [7] NYIAKENG PUACHUE HMONG SIGN FOR PERSON..NYIAKENG PUACHUE HMONG SYLLABLE LENGTHENER -1E140..1E149;N # Nd [10] NYIAKENG PUACHUE HMONG DIGIT ZERO..NYIAKENG PUACHUE HMONG DIGIT NINE -1E14E;N # Lo NYIAKENG PUACHUE HMONG LOGOGRAM NYAJ -1E14F;N # So NYIAKENG PUACHUE HMONG CIRCLED CA -1E290..1E2AD;N # Lo [30] TOTO LETTER PA..TOTO LETTER A -1E2AE;N # Mn TOTO SIGN RISING TONE -1E2C0..1E2EB;N # Lo [44] WANCHO LETTER AA..WANCHO LETTER YIH -1E2EC..1E2EF;N # Mn [4] WANCHO TONE TUP..WANCHO TONE KOINI -1E2F0..1E2F9;N # Nd [10] WANCHO DIGIT ZERO..WANCHO DIGIT NINE -1E2FF;N # Sc WANCHO NGUN SIGN -1E4D0..1E4EA;N # Lo [27] NAG MUNDARI LETTER O..NAG MUNDARI LETTER ELL -1E4EB;N # Lm NAG MUNDARI SIGN OJOD -1E4EC..1E4EF;N # Mn [4] NAG MUNDARI SIGN MUHOR..NAG MUNDARI SIGN SUTUH -1E4F0..1E4F9;N # Nd [10] NAG MUNDARI DIGIT ZERO..NAG MUNDARI DIGIT NINE -1E7E0..1E7E6;N # Lo [7] ETHIOPIC SYLLABLE HHYA..ETHIOPIC SYLLABLE HHYO -1E7E8..1E7EB;N # Lo [4] ETHIOPIC SYLLABLE GURAGE HHWA..ETHIOPIC SYLLABLE HHWE -1E7ED..1E7EE;N # Lo [2] ETHIOPIC SYLLABLE GURAGE MWI..ETHIOPIC SYLLABLE GURAGE MWEE -1E7F0..1E7FE;N # Lo [15] ETHIOPIC SYLLABLE GURAGE QWI..ETHIOPIC SYLLABLE GURAGE PWEE -1E800..1E8C4;N # Lo [197] MENDE KIKAKUI SYLLABLE M001 KI..MENDE KIKAKUI SYLLABLE M060 NYON -1E8C7..1E8CF;N # No [9] MENDE KIKAKUI DIGIT ONE..MENDE KIKAKUI DIGIT NINE -1E8D0..1E8D6;N # Mn [7] MENDE KIKAKUI COMBINING NUMBER TEENS..MENDE KIKAKUI COMBINING NUMBER MILLIONS -1E900..1E943;N # L& [68] ADLAM CAPITAL LETTER ALIF..ADLAM SMALL LETTER SHA -1E944..1E94A;N # Mn [7] ADLAM ALIF LENGTHENER..ADLAM NUKTA -1E94B;N # Lm ADLAM NASALIZATION MARK -1E950..1E959;N # Nd [10] ADLAM DIGIT ZERO..ADLAM DIGIT NINE -1E95E..1E95F;N # Po [2] ADLAM INITIAL EXCLAMATION MARK..ADLAM INITIAL QUESTION MARK -1EC71..1ECAB;N # No [59] INDIC SIYAQ NUMBER ONE..INDIC SIYAQ NUMBER PREFIXED NINE -1ECAC;N # So INDIC SIYAQ PLACEHOLDER -1ECAD..1ECAF;N # No [3] INDIC SIYAQ FRACTION ONE QUARTER..INDIC SIYAQ FRACTION THREE QUARTERS -1ECB0;N # Sc INDIC SIYAQ RUPEE MARK -1ECB1..1ECB4;N # No [4] INDIC SIYAQ NUMBER ALTERNATE ONE..INDIC SIYAQ ALTERNATE LAKH MARK -1ED01..1ED2D;N # No [45] OTTOMAN SIYAQ NUMBER ONE..OTTOMAN SIYAQ NUMBER NINETY THOUSAND -1ED2E;N # So OTTOMAN SIYAQ MARRATAN -1ED2F..1ED3D;N # No [15] OTTOMAN SIYAQ ALTERNATE NUMBER TWO..OTTOMAN SIYAQ FRACTION ONE SIXTH -1EE00..1EE03;N # Lo [4] ARABIC MATHEMATICAL ALEF..ARABIC MATHEMATICAL DAL -1EE05..1EE1F;N # Lo [27] ARABIC MATHEMATICAL WAW..ARABIC MATHEMATICAL DOTLESS QAF -1EE21..1EE22;N # Lo [2] ARABIC MATHEMATICAL INITIAL BEH..ARABIC MATHEMATICAL INITIAL JEEM -1EE24;N # Lo ARABIC MATHEMATICAL INITIAL HEH -1EE27;N # Lo ARABIC MATHEMATICAL INITIAL HAH -1EE29..1EE32;N # Lo [10] ARABIC MATHEMATICAL INITIAL YEH..ARABIC MATHEMATICAL INITIAL QAF -1EE34..1EE37;N # Lo [4] ARABIC MATHEMATICAL INITIAL SHEEN..ARABIC MATHEMATICAL INITIAL KHAH -1EE39;N # Lo ARABIC MATHEMATICAL INITIAL DAD -1EE3B;N # Lo ARABIC MATHEMATICAL INITIAL GHAIN -1EE42;N # Lo ARABIC MATHEMATICAL TAILED JEEM -1EE47;N # Lo ARABIC MATHEMATICAL TAILED HAH -1EE49;N # Lo ARABIC MATHEMATICAL TAILED YEH -1EE4B;N # Lo ARABIC MATHEMATICAL TAILED LAM -1EE4D..1EE4F;N # Lo [3] ARABIC MATHEMATICAL TAILED NOON..ARABIC MATHEMATICAL TAILED AIN -1EE51..1EE52;N # Lo [2] ARABIC MATHEMATICAL TAILED SAD..ARABIC MATHEMATICAL TAILED QAF -1EE54;N # Lo ARABIC MATHEMATICAL TAILED SHEEN -1EE57;N # Lo ARABIC MATHEMATICAL TAILED KHAH -1EE59;N # Lo ARABIC MATHEMATICAL TAILED DAD -1EE5B;N # Lo ARABIC MATHEMATICAL TAILED GHAIN -1EE5D;N # Lo ARABIC MATHEMATICAL TAILED DOTLESS NOON -1EE5F;N # Lo ARABIC MATHEMATICAL TAILED DOTLESS QAF -1EE61..1EE62;N # Lo [2] ARABIC MATHEMATICAL STRETCHED BEH..ARABIC MATHEMATICAL STRETCHED JEEM -1EE64;N # Lo ARABIC MATHEMATICAL STRETCHED HEH -1EE67..1EE6A;N # Lo [4] ARABIC MATHEMATICAL STRETCHED HAH..ARABIC MATHEMATICAL STRETCHED KAF -1EE6C..1EE72;N # Lo [7] ARABIC MATHEMATICAL STRETCHED MEEM..ARABIC MATHEMATICAL STRETCHED QAF -1EE74..1EE77;N # Lo [4] ARABIC MATHEMATICAL STRETCHED SHEEN..ARABIC MATHEMATICAL STRETCHED KHAH -1EE79..1EE7C;N # Lo [4] ARABIC MATHEMATICAL STRETCHED DAD..ARABIC MATHEMATICAL STRETCHED DOTLESS BEH -1EE7E;N # Lo ARABIC MATHEMATICAL STRETCHED DOTLESS FEH -1EE80..1EE89;N # Lo [10] ARABIC MATHEMATICAL LOOPED ALEF..ARABIC MATHEMATICAL LOOPED YEH -1EE8B..1EE9B;N # Lo [17] ARABIC MATHEMATICAL LOOPED LAM..ARABIC MATHEMATICAL LOOPED GHAIN -1EEA1..1EEA3;N # Lo [3] ARABIC MATHEMATICAL DOUBLE-STRUCK BEH..ARABIC MATHEMATICAL DOUBLE-STRUCK DAL -1EEA5..1EEA9;N # Lo [5] ARABIC MATHEMATICAL DOUBLE-STRUCK WAW..ARABIC MATHEMATICAL DOUBLE-STRUCK YEH -1EEAB..1EEBB;N # Lo [17] ARABIC MATHEMATICAL DOUBLE-STRUCK LAM..ARABIC MATHEMATICAL DOUBLE-STRUCK GHAIN -1EEF0..1EEF1;N # Sm [2] ARABIC MATHEMATICAL OPERATOR MEEM WITH HAH WITH TATWEEL..ARABIC MATHEMATICAL OPERATOR HAH WITH DAL -1F000..1F003;N # So [4] MAHJONG TILE EAST WIND..MAHJONG TILE NORTH WIND -1F004;W # So MAHJONG TILE RED DRAGON -1F005..1F02B;N # So [39] MAHJONG TILE GREEN DRAGON..MAHJONG TILE BACK -1F030..1F093;N # So [100] DOMINO TILE HORIZONTAL BACK..DOMINO TILE VERTICAL-06-06 -1F0A0..1F0AE;N # So [15] PLAYING CARD BACK..PLAYING CARD KING OF SPADES -1F0B1..1F0BF;N # So [15] PLAYING CARD ACE OF HEARTS..PLAYING CARD RED JOKER -1F0C1..1F0CE;N # So [14] PLAYING CARD ACE OF DIAMONDS..PLAYING CARD KING OF DIAMONDS -1F0CF;W # So PLAYING CARD BLACK JOKER -1F0D1..1F0F5;N # So [37] PLAYING CARD ACE OF CLUBS..PLAYING CARD TRUMP-21 -1F100..1F10A;A # No [11] DIGIT ZERO FULL STOP..DIGIT NINE COMMA -1F10B..1F10C;N # No [2] DINGBAT CIRCLED SANS-SERIF DIGIT ZERO..DINGBAT NEGATIVE CIRCLED SANS-SERIF DIGIT ZERO -1F10D..1F10F;N # So [3] CIRCLED ZERO WITH SLASH..CIRCLED DOLLAR SIGN WITH OVERLAID BACKSLASH -1F110..1F12D;A # So [30] PARENTHESIZED LATIN CAPITAL LETTER A..CIRCLED CD -1F12E..1F12F;N # So [2] CIRCLED WZ..COPYLEFT SYMBOL -1F130..1F169;A # So [58] SQUARED LATIN CAPITAL LETTER A..NEGATIVE CIRCLED LATIN CAPITAL LETTER Z -1F16A..1F16F;N # So [6] RAISED MC SIGN..CIRCLED HUMAN FIGURE -1F170..1F18D;A # So [30] NEGATIVE SQUARED LATIN CAPITAL LETTER A..NEGATIVE SQUARED SA -1F18E;W # So NEGATIVE SQUARED AB -1F18F..1F190;A # So [2] NEGATIVE SQUARED WC..SQUARE DJ -1F191..1F19A;W # So [10] SQUARED CL..SQUARED VS -1F19B..1F1AC;A # So [18] SQUARED THREE D..SQUARED VOD -1F1AD;N # So MASK WORK SYMBOL -1F1E6..1F1FF;N # So [26] REGIONAL INDICATOR SYMBOL LETTER A..REGIONAL INDICATOR SYMBOL LETTER Z -1F200..1F202;W # So [3] SQUARE HIRAGANA HOKA..SQUARED KATAKANA SA -1F210..1F23B;W # So [44] SQUARED CJK UNIFIED IDEOGRAPH-624B..SQUARED CJK UNIFIED IDEOGRAPH-914D -1F240..1F248;W # So [9] TORTOISE SHELL BRACKETED CJK UNIFIED IDEOGRAPH-672C..TORTOISE SHELL BRACKETED CJK UNIFIED IDEOGRAPH-6557 -1F250..1F251;W # So [2] CIRCLED IDEOGRAPH ADVANTAGE..CIRCLED IDEOGRAPH ACCEPT -1F260..1F265;W # So [6] ROUNDED SYMBOL FOR FU..ROUNDED SYMBOL FOR CAI -1F300..1F320;W # So [33] CYCLONE..SHOOTING STAR -1F321..1F32C;N # So [12] THERMOMETER..WIND BLOWING FACE -1F32D..1F335;W # So [9] HOT DOG..CACTUS -1F336;N # So HOT PEPPER -1F337..1F37C;W # So [70] TULIP..BABY BOTTLE -1F37D;N # So FORK AND KNIFE WITH PLATE -1F37E..1F393;W # So [22] BOTTLE WITH POPPING CORK..GRADUATION CAP -1F394..1F39F;N # So [12] HEART WITH TIP ON THE LEFT..ADMISSION TICKETS -1F3A0..1F3CA;W # So [43] CAROUSEL HORSE..SWIMMER -1F3CB..1F3CE;N # So [4] WEIGHT LIFTER..RACING CAR -1F3CF..1F3D3;W # So [5] CRICKET BAT AND BALL..TABLE TENNIS PADDLE AND BALL -1F3D4..1F3DF;N # So [12] SNOW CAPPED MOUNTAIN..STADIUM -1F3E0..1F3F0;W # So [17] HOUSE BUILDING..EUROPEAN CASTLE -1F3F1..1F3F3;N # So [3] WHITE PENNANT..WAVING WHITE FLAG -1F3F4;W # So WAVING BLACK FLAG -1F3F5..1F3F7;N # So [3] ROSETTE..LABEL -1F3F8..1F3FA;W # So [3] BADMINTON RACQUET AND SHUTTLECOCK..AMPHORA -1F3FB..1F3FF;W # Sk [5] EMOJI MODIFIER FITZPATRICK TYPE-1-2..EMOJI MODIFIER FITZPATRICK TYPE-6 -1F400..1F43E;W # So [63] RAT..PAW PRINTS -1F43F;N # So CHIPMUNK -1F440;W # So EYES -1F441;N # So EYE -1F442..1F4FC;W # So [187] EAR..VIDEOCASSETTE -1F4FD..1F4FE;N # So [2] FILM PROJECTOR..PORTABLE STEREO -1F4FF..1F53D;W # So [63] PRAYER BEADS..DOWN-POINTING SMALL RED TRIANGLE -1F53E..1F54A;N # So [13] LOWER RIGHT SHADOWED WHITE CIRCLE..DOVE OF PEACE -1F54B..1F54E;W # So [4] KAABA..MENORAH WITH NINE BRANCHES -1F54F;N # So BOWL OF HYGIEIA -1F550..1F567;W # So [24] CLOCK FACE ONE OCLOCK..CLOCK FACE TWELVE-THIRTY -1F568..1F579;N # So [18] RIGHT SPEAKER..JOYSTICK -1F57A;W # So MAN DANCING -1F57B..1F594;N # So [26] LEFT HAND TELEPHONE RECEIVER..REVERSED VICTORY HAND -1F595..1F596;W # So [2] REVERSED HAND WITH MIDDLE FINGER EXTENDED..RAISED HAND WITH PART BETWEEN MIDDLE AND RING FINGERS -1F597..1F5A3;N # So [13] WHITE DOWN POINTING LEFT HAND INDEX..BLACK DOWN POINTING BACKHAND INDEX -1F5A4;W # So BLACK HEART -1F5A5..1F5FA;N # So [86] DESKTOP COMPUTER..WORLD MAP -1F5FB..1F5FF;W # So [5] MOUNT FUJI..MOYAI -1F600..1F64F;W # So [80] GRINNING FACE..PERSON WITH FOLDED HANDS -1F650..1F67F;N # So [48] NORTH WEST POINTING LEAF..REVERSE CHECKER BOARD -1F680..1F6C5;W # So [70] ROCKET..LEFT LUGGAGE -1F6C6..1F6CB;N # So [6] TRIANGLE WITH ROUNDED CORNERS..COUCH AND LAMP -1F6CC;W # So SLEEPING ACCOMMODATION -1F6CD..1F6CF;N # So [3] SHOPPING BAGS..BED -1F6D0..1F6D2;W # So [3] PLACE OF WORSHIP..SHOPPING TROLLEY -1F6D3..1F6D4;N # So [2] STUPA..PAGODA -1F6D5..1F6D7;W # So [3] HINDU TEMPLE..ELEVATOR -1F6DC..1F6DF;W # So [4] WIRELESS..RING BUOY -1F6E0..1F6EA;N # So [11] HAMMER AND WRENCH..NORTHEAST-POINTING AIRPLANE -1F6EB..1F6EC;W # So [2] AIRPLANE DEPARTURE..AIRPLANE ARRIVING -1F6F0..1F6F3;N # So [4] SATELLITE..PASSENGER SHIP -1F6F4..1F6FC;W # So [9] SCOOTER..ROLLER SKATE -1F700..1F776;N # So [119] ALCHEMICAL SYMBOL FOR QUINTESSENCE..LUNAR ECLIPSE -1F77B..1F77F;N # So [5] HAUMEA..ORCUS -1F780..1F7D9;N # So [90] BLACK LEFT-POINTING ISOSCELES RIGHT TRIANGLE..NINE POINTED WHITE STAR -1F7E0..1F7EB;W # So [12] LARGE ORANGE CIRCLE..LARGE BROWN SQUARE -1F7F0;W # So HEAVY EQUALS SIGN -1F800..1F80B;N # So [12] LEFTWARDS ARROW WITH SMALL TRIANGLE ARROWHEAD..DOWNWARDS ARROW WITH LARGE TRIANGLE ARROWHEAD -1F810..1F847;N # So [56] LEFTWARDS ARROW WITH SMALL EQUILATERAL ARROWHEAD..DOWNWARDS HEAVY ARROW -1F850..1F859;N # So [10] LEFTWARDS SANS-SERIF ARROW..UP DOWN SANS-SERIF ARROW -1F860..1F887;N # So [40] WIDE-HEADED LEFTWARDS LIGHT BARB ARROW..WIDE-HEADED SOUTH WEST VERY HEAVY BARB ARROW -1F890..1F8AD;N # So [30] LEFTWARDS TRIANGLE ARROWHEAD..WHITE ARROW SHAFT WIDTH TWO THIRDS -1F8B0..1F8B1;N # So [2] ARROW POINTING UPWARDS THEN NORTH WEST..ARROW POINTING RIGHTWARDS THEN CURVING SOUTH WEST -1F900..1F90B;N # So [12] CIRCLED CROSS FORMEE WITH FOUR DOTS..DOWNWARD FACING NOTCHED HOOK WITH DOT -1F90C..1F93A;W # So [47] PINCHED FINGERS..FENCER -1F93B;N # So MODERN PENTATHLON -1F93C..1F945;W # So [10] WRESTLERS..GOAL NET -1F946;N # So RIFLE -1F947..1F9FF;W # So [185] FIRST PLACE MEDAL..NAZAR AMULET -1FA00..1FA53;N # So [84] NEUTRAL CHESS KING..BLACK CHESS KNIGHT-BISHOP -1FA60..1FA6D;N # So [14] XIANGQI RED GENERAL..XIANGQI BLACK SOLDIER -1FA70..1FA7C;W # So [13] BALLET SHOES..CRUTCH -1FA80..1FA88;W # So [9] YO-YO..FLUTE -1FA90..1FABD;W # So [46] RINGED PLANET..WING -1FABF..1FAC5;W # So [7] GOOSE..PERSON WITH CROWN -1FACE..1FADB;W # So [14] MOOSE..PEA POD -1FAE0..1FAE8;W # So [9] MELTING FACE..SHAKING FACE -1FAF0..1FAF8;W # So [9] HAND WITH INDEX FINGER AND THUMB CROSSED..RIGHTWARDS PUSHING HAND -1FB00..1FB92;N # So [147] BLOCK SEXTANT-1..UPPER HALF INVERSE MEDIUM SHADE AND LOWER HALF BLOCK -1FB94..1FBCA;N # So [55] LEFT HALF INVERSE MEDIUM SHADE AND RIGHT HALF BLOCK..WHITE UP-POINTING CHEVRON -1FBF0..1FBF9;N # Nd [10] SEGMENTED DIGIT ZERO..SEGMENTED DIGIT NINE -20000..2A6DF;W # Lo [42720] CJK UNIFIED IDEOGRAPH-20000..CJK UNIFIED IDEOGRAPH-2A6DF -2A6E0..2A6FF;W # Cn [32] .. -2A700..2B739;W # Lo [4154] CJK UNIFIED IDEOGRAPH-2A700..CJK UNIFIED IDEOGRAPH-2B739 -2B73A..2B73F;W # Cn [6] .. -2B740..2B81D;W # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D -2B81E..2B81F;W # Cn [2] .. -2B820..2CEA1;W # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 -2CEA2..2CEAF;W # Cn [14] .. -2CEB0..2EBE0;W # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 -2EBE1..2F7FF;W # Cn [3103] .. -2F800..2FA1D;W # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D -2FA1E..2FA1F;W # Cn [2] .. -2FA20..2FFFD;W # Cn [1502] .. -30000..3134A;W # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A -3134B..3134F;W # Cn [5] .. -31350..323AF;W # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF -323B0..3FFFD;W # Cn [56398] .. -E0001;N # Cf LANGUAGE TAG -E0020..E007F;N # Cf [96] TAG SPACE..CANCEL TAG -E0100..E01EF;A # Mn [240] VARIATION SELECTOR-17..VARIATION SELECTOR-256 -F0000..FFFFD;A # Co [65534] .. -100000..10FFFD;A # Co [65534] .. +0000..001F ; N # Cc [32] .. +0020 ; Na # Zs SPACE +0021..0023 ; Na # Po [3] EXCLAMATION MARK..NUMBER SIGN +0024 ; Na # Sc DOLLAR SIGN +0025..0027 ; Na # Po [3] PERCENT SIGN..APOSTROPHE +0028 ; Na # Ps LEFT PARENTHESIS +0029 ; Na # Pe RIGHT PARENTHESIS +002A ; Na # Po ASTERISK +002B ; Na # Sm PLUS SIGN +002C ; Na # Po COMMA +002D ; Na # Pd HYPHEN-MINUS +002E..002F ; Na # Po [2] FULL STOP..SOLIDUS +0030..0039 ; Na # Nd [10] DIGIT ZERO..DIGIT NINE +003A..003B ; Na # Po [2] COLON..SEMICOLON +003C..003E ; Na # Sm [3] LESS-THAN SIGN..GREATER-THAN SIGN +003F..0040 ; Na # Po [2] QUESTION MARK..COMMERCIAL AT +0041..005A ; Na # Lu [26] LATIN CAPITAL LETTER A..LATIN CAPITAL LETTER Z +005B ; Na # Ps LEFT SQUARE BRACKET +005C ; Na # Po REVERSE SOLIDUS +005D ; Na # Pe RIGHT SQUARE BRACKET +005E ; Na # Sk CIRCUMFLEX ACCENT +005F ; Na # Pc LOW LINE +0060 ; Na # Sk GRAVE ACCENT +0061..007A ; Na # Ll [26] LATIN SMALL LETTER A..LATIN SMALL LETTER Z +007B ; Na # Ps LEFT CURLY BRACKET +007C ; Na # Sm VERTICAL LINE +007D ; Na # Pe RIGHT CURLY BRACKET +007E ; Na # Sm TILDE +007F ; N # Cc +0080..009F ; N # Cc [32] .. +00A0 ; N # Zs NO-BREAK SPACE +00A1 ; A # Po INVERTED EXCLAMATION MARK +00A2..00A3 ; Na # Sc [2] CENT SIGN..POUND SIGN +00A4 ; A # Sc CURRENCY SIGN +00A5 ; Na # Sc YEN SIGN +00A6 ; Na # So BROKEN BAR +00A7 ; A # Po SECTION SIGN +00A8 ; A # Sk DIAERESIS +00A9 ; N # So COPYRIGHT SIGN +00AA ; A # Lo FEMININE ORDINAL INDICATOR +00AB ; N # Pi LEFT-POINTING DOUBLE ANGLE QUOTATION MARK +00AC ; Na # Sm NOT SIGN +00AD ; A # Cf SOFT HYPHEN +00AE ; A # So REGISTERED SIGN +00AF ; Na # Sk MACRON +00B0 ; A # So DEGREE SIGN +00B1 ; A # Sm PLUS-MINUS SIGN +00B2..00B3 ; A # No [2] SUPERSCRIPT TWO..SUPERSCRIPT THREE +00B4 ; A # Sk ACUTE ACCENT +00B5 ; N # Ll MICRO SIGN +00B6..00B7 ; A # Po [2] PILCROW SIGN..MIDDLE DOT +00B8 ; A # Sk CEDILLA +00B9 ; A # No SUPERSCRIPT ONE +00BA ; A # Lo MASCULINE ORDINAL INDICATOR +00BB ; N # Pf RIGHT-POINTING DOUBLE ANGLE QUOTATION MARK +00BC..00BE ; A # No [3] VULGAR FRACTION ONE QUARTER..VULGAR FRACTION THREE QUARTERS +00BF ; A # Po INVERTED QUESTION MARK +00C0..00C5 ; N # Lu [6] LATIN CAPITAL LETTER A WITH GRAVE..LATIN CAPITAL LETTER A WITH RING ABOVE +00C6 ; A # Lu LATIN CAPITAL LETTER AE +00C7..00CF ; N # Lu [9] LATIN CAPITAL LETTER C WITH CEDILLA..LATIN CAPITAL LETTER I WITH DIAERESIS +00D0 ; A # Lu LATIN CAPITAL LETTER ETH +00D1..00D6 ; N # Lu [6] LATIN CAPITAL LETTER N WITH TILDE..LATIN CAPITAL LETTER O WITH DIAERESIS +00D7 ; A # Sm MULTIPLICATION SIGN +00D8 ; A # Lu LATIN CAPITAL LETTER O WITH STROKE +00D9..00DD ; N # Lu [5] LATIN CAPITAL LETTER U WITH GRAVE..LATIN CAPITAL LETTER Y WITH ACUTE +00DE..00E1 ; A # L& [4] LATIN CAPITAL LETTER THORN..LATIN SMALL LETTER A WITH ACUTE +00E2..00E5 ; N # Ll [4] LATIN SMALL LETTER A WITH CIRCUMFLEX..LATIN SMALL LETTER A WITH RING ABOVE +00E6 ; A # Ll LATIN SMALL LETTER AE +00E7 ; N # Ll LATIN SMALL LETTER C WITH CEDILLA +00E8..00EA ; A # Ll [3] LATIN SMALL LETTER E WITH GRAVE..LATIN SMALL LETTER E WITH CIRCUMFLEX +00EB ; N # Ll LATIN SMALL LETTER E WITH DIAERESIS +00EC..00ED ; A # Ll [2] LATIN SMALL LETTER I WITH GRAVE..LATIN SMALL LETTER I WITH ACUTE +00EE..00EF ; N # Ll [2] LATIN SMALL LETTER I WITH CIRCUMFLEX..LATIN SMALL LETTER I WITH DIAERESIS +00F0 ; A # Ll LATIN SMALL LETTER ETH +00F1 ; N # Ll LATIN SMALL LETTER N WITH TILDE +00F2..00F3 ; A # Ll [2] LATIN SMALL LETTER O WITH GRAVE..LATIN SMALL LETTER O WITH ACUTE +00F4..00F6 ; N # Ll [3] LATIN SMALL LETTER O WITH CIRCUMFLEX..LATIN SMALL LETTER O WITH DIAERESIS +00F7 ; A # Sm DIVISION SIGN +00F8..00FA ; A # Ll [3] LATIN SMALL LETTER O WITH STROKE..LATIN SMALL LETTER U WITH ACUTE +00FB ; N # Ll LATIN SMALL LETTER U WITH CIRCUMFLEX +00FC ; A # Ll LATIN SMALL LETTER U WITH DIAERESIS +00FD ; N # Ll LATIN SMALL LETTER Y WITH ACUTE +00FE ; A # Ll LATIN SMALL LETTER THORN +00FF ; N # Ll LATIN SMALL LETTER Y WITH DIAERESIS +0100 ; N # Lu LATIN CAPITAL LETTER A WITH MACRON +0101 ; A # Ll LATIN SMALL LETTER A WITH MACRON +0102..0110 ; N # L& [15] LATIN CAPITAL LETTER A WITH BREVE..LATIN CAPITAL LETTER D WITH STROKE +0111 ; A # Ll LATIN SMALL LETTER D WITH STROKE +0112 ; N # Lu LATIN CAPITAL LETTER E WITH MACRON +0113 ; A # Ll LATIN SMALL LETTER E WITH MACRON +0114..011A ; N # L& [7] LATIN CAPITAL LETTER E WITH BREVE..LATIN CAPITAL LETTER E WITH CARON +011B ; A # Ll LATIN SMALL LETTER E WITH CARON +011C..0125 ; N # L& [10] LATIN CAPITAL LETTER G WITH CIRCUMFLEX..LATIN SMALL LETTER H WITH CIRCUMFLEX +0126..0127 ; A # L& [2] LATIN CAPITAL LETTER H WITH STROKE..LATIN SMALL LETTER H WITH STROKE +0128..012A ; N # L& [3] LATIN CAPITAL LETTER I WITH TILDE..LATIN CAPITAL LETTER I WITH MACRON +012B ; A # Ll LATIN SMALL LETTER I WITH MACRON +012C..0130 ; N # L& [5] LATIN CAPITAL LETTER I WITH BREVE..LATIN CAPITAL LETTER I WITH DOT ABOVE +0131..0133 ; A # L& [3] LATIN SMALL LETTER DOTLESS I..LATIN SMALL LIGATURE IJ +0134..0137 ; N # L& [4] LATIN CAPITAL LETTER J WITH CIRCUMFLEX..LATIN SMALL LETTER K WITH CEDILLA +0138 ; A # Ll LATIN SMALL LETTER KRA +0139..013E ; N # L& [6] LATIN CAPITAL LETTER L WITH ACUTE..LATIN SMALL LETTER L WITH CARON +013F..0142 ; A # L& [4] LATIN CAPITAL LETTER L WITH MIDDLE DOT..LATIN SMALL LETTER L WITH STROKE +0143 ; N # Lu LATIN CAPITAL LETTER N WITH ACUTE +0144 ; A # Ll LATIN SMALL LETTER N WITH ACUTE +0145..0147 ; N # L& [3] LATIN CAPITAL LETTER N WITH CEDILLA..LATIN CAPITAL LETTER N WITH CARON +0148..014B ; A # L& [4] LATIN SMALL LETTER N WITH CARON..LATIN SMALL LETTER ENG +014C ; N # Lu LATIN CAPITAL LETTER O WITH MACRON +014D ; A # Ll LATIN SMALL LETTER O WITH MACRON +014E..0151 ; N # L& [4] LATIN CAPITAL LETTER O WITH BREVE..LATIN SMALL LETTER O WITH DOUBLE ACUTE +0152..0153 ; A # L& [2] LATIN CAPITAL LIGATURE OE..LATIN SMALL LIGATURE OE +0154..0165 ; N # L& [18] LATIN CAPITAL LETTER R WITH ACUTE..LATIN SMALL LETTER T WITH CARON +0166..0167 ; A # L& [2] LATIN CAPITAL LETTER T WITH STROKE..LATIN SMALL LETTER T WITH STROKE +0168..016A ; N # L& [3] LATIN CAPITAL LETTER U WITH TILDE..LATIN CAPITAL LETTER U WITH MACRON +016B ; A # Ll LATIN SMALL LETTER U WITH MACRON +016C..017F ; N # L& [20] LATIN CAPITAL LETTER U WITH BREVE..LATIN SMALL LETTER LONG S +0180..01BA ; N # L& [59] LATIN SMALL LETTER B WITH STROKE..LATIN SMALL LETTER EZH WITH TAIL +01BB ; N # Lo LATIN LETTER TWO WITH STROKE +01BC..01BF ; N # L& [4] LATIN CAPITAL LETTER TONE FIVE..LATIN LETTER WYNN +01C0..01C3 ; N # Lo [4] LATIN LETTER DENTAL CLICK..LATIN LETTER RETROFLEX CLICK +01C4..01CD ; N # L& [10] LATIN CAPITAL LETTER DZ WITH CARON..LATIN CAPITAL LETTER A WITH CARON +01CE ; A # Ll LATIN SMALL LETTER A WITH CARON +01CF ; N # Lu LATIN CAPITAL LETTER I WITH CARON +01D0 ; A # Ll LATIN SMALL LETTER I WITH CARON +01D1 ; N # Lu LATIN CAPITAL LETTER O WITH CARON +01D2 ; A # Ll LATIN SMALL LETTER O WITH CARON +01D3 ; N # Lu LATIN CAPITAL LETTER U WITH CARON +01D4 ; A # Ll LATIN SMALL LETTER U WITH CARON +01D5 ; N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND MACRON +01D6 ; A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND MACRON +01D7 ; N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND ACUTE +01D8 ; A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND ACUTE +01D9 ; N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND CARON +01DA ; A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND CARON +01DB ; N # Lu LATIN CAPITAL LETTER U WITH DIAERESIS AND GRAVE +01DC ; A # Ll LATIN SMALL LETTER U WITH DIAERESIS AND GRAVE +01DD..024F ; N # L& [115] LATIN SMALL LETTER TURNED E..LATIN SMALL LETTER Y WITH STROKE +0250 ; N # Ll LATIN SMALL LETTER TURNED A +0251 ; A # Ll LATIN SMALL LETTER ALPHA +0252..0260 ; N # Ll [15] LATIN SMALL LETTER TURNED ALPHA..LATIN SMALL LETTER G WITH HOOK +0261 ; A # Ll LATIN SMALL LETTER SCRIPT G +0262..0293 ; N # Ll [50] LATIN LETTER SMALL CAPITAL G..LATIN SMALL LETTER EZH WITH CURL +0294 ; N # Lo LATIN LETTER GLOTTAL STOP +0295..02AF ; N # Ll [27] LATIN LETTER PHARYNGEAL VOICED FRICATIVE..LATIN SMALL LETTER TURNED H WITH FISHHOOK AND TAIL +02B0..02C1 ; N # Lm [18] MODIFIER LETTER SMALL H..MODIFIER LETTER REVERSED GLOTTAL STOP +02C2..02C3 ; N # Sk [2] MODIFIER LETTER LEFT ARROWHEAD..MODIFIER LETTER RIGHT ARROWHEAD +02C4 ; A # Sk MODIFIER LETTER UP ARROWHEAD +02C5 ; N # Sk MODIFIER LETTER DOWN ARROWHEAD +02C6 ; N # Lm MODIFIER LETTER CIRCUMFLEX ACCENT +02C7 ; A # Lm CARON +02C8 ; N # Lm MODIFIER LETTER VERTICAL LINE +02C9..02CB ; A # Lm [3] MODIFIER LETTER MACRON..MODIFIER LETTER GRAVE ACCENT +02CC ; N # Lm MODIFIER LETTER LOW VERTICAL LINE +02CD ; A # Lm MODIFIER LETTER LOW MACRON +02CE..02CF ; N # Lm [2] MODIFIER LETTER LOW GRAVE ACCENT..MODIFIER LETTER LOW ACUTE ACCENT +02D0 ; A # Lm MODIFIER LETTER TRIANGULAR COLON +02D1 ; N # Lm MODIFIER LETTER HALF TRIANGULAR COLON +02D2..02D7 ; N # Sk [6] MODIFIER LETTER CENTRED RIGHT HALF RING..MODIFIER LETTER MINUS SIGN +02D8..02DB ; A # Sk [4] BREVE..OGONEK +02DC ; N # Sk SMALL TILDE +02DD ; A # Sk DOUBLE ACUTE ACCENT +02DE ; N # Sk MODIFIER LETTER RHOTIC HOOK +02DF ; A # Sk MODIFIER LETTER CROSS ACCENT +02E0..02E4 ; N # Lm [5] MODIFIER LETTER SMALL GAMMA..MODIFIER LETTER SMALL REVERSED GLOTTAL STOP +02E5..02EB ; N # Sk [7] MODIFIER LETTER EXTRA-HIGH TONE BAR..MODIFIER LETTER YANG DEPARTING TONE MARK +02EC ; N # Lm MODIFIER LETTER VOICING +02ED ; N # Sk MODIFIER LETTER UNASPIRATED +02EE ; N # Lm MODIFIER LETTER DOUBLE APOSTROPHE +02EF..02FF ; N # Sk [17] MODIFIER LETTER LOW DOWN ARROWHEAD..MODIFIER LETTER LOW LEFT ARROW +0300..036F ; A # Mn [112] COMBINING GRAVE ACCENT..COMBINING LATIN SMALL LETTER X +0370..0373 ; N # L& [4] GREEK CAPITAL LETTER HETA..GREEK SMALL LETTER ARCHAIC SAMPI +0374 ; N # Lm GREEK NUMERAL SIGN +0375 ; N # Sk GREEK LOWER NUMERAL SIGN +0376..0377 ; N # L& [2] GREEK CAPITAL LETTER PAMPHYLIAN DIGAMMA..GREEK SMALL LETTER PAMPHYLIAN DIGAMMA +037A ; N # Lm GREEK YPOGEGRAMMENI +037B..037D ; N # Ll [3] GREEK SMALL REVERSED LUNATE SIGMA SYMBOL..GREEK SMALL REVERSED DOTTED LUNATE SIGMA SYMBOL +037E ; N # Po GREEK QUESTION MARK +037F ; N # Lu GREEK CAPITAL LETTER YOT +0384..0385 ; N # Sk [2] GREEK TONOS..GREEK DIALYTIKA TONOS +0386 ; N # Lu GREEK CAPITAL LETTER ALPHA WITH TONOS +0387 ; N # Po GREEK ANO TELEIA +0388..038A ; N # Lu [3] GREEK CAPITAL LETTER EPSILON WITH TONOS..GREEK CAPITAL LETTER IOTA WITH TONOS +038C ; N # Lu GREEK CAPITAL LETTER OMICRON WITH TONOS +038E..0390 ; N # L& [3] GREEK CAPITAL LETTER UPSILON WITH TONOS..GREEK SMALL LETTER IOTA WITH DIALYTIKA AND TONOS +0391..03A1 ; A # Lu [17] GREEK CAPITAL LETTER ALPHA..GREEK CAPITAL LETTER RHO +03A3..03A9 ; A # Lu [7] GREEK CAPITAL LETTER SIGMA..GREEK CAPITAL LETTER OMEGA +03AA..03B0 ; N # L& [7] GREEK CAPITAL LETTER IOTA WITH DIALYTIKA..GREEK SMALL LETTER UPSILON WITH DIALYTIKA AND TONOS +03B1..03C1 ; A # Ll [17] GREEK SMALL LETTER ALPHA..GREEK SMALL LETTER RHO +03C2 ; N # Ll GREEK SMALL LETTER FINAL SIGMA +03C3..03C9 ; A # Ll [7] GREEK SMALL LETTER SIGMA..GREEK SMALL LETTER OMEGA +03CA..03F5 ; N # L& [44] GREEK SMALL LETTER IOTA WITH DIALYTIKA..GREEK LUNATE EPSILON SYMBOL +03F6 ; N # Sm GREEK REVERSED LUNATE EPSILON SYMBOL +03F7..03FF ; N # L& [9] GREEK CAPITAL LETTER SHO..GREEK CAPITAL REVERSED DOTTED LUNATE SIGMA SYMBOL +0400 ; N # Lu CYRILLIC CAPITAL LETTER IE WITH GRAVE +0401 ; A # Lu CYRILLIC CAPITAL LETTER IO +0402..040F ; N # Lu [14] CYRILLIC CAPITAL LETTER DJE..CYRILLIC CAPITAL LETTER DZHE +0410..044F ; A # L& [64] CYRILLIC CAPITAL LETTER A..CYRILLIC SMALL LETTER YA +0450 ; N # Ll CYRILLIC SMALL LETTER IE WITH GRAVE +0451 ; A # Ll CYRILLIC SMALL LETTER IO +0452..0481 ; N # L& [48] CYRILLIC SMALL LETTER DJE..CYRILLIC SMALL LETTER KOPPA +0482 ; N # So CYRILLIC THOUSANDS SIGN +0483..0487 ; N # Mn [5] COMBINING CYRILLIC TITLO..COMBINING CYRILLIC POKRYTIE +0488..0489 ; N # Me [2] COMBINING CYRILLIC HUNDRED THOUSANDS SIGN..COMBINING CYRILLIC MILLIONS SIGN +048A..04FF ; N # L& [118] CYRILLIC CAPITAL LETTER SHORT I WITH TAIL..CYRILLIC SMALL LETTER HA WITH STROKE +0500..052F ; N # L& [48] CYRILLIC CAPITAL LETTER KOMI DE..CYRILLIC SMALL LETTER EL WITH DESCENDER +0531..0556 ; N # Lu [38] ARMENIAN CAPITAL LETTER AYB..ARMENIAN CAPITAL LETTER FEH +0559 ; N # Lm ARMENIAN MODIFIER LETTER LEFT HALF RING +055A..055F ; N # Po [6] ARMENIAN APOSTROPHE..ARMENIAN ABBREVIATION MARK +0560..0588 ; N # Ll [41] ARMENIAN SMALL LETTER TURNED AYB..ARMENIAN SMALL LETTER YI WITH STROKE +0589 ; N # Po ARMENIAN FULL STOP +058A ; N # Pd ARMENIAN HYPHEN +058D..058E ; N # So [2] RIGHT-FACING ARMENIAN ETERNITY SIGN..LEFT-FACING ARMENIAN ETERNITY SIGN +058F ; N # Sc ARMENIAN DRAM SIGN +0591..05BD ; N # Mn [45] HEBREW ACCENT ETNAHTA..HEBREW POINT METEG +05BE ; N # Pd HEBREW PUNCTUATION MAQAF +05BF ; N # Mn HEBREW POINT RAFE +05C0 ; N # Po HEBREW PUNCTUATION PASEQ +05C1..05C2 ; N # Mn [2] HEBREW POINT SHIN DOT..HEBREW POINT SIN DOT +05C3 ; N # Po HEBREW PUNCTUATION SOF PASUQ +05C4..05C5 ; N # Mn [2] HEBREW MARK UPPER DOT..HEBREW MARK LOWER DOT +05C6 ; N # Po HEBREW PUNCTUATION NUN HAFUKHA +05C7 ; N # Mn HEBREW POINT QAMATS QATAN +05D0..05EA ; N # Lo [27] HEBREW LETTER ALEF..HEBREW LETTER TAV +05EF..05F2 ; N # Lo [4] HEBREW YOD TRIANGLE..HEBREW LIGATURE YIDDISH DOUBLE YOD +05F3..05F4 ; N # Po [2] HEBREW PUNCTUATION GERESH..HEBREW PUNCTUATION GERSHAYIM +0600..0605 ; N # Cf [6] ARABIC NUMBER SIGN..ARABIC NUMBER MARK ABOVE +0606..0608 ; N # Sm [3] ARABIC-INDIC CUBE ROOT..ARABIC RAY +0609..060A ; N # Po [2] ARABIC-INDIC PER MILLE SIGN..ARABIC-INDIC PER TEN THOUSAND SIGN +060B ; N # Sc AFGHANI SIGN +060C..060D ; N # Po [2] ARABIC COMMA..ARABIC DATE SEPARATOR +060E..060F ; N # So [2] ARABIC POETIC VERSE SIGN..ARABIC SIGN MISRA +0610..061A ; N # Mn [11] ARABIC SIGN SALLALLAHOU ALAYHE WASSALLAM..ARABIC SMALL KASRA +061B ; N # Po ARABIC SEMICOLON +061C ; N # Cf ARABIC LETTER MARK +061D..061F ; N # Po [3] ARABIC END OF TEXT MARK..ARABIC QUESTION MARK +0620..063F ; N # Lo [32] ARABIC LETTER KASHMIRI YEH..ARABIC LETTER FARSI YEH WITH THREE DOTS ABOVE +0640 ; N # Lm ARABIC TATWEEL +0641..064A ; N # Lo [10] ARABIC LETTER FEH..ARABIC LETTER YEH +064B..065F ; N # Mn [21] ARABIC FATHATAN..ARABIC WAVY HAMZA BELOW +0660..0669 ; N # Nd [10] ARABIC-INDIC DIGIT ZERO..ARABIC-INDIC DIGIT NINE +066A..066D ; N # Po [4] ARABIC PERCENT SIGN..ARABIC FIVE POINTED STAR +066E..066F ; N # Lo [2] ARABIC LETTER DOTLESS BEH..ARABIC LETTER DOTLESS QAF +0670 ; N # Mn ARABIC LETTER SUPERSCRIPT ALEF +0671..06D3 ; N # Lo [99] ARABIC LETTER ALEF WASLA..ARABIC LETTER YEH BARREE WITH HAMZA ABOVE +06D4 ; N # Po ARABIC FULL STOP +06D5 ; N # Lo ARABIC LETTER AE +06D6..06DC ; N # Mn [7] ARABIC SMALL HIGH LIGATURE SAD WITH LAM WITH ALEF MAKSURA..ARABIC SMALL HIGH SEEN +06DD ; N # Cf ARABIC END OF AYAH +06DE ; N # So ARABIC START OF RUB EL HIZB +06DF..06E4 ; N # Mn [6] ARABIC SMALL HIGH ROUNDED ZERO..ARABIC SMALL HIGH MADDA +06E5..06E6 ; N # Lm [2] ARABIC SMALL WAW..ARABIC SMALL YEH +06E7..06E8 ; N # Mn [2] ARABIC SMALL HIGH YEH..ARABIC SMALL HIGH NOON +06E9 ; N # So ARABIC PLACE OF SAJDAH +06EA..06ED ; N # Mn [4] ARABIC EMPTY CENTRE LOW STOP..ARABIC SMALL LOW MEEM +06EE..06EF ; N # Lo [2] ARABIC LETTER DAL WITH INVERTED V..ARABIC LETTER REH WITH INVERTED V +06F0..06F9 ; N # Nd [10] EXTENDED ARABIC-INDIC DIGIT ZERO..EXTENDED ARABIC-INDIC DIGIT NINE +06FA..06FC ; N # Lo [3] ARABIC LETTER SHEEN WITH DOT BELOW..ARABIC LETTER GHAIN WITH DOT BELOW +06FD..06FE ; N # So [2] ARABIC SIGN SINDHI AMPERSAND..ARABIC SIGN SINDHI POSTPOSITION MEN +06FF ; N # Lo ARABIC LETTER HEH WITH INVERTED V +0700..070D ; N # Po [14] SYRIAC END OF PARAGRAPH..SYRIAC HARKLEAN ASTERISCUS +070F ; N # Cf SYRIAC ABBREVIATION MARK +0710 ; N # Lo SYRIAC LETTER ALAPH +0711 ; N # Mn SYRIAC LETTER SUPERSCRIPT ALAPH +0712..072F ; N # Lo [30] SYRIAC LETTER BETH..SYRIAC LETTER PERSIAN DHALATH +0730..074A ; N # Mn [27] SYRIAC PTHAHA ABOVE..SYRIAC BARREKH +074D..074F ; N # Lo [3] SYRIAC LETTER SOGDIAN ZHAIN..SYRIAC LETTER SOGDIAN FE +0750..077F ; N # Lo [48] ARABIC LETTER BEH WITH THREE DOTS HORIZONTALLY BELOW..ARABIC LETTER KAF WITH TWO DOTS ABOVE +0780..07A5 ; N # Lo [38] THAANA LETTER HAA..THAANA LETTER WAAVU +07A6..07B0 ; N # Mn [11] THAANA ABAFILI..THAANA SUKUN +07B1 ; N # Lo THAANA LETTER NAA +07C0..07C9 ; N # Nd [10] NKO DIGIT ZERO..NKO DIGIT NINE +07CA..07EA ; N # Lo [33] NKO LETTER A..NKO LETTER JONA RA +07EB..07F3 ; N # Mn [9] NKO COMBINING SHORT HIGH TONE..NKO COMBINING DOUBLE DOT ABOVE +07F4..07F5 ; N # Lm [2] NKO HIGH TONE APOSTROPHE..NKO LOW TONE APOSTROPHE +07F6 ; N # So NKO SYMBOL OO DENNEN +07F7..07F9 ; N # Po [3] NKO SYMBOL GBAKURUNEN..NKO EXCLAMATION MARK +07FA ; N # Lm NKO LAJANYALAN +07FD ; N # Mn NKO DANTAYALAN +07FE..07FF ; N # Sc [2] NKO DOROME SIGN..NKO TAMAN SIGN +0800..0815 ; N # Lo [22] SAMARITAN LETTER ALAF..SAMARITAN LETTER TAAF +0816..0819 ; N # Mn [4] SAMARITAN MARK IN..SAMARITAN MARK DAGESH +081A ; N # Lm SAMARITAN MODIFIER LETTER EPENTHETIC YUT +081B..0823 ; N # Mn [9] SAMARITAN MARK EPENTHETIC YUT..SAMARITAN VOWEL SIGN A +0824 ; N # Lm SAMARITAN MODIFIER LETTER SHORT A +0825..0827 ; N # Mn [3] SAMARITAN VOWEL SIGN SHORT A..SAMARITAN VOWEL SIGN U +0828 ; N # Lm SAMARITAN MODIFIER LETTER I +0829..082D ; N # Mn [5] SAMARITAN VOWEL SIGN LONG I..SAMARITAN MARK NEQUDAA +0830..083E ; N # Po [15] SAMARITAN PUNCTUATION NEQUDAA..SAMARITAN PUNCTUATION ANNAAU +0840..0858 ; N # Lo [25] MANDAIC LETTER HALQA..MANDAIC LETTER AIN +0859..085B ; N # Mn [3] MANDAIC AFFRICATION MARK..MANDAIC GEMINATION MARK +085E ; N # Po MANDAIC PUNCTUATION +0860..086A ; N # Lo [11] SYRIAC LETTER MALAYALAM NGA..SYRIAC LETTER MALAYALAM SSA +0870..0887 ; N # Lo [24] ARABIC LETTER ALEF WITH ATTACHED FATHA..ARABIC BASELINE ROUND DOT +0888 ; N # Sk ARABIC RAISED ROUND DOT +0889..088E ; N # Lo [6] ARABIC LETTER NOON WITH INVERTED SMALL V..ARABIC VERTICAL TAIL +0890..0891 ; N # Cf [2] ARABIC POUND MARK ABOVE..ARABIC PIASTRE MARK ABOVE +0898..089F ; N # Mn [8] ARABIC SMALL HIGH WORD AL-JUZ..ARABIC HALF MADDA OVER MADDA +08A0..08C8 ; N # Lo [41] ARABIC LETTER BEH WITH SMALL V BELOW..ARABIC LETTER GRAF +08C9 ; N # Lm ARABIC SMALL FARSI YEH +08CA..08E1 ; N # Mn [24] ARABIC SMALL HIGH FARSI YEH..ARABIC SMALL HIGH SIGN SAFHA +08E2 ; N # Cf ARABIC DISPUTED END OF AYAH +08E3..08FF ; N # Mn [29] ARABIC TURNED DAMMA BELOW..ARABIC MARK SIDEWAYS NOON GHUNNA +0900..0902 ; N # Mn [3] DEVANAGARI SIGN INVERTED CANDRABINDU..DEVANAGARI SIGN ANUSVARA +0903 ; N # Mc DEVANAGARI SIGN VISARGA +0904..0939 ; N # Lo [54] DEVANAGARI LETTER SHORT A..DEVANAGARI LETTER HA +093A ; N # Mn DEVANAGARI VOWEL SIGN OE +093B ; N # Mc DEVANAGARI VOWEL SIGN OOE +093C ; N # Mn DEVANAGARI SIGN NUKTA +093D ; N # Lo DEVANAGARI SIGN AVAGRAHA +093E..0940 ; N # Mc [3] DEVANAGARI VOWEL SIGN AA..DEVANAGARI VOWEL SIGN II +0941..0948 ; N # Mn [8] DEVANAGARI VOWEL SIGN U..DEVANAGARI VOWEL SIGN AI +0949..094C ; N # Mc [4] DEVANAGARI VOWEL SIGN CANDRA O..DEVANAGARI VOWEL SIGN AU +094D ; N # Mn DEVANAGARI SIGN VIRAMA +094E..094F ; N # Mc [2] DEVANAGARI VOWEL SIGN PRISHTHAMATRA E..DEVANAGARI VOWEL SIGN AW +0950 ; N # Lo DEVANAGARI OM +0951..0957 ; N # Mn [7] DEVANAGARI STRESS SIGN UDATTA..DEVANAGARI VOWEL SIGN UUE +0958..0961 ; N # Lo [10] DEVANAGARI LETTER QA..DEVANAGARI LETTER VOCALIC LL +0962..0963 ; N # Mn [2] DEVANAGARI VOWEL SIGN VOCALIC L..DEVANAGARI VOWEL SIGN VOCALIC LL +0964..0965 ; N # Po [2] DEVANAGARI DANDA..DEVANAGARI DOUBLE DANDA +0966..096F ; N # Nd [10] DEVANAGARI DIGIT ZERO..DEVANAGARI DIGIT NINE +0970 ; N # Po DEVANAGARI ABBREVIATION SIGN +0971 ; N # Lm DEVANAGARI SIGN HIGH SPACING DOT +0972..097F ; N # Lo [14] DEVANAGARI LETTER CANDRA A..DEVANAGARI LETTER BBA +0980 ; N # Lo BENGALI ANJI +0981 ; N # Mn BENGALI SIGN CANDRABINDU +0982..0983 ; N # Mc [2] BENGALI SIGN ANUSVARA..BENGALI SIGN VISARGA +0985..098C ; N # Lo [8] BENGALI LETTER A..BENGALI LETTER VOCALIC L +098F..0990 ; N # Lo [2] BENGALI LETTER E..BENGALI LETTER AI +0993..09A8 ; N # Lo [22] BENGALI LETTER O..BENGALI LETTER NA +09AA..09B0 ; N # Lo [7] BENGALI LETTER PA..BENGALI LETTER RA +09B2 ; N # Lo BENGALI LETTER LA +09B6..09B9 ; N # Lo [4] BENGALI LETTER SHA..BENGALI LETTER HA +09BC ; N # Mn BENGALI SIGN NUKTA +09BD ; N # Lo BENGALI SIGN AVAGRAHA +09BE..09C0 ; N # Mc [3] BENGALI VOWEL SIGN AA..BENGALI VOWEL SIGN II +09C1..09C4 ; N # Mn [4] BENGALI VOWEL SIGN U..BENGALI VOWEL SIGN VOCALIC RR +09C7..09C8 ; N # Mc [2] BENGALI VOWEL SIGN E..BENGALI VOWEL SIGN AI +09CB..09CC ; N # Mc [2] BENGALI VOWEL SIGN O..BENGALI VOWEL SIGN AU +09CD ; N # Mn BENGALI SIGN VIRAMA +09CE ; N # Lo BENGALI LETTER KHANDA TA +09D7 ; N # Mc BENGALI AU LENGTH MARK +09DC..09DD ; N # Lo [2] BENGALI LETTER RRA..BENGALI LETTER RHA +09DF..09E1 ; N # Lo [3] BENGALI LETTER YYA..BENGALI LETTER VOCALIC LL +09E2..09E3 ; N # Mn [2] BENGALI VOWEL SIGN VOCALIC L..BENGALI VOWEL SIGN VOCALIC LL +09E6..09EF ; N # Nd [10] BENGALI DIGIT ZERO..BENGALI DIGIT NINE +09F0..09F1 ; N # Lo [2] BENGALI LETTER RA WITH MIDDLE DIAGONAL..BENGALI LETTER RA WITH LOWER DIAGONAL +09F2..09F3 ; N # Sc [2] BENGALI RUPEE MARK..BENGALI RUPEE SIGN +09F4..09F9 ; N # No [6] BENGALI CURRENCY NUMERATOR ONE..BENGALI CURRENCY DENOMINATOR SIXTEEN +09FA ; N # So BENGALI ISSHAR +09FB ; N # Sc BENGALI GANDA MARK +09FC ; N # Lo BENGALI LETTER VEDIC ANUSVARA +09FD ; N # Po BENGALI ABBREVIATION SIGN +09FE ; N # Mn BENGALI SANDHI MARK +0A01..0A02 ; N # Mn [2] GURMUKHI SIGN ADAK BINDI..GURMUKHI SIGN BINDI +0A03 ; N # Mc GURMUKHI SIGN VISARGA +0A05..0A0A ; N # Lo [6] GURMUKHI LETTER A..GURMUKHI LETTER UU +0A0F..0A10 ; N # Lo [2] GURMUKHI LETTER EE..GURMUKHI LETTER AI +0A13..0A28 ; N # Lo [22] GURMUKHI LETTER OO..GURMUKHI LETTER NA +0A2A..0A30 ; N # Lo [7] GURMUKHI LETTER PA..GURMUKHI LETTER RA +0A32..0A33 ; N # Lo [2] GURMUKHI LETTER LA..GURMUKHI LETTER LLA +0A35..0A36 ; N # Lo [2] GURMUKHI LETTER VA..GURMUKHI LETTER SHA +0A38..0A39 ; N # Lo [2] GURMUKHI LETTER SA..GURMUKHI LETTER HA +0A3C ; N # Mn GURMUKHI SIGN NUKTA +0A3E..0A40 ; N # Mc [3] GURMUKHI VOWEL SIGN AA..GURMUKHI VOWEL SIGN II +0A41..0A42 ; N # Mn [2] GURMUKHI VOWEL SIGN U..GURMUKHI VOWEL SIGN UU +0A47..0A48 ; N # Mn [2] GURMUKHI VOWEL SIGN EE..GURMUKHI VOWEL SIGN AI +0A4B..0A4D ; N # Mn [3] GURMUKHI VOWEL SIGN OO..GURMUKHI SIGN VIRAMA +0A51 ; N # Mn GURMUKHI SIGN UDAAT +0A59..0A5C ; N # Lo [4] GURMUKHI LETTER KHHA..GURMUKHI LETTER RRA +0A5E ; N # Lo GURMUKHI LETTER FA +0A66..0A6F ; N # Nd [10] GURMUKHI DIGIT ZERO..GURMUKHI DIGIT NINE +0A70..0A71 ; N # Mn [2] GURMUKHI TIPPI..GURMUKHI ADDAK +0A72..0A74 ; N # Lo [3] GURMUKHI IRI..GURMUKHI EK ONKAR +0A75 ; N # Mn GURMUKHI SIGN YAKASH +0A76 ; N # Po GURMUKHI ABBREVIATION SIGN +0A81..0A82 ; N # Mn [2] GUJARATI SIGN CANDRABINDU..GUJARATI SIGN ANUSVARA +0A83 ; N # Mc GUJARATI SIGN VISARGA +0A85..0A8D ; N # Lo [9] GUJARATI LETTER A..GUJARATI VOWEL CANDRA E +0A8F..0A91 ; N # Lo [3] GUJARATI LETTER E..GUJARATI VOWEL CANDRA O +0A93..0AA8 ; N # Lo [22] GUJARATI LETTER O..GUJARATI LETTER NA +0AAA..0AB0 ; N # Lo [7] GUJARATI LETTER PA..GUJARATI LETTER RA +0AB2..0AB3 ; N # Lo [2] GUJARATI LETTER LA..GUJARATI LETTER LLA +0AB5..0AB9 ; N # Lo [5] GUJARATI LETTER VA..GUJARATI LETTER HA +0ABC ; N # Mn GUJARATI SIGN NUKTA +0ABD ; N # Lo GUJARATI SIGN AVAGRAHA +0ABE..0AC0 ; N # Mc [3] GUJARATI VOWEL SIGN AA..GUJARATI VOWEL SIGN II +0AC1..0AC5 ; N # Mn [5] GUJARATI VOWEL SIGN U..GUJARATI VOWEL SIGN CANDRA E +0AC7..0AC8 ; N # Mn [2] GUJARATI VOWEL SIGN E..GUJARATI VOWEL SIGN AI +0AC9 ; N # Mc GUJARATI VOWEL SIGN CANDRA O +0ACB..0ACC ; N # Mc [2] GUJARATI VOWEL SIGN O..GUJARATI VOWEL SIGN AU +0ACD ; N # Mn GUJARATI SIGN VIRAMA +0AD0 ; N # Lo GUJARATI OM +0AE0..0AE1 ; N # Lo [2] GUJARATI LETTER VOCALIC RR..GUJARATI LETTER VOCALIC LL +0AE2..0AE3 ; N # Mn [2] GUJARATI VOWEL SIGN VOCALIC L..GUJARATI VOWEL SIGN VOCALIC LL +0AE6..0AEF ; N # Nd [10] GUJARATI DIGIT ZERO..GUJARATI DIGIT NINE +0AF0 ; N # Po GUJARATI ABBREVIATION SIGN +0AF1 ; N # Sc GUJARATI RUPEE SIGN +0AF9 ; N # Lo GUJARATI LETTER ZHA +0AFA..0AFF ; N # Mn [6] GUJARATI SIGN SUKUN..GUJARATI SIGN TWO-CIRCLE NUKTA ABOVE +0B01 ; N # Mn ORIYA SIGN CANDRABINDU +0B02..0B03 ; N # Mc [2] ORIYA SIGN ANUSVARA..ORIYA SIGN VISARGA +0B05..0B0C ; N # Lo [8] ORIYA LETTER A..ORIYA LETTER VOCALIC L +0B0F..0B10 ; N # Lo [2] ORIYA LETTER E..ORIYA LETTER AI +0B13..0B28 ; N # Lo [22] ORIYA LETTER O..ORIYA LETTER NA +0B2A..0B30 ; N # Lo [7] ORIYA LETTER PA..ORIYA LETTER RA +0B32..0B33 ; N # Lo [2] ORIYA LETTER LA..ORIYA LETTER LLA +0B35..0B39 ; N # Lo [5] ORIYA LETTER VA..ORIYA LETTER HA +0B3C ; N # Mn ORIYA SIGN NUKTA +0B3D ; N # Lo ORIYA SIGN AVAGRAHA +0B3E ; N # Mc ORIYA VOWEL SIGN AA +0B3F ; N # Mn ORIYA VOWEL SIGN I +0B40 ; N # Mc ORIYA VOWEL SIGN II +0B41..0B44 ; N # Mn [4] ORIYA VOWEL SIGN U..ORIYA VOWEL SIGN VOCALIC RR +0B47..0B48 ; N # Mc [2] ORIYA VOWEL SIGN E..ORIYA VOWEL SIGN AI +0B4B..0B4C ; N # Mc [2] ORIYA VOWEL SIGN O..ORIYA VOWEL SIGN AU +0B4D ; N # Mn ORIYA SIGN VIRAMA +0B55..0B56 ; N # Mn [2] ORIYA SIGN OVERLINE..ORIYA AI LENGTH MARK +0B57 ; N # Mc ORIYA AU LENGTH MARK +0B5C..0B5D ; N # Lo [2] ORIYA LETTER RRA..ORIYA LETTER RHA +0B5F..0B61 ; N # Lo [3] ORIYA LETTER YYA..ORIYA LETTER VOCALIC LL +0B62..0B63 ; N # Mn [2] ORIYA VOWEL SIGN VOCALIC L..ORIYA VOWEL SIGN VOCALIC LL +0B66..0B6F ; N # Nd [10] ORIYA DIGIT ZERO..ORIYA DIGIT NINE +0B70 ; N # So ORIYA ISSHAR +0B71 ; N # Lo ORIYA LETTER WA +0B72..0B77 ; N # No [6] ORIYA FRACTION ONE QUARTER..ORIYA FRACTION THREE SIXTEENTHS +0B82 ; N # Mn TAMIL SIGN ANUSVARA +0B83 ; N # Lo TAMIL SIGN VISARGA +0B85..0B8A ; N # Lo [6] TAMIL LETTER A..TAMIL LETTER UU +0B8E..0B90 ; N # Lo [3] TAMIL LETTER E..TAMIL LETTER AI +0B92..0B95 ; N # Lo [4] TAMIL LETTER O..TAMIL LETTER KA +0B99..0B9A ; N # Lo [2] TAMIL LETTER NGA..TAMIL LETTER CA +0B9C ; N # Lo TAMIL LETTER JA +0B9E..0B9F ; N # Lo [2] TAMIL LETTER NYA..TAMIL LETTER TTA +0BA3..0BA4 ; N # Lo [2] TAMIL LETTER NNA..TAMIL LETTER TA +0BA8..0BAA ; N # Lo [3] TAMIL LETTER NA..TAMIL LETTER PA +0BAE..0BB9 ; N # Lo [12] TAMIL LETTER MA..TAMIL LETTER HA +0BBE..0BBF ; N # Mc [2] TAMIL VOWEL SIGN AA..TAMIL VOWEL SIGN I +0BC0 ; N # Mn TAMIL VOWEL SIGN II +0BC1..0BC2 ; N # Mc [2] TAMIL VOWEL SIGN U..TAMIL VOWEL SIGN UU +0BC6..0BC8 ; N # Mc [3] TAMIL VOWEL SIGN E..TAMIL VOWEL SIGN AI +0BCA..0BCC ; N # Mc [3] TAMIL VOWEL SIGN O..TAMIL VOWEL SIGN AU +0BCD ; N # Mn TAMIL SIGN VIRAMA +0BD0 ; N # Lo TAMIL OM +0BD7 ; N # Mc TAMIL AU LENGTH MARK +0BE6..0BEF ; N # Nd [10] TAMIL DIGIT ZERO..TAMIL DIGIT NINE +0BF0..0BF2 ; N # No [3] TAMIL NUMBER TEN..TAMIL NUMBER ONE THOUSAND +0BF3..0BF8 ; N # So [6] TAMIL DAY SIGN..TAMIL AS ABOVE SIGN +0BF9 ; N # Sc TAMIL RUPEE SIGN +0BFA ; N # So TAMIL NUMBER SIGN +0C00 ; N # Mn TELUGU SIGN COMBINING CANDRABINDU ABOVE +0C01..0C03 ; N # Mc [3] TELUGU SIGN CANDRABINDU..TELUGU SIGN VISARGA +0C04 ; N # Mn TELUGU SIGN COMBINING ANUSVARA ABOVE +0C05..0C0C ; N # Lo [8] TELUGU LETTER A..TELUGU LETTER VOCALIC L +0C0E..0C10 ; N # Lo [3] TELUGU LETTER E..TELUGU LETTER AI +0C12..0C28 ; N # Lo [23] TELUGU LETTER O..TELUGU LETTER NA +0C2A..0C39 ; N # Lo [16] TELUGU LETTER PA..TELUGU LETTER HA +0C3C ; N # Mn TELUGU SIGN NUKTA +0C3D ; N # Lo TELUGU SIGN AVAGRAHA +0C3E..0C40 ; N # Mn [3] TELUGU VOWEL SIGN AA..TELUGU VOWEL SIGN II +0C41..0C44 ; N # Mc [4] TELUGU VOWEL SIGN U..TELUGU VOWEL SIGN VOCALIC RR +0C46..0C48 ; N # Mn [3] TELUGU VOWEL SIGN E..TELUGU VOWEL SIGN AI +0C4A..0C4D ; N # Mn [4] TELUGU VOWEL SIGN O..TELUGU SIGN VIRAMA +0C55..0C56 ; N # Mn [2] TELUGU LENGTH MARK..TELUGU AI LENGTH MARK +0C58..0C5A ; N # Lo [3] TELUGU LETTER TSA..TELUGU LETTER RRRA +0C5D ; N # Lo TELUGU LETTER NAKAARA POLLU +0C60..0C61 ; N # Lo [2] TELUGU LETTER VOCALIC RR..TELUGU LETTER VOCALIC LL +0C62..0C63 ; N # Mn [2] TELUGU VOWEL SIGN VOCALIC L..TELUGU VOWEL SIGN VOCALIC LL +0C66..0C6F ; N # Nd [10] TELUGU DIGIT ZERO..TELUGU DIGIT NINE +0C77 ; N # Po TELUGU SIGN SIDDHAM +0C78..0C7E ; N # No [7] TELUGU FRACTION DIGIT ZERO FOR ODD POWERS OF FOUR..TELUGU FRACTION DIGIT THREE FOR EVEN POWERS OF FOUR +0C7F ; N # So TELUGU SIGN TUUMU +0C80 ; N # Lo KANNADA SIGN SPACING CANDRABINDU +0C81 ; N # Mn KANNADA SIGN CANDRABINDU +0C82..0C83 ; N # Mc [2] KANNADA SIGN ANUSVARA..KANNADA SIGN VISARGA +0C84 ; N # Po KANNADA SIGN SIDDHAM +0C85..0C8C ; N # Lo [8] KANNADA LETTER A..KANNADA LETTER VOCALIC L +0C8E..0C90 ; N # Lo [3] KANNADA LETTER E..KANNADA LETTER AI +0C92..0CA8 ; N # Lo [23] KANNADA LETTER O..KANNADA LETTER NA +0CAA..0CB3 ; N # Lo [10] KANNADA LETTER PA..KANNADA LETTER LLA +0CB5..0CB9 ; N # Lo [5] KANNADA LETTER VA..KANNADA LETTER HA +0CBC ; N # Mn KANNADA SIGN NUKTA +0CBD ; N # Lo KANNADA SIGN AVAGRAHA +0CBE ; N # Mc KANNADA VOWEL SIGN AA +0CBF ; N # Mn KANNADA VOWEL SIGN I +0CC0..0CC4 ; N # Mc [5] KANNADA VOWEL SIGN II..KANNADA VOWEL SIGN VOCALIC RR +0CC6 ; N # Mn KANNADA VOWEL SIGN E +0CC7..0CC8 ; N # Mc [2] KANNADA VOWEL SIGN EE..KANNADA VOWEL SIGN AI +0CCA..0CCB ; N # Mc [2] KANNADA VOWEL SIGN O..KANNADA VOWEL SIGN OO +0CCC..0CCD ; N # Mn [2] KANNADA VOWEL SIGN AU..KANNADA SIGN VIRAMA +0CD5..0CD6 ; N # Mc [2] KANNADA LENGTH MARK..KANNADA AI LENGTH MARK +0CDD..0CDE ; N # Lo [2] KANNADA LETTER NAKAARA POLLU..KANNADA LETTER FA +0CE0..0CE1 ; N # Lo [2] KANNADA LETTER VOCALIC RR..KANNADA LETTER VOCALIC LL +0CE2..0CE3 ; N # Mn [2] KANNADA VOWEL SIGN VOCALIC L..KANNADA VOWEL SIGN VOCALIC LL +0CE6..0CEF ; N # Nd [10] KANNADA DIGIT ZERO..KANNADA DIGIT NINE +0CF1..0CF2 ; N # Lo [2] KANNADA SIGN JIHVAMULIYA..KANNADA SIGN UPADHMANIYA +0CF3 ; N # Mc KANNADA SIGN COMBINING ANUSVARA ABOVE RIGHT +0D00..0D01 ; N # Mn [2] MALAYALAM SIGN COMBINING ANUSVARA ABOVE..MALAYALAM SIGN CANDRABINDU +0D02..0D03 ; N # Mc [2] MALAYALAM SIGN ANUSVARA..MALAYALAM SIGN VISARGA +0D04..0D0C ; N # Lo [9] MALAYALAM LETTER VEDIC ANUSVARA..MALAYALAM LETTER VOCALIC L +0D0E..0D10 ; N # Lo [3] MALAYALAM LETTER E..MALAYALAM LETTER AI +0D12..0D3A ; N # Lo [41] MALAYALAM LETTER O..MALAYALAM LETTER TTTA +0D3B..0D3C ; N # Mn [2] MALAYALAM SIGN VERTICAL BAR VIRAMA..MALAYALAM SIGN CIRCULAR VIRAMA +0D3D ; N # Lo MALAYALAM SIGN AVAGRAHA +0D3E..0D40 ; N # Mc [3] MALAYALAM VOWEL SIGN AA..MALAYALAM VOWEL SIGN II +0D41..0D44 ; N # Mn [4] MALAYALAM VOWEL SIGN U..MALAYALAM VOWEL SIGN VOCALIC RR +0D46..0D48 ; N # Mc [3] MALAYALAM VOWEL SIGN E..MALAYALAM VOWEL SIGN AI +0D4A..0D4C ; N # Mc [3] MALAYALAM VOWEL SIGN O..MALAYALAM VOWEL SIGN AU +0D4D ; N # Mn MALAYALAM SIGN VIRAMA +0D4E ; N # Lo MALAYALAM LETTER DOT REPH +0D4F ; N # So MALAYALAM SIGN PARA +0D54..0D56 ; N # Lo [3] MALAYALAM LETTER CHILLU M..MALAYALAM LETTER CHILLU LLL +0D57 ; N # Mc MALAYALAM AU LENGTH MARK +0D58..0D5E ; N # No [7] MALAYALAM FRACTION ONE ONE-HUNDRED-AND-SIXTIETH..MALAYALAM FRACTION ONE FIFTH +0D5F..0D61 ; N # Lo [3] MALAYALAM LETTER ARCHAIC II..MALAYALAM LETTER VOCALIC LL +0D62..0D63 ; N # Mn [2] MALAYALAM VOWEL SIGN VOCALIC L..MALAYALAM VOWEL SIGN VOCALIC LL +0D66..0D6F ; N # Nd [10] MALAYALAM DIGIT ZERO..MALAYALAM DIGIT NINE +0D70..0D78 ; N # No [9] MALAYALAM NUMBER TEN..MALAYALAM FRACTION THREE SIXTEENTHS +0D79 ; N # So MALAYALAM DATE MARK +0D7A..0D7F ; N # Lo [6] MALAYALAM LETTER CHILLU NN..MALAYALAM LETTER CHILLU K +0D81 ; N # Mn SINHALA SIGN CANDRABINDU +0D82..0D83 ; N # Mc [2] SINHALA SIGN ANUSVARAYA..SINHALA SIGN VISARGAYA +0D85..0D96 ; N # Lo [18] SINHALA LETTER AYANNA..SINHALA LETTER AUYANNA +0D9A..0DB1 ; N # Lo [24] SINHALA LETTER ALPAPRAANA KAYANNA..SINHALA LETTER DANTAJA NAYANNA +0DB3..0DBB ; N # Lo [9] SINHALA LETTER SANYAKA DAYANNA..SINHALA LETTER RAYANNA +0DBD ; N # Lo SINHALA LETTER DANTAJA LAYANNA +0DC0..0DC6 ; N # Lo [7] SINHALA LETTER VAYANNA..SINHALA LETTER FAYANNA +0DCA ; N # Mn SINHALA SIGN AL-LAKUNA +0DCF..0DD1 ; N # Mc [3] SINHALA VOWEL SIGN AELA-PILLA..SINHALA VOWEL SIGN DIGA AEDA-PILLA +0DD2..0DD4 ; N # Mn [3] SINHALA VOWEL SIGN KETTI IS-PILLA..SINHALA VOWEL SIGN KETTI PAA-PILLA +0DD6 ; N # Mn SINHALA VOWEL SIGN DIGA PAA-PILLA +0DD8..0DDF ; N # Mc [8] SINHALA VOWEL SIGN GAETTA-PILLA..SINHALA VOWEL SIGN GAYANUKITTA +0DE6..0DEF ; N # Nd [10] SINHALA LITH DIGIT ZERO..SINHALA LITH DIGIT NINE +0DF2..0DF3 ; N # Mc [2] SINHALA VOWEL SIGN DIGA GAETTA-PILLA..SINHALA VOWEL SIGN DIGA GAYANUKITTA +0DF4 ; N # Po SINHALA PUNCTUATION KUNDDALIYA +0E01..0E30 ; N # Lo [48] THAI CHARACTER KO KAI..THAI CHARACTER SARA A +0E31 ; N # Mn THAI CHARACTER MAI HAN-AKAT +0E32..0E33 ; N # Lo [2] THAI CHARACTER SARA AA..THAI CHARACTER SARA AM +0E34..0E3A ; N # Mn [7] THAI CHARACTER SARA I..THAI CHARACTER PHINTHU +0E3F ; N # Sc THAI CURRENCY SYMBOL BAHT +0E40..0E45 ; N # Lo [6] THAI CHARACTER SARA E..THAI CHARACTER LAKKHANGYAO +0E46 ; N # Lm THAI CHARACTER MAIYAMOK +0E47..0E4E ; N # Mn [8] THAI CHARACTER MAITAIKHU..THAI CHARACTER YAMAKKAN +0E4F ; N # Po THAI CHARACTER FONGMAN +0E50..0E59 ; N # Nd [10] THAI DIGIT ZERO..THAI DIGIT NINE +0E5A..0E5B ; N # Po [2] THAI CHARACTER ANGKHANKHU..THAI CHARACTER KHOMUT +0E81..0E82 ; N # Lo [2] LAO LETTER KO..LAO LETTER KHO SUNG +0E84 ; N # Lo LAO LETTER KHO TAM +0E86..0E8A ; N # Lo [5] LAO LETTER PALI GHA..LAO LETTER SO TAM +0E8C..0EA3 ; N # Lo [24] LAO LETTER PALI JHA..LAO LETTER LO LING +0EA5 ; N # Lo LAO LETTER LO LOOT +0EA7..0EB0 ; N # Lo [10] LAO LETTER WO..LAO VOWEL SIGN A +0EB1 ; N # Mn LAO VOWEL SIGN MAI KAN +0EB2..0EB3 ; N # Lo [2] LAO VOWEL SIGN AA..LAO VOWEL SIGN AM +0EB4..0EBC ; N # Mn [9] LAO VOWEL SIGN I..LAO SEMIVOWEL SIGN LO +0EBD ; N # Lo LAO SEMIVOWEL SIGN NYO +0EC0..0EC4 ; N # Lo [5] LAO VOWEL SIGN E..LAO VOWEL SIGN AI +0EC6 ; N # Lm LAO KO LA +0EC8..0ECE ; N # Mn [7] LAO TONE MAI EK..LAO YAMAKKAN +0ED0..0ED9 ; N # Nd [10] LAO DIGIT ZERO..LAO DIGIT NINE +0EDC..0EDF ; N # Lo [4] LAO HO NO..LAO LETTER KHMU NYO +0F00 ; N # Lo TIBETAN SYLLABLE OM +0F01..0F03 ; N # So [3] TIBETAN MARK GTER YIG MGO TRUNCATED A..TIBETAN MARK GTER YIG MGO -UM GTER TSHEG MA +0F04..0F12 ; N # Po [15] TIBETAN MARK INITIAL YIG MGO MDUN MA..TIBETAN MARK RGYA GRAM SHAD +0F13 ; N # So TIBETAN MARK CARET -DZUD RTAGS ME LONG CAN +0F14 ; N # Po TIBETAN MARK GTER TSHEG +0F15..0F17 ; N # So [3] TIBETAN LOGOTYPE SIGN CHAD RTAGS..TIBETAN ASTROLOGICAL SIGN SGRA GCAN -CHAR RTAGS +0F18..0F19 ; N # Mn [2] TIBETAN ASTROLOGICAL SIGN -KHYUD PA..TIBETAN ASTROLOGICAL SIGN SDONG TSHUGS +0F1A..0F1F ; N # So [6] TIBETAN SIGN RDEL DKAR GCIG..TIBETAN SIGN RDEL DKAR RDEL NAG +0F20..0F29 ; N # Nd [10] TIBETAN DIGIT ZERO..TIBETAN DIGIT NINE +0F2A..0F33 ; N # No [10] TIBETAN DIGIT HALF ONE..TIBETAN DIGIT HALF ZERO +0F34 ; N # So TIBETAN MARK BSDUS RTAGS +0F35 ; N # Mn TIBETAN MARK NGAS BZUNG NYI ZLA +0F36 ; N # So TIBETAN MARK CARET -DZUD RTAGS BZHI MIG CAN +0F37 ; N # Mn TIBETAN MARK NGAS BZUNG SGOR RTAGS +0F38 ; N # So TIBETAN MARK CHE MGO +0F39 ; N # Mn TIBETAN MARK TSA -PHRU +0F3A ; N # Ps TIBETAN MARK GUG RTAGS GYON +0F3B ; N # Pe TIBETAN MARK GUG RTAGS GYAS +0F3C ; N # Ps TIBETAN MARK ANG KHANG GYON +0F3D ; N # Pe TIBETAN MARK ANG KHANG GYAS +0F3E..0F3F ; N # Mc [2] TIBETAN SIGN YAR TSHES..TIBETAN SIGN MAR TSHES +0F40..0F47 ; N # Lo [8] TIBETAN LETTER KA..TIBETAN LETTER JA +0F49..0F6C ; N # Lo [36] TIBETAN LETTER NYA..TIBETAN LETTER RRA +0F71..0F7E ; N # Mn [14] TIBETAN VOWEL SIGN AA..TIBETAN SIGN RJES SU NGA RO +0F7F ; N # Mc TIBETAN SIGN RNAM BCAD +0F80..0F84 ; N # Mn [5] TIBETAN VOWEL SIGN REVERSED I..TIBETAN MARK HALANTA +0F85 ; N # Po TIBETAN MARK PALUTA +0F86..0F87 ; N # Mn [2] TIBETAN SIGN LCI RTAGS..TIBETAN SIGN YANG RTAGS +0F88..0F8C ; N # Lo [5] TIBETAN SIGN LCE TSA CAN..TIBETAN SIGN INVERTED MCHU CAN +0F8D..0F97 ; N # Mn [11] TIBETAN SUBJOINED SIGN LCE TSA CAN..TIBETAN SUBJOINED LETTER JA +0F99..0FBC ; N # Mn [36] TIBETAN SUBJOINED LETTER NYA..TIBETAN SUBJOINED LETTER FIXED-FORM RA +0FBE..0FC5 ; N # So [8] TIBETAN KU RU KHA..TIBETAN SYMBOL RDO RJE +0FC6 ; N # Mn TIBETAN SYMBOL PADMA GDAN +0FC7..0FCC ; N # So [6] TIBETAN SYMBOL RDO RJE RGYA GRAM..TIBETAN SYMBOL NOR BU BZHI -KHYIL +0FCE..0FCF ; N # So [2] TIBETAN SIGN RDEL NAG RDEL DKAR..TIBETAN SIGN RDEL NAG GSUM +0FD0..0FD4 ; N # Po [5] TIBETAN MARK BSKA- SHOG GI MGO RGYAN..TIBETAN MARK CLOSING BRDA RNYING YIG MGO SGAB MA +0FD5..0FD8 ; N # So [4] RIGHT-FACING SVASTI SIGN..LEFT-FACING SVASTI SIGN WITH DOTS +0FD9..0FDA ; N # Po [2] TIBETAN MARK LEADING MCHAN RTAGS..TIBETAN MARK TRAILING MCHAN RTAGS +1000..102A ; N # Lo [43] MYANMAR LETTER KA..MYANMAR LETTER AU +102B..102C ; N # Mc [2] MYANMAR VOWEL SIGN TALL AA..MYANMAR VOWEL SIGN AA +102D..1030 ; N # Mn [4] MYANMAR VOWEL SIGN I..MYANMAR VOWEL SIGN UU +1031 ; N # Mc MYANMAR VOWEL SIGN E +1032..1037 ; N # Mn [6] MYANMAR VOWEL SIGN AI..MYANMAR SIGN DOT BELOW +1038 ; N # Mc MYANMAR SIGN VISARGA +1039..103A ; N # Mn [2] MYANMAR SIGN VIRAMA..MYANMAR SIGN ASAT +103B..103C ; N # Mc [2] MYANMAR CONSONANT SIGN MEDIAL YA..MYANMAR CONSONANT SIGN MEDIAL RA +103D..103E ; N # Mn [2] MYANMAR CONSONANT SIGN MEDIAL WA..MYANMAR CONSONANT SIGN MEDIAL HA +103F ; N # Lo MYANMAR LETTER GREAT SA +1040..1049 ; N # Nd [10] MYANMAR DIGIT ZERO..MYANMAR DIGIT NINE +104A..104F ; N # Po [6] MYANMAR SIGN LITTLE SECTION..MYANMAR SYMBOL GENITIVE +1050..1055 ; N # Lo [6] MYANMAR LETTER SHA..MYANMAR LETTER VOCALIC LL +1056..1057 ; N # Mc [2] MYANMAR VOWEL SIGN VOCALIC R..MYANMAR VOWEL SIGN VOCALIC RR +1058..1059 ; N # Mn [2] MYANMAR VOWEL SIGN VOCALIC L..MYANMAR VOWEL SIGN VOCALIC LL +105A..105D ; N # Lo [4] MYANMAR LETTER MON NGA..MYANMAR LETTER MON BBE +105E..1060 ; N # Mn [3] MYANMAR CONSONANT SIGN MON MEDIAL NA..MYANMAR CONSONANT SIGN MON MEDIAL LA +1061 ; N # Lo MYANMAR LETTER SGAW KAREN SHA +1062..1064 ; N # Mc [3] MYANMAR VOWEL SIGN SGAW KAREN EU..MYANMAR TONE MARK SGAW KAREN KE PHO +1065..1066 ; N # Lo [2] MYANMAR LETTER WESTERN PWO KAREN THA..MYANMAR LETTER WESTERN PWO KAREN PWA +1067..106D ; N # Mc [7] MYANMAR VOWEL SIGN WESTERN PWO KAREN EU..MYANMAR SIGN WESTERN PWO KAREN TONE-5 +106E..1070 ; N # Lo [3] MYANMAR LETTER EASTERN PWO KAREN NNA..MYANMAR LETTER EASTERN PWO KAREN GHWA +1071..1074 ; N # Mn [4] MYANMAR VOWEL SIGN GEBA KAREN I..MYANMAR VOWEL SIGN KAYAH EE +1075..1081 ; N # Lo [13] MYANMAR LETTER SHAN KA..MYANMAR LETTER SHAN HA +1082 ; N # Mn MYANMAR CONSONANT SIGN SHAN MEDIAL WA +1083..1084 ; N # Mc [2] MYANMAR VOWEL SIGN SHAN AA..MYANMAR VOWEL SIGN SHAN E +1085..1086 ; N # Mn [2] MYANMAR VOWEL SIGN SHAN E ABOVE..MYANMAR VOWEL SIGN SHAN FINAL Y +1087..108C ; N # Mc [6] MYANMAR SIGN SHAN TONE-2..MYANMAR SIGN SHAN COUNCIL TONE-3 +108D ; N # Mn MYANMAR SIGN SHAN COUNCIL EMPHATIC TONE +108E ; N # Lo MYANMAR LETTER RUMAI PALAUNG FA +108F ; N # Mc MYANMAR SIGN RUMAI PALAUNG TONE-5 +1090..1099 ; N # Nd [10] MYANMAR SHAN DIGIT ZERO..MYANMAR SHAN DIGIT NINE +109A..109C ; N # Mc [3] MYANMAR SIGN KHAMTI TONE-1..MYANMAR VOWEL SIGN AITON A +109D ; N # Mn MYANMAR VOWEL SIGN AITON AI +109E..109F ; N # So [2] MYANMAR SYMBOL SHAN ONE..MYANMAR SYMBOL SHAN EXCLAMATION +10A0..10C5 ; N # Lu [38] GEORGIAN CAPITAL LETTER AN..GEORGIAN CAPITAL LETTER HOE +10C7 ; N # Lu GEORGIAN CAPITAL LETTER YN +10CD ; N # Lu GEORGIAN CAPITAL LETTER AEN +10D0..10FA ; N # Ll [43] GEORGIAN LETTER AN..GEORGIAN LETTER AIN +10FB ; N # Po GEORGIAN PARAGRAPH SEPARATOR +10FC ; N # Lm MODIFIER LETTER GEORGIAN NAR +10FD..10FF ; N # Ll [3] GEORGIAN LETTER AEN..GEORGIAN LETTER LABIAL SIGN +1100..115F ; W # Lo [96] HANGUL CHOSEONG KIYEOK..HANGUL CHOSEONG FILLER +1160..11FF ; N # Lo [160] HANGUL JUNGSEONG FILLER..HANGUL JONGSEONG SSANGNIEUN +1200..1248 ; N # Lo [73] ETHIOPIC SYLLABLE HA..ETHIOPIC SYLLABLE QWA +124A..124D ; N # Lo [4] ETHIOPIC SYLLABLE QWI..ETHIOPIC SYLLABLE QWE +1250..1256 ; N # Lo [7] ETHIOPIC SYLLABLE QHA..ETHIOPIC SYLLABLE QHO +1258 ; N # Lo ETHIOPIC SYLLABLE QHWA +125A..125D ; N # Lo [4] ETHIOPIC SYLLABLE QHWI..ETHIOPIC SYLLABLE QHWE +1260..1288 ; N # Lo [41] ETHIOPIC SYLLABLE BA..ETHIOPIC SYLLABLE XWA +128A..128D ; N # Lo [4] ETHIOPIC SYLLABLE XWI..ETHIOPIC SYLLABLE XWE +1290..12B0 ; N # Lo [33] ETHIOPIC SYLLABLE NA..ETHIOPIC SYLLABLE KWA +12B2..12B5 ; N # Lo [4] ETHIOPIC SYLLABLE KWI..ETHIOPIC SYLLABLE KWE +12B8..12BE ; N # Lo [7] ETHIOPIC SYLLABLE KXA..ETHIOPIC SYLLABLE KXO +12C0 ; N # Lo ETHIOPIC SYLLABLE KXWA +12C2..12C5 ; N # Lo [4] ETHIOPIC SYLLABLE KXWI..ETHIOPIC SYLLABLE KXWE +12C8..12D6 ; N # Lo [15] ETHIOPIC SYLLABLE WA..ETHIOPIC SYLLABLE PHARYNGEAL O +12D8..1310 ; N # Lo [57] ETHIOPIC SYLLABLE ZA..ETHIOPIC SYLLABLE GWA +1312..1315 ; N # Lo [4] ETHIOPIC SYLLABLE GWI..ETHIOPIC SYLLABLE GWE +1318..135A ; N # Lo [67] ETHIOPIC SYLLABLE GGA..ETHIOPIC SYLLABLE FYA +135D..135F ; N # Mn [3] ETHIOPIC COMBINING GEMINATION AND VOWEL LENGTH MARK..ETHIOPIC COMBINING GEMINATION MARK +1360..1368 ; N # Po [9] ETHIOPIC SECTION MARK..ETHIOPIC PARAGRAPH SEPARATOR +1369..137C ; N # No [20] ETHIOPIC DIGIT ONE..ETHIOPIC NUMBER TEN THOUSAND +1380..138F ; N # Lo [16] ETHIOPIC SYLLABLE SEBATBEIT MWA..ETHIOPIC SYLLABLE PWE +1390..1399 ; N # So [10] ETHIOPIC TONAL MARK YIZET..ETHIOPIC TONAL MARK KURT +13A0..13F5 ; N # Lu [86] CHEROKEE LETTER A..CHEROKEE LETTER MV +13F8..13FD ; N # Ll [6] CHEROKEE SMALL LETTER YE..CHEROKEE SMALL LETTER MV +1400 ; N # Pd CANADIAN SYLLABICS HYPHEN +1401..166C ; N # Lo [620] CANADIAN SYLLABICS E..CANADIAN SYLLABICS CARRIER TTSA +166D ; N # So CANADIAN SYLLABICS CHI SIGN +166E ; N # Po CANADIAN SYLLABICS FULL STOP +166F..167F ; N # Lo [17] CANADIAN SYLLABICS QAI..CANADIAN SYLLABICS BLACKFOOT W +1680 ; N # Zs OGHAM SPACE MARK +1681..169A ; N # Lo [26] OGHAM LETTER BEITH..OGHAM LETTER PEITH +169B ; N # Ps OGHAM FEATHER MARK +169C ; N # Pe OGHAM REVERSED FEATHER MARK +16A0..16EA ; N # Lo [75] RUNIC LETTER FEHU FEOH FE F..RUNIC LETTER X +16EB..16ED ; N # Po [3] RUNIC SINGLE PUNCTUATION..RUNIC CROSS PUNCTUATION +16EE..16F0 ; N # Nl [3] RUNIC ARLAUG SYMBOL..RUNIC BELGTHOR SYMBOL +16F1..16F8 ; N # Lo [8] RUNIC LETTER K..RUNIC LETTER FRANKS CASKET AESC +1700..1711 ; N # Lo [18] TAGALOG LETTER A..TAGALOG LETTER HA +1712..1714 ; N # Mn [3] TAGALOG VOWEL SIGN I..TAGALOG SIGN VIRAMA +1715 ; N # Mc TAGALOG SIGN PAMUDPOD +171F ; N # Lo TAGALOG LETTER ARCHAIC RA +1720..1731 ; N # Lo [18] HANUNOO LETTER A..HANUNOO LETTER HA +1732..1733 ; N # Mn [2] HANUNOO VOWEL SIGN I..HANUNOO VOWEL SIGN U +1734 ; N # Mc HANUNOO SIGN PAMUDPOD +1735..1736 ; N # Po [2] PHILIPPINE SINGLE PUNCTUATION..PHILIPPINE DOUBLE PUNCTUATION +1740..1751 ; N # Lo [18] BUHID LETTER A..BUHID LETTER HA +1752..1753 ; N # Mn [2] BUHID VOWEL SIGN I..BUHID VOWEL SIGN U +1760..176C ; N # Lo [13] TAGBANWA LETTER A..TAGBANWA LETTER YA +176E..1770 ; N # Lo [3] TAGBANWA LETTER LA..TAGBANWA LETTER SA +1772..1773 ; N # Mn [2] TAGBANWA VOWEL SIGN I..TAGBANWA VOWEL SIGN U +1780..17B3 ; N # Lo [52] KHMER LETTER KA..KHMER INDEPENDENT VOWEL QAU +17B4..17B5 ; N # Mn [2] KHMER VOWEL INHERENT AQ..KHMER VOWEL INHERENT AA +17B6 ; N # Mc KHMER VOWEL SIGN AA +17B7..17BD ; N # Mn [7] KHMER VOWEL SIGN I..KHMER VOWEL SIGN UA +17BE..17C5 ; N # Mc [8] KHMER VOWEL SIGN OE..KHMER VOWEL SIGN AU +17C6 ; N # Mn KHMER SIGN NIKAHIT +17C7..17C8 ; N # Mc [2] KHMER SIGN REAHMUK..KHMER SIGN YUUKALEAPINTU +17C9..17D3 ; N # Mn [11] KHMER SIGN MUUSIKATOAN..KHMER SIGN BATHAMASAT +17D4..17D6 ; N # Po [3] KHMER SIGN KHAN..KHMER SIGN CAMNUC PII KUUH +17D7 ; N # Lm KHMER SIGN LEK TOO +17D8..17DA ; N # Po [3] KHMER SIGN BEYYAL..KHMER SIGN KOOMUUT +17DB ; N # Sc KHMER CURRENCY SYMBOL RIEL +17DC ; N # Lo KHMER SIGN AVAKRAHASANYA +17DD ; N # Mn KHMER SIGN ATTHACAN +17E0..17E9 ; N # Nd [10] KHMER DIGIT ZERO..KHMER DIGIT NINE +17F0..17F9 ; N # No [10] KHMER SYMBOL LEK ATTAK SON..KHMER SYMBOL LEK ATTAK PRAM-BUON +1800..1805 ; N # Po [6] MONGOLIAN BIRGA..MONGOLIAN FOUR DOTS +1806 ; N # Pd MONGOLIAN TODO SOFT HYPHEN +1807..180A ; N # Po [4] MONGOLIAN SIBE SYLLABLE BOUNDARY MARKER..MONGOLIAN NIRUGU +180B..180D ; N # Mn [3] MONGOLIAN FREE VARIATION SELECTOR ONE..MONGOLIAN FREE VARIATION SELECTOR THREE +180E ; N # Cf MONGOLIAN VOWEL SEPARATOR +180F ; N # Mn MONGOLIAN FREE VARIATION SELECTOR FOUR +1810..1819 ; N # Nd [10] MONGOLIAN DIGIT ZERO..MONGOLIAN DIGIT NINE +1820..1842 ; N # Lo [35] MONGOLIAN LETTER A..MONGOLIAN LETTER CHI +1843 ; N # Lm MONGOLIAN LETTER TODO LONG VOWEL SIGN +1844..1878 ; N # Lo [53] MONGOLIAN LETTER TODO E..MONGOLIAN LETTER CHA WITH TWO DOTS +1880..1884 ; N # Lo [5] MONGOLIAN LETTER ALI GALI ANUSVARA ONE..MONGOLIAN LETTER ALI GALI INVERTED UBADAMA +1885..1886 ; N # Mn [2] MONGOLIAN LETTER ALI GALI BALUDA..MONGOLIAN LETTER ALI GALI THREE BALUDA +1887..18A8 ; N # Lo [34] MONGOLIAN LETTER ALI GALI A..MONGOLIAN LETTER MANCHU ALI GALI BHA +18A9 ; N # Mn MONGOLIAN LETTER ALI GALI DAGALGA +18AA ; N # Lo MONGOLIAN LETTER MANCHU ALI GALI LHA +18B0..18F5 ; N # Lo [70] CANADIAN SYLLABICS OY..CANADIAN SYLLABICS CARRIER DENTAL S +1900..191E ; N # Lo [31] LIMBU VOWEL-CARRIER LETTER..LIMBU LETTER TRA +1920..1922 ; N # Mn [3] LIMBU VOWEL SIGN A..LIMBU VOWEL SIGN U +1923..1926 ; N # Mc [4] LIMBU VOWEL SIGN EE..LIMBU VOWEL SIGN AU +1927..1928 ; N # Mn [2] LIMBU VOWEL SIGN E..LIMBU VOWEL SIGN O +1929..192B ; N # Mc [3] LIMBU SUBJOINED LETTER YA..LIMBU SUBJOINED LETTER WA +1930..1931 ; N # Mc [2] LIMBU SMALL LETTER KA..LIMBU SMALL LETTER NGA +1932 ; N # Mn LIMBU SMALL LETTER ANUSVARA +1933..1938 ; N # Mc [6] LIMBU SMALL LETTER TA..LIMBU SMALL LETTER LA +1939..193B ; N # Mn [3] LIMBU SIGN MUKPHRENG..LIMBU SIGN SA-I +1940 ; N # So LIMBU SIGN LOO +1944..1945 ; N # Po [2] LIMBU EXCLAMATION MARK..LIMBU QUESTION MARK +1946..194F ; N # Nd [10] LIMBU DIGIT ZERO..LIMBU DIGIT NINE +1950..196D ; N # Lo [30] TAI LE LETTER KA..TAI LE LETTER AI +1970..1974 ; N # Lo [5] TAI LE LETTER TONE-2..TAI LE LETTER TONE-6 +1980..19AB ; N # Lo [44] NEW TAI LUE LETTER HIGH QA..NEW TAI LUE LETTER LOW SUA +19B0..19C9 ; N # Lo [26] NEW TAI LUE VOWEL SIGN VOWEL SHORTENER..NEW TAI LUE TONE MARK-2 +19D0..19D9 ; N # Nd [10] NEW TAI LUE DIGIT ZERO..NEW TAI LUE DIGIT NINE +19DA ; N # No NEW TAI LUE THAM DIGIT ONE +19DE..19DF ; N # So [2] NEW TAI LUE SIGN LAE..NEW TAI LUE SIGN LAEV +19E0..19FF ; N # So [32] KHMER SYMBOL PATHAMASAT..KHMER SYMBOL DAP-PRAM ROC +1A00..1A16 ; N # Lo [23] BUGINESE LETTER KA..BUGINESE LETTER HA +1A17..1A18 ; N # Mn [2] BUGINESE VOWEL SIGN I..BUGINESE VOWEL SIGN U +1A19..1A1A ; N # Mc [2] BUGINESE VOWEL SIGN E..BUGINESE VOWEL SIGN O +1A1B ; N # Mn BUGINESE VOWEL SIGN AE +1A1E..1A1F ; N # Po [2] BUGINESE PALLAWA..BUGINESE END OF SECTION +1A20..1A54 ; N # Lo [53] TAI THAM LETTER HIGH KA..TAI THAM LETTER GREAT SA +1A55 ; N # Mc TAI THAM CONSONANT SIGN MEDIAL RA +1A56 ; N # Mn TAI THAM CONSONANT SIGN MEDIAL LA +1A57 ; N # Mc TAI THAM CONSONANT SIGN LA TANG LAI +1A58..1A5E ; N # Mn [7] TAI THAM SIGN MAI KANG LAI..TAI THAM CONSONANT SIGN SA +1A60 ; N # Mn TAI THAM SIGN SAKOT +1A61 ; N # Mc TAI THAM VOWEL SIGN A +1A62 ; N # Mn TAI THAM VOWEL SIGN MAI SAT +1A63..1A64 ; N # Mc [2] TAI THAM VOWEL SIGN AA..TAI THAM VOWEL SIGN TALL AA +1A65..1A6C ; N # Mn [8] TAI THAM VOWEL SIGN I..TAI THAM VOWEL SIGN OA BELOW +1A6D..1A72 ; N # Mc [6] TAI THAM VOWEL SIGN OY..TAI THAM VOWEL SIGN THAM AI +1A73..1A7C ; N # Mn [10] TAI THAM VOWEL SIGN OA ABOVE..TAI THAM SIGN KHUEN-LUE KARAN +1A7F ; N # Mn TAI THAM COMBINING CRYPTOGRAMMIC DOT +1A80..1A89 ; N # Nd [10] TAI THAM HORA DIGIT ZERO..TAI THAM HORA DIGIT NINE +1A90..1A99 ; N # Nd [10] TAI THAM THAM DIGIT ZERO..TAI THAM THAM DIGIT NINE +1AA0..1AA6 ; N # Po [7] TAI THAM SIGN WIANG..TAI THAM SIGN REVERSED ROTATED RANA +1AA7 ; N # Lm TAI THAM SIGN MAI YAMOK +1AA8..1AAD ; N # Po [6] TAI THAM SIGN KAAN..TAI THAM SIGN CAANG +1AB0..1ABD ; N # Mn [14] COMBINING DOUBLED CIRCUMFLEX ACCENT..COMBINING PARENTHESES BELOW +1ABE ; N # Me COMBINING PARENTHESES OVERLAY +1ABF..1ACE ; N # Mn [16] COMBINING LATIN SMALL LETTER W BELOW..COMBINING LATIN SMALL LETTER INSULAR T +1B00..1B03 ; N # Mn [4] BALINESE SIGN ULU RICEM..BALINESE SIGN SURANG +1B04 ; N # Mc BALINESE SIGN BISAH +1B05..1B33 ; N # Lo [47] BALINESE LETTER AKARA..BALINESE LETTER HA +1B34 ; N # Mn BALINESE SIGN REREKAN +1B35 ; N # Mc BALINESE VOWEL SIGN TEDUNG +1B36..1B3A ; N # Mn [5] BALINESE VOWEL SIGN ULU..BALINESE VOWEL SIGN RA REPA +1B3B ; N # Mc BALINESE VOWEL SIGN RA REPA TEDUNG +1B3C ; N # Mn BALINESE VOWEL SIGN LA LENGA +1B3D..1B41 ; N # Mc [5] BALINESE VOWEL SIGN LA LENGA TEDUNG..BALINESE VOWEL SIGN TALING REPA TEDUNG +1B42 ; N # Mn BALINESE VOWEL SIGN PEPET +1B43..1B44 ; N # Mc [2] BALINESE VOWEL SIGN PEPET TEDUNG..BALINESE ADEG ADEG +1B45..1B4C ; N # Lo [8] BALINESE LETTER KAF SASAK..BALINESE LETTER ARCHAIC JNYA +1B50..1B59 ; N # Nd [10] BALINESE DIGIT ZERO..BALINESE DIGIT NINE +1B5A..1B60 ; N # Po [7] BALINESE PANTI..BALINESE PAMENENG +1B61..1B6A ; N # So [10] BALINESE MUSICAL SYMBOL DONG..BALINESE MUSICAL SYMBOL DANG GEDE +1B6B..1B73 ; N # Mn [9] BALINESE MUSICAL SYMBOL COMBINING TEGEH..BALINESE MUSICAL SYMBOL COMBINING GONG +1B74..1B7C ; N # So [9] BALINESE MUSICAL SYMBOL RIGHT-HAND OPEN DUG..BALINESE MUSICAL SYMBOL LEFT-HAND OPEN PING +1B7D..1B7E ; N # Po [2] BALINESE PANTI LANTANG..BALINESE PAMADA LANTANG +1B80..1B81 ; N # Mn [2] SUNDANESE SIGN PANYECEK..SUNDANESE SIGN PANGLAYAR +1B82 ; N # Mc SUNDANESE SIGN PANGWISAD +1B83..1BA0 ; N # Lo [30] SUNDANESE LETTER A..SUNDANESE LETTER HA +1BA1 ; N # Mc SUNDANESE CONSONANT SIGN PAMINGKAL +1BA2..1BA5 ; N # Mn [4] SUNDANESE CONSONANT SIGN PANYAKRA..SUNDANESE VOWEL SIGN PANYUKU +1BA6..1BA7 ; N # Mc [2] SUNDANESE VOWEL SIGN PANAELAENG..SUNDANESE VOWEL SIGN PANOLONG +1BA8..1BA9 ; N # Mn [2] SUNDANESE VOWEL SIGN PAMEPET..SUNDANESE VOWEL SIGN PANEULEUNG +1BAA ; N # Mc SUNDANESE SIGN PAMAAEH +1BAB..1BAD ; N # Mn [3] SUNDANESE SIGN VIRAMA..SUNDANESE CONSONANT SIGN PASANGAN WA +1BAE..1BAF ; N # Lo [2] SUNDANESE LETTER KHA..SUNDANESE LETTER SYA +1BB0..1BB9 ; N # Nd [10] SUNDANESE DIGIT ZERO..SUNDANESE DIGIT NINE +1BBA..1BBF ; N # Lo [6] SUNDANESE AVAGRAHA..SUNDANESE LETTER FINAL M +1BC0..1BE5 ; N # Lo [38] BATAK LETTER A..BATAK LETTER U +1BE6 ; N # Mn BATAK SIGN TOMPI +1BE7 ; N # Mc BATAK VOWEL SIGN E +1BE8..1BE9 ; N # Mn [2] BATAK VOWEL SIGN PAKPAK E..BATAK VOWEL SIGN EE +1BEA..1BEC ; N # Mc [3] BATAK VOWEL SIGN I..BATAK VOWEL SIGN O +1BED ; N # Mn BATAK VOWEL SIGN KARO O +1BEE ; N # Mc BATAK VOWEL SIGN U +1BEF..1BF1 ; N # Mn [3] BATAK VOWEL SIGN U FOR SIMALUNGUN SA..BATAK CONSONANT SIGN H +1BF2..1BF3 ; N # Mc [2] BATAK PANGOLAT..BATAK PANONGONAN +1BFC..1BFF ; N # Po [4] BATAK SYMBOL BINDU NA METEK..BATAK SYMBOL BINDU PANGOLAT +1C00..1C23 ; N # Lo [36] LEPCHA LETTER KA..LEPCHA LETTER A +1C24..1C2B ; N # Mc [8] LEPCHA SUBJOINED LETTER YA..LEPCHA VOWEL SIGN UU +1C2C..1C33 ; N # Mn [8] LEPCHA VOWEL SIGN E..LEPCHA CONSONANT SIGN T +1C34..1C35 ; N # Mc [2] LEPCHA CONSONANT SIGN NYIN-DO..LEPCHA CONSONANT SIGN KANG +1C36..1C37 ; N # Mn [2] LEPCHA SIGN RAN..LEPCHA SIGN NUKTA +1C3B..1C3F ; N # Po [5] LEPCHA PUNCTUATION TA-ROL..LEPCHA PUNCTUATION TSHOOK +1C40..1C49 ; N # Nd [10] LEPCHA DIGIT ZERO..LEPCHA DIGIT NINE +1C4D..1C4F ; N # Lo [3] LEPCHA LETTER TTA..LEPCHA LETTER DDA +1C50..1C59 ; N # Nd [10] OL CHIKI DIGIT ZERO..OL CHIKI DIGIT NINE +1C5A..1C77 ; N # Lo [30] OL CHIKI LETTER LA..OL CHIKI LETTER OH +1C78..1C7D ; N # Lm [6] OL CHIKI MU TTUDDAG..OL CHIKI AHAD +1C7E..1C7F ; N # Po [2] OL CHIKI PUNCTUATION MUCAAD..OL CHIKI PUNCTUATION DOUBLE MUCAAD +1C80..1C88 ; N # Ll [9] CYRILLIC SMALL LETTER ROUNDED VE..CYRILLIC SMALL LETTER UNBLENDED UK +1C90..1CBA ; N # Lu [43] GEORGIAN MTAVRULI CAPITAL LETTER AN..GEORGIAN MTAVRULI CAPITAL LETTER AIN +1CBD..1CBF ; N # Lu [3] GEORGIAN MTAVRULI CAPITAL LETTER AEN..GEORGIAN MTAVRULI CAPITAL LETTER LABIAL SIGN +1CC0..1CC7 ; N # Po [8] SUNDANESE PUNCTUATION BINDU SURYA..SUNDANESE PUNCTUATION BINDU BA SATANGA +1CD0..1CD2 ; N # Mn [3] VEDIC TONE KARSHANA..VEDIC TONE PRENKHA +1CD3 ; N # Po VEDIC SIGN NIHSHVASA +1CD4..1CE0 ; N # Mn [13] VEDIC SIGN YAJURVEDIC MIDLINE SVARITA..VEDIC TONE RIGVEDIC KASHMIRI INDEPENDENT SVARITA +1CE1 ; N # Mc VEDIC TONE ATHARVAVEDIC INDEPENDENT SVARITA +1CE2..1CE8 ; N # Mn [7] VEDIC SIGN VISARGA SVARITA..VEDIC SIGN VISARGA ANUDATTA WITH TAIL +1CE9..1CEC ; N # Lo [4] VEDIC SIGN ANUSVARA ANTARGOMUKHA..VEDIC SIGN ANUSVARA VAMAGOMUKHA WITH TAIL +1CED ; N # Mn VEDIC SIGN TIRYAK +1CEE..1CF3 ; N # Lo [6] VEDIC SIGN HEXIFORM LONG ANUSVARA..VEDIC SIGN ROTATED ARDHAVISARGA +1CF4 ; N # Mn VEDIC TONE CANDRA ABOVE +1CF5..1CF6 ; N # Lo [2] VEDIC SIGN JIHVAMULIYA..VEDIC SIGN UPADHMANIYA +1CF7 ; N # Mc VEDIC SIGN ATIKRAMA +1CF8..1CF9 ; N # Mn [2] VEDIC TONE RING ABOVE..VEDIC TONE DOUBLE RING ABOVE +1CFA ; N # Lo VEDIC SIGN DOUBLE ANUSVARA ANTARGOMUKHA +1D00..1D2B ; N # Ll [44] LATIN LETTER SMALL CAPITAL A..CYRILLIC LETTER SMALL CAPITAL EL +1D2C..1D6A ; N # Lm [63] MODIFIER LETTER CAPITAL A..GREEK SUBSCRIPT SMALL LETTER CHI +1D6B..1D77 ; N # Ll [13] LATIN SMALL LETTER UE..LATIN SMALL LETTER TURNED G +1D78 ; N # Lm MODIFIER LETTER CYRILLIC EN +1D79..1D7F ; N # Ll [7] LATIN SMALL LETTER INSULAR G..LATIN SMALL LETTER UPSILON WITH STROKE +1D80..1D9A ; N # Ll [27] LATIN SMALL LETTER B WITH PALATAL HOOK..LATIN SMALL LETTER EZH WITH RETROFLEX HOOK +1D9B..1DBF ; N # Lm [37] MODIFIER LETTER SMALL TURNED ALPHA..MODIFIER LETTER SMALL THETA +1DC0..1DFF ; N # Mn [64] COMBINING DOTTED GRAVE ACCENT..COMBINING RIGHT ARROWHEAD AND DOWN ARROWHEAD BELOW +1E00..1EFF ; N # L& [256] LATIN CAPITAL LETTER A WITH RING BELOW..LATIN SMALL LETTER Y WITH LOOP +1F00..1F15 ; N # L& [22] GREEK SMALL LETTER ALPHA WITH PSILI..GREEK SMALL LETTER EPSILON WITH DASIA AND OXIA +1F18..1F1D ; N # Lu [6] GREEK CAPITAL LETTER EPSILON WITH PSILI..GREEK CAPITAL LETTER EPSILON WITH DASIA AND OXIA +1F20..1F45 ; N # L& [38] GREEK SMALL LETTER ETA WITH PSILI..GREEK SMALL LETTER OMICRON WITH DASIA AND OXIA +1F48..1F4D ; N # Lu [6] GREEK CAPITAL LETTER OMICRON WITH PSILI..GREEK CAPITAL LETTER OMICRON WITH DASIA AND OXIA +1F50..1F57 ; N # Ll [8] GREEK SMALL LETTER UPSILON WITH PSILI..GREEK SMALL LETTER UPSILON WITH DASIA AND PERISPOMENI +1F59 ; N # Lu GREEK CAPITAL LETTER UPSILON WITH DASIA +1F5B ; N # Lu GREEK CAPITAL LETTER UPSILON WITH DASIA AND VARIA +1F5D ; N # Lu GREEK CAPITAL LETTER UPSILON WITH DASIA AND OXIA +1F5F..1F7D ; N # L& [31] GREEK CAPITAL LETTER UPSILON WITH DASIA AND PERISPOMENI..GREEK SMALL LETTER OMEGA WITH OXIA +1F80..1FB4 ; N # L& [53] GREEK SMALL LETTER ALPHA WITH PSILI AND YPOGEGRAMMENI..GREEK SMALL LETTER ALPHA WITH OXIA AND YPOGEGRAMMENI +1FB6..1FBC ; N # L& [7] GREEK SMALL LETTER ALPHA WITH PERISPOMENI..GREEK CAPITAL LETTER ALPHA WITH PROSGEGRAMMENI +1FBD ; N # Sk GREEK KORONIS +1FBE ; N # Ll GREEK PROSGEGRAMMENI +1FBF..1FC1 ; N # Sk [3] GREEK PSILI..GREEK DIALYTIKA AND PERISPOMENI +1FC2..1FC4 ; N # Ll [3] GREEK SMALL LETTER ETA WITH VARIA AND YPOGEGRAMMENI..GREEK SMALL LETTER ETA WITH OXIA AND YPOGEGRAMMENI +1FC6..1FCC ; N # L& [7] GREEK SMALL LETTER ETA WITH PERISPOMENI..GREEK CAPITAL LETTER ETA WITH PROSGEGRAMMENI +1FCD..1FCF ; N # Sk [3] GREEK PSILI AND VARIA..GREEK PSILI AND PERISPOMENI +1FD0..1FD3 ; N # Ll [4] GREEK SMALL LETTER IOTA WITH VRACHY..GREEK SMALL LETTER IOTA WITH DIALYTIKA AND OXIA +1FD6..1FDB ; N # L& [6] GREEK SMALL LETTER IOTA WITH PERISPOMENI..GREEK CAPITAL LETTER IOTA WITH OXIA +1FDD..1FDF ; N # Sk [3] GREEK DASIA AND VARIA..GREEK DASIA AND PERISPOMENI +1FE0..1FEC ; N # L& [13] GREEK SMALL LETTER UPSILON WITH VRACHY..GREEK CAPITAL LETTER RHO WITH DASIA +1FED..1FEF ; N # Sk [3] GREEK DIALYTIKA AND VARIA..GREEK VARIA +1FF2..1FF4 ; N # Ll [3] GREEK SMALL LETTER OMEGA WITH VARIA AND YPOGEGRAMMENI..GREEK SMALL LETTER OMEGA WITH OXIA AND YPOGEGRAMMENI +1FF6..1FFC ; N # L& [7] GREEK SMALL LETTER OMEGA WITH PERISPOMENI..GREEK CAPITAL LETTER OMEGA WITH PROSGEGRAMMENI +1FFD..1FFE ; N # Sk [2] GREEK OXIA..GREEK DASIA +2000..200A ; N # Zs [11] EN QUAD..HAIR SPACE +200B..200F ; N # Cf [5] ZERO WIDTH SPACE..RIGHT-TO-LEFT MARK +2010 ; A # Pd HYPHEN +2011..2012 ; N # Pd [2] NON-BREAKING HYPHEN..FIGURE DASH +2013..2015 ; A # Pd [3] EN DASH..HORIZONTAL BAR +2016 ; A # Po DOUBLE VERTICAL LINE +2017 ; N # Po DOUBLE LOW LINE +2018 ; A # Pi LEFT SINGLE QUOTATION MARK +2019 ; A # Pf RIGHT SINGLE QUOTATION MARK +201A ; N # Ps SINGLE LOW-9 QUOTATION MARK +201B ; N # Pi SINGLE HIGH-REVERSED-9 QUOTATION MARK +201C ; A # Pi LEFT DOUBLE QUOTATION MARK +201D ; A # Pf RIGHT DOUBLE QUOTATION MARK +201E ; N # Ps DOUBLE LOW-9 QUOTATION MARK +201F ; N # Pi DOUBLE HIGH-REVERSED-9 QUOTATION MARK +2020..2022 ; A # Po [3] DAGGER..BULLET +2023 ; N # Po TRIANGULAR BULLET +2024..2027 ; A # Po [4] ONE DOT LEADER..HYPHENATION POINT +2028 ; N # Zl LINE SEPARATOR +2029 ; N # Zp PARAGRAPH SEPARATOR +202A..202E ; N # Cf [5] LEFT-TO-RIGHT EMBEDDING..RIGHT-TO-LEFT OVERRIDE +202F ; N # Zs NARROW NO-BREAK SPACE +2030 ; A # Po PER MILLE SIGN +2031 ; N # Po PER TEN THOUSAND SIGN +2032..2033 ; A # Po [2] PRIME..DOUBLE PRIME +2034 ; N # Po TRIPLE PRIME +2035 ; A # Po REVERSED PRIME +2036..2038 ; N # Po [3] REVERSED DOUBLE PRIME..CARET +2039 ; N # Pi SINGLE LEFT-POINTING ANGLE QUOTATION MARK +203A ; N # Pf SINGLE RIGHT-POINTING ANGLE QUOTATION MARK +203B ; A # Po REFERENCE MARK +203C..203D ; N # Po [2] DOUBLE EXCLAMATION MARK..INTERROBANG +203E ; A # Po OVERLINE +203F..2040 ; N # Pc [2] UNDERTIE..CHARACTER TIE +2041..2043 ; N # Po [3] CARET INSERTION POINT..HYPHEN BULLET +2044 ; N # Sm FRACTION SLASH +2045 ; N # Ps LEFT SQUARE BRACKET WITH QUILL +2046 ; N # Pe RIGHT SQUARE BRACKET WITH QUILL +2047..2051 ; N # Po [11] DOUBLE QUESTION MARK..TWO ASTERISKS ALIGNED VERTICALLY +2052 ; N # Sm COMMERCIAL MINUS SIGN +2053 ; N # Po SWUNG DASH +2054 ; N # Pc INVERTED UNDERTIE +2055..205E ; N # Po [10] FLOWER PUNCTUATION MARK..VERTICAL FOUR DOTS +205F ; N # Zs MEDIUM MATHEMATICAL SPACE +2060..2064 ; N # Cf [5] WORD JOINER..INVISIBLE PLUS +2066..206F ; N # Cf [10] LEFT-TO-RIGHT ISOLATE..NOMINAL DIGIT SHAPES +2070 ; N # No SUPERSCRIPT ZERO +2071 ; N # Lm SUPERSCRIPT LATIN SMALL LETTER I +2074 ; A # No SUPERSCRIPT FOUR +2075..2079 ; N # No [5] SUPERSCRIPT FIVE..SUPERSCRIPT NINE +207A..207C ; N # Sm [3] SUPERSCRIPT PLUS SIGN..SUPERSCRIPT EQUALS SIGN +207D ; N # Ps SUPERSCRIPT LEFT PARENTHESIS +207E ; N # Pe SUPERSCRIPT RIGHT PARENTHESIS +207F ; A # Lm SUPERSCRIPT LATIN SMALL LETTER N +2080 ; N # No SUBSCRIPT ZERO +2081..2084 ; A # No [4] SUBSCRIPT ONE..SUBSCRIPT FOUR +2085..2089 ; N # No [5] SUBSCRIPT FIVE..SUBSCRIPT NINE +208A..208C ; N # Sm [3] SUBSCRIPT PLUS SIGN..SUBSCRIPT EQUALS SIGN +208D ; N # Ps SUBSCRIPT LEFT PARENTHESIS +208E ; N # Pe SUBSCRIPT RIGHT PARENTHESIS +2090..209C ; N # Lm [13] LATIN SUBSCRIPT SMALL LETTER A..LATIN SUBSCRIPT SMALL LETTER T +20A0..20A8 ; N # Sc [9] EURO-CURRENCY SIGN..RUPEE SIGN +20A9 ; H # Sc WON SIGN +20AA..20AB ; N # Sc [2] NEW SHEQEL SIGN..DONG SIGN +20AC ; A # Sc EURO SIGN +20AD..20C0 ; N # Sc [20] KIP SIGN..SOM SIGN +20D0..20DC ; N # Mn [13] COMBINING LEFT HARPOON ABOVE..COMBINING FOUR DOTS ABOVE +20DD..20E0 ; N # Me [4] COMBINING ENCLOSING CIRCLE..COMBINING ENCLOSING CIRCLE BACKSLASH +20E1 ; N # Mn COMBINING LEFT RIGHT ARROW ABOVE +20E2..20E4 ; N # Me [3] COMBINING ENCLOSING SCREEN..COMBINING ENCLOSING UPWARD POINTING TRIANGLE +20E5..20F0 ; N # Mn [12] COMBINING REVERSE SOLIDUS OVERLAY..COMBINING ASTERISK ABOVE +2100..2101 ; N # So [2] ACCOUNT OF..ADDRESSED TO THE SUBJECT +2102 ; N # Lu DOUBLE-STRUCK CAPITAL C +2103 ; A # So DEGREE CELSIUS +2104 ; N # So CENTRE LINE SYMBOL +2105 ; A # So CARE OF +2106 ; N # So CADA UNA +2107 ; N # Lu EULER CONSTANT +2108 ; N # So SCRUPLE +2109 ; A # So DEGREE FAHRENHEIT +210A..2112 ; N # L& [9] SCRIPT SMALL G..SCRIPT CAPITAL L +2113 ; A # Ll SCRIPT SMALL L +2114 ; N # So L B BAR SYMBOL +2115 ; N # Lu DOUBLE-STRUCK CAPITAL N +2116 ; A # So NUMERO SIGN +2117 ; N # So SOUND RECORDING COPYRIGHT +2118 ; N # Sm SCRIPT CAPITAL P +2119..211D ; N # Lu [5] DOUBLE-STRUCK CAPITAL P..DOUBLE-STRUCK CAPITAL R +211E..2120 ; N # So [3] PRESCRIPTION TAKE..SERVICE MARK +2121..2122 ; A # So [2] TELEPHONE SIGN..TRADE MARK SIGN +2123 ; N # So VERSICLE +2124 ; N # Lu DOUBLE-STRUCK CAPITAL Z +2125 ; N # So OUNCE SIGN +2126 ; A # Lu OHM SIGN +2127 ; N # So INVERTED OHM SIGN +2128 ; N # Lu BLACK-LETTER CAPITAL Z +2129 ; N # So TURNED GREEK SMALL LETTER IOTA +212A ; N # Lu KELVIN SIGN +212B ; A # Lu ANGSTROM SIGN +212C..212D ; N # Lu [2] SCRIPT CAPITAL B..BLACK-LETTER CAPITAL C +212E ; N # So ESTIMATED SYMBOL +212F..2134 ; N # L& [6] SCRIPT SMALL E..SCRIPT SMALL O +2135..2138 ; N # Lo [4] ALEF SYMBOL..DALET SYMBOL +2139 ; N # Ll INFORMATION SOURCE +213A..213B ; N # So [2] ROTATED CAPITAL Q..FACSIMILE SIGN +213C..213F ; N # L& [4] DOUBLE-STRUCK SMALL PI..DOUBLE-STRUCK CAPITAL PI +2140..2144 ; N # Sm [5] DOUBLE-STRUCK N-ARY SUMMATION..TURNED SANS-SERIF CAPITAL Y +2145..2149 ; N # L& [5] DOUBLE-STRUCK ITALIC CAPITAL D..DOUBLE-STRUCK ITALIC SMALL J +214A ; N # So PROPERTY LINE +214B ; N # Sm TURNED AMPERSAND +214C..214D ; N # So [2] PER SIGN..AKTIESELSKAB +214E ; N # Ll TURNED SMALL F +214F ; N # So SYMBOL FOR SAMARITAN SOURCE +2150..2152 ; N # No [3] VULGAR FRACTION ONE SEVENTH..VULGAR FRACTION ONE TENTH +2153..2154 ; A # No [2] VULGAR FRACTION ONE THIRD..VULGAR FRACTION TWO THIRDS +2155..215A ; N # No [6] VULGAR FRACTION ONE FIFTH..VULGAR FRACTION FIVE SIXTHS +215B..215E ; A # No [4] VULGAR FRACTION ONE EIGHTH..VULGAR FRACTION SEVEN EIGHTHS +215F ; N # No FRACTION NUMERATOR ONE +2160..216B ; A # Nl [12] ROMAN NUMERAL ONE..ROMAN NUMERAL TWELVE +216C..216F ; N # Nl [4] ROMAN NUMERAL FIFTY..ROMAN NUMERAL ONE THOUSAND +2170..2179 ; A # Nl [10] SMALL ROMAN NUMERAL ONE..SMALL ROMAN NUMERAL TEN +217A..2182 ; N # Nl [9] SMALL ROMAN NUMERAL ELEVEN..ROMAN NUMERAL TEN THOUSAND +2183..2184 ; N # L& [2] ROMAN NUMERAL REVERSED ONE HUNDRED..LATIN SMALL LETTER REVERSED C +2185..2188 ; N # Nl [4] ROMAN NUMERAL SIX LATE FORM..ROMAN NUMERAL ONE HUNDRED THOUSAND +2189 ; A # No VULGAR FRACTION ZERO THIRDS +218A..218B ; N # So [2] TURNED DIGIT TWO..TURNED DIGIT THREE +2190..2194 ; A # Sm [5] LEFTWARDS ARROW..LEFT RIGHT ARROW +2195..2199 ; A # So [5] UP DOWN ARROW..SOUTH WEST ARROW +219A..219B ; N # Sm [2] LEFTWARDS ARROW WITH STROKE..RIGHTWARDS ARROW WITH STROKE +219C..219F ; N # So [4] LEFTWARDS WAVE ARROW..UPWARDS TWO HEADED ARROW +21A0 ; N # Sm RIGHTWARDS TWO HEADED ARROW +21A1..21A2 ; N # So [2] DOWNWARDS TWO HEADED ARROW..LEFTWARDS ARROW WITH TAIL +21A3 ; N # Sm RIGHTWARDS ARROW WITH TAIL +21A4..21A5 ; N # So [2] LEFTWARDS ARROW FROM BAR..UPWARDS ARROW FROM BAR +21A6 ; N # Sm RIGHTWARDS ARROW FROM BAR +21A7..21AD ; N # So [7] DOWNWARDS ARROW FROM BAR..LEFT RIGHT WAVE ARROW +21AE ; N # Sm LEFT RIGHT ARROW WITH STROKE +21AF..21B7 ; N # So [9] DOWNWARDS ZIGZAG ARROW..CLOCKWISE TOP SEMICIRCLE ARROW +21B8..21B9 ; A # So [2] NORTH WEST ARROW TO LONG BAR..LEFTWARDS ARROW TO BAR OVER RIGHTWARDS ARROW TO BAR +21BA..21CD ; N # So [20] ANTICLOCKWISE OPEN CIRCLE ARROW..LEFTWARDS DOUBLE ARROW WITH STROKE +21CE..21CF ; N # Sm [2] LEFT RIGHT DOUBLE ARROW WITH STROKE..RIGHTWARDS DOUBLE ARROW WITH STROKE +21D0..21D1 ; N # So [2] LEFTWARDS DOUBLE ARROW..UPWARDS DOUBLE ARROW +21D2 ; A # Sm RIGHTWARDS DOUBLE ARROW +21D3 ; N # So DOWNWARDS DOUBLE ARROW +21D4 ; A # Sm LEFT RIGHT DOUBLE ARROW +21D5..21E6 ; N # So [18] UP DOWN DOUBLE ARROW..LEFTWARDS WHITE ARROW +21E7 ; A # So UPWARDS WHITE ARROW +21E8..21F3 ; N # So [12] RIGHTWARDS WHITE ARROW..UP DOWN WHITE ARROW +21F4..21FF ; N # Sm [12] RIGHT ARROW WITH SMALL CIRCLE..LEFT RIGHT OPEN-HEADED ARROW +2200 ; A # Sm FOR ALL +2201 ; N # Sm COMPLEMENT +2202..2203 ; A # Sm [2] PARTIAL DIFFERENTIAL..THERE EXISTS +2204..2206 ; N # Sm [3] THERE DOES NOT EXIST..INCREMENT +2207..2208 ; A # Sm [2] NABLA..ELEMENT OF +2209..220A ; N # Sm [2] NOT AN ELEMENT OF..SMALL ELEMENT OF +220B ; A # Sm CONTAINS AS MEMBER +220C..220E ; N # Sm [3] DOES NOT CONTAIN AS MEMBER..END OF PROOF +220F ; A # Sm N-ARY PRODUCT +2210 ; N # Sm N-ARY COPRODUCT +2211 ; A # Sm N-ARY SUMMATION +2212..2214 ; N # Sm [3] MINUS SIGN..DOT PLUS +2215 ; A # Sm DIVISION SLASH +2216..2219 ; N # Sm [4] SET MINUS..BULLET OPERATOR +221A ; A # Sm SQUARE ROOT +221B..221C ; N # Sm [2] CUBE ROOT..FOURTH ROOT +221D..2220 ; A # Sm [4] PROPORTIONAL TO..ANGLE +2221..2222 ; N # Sm [2] MEASURED ANGLE..SPHERICAL ANGLE +2223 ; A # Sm DIVIDES +2224 ; N # Sm DOES NOT DIVIDE +2225 ; A # Sm PARALLEL TO +2226 ; N # Sm NOT PARALLEL TO +2227..222C ; A # Sm [6] LOGICAL AND..DOUBLE INTEGRAL +222D ; N # Sm TRIPLE INTEGRAL +222E ; A # Sm CONTOUR INTEGRAL +222F..2233 ; N # Sm [5] SURFACE INTEGRAL..ANTICLOCKWISE CONTOUR INTEGRAL +2234..2237 ; A # Sm [4] THEREFORE..PROPORTION +2238..223B ; N # Sm [4] DOT MINUS..HOMOTHETIC +223C..223D ; A # Sm [2] TILDE OPERATOR..REVERSED TILDE +223E..2247 ; N # Sm [10] INVERTED LAZY S..NEITHER APPROXIMATELY NOR ACTUALLY EQUAL TO +2248 ; A # Sm ALMOST EQUAL TO +2249..224B ; N # Sm [3] NOT ALMOST EQUAL TO..TRIPLE TILDE +224C ; A # Sm ALL EQUAL TO +224D..2251 ; N # Sm [5] EQUIVALENT TO..GEOMETRICALLY EQUAL TO +2252 ; A # Sm APPROXIMATELY EQUAL TO OR THE IMAGE OF +2253..225F ; N # Sm [13] IMAGE OF OR APPROXIMATELY EQUAL TO..QUESTIONED EQUAL TO +2260..2261 ; A # Sm [2] NOT EQUAL TO..IDENTICAL TO +2262..2263 ; N # Sm [2] NOT IDENTICAL TO..STRICTLY EQUIVALENT TO +2264..2267 ; A # Sm [4] LESS-THAN OR EQUAL TO..GREATER-THAN OVER EQUAL TO +2268..2269 ; N # Sm [2] LESS-THAN BUT NOT EQUAL TO..GREATER-THAN BUT NOT EQUAL TO +226A..226B ; A # Sm [2] MUCH LESS-THAN..MUCH GREATER-THAN +226C..226D ; N # Sm [2] BETWEEN..NOT EQUIVALENT TO +226E..226F ; A # Sm [2] NOT LESS-THAN..NOT GREATER-THAN +2270..2281 ; N # Sm [18] NEITHER LESS-THAN NOR EQUAL TO..DOES NOT SUCCEED +2282..2283 ; A # Sm [2] SUBSET OF..SUPERSET OF +2284..2285 ; N # Sm [2] NOT A SUBSET OF..NOT A SUPERSET OF +2286..2287 ; A # Sm [2] SUBSET OF OR EQUAL TO..SUPERSET OF OR EQUAL TO +2288..2294 ; N # Sm [13] NEITHER A SUBSET OF NOR EQUAL TO..SQUARE CUP +2295 ; A # Sm CIRCLED PLUS +2296..2298 ; N # Sm [3] CIRCLED MINUS..CIRCLED DIVISION SLASH +2299 ; A # Sm CIRCLED DOT OPERATOR +229A..22A4 ; N # Sm [11] CIRCLED RING OPERATOR..DOWN TACK +22A5 ; A # Sm UP TACK +22A6..22BE ; N # Sm [25] ASSERTION..RIGHT ANGLE WITH ARC +22BF ; A # Sm RIGHT TRIANGLE +22C0..22FF ; N # Sm [64] N-ARY LOGICAL AND..Z NOTATION BAG MEMBERSHIP +2300..2307 ; N # So [8] DIAMETER SIGN..WAVY LINE +2308 ; N # Ps LEFT CEILING +2309 ; N # Pe RIGHT CEILING +230A ; N # Ps LEFT FLOOR +230B ; N # Pe RIGHT FLOOR +230C..2311 ; N # So [6] BOTTOM RIGHT CROP..SQUARE LOZENGE +2312 ; A # So ARC +2313..2319 ; N # So [7] SEGMENT..TURNED NOT SIGN +231A..231B ; W # So [2] WATCH..HOURGLASS +231C..231F ; N # So [4] TOP LEFT CORNER..BOTTOM RIGHT CORNER +2320..2321 ; N # Sm [2] TOP HALF INTEGRAL..BOTTOM HALF INTEGRAL +2322..2328 ; N # So [7] FROWN..KEYBOARD +2329 ; W # Ps LEFT-POINTING ANGLE BRACKET +232A ; W # Pe RIGHT-POINTING ANGLE BRACKET +232B..237B ; N # So [81] ERASE TO THE LEFT..NOT CHECK MARK +237C ; N # Sm RIGHT ANGLE WITH DOWNWARDS ZIGZAG ARROW +237D..239A ; N # So [30] SHOULDERED OPEN BOX..CLEAR SCREEN SYMBOL +239B..23B3 ; N # Sm [25] LEFT PARENTHESIS UPPER HOOK..SUMMATION BOTTOM +23B4..23DB ; N # So [40] TOP SQUARE BRACKET..FUSE +23DC..23E1 ; N # Sm [6] TOP PARENTHESIS..BOTTOM TORTOISE SHELL BRACKET +23E2..23E8 ; N # So [7] WHITE TRAPEZIUM..DECIMAL EXPONENT SYMBOL +23E9..23EC ; W # So [4] BLACK RIGHT-POINTING DOUBLE TRIANGLE..BLACK DOWN-POINTING DOUBLE TRIANGLE +23ED..23EF ; N # So [3] BLACK RIGHT-POINTING DOUBLE TRIANGLE WITH VERTICAL BAR..BLACK RIGHT-POINTING TRIANGLE WITH DOUBLE VERTICAL BAR +23F0 ; W # So ALARM CLOCK +23F1..23F2 ; N # So [2] STOPWATCH..TIMER CLOCK +23F3 ; W # So HOURGLASS WITH FLOWING SAND +23F4..23FF ; N # So [12] BLACK MEDIUM LEFT-POINTING TRIANGLE..OBSERVER EYE SYMBOL +2400..2426 ; N # So [39] SYMBOL FOR NULL..SYMBOL FOR SUBSTITUTE FORM TWO +2440..244A ; N # So [11] OCR HOOK..OCR DOUBLE BACKSLASH +2460..249B ; A # No [60] CIRCLED DIGIT ONE..NUMBER TWENTY FULL STOP +249C..24E9 ; A # So [78] PARENTHESIZED LATIN SMALL LETTER A..CIRCLED LATIN SMALL LETTER Z +24EA ; N # No CIRCLED DIGIT ZERO +24EB..24FF ; A # No [21] NEGATIVE CIRCLED NUMBER ELEVEN..NEGATIVE CIRCLED DIGIT ZERO +2500..254B ; A # So [76] BOX DRAWINGS LIGHT HORIZONTAL..BOX DRAWINGS HEAVY VERTICAL AND HORIZONTAL +254C..254F ; N # So [4] BOX DRAWINGS LIGHT DOUBLE DASH HORIZONTAL..BOX DRAWINGS HEAVY DOUBLE DASH VERTICAL +2550..2573 ; A # So [36] BOX DRAWINGS DOUBLE HORIZONTAL..BOX DRAWINGS LIGHT DIAGONAL CROSS +2574..257F ; N # So [12] BOX DRAWINGS LIGHT LEFT..BOX DRAWINGS HEAVY UP AND LIGHT DOWN +2580..258F ; A # So [16] UPPER HALF BLOCK..LEFT ONE EIGHTH BLOCK +2590..2591 ; N # So [2] RIGHT HALF BLOCK..LIGHT SHADE +2592..2595 ; A # So [4] MEDIUM SHADE..RIGHT ONE EIGHTH BLOCK +2596..259F ; N # So [10] QUADRANT LOWER LEFT..QUADRANT UPPER RIGHT AND LOWER LEFT AND LOWER RIGHT +25A0..25A1 ; A # So [2] BLACK SQUARE..WHITE SQUARE +25A2 ; N # So WHITE SQUARE WITH ROUNDED CORNERS +25A3..25A9 ; A # So [7] WHITE SQUARE CONTAINING BLACK SMALL SQUARE..SQUARE WITH DIAGONAL CROSSHATCH FILL +25AA..25B1 ; N # So [8] BLACK SMALL SQUARE..WHITE PARALLELOGRAM +25B2..25B3 ; A # So [2] BLACK UP-POINTING TRIANGLE..WHITE UP-POINTING TRIANGLE +25B4..25B5 ; N # So [2] BLACK UP-POINTING SMALL TRIANGLE..WHITE UP-POINTING SMALL TRIANGLE +25B6 ; A # So BLACK RIGHT-POINTING TRIANGLE +25B7 ; A # Sm WHITE RIGHT-POINTING TRIANGLE +25B8..25BB ; N # So [4] BLACK RIGHT-POINTING SMALL TRIANGLE..WHITE RIGHT-POINTING POINTER +25BC..25BD ; A # So [2] BLACK DOWN-POINTING TRIANGLE..WHITE DOWN-POINTING TRIANGLE +25BE..25BF ; N # So [2] BLACK DOWN-POINTING SMALL TRIANGLE..WHITE DOWN-POINTING SMALL TRIANGLE +25C0 ; A # So BLACK LEFT-POINTING TRIANGLE +25C1 ; A # Sm WHITE LEFT-POINTING TRIANGLE +25C2..25C5 ; N # So [4] BLACK LEFT-POINTING SMALL TRIANGLE..WHITE LEFT-POINTING POINTER +25C6..25C8 ; A # So [3] BLACK DIAMOND..WHITE DIAMOND CONTAINING BLACK SMALL DIAMOND +25C9..25CA ; N # So [2] FISHEYE..LOZENGE +25CB ; A # So WHITE CIRCLE +25CC..25CD ; N # So [2] DOTTED CIRCLE..CIRCLE WITH VERTICAL FILL +25CE..25D1 ; A # So [4] BULLSEYE..CIRCLE WITH RIGHT HALF BLACK +25D2..25E1 ; N # So [16] CIRCLE WITH LOWER HALF BLACK..LOWER HALF CIRCLE +25E2..25E5 ; A # So [4] BLACK LOWER RIGHT TRIANGLE..BLACK UPPER RIGHT TRIANGLE +25E6..25EE ; N # So [9] WHITE BULLET..UP-POINTING TRIANGLE WITH RIGHT HALF BLACK +25EF ; A # So LARGE CIRCLE +25F0..25F7 ; N # So [8] WHITE SQUARE WITH UPPER LEFT QUADRANT..WHITE CIRCLE WITH UPPER RIGHT QUADRANT +25F8..25FC ; N # Sm [5] UPPER LEFT TRIANGLE..BLACK MEDIUM SQUARE +25FD..25FE ; W # Sm [2] WHITE MEDIUM SMALL SQUARE..BLACK MEDIUM SMALL SQUARE +25FF ; N # Sm LOWER RIGHT TRIANGLE +2600..2604 ; N # So [5] BLACK SUN WITH RAYS..COMET +2605..2606 ; A # So [2] BLACK STAR..WHITE STAR +2607..2608 ; N # So [2] LIGHTNING..THUNDERSTORM +2609 ; A # So SUN +260A..260D ; N # So [4] ASCENDING NODE..OPPOSITION +260E..260F ; A # So [2] BLACK TELEPHONE..WHITE TELEPHONE +2610..2613 ; N # So [4] BALLOT BOX..SALTIRE +2614..2615 ; W # So [2] UMBRELLA WITH RAIN DROPS..HOT BEVERAGE +2616..261B ; N # So [6] WHITE SHOGI PIECE..BLACK RIGHT POINTING INDEX +261C ; A # So WHITE LEFT POINTING INDEX +261D ; N # So WHITE UP POINTING INDEX +261E ; A # So WHITE RIGHT POINTING INDEX +261F..263F ; N # So [33] WHITE DOWN POINTING INDEX..MERCURY +2640 ; A # So FEMALE SIGN +2641 ; N # So EARTH +2642 ; A # So MALE SIGN +2643..2647 ; N # So [5] JUPITER..PLUTO +2648..2653 ; W # So [12] ARIES..PISCES +2654..265F ; N # So [12] WHITE CHESS KING..BLACK CHESS PAWN +2660..2661 ; A # So [2] BLACK SPADE SUIT..WHITE HEART SUIT +2662 ; N # So WHITE DIAMOND SUIT +2663..2665 ; A # So [3] BLACK CLUB SUIT..BLACK HEART SUIT +2666 ; N # So BLACK DIAMOND SUIT +2667..266A ; A # So [4] WHITE CLUB SUIT..EIGHTH NOTE +266B ; N # So BEAMED EIGHTH NOTES +266C..266D ; A # So [2] BEAMED SIXTEENTH NOTES..MUSIC FLAT SIGN +266E ; N # So MUSIC NATURAL SIGN +266F ; A # Sm MUSIC SHARP SIGN +2670..267E ; N # So [15] WEST SYRIAC CROSS..PERMANENT PAPER SIGN +267F ; W # So WHEELCHAIR SYMBOL +2680..2692 ; N # So [19] DIE FACE-1..HAMMER AND PICK +2693 ; W # So ANCHOR +2694..269D ; N # So [10] CROSSED SWORDS..OUTLINED WHITE STAR +269E..269F ; A # So [2] THREE LINES CONVERGING RIGHT..THREE LINES CONVERGING LEFT +26A0 ; N # So WARNING SIGN +26A1 ; W # So HIGH VOLTAGE SIGN +26A2..26A9 ; N # So [8] DOUBLED FEMALE SIGN..HORIZONTAL MALE WITH STROKE SIGN +26AA..26AB ; W # So [2] MEDIUM WHITE CIRCLE..MEDIUM BLACK CIRCLE +26AC..26BC ; N # So [17] MEDIUM SMALL WHITE CIRCLE..SESQUIQUADRATE +26BD..26BE ; W # So [2] SOCCER BALL..BASEBALL +26BF ; A # So SQUARED KEY +26C0..26C3 ; N # So [4] WHITE DRAUGHTS MAN..BLACK DRAUGHTS KING +26C4..26C5 ; W # So [2] SNOWMAN WITHOUT SNOW..SUN BEHIND CLOUD +26C6..26CD ; A # So [8] RAIN..DISABLED CAR +26CE ; W # So OPHIUCHUS +26CF..26D3 ; A # So [5] PICK..CHAINS +26D4 ; W # So NO ENTRY +26D5..26E1 ; A # So [13] ALTERNATE ONE-WAY LEFT WAY TRAFFIC..RESTRICTED LEFT ENTRY-2 +26E2 ; N # So ASTRONOMICAL SYMBOL FOR URANUS +26E3 ; A # So HEAVY CIRCLE WITH STROKE AND TWO DOTS ABOVE +26E4..26E7 ; N # So [4] PENTAGRAM..INVERTED PENTAGRAM +26E8..26E9 ; A # So [2] BLACK CROSS ON SHIELD..SHINTO SHRINE +26EA ; W # So CHURCH +26EB..26F1 ; A # So [7] CASTLE..UMBRELLA ON GROUND +26F2..26F3 ; W # So [2] FOUNTAIN..FLAG IN HOLE +26F4 ; A # So FERRY +26F5 ; W # So SAILBOAT +26F6..26F9 ; A # So [4] SQUARE FOUR CORNERS..PERSON WITH BALL +26FA ; W # So TENT +26FB..26FC ; A # So [2] JAPANESE BANK SYMBOL..HEADSTONE GRAVEYARD SYMBOL +26FD ; W # So FUEL PUMP +26FE..26FF ; A # So [2] CUP ON BLACK SQUARE..WHITE FLAG WITH HORIZONTAL MIDDLE BLACK STRIPE +2700..2704 ; N # So [5] BLACK SAFETY SCISSORS..WHITE SCISSORS +2705 ; W # So WHITE HEAVY CHECK MARK +2706..2709 ; N # So [4] TELEPHONE LOCATION SIGN..ENVELOPE +270A..270B ; W # So [2] RAISED FIST..RAISED HAND +270C..2727 ; N # So [28] VICTORY HAND..WHITE FOUR POINTED STAR +2728 ; W # So SPARKLES +2729..273C ; N # So [20] STRESS OUTLINED WHITE STAR..OPEN CENTRE TEARDROP-SPOKED ASTERISK +273D ; A # So HEAVY TEARDROP-SPOKED ASTERISK +273E..274B ; N # So [14] SIX PETALLED BLACK AND WHITE FLORETTE..HEAVY EIGHT TEARDROP-SPOKED PROPELLER ASTERISK +274C ; W # So CROSS MARK +274D ; N # So SHADOWED WHITE CIRCLE +274E ; W # So NEGATIVE SQUARED CROSS MARK +274F..2752 ; N # So [4] LOWER RIGHT DROP-SHADOWED WHITE SQUARE..UPPER RIGHT SHADOWED WHITE SQUARE +2753..2755 ; W # So [3] BLACK QUESTION MARK ORNAMENT..WHITE EXCLAMATION MARK ORNAMENT +2756 ; N # So BLACK DIAMOND MINUS WHITE X +2757 ; W # So HEAVY EXCLAMATION MARK SYMBOL +2758..2767 ; N # So [16] LIGHT VERTICAL BAR..ROTATED FLORAL HEART BULLET +2768 ; N # Ps MEDIUM LEFT PARENTHESIS ORNAMENT +2769 ; N # Pe MEDIUM RIGHT PARENTHESIS ORNAMENT +276A ; N # Ps MEDIUM FLATTENED LEFT PARENTHESIS ORNAMENT +276B ; N # Pe MEDIUM FLATTENED RIGHT PARENTHESIS ORNAMENT +276C ; N # Ps MEDIUM LEFT-POINTING ANGLE BRACKET ORNAMENT +276D ; N # Pe MEDIUM RIGHT-POINTING ANGLE BRACKET ORNAMENT +276E ; N # Ps HEAVY LEFT-POINTING ANGLE QUOTATION MARK ORNAMENT +276F ; N # Pe HEAVY RIGHT-POINTING ANGLE QUOTATION MARK ORNAMENT +2770 ; N # Ps HEAVY LEFT-POINTING ANGLE BRACKET ORNAMENT +2771 ; N # Pe HEAVY RIGHT-POINTING ANGLE BRACKET ORNAMENT +2772 ; N # Ps LIGHT LEFT TORTOISE SHELL BRACKET ORNAMENT +2773 ; N # Pe LIGHT RIGHT TORTOISE SHELL BRACKET ORNAMENT +2774 ; N # Ps MEDIUM LEFT CURLY BRACKET ORNAMENT +2775 ; N # Pe MEDIUM RIGHT CURLY BRACKET ORNAMENT +2776..277F ; A # No [10] DINGBAT NEGATIVE CIRCLED DIGIT ONE..DINGBAT NEGATIVE CIRCLED NUMBER TEN +2780..2793 ; N # No [20] DINGBAT CIRCLED SANS-SERIF DIGIT ONE..DINGBAT NEGATIVE CIRCLED SANS-SERIF NUMBER TEN +2794 ; N # So HEAVY WIDE-HEADED RIGHTWARDS ARROW +2795..2797 ; W # So [3] HEAVY PLUS SIGN..HEAVY DIVISION SIGN +2798..27AF ; N # So [24] HEAVY SOUTH EAST ARROW..NOTCHED LOWER RIGHT-SHADOWED WHITE RIGHTWARDS ARROW +27B0 ; W # So CURLY LOOP +27B1..27BE ; N # So [14] NOTCHED UPPER RIGHT-SHADOWED WHITE RIGHTWARDS ARROW..OPEN-OUTLINED RIGHTWARDS ARROW +27BF ; W # So DOUBLE CURLY LOOP +27C0..27C4 ; N # Sm [5] THREE DIMENSIONAL ANGLE..OPEN SUPERSET +27C5 ; N # Ps LEFT S-SHAPED BAG DELIMITER +27C6 ; N # Pe RIGHT S-SHAPED BAG DELIMITER +27C7..27E5 ; N # Sm [31] OR WITH DOT INSIDE..WHITE SQUARE WITH RIGHTWARDS TICK +27E6 ; Na # Ps MATHEMATICAL LEFT WHITE SQUARE BRACKET +27E7 ; Na # Pe MATHEMATICAL RIGHT WHITE SQUARE BRACKET +27E8 ; Na # Ps MATHEMATICAL LEFT ANGLE BRACKET +27E9 ; Na # Pe MATHEMATICAL RIGHT ANGLE BRACKET +27EA ; Na # Ps MATHEMATICAL LEFT DOUBLE ANGLE BRACKET +27EB ; Na # Pe MATHEMATICAL RIGHT DOUBLE ANGLE BRACKET +27EC ; Na # Ps MATHEMATICAL LEFT WHITE TORTOISE SHELL BRACKET +27ED ; Na # Pe MATHEMATICAL RIGHT WHITE TORTOISE SHELL BRACKET +27EE ; N # Ps MATHEMATICAL LEFT FLATTENED PARENTHESIS +27EF ; N # Pe MATHEMATICAL RIGHT FLATTENED PARENTHESIS +27F0..27FF ; N # Sm [16] UPWARDS QUADRUPLE ARROW..LONG RIGHTWARDS SQUIGGLE ARROW +2800..28FF ; N # So [256] BRAILLE PATTERN BLANK..BRAILLE PATTERN DOTS-12345678 +2900..297F ; N # Sm [128] RIGHTWARDS TWO-HEADED ARROW WITH VERTICAL STROKE..DOWN FISH TAIL +2980..2982 ; N # Sm [3] TRIPLE VERTICAL BAR DELIMITER..Z NOTATION TYPE COLON +2983 ; N # Ps LEFT WHITE CURLY BRACKET +2984 ; N # Pe RIGHT WHITE CURLY BRACKET +2985 ; Na # Ps LEFT WHITE PARENTHESIS +2986 ; Na # Pe RIGHT WHITE PARENTHESIS +2987 ; N # Ps Z NOTATION LEFT IMAGE BRACKET +2988 ; N # Pe Z NOTATION RIGHT IMAGE BRACKET +2989 ; N # Ps Z NOTATION LEFT BINDING BRACKET +298A ; N # Pe Z NOTATION RIGHT BINDING BRACKET +298B ; N # Ps LEFT SQUARE BRACKET WITH UNDERBAR +298C ; N # Pe RIGHT SQUARE BRACKET WITH UNDERBAR +298D ; N # Ps LEFT SQUARE BRACKET WITH TICK IN TOP CORNER +298E ; N # Pe RIGHT SQUARE BRACKET WITH TICK IN BOTTOM CORNER +298F ; N # Ps LEFT SQUARE BRACKET WITH TICK IN BOTTOM CORNER +2990 ; N # Pe RIGHT SQUARE BRACKET WITH TICK IN TOP CORNER +2991 ; N # Ps LEFT ANGLE BRACKET WITH DOT +2992 ; N # Pe RIGHT ANGLE BRACKET WITH DOT +2993 ; N # Ps LEFT ARC LESS-THAN BRACKET +2994 ; N # Pe RIGHT ARC GREATER-THAN BRACKET +2995 ; N # Ps DOUBLE LEFT ARC GREATER-THAN BRACKET +2996 ; N # Pe DOUBLE RIGHT ARC LESS-THAN BRACKET +2997 ; N # Ps LEFT BLACK TORTOISE SHELL BRACKET +2998 ; N # Pe RIGHT BLACK TORTOISE SHELL BRACKET +2999..29D7 ; N # Sm [63] DOTTED FENCE..BLACK HOURGLASS +29D8 ; N # Ps LEFT WIGGLY FENCE +29D9 ; N # Pe RIGHT WIGGLY FENCE +29DA ; N # Ps LEFT DOUBLE WIGGLY FENCE +29DB ; N # Pe RIGHT DOUBLE WIGGLY FENCE +29DC..29FB ; N # Sm [32] INCOMPLETE INFINITY..TRIPLE PLUS +29FC ; N # Ps LEFT-POINTING CURVED ANGLE BRACKET +29FD ; N # Pe RIGHT-POINTING CURVED ANGLE BRACKET +29FE..29FF ; N # Sm [2] TINY..MINY +2A00..2AFF ; N # Sm [256] N-ARY CIRCLED DOT OPERATOR..N-ARY WHITE VERTICAL BAR +2B00..2B1A ; N # So [27] NORTH EAST WHITE ARROW..DOTTED SQUARE +2B1B..2B1C ; W # So [2] BLACK LARGE SQUARE..WHITE LARGE SQUARE +2B1D..2B2F ; N # So [19] BLACK VERY SMALL SQUARE..WHITE VERTICAL ELLIPSE +2B30..2B44 ; N # Sm [21] LEFT ARROW WITH SMALL CIRCLE..RIGHTWARDS ARROW THROUGH SUPERSET +2B45..2B46 ; N # So [2] LEFTWARDS QUADRUPLE ARROW..RIGHTWARDS QUADRUPLE ARROW +2B47..2B4C ; N # Sm [6] REVERSE TILDE OPERATOR ABOVE RIGHTWARDS ARROW..RIGHTWARDS ARROW ABOVE REVERSE TILDE OPERATOR +2B4D..2B4F ; N # So [3] DOWNWARDS TRIANGLE-HEADED ZIGZAG ARROW..SHORT BACKSLANTED SOUTH ARROW +2B50 ; W # So WHITE MEDIUM STAR +2B51..2B54 ; N # So [4] BLACK SMALL STAR..WHITE RIGHT-POINTING PENTAGON +2B55 ; W # So HEAVY LARGE CIRCLE +2B56..2B59 ; A # So [4] HEAVY OVAL WITH OVAL INSIDE..HEAVY CIRCLED SALTIRE +2B5A..2B73 ; N # So [26] SLANTED NORTH ARROW WITH HOOKED HEAD..DOWNWARDS TRIANGLE-HEADED ARROW TO BAR +2B76..2B95 ; N # So [32] NORTH WEST TRIANGLE-HEADED ARROW TO BAR..RIGHTWARDS BLACK ARROW +2B97..2BFF ; N # So [105] SYMBOL FOR TYPE A ELECTRONICS..HELLSCHREIBER PAUSE SYMBOL +2C00..2C5F ; N # L& [96] GLAGOLITIC CAPITAL LETTER AZU..GLAGOLITIC SMALL LETTER CAUDATE CHRIVI +2C60..2C7B ; N # L& [28] LATIN CAPITAL LETTER L WITH DOUBLE BAR..LATIN LETTER SMALL CAPITAL TURNED E +2C7C..2C7D ; N # Lm [2] LATIN SUBSCRIPT SMALL LETTER J..MODIFIER LETTER CAPITAL V +2C7E..2C7F ; N # Lu [2] LATIN CAPITAL LETTER S WITH SWASH TAIL..LATIN CAPITAL LETTER Z WITH SWASH TAIL +2C80..2CE4 ; N # L& [101] COPTIC CAPITAL LETTER ALFA..COPTIC SYMBOL KAI +2CE5..2CEA ; N # So [6] COPTIC SYMBOL MI RO..COPTIC SYMBOL SHIMA SIMA +2CEB..2CEE ; N # L& [4] COPTIC CAPITAL LETTER CRYPTOGRAMMIC SHEI..COPTIC SMALL LETTER CRYPTOGRAMMIC GANGIA +2CEF..2CF1 ; N # Mn [3] COPTIC COMBINING NI ABOVE..COPTIC COMBINING SPIRITUS LENIS +2CF2..2CF3 ; N # L& [2] COPTIC CAPITAL LETTER BOHAIRIC KHEI..COPTIC SMALL LETTER BOHAIRIC KHEI +2CF9..2CFC ; N # Po [4] COPTIC OLD NUBIAN FULL STOP..COPTIC OLD NUBIAN VERSE DIVIDER +2CFD ; N # No COPTIC FRACTION ONE HALF +2CFE..2CFF ; N # Po [2] COPTIC FULL STOP..COPTIC MORPHOLOGICAL DIVIDER +2D00..2D25 ; N # Ll [38] GEORGIAN SMALL LETTER AN..GEORGIAN SMALL LETTER HOE +2D27 ; N # Ll GEORGIAN SMALL LETTER YN +2D2D ; N # Ll GEORGIAN SMALL LETTER AEN +2D30..2D67 ; N # Lo [56] TIFINAGH LETTER YA..TIFINAGH LETTER YO +2D6F ; N # Lm TIFINAGH MODIFIER LETTER LABIALIZATION MARK +2D70 ; N # Po TIFINAGH SEPARATOR MARK +2D7F ; N # Mn TIFINAGH CONSONANT JOINER +2D80..2D96 ; N # Lo [23] ETHIOPIC SYLLABLE LOA..ETHIOPIC SYLLABLE GGWE +2DA0..2DA6 ; N # Lo [7] ETHIOPIC SYLLABLE SSA..ETHIOPIC SYLLABLE SSO +2DA8..2DAE ; N # Lo [7] ETHIOPIC SYLLABLE CCA..ETHIOPIC SYLLABLE CCO +2DB0..2DB6 ; N # Lo [7] ETHIOPIC SYLLABLE ZZA..ETHIOPIC SYLLABLE ZZO +2DB8..2DBE ; N # Lo [7] ETHIOPIC SYLLABLE CCHA..ETHIOPIC SYLLABLE CCHO +2DC0..2DC6 ; N # Lo [7] ETHIOPIC SYLLABLE QYA..ETHIOPIC SYLLABLE QYO +2DC8..2DCE ; N # Lo [7] ETHIOPIC SYLLABLE KYA..ETHIOPIC SYLLABLE KYO +2DD0..2DD6 ; N # Lo [7] ETHIOPIC SYLLABLE XYA..ETHIOPIC SYLLABLE XYO +2DD8..2DDE ; N # Lo [7] ETHIOPIC SYLLABLE GYA..ETHIOPIC SYLLABLE GYO +2DE0..2DFF ; N # Mn [32] COMBINING CYRILLIC LETTER BE..COMBINING CYRILLIC LETTER IOTIFIED BIG YUS +2E00..2E01 ; N # Po [2] RIGHT ANGLE SUBSTITUTION MARKER..RIGHT ANGLE DOTTED SUBSTITUTION MARKER +2E02 ; N # Pi LEFT SUBSTITUTION BRACKET +2E03 ; N # Pf RIGHT SUBSTITUTION BRACKET +2E04 ; N # Pi LEFT DOTTED SUBSTITUTION BRACKET +2E05 ; N # Pf RIGHT DOTTED SUBSTITUTION BRACKET +2E06..2E08 ; N # Po [3] RAISED INTERPOLATION MARKER..DOTTED TRANSPOSITION MARKER +2E09 ; N # Pi LEFT TRANSPOSITION BRACKET +2E0A ; N # Pf RIGHT TRANSPOSITION BRACKET +2E0B ; N # Po RAISED SQUARE +2E0C ; N # Pi LEFT RAISED OMISSION BRACKET +2E0D ; N # Pf RIGHT RAISED OMISSION BRACKET +2E0E..2E16 ; N # Po [9] EDITORIAL CORONIS..DOTTED RIGHT-POINTING ANGLE +2E17 ; N # Pd DOUBLE OBLIQUE HYPHEN +2E18..2E19 ; N # Po [2] INVERTED INTERROBANG..PALM BRANCH +2E1A ; N # Pd HYPHEN WITH DIAERESIS +2E1B ; N # Po TILDE WITH RING ABOVE +2E1C ; N # Pi LEFT LOW PARAPHRASE BRACKET +2E1D ; N # Pf RIGHT LOW PARAPHRASE BRACKET +2E1E..2E1F ; N # Po [2] TILDE WITH DOT ABOVE..TILDE WITH DOT BELOW +2E20 ; N # Pi LEFT VERTICAL BAR WITH QUILL +2E21 ; N # Pf RIGHT VERTICAL BAR WITH QUILL +2E22 ; N # Ps TOP LEFT HALF BRACKET +2E23 ; N # Pe TOP RIGHT HALF BRACKET +2E24 ; N # Ps BOTTOM LEFT HALF BRACKET +2E25 ; N # Pe BOTTOM RIGHT HALF BRACKET +2E26 ; N # Ps LEFT SIDEWAYS U BRACKET +2E27 ; N # Pe RIGHT SIDEWAYS U BRACKET +2E28 ; N # Ps LEFT DOUBLE PARENTHESIS +2E29 ; N # Pe RIGHT DOUBLE PARENTHESIS +2E2A..2E2E ; N # Po [5] TWO DOTS OVER ONE DOT PUNCTUATION..REVERSED QUESTION MARK +2E2F ; N # Lm VERTICAL TILDE +2E30..2E39 ; N # Po [10] RING POINT..TOP HALF SECTION SIGN +2E3A..2E3B ; N # Pd [2] TWO-EM DASH..THREE-EM DASH +2E3C..2E3F ; N # Po [4] STENOGRAPHIC FULL STOP..CAPITULUM +2E40 ; N # Pd DOUBLE HYPHEN +2E41 ; N # Po REVERSED COMMA +2E42 ; N # Ps DOUBLE LOW-REVERSED-9 QUOTATION MARK +2E43..2E4F ; N # Po [13] DASH WITH LEFT UPTURN..CORNISH VERSE DIVIDER +2E50..2E51 ; N # So [2] CROSS PATTY WITH RIGHT CROSSBAR..CROSS PATTY WITH LEFT CROSSBAR +2E52..2E54 ; N # Po [3] TIRONIAN SIGN CAPITAL ET..MEDIEVAL QUESTION MARK +2E55 ; N # Ps LEFT SQUARE BRACKET WITH STROKE +2E56 ; N # Pe RIGHT SQUARE BRACKET WITH STROKE +2E57 ; N # Ps LEFT SQUARE BRACKET WITH DOUBLE STROKE +2E58 ; N # Pe RIGHT SQUARE BRACKET WITH DOUBLE STROKE +2E59 ; N # Ps TOP HALF LEFT PARENTHESIS +2E5A ; N # Pe TOP HALF RIGHT PARENTHESIS +2E5B ; N # Ps BOTTOM HALF LEFT PARENTHESIS +2E5C ; N # Pe BOTTOM HALF RIGHT PARENTHESIS +2E5D ; N # Pd OBLIQUE HYPHEN +2E80..2E99 ; W # So [26] CJK RADICAL REPEAT..CJK RADICAL RAP +2E9B..2EF3 ; W # So [89] CJK RADICAL CHOKE..CJK RADICAL C-SIMPLIFIED TURTLE +2F00..2FD5 ; W # So [214] KANGXI RADICAL ONE..KANGXI RADICAL FLUTE +2FF0..2FFF ; W # So [16] IDEOGRAPHIC DESCRIPTION CHARACTER LEFT TO RIGHT..IDEOGRAPHIC DESCRIPTION CHARACTER ROTATION +3000 ; F # Zs IDEOGRAPHIC SPACE +3001..3003 ; W # Po [3] IDEOGRAPHIC COMMA..DITTO MARK +3004 ; W # So JAPANESE INDUSTRIAL STANDARD SYMBOL +3005 ; W # Lm IDEOGRAPHIC ITERATION MARK +3006 ; W # Lo IDEOGRAPHIC CLOSING MARK +3007 ; W # Nl IDEOGRAPHIC NUMBER ZERO +3008 ; W # Ps LEFT ANGLE BRACKET +3009 ; W # Pe RIGHT ANGLE BRACKET +300A ; W # Ps LEFT DOUBLE ANGLE BRACKET +300B ; W # Pe RIGHT DOUBLE ANGLE BRACKET +300C ; W # Ps LEFT CORNER BRACKET +300D ; W # Pe RIGHT CORNER BRACKET +300E ; W # Ps LEFT WHITE CORNER BRACKET +300F ; W # Pe RIGHT WHITE CORNER BRACKET +3010 ; W # Ps LEFT BLACK LENTICULAR BRACKET +3011 ; W # Pe RIGHT BLACK LENTICULAR BRACKET +3012..3013 ; W # So [2] POSTAL MARK..GETA MARK +3014 ; W # Ps LEFT TORTOISE SHELL BRACKET +3015 ; W # Pe RIGHT TORTOISE SHELL BRACKET +3016 ; W # Ps LEFT WHITE LENTICULAR BRACKET +3017 ; W # Pe RIGHT WHITE LENTICULAR BRACKET +3018 ; W # Ps LEFT WHITE TORTOISE SHELL BRACKET +3019 ; W # Pe RIGHT WHITE TORTOISE SHELL BRACKET +301A ; W # Ps LEFT WHITE SQUARE BRACKET +301B ; W # Pe RIGHT WHITE SQUARE BRACKET +301C ; W # Pd WAVE DASH +301D ; W # Ps REVERSED DOUBLE PRIME QUOTATION MARK +301E..301F ; W # Pe [2] DOUBLE PRIME QUOTATION MARK..LOW DOUBLE PRIME QUOTATION MARK +3020 ; W # So POSTAL MARK FACE +3021..3029 ; W # Nl [9] HANGZHOU NUMERAL ONE..HANGZHOU NUMERAL NINE +302A..302D ; W # Mn [4] IDEOGRAPHIC LEVEL TONE MARK..IDEOGRAPHIC ENTERING TONE MARK +302E..302F ; W # Mc [2] HANGUL SINGLE DOT TONE MARK..HANGUL DOUBLE DOT TONE MARK +3030 ; W # Pd WAVY DASH +3031..3035 ; W # Lm [5] VERTICAL KANA REPEAT MARK..VERTICAL KANA REPEAT MARK LOWER HALF +3036..3037 ; W # So [2] CIRCLED POSTAL MARK..IDEOGRAPHIC TELEGRAPH LINE FEED SEPARATOR SYMBOL +3038..303A ; W # Nl [3] HANGZHOU NUMERAL TEN..HANGZHOU NUMERAL THIRTY +303B ; W # Lm VERTICAL IDEOGRAPHIC ITERATION MARK +303C ; W # Lo MASU MARK +303D ; W # Po PART ALTERNATION MARK +303E ; W # So IDEOGRAPHIC VARIATION INDICATOR +303F ; N # So IDEOGRAPHIC HALF FILL SPACE +3041..3096 ; W # Lo [86] HIRAGANA LETTER SMALL A..HIRAGANA LETTER SMALL KE +3099..309A ; W # Mn [2] COMBINING KATAKANA-HIRAGANA VOICED SOUND MARK..COMBINING KATAKANA-HIRAGANA SEMI-VOICED SOUND MARK +309B..309C ; W # Sk [2] KATAKANA-HIRAGANA VOICED SOUND MARK..KATAKANA-HIRAGANA SEMI-VOICED SOUND MARK +309D..309E ; W # Lm [2] HIRAGANA ITERATION MARK..HIRAGANA VOICED ITERATION MARK +309F ; W # Lo HIRAGANA DIGRAPH YORI +30A0 ; W # Pd KATAKANA-HIRAGANA DOUBLE HYPHEN +30A1..30FA ; W # Lo [90] KATAKANA LETTER SMALL A..KATAKANA LETTER VO +30FB ; W # Po KATAKANA MIDDLE DOT +30FC..30FE ; W # Lm [3] KATAKANA-HIRAGANA PROLONGED SOUND MARK..KATAKANA VOICED ITERATION MARK +30FF ; W # Lo KATAKANA DIGRAPH KOTO +3105..312F ; W # Lo [43] BOPOMOFO LETTER B..BOPOMOFO LETTER NN +3131..318E ; W # Lo [94] HANGUL LETTER KIYEOK..HANGUL LETTER ARAEAE +3190..3191 ; W # So [2] IDEOGRAPHIC ANNOTATION LINKING MARK..IDEOGRAPHIC ANNOTATION REVERSE MARK +3192..3195 ; W # No [4] IDEOGRAPHIC ANNOTATION ONE MARK..IDEOGRAPHIC ANNOTATION FOUR MARK +3196..319F ; W # So [10] IDEOGRAPHIC ANNOTATION TOP MARK..IDEOGRAPHIC ANNOTATION MAN MARK +31A0..31BF ; W # Lo [32] BOPOMOFO LETTER BU..BOPOMOFO LETTER AH +31C0..31E3 ; W # So [36] CJK STROKE T..CJK STROKE Q +31EF ; W # So IDEOGRAPHIC DESCRIPTION CHARACTER SUBTRACTION +31F0..31FF ; W # Lo [16] KATAKANA LETTER SMALL KU..KATAKANA LETTER SMALL RO +3200..321E ; W # So [31] PARENTHESIZED HANGUL KIYEOK..PARENTHESIZED KOREAN CHARACTER O HU +3220..3229 ; W # No [10] PARENTHESIZED IDEOGRAPH ONE..PARENTHESIZED IDEOGRAPH TEN +322A..3247 ; W # So [30] PARENTHESIZED IDEOGRAPH MOON..CIRCLED IDEOGRAPH KOTO +3248..324F ; A # No [8] CIRCLED NUMBER TEN ON BLACK SQUARE..CIRCLED NUMBER EIGHTY ON BLACK SQUARE +3250 ; W # So PARTNERSHIP SIGN +3251..325F ; W # No [15] CIRCLED NUMBER TWENTY ONE..CIRCLED NUMBER THIRTY FIVE +3260..327F ; W # So [32] CIRCLED HANGUL KIYEOK..KOREAN STANDARD SYMBOL +3280..3289 ; W # No [10] CIRCLED IDEOGRAPH ONE..CIRCLED IDEOGRAPH TEN +328A..32B0 ; W # So [39] CIRCLED IDEOGRAPH MOON..CIRCLED IDEOGRAPH NIGHT +32B1..32BF ; W # No [15] CIRCLED NUMBER THIRTY SIX..CIRCLED NUMBER FIFTY +32C0..32FF ; W # So [64] IDEOGRAPHIC TELEGRAPH SYMBOL FOR JANUARY..SQUARE ERA NAME REIWA +3300..33FF ; W # So [256] SQUARE APAATO..SQUARE GAL +3400..4DBF ; W # Lo [6592] CJK UNIFIED IDEOGRAPH-3400..CJK UNIFIED IDEOGRAPH-4DBF +4DC0..4DFF ; N # So [64] HEXAGRAM FOR THE CREATIVE HEAVEN..HEXAGRAM FOR BEFORE COMPLETION +4E00..9FFF ; W # Lo [20992] CJK UNIFIED IDEOGRAPH-4E00..CJK UNIFIED IDEOGRAPH-9FFF +A000..A014 ; W # Lo [21] YI SYLLABLE IT..YI SYLLABLE E +A015 ; W # Lm YI SYLLABLE WU +A016..A48C ; W # Lo [1143] YI SYLLABLE BIT..YI SYLLABLE YYR +A490..A4C6 ; W # So [55] YI RADICAL QOT..YI RADICAL KE +A4D0..A4F7 ; N # Lo [40] LISU LETTER BA..LISU LETTER OE +A4F8..A4FD ; N # Lm [6] LISU LETTER TONE MYA TI..LISU LETTER TONE MYA JEU +A4FE..A4FF ; N # Po [2] LISU PUNCTUATION COMMA..LISU PUNCTUATION FULL STOP +A500..A60B ; N # Lo [268] VAI SYLLABLE EE..VAI SYLLABLE NG +A60C ; N # Lm VAI SYLLABLE LENGTHENER +A60D..A60F ; N # Po [3] VAI COMMA..VAI QUESTION MARK +A610..A61F ; N # Lo [16] VAI SYLLABLE NDOLE FA..VAI SYMBOL JONG +A620..A629 ; N # Nd [10] VAI DIGIT ZERO..VAI DIGIT NINE +A62A..A62B ; N # Lo [2] VAI SYLLABLE NDOLE MA..VAI SYLLABLE NDOLE DO +A640..A66D ; N # L& [46] CYRILLIC CAPITAL LETTER ZEMLYA..CYRILLIC SMALL LETTER DOUBLE MONOCULAR O +A66E ; N # Lo CYRILLIC LETTER MULTIOCULAR O +A66F ; N # Mn COMBINING CYRILLIC VZMET +A670..A672 ; N # Me [3] COMBINING CYRILLIC TEN MILLIONS SIGN..COMBINING CYRILLIC THOUSAND MILLIONS SIGN +A673 ; N # Po SLAVONIC ASTERISK +A674..A67D ; N # Mn [10] COMBINING CYRILLIC LETTER UKRAINIAN IE..COMBINING CYRILLIC PAYEROK +A67E ; N # Po CYRILLIC KAVYKA +A67F ; N # Lm CYRILLIC PAYEROK +A680..A69B ; N # L& [28] CYRILLIC CAPITAL LETTER DWE..CYRILLIC SMALL LETTER CROSSED O +A69C..A69D ; N # Lm [2] MODIFIER LETTER CYRILLIC HARD SIGN..MODIFIER LETTER CYRILLIC SOFT SIGN +A69E..A69F ; N # Mn [2] COMBINING CYRILLIC LETTER EF..COMBINING CYRILLIC LETTER IOTIFIED E +A6A0..A6E5 ; N # Lo [70] BAMUM LETTER A..BAMUM LETTER KI +A6E6..A6EF ; N # Nl [10] BAMUM LETTER MO..BAMUM LETTER KOGHOM +A6F0..A6F1 ; N # Mn [2] BAMUM COMBINING MARK KOQNDON..BAMUM COMBINING MARK TUKWENTIS +A6F2..A6F7 ; N # Po [6] BAMUM NJAEMLI..BAMUM QUESTION MARK +A700..A716 ; N # Sk [23] MODIFIER LETTER CHINESE TONE YIN PING..MODIFIER LETTER EXTRA-LOW LEFT-STEM TONE BAR +A717..A71F ; N # Lm [9] MODIFIER LETTER DOT VERTICAL BAR..MODIFIER LETTER LOW INVERTED EXCLAMATION MARK +A720..A721 ; N # Sk [2] MODIFIER LETTER STRESS AND HIGH TONE..MODIFIER LETTER STRESS AND LOW TONE +A722..A76F ; N # L& [78] LATIN CAPITAL LETTER EGYPTOLOGICAL ALEF..LATIN SMALL LETTER CON +A770 ; N # Lm MODIFIER LETTER US +A771..A787 ; N # L& [23] LATIN SMALL LETTER DUM..LATIN SMALL LETTER INSULAR T +A788 ; N # Lm MODIFIER LETTER LOW CIRCUMFLEX ACCENT +A789..A78A ; N # Sk [2] MODIFIER LETTER COLON..MODIFIER LETTER SHORT EQUALS SIGN +A78B..A78E ; N # L& [4] LATIN CAPITAL LETTER SALTILLO..LATIN SMALL LETTER L WITH RETROFLEX HOOK AND BELT +A78F ; N # Lo LATIN LETTER SINOLOGICAL DOT +A790..A7CA ; N # L& [59] LATIN CAPITAL LETTER N WITH DESCENDER..LATIN SMALL LETTER S WITH SHORT STROKE OVERLAY +A7D0..A7D1 ; N # L& [2] LATIN CAPITAL LETTER CLOSED INSULAR G..LATIN SMALL LETTER CLOSED INSULAR G +A7D3 ; N # Ll LATIN SMALL LETTER DOUBLE THORN +A7D5..A7D9 ; N # L& [5] LATIN SMALL LETTER DOUBLE WYNN..LATIN SMALL LETTER SIGMOID S +A7F2..A7F4 ; N # Lm [3] MODIFIER LETTER CAPITAL C..MODIFIER LETTER CAPITAL Q +A7F5..A7F6 ; N # L& [2] LATIN CAPITAL LETTER REVERSED HALF H..LATIN SMALL LETTER REVERSED HALF H +A7F7 ; N # Lo LATIN EPIGRAPHIC LETTER SIDEWAYS I +A7F8..A7F9 ; N # Lm [2] MODIFIER LETTER CAPITAL H WITH STROKE..MODIFIER LETTER SMALL LIGATURE OE +A7FA ; N # Ll LATIN LETTER SMALL CAPITAL TURNED M +A7FB..A7FF ; N # Lo [5] LATIN EPIGRAPHIC LETTER REVERSED F..LATIN EPIGRAPHIC LETTER ARCHAIC M +A800..A801 ; N # Lo [2] SYLOTI NAGRI LETTER A..SYLOTI NAGRI LETTER I +A802 ; N # Mn SYLOTI NAGRI SIGN DVISVARA +A803..A805 ; N # Lo [3] SYLOTI NAGRI LETTER U..SYLOTI NAGRI LETTER O +A806 ; N # Mn SYLOTI NAGRI SIGN HASANTA +A807..A80A ; N # Lo [4] SYLOTI NAGRI LETTER KO..SYLOTI NAGRI LETTER GHO +A80B ; N # Mn SYLOTI NAGRI SIGN ANUSVARA +A80C..A822 ; N # Lo [23] SYLOTI NAGRI LETTER CO..SYLOTI NAGRI LETTER HO +A823..A824 ; N # Mc [2] SYLOTI NAGRI VOWEL SIGN A..SYLOTI NAGRI VOWEL SIGN I +A825..A826 ; N # Mn [2] SYLOTI NAGRI VOWEL SIGN U..SYLOTI NAGRI VOWEL SIGN E +A827 ; N # Mc SYLOTI NAGRI VOWEL SIGN OO +A828..A82B ; N # So [4] SYLOTI NAGRI POETRY MARK-1..SYLOTI NAGRI POETRY MARK-4 +A82C ; N # Mn SYLOTI NAGRI SIGN ALTERNATE HASANTA +A830..A835 ; N # No [6] NORTH INDIC FRACTION ONE QUARTER..NORTH INDIC FRACTION THREE SIXTEENTHS +A836..A837 ; N # So [2] NORTH INDIC QUARTER MARK..NORTH INDIC PLACEHOLDER MARK +A838 ; N # Sc NORTH INDIC RUPEE MARK +A839 ; N # So NORTH INDIC QUANTITY MARK +A840..A873 ; N # Lo [52] PHAGS-PA LETTER KA..PHAGS-PA LETTER CANDRABINDU +A874..A877 ; N # Po [4] PHAGS-PA SINGLE HEAD MARK..PHAGS-PA MARK DOUBLE SHAD +A880..A881 ; N # Mc [2] SAURASHTRA SIGN ANUSVARA..SAURASHTRA SIGN VISARGA +A882..A8B3 ; N # Lo [50] SAURASHTRA LETTER A..SAURASHTRA LETTER LLA +A8B4..A8C3 ; N # Mc [16] SAURASHTRA CONSONANT SIGN HAARU..SAURASHTRA VOWEL SIGN AU +A8C4..A8C5 ; N # Mn [2] SAURASHTRA SIGN VIRAMA..SAURASHTRA SIGN CANDRABINDU +A8CE..A8CF ; N # Po [2] SAURASHTRA DANDA..SAURASHTRA DOUBLE DANDA +A8D0..A8D9 ; N # Nd [10] SAURASHTRA DIGIT ZERO..SAURASHTRA DIGIT NINE +A8E0..A8F1 ; N # Mn [18] COMBINING DEVANAGARI DIGIT ZERO..COMBINING DEVANAGARI SIGN AVAGRAHA +A8F2..A8F7 ; N # Lo [6] DEVANAGARI SIGN SPACING CANDRABINDU..DEVANAGARI SIGN CANDRABINDU AVAGRAHA +A8F8..A8FA ; N # Po [3] DEVANAGARI SIGN PUSHPIKA..DEVANAGARI CARET +A8FB ; N # Lo DEVANAGARI HEADSTROKE +A8FC ; N # Po DEVANAGARI SIGN SIDDHAM +A8FD..A8FE ; N # Lo [2] DEVANAGARI JAIN OM..DEVANAGARI LETTER AY +A8FF ; N # Mn DEVANAGARI VOWEL SIGN AY +A900..A909 ; N # Nd [10] KAYAH LI DIGIT ZERO..KAYAH LI DIGIT NINE +A90A..A925 ; N # Lo [28] KAYAH LI LETTER KA..KAYAH LI LETTER OO +A926..A92D ; N # Mn [8] KAYAH LI VOWEL UE..KAYAH LI TONE CALYA PLOPHU +A92E..A92F ; N # Po [2] KAYAH LI SIGN CWI..KAYAH LI SIGN SHYA +A930..A946 ; N # Lo [23] REJANG LETTER KA..REJANG LETTER A +A947..A951 ; N # Mn [11] REJANG VOWEL SIGN I..REJANG CONSONANT SIGN R +A952..A953 ; N # Mc [2] REJANG CONSONANT SIGN H..REJANG VIRAMA +A95F ; N # Po REJANG SECTION MARK +A960..A97C ; W # Lo [29] HANGUL CHOSEONG TIKEUT-MIEUM..HANGUL CHOSEONG SSANGYEORINHIEUH +A980..A982 ; N # Mn [3] JAVANESE SIGN PANYANGGA..JAVANESE SIGN LAYAR +A983 ; N # Mc JAVANESE SIGN WIGNYAN +A984..A9B2 ; N # Lo [47] JAVANESE LETTER A..JAVANESE LETTER HA +A9B3 ; N # Mn JAVANESE SIGN CECAK TELU +A9B4..A9B5 ; N # Mc [2] JAVANESE VOWEL SIGN TARUNG..JAVANESE VOWEL SIGN TOLONG +A9B6..A9B9 ; N # Mn [4] JAVANESE VOWEL SIGN WULU..JAVANESE VOWEL SIGN SUKU MENDUT +A9BA..A9BB ; N # Mc [2] JAVANESE VOWEL SIGN TALING..JAVANESE VOWEL SIGN DIRGA MURE +A9BC..A9BD ; N # Mn [2] JAVANESE VOWEL SIGN PEPET..JAVANESE CONSONANT SIGN KERET +A9BE..A9C0 ; N # Mc [3] JAVANESE CONSONANT SIGN PENGKAL..JAVANESE PANGKON +A9C1..A9CD ; N # Po [13] JAVANESE LEFT RERENGGAN..JAVANESE TURNED PADA PISELEH +A9CF ; N # Lm JAVANESE PANGRANGKEP +A9D0..A9D9 ; N # Nd [10] JAVANESE DIGIT ZERO..JAVANESE DIGIT NINE +A9DE..A9DF ; N # Po [2] JAVANESE PADA TIRTA TUMETES..JAVANESE PADA ISEN-ISEN +A9E0..A9E4 ; N # Lo [5] MYANMAR LETTER SHAN GHA..MYANMAR LETTER SHAN BHA +A9E5 ; N # Mn MYANMAR SIGN SHAN SAW +A9E6 ; N # Lm MYANMAR MODIFIER LETTER SHAN REDUPLICATION +A9E7..A9EF ; N # Lo [9] MYANMAR LETTER TAI LAING NYA..MYANMAR LETTER TAI LAING NNA +A9F0..A9F9 ; N # Nd [10] MYANMAR TAI LAING DIGIT ZERO..MYANMAR TAI LAING DIGIT NINE +A9FA..A9FE ; N # Lo [5] MYANMAR LETTER TAI LAING LLA..MYANMAR LETTER TAI LAING BHA +AA00..AA28 ; N # Lo [41] CHAM LETTER A..CHAM LETTER HA +AA29..AA2E ; N # Mn [6] CHAM VOWEL SIGN AA..CHAM VOWEL SIGN OE +AA2F..AA30 ; N # Mc [2] CHAM VOWEL SIGN O..CHAM VOWEL SIGN AI +AA31..AA32 ; N # Mn [2] CHAM VOWEL SIGN AU..CHAM VOWEL SIGN UE +AA33..AA34 ; N # Mc [2] CHAM CONSONANT SIGN YA..CHAM CONSONANT SIGN RA +AA35..AA36 ; N # Mn [2] CHAM CONSONANT SIGN LA..CHAM CONSONANT SIGN WA +AA40..AA42 ; N # Lo [3] CHAM LETTER FINAL K..CHAM LETTER FINAL NG +AA43 ; N # Mn CHAM CONSONANT SIGN FINAL NG +AA44..AA4B ; N # Lo [8] CHAM LETTER FINAL CH..CHAM LETTER FINAL SS +AA4C ; N # Mn CHAM CONSONANT SIGN FINAL M +AA4D ; N # Mc CHAM CONSONANT SIGN FINAL H +AA50..AA59 ; N # Nd [10] CHAM DIGIT ZERO..CHAM DIGIT NINE +AA5C..AA5F ; N # Po [4] CHAM PUNCTUATION SPIRAL..CHAM PUNCTUATION TRIPLE DANDA +AA60..AA6F ; N # Lo [16] MYANMAR LETTER KHAMTI GA..MYANMAR LETTER KHAMTI FA +AA70 ; N # Lm MYANMAR MODIFIER LETTER KHAMTI REDUPLICATION +AA71..AA76 ; N # Lo [6] MYANMAR LETTER KHAMTI XA..MYANMAR LOGOGRAM KHAMTI HM +AA77..AA79 ; N # So [3] MYANMAR SYMBOL AITON EXCLAMATION..MYANMAR SYMBOL AITON TWO +AA7A ; N # Lo MYANMAR LETTER AITON RA +AA7B ; N # Mc MYANMAR SIGN PAO KAREN TONE +AA7C ; N # Mn MYANMAR SIGN TAI LAING TONE-2 +AA7D ; N # Mc MYANMAR SIGN TAI LAING TONE-5 +AA7E..AA7F ; N # Lo [2] MYANMAR LETTER SHWE PALAUNG CHA..MYANMAR LETTER SHWE PALAUNG SHA +AA80..AAAF ; N # Lo [48] TAI VIET LETTER LOW KO..TAI VIET LETTER HIGH O +AAB0 ; N # Mn TAI VIET MAI KANG +AAB1 ; N # Lo TAI VIET VOWEL AA +AAB2..AAB4 ; N # Mn [3] TAI VIET VOWEL I..TAI VIET VOWEL U +AAB5..AAB6 ; N # Lo [2] TAI VIET VOWEL E..TAI VIET VOWEL O +AAB7..AAB8 ; N # Mn [2] TAI VIET MAI KHIT..TAI VIET VOWEL IA +AAB9..AABD ; N # Lo [5] TAI VIET VOWEL UEA..TAI VIET VOWEL AN +AABE..AABF ; N # Mn [2] TAI VIET VOWEL AM..TAI VIET TONE MAI EK +AAC0 ; N # Lo TAI VIET TONE MAI NUENG +AAC1 ; N # Mn TAI VIET TONE MAI THO +AAC2 ; N # Lo TAI VIET TONE MAI SONG +AADB..AADC ; N # Lo [2] TAI VIET SYMBOL KON..TAI VIET SYMBOL NUENG +AADD ; N # Lm TAI VIET SYMBOL SAM +AADE..AADF ; N # Po [2] TAI VIET SYMBOL HO HOI..TAI VIET SYMBOL KOI KOI +AAE0..AAEA ; N # Lo [11] MEETEI MAYEK LETTER E..MEETEI MAYEK LETTER SSA +AAEB ; N # Mc MEETEI MAYEK VOWEL SIGN II +AAEC..AAED ; N # Mn [2] MEETEI MAYEK VOWEL SIGN UU..MEETEI MAYEK VOWEL SIGN AAI +AAEE..AAEF ; N # Mc [2] MEETEI MAYEK VOWEL SIGN AU..MEETEI MAYEK VOWEL SIGN AAU +AAF0..AAF1 ; N # Po [2] MEETEI MAYEK CHEIKHAN..MEETEI MAYEK AHANG KHUDAM +AAF2 ; N # Lo MEETEI MAYEK ANJI +AAF3..AAF4 ; N # Lm [2] MEETEI MAYEK SYLLABLE REPETITION MARK..MEETEI MAYEK WORD REPETITION MARK +AAF5 ; N # Mc MEETEI MAYEK VOWEL SIGN VISARGA +AAF6 ; N # Mn MEETEI MAYEK VIRAMA +AB01..AB06 ; N # Lo [6] ETHIOPIC SYLLABLE TTHU..ETHIOPIC SYLLABLE TTHO +AB09..AB0E ; N # Lo [6] ETHIOPIC SYLLABLE DDHU..ETHIOPIC SYLLABLE DDHO +AB11..AB16 ; N # Lo [6] ETHIOPIC SYLLABLE DZU..ETHIOPIC SYLLABLE DZO +AB20..AB26 ; N # Lo [7] ETHIOPIC SYLLABLE CCHHA..ETHIOPIC SYLLABLE CCHHO +AB28..AB2E ; N # Lo [7] ETHIOPIC SYLLABLE BBA..ETHIOPIC SYLLABLE BBO +AB30..AB5A ; N # Ll [43] LATIN SMALL LETTER BARRED ALPHA..LATIN SMALL LETTER Y WITH SHORT RIGHT LEG +AB5B ; N # Sk MODIFIER BREVE WITH INVERTED BREVE +AB5C..AB5F ; N # Lm [4] MODIFIER LETTER SMALL HENG..MODIFIER LETTER SMALL U WITH LEFT HOOK +AB60..AB68 ; N # Ll [9] LATIN SMALL LETTER SAKHA YAT..LATIN SMALL LETTER TURNED R WITH MIDDLE TILDE +AB69 ; N # Lm MODIFIER LETTER SMALL TURNED W +AB6A..AB6B ; N # Sk [2] MODIFIER LETTER LEFT TACK..MODIFIER LETTER RIGHT TACK +AB70..ABBF ; N # Ll [80] CHEROKEE SMALL LETTER A..CHEROKEE SMALL LETTER YA +ABC0..ABE2 ; N # Lo [35] MEETEI MAYEK LETTER KOK..MEETEI MAYEK LETTER I LONSUM +ABE3..ABE4 ; N # Mc [2] MEETEI MAYEK VOWEL SIGN ONAP..MEETEI MAYEK VOWEL SIGN INAP +ABE5 ; N # Mn MEETEI MAYEK VOWEL SIGN ANAP +ABE6..ABE7 ; N # Mc [2] MEETEI MAYEK VOWEL SIGN YENAP..MEETEI MAYEK VOWEL SIGN SOUNAP +ABE8 ; N # Mn MEETEI MAYEK VOWEL SIGN UNAP +ABE9..ABEA ; N # Mc [2] MEETEI MAYEK VOWEL SIGN CHEINAP..MEETEI MAYEK VOWEL SIGN NUNG +ABEB ; N # Po MEETEI MAYEK CHEIKHEI +ABEC ; N # Mc MEETEI MAYEK LUM IYEK +ABED ; N # Mn MEETEI MAYEK APUN IYEK +ABF0..ABF9 ; N # Nd [10] MEETEI MAYEK DIGIT ZERO..MEETEI MAYEK DIGIT NINE +AC00..D7A3 ; W # Lo [11172] HANGUL SYLLABLE GA..HANGUL SYLLABLE HIH +D7B0..D7C6 ; N # Lo [23] HANGUL JUNGSEONG O-YEO..HANGUL JUNGSEONG ARAEA-E +D7CB..D7FB ; N # Lo [49] HANGUL JONGSEONG NIEUN-RIEUL..HANGUL JONGSEONG PHIEUPH-THIEUTH +D800..DB7F ; N # Cs [896] .. +DB80..DBFF ; N # Cs [128] .. +DC00..DFFF ; N # Cs [1024] .. +E000..F8FF ; A # Co [6400] .. +F900..FA6D ; W # Lo [366] CJK COMPATIBILITY IDEOGRAPH-F900..CJK COMPATIBILITY IDEOGRAPH-FA6D +FA6E..FA6F ; W # Cn [2] .. +FA70..FAD9 ; W # Lo [106] CJK COMPATIBILITY IDEOGRAPH-FA70..CJK COMPATIBILITY IDEOGRAPH-FAD9 +FADA..FAFF ; W # Cn [38] .. +FB00..FB06 ; N # Ll [7] LATIN SMALL LIGATURE FF..LATIN SMALL LIGATURE ST +FB13..FB17 ; N # Ll [5] ARMENIAN SMALL LIGATURE MEN NOW..ARMENIAN SMALL LIGATURE MEN XEH +FB1D ; N # Lo HEBREW LETTER YOD WITH HIRIQ +FB1E ; N # Mn HEBREW POINT JUDEO-SPANISH VARIKA +FB1F..FB28 ; N # Lo [10] HEBREW LIGATURE YIDDISH YOD YOD PATAH..HEBREW LETTER WIDE TAV +FB29 ; N # Sm HEBREW LETTER ALTERNATIVE PLUS SIGN +FB2A..FB36 ; N # Lo [13] HEBREW LETTER SHIN WITH SHIN DOT..HEBREW LETTER ZAYIN WITH DAGESH +FB38..FB3C ; N # Lo [5] HEBREW LETTER TET WITH DAGESH..HEBREW LETTER LAMED WITH DAGESH +FB3E ; N # Lo HEBREW LETTER MEM WITH DAGESH +FB40..FB41 ; N # Lo [2] HEBREW LETTER NUN WITH DAGESH..HEBREW LETTER SAMEKH WITH DAGESH +FB43..FB44 ; N # Lo [2] HEBREW LETTER FINAL PE WITH DAGESH..HEBREW LETTER PE WITH DAGESH +FB46..FB4F ; N # Lo [10] HEBREW LETTER TSADI WITH DAGESH..HEBREW LIGATURE ALEF LAMED +FB50..FBB1 ; N # Lo [98] ARABIC LETTER ALEF WASLA ISOLATED FORM..ARABIC LETTER YEH BARREE WITH HAMZA ABOVE FINAL FORM +FBB2..FBC2 ; N # Sk [17] ARABIC SYMBOL DOT ABOVE..ARABIC SYMBOL WASLA ABOVE +FBD3..FD3D ; N # Lo [363] ARABIC LETTER NG ISOLATED FORM..ARABIC LIGATURE ALEF WITH FATHATAN ISOLATED FORM +FD3E ; N # Pe ORNATE LEFT PARENTHESIS +FD3F ; N # Ps ORNATE RIGHT PARENTHESIS +FD40..FD4F ; N # So [16] ARABIC LIGATURE RAHIMAHU ALLAAH..ARABIC LIGATURE RAHIMAHUM ALLAAH +FD50..FD8F ; N # Lo [64] ARABIC LIGATURE TEH WITH JEEM WITH MEEM INITIAL FORM..ARABIC LIGATURE MEEM WITH KHAH WITH MEEM INITIAL FORM +FD92..FDC7 ; N # Lo [54] ARABIC LIGATURE MEEM WITH JEEM WITH KHAH INITIAL FORM..ARABIC LIGATURE NOON WITH JEEM WITH YEH FINAL FORM +FDCF ; N # So ARABIC LIGATURE SALAAMUHU ALAYNAA +FDF0..FDFB ; N # Lo [12] ARABIC LIGATURE SALLA USED AS KORANIC STOP SIGN ISOLATED FORM..ARABIC LIGATURE JALLAJALALOUHOU +FDFC ; N # Sc RIAL SIGN +FDFD..FDFF ; N # So [3] ARABIC LIGATURE BISMILLAH AR-RAHMAN AR-RAHEEM..ARABIC LIGATURE AZZA WA JALL +FE00..FE0F ; A # Mn [16] VARIATION SELECTOR-1..VARIATION SELECTOR-16 +FE10..FE16 ; W # Po [7] PRESENTATION FORM FOR VERTICAL COMMA..PRESENTATION FORM FOR VERTICAL QUESTION MARK +FE17 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT WHITE LENTICULAR BRACKET +FE18 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT WHITE LENTICULAR BRAKCET +FE19 ; W # Po PRESENTATION FORM FOR VERTICAL HORIZONTAL ELLIPSIS +FE20..FE2F ; N # Mn [16] COMBINING LIGATURE LEFT HALF..COMBINING CYRILLIC TITLO RIGHT HALF +FE30 ; W # Po PRESENTATION FORM FOR VERTICAL TWO DOT LEADER +FE31..FE32 ; W # Pd [2] PRESENTATION FORM FOR VERTICAL EM DASH..PRESENTATION FORM FOR VERTICAL EN DASH +FE33..FE34 ; W # Pc [2] PRESENTATION FORM FOR VERTICAL LOW LINE..PRESENTATION FORM FOR VERTICAL WAVY LOW LINE +FE35 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT PARENTHESIS +FE36 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT PARENTHESIS +FE37 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT CURLY BRACKET +FE38 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT CURLY BRACKET +FE39 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT TORTOISE SHELL BRACKET +FE3A ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT TORTOISE SHELL BRACKET +FE3B ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT BLACK LENTICULAR BRACKET +FE3C ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT BLACK LENTICULAR BRACKET +FE3D ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT DOUBLE ANGLE BRACKET +FE3E ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT DOUBLE ANGLE BRACKET +FE3F ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT ANGLE BRACKET +FE40 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT ANGLE BRACKET +FE41 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT CORNER BRACKET +FE42 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT CORNER BRACKET +FE43 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT WHITE CORNER BRACKET +FE44 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT WHITE CORNER BRACKET +FE45..FE46 ; W # Po [2] SESAME DOT..WHITE SESAME DOT +FE47 ; W # Ps PRESENTATION FORM FOR VERTICAL LEFT SQUARE BRACKET +FE48 ; W # Pe PRESENTATION FORM FOR VERTICAL RIGHT SQUARE BRACKET +FE49..FE4C ; W # Po [4] DASHED OVERLINE..DOUBLE WAVY OVERLINE +FE4D..FE4F ; W # Pc [3] DASHED LOW LINE..WAVY LOW LINE +FE50..FE52 ; W # Po [3] SMALL COMMA..SMALL FULL STOP +FE54..FE57 ; W # Po [4] SMALL SEMICOLON..SMALL EXCLAMATION MARK +FE58 ; W # Pd SMALL EM DASH +FE59 ; W # Ps SMALL LEFT PARENTHESIS +FE5A ; W # Pe SMALL RIGHT PARENTHESIS +FE5B ; W # Ps SMALL LEFT CURLY BRACKET +FE5C ; W # Pe SMALL RIGHT CURLY BRACKET +FE5D ; W # Ps SMALL LEFT TORTOISE SHELL BRACKET +FE5E ; W # Pe SMALL RIGHT TORTOISE SHELL BRACKET +FE5F..FE61 ; W # Po [3] SMALL NUMBER SIGN..SMALL ASTERISK +FE62 ; W # Sm SMALL PLUS SIGN +FE63 ; W # Pd SMALL HYPHEN-MINUS +FE64..FE66 ; W # Sm [3] SMALL LESS-THAN SIGN..SMALL EQUALS SIGN +FE68 ; W # Po SMALL REVERSE SOLIDUS +FE69 ; W # Sc SMALL DOLLAR SIGN +FE6A..FE6B ; W # Po [2] SMALL PERCENT SIGN..SMALL COMMERCIAL AT +FE70..FE74 ; N # Lo [5] ARABIC FATHATAN ISOLATED FORM..ARABIC KASRATAN ISOLATED FORM +FE76..FEFC ; N # Lo [135] ARABIC FATHA ISOLATED FORM..ARABIC LIGATURE LAM WITH ALEF FINAL FORM +FEFF ; N # Cf ZERO WIDTH NO-BREAK SPACE +FF01..FF03 ; F # Po [3] FULLWIDTH EXCLAMATION MARK..FULLWIDTH NUMBER SIGN +FF04 ; F # Sc FULLWIDTH DOLLAR SIGN +FF05..FF07 ; F # Po [3] FULLWIDTH PERCENT SIGN..FULLWIDTH APOSTROPHE +FF08 ; F # Ps FULLWIDTH LEFT PARENTHESIS +FF09 ; F # Pe FULLWIDTH RIGHT PARENTHESIS +FF0A ; F # Po FULLWIDTH ASTERISK +FF0B ; F # Sm FULLWIDTH PLUS SIGN +FF0C ; F # Po FULLWIDTH COMMA +FF0D ; F # Pd FULLWIDTH HYPHEN-MINUS +FF0E..FF0F ; F # Po [2] FULLWIDTH FULL STOP..FULLWIDTH SOLIDUS +FF10..FF19 ; F # Nd [10] FULLWIDTH DIGIT ZERO..FULLWIDTH DIGIT NINE +FF1A..FF1B ; F # Po [2] FULLWIDTH COLON..FULLWIDTH SEMICOLON +FF1C..FF1E ; F # Sm [3] FULLWIDTH LESS-THAN SIGN..FULLWIDTH GREATER-THAN SIGN +FF1F..FF20 ; F # Po [2] FULLWIDTH QUESTION MARK..FULLWIDTH COMMERCIAL AT +FF21..FF3A ; F # Lu [26] FULLWIDTH LATIN CAPITAL LETTER A..FULLWIDTH LATIN CAPITAL LETTER Z +FF3B ; F # Ps FULLWIDTH LEFT SQUARE BRACKET +FF3C ; F # Po FULLWIDTH REVERSE SOLIDUS +FF3D ; F # Pe FULLWIDTH RIGHT SQUARE BRACKET +FF3E ; F # Sk FULLWIDTH CIRCUMFLEX ACCENT +FF3F ; F # Pc FULLWIDTH LOW LINE +FF40 ; F # Sk FULLWIDTH GRAVE ACCENT +FF41..FF5A ; F # Ll [26] FULLWIDTH LATIN SMALL LETTER A..FULLWIDTH LATIN SMALL LETTER Z +FF5B ; F # Ps FULLWIDTH LEFT CURLY BRACKET +FF5C ; F # Sm FULLWIDTH VERTICAL LINE +FF5D ; F # Pe FULLWIDTH RIGHT CURLY BRACKET +FF5E ; F # Sm FULLWIDTH TILDE +FF5F ; F # Ps FULLWIDTH LEFT WHITE PARENTHESIS +FF60 ; F # Pe FULLWIDTH RIGHT WHITE PARENTHESIS +FF61 ; H # Po HALFWIDTH IDEOGRAPHIC FULL STOP +FF62 ; H # Ps HALFWIDTH LEFT CORNER BRACKET +FF63 ; H # Pe HALFWIDTH RIGHT CORNER BRACKET +FF64..FF65 ; H # Po [2] HALFWIDTH IDEOGRAPHIC COMMA..HALFWIDTH KATAKANA MIDDLE DOT +FF66..FF6F ; H # Lo [10] HALFWIDTH KATAKANA LETTER WO..HALFWIDTH KATAKANA LETTER SMALL TU +FF70 ; H # Lm HALFWIDTH KATAKANA-HIRAGANA PROLONGED SOUND MARK +FF71..FF9D ; H # Lo [45] HALFWIDTH KATAKANA LETTER A..HALFWIDTH KATAKANA LETTER N +FF9E..FF9F ; H # Lm [2] HALFWIDTH KATAKANA VOICED SOUND MARK..HALFWIDTH KATAKANA SEMI-VOICED SOUND MARK +FFA0..FFBE ; H # Lo [31] HALFWIDTH HANGUL FILLER..HALFWIDTH HANGUL LETTER HIEUH +FFC2..FFC7 ; H # Lo [6] HALFWIDTH HANGUL LETTER A..HALFWIDTH HANGUL LETTER E +FFCA..FFCF ; H # Lo [6] HALFWIDTH HANGUL LETTER YEO..HALFWIDTH HANGUL LETTER OE +FFD2..FFD7 ; H # Lo [6] HALFWIDTH HANGUL LETTER YO..HALFWIDTH HANGUL LETTER YU +FFDA..FFDC ; H # Lo [3] HALFWIDTH HANGUL LETTER EU..HALFWIDTH HANGUL LETTER I +FFE0..FFE1 ; F # Sc [2] FULLWIDTH CENT SIGN..FULLWIDTH POUND SIGN +FFE2 ; F # Sm FULLWIDTH NOT SIGN +FFE3 ; F # Sk FULLWIDTH MACRON +FFE4 ; F # So FULLWIDTH BROKEN BAR +FFE5..FFE6 ; F # Sc [2] FULLWIDTH YEN SIGN..FULLWIDTH WON SIGN +FFE8 ; H # So HALFWIDTH FORMS LIGHT VERTICAL +FFE9..FFEC ; H # Sm [4] HALFWIDTH LEFTWARDS ARROW..HALFWIDTH DOWNWARDS ARROW +FFED..FFEE ; H # So [2] HALFWIDTH BLACK SQUARE..HALFWIDTH WHITE CIRCLE +FFF9..FFFB ; N # Cf [3] INTERLINEAR ANNOTATION ANCHOR..INTERLINEAR ANNOTATION TERMINATOR +FFFC ; N # So OBJECT REPLACEMENT CHARACTER +FFFD ; A # So REPLACEMENT CHARACTER +10000..1000B ; N # Lo [12] LINEAR B SYLLABLE B008 A..LINEAR B SYLLABLE B046 JE +1000D..10026 ; N # Lo [26] LINEAR B SYLLABLE B036 JO..LINEAR B SYLLABLE B032 QO +10028..1003A ; N # Lo [19] LINEAR B SYLLABLE B060 RA..LINEAR B SYLLABLE B042 WO +1003C..1003D ; N # Lo [2] LINEAR B SYLLABLE B017 ZA..LINEAR B SYLLABLE B074 ZE +1003F..1004D ; N # Lo [15] LINEAR B SYLLABLE B020 ZO..LINEAR B SYLLABLE B091 TWO +10050..1005D ; N # Lo [14] LINEAR B SYMBOL B018..LINEAR B SYMBOL B089 +10080..100FA ; N # Lo [123] LINEAR B IDEOGRAM B100 MAN..LINEAR B IDEOGRAM VESSEL B305 +10100..10102 ; N # Po [3] AEGEAN WORD SEPARATOR LINE..AEGEAN CHECK MARK +10107..10133 ; N # No [45] AEGEAN NUMBER ONE..AEGEAN NUMBER NINETY THOUSAND +10137..1013F ; N # So [9] AEGEAN WEIGHT BASE UNIT..AEGEAN MEASURE THIRD SUBUNIT +10140..10174 ; N # Nl [53] GREEK ACROPHONIC ATTIC ONE QUARTER..GREEK ACROPHONIC STRATIAN FIFTY MNAS +10175..10178 ; N # No [4] GREEK ONE HALF SIGN..GREEK THREE QUARTERS SIGN +10179..10189 ; N # So [17] GREEK YEAR SIGN..GREEK TRYBLION BASE SIGN +1018A..1018B ; N # No [2] GREEK ZERO SIGN..GREEK ONE QUARTER SIGN +1018C..1018E ; N # So [3] GREEK SINUSOID SIGN..NOMISMA SIGN +10190..1019C ; N # So [13] ROMAN SEXTANS SIGN..ASCIA SYMBOL +101A0 ; N # So GREEK SYMBOL TAU RHO +101D0..101FC ; N # So [45] PHAISTOS DISC SIGN PEDESTRIAN..PHAISTOS DISC SIGN WAVY BAND +101FD ; N # Mn PHAISTOS DISC SIGN COMBINING OBLIQUE STROKE +10280..1029C ; N # Lo [29] LYCIAN LETTER A..LYCIAN LETTER X +102A0..102D0 ; N # Lo [49] CARIAN LETTER A..CARIAN LETTER UUU3 +102E0 ; N # Mn COPTIC EPACT THOUSANDS MARK +102E1..102FB ; N # No [27] COPTIC EPACT DIGIT ONE..COPTIC EPACT NUMBER NINE HUNDRED +10300..1031F ; N # Lo [32] OLD ITALIC LETTER A..OLD ITALIC LETTER ESS +10320..10323 ; N # No [4] OLD ITALIC NUMERAL ONE..OLD ITALIC NUMERAL FIFTY +1032D..1032F ; N # Lo [3] OLD ITALIC LETTER YE..OLD ITALIC LETTER SOUTHERN TSE +10330..10340 ; N # Lo [17] GOTHIC LETTER AHSA..GOTHIC LETTER PAIRTHRA +10341 ; N # Nl GOTHIC LETTER NINETY +10342..10349 ; N # Lo [8] GOTHIC LETTER RAIDA..GOTHIC LETTER OTHAL +1034A ; N # Nl GOTHIC LETTER NINE HUNDRED +10350..10375 ; N # Lo [38] OLD PERMIC LETTER AN..OLD PERMIC LETTER IA +10376..1037A ; N # Mn [5] COMBINING OLD PERMIC LETTER AN..COMBINING OLD PERMIC LETTER SII +10380..1039D ; N # Lo [30] UGARITIC LETTER ALPA..UGARITIC LETTER SSU +1039F ; N # Po UGARITIC WORD DIVIDER +103A0..103C3 ; N # Lo [36] OLD PERSIAN SIGN A..OLD PERSIAN SIGN HA +103C8..103CF ; N # Lo [8] OLD PERSIAN SIGN AURAMAZDAA..OLD PERSIAN SIGN BUUMISH +103D0 ; N # Po OLD PERSIAN WORD DIVIDER +103D1..103D5 ; N # Nl [5] OLD PERSIAN NUMBER ONE..OLD PERSIAN NUMBER HUNDRED +10400..1044F ; N # L& [80] DESERET CAPITAL LETTER LONG I..DESERET SMALL LETTER EW +10450..1047F ; N # Lo [48] SHAVIAN LETTER PEEP..SHAVIAN LETTER YEW +10480..1049D ; N # Lo [30] OSMANYA LETTER ALEF..OSMANYA LETTER OO +104A0..104A9 ; N # Nd [10] OSMANYA DIGIT ZERO..OSMANYA DIGIT NINE +104B0..104D3 ; N # Lu [36] OSAGE CAPITAL LETTER A..OSAGE CAPITAL LETTER ZHA +104D8..104FB ; N # Ll [36] OSAGE SMALL LETTER A..OSAGE SMALL LETTER ZHA +10500..10527 ; N # Lo [40] ELBASAN LETTER A..ELBASAN LETTER KHE +10530..10563 ; N # Lo [52] CAUCASIAN ALBANIAN LETTER ALT..CAUCASIAN ALBANIAN LETTER KIW +1056F ; N # Po CAUCASIAN ALBANIAN CITATION MARK +10570..1057A ; N # Lu [11] VITHKUQI CAPITAL LETTER A..VITHKUQI CAPITAL LETTER GA +1057C..1058A ; N # Lu [15] VITHKUQI CAPITAL LETTER HA..VITHKUQI CAPITAL LETTER RE +1058C..10592 ; N # Lu [7] VITHKUQI CAPITAL LETTER SE..VITHKUQI CAPITAL LETTER XE +10594..10595 ; N # Lu [2] VITHKUQI CAPITAL LETTER Y..VITHKUQI CAPITAL LETTER ZE +10597..105A1 ; N # Ll [11] VITHKUQI SMALL LETTER A..VITHKUQI SMALL LETTER GA +105A3..105B1 ; N # Ll [15] VITHKUQI SMALL LETTER HA..VITHKUQI SMALL LETTER RE +105B3..105B9 ; N # Ll [7] VITHKUQI SMALL LETTER SE..VITHKUQI SMALL LETTER XE +105BB..105BC ; N # Ll [2] VITHKUQI SMALL LETTER Y..VITHKUQI SMALL LETTER ZE +10600..10736 ; N # Lo [311] LINEAR A SIGN AB001..LINEAR A SIGN A664 +10740..10755 ; N # Lo [22] LINEAR A SIGN A701 A..LINEAR A SIGN A732 JE +10760..10767 ; N # Lo [8] LINEAR A SIGN A800..LINEAR A SIGN A807 +10780..10785 ; N # Lm [6] MODIFIER LETTER SMALL CAPITAL AA..MODIFIER LETTER SMALL B WITH HOOK +10787..107B0 ; N # Lm [42] MODIFIER LETTER SMALL DZ DIGRAPH..MODIFIER LETTER SMALL V WITH RIGHT HOOK +107B2..107BA ; N # Lm [9] MODIFIER LETTER SMALL CAPITAL Y..MODIFIER LETTER SMALL S WITH CURL +10800..10805 ; N # Lo [6] CYPRIOT SYLLABLE A..CYPRIOT SYLLABLE JA +10808 ; N # Lo CYPRIOT SYLLABLE JO +1080A..10835 ; N # Lo [44] CYPRIOT SYLLABLE KA..CYPRIOT SYLLABLE WO +10837..10838 ; N # Lo [2] CYPRIOT SYLLABLE XA..CYPRIOT SYLLABLE XE +1083C ; N # Lo CYPRIOT SYLLABLE ZA +1083F ; N # Lo CYPRIOT SYLLABLE ZO +10840..10855 ; N # Lo [22] IMPERIAL ARAMAIC LETTER ALEPH..IMPERIAL ARAMAIC LETTER TAW +10857 ; N # Po IMPERIAL ARAMAIC SECTION SIGN +10858..1085F ; N # No [8] IMPERIAL ARAMAIC NUMBER ONE..IMPERIAL ARAMAIC NUMBER TEN THOUSAND +10860..10876 ; N # Lo [23] PALMYRENE LETTER ALEPH..PALMYRENE LETTER TAW +10877..10878 ; N # So [2] PALMYRENE LEFT-POINTING FLEURON..PALMYRENE RIGHT-POINTING FLEURON +10879..1087F ; N # No [7] PALMYRENE NUMBER ONE..PALMYRENE NUMBER TWENTY +10880..1089E ; N # Lo [31] NABATAEAN LETTER FINAL ALEPH..NABATAEAN LETTER TAW +108A7..108AF ; N # No [9] NABATAEAN NUMBER ONE..NABATAEAN NUMBER ONE HUNDRED +108E0..108F2 ; N # Lo [19] HATRAN LETTER ALEPH..HATRAN LETTER QOPH +108F4..108F5 ; N # Lo [2] HATRAN LETTER SHIN..HATRAN LETTER TAW +108FB..108FF ; N # No [5] HATRAN NUMBER ONE..HATRAN NUMBER ONE HUNDRED +10900..10915 ; N # Lo [22] PHOENICIAN LETTER ALF..PHOENICIAN LETTER TAU +10916..1091B ; N # No [6] PHOENICIAN NUMBER ONE..PHOENICIAN NUMBER THREE +1091F ; N # Po PHOENICIAN WORD SEPARATOR +10920..10939 ; N # Lo [26] LYDIAN LETTER A..LYDIAN LETTER C +1093F ; N # Po LYDIAN TRIANGULAR MARK +10980..1099F ; N # Lo [32] MEROITIC HIEROGLYPHIC LETTER A..MEROITIC HIEROGLYPHIC SYMBOL VIDJ-2 +109A0..109B7 ; N # Lo [24] MEROITIC CURSIVE LETTER A..MEROITIC CURSIVE LETTER DA +109BC..109BD ; N # No [2] MEROITIC CURSIVE FRACTION ELEVEN TWELFTHS..MEROITIC CURSIVE FRACTION ONE HALF +109BE..109BF ; N # Lo [2] MEROITIC CURSIVE LOGOGRAM RMT..MEROITIC CURSIVE LOGOGRAM IMN +109C0..109CF ; N # No [16] MEROITIC CURSIVE NUMBER ONE..MEROITIC CURSIVE NUMBER SEVENTY +109D2..109FF ; N # No [46] MEROITIC CURSIVE NUMBER ONE HUNDRED..MEROITIC CURSIVE FRACTION TEN TWELFTHS +10A00 ; N # Lo KHAROSHTHI LETTER A +10A01..10A03 ; N # Mn [3] KHAROSHTHI VOWEL SIGN I..KHAROSHTHI VOWEL SIGN VOCALIC R +10A05..10A06 ; N # Mn [2] KHAROSHTHI VOWEL SIGN E..KHAROSHTHI VOWEL SIGN O +10A0C..10A0F ; N # Mn [4] KHAROSHTHI VOWEL LENGTH MARK..KHAROSHTHI SIGN VISARGA +10A10..10A13 ; N # Lo [4] KHAROSHTHI LETTER KA..KHAROSHTHI LETTER GHA +10A15..10A17 ; N # Lo [3] KHAROSHTHI LETTER CA..KHAROSHTHI LETTER JA +10A19..10A35 ; N # Lo [29] KHAROSHTHI LETTER NYA..KHAROSHTHI LETTER VHA +10A38..10A3A ; N # Mn [3] KHAROSHTHI SIGN BAR ABOVE..KHAROSHTHI SIGN DOT BELOW +10A3F ; N # Mn KHAROSHTHI VIRAMA +10A40..10A48 ; N # No [9] KHAROSHTHI DIGIT ONE..KHAROSHTHI FRACTION ONE HALF +10A50..10A58 ; N # Po [9] KHAROSHTHI PUNCTUATION DOT..KHAROSHTHI PUNCTUATION LINES +10A60..10A7C ; N # Lo [29] OLD SOUTH ARABIAN LETTER HE..OLD SOUTH ARABIAN LETTER THETH +10A7D..10A7E ; N # No [2] OLD SOUTH ARABIAN NUMBER ONE..OLD SOUTH ARABIAN NUMBER FIFTY +10A7F ; N # Po OLD SOUTH ARABIAN NUMERIC INDICATOR +10A80..10A9C ; N # Lo [29] OLD NORTH ARABIAN LETTER HEH..OLD NORTH ARABIAN LETTER ZAH +10A9D..10A9F ; N # No [3] OLD NORTH ARABIAN NUMBER ONE..OLD NORTH ARABIAN NUMBER TWENTY +10AC0..10AC7 ; N # Lo [8] MANICHAEAN LETTER ALEPH..MANICHAEAN LETTER WAW +10AC8 ; N # So MANICHAEAN SIGN UD +10AC9..10AE4 ; N # Lo [28] MANICHAEAN LETTER ZAYIN..MANICHAEAN LETTER TAW +10AE5..10AE6 ; N # Mn [2] MANICHAEAN ABBREVIATION MARK ABOVE..MANICHAEAN ABBREVIATION MARK BELOW +10AEB..10AEF ; N # No [5] MANICHAEAN NUMBER ONE..MANICHAEAN NUMBER ONE HUNDRED +10AF0..10AF6 ; N # Po [7] MANICHAEAN PUNCTUATION STAR..MANICHAEAN PUNCTUATION LINE FILLER +10B00..10B35 ; N # Lo [54] AVESTAN LETTER A..AVESTAN LETTER HE +10B39..10B3F ; N # Po [7] AVESTAN ABBREVIATION MARK..LARGE ONE RING OVER TWO RINGS PUNCTUATION +10B40..10B55 ; N # Lo [22] INSCRIPTIONAL PARTHIAN LETTER ALEPH..INSCRIPTIONAL PARTHIAN LETTER TAW +10B58..10B5F ; N # No [8] INSCRIPTIONAL PARTHIAN NUMBER ONE..INSCRIPTIONAL PARTHIAN NUMBER ONE THOUSAND +10B60..10B72 ; N # Lo [19] INSCRIPTIONAL PAHLAVI LETTER ALEPH..INSCRIPTIONAL PAHLAVI LETTER TAW +10B78..10B7F ; N # No [8] INSCRIPTIONAL PAHLAVI NUMBER ONE..INSCRIPTIONAL PAHLAVI NUMBER ONE THOUSAND +10B80..10B91 ; N # Lo [18] PSALTER PAHLAVI LETTER ALEPH..PSALTER PAHLAVI LETTER TAW +10B99..10B9C ; N # Po [4] PSALTER PAHLAVI SECTION MARK..PSALTER PAHLAVI FOUR DOTS WITH DOT +10BA9..10BAF ; N # No [7] PSALTER PAHLAVI NUMBER ONE..PSALTER PAHLAVI NUMBER ONE HUNDRED +10C00..10C48 ; N # Lo [73] OLD TURKIC LETTER ORKHON A..OLD TURKIC LETTER ORKHON BASH +10C80..10CB2 ; N # Lu [51] OLD HUNGARIAN CAPITAL LETTER A..OLD HUNGARIAN CAPITAL LETTER US +10CC0..10CF2 ; N # Ll [51] OLD HUNGARIAN SMALL LETTER A..OLD HUNGARIAN SMALL LETTER US +10CFA..10CFF ; N # No [6] OLD HUNGARIAN NUMBER ONE..OLD HUNGARIAN NUMBER ONE THOUSAND +10D00..10D23 ; N # Lo [36] HANIFI ROHINGYA LETTER A..HANIFI ROHINGYA MARK NA KHONNA +10D24..10D27 ; N # Mn [4] HANIFI ROHINGYA SIGN HARBAHAY..HANIFI ROHINGYA SIGN TASSI +10D30..10D39 ; N # Nd [10] HANIFI ROHINGYA DIGIT ZERO..HANIFI ROHINGYA DIGIT NINE +10E60..10E7E ; N # No [31] RUMI DIGIT ONE..RUMI FRACTION TWO THIRDS +10E80..10EA9 ; N # Lo [42] YEZIDI LETTER ELIF..YEZIDI LETTER ET +10EAB..10EAC ; N # Mn [2] YEZIDI COMBINING HAMZA MARK..YEZIDI COMBINING MADDA MARK +10EAD ; N # Pd YEZIDI HYPHENATION MARK +10EB0..10EB1 ; N # Lo [2] YEZIDI LETTER LAM WITH DOT ABOVE..YEZIDI LETTER YOT WITH CIRCUMFLEX ABOVE +10EFD..10EFF ; N # Mn [3] ARABIC SMALL LOW WORD SAKTA..ARABIC SMALL LOW WORD MADDA +10F00..10F1C ; N # Lo [29] OLD SOGDIAN LETTER ALEPH..OLD SOGDIAN LETTER FINAL TAW WITH VERTICAL TAIL +10F1D..10F26 ; N # No [10] OLD SOGDIAN NUMBER ONE..OLD SOGDIAN FRACTION ONE HALF +10F27 ; N # Lo OLD SOGDIAN LIGATURE AYIN-DALETH +10F30..10F45 ; N # Lo [22] SOGDIAN LETTER ALEPH..SOGDIAN INDEPENDENT SHIN +10F46..10F50 ; N # Mn [11] SOGDIAN COMBINING DOT BELOW..SOGDIAN COMBINING STROKE BELOW +10F51..10F54 ; N # No [4] SOGDIAN NUMBER ONE..SOGDIAN NUMBER ONE HUNDRED +10F55..10F59 ; N # Po [5] SOGDIAN PUNCTUATION TWO VERTICAL BARS..SOGDIAN PUNCTUATION HALF CIRCLE WITH DOT +10F70..10F81 ; N # Lo [18] OLD UYGHUR LETTER ALEPH..OLD UYGHUR LETTER LESH +10F82..10F85 ; N # Mn [4] OLD UYGHUR COMBINING DOT ABOVE..OLD UYGHUR COMBINING TWO DOTS BELOW +10F86..10F89 ; N # Po [4] OLD UYGHUR PUNCTUATION BAR..OLD UYGHUR PUNCTUATION FOUR DOTS +10FB0..10FC4 ; N # Lo [21] CHORASMIAN LETTER ALEPH..CHORASMIAN LETTER TAW +10FC5..10FCB ; N # No [7] CHORASMIAN NUMBER ONE..CHORASMIAN NUMBER ONE HUNDRED +10FE0..10FF6 ; N # Lo [23] ELYMAIC LETTER ALEPH..ELYMAIC LIGATURE ZAYIN-YODH +11000 ; N # Mc BRAHMI SIGN CANDRABINDU +11001 ; N # Mn BRAHMI SIGN ANUSVARA +11002 ; N # Mc BRAHMI SIGN VISARGA +11003..11037 ; N # Lo [53] BRAHMI SIGN JIHVAMULIYA..BRAHMI LETTER OLD TAMIL NNNA +11038..11046 ; N # Mn [15] BRAHMI VOWEL SIGN AA..BRAHMI VIRAMA +11047..1104D ; N # Po [7] BRAHMI DANDA..BRAHMI PUNCTUATION LOTUS +11052..11065 ; N # No [20] BRAHMI NUMBER ONE..BRAHMI NUMBER ONE THOUSAND +11066..1106F ; N # Nd [10] BRAHMI DIGIT ZERO..BRAHMI DIGIT NINE +11070 ; N # Mn BRAHMI SIGN OLD TAMIL VIRAMA +11071..11072 ; N # Lo [2] BRAHMI LETTER OLD TAMIL SHORT E..BRAHMI LETTER OLD TAMIL SHORT O +11073..11074 ; N # Mn [2] BRAHMI VOWEL SIGN OLD TAMIL SHORT E..BRAHMI VOWEL SIGN OLD TAMIL SHORT O +11075 ; N # Lo BRAHMI LETTER OLD TAMIL LLA +1107F ; N # Mn BRAHMI NUMBER JOINER +11080..11081 ; N # Mn [2] KAITHI SIGN CANDRABINDU..KAITHI SIGN ANUSVARA +11082 ; N # Mc KAITHI SIGN VISARGA +11083..110AF ; N # Lo [45] KAITHI LETTER A..KAITHI LETTER HA +110B0..110B2 ; N # Mc [3] KAITHI VOWEL SIGN AA..KAITHI VOWEL SIGN II +110B3..110B6 ; N # Mn [4] KAITHI VOWEL SIGN U..KAITHI VOWEL SIGN AI +110B7..110B8 ; N # Mc [2] KAITHI VOWEL SIGN O..KAITHI VOWEL SIGN AU +110B9..110BA ; N # Mn [2] KAITHI SIGN VIRAMA..KAITHI SIGN NUKTA +110BB..110BC ; N # Po [2] KAITHI ABBREVIATION SIGN..KAITHI ENUMERATION SIGN +110BD ; N # Cf KAITHI NUMBER SIGN +110BE..110C1 ; N # Po [4] KAITHI SECTION MARK..KAITHI DOUBLE DANDA +110C2 ; N # Mn KAITHI VOWEL SIGN VOCALIC R +110CD ; N # Cf KAITHI NUMBER SIGN ABOVE +110D0..110E8 ; N # Lo [25] SORA SOMPENG LETTER SAH..SORA SOMPENG LETTER MAE +110F0..110F9 ; N # Nd [10] SORA SOMPENG DIGIT ZERO..SORA SOMPENG DIGIT NINE +11100..11102 ; N # Mn [3] CHAKMA SIGN CANDRABINDU..CHAKMA SIGN VISARGA +11103..11126 ; N # Lo [36] CHAKMA LETTER AA..CHAKMA LETTER HAA +11127..1112B ; N # Mn [5] CHAKMA VOWEL SIGN A..CHAKMA VOWEL SIGN UU +1112C ; N # Mc CHAKMA VOWEL SIGN E +1112D..11134 ; N # Mn [8] CHAKMA VOWEL SIGN AI..CHAKMA MAAYYAA +11136..1113F ; N # Nd [10] CHAKMA DIGIT ZERO..CHAKMA DIGIT NINE +11140..11143 ; N # Po [4] CHAKMA SECTION MARK..CHAKMA QUESTION MARK +11144 ; N # Lo CHAKMA LETTER LHAA +11145..11146 ; N # Mc [2] CHAKMA VOWEL SIGN AA..CHAKMA VOWEL SIGN EI +11147 ; N # Lo CHAKMA LETTER VAA +11150..11172 ; N # Lo [35] MAHAJANI LETTER A..MAHAJANI LETTER RRA +11173 ; N # Mn MAHAJANI SIGN NUKTA +11174..11175 ; N # Po [2] MAHAJANI ABBREVIATION SIGN..MAHAJANI SECTION MARK +11176 ; N # Lo MAHAJANI LIGATURE SHRI +11180..11181 ; N # Mn [2] SHARADA SIGN CANDRABINDU..SHARADA SIGN ANUSVARA +11182 ; N # Mc SHARADA SIGN VISARGA +11183..111B2 ; N # Lo [48] SHARADA LETTER A..SHARADA LETTER HA +111B3..111B5 ; N # Mc [3] SHARADA VOWEL SIGN AA..SHARADA VOWEL SIGN II +111B6..111BE ; N # Mn [9] SHARADA VOWEL SIGN U..SHARADA VOWEL SIGN O +111BF..111C0 ; N # Mc [2] SHARADA VOWEL SIGN AU..SHARADA SIGN VIRAMA +111C1..111C4 ; N # Lo [4] SHARADA SIGN AVAGRAHA..SHARADA OM +111C5..111C8 ; N # Po [4] SHARADA DANDA..SHARADA SEPARATOR +111C9..111CC ; N # Mn [4] SHARADA SANDHI MARK..SHARADA EXTRA SHORT VOWEL MARK +111CD ; N # Po SHARADA SUTRA MARK +111CE ; N # Mc SHARADA VOWEL SIGN PRISHTHAMATRA E +111CF ; N # Mn SHARADA SIGN INVERTED CANDRABINDU +111D0..111D9 ; N # Nd [10] SHARADA DIGIT ZERO..SHARADA DIGIT NINE +111DA ; N # Lo SHARADA EKAM +111DB ; N # Po SHARADA SIGN SIDDHAM +111DC ; N # Lo SHARADA HEADSTROKE +111DD..111DF ; N # Po [3] SHARADA CONTINUATION SIGN..SHARADA SECTION MARK-2 +111E1..111F4 ; N # No [20] SINHALA ARCHAIC DIGIT ONE..SINHALA ARCHAIC NUMBER ONE THOUSAND +11200..11211 ; N # Lo [18] KHOJKI LETTER A..KHOJKI LETTER JJA +11213..1122B ; N # Lo [25] KHOJKI LETTER NYA..KHOJKI LETTER LLA +1122C..1122E ; N # Mc [3] KHOJKI VOWEL SIGN AA..KHOJKI VOWEL SIGN II +1122F..11231 ; N # Mn [3] KHOJKI VOWEL SIGN U..KHOJKI VOWEL SIGN AI +11232..11233 ; N # Mc [2] KHOJKI VOWEL SIGN O..KHOJKI VOWEL SIGN AU +11234 ; N # Mn KHOJKI SIGN ANUSVARA +11235 ; N # Mc KHOJKI SIGN VIRAMA +11236..11237 ; N # Mn [2] KHOJKI SIGN NUKTA..KHOJKI SIGN SHADDA +11238..1123D ; N # Po [6] KHOJKI DANDA..KHOJKI ABBREVIATION SIGN +1123E ; N # Mn KHOJKI SIGN SUKUN +1123F..11240 ; N # Lo [2] KHOJKI LETTER QA..KHOJKI LETTER SHORT I +11241 ; N # Mn KHOJKI VOWEL SIGN VOCALIC R +11280..11286 ; N # Lo [7] MULTANI LETTER A..MULTANI LETTER GA +11288 ; N # Lo MULTANI LETTER GHA +1128A..1128D ; N # Lo [4] MULTANI LETTER CA..MULTANI LETTER JJA +1128F..1129D ; N # Lo [15] MULTANI LETTER NYA..MULTANI LETTER BA +1129F..112A8 ; N # Lo [10] MULTANI LETTER BHA..MULTANI LETTER RHA +112A9 ; N # Po MULTANI SECTION MARK +112B0..112DE ; N # Lo [47] KHUDAWADI LETTER A..KHUDAWADI LETTER HA +112DF ; N # Mn KHUDAWADI SIGN ANUSVARA +112E0..112E2 ; N # Mc [3] KHUDAWADI VOWEL SIGN AA..KHUDAWADI VOWEL SIGN II +112E3..112EA ; N # Mn [8] KHUDAWADI VOWEL SIGN U..KHUDAWADI SIGN VIRAMA +112F0..112F9 ; N # Nd [10] KHUDAWADI DIGIT ZERO..KHUDAWADI DIGIT NINE +11300..11301 ; N # Mn [2] GRANTHA SIGN COMBINING ANUSVARA ABOVE..GRANTHA SIGN CANDRABINDU +11302..11303 ; N # Mc [2] GRANTHA SIGN ANUSVARA..GRANTHA SIGN VISARGA +11305..1130C ; N # Lo [8] GRANTHA LETTER A..GRANTHA LETTER VOCALIC L +1130F..11310 ; N # Lo [2] GRANTHA LETTER EE..GRANTHA LETTER AI +11313..11328 ; N # Lo [22] GRANTHA LETTER OO..GRANTHA LETTER NA +1132A..11330 ; N # Lo [7] GRANTHA LETTER PA..GRANTHA LETTER RA +11332..11333 ; N # Lo [2] GRANTHA LETTER LA..GRANTHA LETTER LLA +11335..11339 ; N # Lo [5] GRANTHA LETTER VA..GRANTHA LETTER HA +1133B..1133C ; N # Mn [2] COMBINING BINDU BELOW..GRANTHA SIGN NUKTA +1133D ; N # Lo GRANTHA SIGN AVAGRAHA +1133E..1133F ; N # Mc [2] GRANTHA VOWEL SIGN AA..GRANTHA VOWEL SIGN I +11340 ; N # Mn GRANTHA VOWEL SIGN II +11341..11344 ; N # Mc [4] GRANTHA VOWEL SIGN U..GRANTHA VOWEL SIGN VOCALIC RR +11347..11348 ; N # Mc [2] GRANTHA VOWEL SIGN EE..GRANTHA VOWEL SIGN AI +1134B..1134D ; N # Mc [3] GRANTHA VOWEL SIGN OO..GRANTHA SIGN VIRAMA +11350 ; N # Lo GRANTHA OM +11357 ; N # Mc GRANTHA AU LENGTH MARK +1135D..11361 ; N # Lo [5] GRANTHA SIGN PLUTA..GRANTHA LETTER VOCALIC LL +11362..11363 ; N # Mc [2] GRANTHA VOWEL SIGN VOCALIC L..GRANTHA VOWEL SIGN VOCALIC LL +11366..1136C ; N # Mn [7] COMBINING GRANTHA DIGIT ZERO..COMBINING GRANTHA DIGIT SIX +11370..11374 ; N # Mn [5] COMBINING GRANTHA LETTER A..COMBINING GRANTHA LETTER PA +11400..11434 ; N # Lo [53] NEWA LETTER A..NEWA LETTER HA +11435..11437 ; N # Mc [3] NEWA VOWEL SIGN AA..NEWA VOWEL SIGN II +11438..1143F ; N # Mn [8] NEWA VOWEL SIGN U..NEWA VOWEL SIGN AI +11440..11441 ; N # Mc [2] NEWA VOWEL SIGN O..NEWA VOWEL SIGN AU +11442..11444 ; N # Mn [3] NEWA SIGN VIRAMA..NEWA SIGN ANUSVARA +11445 ; N # Mc NEWA SIGN VISARGA +11446 ; N # Mn NEWA SIGN NUKTA +11447..1144A ; N # Lo [4] NEWA SIGN AVAGRAHA..NEWA SIDDHI +1144B..1144F ; N # Po [5] NEWA DANDA..NEWA ABBREVIATION SIGN +11450..11459 ; N # Nd [10] NEWA DIGIT ZERO..NEWA DIGIT NINE +1145A..1145B ; N # Po [2] NEWA DOUBLE COMMA..NEWA PLACEHOLDER MARK +1145D ; N # Po NEWA INSERTION SIGN +1145E ; N # Mn NEWA SANDHI MARK +1145F..11461 ; N # Lo [3] NEWA LETTER VEDIC ANUSVARA..NEWA SIGN UPADHMANIYA +11480..114AF ; N # Lo [48] TIRHUTA ANJI..TIRHUTA LETTER HA +114B0..114B2 ; N # Mc [3] TIRHUTA VOWEL SIGN AA..TIRHUTA VOWEL SIGN II +114B3..114B8 ; N # Mn [6] TIRHUTA VOWEL SIGN U..TIRHUTA VOWEL SIGN VOCALIC LL +114B9 ; N # Mc TIRHUTA VOWEL SIGN E +114BA ; N # Mn TIRHUTA VOWEL SIGN SHORT E +114BB..114BE ; N # Mc [4] TIRHUTA VOWEL SIGN AI..TIRHUTA VOWEL SIGN AU +114BF..114C0 ; N # Mn [2] TIRHUTA SIGN CANDRABINDU..TIRHUTA SIGN ANUSVARA +114C1 ; N # Mc TIRHUTA SIGN VISARGA +114C2..114C3 ; N # Mn [2] TIRHUTA SIGN VIRAMA..TIRHUTA SIGN NUKTA +114C4..114C5 ; N # Lo [2] TIRHUTA SIGN AVAGRAHA..TIRHUTA GVANG +114C6 ; N # Po TIRHUTA ABBREVIATION SIGN +114C7 ; N # Lo TIRHUTA OM +114D0..114D9 ; N # Nd [10] TIRHUTA DIGIT ZERO..TIRHUTA DIGIT NINE +11580..115AE ; N # Lo [47] SIDDHAM LETTER A..SIDDHAM LETTER HA +115AF..115B1 ; N # Mc [3] SIDDHAM VOWEL SIGN AA..SIDDHAM VOWEL SIGN II +115B2..115B5 ; N # Mn [4] SIDDHAM VOWEL SIGN U..SIDDHAM VOWEL SIGN VOCALIC RR +115B8..115BB ; N # Mc [4] SIDDHAM VOWEL SIGN E..SIDDHAM VOWEL SIGN AU +115BC..115BD ; N # Mn [2] SIDDHAM SIGN CANDRABINDU..SIDDHAM SIGN ANUSVARA +115BE ; N # Mc SIDDHAM SIGN VISARGA +115BF..115C0 ; N # Mn [2] SIDDHAM SIGN VIRAMA..SIDDHAM SIGN NUKTA +115C1..115D7 ; N # Po [23] SIDDHAM SIGN SIDDHAM..SIDDHAM SECTION MARK WITH CIRCLES AND FOUR ENCLOSURES +115D8..115DB ; N # Lo [4] SIDDHAM LETTER THREE-CIRCLE ALTERNATE I..SIDDHAM LETTER ALTERNATE U +115DC..115DD ; N # Mn [2] SIDDHAM VOWEL SIGN ALTERNATE U..SIDDHAM VOWEL SIGN ALTERNATE UU +11600..1162F ; N # Lo [48] MODI LETTER A..MODI LETTER LLA +11630..11632 ; N # Mc [3] MODI VOWEL SIGN AA..MODI VOWEL SIGN II +11633..1163A ; N # Mn [8] MODI VOWEL SIGN U..MODI VOWEL SIGN AI +1163B..1163C ; N # Mc [2] MODI VOWEL SIGN O..MODI VOWEL SIGN AU +1163D ; N # Mn MODI SIGN ANUSVARA +1163E ; N # Mc MODI SIGN VISARGA +1163F..11640 ; N # Mn [2] MODI SIGN VIRAMA..MODI SIGN ARDHACANDRA +11641..11643 ; N # Po [3] MODI DANDA..MODI ABBREVIATION SIGN +11644 ; N # Lo MODI SIGN HUVA +11650..11659 ; N # Nd [10] MODI DIGIT ZERO..MODI DIGIT NINE +11660..1166C ; N # Po [13] MONGOLIAN BIRGA WITH ORNAMENT..MONGOLIAN TURNED SWIRL BIRGA WITH DOUBLE ORNAMENT +11680..116AA ; N # Lo [43] TAKRI LETTER A..TAKRI LETTER RRA +116AB ; N # Mn TAKRI SIGN ANUSVARA +116AC ; N # Mc TAKRI SIGN VISARGA +116AD ; N # Mn TAKRI VOWEL SIGN AA +116AE..116AF ; N # Mc [2] TAKRI VOWEL SIGN I..TAKRI VOWEL SIGN II +116B0..116B5 ; N # Mn [6] TAKRI VOWEL SIGN U..TAKRI VOWEL SIGN AU +116B6 ; N # Mc TAKRI SIGN VIRAMA +116B7 ; N # Mn TAKRI SIGN NUKTA +116B8 ; N # Lo TAKRI LETTER ARCHAIC KHA +116B9 ; N # Po TAKRI ABBREVIATION SIGN +116C0..116C9 ; N # Nd [10] TAKRI DIGIT ZERO..TAKRI DIGIT NINE +11700..1171A ; N # Lo [27] AHOM LETTER KA..AHOM LETTER ALTERNATE BA +1171D..1171F ; N # Mn [3] AHOM CONSONANT SIGN MEDIAL LA..AHOM CONSONANT SIGN MEDIAL LIGATING RA +11720..11721 ; N # Mc [2] AHOM VOWEL SIGN A..AHOM VOWEL SIGN AA +11722..11725 ; N # Mn [4] AHOM VOWEL SIGN I..AHOM VOWEL SIGN UU +11726 ; N # Mc AHOM VOWEL SIGN E +11727..1172B ; N # Mn [5] AHOM VOWEL SIGN AW..AHOM SIGN KILLER +11730..11739 ; N # Nd [10] AHOM DIGIT ZERO..AHOM DIGIT NINE +1173A..1173B ; N # No [2] AHOM NUMBER TEN..AHOM NUMBER TWENTY +1173C..1173E ; N # Po [3] AHOM SIGN SMALL SECTION..AHOM SIGN RULAI +1173F ; N # So AHOM SYMBOL VI +11740..11746 ; N # Lo [7] AHOM LETTER CA..AHOM LETTER LLA +11800..1182B ; N # Lo [44] DOGRA LETTER A..DOGRA LETTER RRA +1182C..1182E ; N # Mc [3] DOGRA VOWEL SIGN AA..DOGRA VOWEL SIGN II +1182F..11837 ; N # Mn [9] DOGRA VOWEL SIGN U..DOGRA SIGN ANUSVARA +11838 ; N # Mc DOGRA SIGN VISARGA +11839..1183A ; N # Mn [2] DOGRA SIGN VIRAMA..DOGRA SIGN NUKTA +1183B ; N # Po DOGRA ABBREVIATION SIGN +118A0..118DF ; N # L& [64] WARANG CITI CAPITAL LETTER NGAA..WARANG CITI SMALL LETTER VIYO +118E0..118E9 ; N # Nd [10] WARANG CITI DIGIT ZERO..WARANG CITI DIGIT NINE +118EA..118F2 ; N # No [9] WARANG CITI NUMBER TEN..WARANG CITI NUMBER NINETY +118FF ; N # Lo WARANG CITI OM +11900..11906 ; N # Lo [7] DIVES AKURU LETTER A..DIVES AKURU LETTER E +11909 ; N # Lo DIVES AKURU LETTER O +1190C..11913 ; N # Lo [8] DIVES AKURU LETTER KA..DIVES AKURU LETTER JA +11915..11916 ; N # Lo [2] DIVES AKURU LETTER NYA..DIVES AKURU LETTER TTA +11918..1192F ; N # Lo [24] DIVES AKURU LETTER DDA..DIVES AKURU LETTER ZA +11930..11935 ; N # Mc [6] DIVES AKURU VOWEL SIGN AA..DIVES AKURU VOWEL SIGN E +11937..11938 ; N # Mc [2] DIVES AKURU VOWEL SIGN AI..DIVES AKURU VOWEL SIGN O +1193B..1193C ; N # Mn [2] DIVES AKURU SIGN ANUSVARA..DIVES AKURU SIGN CANDRABINDU +1193D ; N # Mc DIVES AKURU SIGN HALANTA +1193E ; N # Mn DIVES AKURU VIRAMA +1193F ; N # Lo DIVES AKURU PREFIXED NASAL SIGN +11940 ; N # Mc DIVES AKURU MEDIAL YA +11941 ; N # Lo DIVES AKURU INITIAL RA +11942 ; N # Mc DIVES AKURU MEDIAL RA +11943 ; N # Mn DIVES AKURU SIGN NUKTA +11944..11946 ; N # Po [3] DIVES AKURU DOUBLE DANDA..DIVES AKURU END OF TEXT MARK +11950..11959 ; N # Nd [10] DIVES AKURU DIGIT ZERO..DIVES AKURU DIGIT NINE +119A0..119A7 ; N # Lo [8] NANDINAGARI LETTER A..NANDINAGARI LETTER VOCALIC RR +119AA..119D0 ; N # Lo [39] NANDINAGARI LETTER E..NANDINAGARI LETTER RRA +119D1..119D3 ; N # Mc [3] NANDINAGARI VOWEL SIGN AA..NANDINAGARI VOWEL SIGN II +119D4..119D7 ; N # Mn [4] NANDINAGARI VOWEL SIGN U..NANDINAGARI VOWEL SIGN VOCALIC RR +119DA..119DB ; N # Mn [2] NANDINAGARI VOWEL SIGN E..NANDINAGARI VOWEL SIGN AI +119DC..119DF ; N # Mc [4] NANDINAGARI VOWEL SIGN O..NANDINAGARI SIGN VISARGA +119E0 ; N # Mn NANDINAGARI SIGN VIRAMA +119E1 ; N # Lo NANDINAGARI SIGN AVAGRAHA +119E2 ; N # Po NANDINAGARI SIGN SIDDHAM +119E3 ; N # Lo NANDINAGARI HEADSTROKE +119E4 ; N # Mc NANDINAGARI VOWEL SIGN PRISHTHAMATRA E +11A00 ; N # Lo ZANABAZAR SQUARE LETTER A +11A01..11A0A ; N # Mn [10] ZANABAZAR SQUARE VOWEL SIGN I..ZANABAZAR SQUARE VOWEL LENGTH MARK +11A0B..11A32 ; N # Lo [40] ZANABAZAR SQUARE LETTER KA..ZANABAZAR SQUARE LETTER KSSA +11A33..11A38 ; N # Mn [6] ZANABAZAR SQUARE FINAL CONSONANT MARK..ZANABAZAR SQUARE SIGN ANUSVARA +11A39 ; N # Mc ZANABAZAR SQUARE SIGN VISARGA +11A3A ; N # Lo ZANABAZAR SQUARE CLUSTER-INITIAL LETTER RA +11A3B..11A3E ; N # Mn [4] ZANABAZAR SQUARE CLUSTER-FINAL LETTER YA..ZANABAZAR SQUARE CLUSTER-FINAL LETTER VA +11A3F..11A46 ; N # Po [8] ZANABAZAR SQUARE INITIAL HEAD MARK..ZANABAZAR SQUARE CLOSING DOUBLE-LINED HEAD MARK +11A47 ; N # Mn ZANABAZAR SQUARE SUBJOINER +11A50 ; N # Lo SOYOMBO LETTER A +11A51..11A56 ; N # Mn [6] SOYOMBO VOWEL SIGN I..SOYOMBO VOWEL SIGN OE +11A57..11A58 ; N # Mc [2] SOYOMBO VOWEL SIGN AI..SOYOMBO VOWEL SIGN AU +11A59..11A5B ; N # Mn [3] SOYOMBO VOWEL SIGN VOCALIC R..SOYOMBO VOWEL LENGTH MARK +11A5C..11A89 ; N # Lo [46] SOYOMBO LETTER KA..SOYOMBO CLUSTER-INITIAL LETTER SA +11A8A..11A96 ; N # Mn [13] SOYOMBO FINAL CONSONANT SIGN G..SOYOMBO SIGN ANUSVARA +11A97 ; N # Mc SOYOMBO SIGN VISARGA +11A98..11A99 ; N # Mn [2] SOYOMBO GEMINATION MARK..SOYOMBO SUBJOINER +11A9A..11A9C ; N # Po [3] SOYOMBO MARK TSHEG..SOYOMBO MARK DOUBLE SHAD +11A9D ; N # Lo SOYOMBO MARK PLUTA +11A9E..11AA2 ; N # Po [5] SOYOMBO HEAD MARK WITH MOON AND SUN AND TRIPLE FLAME..SOYOMBO TERMINAL MARK-2 +11AB0..11ABF ; N # Lo [16] CANADIAN SYLLABICS NATTILIK HI..CANADIAN SYLLABICS SPA +11AC0..11AF8 ; N # Lo [57] PAU CIN HAU LETTER PA..PAU CIN HAU GLOTTAL STOP FINAL +11B00..11B09 ; N # Po [10] DEVANAGARI HEAD MARK..DEVANAGARI SIGN MINDU +11C00..11C08 ; N # Lo [9] BHAIKSUKI LETTER A..BHAIKSUKI LETTER VOCALIC L +11C0A..11C2E ; N # Lo [37] BHAIKSUKI LETTER E..BHAIKSUKI LETTER HA +11C2F ; N # Mc BHAIKSUKI VOWEL SIGN AA +11C30..11C36 ; N # Mn [7] BHAIKSUKI VOWEL SIGN I..BHAIKSUKI VOWEL SIGN VOCALIC L +11C38..11C3D ; N # Mn [6] BHAIKSUKI VOWEL SIGN E..BHAIKSUKI SIGN ANUSVARA +11C3E ; N # Mc BHAIKSUKI SIGN VISARGA +11C3F ; N # Mn BHAIKSUKI SIGN VIRAMA +11C40 ; N # Lo BHAIKSUKI SIGN AVAGRAHA +11C41..11C45 ; N # Po [5] BHAIKSUKI DANDA..BHAIKSUKI GAP FILLER-2 +11C50..11C59 ; N # Nd [10] BHAIKSUKI DIGIT ZERO..BHAIKSUKI DIGIT NINE +11C5A..11C6C ; N # No [19] BHAIKSUKI NUMBER ONE..BHAIKSUKI HUNDREDS UNIT MARK +11C70..11C71 ; N # Po [2] MARCHEN HEAD MARK..MARCHEN MARK SHAD +11C72..11C8F ; N # Lo [30] MARCHEN LETTER KA..MARCHEN LETTER A +11C92..11CA7 ; N # Mn [22] MARCHEN SUBJOINED LETTER KA..MARCHEN SUBJOINED LETTER ZA +11CA9 ; N # Mc MARCHEN SUBJOINED LETTER YA +11CAA..11CB0 ; N # Mn [7] MARCHEN SUBJOINED LETTER RA..MARCHEN VOWEL SIGN AA +11CB1 ; N # Mc MARCHEN VOWEL SIGN I +11CB2..11CB3 ; N # Mn [2] MARCHEN VOWEL SIGN U..MARCHEN VOWEL SIGN E +11CB4 ; N # Mc MARCHEN VOWEL SIGN O +11CB5..11CB6 ; N # Mn [2] MARCHEN SIGN ANUSVARA..MARCHEN SIGN CANDRABINDU +11D00..11D06 ; N # Lo [7] MASARAM GONDI LETTER A..MASARAM GONDI LETTER E +11D08..11D09 ; N # Lo [2] MASARAM GONDI LETTER AI..MASARAM GONDI LETTER O +11D0B..11D30 ; N # Lo [38] MASARAM GONDI LETTER AU..MASARAM GONDI LETTER TRA +11D31..11D36 ; N # Mn [6] MASARAM GONDI VOWEL SIGN AA..MASARAM GONDI VOWEL SIGN VOCALIC R +11D3A ; N # Mn MASARAM GONDI VOWEL SIGN E +11D3C..11D3D ; N # Mn [2] MASARAM GONDI VOWEL SIGN AI..MASARAM GONDI VOWEL SIGN O +11D3F..11D45 ; N # Mn [7] MASARAM GONDI VOWEL SIGN AU..MASARAM GONDI VIRAMA +11D46 ; N # Lo MASARAM GONDI REPHA +11D47 ; N # Mn MASARAM GONDI RA-KARA +11D50..11D59 ; N # Nd [10] MASARAM GONDI DIGIT ZERO..MASARAM GONDI DIGIT NINE +11D60..11D65 ; N # Lo [6] GUNJALA GONDI LETTER A..GUNJALA GONDI LETTER UU +11D67..11D68 ; N # Lo [2] GUNJALA GONDI LETTER EE..GUNJALA GONDI LETTER AI +11D6A..11D89 ; N # Lo [32] GUNJALA GONDI LETTER OO..GUNJALA GONDI LETTER SA +11D8A..11D8E ; N # Mc [5] GUNJALA GONDI VOWEL SIGN AA..GUNJALA GONDI VOWEL SIGN UU +11D90..11D91 ; N # Mn [2] GUNJALA GONDI VOWEL SIGN EE..GUNJALA GONDI VOWEL SIGN AI +11D93..11D94 ; N # Mc [2] GUNJALA GONDI VOWEL SIGN OO..GUNJALA GONDI VOWEL SIGN AU +11D95 ; N # Mn GUNJALA GONDI SIGN ANUSVARA +11D96 ; N # Mc GUNJALA GONDI SIGN VISARGA +11D97 ; N # Mn GUNJALA GONDI VIRAMA +11D98 ; N # Lo GUNJALA GONDI OM +11DA0..11DA9 ; N # Nd [10] GUNJALA GONDI DIGIT ZERO..GUNJALA GONDI DIGIT NINE +11EE0..11EF2 ; N # Lo [19] MAKASAR LETTER KA..MAKASAR ANGKA +11EF3..11EF4 ; N # Mn [2] MAKASAR VOWEL SIGN I..MAKASAR VOWEL SIGN U +11EF5..11EF6 ; N # Mc [2] MAKASAR VOWEL SIGN E..MAKASAR VOWEL SIGN O +11EF7..11EF8 ; N # Po [2] MAKASAR PASSIMBANG..MAKASAR END OF SECTION +11F00..11F01 ; N # Mn [2] KAWI SIGN CANDRABINDU..KAWI SIGN ANUSVARA +11F02 ; N # Lo KAWI SIGN REPHA +11F03 ; N # Mc KAWI SIGN VISARGA +11F04..11F10 ; N # Lo [13] KAWI LETTER A..KAWI LETTER O +11F12..11F33 ; N # Lo [34] KAWI LETTER KA..KAWI LETTER JNYA +11F34..11F35 ; N # Mc [2] KAWI VOWEL SIGN AA..KAWI VOWEL SIGN ALTERNATE AA +11F36..11F3A ; N # Mn [5] KAWI VOWEL SIGN I..KAWI VOWEL SIGN VOCALIC R +11F3E..11F3F ; N # Mc [2] KAWI VOWEL SIGN E..KAWI VOWEL SIGN AI +11F40 ; N # Mn KAWI VOWEL SIGN EU +11F41 ; N # Mc KAWI SIGN KILLER +11F42 ; N # Mn KAWI CONJOINER +11F43..11F4F ; N # Po [13] KAWI DANDA..KAWI PUNCTUATION CLOSING SPIRAL +11F50..11F59 ; N # Nd [10] KAWI DIGIT ZERO..KAWI DIGIT NINE +11FB0 ; N # Lo LISU LETTER YHA +11FC0..11FD4 ; N # No [21] TAMIL FRACTION ONE THREE-HUNDRED-AND-TWENTIETH..TAMIL FRACTION DOWNSCALING FACTOR KIIZH +11FD5..11FDC ; N # So [8] TAMIL SIGN NEL..TAMIL SIGN MUKKURUNI +11FDD..11FE0 ; N # Sc [4] TAMIL SIGN KAACU..TAMIL SIGN VARAAKAN +11FE1..11FF1 ; N # So [17] TAMIL SIGN PAARAM..TAMIL SIGN VAKAIYARAA +11FFF ; N # Po TAMIL PUNCTUATION END OF TEXT +12000..12399 ; N # Lo [922] CUNEIFORM SIGN A..CUNEIFORM SIGN U U +12400..1246E ; N # Nl [111] CUNEIFORM NUMERIC SIGN TWO ASH..CUNEIFORM NUMERIC SIGN NINE U VARIANT FORM +12470..12474 ; N # Po [5] CUNEIFORM PUNCTUATION SIGN OLD ASSYRIAN WORD DIVIDER..CUNEIFORM PUNCTUATION SIGN DIAGONAL QUADCOLON +12480..12543 ; N # Lo [196] CUNEIFORM SIGN AB TIMES NUN TENU..CUNEIFORM SIGN ZU5 TIMES THREE DISH TENU +12F90..12FF0 ; N # Lo [97] CYPRO-MINOAN SIGN CM001..CYPRO-MINOAN SIGN CM114 +12FF1..12FF2 ; N # Po [2] CYPRO-MINOAN SIGN CM301..CYPRO-MINOAN SIGN CM302 +13000..1342F ; N # Lo [1072] EGYPTIAN HIEROGLYPH A001..EGYPTIAN HIEROGLYPH V011D +13430..1343F ; N # Cf [16] EGYPTIAN HIEROGLYPH VERTICAL JOINER..EGYPTIAN HIEROGLYPH END WALLED ENCLOSURE +13440 ; N # Mn EGYPTIAN HIEROGLYPH MIRROR HORIZONTALLY +13441..13446 ; N # Lo [6] EGYPTIAN HIEROGLYPH FULL BLANK..EGYPTIAN HIEROGLYPH WIDE LOST SIGN +13447..13455 ; N # Mn [15] EGYPTIAN HIEROGLYPH MODIFIER DAMAGED AT TOP START..EGYPTIAN HIEROGLYPH MODIFIER DAMAGED +14400..14646 ; N # Lo [583] ANATOLIAN HIEROGLYPH A001..ANATOLIAN HIEROGLYPH A530 +16800..16A38 ; N # Lo [569] BAMUM LETTER PHASE-A NGKUE MFON..BAMUM LETTER PHASE-F VUEQ +16A40..16A5E ; N # Lo [31] MRO LETTER TA..MRO LETTER TEK +16A60..16A69 ; N # Nd [10] MRO DIGIT ZERO..MRO DIGIT NINE +16A6E..16A6F ; N # Po [2] MRO DANDA..MRO DOUBLE DANDA +16A70..16ABE ; N # Lo [79] TANGSA LETTER OZ..TANGSA LETTER ZA +16AC0..16AC9 ; N # Nd [10] TANGSA DIGIT ZERO..TANGSA DIGIT NINE +16AD0..16AED ; N # Lo [30] BASSA VAH LETTER ENNI..BASSA VAH LETTER I +16AF0..16AF4 ; N # Mn [5] BASSA VAH COMBINING HIGH TONE..BASSA VAH COMBINING HIGH-LOW TONE +16AF5 ; N # Po BASSA VAH FULL STOP +16B00..16B2F ; N # Lo [48] PAHAWH HMONG VOWEL KEEB..PAHAWH HMONG CONSONANT CAU +16B30..16B36 ; N # Mn [7] PAHAWH HMONG MARK CIM TUB..PAHAWH HMONG MARK CIM TAUM +16B37..16B3B ; N # Po [5] PAHAWH HMONG SIGN VOS THOM..PAHAWH HMONG SIGN VOS FEEM +16B3C..16B3F ; N # So [4] PAHAWH HMONG SIGN XYEEM NTXIV..PAHAWH HMONG SIGN XYEEM FAIB +16B40..16B43 ; N # Lm [4] PAHAWH HMONG SIGN VOS SEEV..PAHAWH HMONG SIGN IB YAM +16B44 ; N # Po PAHAWH HMONG SIGN XAUS +16B45 ; N # So PAHAWH HMONG SIGN CIM TSOV ROG +16B50..16B59 ; N # Nd [10] PAHAWH HMONG DIGIT ZERO..PAHAWH HMONG DIGIT NINE +16B5B..16B61 ; N # No [7] PAHAWH HMONG NUMBER TENS..PAHAWH HMONG NUMBER TRILLIONS +16B63..16B77 ; N # Lo [21] PAHAWH HMONG SIGN VOS LUB..PAHAWH HMONG SIGN CIM NRES TOS +16B7D..16B8F ; N # Lo [19] PAHAWH HMONG CLAN SIGN TSHEEJ..PAHAWH HMONG CLAN SIGN VWJ +16E40..16E7F ; N # L& [64] MEDEFAIDRIN CAPITAL LETTER M..MEDEFAIDRIN SMALL LETTER Y +16E80..16E96 ; N # No [23] MEDEFAIDRIN DIGIT ZERO..MEDEFAIDRIN DIGIT THREE ALTERNATE FORM +16E97..16E9A ; N # Po [4] MEDEFAIDRIN COMMA..MEDEFAIDRIN EXCLAMATION OH +16F00..16F4A ; N # Lo [75] MIAO LETTER PA..MIAO LETTER RTE +16F4F ; N # Mn MIAO SIGN CONSONANT MODIFIER BAR +16F50 ; N # Lo MIAO LETTER NASALIZATION +16F51..16F87 ; N # Mc [55] MIAO SIGN ASPIRATION..MIAO VOWEL SIGN UI +16F8F..16F92 ; N # Mn [4] MIAO TONE RIGHT..MIAO TONE BELOW +16F93..16F9F ; N # Lm [13] MIAO LETTER TONE-2..MIAO LETTER REFORMED TONE-8 +16FE0..16FE1 ; W # Lm [2] TANGUT ITERATION MARK..NUSHU ITERATION MARK +16FE2 ; W # Po OLD CHINESE HOOK MARK +16FE3 ; W # Lm OLD CHINESE ITERATION MARK +16FE4 ; W # Mn KHITAN SMALL SCRIPT FILLER +16FF0..16FF1 ; W # Mc [2] VIETNAMESE ALTERNATE READING MARK CA..VIETNAMESE ALTERNATE READING MARK NHAY +17000..187F7 ; W # Lo [6136] TANGUT IDEOGRAPH-17000..TANGUT IDEOGRAPH-187F7 +18800..18AFF ; W # Lo [768] TANGUT COMPONENT-001..TANGUT COMPONENT-768 +18B00..18CD5 ; W # Lo [470] KHITAN SMALL SCRIPT CHARACTER-18B00..KHITAN SMALL SCRIPT CHARACTER-18CD5 +18D00..18D08 ; W # Lo [9] TANGUT IDEOGRAPH-18D00..TANGUT IDEOGRAPH-18D08 +1AFF0..1AFF3 ; W # Lm [4] KATAKANA LETTER MINNAN TONE-2..KATAKANA LETTER MINNAN TONE-5 +1AFF5..1AFFB ; W # Lm [7] KATAKANA LETTER MINNAN TONE-7..KATAKANA LETTER MINNAN NASALIZED TONE-5 +1AFFD..1AFFE ; W # Lm [2] KATAKANA LETTER MINNAN NASALIZED TONE-7..KATAKANA LETTER MINNAN NASALIZED TONE-8 +1B000..1B0FF ; W # Lo [256] KATAKANA LETTER ARCHAIC E..HENTAIGANA LETTER RE-2 +1B100..1B122 ; W # Lo [35] HENTAIGANA LETTER RE-3..KATAKANA LETTER ARCHAIC WU +1B132 ; W # Lo HIRAGANA LETTER SMALL KO +1B150..1B152 ; W # Lo [3] HIRAGANA LETTER SMALL WI..HIRAGANA LETTER SMALL WO +1B155 ; W # Lo KATAKANA LETTER SMALL KO +1B164..1B167 ; W # Lo [4] KATAKANA LETTER SMALL WI..KATAKANA LETTER SMALL N +1B170..1B2FB ; W # Lo [396] NUSHU CHARACTER-1B170..NUSHU CHARACTER-1B2FB +1BC00..1BC6A ; N # Lo [107] DUPLOYAN LETTER H..DUPLOYAN LETTER VOCALIC M +1BC70..1BC7C ; N # Lo [13] DUPLOYAN AFFIX LEFT HORIZONTAL SECANT..DUPLOYAN AFFIX ATTACHED TANGENT HOOK +1BC80..1BC88 ; N # Lo [9] DUPLOYAN AFFIX HIGH ACUTE..DUPLOYAN AFFIX HIGH VERTICAL +1BC90..1BC99 ; N # Lo [10] DUPLOYAN AFFIX LOW ACUTE..DUPLOYAN AFFIX LOW ARROW +1BC9C ; N # So DUPLOYAN SIGN O WITH CROSS +1BC9D..1BC9E ; N # Mn [2] DUPLOYAN THICK LETTER SELECTOR..DUPLOYAN DOUBLE MARK +1BC9F ; N # Po DUPLOYAN PUNCTUATION CHINOOK FULL STOP +1BCA0..1BCA3 ; N # Cf [4] SHORTHAND FORMAT LETTER OVERLAP..SHORTHAND FORMAT UP STEP +1CF00..1CF2D ; N # Mn [46] ZNAMENNY COMBINING MARK GORAZDO NIZKO S KRYZHEM ON LEFT..ZNAMENNY COMBINING MARK KRYZH ON LEFT +1CF30..1CF46 ; N # Mn [23] ZNAMENNY COMBINING TONAL RANGE MARK MRACHNO..ZNAMENNY PRIZNAK MODIFIER ROG +1CF50..1CFC3 ; N # So [116] ZNAMENNY NEUME KRYUK..ZNAMENNY NEUME PAUK +1D000..1D0F5 ; N # So [246] BYZANTINE MUSICAL SYMBOL PSILI..BYZANTINE MUSICAL SYMBOL GORGON NEO KATO +1D100..1D126 ; N # So [39] MUSICAL SYMBOL SINGLE BARLINE..MUSICAL SYMBOL DRUM CLEF-2 +1D129..1D164 ; N # So [60] MUSICAL SYMBOL MULTIPLE MEASURE REST..MUSICAL SYMBOL ONE HUNDRED TWENTY-EIGHTH NOTE +1D165..1D166 ; N # Mc [2] MUSICAL SYMBOL COMBINING STEM..MUSICAL SYMBOL COMBINING SPRECHGESANG STEM +1D167..1D169 ; N # Mn [3] MUSICAL SYMBOL COMBINING TREMOLO-1..MUSICAL SYMBOL COMBINING TREMOLO-3 +1D16A..1D16C ; N # So [3] MUSICAL SYMBOL FINGERED TREMOLO-1..MUSICAL SYMBOL FINGERED TREMOLO-3 +1D16D..1D172 ; N # Mc [6] MUSICAL SYMBOL COMBINING AUGMENTATION DOT..MUSICAL SYMBOL COMBINING FLAG-5 +1D173..1D17A ; N # Cf [8] MUSICAL SYMBOL BEGIN BEAM..MUSICAL SYMBOL END PHRASE +1D17B..1D182 ; N # Mn [8] MUSICAL SYMBOL COMBINING ACCENT..MUSICAL SYMBOL COMBINING LOURE +1D183..1D184 ; N # So [2] MUSICAL SYMBOL ARPEGGIATO UP..MUSICAL SYMBOL ARPEGGIATO DOWN +1D185..1D18B ; N # Mn [7] MUSICAL SYMBOL COMBINING DOIT..MUSICAL SYMBOL COMBINING TRIPLE TONGUE +1D18C..1D1A9 ; N # So [30] MUSICAL SYMBOL RINFORZANDO..MUSICAL SYMBOL DEGREE SLASH +1D1AA..1D1AD ; N # Mn [4] MUSICAL SYMBOL COMBINING DOWN BOW..MUSICAL SYMBOL COMBINING SNAP PIZZICATO +1D1AE..1D1EA ; N # So [61] MUSICAL SYMBOL PEDAL MARK..MUSICAL SYMBOL KORON +1D200..1D241 ; N # So [66] GREEK VOCAL NOTATION SYMBOL-1..GREEK INSTRUMENTAL NOTATION SYMBOL-54 +1D242..1D244 ; N # Mn [3] COMBINING GREEK MUSICAL TRISEME..COMBINING GREEK MUSICAL PENTASEME +1D245 ; N # So GREEK MUSICAL LEIMMA +1D2C0..1D2D3 ; N # No [20] KAKTOVIK NUMERAL ZERO..KAKTOVIK NUMERAL NINETEEN +1D2E0..1D2F3 ; N # No [20] MAYAN NUMERAL ZERO..MAYAN NUMERAL NINETEEN +1D300..1D356 ; N # So [87] MONOGRAM FOR EARTH..TETRAGRAM FOR FOSTERING +1D360..1D378 ; N # No [25] COUNTING ROD UNIT DIGIT ONE..TALLY MARK FIVE +1D400..1D454 ; N # L& [85] MATHEMATICAL BOLD CAPITAL A..MATHEMATICAL ITALIC SMALL G +1D456..1D49C ; N # L& [71] MATHEMATICAL ITALIC SMALL I..MATHEMATICAL SCRIPT CAPITAL A +1D49E..1D49F ; N # Lu [2] MATHEMATICAL SCRIPT CAPITAL C..MATHEMATICAL SCRIPT CAPITAL D +1D4A2 ; N # Lu MATHEMATICAL SCRIPT CAPITAL G +1D4A5..1D4A6 ; N # Lu [2] MATHEMATICAL SCRIPT CAPITAL J..MATHEMATICAL SCRIPT CAPITAL K +1D4A9..1D4AC ; N # Lu [4] MATHEMATICAL SCRIPT CAPITAL N..MATHEMATICAL SCRIPT CAPITAL Q +1D4AE..1D4B9 ; N # L& [12] MATHEMATICAL SCRIPT CAPITAL S..MATHEMATICAL SCRIPT SMALL D +1D4BB ; N # Ll MATHEMATICAL SCRIPT SMALL F +1D4BD..1D4C3 ; N # Ll [7] MATHEMATICAL SCRIPT SMALL H..MATHEMATICAL SCRIPT SMALL N +1D4C5..1D505 ; N # L& [65] MATHEMATICAL SCRIPT SMALL P..MATHEMATICAL FRAKTUR CAPITAL B +1D507..1D50A ; N # Lu [4] MATHEMATICAL FRAKTUR CAPITAL D..MATHEMATICAL FRAKTUR CAPITAL G +1D50D..1D514 ; N # Lu [8] MATHEMATICAL FRAKTUR CAPITAL J..MATHEMATICAL FRAKTUR CAPITAL Q +1D516..1D51C ; N # Lu [7] MATHEMATICAL FRAKTUR CAPITAL S..MATHEMATICAL FRAKTUR CAPITAL Y +1D51E..1D539 ; N # L& [28] MATHEMATICAL FRAKTUR SMALL A..MATHEMATICAL DOUBLE-STRUCK CAPITAL B +1D53B..1D53E ; N # Lu [4] MATHEMATICAL DOUBLE-STRUCK CAPITAL D..MATHEMATICAL DOUBLE-STRUCK CAPITAL G +1D540..1D544 ; N # Lu [5] MATHEMATICAL DOUBLE-STRUCK CAPITAL I..MATHEMATICAL DOUBLE-STRUCK CAPITAL M +1D546 ; N # Lu MATHEMATICAL DOUBLE-STRUCK CAPITAL O +1D54A..1D550 ; N # Lu [7] MATHEMATICAL DOUBLE-STRUCK CAPITAL S..MATHEMATICAL DOUBLE-STRUCK CAPITAL Y +1D552..1D6A5 ; N # L& [340] MATHEMATICAL DOUBLE-STRUCK SMALL A..MATHEMATICAL ITALIC SMALL DOTLESS J +1D6A8..1D6C0 ; N # Lu [25] MATHEMATICAL BOLD CAPITAL ALPHA..MATHEMATICAL BOLD CAPITAL OMEGA +1D6C1 ; N # Sm MATHEMATICAL BOLD NABLA +1D6C2..1D6DA ; N # Ll [25] MATHEMATICAL BOLD SMALL ALPHA..MATHEMATICAL BOLD SMALL OMEGA +1D6DB ; N # Sm MATHEMATICAL BOLD PARTIAL DIFFERENTIAL +1D6DC..1D6FA ; N # L& [31] MATHEMATICAL BOLD EPSILON SYMBOL..MATHEMATICAL ITALIC CAPITAL OMEGA +1D6FB ; N # Sm MATHEMATICAL ITALIC NABLA +1D6FC..1D714 ; N # Ll [25] MATHEMATICAL ITALIC SMALL ALPHA..MATHEMATICAL ITALIC SMALL OMEGA +1D715 ; N # Sm MATHEMATICAL ITALIC PARTIAL DIFFERENTIAL +1D716..1D734 ; N # L& [31] MATHEMATICAL ITALIC EPSILON SYMBOL..MATHEMATICAL BOLD ITALIC CAPITAL OMEGA +1D735 ; N # Sm MATHEMATICAL BOLD ITALIC NABLA +1D736..1D74E ; N # Ll [25] MATHEMATICAL BOLD ITALIC SMALL ALPHA..MATHEMATICAL BOLD ITALIC SMALL OMEGA +1D74F ; N # Sm MATHEMATICAL BOLD ITALIC PARTIAL DIFFERENTIAL +1D750..1D76E ; N # L& [31] MATHEMATICAL BOLD ITALIC EPSILON SYMBOL..MATHEMATICAL SANS-SERIF BOLD CAPITAL OMEGA +1D76F ; N # Sm MATHEMATICAL SANS-SERIF BOLD NABLA +1D770..1D788 ; N # Ll [25] MATHEMATICAL SANS-SERIF BOLD SMALL ALPHA..MATHEMATICAL SANS-SERIF BOLD SMALL OMEGA +1D789 ; N # Sm MATHEMATICAL SANS-SERIF BOLD PARTIAL DIFFERENTIAL +1D78A..1D7A8 ; N # L& [31] MATHEMATICAL SANS-SERIF BOLD EPSILON SYMBOL..MATHEMATICAL SANS-SERIF BOLD ITALIC CAPITAL OMEGA +1D7A9 ; N # Sm MATHEMATICAL SANS-SERIF BOLD ITALIC NABLA +1D7AA..1D7C2 ; N # Ll [25] MATHEMATICAL SANS-SERIF BOLD ITALIC SMALL ALPHA..MATHEMATICAL SANS-SERIF BOLD ITALIC SMALL OMEGA +1D7C3 ; N # Sm MATHEMATICAL SANS-SERIF BOLD ITALIC PARTIAL DIFFERENTIAL +1D7C4..1D7CB ; N # L& [8] MATHEMATICAL SANS-SERIF BOLD ITALIC EPSILON SYMBOL..MATHEMATICAL BOLD SMALL DIGAMMA +1D7CE..1D7FF ; N # Nd [50] MATHEMATICAL BOLD DIGIT ZERO..MATHEMATICAL MONOSPACE DIGIT NINE +1D800..1D9FF ; N # So [512] SIGNWRITING HAND-FIST INDEX..SIGNWRITING HEAD +1DA00..1DA36 ; N # Mn [55] SIGNWRITING HEAD RIM..SIGNWRITING AIR SUCKING IN +1DA37..1DA3A ; N # So [4] SIGNWRITING AIR BLOW SMALL ROTATIONS..SIGNWRITING BREATH EXHALE +1DA3B..1DA6C ; N # Mn [50] SIGNWRITING MOUTH CLOSED NEUTRAL..SIGNWRITING EXCITEMENT +1DA6D..1DA74 ; N # So [8] SIGNWRITING SHOULDER HIP SPINE..SIGNWRITING TORSO-FLOORPLANE TWISTING +1DA75 ; N # Mn SIGNWRITING UPPER BODY TILTING FROM HIP JOINTS +1DA76..1DA83 ; N # So [14] SIGNWRITING LIMB COMBINATION..SIGNWRITING LOCATION DEPTH +1DA84 ; N # Mn SIGNWRITING LOCATION HEAD NECK +1DA85..1DA86 ; N # So [2] SIGNWRITING LOCATION TORSO..SIGNWRITING LOCATION LIMBS DIGITS +1DA87..1DA8B ; N # Po [5] SIGNWRITING COMMA..SIGNWRITING PARENTHESIS +1DA9B..1DA9F ; N # Mn [5] SIGNWRITING FILL MODIFIER-2..SIGNWRITING FILL MODIFIER-6 +1DAA1..1DAAF ; N # Mn [15] SIGNWRITING ROTATION MODIFIER-2..SIGNWRITING ROTATION MODIFIER-16 +1DF00..1DF09 ; N # Ll [10] LATIN SMALL LETTER FENG DIGRAPH WITH TRILL..LATIN SMALL LETTER T WITH HOOK AND RETROFLEX HOOK +1DF0A ; N # Lo LATIN LETTER RETROFLEX CLICK WITH RETROFLEX HOOK +1DF0B..1DF1E ; N # Ll [20] LATIN SMALL LETTER ESH WITH DOUBLE BAR..LATIN SMALL LETTER S WITH CURL +1DF25..1DF2A ; N # Ll [6] LATIN SMALL LETTER D WITH MID-HEIGHT LEFT HOOK..LATIN SMALL LETTER T WITH MID-HEIGHT LEFT HOOK +1E000..1E006 ; N # Mn [7] COMBINING GLAGOLITIC LETTER AZU..COMBINING GLAGOLITIC LETTER ZHIVETE +1E008..1E018 ; N # Mn [17] COMBINING GLAGOLITIC LETTER ZEMLJA..COMBINING GLAGOLITIC LETTER HERU +1E01B..1E021 ; N # Mn [7] COMBINING GLAGOLITIC LETTER SHTA..COMBINING GLAGOLITIC LETTER YATI +1E023..1E024 ; N # Mn [2] COMBINING GLAGOLITIC LETTER YU..COMBINING GLAGOLITIC LETTER SMALL YUS +1E026..1E02A ; N # Mn [5] COMBINING GLAGOLITIC LETTER YO..COMBINING GLAGOLITIC LETTER FITA +1E030..1E06D ; N # Lm [62] MODIFIER LETTER CYRILLIC SMALL A..MODIFIER LETTER CYRILLIC SMALL STRAIGHT U WITH STROKE +1E08F ; N # Mn COMBINING CYRILLIC SMALL LETTER BYELORUSSIAN-UKRAINIAN I +1E100..1E12C ; N # Lo [45] NYIAKENG PUACHUE HMONG LETTER MA..NYIAKENG PUACHUE HMONG LETTER W +1E130..1E136 ; N # Mn [7] NYIAKENG PUACHUE HMONG TONE-B..NYIAKENG PUACHUE HMONG TONE-D +1E137..1E13D ; N # Lm [7] NYIAKENG PUACHUE HMONG SIGN FOR PERSON..NYIAKENG PUACHUE HMONG SYLLABLE LENGTHENER +1E140..1E149 ; N # Nd [10] NYIAKENG PUACHUE HMONG DIGIT ZERO..NYIAKENG PUACHUE HMONG DIGIT NINE +1E14E ; N # Lo NYIAKENG PUACHUE HMONG LOGOGRAM NYAJ +1E14F ; N # So NYIAKENG PUACHUE HMONG CIRCLED CA +1E290..1E2AD ; N # Lo [30] TOTO LETTER PA..TOTO LETTER A +1E2AE ; N # Mn TOTO SIGN RISING TONE +1E2C0..1E2EB ; N # Lo [44] WANCHO LETTER AA..WANCHO LETTER YIH +1E2EC..1E2EF ; N # Mn [4] WANCHO TONE TUP..WANCHO TONE KOINI +1E2F0..1E2F9 ; N # Nd [10] WANCHO DIGIT ZERO..WANCHO DIGIT NINE +1E2FF ; N # Sc WANCHO NGUN SIGN +1E4D0..1E4EA ; N # Lo [27] NAG MUNDARI LETTER O..NAG MUNDARI LETTER ELL +1E4EB ; N # Lm NAG MUNDARI SIGN OJOD +1E4EC..1E4EF ; N # Mn [4] NAG MUNDARI SIGN MUHOR..NAG MUNDARI SIGN SUTUH +1E4F0..1E4F9 ; N # Nd [10] NAG MUNDARI DIGIT ZERO..NAG MUNDARI DIGIT NINE +1E7E0..1E7E6 ; N # Lo [7] ETHIOPIC SYLLABLE HHYA..ETHIOPIC SYLLABLE HHYO +1E7E8..1E7EB ; N # Lo [4] ETHIOPIC SYLLABLE GURAGE HHWA..ETHIOPIC SYLLABLE HHWE +1E7ED..1E7EE ; N # Lo [2] ETHIOPIC SYLLABLE GURAGE MWI..ETHIOPIC SYLLABLE GURAGE MWEE +1E7F0..1E7FE ; N # Lo [15] ETHIOPIC SYLLABLE GURAGE QWI..ETHIOPIC SYLLABLE GURAGE PWEE +1E800..1E8C4 ; N # Lo [197] MENDE KIKAKUI SYLLABLE M001 KI..MENDE KIKAKUI SYLLABLE M060 NYON +1E8C7..1E8CF ; N # No [9] MENDE KIKAKUI DIGIT ONE..MENDE KIKAKUI DIGIT NINE +1E8D0..1E8D6 ; N # Mn [7] MENDE KIKAKUI COMBINING NUMBER TEENS..MENDE KIKAKUI COMBINING NUMBER MILLIONS +1E900..1E943 ; N # L& [68] ADLAM CAPITAL LETTER ALIF..ADLAM SMALL LETTER SHA +1E944..1E94A ; N # Mn [7] ADLAM ALIF LENGTHENER..ADLAM NUKTA +1E94B ; N # Lm ADLAM NASALIZATION MARK +1E950..1E959 ; N # Nd [10] ADLAM DIGIT ZERO..ADLAM DIGIT NINE +1E95E..1E95F ; N # Po [2] ADLAM INITIAL EXCLAMATION MARK..ADLAM INITIAL QUESTION MARK +1EC71..1ECAB ; N # No [59] INDIC SIYAQ NUMBER ONE..INDIC SIYAQ NUMBER PREFIXED NINE +1ECAC ; N # So INDIC SIYAQ PLACEHOLDER +1ECAD..1ECAF ; N # No [3] INDIC SIYAQ FRACTION ONE QUARTER..INDIC SIYAQ FRACTION THREE QUARTERS +1ECB0 ; N # Sc INDIC SIYAQ RUPEE MARK +1ECB1..1ECB4 ; N # No [4] INDIC SIYAQ NUMBER ALTERNATE ONE..INDIC SIYAQ ALTERNATE LAKH MARK +1ED01..1ED2D ; N # No [45] OTTOMAN SIYAQ NUMBER ONE..OTTOMAN SIYAQ NUMBER NINETY THOUSAND +1ED2E ; N # So OTTOMAN SIYAQ MARRATAN +1ED2F..1ED3D ; N # No [15] OTTOMAN SIYAQ ALTERNATE NUMBER TWO..OTTOMAN SIYAQ FRACTION ONE SIXTH +1EE00..1EE03 ; N # Lo [4] ARABIC MATHEMATICAL ALEF..ARABIC MATHEMATICAL DAL +1EE05..1EE1F ; N # Lo [27] ARABIC MATHEMATICAL WAW..ARABIC MATHEMATICAL DOTLESS QAF +1EE21..1EE22 ; N # Lo [2] ARABIC MATHEMATICAL INITIAL BEH..ARABIC MATHEMATICAL INITIAL JEEM +1EE24 ; N # Lo ARABIC MATHEMATICAL INITIAL HEH +1EE27 ; N # Lo ARABIC MATHEMATICAL INITIAL HAH +1EE29..1EE32 ; N # Lo [10] ARABIC MATHEMATICAL INITIAL YEH..ARABIC MATHEMATICAL INITIAL QAF +1EE34..1EE37 ; N # Lo [4] ARABIC MATHEMATICAL INITIAL SHEEN..ARABIC MATHEMATICAL INITIAL KHAH +1EE39 ; N # Lo ARABIC MATHEMATICAL INITIAL DAD +1EE3B ; N # Lo ARABIC MATHEMATICAL INITIAL GHAIN +1EE42 ; N # Lo ARABIC MATHEMATICAL TAILED JEEM +1EE47 ; N # Lo ARABIC MATHEMATICAL TAILED HAH +1EE49 ; N # Lo ARABIC MATHEMATICAL TAILED YEH +1EE4B ; N # Lo ARABIC MATHEMATICAL TAILED LAM +1EE4D..1EE4F ; N # Lo [3] ARABIC MATHEMATICAL TAILED NOON..ARABIC MATHEMATICAL TAILED AIN +1EE51..1EE52 ; N # Lo [2] ARABIC MATHEMATICAL TAILED SAD..ARABIC MATHEMATICAL TAILED QAF +1EE54 ; N # Lo ARABIC MATHEMATICAL TAILED SHEEN +1EE57 ; N # Lo ARABIC MATHEMATICAL TAILED KHAH +1EE59 ; N # Lo ARABIC MATHEMATICAL TAILED DAD +1EE5B ; N # Lo ARABIC MATHEMATICAL TAILED GHAIN +1EE5D ; N # Lo ARABIC MATHEMATICAL TAILED DOTLESS NOON +1EE5F ; N # Lo ARABIC MATHEMATICAL TAILED DOTLESS QAF +1EE61..1EE62 ; N # Lo [2] ARABIC MATHEMATICAL STRETCHED BEH..ARABIC MATHEMATICAL STRETCHED JEEM +1EE64 ; N # Lo ARABIC MATHEMATICAL STRETCHED HEH +1EE67..1EE6A ; N # Lo [4] ARABIC MATHEMATICAL STRETCHED HAH..ARABIC MATHEMATICAL STRETCHED KAF +1EE6C..1EE72 ; N # Lo [7] ARABIC MATHEMATICAL STRETCHED MEEM..ARABIC MATHEMATICAL STRETCHED QAF +1EE74..1EE77 ; N # Lo [4] ARABIC MATHEMATICAL STRETCHED SHEEN..ARABIC MATHEMATICAL STRETCHED KHAH +1EE79..1EE7C ; N # Lo [4] ARABIC MATHEMATICAL STRETCHED DAD..ARABIC MATHEMATICAL STRETCHED DOTLESS BEH +1EE7E ; N # Lo ARABIC MATHEMATICAL STRETCHED DOTLESS FEH +1EE80..1EE89 ; N # Lo [10] ARABIC MATHEMATICAL LOOPED ALEF..ARABIC MATHEMATICAL LOOPED YEH +1EE8B..1EE9B ; N # Lo [17] ARABIC MATHEMATICAL LOOPED LAM..ARABIC MATHEMATICAL LOOPED GHAIN +1EEA1..1EEA3 ; N # Lo [3] ARABIC MATHEMATICAL DOUBLE-STRUCK BEH..ARABIC MATHEMATICAL DOUBLE-STRUCK DAL +1EEA5..1EEA9 ; N # Lo [5] ARABIC MATHEMATICAL DOUBLE-STRUCK WAW..ARABIC MATHEMATICAL DOUBLE-STRUCK YEH +1EEAB..1EEBB ; N # Lo [17] ARABIC MATHEMATICAL DOUBLE-STRUCK LAM..ARABIC MATHEMATICAL DOUBLE-STRUCK GHAIN +1EEF0..1EEF1 ; N # Sm [2] ARABIC MATHEMATICAL OPERATOR MEEM WITH HAH WITH TATWEEL..ARABIC MATHEMATICAL OPERATOR HAH WITH DAL +1F000..1F003 ; N # So [4] MAHJONG TILE EAST WIND..MAHJONG TILE NORTH WIND +1F004 ; W # So MAHJONG TILE RED DRAGON +1F005..1F02B ; N # So [39] MAHJONG TILE GREEN DRAGON..MAHJONG TILE BACK +1F030..1F093 ; N # So [100] DOMINO TILE HORIZONTAL BACK..DOMINO TILE VERTICAL-06-06 +1F0A0..1F0AE ; N # So [15] PLAYING CARD BACK..PLAYING CARD KING OF SPADES +1F0B1..1F0BF ; N # So [15] PLAYING CARD ACE OF HEARTS..PLAYING CARD RED JOKER +1F0C1..1F0CE ; N # So [14] PLAYING CARD ACE OF DIAMONDS..PLAYING CARD KING OF DIAMONDS +1F0CF ; W # So PLAYING CARD BLACK JOKER +1F0D1..1F0F5 ; N # So [37] PLAYING CARD ACE OF CLUBS..PLAYING CARD TRUMP-21 +1F100..1F10A ; A # No [11] DIGIT ZERO FULL STOP..DIGIT NINE COMMA +1F10B..1F10C ; N # No [2] DINGBAT CIRCLED SANS-SERIF DIGIT ZERO..DINGBAT NEGATIVE CIRCLED SANS-SERIF DIGIT ZERO +1F10D..1F10F ; N # So [3] CIRCLED ZERO WITH SLASH..CIRCLED DOLLAR SIGN WITH OVERLAID BACKSLASH +1F110..1F12D ; A # So [30] PARENTHESIZED LATIN CAPITAL LETTER A..CIRCLED CD +1F12E..1F12F ; N # So [2] CIRCLED WZ..COPYLEFT SYMBOL +1F130..1F169 ; A # So [58] SQUARED LATIN CAPITAL LETTER A..NEGATIVE CIRCLED LATIN CAPITAL LETTER Z +1F16A..1F16F ; N # So [6] RAISED MC SIGN..CIRCLED HUMAN FIGURE +1F170..1F18D ; A # So [30] NEGATIVE SQUARED LATIN CAPITAL LETTER A..NEGATIVE SQUARED SA +1F18E ; W # So NEGATIVE SQUARED AB +1F18F..1F190 ; A # So [2] NEGATIVE SQUARED WC..SQUARE DJ +1F191..1F19A ; W # So [10] SQUARED CL..SQUARED VS +1F19B..1F1AC ; A # So [18] SQUARED THREE D..SQUARED VOD +1F1AD ; N # So MASK WORK SYMBOL +1F1E6..1F1FF ; N # So [26] REGIONAL INDICATOR SYMBOL LETTER A..REGIONAL INDICATOR SYMBOL LETTER Z +1F200..1F202 ; W # So [3] SQUARE HIRAGANA HOKA..SQUARED KATAKANA SA +1F210..1F23B ; W # So [44] SQUARED CJK UNIFIED IDEOGRAPH-624B..SQUARED CJK UNIFIED IDEOGRAPH-914D +1F240..1F248 ; W # So [9] TORTOISE SHELL BRACKETED CJK UNIFIED IDEOGRAPH-672C..TORTOISE SHELL BRACKETED CJK UNIFIED IDEOGRAPH-6557 +1F250..1F251 ; W # So [2] CIRCLED IDEOGRAPH ADVANTAGE..CIRCLED IDEOGRAPH ACCEPT +1F260..1F265 ; W # So [6] ROUNDED SYMBOL FOR FU..ROUNDED SYMBOL FOR CAI +1F300..1F320 ; W # So [33] CYCLONE..SHOOTING STAR +1F321..1F32C ; N # So [12] THERMOMETER..WIND BLOWING FACE +1F32D..1F335 ; W # So [9] HOT DOG..CACTUS +1F336 ; N # So HOT PEPPER +1F337..1F37C ; W # So [70] TULIP..BABY BOTTLE +1F37D ; N # So FORK AND KNIFE WITH PLATE +1F37E..1F393 ; W # So [22] BOTTLE WITH POPPING CORK..GRADUATION CAP +1F394..1F39F ; N # So [12] HEART WITH TIP ON THE LEFT..ADMISSION TICKETS +1F3A0..1F3CA ; W # So [43] CAROUSEL HORSE..SWIMMER +1F3CB..1F3CE ; N # So [4] WEIGHT LIFTER..RACING CAR +1F3CF..1F3D3 ; W # So [5] CRICKET BAT AND BALL..TABLE TENNIS PADDLE AND BALL +1F3D4..1F3DF ; N # So [12] SNOW CAPPED MOUNTAIN..STADIUM +1F3E0..1F3F0 ; W # So [17] HOUSE BUILDING..EUROPEAN CASTLE +1F3F1..1F3F3 ; N # So [3] WHITE PENNANT..WAVING WHITE FLAG +1F3F4 ; W # So WAVING BLACK FLAG +1F3F5..1F3F7 ; N # So [3] ROSETTE..LABEL +1F3F8..1F3FA ; W # So [3] BADMINTON RACQUET AND SHUTTLECOCK..AMPHORA +1F3FB..1F3FF ; W # Sk [5] EMOJI MODIFIER FITZPATRICK TYPE-1-2..EMOJI MODIFIER FITZPATRICK TYPE-6 +1F400..1F43E ; W # So [63] RAT..PAW PRINTS +1F43F ; N # So CHIPMUNK +1F440 ; W # So EYES +1F441 ; N # So EYE +1F442..1F4FC ; W # So [187] EAR..VIDEOCASSETTE +1F4FD..1F4FE ; N # So [2] FILM PROJECTOR..PORTABLE STEREO +1F4FF..1F53D ; W # So [63] PRAYER BEADS..DOWN-POINTING SMALL RED TRIANGLE +1F53E..1F54A ; N # So [13] LOWER RIGHT SHADOWED WHITE CIRCLE..DOVE OF PEACE +1F54B..1F54E ; W # So [4] KAABA..MENORAH WITH NINE BRANCHES +1F54F ; N # So BOWL OF HYGIEIA +1F550..1F567 ; W # So [24] CLOCK FACE ONE OCLOCK..CLOCK FACE TWELVE-THIRTY +1F568..1F579 ; N # So [18] RIGHT SPEAKER..JOYSTICK +1F57A ; W # So MAN DANCING +1F57B..1F594 ; N # So [26] LEFT HAND TELEPHONE RECEIVER..REVERSED VICTORY HAND +1F595..1F596 ; W # So [2] REVERSED HAND WITH MIDDLE FINGER EXTENDED..RAISED HAND WITH PART BETWEEN MIDDLE AND RING FINGERS +1F597..1F5A3 ; N # So [13] WHITE DOWN POINTING LEFT HAND INDEX..BLACK DOWN POINTING BACKHAND INDEX +1F5A4 ; W # So BLACK HEART +1F5A5..1F5FA ; N # So [86] DESKTOP COMPUTER..WORLD MAP +1F5FB..1F5FF ; W # So [5] MOUNT FUJI..MOYAI +1F600..1F64F ; W # So [80] GRINNING FACE..PERSON WITH FOLDED HANDS +1F650..1F67F ; N # So [48] NORTH WEST POINTING LEAF..REVERSE CHECKER BOARD +1F680..1F6C5 ; W # So [70] ROCKET..LEFT LUGGAGE +1F6C6..1F6CB ; N # So [6] TRIANGLE WITH ROUNDED CORNERS..COUCH AND LAMP +1F6CC ; W # So SLEEPING ACCOMMODATION +1F6CD..1F6CF ; N # So [3] SHOPPING BAGS..BED +1F6D0..1F6D2 ; W # So [3] PLACE OF WORSHIP..SHOPPING TROLLEY +1F6D3..1F6D4 ; N # So [2] STUPA..PAGODA +1F6D5..1F6D7 ; W # So [3] HINDU TEMPLE..ELEVATOR +1F6DC..1F6DF ; W # So [4] WIRELESS..RING BUOY +1F6E0..1F6EA ; N # So [11] HAMMER AND WRENCH..NORTHEAST-POINTING AIRPLANE +1F6EB..1F6EC ; W # So [2] AIRPLANE DEPARTURE..AIRPLANE ARRIVING +1F6F0..1F6F3 ; N # So [4] SATELLITE..PASSENGER SHIP +1F6F4..1F6FC ; W # So [9] SCOOTER..ROLLER SKATE +1F700..1F776 ; N # So [119] ALCHEMICAL SYMBOL FOR QUINTESSENCE..LUNAR ECLIPSE +1F77B..1F77F ; N # So [5] HAUMEA..ORCUS +1F780..1F7D9 ; N # So [90] BLACK LEFT-POINTING ISOSCELES RIGHT TRIANGLE..NINE POINTED WHITE STAR +1F7E0..1F7EB ; W # So [12] LARGE ORANGE CIRCLE..LARGE BROWN SQUARE +1F7F0 ; W # So HEAVY EQUALS SIGN +1F800..1F80B ; N # So [12] LEFTWARDS ARROW WITH SMALL TRIANGLE ARROWHEAD..DOWNWARDS ARROW WITH LARGE TRIANGLE ARROWHEAD +1F810..1F847 ; N # So [56] LEFTWARDS ARROW WITH SMALL EQUILATERAL ARROWHEAD..DOWNWARDS HEAVY ARROW +1F850..1F859 ; N # So [10] LEFTWARDS SANS-SERIF ARROW..UP DOWN SANS-SERIF ARROW +1F860..1F887 ; N # So [40] WIDE-HEADED LEFTWARDS LIGHT BARB ARROW..WIDE-HEADED SOUTH WEST VERY HEAVY BARB ARROW +1F890..1F8AD ; N # So [30] LEFTWARDS TRIANGLE ARROWHEAD..WHITE ARROW SHAFT WIDTH TWO THIRDS +1F8B0..1F8B1 ; N # So [2] ARROW POINTING UPWARDS THEN NORTH WEST..ARROW POINTING RIGHTWARDS THEN CURVING SOUTH WEST +1F900..1F90B ; N # So [12] CIRCLED CROSS FORMEE WITH FOUR DOTS..DOWNWARD FACING NOTCHED HOOK WITH DOT +1F90C..1F93A ; W # So [47] PINCHED FINGERS..FENCER +1F93B ; N # So MODERN PENTATHLON +1F93C..1F945 ; W # So [10] WRESTLERS..GOAL NET +1F946 ; N # So RIFLE +1F947..1F9FF ; W # So [185] FIRST PLACE MEDAL..NAZAR AMULET +1FA00..1FA53 ; N # So [84] NEUTRAL CHESS KING..BLACK CHESS KNIGHT-BISHOP +1FA60..1FA6D ; N # So [14] XIANGQI RED GENERAL..XIANGQI BLACK SOLDIER +1FA70..1FA7C ; W # So [13] BALLET SHOES..CRUTCH +1FA80..1FA88 ; W # So [9] YO-YO..FLUTE +1FA90..1FABD ; W # So [46] RINGED PLANET..WING +1FABF..1FAC5 ; W # So [7] GOOSE..PERSON WITH CROWN +1FACE..1FADB ; W # So [14] MOOSE..PEA POD +1FAE0..1FAE8 ; W # So [9] MELTING FACE..SHAKING FACE +1FAF0..1FAF8 ; W # So [9] HAND WITH INDEX FINGER AND THUMB CROSSED..RIGHTWARDS PUSHING HAND +1FB00..1FB92 ; N # So [147] BLOCK SEXTANT-1..UPPER HALF INVERSE MEDIUM SHADE AND LOWER HALF BLOCK +1FB94..1FBCA ; N # So [55] LEFT HALF INVERSE MEDIUM SHADE AND RIGHT HALF BLOCK..WHITE UP-POINTING CHEVRON +1FBF0..1FBF9 ; N # Nd [10] SEGMENTED DIGIT ZERO..SEGMENTED DIGIT NINE +20000..2A6DF ; W # Lo [42720] CJK UNIFIED IDEOGRAPH-20000..CJK UNIFIED IDEOGRAPH-2A6DF +2A6E0..2A6FF ; W # Cn [32] .. +2A700..2B739 ; W # Lo [4154] CJK UNIFIED IDEOGRAPH-2A700..CJK UNIFIED IDEOGRAPH-2B739 +2B73A..2B73F ; W # Cn [6] .. +2B740..2B81D ; W # Lo [222] CJK UNIFIED IDEOGRAPH-2B740..CJK UNIFIED IDEOGRAPH-2B81D +2B81E..2B81F ; W # Cn [2] .. +2B820..2CEA1 ; W # Lo [5762] CJK UNIFIED IDEOGRAPH-2B820..CJK UNIFIED IDEOGRAPH-2CEA1 +2CEA2..2CEAF ; W # Cn [14] .. +2CEB0..2EBE0 ; W # Lo [7473] CJK UNIFIED IDEOGRAPH-2CEB0..CJK UNIFIED IDEOGRAPH-2EBE0 +2EBE1..2EBEF ; W # Cn [15] .. +2EBF0..2EE5D ; W # Lo [622] CJK UNIFIED IDEOGRAPH-2EBF0..CJK UNIFIED IDEOGRAPH-2EE5D +2EE5E..2F7FF ; W # Cn [2466] .. +2F800..2FA1D ; W # Lo [542] CJK COMPATIBILITY IDEOGRAPH-2F800..CJK COMPATIBILITY IDEOGRAPH-2FA1D +2FA1E..2FA1F ; W # Cn [2] .. +2FA20..2FFFD ; W # Cn [1502] .. +30000..3134A ; W # Lo [4939] CJK UNIFIED IDEOGRAPH-30000..CJK UNIFIED IDEOGRAPH-3134A +3134B..3134F ; W # Cn [5] .. +31350..323AF ; W # Lo [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF +323B0..3FFFD ; W # Cn [56398] .. +E0001 ; N # Cf LANGUAGE TAG +E0020..E007F ; N # Cf [96] TAG SPACE..CANCEL TAG +E0100..E01EF ; A # Mn [240] VARIATION SELECTOR-17..VARIATION SELECTOR-256 +F0000..FFFFD ; A # Co [65534] .. +100000..10FFFD ; A # Co [65534] .. # EOF diff --git a/libcxx/utils/data/unicode/GraphemeBreakProperty.txt b/libcxx/utils/data/unicode/GraphemeBreakProperty.txt index a12b5eef1efc..12453cbdb54a 100644 --- a/libcxx/utils/data/unicode/GraphemeBreakProperty.txt +++ b/libcxx/utils/data/unicode/GraphemeBreakProperty.txt @@ -1,6 +1,6 @@ -# GraphemeBreakProperty-15.0.0.txt -# Date: 2022-04-27, 17:07:38 GMT -# © 2022 Unicode®, Inc. +# GraphemeBreakProperty-15.1.0.txt +# Date: 2023-01-05, 20:34:41 GMT +# © 2023 Unicode®, Inc. # Unicode and the Unicode Logo are registered trademarks of Unicode, Inc. in the U.S. and other countries. # For terms of use, see https://www.unicode.org/terms_of_use.html # diff --git a/libcxx/utils/data/unicode/GraphemeBreakTest.txt b/libcxx/utils/data/unicode/GraphemeBreakTest.txt index 3c73f97b7b82..4c1ed512e451 100644 --- a/libcxx/utils/data/unicode/GraphemeBreakTest.txt +++ b/libcxx/utils/data/unicode/GraphemeBreakTest.txt @@ -1,6 +1,6 @@ -# GraphemeBreakTest-15.0.0.txt -# Date: 2022-02-26, 00:38:37 GMT -# © 2022 Unicode®, Inc. +# GraphemeBreakTest-15.1.0.txt +# Date: 2023-08-07, 15:52:55 GMT +# © 2023 Unicode®, Inc. # Unicode and the Unicode Logo are registered trademarks of Unicode, Inc. in the U.S. and other countries. # For terms of use, see https://www.unicode.org/terms_of_use.html # @@ -36,8 +36,8 @@ ÷ 0020 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 0020 ÷ 0600 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 0020 × 0308 ÷ 0600 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0020 × 0903 ÷ # ÷ [0.2] SPACE (Other) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0020 × 0308 × 0903 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0020 × 0A03 ÷ # ÷ [0.2] SPACE (Other) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0020 × 0308 × 0A03 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 0020 ÷ 1100 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0020 × 0308 ÷ 1100 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0020 ÷ 1160 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -48,10 +48,24 @@ ÷ 0020 × 0308 ÷ AC00 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 0020 ÷ AC01 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 0020 × 0308 ÷ AC01 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0020 × 0900 ÷ # ÷ [0.2] SPACE (Other) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 × 0308 × 0900 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 × 0903 ÷ # ÷ [0.2] SPACE (Other) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 × 0308 × 0903 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 ÷ 0904 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 × 0308 ÷ 0904 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 ÷ 0D4E ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 × 0308 ÷ 0D4E ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0020 ÷ 0915 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0020 × 0308 ÷ 0915 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 0020 ÷ 231A ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0020 × 0308 ÷ 231A ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0020 × 0300 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 0020 × 0308 × 0300 ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0020 × 093C ÷ # ÷ [0.2] SPACE (Other) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0020 × 0308 × 093C ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0020 × 094D ÷ # ÷ [0.2] SPACE (Other) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0020 × 0308 × 094D ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 0020 × 200D ÷ # ÷ [0.2] SPACE (Other) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0020 × 0308 × 200D ÷ # ÷ [0.2] SPACE (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0020 ÷ 0378 ÷ # ÷ [0.2] SPACE (Other) ÷ [999.0] (Other) ÷ [0.3] @@ -70,8 +84,8 @@ ÷ 000D ÷ 0308 ÷ 1F1E6 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 000D ÷ 0600 ÷ # ÷ [0.2] (CR) ÷ [4.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 000D ÷ 0308 ÷ 0600 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 000D ÷ 0903 ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 000D ÷ 0308 × 0903 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 000D ÷ 0A03 ÷ # ÷ [0.2] (CR) ÷ [4.0] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 000D ÷ 0308 × 0A03 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 000D ÷ 1100 ÷ # ÷ [0.2] (CR) ÷ [4.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 000D ÷ 0308 ÷ 1100 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 000D ÷ 1160 ÷ # ÷ [0.2] (CR) ÷ [4.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -82,10 +96,24 @@ ÷ 000D ÷ 0308 ÷ AC00 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 000D ÷ AC01 ÷ # ÷ [0.2] (CR) ÷ [4.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 000D ÷ 0308 ÷ AC01 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 000D ÷ 0900 ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0308 × 0900 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0903 ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0308 × 0903 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0904 ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0308 ÷ 0904 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0D4E ÷ # ÷ [0.2] (CR) ÷ [4.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0308 ÷ 0D4E ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000D ÷ 0915 ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 000D ÷ 0308 ÷ 0915 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 000D ÷ 231A ÷ # ÷ [0.2] (CR) ÷ [4.0] WATCH (ExtPict) ÷ [0.3] ÷ 000D ÷ 0308 ÷ 231A ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 000D ÷ 0300 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 000D ÷ 0308 × 0300 ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 000D ÷ 093C ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 000D ÷ 0308 × 093C ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 000D ÷ 094D ÷ # ÷ [0.2] (CR) ÷ [4.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 000D ÷ 0308 × 094D ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 000D ÷ 200D ÷ # ÷ [0.2] (CR) ÷ [4.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 000D ÷ 0308 × 200D ÷ # ÷ [0.2] (CR) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 000D ÷ 0378 ÷ # ÷ [0.2] (CR) ÷ [4.0] (Other) ÷ [0.3] @@ -104,8 +132,8 @@ ÷ 000A ÷ 0308 ÷ 1F1E6 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 000A ÷ 0600 ÷ # ÷ [0.2] (LF) ÷ [4.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 000A ÷ 0308 ÷ 0600 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 000A ÷ 0903 ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 000A ÷ 0308 × 0903 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 000A ÷ 0A03 ÷ # ÷ [0.2] (LF) ÷ [4.0] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 000A ÷ 0308 × 0A03 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 000A ÷ 1100 ÷ # ÷ [0.2] (LF) ÷ [4.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 000A ÷ 0308 ÷ 1100 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 000A ÷ 1160 ÷ # ÷ [0.2] (LF) ÷ [4.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -116,10 +144,24 @@ ÷ 000A ÷ 0308 ÷ AC00 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 000A ÷ AC01 ÷ # ÷ [0.2] (LF) ÷ [4.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 000A ÷ 0308 ÷ AC01 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 000A ÷ 0900 ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0308 × 0900 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0903 ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0308 × 0903 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0904 ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0308 ÷ 0904 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0D4E ÷ # ÷ [0.2] (LF) ÷ [4.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0308 ÷ 0D4E ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 000A ÷ 0915 ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 000A ÷ 0308 ÷ 0915 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 000A ÷ 231A ÷ # ÷ [0.2] (LF) ÷ [4.0] WATCH (ExtPict) ÷ [0.3] ÷ 000A ÷ 0308 ÷ 231A ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 000A ÷ 0300 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 000A ÷ 0308 × 0300 ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 000A ÷ 093C ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 000A ÷ 0308 × 093C ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 000A ÷ 094D ÷ # ÷ [0.2] (LF) ÷ [4.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 000A ÷ 0308 × 094D ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 000A ÷ 200D ÷ # ÷ [0.2] (LF) ÷ [4.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 000A ÷ 0308 × 200D ÷ # ÷ [0.2] (LF) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 000A ÷ 0378 ÷ # ÷ [0.2] (LF) ÷ [4.0] (Other) ÷ [0.3] @@ -138,8 +180,8 @@ ÷ 0001 ÷ 0308 ÷ 1F1E6 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 0001 ÷ 0600 ÷ # ÷ [0.2] (Control) ÷ [4.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 0001 ÷ 0308 ÷ 0600 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0001 ÷ 0903 ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0001 ÷ 0308 × 0903 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0001 ÷ 0A03 ÷ # ÷ [0.2] (Control) ÷ [4.0] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0001 ÷ 0308 × 0A03 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 0001 ÷ 1100 ÷ # ÷ [0.2] (Control) ÷ [4.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0001 ÷ 0308 ÷ 1100 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0001 ÷ 1160 ÷ # ÷ [0.2] (Control) ÷ [4.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -150,10 +192,24 @@ ÷ 0001 ÷ 0308 ÷ AC00 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 0001 ÷ AC01 ÷ # ÷ [0.2] (Control) ÷ [4.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 0001 ÷ 0308 ÷ AC01 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0001 ÷ 0900 ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0308 × 0900 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0903 ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0308 × 0903 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0904 ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0308 ÷ 0904 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0D4E ÷ # ÷ [0.2] (Control) ÷ [4.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0308 ÷ 0D4E ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0001 ÷ 0915 ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0001 ÷ 0308 ÷ 0915 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 0001 ÷ 231A ÷ # ÷ [0.2] (Control) ÷ [4.0] WATCH (ExtPict) ÷ [0.3] ÷ 0001 ÷ 0308 ÷ 231A ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0001 ÷ 0300 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 0001 ÷ 0308 × 0300 ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0001 ÷ 093C ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0001 ÷ 0308 × 093C ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0001 ÷ 094D ÷ # ÷ [0.2] (Control) ÷ [4.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0001 ÷ 0308 × 094D ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 0001 ÷ 200D ÷ # ÷ [0.2] (Control) ÷ [4.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0001 ÷ 0308 × 200D ÷ # ÷ [0.2] (Control) ÷ [4.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0001 ÷ 0378 ÷ # ÷ [0.2] (Control) ÷ [4.0] (Other) ÷ [0.3] @@ -172,8 +228,8 @@ ÷ 034F × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 034F ÷ 0600 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 034F × 0308 ÷ 0600 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 034F × 0903 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 034F × 0308 × 0903 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 034F × 0A03 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 034F × 0308 × 0A03 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 034F ÷ 1100 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 034F × 0308 ÷ 1100 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 034F ÷ 1160 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -184,10 +240,24 @@ ÷ 034F × 0308 ÷ AC00 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 034F ÷ AC01 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 034F × 0308 ÷ AC01 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 034F × 0900 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 034F × 0308 × 0900 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 034F × 0903 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 034F × 0308 × 0903 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 034F ÷ 0904 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 034F × 0308 ÷ 0904 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 034F ÷ 0D4E ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 034F × 0308 ÷ 0D4E ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 034F ÷ 0915 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 034F × 0308 ÷ 0915 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 034F ÷ 231A ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 034F × 0308 ÷ 231A ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 034F × 0300 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 034F × 0308 × 0300 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 034F × 093C ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 034F × 0308 × 093C ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 034F × 094D ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 034F × 0308 × 094D ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 034F × 200D ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 034F × 0308 × 200D ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 034F ÷ 0378 ÷ # ÷ [0.2] COMBINING GRAPHEME JOINER (Extend) ÷ [999.0] (Other) ÷ [0.3] @@ -206,8 +276,8 @@ ÷ 1F1E6 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 1F1E6 ÷ 0600 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 1F1E6 × 0308 ÷ 0600 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 1F1E6 × 0903 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 1F1E6 × 0308 × 0903 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 1F1E6 × 0A03 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 1F1E6 × 0308 × 0A03 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 1F1E6 ÷ 1100 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 1F1E6 × 0308 ÷ 1100 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 1F1E6 ÷ 1160 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -218,10 +288,24 @@ ÷ 1F1E6 × 0308 ÷ AC00 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 1F1E6 ÷ AC01 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 1F1E6 × 0308 ÷ AC01 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 1F1E6 × 0900 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 × 0308 × 0900 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 × 0903 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 × 0308 × 0903 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 ÷ 0904 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 × 0308 ÷ 0904 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 ÷ 0D4E ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 × 0308 ÷ 0D4E ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1F1E6 ÷ 0915 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 1F1E6 × 0308 ÷ 0915 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 1F1E6 ÷ 231A ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 1F1E6 × 0308 ÷ 231A ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 1F1E6 × 0300 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 1F1E6 × 0308 × 0300 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 1F1E6 × 093C ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 1F1E6 × 0308 × 093C ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 1F1E6 × 094D ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 1F1E6 × 0308 × 094D ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 1F1E6 × 200D ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 1F1E6 × 0308 × 200D ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 1F1E6 ÷ 0378 ÷ # ÷ [0.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [999.0] (Other) ÷ [0.3] @@ -240,8 +324,8 @@ ÷ 0600 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 0600 × 0600 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 0600 × 0308 ÷ 0600 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0600 × 0903 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0600 × 0308 × 0903 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0600 × 0A03 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0600 × 0308 × 0A03 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 0600 × 1100 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0600 × 0308 ÷ 1100 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0600 × 1160 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -252,48 +336,76 @@ ÷ 0600 × 0308 ÷ AC00 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 0600 × AC01 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 0600 × 0308 ÷ AC01 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0600 × 0900 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0308 × 0900 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0903 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0308 × 0903 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0904 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0308 ÷ 0904 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0D4E ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0308 ÷ 0D4E ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0600 × 0915 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0600 × 0308 ÷ 0915 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 0600 × 231A ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] WATCH (ExtPict) ÷ [0.3] ÷ 0600 × 0308 ÷ 231A ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0600 × 0300 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 0600 × 0308 × 0300 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0600 × 093C ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0600 × 0308 × 093C ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0600 × 094D ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0600 × 0308 × 094D ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 0600 × 200D ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0600 × 0308 × 200D ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0600 × 0378 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.2] (Other) ÷ [0.3] ÷ 0600 × 0308 ÷ 0378 ÷ # ÷ [0.2] ARABIC NUMBER SIGN (Prepend) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] -÷ 0903 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] SPACE (Other) ÷ [0.3] -÷ 0903 × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] -÷ 0903 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [5.0] (CR) ÷ [0.3] -÷ 0903 × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] -÷ 0903 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [5.0] (LF) ÷ [0.3] -÷ 0903 × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] -÷ 0903 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [5.0] (Control) ÷ [0.3] -÷ 0903 × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] -÷ 0903 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] -÷ 0903 × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] -÷ 0903 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] -÷ 0903 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] -÷ 0903 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0903 × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0903 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0903 × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0903 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] -÷ 0903 × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] -÷ 0903 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] -÷ 0903 × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] -÷ 0903 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] -÷ 0903 × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] -÷ 0903 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] -÷ 0903 × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] -÷ 0903 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] -÷ 0903 × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] -÷ 0903 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] -÷ 0903 × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] -÷ 0903 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] -÷ 0903 × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] -÷ 0903 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] -÷ 0903 × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] -÷ 0903 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] (Other) ÷ [0.3] -÷ 0903 × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 0A03 ÷ 0020 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0020 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0A03 ÷ 000D ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [5.0] (CR) ÷ [0.3] +÷ 0A03 × 0308 ÷ 000D ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 0A03 ÷ 000A ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [5.0] (LF) ÷ [0.3] +÷ 0A03 × 0308 ÷ 000A ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 0A03 ÷ 0001 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [5.0] (Control) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0001 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 0A03 × 034F ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0A03 × 0308 × 034F ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0A03 ÷ 1F1E6 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0A03 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0A03 ÷ 0600 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0600 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0A03 × 0A03 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0A03 × 0308 × 0A03 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0A03 ÷ 1100 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0A03 × 0308 ÷ 1100 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0A03 ÷ 1160 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0A03 × 0308 ÷ 1160 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0A03 ÷ 11A8 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0A03 × 0308 ÷ 11A8 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0A03 ÷ AC00 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0A03 × 0308 ÷ AC00 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0A03 ÷ AC01 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0A03 × 0308 ÷ AC01 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0A03 × 0900 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 × 0308 × 0900 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 × 0903 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 × 0308 × 0903 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 ÷ 0904 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0904 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 ÷ 0D4E ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0D4E ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0A03 ÷ 0915 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0915 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0A03 ÷ 231A ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0A03 × 0308 ÷ 231A ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0A03 × 0300 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 0308 × 0300 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 093C ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 0308 × 093C ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 094D ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 0308 × 094D ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 200D ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0A03 × 0308 × 200D ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0A03 ÷ 0378 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [999.0] (Other) ÷ [0.3] +÷ 0A03 × 0308 ÷ 0378 ÷ # ÷ [0.2] GURMUKHI SIGN VISARGA (SpacingMark) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] ÷ 1100 ÷ 0020 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] SPACE (Other) ÷ [0.3] ÷ 1100 × 0308 ÷ 0020 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] ÷ 1100 ÷ 000D ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [5.0] (CR) ÷ [0.3] @@ -308,8 +420,8 @@ ÷ 1100 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 1100 ÷ 0600 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 1100 × 0308 ÷ 0600 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 1100 × 0903 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 1100 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 1100 × 0A03 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 1100 × 0308 × 0A03 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 1100 × 1100 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [6.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 1100 × 0308 ÷ 1100 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 1100 × 1160 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [6.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -320,10 +432,24 @@ ÷ 1100 × 0308 ÷ AC00 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 1100 × AC01 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [6.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 1100 × 0308 ÷ AC01 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 1100 × 0900 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 × 0308 × 0900 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 × 0903 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 ÷ 0904 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 × 0308 ÷ 0904 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 ÷ 0D4E ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 × 0308 ÷ 0D4E ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1100 ÷ 0915 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 1100 × 0308 ÷ 0915 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 1100 ÷ 231A ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 1100 × 0308 ÷ 231A ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 1100 × 0300 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 1100 × 0308 × 0300 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 1100 × 093C ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 1100 × 0308 × 093C ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 1100 × 094D ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 1100 × 0308 × 094D ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 1100 × 200D ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 1100 × 0308 × 200D ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 1100 ÷ 0378 ÷ # ÷ [0.2] HANGUL CHOSEONG KIYEOK (L) ÷ [999.0] (Other) ÷ [0.3] @@ -342,8 +468,8 @@ ÷ 1160 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 1160 ÷ 0600 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 1160 × 0308 ÷ 0600 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 1160 × 0903 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 1160 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 1160 × 0A03 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 1160 × 0308 × 0A03 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 1160 ÷ 1100 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 1160 × 0308 ÷ 1100 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 1160 × 1160 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [7.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -354,10 +480,24 @@ ÷ 1160 × 0308 ÷ AC00 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 1160 ÷ AC01 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 1160 × 0308 ÷ AC01 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 1160 × 0900 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 × 0308 × 0900 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 × 0903 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 ÷ 0904 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 × 0308 ÷ 0904 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 ÷ 0D4E ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 × 0308 ÷ 0D4E ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 1160 ÷ 0915 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 1160 × 0308 ÷ 0915 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 1160 ÷ 231A ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 1160 × 0308 ÷ 231A ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 1160 × 0300 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 1160 × 0308 × 0300 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 1160 × 093C ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 1160 × 0308 × 093C ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 1160 × 094D ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 1160 × 0308 × 094D ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 1160 × 200D ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 1160 × 0308 × 200D ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 1160 ÷ 0378 ÷ # ÷ [0.2] HANGUL JUNGSEONG FILLER (V) ÷ [999.0] (Other) ÷ [0.3] @@ -376,8 +516,8 @@ ÷ 11A8 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 11A8 ÷ 0600 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 11A8 × 0308 ÷ 0600 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 11A8 × 0903 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 11A8 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 11A8 × 0A03 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 11A8 × 0308 × 0A03 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 11A8 ÷ 1100 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 11A8 × 0308 ÷ 1100 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 11A8 ÷ 1160 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -388,10 +528,24 @@ ÷ 11A8 × 0308 ÷ AC00 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 11A8 ÷ AC01 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 11A8 × 0308 ÷ AC01 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 11A8 × 0900 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 × 0308 × 0900 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 × 0903 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 ÷ 0904 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 × 0308 ÷ 0904 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 ÷ 0D4E ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 × 0308 ÷ 0D4E ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 11A8 ÷ 0915 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 11A8 × 0308 ÷ 0915 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 11A8 ÷ 231A ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 11A8 × 0308 ÷ 231A ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 11A8 × 0300 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 11A8 × 0308 × 0300 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 11A8 × 093C ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 11A8 × 0308 × 093C ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 11A8 × 094D ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 11A8 × 0308 × 094D ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 11A8 × 200D ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 11A8 × 0308 × 200D ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 11A8 ÷ 0378 ÷ # ÷ [0.2] HANGUL JONGSEONG KIYEOK (T) ÷ [999.0] (Other) ÷ [0.3] @@ -410,8 +564,8 @@ ÷ AC00 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ AC00 ÷ 0600 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ AC00 × 0308 ÷ 0600 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ AC00 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ AC00 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ AC00 × 0A03 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ AC00 × 0308 × 0A03 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ AC00 ÷ 1100 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ AC00 × 0308 ÷ 1100 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ AC00 × 1160 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [7.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -422,10 +576,24 @@ ÷ AC00 × 0308 ÷ AC00 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ AC00 ÷ AC01 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ AC00 × 0308 ÷ AC01 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ AC00 × 0900 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 × 0308 × 0900 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 ÷ 0904 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 × 0308 ÷ 0904 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 ÷ 0D4E ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 × 0308 ÷ 0D4E ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC00 ÷ 0915 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ AC00 × 0308 ÷ 0915 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ AC00 ÷ 231A ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ AC00 × 0308 ÷ 231A ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ AC00 × 0300 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ AC00 × 0308 × 0300 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ AC00 × 093C ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ AC00 × 0308 × 093C ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ AC00 × 094D ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ AC00 × 0308 × 094D ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ AC00 × 200D ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ AC00 × 0308 × 200D ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ AC00 ÷ 0378 ÷ # ÷ [0.2] HANGUL SYLLABLE GA (LV) ÷ [999.0] (Other) ÷ [0.3] @@ -444,8 +612,8 @@ ÷ AC01 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ AC01 ÷ 0600 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ AC01 × 0308 ÷ 0600 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ AC01 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ AC01 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ AC01 × 0A03 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ AC01 × 0308 × 0A03 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ AC01 ÷ 1100 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ AC01 × 0308 ÷ 1100 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ AC01 ÷ 1160 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -456,14 +624,268 @@ ÷ AC01 × 0308 ÷ AC00 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ AC01 ÷ AC01 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ AC01 × 0308 ÷ AC01 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ AC01 × 0900 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 × 0308 × 0900 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 × 0308 × 0903 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 ÷ 0904 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 × 0308 ÷ 0904 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 ÷ 0D4E ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 × 0308 ÷ 0D4E ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ AC01 ÷ 0915 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ AC01 × 0308 ÷ 0915 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ AC01 ÷ 231A ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ AC01 × 0308 ÷ 231A ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ AC01 × 0300 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ AC01 × 0308 × 0300 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ AC01 × 093C ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ AC01 × 0308 × 093C ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ AC01 × 094D ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ AC01 × 0308 × 094D ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ AC01 × 200D ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ AC01 × 0308 × 200D ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ AC01 ÷ 0378 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) ÷ [999.0] (Other) ÷ [0.3] ÷ AC01 × 0308 ÷ 0378 ÷ # ÷ [0.2] HANGUL SYLLABLE GAG (LVT) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 0900 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0900 × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0900 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [5.0] (CR) ÷ [0.3] +÷ 0900 × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 0900 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [5.0] (LF) ÷ [0.3] +÷ 0900 × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 0900 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [5.0] (Control) ÷ [0.3] +÷ 0900 × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 0900 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0900 × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0900 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0900 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0900 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0900 × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0900 × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0900 × 0308 × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0900 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0900 × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0900 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0900 × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0900 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0900 × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0900 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0900 × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0900 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0900 × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0900 × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 × 0308 × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 × 0308 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 × 0308 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0900 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0900 × 0308 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0900 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0900 × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0900 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0900 × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0900 × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0900 × 0308 × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0900 × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0900 × 0308 × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0900 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0900 × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0900 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [999.0] (Other) ÷ [0.3] +÷ 0900 × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 0903 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0903 × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0903 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [5.0] (CR) ÷ [0.3] +÷ 0903 × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 0903 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [5.0] (LF) ÷ [0.3] +÷ 0903 × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 0903 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [5.0] (Control) ÷ [0.3] +÷ 0903 × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 0903 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0903 × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0903 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0903 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0903 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0903 × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0903 × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0903 × 0308 × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0903 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0903 × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0903 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0903 × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0903 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0903 × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0903 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0903 × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0903 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0903 × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0903 × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 × 0308 × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 × 0308 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 × 0308 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0903 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0903 × 0308 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0903 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0903 × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0903 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0903 × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0903 × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0903 × 0308 × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0903 × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0903 × 0308 × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0903 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0903 × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0903 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] (Other) ÷ [0.3] +÷ 0903 × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 0904 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0904 × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0904 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [5.0] (CR) ÷ [0.3] +÷ 0904 × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 0904 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [5.0] (LF) ÷ [0.3] +÷ 0904 × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 0904 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [5.0] (Control) ÷ [0.3] +÷ 0904 × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 0904 × 034F ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0904 × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0904 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0904 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0904 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0904 × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0904 × 0A03 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0904 × 0308 × 0A03 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0904 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0904 × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0904 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0904 × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0904 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0904 × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0904 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0904 × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0904 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0904 × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0904 × 0900 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 × 0308 × 0900 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 × 0903 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 × 0308 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 × 0308 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0904 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0904 × 0308 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0904 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0904 × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0904 × 0300 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0904 × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0904 × 093C ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0904 × 0308 × 093C ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0904 × 094D ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0904 × 0308 × 094D ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0904 × 200D ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0904 × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0904 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [999.0] (Other) ÷ [0.3] +÷ 0904 × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 0D4E × 0020 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] SPACE (Other) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0020 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0D4E ÷ 000D ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [5.0] (CR) ÷ [0.3] +÷ 0D4E × 0308 ÷ 000D ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 0D4E ÷ 000A ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [5.0] (LF) ÷ [0.3] +÷ 0D4E × 0308 ÷ 000A ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 0D4E ÷ 0001 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [5.0] (Control) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0001 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 0D4E × 034F ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0D4E × 0308 × 034F ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0D4E × 1F1E6 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0D4E × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0D4E × 0600 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0600 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0D4E × 0A03 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0D4E × 0308 × 0A03 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0D4E × 1100 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0D4E × 0308 ÷ 1100 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0D4E × 1160 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0D4E × 0308 ÷ 1160 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0D4E × 11A8 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0D4E × 0308 ÷ 11A8 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0D4E × AC00 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0D4E × 0308 ÷ AC00 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0D4E × AC01 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0D4E × 0308 ÷ AC01 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0D4E × 0900 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0308 × 0900 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0903 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0308 × 0903 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0904 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0904 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0D4E ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0D4E ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0D4E × 0915 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0915 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0D4E × 231A ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] WATCH (ExtPict) ÷ [0.3] +÷ 0D4E × 0308 ÷ 231A ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0D4E × 0300 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 0308 × 0300 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 093C ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 0308 × 093C ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 094D ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 0308 × 094D ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 200D ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 0308 × 200D ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0D4E × 0378 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.2] (Other) ÷ [0.3] +÷ 0D4E × 0308 ÷ 0378 ÷ # ÷ [0.2] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 0915 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0915 × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 0915 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [5.0] (CR) ÷ [0.3] +÷ 0915 × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 0915 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [5.0] (LF) ÷ [0.3] +÷ 0915 × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 0915 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [5.0] (Control) ÷ [0.3] +÷ 0915 × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 0915 × 034F ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0915 × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 0915 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0915 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 0915 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0915 × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 0915 × 0A03 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0915 × 0308 × 0A03 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0915 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0915 × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 0915 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0915 × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 0915 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0915 × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 0915 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0915 × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 0915 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0915 × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0915 × 0900 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 × 0308 × 0900 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 × 0903 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 × 0308 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 × 0308 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0915 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 0308 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0915 × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 0915 × 0300 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0915 × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0915 × 093C ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0915 × 0308 × 093C ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0915 × 094D ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0915 × 0308 × 094D ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0915 × 200D ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0915 × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 0915 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] (Other) ÷ [0.3] +÷ 0915 × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] ÷ 231A ÷ 0020 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] SPACE (Other) ÷ [0.3] ÷ 231A × 0308 ÷ 0020 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] ÷ 231A ÷ 000D ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [5.0] (CR) ÷ [0.3] @@ -478,8 +900,8 @@ ÷ 231A × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 231A ÷ 0600 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 231A × 0308 ÷ 0600 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 231A × 0903 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 231A × 0308 × 0903 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 231A × 0A03 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 231A × 0308 × 0A03 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 231A ÷ 1100 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 231A × 0308 ÷ 1100 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 231A ÷ 1160 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -490,10 +912,24 @@ ÷ 231A × 0308 ÷ AC00 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 231A ÷ AC01 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 231A × 0308 ÷ AC01 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 231A × 0900 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 231A × 0308 × 0900 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 231A × 0903 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 231A × 0308 × 0903 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 231A ÷ 0904 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 231A × 0308 ÷ 0904 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 231A ÷ 0D4E ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 231A × 0308 ÷ 0D4E ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 231A ÷ 0915 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 231A × 0308 ÷ 0915 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 231A ÷ 231A ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 231A × 0308 ÷ 231A ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 231A × 0300 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 231A × 0308 × 0300 ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 231A × 093C ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 231A × 0308 × 093C ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 231A × 094D ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 231A × 0308 × 094D ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 231A × 200D ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 231A × 0308 × 200D ÷ # ÷ [0.2] WATCH (ExtPict) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 231A ÷ 0378 ÷ # ÷ [0.2] WATCH (ExtPict) ÷ [999.0] (Other) ÷ [0.3] @@ -512,8 +948,8 @@ ÷ 0300 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 0300 ÷ 0600 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 0300 × 0308 ÷ 0600 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0300 × 0903 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0300 × 0308 × 0903 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0300 × 0A03 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0300 × 0308 × 0A03 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 0300 ÷ 1100 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0300 × 0308 ÷ 1100 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0300 ÷ 1160 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -524,14 +960,124 @@ ÷ 0300 × 0308 ÷ AC00 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 0300 ÷ AC01 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 0300 × 0308 ÷ AC01 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0300 × 0900 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 × 0308 × 0900 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 × 0903 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 × 0308 × 0903 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 ÷ 0904 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 × 0308 ÷ 0904 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 ÷ 0D4E ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 × 0308 ÷ 0D4E ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0300 ÷ 0915 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0300 × 0308 ÷ 0915 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 0300 ÷ 231A ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0300 × 0308 ÷ 231A ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0300 × 0300 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 0300 × 0308 × 0300 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0300 × 093C ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0300 × 0308 × 093C ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0300 × 094D ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0300 × 0308 × 094D ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 0300 × 200D ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0300 × 0308 × 200D ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0300 ÷ 0378 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] ÷ 0300 × 0308 ÷ 0378 ÷ # ÷ [0.2] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 093C ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 093C × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 093C ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 093C × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 093C ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 093C × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 093C ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 093C × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 093C × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 093C × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 093C ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 093C × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 093C ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 093C × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 093C × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 093C × 0308 × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 093C ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 093C × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 093C ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 093C × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 093C ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 093C × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 093C ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 093C × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 093C ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 093C × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 093C × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 093C × 0308 × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 093C × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 093C × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 093C ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 093C × 0308 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 093C ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 093C × 0308 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 093C ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 093C × 0308 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 093C ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 093C × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 093C × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 093C × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 093C × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 093C × 0308 × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 093C × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 093C × 0308 × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 093C × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 093C × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 093C ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 093C × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 094D ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 094D × 0308 ÷ 0020 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] +÷ 094D ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 094D × 0308 ÷ 000D ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] +÷ 094D ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 094D × 0308 ÷ 000A ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (LF) ÷ [0.3] +÷ 094D ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 094D × 0308 ÷ 0001 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [5.0] (Control) ÷ [0.3] +÷ 094D × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 094D × 0308 × 034F ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAPHEME JOINER (Extend) ÷ [0.3] +÷ 094D ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 094D × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] +÷ 094D ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 094D × 0308 ÷ 0600 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] +÷ 094D × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 094D × 0308 × 0A03 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 094D ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 094D × 0308 ÷ 1100 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] +÷ 094D ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 094D × 0308 ÷ 1160 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] +÷ 094D ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 094D × 0308 ÷ 11A8 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL JONGSEONG KIYEOK (T) ÷ [0.3] +÷ 094D ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 094D × 0308 ÷ AC00 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] +÷ 094D ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 094D × 0308 ÷ AC01 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 094D × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 094D × 0308 × 0900 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 094D × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 094D × 0308 × 0903 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 094D ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 094D × 0308 ÷ 0904 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 094D ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 094D × 0308 ÷ 0D4E ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 094D ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 094D × 0308 ÷ 0915 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 094D ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 094D × 0308 ÷ 231A ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] +÷ 094D × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 094D × 0308 × 0300 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 094D × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 094D × 0308 × 093C ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 094D × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 094D × 0308 × 094D ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 094D × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 094D × 0308 × 200D ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] +÷ 094D ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] +÷ 094D × 0308 ÷ 0378 ÷ # ÷ [0.2] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] ÷ 200D ÷ 0020 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] ÷ 200D × 0308 ÷ 0020 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] SPACE (Other) ÷ [0.3] ÷ 200D ÷ 000D ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [5.0] (CR) ÷ [0.3] @@ -546,8 +1092,8 @@ ÷ 200D × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 200D ÷ 0600 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 200D × 0308 ÷ 0600 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 200D × 0903 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 200D × 0308 × 0903 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 200D × 0A03 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 200D × 0308 × 0A03 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 200D ÷ 1100 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 200D × 0308 ÷ 1100 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 200D ÷ 1160 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -558,10 +1104,24 @@ ÷ 200D × 0308 ÷ AC00 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 200D ÷ AC01 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 200D × 0308 ÷ AC01 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 200D × 0900 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 200D × 0308 × 0900 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 200D × 0903 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 200D × 0308 × 0903 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 200D ÷ 0904 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 200D × 0308 ÷ 0904 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 200D ÷ 0D4E ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 200D × 0308 ÷ 0D4E ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 200D ÷ 0915 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 200D × 0308 ÷ 0915 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 200D ÷ 231A ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 200D × 0308 ÷ 231A ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 200D × 0300 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 200D × 0308 × 0300 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 200D × 093C ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 200D × 0308 × 093C ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 200D × 094D ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 200D × 0308 × 094D ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 200D × 200D ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 200D × 0308 × 200D ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 200D ÷ 0378 ÷ # ÷ [0.2] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] (Other) ÷ [0.3] @@ -580,8 +1140,8 @@ ÷ 0378 × 0308 ÷ 1F1E6 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) ÷ [0.3] ÷ 0378 ÷ 0600 ÷ # ÷ [0.2] (Other) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] ÷ 0378 × 0308 ÷ 0600 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) ÷ [0.3] -÷ 0378 × 0903 ÷ # ÷ [0.2] (Other) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] -÷ 0378 × 0308 × 0903 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0378 × 0A03 ÷ # ÷ [0.2] (Other) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] +÷ 0378 × 0308 × 0A03 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] GURMUKHI SIGN VISARGA (SpacingMark) ÷ [0.3] ÷ 0378 ÷ 1100 ÷ # ÷ [0.2] (Other) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0378 × 0308 ÷ 1100 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL CHOSEONG KIYEOK (L) ÷ [0.3] ÷ 0378 ÷ 1160 ÷ # ÷ [0.2] (Other) ÷ [999.0] HANGUL JUNGSEONG FILLER (V) ÷ [0.3] @@ -592,10 +1152,24 @@ ÷ 0378 × 0308 ÷ AC00 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GA (LV) ÷ [0.3] ÷ 0378 ÷ AC01 ÷ # ÷ [0.2] (Other) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] ÷ 0378 × 0308 ÷ AC01 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] HANGUL SYLLABLE GAG (LVT) ÷ [0.3] +÷ 0378 × 0900 ÷ # ÷ [0.2] (Other) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 × 0308 × 0900 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN INVERTED CANDRABINDU (Extend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 × 0903 ÷ # ÷ [0.2] (Other) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 × 0308 × 0903 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 ÷ 0904 ÷ # ÷ [0.2] (Other) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 × 0308 ÷ 0904 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER SHORT A (ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 ÷ 0D4E ÷ # ÷ [0.2] (Other) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 × 0308 ÷ 0D4E ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] MALAYALAM LETTER DOT REPH (Prepend_ConjunctLinkingScripts) ÷ [0.3] +÷ 0378 ÷ 0915 ÷ # ÷ [0.2] (Other) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0378 × 0308 ÷ 0915 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] ÷ 0378 ÷ 231A ÷ # ÷ [0.2] (Other) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0378 × 0308 ÷ 231A ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] WATCH (ExtPict) ÷ [0.3] ÷ 0378 × 0300 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] ÷ 0378 × 0308 × 0300 ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] COMBINING GRAVE ACCENT (Extend_ExtCccZwj) ÷ [0.3] +÷ 0378 × 093C ÷ # ÷ [0.2] (Other) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0378 × 0308 × 093C ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) ÷ [0.3] +÷ 0378 × 094D ÷ # ÷ [0.2] (Other) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] +÷ 0378 × 0308 × 094D ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [0.3] ÷ 0378 × 200D ÷ # ÷ [0.2] (Other) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0378 × 0308 × 200D ÷ # ÷ [0.2] (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0378 ÷ 0378 ÷ # ÷ [0.2] (Other) ÷ [999.0] (Other) ÷ [0.3] @@ -614,7 +1188,7 @@ ÷ 0061 ÷ 1F1E6 × 1F1E7 ÷ 1F1E8 × 1F1E9 ÷ 0062 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER A (RI) × [13.0] REGIONAL INDICATOR SYMBOL LETTER B (RI) ÷ [999.0] REGIONAL INDICATOR SYMBOL LETTER C (RI) × [13.0] REGIONAL INDICATOR SYMBOL LETTER D (RI) ÷ [999.0] LATIN SMALL LETTER B (Other) ÷ [0.3] ÷ 0061 × 200D ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [0.3] ÷ 0061 × 0308 ÷ 0062 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.0] COMBINING DIAERESIS (Extend_ExtCccZwj) ÷ [999.0] LATIN SMALL LETTER B (Other) ÷ [0.3] -÷ 0061 × 0903 ÷ 0062 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark) ÷ [999.0] LATIN SMALL LETTER B (Other) ÷ [0.3] +÷ 0061 × 0903 ÷ 0062 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.1] DEVANAGARI SIGN VISARGA (SpacingMark_ConjunctLinkingScripts) ÷ [999.0] LATIN SMALL LETTER B (Other) ÷ [0.3] ÷ 0061 ÷ 0600 × 0062 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) ÷ [999.0] ARABIC NUMBER SIGN (Prepend) × [9.2] LATIN SMALL LETTER B (Other) ÷ [0.3] ÷ 1F476 × 1F3FF ÷ 1F476 ÷ # ÷ [0.2] BABY (ExtPict) × [9.0] EMOJI MODIFIER FITZPATRICK TYPE-6 (Extend) ÷ [999.0] BABY (ExtPict) ÷ [0.3] ÷ 0061 × 1F3FF ÷ 1F476 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.0] EMOJI MODIFIER FITZPATRICK TYPE-6 (Extend) ÷ [999.0] BABY (ExtPict) ÷ [0.3] @@ -624,7 +1198,18 @@ ÷ 0061 × 200D ÷ 1F6D1 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] OCTAGONAL SIGN (ExtPict) ÷ [0.3] ÷ 2701 × 200D × 2701 ÷ # ÷ [0.2] UPPER BLADE SCISSORS (Other) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [11.0] UPPER BLADE SCISSORS (Other) ÷ [0.3] ÷ 0061 × 200D ÷ 2701 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) ÷ [999.0] UPPER BLADE SCISSORS (Other) ÷ [0.3] +÷ 0915 ÷ 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) ÷ [999.0] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 094D × 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 094D × 094D × 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 094D × 200D × 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 093C × 200D × 094D × 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 093C × 094D × 200D × 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN NUKTA (Extend_ConjunctLinkingScripts_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] ZERO WIDTH JOINER (ZWJ_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 094D × 0924 × 094D × 092F ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.3] DEVANAGARI LETTER YA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 094D ÷ 0061 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] LATIN SMALL LETTER A (Other) ÷ [0.3] +÷ 0061 × 094D ÷ 0924 ÷ # ÷ [0.2] LATIN SMALL LETTER A (Other) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 003F × 094D ÷ 0924 ÷ # ÷ [0.2] QUESTION MARK (Other) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) ÷ [999.0] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] +÷ 0915 × 094D × 094D × 0924 ÷ # ÷ [0.2] DEVANAGARI LETTER KA (ConjunctLinkingScripts_LinkingConsonant) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.0] DEVANAGARI SIGN VIRAMA (Extend_ConjunctLinkingScripts_ConjunctLinker_ExtCccZwj) × [9.3] DEVANAGARI LETTER TA (ConjunctLinkingScripts_LinkingConsonant) ÷ [0.3] # -# Lines: 602 +# Lines: 1187 # # EOF diff --git a/libcxx/utils/data/unicode/emoji-data.txt b/libcxx/utils/data/unicode/emoji-data.txt index 7942fc89a355..0ba10e9ce4c9 100644 --- a/libcxx/utils/data/unicode/emoji-data.txt +++ b/libcxx/utils/data/unicode/emoji-data.txt @@ -1,16 +1,16 @@ # emoji-data.txt -# Date: 2022-08-02, 00:26:10 GMT -# © 2022 Unicode®, Inc. +# Date: 2023-02-01, 02:22:54 GMT +# © 2023 Unicode®, Inc. # Unicode and the Unicode Logo are registered trademarks of Unicode, Inc. in the U.S. and other countries. # For terms of use, see https://www.unicode.org/terms_of_use.html # # Emoji Data for UTS #51 -# Used with Emoji Version 15.0 and subsequent minor revisions (if any) +# Used with Emoji Version 15.1 and subsequent minor revisions (if any) # # For documentation and usage, see https://www.unicode.org/reports/tr51 # -# Format: -# ; # +# Format: +# ; # # Note: there is no guarantee as to the structure of whitespace or comments # # Characters and sequences are listed in code point order. Users should be shown a more natural order. diff --git a/libcxx/utils/generate_extended_grapheme_cluster_table.py b/libcxx/utils/generate_extended_grapheme_cluster_table.py index 6a598399ce47..76d1e78e9239 100755 --- a/libcxx/utils/generate_extended_grapheme_cluster_table.py +++ b/libcxx/utils/generate_extended_grapheme_cluster_table.py @@ -289,25 +289,16 @@ def generate_cpp_data(prop_name: str, ranges: list[PropertyRange]) -> str: def generate_data_tables() -> str: """ Generate Unicode data for inclusion into from - GraphemeBreakProperty.txt and emoji-data.txt. + - https://www.unicode.org/Public/UCD/latest/ucd/auxiliary/GraphemeBreakProperty.txt + - https://www.unicode.org/Public/UCD/latest/ucd/emoji/emoji-data.txt + - https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt - GraphemeBreakProperty.txt can be found at - https://www.unicode.org/Public/UCD/latest/ucd/auxiliary/GraphemeBreakProperty.txt - - emoji-data.txt can be found at - https://www.unicode.org/Public/UCD/latest/ucd/emoji/emoji-data.txt - - Both files are expected to be in the same directory as this script. + These files are expected to be stored in the same directory as this script. """ - gbp_data_path = ( - Path(__file__).absolute().parent - / "data" - / "unicode" - / "GraphemeBreakProperty.txt" - ) - emoji_data_path = ( - Path(__file__).absolute().parent / "data" / "unicode" / "emoji-data.txt" - ) + root = Path(__file__).absolute().parent / "data" / "unicode" + gbp_data_path = root / "GraphemeBreakProperty.txt" + emoji_data_path = root / "emoji-data.txt" + gbp_ranges = list() emoji_ranges = list() with gbp_data_path.open(encoding="utf-8") as f: diff --git a/libcxx/utils/generate_indic_conjunct_break_table.py b/libcxx/utils/generate_indic_conjunct_break_table.py new file mode 100755 index 000000000000..762dfa73b51f --- /dev/null +++ b/libcxx/utils/generate_indic_conjunct_break_table.py @@ -0,0 +1,309 @@ +#!/usr/bin/env python +# ===----------------------------------------------------------------------===## +# +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +# +# ===----------------------------------------------------------------------===## + +# The code is based on +# https://github.com/microsoft/STL/blob/main/tools/unicode_properties_parse/grapheme_break_property_data_gen.py +# +# Copyright (c) Microsoft Corporation. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +from io import StringIO +from pathlib import Path +from dataclasses import dataclass +from typing import Optional +import re +import sys + + +@dataclass +class PropertyRange: + lower: int = -1 + upper: int = -1 + prop: str = None + + +@dataclass +class Entry: + lower: int = -1 + offset: int = -1 + prop: int = -1 + + +LINE_REGEX = re.compile( + r"^(?P[0-9A-F]{4,5})(?:\.\.(?P[0-9A-F]{4,5}))?\s*;\s*InCB;\s*(?P\w+)" +) + +def parsePropertyLine(inputLine: str) -> Optional[PropertyRange]: + result = PropertyRange() + if m := LINE_REGEX.match(inputLine): + lower_str, upper_str, result.prop = m.group("lower", "upper", "prop") + result.lower = int(lower_str, base=16) + result.upper = result.lower + if upper_str is not None: + result.upper = int(upper_str, base=16) + return result + + else: + return None + + + +def compactPropertyRanges(input: list[PropertyRange]) -> list[PropertyRange]: + """ + Merges consecutive ranges with the same property to one range. + + Merging the ranges results in fewer ranges in the output table, + reducing binary and improving lookup performance. + """ + result = list() + for x in input: + if ( + len(result) + and result[-1].prop == x.prop + and result[-1].upper + 1 == x.lower + ): + result[-1].upper = x.upper + continue + result.append(x) + return result + + +PROP_VALUE_ENUMERATOR_TEMPLATE = " __{}" +PROP_VALUE_ENUM_TEMPLATE = """ +enum class __property : uint8_t {{ + // Values generated from the data files. +{enumerators}, + + // The code unit has none of above properties. + __none +}}; +""" + +DATA_ARRAY_TEMPLATE = """ +/// The entries of the indic conjunct break property table. +/// +/// The data is generated from +/// - https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt +/// +/// The data has 3 values +/// - bits [0, 1] The property. One of the values generated from the datafiles +/// of \\ref __property +/// - bits [2, 10] The size of the range. +/// - bits [11, 31] The lower bound code point of the range. The upper bound of +/// the range is lower bound + size. +/// +/// The 9 bits for the size allow a maximum range of 512 elements. Some ranges +/// in the Unicode tables are larger. They are stored in multiple consecutive +/// ranges in the data table. An alternative would be to store the sizes in a +/// separate 16-bit value. The original MSVC STL code had such an approach, but +/// this approach uses less space for the data and is about 4% faster in the +/// following benchmark. +/// libcxx/benchmarks/std_format_spec_string_unicode.bench.cpp +// clang-format off +_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[{size}] = {{ +{entries}}}; +// clang-format on + +/// Returns the indic conjuct break property of a code point. +[[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr __property __get_property(const char32_t __code_point) noexcept {{ + // The algorithm searches for the upper bound of the range and, when found, + // steps back one entry. This algorithm is used since the code point can be + // anywhere in the range. After a lower bound is found the next step is to + // compare whether the code unit is indeed in the range. + // + // Since the entry contains a code unit, size, and property the code point + // being sought needs to be adjusted. Just shifting the code point to the + // proper position doesn't work; suppose an entry has property 0, size 1, + // and lower bound 3. This results in the entry 0x1810. + // When searching for code point 3 it will search for 0x1800, find 0x1810 + // and moves to the previous entry. Thus the lower bound value will never + // be found. + // The simple solution is to set the bits belonging to the property and + // size. Then the upper bound for code point 3 will return the entry after + // 0x1810. After moving to the previous entry the algorithm arrives at the + // correct entry. + ptrdiff_t __i = std::ranges::upper_bound(__entries, (__code_point << 11) | 0x7ffu) - __entries; + if (__i == 0) + return __property::__none; + + --__i; + uint32_t __upper_bound = (__entries[__i] >> 11) + ((__entries[__i] >> 2) & 0b1'1111'1111); + if (__code_point <= __upper_bound) + return static_cast<__property>(__entries[__i] & 0b11); + + return __property::__none; +}} +""" + +MSVC_FORMAT_UCD_TABLES_HPP_TEMPLATE = """ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// WARNING, this entire header is generated by +// utils/generate_indic_conjunct_break_table.py +// DO NOT MODIFY! + +// UNICODE, INC. LICENSE AGREEMENT - DATA FILES AND SOFTWARE +// +// See Terms of Use +// for definitions of Unicode Inc.'s Data Files and Software. +// +// NOTICE TO USER: Carefully read the following legal agreement. +// BY DOWNLOADING, INSTALLING, COPYING OR OTHERWISE USING UNICODE INC.'S +// DATA FILES ("DATA FILES"), AND/OR SOFTWARE ("SOFTWARE"), +// YOU UNEQUIVOCALLY ACCEPT, AND AGREE TO BE BOUND BY, ALL OF THE +// TERMS AND CONDITIONS OF THIS AGREEMENT. +// IF YOU DO NOT AGREE, DO NOT DOWNLOAD, INSTALL, COPY, DISTRIBUTE OR USE +// THE DATA FILES OR SOFTWARE. +// +// COPYRIGHT AND PERMISSION NOTICE +// +// Copyright (c) 1991-2022 Unicode, Inc. All rights reserved. +// Distributed under the Terms of Use in https://www.unicode.org/copyright.html. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of the Unicode data files and any associated documentation +// (the "Data Files") or Unicode software and any associated documentation +// (the "Software") to deal in the Data Files or Software +// without restriction, including without limitation the rights to use, +// copy, modify, merge, publish, distribute, and/or sell copies of +// the Data Files or Software, and to permit persons to whom the Data Files +// or Software are furnished to do so, provided that either +// (a) this copyright and permission notice appear with all copies +// of the Data Files or Software, or +// (b) this copyright and permission notice appear in associated +// Documentation. +// +// THE DATA FILES AND SOFTWARE ARE PROVIDED "AS IS", WITHOUT WARRANTY OF +// ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +// WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT OF THIRD PARTY RIGHTS. +// IN NO EVENT SHALL THE COPYRIGHT HOLDER OR HOLDERS INCLUDED IN THIS +// NOTICE BE LIABLE FOR ANY CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL +// DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, +// DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER +// TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +// PERFORMANCE OF THE DATA FILES OR SOFTWARE. +// +// Except as contained in this notice, the name of a copyright holder +// shall not be used in advertising or otherwise to promote the sale, +// use or other dealings in these Data Files or Software without prior +// written authorization of the copyright holder. + +#ifndef _LIBCPP___FORMAT_INDIC_CONJUNCT_BREAK_TABLE_H +#define _LIBCPP___FORMAT_INDIC_CONJUNCT_BREAK_TABLE_H + +#include <__algorithm/ranges_upper_bound.h> +#include <__config> +#include <__iterator/access.h> +#include +#include + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +_LIBCPP_BEGIN_NAMESPACE_STD + +#if _LIBCPP_STD_VER >= 20 + +namespace __indic_conjunct_break {{ +{content} +}} // namespace __indic_conjunct_break + +#endif //_LIBCPP_STD_VER >= 20 + +_LIBCPP_END_NAMESPACE_STD + +#endif // _LIBCPP___FORMAT_INDIC_CONJUNCT_BREAK_TABLE_H""" + + +def property_ranges_to_table( + ranges: list[PropertyRange], props: list[str] +) -> list[Entry]: + assert len(props) < 4 + result = list[Entry]() + high = -1 + for range in sorted(ranges, key=lambda x: x.lower): + # Validate overlapping ranges + assert range.lower > high + high = range.upper + + while True: + e = Entry(range.lower, range.upper - range.lower, props.index(range.prop)) + if e.offset <= 511: + result.append(e) + break + e.offset = 511 + result.append(e) + range.lower += 512 + return result + + +cpp_entrytemplate = " 0x{:08x}" + + +def generate_cpp_data(prop_name: str, ranges: list[PropertyRange]) -> str: + result = StringIO() + prop_values = sorted(set(x.prop for x in ranges)) + table = property_ranges_to_table(ranges, prop_values) + enumerator_values = [PROP_VALUE_ENUMERATOR_TEMPLATE.format(x) for x in prop_values] + result.write( + PROP_VALUE_ENUM_TEMPLATE.format(enumerators=",\n".join(enumerator_values)) + ) + result.write( + DATA_ARRAY_TEMPLATE.format( + prop_name=prop_name, + size=len(table), + entries=",\n".join( + [ + cpp_entrytemplate.format(x.lower << 11 | x.offset << 2 | x.prop) + for x in table + ] + ), + ) + ) + + return result.getvalue() + + +def generate_data_tables() -> str: + """ + Generate Unicode data for inclusion into from + - https://www.unicode.org/Public/UCD/latest/ucd/DerivedCoreProperties.txt + + These files are expected to be stored in the same directory as this script. + """ + root = Path(__file__).absolute().parent / "data" / "unicode" + derived_core_path = root / "DerivedCoreProperties.txt" + + indic_conjunct_break = list() + with derived_core_path.open(encoding="utf-8") as f: + indic_conjunct_break_ranges = compactPropertyRanges( + [x for line in f if (x := parsePropertyLine(line))] + ) + + indic_conjunct_break_data = generate_cpp_data("Grapheme_Break", indic_conjunct_break_ranges) + return "\n".join([indic_conjunct_break_data]) + + +if __name__ == "__main__": + if len(sys.argv) == 2: + sys.stdout = open(sys.argv[1], "w") + print( + MSVC_FORMAT_UCD_TABLES_HPP_TEMPLATE.lstrip().format( + content=generate_data_tables() + ) + ) -- GitLab From ca705681dff4d7b28fad84b8e6846e0463a8860d Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Tue, 9 Apr 2024 13:21:16 -0400 Subject: [PATCH 310/695] Revert "[ADT] Use `adl_*` wrappers across STLExtras" (#88158) Reverts llvm/llvm-project#87936 Seems like this broke some clang designated initializers tests, reverting. --- llvm/include/llvm/ADT/STLExtras.h | 49 ++++++++++++++++--------------- 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index f906f7acfc1c..08a708e5c587 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -320,8 +320,7 @@ public: /// Returns true if the given container only contains a single element. template bool hasSingleElement(ContainerTy &&C) { - auto B = adl_begin(C); - auto E = adl_end(C); + auto B = std::begin(C), E = std::end(C); return B != E && std::next(B) == E; } @@ -376,7 +375,8 @@ inline mapped_iterator map_iterator(ItTy I, FuncTy F) { template auto map_range(ContainerTy &&C, FuncTy F) { - return make_range(map_iterator(adl_begin(C), F), map_iterator(adl_end(C), F)); + return make_range(map_iterator(std::begin(C), F), + map_iterator(std::end(C), F)); } /// A base type of mapped iterator, that is useful for building derived @@ -572,11 +572,11 @@ iterator_range, PredicateT>> make_filter_range(RangeT &&Range, PredicateT Pred) { using FilterIteratorT = filter_iterator, PredicateT>; - return make_range(FilterIteratorT(adl_begin(std::forward(Range)), - adl_end(std::forward(Range)), Pred), - FilterIteratorT(adl_end(std::forward(Range)), - adl_end(std::forward(Range)), - Pred)); + return make_range( + FilterIteratorT(std::begin(std::forward(Range)), + std::end(std::forward(Range)), Pred), + FilterIteratorT(std::end(std::forward(Range)), + std::end(std::forward(Range)), Pred)); } /// A pseudo-iterator adaptor that is designed to implement "early increment" @@ -656,8 +656,8 @@ iterator_range>> make_early_inc_range(RangeT &&Range) { using EarlyIncIteratorT = early_inc_iterator_impl>; - return make_range(EarlyIncIteratorT(adl_begin(std::forward(Range))), - EarlyIncIteratorT(adl_end(std::forward(Range)))); + return make_range(EarlyIncIteratorT(std::begin(std::forward(Range))), + EarlyIncIteratorT(std::end(std::forward(Range)))); } // Forward declarations required by zip_shortest/zip_equal/zip_first/zip_longest @@ -1097,8 +1097,8 @@ public: /// We need the full range to know how to switch between each of the /// iterators. template - explicit concat_iterator(RangeTs &&...Ranges) - : Begins(adl_begin(Ranges)...), Ends(adl_end(Ranges)...) {} + explicit concat_iterator(RangeTs &&... Ranges) + : Begins(std::begin(Ranges)...), Ends(std::end(Ranges)...) {} using BaseT::operator++; @@ -1127,12 +1127,13 @@ template class concat_range { public: using iterator = concat_iterator()))...>; + decltype(std::begin(std::declval()))...>; private: std::tuple Ranges; - template iterator begin_impl(std::index_sequence) { + template + iterator begin_impl(std::index_sequence) { return iterator(std::get(Ranges)...); } template @@ -1140,12 +1141,12 @@ private: return iterator(std::get(Ranges)...); } template iterator end_impl(std::index_sequence) { - return iterator(make_range(adl_end(std::get(Ranges)), - adl_end(std::get(Ranges)))...); + return iterator(make_range(std::end(std::get(Ranges)), + std::end(std::get(Ranges)))...); } template iterator end_impl(std::index_sequence) const { - return iterator(make_range(adl_end(std::get(Ranges)), - adl_end(std::get(Ranges)))...); + return iterator(make_range(std::end(std::get(Ranges)), + std::end(std::get(Ranges)))...); } public: @@ -1419,7 +1420,7 @@ public: /// Given a container of pairs, return a range over the first elements. template auto make_first_range(ContainerTy &&c) { - using EltTy = decltype((*adl_begin(c))); + using EltTy = decltype((*std::begin(c))); return llvm::map_range(std::forward(c), [](EltTy elt) -> typename detail::first_or_second_type< EltTy, decltype((elt.first))>::type { @@ -1429,7 +1430,7 @@ template auto make_first_range(ContainerTy &&c) { /// Given a container of pairs, return a range over the second elements. template auto make_second_range(ContainerTy &&c) { - using EltTy = decltype((*adl_begin(c))); + using EltTy = decltype((*std::begin(c))); return llvm::map_range( std::forward(c), [](EltTy elt) -> @@ -2105,7 +2106,7 @@ template> void replace(Container &Cont, typename Container::iterator ContIt, typename Container::iterator ContEnd, Range R) { - replace(Cont, ContIt, ContEnd, adl_begin(R), adl_begin(R)); + replace(Cont, ContIt, ContEnd, R.begin(), R.end()); } /// An STL-style algorithm similar to std::for_each that applies a second @@ -2518,19 +2519,19 @@ bool hasNItemsOrLess( /// Returns true if the given container has exactly N items template bool hasNItems(ContainerTy &&C, unsigned N) { - return hasNItems(adl_begin(C), adl_end(C), N); + return hasNItems(std::begin(C), std::end(C), N); } /// Returns true if the given container has N or more items template bool hasNItemsOrMore(ContainerTy &&C, unsigned N) { - return hasNItemsOrMore(adl_begin(C), adl_end(C), N); + return hasNItemsOrMore(std::begin(C), std::end(C), N); } /// Returns true if the given container has N or less items template bool hasNItemsOrLess(ContainerTy &&C, unsigned N) { - return hasNItemsOrLess(adl_begin(C), adl_end(C), N); + return hasNItemsOrLess(std::begin(C), std::end(C), N); } /// Returns a raw pointer that represents the same address as the argument. -- GitLab From 60c5c4ccadfb333335649103a71dbddc953f4ff3 Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Tue, 9 Apr 2024 19:33:53 +0200 Subject: [PATCH 311/695] [MLIR] Don't check for key before inserting in map in GreedyPatternRewriteDriver worklist (NFC) (#88148) This is a common anti-pattern (any volunteer for a clang-tidy check?). This does not show real word significant impact though. --- mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp b/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp index bbecbdb85669..cfd4f9c03aaf 100644 --- a/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp +++ b/mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp @@ -243,9 +243,8 @@ bool Worklist::empty() const { void Worklist::push(Operation *op) { assert(op && "cannot push nullptr to worklist"); // Check to see if the worklist already contains this op. - if (map.count(op)) + if (!map.insert({op, list.size()}).second) return; - map[op] = list.size(); list.push_back(op); } -- GitLab From 4dfc55f7e77821c87d35e1e888fecb8cfb854f7e Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 9 Apr 2024 10:38:27 -0700 Subject: [PATCH 312/695] [SLP][NFC]Add a test for PR88103, where zext is incoming to signed comparison. --- .../X86/zext-incoming-for-neg-icmp.ll | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll diff --git a/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll b/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll new file mode 100644 index 000000000000..f76b6be02477 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll @@ -0,0 +1,46 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define i32 @test(i32 %a, i8 %b, i8 %c) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: i32 [[A:%.*]], i8 [[B:%.*]], i8 [[C:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[C]], i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = icmp sle <4 x i8> [[TMP2]], [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP5]] to <4 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP6]]) +; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP7]], [[A]] +; CHECK-NEXT: ret i32 [[OP_RDX]] +; +entry: + %0 = add i8 %c, -3 + %dec19 = add i8 %c, -1 + %conv20 = zext i8 %dec19 to i32 + %conv16.1 = sext i8 %b to i32 + %cmp17.1 = icmp sle i32 %conv20, %conv16.1 + %conv18.1 = zext i1 %cmp17.1 to i32 + %a.1 = add nsw i32 %conv18.1, %a + %dec19.1 = add i8 %c, -2 + %conv20.1 = zext i8 %dec19.1 to i32 + %conv16.2 = sext i8 %b to i32 + %cmp17.2 = icmp sle i32 %conv20.1, %conv16.2 + %conv18.2 = zext i1 %cmp17.2 to i32 + %a.2 = add nsw i32 %a.1, %conv18.2 + %1 = zext i8 %0 to i32 + %conv16.158 = sext i8 %b to i32 + %cmp17.159 = icmp sle i32 %1, %conv16.158 + %conv18.160 = zext i1 %cmp17.159 to i32 + %a.161 = add nsw i32 %a.2, %conv18.160 + %dec19.162 = add i8 %c, -4 + %conv20.163 = zext i8 %dec19.162 to i32 + %conv16.1.1 = sext i8 %b to i32 + %cmp17.1.1 = icmp sle i32 %conv20.163, %conv16.1.1 + %conv18.1.1 = zext i1 %cmp17.1.1 to i32 + %a.1.1 = add nsw i32 %a.161, %conv18.1.1 + ret i32 %a.1.1 +} + -- GitLab From 910d2de357de8a490cac3ecbd27196356fe1f2a3 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 9 Apr 2024 10:47:47 -0700 Subject: [PATCH 313/695] [SLP]Fix PR88103: consider the sign of the compare for non-negative operands. Need to improve detection of number of bits, required for the operand, before doing a reduction. If the instruction is incoming operand of the signed compare, need to consider adding an extra bit for signedness. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 30 +++++++++++++++---- .../X86/zext-incoming-for-neg-icmp.ll | 4 ++- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index da2b61ea6a63..c3dcf73b0b76 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -14430,6 +14430,8 @@ bool BoUpSLP::collectValuesToDemote( return FinalAnalysis(); } +static RecurKind getRdxKind(Value *V); + void BoUpSLP::computeMinimumValueSizes() { // We only attempt to truncate integer expressions. bool IsStoreOrInsertElt = @@ -14480,7 +14482,7 @@ void BoUpSLP::computeMinimumValueSizes() { auto ComputeMaxBitWidth = [&](ArrayRef TreeRoot, unsigned VF, bool IsTopRoot, bool IsProfitableToDemoteRoot, unsigned Opcode, unsigned Limit, - bool IsTruncRoot) { + bool IsTruncRoot, bool IsSignedCmp) { ToDemote.clear(); auto *TreeRootIT = dyn_cast(TreeRoot[0]->getType()); if (!TreeRootIT || !Opcode) @@ -14503,7 +14505,7 @@ void BoUpSLP::computeMinimumValueSizes() { // True. // Determine if the sign bit of all the roots is known to be zero. If not, // IsKnownPositive is set to False. - bool IsKnownPositive = all_of(TreeRoot, [&](Value *R) { + bool IsKnownPositive = !IsSignedCmp && all_of(TreeRoot, [&](Value *R) { KnownBits Known = computeKnownBits(R, *DL); return Known.isNonNegative(); }); @@ -14590,8 +14592,11 @@ void BoUpSLP::computeMinimumValueSizes() { unsigned BitWidth1 = NumTypeBits - NumSignBits; if (!isKnownNonNegative(V, SimplifyQuery(*DL))) ++BitWidth1; - auto Mask = DB->getDemandedBits(cast(V)); - unsigned BitWidth2 = Mask.getBitWidth() - Mask.countl_zero(); + unsigned BitWidth2 = BitWidth1; + if (!RecurrenceDescriptor::isIntMinMaxRecurrenceKind(::getRdxKind(V))) { + auto Mask = DB->getDemandedBits(cast(V)); + BitWidth2 = Mask.getBitWidth() - Mask.countl_zero(); + } ReductionBitWidth = std::max(std::min(BitWidth1, BitWidth2), ReductionBitWidth); } @@ -14608,6 +14613,7 @@ void BoUpSLP::computeMinimumValueSizes() { ++NodeIdx; IsTruncRoot = true; } + bool IsSignedCmp = false; while (NodeIdx < VectorizableTree.size()) { ArrayRef TreeRoot = VectorizableTree[NodeIdx]->Scalars; unsigned Limit = 2; @@ -14619,7 +14625,7 @@ void BoUpSLP::computeMinimumValueSizes() { Limit = 3; unsigned MaxBitWidth = ComputeMaxBitWidth( TreeRoot, VectorizableTree[NodeIdx]->getVectorFactor(), IsTopRoot, - IsProfitableToDemoteRoot, Opcode, Limit, IsTruncRoot); + IsProfitableToDemoteRoot, Opcode, Limit, IsTruncRoot, IsSignedCmp); if (ReductionBitWidth != 0 && (IsTopRoot || !RootDemotes.empty())) { if (MaxBitWidth != 0 && ReductionBitWidth < MaxBitWidth) ReductionBitWidth = bit_ceil(MaxBitWidth); @@ -14657,6 +14663,16 @@ void BoUpSLP::computeMinimumValueSizes() { EI.UserTE->getOpcode() == Instruction::Trunc && !EI.UserTE->isAltShuffle(); }); + IsSignedCmp = + NodeIdx < VectorizableTree.size() && + any_of(VectorizableTree[NodeIdx]->UserTreeIndices, + [](const EdgeInfo &EI) { + return EI.UserTE->getOpcode() == Instruction::ICmp && + any_of(EI.UserTE->Scalars, [](Value *V) { + auto *IC = dyn_cast(V); + return IC && IC->isSigned(); + }); + }); } // If the maximum bit width we compute is less than the with of the roots' @@ -16697,6 +16713,10 @@ private: }; } // end anonymous namespace +/// Gets recurrence kind from the specified value. +static RecurKind getRdxKind(Value *V) { + return HorizontalReduction::getRdxKind(V); +} static std::optional getAggregateSize(Instruction *InsertInst) { if (auto *IE = dyn_cast(InsertInst)) return cast(IE->getType())->getNumElements(); diff --git a/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll b/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll index f76b6be02477..7f086d17ca4c 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/zext-incoming-for-neg-icmp.ll @@ -10,7 +10,9 @@ define i32 @test(i32 %a, i8 %b, i8 %c) { ; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i8> poison, i8 [[B]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i8> [[TMP3]], <4 x i8> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = icmp sle <4 x i8> [[TMP2]], [[TMP4]] +; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16> +; CHECK-NEXT: [[TMP9:%.*]] = sext <4 x i8> [[TMP4]] to <4 x i16> +; CHECK-NEXT: [[TMP5:%.*]] = icmp sle <4 x i16> [[TMP8]], [[TMP9]] ; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP5]] to <4 x i32> ; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP6]]) ; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP7]], [[A]] -- GitLab From f48895a8be517be058153385438ad64fa09d4883 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Tue, 9 Apr 2024 13:56:37 -0400 Subject: [PATCH 314/695] [C11] Claim conformance to WG14 N1514 This paper made Annex G a normative, but conditionally supported, annex. Clang does not implement Annex G, so we conform to this paper. --- clang/test/C/C11/n1514.c | 14 ++++++++++++++ clang/www/c_status.html | 5 ++++- 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 clang/test/C/C11/n1514.c diff --git a/clang/test/C/C11/n1514.c b/clang/test/C/C11/n1514.c new file mode 100644 index 000000000000..c4c3c1cb86a1 --- /dev/null +++ b/clang/test/C/C11/n1514.c @@ -0,0 +1,14 @@ +// RUN: %clang_cc1 -verify -std=c11 %s +// expected-no-diagnostics + +/* WG14 N1514: Yes + * Conditional normative status for Annex G + */ + +// We don't support Annex G (which introduces imaginary types), but support for +// this annex is conditional in C11. So we can test for conformance to this +// paper by ensuring we don't define the macro claiming we support Annex G. + +#ifdef __STDC_IEC_559_COMPLEX__ +#error "when did this happen??" +#endif diff --git a/clang/www/c_status.html b/clang/www/c_status.html index 7ee1d2b507e8..411f55447be7 100644 --- a/clang/www/c_status.html +++ b/clang/www/c_status.html @@ -568,7 +568,7 @@ conformance.

Conditional normative status for Annex G N1514 - Unknown + Yes (1) Creation of complex value @@ -606,6 +606,9 @@ conformance.

Unknown +(1): Clang does not implement Annex G, so our conditional support +conforms by not defining the __STDC_IEC_559_COMPLEX__ macro. +

C17 implementation status

-- GitLab From a454d92c5ac906d391b683661ac3d9a362ab0107 Mon Sep 17 00:00:00 2001 From: Peiming Liu Date: Tue, 9 Apr 2024 10:59:15 -0700 Subject: [PATCH 315/695] [mlir][sparse] rename files and unifies APIs (#88162) --- .../SparseTensor/Transforms/CMakeLists.txt | 2 +- .../Transforms/Utils/LoopEmitter.h | 2 +- ...nsorLevel.cpp => SparseTensorIterator.cpp} | 66 ++++++++++++------- ...seTensorLevel.h => SparseTensorIterator.h} | 9 +-- 4 files changed, 49 insertions(+), 30 deletions(-) rename mlir/lib/Dialect/SparseTensor/Transforms/Utils/{SparseTensorLevel.cpp => SparseTensorIterator.cpp} (96%) rename mlir/lib/Dialect/SparseTensor/Transforms/Utils/{SparseTensorLevel.h => SparseTensorIterator.h} (97%) diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt b/mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt index 3c0f82fc00bb..af3a1b48f45a 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt @@ -20,7 +20,7 @@ add_mlir_dialect_library(MLIRSparseTensorTransforms Utils/IterationGraphSorter.cpp Utils/LoopEmitter.cpp Utils/SparseTensorDescriptor.cpp - Utils/SparseTensorLevel.cpp + Utils/SparseTensorIterator.cpp ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/SparseTensor diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h index b5a0ac8484ab..59c3e49264db 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h @@ -11,7 +11,7 @@ #include -#include "SparseTensorLevel.h" +#include "SparseTensorIterator.h" #include "mlir/Dialect/SparseTensor/IR/Enums.h" #include "mlir/Dialect/SparseTensor/IR/SparseTensor.h" diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.cpp similarity index 96% rename from mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp rename to mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.cpp index bc27fae5d194..60dca3c55dec 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.cpp @@ -1,4 +1,4 @@ -//===- SparseTensorLevel.cpp - Tensor management class -------------------===// +//===- SparseTensorIterator.cpp -------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "SparseTensorLevel.h" +#include "SparseTensorIterator.h" #include "CodegenUtils.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" @@ -46,21 +46,41 @@ using ValueTuple = std::tuple; namespace { +template class SparseLevel : public SparseTensorLevel { + // It is either an array of size 2 or size 1 depending on whether the sparse + // level requires a position array. + using BufferT = std::conditional_t, + std::array>; + public: SparseLevel(unsigned tid, Level lvl, LevelType lt, Value lvlSize, - Value crdBuffer) - : SparseTensorLevel(tid, lvl, lt, lvlSize), crdBuffer(crdBuffer) {} + BufferT buffers) + : SparseTensorLevel(tid, lvl, lt, lvlSize), buffers(buffers) {} + + ValueRange getLvlBuffers() const override { return buffers; } Value peekCrdAt(OpBuilder &b, Location l, ValueRange batchPrefix, Value iv) const override { SmallVector memCrd(batchPrefix); memCrd.push_back(iv); - return genIndexLoad(b, l, crdBuffer, memCrd); + return genIndexLoad(b, l, getCrdBuf(), memCrd); } protected: - const Value crdBuffer; + template > + Value getPosBuf() const { + return buffers[0]; + } + + Value getCrdBuf() const { + if constexpr (hasPosBuffer) + return buffers[1]; + else + return buffers[0]; + } + + const BufferT buffers; }; class DenseLevel : public SparseTensorLevel { @@ -72,6 +92,8 @@ public: llvm_unreachable("locate random-accessible level instead"); } + ValueRange getLvlBuffers() const override { return {}; } + ValuePair peekRangeAt(OpBuilder &b, Location l, ValueRange, Value p, Value max) const override { Value posLo = MULI(p, lvlSize); @@ -88,6 +110,8 @@ public: llvm_unreachable("locate random-accessible level instead"); } + ValueRange getLvlBuffers() const override { return {}; } + ValuePair peekRangeAt(OpBuilder &b, Location l, ValueRange, Value p, Value max) const override { assert(max == nullptr && "Dense level can not be non-unique."); @@ -96,11 +120,11 @@ public: } }; -class CompressedLevel : public SparseLevel { +class CompressedLevel : public SparseLevel { public: CompressedLevel(unsigned tid, Level lvl, LevelType lt, Value lvlSize, Value posBuffer, Value crdBuffer) - : SparseLevel(tid, lvl, lt, lvlSize, crdBuffer), posBuffer(posBuffer) {} + : SparseLevel(tid, lvl, lt, lvlSize, {posBuffer, crdBuffer}) {} ValuePair peekRangeAt(OpBuilder &b, Location l, ValueRange batchPrefix, Value p, Value max) const override { @@ -109,21 +133,18 @@ public: SmallVector memCrd(batchPrefix); memCrd.push_back(p); - Value pLo = genIndexLoad(b, l, posBuffer, memCrd); + Value pLo = genIndexLoad(b, l, getPosBuf(), memCrd); memCrd.back() = ADDI(p, C_IDX(1)); - Value pHi = genIndexLoad(b, l, posBuffer, memCrd); + Value pHi = genIndexLoad(b, l, getPosBuf(), memCrd); return {pLo, pHi}; } - -private: - const Value posBuffer; }; -class LooseCompressedLevel : public SparseLevel { +class LooseCompressedLevel : public SparseLevel { public: LooseCompressedLevel(unsigned tid, Level lvl, LevelType lt, Value lvlSize, Value posBuffer, Value crdBuffer) - : SparseLevel(tid, lvl, lt, lvlSize, crdBuffer), posBuffer(posBuffer) {} + : SparseLevel(tid, lvl, lt, lvlSize, {posBuffer, crdBuffer}) {} ValuePair peekRangeAt(OpBuilder &b, Location l, ValueRange batchPrefix, Value p, Value max) const override { @@ -133,21 +154,18 @@ public: p = MULI(p, C_IDX(2)); memCrd.push_back(p); - Value pLo = genIndexLoad(b, l, posBuffer, memCrd); + Value pLo = genIndexLoad(b, l, getPosBuf(), memCrd); memCrd.back() = ADDI(p, C_IDX(1)); - Value pHi = genIndexLoad(b, l, posBuffer, memCrd); + Value pHi = genIndexLoad(b, l, getPosBuf(), memCrd); return {pLo, pHi}; } - -private: - const Value posBuffer; }; -class SingletonLevel : public SparseLevel { +class SingletonLevel : public SparseLevel { public: SingletonLevel(unsigned tid, Level lvl, LevelType lt, Value lvlSize, Value crdBuffer) - : SparseLevel(tid, lvl, lt, lvlSize, crdBuffer) {} + : SparseLevel(tid, lvl, lt, lvlSize, {crdBuffer}) {} ValuePair peekRangeAt(OpBuilder &b, Location l, ValueRange batchPrefix, Value p, Value segHi) const override { @@ -159,11 +177,11 @@ public: } }; -class NOutOfMLevel : public SparseLevel { +class NOutOfMLevel : public SparseLevel { public: NOutOfMLevel(unsigned tid, Level lvl, LevelType lt, Value lvlSize, Value crdBuffer) - : SparseLevel(tid, lvl, lt, lvlSize, crdBuffer) {} + : SparseLevel(tid, lvl, lt, lvlSize, {crdBuffer}) {} ValuePair peekRangeAt(OpBuilder &b, Location l, ValueRange batchPrefix, Value p, Value max) const override { diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h similarity index 97% rename from mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h rename to mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h index 9f92eecdf75c..9d69a2335559 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h @@ -1,4 +1,4 @@ -//===- SparseTensorLevel.h --------------------------------------*- C++ -*-===// +//===- SparseTensorIterator.h ---------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MLIR_DIALECT_SPARSETENSOR_TRANSFORMS_UTILS_SPARSETENSORLEVEL_H_ -#define MLIR_DIALECT_SPARSETENSOR_TRANSFORMS_UTILS_SPARSETENSORLEVEL_H_ +#ifndef MLIR_DIALECT_SPARSETENSOR_TRANSFORMS_UTILS_SPARSETENSORITERATOR_H_ +#define MLIR_DIALECT_SPARSETENSOR_TRANSFORMS_UTILS_SPARSETENSORITERATOR_H_ #include "mlir/Dialect/SparseTensor/IR/SparseTensor.h" #include "mlir/Dialect/SparseTensor/Transforms/Passes.h" @@ -55,6 +55,7 @@ public: Level getLevel() const { return lvl; } LevelType getLT() const { return lt; } Value getSize() const { return lvlSize; } + virtual ValueRange getLvlBuffers() const = 0; // // Level properties @@ -321,4 +322,4 @@ std::unique_ptr makeTraverseSubSectIterator( } // namespace sparse_tensor } // namespace mlir -#endif // MLIR_DIALECT_SPARSETENSOR_TRANSFORMS_UTILS_SPARSETENSORLEVEL_H_ +#endif // MLIR_DIALECT_SPARSETENSOR_TRANSFORMS_UTILS_SPARSETENSORITERATOR_H_ -- GitLab From d3016aa889ac12fd8a047d68fed2ddaca107b990 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Apr 2024 11:02:39 -0700 Subject: [PATCH 316/695] [DWARF] Refactor .debug_names bucket count computation (#88087) `getDebugNamesBucketAndHashCount` lures users to provide an array to compute the bucket count using an O(n log n) sort. This is inefficient as hash table based uniquifying is faster. The performance issue matters less for Clang as the number of names is relatively small. For `ld.lld --debug-names`, I plan to compute the unique hash count as a side product of parallel entry pool computation, and I just need a function to suggest a bucket count. --- llvm/include/llvm/BinaryFormat/Dwarf.h | 22 ++++++---------------- llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp | 7 +++---- 2 files changed, 9 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.h b/llvm/include/llvm/BinaryFormat/Dwarf.h index a53e79bf6e39..298700c8941e 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.h +++ b/llvm/include/llvm/BinaryFormat/Dwarf.h @@ -613,23 +613,13 @@ enum AcceleratorTable { DW_hash_function_djb = 0u }; -// Uniquify the string hashes and calculate the bucket count for the -// DWARF v5 Accelerator Table. NOTE: This function effectively consumes the -// 'Hashes' input parameter. -inline std::pair -getDebugNamesBucketAndHashCount(MutableArrayRef Hashes) { - uint32_t BucketCount = 0; - - sort(Hashes); - uint32_t UniqueHashCount = llvm::unique(Hashes) - Hashes.begin(); +// Return a suggested bucket count for the DWARF v5 Accelerator Table. +inline uint32_t getDebugNamesBucketCount(uint32_t UniqueHashCount) { if (UniqueHashCount > 1024) - BucketCount = UniqueHashCount / 4; - else if (UniqueHashCount > 16) - BucketCount = UniqueHashCount / 2; - else - BucketCount = std::max(UniqueHashCount, 1); - - return {BucketCount, UniqueHashCount}; + return UniqueHashCount / 4; + if (UniqueHashCount > 16) + return UniqueHashCount / 2; + return std::max(UniqueHashCount, 1); } // Constants for the GNU pubnames/pubtypes extensions supporting gdb index. diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp index 2e8e7d0a88af..5b679fd3b9f9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -32,14 +32,13 @@ using namespace llvm; void AccelTableBase::computeBucketCount() { - // First get the number of unique hashes. SmallVector Uniques; Uniques.reserve(Entries.size()); for (const auto &E : Entries) Uniques.push_back(E.second.HashValue); - - std::tie(BucketCount, UniqueHashCount) = - llvm::dwarf::getDebugNamesBucketAndHashCount(Uniques); + llvm::sort(Uniques); + UniqueHashCount = llvm::unique(Uniques) - Uniques.begin(); + BucketCount = dwarf::getDebugNamesBucketCount(UniqueHashCount); } void AccelTableBase::finalize(AsmPrinter *Asm, StringRef Prefix) { -- GitLab From 5d9d740c39a6cf21f0d54ec572aed3c2f556cbcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Pettersson?= Date: Tue, 9 Apr 2024 20:12:26 +0200 Subject: [PATCH 317/695] Remove the unused IntervalPartition analysis pass (#88133) This removes the old legacy PM "intervals" analysis pass (aka IntervalPartition). It also removes the associated Interval and IntervalIterator help classes. Reasons for removal: 1) The pass is not used by llvm-project (not even being tested by any regression tests). 2) Pass has not been ported to new pass manager, which at least indicates that it isn't used by the middle-end. 3) ASan reports heap-use-after-free on ++I; // After the first one... even if false is passed to intervals_begin. Not sure if that is a false positive, but it makes the code a bit less trustworthy. --- llvm/include/llvm/Analysis/Interval.h | 138 --------- llvm/include/llvm/Analysis/IntervalIterator.h | 264 ------------------ .../include/llvm/Analysis/IntervalPartition.h | 108 ------- llvm/include/llvm/InitializePasses.h | 1 - llvm/include/llvm/LinkAllPasses.h | 2 - llvm/lib/Analysis/Analysis.cpp | 1 - llvm/lib/Analysis/CMakeLists.txt | 2 - llvm/lib/Analysis/Interval.cpp | 39 --- llvm/lib/Analysis/IntervalPartition.cpp | 118 -------- .../CodeGen/AssignmentTrackingAnalysis.cpp | 1 - .../gn/secondary/llvm/lib/Analysis/BUILD.gn | 2 - 11 files changed, 676 deletions(-) delete mode 100644 llvm/include/llvm/Analysis/Interval.h delete mode 100644 llvm/include/llvm/Analysis/IntervalIterator.h delete mode 100644 llvm/include/llvm/Analysis/IntervalPartition.h delete mode 100644 llvm/lib/Analysis/Interval.cpp delete mode 100644 llvm/lib/Analysis/IntervalPartition.cpp diff --git a/llvm/include/llvm/Analysis/Interval.h b/llvm/include/llvm/Analysis/Interval.h deleted file mode 100644 index 9afe659d00dd..000000000000 --- a/llvm/include/llvm/Analysis/Interval.h +++ /dev/null @@ -1,138 +0,0 @@ -//===- llvm/Analysis/Interval.h - Interval Class Declaration ----*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the Interval class, which -// represents a set of CFG nodes and is a portion of an interval partition. -// -// Intervals have some interesting and useful properties, including the -// following: -// 1. The header node of an interval dominates all of the elements of the -// interval -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_ANALYSIS_INTERVAL_H -#define LLVM_ANALYSIS_INTERVAL_H - -#include "llvm/ADT/GraphTraits.h" -#include - -namespace llvm { - -class BasicBlock; -class raw_ostream; - -//===----------------------------------------------------------------------===// -// -/// Interval Class - An Interval is a set of nodes defined such that every node -/// in the interval has all of its predecessors in the interval (except for the -/// header) -/// -class Interval { - /// HeaderNode - The header BasicBlock, which dominates all BasicBlocks in this - /// interval. Also, any loops in this interval must go through the HeaderNode. - /// - BasicBlock *HeaderNode; - -public: - using succ_iterator = std::vector::iterator; - using pred_iterator = std::vector::iterator; - using node_iterator = std::vector::iterator; - - inline Interval(BasicBlock *Header) : HeaderNode(Header) { - Nodes.push_back(Header); - } - - inline BasicBlock *getHeaderNode() const { return HeaderNode; } - - /// Nodes - The basic blocks in this interval. - std::vector Nodes; - - /// Successors - List of BasicBlocks that are reachable directly from nodes in - /// this interval, but are not in the interval themselves. - /// These nodes necessarily must be header nodes for other intervals. - std::vector Successors; - - /// Predecessors - List of BasicBlocks that have this Interval's header block - /// as one of their successors. - std::vector Predecessors; - - /// contains - Find out if a basic block is in this interval - inline bool contains(BasicBlock *BB) const { - for (BasicBlock *Node : Nodes) - if (Node == BB) - return true; - return false; - // I don't want the dependency on - //return find(Nodes.begin(), Nodes.end(), BB) != Nodes.end(); - } - - /// isSuccessor - find out if a basic block is a successor of this Interval - inline bool isSuccessor(BasicBlock *BB) const { - for (BasicBlock *Successor : Successors) - if (Successor == BB) - return true; - return false; - // I don't want the dependency on - //return find(Successors.begin(), Successors.end(), BB) != Successors.end(); - } - - /// Equality operator. It is only valid to compare two intervals from the - /// same partition, because of this, all we have to check is the header node - /// for equality. - inline bool operator==(const Interval &I) const { - return HeaderNode == I.HeaderNode; - } - - /// print - Show contents in human readable format... - void print(raw_ostream &O) const; -}; - -/// succ_begin/succ_end - define methods so that Intervals may be used -/// just like BasicBlocks can with the succ_* functions, and *::succ_iterator. -/// -inline Interval::succ_iterator succ_begin(Interval *I) { - return I->Successors.begin(); -} -inline Interval::succ_iterator succ_end(Interval *I) { - return I->Successors.end(); -} - -/// pred_begin/pred_end - define methods so that Intervals may be used -/// just like BasicBlocks can with the pred_* functions, and *::pred_iterator. -/// -inline Interval::pred_iterator pred_begin(Interval *I) { - return I->Predecessors.begin(); -} -inline Interval::pred_iterator pred_end(Interval *I) { - return I->Predecessors.end(); -} - -template <> struct GraphTraits { - using NodeRef = Interval *; - using ChildIteratorType = Interval::succ_iterator; - - static NodeRef getEntryNode(Interval *I) { return I; } - - /// nodes_iterator/begin/end - Allow iteration over all nodes in the graph - static ChildIteratorType child_begin(NodeRef N) { return succ_begin(N); } - static ChildIteratorType child_end(NodeRef N) { return succ_end(N); } -}; - -template <> struct GraphTraits> { - using NodeRef = Interval *; - using ChildIteratorType = Interval::pred_iterator; - - static NodeRef getEntryNode(Inverse G) { return G.Graph; } - static ChildIteratorType child_begin(NodeRef N) { return pred_begin(N); } - static ChildIteratorType child_end(NodeRef N) { return pred_end(N); } -}; - -} // end namespace llvm - -#endif // LLVM_ANALYSIS_INTERVAL_H diff --git a/llvm/include/llvm/Analysis/IntervalIterator.h b/llvm/include/llvm/Analysis/IntervalIterator.h deleted file mode 100644 index 30e91f1734b6..000000000000 --- a/llvm/include/llvm/Analysis/IntervalIterator.h +++ /dev/null @@ -1,264 +0,0 @@ -//===- IntervalIterator.h - Interval Iterator Declaration -------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file defines an iterator that enumerates the intervals in a control flow -// graph of some sort. This iterator is parametric, allowing iterator over the -// following types of graphs: -// -// 1. A Function* object, composed of BasicBlock nodes. -// 2. An IntervalPartition& object, composed of Interval nodes. -// -// This iterator is defined to walk the control flow graph, returning intervals -// in depth first order. These intervals are completely filled in except for -// the predecessor fields (the successor information is filled in however). -// -// By default, the intervals created by this iterator are deleted after they -// are no longer any use to the iterator. This behavior can be changed by -// passing a false value into the intervals_begin() function. This causes the -// IOwnMem member to be set, and the intervals to not be deleted. -// -// It is only safe to use this if all of the intervals are deleted by the caller -// and all of the intervals are processed. However, the user of the iterator is -// not allowed to modify or delete the intervals until after the iterator has -// been used completely. The IntervalPartition class uses this functionality. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_ANALYSIS_INTERVALITERATOR_H -#define LLVM_ANALYSIS_INTERVALITERATOR_H - -#include "llvm/ADT/GraphTraits.h" -#include "llvm/Analysis/Interval.h" -#include "llvm/Analysis/IntervalPartition.h" -#include "llvm/IR/CFG.h" -#include -#include -#include -#include -#include -#include - -namespace llvm { - -class BasicBlock; -class Function; - -// getNodeHeader - Given a source graph node and the source graph, return the -// BasicBlock that is the header node. This is the opposite of -// getSourceGraphNode. -inline BasicBlock *getNodeHeader(BasicBlock *BB) { return BB; } -inline BasicBlock *getNodeHeader(Interval *I) { return I->getHeaderNode(); } - -// getSourceGraphNode - Given a BasicBlock and the source graph, return the -// source graph node that corresponds to the BasicBlock. This is the opposite -// of getNodeHeader. -inline BasicBlock *getSourceGraphNode(Function *, BasicBlock *BB) { - return BB; -} -inline Interval *getSourceGraphNode(IntervalPartition *IP, BasicBlock *BB) { - return IP->getBlockInterval(BB); -} - -// addNodeToInterval - This method exists to assist the generic ProcessNode -// with the task of adding a node to the new interval, depending on the -// type of the source node. In the case of a CFG source graph (BasicBlock -// case), the BasicBlock itself is added to the interval. -inline void addNodeToInterval(Interval *Int, BasicBlock *BB) { - Int->Nodes.push_back(BB); -} - -// addNodeToInterval - This method exists to assist the generic ProcessNode -// with the task of adding a node to the new interval, depending on the -// type of the source node. In the case of a CFG source graph (BasicBlock -// case), the BasicBlock itself is added to the interval. In the case of -// an IntervalPartition source graph (Interval case), all of the member -// BasicBlocks are added to the interval. -inline void addNodeToInterval(Interval *Int, Interval *I) { - // Add all of the nodes in I as new nodes in Int. - llvm::append_range(Int->Nodes, I->Nodes); -} - -template, - class IGT = GraphTraits>> -class IntervalIterator { - std::vector> IntStack; - std::set Visited; - OrigContainer_t *OrigContainer; - bool IOwnMem; // If True, delete intervals when done with them - // See file header for conditions of use - -public: - using iterator_category = std::forward_iterator_tag; - - IntervalIterator() = default; // End iterator, empty stack - - IntervalIterator(Function *M, bool OwnMemory) : IOwnMem(OwnMemory) { - OrigContainer = M; - if (!ProcessInterval(&M->front())) { - llvm_unreachable("ProcessInterval should never fail for first interval!"); - } - } - - IntervalIterator(IntervalIterator &&x) - : IntStack(std::move(x.IntStack)), Visited(std::move(x.Visited)), - OrigContainer(x.OrigContainer), IOwnMem(x.IOwnMem) { - x.IOwnMem = false; - } - - IntervalIterator(IntervalPartition &IP, bool OwnMemory) : IOwnMem(OwnMemory) { - OrigContainer = &IP; - if (!ProcessInterval(IP.getRootInterval())) { - llvm_unreachable("ProcessInterval should never fail for first interval!"); - } - } - - ~IntervalIterator() { - if (IOwnMem) - while (!IntStack.empty()) { - delete operator*(); - IntStack.pop_back(); - } - } - - bool operator==(const IntervalIterator &x) const { - return IntStack == x.IntStack; - } - bool operator!=(const IntervalIterator &x) const { return !(*this == x); } - - const Interval *operator*() const { return IntStack.back().first; } - Interval *operator*() { return IntStack.back().first; } - const Interval *operator->() const { return operator*(); } - Interval *operator->() { return operator*(); } - - IntervalIterator &operator++() { // Preincrement - assert(!IntStack.empty() && "Attempting to use interval iterator at end!"); - do { - // All of the intervals on the stack have been visited. Try visiting - // their successors now. - Interval::succ_iterator &SuccIt = IntStack.back().second, - EndIt = succ_end(IntStack.back().first); - while (SuccIt != EndIt) { // Loop over all interval succs - bool Done = ProcessInterval(getSourceGraphNode(OrigContainer, *SuccIt)); - ++SuccIt; // Increment iterator - if (Done) return *this; // Found a new interval! Use it! - } - - // Free interval memory... if necessary - if (IOwnMem) delete IntStack.back().first; - - // We ran out of successors for this interval... pop off the stack - IntStack.pop_back(); - } while (!IntStack.empty()); - - return *this; - } - - IntervalIterator operator++(int) { // Postincrement - IntervalIterator tmp = *this; - ++*this; - return tmp; - } - -private: - // ProcessInterval - This method is used during the construction of the - // interval graph. It walks through the source graph, recursively creating - // an interval per invocation until the entire graph is covered. This uses - // the ProcessNode method to add all of the nodes to the interval. - // - // This method is templated because it may operate on two different source - // graphs: a basic block graph, or a preexisting interval graph. - bool ProcessInterval(NodeTy *Node) { - BasicBlock *Header = getNodeHeader(Node); - if (!Visited.insert(Header).second) - return false; - - Interval *Int = new Interval(Header); - - // Check all of our successors to see if they are in the interval... - for (typename GT::ChildIteratorType I = GT::child_begin(Node), - E = GT::child_end(Node); I != E; ++I) - ProcessNode(Int, getSourceGraphNode(OrigContainer, *I)); - - IntStack.push_back(std::make_pair(Int, succ_begin(Int))); - return true; - } - - // ProcessNode - This method is called by ProcessInterval to add nodes to the - // interval being constructed, and it is also called recursively as it walks - // the source graph. A node is added to the current interval only if all of - // its predecessors are already in the graph. This also takes care of keeping - // the successor set of an interval up to date. - // - // This method is templated because it may operate on two different source - // graphs: a basic block graph, or a preexisting interval graph. - void ProcessNode(Interval *Int, NodeTy *Node) { - assert(Int && "Null interval == bad!"); - assert(Node && "Null Node == bad!"); - - BasicBlock *NodeHeader = getNodeHeader(Node); - - if (Visited.count(NodeHeader)) { // Node already been visited? - if (Int->contains(NodeHeader)) { // Already in this interval... - return; - } else { // In other interval, add as successor - if (!Int->isSuccessor(NodeHeader)) // Add only if not already in set - Int->Successors.push_back(NodeHeader); - } - } else { // Otherwise, not in interval yet - for (typename IGT::ChildIteratorType I = IGT::child_begin(Node), - E = IGT::child_end(Node); I != E; ++I) { - if (!Int->contains(*I)) { // If pred not in interval, we can't be - if (!Int->isSuccessor(NodeHeader)) // Add only if not already in set - Int->Successors.push_back(NodeHeader); - return; // See you later - } - } - - // If we get here, then all of the predecessors of BB are in the interval - // already. In this case, we must add BB to the interval! - addNodeToInterval(Int, Node); - Visited.insert(NodeHeader); // The node has now been visited! - - if (Int->isSuccessor(NodeHeader)) { - // If we were in the successor list from before... remove from succ list - llvm::erase(Int->Successors, NodeHeader); - } - - // Now that we have discovered that Node is in the interval, perhaps some - // of its successors are as well? - for (typename GT::ChildIteratorType It = GT::child_begin(Node), - End = GT::child_end(Node); It != End; ++It) - ProcessNode(Int, getSourceGraphNode(OrigContainer, *It)); - } - } -}; - -using function_interval_iterator = IntervalIterator; -using interval_part_interval_iterator = - IntervalIterator; - -inline function_interval_iterator intervals_begin(Function *F, - bool DeleteInts = true) { - return function_interval_iterator(F, DeleteInts); -} -inline function_interval_iterator intervals_end(Function *) { - return function_interval_iterator(); -} - -inline interval_part_interval_iterator - intervals_begin(IntervalPartition &IP, bool DeleteIntervals = true) { - return interval_part_interval_iterator(IP, DeleteIntervals); -} - -inline interval_part_interval_iterator intervals_end(IntervalPartition &IP) { - return interval_part_interval_iterator(); -} - -} // end namespace llvm - -#endif // LLVM_ANALYSIS_INTERVALITERATOR_H diff --git a/llvm/include/llvm/Analysis/IntervalPartition.h b/llvm/include/llvm/Analysis/IntervalPartition.h deleted file mode 100644 index 66a99fb15bfb..000000000000 --- a/llvm/include/llvm/Analysis/IntervalPartition.h +++ /dev/null @@ -1,108 +0,0 @@ -//===- IntervalPartition.h - Interval partition Calculation -----*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the IntervalPartition class, which -// calculates and represents the interval partition of a function, or a -// preexisting interval partition. -// -// In this way, the interval partition may be used to reduce a flow graph down -// to its degenerate single node interval partition (unless it is irreducible). -// -// TODO: The IntervalPartition class should take a bool parameter that tells -// whether it should add the "tails" of an interval to an interval itself or if -// they should be represented as distinct intervals. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_ANALYSIS_INTERVALPARTITION_H -#define LLVM_ANALYSIS_INTERVALPARTITION_H - -#include "llvm/Pass.h" -#include -#include - -namespace llvm { - -class BasicBlock; -class Interval; - -//===----------------------------------------------------------------------===// -// -// IntervalPartition - This class builds and holds an "interval partition" for -// a function. This partition divides the control flow graph into a set of -// maximal intervals, as defined with the properties above. Intuitively, an -// interval is a (possibly nonexistent) loop with a "tail" of non-looping -// nodes following it. -// -class IntervalPartition : public FunctionPass { - using IntervalMapTy = std::map; - IntervalMapTy IntervalMap; - - using IntervalListTy = std::vector; - Interval *RootInterval = nullptr; - std::vector Intervals; - -public: - static char ID; // Pass identification, replacement for typeid - - IntervalPartition(); - - // run - Calculate the interval partition for this function - bool runOnFunction(Function &F) override; - - // IntervalPartition ctor - Build a reduced interval partition from an - // existing interval graph. This takes an additional boolean parameter to - // distinguish it from a copy constructor. Always pass in false for now. - IntervalPartition(IntervalPartition &I, bool); - - // print - Show contents in human readable format... - void print(raw_ostream &O, const Module* = nullptr) const override; - - // getRootInterval() - Return the root interval that contains the starting - // block of the function. - inline Interval *getRootInterval() { return RootInterval; } - - // isDegeneratePartition() - Returns true if the interval partition contains - // a single interval, and thus cannot be simplified anymore. - bool isDegeneratePartition() { return Intervals.size() == 1; } - - // TODO: isIrreducible - look for triangle graph. - - // getBlockInterval - Return the interval that a basic block exists in. - inline Interval *getBlockInterval(BasicBlock *BB) { - IntervalMapTy::iterator I = IntervalMap.find(BB); - return I != IntervalMap.end() ? I->second : nullptr; - } - - // getAnalysisUsage - Implement the Pass API - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesAll(); - } - - // Interface to Intervals vector... - const std::vector &getIntervals() const { return Intervals; } - - // releaseMemory - Reset state back to before function was analyzed - void releaseMemory() override; - -private: - // addIntervalToPartition - Add an interval to the internal list of intervals, - // and then add mappings from all of the basic blocks in the interval to the - // interval itself (in the IntervalMap). - void addIntervalToPartition(Interval *I); - - // updatePredecessors - Interval generation only sets the successor fields of - // the interval data structures. After interval generation is complete, - // run through all of the intervals and propagate successor info as - // predecessor info. - void updatePredecessors(Interval *Int); -}; - -} // end namespace llvm - -#endif // LLVM_ANALYSIS_INTERVALPARTITION_H diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index e4bf3868d000..9ba75d491c1c 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -136,7 +136,6 @@ void initializeInstructionCombiningPassPass(PassRegistry&); void initializeInstructionSelectPass(PassRegistry&); void initializeInterleavedAccessPass(PassRegistry&); void initializeInterleavedLoadCombinePass(PassRegistry &); -void initializeIntervalPartitionPass(PassRegistry&); void initializeJMCInstrumenterPass(PassRegistry&); void initializeKCFIPass(PassRegistry &); void initializeLCSSAVerificationPassPass(PassRegistry&); diff --git a/llvm/include/llvm/LinkAllPasses.h b/llvm/include/llvm/LinkAllPasses.h index 2eaed42e62fc..30e7c22f3146 100644 --- a/llvm/include/llvm/LinkAllPasses.h +++ b/llvm/include/llvm/LinkAllPasses.h @@ -21,7 +21,6 @@ #include "llvm/Analysis/CallPrinter.h" #include "llvm/Analysis/DomPrinter.h" #include "llvm/Analysis/GlobalsModRef.h" -#include "llvm/Analysis/IntervalPartition.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/PostDominators.h" #include "llvm/Analysis/RegionPass.h" @@ -139,7 +138,6 @@ namespace { (void) llvm::createFixIrreduciblePass(); (void)llvm::createSelectOptimizePass(); - (void)new llvm::IntervalPartition(); (void)new llvm::ScalarEvolutionWrapperPass(); llvm::Function::Create(nullptr, llvm::GlobalValue::ExternalLinkage)->viewCFGOnly(); llvm::RGPassManager RGM; diff --git a/llvm/lib/Analysis/Analysis.cpp b/llvm/lib/Analysis/Analysis.cpp index 44d2ff18a694..11cc6cfccea6 100644 --- a/llvm/lib/Analysis/Analysis.cpp +++ b/llvm/lib/Analysis/Analysis.cpp @@ -38,7 +38,6 @@ void llvm::initializeAnalysis(PassRegistry &Registry) { initializeAAResultsWrapperPassPass(Registry); initializeGlobalsAAWrapperPassPass(Registry); initializeIVUsersWrapperPassPass(Registry); - initializeIntervalPartitionPass(Registry); initializeIRSimilarityIdentifierWrapperPassPass(Registry); initializeLazyBranchProbabilityInfoPassPass(Registry); initializeLazyBlockFrequencyInfoPassPass(Registry); diff --git a/llvm/lib/Analysis/CMakeLists.txt b/llvm/lib/Analysis/CMakeLists.txt index 35ea03f42f82..474b8d20fde1 100644 --- a/llvm/lib/Analysis/CMakeLists.txt +++ b/llvm/lib/Analysis/CMakeLists.txt @@ -76,8 +76,6 @@ add_llvm_component_library(LLVMAnalysis InstructionPrecedenceTracking.cpp InstructionSimplify.cpp InteractiveModelRunner.cpp - Interval.cpp - IntervalPartition.cpp LazyBranchProbabilityInfo.cpp LazyBlockFrequencyInfo.cpp LazyCallGraph.cpp diff --git a/llvm/lib/Analysis/Interval.cpp b/llvm/lib/Analysis/Interval.cpp deleted file mode 100644 index f7fffcb3d5e6..000000000000 --- a/llvm/lib/Analysis/Interval.cpp +++ /dev/null @@ -1,39 +0,0 @@ -//===- Interval.cpp - Interval class code ---------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file contains the definition of the Interval class, which represents a -// partition of a control flow graph of some kind. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Analysis/Interval.h" -#include "llvm/IR/BasicBlock.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -//===----------------------------------------------------------------------===// -// Interval Implementation -//===----------------------------------------------------------------------===// - -void Interval::print(raw_ostream &OS) const { - OS << "-------------------------------------------------------------\n" - << "Interval Contents:\n"; - - // Print out all of the basic blocks in the interval... - for (const BasicBlock *Node : Nodes) - OS << *Node << "\n"; - - OS << "Interval Predecessors:\n"; - for (const BasicBlock *Predecessor : Predecessors) - OS << *Predecessor << "\n"; - - OS << "Interval Successors:\n"; - for (const BasicBlock *Successor : Successors) - OS << *Successor << "\n"; -} diff --git a/llvm/lib/Analysis/IntervalPartition.cpp b/llvm/lib/Analysis/IntervalPartition.cpp deleted file mode 100644 index d9620fd405bc..000000000000 --- a/llvm/lib/Analysis/IntervalPartition.cpp +++ /dev/null @@ -1,118 +0,0 @@ -//===- IntervalPartition.cpp - Interval Partition module code -------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file contains the definition of the IntervalPartition class, which -// calculates and represent the interval partition of a function. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Analysis/IntervalPartition.h" -#include "llvm/Analysis/Interval.h" -#include "llvm/Analysis/IntervalIterator.h" -#include "llvm/InitializePasses.h" -#include "llvm/Pass.h" -#include -#include - -using namespace llvm; - -char IntervalPartition::ID = 0; - -IntervalPartition::IntervalPartition() : FunctionPass(ID) { - initializeIntervalPartitionPass(*PassRegistry::getPassRegistry()); -} - -INITIALIZE_PASS(IntervalPartition, "intervals", - "Interval Partition Construction", true, true) - -//===----------------------------------------------------------------------===// -// IntervalPartition Implementation -//===----------------------------------------------------------------------===// - -// releaseMemory - Reset state back to before function was analyzed -void IntervalPartition::releaseMemory() { - for (Interval *I : Intervals) - delete I; - IntervalMap.clear(); - Intervals.clear(); - RootInterval = nullptr; -} - -void IntervalPartition::print(raw_ostream &O, const Module*) const { - for (const Interval *I : Intervals) - I->print(O); -} - -// addIntervalToPartition - Add an interval to the internal list of intervals, -// and then add mappings from all of the basic blocks in the interval to the -// interval itself (in the IntervalMap). -void IntervalPartition::addIntervalToPartition(Interval *I) { - Intervals.push_back(I); - - // Add mappings for all of the basic blocks in I to the IntervalPartition - for (Interval::node_iterator It = I->Nodes.begin(), End = I->Nodes.end(); - It != End; ++It) - IntervalMap.insert(std::make_pair(*It, I)); -} - -// updatePredecessors - Interval generation only sets the successor fields of -// the interval data structures. After interval generation is complete, -// run through all of the intervals and propagate successor info as -// predecessor info. -void IntervalPartition::updatePredecessors(Interval *Int) { - BasicBlock *Header = Int->getHeaderNode(); - for (BasicBlock *Successor : Int->Successors) - getBlockInterval(Successor)->Predecessors.push_back(Header); -} - -// IntervalPartition ctor - Build the first level interval partition for the -// specified function... -bool IntervalPartition::runOnFunction(Function &F) { - // Pass false to intervals_begin because we take ownership of it's memory - function_interval_iterator I = intervals_begin(&F, false); - assert(I != intervals_end(&F) && "No intervals in function!?!?!"); - - addIntervalToPartition(RootInterval = *I); - - ++I; // After the first one... - - // Add the rest of the intervals to the partition. - for (function_interval_iterator E = intervals_end(&F); I != E; ++I) - addIntervalToPartition(*I); - - // Now that we know all of the successor information, propagate this to the - // predecessors for each block. - for (Interval *I : Intervals) - updatePredecessors(I); - return false; -} - -// IntervalPartition ctor - Build a reduced interval partition from an -// existing interval graph. This takes an additional boolean parameter to -// distinguish it from a copy constructor. Always pass in false for now. -IntervalPartition::IntervalPartition(IntervalPartition &IP, bool) - : FunctionPass(ID) { - assert(IP.getRootInterval() && "Cannot operate on empty IntervalPartitions!"); - - // Pass false to intervals_begin because we take ownership of it's memory - interval_part_interval_iterator I = intervals_begin(IP, false); - assert(I != intervals_end(IP) && "No intervals in interval partition!?!?!"); - - addIntervalToPartition(RootInterval = *I); - - ++I; // After the first one... - - // Add the rest of the intervals to the partition. - for (interval_part_interval_iterator E = intervals_end(IP); I != E; ++I) - addIntervalToPartition(*I); - - // Now that we know all of the successor information, propagate this to the - // predecessors for each block. - for (Interval *I : Intervals) - updatePredecessors(I); -} diff --git a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp index 09177950fc82..ec5fc06d01fb 100644 --- a/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp +++ b/llvm/lib/CodeGen/AssignmentTrackingAnalysis.cpp @@ -15,7 +15,6 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/UniqueVector.h" -#include "llvm/Analysis/Interval.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/DataLayout.h" diff --git a/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn index 27f7e2b395ec..4f03e01c39c1 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn @@ -65,8 +65,6 @@ static_library("Analysis") { "InstructionPrecedenceTracking.cpp", "InstructionSimplify.cpp", "InteractiveModelRunner.cpp", - "Interval.cpp", - "IntervalPartition.cpp", "LazyBlockFrequencyInfo.cpp", "LazyBranchProbabilityInfo.cpp", "LazyCallGraph.cpp", -- GitLab From 759bab068157d93a71ef20dc28a2eaed4fec6d40 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Sun, 7 Apr 2024 14:40:21 -0500 Subject: [PATCH 318/695] [InstCombine] Add tests for folding `(icmp eq/ne (add nuw x, y), 0)`; NFC --- llvm/test/Transforms/InstCombine/icmp-add.ll | 24 ++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll index b99ed20d7d43..6f990890dbb2 100644 --- a/llvm/test/Transforms/InstCombine/icmp-add.ll +++ b/llvm/test/Transforms/InstCombine/icmp-add.ll @@ -3003,4 +3003,28 @@ define i1 @icmp_dec_notnonzero(i8 %x) { ret i1 %c } +define i1 @icmp_addnuw_nonzero(i8 %x, i8 %y) { +; CHECK-LABEL: @icmp_addnuw_nonzero( +; CHECK-NEXT: [[I:%.*]] = sub i8 0, [[Y:%.*]] +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[I]], [[X:%.*]] +; CHECK-NEXT: ret i1 [[C]] +; + %i = add nuw i8 %x, %y + %c = icmp eq i8 %i, 0 + ret i1 %c +} + +define i1 @icmp_addnuw_nonzero_fail_multiuse(i32 %x, i32 %y) { +; CHECK-LABEL: @icmp_addnuw_nonzero_fail_multiuse( +; CHECK-NEXT: [[I:%.*]] = add nuw i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[I]], 0 +; CHECK-NEXT: call void @use(i32 [[I]]) +; CHECK-NEXT: ret i1 [[C]] +; + %i = add nuw i32 %x, %y + %c = icmp eq i32 %i, 0 + call void @use(i32 %i) + ret i1 %c +} + declare void @llvm.assume(i1) -- GitLab From 7599d478efb1576b5013d17a70971f76d6f7c25a Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Sun, 7 Apr 2024 14:38:03 -0500 Subject: [PATCH 319/695] [InstCombine] Fold `(icmp eq/ne (add nuw x, y), 0)` -> `(icmp eq/ne (or x, y), 0)` `(icmp eq/ne (or x, y), 0)` is probably easier to analyze than `(icmp eq/ne x, -y)` Proof: https://alive2.llvm.org/ce/z/2-VTb6 Closes #88088 --- .../InstCombine/InstCombineCompares.cpp | 5 +++++ llvm/test/Transforms/InstCombine/icmp-add.ll | 16 ++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index db302d7e5268..53aa84d53f30 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -3453,6 +3453,11 @@ Instruction *InstCombinerImpl::foldICmpBinOpEqualityWithConstant( if (Value *NegVal = dyn_castNegVal(BOp0)) return new ICmpInst(Pred, NegVal, BOp1); if (BO->hasOneUse()) { + // (add nuw A, B) != 0 -> (or A, B) != 0 + if (match(BO, m_NUWAdd(m_Value(), m_Value()))) { + Value *Or = Builder.CreateOr(BOp0, BOp1); + return new ICmpInst(Pred, Or, Constant::getNullValue(BO->getType())); + } Value *Neg = Builder.CreateNeg(BOp1); Neg->takeName(BO); return new ICmpInst(Pred, BOp0, Neg); diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll index 6f990890dbb2..6b4e5a5372c5 100644 --- a/llvm/test/Transforms/InstCombine/icmp-add.ll +++ b/llvm/test/Transforms/InstCombine/icmp-add.ll @@ -9,10 +9,8 @@ declare void @use(i32) define i1 @cvt_icmp_0_zext_plus_zext_eq_i16(i16 %arg, i16 %arg1) { ; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_eq_i16( ; CHECK-NEXT: bb: -; CHECK-NEXT: [[I:%.*]] = zext i16 [[ARG:%.*]] to i32 -; CHECK-NEXT: [[I2:%.*]] = zext i16 [[ARG1:%.*]] to i32 -; CHECK-NEXT: [[I3:%.*]] = sub nsw i32 0, [[I]] -; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I2]], [[I3]] +; CHECK-NEXT: [[TMP0:%.*]] = or i16 [[ARG1:%.*]], [[ARG:%.*]] +; CHECK-NEXT: [[I4:%.*]] = icmp eq i16 [[TMP0]], 0 ; CHECK-NEXT: ret i1 [[I4]] ; bb: @@ -27,10 +25,8 @@ bb: define i1 @cvt_icmp_0_zext_plus_zext_eq_i8(i8 %arg, i8 %arg1) { ; CHECK-LABEL: @cvt_icmp_0_zext_plus_zext_eq_i8( ; CHECK-NEXT: bb: -; CHECK-NEXT: [[I:%.*]] = zext i8 [[ARG:%.*]] to i32 -; CHECK-NEXT: [[I2:%.*]] = zext i8 [[ARG1:%.*]] to i32 -; CHECK-NEXT: [[I3:%.*]] = sub nsw i32 0, [[I]] -; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I2]], [[I3]] +; CHECK-NEXT: [[TMP0:%.*]] = or i8 [[ARG1:%.*]], [[ARG:%.*]] +; CHECK-NEXT: [[I4:%.*]] = icmp eq i8 [[TMP0]], 0 ; CHECK-NEXT: ret i1 [[I4]] ; bb: @@ -3005,8 +3001,8 @@ define i1 @icmp_dec_notnonzero(i8 %x) { define i1 @icmp_addnuw_nonzero(i8 %x, i8 %y) { ; CHECK-LABEL: @icmp_addnuw_nonzero( -; CHECK-NEXT: [[I:%.*]] = sub i8 0, [[Y:%.*]] -; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[I]], [[X:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[C]] ; %i = add nuw i8 %x, %y -- GitLab From e248f0df14e407b8ae98cd31fb2e77fc058f3c7e Mon Sep 17 00:00:00 2001 From: Daniel Chen Date: Tue, 9 Apr 2024 15:05:12 -0400 Subject: [PATCH 320/695] [Flang] Update Extensions.md for supported BIND(C) LOGICAL kind. (#88159) Flang also supports non-scalar logical dummy argument with a different KIND from C_BOOL to a bind(c) routine as well as a component in a bind(c) derived type. Update the document. ``` subroutine sub(arg) logical(4) :: arg(4) end ``` ``` type dt logical(4) :: comp end type end ``` --- flang/docs/Extensions.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/flang/docs/Extensions.md b/flang/docs/Extensions.md index 4c3847291a3f..9030207d9bda 100644 --- a/flang/docs/Extensions.md +++ b/flang/docs/Extensions.md @@ -308,9 +308,10 @@ end enforce it and the constraint is not necessary for a correct implementation. * A label may follow a semicolon in fixed form source. -* A scalar logical dummy argument to a `BIND(C)` procedure does - not have to have `KIND=C_BOOL` since it can be converted to/from - `_Bool` without loss of information. +* A logical dummy argument to a `BIND(C)` procedure, or a logical + component to a `BIND(C)` derived type does not have to have + `KIND=C_BOOL` since it can be converted to/from `_Bool` without + loss of information. * The character length of the `SOURCE=` or `MOLD=` in `ALLOCATE` may be distinct from the constant character length, if any, of an allocated object. -- GitLab From 9797a7ea6bf84b48f267c781be209951d62bc6c9 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Apr 2024 12:32:15 -0700 Subject: [PATCH 321/695] [DWARF] Refactor findDebugNamesOffsets Address some post-review comments in #82153 and move the function inside llvm::dwarf, used by certain free functions. Pull Request: https://github.com/llvm/llvm-project/pull/88064 --- .../DebugInfo/DWARF/DWARFAcceleratorTable.h | 8 ++-- .../DebugInfo/DWARF/DWARFAcceleratorTable.cpp | 43 ++++++++----------- 2 files changed, 22 insertions(+), 29 deletions(-) diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h index f1d4fc72d5a7..9543b78ea613 100644 --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h @@ -804,9 +804,11 @@ public: /// Calculates the starting offsets for various sections within the /// .debug_names section. -void findDebugNamesOffsets(DWARFDebugNames::DWARFDebugNamesOffsets &Offsets, - uint64_t HdrSize, const dwarf::DwarfFormat Format, - const DWARFDebugNames::Header &Hdr); +namespace dwarf { +DWARFDebugNames::DWARFDebugNamesOffsets +findDebugNamesOffsets(uint64_t EndOfHeaderOffset, + const DWARFDebugNames::Header &Hdr); +} /// If `Name` is the name of a templated function that includes template /// parameters, returns a substring of `Name` containing no template diff --git a/llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp b/llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp index 9c65d85985f1..22c9e8cd143c 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp @@ -552,31 +552,22 @@ DWARFDebugNames::NameIndex::extractAbbrev(uint64_t *Offset) { return Abbrev(Code, dwarf::Tag(Tag), AbbrevOffset, std::move(*AttrEncOr)); } -void llvm::findDebugNamesOffsets( - DWARFDebugNames::DWARFDebugNamesOffsets &Offsets, uint64_t HdrSize, - dwarf::DwarfFormat Format, const DWARFDebugNames::Header &Hdr) { - uint32_t DwarfSize = (Format == llvm::dwarf::DwarfFormat::DWARF64) ? 8 : 4; - uint64_t Offset = HdrSize; - Offsets.CUsBase = Offset; - Offset += Hdr.CompUnitCount * DwarfSize; - Offset += Hdr.LocalTypeUnitCount * DwarfSize; - Offset += Hdr.ForeignTypeUnitCount * 8; - - Offsets.BucketsBase = Offset; - Offset += Hdr.BucketCount * 4; - - Offsets.HashesBase = Offset; - if (Hdr.BucketCount > 0) - Offset += Hdr.NameCount * 4; - - Offsets.StringOffsetsBase = Offset; - Offset += Hdr.NameCount * DwarfSize; - - Offsets.EntryOffsetsBase = Offset; - Offset += Hdr.NameCount * DwarfSize; - - Offset += Hdr.AbbrevTableSize; - Offsets.EntriesBase = Offset; +DWARFDebugNames::DWARFDebugNamesOffsets +dwarf::findDebugNamesOffsets(uint64_t EndOfHeaderOffset, + const DWARFDebugNames::Header &Hdr) { + uint64_t DwarfSize = getDwarfOffsetByteSize(Hdr.Format); + DWARFDebugNames::DWARFDebugNamesOffsets Ret; + Ret.CUsBase = EndOfHeaderOffset; + Ret.BucketsBase = Ret.CUsBase + Hdr.CompUnitCount * DwarfSize + + Hdr.LocalTypeUnitCount * DwarfSize + + Hdr.ForeignTypeUnitCount * 8; + Ret.HashesBase = Ret.BucketsBase + Hdr.BucketCount * 4; + Ret.StringOffsetsBase = + Ret.HashesBase + (Hdr.BucketCount > 0 ? Hdr.NameCount * 4 : 0); + Ret.EntryOffsetsBase = Ret.StringOffsetsBase + Hdr.NameCount * DwarfSize; + Ret.EntriesBase = + Ret.EntryOffsetsBase + Hdr.NameCount * DwarfSize + Hdr.AbbrevTableSize; + return Ret; } Error DWARFDebugNames::NameIndex::extract() { @@ -586,7 +577,7 @@ Error DWARFDebugNames::NameIndex::extract() { return E; const unsigned SectionOffsetSize = dwarf::getDwarfOffsetByteSize(Hdr.Format); - findDebugNamesOffsets(Offsets, hdrSize, Hdr.Format, Hdr); + Offsets = dwarf::findDebugNamesOffsets(hdrSize, Hdr); uint64_t Offset = Offsets.EntryOffsetsBase + (Hdr.NameCount * SectionOffsetSize); -- GitLab From 9d9560facb5597e0232ab15716a7915a33d4f0a6 Mon Sep 17 00:00:00 2001 From: Raghu Maddhipatla <7686592+raghavendhra@users.noreply.github.com> Date: Tue, 9 Apr 2024 14:59:20 -0500 Subject: [PATCH 322/695] [Flang] [OpenMP] [Semantics] [MLIR] [Lowering] Add lowering support for IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses on OMP TARGET directive. (#74187) Added lowering support for IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses for OMP TARGET directive and added related tests for these changes. IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses apply to OMP TARGET directive OpenMP spec states `The **is_device_ptr** clause indicates that its list items are device pointers.` `The **has_device_addr** clause indicates that its list items already have device addresses and therefore they may be directly accessed from a target device.` Whereas USE_DEVICE_PTR and USE_DEVICE_ADDR clauses apply to OMP TARGET DATA directive and OpenMP spec for them states `Each list item in the **use_device_ptr** clause results in a new list item that is a device pointer that refers to a device address` `Each list item in a **use_device_addr** clause that is present in the device data environment is treated as if it is implicitly mapped by a map clause on the construct with a map-type of alloc` --- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 29 +++++++++++++ flang/lib/Lower/OpenMP/ClauseProcessor.h | 12 ++++++ flang/lib/Lower/OpenMP/OpenMP.cpp | 22 +++++++--- flang/test/Lower/OpenMP/FIR/target.f90 | 43 ++++++++++++++++++- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 18 ++++++-- mlir/test/Dialect/OpenMP/invalid.mlir | 2 +- mlir/test/Dialect/OpenMP/ops.mlir | 8 ++-- 7 files changed, 120 insertions(+), 14 deletions(-) diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 0a57a1496289..fb24c8d1fe3e 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -751,6 +751,20 @@ bool ClauseProcessor::processDepend( }); } +bool ClauseProcessor::processHasDeviceAddr( + llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl &isDeviceSymbols) + const { + return findRepeatableClause( + [&](const omp::clause::HasDeviceAddr &devAddrClause, + const Fortran::parser::CharBlock &) { + addUseDeviceClause(converter, devAddrClause.v, operands, isDeviceTypes, + isDeviceLocs, isDeviceSymbols); + }); +} + bool ClauseProcessor::processIf( omp::clause::If::DirectiveNameModifier directiveName, mlir::Value &result) const { @@ -771,6 +785,20 @@ bool ClauseProcessor::processIf( return found; } +bool ClauseProcessor::processIsDevicePtr( + llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl &isDeviceSymbols) + const { + return findRepeatableClause( + [&](const omp::clause::IsDevicePtr &devPtrClause, + const Fortran::parser::CharBlock &) { + addUseDeviceClause(converter, devPtrClause.v, operands, isDeviceTypes, + isDeviceLocs, isDeviceSymbols); + }); +} + bool ClauseProcessor::processLink( llvm::SmallVectorImpl &result) const { return findRepeatableClause( @@ -993,6 +1021,7 @@ bool ClauseProcessor::processUseDevicePtr( useDeviceLocs, useDeviceSymbols); }); } + } // namespace omp } // namespace lower } // namespace Fortran diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.h b/flang/lib/Lower/OpenMP/ClauseProcessor.h index d31d6a5c2062..df8f4f5310fc 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.h +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.h @@ -66,6 +66,12 @@ public: bool processDeviceType(mlir::omp::DeclareTargetDeviceType &result) const; bool processFinal(Fortran::lower::StatementContext &stmtCtx, mlir::Value &result) const; + bool + processHasDeviceAddr(llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl + &isDeviceSymbols) const; bool processHint(mlir::IntegerAttr &result) const; bool processMergeable(mlir::UnitAttr &result) const; bool processNowait(mlir::UnitAttr &result) const; @@ -104,6 +110,12 @@ public: bool processIf(omp::clause::If::DirectiveNameModifier directiveName, mlir::Value &result) const; bool + processIsDevicePtr(llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl + &isDeviceSymbols) const; + bool processLink(llvm::SmallVectorImpl &result) const; // This method is used to process a map clause. diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 340921c86724..50ad889052ab 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -1294,6 +1294,11 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, llvm::SmallVector mapSymTypes; llvm::SmallVector mapSymLocs; llvm::SmallVector mapSymbols; + llvm::SmallVector devicePtrOperands, deviceAddrOperands; + llvm::SmallVector devicePtrTypes, deviceAddrTypes; + llvm::SmallVector devicePtrLocs, deviceAddrLocs; + llvm::SmallVector devicePtrSymbols, + deviceAddrSymbols; ClauseProcessor cp(converter, semaCtx, clauseList); cp.processIf(llvm::omp::Directive::OMPD_target, ifClauseOperand); @@ -1303,11 +1308,15 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, cp.processNowait(nowaitAttr); cp.processMap(currentLocation, directive, stmtCtx, mapOperands, &mapSymTypes, &mapSymLocs, &mapSymbols); + cp.processIsDevicePtr(devicePtrOperands, devicePtrTypes, devicePtrLocs, + devicePtrSymbols); + cp.processHasDeviceAddr(deviceAddrOperands, deviceAddrTypes, deviceAddrLocs, + deviceAddrSymbols); - cp.processTODO( - currentLocation, llvm::omp::Directive::OMPD_target); + cp.processTODO(currentLocation, + llvm::omp::Directive::OMPD_target); // 5.8.1 Implicit Data-Mapping Attribute Rules // The following code follows the implicit data-mapping rules to map all the @@ -1400,7 +1409,8 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, ? nullptr : mlir::ArrayAttr::get(converter.getFirOpBuilder().getContext(), dependTypeOperands), - dependOperands, nowaitAttr, mapOperands); + dependOperands, nowaitAttr, devicePtrOperands, deviceAddrOperands, + mapOperands); genBodyOfTargetOp(converter, semaCtx, eval, genNested, targetOp, mapSymTypes, mapSymLocs, mapSymbols, currentLocation); @@ -2059,6 +2069,8 @@ genOMP(Fortran::lower::AbstractConverter &converter, !std::get_if(&clause.u) && !std::get_if(&clause.u) && !std::get_if(&clause.u) && + !std::get_if(&clause.u) && + !std::get_if(&clause.u) && !std::get_if(&clause.u) && !std::get_if(&clause.u)) { TODO(clauseLocation, "OpenMP Block construct clause"); diff --git a/flang/test/Lower/OpenMP/FIR/target.f90 b/flang/test/Lower/OpenMP/FIR/target.f90 index 821196b83c3b..022327f9c25d 100644 --- a/flang/test/Lower/OpenMP/FIR/target.f90 +++ b/flang/test/Lower/OpenMP/FIR/target.f90 @@ -506,4 +506,45 @@ subroutine omp_target_parallel_do !CHECK: omp.terminator !CHECK: } !$omp end target parallel do - end subroutine omp_target_parallel_do +end subroutine omp_target_parallel_do + +!=============================================================================== +! Target `is_device_ptr` clause +!=============================================================================== + +!CHECK-LABEL: func.func @_QPomp_target_is_device_ptr() { +subroutine omp_target_is_device_ptr + use iso_c_binding, only : c_ptr, c_loc + !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> {bindc_name = "a", uniq_name = "_QFomp_target_is_device_ptrEa"} + type(c_ptr) :: a + !CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "b", fir.target, uniq_name = "_QFomp_target_is_device_ptrEb"} + integer, target :: b + !CHECK: %[[MAP_0:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(tofrom) capture(ByRef) -> !fir.ref> {name = "a"} + !CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr(%[[VAL_0:.*]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "b"} + !CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByRef) -> !fir.ref> {name = "a"} + !CHECK: omp.target is_device_ptr(%[[DEV_PTR:.*]] : !fir.ref>) map_entries(%[[MAP_0:.*]] -> %[[ARG0:.*]], %[[MAP_1:.*]] -> %[[ARG1:.*]], %[[MAP_2:.*]] -> %[[ARG2:.*]] : !fir.ref>, !fir.ref, !fir.ref>) { + !CHECK: ^bb0(%[[ARG0]]: !fir.ref>, %[[ARG1]]: !fir.ref, %[[ARG2]]: !fir.ref>): + !$omp target map(tofrom: a,b) is_device_ptr(a) + !CHECK: {{.*}} = fir.coordinate_of %[[VAL_0:.*]], {{.*}} : (!fir.ref>, !fir.field) -> !fir.ref + a = c_loc(b) + !CHECK: omp.terminator + !$omp end target + !CHECK: } +end subroutine omp_target_is_device_ptr + + !=============================================================================== + ! Target `has_device_addr` clause + !=============================================================================== + + !CHECK-LABEL: func.func @_QPomp_target_has_device_addr() { + subroutine omp_target_has_device_addr + !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFomp_target_has_device_addrEa"} + integer, pointer :: a + !CHECK: omp.target has_device_addr(%[[VAL_0:.*]] : !fir.ref>>) map_entries({{.*}} -> {{.*}}, {{.*}} -> {{.*}} : !fir.llvm_ptr>, !fir.ref>>) { + !$omp target has_device_addr(a) + !CHECK: {{.*}} = fir.load %[[VAL_0:.*]] : !fir.ref>> + a = 10 + !CHECK: omp.terminator + !$omp end target + !CHECK: } +end subroutine omp_target_has_device_addr diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index a38a82f9cc60..2a8582be3833 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -1678,14 +1678,23 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac The optional $thread_limit specifies the limit on the number of threads - The optional $nowait elliminates the implicit barrier so the parent task can make progress + The optional $nowait eliminates the implicit barrier so the parent task can make progress even if the target task is not yet completed. The `depends` and `depend_vars` arguments are variadic lists of values that specify the dependencies of this particular target task in relation to other tasks. - TODO: is_device_ptr, defaultmap, in_reduction + The optional $is_device_ptr indicates list items are device pointers. + + The optional $has_device_addr indicates that list items already have device + addresses, so they may be directly accessed from the target device. This + includes array sections. + + The optional $map_operands maps data from the task’s environment to the + device environment. + + TODO: defaultmap, in_reduction }]; @@ -1695,8 +1704,9 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac OptionalAttr:$depends, Variadic:$depend_vars, UnitAttr:$nowait, + Variadic:$is_device_ptr, + Variadic:$has_device_addr, Variadic:$map_operands); - let regions = (region AnyRegion:$region); let builders = [ @@ -1708,6 +1718,8 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac | `device` `(` $device `:` type($device) `)` | `thread_limit` `(` $thread_limit `:` type($thread_limit) `)` | `nowait` $nowait + | `is_device_ptr` `(` $is_device_ptr `:` type($is_device_ptr) `)` + | `has_device_addr` `(` $has_device_addr `:` type($has_device_addr) `)` | `map_entries` `(` custom($map_operands, type($map_operands)) `)` | `depend` `(` custom($depend_vars, type($depend_vars), $depends) `)` ) $region attr-dict diff --git a/mlir/test/Dialect/OpenMP/invalid.mlir b/mlir/test/Dialect/OpenMP/invalid.mlir index 1134db77d5ba..27a440b3f97c 100644 --- a/mlir/test/Dialect/OpenMP/invalid.mlir +++ b/mlir/test/Dialect/OpenMP/invalid.mlir @@ -1809,7 +1809,7 @@ func.func @omp_target_depend(%data_var: memref) { // expected-error @below {{op expected as many depend values as depend variables}} "omp.target"(%data_var) ({ "omp.terminator"() : () -> () - }) {depends = [], operandSegmentSizes = array} : (memref) -> () + }) {depends = [], operandSegmentSizes = array} : (memref) -> () "func.return"() : () -> () } diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index e2c255c7a3cc..ad5b74b84ac7 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -510,22 +510,22 @@ return // CHECK-LABEL: omp_target -func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %map1: memref, %map2: memref) -> () { +func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %device_ptr: memref, %device_addr: memref, %map1: memref, %map2: memref) -> () { // Test with optional operands; if_expr, device, thread_limit, private, firstprivate and nowait. // CHECK: omp.target if({{.*}}) device({{.*}}) thread_limit({{.*}}) nowait "omp.target"(%if_cond, %device, %num_threads) ({ // CHECK: omp.terminator omp.terminator - }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () + }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () // Test with optional map clause. // CHECK: %[[MAP_A:.*]] = omp.map.info var_ptr(%[[VAL_1:.*]] : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} // CHECK: %[[MAP_B:.*]] = omp.map.info var_ptr(%[[VAL_2:.*]] : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} - // CHECK: omp.target map_entries(%[[MAP_A]] -> {{.*}}, %[[MAP_B]] -> {{.*}} : memref, memref) { + // CHECK: omp.target is_device_ptr(%[[VAL_4:.*]] : memref) has_device_addr(%[[VAL_5:.*]] : memref) map_entries(%[[MAP_A]] -> {{.*}}, %[[MAP_B]] -> {{.*}} : memref, memref) { %mapv1 = omp.map.info var_ptr(%map1 : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} %mapv2 = omp.map.info var_ptr(%map2 : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} - omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) { + omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) is_device_ptr(%device_ptr : memref) has_device_addr(%device_addr : memref) { ^bb0(%arg0: memref, %arg1: memref): omp.terminator } -- GitLab From aacb8985f734e7e11fc94947f7bc348d1d39f7af Mon Sep 17 00:00:00 2001 From: Ben Langmuir Date: Tue, 9 Apr 2024 13:01:00 -0700 Subject: [PATCH 323/695] [orc] Reduce memory usage from empty materialization info DenseMaps (#88167) Saves several MB of memory in larger applications after linking finishes by clearing DenseMap storage that is empty. This does not attempt to shrink partially full materialization infos. The assumption is that adding more after linking finishes is rare. rdar://126145336 --- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 4 ++++ llvm/lib/ExecutionEngine/Orc/Core.cpp | 23 ++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h index 09b2f6a10e35..7121b3fe7627 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h @@ -1333,6 +1333,10 @@ private: void unlinkMaterializationResponsibility(MaterializationResponsibility &MR); + /// Attempt to reduce memory usage from empty \c UnmaterializedInfos and + /// \c MaterializingInfos tables. + void shrinkMaterializationInfoMemory(); + ExecutionSession &ES; enum { Open, Closing, Closed } State = Open; std::mutex GeneratorsMutex; diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp index a9d1998e0930..4841a2d8c4fd 100644 --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -1002,6 +1002,17 @@ void JITDylib::unlinkMaterializationResponsibility( }); } +void JITDylib::shrinkMaterializationInfoMemory() { + // DenseMap::erase never shrinks its storage; use clear to heuristically free + // memory since we may have long-lived JDs after linking is done. + + if (UnmaterializedInfos.empty()) + UnmaterializedInfos.clear(); + + if (MaterializingInfos.empty()) + MaterializingInfos.clear(); +} + void JITDylib::setLinkOrder(JITDylibSearchOrder NewLinkOrder, bool LinkAgainstThisJITDylibFirst) { ES.runSessionLocked([&]() { @@ -1112,6 +1123,8 @@ Error JITDylib::remove(const SymbolNameSet &Names) { Symbols.erase(SymI); } + shrinkMaterializationInfoMemory(); + return Error::success(); }); } @@ -1313,6 +1326,8 @@ JITDylib::removeTracker(ResourceTracker &RT) { Symbols.erase(I); } + shrinkMaterializationInfoMemory(); + return Result; } @@ -2675,6 +2690,8 @@ void ExecutionSession::OL_completeLookup( return true; }); + JD.shrinkMaterializationInfoMemory(); + // Handle failure. if (Err) { @@ -3118,6 +3135,8 @@ void ExecutionSession::IL_makeEDUReady( JD.MaterializingInfos.erase(MII); } + + JD.shrinkMaterializationInfoMemory(); } void ExecutionSession::IL_makeEDUEmitted( @@ -3632,6 +3651,8 @@ ExecutionSession::IL_failSymbols(JITDylib &JD, ExtractFailedQueries(DepMI); DepJD.MaterializingInfos.erase(SymbolStringPtr(DepName)); } + + DepJD.shrinkMaterializationInfoMemory(); } MI.DependantEDUs.clear(); @@ -3645,6 +3666,8 @@ ExecutionSession::IL_failSymbols(JITDylib &JD, JD.MaterializingInfos.erase(Name); } + JD.shrinkMaterializationInfoMemory(); + #ifdef EXPENSIVE_CHECKS verifySessionState("exiting ExecutionSession::IL_failSymbols"); #endif -- GitLab From 4bc4c7baed1a4ef13a0964fbf97f4dc1560de592 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Tue, 9 Apr 2024 12:59:25 -0700 Subject: [PATCH 324/695] [NFC] Change name of two helper functions to match naming conventions Brought up in #88135, I inadvertently mis-named these functions, so correcting them here. --- clang/include/clang/Basic/OpenACCKinds.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index 4456f4afd142..95fc35a5bedb 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -67,7 +67,7 @@ enum class OpenACCDirectiveKind { }; template -inline StreamTy &PrintOpenACCDirectiveKind(StreamTy &Out, +inline StreamTy &printOpenACCDirectiveKind(StreamTy &Out, OpenACCDirectiveKind K) { switch (K) { case OpenACCDirectiveKind::Parallel: @@ -138,12 +138,12 @@ inline StreamTy &PrintOpenACCDirectiveKind(StreamTy &Out, inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &Out, OpenACCDirectiveKind K) { - return PrintOpenACCDirectiveKind(Out, K); + return printOpenACCDirectiveKind(Out, K); } inline llvm::raw_ostream &operator<<(llvm::raw_ostream &Out, OpenACCDirectiveKind K) { - return PrintOpenACCDirectiveKind(Out, K); + return printOpenACCDirectiveKind(Out, K); } enum class OpenACCAtomicKind { @@ -266,7 +266,7 @@ enum class OpenACCClauseKind { }; template -inline StreamTy &PrintOpenACCClauseKind(StreamTy &Out, OpenACCClauseKind K) { +inline StreamTy &printOpenACCClauseKind(StreamTy &Out, OpenACCClauseKind K) { switch (K) { case OpenACCClauseKind::Finalize: return Out << "finalize"; @@ -402,12 +402,12 @@ inline StreamTy &PrintOpenACCClauseKind(StreamTy &Out, OpenACCClauseKind K) { inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &Out, OpenACCClauseKind K) { - return PrintOpenACCClauseKind(Out, K); + return printOpenACCClauseKind(Out, K); } inline llvm::raw_ostream &operator<<(llvm::raw_ostream &Out, OpenACCClauseKind K) { - return PrintOpenACCClauseKind(Out, K); + return printOpenACCClauseKind(Out, K); } enum class OpenACCDefaultClauseKind { -- GitLab From 63934821d56f4d366f61048ed6060978bbde1bc6 Mon Sep 17 00:00:00 2001 From: Ziqing Luo Date: Tue, 9 Apr 2024 13:09:52 -0700 Subject: [PATCH 325/695] [Static Analyzer] Add handling of the `-nostdlibinc` option to ccc-analyzer (#88017) Compiler options recognizable to ccc-analyzer are stored in maps. An option missing in the map will be dropped by ccc-analyzer. This causes a build error in one of our projects that only happens in scan-build but not regular build, because ccc-analyzer do not recognize `-nostdlibinc`. This commit adds the option to the map. rdar://126082053 --- clang/tools/scan-build/libexec/ccc-analyzer | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/tools/scan-build/libexec/ccc-analyzer b/clang/tools/scan-build/libexec/ccc-analyzer index 60796a543fcd..c5588814e8f0 100755 --- a/clang/tools/scan-build/libexec/ccc-analyzer +++ b/clang/tools/scan-build/libexec/ccc-analyzer @@ -361,6 +361,7 @@ sub Analyze { my %CompileOptionMap = ( '-nostdinc' => 0, + '-nostdlibinc' => 0, '-include' => 1, '-idirafter' => 1, '-imacros' => 1, -- GitLab From fe5dba3c08e31db6b96119787b0836f180aac584 Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Tue, 9 Apr 2024 20:20:41 +0000 Subject: [PATCH 326/695] [bazel][libc] Add missing fenv dep for aarch64 For 49561181bdc8698aa28ee2a46d2faa4cf6767bbe. --- utils/bazel/llvm-project-overlay/libc/BUILD.bazel | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index ee9f5b8bd83d..d38dc3029f74 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -747,6 +747,7 @@ libc_support_library( ":__support_macros_properties_architectures", ":__support_macros_sanitizer", ":errno", + ":hdr_fenv_macros", ":hdr_math_macros", ], ) @@ -756,7 +757,7 @@ libc_support_library( hdrs = ["src/__support/FPUtil/rounding_mode.h"], deps = [ ":__support_macros_attributes", - ":hdr_fenv_macros", + ":hdr_fenv_macros", ], ) -- GitLab From 4ae8694cca1b19425ac8707eacc6959ca9770802 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Tue, 9 Apr 2024 13:22:09 -0700 Subject: [PATCH 327/695] gn build: Manually port a30662fc2acd --- .../gn/secondary/clang/include/clang/Basic/BUILD.gn | 10 ---------- llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn | 2 -- 2 files changed, 12 deletions(-) diff --git a/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn index b18b109dcff5..39ff9d0f18fa 100644 --- a/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn @@ -68,16 +68,6 @@ clang_tablegen("AttrList") { td_file = "Attr.td" } -clang_tablegen("AttrLeftSideCanPrintList") { - args = [ "-gen-clang-attr-can-print-left-list" ] - td_file = "Attr.td" -} - -clang_tablegen("AttrLeftSideMustPrintList") { - args = [ "-gen-clang-attr-must-print-left-list" ] - td_file = "Attr.td" -} - clang_tablegen("AttrSubMatchRulesList") { args = [ "-gen-clang-attr-subject-match-rule-list" ] td_file = "Attr.td" diff --git a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn index bbe937301620..05504ddb79f8 100644 --- a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn @@ -21,8 +21,6 @@ static_library("Basic") { configs += [ "//llvm/utils/gn/build:clang_code" ] public_deps = [ # public_dep because public header Version.h includes generated Version.inc. - "//clang/include/clang/Basic:AttrLeftSideCanPrintList", - "//clang/include/clang/Basic:AttrLeftSideMustPrintList", "//clang/include/clang/Basic:AttrList", "//clang/include/clang/Basic:AttrSubMatchRulesList", "//clang/include/clang/Basic:Builtins", -- GitLab From 2248164a9ab791a3ed1b9586dc340b5303155021 Mon Sep 17 00:00:00 2001 From: Jan Svoboda Date: Tue, 9 Apr 2024 11:28:24 -0700 Subject: [PATCH 328/695] Revert "[clang] Move state out of `PreprocessorOptions` (1/n) (#86358)" This reverts commit 407a2f23 which stopped propagating the callback to module compiles, effectively disabling dependency directive scanning for all modular dependencies. Also added a regression test. --- .../include/clang/Frontend/FrontendActions.h | 14 ++------ clang/include/clang/Lex/Preprocessor.h | 18 ---------- clang/include/clang/Lex/PreprocessorOptions.h | 13 ++++++++ clang/lib/Frontend/FrontendActions.cpp | 7 +--- clang/lib/Lex/PPLexerChange.cpp | 12 +++++-- .../DependencyScanningWorker.cpp | 33 ++++++++----------- ...tension.c => modules-minimize-extension.c} | 0 .../ClangScanDeps/modules-minimize-module.c | 24 ++++++++++++++ .../Lex/PPDependencyDirectivesTest.cpp | 11 +++---- 9 files changed, 67 insertions(+), 65 deletions(-) rename clang/test/ClangScanDeps/{modules-extension.c => modules-minimize-extension.c} (100%) create mode 100644 clang/test/ClangScanDeps/modules-minimize-module.c diff --git a/clang/include/clang/Frontend/FrontendActions.h b/clang/include/clang/Frontend/FrontendActions.h index 0518a8823a03..a620ddfc4044 100644 --- a/clang/include/clang/Frontend/FrontendActions.h +++ b/clang/include/clang/Frontend/FrontendActions.h @@ -34,18 +34,12 @@ public: /// Preprocessor-based frontend action that also loads PCH files. class ReadPCHAndPreprocessAction : public FrontendAction { - llvm::unique_function AdjustCI; - void ExecuteAction() override; std::unique_ptr CreateASTConsumer(CompilerInstance &CI, StringRef InFile) override; public: - ReadPCHAndPreprocessAction( - llvm::unique_function AdjustCI) - : AdjustCI(std::move(AdjustCI)) {} - bool usesPreprocessorOnly() const override { return false; } }; @@ -327,15 +321,11 @@ protected: class GetDependenciesByModuleNameAction : public PreprocessOnlyAction { StringRef ModuleName; - llvm::unique_function AdjustCI; - void ExecuteAction() override; public: - GetDependenciesByModuleNameAction( - StringRef ModuleName, - llvm::unique_function AdjustCI) - : ModuleName(ModuleName), AdjustCI(std::move(AdjustCI)) {} + GetDependenciesByModuleNameAction(StringRef ModuleName) + : ModuleName(ModuleName) {} }; } // end namespace clang diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 24e146a589a7..0836b7d439bb 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -736,19 +736,6 @@ private: State ConditionalStackState = Off; } PreambleConditionalStack; - /// Function for getting the dependency preprocessor directives of a file. - /// - /// These are directives derived from a special form of lexing where the - /// source input is scanned for the preprocessor directives that might have an - /// effect on the dependencies for a compilation unit. - /// - /// Enables a client to cache the directives for a file and provide them - /// across multiple compiler invocations. - /// FIXME: Allow returning an error. - using DependencyDirectivesFn = llvm::unique_function>(FileEntryRef)>; - DependencyDirectivesFn DependencyDirectivesForFile; - /// The current top of the stack that we're lexing from if /// not expanding a macro and we are lexing directly from source code. /// @@ -1283,11 +1270,6 @@ public: /// false if it is producing tokens to be consumed by Parse and Sema. bool isPreprocessedOutput() const { return PreprocessedOutput; } - /// Set the function used to get dependency directives for a file. - void setDependencyDirectivesFn(DependencyDirectivesFn Fn) { - DependencyDirectivesForFile = std::move(Fn); - } - /// Return true if we are lexing directly from the specified lexer. bool isCurrentLexer(const PreprocessorLexer *L) const { return CurPPLexer == L; diff --git a/clang/include/clang/Lex/PreprocessorOptions.h b/clang/include/clang/Lex/PreprocessorOptions.h index 50b5fba0ff77..635971d0ce5e 100644 --- a/clang/include/clang/Lex/PreprocessorOptions.h +++ b/clang/include/clang/Lex/PreprocessorOptions.h @@ -186,6 +186,19 @@ public: /// with support for lifetime-qualified pointers. ObjCXXARCStandardLibraryKind ObjCXXARCStandardLibrary = ARCXX_nolib; + /// Function for getting the dependency preprocessor directives of a file. + /// + /// These are directives derived from a special form of lexing where the + /// source input is scanned for the preprocessor directives that might have an + /// effect on the dependencies for a compilation unit. + /// + /// Enables a client to cache the directives for a file and provide them + /// across multiple compiler invocations. + /// FIXME: Allow returning an error. + std::function>( + FileEntryRef)> + DependencyDirectivesForFile; + /// Set up preprocessor for RunAnalysis action. bool SetUpStaticAnalyzer = false; diff --git a/clang/lib/Frontend/FrontendActions.cpp b/clang/lib/Frontend/FrontendActions.cpp index 58fcb2217b05..642b14d8b09d 100644 --- a/clang/lib/Frontend/FrontendActions.cpp +++ b/clang/lib/Frontend/FrontendActions.cpp @@ -69,10 +69,7 @@ void InitOnlyAction::ExecuteAction() { // Basically PreprocessOnlyAction::ExecuteAction. void ReadPCHAndPreprocessAction::ExecuteAction() { - CompilerInstance &CI = getCompilerInstance(); - AdjustCI(CI); - - Preprocessor &PP = CI.getPreprocessor(); + Preprocessor &PP = getCompilerInstance().getPreprocessor(); // Ignore unknown pragmas. PP.IgnorePragmas(); @@ -1193,8 +1190,6 @@ void PrintDependencyDirectivesSourceMinimizerAction::ExecuteAction() { void GetDependenciesByModuleNameAction::ExecuteAction() { CompilerInstance &CI = getCompilerInstance(); - AdjustCI(CI); - Preprocessor &PP = CI.getPreprocessor(); SourceManager &SM = PP.getSourceManager(); FileID MainFileID = SM.getMainFileID(); diff --git a/clang/lib/Lex/PPLexerChange.cpp b/clang/lib/Lex/PPLexerChange.cpp index a0cc2b516574..3b1b6df1dbae 100644 --- a/clang/lib/Lex/PPLexerChange.cpp +++ b/clang/lib/Lex/PPLexerChange.cpp @@ -93,10 +93,16 @@ bool Preprocessor::EnterSourceFile(FileID FID, ConstSearchDirIterator CurDir, } Lexer *TheLexer = new Lexer(FID, *InputFile, *this, IsFirstIncludeOfFile); - if (DependencyDirectivesForFile && FID != PredefinesFileID) - if (OptionalFileEntryRef File = SourceMgr.getFileEntryRefForID(FID)) - if (auto DepDirectives = DependencyDirectivesForFile(*File)) + if (getPreprocessorOpts().DependencyDirectivesForFile && + FID != PredefinesFileID) { + if (OptionalFileEntryRef File = SourceMgr.getFileEntryRefForID(FID)) { + if (std::optional> + DepDirectives = + getPreprocessorOpts().DependencyDirectivesForFile(*File)) { TheLexer->DepDirectives = *DepDirectives; + } + } + } EnterSourceFileWithLexer(TheLexer, CurDir); return false; diff --git a/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp b/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp index 492b8f1e2b38..32850f5eea92 100644 --- a/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp +++ b/clang/lib/Tooling/DependencyScanning/DependencyScanningWorker.cpp @@ -363,22 +363,17 @@ public: PrebuiltModuleVFSMap, ScanInstance.getDiagnostics())) return false; - auto AdjustCI = [&](CompilerInstance &CI) { - // Set up the dependency scanning file system callback if requested. - if (DepFS) { - auto GetDependencyDirectives = [LocalDepFS = DepFS](FileEntryRef File) - -> std::optional> { - if (llvm::ErrorOr Entry = - LocalDepFS->getOrCreateFileSystemEntry(File.getName())) - if (LocalDepFS->ensureDirectiveTokensArePopulated(*Entry)) - return Entry->getDirectiveTokens(); - return std::nullopt; - }; - - CI.getPreprocessor().setDependencyDirectivesFn( - std::move(GetDependencyDirectives)); - } - }; + // Use the dependency scanning optimized file system if requested to do so. + if (DepFS) + ScanInstance.getPreprocessorOpts().DependencyDirectivesForFile = + [LocalDepFS = DepFS](FileEntryRef File) + -> std::optional> { + if (llvm::ErrorOr Entry = + LocalDepFS->getOrCreateFileSystemEntry(File.getName())) + if (LocalDepFS->ensureDirectiveTokensArePopulated(*Entry)) + return Entry->getDirectiveTokens(); + return std::nullopt; + }; // Create the dependency collector that will collect the produced // dependencies. @@ -430,11 +425,9 @@ public: std::unique_ptr Action; if (ModuleName) - Action = std::make_unique( - *ModuleName, std::move(AdjustCI)); + Action = std::make_unique(*ModuleName); else - Action = - std::make_unique(std::move(AdjustCI)); + Action = std::make_unique(); if (ScanInstance.getDiagnostics().hasErrorOccurred()) return false; diff --git a/clang/test/ClangScanDeps/modules-extension.c b/clang/test/ClangScanDeps/modules-minimize-extension.c similarity index 100% rename from clang/test/ClangScanDeps/modules-extension.c rename to clang/test/ClangScanDeps/modules-minimize-extension.c diff --git a/clang/test/ClangScanDeps/modules-minimize-module.c b/clang/test/ClangScanDeps/modules-minimize-module.c new file mode 100644 index 000000000000..fb58c61bc509 --- /dev/null +++ b/clang/test/ClangScanDeps/modules-minimize-module.c @@ -0,0 +1,24 @@ +// RUN: rm -rf %t +// RUN: split-file %s %t + +// This test checks that source files of modules undergo dependency directives +// scan. If a.h would not, the scan would fail when lexing `#error`. + +//--- module.modulemap +module A { header "a.h" } + +//--- a.h +#error blah + +//--- tu.c +#include "a.h" + +//--- cdb.json.in +[{ + "directory": "DIR", + "file": "DIR/tu.c", + "command": "clang -c DIR/tu.c -fmodules -fmodules-cache-path=DIR/cache" +}] + +// RUN: sed -e "s|DIR|%/t|g" %t/cdb.json.in > %t/cdb.json +// RUN: clang-scan-deps -compilation-database %t/cdb.json -format experimental-full > %t/deps.json diff --git a/clang/unittests/Lex/PPDependencyDirectivesTest.cpp b/clang/unittests/Lex/PPDependencyDirectivesTest.cpp index 0c396720ece6..6ff87f720a55 100644 --- a/clang/unittests/Lex/PPDependencyDirectivesTest.cpp +++ b/clang/unittests/Lex/PPDependencyDirectivesTest.cpp @@ -117,6 +117,11 @@ TEST_F(PPDependencyDirectivesTest, MacroGuard) { }; auto PPOpts = std::make_shared(); + PPOpts->DependencyDirectivesForFile = [&](FileEntryRef File) + -> std::optional> { + return getDependencyDirectives(File); + }; + TrivialModuleLoader ModLoader; HeaderSearch HeaderInfo(std::make_shared(), SourceMgr, Diags, LangOpts, Target.get()); @@ -125,12 +130,6 @@ TEST_F(PPDependencyDirectivesTest, MacroGuard) { /*OwnsHeaderSearch =*/false); PP.Initialize(*Target); - PP.setDependencyDirectivesFn( - [&](FileEntryRef File) - -> std::optional> { - return getDependencyDirectives(File); - }); - SmallVector IncludedFiles; PP.addPPCallbacks(std::make_unique(PP, IncludedFiles)); PP.EnterMainSourceFile(); -- GitLab From a8ec1eb843c9c999d1c55b7b34cabebeacc533d7 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 9 Apr 2024 21:30:50 +0100 Subject: [PATCH 329/695] [VPlan] Dont assign slots to VPValues with an underlying value. This makes sure the numbering for VPValues without underlying values is consecutive. --- llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 ++ .../PowerPC/vplan-force-tail-with-evl.ll | 36 +++++++++---------- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp index 8ebd75da3465..3e1069d82dda 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -1374,6 +1374,8 @@ VPInterleavedAccessInfo::VPInterleavedAccessInfo(VPlan &Plan, } void VPSlotTracker::assignSlot(const VPValue *V) { + if (V->getUnderlyingValue()) + return; assert(!Slots.contains(V) && "VPValue already has a slot!"); Slots[V] = NextSlot++; } diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll index 5d1a471c5d16..bd52c2a8f064 100644 --- a/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll +++ b/llvm/test/Transforms/LoopVectorize/PowerPC/vplan-force-tail-with-evl.ll @@ -18,37 +18,37 @@ define void @foo(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) { ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<%3> = CANONICAL-INDUCTION ir<0>, vp<%16> +; CHECK-NEXT: EMIT vp<%3> = CANONICAL-INDUCTION ir<0>, vp<%8> ; CHECK-NEXT: WIDEN-INDUCTION %iv = phi 0, %iv.next, ir<1> -; CHECK-NEXT: EMIT vp<%5> = icmp ule ir<%iv>, vp<%2> +; CHECK-NEXT: EMIT vp<%4> = icmp ule ir<%iv>, vp<%2> ; CHECK-NEXT: Successor(s): pred.store ; CHECK-EMPTY: ; CHECK-NEXT: pred.store: { ; CHECK-NEXT: pred.store.entry: -; CHECK-NEXT: BRANCH-ON-MASK vp<%5> +; CHECK-NEXT: BRANCH-ON-MASK vp<%4> ; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue ; CHECK-EMPTY: ; CHECK-NEXT: pred.store.if: -; CHECK-NEXT: vp<%6> = SCALAR-STEPS vp<%3>, ir<1> -; CHECK-NEXT: REPLICATE ir<%arrayidx> = getelementptr inbounds ir<%b>, vp<%6> +; CHECK-NEXT: vp<%5> = SCALAR-STEPS vp<%3>, ir<1> +; CHECK-NEXT: REPLICATE ir<%arrayidx> = getelementptr inbounds ir<%b>, vp<%5> ; CHECK-NEXT: REPLICATE ir<%0> = load ir<%arrayidx> -; CHECK-NEXT: REPLICATE ir<%arrayidx2> = getelementptr inbounds ir<%c>, vp<%6> +; CHECK-NEXT: REPLICATE ir<%arrayidx2> = getelementptr inbounds ir<%c>, vp<%5> ; CHECK-NEXT: REPLICATE ir<%1> = load ir<%arrayidx2> -; CHECK-NEXT: REPLICATE ir<%arrayidx4> = getelementptr inbounds ir<%a>, vp<%6> +; CHECK-NEXT: REPLICATE ir<%arrayidx4> = getelementptr inbounds ir<%a>, vp<%5> ; CHECK-NEXT: REPLICATE ir<%add> = add nsw ir<%1>, ir<%0> ; CHECK-NEXT: REPLICATE store ir<%add>, ir<%arrayidx4> ; CHECK-NEXT: Successor(s): pred.store.continue ; CHECK-EMPTY: ; CHECK-NEXT: pred.store.continue: -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%14> = ir<%0> -; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%15> = ir<%1> +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%6> = ir<%0> +; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%7> = ir<%1> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; CHECK-NEXT: Successor(s): for.body.2 ; CHECK-EMPTY: ; CHECK-NEXT: for.body.2: -; CHECK-NEXT: EMIT vp<%16> = add vp<%3>, vp<%0> -; CHECK-NEXT: EMIT branch-on-count vp<%16>, vp<%1> +; CHECK-NEXT: EMIT vp<%8> = add vp<%3>, vp<%0> +; CHECK-NEXT: EMIT branch-on-count vp<%8>, vp<%1> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; @@ -83,17 +83,17 @@ define void @safe_dep(ptr %p) { ; CHECK-EMPTY: ; CHECK-NEXT: vector loop: { ; CHECK-NEXT: vector.body: -; CHECK-NEXT: EMIT vp<%2> = CANONICAL-INDUCTION ir<0>, vp<%10> +; CHECK-NEXT: EMIT vp<%2> = CANONICAL-INDUCTION ir<0>, vp<%6> ; CHECK-NEXT: vp<%3> = SCALAR-STEPS vp<%2>, ir<1> ; CHECK-NEXT: CLONE ir<%a1> = getelementptr ir<%p>, vp<%3> -; CHECK-NEXT: vp<%5> = vector-pointer ir<%a1> -; CHECK-NEXT: WIDEN ir<%v> = load vp<%5> +; CHECK-NEXT: vp<%4> = vector-pointer ir<%a1> +; CHECK-NEXT: WIDEN ir<%v> = load vp<%4> ; CHECK-NEXT: CLONE ir<%offset> = add vp<%3>, ir<100> ; CHECK-NEXT: CLONE ir<%a2> = getelementptr ir<%p>, ir<%offset> -; CHECK-NEXT: vp<%9> = vector-pointer ir<%a2> -; CHECK-NEXT: WIDEN store vp<%9>, ir<%v> -; CHECK-NEXT: EMIT vp<%10> = add nuw vp<%2>, vp<%0> -; CHECK-NEXT: EMIT branch-on-count vp<%10>, vp<%1> +; CHECK-NEXT: vp<%5> = vector-pointer ir<%a2> +; CHECK-NEXT: WIDEN store vp<%5>, ir<%v> +; CHECK-NEXT: EMIT vp<%6> = add nuw vp<%2>, vp<%0> +; CHECK-NEXT: EMIT branch-on-count vp<%6>, vp<%1> ; CHECK-NEXT: No successors ; CHECK-NEXT: } ; -- GitLab From e953c862e9b082e16ac3306c36dc8fdfc5f03ee3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Tue, 9 Apr 2024 13:32:21 -0700 Subject: [PATCH 330/695] [flang][cuda] Add UNIFIED data attribute (#88171) Latest version of the specification introduced the `UNIFIED` attribute for data. https://docs.nvidia.com/hpc-sdk/compilers/cuda-fortran-prog-guide/#cfref-var-attr-unified-data This patch adds the attribute to parsing, semantic and lowering. The matching rules for dummy/actual arguments is not part of this patch. --- flang/include/flang/Common/Fortran.h | 3 ++- flang/include/flang/Optimizer/Support/Utils.h | 3 +++ flang/include/flang/Parser/parse-tree.h | 2 +- flang/lib/Parser/Fortran-parsers.cpp | 6 ++++-- flang/lib/Semantics/check-declarations.cpp | 7 +++++++ flang/test/Lower/CUDA/cuda-data-attribute.cuf | 11 +++++++++++ flang/test/Semantics/cuf03.cuf | 17 +++++++++++++++++ 7 files changed, 45 insertions(+), 4 deletions(-) diff --git a/flang/include/flang/Common/Fortran.h b/flang/include/flang/Common/Fortran.h index ac1973fdff66..2a53452a2774 100644 --- a/flang/include/flang/Common/Fortran.h +++ b/flang/include/flang/Common/Fortran.h @@ -85,7 +85,8 @@ static constexpr int maxRank{15}; ENUM_CLASS(CUDASubprogramAttrs, Host, Device, HostDevice, Global, Grid_Global) // CUDA data attributes; mutually exclusive -ENUM_CLASS(CUDADataAttr, Constant, Device, Managed, Pinned, Shared, Texture) +ENUM_CLASS( + CUDADataAttr, Constant, Device, Managed, Pinned, Shared, Texture, Unified) // OpenACC device types ENUM_CLASS( diff --git a/flang/include/flang/Optimizer/Support/Utils.h b/flang/include/flang/Optimizer/Support/Utils.h index 7a8a34c25ce9..2b4fa50e0e42 100644 --- a/flang/include/flang/Optimizer/Support/Utils.h +++ b/flang/include/flang/Optimizer/Support/Utils.h @@ -158,6 +158,9 @@ getCUDADataAttribute(mlir::MLIRContext *mlirContext, case Fortran::common::CUDADataAttr::Texture: // Obsolete attribute return {}; + case Fortran::common::CUDADataAttr::Unified: + attr = fir::CUDADataAttribute::Unified; + break; } return fir::CUDADataAttributeAttr::get(mlirContext, attr); } diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index be59e3912a36..574a95cf22af 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -991,7 +991,7 @@ struct ComponentArraySpec { // access-spec | ALLOCATABLE | // CODIMENSION lbracket coarray-spec rbracket | // CONTIGUOUS | DIMENSION ( component-array-spec ) | POINTER | -// (CUDA) CONSTANT | DEVICE | MANAGED | PINNED | SHARED | TEXTURE +// (CUDA) CONSTANT | DEVICE | MANAGED | PINNED | SHARED | TEXTURE | UNIFIED EMPTY_CLASS(Allocatable); EMPTY_CLASS(Pointer); EMPTY_CLASS(Contiguous); diff --git a/flang/lib/Parser/Fortran-parsers.cpp b/flang/lib/Parser/Fortran-parsers.cpp index 5186d3baa54c..2bdb8e38db95 100644 --- a/flang/lib/Parser/Fortran-parsers.cpp +++ b/flang/lib/Parser/Fortran-parsers.cpp @@ -703,13 +703,15 @@ TYPE_PARSER(construct(accessSpec) || extension( construct(Parser{}))) -// CUDA-data-attr -> CONSTANT | DEVICE | MANAGED | PINNED | SHARED | TEXTURE +// CUDA-data-attr -> +// CONSTANT | DEVICE | MANAGED | PINNED | SHARED | TEXTURE | UNIFIED TYPE_PARSER("CONSTANT" >> pure(common::CUDADataAttr::Constant) || "DEVICE" >> pure(common::CUDADataAttr::Device) || "MANAGED" >> pure(common::CUDADataAttr::Managed) || "PINNED" >> pure(common::CUDADataAttr::Pinned) || "SHARED" >> pure(common::CUDADataAttr::Shared) || - "TEXTURE" >> pure(common::CUDADataAttr::Texture)) + "TEXTURE" >> pure(common::CUDADataAttr::Texture) || + "UNIFIED" >> pure(common::CUDADataAttr::Unified)) // R804 object-name -> name constexpr auto objectName{name}; diff --git a/flang/lib/Semantics/check-declarations.cpp b/flang/lib/Semantics/check-declarations.cpp index b2de37759a06..824f1b6053ca 100644 --- a/flang/lib/Semantics/check-declarations.cpp +++ b/flang/lib/Semantics/check-declarations.cpp @@ -988,6 +988,13 @@ void CheckHelper::CheckObjectEntity( symbol.name()); } break; + case common::CUDADataAttr::Unified: + if ((!subpDetails || inDeviceSubprogram) && !isComponent) { + messages_.Say( + "Object '%s' with ATTRIBUTES(UNIFIED) must be declared in a host subprogram"_err_en_US, + symbol.name()); + } + break; case common::CUDADataAttr::Texture: messages_.Say( "ATTRIBUTES(TEXTURE) is obsolete and no longer supported"_err_en_US); diff --git a/flang/test/Lower/CUDA/cuda-data-attribute.cuf b/flang/test/Lower/CUDA/cuda-data-attribute.cuf index 94aa62352c2a..937c981bddd3 100644 --- a/flang/test/Lower/CUDA/cuda-data-attribute.cuf +++ b/flang/test/Lower/CUDA/cuda-data-attribute.cuf @@ -19,16 +19,20 @@ subroutine local_var_attrs real, device :: rd real, allocatable, managed :: rm real, allocatable, pinned :: rp + real, unified :: ru end subroutine ! CHECK-LABEL: func.func @_QMcuda_varPlocal_var_attrs() ! CHECK: %{{.*}}:2 = hlfir.declare %{{.*}} {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFlocal_var_attrsErd"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %{{.*}}:2 = hlfir.declare %{{.*}} {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFlocal_var_attrsErm"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) ! CHECK: %{{.*}}:2 = hlfir.declare %{{.*}} {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFlocal_var_attrsErp"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %{{.*}}:2 = hlfir.declare %{{.*}} {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFlocal_var_attrsEru"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! FIR: %{{.*}} = fir.declare %{{.*}} {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFlocal_var_attrsErd"} : (!fir.ref) -> !fir.ref ! FIR: %{{.*}} = fir.declare %{{.*}} {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFlocal_var_attrsErm"} : (!fir.ref>>) -> !fir.ref>> ! FIR: %{{.*}} = fir.declare %{{.*}} {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFlocal_var_attrsErp"} : (!fir.ref>>) -> !fir.ref>> +! FIR: %{{.*}} = fir.declare %{{.*}} {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFlocal_var_attrsEru"} : (!fir.ref) -> !fir.ref subroutine dummy_arg_device(dd) real, device :: dd @@ -51,4 +55,11 @@ end subroutine ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref>> {fir.bindc_name = "dp", fir.cuda_attr = #fir.cuda}) { ! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {cuda_attr = #fir.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QMcuda_varFdummy_arg_pinnedEdp"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +subroutine dummy_arg_unified(du) + real, unified :: du +end subroutine +! CHECK-LABEL: func.func @_QMcuda_varPdummy_arg_unified( +! CHECK-SAME: %[[ARG0:.*]]: !fir.ref {fir.bindc_name = "du", fir.cuda_attr = #fir.cuda}) +! CHECK: %{{.*}}:2 = hlfir.declare %[[ARG0]] {cuda_attr = #fir.cuda, uniq_name = "_QMcuda_varFdummy_arg_unifiedEdu"} : (!fir.ref) -> (!fir.ref, !fir.ref) + end module diff --git a/flang/test/Semantics/cuf03.cuf b/flang/test/Semantics/cuf03.cuf index 7384a104831d..574add9faaad 100644 --- a/flang/test/Semantics/cuf03.cuf +++ b/flang/test/Semantics/cuf03.cuf @@ -1,6 +1,12 @@ ! RUN: %python %S/test_errors.py %s %flang_fc1 ! Exercise CUDA data attribute checks module m + type :: t1 + integer :: i + end type + type :: t2 + real, unified :: r(10) ! ok + end type real, constant :: mc ! ok real, constant :: mci = 1. ! ok !ERROR: Object 'mcl' with ATTRIBUTES(CONSTANT) may not be allocatable, pointer, or target @@ -48,6 +54,9 @@ module m real, texture, pointer :: mt !ERROR: 'bigint' has intrinsic type 'INTEGER(16)' that is not available on the device integer(16), device :: bigint + !ERROR: Object 'um' with ATTRIBUTES(UNIFIED) must be declared in a host subprogram + real, unified :: um + contains attributes(device) subroutine devsubr(n,da) integer, intent(in) :: n @@ -57,6 +66,8 @@ module m !WARNING: Pointer 'dp' may not be associated in a device subprogram real, device, pointer :: dp real, constant :: rc ! ok + !ERROR: Object 'u' with ATTRIBUTES(UNIFIED) must be declared in a host subprogram + real, unified :: u end subroutine subroutine host() @@ -70,4 +81,10 @@ module m rs = 1 ! ok end subroutine + subroutine host2() + real, unified :: ru ! ok + type(t1), unified :: tu ! ok + type(t2) :: t ! ok + end subroutine + end module -- GitLab From 5b58eb68ed36717971970f35a1192213e3eb4ec5 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Thu, 4 Apr 2024 21:07:34 -0500 Subject: [PATCH 331/695] [InstCombine] Add tests for folding `(icmp eq/ne (or disjoint x, C0), C1)`; NFC --- llvm/test/Transforms/InstCombine/icmp-or.ll | 50 +++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-or.ll b/llvm/test/Transforms/InstCombine/icmp-or.ll index 922845c1e7e2..ce6ebfc19655 100644 --- a/llvm/test/Transforms/InstCombine/icmp-or.ll +++ b/llvm/test/Transforms/InstCombine/icmp-or.ll @@ -951,3 +951,53 @@ define i1 @icmp_or_xor_with_sub_3_6(i64 %x1, i64 %y1, i64 %x2, i64 %y2, i64 %x3, %cmp = icmp eq i64 %or1, 0 ret i1 %cmp } + + +define i1 @or_disjoint_with_constants(i8 %x) { +; CHECK-LABEL: @or_disjoint_with_constants( +; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -2 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 18 +; CHECK-NEXT: ret i1 [[CMP]] +; + %or = or disjoint i8 %x, 1 + %cmp = icmp eq i8 %or, 19 + ret i1 %cmp +} + + +define i1 @or_disjoint_with_constants2(i8 %x) { +; CHECK-LABEL: @or_disjoint_with_constants2( +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], 5 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[OR]], 71 +; CHECK-NEXT: call void @use(i8 [[OR]]) +; CHECK-NEXT: ret i1 [[CMP]] +; + %or = or disjoint i8 %x, 5 + %cmp = icmp ne i8 %or, 71 + call void @use(i8 %or) + ret i1 %cmp +} + + +define i1 @or_disjoint_with_constants_fail_missing_const1(i8 %x, i8 %y) { +; CHECK-LABEL: @or_disjoint_with_constants_fail_missing_const1( +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 19 +; CHECK-NEXT: ret i1 [[CMP]] +; + %or = or disjoint i8 %x, %y + %cmp = icmp eq i8 %or, 19 + ret i1 %cmp +} + +define i1 @or_disjoint_with_constants_fail_missing_const2(i8 %x, i8 %y) { +; CHECK-LABEL: @or_disjoint_with_constants_fail_missing_const2( +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], 19 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], [[Y:%.*]] +; CHECK-NEXT: ret i1 [[CMP]] +; + %or = or disjoint i8 %x, 19 + %cmp = icmp eq i8 %or, %y + ret i1 %cmp +} + -- GitLab From 71ef04d7cd6c0d6133ab11ca4cfceefe506a1acb Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Thu, 4 Apr 2024 21:07:37 -0500 Subject: [PATCH 332/695] [InstCombine] fold `(icmp eq/ne (or disjoint x, C0), C1)` -> `(icmp eq/ne x, C0^C1)` Proof: https://alive2.llvm.org/ce/z/m3xoo_ Closes #87734 --- .../Transforms/InstCombine/InstCombineCompares.cpp | 11 +++++++++++ llvm/test/Transforms/InstCombine/icmp-or.ll | 7 +++---- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 53aa84d53f30..9ff1e3aa5502 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -23,6 +23,7 @@ #include "llvm/Analysis/VectorUtils.h" #include "llvm/IR/ConstantRange.h" #include "llvm/IR/DataLayout.h" +#include "llvm/IR/InstrTypes.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/PatternMatch.h" #include "llvm/Support/KnownBits.h" @@ -2049,6 +2050,16 @@ Instruction *InstCombinerImpl::foldICmpOrConstant(ICmpInst &Cmp, } Value *OrOp0 = Or->getOperand(0), *OrOp1 = Or->getOperand(1); + + // (icmp eq/ne (or disjoint x, C0), C1) + // -> (icmp eq/ne x, C0^C1) + if (Cmp.isEquality() && match(OrOp1, m_ImmConstant()) && + cast(Or)->isDisjoint()) { + Value *NewC = + Builder.CreateXor(OrOp1, ConstantInt::get(OrOp1->getType(), C)); + return new ICmpInst(Pred, OrOp0, NewC); + } + const APInt *MaskC; if (match(OrOp1, m_APInt(MaskC)) && Cmp.isEquality()) { if (*MaskC == C && (C + 1).isPowerOf2()) { diff --git a/llvm/test/Transforms/InstCombine/icmp-or.ll b/llvm/test/Transforms/InstCombine/icmp-or.ll index ce6ebfc19655..1f9db5e5db9a 100644 --- a/llvm/test/Transforms/InstCombine/icmp-or.ll +++ b/llvm/test/Transforms/InstCombine/icmp-or.ll @@ -955,8 +955,7 @@ define i1 @icmp_or_xor_with_sub_3_6(i64 %x1, i64 %y1, i64 %x2, i64 %y2, i64 %x3, define i1 @or_disjoint_with_constants(i8 %x) { ; CHECK-LABEL: @or_disjoint_with_constants( -; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[X:%.*]], -2 -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1]], 18 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP1:%.*]], 18 ; CHECK-NEXT: ret i1 [[CMP]] ; %or = or disjoint i8 %x, 1 @@ -967,8 +966,8 @@ define i1 @or_disjoint_with_constants(i8 %x) { define i1 @or_disjoint_with_constants2(i8 %x) { ; CHECK-LABEL: @or_disjoint_with_constants2( -; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[X:%.*]], 5 -; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[OR]], 71 +; CHECK-NEXT: [[OR:%.*]] = or disjoint i8 [[TMP1:%.*]], 5 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[TMP1]], 66 ; CHECK-NEXT: call void @use(i8 [[OR]]) ; CHECK-NEXT: ret i1 [[CMP]] ; -- GitLab From 470aefb240dee7d791875284b9917bf641ca971a Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Tue, 9 Apr 2024 15:50:15 -0500 Subject: [PATCH 333/695] [Offload][NFC] Remove `omp_` prefix from offloading entries (#88071) Summary: These entires are generic for offloading with the new driver now. Having the `omp` prefix was a historical artifact and is confusing when used for CUDA. This patch just renames them for now, future patches will rework the binary format to make it more common. --- clang/test/CodeGenCUDA/offloading-entries.cu | 82 +++++++++---------- .../OpenMP/declare_target_link_codegen.cpp | 10 +-- .../declare_target_visibility_codegen.cpp | 8 +- .../OpenMP/target_codegen_registration.cpp | 48 +++++------ clang/test/OpenMP/target_indirect_codegen.cpp | 8 +- llvm/lib/Frontend/Offloading/Utility.cpp | 6 +- .../Frontend/OpenMPIRBuilderTest.cpp | 10 +-- .../omptarget-declare-target-llvm-host.mlir | 60 +++++++------- 8 files changed, 116 insertions(+), 116 deletions(-) diff --git a/clang/test/CodeGenCUDA/offloading-entries.cu b/clang/test/CodeGenCUDA/offloading-entries.cu index 4f5cf65ecd0b..ec21f018607f 100644 --- a/clang/test/CodeGenCUDA/offloading-entries.cu +++ b/clang/test/CodeGenCUDA/offloading-entries.cu @@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --global-value-regex ".omp_offloading.entry.*" +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --global-value-regex ".offloading.entry.*" // RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu -fgpu-rdc \ // RUN: --offload-new-driver -emit-llvm -o - -x cuda %s | FileCheck \ // RUN: --check-prefix=CUDA %s @@ -15,49 +15,49 @@ #include "Inputs/cuda.h" //. -// CUDA: @.omp_offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" -// CUDA: @.omp_offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z18__device_stub__foov, ptr @.omp_offloading.entry_name, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries", align 1 -// CUDA: @.omp_offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" -// CUDA: @.omp_offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z21__device_stub__kernelv, ptr @.omp_offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries", align 1 -// CUDA: @.omp_offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" -// CUDA: @.omp_offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.omp_offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "cuda_offloading_entries", align 1 -// CUDA: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" -// CUDA: @.omp_offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.omp_offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "cuda_offloading_entries", align 1 -// CUDA: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" -// CUDA: @.omp_offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.omp_offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "cuda_offloading_entries", align 1 +// CUDA: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" +// CUDA: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z18__device_stub__foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries", align 1 +// CUDA: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" +// CUDA: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z21__device_stub__kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries", align 1 +// CUDA: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" +// CUDA: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "cuda_offloading_entries", align 1 +// CUDA: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" +// CUDA: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "cuda_offloading_entries", align 1 +// CUDA: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" +// CUDA: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "cuda_offloading_entries", align 1 //. -// HIP: @.omp_offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" -// HIP: @.omp_offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @.omp_offloading.entry_name, i64 0, i32 0, i32 0 }, section "hip_offloading_entries", align 1 -// HIP: @.omp_offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" -// HIP: @.omp_offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z6kernelv, ptr @.omp_offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "hip_offloading_entries", align 1 -// HIP: @.omp_offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" -// HIP: @.omp_offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.omp_offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "hip_offloading_entries", align 1 -// HIP: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" -// HIP: @.omp_offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.omp_offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "hip_offloading_entries", align 1 -// HIP: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" -// HIP: @.omp_offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.omp_offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "hip_offloading_entries", align 1 +// HIP: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" +// HIP: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "hip_offloading_entries", align 1 +// HIP: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" +// HIP: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z6kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "hip_offloading_entries", align 1 +// HIP: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" +// HIP: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "hip_offloading_entries", align 1 +// HIP: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" +// HIP: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "hip_offloading_entries", align 1 +// HIP: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" +// HIP: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "hip_offloading_entries", align 1 //. -// CUDA-COFF: @.omp_offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" -// CUDA-COFF: @.omp_offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z18__device_stub__foov, ptr @.omp_offloading.entry_name, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1 -// CUDA-COFF: @.omp_offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" -// CUDA-COFF: @.omp_offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z21__device_stub__kernelv, ptr @.omp_offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1 -// CUDA-COFF: @.omp_offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" -// CUDA-COFF: @.omp_offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.omp_offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1 -// CUDA-COFF: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" -// CUDA-COFF: @.omp_offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.omp_offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "cuda_offloading_entries$OE", align 1 -// CUDA-COFF: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" -// CUDA-COFF: @.omp_offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.omp_offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "cuda_offloading_entries$OE", align 1 +// CUDA-COFF: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" +// CUDA-COFF: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z18__device_stub__foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1 +// CUDA-COFF: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" +// CUDA-COFF: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z21__device_stub__kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1 +// CUDA-COFF: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" +// CUDA-COFF: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "cuda_offloading_entries$OE", align 1 +// CUDA-COFF: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" +// CUDA-COFF: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "cuda_offloading_entries$OE", align 1 +// CUDA-COFF: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" +// CUDA-COFF: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "cuda_offloading_entries$OE", align 1 //. -// HIP-COFF: @.omp_offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" -// HIP-COFF: @.omp_offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @.omp_offloading.entry_name, i64 0, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1 -// HIP-COFF: @.omp_offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" -// HIP-COFF: @.omp_offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z6kernelv, ptr @.omp_offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1 -// HIP-COFF: @.omp_offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" -// HIP-COFF: @.omp_offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.omp_offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1 -// HIP-COFF: @.omp_offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" -// HIP-COFF: @.omp_offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.omp_offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "hip_offloading_entries$OE", align 1 -// HIP-COFF: @.omp_offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" -// HIP-COFF: @.omp_offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.omp_offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "hip_offloading_entries$OE", align 1 +// HIP-COFF: @.offloading.entry_name = internal unnamed_addr constant [8 x i8] c"_Z3foov\00" +// HIP-COFF: @.offloading.entry._Z3foov = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @.offloading.entry_name, i64 0, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1 +// HIP-COFF: @.offloading.entry_name.1 = internal unnamed_addr constant [11 x i8] c"_Z6kernelv\00" +// HIP-COFF: @.offloading.entry._Z6kernelv = weak constant %struct.__tgt_offload_entry { ptr @_Z6kernelv, ptr @.offloading.entry_name.1, i64 0, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1 +// HIP-COFF: @.offloading.entry_name.2 = internal unnamed_addr constant [4 x i8] c"var\00" +// HIP-COFF: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @var, ptr @.offloading.entry_name.2, i64 4, i32 0, i32 0 }, section "hip_offloading_entries$OE", align 1 +// HIP-COFF: @.offloading.entry_name.3 = internal unnamed_addr constant [5 x i8] c"surf\00" +// HIP-COFF: @.offloading.entry.surf = weak constant %struct.__tgt_offload_entry { ptr @surf, ptr @.offloading.entry_name.3, i64 4, i32 2, i32 1 }, section "hip_offloading_entries$OE", align 1 +// HIP-COFF: @.offloading.entry_name.4 = internal unnamed_addr constant [4 x i8] c"tex\00" +// HIP-COFF: @.offloading.entry.tex = weak constant %struct.__tgt_offload_entry { ptr @tex, ptr @.offloading.entry_name.4, i64 4, i32 3, i32 1 }, section "hip_offloading_entries$OE", align 1 //. // CUDA-LABEL: @_Z18__device_stub__foov( // CUDA-NEXT: entry: diff --git a/clang/test/OpenMP/declare_target_link_codegen.cpp b/clang/test/OpenMP/declare_target_link_codegen.cpp index 2372b2738b5b..dd1ac813efaa 100644 --- a/clang/test/OpenMP/declare_target_link_codegen.cpp +++ b/clang/test/OpenMP/declare_target_link_codegen.cpp @@ -26,12 +26,12 @@ // DEVICE: @c_decl_tgt_ref_ptr = weak global ptr null // HOST: [[SIZES:@.+]] = private unnamed_addr constant [3 x i64] [i64 4, i64 4, i64 4] // HOST: [[MAPTYPES:@.+]] = private unnamed_addr constant [3 x i64] [i64 35, i64 531, i64 531] -// HOST: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [{{[0-9]+}} x i8] c"c_decl_tgt_ref_ptr\00" -// HOST: @.omp_offloading.entry.c_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @c_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 -// HOST-COFF: @.omp_offloading.entry.{{.*}} = weak constant %struct.__tgt_offload_entry { ptr @.{{.*}}, ptr @.{{.*}}, i64 0, i32 0, i32 0 }, section "omp_offloading_entries$OE", align 1 +// HOST: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [{{[0-9]+}} x i8] c"c_decl_tgt_ref_ptr\00" +// HOST: @.offloading.entry.c_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @c_decl_tgt_ref_ptr, ptr @.offloading.entry_name, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 +// HOST-COFF: @.offloading.entry.{{.*}} = weak constant %struct.__tgt_offload_entry { ptr @.{{.*}}, ptr @.{{.*}}, i64 0, i32 0, i32 0 }, section "omp_offloading_entries$OE", align 1 // DEVICE-NOT: internal unnamed_addr constant [{{[0-9]+}} x i8] c"c_{{.*}}_decl_tgt_ref_ptr\00" -// HOST: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [{{[0-9]+}} x i8] c"_{{.*}}d_{{.*}}_decl_tgt_ref_ptr\00" -// HOST: @.omp_offloading.entry.[[D_PTR]] = weak constant %struct.__tgt_offload_entry { ptr @[[D_PTR]], ptr @.omp_offloading.entry_name{{.*}} +// HOST: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [{{[0-9]+}} x i8] c"_{{.*}}d_{{.*}}_decl_tgt_ref_ptr\00" +// HOST: @.offloading.entry.[[D_PTR]] = weak constant %struct.__tgt_offload_entry { ptr @[[D_PTR]], ptr @.offloading.entry_name{{.*}} extern int c; #pragma omp declare target link(c) diff --git a/clang/test/OpenMP/declare_target_visibility_codegen.cpp b/clang/test/OpenMP/declare_target_visibility_codegen.cpp index 6518bac50623..6643a9bb4f0c 100644 --- a/clang/test/OpenMP/declare_target_visibility_codegen.cpp +++ b/clang/test/OpenMP/declare_target_visibility_codegen.cpp @@ -8,10 +8,10 @@ public: // HOST: @[[X:.+]] = internal global i32 0, align 4 // HOST: @y = hidden global i32 0 // HOST: @z = global i32 0 -// HOST-NOT: @.omp_offloading.entry.c -// HOST-NOT: @.omp_offloading.entry.x -// HOST-NOT: @.omp_offloading.entry.y -// HOST: @.omp_offloading.entry.z +// HOST-NOT: @.offloading.entry.c +// HOST-NOT: @.offloading.entry.x +// HOST-NOT: @.offloading.entry.y +// HOST: @.offloading.entry.z C() : x(0) {} int x; diff --git a/clang/test/OpenMP/target_codegen_registration.cpp b/clang/test/OpenMP/target_codegen_registration.cpp index 5313da30c4ec..4927147d080f 100644 --- a/clang/test/OpenMP/target_codegen_registration.cpp +++ b/clang/test/OpenMP/target_codegen_registration.cpp @@ -119,54 +119,54 @@ // CHECK-NTARGET-NOT: private unnamed_addr constant [1 x i // CHECK-DAG: [[NAMEPTR1:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME1:__omp_offloading_[0-9a-f]+_[0-9a-f]+__Z.+_l[0-9]+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME1]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR1]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME1]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR1]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR2:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME2:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME2]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR2]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME2]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR2]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR3:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME3:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME3]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR3]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME3]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR3]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR4:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME4:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME4]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR4]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME4]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR4]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR5:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME5:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME5]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR5]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME5]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR5]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR6:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME6:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME6]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR6]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME6]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR6]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR7:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME7:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME7]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR7]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME7]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR7]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR8:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME8:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME8]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR8]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME8]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR8]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR9:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME9:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME9]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR9]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME9]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR9]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR10:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME10:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME10]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR10]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME10]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR10]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR11:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME11:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME11]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR11]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME11]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR11]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: [[NAMEPTR12:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME12:.+]]\00" -// CHECK-DAG: @.omp_offloading.entry.[[NAME12]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR12]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// CHECK-DAG: @.offloading.entry.[[NAME12]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR12]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR1:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME1:__omp_offloading_[0-9a-f]+_[0-9a-f]+__Z.+_l[0-9]+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME1]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR1]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME1]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR1]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR2:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME2:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME2]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR2]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME2]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR2]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR3:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME3:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME3]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR3]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME3]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR3]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR4:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME4:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME4]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR4]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME4]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR4]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR5:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME5:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME5]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR5]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME5]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR5]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR6:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME6:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME6]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR6]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME6]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR6]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR7:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME7:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME7]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR7]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME7]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR7]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR8:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME8:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME8]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR8]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME8]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR8]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR9:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME9:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME9]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR9]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME9]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR9]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR10:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME10:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME10]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR10]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME10]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR10]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR11:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME11:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME11]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR11]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME11]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR11]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // TCHECK-DAG: [[NAMEPTR12:@.+]] = internal unnamed_addr constant [{{.*}} x i8] c"[[NAME12:.+]]\00" -// TCHECK-DAG: @.omp_offloading.entry.[[NAME12]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR12]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// TCHECK-DAG: @.offloading.entry.[[NAME12]] = weak{{.*}} constant [[ENTTY]] { ptr @{{.*}}, ptr [[NAMEPTR12]], i[[SZ]] 0, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // We have 4 initializers, one for the 500 priority, another one for 501, or more for the default priority, and the last one for the offloading registration function. // CHECK: @llvm.global_ctors = appending global [3 x { i32, ptr, ptr }] [ diff --git a/clang/test/OpenMP/target_indirect_codegen.cpp b/clang/test/OpenMP/target_indirect_codegen.cpp index 0ecdb7279e20..bc0aa4541703 100644 --- a/clang/test/OpenMP/target_indirect_codegen.cpp +++ b/clang/test/OpenMP/target_indirect_codegen.cpp @@ -11,13 +11,13 @@ //. // HOST: @[[VAR:.+]] = global i8 0, align 1 // HOST: @[[FOO_ENTRY_NAME:.+]] = internal unnamed_addr constant [{{[0-9]+}} x i8] c"[[FOO_NAME:__omp_offloading_[0-9a-z]+_[0-9a-z]+_foo_l[0-9]+]]\00" -// HOST: @.omp_offloading.entry.[[FOO_NAME]] = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @[[FOO_ENTRY_NAME]], i64 8, i32 8, i32 0 }, section "omp_offloading_entries", align 1 +// HOST: @.offloading.entry.[[FOO_NAME]] = weak constant %struct.__tgt_offload_entry { ptr @_Z3foov, ptr @[[FOO_ENTRY_NAME]], i64 8, i32 8, i32 0 }, section "omp_offloading_entries", align 1 // HOST: @[[BAZ_ENTRY_NAME:.+]] = internal unnamed_addr constant [{{[0-9]+}} x i8] c"[[BAZ_NAME:__omp_offloading_[0-9a-z]+_[0-9a-z]+_baz_l[0-9]+]]\00" -// HOST: @.omp_offloading.entry.[[BAZ_NAME]] = weak constant %struct.__tgt_offload_entry { ptr @_Z3bazv, ptr @[[BAZ_ENTRY_NAME]], i64 8, i32 8, i32 0 }, section "omp_offloading_entries", align 1 +// HOST: @.offloading.entry.[[BAZ_NAME]] = weak constant %struct.__tgt_offload_entry { ptr @_Z3bazv, ptr @[[BAZ_ENTRY_NAME]], i64 8, i32 8, i32 0 }, section "omp_offloading_entries", align 1 // HOST: @[[VAR_ENTRY_NAME:.+]] = internal unnamed_addr constant [4 x i8] c"var\00" -// HOST: @.omp_offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @[[VAR]], ptr @[[VAR_ENTRY_NAME]], i64 1, i32 0, i32 0 }, section "omp_offloading_entries", align 1 +// HOST: @.offloading.entry.var = weak constant %struct.__tgt_offload_entry { ptr @[[VAR]], ptr @[[VAR_ENTRY_NAME]], i64 1, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // HOST: @[[BAR_ENTRY_NAME:.+]] = internal unnamed_addr constant [{{[0-9]+}} x i8] c"[[BAR_NAME:__omp_offloading_[0-9a-z]+_[0-9a-z]+_bar_l[0-9]+]]\00" -// HOST: @.omp_offloading.entry.[[BAR_NAME]] = weak constant %struct.__tgt_offload_entry { ptr @_ZL3barv, ptr @[[BAR_ENTRY_NAME]], i64 8, i32 8, i32 0 }, section "omp_offloading_entries", align 1 +// HOST: @.offloading.entry.[[BAR_NAME]] = weak constant %struct.__tgt_offload_entry { ptr @_ZL3barv, ptr @[[BAR_ENTRY_NAME]], i64 8, i32 8, i32 0 }, section "omp_offloading_entries", align 1 //. // DEVICE: @[[FOO_NAME:__omp_offloading_[0-9a-z]+_[0-9a-z]+_foo_l[0-9]+]] = protected addrspace(1) constant ptr @_Z3foov // DEVICE: @[[BAZ_NAME:__omp_offloading_[0-9a-z]+_[0-9a-z]+_baz_l[0-9]+]] = protected addrspace(1) constant ptr @_Z3bazv diff --git a/llvm/lib/Frontend/Offloading/Utility.cpp b/llvm/lib/Frontend/Offloading/Utility.cpp index a0d9dfa9e2b5..919b9462e32d 100644 --- a/llvm/lib/Frontend/Offloading/Utility.cpp +++ b/llvm/lib/Frontend/Offloading/Utility.cpp @@ -40,8 +40,8 @@ offloading::getOffloadingEntryInitializer(Module &M, Constant *Addr, Constant *AddrName = ConstantDataArray::getString(M.getContext(), Name); - StringRef Prefix = Triple.isNVPTX() ? "$omp_offloading$entry_name" - : ".omp_offloading.entry_name"; + StringRef Prefix = + Triple.isNVPTX() ? "$offloading$entry_name" : ".offloading.entry_name"; // Create the constant string used to look up the symbol in the device. auto *Str = @@ -70,7 +70,7 @@ void offloading::emitOffloadingEntry(Module &M, Constant *Addr, StringRef Name, getOffloadingEntryInitializer(M, Addr, Name, Size, Flags, Data); StringRef Prefix = - Triple.isNVPTX() ? "$omp_offloading$entry$" : ".omp_offloading.entry."; + Triple.isNVPTX() ? "$offloading$entry$" : ".offloading.entry."; auto *Entry = new GlobalVariable( M, getEntryTy(M), /*isConstant=*/true, GlobalValue::WeakAnyLinkage, EntryInitializer, diff --git a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp index 5c415cadcd68..db1c4a8951ad 100644 --- a/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp +++ b/llvm/unittests/Frontend/OpenMPIRBuilderTest.cpp @@ -6975,16 +6975,16 @@ TEST_F(OpenMPIRBuilderTest, registerTargetGlobalVariable) { // Clauses for data_int_0 with To + Any clauses for the host std::vector OffloadEntries; - OffloadEntries.push_back(M->getNamedGlobal(".omp_offloading.entry_name")); + OffloadEntries.push_back(M->getNamedGlobal(".offloading.entry_name")); OffloadEntries.push_back( - M->getNamedGlobal(".omp_offloading.entry.test_data_int_0")); + M->getNamedGlobal(".offloading.entry.test_data_int_0")); // Clauses for data_int_1 with Link + Any clauses for the host OffloadEntries.push_back( M->getNamedGlobal("test_data_int_1_decl_tgt_ref_ptr")); - OffloadEntries.push_back(M->getNamedGlobal(".omp_offloading.entry_name.1")); - OffloadEntries.push_back(M->getNamedGlobal( - ".omp_offloading.entry.test_data_int_1_decl_tgt_ref_ptr")); + OffloadEntries.push_back(M->getNamedGlobal(".offloading.entry_name.1")); + OffloadEntries.push_back( + M->getNamedGlobal(".offloading.entry.test_data_int_1_decl_tgt_ref_ptr")); for (unsigned I = 0; I < OffloadEntries.size(); ++I) EXPECT_NE(OffloadEntries[I], nullptr); diff --git a/mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir b/mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir index 2baa20010d05..244c0315c2db 100644 --- a/mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-declare-target-llvm-host.mlir @@ -6,15 +6,15 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe // CHECK-DAG: @_QMtest_0Earray_1d = global [3 x i32] [i32 1, i32 2, i32 3] // CHECK-DAG: @_QMtest_0Earray_1d_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Earray_1d - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Earray_1d_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Earray_1d_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Earray_1d_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Earray_1d_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Earray_1d_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Earray_1d_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Earray_1d_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Earray_1d(dense<[1, 2, 3]> : tensor<3xi32>) {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : !llvm.array<3 x i32> // CHECK-DAG: @_QMtest_0Earray_2d = global [2 x [2 x i32]] {{.*}} // CHECK-DAG: @_QMtest_0Earray_2d_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Earray_2d - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Earray_2d_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Earray_2d_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Earray_2d_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Earray_2d_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Earray_2d_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Earray_2d_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Earray_2d_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Earray_2d() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : !llvm.array<2 x array<2 x i32>> { %0 = llvm.mlir.undef : !llvm.array<2 x array<2 x i32>> @@ -33,8 +33,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe // CHECK-DAG: @_QMtest_0Edata_extended_link_1 = global float 2.000000e+00 // CHECK-DAG: @_QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Edata_extended_link_1 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [48 x i8] c"_QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [48 x i8] c"_QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_extended_link_1_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_extended_link_1() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : f32 { %0 = llvm.mlir.constant(2.000000e+00 : f32) : f32 @@ -43,8 +43,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe // CHECK-DAG: @_QMtest_0Edata_extended_link_2 = global float 3.000000e+00 // CHECK-DAG: @_QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Edata_extended_link_2 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [48 x i8] c"_QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [48 x i8] c"_QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_extended_link_2_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_extended_link_2() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : f32 { %0 = llvm.mlir.constant(3.000000e+00 : f32) : f32 @@ -52,8 +52,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_extended_to_1 = global float 2.000000e+00 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [29 x i8] c"_QMtest_0Edata_extended_to_1\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_extended_to_1 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_to_1, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [29 x i8] c"_QMtest_0Edata_extended_to_1\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_extended_to_1 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_to_1, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_extended_to_1", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_extended_to_1() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : f32 { %0 = llvm.mlir.constant(2.000000e+00 : f32) : f32 @@ -61,8 +61,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_extended_enter_1 = global float 2.000000e+00 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [32 x i8] c"_QMtest_0Edata_extended_enter_1\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_extended_enter_1 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_enter_1, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [32 x i8] c"_QMtest_0Edata_extended_enter_1\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_extended_enter_1 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_enter_1, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_extended_enter_1", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_extended_enter_1() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : f32 { %0 = llvm.mlir.constant(2.000000e+00 : f32) : f32 @@ -70,8 +70,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_extended_to_2 = global float 3.000000e+00 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [29 x i8] c"_QMtest_0Edata_extended_to_2\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_extended_to_2 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_to_2, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [29 x i8] c"_QMtest_0Edata_extended_to_2\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_extended_to_2 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_to_2, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_extended_to_2", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_extended_to_2() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : f32 { %0 = llvm.mlir.constant(3.000000e+00 : f32) : f32 @@ -79,8 +79,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_extended_enter_2 = global float 3.000000e+00 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [32 x i8] c"_QMtest_0Edata_extended_enter_2\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_extended_enter_2 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_enter_2, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [32 x i8] c"_QMtest_0Edata_extended_enter_2\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_extended_enter_2 = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_extended_enter_2, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_extended_enter_2", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_extended_enter_2() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : f32 { %0 = llvm.mlir.constant(3.000000e+00 : f32) : f32 @@ -89,8 +89,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe // CHECK-DAG: @_QMtest_0Edata_int = global i32 1 // CHECK-DAG: @_QMtest_0Edata_int_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Edata_int - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Edata_int_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_int_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Edata_int_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_int_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_int_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_int() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : i32 { %0 = llvm.mlir.constant(10 : i32) : i32 @@ -98,8 +98,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_int_clauseless_to = global i32 1 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [33 x i8] c"_QMtest_0Edata_int_clauseless_to\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_int_clauseless_to = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_clauseless_to, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [33 x i8] c"_QMtest_0Edata_int_clauseless_to\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_int_clauseless_to = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_clauseless_to, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_int_clauseless_to", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_int_clauseless_to() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : i32 { %0 = llvm.mlir.constant(1 : i32) : i32 @@ -107,8 +107,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_int_clauseless_enter = global i32 1 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Edata_int_clauseless_enter\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_int_clauseless_enter = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_clauseless_enter, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [36 x i8] c"_QMtest_0Edata_int_clauseless_enter\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_int_clauseless_enter = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_clauseless_enter, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_int_clauseless_enter", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_int_clauseless_enter() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : i32 { %0 = llvm.mlir.constant(1 : i32) : i32 @@ -116,8 +116,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_int_to = global i32 5 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [22 x i8] c"_QMtest_0Edata_int_to\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_int_to = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_to, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [22 x i8] c"_QMtest_0Edata_int_to\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_int_to = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_to, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_int_to", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_int_to() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : i32 { %0 = llvm.mlir.constant(5 : i32) : i32 @@ -125,8 +125,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe } // CHECK-DAG: @_QMtest_0Edata_int_enter = global i32 5 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [25 x i8] c"_QMtest_0Edata_int_enter\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Edata_int_enter = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_enter, ptr @.omp_offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [25 x i8] c"_QMtest_0Edata_int_enter\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Edata_int_enter = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Edata_int_enter, ptr @.offloading.entry_name{{.*}}, i64 4, i32 0, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Edata_int_enter", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Edata_int_enter() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : i32 { %0 = llvm.mlir.constant(5 : i32) : i32 @@ -135,8 +135,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe // CHECK-DAG: @_QMtest_0Ept1 = global { ptr, i64, i32, i8, i8, i8, i8 } { ptr null, i64 ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64), i32 20180515, i8 0, i8 9, i8 1, i8 0 } // CHECK-DAG: @_QMtest_0Ept1_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Ept1 - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [31 x i8] c"_QMtest_0Ept1_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Ept1_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Ept1_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [31 x i8] c"_QMtest_0Ept1_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Ept1_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Ept1_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Ept1_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Ept1() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8)> { %0 = llvm.mlir.zero : !llvm.ptr @@ -166,8 +166,8 @@ module attributes {llvm.target_triple = "x86_64-unknown-linux-gnu", omp.is_targe // CHECK-DAG: @_QMtest_0Ept2_tar = global i32 5 // CHECK-DAG: @_QMtest_0Ept2_tar_decl_tgt_ref_ptr = weak global ptr @_QMtest_0Ept2_tar - // CHECK-DAG: @.omp_offloading.entry_name{{.*}} = internal unnamed_addr constant [35 x i8] c"_QMtest_0Ept2_tar_decl_tgt_ref_ptr\00" - // CHECK-DAG: @.omp_offloading.entry._QMtest_0Ept2_tar_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Ept2_tar_decl_tgt_ref_ptr, ptr @.omp_offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 + // CHECK-DAG: @.offloading.entry_name{{.*}} = internal unnamed_addr constant [35 x i8] c"_QMtest_0Ept2_tar_decl_tgt_ref_ptr\00" + // CHECK-DAG: @.offloading.entry._QMtest_0Ept2_tar_decl_tgt_ref_ptr = weak constant %struct.__tgt_offload_entry { ptr @_QMtest_0Ept2_tar_decl_tgt_ref_ptr, ptr @.offloading.entry_name{{.*}}, i64 8, i32 1, i32 0 }, section "omp_offloading_entries", align 1 // CHECK-DAG: !{{.*}} = !{i32 {{.*}}, !"_QMtest_0Ept2_tar_decl_tgt_ref_ptr", i32 {{.*}}, i32 {{.*}}} llvm.mlir.global external @_QMtest_0Ept2_tar() {addr_space = 0 : i32, omp.declare_target = #omp.declaretarget} : i32 { %0 = llvm.mlir.constant(5 : i32) : i32 -- GitLab From b79db396599f42d106b930d61e20c9d5146a6866 Mon Sep 17 00:00:00 2001 From: srcarroll <50210727+srcarroll@users.noreply.github.com> Date: Tue, 9 Apr 2024 15:52:40 -0500 Subject: [PATCH 334/695] [mlir][linalg] Support `ParamType` in `vector_sizes` option of `VectorizeOp` transform (#87557) --- .../Linalg/TransformOps/LinalgTransformOps.td | 21 +--- .../TransformOps/LinalgTransformOps.cpp | 82 ++++++++++++ .../Dialect/Linalg/transform-ops-invalid.mlir | 21 ++++ mlir/test/Dialect/Linalg/transform-ops.mlir | 11 +- mlir/test/Dialect/Linalg/vectorization.mlir | 118 ++++++++++++++++++ .../dialects/transform_structured_ext.py | 14 ++- 6 files changed, 249 insertions(+), 18 deletions(-) diff --git a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td index c260fe3f7a46..8edaa7db6cef 100644 --- a/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td +++ b/mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td @@ -2138,25 +2138,16 @@ def VectorizeOp : Op:$vector_sizes, + Variadic:$vector_sizes, + DefaultValuedOptionalAttr: + $static_vector_sizes, OptionalAttr:$vectorize_nd_extract, DefaultValuedOptionalAttr: - $scalable_sizes, - DefaultValuedOptionalAttr: - $static_vector_sizes); + $scalable_sizes); let results = (outs); - let assemblyFormat = [{ - $target oilist( - `vector_sizes` custom($vector_sizes, - $static_vector_sizes, - type($vector_sizes), - $scalable_sizes) | - `vectorize_nd_extract` $vectorize_nd_extract - ) - attr-dict - `:` type($target) - }]; + + let hasCustomAssemblyFormat = 1; let hasVerifier = 1; let extraClassDeclaration = [{ diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp index 88819cd96435..7e7cf1d02446 100644 --- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp +++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp @@ -3122,6 +3122,81 @@ transform::VectorizeChildrenAndApplyPatternsOp::applyToOne( //===----------------------------------------------------------------------===// // VectorizeOp //===----------------------------------------------------------------------===// + +static const StringLiteral kVectorSizesKeyword = "vector_sizes"; + +ParseResult transform::VectorizeOp::parse(OpAsmParser &parser, + OperationState &result) { + OpAsmParser::UnresolvedOperand target; + SmallVector dynamicSizes; + DenseI64ArrayAttr staticSizes; + SmallVector operandTypes; + llvm::SMLoc operandLoc; + DenseBoolArrayAttr scalableVals; + + if (parser.parseOperand(target) || parser.getCurrentLocation(&operandLoc)) + return ParseResult::failure(); + + if (succeeded(parser.parseOptionalKeyword(kVectorSizesKeyword))) { + if (failed(parseDynamicIndexList(parser, dynamicSizes, staticSizes, + scalableVals))) + return ParseResult::failure(); + } + + if (succeeded(parser.parseOptionalKeyword( + getVectorizeNdExtractAttrName(result.name)))) + result.addAttribute(getVectorizeNdExtractAttrName(result.name), + parser.getBuilder().getUnitAttr()); + + if (parser.parseOptionalAttrDict(result.attributes) || + parser.parseColonTypeList(operandTypes)) + return ParseResult::failure(); + + if (operandTypes.size() != dynamicSizes.size() + 1) { + return parser.emitError(operandLoc) + << "expected " << dynamicSizes.size() + 1 << " operand type(s)"; + } + if (parser.resolveOperand(target, operandTypes.front(), result.operands) || + parser.resolveOperands(dynamicSizes, ArrayRef(operandTypes).drop_front(), + operandLoc, result.operands)) { + return failure(); + } + + if (scalableVals) + result.addAttribute(getScalableSizesAttrName(result.name), scalableVals); + if (staticSizes) + result.addAttribute(getStaticVectorSizesAttrName(result.name), staticSizes); + + return success(); +} + +void transform::VectorizeOp::print(OpAsmPrinter &p) { + p << ' ' << getTarget() << ' '; + if (!getMixedVectorSizes().empty()) { + p << kVectorSizesKeyword << ' '; + printDynamicIndexList(p, getOperation(), getVectorSizes(), + getStaticVectorSizesAttr(), + /*valueTypes=*/{}, getScalableSizesAttr(), + OpAsmParser::Delimiter::Square); + } + + if (getVectorizeNdExtract()) + p << getVectorizeNdExtractAttrName() << ' '; + + p.printOptionalAttrDict( + (*this)->getAttrs(), + /*elidedAttrs=*/{ + getScalableSizesAttrName(getOperation()->getName()), + getStaticVectorSizesAttrName(getOperation()->getName())}); + p << " : "; + p << getTarget().getType(); + if (!getVectorSizes().empty()) { + p << ", "; + llvm::interleaveComma(getVectorSizes(), p, + [&](Value operand) { p << operand.getType(); }); + } +} + DiagnosedSilenceableFailure transform::VectorizeOp::apply( transform::TransformRewriter &rewriter, mlir::transform::TransformResults &transformResults, @@ -3136,6 +3211,13 @@ DiagnosedSilenceableFailure transform::VectorizeOp::apply( auto attr = sz.get(); vectorSizes.push_back(cast(attr).getInt()); continue; + } else if (sz.is() && isa(sz.get().getType())) { + ArrayRef params = state.getParams(sz.get()); + if (params.size() != 1) + return emitSilenceableFailure(getLoc()) << "expected a single param"; + vectorSizes.push_back( + cast(params.front()).getValue().getSExtValue()); + continue; } auto szPayloads = state.getPayloadOps(sz.get()); diff --git a/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir b/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir index 5143be393066..e7d9815ab222 100644 --- a/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir +++ b/mlir/test/Dialect/Linalg/transform-ops-invalid.mlir @@ -71,3 +71,24 @@ transform.sequence failures(propagate) { : (!transform.any_op) -> !transform.op<"linalg.generic"> } + +// ----- + +transform.sequence failures(propagate) { +^bb0(%arg0: !transform.any_op): + %0 = transform.param.constant 2 : i64 -> !transform.param + // expected-error@below {{custom op 'transform.structured.vectorize' expected 2 operand type(s)}} + transform.structured.vectorize %arg0 vector_sizes [%0, 2] : !transform.any_op, !transform.param, !transform.param + +} + +// ----- + +transform.sequence failures(propagate) { +^bb0(%arg0: !transform.any_op): + %0 = transform.param.constant 2 : i64 -> !transform.param + // expected-error@below {{expected ']' in dynamic index list}} + // expected-error@below {{custom op 'transform.structured.vectorize' expected SSA value or integer}} + transform.structured.vectorize %arg0 vector_sizes [%0 : !transform.param, 2] : !transform.any_op, !transform.param + +} diff --git a/mlir/test/Dialect/Linalg/transform-ops.mlir b/mlir/test/Dialect/Linalg/transform-ops.mlir index 6b276e69a595..8f6274fd22c2 100644 --- a/mlir/test/Dialect/Linalg/transform-ops.mlir +++ b/mlir/test/Dialect/Linalg/transform-ops.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s | mlir-opt | FileCheck %s +// RUN: mlir-opt %s --split-input-file | mlir-opt | FileCheck %s transform.sequence failures(propagate) { ^bb1(%arg0: !transform.any_op): @@ -57,3 +57,12 @@ transform.sequence failures(propagate) { %1:2 = transform.structured.fuse_into_containing_op %arg2 into %loop : (!transform.any_op, !transform.any_op) -> (!transform.any_op, !transform.any_op) } + +// ----- + +transform.sequence failures(propagate) { +^bb0(%arg0: !transform.any_op): + // CHECK: transform.structured.vectorize %arg0 : !transform.any_op + transform.structured.vectorize %arg0 vector_sizes [] : !transform.any_op + +} diff --git a/mlir/test/Dialect/Linalg/vectorization.mlir b/mlir/test/Dialect/Linalg/vectorization.mlir index 2d01d5730401..fd7d3b4767eb 100644 --- a/mlir/test/Dialect/Linalg/vectorization.mlir +++ b/mlir/test/Dialect/Linalg/vectorization.mlir @@ -36,6 +36,81 @@ module attributes {transform.with_named_sequence} { // ----- +func.func @vectorize_dynamic_identity_with_constant(%arg0: tensor, + %arg1: tensor, + %arg2: tensor) -> tensor { + %c4 = arith.constant 4 : index + %0 = linalg.generic { indexing_maps = [affine_map<(d0) -> (d0)>, + affine_map<(d0) -> (d0)>, + affine_map<(d0) -> (d0)>], + iterator_types = ["parallel"] } + ins(%arg0, %arg1 : tensor, tensor) + outs(%arg2 : tensor) { + ^bb(%in0: f32, %in1: f32, %out: f32) : + %0 = arith.addf %in0, %in1 : f32 + linalg.yield %0 : f32 + } -> tensor + return %0 : tensor +} + +// CHECK-LABEL: @vectorize_dynamic_identity_with_constant +// CHECK: %[[VAL_3:.*]] = arith.constant 0 : index +// CHECK: %[[VAL_4:.*]] = tensor.dim %{{.*}}, %[[VAL_3]] : tensor +// CHECK: %[[VAL_7:.*]] = vector.create_mask %[[VAL_4]] : vector<4xi1> +// CHECK: %[[VAL_8:.*]] = vector.mask %[[VAL_7]] { vector.transfer_read %{{.*}} {in_bounds = [true]} : tensor, vector<4xf32> } : vector<4xi1> -> vector<4xf32> +// CHECK: %[[VAL_10:.*]] = vector.mask %[[VAL_7]] { vector.transfer_read %{{.*}} {in_bounds = [true]} : tensor, vector<4xf32> } : vector<4xi1> -> vector<4xf32> +// CHECK: %[[VAL_12:.*]] = vector.mask %[[VAL_7]] { vector.transfer_read %{{.*}} {in_bounds = [true]} : tensor, vector<4xf32> } : vector<4xi1> -> vector<4xf32> +// CHECK: %[[VAL_13:.*]] = arith.addf %[[VAL_8]], %[[VAL_10]] : vector<4xf32> +// CHECK: %[[VAL_14:.*]] = vector.mask %[[VAL_7]] { vector.transfer_write %{{.*}} {in_bounds = [true]} : vector<4xf32>, tensor } : vector<4xi1> -> tensor + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %size = transform.structured.match ops{["arith.constant"]} in %arg1 : (!transform.any_op) -> !transform.any_op + transform.structured.vectorize %0 vector_sizes [%size] : !transform.any_op, !transform.any_op + transform.yield + } +} + +// ----- + +func.func @vectorize_dynamic_identity_with_param(%arg0: tensor, + %arg1: tensor, + %arg2: tensor) -> tensor { + %0 = linalg.generic { indexing_maps = [affine_map<(d0) -> (d0)>, + affine_map<(d0) -> (d0)>, + affine_map<(d0) -> (d0)>], + iterator_types = ["parallel"] } + ins(%arg0, %arg1 : tensor, tensor) + outs(%arg2 : tensor) { + ^bb(%in0: f32, %in1: f32, %out: f32) : + %0 = arith.addf %in0, %in1 : f32 + linalg.yield %0 : f32 + } -> tensor + return %0 : tensor +} + +// CHECK-LABEL: @vectorize_dynamic_identity_with_param +// CHECK: %[[VAL_3:.*]] = arith.constant 0 : index +// CHECK: %[[VAL_4:.*]] = tensor.dim %{{.*}}, %[[VAL_3]] : tensor +// CHECK: %[[VAL_7:.*]] = vector.create_mask %[[VAL_4]] : vector<4xi1> +// CHECK: %[[VAL_8:.*]] = vector.mask %[[VAL_7]] { vector.transfer_read %{{.*}} {in_bounds = [true]} : tensor, vector<4xf32> } : vector<4xi1> -> vector<4xf32> +// CHECK: %[[VAL_10:.*]] = vector.mask %[[VAL_7]] { vector.transfer_read %{{.*}} {in_bounds = [true]} : tensor, vector<4xf32> } : vector<4xi1> -> vector<4xf32> +// CHECK: %[[VAL_12:.*]] = vector.mask %[[VAL_7]] { vector.transfer_read %{{.*}} {in_bounds = [true]} : tensor, vector<4xf32> } : vector<4xi1> -> vector<4xf32> +// CHECK: %[[VAL_13:.*]] = arith.addf %[[VAL_8]], %[[VAL_10]] : vector<4xf32> +// CHECK: %[[VAL_14:.*]] = vector.mask %[[VAL_7]] { vector.transfer_write %{{.*}} {in_bounds = [true]} : vector<4xf32>, tensor } : vector<4xi1> -> tensor + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %vector_size = transform.param.constant 4 : i64 -> !transform.param + transform.structured.vectorize %0 vector_sizes [%vector_size] : !transform.any_op, !transform.param + transform.yield + } +} + +// ----- + func.func @vectorize_dynamic_1d_broadcast(%arg0: tensor, %arg1: tensor, %arg2: tensor) -> tensor { @@ -231,6 +306,49 @@ module attributes {transform.with_named_sequence} { // ----- +func.func @vectorize_dynamic_transpose_reduction_with_params(%arg0: tensor, + %arg1: tensor) -> tensor { + %0 = linalg.generic { indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d1, d2)>, + affine_map<(d0, d1, d2) -> (d2, d1)>], + iterator_types = ["reduction", "parallel", "parallel"] } + ins(%arg0 : tensor) + outs(%arg1 : tensor) { + ^bb(%in: f32, %out: f32) : + %0 = arith.addf %in, %out : f32 + linalg.yield %0 : f32 + } -> tensor + return %0 : tensor +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["linalg.generic"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %vector_size_0 = transform.param.constant 4 : i64 -> !transform.param + %vector_size_2 = transform.param.constant 16 : i64 -> !transform.param + transform.structured.vectorize %0 vector_sizes + [%vector_size_0, 8, %vector_size_2] : !transform.any_op, !transform.param, !transform.param + transform.yield + } +} + +// CHECK-LABEL: @vectorize_dynamic_transpose_reduction_with_params( +// CHECK-SAME: %[[VAL_0:.*]]: tensor, +// CHECK-SAME: %[[VAL_1:.*]]: tensor) -> tensor { +// CHECK: %[[VAL_2:.*]] = arith.constant 0 : index +// CHECK: %[[VAL_3:.*]] = tensor.dim %[[VAL_0]], %[[VAL_2]] : tensor +// CHECK: %[[VAL_4:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_5:.*]] = tensor.dim %[[VAL_0]], %[[VAL_4]] : tensor +// CHECK: %[[VAL_6:.*]] = arith.constant 2 : index +// CHECK: %[[VAL_7:.*]] = tensor.dim %[[VAL_0]], %[[VAL_6]] : tensor +// CHECK: %[[VAL_10:.*]] = vector.create_mask %[[VAL_3]], %[[VAL_5]], %[[VAL_7]] : vector<4x8x16xi1> +// CHECK: %[[VAL_11:.*]] = vector.mask %[[VAL_10]] { vector.transfer_read %[[VAL_0]]{{.*}} {in_bounds = [true, true, true]} : tensor, vector<4x8x16xf32> } : vector<4x8x16xi1> -> vector<4x8x16xf32> +// CHECK: %[[VAL_13:.*]] = vector.create_mask %[[VAL_7]], %[[VAL_5]] : vector<16x8xi1> +// CHECK: %[[VAL_14:.*]] = vector.mask %[[VAL_13]] { vector.transfer_read %[[VAL_1]]{{.*}} {in_bounds = [true, true], permutation_map = #{{.*}}} : tensor, vector<8x16xf32> } : vector<16x8xi1> -> vector<8x16xf32> +// CHECK: %[[VAL_15:.*]] = vector.mask %[[VAL_10]] { vector.multi_reduction , %[[VAL_11]], %[[VAL_14]] [0] : vector<4x8x16xf32> to vector<8x16xf32> } : vector<4x8x16xi1> -> vector<8x16xf32> +// CHECK: %[[VAL_17:.*]] = vector.mask %[[VAL_13]] { vector.transfer_write %[[VAL_15]], %{{.*}} {in_bounds = [true, true], permutation_map = #{{.*}}} : vector<8x16xf32>, tensor } : vector<16x8xi1> -> tensor + +// ----- + func.func @vectorize_partial_dynamic_identity(%arg0: tensor<8x?xf32>, %arg1: tensor<8x?xf32>, %arg2: tensor<8x?xf32>) -> tensor<8x?xf32> { diff --git a/mlir/test/python/dialects/transform_structured_ext.py b/mlir/test/python/dialects/transform_structured_ext.py index c9b7802e1cc4..91ecd0fc38e1 100644 --- a/mlir/test/python/dialects/transform_structured_ext.py +++ b/mlir/test/python/dialects/transform_structured_ext.py @@ -210,7 +210,17 @@ def testVectorizeMixed(target): # CHECK: transform.sequence # CHECK: %[[V0:.*]] = transform.structured.match # CHECK: transform.structured.vectorize - # CHECK-SAME: vector_sizes [%[[V0]] : !transform.any_op, 4] + # CHECK-SAME: vector_sizes [%[[V0]], 4] + + +@run +@create_sequence +def testVectorizeEmpty(target): + structured.VectorizeOp(target, []) + # CHECK-LABEL: TEST: testVectorizeEmpty + # CHECK: transform.sequence + # CHECK: transform.structured.vectorize + # CHECK-NOT: vector_sizes @run @@ -223,7 +233,7 @@ def testVectorizeScalable(target): # CHECK: transform.sequence # CHECK-DAG: %[[V0:.*]] = transform.structured.match # CHECK-DAG: transform.structured.vectorize - # CHECK-SAME: vector_sizes [16, [%[[V0]] : !transform.any_op], [4], [8]] + # CHECK-SAME: vector_sizes [16, [%[[V0]]], [4], [8]] @run -- GitLab From b561fd37266753c645f073b7fabf7a75cf65d2ec Mon Sep 17 00:00:00 2001 From: Youngsuk Kim Date: Tue, 9 Apr 2024 17:06:41 -0400 Subject: [PATCH 335/695] [docs] Fix broken link in Benchmarking docs (#88117) Fixes #58813 --- llvm/docs/Benchmarking.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/docs/Benchmarking.rst b/llvm/docs/Benchmarking.rst index 0f88db745a68..7deb22144606 100644 --- a/llvm/docs/Benchmarking.rst +++ b/llvm/docs/Benchmarking.rst @@ -10,9 +10,9 @@ For benchmarking a patch we want to reduce all possible sources of noise as much as possible. How to do that is very OS dependent. Note that low noise is required, but not sufficient. It does not -exclude measurement bias. See -https://www.cis.upenn.edu/~cis501/papers/producing-wrong-data.pdf for -example. +exclude measurement bias. +See `"Producing Wrong Data Without Doing Anything Obviously Wrong!" by Mytkowicz, Diwan, Hauswith and Sweeney (ASPLOS 2009) `_ +for example. General ================================ -- GitLab From a332cfc986e431de11cdbf632b5769878e0d826b Mon Sep 17 00:00:00 2001 From: Teresa Johnson Date: Tue, 9 Apr 2024 14:12:32 -0700 Subject: [PATCH 336/695] [MemProf] Perform cloning for each allocation separately (#87112) Restructures the cloning slightly to perform all cloning for each allocation separately. The prior algorithm would sometimes miss cloning opportunities in cases where trimmed cold contexts partially overlapped with longer contexts for different allocations. Most of the change is isolated to the helpers that move edges to new or existing clones, which now support moving a subset of context ids. --- .../IPO/MemProfContextDisambiguation.cpp | 144 ++++++++--- .../overlapping-contexts.ll | 232 ++++++++++++++++++ 2 files changed, 344 insertions(+), 32 deletions(-) create mode 100644 llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll diff --git a/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp b/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp index 4e4a49997766..b9d84d583f49 100644 --- a/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp +++ b/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp @@ -526,25 +526,30 @@ private: /// Create a clone of Edge's callee and move Edge to that new callee node, /// performing the necessary context id and allocation type updates. /// If callee's caller edge iterator is supplied, it is updated when removing - /// the edge from that list. + /// the edge from that list. If ContextIdsToMove is non-empty, only that + /// subset of Edge's ids are moved to an edge to the new callee. ContextNode * moveEdgeToNewCalleeClone(const std::shared_ptr &Edge, - EdgeIter *CallerEdgeI = nullptr); + EdgeIter *CallerEdgeI = nullptr, + DenseSet ContextIdsToMove = {}); /// Change the callee of Edge to existing callee clone NewCallee, performing /// the necessary context id and allocation type updates. /// If callee's caller edge iterator is supplied, it is updated when removing - /// the edge from that list. + /// the edge from that list. If ContextIdsToMove is non-empty, only that + /// subset of Edge's ids are moved to an edge to the new callee. void moveEdgeToExistingCalleeClone(const std::shared_ptr &Edge, ContextNode *NewCallee, EdgeIter *CallerEdgeI = nullptr, - bool NewClone = false); + bool NewClone = false, + DenseSet ContextIdsToMove = {}); /// Recursively perform cloning on the graph for the given Node and its /// callers, in order to uniquely identify the allocation behavior of an - /// allocation given its context. - void identifyClones(ContextNode *Node, - DenseSet &Visited); + /// allocation given its context. The context ids of the allocation being + /// processed are given in AllocContextIds. + void identifyClones(ContextNode *Node, DenseSet &Visited, + const DenseSet &AllocContextIds); /// Map from each context ID to the AllocationType assigned to that context. std::map ContextIdToAllocationType; @@ -2358,7 +2363,8 @@ void CallsiteContextGraph::exportToDot( template typename CallsiteContextGraph::ContextNode * CallsiteContextGraph::moveEdgeToNewCalleeClone( - const std::shared_ptr &Edge, EdgeIter *CallerEdgeI) { + const std::shared_ptr &Edge, EdgeIter *CallerEdgeI, + DenseSet ContextIdsToMove) { ContextNode *Node = Edge->Callee; NodeOwner.push_back( std::make_unique(Node->IsAllocation, Node->Call)); @@ -2366,7 +2372,8 @@ CallsiteContextGraph::moveEdgeToNewCalleeClone( Node->addClone(Clone); assert(NodeToCallingFunc.count(Node)); NodeToCallingFunc[Clone] = NodeToCallingFunc[Node]; - moveEdgeToExistingCalleeClone(Edge, Clone, CallerEdgeI, /*NewClone=*/true); + moveEdgeToExistingCalleeClone(Edge, Clone, CallerEdgeI, /*NewClone=*/true, + ContextIdsToMove); return Clone; } @@ -2374,23 +2381,81 @@ template void CallsiteContextGraph:: moveEdgeToExistingCalleeClone(const std::shared_ptr &Edge, ContextNode *NewCallee, EdgeIter *CallerEdgeI, - bool NewClone) { + bool NewClone, + DenseSet ContextIdsToMove) { // NewCallee and Edge's current callee must be clones of the same original // node (Edge's current callee may be the original node too). assert(NewCallee->getOrigNode() == Edge->Callee->getOrigNode()); - auto &EdgeContextIds = Edge->getContextIds(); + ContextNode *OldCallee = Edge->Callee; - if (CallerEdgeI) - *CallerEdgeI = OldCallee->CallerEdges.erase(*CallerEdgeI); - else - OldCallee->eraseCallerEdge(Edge.get()); - Edge->Callee = NewCallee; - NewCallee->CallerEdges.push_back(Edge); - // Don't need to update Edge's context ids since we are simply reconnecting - // it. - set_subtract(OldCallee->ContextIds, EdgeContextIds); - NewCallee->ContextIds.insert(EdgeContextIds.begin(), EdgeContextIds.end()); - NewCallee->AllocTypes |= Edge->AllocTypes; + + // We might already have an edge to the new callee from earlier cloning for a + // different allocation. If one exists we will reuse it. + auto ExistingEdgeToNewCallee = NewCallee->findEdgeFromCaller(Edge->Caller); + + // Callers will pass an empty ContextIdsToMove set when they want to move the + // edge. Copy in Edge's ids for simplicity. + if (ContextIdsToMove.empty()) + ContextIdsToMove = Edge->getContextIds(); + + // If we are moving all of Edge's ids, then just move the whole Edge. + // Otherwise only move the specified subset, to a new edge if needed. + if (Edge->getContextIds().size() == ContextIdsToMove.size()) { + // Moving the whole Edge. + if (CallerEdgeI) + *CallerEdgeI = OldCallee->CallerEdges.erase(*CallerEdgeI); + else + OldCallee->eraseCallerEdge(Edge.get()); + if (ExistingEdgeToNewCallee) { + // Since we already have an edge to NewCallee, simply move the ids + // onto it, and remove the existing Edge. + ExistingEdgeToNewCallee->getContextIds().insert(ContextIdsToMove.begin(), + ContextIdsToMove.end()); + ExistingEdgeToNewCallee->AllocTypes |= Edge->AllocTypes; + assert(Edge->ContextIds == ContextIdsToMove); + Edge->ContextIds.clear(); + Edge->AllocTypes = (uint8_t)AllocationType::None; + Edge->Caller->eraseCalleeEdge(Edge.get()); + } else { + // Otherwise just reconnect Edge to NewCallee. + Edge->Callee = NewCallee; + NewCallee->CallerEdges.push_back(Edge); + // Don't need to update Edge's context ids since we are simply + // reconnecting it. + } + // In either case, need to update the alloc types on New Callee. + NewCallee->AllocTypes |= Edge->AllocTypes; + } else { + // Only moving a subset of Edge's ids. + if (CallerEdgeI) + ++CallerEdgeI; + // Compute the alloc type of the subset of ids being moved. + auto CallerEdgeAllocType = computeAllocType(ContextIdsToMove); + if (ExistingEdgeToNewCallee) { + // Since we already have an edge to NewCallee, simply move the ids + // onto it. + ExistingEdgeToNewCallee->getContextIds().insert(ContextIdsToMove.begin(), + ContextIdsToMove.end()); + ExistingEdgeToNewCallee->AllocTypes |= CallerEdgeAllocType; + } else { + // Otherwise, create a new edge to NewCallee for the ids being moved. + auto NewEdge = std::make_shared( + NewCallee, Edge->Caller, CallerEdgeAllocType, ContextIdsToMove); + Edge->Caller->CalleeEdges.push_back(NewEdge); + NewCallee->CallerEdges.push_back(NewEdge); + } + // In either case, need to update the alloc types on NewCallee, and remove + // those ids and update the alloc type on the original Edge. + NewCallee->AllocTypes |= CallerEdgeAllocType; + set_subtract(Edge->ContextIds, ContextIdsToMove); + Edge->AllocTypes = computeAllocType(Edge->ContextIds); + } + // Now perform some updates that are common to all cases: the NewCallee gets + // the moved ids added, and we need to remove those ids from OldCallee and + // update its alloc type (NewCallee alloc type updates handled above). + NewCallee->ContextIds.insert(ContextIdsToMove.begin(), + ContextIdsToMove.end()); + set_subtract(OldCallee->ContextIds, ContextIdsToMove); OldCallee->AllocTypes = computeAllocType(OldCallee->ContextIds); // OldCallee alloc type should be None iff its context id set is now empty. assert((OldCallee->AllocTypes == (uint8_t)AllocationType::None) == @@ -2402,7 +2467,7 @@ void CallsiteContextGraph:: // The context ids moving to the new callee are the subset of this edge's // context ids and the context ids on the caller edge being moved. DenseSet EdgeContextIdsToMove = - set_intersection(OldCalleeEdge->getContextIds(), EdgeContextIds); + set_intersection(OldCalleeEdge->getContextIds(), ContextIdsToMove); set_subtract(OldCalleeEdge->getContextIds(), EdgeContextIdsToMove); OldCalleeEdge->AllocTypes = computeAllocType(OldCalleeEdge->getContextIds()); @@ -2468,8 +2533,10 @@ void CallsiteContextGraph:: template void CallsiteContextGraph::identifyClones() { DenseSet Visited; - for (auto &Entry : AllocationCallToContextNodeMap) - identifyClones(Entry.second, Visited); + for (auto &Entry : AllocationCallToContextNodeMap) { + Visited.clear(); + identifyClones(Entry.second, Visited, Entry.second->ContextIds); + } Visited.clear(); for (auto &Entry : AllocationCallToContextNodeMap) recursivelyRemoveNoneTypeCalleeEdges(Entry.second, Visited); @@ -2487,7 +2554,8 @@ bool checkColdOrNotCold(uint8_t AllocType) { template void CallsiteContextGraph::identifyClones( - ContextNode *Node, DenseSet &Visited) { + ContextNode *Node, DenseSet &Visited, + const DenseSet &AllocContextIds) { if (VerifyNodes) checkNode(Node, /*CheckEdges=*/false); assert(!Node->CloneOf); @@ -2521,7 +2589,7 @@ void CallsiteContextGraph::identifyClones( } // Ignore any caller we previously visited via another edge. if (!Visited.count(Edge->Caller) && !Edge->Caller->CloneOf) { - identifyClones(Edge->Caller, Visited); + identifyClones(Edge->Caller, Visited, AllocContextIds); } } } @@ -2584,13 +2652,23 @@ void CallsiteContextGraph::identifyClones( if (hasSingleAllocType(Node->AllocTypes) || Node->CallerEdges.size() <= 1) break; + // Only need to process the ids along this edge pertaining to the given + // allocation. + auto CallerEdgeContextsForAlloc = + set_intersection(CallerEdge->getContextIds(), AllocContextIds); + if (CallerEdgeContextsForAlloc.empty()) { + ++EI; + continue; + } + auto CallerAllocTypeForAlloc = computeAllocType(CallerEdgeContextsForAlloc); + // Compute the node callee edge alloc types corresponding to the context ids // for this caller edge. std::vector CalleeEdgeAllocTypesForCallerEdge; CalleeEdgeAllocTypesForCallerEdge.reserve(Node->CalleeEdges.size()); for (auto &CalleeEdge : Node->CalleeEdges) CalleeEdgeAllocTypesForCallerEdge.push_back(intersectAllocTypes( - CalleeEdge->getContextIds(), CallerEdge->getContextIds())); + CalleeEdge->getContextIds(), CallerEdgeContextsForAlloc)); // Don't clone if doing so will not disambiguate any alloc types amongst // caller edges (including the callee edges that would be cloned). @@ -2605,7 +2683,7 @@ void CallsiteContextGraph::identifyClones( // disambiguated by splitting out different context ids. assert(CallerEdge->AllocTypes != (uint8_t)AllocationType::None); assert(Node->AllocTypes != (uint8_t)AllocationType::None); - if (allocTypeToUse(CallerEdge->AllocTypes) == + if (allocTypeToUse(CallerAllocTypeForAlloc) == allocTypeToUse(Node->AllocTypes) && allocTypesMatch( CalleeEdgeAllocTypesForCallerEdge, Node->CalleeEdges)) { @@ -2618,7 +2696,7 @@ void CallsiteContextGraph::identifyClones( ContextNode *Clone = nullptr; for (auto *CurClone : Node->Clones) { if (allocTypeToUse(CurClone->AllocTypes) != - allocTypeToUse(CallerEdge->AllocTypes)) + allocTypeToUse(CallerAllocTypeForAlloc)) continue; if (!allocTypesMatch( @@ -2630,9 +2708,11 @@ void CallsiteContextGraph::identifyClones( // The edge iterator is adjusted when we move the CallerEdge to the clone. if (Clone) - moveEdgeToExistingCalleeClone(CallerEdge, Clone, &EI); + moveEdgeToExistingCalleeClone(CallerEdge, Clone, &EI, /*NewClone=*/false, + CallerEdgeContextsForAlloc); else - Clone = moveEdgeToNewCalleeClone(CallerEdge, &EI); + Clone = + moveEdgeToNewCalleeClone(CallerEdge, &EI, CallerEdgeContextsForAlloc); assert(EI == Node->CallerEdges.end() || Node->AllocTypes != (uint8_t)AllocationType::None); diff --git a/llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll b/llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll new file mode 100644 index 000000000000..7fe9dc96921c --- /dev/null +++ b/llvm/test/Transforms/MemProfContextDisambiguation/overlapping-contexts.ll @@ -0,0 +1,232 @@ +;; This test ensures that the logic which assigns calls to stack nodes +;; correctly handles cloning of a callsite for a trimmed cold context +;; that partially overlaps with a longer context for a different allocation. + +;; The profile data and call stacks were all manually added, but the code +;; would be structured something like the following (fairly contrived to +;; result in the type of control flow needed to test): + +;; void A(bool b) { +;; if (b) +;; // cold: stack ids 10, 12, 13, 15 (trimmed ids 19, 20) +;; // not cold: stack ids 10, 12, 13, 14 (trimmed id 21) +;; new char[10]; // stack id 10 +;; else +;; // not cold: stack ids 11, 12, 13, 15, 16, 17 (trimmed id 22) +;; // cold: stack ids 11, 12, 13, 15, 16, 18 (trimmed id 23) +;; new char[10]; // stack id 11 +;; } +;; +;; void X(bool b) { +;; A(b); // stack ids 12 +;; } +;; +;; void B(bool b) { +;; X(b); // stack id 13 +;; } +;; +;; void D() { +;; B(true); // stack id 14 +;; } +;; +;; void C(bool b) { +;; B(b); // stack id 15 +;; } +;; +;; void E(bool b) { +;; C(b); // stack id 16 +;; } +;; +;; void F() { +;; E(false); // stack id 17 +;; } +;; +;; void G() { +;; E(false); // stack id 18 +;; } +;; +;; void M() { +;; C(true); // stack id 19 +;; } +;; +;; int main() { +;; D(); // stack id 20 (leads to not cold allocation) +;; M(); // stack id 21 (leads to cold allocation) +;; F(); // stack id 22 (leads to not cold allocation) +;; G(); // stack id 23 (leads to cold allocation) +;; } + +;; -stats requires asserts +; REQUIRES: asserts + +; RUN: opt -passes=memprof-context-disambiguation -supports-hot-cold-new \ +; RUN: -memprof-verify-ccg -memprof-verify-nodes \ +; RUN: -stats -pass-remarks=memprof-context-disambiguation \ +; RUN: %s -S 2>&1 | FileCheck %s --check-prefix=IR \ +; RUN: --check-prefix=STATS --check-prefix=REMARKS + +; REMARKS: created clone _Z1Ab.memprof.1 +; REMARKS: created clone _Z1Xb.memprof.1 +; REMARKS: created clone _Z1Bb.memprof.1 +; REMARKS: created clone _Z1Cb.memprof.1 +; REMARKS: created clone _Z1Eb.memprof.1 +; REMARKS: call in clone _Z1Gv assigned to call function clone _Z1Eb.memprof.1 +; REMARKS: call in clone _Z1Eb.memprof.1 assigned to call function clone _Z1Cb.memprof.1 +;; If we don't perform cloning for each allocation separately, we will miss +;; cloning _Z1Cb for the trimmed cold allocation context leading to the +;; allocation at stack id 10. +; REMARKS: call in clone _Z1Cb.memprof.1 assigned to call function clone _Z1Bb.memprof.1 +; REMARKS: call in clone _Z1Fv assigned to call function clone _Z1Eb +; REMARKS: call in clone _Z1Eb assigned to call function clone _Z1Cb +; REMARKS: call in clone _Z1Cb assigned to call function clone _Z1Bb.memprof.1 +; REMARKS: call in clone _Z1Bb.memprof.1 assigned to call function clone _Z1Xb.memprof.1 +; REMARKS: call in clone _Z1Xb.memprof.1 assigned to call function clone _Z1Ab.memprof.1 +; REMARKS: call in clone _Z1Ab.memprof.1 marked with memprof allocation attribute cold +; REMARKS: call in clone _Z1Bb.memprof.1 assigned to call function clone _Z1Xb +; REMARKS: call in clone _Z1Dv assigned to call function clone _Z1Bb +; REMARKS: call in clone _Z1Bb assigned to call function clone _Z1Xb +; REMARKS: call in clone _Z1Xb assigned to call function clone _Z1Ab +; REMARKS: call in clone _Z1Ab marked with memprof allocation attribute notcold +; REMARKS: call in clone _Z1Ab.memprof.1 marked with memprof allocation attribute cold +; REMARKS: call in clone _Z1Ab marked with memprof allocation attribute notcold + + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define dso_local void @_Z1Ab(i1 noundef zeroext %b) { +entry: + br i1 %b, label %if.then, label %if.else + +if.then: + %call = call noalias noundef nonnull ptr @_Znam(i64 noundef 10) #7, !memprof !0, !callsite !10 + br label %if.end + +if.else: + %call2 = call noalias noundef nonnull ptr @_Znam(i64 noundef 10) #7, !memprof !5, !callsite !11 + br label %if.end + +if.end: + ret void +} + +; Function Attrs: nobuiltin +declare ptr @_Znam(i64) #0 + +define dso_local void @_Z1Xb(i1 noundef zeroext %b) { +entry: + tail call void @_Z1Ab(i1 noundef zeroext %b), !callsite !12 + ret void +} + +define dso_local void @_Z1Bb(i1 noundef zeroext %b) { +entry: + tail call void @_Z1Xb(i1 noundef zeroext %b), !callsite !13 + ret void +} + +define dso_local void @_Z1Dv() { +entry: + tail call void @_Z1Bb(i1 noundef zeroext true), !callsite !14 + ret void +} + +define dso_local void @_Z1Cb(i1 noundef zeroext %b) { +entry: + tail call void @_Z1Bb(i1 noundef zeroext %b), !callsite !15 + ret void +} + +define dso_local void @_Z1Eb(i1 noundef zeroext %b) { +entry: + tail call void @_Z1Cb(i1 noundef zeroext %b), !callsite !16 + ret void +} + +define dso_local void @_Z1Fv() { +entry: + tail call void @_Z1Eb(i1 noundef zeroext false), !callsite !17 + ret void +} + +define dso_local void @_Z1Gv() { +entry: + tail call void @_Z1Eb(i1 noundef zeroext false), !callsite !18 + ret void +} + +define dso_local void @_Z1Mv() { +entry: + tail call void @_Z1Cb(i1 noundef zeroext true), !callsite !19 + ret void +} + +define dso_local noundef i32 @main() local_unnamed_addr { +entry: + tail call void @_Z1Dv(), !callsite !20 ;; Not cold context + tail call void @_Z1Mv(), !callsite !21 ;; Cold context + tail call void @_Z1Fv(), !callsite !22 ;; Not cold context + tail call void @_Z1Gv(), !callsite !23 ;; Cold context + ret i32 0 +} + +attributes #0 = { nobuiltin } +attributes #7 = { builtin } + +!0 = !{!1, !3} +;; Cold (trimmed) context via call to _Z1Dv in main +!1 = !{!2, !"cold"} +!2 = !{i64 10, i64 12, i64 13, i64 15} +;; Not cold (trimmed) context via call to _Z1Mv in main +!3 = !{!4, !"notcold"} +!4 = !{i64 10, i64 12, i64 13, i64 14} +!5 = !{!6, !8} +;; Not cold (trimmed) context via call to _Z1Fv in main +!6 = !{!7, !"notcold"} +!7 = !{i64 11, i64 12, i64 13, i64 15, i64 16, i64 17} +;; Cold (trimmed) context via call to _Z1Gv in main +!8 = !{!9, !"cold"} +!9 = !{i64 11, i64 12, i64 13, i64 15, i64 16, i64 18} +!10 = !{i64 10} +!11 = !{i64 11} +!12 = !{i64 12} +!13 = !{i64 13} +!14 = !{i64 14} +!15 = !{i64 15} +!16 = !{i64 16} +!17 = !{i64 17} +!18 = !{i64 18} +!19 = !{i64 19} +!20 = !{i64 20} +!21 = !{i64 21} +!22 = !{i64 22} +!23 = !{i64 23} + +; IR: define {{.*}} @_Z1Cb(i1 noundef zeroext %b) +; IR-NEXT: entry: +; IR-NEXT: call {{.*}} @_Z1Bb.memprof.1(i1 noundef zeroext %b) + +; IR: define {{.*}} @_Z1Ab.memprof.1(i1 noundef zeroext %b) +; IR-NEXT: entry: +; IR-NEXT: br i1 %b, label %if.then, label %if.else +; IR-EMPTY: +; IR-NEXT: if.then: +; IR-NEXT: call {{.*}} @_Znam(i64 noundef 10) #[[COLD:[0-9]+]] +; IR-NEXT: br label %if.end +; IR-EMPTY: +; IR-NEXT: if.else: +; IR-NEXT: call {{.*}} @_Znam(i64 noundef 10) #[[COLD]] + +; IR: define {{.*}} @_Z1Xb.memprof.1(i1 noundef zeroext %b) +; IR-NEXT: entry: +; IR-NEXT: call {{.*}} @_Z1Ab.memprof.1(i1 noundef zeroext %b) + +; IR: define {{.*}} @_Z1Bb.memprof.1(i1 noundef zeroext %b) +; IR-NEXT: entry: +; IR-NEXT: call {{.*}} @_Z1Xb.memprof.1(i1 noundef zeroext %b) + +; IR: attributes #[[COLD]] = { builtin "memprof"="cold" } + +; STATS: 2 memprof-context-disambiguation - Number of cold static allocations (possibly cloned) +; STATS: 2 memprof-context-disambiguation - Number of not cold static allocations (possibly cloned) +; STATS: 5 memprof-context-disambiguation - Number of function clones created during whole program analysis -- GitLab From 4afcfd7498363e42c002ee33a6e925c2d2c7b45e Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Apr 2024 14:13:45 -0700 Subject: [PATCH 337/695] [ELF] Sort DWARF.h sections. NFC to make it clear whether .debug_names should be added. And include llvm/ADT/STLFunctionalExtras.h for IWYU. --- lld/ELF/DWARF.h | 25 ++++++++++--------------- lld/ELF/SyntheticSections.h | 1 + 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/lld/ELF/DWARF.h b/lld/ELF/DWARF.h index d56895277bcc..ada38a043bc2 100644 --- a/lld/ELF/DWARF.h +++ b/lld/ELF/DWARF.h @@ -11,6 +11,7 @@ #include "InputFiles.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/STLFunctionalExtras.h" #include "llvm/DebugInfo/DWARF/DWARFContext.h" #include "llvm/Object/ELF.h" #include @@ -36,34 +37,28 @@ public: return cast(infoSection.sec); } + const llvm::DWARFSection &getAddrSection() const override { + return addrSection; + } + const llvm::DWARFSection &getLineSection() const override { + return lineSection; + } const llvm::DWARFSection &getLoclistsSection() const override { return loclistsSection; } - const llvm::DWARFSection &getRangesSection() const override { return rangesSection; } - const llvm::DWARFSection &getRnglistsSection() const override { return rnglistsSection; } - const llvm::DWARFSection &getStrOffsetsSection() const override { return strOffsetsSection; } - const llvm::DWARFSection &getLineSection() const override { - return lineSection; - } - - const llvm::DWARFSection &getAddrSection() const override { - return addrSection; - } - const LLDDWARFSection &getGnuPubnamesSection() const override { return gnuPubnamesSection; } - const LLDDWARFSection &getGnuPubtypesSection() const override { return gnuPubtypesSection; } @@ -86,18 +81,18 @@ private: uint64_t pos, ArrayRef rels) const; + LLDDWARFSection addrSection; LLDDWARFSection gnuPubnamesSection; LLDDWARFSection gnuPubtypesSection; LLDDWARFSection infoSection; + LLDDWARFSection lineSection; LLDDWARFSection loclistsSection; LLDDWARFSection rangesSection; LLDDWARFSection rnglistsSection; LLDDWARFSection strOffsetsSection; - LLDDWARFSection lineSection; - LLDDWARFSection addrSection; StringRef abbrevSection; - StringRef strSection; StringRef lineStrSection; + StringRef strSection; }; } // namespace lld::elf diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index 02a669b01d15..7490fb61fb6f 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -25,6 +25,7 @@ #include "Symbols.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/MapVector.h" +#include "llvm/ADT/STLFunctionalExtras.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/StringTableBuilder.h" #include "llvm/Support/Compiler.h" -- GitLab From eec41d2f8d81b546d7b97648cca6b2d656104bd3 Mon Sep 17 00:00:00 2001 From: Raghu Maddhipatla <7686592+raghavendhra@users.noreply.github.com> Date: Tue, 9 Apr 2024 16:18:56 -0500 Subject: [PATCH 338/695] Revert "[Flang] [OpenMP] [Semantics] [MLIR] [Lowering] Add lowering support for IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses on OMP TARGET directive." (#88198) Reverts llvm/llvm-project#74187 --- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 29 ------------- flang/lib/Lower/OpenMP/ClauseProcessor.h | 12 ------ flang/lib/Lower/OpenMP/OpenMP.cpp | 22 +++------- flang/test/Lower/OpenMP/FIR/target.f90 | 43 +------------------ mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 18 ++------ mlir/test/Dialect/OpenMP/invalid.mlir | 2 +- mlir/test/Dialect/OpenMP/ops.mlir | 8 ++-- 7 files changed, 14 insertions(+), 120 deletions(-) diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index fb24c8d1fe3e..0a57a1496289 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -751,20 +751,6 @@ bool ClauseProcessor::processDepend( }); } -bool ClauseProcessor::processHasDeviceAddr( - llvm::SmallVectorImpl &operands, - llvm::SmallVectorImpl &isDeviceTypes, - llvm::SmallVectorImpl &isDeviceLocs, - llvm::SmallVectorImpl &isDeviceSymbols) - const { - return findRepeatableClause( - [&](const omp::clause::HasDeviceAddr &devAddrClause, - const Fortran::parser::CharBlock &) { - addUseDeviceClause(converter, devAddrClause.v, operands, isDeviceTypes, - isDeviceLocs, isDeviceSymbols); - }); -} - bool ClauseProcessor::processIf( omp::clause::If::DirectiveNameModifier directiveName, mlir::Value &result) const { @@ -785,20 +771,6 @@ bool ClauseProcessor::processIf( return found; } -bool ClauseProcessor::processIsDevicePtr( - llvm::SmallVectorImpl &operands, - llvm::SmallVectorImpl &isDeviceTypes, - llvm::SmallVectorImpl &isDeviceLocs, - llvm::SmallVectorImpl &isDeviceSymbols) - const { - return findRepeatableClause( - [&](const omp::clause::IsDevicePtr &devPtrClause, - const Fortran::parser::CharBlock &) { - addUseDeviceClause(converter, devPtrClause.v, operands, isDeviceTypes, - isDeviceLocs, isDeviceSymbols); - }); -} - bool ClauseProcessor::processLink( llvm::SmallVectorImpl &result) const { return findRepeatableClause( @@ -1021,7 +993,6 @@ bool ClauseProcessor::processUseDevicePtr( useDeviceLocs, useDeviceSymbols); }); } - } // namespace omp } // namespace lower } // namespace Fortran diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.h b/flang/lib/Lower/OpenMP/ClauseProcessor.h index df8f4f5310fc..d31d6a5c2062 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.h +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.h @@ -66,12 +66,6 @@ public: bool processDeviceType(mlir::omp::DeclareTargetDeviceType &result) const; bool processFinal(Fortran::lower::StatementContext &stmtCtx, mlir::Value &result) const; - bool - processHasDeviceAddr(llvm::SmallVectorImpl &operands, - llvm::SmallVectorImpl &isDeviceTypes, - llvm::SmallVectorImpl &isDeviceLocs, - llvm::SmallVectorImpl - &isDeviceSymbols) const; bool processHint(mlir::IntegerAttr &result) const; bool processMergeable(mlir::UnitAttr &result) const; bool processNowait(mlir::UnitAttr &result) const; @@ -110,12 +104,6 @@ public: bool processIf(omp::clause::If::DirectiveNameModifier directiveName, mlir::Value &result) const; bool - processIsDevicePtr(llvm::SmallVectorImpl &operands, - llvm::SmallVectorImpl &isDeviceTypes, - llvm::SmallVectorImpl &isDeviceLocs, - llvm::SmallVectorImpl - &isDeviceSymbols) const; - bool processLink(llvm::SmallVectorImpl &result) const; // This method is used to process a map clause. diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 50ad889052ab..340921c86724 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -1294,11 +1294,6 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, llvm::SmallVector mapSymTypes; llvm::SmallVector mapSymLocs; llvm::SmallVector mapSymbols; - llvm::SmallVector devicePtrOperands, deviceAddrOperands; - llvm::SmallVector devicePtrTypes, deviceAddrTypes; - llvm::SmallVector devicePtrLocs, deviceAddrLocs; - llvm::SmallVector devicePtrSymbols, - deviceAddrSymbols; ClauseProcessor cp(converter, semaCtx, clauseList); cp.processIf(llvm::omp::Directive::OMPD_target, ifClauseOperand); @@ -1308,15 +1303,11 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, cp.processNowait(nowaitAttr); cp.processMap(currentLocation, directive, stmtCtx, mapOperands, &mapSymTypes, &mapSymLocs, &mapSymbols); - cp.processIsDevicePtr(devicePtrOperands, devicePtrTypes, devicePtrLocs, - devicePtrSymbols); - cp.processHasDeviceAddr(deviceAddrOperands, deviceAddrTypes, deviceAddrLocs, - deviceAddrSymbols); - cp.processTODO(currentLocation, - llvm::omp::Directive::OMPD_target); + cp.processTODO( + currentLocation, llvm::omp::Directive::OMPD_target); // 5.8.1 Implicit Data-Mapping Attribute Rules // The following code follows the implicit data-mapping rules to map all the @@ -1409,8 +1400,7 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, ? nullptr : mlir::ArrayAttr::get(converter.getFirOpBuilder().getContext(), dependTypeOperands), - dependOperands, nowaitAttr, devicePtrOperands, deviceAddrOperands, - mapOperands); + dependOperands, nowaitAttr, mapOperands); genBodyOfTargetOp(converter, semaCtx, eval, genNested, targetOp, mapSymTypes, mapSymLocs, mapSymbols, currentLocation); @@ -2069,8 +2059,6 @@ genOMP(Fortran::lower::AbstractConverter &converter, !std::get_if(&clause.u) && !std::get_if(&clause.u) && !std::get_if(&clause.u) && - !std::get_if(&clause.u) && - !std::get_if(&clause.u) && !std::get_if(&clause.u) && !std::get_if(&clause.u)) { TODO(clauseLocation, "OpenMP Block construct clause"); diff --git a/flang/test/Lower/OpenMP/FIR/target.f90 b/flang/test/Lower/OpenMP/FIR/target.f90 index 022327f9c25d..821196b83c3b 100644 --- a/flang/test/Lower/OpenMP/FIR/target.f90 +++ b/flang/test/Lower/OpenMP/FIR/target.f90 @@ -506,45 +506,4 @@ subroutine omp_target_parallel_do !CHECK: omp.terminator !CHECK: } !$omp end target parallel do -end subroutine omp_target_parallel_do - -!=============================================================================== -! Target `is_device_ptr` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_is_device_ptr() { -subroutine omp_target_is_device_ptr - use iso_c_binding, only : c_ptr, c_loc - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> {bindc_name = "a", uniq_name = "_QFomp_target_is_device_ptrEa"} - type(c_ptr) :: a - !CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "b", fir.target, uniq_name = "_QFomp_target_is_device_ptrEb"} - integer, target :: b - !CHECK: %[[MAP_0:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(tofrom) capture(ByRef) -> !fir.ref> {name = "a"} - !CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr(%[[VAL_0:.*]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "b"} - !CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByRef) -> !fir.ref> {name = "a"} - !CHECK: omp.target is_device_ptr(%[[DEV_PTR:.*]] : !fir.ref>) map_entries(%[[MAP_0:.*]] -> %[[ARG0:.*]], %[[MAP_1:.*]] -> %[[ARG1:.*]], %[[MAP_2:.*]] -> %[[ARG2:.*]] : !fir.ref>, !fir.ref, !fir.ref>) { - !CHECK: ^bb0(%[[ARG0]]: !fir.ref>, %[[ARG1]]: !fir.ref, %[[ARG2]]: !fir.ref>): - !$omp target map(tofrom: a,b) is_device_ptr(a) - !CHECK: {{.*}} = fir.coordinate_of %[[VAL_0:.*]], {{.*}} : (!fir.ref>, !fir.field) -> !fir.ref - a = c_loc(b) - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_is_device_ptr - - !=============================================================================== - ! Target `has_device_addr` clause - !=============================================================================== - - !CHECK-LABEL: func.func @_QPomp_target_has_device_addr() { - subroutine omp_target_has_device_addr - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFomp_target_has_device_addrEa"} - integer, pointer :: a - !CHECK: omp.target has_device_addr(%[[VAL_0:.*]] : !fir.ref>>) map_entries({{.*}} -> {{.*}}, {{.*}} -> {{.*}} : !fir.llvm_ptr>, !fir.ref>>) { - !$omp target has_device_addr(a) - !CHECK: {{.*}} = fir.load %[[VAL_0:.*]] : !fir.ref>> - a = 10 - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_has_device_addr + end subroutine omp_target_parallel_do diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index 2a8582be3833..a38a82f9cc60 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -1678,23 +1678,14 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac The optional $thread_limit specifies the limit on the number of threads - The optional $nowait eliminates the implicit barrier so the parent task can make progress + The optional $nowait elliminates the implicit barrier so the parent task can make progress even if the target task is not yet completed. The `depends` and `depend_vars` arguments are variadic lists of values that specify the dependencies of this particular target task in relation to other tasks. - The optional $is_device_ptr indicates list items are device pointers. - - The optional $has_device_addr indicates that list items already have device - addresses, so they may be directly accessed from the target device. This - includes array sections. - - The optional $map_operands maps data from the task’s environment to the - device environment. - - TODO: defaultmap, in_reduction + TODO: is_device_ptr, defaultmap, in_reduction }]; @@ -1704,9 +1695,8 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac OptionalAttr:$depends, Variadic:$depend_vars, UnitAttr:$nowait, - Variadic:$is_device_ptr, - Variadic:$has_device_addr, Variadic:$map_operands); + let regions = (region AnyRegion:$region); let builders = [ @@ -1718,8 +1708,6 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac | `device` `(` $device `:` type($device) `)` | `thread_limit` `(` $thread_limit `:` type($thread_limit) `)` | `nowait` $nowait - | `is_device_ptr` `(` $is_device_ptr `:` type($is_device_ptr) `)` - | `has_device_addr` `(` $has_device_addr `:` type($has_device_addr) `)` | `map_entries` `(` custom($map_operands, type($map_operands)) `)` | `depend` `(` custom($depend_vars, type($depend_vars), $depends) `)` ) $region attr-dict diff --git a/mlir/test/Dialect/OpenMP/invalid.mlir b/mlir/test/Dialect/OpenMP/invalid.mlir index 27a440b3f97c..1134db77d5ba 100644 --- a/mlir/test/Dialect/OpenMP/invalid.mlir +++ b/mlir/test/Dialect/OpenMP/invalid.mlir @@ -1809,7 +1809,7 @@ func.func @omp_target_depend(%data_var: memref) { // expected-error @below {{op expected as many depend values as depend variables}} "omp.target"(%data_var) ({ "omp.terminator"() : () -> () - }) {depends = [], operandSegmentSizes = array} : (memref) -> () + }) {depends = [], operandSegmentSizes = array} : (memref) -> () "func.return"() : () -> () } diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index ad5b74b84ac7..e2c255c7a3cc 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -510,22 +510,22 @@ return // CHECK-LABEL: omp_target -func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %device_ptr: memref, %device_addr: memref, %map1: memref, %map2: memref) -> () { +func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %map1: memref, %map2: memref) -> () { // Test with optional operands; if_expr, device, thread_limit, private, firstprivate and nowait. // CHECK: omp.target if({{.*}}) device({{.*}}) thread_limit({{.*}}) nowait "omp.target"(%if_cond, %device, %num_threads) ({ // CHECK: omp.terminator omp.terminator - }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () + }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () // Test with optional map clause. // CHECK: %[[MAP_A:.*]] = omp.map.info var_ptr(%[[VAL_1:.*]] : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} // CHECK: %[[MAP_B:.*]] = omp.map.info var_ptr(%[[VAL_2:.*]] : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} - // CHECK: omp.target is_device_ptr(%[[VAL_4:.*]] : memref) has_device_addr(%[[VAL_5:.*]] : memref) map_entries(%[[MAP_A]] -> {{.*}}, %[[MAP_B]] -> {{.*}} : memref, memref) { + // CHECK: omp.target map_entries(%[[MAP_A]] -> {{.*}}, %[[MAP_B]] -> {{.*}} : memref, memref) { %mapv1 = omp.map.info var_ptr(%map1 : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} %mapv2 = omp.map.info var_ptr(%map2 : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} - omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) is_device_ptr(%device_ptr : memref) has_device_addr(%device_addr : memref) { + omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) { ^bb0(%arg0: memref, %arg1: memref): omp.terminator } -- GitLab From f04452de1986e4e01296a80231efb212d6c84c42 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Tue, 9 Apr 2024 15:13:55 -0700 Subject: [PATCH 339/695] [InstallAPI] Tie lifetime of FE objects to DylibVerifier (#88189) A few verification checks need to happen until all AST's have been traversed, specifically for zippered framework checking. To keep source location until that time valid, hold onto to references of FrontendRecords + SourceManager. --- .../include/clang/InstallAPI/DylibVerifier.h | 10 ++-- clang/include/clang/InstallAPI/Frontend.h | 2 +- .../clang/InstallAPI/FrontendRecords.h | 1 + clang/lib/InstallAPI/DylibVerifier.cpp | 47 +++++++++---------- clang/lib/InstallAPI/Frontend.cpp | 15 +++--- .../clang-installapi/ClangInstallAPI.cpp | 2 + 6 files changed, 40 insertions(+), 37 deletions(-) diff --git a/clang/include/clang/InstallAPI/DylibVerifier.h b/clang/include/clang/InstallAPI/DylibVerifier.h index 07dbd3bf5f2b..a3df25f10de4 100644 --- a/clang/include/clang/InstallAPI/DylibVerifier.h +++ b/clang/include/clang/InstallAPI/DylibVerifier.h @@ -10,6 +10,7 @@ #define LLVM_CLANG_INSTALLAPI_DYLIBVERIFIER_H #include "clang/Basic/Diagnostic.h" +#include "clang/Basic/SourceManager.h" #include "clang/InstallAPI/MachO.h" namespace clang { @@ -99,11 +100,7 @@ public: Result getState() const { return Ctx.FrontendState; } /// Set different source managers to the same diagnostics engine. - void setSourceManager(SourceManager &SourceMgr) const { - if (!Ctx.Diag) - return; - Ctx.Diag->setSourceManager(&SourceMgr); - } + void setSourceManager(IntrusiveRefCntPtr SourceMgr); private: /// Determine whether to compare declaration to symbol in binary. @@ -190,6 +187,9 @@ private: // Track DWARF provided source location for dylibs. DWARFContext *DWARFCtx = nullptr; + + // Source manager for each unique compiler instance. + llvm::SmallVector, 12> SourceManagers; }; } // namespace installapi diff --git a/clang/include/clang/InstallAPI/Frontend.h b/clang/include/clang/InstallAPI/Frontend.h index 5cccd891c580..bc4e77de2b72 100644 --- a/clang/include/clang/InstallAPI/Frontend.h +++ b/clang/include/clang/InstallAPI/Frontend.h @@ -36,7 +36,7 @@ public: std::unique_ptr CreateASTConsumer(CompilerInstance &CI, StringRef InFile) override { Ctx.Diags->getClient()->BeginSourceFile(CI.getLangOpts()); - Ctx.Verifier->setSourceManager(CI.getSourceManager()); + Ctx.Verifier->setSourceManager(CI.getSourceManagerPtr()); return std::make_unique( CI.getASTContext(), Ctx, CI.getSourceManager(), CI.getPreprocessor()); } diff --git a/clang/include/clang/InstallAPI/FrontendRecords.h b/clang/include/clang/InstallAPI/FrontendRecords.h index 59271e81e230..ef82398addd7 100644 --- a/clang/include/clang/InstallAPI/FrontendRecords.h +++ b/clang/include/clang/InstallAPI/FrontendRecords.h @@ -21,6 +21,7 @@ namespace installapi { struct FrontendAttrs { const AvailabilityInfo Avail; const Decl *D; + const SourceLocation Loc; const HeaderType Access; }; diff --git a/clang/lib/InstallAPI/DylibVerifier.cpp b/clang/lib/InstallAPI/DylibVerifier.cpp index 2387ee0e78ad..4fa2d4e9292c 100644 --- a/clang/lib/InstallAPI/DylibVerifier.cpp +++ b/clang/lib/InstallAPI/DylibVerifier.cpp @@ -214,16 +214,16 @@ bool DylibVerifier::compareObjCInterfaceSymbols(const Record *R, StringRef SymName, bool PrintAsWarning = false) { if (SymLinkage == RecordLinkage::Unknown) Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - PrintAsWarning ? diag::warn_library_missing_symbol - : diag::err_library_missing_symbol) + Ctx.Diag->Report(SymCtx.FA->Loc, PrintAsWarning + ? diag::warn_library_missing_symbol + : diag::err_library_missing_symbol) << SymName; }); else Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - PrintAsWarning ? diag::warn_library_hidden_symbol - : diag::err_library_hidden_symbol) + Ctx.Diag->Report(SymCtx.FA->Loc, PrintAsWarning + ? diag::warn_library_hidden_symbol + : diag::err_library_hidden_symbol) << SymName; }); }; @@ -270,16 +270,14 @@ DylibVerifier::Result DylibVerifier::compareVisibility(const Record *R, if (R->isExported()) { if (!DR) { Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_library_missing_symbol) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_library_missing_symbol) << getAnnotatedName(R, SymCtx); }); return Result::Invalid; } if (DR->isInternal()) { Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_library_hidden_symbol) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_library_hidden_symbol) << getAnnotatedName(R, SymCtx); }); return Result::Invalid; @@ -306,8 +304,7 @@ DylibVerifier::Result DylibVerifier::compareVisibility(const Record *R, Outcome = Result::Invalid; } Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), ID) - << getAnnotatedName(R, SymCtx); + Ctx.Diag->Report(SymCtx.FA->Loc, ID) << getAnnotatedName(R, SymCtx); }); return Outcome; } @@ -329,15 +326,13 @@ DylibVerifier::Result DylibVerifier::compareAvailability(const Record *R, switch (Mode) { case VerificationMode::ErrorsAndWarnings: Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::warn_header_availability_mismatch) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::warn_header_availability_mismatch) << getAnnotatedName(R, SymCtx) << IsDeclAvailable << IsDeclAvailable; }); return Result::Ignore; case VerificationMode::Pedantic: Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_header_availability_mismatch) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_header_availability_mismatch) << getAnnotatedName(R, SymCtx) << IsDeclAvailable << IsDeclAvailable; }); return Result::Invalid; @@ -353,16 +348,14 @@ bool DylibVerifier::compareSymbolFlags(const Record *R, SymbolContext &SymCtx, const Record *DR) { if (DR->isThreadLocalValue() && !R->isThreadLocalValue()) { Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_dylib_symbol_flags_mismatch) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_dylib_symbol_flags_mismatch) << getAnnotatedName(DR, SymCtx) << DR->isThreadLocalValue(); }); return false; } if (!DR->isThreadLocalValue() && R->isThreadLocalValue()) { Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_header_symbol_flags_mismatch) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_header_symbol_flags_mismatch) << getAnnotatedName(R, SymCtx) << R->isThreadLocalValue(); }); return false; @@ -370,16 +363,14 @@ bool DylibVerifier::compareSymbolFlags(const Record *R, SymbolContext &SymCtx, if (DR->isWeakDefined() && !R->isWeakDefined()) { Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_dylib_symbol_flags_mismatch) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_dylib_symbol_flags_mismatch) << getAnnotatedName(DR, SymCtx) << R->isWeakDefined(); }); return false; } if (!DR->isWeakDefined() && R->isWeakDefined()) { Ctx.emitDiag([&]() { - Ctx.Diag->Report(SymCtx.FA->D->getLocation(), - diag::err_header_symbol_flags_mismatch) + Ctx.Diag->Report(SymCtx.FA->Loc, diag::err_header_symbol_flags_mismatch) << getAnnotatedName(R, SymCtx) << R->isWeakDefined(); }); return false; @@ -487,6 +478,14 @@ void DylibVerifier::setTarget(const Target &T) { assignSlice(T); } +void DylibVerifier::setSourceManager( + IntrusiveRefCntPtr SourceMgr) { + if (!Ctx.Diag) + return; + SourceManagers.push_back(std::move(SourceMgr)); + Ctx.Diag->setSourceManager(SourceManagers.back().get()); +} + DylibVerifier::Result DylibVerifier::verify(ObjCIVarRecord *R, const FrontendAttrs *FA, const StringRef SuperClass) { diff --git a/clang/lib/InstallAPI/Frontend.cpp b/clang/lib/InstallAPI/Frontend.cpp index bd7589c13e04..04d06f46d265 100644 --- a/clang/lib/InstallAPI/Frontend.cpp +++ b/clang/lib/InstallAPI/Frontend.cpp @@ -23,7 +23,8 @@ std::pair FrontendRecordsSlice::addGlobal( GlobalRecord *GR = llvm::MachO::RecordsSlice::addGlobal(Name, Linkage, GV, Flags, Inlined); - auto Result = FrontendRecords.insert({GR, FrontendAttrs{Avail, D, Access}}); + auto Result = FrontendRecords.insert( + {GR, FrontendAttrs{Avail, D, D->getLocation(), Access}}); return {GR, &(Result.first->second)}; } @@ -39,8 +40,8 @@ FrontendRecordsSlice::addObjCInterface(StringRef Name, RecordLinkage Linkage, ObjCInterfaceRecord *ObjCR = llvm::MachO::RecordsSlice::addObjCInterface(Name, Linkage, SymType); - auto Result = - FrontendRecords.insert({ObjCR, FrontendAttrs{Avail, D, Access}}); + auto Result = FrontendRecords.insert( + {ObjCR, FrontendAttrs{Avail, D, D->getLocation(), Access}}); return {ObjCR, &(Result.first->second)}; } @@ -51,8 +52,8 @@ FrontendRecordsSlice::addObjCCategory(StringRef ClassToExtend, const Decl *D, HeaderType Access) { ObjCCategoryRecord *ObjCR = llvm::MachO::RecordsSlice::addObjCCategory(ClassToExtend, CategoryName); - auto Result = - FrontendRecords.insert({ObjCR, FrontendAttrs{Avail, D, Access}}); + auto Result = FrontendRecords.insert( + {ObjCR, FrontendAttrs{Avail, D, D->getLocation(), Access}}); return {ObjCR, &(Result.first->second)}; } @@ -67,8 +68,8 @@ std::pair FrontendRecordsSlice::addObjCIVar( Linkage = RecordLinkage::Internal; ObjCIVarRecord *ObjCR = llvm::MachO::RecordsSlice::addObjCIVar(Container, IvarName, Linkage); - auto Result = - FrontendRecords.insert({ObjCR, FrontendAttrs{Avail, D, Access}}); + auto Result = FrontendRecords.insert( + {ObjCR, FrontendAttrs{Avail, D, D->getLocation(), Access}}); return {ObjCR, &(Result.first->second)}; } diff --git a/clang/tools/clang-installapi/ClangInstallAPI.cpp b/clang/tools/clang-installapi/ClangInstallAPI.cpp index 0c1980ba5d62..fd71aaec5943 100644 --- a/clang/tools/clang-installapi/ClangInstallAPI.cpp +++ b/clang/tools/clang-installapi/ClangInstallAPI.cpp @@ -121,6 +121,7 @@ static bool run(ArrayRef Args, const char *ProgName) { // Execute, verify and gather AST results. // An invocation is ran for each unique target triple and for each header // access level. + Records FrontendRecords; for (const auto &[Targ, Trip] : Opts.DriverOpts.Targets) { Ctx.Verifier->setTarget(Targ); Ctx.Slice = std::make_shared(Trip); @@ -131,6 +132,7 @@ static bool run(ArrayRef Args, const char *ProgName) { InMemoryFileSystem.get(), Opts.getClangFrontendArgs())) return EXIT_FAILURE; } + FrontendRecords.emplace_back(std::move(Ctx.Slice)); } if (Ctx.Verifier->verifyRemainingSymbols() == DylibVerifier::Result::Invalid) -- GitLab From 4a04fca9e2f936264bccba58081893c6703de7ec Mon Sep 17 00:00:00 2001 From: PiJoules <6019989+PiJoules@users.noreply.github.com> Date: Tue, 9 Apr 2024 15:39:05 -0700 Subject: [PATCH 340/695] [compiler-rt][asan] Fix for flaky asan check (#88177) This fixes https://github.com/llvm/llvm-project/issues/87324. We haven't been able to come up with a minimal reproducer but we can reliabely avoid this failure with the following fix. Prior to the GetGlobalLowLevelAllocator change, the old LowLevelAllocator aquired a lock associated with it preventing that specific allocator from being accessed at the same time by many threads. With the GetGlobalLowLevelAllocator change, I had accidentally replaced it but not taken into account the lock, so we can have a data race if the allocator is used at any point while a thread is being created. The global allocator can be used for flag parsing or registering asan globals. --- compiler-rt/lib/asan/asan_thread.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/compiler-rt/lib/asan/asan_thread.cpp b/compiler-rt/lib/asan/asan_thread.cpp index 8798968947e8..480a423952e8 100644 --- a/compiler-rt/lib/asan/asan_thread.cpp +++ b/compiler-rt/lib/asan/asan_thread.cpp @@ -44,10 +44,15 @@ static ThreadRegistry *asan_thread_registry; static ThreadArgRetval *thread_data; static Mutex mu_for_thread_context; +// TODO(leonardchan@): It should be possible to make LowLevelAllocator +// threadsafe and consolidate this one into the GlobalLoweLevelAllocator. +// We should be able to do something similar to what's in +// sanitizer_stack_store.cpp. +static LowLevelAllocator allocator_for_thread_context; static ThreadContextBase *GetAsanThreadContext(u32 tid) { Lock lock(&mu_for_thread_context); - return new (GetGlobalLowLevelAllocator()) AsanThreadContext(tid); + return new (allocator_for_thread_context) AsanThreadContext(tid); } static void InitThreads() { -- GitLab From 788be0d9fc6aeca548c90bac5ebe6990dd3c66ec Mon Sep 17 00:00:00 2001 From: Brooks Davis Date: Tue, 9 Apr 2024 15:55:11 -0700 Subject: [PATCH 341/695] [flang] fix build on *BSD after 4762c6557d15 (#86204) The HUGE definition collides with the HUGE macro from math.h. Unlike the fix in 3149c934cb26 (#84478) (largely reverted in f95710c76519), add another #undef HUGE since there is no practical way to make FreeBSD's headers not define HUGE and still define XSI interfaces such as isascii or strnlen. Update comments above `#undef HUGE` instances to reflect the fact that all major BSD versions (I checked DragonFly, FreeBSD, NetBSD, and OpenBSD) leak the HUGE macro from math.h to various degrees. Fixes #86038 --- flang/include/flang/Evaluate/integer.h | 2 +- flang/include/flang/Evaluate/real.h | 2 +- flang/lib/Decimal/decimal-to-binary.cpp | 4 ++++ flang/lib/Evaluate/fold-implementation.h | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/flang/include/flang/Evaluate/integer.h b/flang/include/flang/Evaluate/integer.h index 739564570126..b62e2bcb90f2 100644 --- a/flang/include/flang/Evaluate/integer.h +++ b/flang/include/flang/Evaluate/integer.h @@ -27,7 +27,7 @@ #include #include -// Some environments, viz. glibc 2.17, allow the macro HUGE +// Some environments, viz. glibc 2.17 and *BSD, allow the macro HUGE // to leak out of . #undef HUGE diff --git a/flang/include/flang/Evaluate/real.h b/flang/include/flang/Evaluate/real.h index b7af0ff6b431..6f2466c9da67 100644 --- a/flang/include/flang/Evaluate/real.h +++ b/flang/include/flang/Evaluate/real.h @@ -18,7 +18,7 @@ #include #include -// Some environments, viz. glibc 2.17, allow the macro HUGE +// Some environments, viz. glibc 2.17 and *BSD, allow the macro HUGE // to leak out of . #undef HUGE diff --git a/flang/lib/Decimal/decimal-to-binary.cpp b/flang/lib/Decimal/decimal-to-binary.cpp index eebd0736b67a..94c517742373 100644 --- a/flang/lib/Decimal/decimal-to-binary.cpp +++ b/flang/lib/Decimal/decimal-to-binary.cpp @@ -16,6 +16,10 @@ #include #include +// Some environments, viz. glibc 2.17 and *BSD, allow the macro HUGE +// to leak out of . +#undef HUGE + namespace Fortran::decimal { template diff --git a/flang/lib/Evaluate/fold-implementation.h b/flang/lib/Evaluate/fold-implementation.h index 470dbe9e7409..34f79f9e6f25 100644 --- a/flang/lib/Evaluate/fold-implementation.h +++ b/flang/lib/Evaluate/fold-implementation.h @@ -39,7 +39,7 @@ #include #include -// Some environments, viz. glibc 2.17, allow the macro HUGE +// Some environments, viz. glibc 2.17 and *BSD, allow the macro HUGE // to leak out of . #undef HUGE -- GitLab From 9170e3857521324c096240bf38877e0ffe1a402e Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 20 Mar 2024 16:46:24 -0500 Subject: [PATCH 342/695] Add support for `nneg` flag with `uitofp` As noted when #82404 was pushed (canonicalizing `sitofp` -> `uitofp`), different signedness on fp casts can have dramatic performance implications on different backends. So, it makes to create a reliable means for the backend to pick its cast signedness if either are correct. Further, this allows us to start canonicalizing `sitofp`- > `uitofp` which may easy middle end analysis. Closes #86141 --- llvm/docs/LangRef.rst | 10 ++++++ llvm/include/llvm/IR/IRBuilder.h | 10 ++++-- llvm/include/llvm/IR/InstrTypes.h | 10 ++++-- llvm/lib/AsmParser/LLParser.cpp | 2 +- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 2 +- llvm/lib/IR/Instruction.cpp | 5 +-- llvm/lib/IR/Operator.cpp | 1 + llvm/test/Assembler/flags.ll | 7 +++++ llvm/test/Bitcode/flags.ll | 4 +++ llvm/test/Transforms/InstCombine/freeze.ll | 11 +++++++ llvm/test/Transforms/SimplifyCFG/HoistCode.ll | 31 +++++++++++++++++++ 11 files changed, 85 insertions(+), 8 deletions(-) diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 18fc46584d09..f6ada292b93b 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -11751,6 +11751,10 @@ Overview: The '``uitofp``' instruction regards ``value`` as an unsigned integer and converts that value to the ``ty2`` type. +The ``nneg`` (non-negative) flag, if present, specifies that the +operand is non-negative. This property may be used by optimization +passes to later convert the ``uitofp`` into a ``sitofp``. + Arguments: """""""""" @@ -11768,6 +11772,9 @@ integer quantity and converts it to the corresponding floating-point value. If the value cannot be exactly represented, it is rounded using the default rounding mode. +If the ``nneg`` flag is set, and the ``uitofp`` argument is negative, +the result is a poison value. + Example: """""""" @@ -11777,6 +11784,9 @@ Example: %X = uitofp i32 257 to float ; yields float:257.0 %Y = uitofp i8 -1 to double ; yields double:255.0 + %a = uitofp nneg i32 256 to i32 ; yields float:256.0 + %b = uitofp nneg i32 -256 to i32 ; yields i32 poison + '``sitofp .. to``' Instruction ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h index 2e2ec9a1c830..f381273c46cf 100644 --- a/llvm/include/llvm/IR/IRBuilder.h +++ b/llvm/include/llvm/IR/IRBuilder.h @@ -2068,11 +2068,17 @@ public: return CreateCast(Instruction::FPToSI, V, DestTy, Name); } - Value *CreateUIToFP(Value *V, Type *DestTy, const Twine &Name = ""){ + Value *CreateUIToFP(Value *V, Type *DestTy, const Twine &Name = "", + bool IsNonNeg = false) { if (IsFPConstrained) return CreateConstrainedFPCast(Intrinsic::experimental_constrained_uitofp, V, DestTy, nullptr, Name); - return CreateCast(Instruction::UIToFP, V, DestTy, Name); + if (Value *Folded = Folder.FoldCast(Instruction::UIToFP, V, DestTy)) + return Folded; + Instruction *I = Insert(new UIToFPInst(V, DestTy), Name); + if (IsNonNeg) + I->setNonNeg(); + return I; } Value *CreateSIToFP(Value *V, Type *DestTy, const Twine &Name = ""){ diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index e4e5fa15c399..cfe1b11ade5a 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -927,13 +927,19 @@ public: } }; -/// Instruction that can have a nneg flag (only zext). +/// Instruction that can have a nneg flag (zext/uitofp). class PossiblyNonNegInst : public CastInst { public: enum { NonNeg = (1 << 0) }; static bool classof(const Instruction *I) { - return I->getOpcode() == Instruction::ZExt; + switch (I->getOpcode()) { + case Instruction::ZExt: + case Instruction::UIToFP: + return true; + default: + return false; + } } static bool classof(const Value *V) { diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 8609f3d6276c..f546e05a5d37 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -6816,6 +6816,7 @@ int LLParser::parseInstruction(Instruction *&Inst, BasicBlock *BB, } // Casts. + case lltok::kw_uitofp: case lltok::kw_zext: { bool NonNeg = EatIfPresent(lltok::kw_nneg); bool Res = parseCast(Inst, PFS, KeywordVal); @@ -6843,7 +6844,6 @@ int LLParser::parseInstruction(Instruction *&Inst, BasicBlock *BB, case lltok::kw_fpext: case lltok::kw_bitcast: case lltok::kw_addrspacecast: - case lltok::kw_uitofp: case lltok::kw_sitofp: case lltok::kw_fptoui: case lltok::kw_fptosi: diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 5ea6cc2c6b52..92c349525aff 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -5039,7 +5039,7 @@ Error BitcodeReader::parseFunctionBody(Function *F) { } if (OpNum < Record.size()) { - if (Opc == Instruction::ZExt) { + if (Opc == Instruction::ZExt || Opc == Instruction::UIToFP) { if (Record[OpNum] & (1 << bitc::PNNI_NON_NEG)) cast(I)->setNonNeg(true); } else if (Opc == Instruction::Trunc) { diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index 0602a55b9fe7..b9efe9cdcfe3 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -388,7 +388,7 @@ void Instruction::setIsExact(bool b) { } void Instruction::setNonNeg(bool b) { - assert(isa(this) && "Must be zext"); + assert(isa(this) && "Must be zext/uitofp"); SubclassOptionalData = (SubclassOptionalData & ~PossiblyNonNegInst::NonNeg) | (b * PossiblyNonNegInst::NonNeg); } @@ -408,7 +408,7 @@ bool Instruction::hasNoSignedWrap() const { } bool Instruction::hasNonNeg() const { - assert(isa(this) && "Must be zext"); + assert(isa(this) && "Must be zext/uitofp"); return (SubclassOptionalData & PossiblyNonNegInst::NonNeg) != 0; } @@ -441,6 +441,7 @@ void Instruction::dropPoisonGeneratingFlags() { cast(this)->setIsInBounds(false); break; + case Instruction::UIToFP: case Instruction::ZExt: setNonNeg(false); break; diff --git a/llvm/lib/IR/Operator.cpp b/llvm/lib/IR/Operator.cpp index 7b4449cd825f..ccc624d85442 100644 --- a/llvm/lib/IR/Operator.cpp +++ b/llvm/lib/IR/Operator.cpp @@ -44,6 +44,7 @@ bool Operator::hasPoisonGeneratingFlags() const { // Note: inrange exists on constexpr only return GEP->isInBounds() || GEP->getInRange() != std::nullopt; } + case Instruction::UIToFP: case Instruction::ZExt: if (auto *NNI = dyn_cast(this)) return NNI->hasNonNeg(); diff --git a/llvm/test/Assembler/flags.ll b/llvm/test/Assembler/flags.ll index d75b0cb0ea82..e0ad8bf000be 100644 --- a/llvm/test/Assembler/flags.ll +++ b/llvm/test/Assembler/flags.ll @@ -256,6 +256,13 @@ define i64 @test_zext(i32 %a) { ret i64 %res } +define float @test_uitofp(i32 %a) { +; CHECK: %res = uitofp nneg i32 %a to float + %res = uitofp nneg i32 %a to float + ret float %res +} + + define i64 @test_or(i64 %a, i64 %b) { ; CHECK: %res = or disjoint i64 %a, %b %res = or disjoint i64 %a, %b diff --git a/llvm/test/Bitcode/flags.ll b/llvm/test/Bitcode/flags.ll index 96995ec570c9..fd56694ccceb 100644 --- a/llvm/test/Bitcode/flags.ll +++ b/llvm/test/Bitcode/flags.ll @@ -18,6 +18,8 @@ second: ; preds = %first %z = add i32 %a, 0 ; [#uses=0] %hh = zext nneg i32 %a to i64 %ll = zext i32 %s to i64 + %ff = uitofp nneg i32 %a to float + %bb = uitofp i32 %s to float %jj = or disjoint i32 %a, 0 %oo = or i32 %a, 0 %tu = trunc nuw i32 %a to i16 @@ -39,6 +41,8 @@ first: ; preds = %entry %zz = add i32 %a, 0 ; [#uses=0] %kk = zext nneg i32 %a to i64 %rr = zext i32 %ss to i64 + %ww = uitofp nneg i32 %a to float + %xx = uitofp i32 %ss to float %mm = or disjoint i32 %a, 0 %nn = or i32 %a, 0 %tuu = trunc nuw i32 %a to i16 diff --git a/llvm/test/Transforms/InstCombine/freeze.ll b/llvm/test/Transforms/InstCombine/freeze.ll index e8105b6287d0..668f3033ed4b 100644 --- a/llvm/test/Transforms/InstCombine/freeze.ll +++ b/llvm/test/Transforms/InstCombine/freeze.ll @@ -1127,6 +1127,17 @@ define i32 @freeze_zext_nneg(i8 %x) { ret i32 %fr } +define float @freeze_uitofp_nneg(i8 %x) { +; CHECK-LABEL: @freeze_uitofp_nneg( +; CHECK-NEXT: [[X_FR:%.*]] = freeze i8 [[X:%.*]] +; CHECK-NEXT: [[UITOFP:%.*]] = uitofp i8 [[X_FR]] to float +; CHECK-NEXT: ret float [[UITOFP]] +; + %uitofp = uitofp nneg i8 %x to float + %fr = freeze float %uitofp + ret float %fr +} + define i32 @propagate_drop_flags_or(i32 %arg) { ; CHECK-LABEL: @propagate_drop_flags_or( ; CHECK-NEXT: [[ARG_FR:%.*]] = freeze i32 [[ARG:%.*]] diff --git a/llvm/test/Transforms/SimplifyCFG/HoistCode.ll b/llvm/test/Transforms/SimplifyCFG/HoistCode.ll index 4a4c94098ab9..887d18201681 100644 --- a/llvm/test/Transforms/SimplifyCFG/HoistCode.ll +++ b/llvm/test/Transforms/SimplifyCFG/HoistCode.ll @@ -125,6 +125,37 @@ F: ret i32 %z2 } + +define float @hoist_uitofp_flags_preserve(i1 %C, i8 %x) { +; CHECK-LABEL: @hoist_uitofp_flags_preserve( +; CHECK-NEXT: common.ret: +; CHECK-NEXT: [[Z1:%.*]] = uitofp nneg i8 [[X:%.*]] to float +; CHECK-NEXT: ret float [[Z1]] +; + br i1 %C, label %T, label %F +T: + %z1 = uitofp nneg i8 %x to float + ret float %z1 +F: + %z2 = uitofp nneg i8 %x to float + ret float %z2 +} + +define float @hoist_uitofp_flags_drop(i1 %C, i8 %x) { +; CHECK-LABEL: @hoist_uitofp_flags_drop( +; CHECK-NEXT: common.ret: +; CHECK-NEXT: [[Z1:%.*]] = uitofp i8 [[X:%.*]] to float +; CHECK-NEXT: ret float [[Z1]] +; + br i1 %C, label %T, label %F +T: + %z1 = uitofp nneg i8 %x to float + ret float %z1 +F: + %z2 = uitofp i8 %x to float + ret float %z2 +} + define i32 @hoist_or_flags_preserve(i1 %C, i32 %x, i32 %y) { ; CHECK-LABEL: @hoist_or_flags_preserve( ; CHECK-NEXT: common.ret: -- GitLab From e8a3b72272e3e67e94ee9d7144d3c8292c49e868 Mon Sep 17 00:00:00 2001 From: Evgenii Stepanov Date: Mon, 8 Apr 2024 16:14:39 -0700 Subject: [PATCH 343/695] [msan] Precommit tests. Precommit tests for overflowing and saturating arithmetic intrinsics. --- .../MemorySanitizer/overflow.ll | 163 ++++++++++++++++++ .../MemorySanitizer/saturating.ll | 113 ++++++++++++ 2 files changed, 276 insertions(+) create mode 100644 llvm/test/Instrumentation/MemorySanitizer/overflow.ll create mode 100644 llvm/test/Instrumentation/MemorySanitizer/saturating.ll diff --git a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll new file mode 100644 index 000000000000..b1304faec3df --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll @@ -0,0 +1,163 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_sadd_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} + +define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_uadd_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} + +define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_smul_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} +define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_umul_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} +define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_ssub_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} +define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define { i64, i1 } @test_usub_with_overflow( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] +; CHECK: 3: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 4: +; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { i64, i1 } [[RES]] +; + %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) + ret { i64, i1 } %res +} + +define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32> %b) #0 { +; CHECK-LABEL: define { <4 x i32>, <4 x i1> } @test_sadd_with_overflow_vec( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 +; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 +; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] +; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] +; CHECK: 5: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] +; CHECK-NEXT: unreachable +; CHECK: 6: +; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] +; + %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) + ret { <4 x i32>, <4 x i1> } %res +} + +attributes #0 = { sanitize_memory } +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} +;. diff --git a/llvm/test/Instrumentation/MemorySanitizer/saturating.ll b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll new file mode 100644 index 000000000000..dcd8a080144b --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/saturating.ll @@ -0,0 +1,113 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @test_sadd_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_sadd_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.sadd.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_uadd_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_uadd_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.uadd.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_ssub_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_ssub_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.ssub.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_usub_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_usub_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.usub.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_sshl_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_sshl_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.sshl.sat(i64 %a, i64 %b) + ret i64 %res +} + +define i64 @test_ushl_sat(i64 %a, i64 %b) #0 { +; CHECK-LABEL: define i64 @test_ushl_sat( +; CHECK-SAME: i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]]) +; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret i64 [[RES]] +; + %res = call i64 @llvm.ushl.sat(i64 %a, i64 %b) + ret i64 %res +} + +define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 { +; CHECK-LABEL: define <4 x i32> @test_sadd_sat_vec( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret <4 x i32> [[RES]] +; + %res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b) + ret <4 x i32> %res +} + + +attributes #0 = { sanitize_memory } -- GitLab From 9760872b537ba8e6eee2e68eb81b7d26af5b40e4 Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Wed, 10 Apr 2024 00:22:10 +0000 Subject: [PATCH 344/695] [bazel][libc] Add missing fenv dep for rint test template For 49561181bdc8698aa28ee2a46d2faa4cf6767bbe. --- utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel index 3c43c604316f..e30c8bf023cf 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel @@ -379,6 +379,7 @@ libc_support_library( deps = [ "//libc:__support_fputil_fenv_impl", "//libc:__support_fputil_fp_bits", + "//libc:hdr_fenv_macros", "//libc:hdr_math_macros", "//libc/test/UnitTest:LibcUnitTest", "//libc/test/UnitTest:fp_test_helpers", -- GitLab From 36e25772ddd049c8c742e55fbd2b3c9aaceb7060 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Wed, 10 Apr 2024 10:12:40 +0900 Subject: [PATCH 345/695] clang/test/APINotes/instancetype.m: Clean the cache dir It has been incompatible since #87761 --- clang/test/APINotes/instancetype.m | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/APINotes/instancetype.m b/clang/test/APINotes/instancetype.m index 30339e5386f6..e3c13188ae9f 100644 --- a/clang/test/APINotes/instancetype.m +++ b/clang/test/APINotes/instancetype.m @@ -1,3 +1,4 @@ +// RUN: rm -rf %t // RUN: %clang_cc1 -fmodules -fimplicit-module-maps -fmodules-cache-path=%t/ModulesCache -fapinotes-modules -fsyntax-only -I %S/Inputs/Headers -verify %s @import InstancetypeModule; -- GitLab From 892f01a7437b20f5df3edf53824a53889f733b06 Mon Sep 17 00:00:00 2001 From: Lei Wang Date: Tue, 9 Apr 2024 18:53:09 -0700 Subject: [PATCH 346/695] Remove the assertion to unblock breakages (#88035) as titled. --- .../Transforms/Utils/SampleProfileLoaderBaseImpl.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h b/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h index 581d354fc476..39295d6d81b8 100644 --- a/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h +++ b/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h @@ -140,13 +140,9 @@ public: // be different and result in different checksums. So we should use the // state from the new (available_externally) function, which is saved in its // attribute. - assert((LTOPhase != ThinOrFullLTOPhase::ThinLTOPostLink || - IsAvailableExternallyLinkage || !Desc || - profileIsHashMismatched(*Desc, Samples) == - F.hasFnAttribute("profile-checksum-mismatch")) && - "In post-link, profile checksum matching state doesn't match the " - "internal function's 'profile-checksum-mismatch' attribute."); - (void)LTOPhase; + // TODO: If the function's profile only exists as nested inlinee profile in + // a different module, we don't have the attr mismatch state(unknown), we + // need to fix it later. if (IsAvailableExternallyLinkage || !Desc) return !F.hasFnAttribute("profile-checksum-mismatch"); -- GitLab From ee52add6cb4a6a4ba4beb941c1f2cfa82266e0df Mon Sep 17 00:00:00 2001 From: Shih-Po Hung Date: Wed, 10 Apr 2024 10:08:33 +0800 Subject: [PATCH 347/695] [RISCV][TTI] Implement cost of intrinsic active_lane_mask (#87931) This patch uses the argument type to infer the LMUL cost for the index generation, add, and comparison. --- .../Target/RISCV/RISCVTargetTransformInfo.cpp | 15 +++++++ .../CostModel/RISCV/active_lane_mask.ll | 44 +++++++++---------- 2 files changed, 37 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 55637b8ea47f..58132c1fc431 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -864,6 +864,21 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, } break; } + case Intrinsic::get_active_lane_mask: { + if (ST->hasVInstructions()) { + Type *ExpRetTy = VectorType::get( + ICA.getArgTypes()[0], cast(RetTy)->getElementCount()); + auto LT = getTypeLegalizationCost(ExpRetTy); + + // vid.v v8 // considered hoisted + // vsaddu.vx v8, v8, a0 + // vmsltu.vx v0, v8, a1 + return LT.first * + getRISCVInstructionCost({RISCV::VSADDU_VX, RISCV::VMSLTU_VX}, + LT.second, CostKind); + } + break; + } // TODO: add more intrinsic case Intrinsic::experimental_stepvector: { auto LT = getTypeLegalizationCost(RetTy); diff --git a/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll b/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll index ba62056f5851..7ebe14d98b21 100644 --- a/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll +++ b/llvm/test/Analysis/CostModel/RISCV/active_lane_mask.ll @@ -3,28 +3,28 @@ define void @get_lane_mask() { ; CHECK-LABEL: 'get_lane_mask' -; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %mask_nxv16i1_i64 = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %mask_nxv8i1_i64 = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %mask_nxv4i1_i64 = call @llvm.get.active.lane.mask.nxv4i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %mask_nxv2i1_i64 = call @llvm.get.active.lane.mask.nxv2i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_nxv1i1_i64 = call @llvm.get.active.lane.mask.nxv1i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %mask_nxv16i1_i32 = call @llvm.get.active.lane.mask.nxv16i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %mask_nxv8i1_i32 = call @llvm.get.active.lane.mask.nxv8i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %mask_nxv4i1_i32 = call @llvm.get.active.lane.mask.nxv4i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_nxv2i1_i32 = call @llvm.get.active.lane.mask.nxv2i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_nxv1i1_i32 = call @llvm.get.active.lane.mask.nxv1i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 44 for instruction: %mask_nxv32i1_i64 = call @llvm.get.active.lane.mask.nxv32i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %mask_nxv16i1_i16 = call @llvm.get.active.lane.mask.nxv16i1.i16(i16 undef, i16 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %mask_nxv16i1_i64 = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_nxv8i1_i64 = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_nxv4i1_i64 = call @llvm.get.active.lane.mask.nxv4i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_nxv2i1_i64 = call @llvm.get.active.lane.mask.nxv2i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %mask_nxv1i1_i64 = call @llvm.get.active.lane.mask.nxv1i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_nxv16i1_i32 = call @llvm.get.active.lane.mask.nxv16i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_nxv8i1_i32 = call @llvm.get.active.lane.mask.nxv8i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_nxv4i1_i32 = call @llvm.get.active.lane.mask.nxv4i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %mask_nxv2i1_i32 = call @llvm.get.active.lane.mask.nxv2i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %mask_nxv1i1_i32 = call @llvm.get.active.lane.mask.nxv1i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %mask_nxv32i1_i64 = call @llvm.get.active.lane.mask.nxv32i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_nxv16i1_i16 = call @llvm.get.active.lane.mask.nxv16i1.i16(i16 undef, i16 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; %mask_nxv16i1_i64 = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 undef, i64 undef) -- GitLab From 44c79da3ae90795ca8b252e8a92910eee9d889c0 Mon Sep 17 00:00:00 2001 From: hanbeom Date: Wed, 10 Apr 2024 11:19:09 +0900 Subject: [PATCH 348/695] [InstCombine] Remove shl if we only demand known signbits of shift source (#79014) This patch resolve TODO written in commit: https://github.com/llvm/llvm-project/commit/5909c678831f3a5c1669f6906f777d4ec4532fa1 Proof: https://alive2.llvm.org/ce/z/C3VNoR --- .../InstCombineSimplifyDemanded.cpp | 42 ++++--- .../test/Transforms/InstCombine/shl-demand.ll | 118 ++++++++++++++++++ 2 files changed, 143 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index c691c8b1c55b..6739b8745d74 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -655,25 +655,33 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, } } - // TODO: If we only want bits that already match the signbit then we don't + // We only want bits that already match the signbit then we don't // need to shift. + uint64_t ShiftAmt = SA->getLimitedValue(BitWidth - 1); + if (DemandedMask.countr_zero() >= ShiftAmt) { + if (I->hasNoSignedWrap()) { + unsigned NumHiDemandedBits = BitWidth - DemandedMask.countr_zero(); + unsigned SignBits = + ComputeNumSignBits(I->getOperand(0), Depth + 1, CxtI); + if (SignBits > ShiftAmt && SignBits - ShiftAmt >= NumHiDemandedBits) + return I->getOperand(0); + } - // If we can pre-shift a right-shifted constant to the left without - // losing any high bits amd we don't demand the low bits, then eliminate - // the left-shift: - // (C >> X) << LeftShiftAmtC --> (C << RightShiftAmtC) >> X - uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); - Value *X; - Constant *C; - if (DemandedMask.countr_zero() >= ShiftAmt && - match(I->getOperand(0), m_LShr(m_ImmConstant(C), m_Value(X)))) { - Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt); - Constant *NewC = ConstantFoldBinaryOpOperands(Instruction::Shl, C, - LeftShiftAmtC, DL); - if (ConstantFoldBinaryOpOperands(Instruction::LShr, NewC, LeftShiftAmtC, - DL) == C) { - Instruction *Lshr = BinaryOperator::CreateLShr(NewC, X); - return InsertNewInstWith(Lshr, I->getIterator()); + // If we can pre-shift a right-shifted constant to the left without + // losing any high bits and we don't demand the low bits, then eliminate + // the left-shift: + // (C >> X) << LeftShiftAmtC --> (C << LeftShiftAmtC) >> X + Value *X; + Constant *C; + if (match(I->getOperand(0), m_LShr(m_ImmConstant(C), m_Value(X)))) { + Constant *LeftShiftAmtC = ConstantInt::get(VTy, ShiftAmt); + Constant *NewC = ConstantFoldBinaryOpOperands(Instruction::Shl, C, + LeftShiftAmtC, DL); + if (ConstantFoldBinaryOpOperands(Instruction::LShr, NewC, + LeftShiftAmtC, DL) == C) { + Instruction *Lshr = BinaryOperator::CreateLShr(NewC, X); + return InsertNewInstWith(Lshr, I->getIterator()); + } } } diff --git a/llvm/test/Transforms/InstCombine/shl-demand.ll b/llvm/test/Transforms/InstCombine/shl-demand.ll index 85752890b4b8..26175ebbe153 100644 --- a/llvm/test/Transforms/InstCombine/shl-demand.ll +++ b/llvm/test/Transforms/InstCombine/shl-demand.ll @@ -1,6 +1,124 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -passes=instcombine -S < %s | FileCheck %s + +; If we only want bits that already match the signbit then we don't need to shift. +; https://alive2.llvm.org/ce/z/WJBPVt +define i32 @src_srem_shl_demand_max_signbit(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_max_signbit( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 2 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -2147483648 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 2 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD + %shl = shl i32 %srem, 30 ; shl = SD000000000000000000000000000000 + %mask = and i32 %shl, -2147483648 ; mask = 10000000000000000000000000000000 + ret i32 %mask +} + +define i32 @src_srem_shl_demand_min_signbit(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_min_signbit( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 1073741823 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -2147483648 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 1073741823 ; srem = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD + %shl = shl i32 %srem, 1 ; shl = SDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0 + %mask = and i32 %shl, -2147483648 ; mask = 10000000000000000000000000000000 + ret i32 %mask +} + +define i32 @src_srem_shl_demand_max_mask(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_max_mask( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 2 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -4 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 2 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD + %shl = shl i32 %srem, 1 ; shl = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD0 + %mask = and i32 %shl, -4 ; mask = 11111111111111111111111111111100 + ret i32 %mask +} + +; Negative test - mask demands non-signbit from shift source +define i32 @src_srem_shl_demand_max_signbit_mask_hit_first_demand(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_max_signbit_mask_hit_first_demand( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 4 +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 29 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -1073741824 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 4 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD + %shl = shl i32 %srem, 29 ; shl = SDD00000000000000000000000000000 + %mask = and i32 %shl, -1073741824 ; mask = 11000000000000000000000000000000 + ret i32 %mask +} + +define i32 @src_srem_shl_demand_min_signbit_mask_hit_last_demand(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_min_signbit_mask_hit_last_demand( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 536870912 +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 1 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -1073741822 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 536870912 ; srem = SSSDDDDDDDDDDDDDDDDDDDDDDDDDDDDD + %shl = shl i32 %srem, 1 ; shl = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0 + %mask = and i32 %shl, -1073741822 ; mask = 11000000000000000000000000000010 + ret i32 %mask +} + +define i32 @src_srem_shl_demand_eliminate_signbit(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_eliminate_signbit( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 1073741824 +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 1 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], 2 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 1073741824 ; srem = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD + %shl = shl i32 %srem, 1 ; shl = DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0 + %mask = and i32 %shl, 2 ; mask = 00000000000000000000000000000010 + ret i32 %mask +} + +define i32 @src_srem_shl_demand_max_mask_hit_demand(i32 %a0) { +; CHECK-LABEL: @src_srem_shl_demand_max_mask_hit_demand( +; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 4 +; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 1 +; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -4 +; CHECK-NEXT: ret i32 [[MASK]] +; + %srem = srem i32 %a0, 4 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD + %shl= shl i32 %srem, 1 ; shl = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD0 + %mask = and i32 %shl, -4 ; mask = 11111111111111111111111111111100 + ret i32 %mask +} + +define <2 x i32> @src_srem_shl_mask_vector(<2 x i32> %a0) { +; CHECK-LABEL: @src_srem_shl_mask_vector( +; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], +; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i32> [[SREM]], +; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHL]], +; CHECK-NEXT: ret <2 x i32> [[MASK]] +; + %srem = srem <2 x i32> %a0, + %shl = shl <2 x i32> %srem, + %mask = and <2 x i32> %shl, + ret <2 x i32> %mask +} + +define <2 x i32> @src_srem_shl_mask_vector_nonconstant(<2 x i32> %a0, <2 x i32> %a1) { +; CHECK-LABEL: @src_srem_shl_mask_vector_nonconstant( +; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], +; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[SREM]], [[A1:%.*]] +; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHL]], +; CHECK-NEXT: ret <2 x i32> [[MASK]] +; + %srem = srem <2 x i32> %a0, + %shl = shl <2 x i32> %srem, %a1 + %mask = and <2 x i32> %shl, + ret <2 x i32> %mask +} + define i16 @sext_shl_trunc_same_size(i16 %x, i32 %y) { ; CHECK-LABEL: @sext_shl_trunc_same_size( ; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32 -- GitLab From 1aceee7bb6c4423da73f71aff2004493bdf620d1 Mon Sep 17 00:00:00 2001 From: Lei Wang Date: Tue, 9 Apr 2024 19:25:08 -0700 Subject: [PATCH 349/695] Remove unused variable (#88223) fix the CI --- .../llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h | 5 +---- llvm/lib/Transforms/IPO/SampleProfile.cpp | 2 +- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h b/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h index 39295d6d81b8..7c725a3c1216 100644 --- a/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h +++ b/llvm/include/llvm/Transforms/Utils/SampleProfileLoaderBaseImpl.h @@ -86,12 +86,9 @@ template <> struct IRTraits { // SampleProfileProber. class PseudoProbeManager { DenseMap GUIDToProbeDescMap; - const ThinOrFullLTOPhase LTOPhase; public: - PseudoProbeManager(const Module &M, - ThinOrFullLTOPhase LTOPhase = ThinOrFullLTOPhase::None) - : LTOPhase(LTOPhase) { + PseudoProbeManager(const Module &M) { if (NamedMDNode *FuncInfo = M.getNamedMetadata(PseudoProbeDescMetadataName)) { for (const auto *Operand : FuncInfo->operands()) { diff --git a/llvm/lib/Transforms/IPO/SampleProfile.cpp b/llvm/lib/Transforms/IPO/SampleProfile.cpp index b5f45a252c7b..0b3a6931e779 100644 --- a/llvm/lib/Transforms/IPO/SampleProfile.cpp +++ b/llvm/lib/Transforms/IPO/SampleProfile.cpp @@ -2059,7 +2059,7 @@ bool SampleProfileLoader::doInitialization(Module &M, // Load pseudo probe descriptors for probe-based function samples. if (Reader->profileIsProbeBased()) { - ProbeManager = std::make_unique(M, LTOPhase); + ProbeManager = std::make_unique(M); if (!ProbeManager->moduleIsProbed(M)) { const char *Msg = "Pseudo-probe-based profile requires SampleProfileProbePass"; -- GitLab From e0219f2d53686135b7363450b44877342a960e71 Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Tue, 9 Apr 2024 07:49:40 -0700 Subject: [PATCH 350/695] [lldb] Overwrite existing LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES on apple-linux --- lldb/cmake/caches/Apple-lldb-Linux.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/cmake/caches/Apple-lldb-Linux.cmake b/lldb/cmake/caches/Apple-lldb-Linux.cmake index 9258f01e2ec2..bfa660d8654b 100644 --- a/lldb/cmake/caches/Apple-lldb-Linux.cmake +++ b/lldb/cmake/caches/Apple-lldb-Linux.cmake @@ -1,5 +1,5 @@ include(${CMAKE_CURRENT_LIST_DIR}/Apple-lldb-base.cmake) -set(LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES ON CACHE BOOL "") +set(LLVM_ENABLE_EXPORTED_SYMBOLS_IN_EXECUTABLES ON CACHE BOOL "" FORCE) set(LLVM_DISTRIBUTION_COMPONENTS lldb -- GitLab From 349327f7e73ab7a314ef08c463dd04fcea623150 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Tue, 9 Apr 2024 14:53:10 -0700 Subject: [PATCH 351/695] [ARM64EC] Make intrin.h include arm64intrin.h. Fixes compiling windows.h using clang's intrin.h. --- clang/lib/Headers/intrin.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h index e890dcd7feeb..7eb6dceaabfa 100644 --- a/clang/lib/Headers/intrin.h +++ b/clang/lib/Headers/intrin.h @@ -26,7 +26,7 @@ #include #endif -#if defined(__aarch64__) +#if defined(__aarch64__) || defined(__arm64ec__) #include #endif -- GitLab From 4c6ae8ebb69525118e7fc3cf57908e9de74ebef9 Mon Sep 17 00:00:00 2001 From: Karthika Devi C Date: Wed, 10 Apr 2024 08:21:59 +0530 Subject: [PATCH 352/695] [polly] Fix cppcheck SA comments reported in #82263 (#85749) This patch addresses the (performance )suggestions by checkcpp static analyzer for couple of files. Here we use const reference for the suggested function arguments. Fixes #82263. --- polly/lib/Support/GICHelper.cpp | 15 +++++++-------- polly/lib/Transform/MatmulOptimizer.cpp | 8 ++++---- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/polly/lib/Support/GICHelper.cpp b/polly/lib/Support/GICHelper.cpp index 0e491944c162..04d422cf9946 100644 --- a/polly/lib/Support/GICHelper.cpp +++ b/polly/lib/Support/GICHelper.cpp @@ -83,10 +83,10 @@ APInt polly::APIntFromVal(__isl_take isl_val *Val) { } template -static inline std::string stringFromIslObjInternal(__isl_keep ISLTy *isl_obj, - ISL_CTX_GETTER ctx_getter_fn, - ISL_PRINTER printer_fn, - std::string DefaultValue) { +static inline std::string +stringFromIslObjInternal(__isl_keep ISLTy *isl_obj, + ISL_CTX_GETTER ctx_getter_fn, ISL_PRINTER printer_fn, + const std::string &DefaultValue) { if (!isl_obj) return DefaultValue; isl_ctx *ctx = ctx_getter_fn(isl_obj); @@ -134,12 +134,11 @@ ISL_C_OBJECT_TO_STRING(union_map) ISL_C_OBJECT_TO_STRING(union_pw_aff) ISL_C_OBJECT_TO_STRING(union_pw_multi_aff) -static void replace(std::string &str, const std::string &find, - const std::string &replace) { +static void replace(std::string &str, StringRef find, StringRef replace) { size_t pos = 0; while ((pos = str.find(find, pos)) != std::string::npos) { - str.replace(pos, find.length(), replace); - pos += replace.length(); + str.replace(pos, find.size(), replace); + pos += replace.size(); } } diff --git a/polly/lib/Transform/MatmulOptimizer.cpp b/polly/lib/Transform/MatmulOptimizer.cpp index 51ae5a778e4f..ff1683b2d63c 100644 --- a/polly/lib/Transform/MatmulOptimizer.cpp +++ b/polly/lib/Transform/MatmulOptimizer.cpp @@ -598,7 +598,7 @@ createMacroKernel(isl::schedule_node Node, /// @param MMI Parameters of the matrix multiplication operands. /// @return The size of the widest type of the matrix multiplication operands /// in bytes, including alignment padding. -static uint64_t getMatMulAlignTypeSize(MatMulInfoTy MMI) { +static uint64_t getMatMulAlignTypeSize(const MatMulInfoTy &MMI) { auto *S = MMI.A->getStatement()->getParent(); auto &DL = S->getFunction().getParent()->getDataLayout(); auto ElementSizeA = DL.getTypeAllocSize(MMI.A->getElementType()); @@ -613,7 +613,7 @@ static uint64_t getMatMulAlignTypeSize(MatMulInfoTy MMI) { /// @param MMI Parameters of the matrix multiplication operands. /// @return The size of the widest type of the matrix multiplication operands /// in bits. -static uint64_t getMatMulTypeSize(MatMulInfoTy MMI) { +static uint64_t getMatMulTypeSize(const MatMulInfoTy &MMI) { auto *S = MMI.A->getStatement()->getParent(); auto &DL = S->getFunction().getParent()->getDataLayout(); auto ElementSizeA = DL.getTypeSizeInBits(MMI.A->getElementType()); @@ -635,7 +635,7 @@ static uint64_t getMatMulTypeSize(MatMulInfoTy MMI) { /// @return The structure of type MicroKernelParamsTy. /// @see MicroKernelParamsTy static MicroKernelParamsTy getMicroKernelParams(const TargetTransformInfo *TTI, - MatMulInfoTy MMI) { + const MatMulInfoTy &MMI) { assert(TTI && "The target transform info should be provided."); // Nvec - Number of double-precision floating-point numbers that can be hold @@ -712,7 +712,7 @@ static void getTargetCacheParameters(const llvm::TargetTransformInfo *TTI) { static MacroKernelParamsTy getMacroKernelParams(const llvm::TargetTransformInfo *TTI, const MicroKernelParamsTy &MicroKernelParams, - MatMulInfoTy MMI) { + const MatMulInfoTy &MMI) { getTargetCacheParameters(TTI); // According to www.cs.utexas.edu/users/flame/pubs/TOMS-BLIS-Analytical.pdf, // it requires information about the first two levels of a cache to determine -- GitLab From 71097e927141e278dd92e847e67f636526510a31 Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Tue, 9 Apr 2024 19:53:56 -0700 Subject: [PATCH 353/695] [ARM64EC] Add support for parsing __vectorcall (#87725) MSVC doesn't support generating __vectorcall calls in Arm64EC mode, but it does treat it as a distinct type. The Microsoft STL depends on this functionality. (Not sure if this is intentional.) Add support for parsing the same way as MSVC, and add some checks to ensure we don't try to actually generate code. The error handling in CodeGen is ugly, but I can't think of a better way to do it. --- clang/lib/Basic/Targets/AArch64.cpp | 5 ++++- clang/lib/CodeGen/CGCall.cpp | 6 ++++++ clang/lib/CodeGen/CodeGenModule.cpp | 8 ++++++++ clang/test/CodeGenCXX/arm64ec-vectorcall.cpp | 14 ++++++++++++++ 4 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 clang/test/CodeGenCXX/arm64ec-vectorcall.cpp diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 1569b5e04b77..c8d243a8fb7a 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -1543,10 +1543,13 @@ WindowsARM64TargetInfo::getBuiltinVaListKind() const { TargetInfo::CallingConvCheckResult WindowsARM64TargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { + case CC_X86VectorCall: + if (getTriple().isWindowsArm64EC()) + return CCCR_OK; + return CCCR_Ignore; case CC_X86StdCall: case CC_X86ThisCall: case CC_X86FastCall: - case CC_X86VectorCall: return CCCR_Ignore; case CC_C: case CC_OpenCLKernel: diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index f12765b82693..3f5463a9a70e 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -5591,6 +5591,12 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, /*AttrOnCallSite=*/true, /*IsThunk=*/false); + if (CallingConv == llvm::CallingConv::X86_VectorCall && + getTarget().getTriple().isWindowsArm64EC()) { + CGM.Error(Loc, "__vectorcall calling convention is not currently " + "supported"); + } + if (const FunctionDecl *FD = dyn_cast_or_null(CurFuncDecl)) { if (FD->hasAttr()) // All calls within a strictfp function are marked strictfp diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 00b3bfcaa0bc..75519be8bba0 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -2087,6 +2087,14 @@ void CodeGenModule::SetLLVMFunctionAttributes(GlobalDecl GD, llvm::AttributeList PAL; ConstructAttributeList(F->getName(), Info, GD, PAL, CallingConv, /*AttrOnCallSite=*/false, IsThunk); + if (CallingConv == llvm::CallingConv::X86_VectorCall && + getTarget().getTriple().isWindowsArm64EC()) { + SourceLocation Loc; + if (const Decl *D = GD.getDecl()) + Loc = D->getLocation(); + + Error(Loc, "__vectorcall calling convention is not currently supported"); + } F->setAttributes(PAL); F->setCallingConv(static_cast(CallingConv)); } diff --git a/clang/test/CodeGenCXX/arm64ec-vectorcall.cpp b/clang/test/CodeGenCXX/arm64ec-vectorcall.cpp new file mode 100644 index 000000000000..73d2d6383591 --- /dev/null +++ b/clang/test/CodeGenCXX/arm64ec-vectorcall.cpp @@ -0,0 +1,14 @@ +// RUN: %clang_cc1 -triple arm64ec-windows-msvc -emit-llvm -o - %s -verify + +// ARM64EC doesn't support generating __vectorcall calls... but __vectorcall +// function types need to be distinct from __cdecl function types to support +// compiling the STL. Make sure we only diagnose constructs that actually +// require generating code. +void __vectorcall f1(); +void f2(void __vectorcall p()) {} +void f2(void p()) {} +void __vectorcall (*f3)(); +void __vectorcall f4(); // expected-error {{__vectorcall}} +void __vectorcall f5() { // expected-error {{__vectorcall}} + f4(); // expected-error{{__vectorcall}} +} -- GitLab From 000f2b51633d181bf4a5919fc38cf964a83f2091 Mon Sep 17 00:00:00 2001 From: Longsheng Mou Date: Wed, 10 Apr 2024 10:57:35 +0800 Subject: [PATCH 354/695] [X86_64] fix arg pass error in struct. (#86902) ``` typedef long long t67 __attribute__((aligned (4))); struct s67 { int a; t67 b; }; void f67(struct s67 x) { } ``` When classify: a: Lo = Integer, Hi = NoClass b: Lo = Integer, Hi = NoClass struct S: Lo = Integer, Hi = NoClass ``` define dso_local void @f67(i64 %x.coerce) { ``` In this case, only one i64 register is used when the structure parameter is transferred, which is obviously incorrect.So we need to treat the split case specially. fix https://github.com/llvm/llvm-project/issues/85387. --- clang/lib/CodeGen/Targets/X86.cpp | 5 ++++- clang/test/CodeGen/X86/x86_64-arguments.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/clang/lib/CodeGen/Targets/X86.cpp b/clang/lib/CodeGen/Targets/X86.cpp index c831777699f6..f04db56db335 100644 --- a/clang/lib/CodeGen/Targets/X86.cpp +++ b/clang/lib/CodeGen/Targets/X86.cpp @@ -2106,8 +2106,11 @@ void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase, Class &Lo, postMerge(Size, Lo, Hi); return; } + + bool IsInMemory = + Offset % getContext().getTypeAlign(i->getType().getCanonicalType()); // Note, skip this test for bit-fields, see below. - if (!BitField && Offset % getContext().getTypeAlign(i->getType())) { + if (!BitField && IsInMemory) { Lo = Memory; postMerge(Size, Lo, Hi); return; diff --git a/clang/test/CodeGen/X86/x86_64-arguments.c b/clang/test/CodeGen/X86/x86_64-arguments.c index cf5636cfd518..82845f0a2b31 100644 --- a/clang/test/CodeGen/X86/x86_64-arguments.c +++ b/clang/test/CodeGen/X86/x86_64-arguments.c @@ -533,6 +533,24 @@ typedef float t66 __attribute__((__vector_size__(128), __aligned__(128))); void f66(t66 a0) { } +typedef long long t67 __attribute__((aligned (4))); +struct s67 { + int a; + t67 b; +}; +// CHECK-LABEL: define{{.*}} void @f67(ptr noundef byval(%struct.s67) align 8 %x) +void f67(struct s67 x) { +} + +typedef double t68 __attribute__((aligned (4))); +struct s68 { + int a; + t68 b; +}; +// CHECK-LABEL: define{{.*}} void @f68(ptr noundef byval(%struct.s68) align 8 %x) +void f68(struct s68 x) { +} + /// The synthesized __va_list_tag does not have file/line fields. // CHECK: = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "__va_list_tag", // CHECK-NOT: file: -- GitLab From 58323de2e5ed0fec81ccfe421488d7fb27ecbe38 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Tue, 9 Apr 2024 19:59:36 -0700 Subject: [PATCH 355/695] [clang-format] Correctly annotate braces in macros (#87953) Also fix unit tests and reformat polly. Fixes #86550. --- clang/lib/Format/UnwrappedLineParser.cpp | 20 +++++++++--------- clang/unittests/Format/FormatTest.cpp | 9 +++++++- clang/unittests/Format/TokenAnnotatorTest.cpp | 21 +++++++++++++++---- .../lib/Analysis/ScopDetectionDiagnostic.cpp | 2 +- 4 files changed, 36 insertions(+), 16 deletions(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index af57b1420c6e..c1f7e2874beb 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -538,16 +538,6 @@ void UnwrappedLineParser::calculateBraceTypes(bool ExpectClassBody) { if (Style.Language == FormatStyle::LK_Proto) { ProbablyBracedList = NextTok->isOneOf(tok::comma, tok::r_square); } else { - // Skip NextTok over preprocessor lines, otherwise we may not - // properly diagnose the block as a braced intializer - // if the comma separator appears after the pp directive. - while (NextTok->is(tok::hash)) { - ScopedMacroState MacroState(*Line, Tokens, NextTok); - do { - NextTok = Tokens->getNextToken(); - } while (NextTok->isNot(tok::eof)); - } - // Using OriginalColumn to distinguish between ObjC methods and // binary operators is a bit hacky. bool NextIsObjCMethod = NextTok->isOneOf(tok::plus, tok::minus) && @@ -606,6 +596,16 @@ void UnwrappedLineParser::calculateBraceTypes(bool ExpectClassBody) { NextTok = Tokens->getNextToken(); ProbablyBracedList = NextTok->isNot(tok::l_square); } + + // Cpp macro definition body that is a nonempty braced list or block: + if (IsCpp && Line->InMacroBody && PrevTok != FormatTok && + !FormatTok->Previous && NextTok->is(tok::eof) && + // A statement can end with only `;` (simple statement), a block + // closing brace (compound statement), or `:` (label statement). + // If PrevTok is a block opening brace, Tok ends an empty block. + !PrevTok->isOneOf(tok::semi, BK_Block, tok::colon)) { + ProbablyBracedList = true; + } } if (ProbablyBracedList) { Tok->setBlockKind(BK_BracedInit); diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 71450f433cec..f312a9e21158 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -1865,6 +1865,13 @@ TEST_F(FormatTest, UnderstandsMacros) { verifyFormat("MACRO(co_return##something)"); verifyFormat("#define A x:"); + + verifyFormat("#define Foo(Bar) {#Bar}", "#define Foo(Bar) \\\n" + " { \\\n" + " #Bar \\\n" + " }"); + verifyFormat("#define Foo(Bar) {#Bar}", "#define Foo(Bar) \\\n" + " { #Bar }"); } TEST_F(FormatTest, ShortBlocksInMacrosDontMergeWithCodeAfterMacro) { @@ -11033,7 +11040,7 @@ TEST_F(FormatTest, UnderstandsTemplateParameters) { verifyFormat("some_templated_type"); verifyFormat("#define FOO(typeName, realClass) \\\n" - " { #typeName, foo(new foo(#typeName)) }", + " {#typeName, foo(new foo(#typeName))}", getLLVMStyleWithColumns(60)); } diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index 5ba5e0fbd16f..251e317c7499 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -1933,14 +1933,20 @@ TEST_F(TokenAnnotatorTest, UnderstandHashInMacro) { " #Bar \\\n" " }"); ASSERT_EQ(Tokens.size(), 11u) << Tokens; - EXPECT_BRACE_KIND(Tokens[6], BK_Block); - EXPECT_BRACE_KIND(Tokens[9], BK_Block); + EXPECT_BRACE_KIND(Tokens[6], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[9], BK_BracedInit); Tokens = annotate("#define Foo(Bar) \\\n" " { #Bar }"); ASSERT_EQ(Tokens.size(), 11u) << Tokens; - EXPECT_BRACE_KIND(Tokens[6], BK_Block); - EXPECT_BRACE_KIND(Tokens[9], BK_Block); + EXPECT_BRACE_KIND(Tokens[6], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[9], BK_BracedInit); + + Tokens = annotate("#define FOO(typeName, realClass) \\\n" + " {#typeName, foo(new foo(#typeName))}"); + ASSERT_EQ(Tokens.size(), 29u) << Tokens; + EXPECT_BRACE_KIND(Tokens[8], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[27], BK_BracedInit); } TEST_F(TokenAnnotatorTest, UnderstandsAttributeMacros) { @@ -2822,6 +2828,13 @@ TEST_F(TokenAnnotatorTest, BraceKind) { EXPECT_BRACE_KIND(Tokens[0], BK_Block); EXPECT_BRACE_KIND(Tokens[7], BK_BracedInit); EXPECT_BRACE_KIND(Tokens[21], BK_BracedInit); + + Tokens = + annotate("#define SCOP_STAT(NAME, DESC) \\\n" + " {\"polly\", #NAME, \"Number of rejected regions: \" DESC}"); + ASSERT_EQ(Tokens.size(), 18u) << Tokens; + EXPECT_BRACE_KIND(Tokens[8], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[16], BK_BracedInit); } TEST_F(TokenAnnotatorTest, StreamOperator) { diff --git a/polly/lib/Analysis/ScopDetectionDiagnostic.cpp b/polly/lib/Analysis/ScopDetectionDiagnostic.cpp index 30fbd17c78bf..d2fbcf731985 100644 --- a/polly/lib/Analysis/ScopDetectionDiagnostic.cpp +++ b/polly/lib/Analysis/ScopDetectionDiagnostic.cpp @@ -45,7 +45,7 @@ using namespace llvm; #define DEBUG_TYPE "polly-detect" #define SCOP_STAT(NAME, DESC) \ - { "polly-detect", "NAME", "Number of rejected regions: " DESC } + {"polly-detect", "NAME", "Number of rejected regions: " DESC} static Statistic RejectStatistics[] = { SCOP_STAT(CFG, ""), -- GitLab From bcf849b1e5faea405cfbbd4bc848048651055b25 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Tue, 9 Apr 2024 20:00:03 -0700 Subject: [PATCH 356/695] [clang-format] instanceof is a keyword only in Java/JavaScript (#88085) Fixes #87907. --- clang/lib/Format/TokenAnnotator.cpp | 3 ++- clang/unittests/Format/TokenAnnotatorTest.cpp | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 9abd4282103b..628f70417866 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -2354,7 +2354,8 @@ private: // Line.MightBeFunctionDecl can only be true after the parentheses of a // function declaration have been found. In this case, 'Current' is a // trailing token of this declaration and thus cannot be a name. - if (Current.is(Keywords.kw_instanceof)) { + if ((Style.isJavaScript() || Style.Language == FormatStyle::LK_Java) && + Current.is(Keywords.kw_instanceof)) { Current.setType(TT_BinaryOperator); } else if (isStartOfName(Current) && (!Line.MightBeFunctionDecl || Current.NestingLevel != 0)) { diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index 251e317c7499..c3153cf6b16f 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -1769,6 +1769,10 @@ TEST_F(TokenAnnotatorTest, UnderstandsFunctionDeclarationNames) { EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown); EXPECT_TOKEN(Tokens[4], tok::l_paren, TT_FunctionTypeLParen); + Tokens = annotate("void instanceof();"); + ASSERT_EQ(Tokens.size(), 6u); + EXPECT_TOKEN(Tokens[1], tok::identifier, TT_FunctionDeclarationName); + Tokens = annotate("int iso_time(time_t);"); ASSERT_EQ(Tokens.size(), 7u) << Tokens; EXPECT_TOKEN(Tokens[1], tok::identifier, TT_FunctionDeclarationName); -- GitLab From 8dc006ea4008c1af298e56c4db6fffe2a40a2ba9 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Wed, 10 Apr 2024 11:02:55 +0800 Subject: [PATCH 357/695] [RISCV] Make EmitToStreamer return whether Inst is compressed This is helpful to reduce calls of `RISCVRVC::compress` in #77337. Reviewers: asb, lukel97, topperc Reviewed By: topperc Pull Request: https://github.com/llvm/llvm-project/pull/88120 --- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 5bf594c0b5ea..9982a73ee914 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -80,7 +80,8 @@ public: bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; - void EmitToStreamer(MCStreamer &S, const MCInst &Inst); + // Returns whether Inst is compressed. + bool EmitToStreamer(MCStreamer &S, const MCInst &Inst); bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI); @@ -180,12 +181,13 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM, SM.recordStatepoint(*MILabel, MI); } -void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { +bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst; bool Res = RISCVRVC::compress(CInst, Inst, *STI); if (Res) ++RISCVNumInstrsCompressed; AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst); + return Res; } // Simple pseudo-instructions have their lowering (with expansion to real -- GitLab From 289a2c380e47d64a1e626259c53fc8c7d6c2be66 Mon Sep 17 00:00:00 2001 From: Nhat Nguyen Date: Tue, 9 Apr 2024 23:38:23 -0400 Subject: [PATCH 358/695] [libc] implement ioctl (#85890) This PR is to work on the issue #85275 --- libc/config/linux/aarch64/entrypoints.txt | 3 ++ libc/config/linux/riscv/entrypoints.txt | 3 ++ libc/config/linux/x86_64/entrypoints.txt | 3 ++ libc/spec/linux.td | 18 ++++++++++ libc/src/sys/CMakeLists.txt | 1 + libc/src/sys/ioctl/CMakeLists.txt | 12 +++++++ libc/src/sys/ioctl/ioctl.h | 17 +++++++++ libc/src/sys/ioctl/linux/CMakeLists.txt | 13 +++++++ libc/src/sys/ioctl/linux/ioctl.cpp | 38 ++++++++++++++++++++ libc/test/src/sys/ioctl/CMakeLists.txt | 3 ++ libc/test/src/sys/ioctl/linux/CMakeLists.txt | 14 ++++++++ libc/test/src/sys/ioctl/linux/ioctl_test.cpp | 27 ++++++++++++++ 12 files changed, 152 insertions(+) create mode 100644 libc/src/sys/ioctl/CMakeLists.txt create mode 100644 libc/src/sys/ioctl/ioctl.h create mode 100644 libc/src/sys/ioctl/linux/CMakeLists.txt create mode 100644 libc/src/sys/ioctl/linux/ioctl.cpp create mode 100644 libc/test/src/sys/ioctl/CMakeLists.txt create mode 100644 libc/test/src/sys/ioctl/linux/CMakeLists.txt create mode 100644 libc/test/src/sys/ioctl/linux/ioctl_test.cpp diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index f5f5c437685a..5649e3ca29f9 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -204,6 +204,9 @@ set(TARGET_LIBC_ENTRYPOINTS #libc.src.stdio.scanf #libc.src.stdio.fscanf + # sys/ioctl.h entrypoints + libc.src.sys.ioctl.ioctl + # sys/mman.h entrypoints libc.src.sys.mman.madvise libc.src.sys.mman.mmap diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index 71289789158f..6c719320b084 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -209,6 +209,9 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.stdio.scanf libc.src.stdio.fscanf + # sys/ioctl.h entrypoints + libc.src.sys.ioctl.ioctl + # sys/mman.h entrypoints libc.src.sys.mman.madvise libc.src.sys.mman.mmap diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index 6bb53cb76220..5880ad55b71c 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -221,6 +221,9 @@ set(TARGET_LIBC_ENTRYPOINTS # https://github.com/llvm/llvm-project/issues/80060 # libc.src.sys.epoll.epoll_pwait2 + # sys/ioctl.h entrypoints + libc.src.sys.ioctl.ioctl + # sys/mman.h entrypoints libc.src.sys.mman.madvise libc.src.sys.mman.mmap diff --git a/libc/spec/linux.td b/libc/spec/linux.td index f91f55ddac78..6e9b64f5a6b4 100644 --- a/libc/spec/linux.td +++ b/libc/spec/linux.td @@ -79,6 +79,24 @@ def Linux : StandardSpec<"Linux"> { [] // Functions >; + HeaderSpec SysIoctl = HeaderSpec< + "sys/ioctl.h", + [Macro<"MAP_ANONYMOUS">], + [], // Types + [], // Enumerations + [ + FunctionSpec< + "ioctl", + RetValSpec, + [ + ArgSpec, + ArgSpec, + ArgSpec, + ] + >, + ] // Functions + >; + HeaderSpec SysMMan = HeaderSpec< "sys/mman.h", [Macro<"MAP_ANONYMOUS">], diff --git a/libc/src/sys/CMakeLists.txt b/libc/src/sys/CMakeLists.txt index adc666b94202..ac54df35284a 100644 --- a/libc/src/sys/CMakeLists.txt +++ b/libc/src/sys/CMakeLists.txt @@ -1,5 +1,6 @@ add_subdirectory(auxv) add_subdirectory(epoll) +add_subdirectory(ioctl) add_subdirectory(mman) add_subdirectory(random) add_subdirectory(resource) diff --git a/libc/src/sys/ioctl/CMakeLists.txt b/libc/src/sys/ioctl/CMakeLists.txt new file mode 100644 index 000000000000..4b50c278c787 --- /dev/null +++ b/libc/src/sys/ioctl/CMakeLists.txt @@ -0,0 +1,12 @@ +if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) + add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) +endif() + +add_entrypoint_object( + ioctl + ALIAS + DEPENDS + .${LIBC_TARGET_OS}.ioctl +) + + diff --git a/libc/src/sys/ioctl/ioctl.h b/libc/src/sys/ioctl/ioctl.h new file mode 100644 index 000000000000..8365678276a4 --- /dev/null +++ b/libc/src/sys/ioctl/ioctl.h @@ -0,0 +1,17 @@ +//===-- Implementation header for mmap function -----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_SYS_IOCTL_IOCTL_H +#define LLVM_LIBC_SRC_SYS_IOCTL_IOCTL_H +namespace LIBC_NAMESPACE { + +int ioctl(int fd, unsigned long request, ...); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_SYS_IOCTL_IOCTL_H diff --git a/libc/src/sys/ioctl/linux/CMakeLists.txt b/libc/src/sys/ioctl/linux/CMakeLists.txt new file mode 100644 index 000000000000..8a23505d4e9d --- /dev/null +++ b/libc/src/sys/ioctl/linux/CMakeLists.txt @@ -0,0 +1,13 @@ +add_entrypoint_object( + ioctl + SRCS + ioctl.cpp + HDRS + ../ioctl.h + DEPENDS + libc.include.sys_ioctl + libc.include.sys_syscall + libc.src.__support.OSUtil.osutil + libc.src.errno.errno +) + diff --git a/libc/src/sys/ioctl/linux/ioctl.cpp b/libc/src/sys/ioctl/linux/ioctl.cpp new file mode 100644 index 000000000000..6c8ff54dc2ae --- /dev/null +++ b/libc/src/sys/ioctl/linux/ioctl.cpp @@ -0,0 +1,38 @@ +//===---------- Linux implementation of the POSIX ioctl function --------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/sys/ioctl/ioctl.h" + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. +#include "src/__support/common.h" +#include "src/errno/libc_errno.h" +#include +#include // For syscall numbers. + +namespace LIBC_NAMESPACE { + +// This function is currently linux only. It has to be refactored suitably if +// madvise is to be supported on non-linux operating systems also. +LLVM_LIBC_FUNCTION(int, ioctl, (int fd, unsigned long request, ...)) { + va_list ptr_to_memory; + va_start(ptr_to_memory, 1); + va_arg(ptr_to_memory, void *) int ret = + LIBC_NAMESPACE::syscall_impl(SYS_ioctl, fd, request, ptr_to_memory); + va_end(ptr_to_memory); + + // A negative return value indicates an error with the magnitude of the + // value being the error code. + if (ret < 0) { + libc_errno = -ret; + return -1; + } + + return 0; +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/test/src/sys/ioctl/CMakeLists.txt b/libc/test/src/sys/ioctl/CMakeLists.txt new file mode 100644 index 000000000000..b4bbe81c92ff --- /dev/null +++ b/libc/test/src/sys/ioctl/CMakeLists.txt @@ -0,0 +1,3 @@ +if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) + add_subdirectory(${LIBC_TARGET_OS}) +endif() diff --git a/libc/test/src/sys/ioctl/linux/CMakeLists.txt b/libc/test/src/sys/ioctl/linux/CMakeLists.txt new file mode 100644 index 000000000000..93e68975c4e1 --- /dev/null +++ b/libc/test/src/sys/ioctl/linux/CMakeLists.txt @@ -0,0 +1,14 @@ +add_custom_target(libc_sys_ioctl_unittests) + +add_libc_unittest( + ioctl_test + SUITE + libc_sys_ioctl_unittests + SRCS + ioctl_test.cpp + DEPENDS + libc.include.sys_ioctl + libc.src.errno.errno + libc.test.errno_setter_matcher +) + diff --git a/libc/test/src/sys/ioctl/linux/ioctl_test.cpp b/libc/test/src/sys/ioctl/linux/ioctl_test.cpp new file mode 100644 index 000000000000..3de3eff3e8d4 --- /dev/null +++ b/libc/test/src/sys/ioctl/linux/ioctl_test.cpp @@ -0,0 +1,27 @@ +//===-- Unittests for ioctl -----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/OSUtil/syscall.h" // For internal syscall function. +#include "src/errno/libc_errno.h" +#include "src/sys/ioctl/ioctl.h" +#include "test/UnitTest/ErrnoSetterMatcher.h" +#include "test/UnitTest/LibcTest.h" +#include "test/UnitTest/Test.h" + +#include +#include + +using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; +using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; + +TEST(LlvmLibcIoctlTest, InvalidFileDescriptor) { + int fd = 10; + unsigned long request = 10; + int res = LIBC_NAMESPACE::ioctl(fd, 10, NULL); + EXPECT_THAT(res, Fails(EBADF, -1)); +} -- GitLab From 87e6f87fe7e343eb656e9b49d30cbb065c086651 Mon Sep 17 00:00:00 2001 From: Connor Sughrue <55301806+cpsughrue@users.noreply.github.com> Date: Tue, 9 Apr 2024 23:41:18 -0400 Subject: [PATCH 359/695] [llvm][Support] Improvements to ListeningSocket functionality and documentation (#84710) Improvements include * Enable `ListeningSocket::accept` to timeout after a specified amount of time or block indefinitely * Enable `ListeningSocket::createUnix` to handle instances where the target socket address already exists and differentiate between situations where the existing file does and does not already have a bound socket * Doxygen comments Functionality added for the module build daemon --------- Co-authored-by: Michael Spencer --- llvm/include/llvm/Support/raw_socket_stream.h | 86 +++++- llvm/lib/Support/raw_socket_stream.cpp | 253 +++++++++++++----- .../Support/raw_socket_stream_test.cpp | 73 ++++- 3 files changed, 339 insertions(+), 73 deletions(-) diff --git a/llvm/include/llvm/Support/raw_socket_stream.h b/llvm/include/llvm/Support/raw_socket_stream.h index c219792d8246..bddd47eb75e1 100644 --- a/llvm/include/llvm/Support/raw_socket_stream.h +++ b/llvm/include/llvm/Support/raw_socket_stream.h @@ -17,12 +17,17 @@ #include "llvm/Support/Threading.h" #include "llvm/Support/raw_ostream.h" +#include +#include + namespace llvm { class raw_socket_stream; -// Make sure that calls to WSAStartup and WSACleanup are balanced. #ifdef _WIN32 +/// Ensures proper initialization and cleanup of winsock resources +/// +/// Make sure that calls to WSAStartup and WSACleanup are balanced. class WSABalancer { public: WSABalancer(); @@ -30,22 +35,87 @@ public: }; #endif // _WIN32 +/// Manages a passive (i.e., listening) UNIX domain socket +/// +/// The ListeningSocket class encapsulates a UNIX domain socket that can listen +/// and accept incoming connections. ListeningSocket is portable and supports +/// Windows builds begining with Insider Build 17063. ListeningSocket is +/// designed for server-side operations, working alongside \p raw_socket_streams +/// that function as client connections. +/// +/// Usage example: +/// \code{.cpp} +/// std::string Path = "/path/to/socket" +/// Expected S = ListeningSocket::createUnix(Path); +/// +/// if (S) { +/// Expected> connection = S->accept(); +/// if (connection) { +/// // Use the accepted raw_socket_stream for communication. +/// } +/// } +/// \endcode +/// class ListeningSocket { - int FD; - std::string SocketPath; - ListeningSocket(int SocketFD, StringRef SocketPath); + + std::atomic FD; + std::string SocketPath; // Not modified after construction + + /// If a seperate thread calls ListeningSocket::shutdown, the ListeningSocket + /// file descriptor (FD) could be closed while ::poll is waiting for it to be + /// ready to perform a I/O operations. ::poll will continue to block even + /// after FD is closed so use a self-pipe mechanism to get ::poll to return + int PipeFD[2]; // Not modified after construction other then move constructor + + ListeningSocket(int SocketFD, StringRef SocketPath, int PipeFD[2]); + #ifdef _WIN32 WSABalancer _; #endif // _WIN32 public: + ~ListeningSocket(); + ListeningSocket(ListeningSocket &&LS); + ListeningSocket(const ListeningSocket &LS) = delete; + ListeningSocket &operator=(const ListeningSocket &) = delete; + + /// Closes the FD, unlinks the socket file, and writes to PipeFD. + /// + /// After the construction of the ListeningSocket, shutdown is signal safe if + /// it is called during the lifetime of the object. shutdown can be called + /// concurrently with ListeningSocket::accept as writing to PipeFD will cause + /// a blocking call to ::poll to return. + /// + /// Once shutdown is called there is no way to reinitialize ListeningSocket. + void shutdown(); + + /// Accepts an incoming connection on the listening socket. This method can + /// optionally either block until a connection is available or timeout after a + /// specified amount of time has passed. By default the method will block + /// until the socket has recieved a connection. + /// + /// \param Timeout An optional timeout duration in milliseconds. Setting + /// Timeout to -1 causes accept to block indefinitely + /// + Expected> + accept(std::chrono::milliseconds Timeout = std::chrono::milliseconds(-1)); + + /// Creates a listening socket bound to the specified file system path. + /// Handles the socket creation, binding, and immediately starts listening for + /// incoming connections. + /// + /// \param SocketPath The file system path where the socket will be created + /// \param MaxBacklog The max number of connections in a socket's backlog + /// static Expected createUnix( StringRef SocketPath, int MaxBacklog = llvm::hardware_concurrency().compute_thread_count()); - Expected> accept(); - ListeningSocket(ListeningSocket &&LS); - ~ListeningSocket(); }; + +//===----------------------------------------------------------------------===// +// raw_socket_stream +//===----------------------------------------------------------------------===// + class raw_socket_stream : public raw_fd_stream { uint64_t current_pos() const override { return 0; } #ifdef _WIN32 @@ -54,7 +124,7 @@ class raw_socket_stream : public raw_fd_stream { public: raw_socket_stream(int SocketFD); - /// Create a \p raw_socket_stream connected to the Unix domain socket at \p + /// Create a \p raw_socket_stream connected to the UNIX domain socket at \p /// SocketPath. static Expected> createConnectedUnix(StringRef SocketPath); diff --git a/llvm/lib/Support/raw_socket_stream.cpp b/llvm/lib/Support/raw_socket_stream.cpp index afb0ed11b2c2..1dcf6352f2cc 100644 --- a/llvm/lib/Support/raw_socket_stream.cpp +++ b/llvm/lib/Support/raw_socket_stream.cpp @@ -14,8 +14,14 @@ #include "llvm/Support/raw_socket_stream.h" #include "llvm/Config/config.h" #include "llvm/Support/Error.h" +#include "llvm/Support/FileSystem.h" + +#include +#include +#include #ifndef _WIN32 +#include #include #include #else @@ -45,7 +51,6 @@ WSABalancer::WSABalancer() { } WSABalancer::~WSABalancer() { WSACleanup(); } - #endif // _WIN32 static std::error_code getLastSocketErrorCode() { @@ -56,104 +61,231 @@ static std::error_code getLastSocketErrorCode() { #endif } -ListeningSocket::ListeningSocket(int SocketFD, StringRef SocketPath) - : FD(SocketFD), SocketPath(SocketPath) {} +static sockaddr_un setSocketAddr(StringRef SocketPath) { + struct sockaddr_un Addr; + memset(&Addr, 0, sizeof(Addr)); + Addr.sun_family = AF_UNIX; + strncpy(Addr.sun_path, SocketPath.str().c_str(), sizeof(Addr.sun_path) - 1); + return Addr; +} + +static Expected getSocketFD(StringRef SocketPath) { +#ifdef _WIN32 + SOCKET Socket = socket(AF_UNIX, SOCK_STREAM, 0); + if (Socket == INVALID_SOCKET) { +#else + int Socket = socket(AF_UNIX, SOCK_STREAM, 0); + if (Socket == -1) { +#endif // _WIN32 + return llvm::make_error(getLastSocketErrorCode(), + "Create socket failed"); + } + + struct sockaddr_un Addr = setSocketAddr(SocketPath); + if (::connect(Socket, (struct sockaddr *)&Addr, sizeof(Addr)) == -1) + return llvm::make_error(getLastSocketErrorCode(), + "Connect socket failed"); + +#ifdef _WIN32 + return _open_osfhandle(Socket, 0); +#else + return Socket; +#endif // _WIN32 +} + +ListeningSocket::ListeningSocket(int SocketFD, StringRef SocketPath, + int PipeFD[2]) + : FD(SocketFD), SocketPath(SocketPath), PipeFD{PipeFD[0], PipeFD[1]} {} ListeningSocket::ListeningSocket(ListeningSocket &&LS) - : FD(LS.FD), SocketPath(LS.SocketPath) { + : FD(LS.FD.load()), SocketPath(LS.SocketPath), + PipeFD{LS.PipeFD[0], LS.PipeFD[1]} { + LS.FD = -1; + LS.SocketPath.clear(); + LS.PipeFD[0] = -1; + LS.PipeFD[1] = -1; } Expected ListeningSocket::createUnix(StringRef SocketPath, int MaxBacklog) { + // Handle instances where the target socket address already exists and + // differentiate between a preexisting file with and without a bound socket + // + // ::bind will return std::errc:address_in_use if a file at the socket address + // already exists (e.g., the file was not properly unlinked due to a crash) + // even if another socket has not yet binded to that address + if (llvm::sys::fs::exists(SocketPath)) { + Expected MaybeFD = getSocketFD(SocketPath); + if (!MaybeFD) { + + // Regardless of the error, notify the caller that a file already exists + // at the desired socket address and that there is no bound socket at that + // address. The file must be removed before ::bind can use the address + consumeError(MaybeFD.takeError()); + return llvm::make_error( + std::make_error_code(std::errc::file_exists), + "Socket address unavailable"); + } + ::close(std::move(*MaybeFD)); + + // Notify caller that the provided socket address already has a bound socket + return llvm::make_error( + std::make_error_code(std::errc::address_in_use), + "Socket address unavailable"); + } + #ifdef _WIN32 WSABalancer _; - SOCKET MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); - if (MaybeWinsocket == INVALID_SOCKET) { + SOCKET Socket = socket(AF_UNIX, SOCK_STREAM, 0); + if (Socket == INVALID_SOCKET) #else - int MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); - if (MaybeWinsocket == -1) { + int Socket = socket(AF_UNIX, SOCK_STREAM, 0); + if (Socket == -1) #endif return llvm::make_error(getLastSocketErrorCode(), "socket create failed"); - } - struct sockaddr_un Addr; - memset(&Addr, 0, sizeof(Addr)); - Addr.sun_family = AF_UNIX; - strncpy(Addr.sun_path, SocketPath.str().c_str(), sizeof(Addr.sun_path) - 1); - - if (bind(MaybeWinsocket, (struct sockaddr *)&Addr, sizeof(Addr)) == -1) { - std::error_code Err = getLastSocketErrorCode(); - if (Err == std::errc::address_in_use) - ::close(MaybeWinsocket); - return llvm::make_error(Err, "Bind error"); + struct sockaddr_un Addr = setSocketAddr(SocketPath); + if (::bind(Socket, (struct sockaddr *)&Addr, sizeof(Addr)) == -1) { + // Grab error code from call to ::bind before calling ::close + std::error_code EC = getLastSocketErrorCode(); + ::close(Socket); + return llvm::make_error(EC, "Bind error"); } - if (listen(MaybeWinsocket, MaxBacklog) == -1) { + + // Mark socket as passive so incoming connections can be accepted + if (::listen(Socket, MaxBacklog) == -1) return llvm::make_error(getLastSocketErrorCode(), "Listen error"); - } - int UnixSocket; + + int PipeFD[2]; #ifdef _WIN32 - UnixSocket = _open_osfhandle(MaybeWinsocket, 0); + // Reserve 1 byte for the pipe and use default textmode + if (::_pipe(PipeFD, 1, 0) == -1) #else - UnixSocket = MaybeWinsocket; + if (::pipe(PipeFD) == -1) +#endif // _WIN32 + return llvm::make_error(getLastSocketErrorCode(), + "pipe failed"); + +#ifdef _WIN32 + return ListeningSocket{_open_osfhandle(Socket, 0), SocketPath, PipeFD}; +#else + return ListeningSocket{Socket, SocketPath, PipeFD}; #endif // _WIN32 - return ListeningSocket{UnixSocket, SocketPath}; } -Expected> ListeningSocket::accept() { - int AcceptFD; +Expected> +ListeningSocket::accept(std::chrono::milliseconds Timeout) { + + struct pollfd FDs[2]; + FDs[0].events = POLLIN; #ifdef _WIN32 SOCKET WinServerSock = _get_osfhandle(FD); + FDs[0].fd = WinServerSock; +#else + FDs[0].fd = FD; +#endif + FDs[1].events = POLLIN; + FDs[1].fd = PipeFD[0]; + + // Keep track of how much time has passed in case poll is interupted by a + // signal and needs to be recalled + int RemainingTime = Timeout.count(); + std::chrono::milliseconds ElapsedTime = std::chrono::milliseconds(0); + int PollStatus = -1; + + while (PollStatus == -1 && (Timeout.count() == -1 || ElapsedTime < Timeout)) { + if (Timeout.count() != -1) + RemainingTime -= ElapsedTime.count(); + + auto Start = std::chrono::steady_clock::now(); +#ifdef _WIN32 + PollStatus = WSAPoll(FDs, 2, RemainingTime); + if (PollStatus == SOCKET_ERROR) { +#else + PollStatus = ::poll(FDs, 2, RemainingTime); + if (PollStatus == -1) { +#endif + // Ignore error if caused by interupting signal + std::error_code PollErrCode = getLastSocketErrorCode(); + if (PollErrCode != std::errc::interrupted) + return llvm::make_error(PollErrCode, "FD poll failed"); + } + + if (PollStatus == 0) + return llvm::make_error( + std::make_error_code(std::errc::timed_out), + "No client requests within timeout window"); + + if (FDs[0].revents & POLLNVAL) + return llvm::make_error( + std::make_error_code(std::errc::bad_file_descriptor), + "File descriptor closed by another thread"); + + if (FDs[1].revents & POLLIN) + return llvm::make_error( + std::make_error_code(std::errc::operation_canceled), + "Accept canceled"); + + auto Stop = std::chrono::steady_clock::now(); + ElapsedTime += + std::chrono::duration_cast(Stop - Start); + } + + int AcceptFD; +#ifdef _WIN32 SOCKET WinAcceptSock = ::accept(WinServerSock, NULL, NULL); AcceptFD = _open_osfhandle(WinAcceptSock, 0); #else AcceptFD = ::accept(FD, NULL, NULL); -#endif //_WIN32 +#endif + if (AcceptFD == -1) return llvm::make_error(getLastSocketErrorCode(), - "Accept failed"); + "Socket accept failed"); return std::make_unique(AcceptFD); } -ListeningSocket::~ListeningSocket() { - if (FD == -1) +void ListeningSocket::shutdown() { + int ObservedFD = FD.load(); + + if (ObservedFD == -1) return; - ::close(FD); - unlink(SocketPath.c_str()); -} -static Expected GetSocketFD(StringRef SocketPath) { -#ifdef _WIN32 - SOCKET MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); - if (MaybeWinsocket == INVALID_SOCKET) { -#else - int MaybeWinsocket = socket(AF_UNIX, SOCK_STREAM, 0); - if (MaybeWinsocket == -1) { -#endif // _WIN32 - return llvm::make_error(getLastSocketErrorCode(), - "Create socket failed"); - } + // If FD equals ObservedFD set FD to -1; If FD doesn't equal ObservedFD then + // another thread is responsible for shutdown so return + if (!FD.compare_exchange_strong(ObservedFD, -1)) + return; - struct sockaddr_un Addr; - memset(&Addr, 0, sizeof(Addr)); - Addr.sun_family = AF_UNIX; - strncpy(Addr.sun_path, SocketPath.str().c_str(), sizeof(Addr.sun_path) - 1); + ::close(ObservedFD); + ::unlink(SocketPath.c_str()); - int status = connect(MaybeWinsocket, (struct sockaddr *)&Addr, sizeof(Addr)); - if (status == -1) { - return llvm::make_error(getLastSocketErrorCode(), - "Connect socket failed"); - } -#ifdef _WIN32 - return _open_osfhandle(MaybeWinsocket, 0); -#else - return MaybeWinsocket; -#endif // _WIN32 + // Ensure ::poll returns if shutdown is called by a seperate thread + char Byte = 'A'; + ::write(PipeFD[1], &Byte, 1); } +ListeningSocket::~ListeningSocket() { + shutdown(); + + // Close the pipe's FDs in the destructor instead of within + // ListeningSocket::shutdown to avoid unnecessary synchronization issues that + // would occur as PipeFD's values would have to be changed to -1 + // + // The move constructor sets PipeFD to -1 + if (PipeFD[0] != -1) + ::close(PipeFD[0]); + if (PipeFD[1] != -1) + ::close(PipeFD[1]); +} + +//===----------------------------------------------------------------------===// +// raw_socket_stream +//===----------------------------------------------------------------------===// + raw_socket_stream::raw_socket_stream(int SocketFD) : raw_fd_stream(SocketFD, true) {} @@ -162,11 +294,10 @@ raw_socket_stream::createConnectedUnix(StringRef SocketPath) { #ifdef _WIN32 WSABalancer _; #endif // _WIN32 - Expected FD = GetSocketFD(SocketPath); + Expected FD = getSocketFD(SocketPath); if (!FD) return FD.takeError(); return std::make_unique(*FD); } raw_socket_stream::~raw_socket_stream() {} - diff --git a/llvm/unittests/Support/raw_socket_stream_test.cpp b/llvm/unittests/Support/raw_socket_stream_test.cpp index 6903862e5403..a8536228666d 100644 --- a/llvm/unittests/Support/raw_socket_stream_test.cpp +++ b/llvm/unittests/Support/raw_socket_stream_test.cpp @@ -9,6 +9,7 @@ #include #include #include +#include #ifdef _WIN32 #include "llvm/Support/Windows/WindowsSupport.h" @@ -32,10 +33,10 @@ TEST(raw_socket_streamTest, CLIENT_TO_SERVER_AND_SERVER_TO_CLIENT) { GTEST_SKIP(); SmallString<100> SocketPath; - llvm::sys::fs::createUniquePath("test_raw_socket_stream.sock", SocketPath, - true); + llvm::sys::fs::createUniquePath("client_server_comms.sock", SocketPath, true); - char Bytes[8]; + // Make sure socket file does not exist. May still be there from the last test + std::remove(SocketPath.c_str()); Expected MaybeServerListener = ListeningSocket::createUnix(SocketPath); @@ -58,6 +59,7 @@ TEST(raw_socket_streamTest, CLIENT_TO_SERVER_AND_SERVER_TO_CLIENT) { Client << "01234567"; Client.flush(); + char Bytes[8]; ssize_t BytesRead = Server.read(Bytes, 8); std::string string(Bytes, 8); @@ -65,4 +67,67 @@ TEST(raw_socket_streamTest, CLIENT_TO_SERVER_AND_SERVER_TO_CLIENT) { ASSERT_EQ(8, BytesRead); ASSERT_EQ("01234567", string); } -} // namespace \ No newline at end of file + +TEST(raw_socket_streamTest, TIMEOUT_PROVIDED) { + if (!hasUnixSocketSupport()) + GTEST_SKIP(); + + SmallString<100> SocketPath; + llvm::sys::fs::createUniquePath("timout_provided.sock", SocketPath, true); + + // Make sure socket file does not exist. May still be there from the last test + std::remove(SocketPath.c_str()); + + Expected MaybeServerListener = + ListeningSocket::createUnix(SocketPath); + ASSERT_THAT_EXPECTED(MaybeServerListener, llvm::Succeeded()); + ListeningSocket ServerListener = std::move(*MaybeServerListener); + + std::chrono::milliseconds Timeout = std::chrono::milliseconds(100); + Expected> MaybeServer = + ServerListener.accept(Timeout); + + ASSERT_THAT_EXPECTED(MaybeServer, Failed()); + llvm::Error Err = MaybeServer.takeError(); + llvm::handleAllErrors(std::move(Err), [&](const llvm::StringError &SE) { + std::error_code EC = SE.convertToErrorCode(); + ASSERT_EQ(EC, std::errc::timed_out); + }); +} + +TEST(raw_socket_streamTest, FILE_DESCRIPTOR_CLOSED) { + if (!hasUnixSocketSupport()) + GTEST_SKIP(); + + SmallString<100> SocketPath; + llvm::sys::fs::createUniquePath("fd_closed.sock", SocketPath, true); + + // Make sure socket file does not exist. May still be there from the last test + std::remove(SocketPath.c_str()); + + Expected MaybeServerListener = + ListeningSocket::createUnix(SocketPath); + ASSERT_THAT_EXPECTED(MaybeServerListener, llvm::Succeeded()); + ListeningSocket ServerListener = std::move(*MaybeServerListener); + + // Create a separate thread to close the socket after a delay. Simulates a + // signal handler calling ServerListener::shutdown + std::thread CloseThread([&]() { + std::this_thread::sleep_for(std::chrono::milliseconds(500)); + ServerListener.shutdown(); + }); + + Expected> MaybeServer = + ServerListener.accept(); + + // Wait for the CloseThread to finish + CloseThread.join(); + + ASSERT_THAT_EXPECTED(MaybeServer, Failed()); + llvm::Error Err = MaybeServer.takeError(); + llvm::handleAllErrors(std::move(Err), [&](const llvm::StringError &SE) { + std::error_code EC = SE.convertToErrorCode(); + ASSERT_EQ(EC, std::errc::operation_canceled); + }); +} +} // namespace -- GitLab From 3c2feab7d152b7f161b4adaecef4ec81f038a23e Mon Sep 17 00:00:00 2001 From: lntue <35648136+lntue@users.noreply.github.com> Date: Tue, 9 Apr 2024 23:48:09 -0400 Subject: [PATCH 360/695] Revert "[libc] implement ioctl" (#88226) Reverts llvm/llvm-project#85890 This fails in full build mode: https://lab.llvm.org/buildbot/#/builders/163/builds/54478/steps/4/logs/stdio --- libc/config/linux/aarch64/entrypoints.txt | 3 -- libc/config/linux/riscv/entrypoints.txt | 3 -- libc/config/linux/x86_64/entrypoints.txt | 3 -- libc/spec/linux.td | 18 ---------- libc/src/sys/CMakeLists.txt | 1 - libc/src/sys/ioctl/CMakeLists.txt | 12 ------- libc/src/sys/ioctl/ioctl.h | 17 --------- libc/src/sys/ioctl/linux/CMakeLists.txt | 13 ------- libc/src/sys/ioctl/linux/ioctl.cpp | 38 -------------------- libc/test/src/sys/ioctl/CMakeLists.txt | 3 -- libc/test/src/sys/ioctl/linux/CMakeLists.txt | 14 -------- libc/test/src/sys/ioctl/linux/ioctl_test.cpp | 27 -------------- 12 files changed, 152 deletions(-) delete mode 100644 libc/src/sys/ioctl/CMakeLists.txt delete mode 100644 libc/src/sys/ioctl/ioctl.h delete mode 100644 libc/src/sys/ioctl/linux/CMakeLists.txt delete mode 100644 libc/src/sys/ioctl/linux/ioctl.cpp delete mode 100644 libc/test/src/sys/ioctl/CMakeLists.txt delete mode 100644 libc/test/src/sys/ioctl/linux/CMakeLists.txt delete mode 100644 libc/test/src/sys/ioctl/linux/ioctl_test.cpp diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index 5649e3ca29f9..f5f5c437685a 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -204,9 +204,6 @@ set(TARGET_LIBC_ENTRYPOINTS #libc.src.stdio.scanf #libc.src.stdio.fscanf - # sys/ioctl.h entrypoints - libc.src.sys.ioctl.ioctl - # sys/mman.h entrypoints libc.src.sys.mman.madvise libc.src.sys.mman.mmap diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index 6c719320b084..71289789158f 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -209,9 +209,6 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.stdio.scanf libc.src.stdio.fscanf - # sys/ioctl.h entrypoints - libc.src.sys.ioctl.ioctl - # sys/mman.h entrypoints libc.src.sys.mman.madvise libc.src.sys.mman.mmap diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index 5880ad55b71c..6bb53cb76220 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -221,9 +221,6 @@ set(TARGET_LIBC_ENTRYPOINTS # https://github.com/llvm/llvm-project/issues/80060 # libc.src.sys.epoll.epoll_pwait2 - # sys/ioctl.h entrypoints - libc.src.sys.ioctl.ioctl - # sys/mman.h entrypoints libc.src.sys.mman.madvise libc.src.sys.mman.mmap diff --git a/libc/spec/linux.td b/libc/spec/linux.td index 6e9b64f5a6b4..f91f55ddac78 100644 --- a/libc/spec/linux.td +++ b/libc/spec/linux.td @@ -79,24 +79,6 @@ def Linux : StandardSpec<"Linux"> { [] // Functions >; - HeaderSpec SysIoctl = HeaderSpec< - "sys/ioctl.h", - [Macro<"MAP_ANONYMOUS">], - [], // Types - [], // Enumerations - [ - FunctionSpec< - "ioctl", - RetValSpec, - [ - ArgSpec, - ArgSpec, - ArgSpec, - ] - >, - ] // Functions - >; - HeaderSpec SysMMan = HeaderSpec< "sys/mman.h", [Macro<"MAP_ANONYMOUS">], diff --git a/libc/src/sys/CMakeLists.txt b/libc/src/sys/CMakeLists.txt index ac54df35284a..adc666b94202 100644 --- a/libc/src/sys/CMakeLists.txt +++ b/libc/src/sys/CMakeLists.txt @@ -1,6 +1,5 @@ add_subdirectory(auxv) add_subdirectory(epoll) -add_subdirectory(ioctl) add_subdirectory(mman) add_subdirectory(random) add_subdirectory(resource) diff --git a/libc/src/sys/ioctl/CMakeLists.txt b/libc/src/sys/ioctl/CMakeLists.txt deleted file mode 100644 index 4b50c278c787..000000000000 --- a/libc/src/sys/ioctl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) - add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) -endif() - -add_entrypoint_object( - ioctl - ALIAS - DEPENDS - .${LIBC_TARGET_OS}.ioctl -) - - diff --git a/libc/src/sys/ioctl/ioctl.h b/libc/src/sys/ioctl/ioctl.h deleted file mode 100644 index 8365678276a4..000000000000 --- a/libc/src/sys/ioctl/ioctl.h +++ /dev/null @@ -1,17 +0,0 @@ -//===-- Implementation header for mmap function -----------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIBC_SRC_SYS_IOCTL_IOCTL_H -#define LLVM_LIBC_SRC_SYS_IOCTL_IOCTL_H -namespace LIBC_NAMESPACE { - -int ioctl(int fd, unsigned long request, ...); - -} // namespace LIBC_NAMESPACE - -#endif // LLVM_LIBC_SRC_SYS_IOCTL_IOCTL_H diff --git a/libc/src/sys/ioctl/linux/CMakeLists.txt b/libc/src/sys/ioctl/linux/CMakeLists.txt deleted file mode 100644 index 8a23505d4e9d..000000000000 --- a/libc/src/sys/ioctl/linux/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -add_entrypoint_object( - ioctl - SRCS - ioctl.cpp - HDRS - ../ioctl.h - DEPENDS - libc.include.sys_ioctl - libc.include.sys_syscall - libc.src.__support.OSUtil.osutil - libc.src.errno.errno -) - diff --git a/libc/src/sys/ioctl/linux/ioctl.cpp b/libc/src/sys/ioctl/linux/ioctl.cpp deleted file mode 100644 index 6c8ff54dc2ae..000000000000 --- a/libc/src/sys/ioctl/linux/ioctl.cpp +++ /dev/null @@ -1,38 +0,0 @@ -//===---------- Linux implementation of the POSIX ioctl function --------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "src/sys/ioctl/ioctl.h" - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. -#include "src/__support/common.h" -#include "src/errno/libc_errno.h" -#include -#include // For syscall numbers. - -namespace LIBC_NAMESPACE { - -// This function is currently linux only. It has to be refactored suitably if -// madvise is to be supported on non-linux operating systems also. -LLVM_LIBC_FUNCTION(int, ioctl, (int fd, unsigned long request, ...)) { - va_list ptr_to_memory; - va_start(ptr_to_memory, 1); - va_arg(ptr_to_memory, void *) int ret = - LIBC_NAMESPACE::syscall_impl(SYS_ioctl, fd, request, ptr_to_memory); - va_end(ptr_to_memory); - - // A negative return value indicates an error with the magnitude of the - // value being the error code. - if (ret < 0) { - libc_errno = -ret; - return -1; - } - - return 0; -} - -} // namespace LIBC_NAMESPACE diff --git a/libc/test/src/sys/ioctl/CMakeLists.txt b/libc/test/src/sys/ioctl/CMakeLists.txt deleted file mode 100644 index b4bbe81c92ff..000000000000 --- a/libc/test/src/sys/ioctl/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) - add_subdirectory(${LIBC_TARGET_OS}) -endif() diff --git a/libc/test/src/sys/ioctl/linux/CMakeLists.txt b/libc/test/src/sys/ioctl/linux/CMakeLists.txt deleted file mode 100644 index 93e68975c4e1..000000000000 --- a/libc/test/src/sys/ioctl/linux/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -add_custom_target(libc_sys_ioctl_unittests) - -add_libc_unittest( - ioctl_test - SUITE - libc_sys_ioctl_unittests - SRCS - ioctl_test.cpp - DEPENDS - libc.include.sys_ioctl - libc.src.errno.errno - libc.test.errno_setter_matcher -) - diff --git a/libc/test/src/sys/ioctl/linux/ioctl_test.cpp b/libc/test/src/sys/ioctl/linux/ioctl_test.cpp deleted file mode 100644 index 3de3eff3e8d4..000000000000 --- a/libc/test/src/sys/ioctl/linux/ioctl_test.cpp +++ /dev/null @@ -1,27 +0,0 @@ -//===-- Unittests for ioctl -----------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "src/__support/OSUtil/syscall.h" // For internal syscall function. -#include "src/errno/libc_errno.h" -#include "src/sys/ioctl/ioctl.h" -#include "test/UnitTest/ErrnoSetterMatcher.h" -#include "test/UnitTest/LibcTest.h" -#include "test/UnitTest/Test.h" - -#include -#include - -using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; -using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; - -TEST(LlvmLibcIoctlTest, InvalidFileDescriptor) { - int fd = 10; - unsigned long request = 10; - int res = LIBC_NAMESPACE::ioctl(fd, 10, NULL); - EXPECT_THAT(res, Fails(EBADF, -1)); -} -- GitLab From 84a5332a68f2b6cb6f48b9483e50d3f821f17119 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Fri, 22 Mar 2024 12:29:30 -0500 Subject: [PATCH 361/695] [X86] Add tests for `uitofp nneg` -> `sitofp`; NFC --- llvm/test/CodeGen/X86/uint_to_fp.ll | 70 +++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/llvm/test/CodeGen/X86/uint_to_fp.ll b/llvm/test/CodeGen/X86/uint_to_fp.ll index d8e0b61ed199..8b9dfedb8da0 100644 --- a/llvm/test/CodeGen/X86/uint_to_fp.ll +++ b/llvm/test/CodeGen/X86/uint_to_fp.ll @@ -25,3 +25,73 @@ entry: store float %1, ptr %y ret void } + +define float @test_without_nneg(i32 %x) nounwind { +; X86-LABEL: test_without_nneg: +; X86: ## %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: cvtsd2ss %xmm0, %xmm0 +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl +; +; X64-LABEL: test_without_nneg: +; X64: ## %bb.0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: cvtsi2ss %rax, %xmm0 +; X64-NEXT: retq + %r = uitofp i32 %x to float + ret float %r +} + +define float @test_with_nneg(i32 %x) nounwind { +; X86-LABEL: test_with_nneg: +; X86: ## %bb.0: +; X86-NEXT: pushl %eax +; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: cvtsd2ss %xmm0, %xmm0 +; X86-NEXT: movss %xmm0, (%esp) +; X86-NEXT: flds (%esp) +; X86-NEXT: popl %eax +; X86-NEXT: retl +; +; X64-LABEL: test_with_nneg: +; X64: ## %bb.0: +; X64-NEXT: movl %edi, %eax +; X64-NEXT: cvtsi2ss %rax, %xmm0 +; X64-NEXT: retq + %r = uitofp nneg i32 %x to float + ret float %r +} + +define <4 x float> @test_with_nneg_vec(<4 x i32> %x) nounwind { +; X86-LABEL: test_with_nneg_vec: +; X86: ## %bb.0: +; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] +; X86-NEXT: pand %xmm0, %xmm1 +; X86-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 +; X86-NEXT: psrld $16, %xmm0 +; X86-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: addps %xmm1, %xmm0 +; X86-NEXT: retl +; +; X64-LABEL: test_with_nneg_vec: +; X64: ## %bb.0: +; X64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] +; X64-NEXT: pand %xmm0, %xmm1 +; X64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; X64-NEXT: psrld $16, %xmm0 +; X64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-NEXT: addps %xmm1, %xmm0 +; X64-NEXT: retq + %r = uitofp nneg <4 x i32> %x to <4 x float> + ret <4 x float> %r +} -- GitLab From 70136389788b90c2e6bbaef5ad8bb0285d460068 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 27 Mar 2024 13:07:46 -0500 Subject: [PATCH 362/695] [DAG] Add support for `nneg` flag with `uitofp` Copy `nneg` flag when building `UINT_TO_FP` from `uitofp` and use `nneg` flag in the one place we transform `UINT_TO_FP` -> `SINT_TO_FP` if the operand is non-negative. --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 4ba27157ec1c..3f69f7ad5447 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -3882,7 +3882,11 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) { SDValue N = getValue(I.getOperand(0)); EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), I.getType()); - setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N)); + SDNodeFlags Flags; + if (auto *PNI = dyn_cast(&I)) + Flags.setNonNeg(PNI->hasNonNeg()); + + setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N, Flags)); } void SelectionDAGBuilder::visitSIToFP(const User &I) { -- GitLab From 6c40d463c28e7a6843bea9f6d838cd89e586cbe8 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Fri, 22 Mar 2024 11:42:02 -0500 Subject: [PATCH 363/695] [X86] Use `nneg` flag when trying to convert `uitofp` -> `sitofp` Closes #86694 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 3 ++- llvm/test/CodeGen/X86/uint_to_fp.ll | 24 ++++-------------------- 2 files changed, 6 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5405c2921e51..010f9c30ab40 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -54126,7 +54126,8 @@ static SDValue combineUIntToFP(SDNode *N, SelectionDAG &DAG, // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform // the optimization here. - if (DAG.SignBitIsZero(Op0)) { + SDNodeFlags Flags = N->getFlags(); + if (Flags.hasNonNeg() || DAG.SignBitIsZero(Op0)) { if (IsStrict) return DAG.getNode(ISD::STRICT_SINT_TO_FP, SDLoc(N), {VT, MVT::Other}, {N->getOperand(0), Op0}); diff --git a/llvm/test/CodeGen/X86/uint_to_fp.ll b/llvm/test/CodeGen/X86/uint_to_fp.ll index 8b9dfedb8da0..8c8cbb151974 100644 --- a/llvm/test/CodeGen/X86/uint_to_fp.ll +++ b/llvm/test/CodeGen/X86/uint_to_fp.ll @@ -52,10 +52,7 @@ define float @test_with_nneg(i32 %x) nounwind { ; X86-LABEL: test_with_nneg: ; X86: ## %bb.0: ; X86-NEXT: pushl %eax -; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero -; X86-NEXT: orpd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: subsd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: cvtsd2ss %xmm0, %xmm0 +; X86-NEXT: cvtsi2ssl {{[0-9]+}}(%esp), %xmm0 ; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: flds (%esp) ; X86-NEXT: popl %eax @@ -63,8 +60,7 @@ define float @test_with_nneg(i32 %x) nounwind { ; ; X64-LABEL: test_with_nneg: ; X64: ## %bb.0: -; X64-NEXT: movl %edi, %eax -; X64-NEXT: cvtsi2ss %rax, %xmm0 +; X64-NEXT: cvtsi2ss %edi, %xmm0 ; X64-NEXT: retq %r = uitofp nneg i32 %x to float ret float %r @@ -73,24 +69,12 @@ define float @test_with_nneg(i32 %x) nounwind { define <4 x float> @test_with_nneg_vec(<4 x i32> %x) nounwind { ; X86-LABEL: test_with_nneg_vec: ; X86: ## %bb.0: -; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] -; X86-NEXT: pand %xmm0, %xmm1 -; X86-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1 -; X86-NEXT: psrld $16, %xmm0 -; X86-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: addps %xmm1, %xmm0 +; X86-NEXT: cvtdq2ps %xmm0, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: test_with_nneg_vec: ; X64: ## %bb.0: -; X64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] -; X64-NEXT: pand %xmm0, %xmm1 -; X64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; X64-NEXT: psrld $16, %xmm0 -; X64-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; X64-NEXT: subps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; X64-NEXT: addps %xmm1, %xmm0 +; X64-NEXT: cvtdq2ps %xmm0, %xmm0 ; X64-NEXT: retq %r = uitofp nneg <4 x i32> %x to <4 x float> ret <4 x float> %r -- GitLab From 817c832e72f0df3efe1ddd804283c8c89b78639f Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Wed, 10 Apr 2024 08:21:18 +0400 Subject: [PATCH 364/695] [clang] Improve source location in binary type traits diagnostics (#88097) This patch takes advantage of a recent NFC change that refactored `EvaluateBinaryTypeTrait()` to accept `TypeSourceInfo` instead of `QualType` c7db450e5c1a83ea768765dcdedfd50f3358d418. Before: ``` test2.cpp:105:55: error: variable length arrays are not supported in '__is_layout_compatible' 105 | static_assert(!__is_layout_compatible(int[n], int[n])); | ^ test2.cpp:125:76: error: incomplete type 'CStructIncomplete' where a complete type is required 125 | static_assert(__is_layout_compatible(CStructIncomplete, CStructIncomplete)); | ^ ``` After: ``` test2.cpp:105:41: error: variable length arrays are not supported in '__is_layout_compatible' 105 | static_assert(!__is_layout_compatible(int[n], int[n])); | ^ test2.cpp:125:40: error: incomplete type 'CStructIncomplete' where a complete type is required 125 | static_assert(__is_layout_compatible(CStructIncomplete, CStructIncomplete)); | ^ ``` --- clang/lib/Sema/SemaExprCXX.cpp | 34 +++++++++++++++++++----------- clang/test/SemaCXX/type-traits.cpp | 1 + 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 80c01b14379c..9822477260e5 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -5895,7 +5895,8 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI return false; if (Self.RequireCompleteType( - KeyLoc, RhsT, diag::err_incomplete_type_used_in_type_trait_expr)) + Rhs->getTypeLoc().getBeginLoc(), RhsT, + diag::err_incomplete_type_used_in_type_trait_expr)) return false; return BaseInterface->isSuperClassOf(DerivedInterface); @@ -5918,8 +5919,9 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI // If Base and Derived are class types and are different types // (ignoring possible cv-qualifiers) then Derived shall be a // complete type. - if (Self.RequireCompleteType(KeyLoc, RhsT, - diag::err_incomplete_type_used_in_type_trait_expr)) + if (Self.RequireCompleteType( + Rhs->getTypeLoc().getBeginLoc(), RhsT, + diag::err_incomplete_type_used_in_type_trait_expr)) return false; return cast(rhsRecord->getDecl()) @@ -5971,7 +5973,8 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI return LhsT->isVoidType(); // A function definition requires a complete, non-abstract return type. - if (!Self.isCompleteType(KeyLoc, RhsT) || Self.isAbstractType(KeyLoc, RhsT)) + if (!Self.isCompleteType(Rhs->getTypeLoc().getBeginLoc(), RhsT) || + Self.isAbstractType(Rhs->getTypeLoc().getBeginLoc(), RhsT)) return false; // Compute the result of add_rvalue_reference. @@ -6021,12 +6024,14 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI // For both, T and U shall be complete types, (possibly cv-qualified) // void, or arrays of unknown bound. if (!LhsT->isVoidType() && !LhsT->isIncompleteArrayType() && - Self.RequireCompleteType(KeyLoc, LhsT, - diag::err_incomplete_type_used_in_type_trait_expr)) + Self.RequireCompleteType( + Lhs->getTypeLoc().getBeginLoc(), LhsT, + diag::err_incomplete_type_used_in_type_trait_expr)) return false; if (!RhsT->isVoidType() && !RhsT->isIncompleteArrayType() && - Self.RequireCompleteType(KeyLoc, RhsT, - diag::err_incomplete_type_used_in_type_trait_expr)) + Self.RequireCompleteType( + Rhs->getTypeLoc().getBeginLoc(), RhsT, + diag::err_incomplete_type_used_in_type_trait_expr)) return false; // cv void is never assignable. @@ -6081,12 +6086,17 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI } case BTT_IsLayoutCompatible: { if (!LhsT->isVoidType() && !LhsT->isIncompleteArrayType()) - Self.RequireCompleteType(KeyLoc, LhsT, diag::err_incomplete_type); + Self.RequireCompleteType(Lhs->getTypeLoc().getBeginLoc(), LhsT, + diag::err_incomplete_type); if (!RhsT->isVoidType() && !RhsT->isIncompleteArrayType()) - Self.RequireCompleteType(KeyLoc, RhsT, diag::err_incomplete_type); + Self.RequireCompleteType(Rhs->getTypeLoc().getBeginLoc(), RhsT, + diag::err_incomplete_type); - if (LhsT->isVariableArrayType() || RhsT->isVariableArrayType()) - Self.Diag(KeyLoc, diag::err_vla_unsupported) + if (LhsT->isVariableArrayType()) + Self.Diag(Lhs->getTypeLoc().getBeginLoc(), diag::err_vla_unsupported) + << 1 << tok::kw___is_layout_compatible; + if (RhsT->isVariableArrayType()) + Self.Diag(Rhs->getTypeLoc().getBeginLoc(), diag::err_vla_unsupported) << 1 << tok::kw___is_layout_compatible; return Self.IsLayoutCompatible(LhsT, RhsT); } diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index e29763714341..421d3007d27f 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -1759,6 +1759,7 @@ void is_layout_compatible(int n) // expected-error@-1 {{variable length arrays are not supported in '__is_layout_compatible'}} static_assert(!__is_layout_compatible(int[n], int[n])); // expected-error@-1 {{variable length arrays are not supported in '__is_layout_compatible'}} + // expected-error@-2 {{variable length arrays are not supported in '__is_layout_compatible'}} static_assert(__is_layout_compatible(int&, int&)); static_assert(!__is_layout_compatible(int&, char&)); static_assert(__is_layout_compatible(void(int), void(int))); -- GitLab From b0662a7a7d6d7a4a5339b95d3a20a53390636716 Mon Sep 17 00:00:00 2001 From: Congzhe Date: Wed, 10 Apr 2024 00:28:21 -0400 Subject: [PATCH 365/695] [CodeMoverUtils] Enhance CodeMoverUtils to sink an entire BB (#87857) When moving an entire basic block after `InsertPoint`, currently we check each instruction whether their users are dominated by `InsertPoint`, however, this can be improved such that even a user is not dominated by `InsertPoint`, as long as it appears as a subsequent instruction in the same BB, it is safe to move. This patch is similar to commit 751be2a064f119af74c7b9b1e52bc904d8aa114d that enhanced hoisting an entire BB, and this patch enhances sinking an entire BB. Please refer to the added functionality in test case `llvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp` that was not supported without this patch. --- llvm/lib/Transforms/Utils/CodeMoverUtils.cpp | 17 +++++++++++++++-- .../Transforms/Utils/CodeMoverUtilsTest.cpp | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp b/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp index 6a2dae5bab68..ac106e4aa2a3 100644 --- a/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp +++ b/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp @@ -336,9 +336,22 @@ bool llvm::isSafeToMoveBefore(Instruction &I, Instruction &InsertPoint, if (isReachedBefore(&I, &InsertPoint, &DT, PDT)) for (const Use &U : I.uses()) - if (auto *UserInst = dyn_cast(U.getUser())) - if (UserInst != &InsertPoint && !DT.dominates(&InsertPoint, U)) + if (auto *UserInst = dyn_cast(U.getUser())) { + // If InsertPoint is in a BB that comes after I, then we cannot move if + // I is used in the terminator of the current BB. + if (I.getParent() == InsertPoint.getParent() && + UserInst == I.getParent()->getTerminator()) return false; + if (UserInst != &InsertPoint && !DT.dominates(&InsertPoint, U)) { + // If UserInst is an instruction that appears later in the same BB as + // I, then it is okay to move since I will still be available when + // UserInst is executed. + if (CheckForEntireBlock && I.getParent() == UserInst->getParent() && + DT.dominates(&I, UserInst)) + continue; + return false; + } + } if (isReachedBefore(&InsertPoint, &I, &DT, PDT)) for (const Value *Op : I.operands()) if (auto *OpInst = dyn_cast(Op)) { diff --git a/llvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp b/llvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp index 8554d1a33cad..dbc1e2152785 100644 --- a/llvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp +++ b/llvm/unittests/Transforms/Utils/CodeMoverUtilsTest.cpp @@ -673,6 +673,11 @@ TEST(CodeMoverUtils, IsSafeToMoveTest4) { // Can move as %add2 and %sub2 are control flow equivalent, // although %add2 does not strictly dominate %sub2. EXPECT_TRUE(isSafeToMoveBefore(*SubInst2, *AddInst2, DT, &PDT, &DI)); + + BasicBlock *BB0 = getBasicBlockByName(F, "if.then.first"); + BasicBlock *BB1 = getBasicBlockByName(F, "if.then.second"); + EXPECT_TRUE( + isSafeToMoveBefore(*BB0, *BB1->getTerminator(), DT, &PDT, &DI)); }); } -- GitLab From ee284d2da0720dc21191d6f545504cbfcf5dcbcf Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 9 Apr 2024 21:32:37 -0700 Subject: [PATCH 366/695] [ELF] Avoid make. NFC --- lld/ELF/SyntheticSections.cpp | 14 ++++++++------ lld/ELF/SyntheticSections.h | 4 +++- lld/ELF/Writer.cpp | 8 +++++--- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index 4427a1200868..550659464a44 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -2872,7 +2872,8 @@ createSymbols( } // Returns a newly-created .gdb_index section. -template GdbIndexSection *GdbIndexSection::create() { +template +std::unique_ptr GdbIndexSection::create() { llvm::TimeTraceScope timeScope("Create gdb index"); // Collect InputFiles with .debug_info. See the comment in @@ -2918,7 +2919,7 @@ template GdbIndexSection *GdbIndexSection::create() { nameAttrs[i] = readPubNamesAndTypes(dobj, chunks[i].compilationUnits); }); - auto *ret = make(); + auto ret = std::make_unique(); ret->chunks = std::move(chunks); std::tie(ret->symbols, ret->size) = createSymbols(nameAttrs, ret->chunks); @@ -3860,6 +3861,7 @@ void InStruct::reset() { ppc32Got2.reset(); ibtPlt.reset(); relaPlt.reset(); + gdbIndex.reset(); shStrTab.reset(); strTab.reset(); symTab.reset(); @@ -3986,10 +3988,10 @@ InStruct elf::in; std::vector elf::partitions; Partition *elf::mainPart; -template GdbIndexSection *GdbIndexSection::create(); -template GdbIndexSection *GdbIndexSection::create(); -template GdbIndexSection *GdbIndexSection::create(); -template GdbIndexSection *GdbIndexSection::create(); +template std::unique_ptr GdbIndexSection::create(); +template std::unique_ptr GdbIndexSection::create(); +template std::unique_ptr GdbIndexSection::create(); +template std::unique_ptr GdbIndexSection::create(); template void elf::splitSections(); template void elf::splitSections(); diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index 7490fb61fb6f..68b4cdb1dde0 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -822,7 +822,7 @@ public: }; GdbIndexSection(); - template static GdbIndexSection *create(); + template static std::unique_ptr create(); void writeTo(uint8_t *buf) override; size_t getSize() const override { return size; } bool isNeeded() const override; @@ -1359,6 +1359,8 @@ struct InStruct { std::unique_ptr ppc32Got2; std::unique_ptr ibtPlt; std::unique_ptr relaPlt; + // Non-SHF_ALLOC sections + std::unique_ptr gdbIndex; std::unique_ptr shStrTab; std::unique_ptr strTab; std::unique_ptr symTab; diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index fc9084f40044..021b9bb0d5e2 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -541,9 +541,6 @@ template void elf::createSyntheticSections() { in.got->hasGotOffRel = true; } - if (config->gdbIndex) - add(*GdbIndexSection::create()); - // We always need to add rel[a].plt to output if it has entries. // Even for static linking it can contain R_[*]_IRELATIVE relocations. in.relaPlt = std::make_unique>( @@ -568,6 +565,11 @@ template void elf::createSyntheticSections() { if (config->andFeatures || !ctx.aarch64PauthAbiCoreInfo.empty()) add(*make()); + if (config->gdbIndex) { + in.gdbIndex = GdbIndexSection::create(); + add(*in.gdbIndex); + } + // .note.GNU-stack is always added when we are creating a re-linkable // object file. Other linkers are using the presence of this marker // section to control the executable-ness of the stack area, but that -- GitLab From 1fda1776e32b5582bfcfcbd8094f3c280d936cec Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Wed, 10 Apr 2024 07:50:17 +0200 Subject: [PATCH 367/695] [libc++][chrono] Adds the sys_info class. (#85619) Adds the sys_info class and time_zone::get_info(). The code still has a few quirks and has not been optimized for performance yet. The returned sys_info is compared against the output of the zdump tool in the test giving confidence the implementation is correct. Implements parts of: - P0355 Extending to Calendars and Time Zones Implements: - LWGXXXX The sys_info range should be affected by save --- libcxx/docs/Status/Cxx2cIssues.csv | 1 + libcxx/include/CMakeLists.txt | 1 + libcxx/include/__chrono/sys_info.h | 51 + libcxx/include/__chrono/time_zone.h | 11 + libcxx/include/chrono | 13 + libcxx/include/libcxx.imp | 1 + libcxx/include/module.modulemap | 3 + libcxx/modules/std/chrono.inc | 2 + libcxx/src/include/tzdb/time_zone_private.h | 11 +- libcxx/src/include/tzdb/types_private.h | 15 +- libcxx/src/time_zone.cpp | 865 +++++++++++ libcxx/src/tzdb.cpp | 2 +- ...rono.nodiscard_extensions.compile.pass.cpp | 1 + .../chrono.nodiscard_extensions.verify.cpp | 2 + .../get_info.sys_time.pass.cpp | 199 +++ .../get_info.sys_time.rule_selection.pass.cpp | 185 +++ .../test/libcxx/transitive_includes/cxx23.csv | 1 - .../test/libcxx/transitive_includes/cxx26.csv | 1 - .../sys_info.members.pass.cpp | 48 + .../get_info.sys_time.pass.cpp | 1374 +++++++++++++++++ .../time.zone.members/sys_info.zdump.pass.cpp | 129 ++ libcxx/utils/libcxx/test/features.py | 6 + 22 files changed, 2916 insertions(+), 6 deletions(-) create mode 100644 libcxx/include/__chrono/sys_info.h create mode 100644 libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp create mode 100644 libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.rule_selection.pass.cpp create mode 100644 libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/sys_info.members.pass.cpp create mode 100644 libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp create mode 100644 libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/sys_info.zdump.pass.cpp diff --git a/libcxx/docs/Status/Cxx2cIssues.csv b/libcxx/docs/Status/Cxx2cIssues.csv index b402fb835bc1..008f7418ab9c 100644 --- a/libcxx/docs/Status/Cxx2cIssues.csv +++ b/libcxx/docs/Status/Cxx2cIssues.csv @@ -63,4 +63,5 @@ "`4054 `__","Repeating a ``repeat_view`` should repeat the view","Tokyo March 2024","","","|ranges|" "","","","","","" "`3343 `__","Ordering of calls to ``unlock()`` and ``notify_all()`` in Effects element of ``notify_all_at_thread_exit()`` should be reversed","Not Yet Adopted","|Complete|","16.0","" +"XXXX","","The sys_info range should be affected by save","Not Yet Adopted","|Complete|","19.0" "","","","","","" diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index 3cbca9ff4bd1..a4a58a787ee9 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -291,6 +291,7 @@ set(files __chrono/parser_std_format_spec.h __chrono/statically_widen.h __chrono/steady_clock.h + __chrono/sys_info.h __chrono/system_clock.h __chrono/time_point.h __chrono/time_zone.h diff --git a/libcxx/include/__chrono/sys_info.h b/libcxx/include/__chrono/sys_info.h new file mode 100644 index 000000000000..794d22f2ccc1 --- /dev/null +++ b/libcxx/include/__chrono/sys_info.h @@ -0,0 +1,51 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// For information see https://libcxx.llvm.org/DesignDocs/TimeZone.html + +#ifndef _LIBCPP___CHRONO_SYS_INFO_H +#define _LIBCPP___CHRONO_SYS_INFO_H + +#include +// Enable the contents of the header only when libc++ was built with experimental features enabled. +#if !defined(_LIBCPP_HAS_NO_INCOMPLETE_TZDB) + +# include <__chrono/duration.h> +# include <__chrono/system_clock.h> +# include <__chrono/time_point.h> +# include <__config> +# include + +# if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +# endif + +_LIBCPP_BEGIN_NAMESPACE_STD + +# if _LIBCPP_STD_VER >= 20 + +namespace chrono { + +struct sys_info { + sys_seconds begin; + sys_seconds end; + seconds offset; + minutes save; + string abbrev; +}; + +} // namespace chrono + +# endif //_LIBCPP_STD_VER >= 20 + +_LIBCPP_END_NAMESPACE_STD + +#endif // !defined(_LIBCPP_HAS_NO_INCOMPLETE_TZDB) + +#endif // _LIBCPP___CHRONO_SYS_INFO_H diff --git a/libcxx/include/__chrono/time_zone.h b/libcxx/include/__chrono/time_zone.h index 7d97327a6c8e..8e30034b799a 100644 --- a/libcxx/include/__chrono/time_zone.h +++ b/libcxx/include/__chrono/time_zone.h @@ -16,6 +16,9 @@ // Enable the contents of the header only when libc++ was built with experimental features enabled. #if !defined(_LIBCPP_HAS_NO_INCOMPLETE_TZDB) +# include <__chrono/duration.h> +# include <__chrono/sys_info.h> +# include <__chrono/system_clock.h> # include <__compare/strong_order.h> # include <__config> # include <__memory/unique_ptr.h> @@ -55,10 +58,18 @@ public: _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI string_view name() const noexcept { return __name(); } + template + _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI sys_info get_info(const sys_time<_Duration>& __time) const { + return __get_info(chrono::time_point_cast(__time)); + } + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI const __impl& __implementation() const noexcept { return *__impl_; } private: [[nodiscard]] _LIBCPP_EXPORTED_FROM_ABI string_view __name() const noexcept; + + [[nodiscard]] _LIBCPP_AVAILABILITY_TZDB _LIBCPP_EXPORTED_FROM_ABI sys_info __get_info(sys_seconds __time) const; + unique_ptr<__impl> __impl_; }; diff --git a/libcxx/include/chrono b/libcxx/include/chrono index 8fdc30a3624d..5eddd050196d 100644 --- a/libcxx/include/chrono +++ b/libcxx/include/chrono @@ -724,6 +724,15 @@ const time_zone* current_zone() const tzdb& reload_tzdb(); // C++20 string remote_version(); // C++20 +// [time.zone.info], information classes +struct sys_info { // C++20 + sys_seconds begin; + sys_seconds end; + seconds offset; + minutes save; + string abbrev; +}; + // 25.10.5, class time_zone // C++20 enum class choose {earliest, latest}; class time_zone { @@ -733,6 +742,9 @@ class time_zone { // unspecified additional constructors string_view name() const noexcept; + + template + sys_info get_info(const sys_time& st) const; }; bool operator==(const time_zone& x, const time_zone& y) noexcept; // C++20 strong_ordering operator<=>(const time_zone& x, const time_zone& y) noexcept; // C++20 @@ -881,6 +893,7 @@ constexpr chrono::year operator ""y(unsigned lo #include <__chrono/month_weekday.h> #include <__chrono/monthday.h> #include <__chrono/steady_clock.h> +#include <__chrono/sys_info.h> #include <__chrono/system_clock.h> #include <__chrono/time_point.h> #include <__chrono/weekday.h> diff --git a/libcxx/include/libcxx.imp b/libcxx/include/libcxx.imp index a79e8fedbdac..6c77ba8343c6 100644 --- a/libcxx/include/libcxx.imp +++ b/libcxx/include/libcxx.imp @@ -288,6 +288,7 @@ { include: [ "<__chrono/parser_std_format_spec.h>", "private", "", "public" ] }, { include: [ "<__chrono/statically_widen.h>", "private", "", "public" ] }, { include: [ "<__chrono/steady_clock.h>", "private", "", "public" ] }, + { include: [ "<__chrono/sys_info.h>", "private", "", "public" ] }, { include: [ "<__chrono/system_clock.h>", "private", "", "public" ] }, { include: [ "<__chrono/time_point.h>", "private", "", "public" ] }, { include: [ "<__chrono/time_zone.h>", "private", "", "public" ] }, diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index e1637907b3ec..011a4818ab9d 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -1167,6 +1167,9 @@ module std_private_chrono_time_zone [system] { module std_private_chrono_time_zone_link [system] { header "__chrono/time_zone_link.h" } +module std_private_chrono_sys_info [system] { + header "__chrono/sys_info.h" +} module std_private_chrono_system_clock [system] { header "__chrono/system_clock.h" export std_private_chrono_time_point diff --git a/libcxx/modules/std/chrono.inc b/libcxx/modules/std/chrono.inc index e14228043d3b..575e6347aecc 100644 --- a/libcxx/modules/std/chrono.inc +++ b/libcxx/modules/std/chrono.inc @@ -212,10 +212,12 @@ export namespace std { // [time.zone.exception], exception classes using std::chrono::ambiguous_local_time; using std::chrono::nonexistent_local_time; +# endif // if 0 // [time.zone.info], information classes using std::chrono::sys_info; +# if 0 // [time.zone.timezone], class time_zone using std::chrono::choose; # endif // if 0 diff --git a/libcxx/src/include/tzdb/time_zone_private.h b/libcxx/src/include/tzdb/time_zone_private.h index 039a3b0ffeb7..2c47e9fdb13d 100644 --- a/libcxx/src/include/tzdb/time_zone_private.h +++ b/libcxx/src/include/tzdb/time_zone_private.h @@ -24,7 +24,8 @@ namespace chrono { class time_zone::__impl { public: - explicit _LIBCPP_HIDE_FROM_ABI __impl(string&& __name) : __name_(std::move(__name)) {} + explicit _LIBCPP_HIDE_FROM_ABI __impl(string&& __name, const __tz::__rules_storage_type& __rules_db) + : __name_(std::move(__name)), __rules_db_(__rules_db) {} [[nodiscard]] _LIBCPP_HIDE_FROM_ABI string_view __name() const noexcept { return __name_; } @@ -33,12 +34,20 @@ public: return __continuations_; } + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI const __tz::__rules_storage_type& __rules_db() const { return __rules_db_; } + private: string __name_; // Note the first line has a name + __continuation, the other lines // are just __continuations. So there is always at least one item in // the vector. vector<__tz::__continuation> __continuations_; + + // Continuations often depend on a set of rules. The rules are stored in + // parallel data structurs in tzdb_list. From the time_zone it's not possible + // to find its associated tzdb entry and thus not possible to find its + // associated rules. Therefore a link to the rules in stored in this class. + const __tz::__rules_storage_type& __rules_db_; }; } // namespace chrono diff --git a/libcxx/src/include/tzdb/types_private.h b/libcxx/src/include/tzdb/types_private.h index 4604b9fc8811..c86982948b61 100644 --- a/libcxx/src/include/tzdb/types_private.h +++ b/libcxx/src/include/tzdb/types_private.h @@ -33,7 +33,17 @@ namespace chrono::__tz { // Sun>=8 first Sunday on or after the eighth // Sun<=25 last Sunday on or before the 25th struct __constrained_weekday { - /* year_month_day operator()(year __year, month __month);*/ // needed but not implemented + [[nodiscard]] _LIBCPP_HIDE_FROM_ABI year_month_day operator()(year __year, month __month) const { + auto __result = static_cast(year_month_day{__year, __month, __day}); + weekday __wd{static_cast(__result)}; + + if (__comparison == __le) + __result -= __wd - __weekday; + else + __result += __weekday - __wd; + + return __result; + } weekday __weekday; enum __comparison_t { __le, __ge } __comparison; @@ -85,7 +95,8 @@ struct __continuation { // used. // If this field contains - then standard time always // applies. This is indicated by the monostate. - using __rules_t = variant; + // TODO TZDB Investigate implantation the size_t based caching. + using __rules_t = variant; __rules_t __rules; diff --git a/libcxx/src/time_zone.cpp b/libcxx/src/time_zone.cpp index b6bf06a116f6..aef6ac674a11 100644 --- a/libcxx/src/time_zone.cpp +++ b/libcxx/src/time_zone.cpp @@ -8,14 +8,712 @@ // For information see https://libcxx.llvm.org/DesignDocs/TimeZone.html +// TODO TZDB look at optimizations +// +// The current algorithm is correct but not efficient. For example, in a named +// rule based continuation finding the next rule does quite a bit of work, +// returns the next rule and "forgets" its state. This could be better. +// +// It would be possible to cache lookups. If a time for a zone is calculated its +// sys_info could be kept and the next lookup could test whether the time is in +// a "known" sys_info. The wording in the Standard hints at this slowness by +// "suggesting" this could be implemented on the user's side. + +// TODO TZDB look at removing quirks +// +// The code has some special rules to adjust the timing at the continuation +// switches. This works correctly, but some of the places feel odd. It would be +// good to investigate this further and see whether all quirks are needed or +// that there are better fixes. +// +// These quirks often use a 12h interval; this is the scan interval of zdump, +// which implies there are no sys_info objects with a duration of less than 12h. + +#include +#include #include +#include +#include +#include #include "include/tzdb/time_zone_private.h" +#include "include/tzdb/tzdb_list_private.h" + +// TODO TZDB remove debug printing +#ifdef PRINT +# include +#endif _LIBCPP_BEGIN_NAMESPACE_STD +#ifdef PRINT +template <> +struct formatter { + template + constexpr typename ParseContext::iterator parse(ParseContext& ctx) { + return ctx.begin(); + } + + template + typename FormatContext::iterator format(const chrono::sys_info& info, FormatContext& ctx) const { + return std::format_to( + ctx.out(), "[{}, {}) {:%Q%q} {:%Q%q} {}", info.begin, info.end, info.offset, info.save, info.abbrev); + } +}; +#endif + namespace chrono { +//===----------------------------------------------------------------------===// +// Details +//===----------------------------------------------------------------------===// + +struct __sys_info { + sys_info __info; + bool __can_merge; // Can the returned sys_info object be merged with +}; + +// Return type for helper function to get a sys_info. +// - The expected result returns the "best" sys_info object. This object can be +// before the requested time. Sometimes sys_info objects from different +// continuations share their offset, save, and abbrev and these objects are +// merged to one sys_info object. The __can_merge flag determines whether the +// current result can be merged with the next result. +// - The unexpected result means no sys_info object was found and the time is +// the time to be used for the next search iteration. +using __sys_info_result = expected<__sys_info, sys_seconds>; + +template , _Proj>> _Comp = ranges::less> +[[nodiscard]] static ranges::borrowed_iterator_t<_Range> +__binary_find(_Range&& __r, const _Type& __value, _Comp __comp = {}, _Proj __proj = {}) { + auto __end = ranges::end(__r); + auto __ret = ranges::lower_bound(ranges::begin(__r), __end, __value, __comp, __proj); + if (__ret == __end) + return __end; + + // When the value does not match the predicate it's equal and a valid result + // was found. + return !std::invoke(__comp, __value, std::invoke(__proj, *__ret)) ? __ret : __end; +} + +// Format based on https://data.iana.org/time-zones/tz-how-to.html +// +// 1 a time zone abbreviation that is a string of three or more characters that +// are either ASCII alphanumerics, "+", or "-" +// 2 the string "%z", in which case the "%z" will be replaced by a numeric time +// zone abbreviation +// 3 a pair of time zone abbreviations separated by a slash ('/'), in which +// case the first string is the abbreviation for the standard time name and +// the second string is the abbreviation for the daylight saving time name +// 4 a string containing "%s", in which case the "%s" will be replaced by the +// text in the appropriate Rule's LETTER column, and the resulting string +// should be a time zone abbreviation +// +// Rule 1 is not strictly validated since America/Barbados uses a two letter +// abbreviation AT. +[[nodiscard]] static string +__format(const __tz::__continuation& __continuation, const string& __letters, seconds __save) { + bool __shift = false; + string __result; + for (char __c : __continuation.__format) { + if (__shift) { + switch (__c) { + case 's': + std::ranges::copy(__letters, std::back_inserter(__result)); + break; + + case 'z': { + if (__continuation.__format.size() != 2) + std::__throw_runtime_error( + std::format("corrupt tzdb FORMAT field: %z should be the entire contents, instead contains '{}'", + __continuation.__format) + .c_str()); + chrono::hh_mm_ss __offset{__continuation.__stdoff + __save}; + if (__offset.is_negative()) { + __result += '-'; + __offset = chrono::hh_mm_ss{-(__continuation.__stdoff + __save)}; + } else + __result += '+'; + + if (__offset.minutes() != 0min) + std::format_to(std::back_inserter(__result), "{:%H%M}", __offset); + else + std::format_to(std::back_inserter(__result), "{:%H}", __offset); + } break; + + default: + std::__throw_runtime_error( + std::format("corrupt tzdb FORMAT field: invalid sequence '%{}' found, expected %s or %z", __c).c_str()); + } + __shift = false; + + } else if (__c == '/') { + if (__save != 0s) + __result.clear(); + else + break; + + } else if (__c == '%') { + __shift = true; + } else if (__c == '+' || __c == '-' || std::isalnum(__c)) { + __result.push_back(__c); + } else { + std::__throw_runtime_error( + std::format( + "corrupt tzdb FORMAT field: invalid character '{}' found, expected +, -, or an alphanumeric value", __c) + .c_str()); + } + } + + if (__shift) + std::__throw_runtime_error("corrupt tzdb FORMAT field: input ended with the start of the escape sequence '%'"); + + if (__result.empty()) + std::__throw_runtime_error("corrupt tzdb FORMAT field: result is empty"); + + return __result; +} + +[[nodiscard]] static sys_seconds __to_sys_seconds(year_month_day __ymd, seconds __seconds) { + seconds __result = static_cast(__ymd).time_since_epoch() + __seconds; + return sys_seconds{__result}; +} + +[[nodiscard]] static seconds __at_to_sys_seconds(const __tz::__continuation& __continuation) { + switch (__continuation.__at.__clock) { + case __tz::__clock::__local: + return __continuation.__at.__time - __continuation.__stdoff - + std::visit( + [](const auto& __value) { + using _Tp = decay_t; + if constexpr (same_as<_Tp, monostate>) + return chrono::seconds{0}; + else if constexpr (same_as<_Tp, __tz::__save>) + return chrono::duration_cast(__value.__time); + else if constexpr (same_as<_Tp, std::string>) + // For a named rule based continuation the SAVE depends on the RULE + // active at the end. This should be determined separately. + return chrono::seconds{0}; + else + static_assert(sizeof(_Tp) == 0); // TODO TZDB static_assert(false); after droping clang-16 support + + std::__libcpp_unreachable(); + }, + __continuation.__rules); + + case __tz::__clock::__universal: + return __continuation.__at.__time; + + case __tz::__clock::__standard: + return __continuation.__at.__time - __continuation.__stdoff; + } + std::__libcpp_unreachable(); +} + +[[nodiscard]] static year_month_day __to_year_month_day(year __year, month __month, __tz::__on __on) { + return std::visit( + [&](const auto& __value) { + using _Tp = decay_t; + if constexpr (same_as<_Tp, chrono::day>) + return year_month_day{__year, __month, __value}; + else if constexpr (same_as<_Tp, weekday_last>) + return year_month_day{static_cast(year_month_weekday_last{__year, __month, __value})}; + else if constexpr (same_as<_Tp, __tz::__constrained_weekday>) + return __value(__year, __month); + else + static_assert(sizeof(_Tp) == 0); // TODO TZDB static_assert(false); after droping clang-16 support + + std::__libcpp_unreachable(); + }, + __on); +} + +[[nodiscard]] static sys_seconds __until_to_sys_seconds(const __tz::__continuation& __continuation) { + // Does UNTIL contain the magic value for the last continuation? + if (__continuation.__year == chrono::year::min()) + return sys_seconds::max(); + + year_month_day __ymd = chrono::__to_year_month_day(__continuation.__year, __continuation.__in, __continuation.__on); + return chrono::__to_sys_seconds(__ymd, chrono::__at_to_sys_seconds(__continuation)); +} + +// Holds the UNTIL time for a continuation with a named rule. +// +// Unlike continuations with an fixed SAVE named rules have a variable SAVE. +// This means when the UNTIL uses the local wall time the actual UNTIL value can +// only be determined when the SAVE is known. This class holds that abstraction. +class __named_rule_until { +public: + explicit __named_rule_until(const __tz::__continuation& __continuation) + : __until_{chrono::__until_to_sys_seconds(__continuation)}, + __needs_adjustment_{ + // The last continuation of a ZONE has no UNTIL which basically is + // until the end of _local_ time. This value is expressed by + // sys_seconds::max(). Subtracting the SAVE leaves large value. + // However SAVE can be negative, which would add a value to maximum + // leading to undefined behaviour. In practice this often results in + // an overflow to a very small value. + __until_ != sys_seconds::max() && __continuation.__at.__clock == __tz::__clock::__local} {} + + // Gives the unadjusted until value, this is useful when the SAVE is not known + // at all. + sys_seconds __until() const noexcept { return __until_; } + + bool __needs_adjustment() const noexcept { return __needs_adjustment_; } + + // Returns the UNTIL adjusted for SAVE. + sys_seconds operator()(seconds __save) const noexcept { return __until_ - __needs_adjustment_ * __save; } + +private: + sys_seconds __until_; + bool __needs_adjustment_; +}; + +[[nodiscard]] static seconds __at_to_seconds(seconds __stdoff, const __tz::__rule& __rule) { + switch (__rule.__at.__clock) { + case __tz::__clock::__local: + // Local time and standard time behave the same. This is not + // correct. Local time needs to adjust for the current saved time. + // To know the saved time the rules need to be known and sorted. + // This needs a time so to avoid the chicken and egg adjust the + // saving of the local time later. + return __rule.__at.__time - __stdoff; + + case __tz::__clock::__universal: + return __rule.__at.__time; + + case __tz::__clock::__standard: + return __rule.__at.__time - __stdoff; + } + std::__libcpp_unreachable(); +} + +[[nodiscard]] static sys_seconds __from_to_sys_seconds(seconds __stdoff, const __tz::__rule& __rule, year __year) { + year_month_day __ymd = chrono::__to_year_month_day(__year, __rule.__in, __rule.__on); + + seconds __at = chrono::__at_to_seconds(__stdoff, __rule); + return chrono::__to_sys_seconds(__ymd, __at); +} + +[[nodiscard]] static sys_seconds __from_to_sys_seconds(seconds __stdoff, const __tz::__rule& __rule) { + return chrono::__from_to_sys_seconds(__stdoff, __rule, __rule.__from); +} + +[[nodiscard]] static const vector<__tz::__rule>& +__get_rules(const __tz::__rules_storage_type& __rules_db, const string& __rule_name) { + auto __result = chrono::__binary_find(__rules_db, __rule_name, {}, [](const auto& __p) { return __p.first; }); + if (__result == std::end(__rules_db)) + std::__throw_runtime_error(("corrupt tzdb: rule '" + __rule_name + " 'does not exist").c_str()); + + return __result->second; +} + +// Returns the letters field for a time before the first rule. +// +// Per https://data.iana.org/time-zones/tz-how-to.html +// One wrinkle, not fully explained in zic.8.txt, is what happens when switching +// to a named rule. To what values should the SAVE and LETTER data be +// initialized? +// +// 1 If at least one transition has happened, use the SAVE and LETTER data from +// the most recent. +// 2 If switching to a named rule before any transition has happened, assume +// standard time (SAVE zero), and use the LETTER data from the earliest +// transition with a SAVE of zero. +// +// This function implements case 2. +[[nodiscard]] static string __letters_before_first_rule(const vector<__tz::__rule>& __rules) { + auto __letters = + __rules // + | views::filter([](const __tz::__rule& __rule) { return __rule.__save.__time == 0s; }) // + | views::transform([](const __tz::__rule& __rule) { return __rule.__letters; }) // + | views::take(1); + + if (__letters.empty()) + std::__throw_runtime_error("corrupt tzdb: rule has zero entries"); + + return __letters.front(); +} + +// Determines the information based on the continuation and the rules. +// +// There are several special cases to take into account +// +// === Entries before the first rule becomes active === +// Asia/Hong_Kong +// 9 - JST 1945 N 18 2 // (1) +// 8 HK HK%sT // (2) +// R HK 1946 o - Ap 21 0 1 S // (3) +// There (1) is active until Novemer 18th 1945 at 02:00, after this time +// (2) becomes active. The first rule entry for HK (3) becomes active +// from April 21st 1945 at 01:00. In the period between (2) is active. +// This entry has an offset. +// This entry has no save, letters, or dst flag. So in the period +// after (1) and until (3) no rule entry is associated with the time. + +[[nodiscard]] static sys_info __get_sys_info_before_first_rule( + sys_seconds __begin, + sys_seconds __end, + const __tz::__continuation& __continuation, + const vector<__tz::__rule>& __rules) { + return sys_info{ + __begin, + __end, + __continuation.__stdoff, + chrono::minutes(0), + chrono::__format(__continuation, __letters_before_first_rule(__rules), 0s)}; +} + +// Returns the sys_info object for a time before the first rule. +// When this first rule has a SAVE of 0s the sys_info for the time before the +// first rule and for the first rule are identical and will be merged. +[[nodiscard]] static sys_info __get_sys_info_before_first_rule( + sys_seconds __begin, + sys_seconds __rule_end, // The end used when SAVE != 0s + sys_seconds __next_end, // The end used when SAVE == 0s the times are merged + const __tz::__continuation& __continuation, + const vector<__tz::__rule>& __rules, + vector<__tz::__rule>::const_iterator __rule) { + if (__rule->__save.__time != 0s) + return __get_sys_info_before_first_rule(__begin, __rule_end, __continuation, __rules); + + return sys_info{ + __begin, __next_end, __continuation.__stdoff, 0min, chrono::__format(__continuation, __rule->__letters, 0s)}; +} + +[[nodiscard]] static seconds __at_to_seconds(seconds __stdoff, seconds __save, const __tz::__rule& __rule) { + switch (__rule.__at.__clock) { + case __tz::__clock::__local: + return __rule.__at.__time - __stdoff - __save; + + case __tz::__clock::__universal: + return __rule.__at.__time; + + case __tz::__clock::__standard: + return __rule.__at.__time - __stdoff; + } + std::__libcpp_unreachable(); +} + +[[nodiscard]] static sys_seconds +__rule_to_sys_seconds(seconds __stdoff, seconds __save, const __tz::__rule& __rule, year __year) { + year_month_day __ymd = chrono::__to_year_month_day(__year, __rule.__in, __rule.__on); + + seconds __at = chrono::__at_to_seconds(__stdoff, __save, __rule); + return chrono::__to_sys_seconds(__ymd, __at); +} + +// Returns the first rule after __time. +// Note that a rule can be "active" in multiple years, this may result in an +// infinite loop where the same rule is returned every time, use __current to +// guard against that. +// +// When no next rule exists the returned time will be sys_seconds::max(). This +// can happen in practice. For example, +// +// R So 1945 o - May 24 2 2 M +// R So 1945 o - S 24 3 1 S +// R So 1945 o - N 18 2s 0 - +// +// Has 3 rules that are all only active in 1945. +[[nodiscard]] static pair::const_iterator> +__next_rule(sys_seconds __time, + seconds __stdoff, + seconds __save, + const vector<__tz::__rule>& __rules, + vector<__tz::__rule>::const_iterator __current) { + year __year = year_month_day{chrono::floor(__time)}.year(); + + // Note it would probably be better to store the pairs in a vector and then + // use min() to get the smallest element + map::const_iterator> __candidates; + // Note this evaluates all rules which is a waste of effort; when the entries + // are beyond the current year's "next year" (where "next year" is not always + // year + 1) the algorithm should end. + for (auto __it = __rules.begin(); __it != __rules.end(); ++__it) { + for (year __y = __it->__from; __y <= __it->__to; ++__y) { + // Adding the current entry for the current year may lead to infinite + // loops due to the SAVE adjustment. Skip these entries. + if (__y == __year && __it == __current) + continue; + + sys_seconds __t = chrono::__rule_to_sys_seconds(__stdoff, __save, *__it, __y); + if (__t <= __time) + continue; + + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(!__candidates.contains(__t), "duplicated rule"); + __candidates[__t] = __it; + break; + } + } + + if (!__candidates.empty()) [[likely]] { + auto __it = __candidates.begin(); + + // When no rule is selected the time before the first rule and the first rule + // should not be merged. + if (__time == sys_seconds::min()) + return *__it; + + // There can be two constitutive rules that are the same. For example, + // Hong Kong + // + // R HK 1973 o - D 30 3:30 1 S (R1) + // R HK 1965 1976 - Ap Su>=16 3:30 1 S (R2) + // + // 1973-12-29 19:30:00 R1 becomes active. + // 1974-04-20 18:30:00 R2 becomes active. + // Both rules have a SAVE of 1 hour and LETTERS are S for both of them. + while (__it != __candidates.end()) { + if (__current->__save.__time != __it->second->__save.__time || __current->__letters != __it->second->__letters) + return *__it; + + ++__it; + } + } + + return {sys_seconds::max(), __rules.end()}; +} + +// Returns the first rule of a set of rules. +// This is not always the first of the listed rules. For example +// R Sa 2008 2009 - Mar Su>=8 0 0 - +// R Sa 2007 2008 - O Su>=8 0 1 - +// The transition in October 2007 happens before the transition in March 2008. +[[nodiscard]] static vector<__tz::__rule>::const_iterator +__first_rule(seconds __stdoff, const vector<__tz::__rule>& __rules) { + return chrono::__next_rule(sys_seconds::min(), __stdoff, 0s, __rules, __rules.end()).second; +} + +[[nodiscard]] static __sys_info_result __get_sys_info_rule( + sys_seconds __time, + sys_seconds __continuation_begin, + const __tz::__continuation& __continuation, + const vector<__tz::__rule>& __rules) { + auto __rule = chrono::__first_rule(__continuation.__stdoff, __rules); + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN(__rule != __rules.end(), "the set of rules has no first rule"); + + // Avoid selecting a time before the start of the continuation + __time = std::max(__time, __continuation_begin); + + sys_seconds __rule_begin = chrono::__from_to_sys_seconds(__continuation.__stdoff, *__rule); + + // The time sought is very likely inside the current rule. + // When the continuation's UNTIL uses the local clock there are edge cases + // where this is not true. + // + // Start to walk the rules to find the proper one. + // + // For now we just walk all the rules TODO TZDB investigate whether a smarter + // algorithm would work. + auto __next = chrono::__next_rule(__rule_begin, __continuation.__stdoff, __rule->__save.__time, __rules, __rule); + + // Ignore small steps, this happens with America/Punta_Arenas for the + // transition + // -4:42:46 - SMT 1927 S + // -5 x -05/-04 1932 S + // ... + // + // R x 1927 1931 - S 1 0 1 - + // R x 1928 1932 - Ap 1 0 0 - + // + // America/Punta_Arenas Thu Sep 1 04:42:45 1927 UT = Thu Sep 1 00:42:45 1927 -04 isdst=1 gmtoff=-14400 + // America/Punta_Arenas Sun Apr 1 03:59:59 1928 UT = Sat Mar 31 23:59:59 1928 -04 isdst=1 gmtoff=-14400 + // America/Punta_Arenas Sun Apr 1 04:00:00 1928 UT = Sat Mar 31 23:00:00 1928 -05 isdst=0 gmtoff=-18000 + // + // Without this there will be a transition + // [1927-09-01 04:42:45, 1927-09-01 05:00:00) -05:00:00 0min -05 + + if (sys_seconds __begin = __rule->__save.__time != 0s ? __rule_begin : __next.first; __time < __begin) { + if (__continuation_begin == sys_seconds::min() || __begin - __continuation_begin > 12h) + return __sys_info{__get_sys_info_before_first_rule( + __continuation_begin, __rule_begin, __next.first, __continuation, __rules, __rule), + false}; + + // Europe/Berlin + // 1 c CE%sT 1945 May 24 2 (C1) + // 1 So CE%sT 1946 (C2) + // + // R c 1944 1945 - Ap M>=1 2s 1 S (R1) + // + // R So 1945 o - May 24 2 2 M (R2) + // + // When C2 becomes active the time would be before the first rule R2, + // giving a 1 hour sys_info. + seconds __save = __rule->__save.__time; + __named_rule_until __continuation_end{__continuation}; + sys_seconds __sys_info_end = std::min(__continuation_end(__save), __next.first); + + return __sys_info{ + sys_info{__continuation_begin, + __sys_info_end, + __continuation.__stdoff + __save, + chrono::duration_cast(__save), + chrono::__format(__continuation, __rule->__letters, __save)}, + __sys_info_end == __continuation_end(__save)}; + } + + // See above for America/Asuncion + if (__rule->__save.__time == 0s && __time < __next.first) { + return __sys_info{ + sys_info{__continuation_begin, + __next.first, + __continuation.__stdoff, + 0min, + chrono::__format(__continuation, __rule->__letters, 0s)}, + false}; + } + + __named_rule_until __continuation_end{__continuation}; + if (__time >= __continuation_end.__until() && !__continuation_end.__needs_adjustment()) + // note std::unexpected(__end); is ambiguous with std::unexpected() in , + return __sys_info_result{std::unexpect, __continuation_end.__until()}; + + while (__next.second != __rules.end()) { +#ifdef PRINT + std::print( + stderr, + "Rule for {}: [{}, {}) off={} save={} duration={}\n", + __time, + __rule_begin, + __next.first, + __continuation.__stdoff, + __rule->__save.__time, + __next.first - __rule_begin); +#endif + + sys_seconds __end = __continuation_end(__rule->__save.__time); + + sys_seconds __sys_info_begin = std::max(__continuation_begin, __rule_begin); + sys_seconds __sys_info_end = std::min(__end, __next.first); + seconds __diff = chrono::abs(__sys_info_end - __sys_info_begin); + + if (__diff < 12h) { + // Z America/Argentina/Buenos_Aires -3:53:48 - LMT 1894 O 31 + // -4:16:48 - CMT 1920 May + // -4 - -04 1930 D + // -4 A -04/-03 1969 O 5 + // -3 A -03/-02 1999 O 3 + // -4 A -04/-03 2000 Mar 3 + // ... + // + // ... + // R A 1989 1992 - O Su>=15 0 1 - + // R A 1999 o - O Su>=1 0 1 - + // R A 2000 o - Mar 3 0 0 - + // R A 2007 o - D 30 0 1 - + // ... + + // The 1999 switch uses the same rule, but with a different stdoff. + // R A 1999 o - O Su>=1 0 1 - + // stdoff -3 -> 1999-10-03 03:00:00 + // stdoff -4 -> 1999-10-03 04:00:00 + // This generates an invalid entry and this is evaluated as a transition. + // Looking at the zdump like output in libc++ this generates jumps in + // the UTC time. + + __rule = __next.second; + __next = __next_rule(__next.first, __continuation.__stdoff, __rule->__save.__time, __rules, __rule); + __end = __continuation_end(__rule->__save.__time); + __sys_info_end = std::min(__end, __next.first); + } + + if ((__time >= __rule_begin && __time < __next.first) || __next.first >= __end) { + __sys_info_begin = std::max(__continuation_begin, __rule_begin); + __sys_info_end = std::min(__end, __next.first); + + return __sys_info{ + sys_info{__sys_info_begin, + __sys_info_end, + __continuation.__stdoff + __rule->__save.__time, + chrono::duration_cast(__rule->__save.__time), + chrono::__format(__continuation, __rule->__letters, __rule->__save.__time)}, + __sys_info_end == __end}; + } + + __rule_begin = __next.first; + __rule = __next.second; + __next = __next_rule(__rule_begin, __continuation.__stdoff, __rule->__save.__time, __rules, __rule); + } + + return __sys_info{ + sys_info{std::max(__continuation_begin, __rule_begin), + __continuation_end(__rule->__save.__time), + __continuation.__stdoff + __rule->__save.__time, + chrono::duration_cast(__rule->__save.__time), + chrono::__format(__continuation, __rule->__letters, __rule->__save.__time)}, + true}; +} + +[[nodiscard]] static __sys_info_result __get_sys_info_basic( + sys_seconds __time, sys_seconds __continuation_begin, const __tz::__continuation& __continuation, seconds __save) { + sys_seconds __continuation_end = chrono::__until_to_sys_seconds(__continuation); + return __sys_info{ + sys_info{__continuation_begin, + __continuation_end, + __continuation.__stdoff + __save, + chrono::duration_cast(__save), + __continuation.__format}, + true}; +} + +[[nodiscard]] static __sys_info_result +__get_sys_info(sys_seconds __time, + sys_seconds __continuation_begin, + const __tz::__continuation& __continuation, + const __tz::__rules_storage_type& __rules_db) { + return std::visit( + [&](const auto& __value) { + using _Tp = decay_t; + if constexpr (same_as<_Tp, std::string>) + return chrono::__get_sys_info_rule( + __time, __continuation_begin, __continuation, __get_rules(__rules_db, __value)); + else if constexpr (same_as<_Tp, monostate>) + return chrono::__get_sys_info_basic(__time, __continuation_begin, __continuation, chrono::seconds(0)); + else if constexpr (same_as<_Tp, __tz::__save>) + return chrono::__get_sys_info_basic(__time, __continuation_begin, __continuation, __value.__time); + else + static_assert(sizeof(_Tp) == 0); // TODO TZDB static_assert(false); after droping clang-16 support + + std::__libcpp_unreachable(); + }, + __continuation.__rules); +} + +// The transition from one continuation to the next continuation may result in +// two constitutive continuations with the same "offset" information. +// [time.zone.info.sys]/3 +// The begin and end data members indicate that, for the associated time_zone +// and time_point, the offset and abbrev are in effect in the range +// [begin, end). This information can be used to efficiently iterate the +// transitions of a time_zone. +// +// Note that this does considers a change in the SAVE field not to be a +// different sys_info, zdump does consider this different. +// LWG XXXX The sys_info range should be affected by save +// matches the behaviour of the Standard and zdump. +// +// Iff the "offsets" are the same '__current.__end' is replaced with +// '__next.__end', which effectively merges the two objects in one object. The +// function returns true if a merge occurred. +[[nodiscard]] bool __merge_continuation(sys_info& __current, const sys_info& __next) { + if (__current.end != __next.begin) + return false; + + if (__current.offset != __next.offset || __current.abbrev != __next.abbrev || __current.save != __next.save) + return false; + + __current.end = __next.end; + return true; +} + +//===----------------------------------------------------------------------===// +// Public API +//===----------------------------------------------------------------------===// + [[nodiscard]] _LIBCPP_EXPORTED_FROM_ABI time_zone time_zone::__create(unique_ptr&& __p) { _LIBCPP_ASSERT_NON_NULL(__p != nullptr, "initialized time_zone without a valid pimpl object"); time_zone result; @@ -27,6 +725,173 @@ _LIBCPP_EXPORTED_FROM_ABI time_zone::~time_zone() = default; [[nodiscard]] _LIBCPP_EXPORTED_FROM_ABI string_view time_zone::__name() const noexcept { return __impl_->__name(); } +[[nodiscard]] _LIBCPP_AVAILABILITY_TZDB _LIBCPP_EXPORTED_FROM_ABI sys_info +time_zone::__get_info(sys_seconds __time) const { + optional __result; + bool __valid_result = false; // true iff __result.has_value() is true and + // __result.begin <= __time < __result.end is true. + bool __can_merge = false; + sys_seconds __continuation_begin = sys_seconds::min(); + // Iterates over the Zone entry and its continuations. Internally the Zone + // entry is split in a Zone information and the first continuation. The last + // continuation has no UNTIL field. This means the loop should always find a + // continuation. + // + // For more information on background of zone information please consult the + // following information + // [zic manual](https://www.man7.org/linux/man-pages/man8/zic.8.html) + // [tz source info](https://data.iana.org/time-zones/tz-how-to.html) + // On POSIX systems the zdump tool can be useful: + // zdump -v Asia/Hong_Kong + // Gives all transitions in the Hong Kong time zone. + // + // During iteration the result for the current continuation is returned. If + // no continuation is applicable it will return the end time as "error". When + // two continuations are contiguous and contain the "same" information these + // ranges are merged as one range. + // The merging requires keeping any result that occurs before __time, + // likewise when a valid result is found the algorithm needs to test the next + // continuation to see whether it can be merged. For example, Africa/Ceuta + // Continuations + // 0 s WE%sT 1929 (C1) + // 0 - WET 1967 (C2) + // 0 Sp WE%sT 1984 Mar 16 (C3) + // + // Rules + // R s 1926 1929 - O Sa>=1 24s 0 - (R1) + // + // R Sp 1967 o - Jun 3 12 1 S (R2) + // + // The rule R1 is the last rule used in C1. The rule R2 is the first rule in + // C3. Since R2 is the first rule this means when a continuation uses this + // rule its value prior to R2 will be SAVE 0 LETTERS of the first entry with a + // SAVE of 0, in this case WET. + // This gives the following changes in the information. + // 1928-10-07 00:00:00 C1 R1 becomes active: offset 0 save 0 abbrev WET + // 1929-01-01 00:00:00 C2 becomes active: offset 0 save 0 abbrev WET + // 1967-01-01 00:00:00 C3 becomes active: offset 0 save 0 abbrev WET + // 1967-06-03 12:00:00 C3 R2 becomes active: offset 0 save 1 abbrev WEST + // + // The first 3 entries are contiguous and contain the same information, this + // means the period [1928-10-07 00:00:00, 1967-06-03 12:00:00) should be + // returned in one sys_info object. + + const auto& __continuations = __impl_->__continuations(); + const __tz::__rules_storage_type& __rules_db = __impl_->__rules_db(); + for (auto __it = __continuations.begin(); __it != __continuations.end(); ++__it) { + const auto& __continuation = *__it; + __sys_info_result __sys_info = chrono::__get_sys_info(__time, __continuation_begin, __continuation, __rules_db); + + if (__sys_info) { + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( + __sys_info->__info.begin < __sys_info->__info.end, "invalid sys_info range"); + + // Filters out dummy entries + // Z America/Argentina/Buenos_Aires -3:53:48 - LMT 1894 O 31 + // ... + // -4 A -04/-03 2000 Mar 3 (C1) + // -3 A -03/-02 (C2) + // + // ... + // R A 2000 o - Mar 3 0 0 - + // R A 2007 o - D 30 0 1 - + // ... + // + // This results in an entry + // [2000-03-03 03:00:00, 2000-03-03 04:00:00) -10800s 60min -03 + // for [C1 & R1, C1, R2) which due to the end of the continuation is an + // one hour "sys_info". Instead the entry should be ignored and replaced + // by [C2 & R1, C2 & R2) which is the proper range + // "[2000-03-03 03:00:00, 2007-12-30 03:00:00) -02:00:00 60min -02 + + if (std::holds_alternative(__continuation.__rules) && __sys_info->__can_merge && + __sys_info->__info.begin + 12h > __sys_info->__info.end) { + __continuation_begin = __sys_info->__info.begin; + continue; + } + + if (!__result) { + // First entry found, always keep it. + __result = __sys_info->__info; + + __valid_result = __time >= __result->begin && __time < __result->end; + __can_merge = __sys_info->__can_merge; + } else if (__can_merge && chrono::__merge_continuation(*__result, __sys_info->__info)) { + // The results are merged, update the result state. This may + // "overwrite" a valid sys_info object with another valid sys_info + // object. + __valid_result = __time >= __result->begin && __time < __result->end; + __can_merge = __sys_info->__can_merge; + } else { + // Here things get interesting: + // For example, America/Argentina/San_Luis + // + // -3 A -03/-02 2008 Ja 21 (C1) + // -4 Sa -04/-03 2009 O 11 (C2) + // + // R A 2007 o - D 30 0 1 - (R1) + // + // R Sa 2007 2008 - O Su>=8 0 1 - (R2) + // + // Based on C1 & R1 the end time of C1 is 2008-01-21 03:00:00 + // Based on C2 & R2 the end time of C1 is 2008-01-21 02:00:00 + // In this case the earlier time is the real time of the transition. + // However the algorithm used gives 2008-01-21 03:00:00. + // + // So we need to calculate the previous UNTIL in the current context and + // see whether it's earlier. + + // The results could not be merged. + // - When we have a valid result that result is the final result. + // - Otherwise the result we had is before __time and the result we got + // is at a later time (possibly valid). This result is always better + // than the previous result. + if (__valid_result) { + return *__result; + } else { + _LIBCPP_ASSERT_ARGUMENT_WITHIN_DOMAIN( + __it != __continuations.begin(), "the first rule should always seed the result"); + const auto& __last = *(__it - 1); + if (std::holds_alternative(__last.__rules)) { + // Europe/Berlin + // 1 c CE%sT 1945 May 24 2 (C1) + // 1 So CE%sT 1946 (C2) + // + // R c 1944 1945 - Ap M>=1 2s 1 S (R1) + // + // R So 1945 o - May 24 2 2 M (R2) + // + // When C2 becomes active the time would be before the first rule R2, + // giving a 1 hour sys_info. This is not valid and the results need + // merging. + + if (__result->end != __sys_info->__info.begin) { + // When the UTC gap between the rules is due to the change of + // offsets adjust the new time to remove the gap. + sys_seconds __end = __result->end - __result->offset; + sys_seconds __begin = __sys_info->__info.begin - __sys_info->__info.offset; + if (__end == __begin) { + __sys_info->__info.begin = __result->end; + } + } + } + + __result = __sys_info->__info; + __valid_result = __time >= __result->begin && __time < __result->end; + __can_merge = __sys_info->__can_merge; + } + } + __continuation_begin = __result->end; + } else { + __continuation_begin = __sys_info.error(); + } + } + if (__valid_result) + return *__result; + + std::__throw_runtime_error("tzdb: corrupt db"); +} + } // namespace chrono _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/src/tzdb.cpp b/libcxx/src/tzdb.cpp index 9d06eb920e5c..8909ecd026ad 100644 --- a/libcxx/src/tzdb.cpp +++ b/libcxx/src/tzdb.cpp @@ -561,7 +561,7 @@ static void __parse_rule(tzdb& __tzdb, __tz::__rules_storage_type& __rules, istr static void __parse_zone(tzdb& __tzdb, __tz::__rules_storage_type& __rules, istream& __input) { chrono::__skip_mandatory_whitespace(__input); - auto __p = std::make_unique(chrono::__parse_string(__input)); + auto __p = std::make_unique(chrono::__parse_string(__input), __rules); vector<__tz::__continuation>& __continuations = __p->__continuations(); chrono::__skip_mandatory_whitespace(__input); diff --git a/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.compile.pass.cpp b/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.compile.pass.cpp index 9acb57fa05f7..cbdb2ab1758e 100644 --- a/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.compile.pass.cpp +++ b/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.compile.pass.cpp @@ -50,6 +50,7 @@ void test() { { tz.name(); + tz.get_info(std::chrono::sys_seconds{}); operator==(tz, tz); operator<=>(tz, tz); } diff --git a/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.verify.cpp b/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.verify.cpp index 8795a4eb3c6c..e88c176af4a8 100644 --- a/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.verify.cpp +++ b/libcxx/test/libcxx/diagnostics/chrono.nodiscard_extensions.verify.cpp @@ -47,7 +47,9 @@ void test() { crno::remote_version(); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} { + std::chrono::sys_seconds s{}; tz.name(); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} + tz.get_info(s); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} operator==(tz, tz); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} operator<=>(tz, tz); // expected-warning {{ignoring return value of function declared with 'nodiscard' attribute}} } diff --git a/libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp b/libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp new file mode 100644 index 000000000000..194f58215b92 --- /dev/null +++ b/libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp @@ -0,0 +1,199 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: no-filesystem, no-localization, no-tzdb + +// XFAIL: libcpp-has-no-incomplete-tzdb +// XFAIL: availability-tzdb-missing + +// + +// class time_zone; + +// template +// sys_info get_info(const sys_time<_Duration>& time) const; + +// tests the parts not validated in the public test +// - Validates a zone with an UNTIL in its last continuation is corrupt +// - The formatting of the FORMAT field's constrains +// - Formatting of "%z", this is valid but not present in the actual database + +#include +#include +#include +#include +#include + +#include "test_macros.h" +#include "assert_macros.h" +#include "concat_macros.h" +#include "filesystem_test_helper.h" +#include "test_tzdb.h" + +/***** ***** HELPERS ***** *****/ + +scoped_test_env env; +[[maybe_unused]] const std::filesystem::path dir = env.create_dir("zoneinfo"); +const std::filesystem::path file = env.create_file("zoneinfo/tzdata.zi"); + +std::string_view std::chrono::__libcpp_tzdb_directory() { + static std::string result = dir.string(); + return result; +} + +static void write(std::string_view input) { + static int version = 0; + + std::ofstream f{file}; + f << "# version " << version++ << '\n'; + f.write(input.data(), input.size()); +} + +static const std::chrono::tzdb& parse(std::string_view input) { + write(input); + return std::chrono::reload_tzdb(); +} + +[[nodiscard]] static std::chrono::sys_seconds to_sys_seconds(int year) { + std::chrono::year_month_day result{std::chrono::year{year}, std::chrono::January, std::chrono::day{1}}; + + return std::chrono::time_point_cast(static_cast(result)); +} + +static void test_exception([[maybe_unused]] std::string_view input, [[maybe_unused]] std::string_view what) { +#ifndef TEST_HAS_NO_EXCEPTIONS + const std::chrono::tzdb& tzdb = parse(input); + const std::chrono::time_zone* tz = tzdb.locate_zone("Format"); + TEST_VALIDATE_EXCEPTION( + std::runtime_error, + [&]([[maybe_unused]] const std::runtime_error& e) { + TEST_LIBCPP_REQUIRE( + e.what() == what, + TEST_WRITE_CONCATENATED("\nExpected exception ", what, "\nActual exception ", e.what(), '\n')); + }, + TEST_IGNORE_NODISCARD tz->get_info(to_sys_seconds(2000))); +#endif // TEST_HAS_NO_EXCEPTIONS +} + +static void zone_without_until_entry() { +#ifndef TEST_HAS_NO_EXCEPTIONS + const std::chrono::tzdb& tzdb = parse( + R"( +Z America/Paramaribo -3:40:40 - LMT 1911 +-3:40:52 - PMT 1935 +-3:40:36 - PMT 1945 O +-3:30 - -0330 1984 O +# -3 - -03 Commented out so the last entry has an UNTIL field. +)"); + const std::chrono::time_zone* tz = tzdb.locate_zone("America/Paramaribo"); + + TEST_IGNORE_NODISCARD tz->get_info(to_sys_seconds(1984)); + TEST_VALIDATE_EXCEPTION( + std::runtime_error, + [&]([[maybe_unused]] const std::runtime_error& e) { + std::string what = "tzdb: corrupt db"; + TEST_LIBCPP_REQUIRE( + e.what() == what, + TEST_WRITE_CONCATENATED("\nExpected exception ", what, "\nActual exception ", e.what(), '\n')); + }, + TEST_IGNORE_NODISCARD tz->get_info(to_sys_seconds(1985))); +#endif // TEST_HAS_NO_EXCEPTIONS +} + +static void invalid_format() { + test_exception( + R"( +R F 2000 max - Jan 5 0 0 foo +Z Format 0 F %zandfoo)", + "corrupt tzdb FORMAT field: %z should be the entire contents, instead contains '%zandfoo'"); + + test_exception( + R"( +R F 2000 max - Jan 5 0 0 foo +Z Format 0 F %q)", + "corrupt tzdb FORMAT field: invalid sequence '%q' found, expected %s or %z"); + + test_exception( + R"( +R F 2000 max - Jan 5 0 0 foo +Z Format 0 F !)", + "corrupt tzdb FORMAT field: invalid character '!' found, expected +, -, or an alphanumeric value"); + + test_exception( + R"( +R F 2000 max - Jan 5 0 0 foo +Z Format 0 F @)", + "corrupt tzdb FORMAT field: invalid character '@' found, expected +, -, or an alphanumeric value"); + + test_exception( + R"( +R F 2000 max - Jan 5 0 0 foo +Z Format 0 F $)", + "corrupt tzdb FORMAT field: invalid character '$' found, expected +, -, or an alphanumeric value"); + + test_exception( + R"( +R F 1970 max - Jan 5 0 0 foo +Z Format 0 F %)", + "corrupt tzdb FORMAT field: input ended with the start of the escape sequence '%'"); + + test_exception( + R"( +R F 2000 max - Jan 5 0 0 - +Z Format 0 F %s)", + "corrupt tzdb FORMAT field: result is empty"); +} + +static void test_abbrev(std::string_view input, std::string_view expected) { + const std::chrono::tzdb& tzdb = parse(input); + const std::chrono::time_zone* tz = tzdb.locate_zone("Format"); + std::string result = tz->get_info(to_sys_seconds(2000)).abbrev; + TEST_LIBCPP_REQUIRE(result == expected, TEST_WRITE_CONCATENATED("\nExpected ", expected, "\nActual ", result, '\n')); +} + +// This format is valid, however is not used in the tzdata.zi. +static void percentage_z_format() { + test_abbrev( + R"( +R F 1999 max - Jan 5 0 0 foo +Z Format 0 F %z)", + "+00"); + + test_abbrev( + R"( +R F 1999 max - Jan 5 0 1 foo +Z Format 0 F %z)", + "+01"); + + test_abbrev( + R"( +R F 1999 max - Jan 5 0 -1 foo +Z Format 0 F %z)", + "-01"); + + test_abbrev( + R"( +R F 1999 max - Jan 5 0 0 foo +Z Format 0:45 F %z)", + "+0045"); + + test_abbrev( + R"( +R F 1999 max - Jan 5 0 -1 foo +Z Format 0:45 F %z)", + "-0015"); +} + +int main(int, const char**) { + zone_without_until_entry(); + invalid_format(); + percentage_z_format(); + + return 0; +} diff --git a/libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.rule_selection.pass.cpp b/libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.rule_selection.pass.cpp new file mode 100644 index 000000000000..accd5bcdc89e --- /dev/null +++ b/libcxx/test/libcxx/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.rule_selection.pass.cpp @@ -0,0 +1,185 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: no-filesystem, no-localization, no-tzdb + +// XFAIL: libcpp-has-no-incomplete-tzdb +// XFAIL: availability-tzdb-missing + +// + +// class time_zone; + +// template +// sys_info get_info(const sys_time<_Duration>& time) const; + +// The time zone database contains of the following entries +// - Zones, +// - Rules, +// - Links, and +// - Leapseconds. +// +// The public tzdb struct stores all entries except the Rules. How +// implementations keep track of the Rules is not specified. When the sys_info +// for a time_zone is requested it needs to use the correct Rules. This lookup +// cannot rely on 'get_tzdb()` since that returns the most recently loaded +// database. +// +// A reload could change the rules of a time zone or the time zone could no +// longer be present in the current database. These two conditions are tested. +// +// It is possible the tzdb entry has been removed by the user from the tzdb_list +// after a reload. This is UB and not tested. + +#include +#include +#include + +#include "test_macros.h" +#include "assert_macros.h" +#include "concat_macros.h" +#include "filesystem_test_helper.h" +#include "test_tzdb.h" + +/***** ***** HELPERS ***** *****/ + +scoped_test_env env; +[[maybe_unused]] const std::filesystem::path dir = env.create_dir("zoneinfo"); +const std::filesystem::path file = env.create_file("zoneinfo/tzdata.zi"); + +std::string_view std::chrono::__libcpp_tzdb_directory() { + static std::string result = dir.string(); + return result; +} + +static void write(std::string_view input) { + static int version = 0; + + std::ofstream f{file}; + f << "# version " << version++ << '\n'; + f.write(input.data(), input.size()); +} + +static const std::chrono::tzdb& parse(std::string_view input) { + write(input); + return std::chrono::reload_tzdb(); +} + +[[nodiscard]] static std::chrono::sys_seconds to_sys_seconds( + std::chrono::year year, + std::chrono::month month, + std::chrono::day day, + std::chrono::hours h = std::chrono::hours(0), + std::chrono::minutes m = std::chrono::minutes{0}, + std::chrono::seconds s = std::chrono::seconds{0}) { + std::chrono::year_month_day result{year, month, day}; + + return std::chrono::time_point_cast(static_cast(result)) + h + m + s; +} + +static void assert_equal(const std::chrono::sys_info& lhs, const std::chrono::sys_info& rhs) { + TEST_REQUIRE(lhs.begin == rhs.begin, + TEST_WRITE_CONCATENATED("\nBegin:\nExpected output ", lhs.begin, "\nActual output ", rhs.begin, '\n')); + TEST_REQUIRE(lhs.end == rhs.end, + TEST_WRITE_CONCATENATED("\nEnd:\nExpected output ", lhs.end, "\nActual output ", rhs.end, '\n')); + TEST_REQUIRE( + lhs.offset == rhs.offset, + TEST_WRITE_CONCATENATED("\nOffset:\nExpected output ", lhs.offset, "\nActual output ", rhs.offset, '\n')); + TEST_REQUIRE(lhs.save == rhs.save, + TEST_WRITE_CONCATENATED("\nSave:\nExpected output ", lhs.save, "\nActual output ", rhs.save, '\n')); + TEST_REQUIRE( + lhs.abbrev == rhs.abbrev, + TEST_WRITE_CONCATENATED("\nAbbrev:\nExpected output ", lhs.abbrev, "\nActual output ", rhs.abbrev, '\n')); +} + +/***** ***** TESTS ***** *****/ + +int main(int, const char**) { + using namespace std::literals::chrono_literals; + + // DST starts on the first of March. + const std::chrono::tzdb& tzdb_1 = parse( + R"( +Z Test 0 - LMT 1900 +0 Rule %s + +R Rule 1900 max - Mar 1 2u 1 Summer +R Rule 1900 max - Oct 1 2u 0 Winter +)"); + + const std::chrono::time_zone* tz_1 = tzdb_1.locate_zone("Test"); + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1901y, std::chrono::March, 1d, 2h), + to_sys_seconds(1901y, std::chrono::October, 1d, 2h), + 1h, + 60min, + "Summer"), + tz_1->get_info(to_sys_seconds(1901y, std::chrono::March, 1d, 2h))); + + // The DST start changes from the first of March to the first of April. + const std::chrono::tzdb& tzdb_2 = parse( + R"( +Z Test 0 - LMT 1900 +0 Rule %s + +R Rule 1900 max - Apr 1 2u 1 Summer +R Rule 1900 max - Oct 1 2u 0 Winter +)"); + + const std::chrono::time_zone* tz_2 = tzdb_2.locate_zone("Test"); + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1900y, std::chrono::October, 1d, 2h), + to_sys_seconds(1901y, std::chrono::April, 1d, 2h), + 0s, + 0min, + "Winter"), + tz_2->get_info(to_sys_seconds(1901y, std::chrono::March, 1d, 2h))); + + // Validate when using tz_1 the DST still starts on the first of March. + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1901y, std::chrono::March, 1d, 2h), + to_sys_seconds(1901y, std::chrono::October, 1d, 2h), + 1h, + 60min, + "Summer"), + tz_1->get_info(to_sys_seconds(1901y, std::chrono::March, 1d, 2h))); + + // The zone Test is no longer present + [[maybe_unused]] const std::chrono::tzdb& tzdb_3 = parse("Z Etc/UTC 0 - UTC"); +#ifndef TEST_HAS_NO_EXCEPTIONS + TEST_VALIDATE_EXCEPTION( + std::runtime_error, + [&]([[maybe_unused]] const std::runtime_error& e) { + std::string what = "tzdb: requested time zone not found"; + TEST_LIBCPP_REQUIRE( + e.what() == what, + TEST_WRITE_CONCATENATED("\nExpected exception ", what, "\nActual exception ", e.what(), '\n')); + }, + TEST_IGNORE_NODISCARD tzdb_3.locate_zone("Test")); +#endif // TEST_HAS_NO_EXCEPTIONS + + // Search the zone Test in the original version 1 of the TZDB. + // This database should be unaffected by the removal in version 3. + tz_1 = tzdb_1.locate_zone("Test"); + + // Validate the rules still uses version 1's DST switch in March. + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1901y, std::chrono::March, 1d, 2h), + to_sys_seconds(1901y, std::chrono::October, 1d, 2h), + 1h, + 60min, + "Summer"), + tz_1->get_info(to_sys_seconds(1901y, std::chrono::March, 1d, 2h))); + + return 0; +} diff --git a/libcxx/test/libcxx/transitive_includes/cxx23.csv b/libcxx/test/libcxx/transitive_includes/cxx23.csv index 69429b5bce82..9ae422a31f07 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx23.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx23.csv @@ -80,7 +80,6 @@ chrono cstring chrono ctime chrono cwchar chrono forward_list -chrono initializer_list chrono limits chrono new chrono optional diff --git a/libcxx/test/libcxx/transitive_includes/cxx26.csv b/libcxx/test/libcxx/transitive_includes/cxx26.csv index 69429b5bce82..9ae422a31f07 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx26.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx26.csv @@ -80,7 +80,6 @@ chrono cstring chrono ctime chrono cwchar chrono forward_list -chrono initializer_list chrono limits chrono new chrono optional diff --git a/libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/sys_info.members.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/sys_info.members.pass.cpp new file mode 100644 index 000000000000..2510792c2280 --- /dev/null +++ b/libcxx/test/std/time/time.zone/time.zone.info/time.zone.info.sys/sys_info.members.pass.cpp @@ -0,0 +1,48 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 + +// XFAIL: libcpp-has-no-incomplete-tzdb + +// + +// struct sys_info { +// sys_seconds begin; +// sys_seconds end; +// seconds offset; +// minutes save; +// string abbrev; +// }; + +// Validates whether: +// - The members are present as non-const members. +// - The struct is an aggregate. + +#include +#include +#include + +int main(int, const char**) { + static_assert(std::is_aggregate_v); + + std::chrono::sys_info sys_info{ + .begin = std::chrono::sys_seconds::min(), + .end = std::chrono::sys_seconds::max(), + .offset = std::chrono::seconds(0), + .save = std::chrono::minutes(0), + .abbrev = "UTC"}; + + [[maybe_unused]] std::chrono::sys_seconds& begin = sys_info.begin; + [[maybe_unused]] std::chrono::sys_seconds& end = sys_info.end; + [[maybe_unused]] std::chrono::seconds& offset = sys_info.offset; + [[maybe_unused]] std::chrono::minutes& save = sys_info.save; + [[maybe_unused]] std::string& abbrev = sys_info.abbrev; + + return 0; +} diff --git a/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp new file mode 100644 index 000000000000..2ad408968589 --- /dev/null +++ b/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp @@ -0,0 +1,1374 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: no-filesystem, no-localization, no-tzdb + +// XFAIL: libcpp-has-no-incomplete-tzdb +// XFAIL: availability-tzdb-missing + +// + +// class time_zone; + +// template +// sys_info get_info(const sys_time<_Duration>& time) const; + +// This test uses the system provided database. This makes the test portable, +// but may cause failures when the database information changes. Historic data +// may change if new facts are uncovered, future data may change when regions +// change their time zone or daylight saving time. Most tests will not look in +// the future to attempt to avoid issues. All tests list the data on which they +// are based, this makes debugging easier upon failure; including to see whether +// the provided data has not been changed +// +// +// The data in the tests can be validated by using the zdump tool. For +// example +// zdump -v Asia/Hong_Kong +// show all transistions in the Hong Kong time zone. Or +// zdump -c1970,1980 -v Asia/Hong_Kong +// shows all transitions in Hong Kong between 1970 and 1980. + +#include +#include +#include +#include + +#include "test_macros.h" +#include "assert_macros.h" +#include "concat_macros.h" + +/***** ***** HELPERS ***** *****/ + +[[nodiscard]] static std::chrono::sys_seconds to_sys_seconds( + std::chrono::year year, + std::chrono::month month, + std::chrono::day day, + std::chrono::hours h = std::chrono::hours(0), + std::chrono::minutes m = std::chrono::minutes{0}, + std::chrono::seconds s = std::chrono::seconds{0}) { + std::chrono::year_month_day result{year, month, day}; + + return std::chrono::time_point_cast(static_cast(result)) + h + m + s; +} + +static void assert_equal(const std::chrono::sys_info& lhs, const std::chrono::sys_info& rhs) { + TEST_REQUIRE(lhs.begin == rhs.begin, + TEST_WRITE_CONCATENATED("\nBegin:\nExpected output ", lhs.begin, "\nActual output ", rhs.begin, '\n')); + TEST_REQUIRE(lhs.end == rhs.end, + TEST_WRITE_CONCATENATED("\nEnd:\nExpected output ", lhs.end, "\nActual output ", rhs.end, '\n')); + TEST_REQUIRE( + lhs.offset == rhs.offset, + TEST_WRITE_CONCATENATED("\nOffset:\nExpected output ", lhs.offset, "\nActual output ", rhs.offset, '\n')); + TEST_REQUIRE(lhs.save == rhs.save, + TEST_WRITE_CONCATENATED("\nSave:\nExpected output ", lhs.save, "\nActual output ", rhs.save, '\n')); + TEST_REQUIRE( + lhs.abbrev == rhs.abbrev, + TEST_WRITE_CONCATENATED("\nAbbrev:\nExpected output ", lhs.abbrev, "\nActual output ", rhs.abbrev, '\n')); +} + +static void assert_equal(std::string_view expected, const std::chrono::sys_info& value) { + // Note the output of operator<< is implementation defined, use this + // format to keep the test portable. + std::string result = std::format( + "[{}, {}) {:%T} {:%Q%q} {}", + value.begin, + value.end, + std::chrono::hh_mm_ss{value.offset}, + value.save, + value.abbrev); + + TEST_REQUIRE(expected == result, + TEST_WRITE_CONCATENATED("\nExpected output ", expected, "\nActual output ", result, '\n')); +} + +static void +assert_range(std::string_view expected, const std::chrono::sys_info& begin, const std::chrono::sys_info& end) { + assert_equal(expected, begin); + assert_equal(expected, end); +} + +static void assert_cycle( + std::string_view expected_1, + const std::chrono::sys_info& begin_1, + const std::chrono::sys_info& end_1, + std::string_view expected_2, + const std::chrono::sys_info& begin_2, + const std::chrono::sys_info& end_2 + +) { + assert_range(expected_1, begin_1, end_1); + assert_range(expected_2, begin_2, end_2); +} + +/***** ***** TESTS ***** *****/ + +static void test_gmt() { + // Simple zone always valid, no rule entries, lookup using a link. + // L Etc/GMT GMT + // Z Etc/GMT 0 - GMT + + const std::chrono::time_zone* tz = std::chrono::locate_zone("GMT"); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + std::chrono::sys_seconds::max(), + std::chrono::seconds(0), + std::chrono::minutes(0), + "GMT"), + tz->get_info(std::chrono::sys_seconds::min())); + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + std::chrono::sys_seconds::max(), + std::chrono::seconds(0), + std::chrono::minutes(0), + "GMT"), + tz->get_info(std::chrono::sys_seconds(std::chrono::seconds{0}))); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + std::chrono::sys_seconds::max(), + std::chrono::seconds(0), + std::chrono::minutes(0), + "GMT"), + tz->get_info(std::chrono::sys_seconds::max() - std::chrono::seconds{1})); // max is not valid +} + +static void test_durations() { + // Doesn't test a location, instead tests whether different duration + // specializations work. + const std::chrono::time_zone* tz = std::chrono::locate_zone("GMT"); + + // Using the GMT zone means every call gives the same result. + std::chrono::sys_info expected( + std::chrono::sys_seconds::min(), + std::chrono::sys_seconds::max(), + std::chrono::seconds(0), + std::chrono::minutes(0), + "GMT"); + + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); + assert_equal(expected, tz->get_info(std::chrono::sys_time{})); +} + +static void test_indian_kerguelen() { + // One change, no rules, no dst changes. + + // Z Indian/Kerguelen 0 - -00 1950 + // 5 - +05 + + const std::chrono::time_zone* tz = std::chrono::locate_zone("Indian/Kerguelen"); + + std::chrono::sys_seconds transition = + to_sys_seconds(std::chrono::year(1950), std::chrono::January, std::chrono::day(1)); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), // + transition, // + std::chrono::seconds(0), // + std::chrono::minutes(0), // + "-00"), // + tz->get_info(std::chrono::sys_seconds::min())); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), // + transition, // + std::chrono::seconds(0), // + std::chrono::minutes(0), // + "-00"), // + tz->get_info(transition - std::chrono::seconds{1})); + + assert_equal( + std::chrono::sys_info( + transition, // + std::chrono::sys_seconds::max(), // + std::chrono::hours(5), // + std::chrono::minutes(0), // + "+05"), // + tz->get_info(transition)); +} + +static void test_antarctica_syowa() { + // One change, no rules, no dst changes + // This change uses an ON field with a day number + // + // There don't seem to be rule-less zones that use last day or a + // contrained day + + // Z Antarctica/Syowa 0 - -00 1957 Ja 29 + // 3 - +03 + + const std::chrono::time_zone* tz = std::chrono::locate_zone("Antarctica/Syowa"); + + std::chrono::sys_seconds transition = + to_sys_seconds(std::chrono::year(1957), std::chrono::January, std::chrono::day(29)); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), // + transition, // + std::chrono::seconds(0), // + std::chrono::minutes(0), // + "-00"), // + tz->get_info(std::chrono::sys_seconds::min())); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), // + transition, // + std::chrono::seconds(0), // + std::chrono::minutes(0), // + "-00"), // + tz->get_info(transition - std::chrono::seconds(1))); + + assert_equal( + std::chrono::sys_info( + transition, // + std::chrono::sys_seconds::max(), // + std::chrono::hours(3), // + std::chrono::minutes(0), // + "+03"), // + tz->get_info(transition)); +} + +static void test_asia_hong_kong() { + // A more typical entry, first some hard-coded entires and then at the + // end a rules based entry. This rule is valid for its entire period + // + // Z Asia/Hong_Kong 7:36:42 - LMT 1904 O 30 0:36:42 + // 8 - HKT 1941 Jun 15 3 + // 8 1 HKST 1941 O 1 4 + // 8 0:30 HKWT 1941 D 25 + // 9 - JST 1945 N 18 2 + // 8 HK HK%sT + // + // R HK 1946 o - Ap 21 0 1 S + // R HK 1946 o - D 1 3:30s 0 - + // R HK 1947 o - Ap 13 3:30s 1 S + // R HK 1947 o - N 30 3:30s 0 - + // R HK 1948 o - May 2 3:30s 1 S + // R HK 1948 1952 - O Su>=28 3:30s 0 - + // R HK 1949 1953 - Ap Su>=1 3:30 1 S + // R HK 1953 1964 - O Su>=31 3:30 0 - + // R HK 1954 1964 - Mar Su>=18 3:30 1 S + // R HK 1965 1976 - Ap Su>=16 3:30 1 S + // R HK 1965 1976 - O Su>=16 3:30 0 - + // R HK 1973 o - D 30 3:30 1 S + // R HK 1979 o - May 13 3:30 1 S + // R HK 1979 o - O 21 3:30 0 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Asia/Hong_Kong"); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1904y, std::chrono::October, 29d, 17h), // 7:36:42 - LMT 1904 O 30 0:36:42 + 7h + 36min + 42s, + 0min, + "LMT"), + tz->get_info(std::chrono::sys_seconds::min())); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1904y, std::chrono::October, 29d, 17h), // 7:36:42 - LMT 1904 O 30 0:36:42 + 7h + 36min + 42s, + 0min, + "LMT"), + tz->get_info(to_sys_seconds(1904y, std::chrono::October, 29d, 16h, 59min, 59s))); + + assert_range("[1904-10-29 17:00:00, 1941-06-14 19:00:00) 08:00:00 0min HKT", // 8 - HKT 1941 Jun 15 3 + tz->get_info(to_sys_seconds(1904y, std::chrono::October, 29d, 17h)), + tz->get_info(to_sys_seconds(1941y, std::chrono::June, 14d, 18h, 59min, 59s))); + + assert_range("[1941-06-14 19:00:00, 1941-09-30 19:00:00) 09:00:00 60min HKST", // 8 1 HKST 1941 O 1 4 + tz->get_info(to_sys_seconds(1941y, std::chrono::June, 14d, 19h)), + tz->get_info(to_sys_seconds(1941y, std::chrono::September, 30d, 18h, 59min, 59s))); + + assert_range("[1941-09-30 19:00:00, 1941-12-24 15:30:00) 08:30:00 30min HKWT", // 8 0:30 HKWT 1941 D 25 + tz->get_info(to_sys_seconds(1941y, std::chrono::September, 30d, 19h)), + tz->get_info(to_sys_seconds(1941y, std::chrono::December, 24d, 15h, 29min, 59s))); + + assert_range("[1941-12-24 15:30:00, 1945-11-17 17:00:00) 09:00:00 0min JST", // 9 - JST 1945 N 18 2 + tz->get_info(to_sys_seconds(1941y, std::chrono::December, 24d, 15h, 30min)), + tz->get_info(to_sys_seconds(1945y, std::chrono::November, 17d, 16h, 59min, 59s))); + + assert_range("[1945-11-17 17:00:00, 1946-04-20 16:00:00) 08:00:00 0min HKT", // 8 HK%sT + tz->get_info(to_sys_seconds(1945y, std::chrono::November, 17d, 17h)), + tz->get_info(to_sys_seconds(1946y, std::chrono::April, 20d, 15h, 59min, 59s))); + + assert_cycle( // 8 HK%sT + "[1946-04-20 16:00:00, 1946-11-30 19:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1946y, std::chrono::April, 20d, 16h)), // 1946 o Ap 21 0 1 S + tz->get_info(to_sys_seconds(1946y, std::chrono::November, 30d, 19h, 29min, 59s)), // 1946 o D 1 3:30s 0 - + "[1946-11-30 19:30:00, 1947-04-12 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1946y, std::chrono::November, 30d, 19h, 30min)), // 1946 o D 1 3:30s 0 - + tz->get_info(to_sys_seconds(1947y, std::chrono::April, 12d, 19h, 29min, 59s))); // 1947 o Ap 13 3:30s 1 S + + assert_cycle( // 8 HK%sT + "[1947-04-12 19:30:00, 1947-11-29 19:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1947y, std::chrono::April, 12d, 19h, 30min)), // 1947 o Ap 13 3:30s 1 S + tz->get_info(to_sys_seconds(1947y, std::chrono::November, 29d, 19h, 29min, 59s)), // 1947 o N 30 3:30s 0 - + "[1947-11-29 19:30:00, 1948-05-01 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1947y, std::chrono::November, 29d, 19h, 30min)), // 1947 o N 30 3:30s 0 - + tz->get_info(to_sys_seconds(1948y, std::chrono::May, 1d, 19h, 29min, 59s))); // 1948 o May 2 3:30s 1 S + + assert_cycle( // 8 HK%sT + "[1948-05-01 19:30:00, 1948-10-30 19:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1948y, std::chrono::May, 1d, 19h, 30min)), // 1948 o May 2 3:30s 1 S + tz->get_info(to_sys_seconds(1948y, std::chrono::October, 30d, 19h, 29min, 59s)), // 1948 1952 O Su>=28 3:30s 0 - + "[1948-10-30 19:30:00, 1949-04-02 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1948y, std::chrono::October, 30d, 19h, 30min)), // 1948 1952 O Su>=28 3:30s 0 - + tz->get_info(to_sys_seconds(1949y, std::chrono::April, 2d, 19h, 29min, 59s))); // 1949 1953 Ap Su>=1 3:30 1 S + + assert_cycle( // 8 HK%sT + "[1949-04-02 19:30:00, 1949-10-29 19:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1949y, std::chrono::April, 2d, 19h, 30min)), // 1949 1953 Ap Su>=1 3:30 1 S + tz->get_info(to_sys_seconds(1949y, std::chrono::October, 29d, 19h, 29min, 59s)), // 1948 1952 O Su>=28 3:30s 0 + "[1949-10-29 19:30:00, 1950-04-01 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1949y, std::chrono::October, 29d, 19h, 30min)), // 1948 1952 O Su>=28 3:30s 0 + tz->get_info(to_sys_seconds(1950y, std::chrono::April, 1d, 19h, 29min, 59s))); // 1949 1953 Ap Su>=1 3:30 1 S + + assert_range( + "[1953-10-31 18:30:00, 1954-03-20 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1953y, std::chrono::October, 31d, 18h, 30min)), // 1953 1964 - O Su>=31 3:30 0 - + tz->get_info(to_sys_seconds(1954y, std::chrono::March, 20d, 19h, 29min, 59s))); // 1954 1964 - Mar Su>=18 3:30 1 S + + assert_cycle( // 8 HK%sT + "[1953-04-04 19:30:00, 1953-10-31 18:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1953y, std::chrono::April, 4d, 19h, 30min)), // 1949 1953 Ap Su>=1 3:30 1 S + tz->get_info(to_sys_seconds(1953y, std::chrono::October, 31d, 18h, 29min, 59s)), // 1953 1964 - O Su>=31 3:30 0 - + "[1953-10-31 18:30:00, 1954-03-20 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1953y, std::chrono::October, 31d, 18h, 30min)), // 1953 1964 - O Su>=31 3:30 0 - + tz->get_info(to_sys_seconds(1954y, std::chrono::March, 20d, 19h, 29min, 59s))); // 1954 1964 - Mar Su>=18 3:30 1 S + + assert_cycle( // 8 HK%sT + "[1972-04-15 19:30:00, 1972-10-21 18:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1972y, std::chrono::April, 19d, 19h, 30min)), // 1965 1976 - Ap Su>=16 3:30 1 S + tz->get_info(to_sys_seconds(1972y, std::chrono::October, 21d, 18h, 29min, 59s)), // 1965 1976 - O Su>=16 3:30 0 - + "[1972-10-21 18:30:00, 1973-04-21 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1972y, std::chrono::October, 21d, 18h, 30min)), // 1965 1976 - O Su>=16 3:30 0 - + tz->get_info(to_sys_seconds(1973y, std::chrono::April, 21d, 19h, 29min, 59s))); // 1965 1976 - Ap Su>=16 3:30 1 S + + assert_range( // 8 HK%sT + "[1973-04-21 19:30:00, 1973-10-20 18:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1973y, std::chrono::April, 21d, 19h, 30min)), // 1965 1976 - Ap Su>=16 3:30 1 S + tz->get_info(to_sys_seconds(1973y, std::chrono::October, 20d, 18h, 29min, 59s))); // 1965 1976 - O Su>=16 3:30 0 - + + assert_range( // 8 HK%sT, test "1973 o - D 30 3:30 1 S" + "[1973-10-20 18:30:00, 1973-12-29 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1973y, std::chrono::October, 20d, 18h, 30min)), // 1965 1976 - O Su>=16 3:30 + tz->get_info(to_sys_seconds(1973y, std::chrono::December, 29d, 19h, 29min, 59s))); // 1973 o - D 30 3:30 1 S + + assert_range( // 8 HK%sT + "[1973-12-29 19:30:00, 1974-10-19 18:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1973y, std::chrono::December, 29d, 19h, 30min)), // 1973 o - D 30 3:30 1 S + tz->get_info(to_sys_seconds(1974y, std::chrono::October, 19d, 18h, 29min, 59s))); // 1965 1976 - O Su>=16 3:30 + + assert_range( // 8 HK%sT, between 1973 and 1979 no rule is active so falls back to default + "[1976-04-17 19:30:00, 1976-10-16 18:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1976y, std::chrono::April, 17d, 19h, 30min)), // 1965 1976 - Ap Su>=16 3:30 1 S + tz->get_info(to_sys_seconds(1976y, std::chrono::October, 16d, 18h, 29min, 59s))); // 1965 1976 - O Su>=16 3:30 0 - + + assert_range( // 8 HK%sT, between 1973 and 1979 no rule is active so falls back to default + "[1976-10-16 18:30:00, 1979-05-12 19:30:00) 08:00:00 0min HKT", + tz->get_info(to_sys_seconds(1976y, std::chrono::October, 16d, 18h, 30min)), // 1965 1976 - O Su>=16 3:30 0 - + tz->get_info(to_sys_seconds(1979y, std::chrono::May, 12d, 19h, 29min, 59s))); // 1979 o - May 13 3:30 1 S + + assert_range( // 8 HK%sT + "[1979-05-12 19:30:00, 1979-10-20 18:30:00) 09:00:00 60min HKST", + tz->get_info(to_sys_seconds(1979y, std::chrono::May, 12d, 19h, 30min)), // 1979 o - May 13 3:30 1 S + tz->get_info(to_sys_seconds(1979y, std::chrono::October, 20d, 18h, 29min, 59s))); // 1979 o - O 21 3:30 0 - + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1979y, std::chrono::October, 20d, 18h, 30min), + std::chrono::sys_seconds::max(), + 8h, + std::chrono::minutes(0), + "HKT"), + tz->get_info(to_sys_seconds(1979y, std::chrono::October, 20d, 18h, 30min))); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1979y, std::chrono::October, 20d, 18h, 30min), + std::chrono::sys_seconds::max(), + 8h, + std::chrono::minutes(0), + "HKT"), + tz->get_info(std::chrono::sys_seconds::max() - std::chrono::seconds{1})); // max is not valid +} + +static void test_europe_berlin() { + // A more typical entry, first some hard-coded entires and then at the + // end a rules based entry. This rule is valid for its entire period + // + + // Z Europe/Berlin 0:53:28 - LMT 1893 Ap + // 1 c CE%sT 1945 May 24 2 + // 1 So CE%sT 1946 + // 1 DE CE%sT 1980 + // 1 E CE%sT + // + // R c 1916 o - Ap 30 23 1 S + // R c 1916 o - O 1 1 0 - + // R c 1917 1918 - Ap M>=15 2s 1 S + // R c 1917 1918 - S M>=15 2s 0 - + // R c 1940 o - Ap 1 2s 1 S + // R c 1942 o - N 2 2s 0 - + // R c 1943 o - Mar 29 2s 1 S + // R c 1943 o - O 4 2s 0 - + // R c 1944 1945 - Ap M>=1 2s 1 S + // R c 1944 o - O 2 2s 0 - + // R c 1945 o - S 16 2s 0 - + // R c 1977 1980 - Ap Su>=1 2s 1 S + // R c 1977 o - S lastSu 2s 0 - + // R c 1978 o - O 1 2s 0 - + // R c 1979 1995 - S lastSu 2s 0 - + // R c 1981 ma - Mar lastSu 2s 1 S + // R c 1996 ma - O lastSu 2s 0 - + // + // R So 1945 o - May 24 2 2 M + // R So 1945 o - S 24 3 1 S + // R So 1945 o - N 18 2s 0 - + // + // R DE 1946 o - Ap 14 2s 1 S + // R DE 1946 o - O 7 2s 0 - + // R DE 1947 1949 - O Su>=1 2s 0 - + // R DE 1947 o - Ap 6 3s 1 S + // R DE 1947 o - May 11 2s 2 M + // R DE 1947 o - Jun 29 3 1 S + // R DE 1948 o - Ap 18 2s 1 S + // R DE 1949 o - Ap 10 2s 1 S + // + // R E 1977 1980 - Ap Su>=1 1u 1 S + // R E 1977 o - S lastSu 1u 0 - + // R E 1978 o - O 1 1u 0 - + // R E 1979 1995 - S lastSu 1u 0 - + // R E 1981 ma - Mar lastSu 1u 1 S + // R E 1996 ma - O lastSu 1u 0 - + // + // Note the European Union decided to stop the seasonal change in + // 2021. In 2023 seasonal changes are still in effect. + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Europe/Berlin"); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1893y, std::chrono::March, 31d, 23h, 6min, 32s), // 0:53:28 - LMT 1893 Ap + 53min + 28s, + 0min, + "LMT"), + tz->get_info(std::chrono::sys_seconds::min())); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1893y, std::chrono::March, 31d, 23h, 6min, 32s), // 0:53:28 - LMT 1893 Ap + 53min + 28s, + 0min, + "LMT"), + tz->get_info(to_sys_seconds(1893y, std::chrono::March, 31d, 23h, 6min, 31s))); + + assert_range( + // 1 CE%sT before 1916 o - Ap 30 23 1 S + "[1893-03-31 23:06:32, 1916-04-30 22:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1893y, std::chrono::March, 31d, 23h, 6min, 32s)), + tz->get_info(to_sys_seconds(1916y, std::chrono::April, 30d, 21h, 59min, 59s))); + + assert_cycle( + // 1 CE%sT + "[1916-04-30 22:00:00, 1916-09-30 23:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1916y, std::chrono::April, 30d, 22h)), // 1916 o - Ap 30 23 1 S + tz->get_info(to_sys_seconds(1916y, std::chrono::September, 30d, 22h, 59min, 59s)), // o - O 1 1 0 - + "[1916-09-30 23:00:00, 1917-04-16 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1916y, std::chrono::September, 30d, 23h)), // o - O 1 1 0 - + tz->get_info(to_sys_seconds(1917y, std::chrono::April, 16d, 0h, 59min, 59s))); // 1917 1918 - Ap M>=15 2s 1 S + + assert_cycle( + // 1 CE%sT + "[1917-04-16 01:00:00, 1917-09-17 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1917y, std::chrono::April, 16d, 1h)), // 1917 1918 Ap M>=15 2s 1 S + tz->get_info(to_sys_seconds(1917y, std::chrono::September, 17d, 0h, 59min, 59s)), // 1917 1918 S M>=15 2s 0 - + "[1917-09-17 01:00:00, 1918-04-15 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1917y, std::chrono::September, 17d, 1h)), // 1917 1918 S M>=15 2s 0 - + tz->get_info(to_sys_seconds(1918y, std::chrono::April, 15d, 0h, 59min, 59s))); // 1917 1918 Ap M>=15 2s 1 S + + assert_cycle( + // 1 CE%sT (The cycle is more than 1 year) + "[1918-04-15 01:00:00, 1918-09-16 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1918y, std::chrono::April, 15d, 1h)), // 1917 1918 Ap M>=15 2s 1 S + tz->get_info(to_sys_seconds(1918y, std::chrono::September, 16d, 0h, 59min, 59s)), // 1917 1918 S M>=15 2s 0 - + "[1918-09-16 01:00:00, 1940-04-01 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1918y, std::chrono::September, 16d, 1h)), // 1917 1918 S M>=15 2s 0 - + tz->get_info(to_sys_seconds(1940y, std::chrono::April, 1d, 0h, 59min, 59s))); // 1940 o Ap 1 2s 1 S + + assert_cycle( + // 1 CE%sT (The cycle is more than 1 year) + "[1940-04-01 01:00:00, 1942-11-02 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1940y, std::chrono::April, 1d, 1h)), // 1940 o Ap 1 2s 1 S + tz->get_info(to_sys_seconds(1942y, std::chrono::November, 2d, 0h, 59min, 59s)), // 1942 o N 2 2s 0 - + "[1942-11-02 01:00:00, 1943-03-29 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1942y, std::chrono::November, 2d, 1h)), // 1942 o N 2 2s 0 - + tz->get_info(to_sys_seconds(1943y, std::chrono::March, 29d, 0h, 59min, 59s))); // 1943 o Mar 29 2s 1 S + + assert_range( + // Here the zone changes from c (C-Eur) to So (SovietZone). + // The rule c ends on 1945-09-16, instead it ends at the zone change date/time + // There is a tricky part in the time + // "1 c CE%sT" has an offset of 1 at the moment the rule + // ends there is a save of 60 minutes. This means the + // local offset to UTC is 2 hours. The rule ends at + // 1945-05-24 02:00:00 local time, which is + // 1945-05-24 00:00:00 UTC. + "[1945-04-02 01:00:00, 1945-05-24 00:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1945y, std::chrono::April, 2d, 1h)), // 1 CE%sT & 1945 Ap M>=1 2s 1 S + tz->get_info(to_sys_seconds(1945y, std::chrono::May, 23d, 23h, 59min, 59s))); // 1 c CE%sT & 1945 May 24 2 + + assert_range( // -- + "[1945-05-24 00:00:00, 1945-09-24 00:00:00) 03:00:00 120min CEMT", + tz->get_info(to_sys_seconds(1945y, std::chrono::May, 24d)), // 1 c CE%sT & 1945 May 24 2 + tz->get_info(to_sys_seconds(1945y, std::chrono::September, 23d, 23h, 59min, 59s))); // 1945 o S 24 3 1 S + + assert_range( + // 1 c CE%sT 1945 May 24 2 + "[1945-09-24 00:00:00, 1945-11-18 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1945y, std::chrono::September, 24d)), // 1945 o S 24 3 1 S + tz->get_info(to_sys_seconds(1945y, std::chrono::November, 18d, 0h, 59min, 59s))); // 1945 o N 18 2s 0 - + assert_range( // -- + // Merges 2 continuations + "[1945-11-18 01:00:00, 1946-04-14 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1945y, std::chrono::November, 18d, 1h)), // 1 c CE%sT & 1945 o N 18 2s 0 - + tz->get_info(to_sys_seconds(1946y, std::chrono::April, 14d, 0h, 59min, 59s))); // 1 So CE%sT & 1946 o Ap 14 2s 1 S + + assert_range( + // 1 DE CE%sT 1980 + "[1946-04-14 01:00:00, 1946-10-07 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1946y, std::chrono::April, 14d, 1h)), // 1946 o Ap 14 2s 1 S + tz->get_info(to_sys_seconds(1946y, std::chrono::October, 7d, 0h, 59min, 59s))); // 1946 o O 7 2s 0 - + + // Note 1947 is an interesting year with 4 rules + // R DE 1947 1949 - O Su>=1 2s 0 - + // R DE 1947 o - Ap 6 3s 1 S + // R DE 1947 o - May 11 2s 2 M + // R DE 1947 o - Jun 29 3 1 S + assert_range( + // 1 DE CE%sT 1980 + "[1946-10-07 01:00:00, 1947-04-06 02:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1946y, std::chrono::October, 7d, 1h)), // 1946 o O 7 2s 0 - + tz->get_info(to_sys_seconds(1947y, std::chrono::April, 6d, 1h, 59min, 59s))); // 1947 o Ap 6 3s 1 S + + assert_range( + // 1 DE CE%sT 1980 + "[1947-04-06 02:00:00, 1947-05-11 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1947y, std::chrono::April, 6d, 2h)), // 1947 o Ap 6 3s 1 S + tz->get_info(to_sys_seconds(1947y, std::chrono::May, 11d, 0h, 59min, 59s))); // 1947 o May 11 2s 2 M + + assert_range( + // 1 DE CE%sT 1980 + "[1947-05-11 01:00:00, 1947-06-29 00:00:00) 03:00:00 120min CEMT", + tz->get_info(to_sys_seconds(1947y, std::chrono::May, 11d, 1h)), // 1947 o May 11 2s 2 M + tz->get_info(to_sys_seconds(1947y, std::chrono::June, 28d, 23h, 59min, 59s))); // 1947 o Jun 29 3 1 S + + assert_cycle( + // 1 DE CE%sT 1980 + "[1947-06-29 00:00:00, 1947-10-05 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1947y, std::chrono::June, 29d)), // 1947 o Jun 29 3 1 S + tz->get_info(to_sys_seconds(1947y, std::chrono::October, 5d, 0h, 59min, 59s)), // 1947 1949 O Su>=1 2s 0 - + "[1947-10-05 01:00:00, 1948-04-18 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1947y, std::chrono::October, 5d, 1h)), // 1947 1949 O Su>=1 2s 0 - + tz->get_info(to_sys_seconds(1948y, std::chrono::April, 18d, 0h, 59min, 59s))); // 1948 o Ap 18 2s 1 S + + assert_cycle( + // 1 DE CE%sT 1980 + "[1948-04-18 01:00:00, 1948-10-03 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(1948y, std::chrono::April, 18d, 1h)), // 1948 o Ap 18 2s 1 S + tz->get_info(to_sys_seconds(1948y, std::chrono::October, 3d, 0h, 59min, 59s)), // 1947 1949 O Su>=1 2s 0 - + "[1948-10-03 01:00:00, 1949-04-10 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1948y, std::chrono::October, 3d, 1h)), // 1947 1949 O Su>=1 2s 0 - + tz->get_info(to_sys_seconds(1949y, std::chrono::April, 10d, 0h, 59min, 59s))); // 1949 o Ap 10 2s 1 S + + assert_cycle( // Note the end time is in a different continuation. + "[1949-04-10 01:00:00, 1949-10-02 01:00:00) 02:00:00 60min CEST", // 1 DE CE%sT 1980 + tz->get_info(to_sys_seconds(1949y, std::chrono::April, 10d, 1h)), // 1949 o Ap 10 2s 1 S + tz->get_info(to_sys_seconds(1949y, std::chrono::October, 2d, 0h, 59min, 59s)), // 1947 1949 O Su>=1 2s 0 - + "[1949-10-02 01:00:00, 1980-04-06 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(1949y, std::chrono::October, 2d, 1h)), // 1947 1949 O Su>=1 2s 0 - + tz->get_info( // 1 E CE%sT + to_sys_seconds(1980y, std::chrono::April, 6d, 0h, 59min, 59s))); // 1977 1980 Ap Su>=1 1u 1 S + + assert_cycle( + // 1 E CE%sT + "[2020-03-29 01:00:00, 2020-10-25 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(2020y, std::chrono::March, 29d, 1h)), // 1981 ma Mar lastSu 1u 1 S + tz->get_info(to_sys_seconds(2020y, std::chrono::October, 25d, 0h, 59min, 59s)), // 1996 ma O lastSu 1u 0 - + "[2020-10-25 01:00:00, 2021-03-28 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(2020y, std::chrono::October, 25d, 1h)), // 1996 ma O lastSu 1u 0 - + tz->get_info(to_sys_seconds(2021y, std::chrono::March, 28d, 0h, 59min, 59s))); // 1981 ma Mar lastSu 1u 1 S + + assert_cycle( + // 1 E CE%sT + "[2021-03-28 01:00:00, 2021-10-31 01:00:00) 02:00:00 60min CEST", + tz->get_info(to_sys_seconds(2021y, std::chrono::March, 28d, 1h)), // 1981 ma Mar lastSu 1u 1 S + tz->get_info(to_sys_seconds(2021y, std::chrono::October, 31d, 0h, 59min, 59s)), // 1996 ma O lastSu 1u 0 - + "[2021-10-31 01:00:00, 2022-03-27 01:00:00) 01:00:00 0min CET", + tz->get_info(to_sys_seconds(2021y, std::chrono::October, 31d, 1h)), // 1996 ma O lastSu 1u 0 - + tz->get_info(to_sys_seconds(2022y, std::chrono::March, 27d, 0h, 59min, 59s))); // 1981 ma Mar lastSu 1u 1 S +} + +static void test_america_st_johns() { + // A more typical entry, + // Uses letters both when DST is ative and not and has multiple + // letters. Uses negetive offsets. + // Switches several times between their own and Canadian rules + // Switches the stdoff from -3:30:52 to -3:30 while observing the same rule + + // Z America/St_Johns -3:30:52 - LMT 1884 + // -3:30:52 j N%sT 1918 + // -3:30:52 C N%sT 1919 + // -3:30:52 j N%sT 1935 Mar 30 + // -3:30 j N%sT 1942 May 11 + // -3:30 C N%sT 1946 + // -3:30 j N%sT 2011 N + // -3:30 C N%sT + // + // R j 1917 o - Ap 8 2 1 D + // R j 1917 o - S 17 2 0 S + // R j 1919 o - May 5 23 1 D + // R j 1919 o - Au 12 23 0 S + // R j 1920 1935 - May Su>=1 23 1 D + // R j 1920 1935 - O lastSu 23 0 S + // R j 1936 1941 - May M>=9 0 1 D + // R j 1936 1941 - O M>=2 0 0 S + // R j 1946 1950 - May Su>=8 2 1 D + // R j 1946 1950 - O Su>=2 2 0 S + // R j 1951 1986 - Ap lastSu 2 1 D + // R j 1951 1959 - S lastSu 2 0 S + // R j 1960 1986 - O lastSu 2 0 S + // R j 1987 o - Ap Su>=1 0:1 1 D + // R j 1987 2006 - O lastSu 0:1 0 S + // R j 1988 o - Ap Su>=1 0:1 2 DD + // R j 1989 2006 - Ap Su>=1 0:1 1 D + // R j 2007 2011 - Mar Su>=8 0:1 1 D + // R j 2007 2010 - N Su>=1 0:1 0 S + // + // R C 1918 o - Ap 14 2 1 D + // R C 1918 o - O 27 2 0 S + // R C 1942 o - F 9 2 1 W + // R C 1945 o - Au 14 23u 1 P + // R C 1945 o - S 30 2 0 S + // R C 1974 1986 - Ap lastSu 2 1 D + // R C 1974 2006 - O lastSu 2 0 S + // R C 1987 2006 - Ap Su>=1 2 1 D + // R C 2007 ma - Mar Su>=8 2 1 D + // R C 2007 ma - N Su>=1 2 0 S + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/St_Johns"); + + assert_equal( // -- + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1884y, std::chrono::January, 1d, 3h, 30min, 52s), // -3:30:52 - LMT 1884 + -(3h + 30min + 52s), + 0min, + "LMT"), + tz->get_info(std::chrono::sys_seconds::min())); + + assert_equal( // -- + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1884y, std::chrono::January, 1d, 3h, 30min, 52s), // -3:30:52 - LMT 1884 + -(3h + 30min + 52s), + 0min, + "LMT"), + tz->get_info(to_sys_seconds(1884y, std::chrono::January, 1d, 3h, 30min, 51s))); + + assert_range( // -3:30:52 j N%sT 1918 + "[1884-01-01 03:30:52, 1917-04-08 05:30:52) -03:30:52 0min NST", + tz->get_info(to_sys_seconds(1884y, std::chrono::January, 1d, 3h, 30min, 52s)), // no rule active + tz->get_info(to_sys_seconds(1917y, std::chrono::April, 8d, 5h, 30min, 51s))); // 1917 o Ap 8 2 1 D + + assert_range( // -3:30:52 j N%sT 1918 + "[1917-04-08 05:30:52, 1917-09-17 04:30:52) -02:30:52 60min NDT", + tz->get_info(to_sys_seconds(1917y, std::chrono::April, 8d, 5h, 30min, 52s)), // 1917 o Ap 8 2 1 D + tz->get_info(to_sys_seconds(1917y, std::chrono::September, 17d, 4h, 30min, 51s))); // 1917 o S 17 2 0 S + + assert_range("[1917-09-17 04:30:52, 1918-04-14 05:30:52) -03:30:52 0min NST", + tz->get_info( // -3:30:52 j N%sT 1918 + to_sys_seconds(1917y, std::chrono::September, 17d, 4h, 30min, 52s)), // 1917 o S 17 2 0 S + tz->get_info( // -3:30:52 C N%sT 1919 + to_sys_seconds(1918y, std::chrono::April, 14d, 5h, 30min, 51s))); // 1918 o Ap 14 2 1 D + + assert_range( // -3:30:52 C N%sT 1919 + "[1918-04-14 05:30:52, 1918-10-27 04:30:52) -02:30:52 60min NDT", + tz->get_info(to_sys_seconds(1918y, std::chrono::April, 14d, 5h, 30min, 52s)), // 1918 o Ap 14 2 1 D + tz->get_info(to_sys_seconds(1918y, std::chrono::October, 27d, 4h, 30min, 51s))); // 1918 o O 27 2 0 S + + assert_range("[1918-10-27 04:30:52, 1919-05-06 02:30:52) -03:30:52 0min NST", + tz->get_info( // -3:30:52 C N%sT 1919 + to_sys_seconds(1918y, std::chrono::October, 27d, 4h, 30min, 52s)), // 1918 o O 27 2 0 S + tz->get_info( // -3:30:52 j N%sT 1935 Mar 30 + to_sys_seconds(1919y, std::chrono::May, 6d, 2h, 30min, 51s))); // 1919 o May 5 23 1 D + + assert_range( // -3:30:52 j N%sT 1935 Mar 30 + "[1934-10-29 01:30:52, 1935-03-30 03:30:52) -03:30:52 0min NST", + tz->get_info(to_sys_seconds(1934y, std::chrono::October, 29d, 1h, 30min, 52s)), // 1920 1935 O lastSu 23 0 S + tz->get_info(to_sys_seconds(1935y, std::chrono::March, 30d, 3h, 30min, 51s))); // 1920 1935 May Su>=1 23 1 D + + assert_range( // -3:30 j N%sT 1942 May 11 + // Changed the stdoff while the same rule remains active. + "[1935-03-30 03:30:52, 1935-05-06 02:30:00) -03:30:00 0min NST", + tz->get_info(to_sys_seconds(1935y, std::chrono::March, 30d, 3h, 30min, 52s)), // 1920 1935 O lastSu 23 0 S + tz->get_info(to_sys_seconds(1935y, std::chrono::May, 6d, 2h, 29min, 59s))); // 1920 1935 May Su>=1 23 1 D + + assert_range( // -3:30 j N%sT 1942 May 11 + "[1935-05-06 02:30:00, 1935-10-28 01:30:00) -02:30:00 60min NDT", + tz->get_info(to_sys_seconds(1935y, std::chrono::May, 6d, 2h, 30min, 0s)), // 1920 1935 May Su>=1 23 1 D + tz->get_info(to_sys_seconds(1935y, std::chrono::October, 28d, 1h, 29min, 59s))); // 1920 1935 O lastSu 23 0 S + + assert_range( // -3:30 j N%sT 1942 May 11 + "[1941-10-06 02:30:00, 1942-05-11 03:30:00) -03:30:00 0min NST", + tz->get_info(to_sys_seconds(1941y, std::chrono::October, 6d, 2h, 30min, 0s)), // 1936 1941 O M>=2 0 0 S + tz->get_info(to_sys_seconds(1942y, std::chrono::May, 11d, 3h, 29min, 59s))); // 1946 1950 May Su>=8 2 1 D + + assert_range( // -3:30 C N%sT 1946 + "[1942-05-11 03:30:00, 1945-08-14 23:00:00) -02:30:00 60min NWT", + tz->get_info(to_sys_seconds(1942y, std::chrono::May, 11d, 3h, 30min, 0s)), // 1942 o F 9 2 1 W + tz->get_info(to_sys_seconds(1945y, std::chrono::August, 14d, 22h, 59min, 59s))); // 1945 o Au 14 23u 1 P + + assert_range( // -3:30 C N%sT 1946 + "[1945-08-14 23:00:00, 1945-09-30 04:30:00) -02:30:00 60min NPT", + tz->get_info(to_sys_seconds(1945y, std::chrono::August, 14d, 23h, 0min, 0s)), // 1945 o Au 14 23u 1 P + tz->get_info(to_sys_seconds(1945y, std::chrono::September, 30d, 4h, 29min, 59s))); // 1945 o S 30 2 0 S + + assert_range( + "[1945-09-30 04:30:00, 1946-05-12 05:30:00) -03:30:00 0min NST", + tz->get_info( + to_sys_seconds(1945y, std::chrono::September, 30d, 4h, 30min, 0s)), // -3:30 C N%sT 1946 & 945 o S 30 2 0 S + tz->get_info(to_sys_seconds( + 1946y, std::chrono::May, 12d, 5h, 29min, 59s))); // -3:30 j N%sT 2011 N & 1946 1950 May Su>=8 2 1 D + + assert_range( // -3:30 j N%sT 2011 N + "[1988-04-03 03:31:00, 1988-10-30 01:31:00) -01:30:00 120min NDDT", + tz->get_info(to_sys_seconds(1988y, std::chrono::April, 3d, 3h, 31min, 0s)), // 1988 o Ap Su>=1 0:1 2 DD + tz->get_info(to_sys_seconds(1988y, std::chrono::October, 30d, 1h, 30min, 59s))); // 1987 2006 O lastSu 0:1 0 S + + assert_range("[2011-03-13 03:31:00, 2011-11-06 04:30:00) -02:30:00 60min NDT", + tz->get_info( // -3:30 j N%sT 2011 N + to_sys_seconds(2011y, std::chrono::March, 13d, 3h, 31min, 0s)), // 2007 2011 Mar Su>=8 0:1 1 D + tz->get_info( // -3:30 C N%sT + to_sys_seconds(2011y, std::chrono::November, 6d, 04h, 29min, 59s))); // 2007 ma N Su>=1 2 0 S +} + +static void test_get_at_standard_time_universal() { + // Z Asia/Barnaul 5:35 - LMT 1919 D 10 + // ... + // 7 R +07/+08 1995 May 28 + // 6 R +06/+07 2011 Mar 27 2s + // ... + // + // ... + // R R 1985 2010 - Mar lastSu 2s 1 S + // R R 1996 2010 - O lastSu 2s 0 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Asia/Barnaul"); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(2010y, std::chrono::October, 30d, 20h), + to_sys_seconds(2011y, std::chrono::March, 26d, 20h), + 6h, + 0min, + "+06"), + tz->get_info(to_sys_seconds(2010y, std::chrono::October, 31d, 10h))); +} + +static void test_get_at_standard_time_standard() { + // Z Africa/Bissau -1:2:20 - LMT 1912 Ja 1 1u + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Africa/Bissau"); + + assert_equal( + std::chrono::sys_info( + std::chrono::sys_seconds::min(), + to_sys_seconds(1912y, std::chrono::January, 1d, 1h), + -(1h + 2min + 20s), + 0min, + "LMT"), + tz->get_info(std::chrono::sys_seconds::min())); +} + +static void test_get_at_save_universal() { + // Z America/Tijuana -7:48:4 - LMT 1922 Ja 1 0:11:56 + // -7 - MST 1924 + // -8 - PST 1927 Jun 10 23 + // -7 - MST 1930 N 15 + // -8 - PST 1931 Ap + // -8 1 PDT 1931 S 30 + // -8 - PST 1942 Ap 24 + // -8 1 PWT 1945 Au 14 23u + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Tijuana"); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1942y, std::chrono::April, 24d, 8h), + to_sys_seconds(1945y, std::chrono::August, 14d, 23h), + -7h, + 60min, + "PWT"), + tz->get_info(to_sys_seconds(1942y, std::chrono::April, 24d, 8h))); +} + +static void test_get_at_rule_standard() { + // Z Antarctica/Macquarie 0 - -00 1899 N + // 10 - AEST 1916 O 1 2 + // 10 1 AEDT 1917 F + // 10 AU AE%sT 1919 Ap 1 0s + // ... + // + // R AU 1917 o - Ja 1 2s 1 D + // R AU 1917 o - Mar lastSu 2s 0 S + // R AU 1942 o - Ja 1 2s 1 D + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Antarctica/Macquarie"); + + // Another rule where the S propagates? + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1916y, std::chrono::September, 30d, 16h), + to_sys_seconds(1917y, std::chrono::March, 24d, 16h), + 11h, + 60min, + "AEDT"), + tz->get_info(to_sys_seconds(1916y, std::chrono::September, 30d, 16h))); +} + +static void test_get_at_rule_universal() { + // Z America/Nuuk -3:26:56 - LMT 1916 Jul 28 + // -3 - -03 1980 Ap 6 2 + // -3 E -03/-02 2023 O 29 1u + // -2 E -02/-01 + // + // R E 1977 1980 - Ap Su>=1 1u 1 S + // R E 1977 o - S lastSu 1u 0 - + // R E 1978 o - O 1 1u 0 - + // R E 1979 1995 - S lastSu 1u 0 - + // R E 1981 ma - Mar lastSu 1u 1 S + // R E 1996 ma - O lastSu 1u 0 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Nuuk"); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1980y, std::chrono::April, 6d, 5h), + to_sys_seconds(1980y, std::chrono::September, 28d, 1h), + -2h, + 60min, + "-02"), + tz->get_info(to_sys_seconds(1980y, std::chrono::April, 6d, 5h))); +} + +static void test_format_with_alternatives_west() { + // Z America/Nuuk -3:26:56 - LMT 1916 Jul 28 + // -3 - -03 1980 Ap 6 2 + // -3 E -03/-02 2023 O 29 1u + // -2 E -02/-01 + // + // ... + // R E 1981 ma - Mar lastSu 1u 1 S + // R E 1996 ma - O lastSu 1u 0 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Nuuk"); + + assert_cycle( // -3 E -03/-02 + "[2019-10-27 01:00:00, 2020-03-29 01:00:00) -03:00:00 0min -03", + tz->get_info(to_sys_seconds(2019y, std::chrono::October, 27d, 1h)), // 1981 ma Mar lastSu 1u 1 S + tz->get_info(to_sys_seconds(2020y, std::chrono::March, 29d, 0h, 59min, 59s)), // 1996 ma O lastSu 1u 0 - + "[2020-03-29 01:00:00, 2020-10-25 01:00:00) -02:00:00 60min -02", + tz->get_info(to_sys_seconds(2020y, std::chrono::March, 29d, 1h)), // 1996 ma O lastSu 1u 0 - + tz->get_info(to_sys_seconds(2020y, std::chrono::October, 25d, 0h, 59min, 59s))); // 1981 ma Mar lastSu 1u 1 S +} + +static void test_format_with_alternatives_east() { + // Z Asia/Barnaul 5:35 - LMT 1919 D 10 + // ... + // 6 R +06/+07 2011 Mar 27 2s + // ... + // + // ... + // R R 1985 2010 - Mar lastSu 2s 1 S + // R R 1996 2010 - O lastSu 2s 0 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Asia/Barnaul"); + + assert_cycle( // 6 R +06/+07 2011 Mar 27 2s + "[2000-03-25 20:00:00, 2000-10-28 20:00:00) 07:00:00 60min +07", + tz->get_info(to_sys_seconds(2000y, std::chrono::March, 25d, 20h)), // 1985 2010 Mar lastSu 2s 1 S + tz->get_info(to_sys_seconds(2000y, std::chrono::October, 28d, 19h, 59min, 59s)), // 1996 2010 O lastSu 2s 0 - + "[2000-10-28 20:00:00, 2001-03-24 20:00:00) 06:00:00 0min +06", + tz->get_info(to_sys_seconds(2000y, std::chrono::October, 28d, 20h)), // 1996 2010 O lastSu 2s 0 - + tz->get_info(to_sys_seconds(2001y, std::chrono::March, 24d, 19h, 59min, 59s))); // 1985 2010 Mar lastSu 2s 1 S +} + +static void test_africa_algiers() { + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Africa/Algiers"); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1977y, std::chrono::October, 20d, 23h), + to_sys_seconds(1978y, std::chrono::March, 24d), + 1h, + std::chrono::minutes(0), + "CET"), + tz->get_info(to_sys_seconds(1977y, std::chrono::October, 20d, 23h))); + + assert_range("[1977-05-06 00:00:00, 1977-10-20 23:00:00) 01:00:00 60min WEST", // 0 d WE%sT 1977 O 21 + tz->get_info(to_sys_seconds(1977y, std::chrono::May, 6d)), + tz->get_info(to_sys_seconds(1977y, std::chrono::October, 20d, 22h, 59min, 59s))); + + assert_range("[1977-10-20 23:00:00, 1978-03-24 00:00:00) 01:00:00 0min CET", // 1 d CE%sT 1979 O 26 + tz->get_info(to_sys_seconds(1977y, std::chrono::October, 20d, 23h)), + tz->get_info(to_sys_seconds(1978y, std::chrono::March, 23d, 23h, 59min, 59s))); +} + +static void test_africa_casablanca() { + // Z Africa/Casablanca -0:30:20 - LMT 1913 O 26 + // 0 M +00/+01 1984 Mar 16 + // 1 - +01 1986 + // 0 M +00/+01 2018 O 28 3 + // 1 M +01/+00 + // + // ... + // R M 2013 2018 - O lastSu 3 0 - + // R M 2014 2018 - Mar lastSu 2 1 - + // R M 2014 o - Jun 28 3 0 - + // R M 2014 o - Au 2 2 1 - + // R M 2015 o - Jun 14 3 0 - + // R M 2015 o - Jul 19 2 1 - + // R M 2016 o - Jun 5 3 0 - + // R M 2016 o - Jul 10 2 1 - + // R M 2017 o - May 21 3 0 - + // R M 2017 o - Jul 2 2 1 - + // R M 2018 o - May 13 3 0 - + // R M 2018 o - Jun 17 2 1 - + // R M 2019 o - May 5 3 -1 - + // R M 2019 o - Jun 9 2 0 - + // R M 2020 o - Ap 19 3 -1 - + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Africa/Casablanca"); + + assert_range("[2018-06-17 02:00:00, 2018-10-28 02:00:00) 01:00:00 60min +01", + tz->get_info(to_sys_seconds(2018y, std::chrono::June, 17d, 2h)), + tz->get_info(to_sys_seconds(2018y, std::chrono::October, 28d, 1h, 59min, 59s))); + + assert_range("[2018-10-28 02:00:00, 2019-05-05 02:00:00) 01:00:00 0min +01", + tz->get_info( // 1 M +01/+00 & R M 2018 o - Jun 17 2 1 - + to_sys_seconds(2018y, std::chrono::October, 28d, 2h)), + tz->get_info( // 1 M +01/+00 & R M 2019 o - May 5 3 -1 - + to_sys_seconds(2019y, std::chrono::May, 5d, 1h, 59min, 59s))); + + // 1 M +01/+00 + // Note the SAVE contains a negative value + assert_range("[2019-05-05 02:00:00, 2019-06-09 02:00:00) 00:00:00 -60min +00", + tz->get_info(to_sys_seconds(2019y, std::chrono::May, 5d, 2h)), // R M 2019 o - May 5 3 -1 - + tz->get_info(to_sys_seconds(2019y, std::chrono::June, 9d, 1h, 59min, 59s))); // R M 2019 o - Jun 9 2 0 - + + assert_range("[2019-06-09 02:00:00, 2020-04-19 02:00:00) 01:00:00 0min +01", + tz->get_info( // 1 M +01/+00 & R M 2019 o - Jun 9 2 0 - + to_sys_seconds(2019y, std::chrono::June, 9d, 2h)), + tz->get_info( // 1 M +01/+00 & R M 2020 o - Ap 19 3 -1 - + to_sys_seconds(2020y, std::chrono::April, 19d, 1h, 59min, 59s))); // +} + +static void test_africa_ceuta() { + // Z Africa/Ceuta -0:21:16 - LMT 1900 D 31 23:38:44 + // 0 - WET 1918 May 6 23 + // 0 1 WEST 1918 O 7 23 + // 0 - WET 1924 + // 0 s WE%sT 1929 + // 0 - WET 1967 + // 0 Sp WE%sT 1984 Mar 16 + // 1 - CET 1986 + // 1 E CE%sT + // + // ... + // R s 1926 o - Ap 17 23 1 S + // R s 1926 1929 - O Sa>=1 24s 0 - + // R s 1927 o - Ap 9 23 1 S + // R s 1928 o - Ap 15 0 1 S + // R s 1929 o - Ap 20 23 1 S + // R s 1937 o - Jun 16 23 1 S + // ... + // + // R Sp 1967 o - Jun 3 12 1 S + // R Sp 1967 o - O 1 0 0 - + // R Sp 1974 o - Jun 24 0 1 S + // R Sp 1974 o - S 1 0 0 - + // R Sp 1976 1977 - May 1 0 1 S + // R Sp 1976 o - Au 1 0 0 - + // R Sp 1977 o - S 28 0 0 - + // R Sp 1978 o - Jun 1 0 1 S + // R Sp 1978 o - Au 4 0 0 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Africa/Ceuta"); + + assert_range( + + "[1928-10-07 00:00:00, 1967-06-03 12:00:00) 00:00:00 0min WET", + tz->get_info(to_sys_seconds(1928y, std::chrono::October, 7d)), // 0 s WE%sT 1929 & 1926 1929 O Sa>=1 24s 0 - + tz->get_info( // No transitions in "0 - WET 1967" + to_sys_seconds(1967y, std::chrono::June, 3d, 11h, 59min, 59s))); // 0 - WET 1967 & 1967 o Jun 3 12 1 S +} + +static void test_africa_freetown() { + // Z Africa/Freetown -0:53 - LMT 1882 + // -0:53 - FMT 1913 Jul + // -1 SL %s 1939 S 5 + // -1 - -01 1941 D 6 24 + // 0 - GMT + // + // R SL 1932 o - D 1 0 0:20 -0040 + // R SL 1933 1938 - Mar 31 24 0 -01 + // R SL 1933 1939 - Au 31 24 0:20 -0040 + // R SL 1939 o - May 31 24 0 -01 + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Africa/Freetown"); + + // When a continuation has a named rule, the tranisition time determined by + // the active rule can be wrong. The next continuation may set the clock to an + // earlier time. This is tested for San Luis. This tests the rule is not used + // when the rule is not a named rule. + // + // Fixes: + // Expected output [1882-01-01 00:53:00, 1913-07-01 00:53:00) -00:53:00 0min FMT + // Actual output [1882-01-01 00:53:00, 1913-07-01 00:46:00) -00:53:00 0min FMT + + assert_range("[1882-01-01 00:53:00, 1913-07-01 00:53:00) -00:53:00 0min FMT", + tz->get_info(to_sys_seconds(1882y, std::chrono::January, 1d, 0h, 53min)), // -0:53 - FMT 1913 Jul + tz->get_info( // -1 SL %s 1939 S 5 & before first rule + to_sys_seconds(1913y, std::chrono::July, 1d, 0h, 52min, 59s))); + + // Tests whether the "-1 SL %s 1939 S 5" until gets the proper local time + // adjustment. + assert_range("[1939-09-01 01:00:00, 1939-09-05 00:40:00) -00:40:00 20min -0040", + tz->get_info( // -1 SL %s 1939 S 5 & R SL 1933 1939 - Au 31 24 0:20 -0040 + to_sys_seconds(1939y, std::chrono::September, 1d, 1h)), + tz->get_info( // -1 - -01 1941 D 6 24 + to_sys_seconds(1939y, std::chrono::September, 5d, 0h, 39min, 59s))); +} + +static void test_africa_windhoek() { + // Tests the LETTER/S used before the first rule per + // https://data.iana.org/time-zones/tz-how-to.html + // If switching to a named rule before any transition has happened, + // assume standard time (SAVE zero), and use the LETTER data from + // the earliest transition with a SAVE of zero. + + // Z Africa/Windhoek 1:8:24 - LMT 1892 F 8 + // 1:30 - +0130 1903 Mar + // 2 - SAST 1942 S 20 2 + // 2 1 SAST 1943 Mar 21 2 + // 2 - SAST 1990 Mar 21 + // 2 NA %s + // + // R NA 1994 o - Mar 21 0 -1 WAT + // R NA 1994 2017 - S Su>=1 2 0 CAT + // R NA 1995 2017 - Ap Su>=1 2 -1 WAT + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Africa/Windhoek"); + + assert_range( // 2 - EET 2012 N 10 2 + "[1990-03-20 22:00:00, 1994-03-20 22:00:00) 02:00:00 0min CAT", + tz->get_info(to_sys_seconds(1990y, std::chrono::March, 20d, 22h)), + tz->get_info(to_sys_seconds(1994y, std::chrono::March, 20d, 21h, 59min, 59s))); +} + +static void test_america_adak() { + // Z America/Adak 12:13:22 - LMT 1867 O 19 12:44:35 + // ... + // -11 u B%sT 1983 O 30 2 + // -10 u AH%sT 1983 N 30 + // -10 u H%sT + // + // ... + // R u 1945 o - S 30 2 0 S + // R u 1967 2006 - O lastSu 2 0 S + // R u 1967 1973 - Ap lastSu 2 1 D + // R u 1974 o - Ja 6 2 1 D + // R u 1975 o - F lastSu 2 1 D + // R u 1976 1986 - Ap lastSu 2 1 D + // R u 1987 2006 - Ap Su>=1 2 1 D + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Adak"); + + assert_range( // 2 - EET 2012 N 10 2 + "[1983-10-30 12:00:00, 1983-11-30 10:00:00) -10:00:00 0min AHST", + tz->get_info(to_sys_seconds(1983y, std::chrono::October, 30d, 12h)), // -11 u B%sT 1983 O 30 2 + tz->get_info(to_sys_seconds(1983y, std::chrono::November, 30d, 9h, 59min, 59s))); // -10 u AH%sT 1983 N 30 +} + +static void test_america_auncion() { + // R y 2013 ma - Mar Su>=22 0 0 - + // Z America/Asuncion -3:50:40 - LMT 1890 + // -3:50:40 - AMT 1931 O 10 + // -4 - -04 1972 O + // -3 - -03 1974 Ap + // -4 y -04/-03 + // + // R y 1975 1988 - O 1 0 1 - + // R y 1975 1978 - Mar 1 0 0 - + // R y 1979 1991 - Ap 1 0 0 - + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Asuncion"); + + assert_range("[1974-04-01 03:00:00, 1975-10-01 04:00:00) -04:00:00 0min -04", + tz->get_info(to_sys_seconds(1974y, std::chrono::April, 1d, 3h)), + tz->get_info(to_sys_seconds(1975y, std::chrono::October, 1d, 3h, 59min, 59s))); + + assert_range("[1975-10-01 04:00:00, 1976-03-01 03:00:00) -03:00:00 60min -03", + tz->get_info(to_sys_seconds(1975y, std::chrono::October, 1d, 4h)), + tz->get_info(to_sys_seconds(1976y, std::chrono::March, 1d, 2h, 59min, 59s))); +} + +static void test_america_ciudad_juarez() { + // Z America/Ciudad_Juarez -7:5:56 - LMT 1922 Ja 1 7u + // -7 - MST 1927 Jun 10 23 + // -6 - CST 1930 N 15 + // -7 m MST 1932 Ap + // -6 - CST 1996 + // -6 m C%sT 1998 + // ... + // + // R m 1939 o - F 5 0 1 D + // R m 1939 o - Jun 25 0 0 S + // R m 1940 o - D 9 0 1 D + // R m 1941 o - Ap 1 0 0 S + // R m 1943 o - D 16 0 1 W + // R m 1944 o - May 1 0 0 S + // R m 1950 o - F 12 0 1 D + // R m 1950 o - Jul 30 0 0 S + // R m 1996 2000 - Ap Su>=1 2 1 D + // R m 1996 2000 - O lastSu 2 0 S + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Ciudad_Juarez"); + + // 1996 has a similar issue, instead of __time the __until end before + // the first rule in 1939. Between the two usages of RULE Mexico + // a different continuation RULE is active + assert_range("[1996-04-07 08:00:00, 1996-10-27 07:00:00) -05:00:00 60min CDT", + tz->get_info(to_sys_seconds(1996y, std::chrono::April, 7d, 8h)), + tz->get_info(to_sys_seconds(1996y, std::chrono::October, 27d, 6h, 59min, 59s))); +} + +static void test_america_argentina_buenos_aires() { + // Z America/Argentina/Buenos_Aires -3:53:48 - LMT 1894 O 31 + // -4:16:48 - CMT 1920 May + // -4 - -04 1930 D + // -4 A -04/-03 1969 O 5 + // -3 A -03/-02 1999 O 3 + // -4 A -04/-03 2000 Mar 3 + // -3 A -03/-02 + // + // ... + // R A 1989 1992 - O Su>=15 0 1 - + // R A 1999 o - O Su>=1 0 1 - + // R A 2000 o - Mar 3 0 0 - + // R A 2007 o - D 30 0 1 - + // ... + + // The 1999 switch uses the same rule, but with a different stdoff. + // R A 1999 o - O Su>=1 0 1 - + // stdoff -3 -> 1999-10-03 03:00:00 + // stdoff -4 -> 1999-10-03 04:00:00 + // This generates an invalid entry and this is evaluated as a transition. + // Looking at the zdump like output in libc++ this generates jumps in + // the UTC time + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Argentina/Buenos_Aires"); + + assert_range("[1999-10-03 03:00:00, 2000-03-03 03:00:00) -03:00:00 60min -03", + tz->get_info(to_sys_seconds(1999y, std::chrono::October, 3d, 3h)), + tz->get_info(to_sys_seconds(2000y, std::chrono::March, 3d, 2h, 59min, 59s))); + assert_range("[2000-03-03 03:00:00, 2007-12-30 03:00:00) -03:00:00 0min -03", + tz->get_info(to_sys_seconds(2000y, std::chrono::March, 3d, 3h)), + tz->get_info(to_sys_seconds(2007y, std::chrono::December, 30d, 2h, 59min, 59s))); +} + +static void test_america_argentina_la_rioja() { + // Z America/Argentina/La_Rioja -4:27:24 - LMT 1894 O 31 + // ... + // -4 A -04/-03 1969 O 5 + // -3 A -03/-02 1991 Mar + // -4 - -04 1991 May 7 + // -3 A -03/-02 1999 O 3 + // ... + // + // ... + // R A 1988 o - D 1 0 1 - + // R A 1989 1993 - Mar Su>=1 0 0 - + // R A 1989 1992 - O Su>=15 0 1 - + // R A 1999 o - O Su>=1 0 1 - + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Argentina/La_Rioja"); + + assert_range("[1990-10-21 03:00:00, 1991-03-01 02:00:00) -02:00:00 60min -02", + tz->get_info(to_sys_seconds(1990y, std::chrono::October, 21d, 3h)), + tz->get_info(to_sys_seconds(1991y, std::chrono::March, 1d, 1h, 59min, 59s))); +} + +static void test_america_argentina_san_luis() { + // Z America/Argentina/San_Luis -4:25:24 - LMT 1894 O 31 + // ... + // -4 A -04/-03 1969 O 5 + // -3 A -03/-02 1990 + // -3 1 -02 1990 Mar 14 + // -4 - -04 1990 O 15 + // -4 1 -03 1991 Mar + // -4 - -04 1991 Jun + // -3 - -03 1999 O 3 + // -4 1 -03 2000 Mar 3 + // -4 - -04 2004 Jul 25 + // -3 A -03/-02 2008 Ja 21 + // -4 Sa -04/-03 2009 O 11 + // -3 - -03 + // + // ... + // R A 1988 o - D 1 0 1 - + // R A 1989 1993 - Mar Su>=1 0 0 - + // R A 1989 1992 - O Su>=15 0 1 - + // R A 1999 o - O Su>=1 0 1 - + // R A 2000 o - Mar 3 0 0 - + // R A 2007 o - D 30 0 1 - + // R A 2008 2009 - Mar Su>=15 0 0 - + // R A 2008 o - O Su>=15 0 1 - + // + // R Sa 2008 2009 - Mar Su>=8 0 0 - + // R Sa 2007 2008 - O Su>=8 0 1 - + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Argentina/San_Luis"); + + assert_range("[1989-10-15 03:00:00, 1990-03-14 02:00:00) -02:00:00 60min -02", + tz->get_info( // -3 A -03/-02 1990 & R A 1989 1992 - O Su>=15 0 1 - + to_sys_seconds(1989y, std::chrono::October, 15d, 3h)), + tz->get_info( // UNTIL -3 1 -02 1990 Mar 14 + to_sys_seconds(1990y, std::chrono::March, 14d, 1h, 59min, 59s))); + + assert_range("[2008-01-21 02:00:00, 2008-03-09 03:00:00) -03:00:00 60min -03", + tz->get_info(to_sys_seconds(2008y, std::chrono::January, 21d, 2h)), + tz->get_info(to_sys_seconds(2008y, std::chrono::March, 9d, 2h, 59min, 59s))); +} + +static void test_america_indiana_knox() { + // Z America/Indiana/Knox -5:46:30 - LMT 1883 N 18 12:13:30 + // -6 u C%sT 1947 + // -6 St C%sT 1962 Ap 29 2 + // -5 - EST 1963 O 27 2 + // -6 u C%sT 1991 O 27 2 + // -5 - EST 2006 Ap 2 2 + // -6 u C%sT + // + // ... + // R u 1976 1986 - Ap lastSu 2 1 D + // R u 1987 2006 - Ap Su>=1 2 1 D + // R u 2007 ma - Mar Su>=8 2 1 D + // R u 2007 ma - N Su>=1 2 0 S + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Indiana/Knox"); + + // The continuations + // -5 - EST + // -6 u C%sT + // have different offsets. The start time of the first active rule in + // RULE u should use the offset at the end of -5 - EST. + assert_range("[2006-04-02 07:00:00, 2006-10-29 07:00:00) -05:00:00 60min CDT", + tz->get_info(to_sys_seconds(2006y, std::chrono::April, 2d, 7h)), + tz->get_info(to_sys_seconds(2006y, std::chrono::October, 29d, 6h, 59min, 59s))); +} + +int main(int, const char**) { + // Basic tests + test_gmt(); + test_durations(); + test_indian_kerguelen(); + test_antarctica_syowa(); + test_asia_hong_kong(); + test_europe_berlin(); + + test_america_st_johns(); + + // Small tests for not-yet tested conditions + test_get_at_standard_time_universal(); + test_get_at_standard_time_standard(); + test_get_at_save_universal(); + test_get_at_rule_standard(); + test_get_at_rule_universal(); + + test_format_with_alternatives_west(); + test_format_with_alternatives_east(); + + // Tests based on bugs found + test_africa_algiers(); + test_africa_casablanca(); + test_africa_ceuta(); + test_africa_freetown(); + test_africa_windhoek(); + test_america_adak(); + test_america_argentina_buenos_aires(); + test_america_argentina_la_rioja(); + test_america_argentina_san_luis(); + test_america_auncion(); + test_america_ciudad_juarez(); + test_america_indiana_knox(); + + return 0; +} diff --git a/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/sys_info.zdump.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/sys_info.zdump.pass.cpp new file mode 100644 index 000000000000..05328e2256c7 --- /dev/null +++ b/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/sys_info.zdump.pass.cpp @@ -0,0 +1,129 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: no-filesystem, no-localization, no-tzdb, has-no-zdump + +// XFAIL: libcpp-has-no-incomplete-tzdb +// XFAIL: availability-tzdb-missing + +// TODO TZDB Investigate +// XFAIL: target={{armv(7|8)l-linux-gnueabihf}} + +#include +#include +#include +#include + +#include "filesystem_test_helper.h" +#include "assert_macros.h" +#include "concat_macros.h" + +// The year range to validate. The dates used in practice are expected to be +// inside the tested range. +constexpr std::chrono::year first{1800}; +constexpr std::chrono::year last{2100}; + +// A custom sys_info class that also stores the name of the time zone. +// Its formatter matches the output of zdump. +struct sys_info : public std::chrono::sys_info { + sys_info(std::string_view name_, std::chrono::sys_info info) : std::chrono::sys_info{info}, name{name_} {} + + std::string name; +}; + +template <> +struct std::formatter { + template + constexpr typename ParseContext::iterator parse(ParseContext& ctx) { + return ctx.begin(); + } + + template + typename FormatContext::iterator format(const sys_info& info, FormatContext& ctx) const { + using namespace std::literals::chrono_literals; + + // Every "sys_info" entry of zdump consists of 2 lines. + // - 1 for first second of the range + // - 1 for last second of the range + // For example: + // Africa/Casablanca Sun Mar 25 02:00:00 2018 UT = Sun Mar 25 03:00:00 2018 +01 isdst=1 gmtoff=3600 + // Africa/Casablanca Sun May 13 01:59:59 2018 UT = Sun May 13 02:59:59 2018 +01 isdst=1 gmtoff=3600 + + if (info.begin != std::chrono::sys_seconds::min()) + ctx.advance_to(std::format_to( + ctx.out(), + "{} {:%a %b %e %H:%M:%S %Y} UT = {:%a %b %e %H:%M:%S %Y} {} isdst={:d} gmtoff={:%Q}\n", + info.name, + info.begin, + info.begin + info.offset, + info.abbrev, + info.save != 0s, + info.offset)); + + if (info.end != std::chrono::sys_seconds::max()) + ctx.advance_to(std::format_to( + ctx.out(), + "{} {:%a %b %e %H:%M:%S %Y} UT = {:%a %b %e %H:%M:%S %Y} {} isdst={:d} gmtoff={:%Q}\n", + info.name, + info.end - 1s, + info.end - 1s + info.offset, + info.abbrev, + info.save != 0s, + info.offset)); + + return ctx.out(); + } +}; + +void process(std::ostream& stream, const std::chrono::time_zone& zone) { + using namespace std::literals::chrono_literals; + + constexpr auto begin = std::chrono::time_point_cast( + static_cast(std::chrono::year_month_day{first, std::chrono::January, 1d})); + constexpr auto end = std::chrono::time_point_cast( + static_cast(std::chrono::year_month_day{last, std::chrono::January, 1d})); + + std::chrono::sys_seconds s = begin; + do { + sys_info info{zone.name(), zone.get_info(s)}; + + if (info.end >= end) + info.end = std::chrono::sys_seconds::max(); + + stream << std::format("{}", info); + s = info.end; + } while (s != std::chrono::sys_seconds::max()); +} + +// This test compares the output of the zdump against the output based on the +// standard library implementation. It tests all available time zones and +// validates them. The specification of how to use the IANA database is limited +// and the real database contains quite a number of "interesting" cases. +int main(int, const char**) { + scoped_test_env env; + const std::string file = env.create_file("zdump.txt"); + + const std::chrono::tzdb& tzdb = std::chrono::get_tzdb(); + for (const auto& zone : tzdb.zones) { + std::stringstream libcxx; + process(libcxx, zone); + + int result = std::system(std::format("zdump -V -c{},{} {} > {}", first, last, zone.name(), file).c_str()); + assert(result == 0); + + std::stringstream zdump; + zdump << std::ifstream(file).rdbuf(); + + TEST_REQUIRE( + libcxx.str() == zdump.str(), + TEST_WRITE_CONCATENATED("\nTZ=", zone.name(), "\nlibc++\n", libcxx.str(), "|\n\nzdump\n", zdump.str(), "|")); + } + + return 0; +} diff --git a/libcxx/utils/libcxx/test/features.py b/libcxx/utils/libcxx/test/features.py index 0793c34fd7f0..6ff16309546b 100644 --- a/libcxx/utils/libcxx/test/features.py +++ b/libcxx/utils/libcxx/test/features.py @@ -286,6 +286,12 @@ DEFAULT_FEATURES = [ # Avoid building on platforms that don't support modules properly. or not hasCompileFlag(cfg, "-Wno-reserved-module-identifier"), ), + # The time zone validation tests compare the output of zdump against the + # output generated by 's time zone support. + Feature( + name="has-no-zdump", + when=lambda cfg: runScriptExitCode(cfg, ["zdump --version"]) != 0, + ), ] # Deduce and add the test features that that are implied by the #defines in -- GitLab From c174d8f46546f7e0e861061256a45570f3bdea75 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Wed, 10 Apr 2024 07:55:45 +0200 Subject: [PATCH 368/695] [libc++][CI] Updates Docker LLDB dependencies. (#88174) In order to test the LLDB data formatters make is required and SWIG needs to be updated to version 4. As drive-by, this patch sorts the entries and removes some duplicates. --- libcxx/utils/ci/Dockerfile | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/libcxx/utils/ci/Dockerfile b/libcxx/utils/ci/Dockerfile index db88da20b977..c77f6c435baf 100644 --- a/libcxx/utils/ci/Dockerfile +++ b/libcxx/utils/ci/Dockerfile @@ -72,33 +72,32 @@ RUN sudo apt-get update \ RUN sudo apt-get update \ && sudo apt-get install -y \ - python3 \ - python3-distutils \ - python3-psutil \ - git \ - gdb \ - ccache \ - gpg \ - wget \ bash \ + ccache \ curl \ - python3 \ - python3-dev \ - libpython3-dev \ - uuid-dev \ - libncurses5-dev \ - swig3.0 \ - libxml2-dev \ - libedit-dev \ + gdb \ + git \ + gpg \ language-pack-en \ language-pack-fr \ language-pack-ja \ language-pack-ru \ language-pack-zh-hans \ + libedit-dev \ + libncurses5-dev \ + libpython3-dev \ + libxml2-dev \ lsb-release \ - wget \ - unzip \ + make \ + python3 \ + python3-dev \ + python3-distutils \ + python3-psutil \ software-properties-common \ + swig4.0 \ + unzip \ + uuid-dev \ + wget \ && sudo rm -rf /var/lib/apt/lists/* -- GitLab From 4a93872a4f57d2f205826052150fadc36490445f Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Wed, 10 Apr 2024 13:58:47 +0800 Subject: [PATCH 369/695] Reland "[Win32][ELF] Make CodeView a DebugInfoFormat only for COFF format" (#87987) This relands #87149. The previous commit exposed failures on some targets. The reason is only a few targets support COFF ObjectFormatType on Windows: https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/Triple.cpp#L835-L842 With #87149, the targets don't support COFF will report "warning: argument unused during compilation: '-gcodeview-command-line' [-Wunused-command-line-argument]" in the test gcodeview-command-line.c This patch limits gcodeview-command-line.c only run on targets support COFF. --- clang/lib/Driver/ToolChains/MSVC.h | 5 ++--- clang/test/Driver/gcodeview-command-line.c | 1 + clang/test/Misc/win32-elf.c | 5 +++++ 3 files changed, 8 insertions(+), 3 deletions(-) create mode 100644 clang/test/Misc/win32-elf.c diff --git a/clang/lib/Driver/ToolChains/MSVC.h b/clang/lib/Driver/ToolChains/MSVC.h index 48369e030aad..3950a8ed38e8 100644 --- a/clang/lib/Driver/ToolChains/MSVC.h +++ b/clang/lib/Driver/ToolChains/MSVC.h @@ -61,9 +61,8 @@ public: /// formats, and to DWARF otherwise. Users can use -gcodeview and -gdwarf to /// override the default. llvm::codegenoptions::DebugInfoFormat getDefaultDebugFormat() const override { - return getTriple().isOSBinFormatMachO() - ? llvm::codegenoptions::DIF_DWARF - : llvm::codegenoptions::DIF_CodeView; + return getTriple().isOSBinFormatCOFF() ? llvm::codegenoptions::DIF_CodeView + : llvm::codegenoptions::DIF_DWARF; } /// Set the debugger tuning to "default", since we're definitely not tuning diff --git a/clang/test/Driver/gcodeview-command-line.c b/clang/test/Driver/gcodeview-command-line.c index da8708af3224..83542fc71aec 100644 --- a/clang/test/Driver/gcodeview-command-line.c +++ b/clang/test/Driver/gcodeview-command-line.c @@ -1,5 +1,6 @@ // Note: %s must be preceded by --, otherwise it may be interpreted as a // command-line option, e.g. on Mac where %s is commonly under /Users. +// REQUIRES: aarch64-registered-target,arm-registered-target,x86-registered-target // ON-NOT: "-gno-codview-commandline" // OFF: "-gno-codeview-command-line" diff --git a/clang/test/Misc/win32-elf.c b/clang/test/Misc/win32-elf.c new file mode 100644 index 000000000000..f75281dc4187 --- /dev/null +++ b/clang/test/Misc/win32-elf.c @@ -0,0 +1,5 @@ +// Check that basic use of win32-elf targets works. +// RUN: %clang -fsyntax-only -target x86_64-pc-win32-elf %s + +// RUN: %clang -fsyntax-only -target x86_64-pc-win32-elf -g %s -### 2>&1 | FileCheck %s -check-prefix=DEBUG-INFO +// DEBUG-INFO: -dwarf-version={{.*}} -- GitLab From 749620ea2c738be88f6c0fd59c7217bca6818d5f Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Wed, 10 Apr 2024 08:02:13 +0200 Subject: [PATCH 370/695] [lib++][CI] Changes bootstrap build type. (#88175) The RelWithDebInfo generates a few GB of debug info that is not used. Instead use the normal Release build for testing. --- libcxx/utils/ci/run-buildbot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcxx/utils/ci/run-buildbot b/libcxx/utils/ci/run-buildbot index 2905745355b6..a6f3eb174308 100755 --- a/libcxx/utils/ci/run-buildbot +++ b/libcxx/utils/ci/run-buildbot @@ -374,7 +374,7 @@ bootstrapping-build) -B "${BUILD_DIR}" \ -GNinja -DCMAKE_MAKE_PROGRAM="${NINJA}" \ -DCMAKE_CXX_COMPILER_LAUNCHER="ccache" \ - -DCMAKE_BUILD_TYPE=RelWithDebInfo \ + -DCMAKE_BUILD_TYPE=Release \ -DCMAKE_INSTALL_PREFIX="${INSTALL_DIR}" \ -DLLVM_ENABLE_PROJECTS="clang" \ -DLLVM_ENABLE_RUNTIMES="libcxx;libcxxabi;libunwind" \ -- GitLab From 3d985a6f1bfcdb6e6d550003f9a1276fe47f588d Mon Sep 17 00:00:00 2001 From: Shih-Po Hung Date: Wed, 10 Apr 2024 14:18:15 +0800 Subject: [PATCH 371/695] [RISCV][TTI] Scale the cost of Select with LMUL (#88098) Use the Val type to estimate the instruction cost for SelectInst. --- .../Target/RISCV/RISCVTargetTransformInfo.cpp | 20 ++++-- .../Analysis/CostModel/RISCV/rvv-select.ll | 64 +++++++++---------- 2 files changed, 48 insertions(+), 36 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 58132c1fc431..bc9756c5e6dd 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1342,10 +1342,14 @@ InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, // vmandn.mm v8, v8, v9 // vmand.mm v9, v0, v9 // vmor.mm v0, v9, v8 - return LT.first * 3; + return LT.first * + getRISCVInstructionCost( + {RISCV::VMANDN_MM, RISCV::VMAND_MM, RISCV::VMOR_MM}, + LT.second, CostKind); } // vselect and max/min are supported natively. - return LT.first * 1; + return LT.first * + getRISCVInstructionCost(RISCV::VMERGE_VVM, LT.second, CostKind); } if (ValTy->getScalarSizeInBits() == 1) { @@ -1354,13 +1358,21 @@ InstructionCost RISCVTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, // vmandn.mm v8, v8, v9 // vmand.mm v9, v0, v9 // vmor.mm v0, v9, v8 - return LT.first * 5; + MVT InterimVT = LT.second.changeVectorElementType(MVT::i8); + return LT.first * + getRISCVInstructionCost({RISCV::VMV_V_X, RISCV::VMSNE_VI}, + InterimVT, CostKind) + + LT.first * getRISCVInstructionCost( + {RISCV::VMANDN_MM, RISCV::VMAND_MM, RISCV::VMOR_MM}, + LT.second, CostKind); } // vmv.v.x v10, a0 // vmsne.vi v0, v10, 0 // vmerge.vvm v8, v9, v8, v0 - return LT.first * 3; + return LT.first * getRISCVInstructionCost( + {RISCV::VMV_V_X, RISCV::VMSNE_VI, RISCV::VMERGE_VVM}, + LT.second, CostKind); } if ((Opcode == Instruction::ICmp || Opcode == Instruction::FCmp) && diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-select.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-select.ll index 264a74116449..6dcbc73674aa 100644 --- a/llvm/test/Analysis/CostModel/RISCV/rvv-select.ll +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-select.ll @@ -22,14 +22,14 @@ define void @select() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %15 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %16 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %17 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %18 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %19 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %18 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %19 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %20 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %21 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %22 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %23 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %24 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %25 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %24 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %25 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %26 = select i1 undef, i8 undef, i8 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %27 = select i1 undef, <1 x i8> undef, <1 x i8> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %28 = select i1 undef, <2 x i8> undef, <2 x i8> undef @@ -47,14 +47,14 @@ define void @select() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %40 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %41 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %42 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %43 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %44 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %43 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %44 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %45 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %46 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %47 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %48 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %49 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %50 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %49 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %50 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %51 = select i1 undef, i16 undef, i16 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %52 = select i1 undef, <1 x i16> undef, <1 x i16> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %53 = select i1 undef, <2 x i16> undef, <2 x i16> undef @@ -71,15 +71,15 @@ define void @select() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %64 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %65 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %66 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %67 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %68 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %69 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %67 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %68 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %69 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %70 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %71 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %72 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %73 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %74 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %75 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %73 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %74 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %75 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %76 = select i1 undef, i32 undef, i32 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %77 = select i1 undef, <1 x i32> undef, <1 x i32> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %78 = select i1 undef, <2 x i32> undef, <2 x i32> undef @@ -95,16 +95,16 @@ define void @select() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %88 = select <32 x i1> undef, <32 x i32> undef, <32 x i32> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %89 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %90 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %91 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %92 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %93 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %94 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %91 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %92 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %93 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %94 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %95 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %96 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %97 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %98 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %99 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %100 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %97 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %98 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %99 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %100 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %101 = select i1 undef, i64 undef, i64 undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %102 = select i1 undef, <1 x i64> undef, <1 x i64> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %103 = select i1 undef, <2 x i64> undef, <2 x i64> undef @@ -119,17 +119,17 @@ define void @select() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %112 = select <16 x i1> undef, <16 x i64> undef, <16 x i64> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %113 = select <32 x i1> undef, <32 x i64> undef, <32 x i64> undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %114 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %115 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %116 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %117 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %118 = select i1 undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %119 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %115 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %116 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %117 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %118 = select i1 undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %119 = select i1 undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %120 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %121 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %122 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %123 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %124 = select undef, undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %125 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %121 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %122 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %123 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %124 = select undef, undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %125 = select undef, undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; select i1 undef, i1 undef, i1 undef -- GitLab From 313a33b9dff44dc2b0048484e54f9328d9a0d9db Mon Sep 17 00:00:00 2001 From: XChy Date: Wed, 10 Apr 2024 14:19:44 +0800 Subject: [PATCH 372/695] [InstCombine] Reduce nested logical operator if poison is implied (#86823) Fixes #76623 Alive2 proof: https://alive2.llvm.org/ce/z/gX6znJ (I'm not sure how to write a proof for such transform, maybe there are mistakes) In most cases, `icmp(a, C1) && (other_cond && icmp(a, C2))` will be reduced to `icmp(a, C1) & (other_cond && icmp(a, C2))`, since latter icmp always implies the poison of the former. After reduction, it's easier to simplify the icmp chain. Similarly, this patch does the same thing for `(A && B) && C --> A && (B & C)`. Maybe we could constraint such reduction only on icmps if there is regression in benchmarks. --- .../InstCombine/InstCombineSelect.cpp | 14 ++ .../Transforms/InstCombine/and-or-icmps.ll | 60 +++++ .../Transforms/InstCombine/logical-select.ll | 218 ++++++++++++++++++ 3 files changed, 292 insertions(+) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 4d3de76389c2..2d78fcee1152 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -3091,6 +3091,13 @@ Instruction *InstCombinerImpl::foldSelectOfBools(SelectInst &SI) { return BinaryOperator::CreateOr(CondVal, FalseVal); } + if (match(CondVal, m_OneUse(m_Select(m_Value(A), m_One(), m_Value(B)))) && + impliesPoison(FalseVal, B)) { + // (A || B) || C --> A || (B | C) + return replaceInstUsesWith( + SI, Builder.CreateLogicalOr(A, Builder.CreateOr(B, FalseVal))); + } + if (auto *LHS = dyn_cast(CondVal)) if (auto *RHS = dyn_cast(FalseVal)) if (Value *V = foldLogicOfFCmps(LHS, RHS, /*IsAnd*/ false, @@ -3132,6 +3139,13 @@ Instruction *InstCombinerImpl::foldSelectOfBools(SelectInst &SI) { return BinaryOperator::CreateAnd(CondVal, TrueVal); } + if (match(CondVal, m_OneUse(m_Select(m_Value(A), m_Value(B), m_Zero()))) && + impliesPoison(TrueVal, B)) { + // (A && B) && C --> A && (B & C) + return replaceInstUsesWith( + SI, Builder.CreateLogicalAnd(A, Builder.CreateAnd(B, TrueVal))); + } + if (auto *LHS = dyn_cast(CondVal)) if (auto *RHS = dyn_cast(TrueVal)) if (Value *V = foldLogicOfFCmps(LHS, RHS, /*IsAnd*/ true, diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll index c8d348df5f42..63b11d0c0bc0 100644 --- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll +++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll @@ -3038,3 +3038,63 @@ define i32 @icmp_slt_0_or_icmp_add_1_sge_100_i32_fail(i32 %x) { %D = or i32 %C, %B ret i32 %D } + +define i1 @logical_and_icmps1(i32 %a, i1 %other_cond) { +; CHECK-LABEL: @logical_and_icmps1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP3:%.*]] = icmp ult i32 [[A:%.*]], 10086 +; CHECK-NEXT: [[RET2:%.*]] = select i1 [[RET1:%.*]], i1 [[CMP3]], i1 false +; CHECK-NEXT: ret i1 [[RET2]] +; +entry: + %cmp1 = icmp sgt i32 %a, -1 + %logical_and = select i1 %other_cond, i1 %cmp1, i1 false + %cmp2 = icmp slt i32 %a, 10086 + %ret = select i1 %logical_and, i1 %cmp2, i1 false + ret i1 %ret +} + +define i1 @logical_and_icmps2(i32 %a, i1 %other_cond) { +; CHECK-LABEL: @logical_and_icmps2( +; CHECK-NEXT: entry: +; CHECK-NEXT: ret i1 false +; +entry: + %cmp1 = icmp slt i32 %a, -1 + %logical_and = select i1 %other_cond, i1 %cmp1, i1 false + %cmp2 = icmp eq i32 %a, 10086 + %ret = select i1 %logical_and, i1 %cmp2, i1 false + ret i1 %ret +} + +define <4 x i1> @logical_and_icmps_vec1(<4 x i32> %a, <4 x i1> %other_cond) { +; CHECK-LABEL: @logical_and_icmps_vec1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP3:%.*]] = icmp ult <4 x i32> [[A:%.*]], +; CHECK-NEXT: [[RET2:%.*]] = select <4 x i1> [[RET1:%.*]], <4 x i1> [[CMP3]], <4 x i1> zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[RET2]] +; +entry: + %cmp1 = icmp sgt <4 x i32> %a, + %logical_and = select <4 x i1> %other_cond, <4 x i1> %cmp1, <4 x i1> zeroinitializer + %cmp2 = icmp slt <4 x i32> %a, + %ret = select <4 x i1> %logical_and, <4 x i1> %cmp2, <4 x i1> zeroinitializer + ret <4 x i1> %ret +} + +define i1 @logical_and_icmps_fail1(i32 %a, i32 %b, i1 %other_cond) { +; CHECK-LABEL: @logical_and_icmps_fail1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1 +; CHECK-NEXT: [[LOGICAL_AND:%.*]] = select i1 [[OTHER_COND:%.*]], i1 [[CMP1]], i1 false +; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[A]], [[B:%.*]] +; CHECK-NEXT: [[RET:%.*]] = select i1 [[LOGICAL_AND]], i1 [[CMP2]], i1 false +; CHECK-NEXT: ret i1 [[RET]] +; +entry: + %cmp1 = icmp sgt i32 %a, -1 + %logical_and = select i1 %other_cond, i1 %cmp1, i1 false + %cmp2 = icmp slt i32 %a, %b + %ret = select i1 %logical_and, i1 %cmp2, i1 false + ret i1 %ret +} diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll index f0ea09c08847..c850b87bb2dd 100644 --- a/llvm/test/Transforms/InstCombine/logical-select.ll +++ b/llvm/test/Transforms/InstCombine/logical-select.ll @@ -1303,3 +1303,221 @@ define i1 @logical_or_and_with_common_not_op_variant5(i1 %a) { %or = select i1 %a, i1 true, i1 %and ret i1 %or } + +define i1 @reduce_logical_and1(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_and1( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[CMP1]], [[CMP]] +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 [[TMP0]], i1 false +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 %cmp1, i1 false + %and2 = select i1 %and1, i1 %cmp, i1 false + ret i1 %and2 +} + +define i1 @reduce_logical_and2(i1 %a, i1 %b, i1 %c) { +; CHECK-LABEL: @reduce_logical_and2( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[C:%.*]], true +; CHECK-NEXT: [[B:%.*]] = and i1 [[TMP0]], [[B1:%.*]] +; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2:%.*]], i1 [[B]], i1 false +; CHECK-NEXT: ret i1 [[AND3]] +; +bb: + %or = xor i1 %c, %b + %and1 = select i1 %a, i1 %or, i1 false + %and2 = select i1 %and1, i1 %b, i1 false + ret i1 %and2 +} + +define i1 @reduce_logical_and3(i1 %a, i32 %b, i32 noundef %c) { +; CHECK-LABEL: @reduce_logical_and3( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[CMP]], [[CMP1]] +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 [[TMP0]], i1 false +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 %cmp, i1 false + %and2 = select i1 %and1, i1 %cmp1, i1 false + ret i1 %and2 +} + +define i1 @reduce_logical_or1(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_or1( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[CMP1]], [[CMP]] +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[TMP0]] +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 true, i1 %cmp1 + %and2 = select i1 %and1, i1 true, i1 %cmp + ret i1 %and2 +} + +define i1 @reduce_logical_or2(i1 %a, i1 %b, i1 %c) { +; CHECK-LABEL: @reduce_logical_or2( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[B:%.*]] = or i1 [[C:%.*]], [[B1:%.*]] +; CHECK-NEXT: [[AND3:%.*]] = select i1 [[AND2:%.*]], i1 true, i1 [[B]] +; CHECK-NEXT: ret i1 [[AND3]] +; +bb: + %or = xor i1 %c, %b + %and1 = select i1 %a, i1 true, i1 %or + %and2 = select i1 %and1, i1 true, i1 %b + ret i1 %and2 +} + +define i1 @reduce_logical_or3(i1 %a, i32 %b, i32 noundef %c) { +; CHECK-LABEL: @reduce_logical_or3( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[CMP]], [[CMP1]] +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[TMP0]] +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 true, i1 %cmp + %and2 = select i1 %and1, i1 true, i1 %cmp1 + ret i1 %and2 +} + +define i1 @reduce_logical_and_fail1(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_and_fail1( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP]], i1 false +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP1]], i1 false +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 %cmp, i1 false + %and2 = select i1 %and1, i1 %cmp1, i1 false + ret i1 %and2 +} + +define i1 @reduce_logical_and_fail2(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_and_fail2( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], 7 +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP]], i1 false +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP1]], i1 false +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, 7 + %and1 = select i1 %a, i1 %cmp, i1 false + %and2 = select i1 %and1, i1 %cmp1, i1 false + ret i1 %and2 +} + +define i1 @reduce_logical_or_fail1(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_or_fail1( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP]] +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP1]] +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 true, i1 %cmp + %and2 = select i1 %and1, i1 true, i1 %cmp1 + ret i1 %and2 +} + +define i1 @reduce_logical_or_fail2(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_or_fail2( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], 7 +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[CMP]] +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 true, i1 [[CMP1]] +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, 7 + %and1 = select i1 %a, i1 true, i1 %cmp + %and2 = select i1 %and1, i1 true, i1 %cmp1 + ret i1 %and2 +} + +define i1 @reduce_logical_and_multiuse(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_logical_and_multiuse( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP1]], i1 false +; CHECK-NEXT: call void @use1(i1 [[AND1]]) +; CHECK-NEXT: [[AND2:%.*]] = select i1 [[AND1]], i1 [[CMP]], i1 false +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 %cmp1, i1 false + call void @use1(i1 %and1) + %and2 = select i1 %and1, i1 %cmp, i1 false + ret i1 %and2 +} + +define i1 @reduce_bitwise_and1(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_bitwise_and1( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[AND1:%.*]] = or i1 [[CMP1]], [[A:%.*]] +; CHECK-NEXT: [[AND2:%.*]] = and i1 [[AND1]], [[CMP]] +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = or i1 %a, %cmp1 + %and2 = select i1 %and1, i1 %cmp, i1 false + ret i1 %and2 +} + +define i1 @reduce_bitwise_and2(i1 %a, i32 %b, i32 %c) { +; CHECK-LABEL: @reduce_bitwise_and2( +; CHECK-NEXT: bb: +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[B:%.*]], 6 +; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[C:%.*]], [[B]] +; CHECK-NEXT: [[AND1:%.*]] = select i1 [[A:%.*]], i1 [[CMP1]], i1 false +; CHECK-NEXT: [[AND2:%.*]] = or i1 [[AND1]], [[CMP]] +; CHECK-NEXT: ret i1 [[AND2]] +; +bb: + %cmp = icmp slt i32 %b, 6 + %cmp1 = icmp sgt i32 %c, %b + %and1 = select i1 %a, i1 %cmp1, i1 false + %and2 = or i1 %and1, %cmp + ret i1 %and2 +} -- GitLab From 469caa31e77f1da37434783f9b4f1d87fe8dff71 Mon Sep 17 00:00:00 2001 From: Chia Date: Wed, 10 Apr 2024 15:26:17 +0900 Subject: [PATCH 373/695] [RISCV] Use vwadd.vx for splat vector with extension (#87249) This patch allows `combineBinOp_VLToVWBinOp_VL` to handle patterns like `(splat_vector (sext op))` or `(splat_vector (zext op))`. Then we can use `vwadd.vx` and `vwadd.w` for such a case. ### Source code ``` define @vwadd_vx_splat_sext( %va, i32 %b) { %sb = sext i32 %b to i64 %head = insertelement poison, i64 %sb, i32 0 %splat = shufflevector %head, poison, zeroinitializer %vc = sext %va to %ve = add %vc, %splat ret %ve } ``` ### Before this patch [Compiler Explorer](https://godbolt.org/z/sq191PsT4) ``` vwadd_vx_splat_sext: sext.w a0, a0 vsetvli a1, zero, e64, m8, ta, ma vmv.v.x v16, a0 vsetvli zero, zero, e32, m4, ta, ma vwadd.wv v16, v16, v8 vmv8r.v v8, v16 ret ``` ### After this patch ``` vwadd_vx_splat_sext vsetvli a1, zero, e32, m4, ta, ma vwadd.vx v16, v8, a0 vmv8r.v v8, v16 ret ``` --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 85 ++--- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 336 +++++++++++++------- llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 204 +++++++----- llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll | 156 +++++++++ llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll | 23 +- 5 files changed, 569 insertions(+), 235 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 80cc41b458ca..6e97575c167c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13597,7 +13597,8 @@ struct NodeExtensionHelper { /// Check if this instance represents a splat. bool isSplat() const { - return OrigOperand.getOpcode() == RISCVISD::VMV_V_X_VL; + return OrigOperand.getOpcode() == RISCVISD::VMV_V_X_VL || + OrigOperand.getOpcode() == ISD::SPLAT_VECTOR; } /// Get the extended opcode. @@ -13641,6 +13642,8 @@ struct NodeExtensionHelper { case RISCVISD::VZEXT_VL: case RISCVISD::FP_EXTEND_VL: return DAG.getNode(ExtOpc, DL, NarrowVT, Source, Mask, VL); + case ISD::SPLAT_VECTOR: + return DAG.getSplat(NarrowVT, DL, Source.getOperand(0)); case RISCVISD::VMV_V_X_VL: return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, NarrowVT, DAG.getUNDEF(NarrowVT), Source.getOperand(1), VL); @@ -13776,6 +13779,47 @@ struct NodeExtensionHelper { /// Check if this node needs to be fully folded or extended for all users. bool needToPromoteOtherUsers() const { return EnforceOneUse; } + void fillUpExtensionSupportForSplat(SDNode *Root, SelectionDAG &DAG, + const RISCVSubtarget &Subtarget) { + unsigned Opc = OrigOperand.getOpcode(); + MVT VT = OrigOperand.getSimpleValueType(); + + assert((Opc == ISD::SPLAT_VECTOR || Opc == RISCVISD::VMV_V_X_VL) && + "Unexpected Opcode"); + + // The pasthru must be undef for tail agnostic. + if (Opc == RISCVISD::VMV_V_X_VL && !OrigOperand.getOperand(0).isUndef()) + return; + + // Get the scalar value. + SDValue Op = Opc == ISD::SPLAT_VECTOR ? OrigOperand.getOperand(0) + : OrigOperand.getOperand(1); + + // See if we have enough sign bits or zero bits in the scalar to use a + // widening opcode by splatting to smaller element size. + unsigned EltBits = VT.getScalarSizeInBits(); + unsigned ScalarBits = Op.getValueSizeInBits(); + // Make sure we're getting all element bits from the scalar register. + // FIXME: Support implicit sign extension of vmv.v.x? + if (ScalarBits < EltBits) + return; + + unsigned NarrowSize = VT.getScalarSizeInBits() / 2; + // If the narrow type cannot be expressed with a legal VMV, + // this is not a valid candidate. + if (NarrowSize < 8) + return; + + if (DAG.ComputeMaxSignificantBits(Op) <= NarrowSize) + SupportsSExt = true; + + if (DAG.MaskedValueIsZero(Op, + APInt::getBitsSetFrom(ScalarBits, NarrowSize))) + SupportsZExt = true; + + EnforceOneUse = false; + } + /// Helper method to set the various fields of this struct based on the /// type of \p Root. void fillUpExtensionSupport(SDNode *Root, SelectionDAG &DAG, @@ -13814,43 +13858,10 @@ struct NodeExtensionHelper { case RISCVISD::FP_EXTEND_VL: SupportsFPExt = true; break; - case RISCVISD::VMV_V_X_VL: { - // Historically, we didn't care about splat values not disappearing during - // combines. - EnforceOneUse = false; - - // The operand is a splat of a scalar. - - // The pasthru must be undef for tail agnostic. - if (!OrigOperand.getOperand(0).isUndef()) - break; - - // Get the scalar value. - SDValue Op = OrigOperand.getOperand(1); - - // See if we have enough sign bits or zero bits in the scalar to use a - // widening opcode by splatting to smaller element size. - MVT VT = Root->getSimpleValueType(0); - unsigned EltBits = VT.getScalarSizeInBits(); - unsigned ScalarBits = Op.getValueSizeInBits(); - // Make sure we're getting all element bits from the scalar register. - // FIXME: Support implicit sign extension of vmv.v.x? - if (ScalarBits < EltBits) - break; - - unsigned NarrowSize = VT.getScalarSizeInBits() / 2; - // If the narrow type cannot be expressed with a legal VMV, - // this is not a valid candidate. - if (NarrowSize < 8) - break; - - if (DAG.ComputeMaxSignificantBits(Op) <= NarrowSize) - SupportsSExt = true; - if (DAG.MaskedValueIsZero(Op, - APInt::getBitsSetFrom(ScalarBits, NarrowSize))) - SupportsZExt = true; + case ISD::SPLAT_VECTOR: + case RISCVISD::VMV_V_X_VL: + fillUpExtensionSupportForSplat(Root, DAG, Subtarget); break; - } default: break; } diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll index fc94f8c2a527..d756cfcf7077 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV32,RV32I ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV64,RV64I -; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32F +; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64F ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB @@ -1229,21 +1229,36 @@ define @ctlz_nxv1i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_nxv1i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-F-NEXT: vmv.v.x v9, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-F-NEXT: vsrl.vi v8, v10, 23 -; CHECK-F-NEXT: vwsubu.wv v9, v9, v8 -; CHECK-F-NEXT: li a1, 64 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma -; CHECK-F-NEXT: vminu.vx v8, v9, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_nxv1i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32F-NEXT: vmv.v.x v9, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v10, v8 +; RV32F-NEXT: vsrl.vi v8, v10, 23 +; RV32F-NEXT: vwsubu.wv v9, v9, v8 +; RV32F-NEXT: li a1, 64 +; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; RV32F-NEXT: vminu.vx v8, v9, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_nxv1i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma +; RV64F-NEXT: vmv.v.x v9, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v10, v8 +; RV64F-NEXT: vsrl.vi v8, v10, 23 +; RV64F-NEXT: vwsubu.vv v10, v9, v8 +; RV64F-NEXT: li a1, 64 +; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; RV64F-NEXT: vminu.vx v8, v10, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_nxv1i64: ; CHECK-D: # %bb.0: @@ -1370,21 +1385,36 @@ define @ctlz_nxv2i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_nxv2i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-F-NEXT: vmv.v.x v10, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-F-NEXT: vsrl.vi v8, v12, 23 -; CHECK-F-NEXT: vwsubu.wv v10, v10, v8 -; CHECK-F-NEXT: li a1, 64 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-F-NEXT: vminu.vx v8, v10, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_nxv2i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32F-NEXT: vmv.v.x v10, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v12, v8 +; RV32F-NEXT: vsrl.vi v8, v12, 23 +; RV32F-NEXT: vwsubu.wv v10, v10, v8 +; RV32F-NEXT: li a1, 64 +; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; RV32F-NEXT: vminu.vx v8, v10, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_nxv2i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; RV64F-NEXT: vmv.v.x v10, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v11, v8 +; RV64F-NEXT: vsrl.vi v8, v11, 23 +; RV64F-NEXT: vwsubu.vv v12, v10, v8 +; RV64F-NEXT: li a1, 64 +; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; RV64F-NEXT: vminu.vx v8, v12, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_nxv2i64: ; CHECK-D: # %bb.0: @@ -1511,21 +1541,36 @@ define @ctlz_nxv4i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_nxv4i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-F-NEXT: vmv.v.x v12, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-F-NEXT: vsrl.vi v8, v16, 23 -; CHECK-F-NEXT: vwsubu.wv v12, v12, v8 -; CHECK-F-NEXT: li a1, 64 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma -; CHECK-F-NEXT: vminu.vx v8, v12, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_nxv4i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32F-NEXT: vmv.v.x v12, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v16, v8 +; RV32F-NEXT: vsrl.vi v8, v16, 23 +; RV32F-NEXT: vwsubu.wv v12, v12, v8 +; RV32F-NEXT: li a1, 64 +; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma +; RV32F-NEXT: vminu.vx v8, v12, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_nxv4i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; RV64F-NEXT: vmv.v.x v12, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v14, v8 +; RV64F-NEXT: vsrl.vi v8, v14, 23 +; RV64F-NEXT: vwsubu.vv v16, v12, v8 +; RV64F-NEXT: li a1, 64 +; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma +; RV64F-NEXT: vminu.vx v8, v16, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_nxv4i64: ; CHECK-D: # %bb.0: @@ -1652,21 +1697,36 @@ define @ctlz_nxv8i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_nxv8i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-F-NEXT: vmv.v.x v16, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v24, v8 -; CHECK-F-NEXT: vsrl.vi v8, v24, 23 -; CHECK-F-NEXT: vwsubu.wv v16, v16, v8 -; CHECK-F-NEXT: li a1, 64 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma -; CHECK-F-NEXT: vminu.vx v8, v16, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_nxv8i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32F-NEXT: vmv.v.x v16, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v24, v8 +; RV32F-NEXT: vsrl.vi v8, v24, 23 +; RV32F-NEXT: vwsubu.wv v16, v16, v8 +; RV32F-NEXT: li a1, 64 +; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma +; RV32F-NEXT: vminu.vx v8, v16, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_nxv8i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; RV64F-NEXT: vmv.v.x v16, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v20, v8 +; RV64F-NEXT: vsrl.vi v8, v20, 23 +; RV64F-NEXT: vwsubu.vv v24, v16, v8 +; RV64F-NEXT: li a1, 64 +; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma +; RV64F-NEXT: vminu.vx v8, v24, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_nxv8i64: ; CHECK-D: # %bb.0: @@ -2835,19 +2895,31 @@ define @ctlz_zero_undef_nxv1i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_zero_undef_nxv1i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m1, ta, ma -; CHECK-F-NEXT: vmv.v.x v9, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-F-NEXT: vsrl.vi v8, v10, 23 -; CHECK-F-NEXT: vwsubu.wv v9, v9, v8 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: vmv1r.v v8, v9 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_zero_undef_nxv1i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma +; RV32F-NEXT: vmv.v.x v9, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v10, v8 +; RV32F-NEXT: vsrl.vi v8, v10, 23 +; RV32F-NEXT: vwsubu.wv v9, v9, v8 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: vmv1r.v v8, v9 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_zero_undef_nxv1i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma +; RV64F-NEXT: vmv.v.x v9, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v10, v8 +; RV64F-NEXT: vsrl.vi v10, v10, 23 +; RV64F-NEXT: vwsubu.vv v8, v9, v10 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64: ; CHECK-D: # %bb.0: @@ -2971,19 +3043,31 @@ define @ctlz_zero_undef_nxv2i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_zero_undef_nxv2i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-F-NEXT: vmv.v.x v10, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-F-NEXT: vsrl.vi v8, v12, 23 -; CHECK-F-NEXT: vwsubu.wv v10, v10, v8 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: vmv2r.v v8, v10 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_zero_undef_nxv2i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma +; RV32F-NEXT: vmv.v.x v10, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v12, v8 +; RV32F-NEXT: vsrl.vi v8, v12, 23 +; RV32F-NEXT: vwsubu.wv v10, v10, v8 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: vmv2r.v v8, v10 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_zero_undef_nxv2i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, m1, ta, ma +; RV64F-NEXT: vmv.v.x v10, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v11, v8 +; RV64F-NEXT: vsrl.vi v11, v11, 23 +; RV64F-NEXT: vwsubu.vv v8, v10, v11 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64: ; CHECK-D: # %bb.0: @@ -3107,19 +3191,31 @@ define @ctlz_zero_undef_nxv4i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_zero_undef_nxv4i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m4, ta, ma -; CHECK-F-NEXT: vmv.v.x v12, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-F-NEXT: vsrl.vi v8, v16, 23 -; CHECK-F-NEXT: vwsubu.wv v12, v12, v8 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: vmv4r.v v8, v12 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_zero_undef_nxv4i64: +; RV32F: # %bb.0: +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma +; RV32F-NEXT: vmv.v.x v12, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v16, v8 +; RV32F-NEXT: vsrl.vi v8, v16, 23 +; RV32F-NEXT: vwsubu.wv v12, v12, v8 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: vmv4r.v v8, v12 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_zero_undef_nxv4i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; RV64F-NEXT: vmv.v.x v12, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v14, v8 +; RV64F-NEXT: vsrl.vi v14, v14, 23 +; RV64F-NEXT: vwsubu.vv v8, v12, v14 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64: ; CHECK-D: # %bb.0: @@ -3243,19 +3339,31 @@ define @ctlz_zero_undef_nxv8i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: ctlz_zero_undef_nxv8i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vmv8r.v v16, v8 -; CHECK-F-NEXT: li a0, 190 -; CHECK-F-NEXT: vsetvli a1, zero, e64, m8, ta, ma -; CHECK-F-NEXT: vmv.v.x v8, a0 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v24, v16 -; CHECK-F-NEXT: vsrl.vi v16, v24, 23 -; CHECK-F-NEXT: vwsubu.wv v8, v8, v16 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: ctlz_zero_undef_nxv8i64: +; RV32F: # %bb.0: +; RV32F-NEXT: vmv8r.v v16, v8 +; RV32F-NEXT: li a0, 190 +; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32F-NEXT: vmv.v.x v8, a0 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v24, v16 +; RV32F-NEXT: vsrl.vi v16, v24, 23 +; RV32F-NEXT: vwsubu.wv v8, v8, v16 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: ctlz_zero_undef_nxv8i64: +; RV64F: # %bb.0: +; RV64F-NEXT: li a0, 190 +; RV64F-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; RV64F-NEXT: vmv.v.x v16, a0 +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v20, v8 +; RV64F-NEXT: vsrl.vi v20, v20, 23 +; RV64F-NEXT: vwsubu.vv v8, v16, v20 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64: ; CHECK-D: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll index b14cde25aa85..d13f4d2dca1f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll @@ -1241,13 +1241,12 @@ define @cttz_nxv1i64( %va) { ; RV64F-NEXT: fsrmi a0, 1 ; RV64F-NEXT: vfncvt.f.xu.w v10, v9 ; RV64F-NEXT: vsrl.vi v9, v10, 23 -; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma -; RV64F-NEXT: vzext.vf2 v10, v9 ; RV64F-NEXT: li a1, 127 -; RV64F-NEXT: vsub.vx v9, v10, a1 +; RV64F-NEXT: vwsubu.vx v10, v9, a1 +; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; RV64F-NEXT: vmseq.vi v0, v8, 0 ; RV64F-NEXT: li a1, 64 -; RV64F-NEXT: vmerge.vxm v8, v9, a1, v0 +; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0 ; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: ret ; @@ -1404,13 +1403,12 @@ define @cttz_nxv2i64( %va) { ; RV64F-NEXT: fsrmi a0, 1 ; RV64F-NEXT: vfncvt.f.xu.w v12, v10 ; RV64F-NEXT: vsrl.vi v10, v12, 23 -; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; RV64F-NEXT: vzext.vf2 v12, v10 ; RV64F-NEXT: li a1, 127 -; RV64F-NEXT: vsub.vx v10, v12, a1 +; RV64F-NEXT: vwsubu.vx v12, v10, a1 +; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; RV64F-NEXT: vmseq.vi v0, v8, 0 ; RV64F-NEXT: li a1, 64 -; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0 +; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0 ; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: ret ; @@ -1567,13 +1565,12 @@ define @cttz_nxv4i64( %va) { ; RV64F-NEXT: fsrmi a0, 1 ; RV64F-NEXT: vfncvt.f.xu.w v16, v12 ; RV64F-NEXT: vsrl.vi v12, v16, 23 -; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma -; RV64F-NEXT: vzext.vf2 v16, v12 ; RV64F-NEXT: li a1, 127 -; RV64F-NEXT: vsub.vx v12, v16, a1 +; RV64F-NEXT: vwsubu.vx v16, v12, a1 +; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; RV64F-NEXT: vmseq.vi v0, v8, 0 ; RV64F-NEXT: li a1, 64 -; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0 +; RV64F-NEXT: vmerge.vxm v8, v16, a1, v0 ; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: ret ; @@ -1730,13 +1727,12 @@ define @cttz_nxv8i64( %va) { ; RV64F-NEXT: fsrmi a0, 1 ; RV64F-NEXT: vfncvt.f.xu.w v24, v16 ; RV64F-NEXT: vsrl.vi v16, v24, 23 -; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma -; RV64F-NEXT: vzext.vf2 v24, v16 ; RV64F-NEXT: li a1, 127 -; RV64F-NEXT: vsub.vx v16, v24, a1 +; RV64F-NEXT: vwsubu.vx v24, v16, a1 +; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64F-NEXT: vmseq.vi v0, v8, 0 ; RV64F-NEXT: li a1, 64 -; RV64F-NEXT: vmerge.vxm v8, v16, a1, v0 +; RV64F-NEXT: vmerge.vxm v8, v24, a1, v0 ; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: ret ; @@ -2891,21 +2887,35 @@ define @cttz_zero_undef_nxv1i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: cttz_zero_undef_nxv1i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma -; CHECK-F-NEXT: vrsub.vi v9, v8, 0 -; CHECK-F-NEXT: vand.vv v8, v8, v9 -; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-F-NEXT: vsrl.vi v8, v9, 23 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma -; CHECK-F-NEXT: vzext.vf2 v9, v8 -; CHECK-F-NEXT: li a1, 127 -; CHECK-F-NEXT: vsub.vx v8, v9, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: cttz_zero_undef_nxv1i64: +; RV32F: # %bb.0: +; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; RV32F-NEXT: vrsub.vi v9, v8, 0 +; RV32F-NEXT: vand.vv v8, v8, v9 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v9, v8 +; RV32F-NEXT: vsrl.vi v8, v9, 23 +; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma +; RV32F-NEXT: vzext.vf2 v9, v8 +; RV32F-NEXT: li a1, 127 +; RV32F-NEXT: vsub.vx v8, v9, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: cttz_zero_undef_nxv1i64: +; RV64F: # %bb.0: +; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; RV64F-NEXT: vrsub.vi v9, v8, 0 +; RV64F-NEXT: vand.vv v8, v8, v9 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v9, v8 +; RV64F-NEXT: vsrl.vi v9, v9, 23 +; RV64F-NEXT: li a1, 127 +; RV64F-NEXT: vwsubu.vx v8, v9, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: cttz_zero_undef_nxv1i64: ; CHECK-D: # %bb.0: @@ -3011,21 +3021,35 @@ define @cttz_zero_undef_nxv2i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: cttz_zero_undef_nxv2i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; CHECK-F-NEXT: vrsub.vi v10, v8, 0 -; CHECK-F-NEXT: vand.vv v8, v8, v10 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-F-NEXT: vsrl.vi v8, v10, 23 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma -; CHECK-F-NEXT: vzext.vf2 v10, v8 -; CHECK-F-NEXT: li a1, 127 -; CHECK-F-NEXT: vsub.vx v8, v10, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: cttz_zero_undef_nxv2i64: +; RV32F: # %bb.0: +; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; RV32F-NEXT: vrsub.vi v10, v8, 0 +; RV32F-NEXT: vand.vv v8, v8, v10 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v10, v8 +; RV32F-NEXT: vsrl.vi v8, v10, 23 +; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma +; RV32F-NEXT: vzext.vf2 v10, v8 +; RV32F-NEXT: li a1, 127 +; RV32F-NEXT: vsub.vx v8, v10, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: cttz_zero_undef_nxv2i64: +; RV64F: # %bb.0: +; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; RV64F-NEXT: vrsub.vi v10, v8, 0 +; RV64F-NEXT: vand.vv v8, v8, v10 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v10, v8 +; RV64F-NEXT: vsrl.vi v10, v10, 23 +; RV64F-NEXT: li a1, 127 +; RV64F-NEXT: vwsubu.vx v8, v10, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: cttz_zero_undef_nxv2i64: ; CHECK-D: # %bb.0: @@ -3131,21 +3155,35 @@ define @cttz_zero_undef_nxv4i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: cttz_zero_undef_nxv4i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma -; CHECK-F-NEXT: vrsub.vi v12, v8, 0 -; CHECK-F-NEXT: vand.vv v8, v8, v12 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-F-NEXT: vsrl.vi v8, v12, 23 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma -; CHECK-F-NEXT: vzext.vf2 v12, v8 -; CHECK-F-NEXT: li a1, 127 -; CHECK-F-NEXT: vsub.vx v8, v12, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: cttz_zero_undef_nxv4i64: +; RV32F: # %bb.0: +; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; RV32F-NEXT: vrsub.vi v12, v8, 0 +; RV32F-NEXT: vand.vv v8, v8, v12 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v12, v8 +; RV32F-NEXT: vsrl.vi v8, v12, 23 +; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma +; RV32F-NEXT: vzext.vf2 v12, v8 +; RV32F-NEXT: li a1, 127 +; RV32F-NEXT: vsub.vx v8, v12, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: cttz_zero_undef_nxv4i64: +; RV64F: # %bb.0: +; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; RV64F-NEXT: vrsub.vi v12, v8, 0 +; RV64F-NEXT: vand.vv v8, v8, v12 +; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v12, v8 +; RV64F-NEXT: vsrl.vi v12, v12, 23 +; RV64F-NEXT: li a1, 127 +; RV64F-NEXT: vwsubu.vx v8, v12, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: cttz_zero_undef_nxv4i64: ; CHECK-D: # %bb.0: @@ -3251,21 +3289,35 @@ define @cttz_zero_undef_nxv8i64( %va) { ; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: ret ; -; CHECK-F-LABEL: cttz_zero_undef_nxv8i64: -; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma -; CHECK-F-NEXT: vrsub.vi v16, v8, 0 -; CHECK-F-NEXT: vand.vv v8, v8, v16 -; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma -; CHECK-F-NEXT: fsrmi a0, 1 -; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-F-NEXT: vsrl.vi v8, v16, 23 -; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma -; CHECK-F-NEXT: vzext.vf2 v16, v8 -; CHECK-F-NEXT: li a1, 127 -; CHECK-F-NEXT: vsub.vx v8, v16, a1 -; CHECK-F-NEXT: fsrm a0 -; CHECK-F-NEXT: ret +; RV32F-LABEL: cttz_zero_undef_nxv8i64: +; RV32F: # %bb.0: +; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; RV32F-NEXT: vrsub.vi v16, v8, 0 +; RV32F-NEXT: vand.vv v8, v8, v16 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vfncvt.f.xu.w v16, v8 +; RV32F-NEXT: vsrl.vi v8, v16, 23 +; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma +; RV32F-NEXT: vzext.vf2 v16, v8 +; RV32F-NEXT: li a1, 127 +; RV32F-NEXT: vsub.vx v8, v16, a1 +; RV32F-NEXT: fsrm a0 +; RV32F-NEXT: ret +; +; RV64F-LABEL: cttz_zero_undef_nxv8i64: +; RV64F: # %bb.0: +; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; RV64F-NEXT: vrsub.vi v16, v8, 0 +; RV64F-NEXT: vand.vv v8, v8, v16 +; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vfncvt.f.xu.w v16, v8 +; RV64F-NEXT: vsrl.vi v16, v16, 23 +; RV64F-NEXT: li a1, 127 +; RV64F-NEXT: vwsubu.vx v8, v16, a1 +; RV64F-NEXT: fsrm a0 +; RV64F-NEXT: ret ; ; CHECK-D-LABEL: cttz_zero_undef_nxv8i64: ; CHECK-D: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll index 5dd01c654eff..21ddf1a6e114 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll @@ -1466,3 +1466,159 @@ define @vwadd_wv_disjoint_or( %x.i32, %x.i32, %y.i32 ret %or } + +define @vwadd_vx_splat_zext( %va, i32 %b) { +; RV32-LABEL: vwadd_vx_splat_zext: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw zero, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vwaddu.wv v16, v16, v8 +; RV32-NEXT: vmv8r.v v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vwadd_vx_splat_zext: +; RV64: # %bb.0: +; RV64-NEXT: andi a0, a0, -1 +; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; RV64-NEXT: vwaddu.vx v16, v8, a0 +; RV64-NEXT: vmv8r.v v8, v16 +; RV64-NEXT: ret + %zb = zext i32 %b to i64 + %head = insertelement poison, i64 %zb, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + %vc = zext %va to + %ve = add %vc, %splat + ret %ve +} + +define @vwadd_vx_splat_zext_i1( %va, i16 %b) { +; RV32-LABEL: vwadd_vx_splat_zext_i1: +; RV32: # %bb.0: +; RV32-NEXT: slli a0, a0, 16 +; RV32-NEXT: srli a0, a0, 16 +; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu +; RV32-NEXT: vmv.v.x v8, a0 +; RV32-NEXT: vadd.vi v8, v8, 1, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vwadd_vx_splat_zext_i1: +; RV64: # %bb.0: +; RV64-NEXT: slli a0, a0, 48 +; RV64-NEXT: srli a0, a0, 48 +; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu +; RV64-NEXT: vmv.v.x v8, a0 +; RV64-NEXT: vadd.vi v8, v8, 1, v0.t +; RV64-NEXT: ret + %zb = zext i16 %b to i32 + %head = insertelement poison, i32 %zb, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + %vc = zext %va to + %ve = add %vc, %splat + ret %ve +} + +define @vwadd_wx_splat_zext( %va, i32 %b) { +; RV32-LABEL: vwadd_wx_splat_zext: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -16 +; RV32-NEXT: .cfi_def_cfa_offset 16 +; RV32-NEXT: sw zero, 12(sp) +; RV32-NEXT: sw a0, 8(sp) +; RV32-NEXT: addi a0, sp, 8 +; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vlse64.v v16, (a0), zero +; RV32-NEXT: vadd.vv v8, v8, v16 +; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: ret +; +; RV64-LABEL: vwadd_wx_splat_zext: +; RV64: # %bb.0: +; RV64-NEXT: slli a0, a0, 32 +; RV64-NEXT: srli a0, a0, 32 +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV64-NEXT: vadd.vx v8, v8, a0 +; RV64-NEXT: ret + %zb = zext i32 %b to i64 + %head = insertelement poison, i64 %zb, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + %ve = add %va, %splat + ret %ve +} + +define @vwadd_vx_splat_sext( %va, i32 %b) { +; RV32-LABEL: vwadd_vx_splat_sext: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vmv.v.x v16, a0 +; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma +; RV32-NEXT: vwadd.wv v16, v16, v8 +; RV32-NEXT: vmv8r.v v8, v16 +; RV32-NEXT: ret +; +; RV64-LABEL: vwadd_vx_splat_sext: +; RV64: # %bb.0: +; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma +; RV64-NEXT: vwadd.vx v16, v8, a0 +; RV64-NEXT: vmv8r.v v8, v16 +; RV64-NEXT: ret + %sb = sext i32 %b to i64 + %head = insertelement poison, i64 %sb, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + %vc = sext %va to + %ve = add %vc, %splat + ret %ve +} + +define @vwadd_vx_splat_sext_i1( %va, i16 %b) { +; RV32-LABEL: vwadd_vx_splat_sext_i1: +; RV32: # %bb.0: +; RV32-NEXT: slli a0, a0, 16 +; RV32-NEXT: srai a0, a0, 16 +; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, mu +; RV32-NEXT: vmv.v.x v8, a0 +; RV32-NEXT: li a0, 1 +; RV32-NEXT: vsub.vx v8, v8, a0, v0.t +; RV32-NEXT: ret +; +; RV64-LABEL: vwadd_vx_splat_sext_i1: +; RV64: # %bb.0: +; RV64-NEXT: slli a0, a0, 48 +; RV64-NEXT: srai a0, a0, 48 +; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, mu +; RV64-NEXT: vmv.v.x v8, a0 +; RV64-NEXT: li a0, 1 +; RV64-NEXT: vsub.vx v8, v8, a0, v0.t +; RV64-NEXT: ret + %sb = sext i16 %b to i32 + %head = insertelement poison, i32 %sb, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + %vc = sext %va to + %ve = add %vc, %splat + ret %ve +} + +define @vwadd_wx_splat_sext( %va, i32 %b) { +; RV32-LABEL: vwadd_wx_splat_sext: +; RV32: # %bb.0: +; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV32-NEXT: vadd.vx v8, v8, a0 +; RV32-NEXT: ret +; +; RV64-LABEL: vwadd_wx_splat_sext: +; RV64: # %bb.0: +; RV64-NEXT: sext.w a0, a0 +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma +; RV64-NEXT: vadd.vx v8, v8, a0 +; RV64-NEXT: ret + %sb = sext i32 %b to i64 + %head = insertelement poison, i64 %sb, i32 0 + %splat = shufflevector %head, poison, zeroinitializer + %ve = add %va, %splat + ret %ve +} diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll index 72fc9c918f22..41ec2fc443d0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV32ZVBB +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV64ZVBB ; ============================================================================== ; i32 -> i64 @@ -864,12 +864,19 @@ define @vwsll_vi_nxv2i64_nxv2i8( %a) { ; CHECK-NEXT: vsll.vi v8, v10, 2 ; CHECK-NEXT: ret ; -; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8: -; CHECK-ZVBB: # %bb.0: -; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma -; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8 -; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2 -; CHECK-ZVBB-NEXT: ret +; RV32ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8: +; RV32ZVBB: # %bb.0: +; RV32ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; RV32ZVBB-NEXT: vzext.vf8 v10, v8 +; RV32ZVBB-NEXT: vsll.vi v8, v10, 2 +; RV32ZVBB-NEXT: ret +; +; RV64ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8: +; RV64ZVBB: # %bb.0: +; RV64ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma +; RV64ZVBB-NEXT: vzext.vf4 v10, v8 +; RV64ZVBB-NEXT: vwsll.vi v8, v10, 2 +; RV64ZVBB-NEXT: ret %x = zext %a to %z = shl %x, splat (i64 2) ret %z -- GitLab From 299b636a8f1c9cb2382f9dce4cdf6ec6330a79c6 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Wed, 10 Apr 2024 14:40:07 +0800 Subject: [PATCH 374/695] Revert "Reland "[Win32][ELF] Make CodeView a DebugInfoFormat only for COFF format" (#87987)" This reverts commit 4a93872a4f57d2f205826052150fadc36490445f. Sorry, there're still buildbot failures. --- clang/lib/Driver/ToolChains/MSVC.h | 5 +++-- clang/test/Driver/gcodeview-command-line.c | 1 - clang/test/Misc/win32-elf.c | 5 ----- 3 files changed, 3 insertions(+), 8 deletions(-) delete mode 100644 clang/test/Misc/win32-elf.c diff --git a/clang/lib/Driver/ToolChains/MSVC.h b/clang/lib/Driver/ToolChains/MSVC.h index 3950a8ed38e8..48369e030aad 100644 --- a/clang/lib/Driver/ToolChains/MSVC.h +++ b/clang/lib/Driver/ToolChains/MSVC.h @@ -61,8 +61,9 @@ public: /// formats, and to DWARF otherwise. Users can use -gcodeview and -gdwarf to /// override the default. llvm::codegenoptions::DebugInfoFormat getDefaultDebugFormat() const override { - return getTriple().isOSBinFormatCOFF() ? llvm::codegenoptions::DIF_CodeView - : llvm::codegenoptions::DIF_DWARF; + return getTriple().isOSBinFormatMachO() + ? llvm::codegenoptions::DIF_DWARF + : llvm::codegenoptions::DIF_CodeView; } /// Set the debugger tuning to "default", since we're definitely not tuning diff --git a/clang/test/Driver/gcodeview-command-line.c b/clang/test/Driver/gcodeview-command-line.c index 83542fc71aec..da8708af3224 100644 --- a/clang/test/Driver/gcodeview-command-line.c +++ b/clang/test/Driver/gcodeview-command-line.c @@ -1,6 +1,5 @@ // Note: %s must be preceded by --, otherwise it may be interpreted as a // command-line option, e.g. on Mac where %s is commonly under /Users. -// REQUIRES: aarch64-registered-target,arm-registered-target,x86-registered-target // ON-NOT: "-gno-codview-commandline" // OFF: "-gno-codeview-command-line" diff --git a/clang/test/Misc/win32-elf.c b/clang/test/Misc/win32-elf.c deleted file mode 100644 index f75281dc4187..000000000000 --- a/clang/test/Misc/win32-elf.c +++ /dev/null @@ -1,5 +0,0 @@ -// Check that basic use of win32-elf targets works. -// RUN: %clang -fsyntax-only -target x86_64-pc-win32-elf %s - -// RUN: %clang -fsyntax-only -target x86_64-pc-win32-elf -g %s -### 2>&1 | FileCheck %s -check-prefix=DEBUG-INFO -// DEBUG-INFO: -dwarf-version={{.*}} -- GitLab From 4e85e1ffcaf161736e27a24c291c1177be865976 Mon Sep 17 00:00:00 2001 From: Dinar Temirbulatov Date: Wed, 10 Apr 2024 08:39:50 +0100 Subject: [PATCH 375/695] [Clang][AArch64] Warn when calling non/streaming about vector size difference (#79842) The compiler doesn't know in advance if the streaming and non-streaming vector-lengths are different, so it should be safe to give a warning diagnostic to warn the user about possible undefined behaviour. If the user knows the vector lengths are equal, they can disable the warning separately. --- clang/include/clang/Basic/DiagnosticGroups.td | 3 + .../clang/Basic/DiagnosticSemaKinds.td | 10 ++ clang/lib/Sema/SemaChecking.cpp | 22 ++- clang/lib/Sema/SemaDecl.cpp | 12 +- .../Sema/aarch64-incompat-sm-builtin-calls.c | 6 +- clang/test/Sema/aarch64-sme-func-attrs.c | 136 +++++++++++++++++- 6 files changed, 184 insertions(+), 5 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticGroups.td b/clang/include/clang/Basic/DiagnosticGroups.td index 5251774ff4ef..47747d8704b6 100644 --- a/clang/include/clang/Basic/DiagnosticGroups.td +++ b/clang/include/clang/Basic/DiagnosticGroups.td @@ -1412,6 +1412,9 @@ def MultiGPU: DiagGroup<"multi-gpu">; // libc and the CRT to be skipped. def AVRRtlibLinkingQuirks : DiagGroup<"avr-rtlib-linking-quirks">; +// A warning group related to AArch64 SME function attribues. +def AArch64SMEAttributes : DiagGroup<"aarch64-sme-attributes">; + // A warning group for things that will change semantics in the future. def FutureCompat : DiagGroup<"future-compat">; diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 1c068f6cdb42..64c58ab36338 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -3755,6 +3755,16 @@ def err_sme_definition_using_za_in_non_sme_target : Error< "function using ZA state requires 'sme'">; def err_sme_definition_using_zt0_in_non_sme2_target : Error< "function using ZT0 state requires 'sme2'">; +def warn_sme_streaming_pass_return_vl_to_non_streaming : Warning< + "passing a VL-dependent argument to/from a function that has a different" + " streaming-mode. The streaming and non-streaming vector lengths may be" + " different">, + InGroup, DefaultIgnore; +def warn_sme_locally_streaming_has_vl_args_returns : Warning< + "passing/returning a VL-dependent argument to/from a __arm_locally_streaming" + " function. The streaming and non-streaming vector" + " lengths may be different">, + InGroup, DefaultIgnore; def err_conflicting_attributes_arm_state : Error< "conflicting attributes for state '%0'">; def err_sme_streaming_cannot_be_multiversioned : Error< diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index b84a779b7189..abfd9a303157 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -7938,6 +7938,7 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, // For variadic functions, we may have more args than parameters. // For some K&R functions, we may have less args than parameters. const auto N = std::min(Proto->getNumParams(), Args.size()); + bool AnyScalableArgsOrRet = Proto->getReturnType()->isSizelessVectorType(); for (unsigned ArgIdx = 0; ArgIdx < N; ++ArgIdx) { // Args[ArgIdx] can be null in malformed code. if (const Expr *Arg = Args[ArgIdx]) { @@ -7951,6 +7952,8 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, checkAIXMemberAlignment((Arg->getExprLoc()), Arg); QualType ParamTy = Proto->getParamType(ArgIdx); + if (ParamTy->isSizelessVectorType()) + AnyScalableArgsOrRet = true; QualType ArgTy = Arg->getType(); CheckArgAlignment(Arg->getExprLoc(), FDecl, std::to_string(ArgIdx + 1), ArgTy, ParamTy); @@ -7971,6 +7974,23 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, } } + // If the call requires a streaming-mode change and has scalable vector + // arguments or return values, then warn the user that the streaming and + // non-streaming vector lengths may be different. + const auto *CallerFD = dyn_cast(CurContext); + if (CallerFD && (!FD || !FD->getBuiltinID()) && AnyScalableArgsOrRet) { + bool IsCalleeStreaming = + ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask; + bool IsCalleeStreamingCompatible = + ExtInfo.AArch64SMEAttributes & + FunctionType::SME_PStateSMCompatibleMask; + ArmStreamingType CallerFnType = getArmStreamingFnType(CallerFD); + if (!IsCalleeStreamingCompatible && + (CallerFnType == ArmStreamingCompatible || + ((CallerFnType == ArmStreaming) ^ IsCalleeStreaming))) + Diag(Loc, diag::warn_sme_streaming_pass_return_vl_to_non_streaming); + } + FunctionType::ArmStateValue CalleeArmZAState = FunctionType::getArmZAState(ExtInfo.AArch64SMEAttributes); FunctionType::ArmStateValue CalleeArmZT0State = @@ -7979,7 +7999,7 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, CalleeArmZT0State != FunctionType::ARM_None) { bool CallerHasZAState = false; bool CallerHasZT0State = false; - if (const auto *CallerFD = dyn_cast(CurContext)) { + if (CallerFD) { auto *Attr = CallerFD->getAttr(); if (Attr && Attr->isNewZA()) CallerHasZAState = true; diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index c790dab72dd7..8472aaeb6bad 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -12395,12 +12395,22 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, } // Check if the function definition uses any AArch64 SME features without - // having the '+sme' feature enabled. + // having the '+sme' feature enabled and warn user if sme locally streaming + // function returns or uses arguments with VL-based types. if (DeclIsDefn) { const auto *Attr = NewFD->getAttr(); bool UsesSM = NewFD->hasAttr(); bool UsesZA = Attr && Attr->isNewZA(); bool UsesZT0 = Attr && Attr->isNewZT0(); + + if (NewFD->hasAttr()) { + if (NewFD->getReturnType()->isSizelessVectorType() || + llvm::any_of(NewFD->parameters(), [](ParmVarDecl *P) { + return P->getOriginalType()->isSizelessVectorType(); + })) + Diag(NewFD->getLocation(), + diag::warn_sme_locally_streaming_has_vl_args_returns); + } if (const auto *FPT = NewFD->getType()->getAs()) { FunctionProtoType::ExtProtoInfo EPI = FPT->getExtProtoInfo(); UsesSM |= diff --git a/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c b/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c index 55c97c73e8b6..6a1feeb9bf53 100644 --- a/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c +++ b/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ -// RUN: -target-feature +sme2 -target-feature +sve2 -target-feature +neon -fsyntax-only -verify %s +// RUN: -target-feature +sme2 -target-feature +sve2 -target-feature +neon -Waarch64-sme-attributes -fsyntax-only -verify %s // REQUIRES: aarch64-registered-target @@ -33,6 +33,7 @@ svuint32_t incompat_sve_sm(svbool_t pg, svuint32_t a, int16_t b) __arm_streaming return __builtin_sve_svld1_gather_u32base_index_u32(pg, a, b); } +// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} __arm_locally_streaming svuint32_t incompat_sve_ls(svbool_t pg, svuint32_t a, int64_t b) { // expected-warning@+1 {{builtin call has undefined behaviour when called from a streaming function}} return __builtin_sve_svld1_gather_u32base_index_u32(pg, a, b); @@ -48,6 +49,7 @@ svuint32_t incompat_sve2_sm(svbool_t pg, svuint32_t a, int64_t b) __arm_streamin return __builtin_sve_svldnt1_gather_u32base_index_u32(pg, a, b); } +// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} __arm_locally_streaming svuint32_t incompat_sve2_ls(svbool_t pg, svuint32_t a, int64_t b) { // expected-warning@+1 {{builtin call has undefined behaviour when called from a streaming function}} return __builtin_sve_svldnt1_gather_u32base_index_u32(pg, a, b); @@ -68,6 +70,7 @@ svfloat64_t streaming_caller_sve(svbool_t pg, svfloat64_t a, float64_t b) __arm_ return svadd_n_f64_m(pg, a, b); } +// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} __arm_locally_streaming svfloat64_t locally_streaming_caller_sve(svbool_t pg, svfloat64_t a, float64_t b) { // expected-no-warning return svadd_n_f64_m(pg, a, b); @@ -83,6 +86,7 @@ svint16_t streaming_caller_sve2(svint16_t op1, svint16_t op2) __arm_streaming { return svmul_lane_s16(op1, op2, 0); } +// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} __arm_locally_streaming svint16_t locally_streaming_caller_sve2(svint16_t op1, svint16_t op2) { // expected-no-warning return svmul_lane_s16(op1, op2, 0); diff --git a/clang/test/Sema/aarch64-sme-func-attrs.c b/clang/test/Sema/aarch64-sme-func-attrs.c index bfc8768c3f36..12de16509ccb 100644 --- a/clang/test/Sema/aarch64-sme-func-attrs.c +++ b/clang/test/Sema/aarch64-sme-func-attrs.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -fsyntax-only -verify=expected-cpp -x c++ %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -Waarch64-sme-attributes -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -Waarch64-sme-attributes -fsyntax-only -verify=expected-cpp -x c++ %s // Valid attributes @@ -496,3 +496,135 @@ void fmv_caller() { just_fine(); incompatible_locally_streaming(); } + +void sme_streaming_with_vl_arg(__SVInt8_t a) __arm_streaming { } + +__SVInt8_t sme_streaming_returns_vl(void) __arm_streaming { __SVInt8_t r; return r; } + +void sme_streaming_compatible_with_vl_arg(__SVInt8_t a) __arm_streaming_compatible { } + +__SVInt8_t sme_streaming_compatible_returns_vl(void) __arm_streaming_compatible { __SVInt8_t r; return r; } + +void sme_no_streaming_with_vl_arg(__SVInt8_t a) { } + +__SVInt8_t sme_no_streaming_returns_vl(void) { __SVInt8_t r; return r; } + +// expected-warning@+2 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-cpp-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +__arm_locally_streaming void sme_locally_streaming_with_vl_arg(__SVInt8_t a) { } + +// expected-warning@+2 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-cpp-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +__arm_locally_streaming __SVInt8_t sme_locally_streaming_returns_vl(void) { __SVInt8_t r; return r; } + +void sme_no_streaming_calling_streaming_with_vl_args() { + __SVInt8_t a; + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + sme_streaming_with_vl_arg(a); +} + +void sme_no_streaming_calling_streaming_with_return_vl() { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + __SVInt8_t r = sme_streaming_returns_vl(); +} + +void sme_streaming_calling_non_streaming_with_vl_args(void) __arm_streaming { + __SVInt8_t a; + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + sme_no_streaming_with_vl_arg(a); +} + +void sme_streaming_calling_non_streaming_with_return_vl(void) __arm_streaming { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + __SVInt8_t r = sme_no_streaming_returns_vl(); +} + +void sme_no_streaming_calling_streaming_with_vl_args_param(__SVInt8_t arg, void (*sc)( __SVInt8_t arg) __arm_streaming) { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + sc(arg); +} + +__SVInt8_t sme_no_streaming_calling_streaming_return_vl_param(__SVInt8_t (*s)(void) __arm_streaming) { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + return s(); +} + +void sme_streaming_compatible_calling_streaming_with_vl_args(__SVInt8_t arg) __arm_streaming_compatible { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + sme_streaming_with_vl_arg(arg); +} + +void sme_streaming_compatible_calling_sme_streaming_return_vl(void) __arm_streaming_compatible { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + __SVInt8_t r = sme_streaming_returns_vl(); +} + +void sme_streaming_compatible_calling_no_streaming_with_vl_args(__SVInt8_t arg) __arm_streaming_compatible { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + sme_no_streaming_with_vl_arg(arg); +} + +void sme_streaming_compatible_calling_no_sme_streaming_return_vl(void) __arm_streaming_compatible { + // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + __SVInt8_t r = sme_no_streaming_returns_vl(); +} + +void sme_streaming_calling_streaming(__SVInt8_t arg, void (*s)( __SVInt8_t arg) __arm_streaming) __arm_streaming { + s(arg); +} + +__SVInt8_t sme_streaming_calling_streaming_return_vl(__SVInt8_t (*s)(void) __arm_streaming) __arm_streaming { + return s(); +} + +void sme_streaming_calling_streaming_with_vl_args(__SVInt8_t a) __arm_streaming { + sme_streaming_with_vl_arg(a); +} + +void sme_streaming_calling_streaming_with_return_vl(void) __arm_streaming { + __SVInt8_t r = sme_streaming_returns_vl(); +} + +void sme_streaming_calling_streaming_compatible_with_vl_args(__SVInt8_t a) __arm_streaming { + sme_streaming_compatible_with_vl_arg(a); +} + +void sme_streaming_calling_streaming_compatible_with_return_vl(void) __arm_streaming { + __SVInt8_t r = sme_streaming_compatible_returns_vl(); +} + +void sme_no_streaming_calling_streaming_compatible_with_vl_args() { + __SVInt8_t a; + sme_streaming_compatible_with_vl_arg(a); +} + +void sme_no_streaming_calling_streaming_compatible_with_return_vl() { + __SVInt8_t r = sme_streaming_compatible_returns_vl(); +} + +void sme_no_streaming_calling_non_streaming_compatible_with_vl_args() { + __SVInt8_t a; + sme_no_streaming_with_vl_arg(a); +} + +void sme_no_streaming_calling_non_streaming_compatible_with_return_vl() { + __SVInt8_t r = sme_no_streaming_returns_vl(); +} + +void sme_streaming_compatible_calling_streaming_compatible_with_vl_args(__SVInt8_t arg) __arm_streaming_compatible { + sme_streaming_compatible_with_vl_arg(arg); +} + +void sme_streaming_compatible_calling_streaming_compatible_with_return_vl(void) __arm_streaming_compatible { + __SVInt8_t r = sme_streaming_compatible_returns_vl(); +} -- GitLab From e50c4c83b6d3f595b0eec9c9600fb3de1147fef7 Mon Sep 17 00:00:00 2001 From: Paschalis Mpeis Date: Wed, 10 Apr 2024 09:34:46 +0100 Subject: [PATCH 376/695] [AArch64][TLI] Add TLI mappings for ArmPL modf, sincos, sincospi (#83143) ArmPL 24.04 release fixes a bug concerning these methods, so now they can be re-introduced to TLI mappings. --- llvm/include/llvm/Analysis/VecFuncs.def | 6 ++ .../AArch64/veclib-function-calls.ll | 66 ++++++++++--------- llvm/test/Transforms/Util/add-TLI-mappings.ll | 32 +++++++-- 3 files changed, 67 insertions(+), 37 deletions(-) diff --git a/llvm/include/llvm/Analysis/VecFuncs.def b/llvm/include/llvm/Analysis/VecFuncs.def index 394e4a05fbc0..10f1333cf888 100644 --- a/llvm/include/llvm/Analysis/VecFuncs.def +++ b/llvm/include/llvm/Analysis/VecFuncs.def @@ -1005,6 +1005,8 @@ TLI_DEFINE_VECFUNC("llvm.log2.f32", "armpl_svlog2_f32_x", SCALABLE(4), MASKED, " TLI_DEFINE_VECFUNC("modf", "armpl_vmodfq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vl8") TLI_DEFINE_VECFUNC("modff", "armpl_vmodfq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vl4") +TLI_DEFINE_VECFUNC("modf", "armpl_svmodf_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvl8") +TLI_DEFINE_VECFUNC("modff", "armpl_svmodf_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvl4") TLI_DEFINE_VECFUNC("nextafter", "armpl_vnextafterq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vv") TLI_DEFINE_VECFUNC("nextafterf", "armpl_vnextafterq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vv") @@ -1033,9 +1035,13 @@ TLI_DEFINE_VECFUNC("llvm.sin.f32", "armpl_svsin_f32_x", SCALABLE(4), MASKED, "_Z TLI_DEFINE_VECFUNC("sincos", "armpl_vsincosq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vl8l8") TLI_DEFINE_VECFUNC("sincosf", "armpl_vsincosq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vl4l4") +TLI_DEFINE_VECFUNC("sincos", "armpl_svsincos_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvl8l8") +TLI_DEFINE_VECFUNC("sincosf", "armpl_svsincos_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvl4l4") TLI_DEFINE_VECFUNC("sincospi", "armpl_vsincospiq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2vl8l8") TLI_DEFINE_VECFUNC("sincospif", "armpl_vsincospiq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4vl4l4") +TLI_DEFINE_VECFUNC("sincospi", "armpl_svsincospi_f64_x", SCALABLE(2), MASKED, "_ZGVsMxvl8l8") +TLI_DEFINE_VECFUNC("sincospif", "armpl_svsincospi_f32_x", SCALABLE(4), MASKED, "_ZGVsMxvl4l4") TLI_DEFINE_VECFUNC("sinh", "armpl_vsinhq_f64", FIXED(2), NOMASK, "_ZGV_LLVM_N2v") TLI_DEFINE_VECFUNC("sinhf", "armpl_vsinhq_f32", FIXED(4), NOMASK, "_ZGV_LLVM_N4v") diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll b/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll index dd1495626eb9..d9cc630482fc 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll @@ -2925,11 +2925,12 @@ define void @modf_f64(ptr noalias %a, ptr noalias %b, ptr noalias %c) { ; ; ARMPL-SVE-LABEL: define void @modf_f64 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE: [[DATA:%.*]] = call double @modf(double [[NUM:%.*]], ptr [[GEPB:%.*]]) #[[ATTR4:[0-9]+]] +; ARMPL-SVE: [[TMP23:%.*]] = call @armpl_svmodf_f64_x( [[WIDE_MASKED_LOAD:%.*]], ptr [[TMP22:%.*]], [[ACTIVE_LANE_MASK:%.*]]) ; ; ARMPL-SVE-NOPRED-LABEL: define void @modf_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE-NOPRED: [[TMP5:%.*]] = call <2 x double> @armpl_vmodfq_f64(<2 x double> [[WIDE_LOAD:%.*]], ptr [[TMP4:%.*]]) +; ARMPL-SVE-NOPRED: [[TMP17:%.*]] = call @armpl_svmodf_f64_x( [[WIDE_LOAD:%.*]], ptr [[TMP16:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; ARMPL-SVE-NOPRED: [[DATA:%.*]] = call double @modf(double [[NUM:%.*]], ptr [[GEPB:%.*]]) #[[ATTR64:[0-9]+]] ; entry: br label %for.body @@ -2970,11 +2971,12 @@ define void @modf_f32(ptr noalias %a, ptr noalias %b, ptr noalias %c) { ; ; ARMPL-SVE-LABEL: define void @modf_f32 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE: [[DATA:%.*]] = call float @modff(float [[NUM:%.*]], ptr [[GEPB:%.*]]) #[[ATTR5:[0-9]+]] +; ARMPL-SVE: [[TMP23:%.*]] = call @armpl_svmodf_f32_x( [[WIDE_MASKED_LOAD:%.*]], ptr [[TMP22:%.*]], [[ACTIVE_LANE_MASK:%.*]]) ; ; ARMPL-SVE-NOPRED-LABEL: define void @modf_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE-NOPRED: [[TMP5:%.*]] = call <4 x float> @armpl_vmodfq_f32(<4 x float> [[WIDE_LOAD:%.*]], ptr [[TMP4:%.*]]) +; ARMPL-SVE-NOPRED: [[TMP17:%.*]] = call @armpl_svmodf_f32_x( [[WIDE_LOAD:%.*]], ptr [[TMP16:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; ARMPL-SVE-NOPRED: [[DATA:%.*]] = call float @modff(float [[NUM:%.*]], ptr [[GEPB:%.*]]) #[[ATTR65:[0-9]+]] ; entry: br label %for.body @@ -3023,7 +3025,7 @@ define void @nextafter_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @nextafter_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svnextafter_f64_x( [[WIDE_LOAD:%.*]], [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @nextafter(double [[IN:%.*]], double [[IN]]) #[[ATTR64:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @nextafter(double [[IN:%.*]], double [[IN]]) #[[ATTR66:[0-9]+]] ; entry: br label %for.body @@ -3068,7 +3070,7 @@ define void @nextafter_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @nextafter_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svnextafter_f32_x( [[WIDE_LOAD:%.*]], [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @nextafterf(float [[IN:%.*]], float [[IN]]) #[[ATTR65:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @nextafterf(float [[IN:%.*]], float [[IN]]) #[[ATTR67:[0-9]+]] ; entry: br label %for.body @@ -3116,7 +3118,7 @@ define void @pow_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @pow_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svpow_f64_x( [[WIDE_LOAD:%.*]], [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @pow(double [[IN:%.*]], double [[IN]]) #[[ATTR66:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @pow(double [[IN:%.*]], double [[IN]]) #[[ATTR68:[0-9]+]] ; entry: br label %for.body @@ -3161,7 +3163,7 @@ define void @pow_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @pow_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svpow_f32_x( [[WIDE_LOAD:%.*]], [[WIDE_LOAD]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @powf(float [[IN:%.*]], float [[IN]]) #[[ATTR67:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @powf(float [[IN:%.*]], float [[IN]]) #[[ATTR69:[0-9]+]] ; entry: br label %for.body @@ -3209,7 +3211,7 @@ define void @sin_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sin_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsin_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sin(double [[IN:%.*]]) #[[ATTR68:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sin(double [[IN:%.*]]) #[[ATTR70:[0-9]+]] ; entry: br label %for.body @@ -3254,7 +3256,7 @@ define void @sin_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sin_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsin_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sinf(float [[IN:%.*]]) #[[ATTR69:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sinf(float [[IN:%.*]]) #[[ATTR71:[0-9]+]] ; entry: br label %for.body @@ -3297,11 +3299,12 @@ define void @sincos_f64(ptr noalias %a, ptr noalias %b, ptr noalias %c) { ; ; ARMPL-SVE-LABEL: define void @sincos_f64 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE: call void @sincos(double [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR6:[0-9]+]] +; ARMPL-SVE: call void @armpl_svsincos_f64_x( [[WIDE_MASKED_LOAD:%.*]], ptr [[TMP23:%.*]], ptr [[TMP24:%.*]], [[ACTIVE_LANE_MASK:%.*]]) ; ; ARMPL-SVE-NOPRED-LABEL: define void @sincos_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE-NOPRED: call void @armpl_vsincosq_f64(<2 x double> [[WIDE_LOAD:%.*]], ptr [[TMP5:%.*]], ptr [[TMP6:%.*]]) +; ARMPL-SVE-NOPRED: call void @armpl_svsincos_f64_x( [[WIDE_LOAD:%.*]], ptr [[TMP17:%.*]], ptr [[TMP18:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; ARMPL-SVE-NOPRED: call void @sincos(double [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR72:[0-9]+]] ; entry: br label %for.body @@ -3341,11 +3344,12 @@ define void @sincos_f32(ptr noalias %a, ptr noalias %b, ptr noalias %c) { ; ; ARMPL-SVE-LABEL: define void @sincos_f32 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE: call void @sincosf(float [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR7:[0-9]+]] +; ARMPL-SVE: call void @armpl_svsincos_f32_x( [[WIDE_MASKED_LOAD:%.*]], ptr [[TMP23:%.*]], ptr [[TMP24:%.*]], [[ACTIVE_LANE_MASK:%.*]]) ; ; ARMPL-SVE-NOPRED-LABEL: define void @sincos_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE-NOPRED: call void @armpl_vsincosq_f32(<4 x float> [[WIDE_LOAD:%.*]], ptr [[TMP5:%.*]], ptr [[TMP6:%.*]]) +; ARMPL-SVE-NOPRED: call void @armpl_svsincos_f32_x( [[WIDE_LOAD:%.*]], ptr [[TMP17:%.*]], ptr [[TMP18:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; ARMPL-SVE-NOPRED: call void @sincosf(float [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR73:[0-9]+]] ; entry: br label %for.body @@ -3388,11 +3392,12 @@ define void @sincospi_f64(ptr noalias %a, ptr noalias %b, ptr noalias %c) { ; ; ARMPL-SVE-LABEL: define void @sincospi_f64 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE: call void @sincospi(double [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR8:[0-9]+]] +; ARMPL-SVE: call void @armpl_svsincospi_f64_x( [[WIDE_MASKED_LOAD:%.*]], ptr [[TMP23:%.*]], ptr [[TMP24:%.*]], [[ACTIVE_LANE_MASK:%.*]]) ; ; ARMPL-SVE-NOPRED-LABEL: define void @sincospi_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE-NOPRED: call void @armpl_vsincospiq_f64(<2 x double> [[WIDE_LOAD:%.*]], ptr [[TMP5:%.*]], ptr [[TMP6:%.*]]) +; ARMPL-SVE-NOPRED: call void @armpl_svsincospi_f64_x( [[WIDE_LOAD:%.*]], ptr [[TMP17:%.*]], ptr [[TMP18:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; ARMPL-SVE-NOPRED: call void @sincospi(double [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR74:[0-9]+]] ; entry: br label %for.body @@ -3432,11 +3437,12 @@ define void @sincospi_f32(ptr noalias %a, ptr noalias %b, ptr noalias %c) { ; ; ARMPL-SVE-LABEL: define void @sincospi_f32 ; ARMPL-SVE-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE: call void @sincospif(float [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR9:[0-9]+]] +; ARMPL-SVE: call void @armpl_svsincospi_f32_x( [[WIDE_MASKED_LOAD:%.*]], ptr [[TMP23:%.*]], ptr [[TMP24:%.*]], [[ACTIVE_LANE_MASK:%.*]]) ; ; ARMPL-SVE-NOPRED-LABEL: define void @sincospi_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] { -; ARMPL-SVE-NOPRED: call void @armpl_vsincospiq_f32(<4 x float> [[WIDE_LOAD:%.*]], ptr [[TMP5:%.*]], ptr [[TMP6:%.*]]) +; ARMPL-SVE-NOPRED: call void @armpl_svsincospi_f32_x( [[WIDE_LOAD:%.*]], ptr [[TMP17:%.*]], ptr [[TMP18:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; ARMPL-SVE-NOPRED: call void @sincospif(float [[NUM:%.*]], ptr [[GEPB:%.*]], ptr [[GEPC:%.*]]) #[[ATTR75:[0-9]+]] ; entry: br label %for.body @@ -3484,7 +3490,7 @@ define void @sinh_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sinh_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsinh_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sinh(double [[IN:%.*]]) #[[ATTR70:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sinh(double [[IN:%.*]]) #[[ATTR76:[0-9]+]] ; entry: br label %for.body @@ -3529,7 +3535,7 @@ define void @sinh_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sinh_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsinh_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sinhf(float [[IN:%.*]]) #[[ATTR71:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sinhf(float [[IN:%.*]]) #[[ATTR77:[0-9]+]] ; entry: br label %for.body @@ -3577,7 +3583,7 @@ define void @sinpi_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sinpi_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsinpi_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sinpi(double [[IN:%.*]]) #[[ATTR72:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sinpi(double [[IN:%.*]]) #[[ATTR78:[0-9]+]] ; entry: br label %for.body @@ -3622,7 +3628,7 @@ define void @sinpi_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sinpi_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsinpi_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sinpif(float [[IN:%.*]]) #[[ATTR73:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sinpif(float [[IN:%.*]]) #[[ATTR79:[0-9]+]] ; entry: br label %for.body @@ -3670,7 +3676,7 @@ define void @sqrt_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sqrt_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsqrt_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sqrt(double [[IN:%.*]]) #[[ATTR74:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @sqrt(double [[IN:%.*]]) #[[ATTR80:[0-9]+]] ; entry: br label %for.body @@ -3715,7 +3721,7 @@ define void @sqrt_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @sqrt_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svsqrt_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sqrtf(float [[IN:%.*]]) #[[ATTR75:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @sqrtf(float [[IN:%.*]]) #[[ATTR81:[0-9]+]] ; entry: br label %for.body @@ -3763,7 +3769,7 @@ define void @tan_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @tan_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svtan_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @tan(double [[IN:%.*]]) #[[ATTR76:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @tan(double [[IN:%.*]]) #[[ATTR82:[0-9]+]] ; entry: br label %for.body @@ -3808,7 +3814,7 @@ define void @tan_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @tan_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svtan_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @tanf(float [[IN:%.*]]) #[[ATTR77:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @tanf(float [[IN:%.*]]) #[[ATTR83:[0-9]+]] ; entry: br label %for.body @@ -3856,7 +3862,7 @@ define void @tanh_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @tanh_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svtanh_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @tanh(double [[IN:%.*]]) #[[ATTR78:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @tanh(double [[IN:%.*]]) #[[ATTR84:[0-9]+]] ; entry: br label %for.body @@ -3901,7 +3907,7 @@ define void @tanh_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @tanh_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svtanh_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @tanhf(float [[IN:%.*]]) #[[ATTR79:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @tanhf(float [[IN:%.*]]) #[[ATTR85:[0-9]+]] ; entry: br label %for.body @@ -3949,7 +3955,7 @@ define void @tgamma_f64(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @tgamma_f64 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svtgamma_f64_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @tgamma(double [[IN:%.*]]) #[[ATTR80:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call double @tgamma(double [[IN:%.*]]) #[[ATTR86:[0-9]+]] ; entry: br label %for.body @@ -3994,7 +4000,7 @@ define void @tgamma_f32(ptr noalias %in.ptr, ptr noalias %out.ptr) { ; ARMPL-SVE-NOPRED-LABEL: define void @tgamma_f32 ; ARMPL-SVE-NOPRED-SAME: (ptr noalias [[IN_PTR:%.*]], ptr noalias [[OUT_PTR:%.*]]) #[[ATTR0]] { ; ARMPL-SVE-NOPRED: [[TMP9:%.*]] = call @armpl_svtgamma_f32_x( [[WIDE_LOAD:%.*]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) -; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @tgammaf(float [[IN:%.*]]) #[[ATTR81:[0-9]+]] +; ARMPL-SVE-NOPRED: [[CALL:%.*]] = tail call float @tgammaf(float [[IN:%.*]]) #[[ATTR87:[0-9]+]] ; entry: br label %for.body diff --git a/llvm/test/Transforms/Util/add-TLI-mappings.ll b/llvm/test/Transforms/Util/add-TLI-mappings.ll index d86e44f199b3..0e005ae75ef5 100644 --- a/llvm/test/Transforms/Util/add-TLI-mappings.ll +++ b/llvm/test/Transforms/Util/add-TLI-mappings.ll @@ -46,15 +46,21 @@ ; SLEEFGNUABI-SAME: ptr @_ZGVsNxvl4l4_sincospif, ; SLEEFGNUABI_SAME; ptr @_ZGVnN4v_log10f, ; SLEEFGNUABI-SAME: ptr @_ZGVsMxv_log10f -; ARMPL-SAME: [10 x ptr] [ +; ARMPL-SAME: [16 x ptr] [ ; ARMPL-SAME: ptr @armpl_vmodfq_f64, +; ARMPL-SAME: ptr @armpl_svmodf_f64_x, ; ARMPL-SAME: ptr @armpl_vmodfq_f32, +; ARMPL-SAME: ptr @armpl_svmodf_f32_x, ; ARMPL-SAME: ptr @armpl_vsinq_f64, ; ARMPL-SAME: ptr @armpl_svsin_f64_x, ; ARMPL-SAME: ptr @armpl_vsincosq_f64, +; ARMPL-SAME: ptr @armpl_svsincos_f64_x, ; ARMPL-SAME: ptr @armpl_vsincosq_f32, +; ARMPL-SAME: ptr @armpl_svsincos_f32_x, ; ARMPL-SAME: ptr @armpl_vsincospiq_f64, +; ARMPL-SAME: ptr @armpl_svsincospi_f64_x, ; ARMPL-SAME: ptr @armpl_vsincospiq_f32, +; ARMPL-SAME: ptr @armpl_svsincospi_f32_x, ; ARMPL-SAME: ptr @armpl_vlog10q_f32, ; ARMPL-SAME: ptr @armpl_svlog10_f32_x ; COMMON-SAME: ], section "llvm.metadata" @@ -195,13 +201,19 @@ declare float @llvm.log10.f32(float) #0 ; SLEEFGNUABI: declare @_ZGVsMxv_log10f(, ) ; ARMPL: declare <2 x double> @armpl_vmodfq_f64(<2 x double>, ptr) +; ARMPL: declare @armpl_svmodf_f64_x(, ptr, ) ; ARMPL: declare <4 x float> @armpl_vmodfq_f32(<4 x float>, ptr) +; ARMPL: declare @armpl_svmodf_f32_x(, ptr, ) ; ARMPL: declare <2 x double> @armpl_vsinq_f64(<2 x double>) ; ARMPL: declare @armpl_svsin_f64_x(, ) ; ARMPL: declare void @armpl_vsincosq_f64(<2 x double>, ptr, ptr) +; ARMPL: declare void @armpl_svsincos_f64_x(, ptr, ptr, ) ; ARMPL: declare void @armpl_vsincosq_f32(<4 x float>, ptr, ptr) +; ARMPL: declare void @armpl_svsincos_f32_x(, ptr, ptr, ) ; ARMPL: declare void @armpl_vsincospiq_f64(<2 x double>, ptr, ptr) +; ARMPL: declare void @armpl_svsincospi_f64_x(, ptr, ptr, ) ; ARMPL: declare void @armpl_vsincospiq_f32(<4 x float>, ptr, ptr) +; ARMPL: declare void @armpl_svsincospi_f32_x(, ptr, ptr, ) ; ARMPL: declare <4 x float> @armpl_vlog10q_f32(<4 x float>) ; ARMPL: declare @armpl_svlog10_f32_x(, ) @@ -255,20 +267,26 @@ attributes #0 = { nounwind readnone } ; SLEEFGNUABI-SAME: _ZGVsMxv_llvm.log10.f32(_ZGVsMxv_log10f)" } ; ARMPL: attributes #[[MODF]] = { "vector-function-abi-variant"= -; ARMPL-SAME: "_ZGV_LLVM_N2vl8_modf(armpl_vmodfq_f64)" } +; ARMPL-SAME: "_ZGV_LLVM_N2vl8_modf(armpl_vmodfq_f64), +; ARMPL-SAME: _ZGVsMxvl8_modf(armpl_svmodf_f64_x)" } ; ARMPL: attributes #[[MODFF]] = { "vector-function-abi-variant"= -; ARMPL-SAME: "_ZGV_LLVM_N4vl4_modff(armpl_vmodfq_f32)" } +; ARMPL-SAME: "_ZGV_LLVM_N4vl4_modff(armpl_vmodfq_f32), +; ARMPL-SAME: _ZGVsMxvl4_modff(armpl_svmodf_f32_x)" } ; ARMPL: attributes #[[SIN]] = { "vector-function-abi-variant"= ; ARMPL-SAME: "_ZGV_LLVM_N2v_sin(armpl_vsinq_f64), ; ARMPL-SAME _ZGVsMxv_sin(armpl_svsin_f64_x)" } ; ARMPL: attributes #[[SINCOS]] = { "vector-function-abi-variant"= -; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincos(armpl_vsincosq_f64)" } +; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincos(armpl_vsincosq_f64), +; ARMPL-SAME: _ZGVsMxvl8l8_sincos(armpl_svsincos_f64_x)" } ; ARMPL: attributes #[[SINCOSF]] = { "vector-function-abi-variant"= -; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(armpl_vsincosq_f32)" } +; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(armpl_vsincosq_f32), +; ARMPL-SAME: _ZGVsMxvl4l4_sincosf(armpl_svsincos_f32_x)" } ; ARMPL: attributes #[[SINCOSPI]] = { "vector-function-abi-variant"= -; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(armpl_vsincospiq_f64)" } +; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(armpl_vsincospiq_f64), +; ARMPL-SAME: _ZGVsMxvl8l8_sincospi(armpl_svsincospi_f64_x)" } ; ARMPL: attributes #[[SINCOSPIF]] = { "vector-function-abi-variant"= -; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(armpl_vsincospiq_f32)" } +; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(armpl_vsincospiq_f32), +; ARMPL-SAME: _ZGVsMxvl4l4_sincospif(armpl_svsincospi_f32_x)" } ; ARMPL: attributes #[[LOG10]] = { "vector-function-abi-variant"= ; ARMPL-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(armpl_vlog10q_f32), ; ARMPL-SAME _ZGVsMxv_llvm.log10.f32(armpl_svlog10_f32_x)" } -- GitLab From b7a93bc1f230fe01f38f3648437cee74f339c5ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Wed, 10 Apr 2024 08:50:52 +0200 Subject: [PATCH 377/695] [clang][Interp] Start implementing vector types Map them to primtive arrays, much like complex types. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 28 ++++++++++++++++++++++++ clang/lib/AST/Interp/Context.cpp | 3 ++- clang/lib/AST/Interp/EvalEmitter.cpp | 3 ++- clang/lib/AST/Interp/Pointer.cpp | 19 ++++++++++++++++ clang/lib/AST/Interp/Program.cpp | 7 ++++++ clang/test/AST/Interp/vectors.cpp | 22 +++++++++++++++++++ 6 files changed, 80 insertions(+), 2 deletions(-) create mode 100644 clang/test/AST/Interp/vectors.cpp diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index a1ce65751483..acff63cd9dc0 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -1033,6 +1033,34 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { return true; } + if (const auto *VecT = E->getType()->getAs()) { + unsigned NumVecElements = VecT->getNumElements(); + assert(NumVecElements >= E->getNumInits()); + + QualType ElemQT = VecT->getElementType(); + PrimType ElemT = classifyPrim(ElemQT); + + // All initializer elements. + unsigned InitIndex = 0; + for (const Expr *Init : E->inits()) { + if (!this->visit(Init)) + return false; + + if (!this->emitInitElem(ElemT, InitIndex, E)) + return false; + ++InitIndex; + } + + // Fill the rest with zeroes. + for (; InitIndex != NumVecElements; ++InitIndex) { + if (!this->visitZeroInitializer(ElemT, ElemQT, E)) + return false; + if (!this->emitInitElem(ElemT, InitIndex, E)) + return false; + } + return true; + } + return false; } diff --git a/clang/lib/AST/Interp/Context.cpp b/clang/lib/AST/Interp/Context.cpp index 15a9d46880e9..274178837bf0 100644 --- a/clang/lib/AST/Interp/Context.cpp +++ b/clang/lib/AST/Interp/Context.cpp @@ -120,7 +120,8 @@ std::optional Context::classify(QualType T) const { if (T->isBooleanType()) return PT_Bool; - if (T->isAnyComplexType()) + // We map these to primitive arrays. + if (T->isAnyComplexType() || T->isVectorType()) return std::nullopt; if (T->isSignedIntegerOrEnumerationType()) { diff --git a/clang/lib/AST/Interp/EvalEmitter.cpp b/clang/lib/AST/Interp/EvalEmitter.cpp index caffb69d83e3..d764b4b6f6d1 100644 --- a/clang/lib/AST/Interp/EvalEmitter.cpp +++ b/clang/lib/AST/Interp/EvalEmitter.cpp @@ -51,7 +51,8 @@ EvaluationResult EvalEmitter::interpretDecl(const VarDecl *VD, this->CheckFullyInitialized = CheckFullyInitialized; this->ConvertResultToRValue = VD->getAnyInitializer() && - (VD->getAnyInitializer()->getType()->isAnyComplexType()); + (VD->getAnyInitializer()->getType()->isAnyComplexType() || + VD->getAnyInitializer()->getType()->isVectorType()); EvalResult.setSource(VD); if (!this->visitDecl(VD) && EvalResult.empty()) diff --git a/clang/lib/AST/Interp/Pointer.cpp b/clang/lib/AST/Interp/Pointer.cpp index 53998cc3233c..cddcd6b0151e 100644 --- a/clang/lib/AST/Interp/Pointer.cpp +++ b/clang/lib/AST/Interp/Pointer.cpp @@ -342,6 +342,25 @@ std::optional Pointer::toRValue(const Context &Ctx) const { return false; } + // Vector types. + if (const auto *VT = Ty->getAs()) { + assert(Ptr.getFieldDesc()->isPrimitiveArray()); + QualType ElemTy = VT->getElementType(); + PrimType ElemT = *Ctx.classify(ElemTy); + + SmallVector Values; + Values.reserve(VT->getNumElements()); + for (unsigned I = 0; I != VT->getNumElements(); ++I) { + TYPE_SWITCH(ElemT, { + Values.push_back(Ptr.atIndex(I).deref().toAPValue()); + }); + } + + assert(Values.size() == VT->getNumElements()); + R = APValue(Values.data(), Values.size()); + return true; + } + llvm_unreachable("invalid value to return"); }; diff --git a/clang/lib/AST/Interp/Program.cpp b/clang/lib/AST/Interp/Program.cpp index 25e938e01503..82367164743f 100644 --- a/clang/lib/AST/Interp/Program.cpp +++ b/clang/lib/AST/Interp/Program.cpp @@ -411,5 +411,12 @@ Descriptor *Program::createDescriptor(const DeclTy &D, const Type *Ty, IsMutable); } + // Same with vector types. + if (const auto *VT = Ty->getAs()) { + PrimType ElemTy = *Ctx.classify(VT->getElementType()); + return allocateDescriptor(D, ElemTy, MDSize, VT->getNumElements(), IsConst, + IsTemporary, IsMutable); + } + return nullptr; } diff --git a/clang/test/AST/Interp/vectors.cpp b/clang/test/AST/Interp/vectors.cpp new file mode 100644 index 000000000000..8afef3c897bf --- /dev/null +++ b/clang/test/AST/Interp/vectors.cpp @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify=expected,both %s +// RUN: %clang_cc1 -verify=ref,both %s + +// both-no-diagnostics + +typedef int __attribute__((vector_size(16))) VI4; +constexpr VI4 A = {1,2,3,4}; + +/// From constant-expression-cxx11.cpp +namespace Vector { + typedef int __attribute__((vector_size(16))) VI4; + constexpr VI4 f(int n) { + return VI4 { n * 3, n + 4, n - 5, n / 6 }; + } + constexpr auto v1 = f(10); + + typedef double __attribute__((vector_size(32))) VD4; + constexpr VD4 g(int n) { + return (VD4) { n / 2.0, n + 1.5, n - 5.4, n * 0.9 }; + } + constexpr auto v2 = g(4); +} -- GitLab From 0d17e1f0e5d706ac288ac8a62db92b8df64faf4e Mon Sep 17 00:00:00 2001 From: hev Date: Wed, 10 Apr 2024 17:13:25 +0800 Subject: [PATCH 378/695] [LoongArch] Revert `sp` adjustment in prologue (#88110) After commit 18c5f3c3 ("[RegisterScavenger][RISCV] Don't search for FrameSetup instrs if we were searching from Non-FrameSetup instrs"), we can revert the `sp` adjustment 4e2364a2 ("[LoongArch] Add emergency spill slot for GPR for large frames") to generate better code, as the issue with `RegScavenger` has been resolved. Fixes #88109 --- .../LoongArch/LoongArchFrameLowering.cpp | 57 ++++++------------- .../Target/LoongArch/LoongArchFrameLowering.h | 3 +- .../CodeGen/LoongArch/emergency-spill-slot.ll | 6 +- 3 files changed, 22 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp index dc2d61a6e474..2993726d2b64 100644 --- a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp @@ -206,22 +206,19 @@ void LoongArchFrameLowering::emitPrologue(MachineFunction &MF, if (StackSize == 0 && !MFI.adjustsStack()) return; - uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF, true); - uint64_t SecondSPAdjustAmount = RealStackSize - FirstSPAdjustAmount; + uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); // Split the SP adjustment to reduce the offsets of callee saved spill. if (FirstSPAdjustAmount) StackSize = FirstSPAdjustAmount; // Adjust stack. adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); - if (FirstSPAdjustAmount != 2048 || SecondSPAdjustAmount == 0) { - // Emit ".cfi_def_cfa_offset StackSize". - unsigned CFIIndex = - MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); - BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) - .addCFIIndex(CFIIndex) - .setMIFlag(MachineInstr::FrameSetup); - } + // Emit ".cfi_def_cfa_offset StackSize". + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); + BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex) + .setMIFlag(MachineInstr::FrameSetup); const auto &CSI = MFI.getCalleeSavedInfo(); @@ -258,25 +255,14 @@ void LoongArchFrameLowering::emitPrologue(MachineFunction &MF, } // Emit the second SP adjustment after saving callee saved registers. - if (FirstSPAdjustAmount && SecondSPAdjustAmount) { - if (hasFP(MF)) { - assert(SecondSPAdjustAmount > 0 && - "SecondSPAdjustAmount should be greater than zero"); - adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, - MachineInstr::FrameSetup); - } else { - // FIXME: RegScavenger will place the spill instruction before the - // prologue if a VReg is created in the prologue. This will pollute the - // caller's stack data. Therefore, until there is better way, we just use - // the `addi.w/d` instruction for stack adjustment to ensure that VReg - // will not be created. - for (int Val = SecondSPAdjustAmount; Val > 0; Val -= 2048) - BuildMI(MBB, MBBI, DL, - TII->get(IsLA64 ? LoongArch::ADDI_D : LoongArch::ADDI_W), SPReg) - .addReg(SPReg) - .addImm(Val < 2048 ? -Val : -2048) - .setMIFlag(MachineInstr::FrameSetup); + if (FirstSPAdjustAmount) { + uint64_t SecondSPAdjustAmount = RealStackSize - FirstSPAdjustAmount; + assert(SecondSPAdjustAmount > 0 && + "SecondSPAdjustAmount should be greater than zero"); + adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, + MachineInstr::FrameSetup); + if (!hasFP(MF)) { // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0", // don't emit an sp-based .cfi_def_cfa_offset // Emit ".cfi_def_cfa_offset RealStackSize" @@ -369,27 +355,20 @@ void LoongArchFrameLowering::emitEpilogue(MachineFunction &MF, // st.d $ra, $sp, 2024 // st.d $fp, $sp, 2016 // addi.d $sp, $sp, -16 -uint64_t -LoongArchFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF, - bool IsPrologue) const { +uint64_t LoongArchFrameLowering::getFirstSPAdjustAmount( + const MachineFunction &MF) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); const std::vector &CSI = MFI.getCalleeSavedInfo(); // Return the FirstSPAdjustAmount if the StackSize can not fit in a signed // 12-bit and there exists a callee-saved register needing to be pushed. - if (!isInt<12>(MFI.getStackSize())) { + if (!isInt<12>(MFI.getStackSize()) && (CSI.size() > 0)) { // FirstSPAdjustAmount is chosen as (2048 - StackAlign) because 2048 will // cause sp = sp + 2048 in the epilogue to be split into multiple // instructions. Offsets smaller than 2048 can fit in a single load/store // instruction, and we have to stick with the stack alignment. // So (2048 - StackAlign) will satisfy the stack alignment. - // - // FIXME: This place may seem odd. When using multiple ADDI instructions to - // adjust the stack in Prologue, and there are no callee-saved registers, we - // can take advantage of the logic of split sp ajustment to reduce code - // changes. - return CSI.size() > 0 ? 2048 - getStackAlign().value() - : (IsPrologue ? 2048 : 0); + return 2048 - getStackAlign().value(); } return 0; } diff --git a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.h b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.h index 57d2565c32c0..bc2ac02c91f8 100644 --- a/llvm/lib/Target/LoongArch/LoongArchFrameLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchFrameLowering.h @@ -52,8 +52,7 @@ public: bool hasFP(const MachineFunction &MF) const override; bool hasBP(const MachineFunction &MF) const; - uint64_t getFirstSPAdjustAmount(const MachineFunction &MF, - bool IsPrologue = false) const; + uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const; bool enableShrinkWrapping(const MachineFunction &MF) const override; diff --git a/llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll b/llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll index 08426b07bf74..4565c63f08d9 100644 --- a/llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll +++ b/llvm/test/CodeGen/LoongArch/emergency-spill-slot.ll @@ -6,9 +6,9 @@ define void @func() { ; CHECK-LABEL: func: ; CHECK: # %bb.0: -; CHECK-NEXT: addi.d $sp, $sp, -2048 -; CHECK-NEXT: addi.d $sp, $sp, -2048 -; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: lu12i.w $a0, 1 +; CHECK-NEXT: ori $a0, $a0, 16 +; CHECK-NEXT: sub.d $sp, $sp, $a0 ; CHECK-NEXT: .cfi_def_cfa_offset 4112 ; CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(var) ; CHECK-NEXT: ld.d $a1, $a0, %got_pc_lo12(var) -- GitLab From cac4c14ecfcb892201ae8f4b1559909cc22082d0 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 10 Apr 2024 10:28:42 +0100 Subject: [PATCH 379/695] [LAA] Replace std::tuple with struct (NFCI). As suggested in https://github.com/llvm/llvm-project/pull/88039, replace the tuple with a struct, to make it easier to extend. --- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 27 +++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index c25eede96a18..3bfc9700a145 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -1917,14 +1917,30 @@ isLoopVariantIndirectAddress(ArrayRef UnderlyingObjects, }); } -// Get the dependence distance, stride, type size in whether i is a write for +namespace { +struct DepDistanceStrideAndSizeInfo { + const SCEV *Dist; + uint64_t Stride; + uint64_t TypeByteSize; + bool AIsWrite; + bool BIsWrite; + + DepDistanceStrideAndSizeInfo(const SCEV *Dist, uint64_t Stride, + uint64_t TypeByteSize, bool AIsWrite, + bool BIsWrite) + : Dist(Dist), Stride(Stride), TypeByteSize(TypeByteSize), + AIsWrite(AIsWrite), BIsWrite(BIsWrite) {} +}; +} // namespace + +// Get the dependence distance, stride, type size and whether it is a write for // the dependence between A and B. Returns a DepType, if we can prove there's // no dependence or the analysis fails. Outlined to lambda to limit he scope // of various temporary variables, like A/BPtr, StrideA/BPtr and others. // Returns either the dependence result, if it could already be determined, or a -// tuple with (Distance, Stride, TypeSize, AIsWrite, BIsWrite). +// struct containing (Distance, Stride, TypeSize, AIsWrite, BIsWrite). static std::variant> + DepDistanceStrideAndSizeInfo> getDependenceDistanceStrideAndSize( const AccessAnalysis::MemAccessInfo &A, Instruction *AInst, const AccessAnalysis::MemAccessInfo &B, Instruction *BInst, @@ -1993,7 +2009,8 @@ getDependenceDistanceStrideAndSize( if (!HasSameSize) TypeByteSize = 0; uint64_t Stride = std::abs(StrideAPtr); - return std::make_tuple(Dist, Stride, TypeByteSize, AIsWrite, BIsWrite); + return DepDistanceStrideAndSizeInfo(Dist, Stride, TypeByteSize, AIsWrite, + BIsWrite); } MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( @@ -2012,7 +2029,7 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( return std::get(Res); const auto &[Dist, Stride, TypeByteSize, AIsWrite, BIsWrite] = - std::get>(Res); + std::get(Res); bool HasSameSize = TypeByteSize > 0; ScalarEvolution &SE = *PSE.getSE(); -- GitLab From 0e7d14d2e8ccad8ee1ec60c5c9f434553ec5c6ec Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 10 Apr 2024 10:42:01 +0100 Subject: [PATCH 380/695] [X86] Regenerate mmx-intrinsics.ll test checks --- llvm/test/CodeGen/X86/mmx-intrinsics.ll | 2745 +++++++++++++++++++++-- 1 file changed, 2531 insertions(+), 214 deletions(-) diff --git a/llvm/test/CodeGen/X86/mmx-intrinsics.ll b/llvm/test/CodeGen/X86/mmx-intrinsics.ll index 54b1a3135918..a43d9400cde6 100644 --- a/llvm/test/CodeGen/X86/mmx-intrinsics.ll +++ b/llvm/test/CodeGen/X86/mmx-intrinsics.ll @@ -1,13 +1,42 @@ -; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-prefix=X86 -; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X86 -; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-prefix=X64 -; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X64 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefixes=ALL,X86 +; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+avx | FileCheck %s --check-prefixes=ALL,X86 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefixes=ALL,X64 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+avx | FileCheck %s --check-prefixes=ALL,X64 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test1(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test1 -; ALL: phaddw +; X86-LABEL: test1: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: phaddw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test1: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: phaddw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -23,8 +52,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test88(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test88 -; ALL: pcmpgtd +; X86-LABEL: test88: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pcmpgtd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test88: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pcmpgtd %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -40,8 +97,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pcmpgt.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test87(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test87 -; ALL: pcmpgtw +; X86-LABEL: test87: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pcmpgtw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test87: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pcmpgtw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -57,8 +142,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pcmpgt.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test86(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test86 -; ALL: pcmpgtb +; X86-LABEL: test86: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pcmpgtb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test86: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pcmpgtb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -74,8 +187,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pcmpeq.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test85(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test85 -; ALL: pcmpeqd +; X86-LABEL: test85: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pcmpeqd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test85: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pcmpeqd %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -91,8 +232,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pcmpeq.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test84(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test84 -; ALL: pcmpeqw +; X86-LABEL: test84: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pcmpeqw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test84: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pcmpeqw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -108,8 +277,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pcmpeq.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test83(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test83 -; ALL: pcmpeqb +; X86-LABEL: test83: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pcmpeqb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test83: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pcmpeqb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -125,9 +322,36 @@ entry: declare x86_mmx @llvm.x86.mmx.punpckldq(x86_mmx, x86_mmx) nounwind readnone define i64 @test82(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test82 -; X86: punpckldq {{.*#+}} mm0 = mm0[0],mem[0] -; X64: punpckldq {{.*#+}} mm0 = mm0[0],mm1[0] +; X86-LABEL: test82: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: punpckldq {{[0-9]+}}(%esp), %mm0 # mm0 = mm0[0],mem[0] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test82: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: punpckldq %mm1, %mm0 # mm0 = mm0[0],mm1[0] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -143,9 +367,36 @@ entry: declare x86_mmx @llvm.x86.mmx.punpcklwd(x86_mmx, x86_mmx) nounwind readnone define i64 @test81(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test81 -; X86: punpcklwd {{.*#+}} mm0 = mm0[0],mem[0],mm0[1],mem[1] -; X64: punpcklwd {{.*#+}} mm0 = mm0[0],mm1[0],mm0[1],mm1[1] +; X86-LABEL: test81: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: punpcklwd {{[0-9]+}}(%esp), %mm0 # mm0 = mm0[0],mem[0],mm0[1],mem[1] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test81: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: punpcklwd %mm1, %mm0 # mm0 = mm0[0],mm1[0],mm0[1],mm1[1] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -161,9 +412,36 @@ entry: declare x86_mmx @llvm.x86.mmx.punpcklbw(x86_mmx, x86_mmx) nounwind readnone define i64 @test80(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test80 -; X86: punpcklbw {{.*#+}} mm0 = mm0[0],mem[0],mm0[1],mem[1],mm0[2],mem[2],mm0[3],mem[3] -; X64: punpcklbw {{.*#+}} mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3] +; X86-LABEL: test80: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: punpcklbw {{[0-9]+}}(%esp), %mm0 # mm0 = mm0[0],mem[0],mm0[1],mem[1],mm0[2],mem[2],mm0[3],mem[3] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test80: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: punpcklbw %mm1, %mm0 # mm0 = mm0[0],mm1[0],mm0[1],mm1[1],mm0[2],mm1[2],mm0[3],mm1[3] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -179,9 +457,36 @@ entry: declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx) nounwind readnone define i64 @test79(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test79 -; X86: punpckhdq {{.*#+}} mm0 = mm0[1],mem[1] -; X64: punpckhdq {{.*#+}} mm0 = mm0[1],mm1[1] +; X86-LABEL: test79: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: punpckhdq {{[0-9]+}}(%esp), %mm0 # mm0 = mm0[1],mem[1] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test79: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: punpckhdq %mm1, %mm0 # mm0 = mm0[1],mm1[1] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -197,27 +502,81 @@ entry: declare x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx, x86_mmx) nounwind readnone define i64 @test78(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test78 -; X86: punpckhwd {{.*#+}} mm0 = mm0[2],mem[2],mm0[3],mem[3] -; X64: punpckhwd {{.*#+}} mm0 = mm0[2],mm1[2],mm0[3],mm1[3] -entry: - %0 = bitcast <1 x i64> %b to <4 x i16> - %1 = bitcast <1 x i64> %a to <4 x i16> - %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx - %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx - %2 = tail call x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind - %3 = bitcast x86_mmx %2 to <4 x i16> - %4 = bitcast <4 x i16> %3 to <1 x i64> - %5 = extractelement <1 x i64> %4, i32 0 - ret i64 %5 -} - -declare x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx, x86_mmx) nounwind readnone - +; X86-LABEL: test78: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: punpckhwd {{[0-9]+}}(%esp), %mm0 # mm0 = mm0[2],mem[2],mm0[3],mem[3] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test78: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: punpckhwd %mm1, %mm0 # mm0 = mm0[2],mm1[2],mm0[3],mm1[3] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq +entry: + %0 = bitcast <1 x i64> %b to <4 x i16> + %1 = bitcast <1 x i64> %a to <4 x i16> + %mmx_var.i = bitcast <4 x i16> %1 to x86_mmx + %mmx_var1.i = bitcast <4 x i16> %0 to x86_mmx + %2 = tail call x86_mmx @llvm.x86.mmx.punpckhwd(x86_mmx %mmx_var.i, x86_mmx %mmx_var1.i) nounwind + %3 = bitcast x86_mmx %2 to <4 x i16> + %4 = bitcast <4 x i16> %3 to <1 x i64> + %5 = extractelement <1 x i64> %4, i32 0 + ret i64 %5 +} + +declare x86_mmx @llvm.x86.mmx.punpckhbw(x86_mmx, x86_mmx) nounwind readnone + define i64 @test77(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test77 -; X86: punpckhbw {{.*#+}} mm0 = mm0[4],mem[4],mm0[5],mem[5],mm0[6],mem[6],mm0[7],mem[7] -; X64: punpckhbw {{.*#+}} mm0 = mm0[4],mm1[4],mm0[5],mm1[5],mm0[6],mm1[6],mm0[7],mm1[7] +; X86-LABEL: test77: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: punpckhbw {{[0-9]+}}(%esp), %mm0 # mm0 = mm0[4],mem[4],mm0[5],mem[5],mm0[6],mem[6],mm0[7],mem[7] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test77: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: punpckhbw %mm1, %mm0 # mm0 = mm0[4],mm1[4],mm0[5],mm1[5],mm0[6],mm1[6],mm0[7],mm1[7] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -233,8 +592,36 @@ entry: declare x86_mmx @llvm.x86.mmx.packuswb(x86_mmx, x86_mmx) nounwind readnone define i64 @test76(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test76 -; ALL: packuswb +; X86-LABEL: test76: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: packuswb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test76: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: packuswb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -250,8 +637,36 @@ entry: declare x86_mmx @llvm.x86.mmx.packssdw(x86_mmx, x86_mmx) nounwind readnone define i64 @test75(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test75 -; ALL: packssdw +; X86-LABEL: test75: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: packssdw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test75: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: packssdw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -267,8 +682,36 @@ entry: declare x86_mmx @llvm.x86.mmx.packsswb(x86_mmx, x86_mmx) nounwind readnone define i64 @test74(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test74 -; ALL: packsswb +; X86-LABEL: test74: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: packsswb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test74: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: packsswb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -284,8 +727,31 @@ entry: declare x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx, i32) nounwind readnone define i64 @test73(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test73 -; ALL: psrad +; X86-LABEL: test73: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psrad $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test73: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psrad $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -299,8 +765,31 @@ entry: declare x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx, i32) nounwind readnone define i64 @test72(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test72 -; ALL: psraw +; X86-LABEL: test72: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psraw $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test72: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psraw $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -312,8 +801,28 @@ entry: } define i64 @test72_2(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test72_2 -; ALL-NOT: psraw +; X86-LABEL: test72_2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test72_2: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -327,8 +836,27 @@ entry: declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone define i64 @test71(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test71 -; ALL: psrlq +; X86-LABEL: test71: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: psrlq $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test71: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psrlq $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var.i = bitcast i64 %0 to x86_mmx @@ -340,8 +868,31 @@ entry: declare x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx, i32) nounwind readnone define i64 @test70(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test70 -; ALL: psrld +; X86-LABEL: test70: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psrld $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test70: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psrld $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -353,8 +904,28 @@ entry: } define i64 @test70_2(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test70_2 -; ALL-NOT: psrld +; X86-LABEL: test70_2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test70_2: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -368,8 +939,31 @@ entry: declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone define i64 @test69(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test69 -; ALL: psrlw +; X86-LABEL: test69: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psrlw $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test69: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psrlw $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -383,8 +977,27 @@ entry: declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone define i64 @test68(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test68 -; ALL: psllq +; X86-LABEL: test68: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: psllq $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test68: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psllq $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var.i = bitcast i64 %0 to x86_mmx @@ -396,8 +1009,31 @@ entry: declare x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx, i32) nounwind readnone define i64 @test67(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test67 -; ALL: pslld +; X86-LABEL: test67: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pslld $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test67: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pslld $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -411,8 +1047,31 @@ entry: declare x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx, i32) nounwind readnone define i64 @test66(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test66 -; ALL: psllw +; X86-LABEL: test66: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psllw $3, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test66: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: psllw $3, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -424,8 +1083,28 @@ entry: } define i64 @test66_2(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test66_2 -; ALL-NOT: psllw +; X86-LABEL: test66_2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test66_2: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -439,8 +1118,32 @@ entry: declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test65(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test65 -; ALL: psrad +; X86-LABEL: test65: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psrad 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test65: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psrad %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -456,8 +1159,32 @@ entry: declare x86_mmx @llvm.x86.mmx.psra.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test64(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test64 -; ALL: psraw +; X86-LABEL: test64: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psraw 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test64: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psraw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -473,8 +1200,28 @@ entry: declare x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx, x86_mmx) nounwind readnone define i64 @test63(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test63 -; ALL: psrlq +; X86-LABEL: test63: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: psrlq 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test63: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psrlq %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var.i = bitcast i64 %0 to x86_mmx @@ -488,8 +1235,32 @@ entry: declare x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test62(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test62 -; ALL: psrld +; X86-LABEL: test62: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psrld 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test62: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psrld %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -505,8 +1276,32 @@ entry: declare x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test61(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test61 -; ALL: psrlw +; X86-LABEL: test61: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psrlw 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test61: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psrlw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -522,8 +1317,28 @@ entry: declare x86_mmx @llvm.x86.mmx.psll.q(x86_mmx, x86_mmx) nounwind readnone define i64 @test60(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test60 -; ALL: psllq +; X86-LABEL: test60: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: psllq 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test60: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psllq %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var.i = bitcast i64 %0 to x86_mmx @@ -537,8 +1352,32 @@ entry: declare x86_mmx @llvm.x86.mmx.psll.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test59(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test59 -; ALL: pslld +; X86-LABEL: test59: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pslld 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test59: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pslld %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %mmx_var.i = bitcast <2 x i32> %0 to x86_mmx @@ -554,8 +1393,32 @@ entry: declare x86_mmx @llvm.x86.mmx.psll.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test58(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test58 -; ALL: psllw +; X86-LABEL: test58: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psllw 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test58: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psllw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %mmx_var.i = bitcast <4 x i16> %0 to x86_mmx @@ -571,8 +1434,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pxor(x86_mmx, x86_mmx) nounwind readnone define i64 @test56(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test56 -; ALL: pxor +; X86-LABEL: test56: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pxor {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test56: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pxor %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -588,8 +1479,36 @@ entry: declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx) nounwind readnone define i64 @test55(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test55 -; ALL: por +; X86-LABEL: test55: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: por {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test55: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: por %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -605,8 +1524,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pandn(x86_mmx, x86_mmx) nounwind readnone define i64 @test54(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test54 -; ALL: pandn +; X86-LABEL: test54: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pandn {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test54: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pandn %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -622,8 +1569,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pand(x86_mmx, x86_mmx) nounwind readnone define i64 @test53(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test53 -; ALL: pand +; X86-LABEL: test53: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pand {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test53: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pand %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -639,8 +1614,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmull.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test52(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test52 -; ALL: pmullw +; X86-LABEL: test52: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmullw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test52: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmullw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -654,8 +1657,36 @@ entry: } define i64 @test51(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test51 -; ALL: pmullw +; X86-LABEL: test51: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmullw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test51: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmullw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -671,8 +1702,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmulh.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test50(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test50 -; ALL: pmulhw +; X86-LABEL: test50: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmulhw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test50: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmulhw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -688,8 +1747,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmadd.wd(x86_mmx, x86_mmx) nounwind readnone define i64 @test49(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test49 -; ALL: pmaddwd +; X86-LABEL: test49: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmaddwd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test49: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmaddwd %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -705,8 +1792,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psubus.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test48(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test48 -; ALL: psubusw +; X86-LABEL: test48: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubusw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test48: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubusw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -722,8 +1837,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psubus.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test47(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test47 -; ALL: psubusb +; X86-LABEL: test47: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubusb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test47: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubusb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -739,8 +1882,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psubs.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test46(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test46 -; ALL: psubsw +; X86-LABEL: test46: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test46: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubsw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -756,8 +1927,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psubs.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test45(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test45 -; ALL: psubsb +; X86-LABEL: test45: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubsb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test45: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubsb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -771,8 +1970,28 @@ entry: } define i64 @test44(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test44 -; ALL: psubq +; X86-LABEL: test44: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: psubq 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test44: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubq %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var = bitcast i64 %0 to x86_mmx @@ -788,8 +2007,36 @@ declare x86_mmx @llvm.x86.mmx.psub.q(x86_mmx, x86_mmx) nounwind readnone declare x86_mmx @llvm.x86.mmx.psub.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test43(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test43 -; ALL: psubd +; X86-LABEL: test43: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test43: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubd %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -805,8 +2052,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psub.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test42(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test42 -; ALL: psubw +; X86-LABEL: test42: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test42: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -822,8 +2097,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psub.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test41(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test41 -; ALL: psubb +; X86-LABEL: test41: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psubb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test41: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psubb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -839,8 +2142,36 @@ entry: declare x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test40(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test40 -; ALL: paddusw +; X86-LABEL: test40: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddusw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test40: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddusw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -856,8 +2187,36 @@ entry: declare x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test39(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test39 -; ALL: paddusb +; X86-LABEL: test39: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddusb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test39: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddusb %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -873,8 +2232,36 @@ entry: declare x86_mmx @llvm.x86.mmx.padds.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test38(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test38 -; ALL: paddsw +; X86-LABEL: test38: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test38: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddsw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -890,8 +2277,36 @@ entry: declare x86_mmx @llvm.x86.mmx.padds.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test37(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test37 -; ALL: paddsb +; X86-LABEL: test37: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddsb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test37: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddsb %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -907,8 +2322,28 @@ entry: declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx) nounwind readnone define i64 @test36(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test36 -; ALL: paddq +; X86-LABEL: test36: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: paddq 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test36: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddq %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var = bitcast i64 %0 to x86_mmx @@ -922,8 +2357,36 @@ entry: declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test35(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test35 -; ALL: paddd +; X86-LABEL: test35: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test35: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddd %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -939,8 +2402,36 @@ entry: declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test34(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test34 -; ALL: paddw +; X86-LABEL: test34: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test34: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -956,8 +2447,36 @@ entry: declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test33(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test33 -; ALL: paddb +; X86-LABEL: test33: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: paddb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test33: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: paddb %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -973,8 +2492,36 @@ entry: declare x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx, x86_mmx) nounwind readnone define i64 @test32(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test32 -; ALL: psadbw +; X86-LABEL: test32: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psadbw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test32: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psadbw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -988,8 +2535,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmins.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test31(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test31 -; ALL: pminsw +; X86-LABEL: test31: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pminsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test31: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pminsw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1005,8 +2580,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pminu.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test30(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test30 -; ALL: pminub +; X86-LABEL: test30: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pminub {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test30: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pminub %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -1022,8 +2625,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmaxs.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test29(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test29 -; ALL: pmaxsw +; X86-LABEL: test29: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmaxsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test29: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmaxsw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1039,8 +2670,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmaxu.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test28(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test28 -; ALL: pmaxub +; X86-LABEL: test28: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmaxub {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test28: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmaxub %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -1056,8 +2715,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pavg.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test27(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test27 -; ALL: pavgw +; X86-LABEL: test27: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pavgw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test27: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pavgw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1073,8 +2760,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pavg.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test26(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test26 -; ALL: pavgb +; X86-LABEL: test26: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pavgb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test26: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pavgb %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -1090,8 +2805,18 @@ entry: declare void @llvm.x86.mmx.movnt.dq(ptr, x86_mmx) nounwind define void @test25(ptr %p, <1 x i64> %a) nounwind optsize ssp { -; ALL-LABEL: @test25 -; ALL: movntq +; X86-LABEL: test25: +; X86: # %bb.0: # %entry +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movntq %mm0, (%eax) +; X86-NEXT: retl +; +; X64-LABEL: test25: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rsi, %mm0 +; X64-NEXT: movntq %mm0, (%rdi) +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var.i = bitcast i64 %0 to x86_mmx @@ -1102,8 +2827,27 @@ entry: declare i32 @llvm.x86.mmx.pmovmskb(x86_mmx) nounwind readnone define i32 @test24(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test24 -; ALL: pmovmskb +; X86-LABEL: test24: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: movq (%esp), %mm0 +; X86-NEXT: pmovmskb %mm0, %eax +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test24: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pmovmskb %mm0, %eax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <8 x i8> %mmx_var.i = bitcast <8 x i8> %0 to x86_mmx @@ -1114,8 +2858,37 @@ entry: declare void @llvm.x86.mmx.maskmovq(x86_mmx, x86_mmx, ptr) nounwind define void @test23(<1 x i64> %d, <1 x i64> %n, ptr %p) nounwind optsize ssp { -; ALL-LABEL: @test23 -; ALL: maskmovq +; X86-LABEL: test23: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: pushl %edi +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: movl 24(%ebp), %edi +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq (%esp), %mm1 +; X86-NEXT: maskmovq %mm0, %mm1 +; X86-NEXT: leal -4(%ebp), %esp +; X86-NEXT: popl %edi +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test23: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: movq %rdx, %rdi +; X64-NEXT: maskmovq %mm1, %mm0 +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %n to <8 x i8> %1 = bitcast <1 x i64> %d to <8 x i8> @@ -1128,8 +2901,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmulhu.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test22(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test22 -; ALL: pmulhuw +; X86-LABEL: test22: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmulhuw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test22: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmulhuw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1145,9 +2946,30 @@ entry: declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8) nounwind readnone define i64 @test21(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test21 -; X86: pshufw {{.*#+}} mm0 = mem[3,0,0,0] -; X64: pshufw {{.*#+}} mm0 = mm0[3,0,0,0] +; X86-LABEL: test21: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: pshufw $3, {{[0-9]+}}(%esp), %mm0 # mm0 = mem[3,0,0,0] +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test21: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pshufw $3, %mm0, %mm0 # mm0 = mm0[3,0,0,0] +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %1 = bitcast <4 x i16> %0 to x86_mmx @@ -1159,10 +2981,28 @@ entry: } define i32 @test21_2(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test21_2 -; X86: pshufw {{.*#+}} mm0 = mem[3,0,0,0] -; X64: pshufw {{.*#+}} mm0 = mm0[3,0,0,0] -; ALL: movd +; X86-LABEL: test21_2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: pshufw $3, (%esp), %mm0 # mm0 = mem[3,0,0,0] +; X86-NEXT: movd %mm0, %eax +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test21_2: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pshufw $3, %mm0, %mm0 # mm0 = mm0[3,0,0,0] +; X64-NEXT: movd %mm0, %eax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %1 = bitcast <4 x i16> %0 to x86_mmx @@ -1176,8 +3016,36 @@ entry: declare x86_mmx @llvm.x86.mmx.pmulu.dq(x86_mmx, x86_mmx) nounwind readnone define i64 @test20(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test20 -; ALL: pmuludq +; X86-LABEL: test20: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmuludq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test20: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmuludq %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -1191,8 +3059,26 @@ entry: declare <2 x double> @llvm.x86.sse.cvtpi2pd(x86_mmx) nounwind readnone define <2 x double> @test19(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test19 -; ALL: cvtpi2pd +; X86-LABEL: test19: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, (%esp) +; X86-NEXT: cvtpi2pd (%esp), %xmm0 +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test19: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: cvtpi2pd %mm0, %xmm0 +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %1 = bitcast <2 x i32> %0 to x86_mmx @@ -1203,8 +3089,25 @@ entry: declare x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double>) nounwind readnone define i64 @test18(<2 x double> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test18 -; ALL: cvttpd2pi +; X86-LABEL: test18: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: cvttpd2pi %xmm0, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test18: +; X64: # %bb.0: # %entry +; X64-NEXT: cvttpd2pi %xmm0, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = tail call x86_mmx @llvm.x86.sse.cvttpd2pi(<2 x double> %a) nounwind readnone %1 = bitcast x86_mmx %0 to <2 x i32> @@ -1216,8 +3119,25 @@ entry: declare x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double>) nounwind readnone define i64 @test17(<2 x double> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test17 -; ALL: cvtpd2pi +; X86-LABEL: test17: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: cvtpd2pi %xmm0, %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test17: +; X64: # %bb.0: # %entry +; X64-NEXT: cvtpd2pi %xmm0, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = tail call x86_mmx @llvm.x86.sse.cvtpd2pi(<2 x double> %a) nounwind readnone %1 = bitcast x86_mmx %0 to <2 x i32> @@ -1229,8 +3149,28 @@ entry: declare x86_mmx @llvm.x86.mmx.palignr.b(x86_mmx, x86_mmx, i8) nounwind readnone define i64 @test16(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test16 -; ALL: palignr +; X86-LABEL: test16: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $8, %esp +; X86-NEXT: movq 8(%ebp), %mm0 +; X86-NEXT: palignr $16, 16(%ebp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test16: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: palignr $16, %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = extractelement <1 x i64> %a, i32 0 %mmx_var = bitcast i64 %0 to x86_mmx @@ -1244,8 +3184,30 @@ entry: declare x86_mmx @llvm.x86.ssse3.pabs.d(x86_mmx) nounwind readnone define i64 @test15(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test15 -; ALL: pabsd +; X86-LABEL: test15: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: pabsd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test15: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pabsd %mm0, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <2 x i32> %1 = bitcast <2 x i32> %0 to x86_mmx @@ -1259,8 +3221,30 @@ entry: declare x86_mmx @llvm.x86.ssse3.pabs.w(x86_mmx) nounwind readnone define i64 @test14(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test14 -; ALL: pabsw +; X86-LABEL: test14: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: pabsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test14: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pabsw %mm0, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <4 x i16> %1 = bitcast <4 x i16> %0 to x86_mmx @@ -1274,8 +3258,30 @@ entry: declare x86_mmx @llvm.x86.ssse3.pabs.b(x86_mmx) nounwind readnone define i64 @test13(<1 x i64> %a) nounwind readnone optsize ssp { -; ALL-LABEL: @test13 -; ALL: pabsb +; X86-LABEL: test13: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $16, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: pabsb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test13: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: pabsb %mm0, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %a to <8 x i8> %1 = bitcast <8 x i8> %0 to x86_mmx @@ -1289,8 +3295,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.psign.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test12(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test12 -; ALL: psignd +; X86-LABEL: test12: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psignd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test12: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psignd %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -1306,8 +3340,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.psign.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test11(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test11 -; ALL: psignw +; X86-LABEL: test11: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psignw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test11: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psignw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1323,8 +3385,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.psign.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test10(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test10 -; ALL: psignb +; X86-LABEL: test10: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: psignb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test10: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: psignb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -1340,8 +3430,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.pshuf.b(x86_mmx, x86_mmx) nounwind readnone define i64 @test9(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test9 -; ALL: pshufb +; X86-LABEL: test9: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pshufb {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test9: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pshufb %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -1357,8 +3475,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.pmul.hr.sw(x86_mmx, x86_mmx) nounwind readnone define i64 @test8(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test8 -; ALL: pmulhrsw +; X86-LABEL: test8: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmulhrsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test8: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmulhrsw %mm0, %mm1 +; X64-NEXT: movq %mm1, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1374,8 +3520,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx, x86_mmx) nounwind readnone define i64 @test7(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test7 -; ALL: pmaddubsw +; X86-LABEL: test7: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: pmaddubsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test7: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: pmaddubsw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <8 x i8> %1 = bitcast <1 x i64> %a to <8 x i8> @@ -1391,8 +3565,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.phsub.sw(x86_mmx, x86_mmx) nounwind readnone define i64 @test6(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test6 -; ALL: phsubsw +; X86-LABEL: test6: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: phsubsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test6: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: phsubsw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1408,8 +3610,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.phsub.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test5(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test5 -; ALL: phsubd +; X86-LABEL: test5: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: phsubd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test5: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: phsubd %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -1425,8 +3655,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.phsub.w(x86_mmx, x86_mmx) nounwind readnone define i64 @test4(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test4 -; ALL: phsubw +; X86-LABEL: test4: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: phsubw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test4: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: phsubw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1442,8 +3700,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.phadd.sw(x86_mmx, x86_mmx) nounwind readnone define i64 @test3(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test3 -; ALL: phaddsw +; X86-LABEL: test3: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: phaddsw {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test3: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: phaddsw %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <4 x i16> %1 = bitcast <1 x i64> %a to <4 x i16> @@ -1459,8 +3745,36 @@ entry: declare x86_mmx @llvm.x86.ssse3.phadd.d(x86_mmx, x86_mmx) nounwind readnone define i64 @test2(<1 x i64> %a, <1 x i64> %b) nounwind readnone optsize ssp { -; ALL-LABEL: @test2 -; ALL: phaddd +; X86-LABEL: test2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-8, %esp +; X86-NEXT: subl $24, %esp +; X86-NEXT: movl 8(%ebp), %eax +; X86-NEXT: movl 12(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl 16(%ebp), %eax +; X86-NEXT: movl 20(%ebp), %ecx +; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movq {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: phaddd {{[0-9]+}}(%esp), %mm0 +; X86-NEXT: movq %mm0, (%esp) +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp +; X86-NEXT: retl +; +; X64-LABEL: test2: +; X64: # %bb.0: # %entry +; X64-NEXT: movq %rdi, %mm0 +; X64-NEXT: movq %rsi, %mm1 +; X64-NEXT: phaddd %mm1, %mm0 +; X64-NEXT: movq %mm0, %rax +; X64-NEXT: retq entry: %0 = bitcast <1 x i64> %b to <2 x i32> %1 = bitcast <1 x i64> %a to <2 x i32> @@ -1474,18 +3788,21 @@ entry: } define <4 x float> @test89(<4 x float> %a, x86_mmx %b) nounwind { -; ALL-LABEL: @test89 -; ALL: cvtpi2ps +; ALL-LABEL: test89: +; ALL: # %bb.0: +; ALL-NEXT: cvtpi2ps %mm0, %xmm0 +; ALL-NEXT: ret{{[l|q]}} %c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, x86_mmx %b) ret <4 x float> %c } declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx) nounwind readnone -; ALL-LABEL: test90 define void @test90() { -; ALL-LABEL: @test90 -; ALL: emms +; ALL-LABEL: test90: +; ALL: # %bb.0: +; ALL-NEXT: emms +; ALL-NEXT: ret{{[l|q]}} call void @llvm.x86.mmx.emms() ret void } -- GitLab From 990c4bc95f69afb63849898b6b25b13d49d6cdd4 Mon Sep 17 00:00:00 2001 From: Dinar Temirbulatov Date: Wed, 10 Apr 2024 11:07:59 +0100 Subject: [PATCH 381/695] [AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for bit-twiddling. (#83514) Allow to fold or/and-and to BSL instuction for scalable vectors. --- .../Target/AArch64/AArch64ISelLowering.cpp | 21 ++++++++------ llvm/test/CodeGen/AArch64/sve2-bsl.ll | 28 +++++++++++++++++++ 2 files changed, 41 insertions(+), 8 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/sve2-bsl.ll diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 819e8ccd5c33..744b2cdef504 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -17930,16 +17930,14 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, EVT VT = N->getValueType(0); SelectionDAG &DAG = DCI.DAG; SDLoc DL(N); + const auto &Subtarget = DAG.getSubtarget(); if (!VT.isVector()) return SDValue(); - // The combining code currently only works for NEON vectors. In particular, - // it does not work for SVE when dealing with vectors wider than 128 bits. - // It also doesn't work for streaming mode because it causes generating - // bsl instructions that are invalid in streaming mode. - if (TLI.useSVEForFixedLengthVectorVT( - VT, !DAG.getSubtarget().isNeonAvailable())) + // The combining code works for NEON, SVE2 and SME. + if (TLI.useSVEForFixedLengthVectorVT(VT, !Subtarget.isNeonAvailable()) || + (VT.isScalableVector() && !Subtarget.hasSVE2())) return SDValue(); SDValue N0 = N->getOperand(0); @@ -17994,6 +17992,14 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1); for (int i = 1; i >= 0; --i) for (int j = 1; j >= 0; --j) { + APInt Val1, Val2; + + if (ISD::isConstantSplatVector(N0->getOperand(i).getNode(), Val1) && + ISD::isConstantSplatVector(N1->getOperand(j).getNode(), Val2) && + (BitMask & ~Val1.getZExtValue()) == Val2.getZExtValue()) { + return DAG.getNode(AArch64ISD::BSP, DL, VT, N0->getOperand(i), + N0->getOperand(1 - i), N1->getOperand(1 - j)); + } BuildVectorSDNode *BVN0 = dyn_cast(N0->getOperand(i)); BuildVectorSDNode *BVN1 = dyn_cast(N1->getOperand(j)); if (!BVN0 || !BVN1) @@ -18009,9 +18015,8 @@ static SDValue tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, break; } } - if (FoundMatch) - return DAG.getNode(AArch64ISD::BSP, DL, VT, SDValue(BVN0, 0), + return DAG.getNode(AArch64ISD::BSP, DL, VT, N0->getOperand(i), N0->getOperand(1 - i), N1->getOperand(1 - j)); } diff --git a/llvm/test/CodeGen/AArch64/sve2-bsl.ll b/llvm/test/CodeGen/AArch64/sve2-bsl.ll new file mode 100644 index 000000000000..11f67634a3fb --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve2-bsl.ll @@ -0,0 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sve2 < %s | FileCheck %s --check-prefixes=CHECK + +define @bsl( %a, %b) { +; CHECK-LABEL: bsl: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.s, #0x7fffffff +; CHECK-NEXT: bsl z0.d, z0.d, z1.d, z2.d +; CHECK-NEXT: ret + %1 = and %a, splat(i32 2147483647) + %2 = and %b, splat(i32 -2147483648) + %c = or %1, %2 + ret %c +} + +; we are not expecting bsl instruction here. the constants do not match to fold to bsl. +define @no_bsl_fold( %a, %b) { +; CHECK-LABEL: no_bsl_fold: +; CHECK: // %bb.0: +; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff +; CHECK-NEXT: and z1.s, z1.s, #0x7ffffffe +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %1 = and %a, splat(i32 2147483647) + %2 = and %b, splat(i32 2147483646) + %c = or %1, %2 + ret %c +} -- GitLab From ec40097db28374c1226f0f7e45f18491a596778b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Wed, 10 Apr 2024 12:02:47 +0200 Subject: [PATCH 382/695] [clang][Interp] Implement __builtin_{ctz,clz}g --- clang/lib/AST/Interp/InterpBuiltin.cpp | 46 +++++++- clang/test/AST/Interp/builtin-functions.cpp | 120 ++++++++++++++++++++ 2 files changed, 160 insertions(+), 6 deletions(-) diff --git a/clang/lib/AST/Interp/InterpBuiltin.cpp b/clang/lib/AST/Interp/InterpBuiltin.cpp index 1bf5d55314f1..984ba4f7f268 100644 --- a/clang/lib/AST/Interp/InterpBuiltin.cpp +++ b/clang/lib/AST/Interp/InterpBuiltin.cpp @@ -16,6 +16,16 @@ namespace clang { namespace interp { +static unsigned callArgSize(const InterpState &S, const CallExpr *C) { + unsigned O = 0; + + for (const Expr *E : C->arguments()) { + O += align(primSize(*S.getContext().classify(E))); + } + + return O; +} + template static T getParam(const InterpFrame *Frame, unsigned Index) { assert(Frame->getFunction()->getNumParams() > Index); @@ -816,9 +826,10 @@ static bool interp__builtin_carryop(InterpState &S, CodePtr OpPC, static bool interp__builtin_clz(InterpState &S, CodePtr OpPC, const InterpFrame *Frame, const Function *Func, const CallExpr *Call) { + unsigned CallSize = callArgSize(S, Call); unsigned BuiltinOp = Func->getBuiltinID(); PrimType ValT = *S.getContext().classify(Call->getArg(0)); - const APSInt &Val = peekToAPSInt(S.Stk, ValT); + const APSInt &Val = peekToAPSInt(S.Stk, ValT, CallSize); // When the argument is 0, the result of GCC builtins is undefined, whereas // for Microsoft intrinsics, the result is the bit-width of the argument. @@ -826,8 +837,19 @@ static bool interp__builtin_clz(InterpState &S, CodePtr OpPC, BuiltinOp != Builtin::BI__lzcnt && BuiltinOp != Builtin::BI__lzcnt64; - if (ZeroIsUndefined && Val == 0) - return false; + if (Val == 0) { + if (Func->getBuiltinID() == Builtin::BI__builtin_clzg && + Call->getNumArgs() == 2) { + // We have a fallback parameter. + PrimType FallbackT = *S.getContext().classify(Call->getArg(1)); + const APSInt &Fallback = peekToAPSInt(S.Stk, FallbackT); + pushInteger(S, Fallback, Call->getType()); + return true; + } + + if (ZeroIsUndefined) + return false; + } pushInteger(S, Val.countl_zero(), Call->getType()); return true; @@ -836,11 +858,21 @@ static bool interp__builtin_clz(InterpState &S, CodePtr OpPC, static bool interp__builtin_ctz(InterpState &S, CodePtr OpPC, const InterpFrame *Frame, const Function *Func, const CallExpr *Call) { + unsigned CallSize = callArgSize(S, Call); PrimType ValT = *S.getContext().classify(Call->getArg(0)); - const APSInt &Val = peekToAPSInt(S.Stk, ValT); - - if (Val == 0) + const APSInt &Val = peekToAPSInt(S.Stk, ValT, CallSize); + + if (Val == 0) { + if (Func->getBuiltinID() == Builtin::BI__builtin_ctzg && + Call->getNumArgs() == 2) { + // We have a fallback parameter. + PrimType FallbackT = *S.getContext().classify(Call->getArg(1)); + const APSInt &Fallback = peekToAPSInt(S.Stk, FallbackT); + pushInteger(S, Fallback, Call->getType()); + return true; + } return false; + } pushInteger(S, Val.countr_zero(), Call->getType()); return true; @@ -1223,6 +1255,7 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F, case Builtin::BI__builtin_clzl: case Builtin::BI__builtin_clzll: case Builtin::BI__builtin_clzs: + case Builtin::BI__builtin_clzg: case Builtin::BI__lzcnt16: // Microsoft variants of count leading-zeroes case Builtin::BI__lzcnt: case Builtin::BI__lzcnt64: @@ -1234,6 +1267,7 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F, case Builtin::BI__builtin_ctzl: case Builtin::BI__builtin_ctzll: case Builtin::BI__builtin_ctzs: + case Builtin::BI__builtin_ctzg: if (!interp__builtin_ctz(S, OpPC, Frame, F, Call)) return false; break; diff --git a/clang/test/AST/Interp/builtin-functions.cpp b/clang/test/AST/Interp/builtin-functions.cpp index 2e9d1a831dcf..a7adc92d3714 100644 --- a/clang/test/AST/Interp/builtin-functions.cpp +++ b/clang/test/AST/Interp/builtin-functions.cpp @@ -482,6 +482,9 @@ void test_noexcept(int *i) { #undef TEST_TYPE } // end namespace test_launder + +/// FIXME: The commented out tests here use a IntAP value and fail. +/// This currently means we will leak the IntAP value since nothing cleans it up. namespace clz { char clz1[__builtin_clz(1) == BITSIZE(int) - 1 ? 1 : -1]; char clz2[__builtin_clz(7) == BITSIZE(int) - 3 ? 1 : -1]; @@ -492,6 +495,63 @@ namespace clz { char clz7[__builtin_clzs(0x1) == BITSIZE(short) - 1 ? 1 : -1]; char clz8[__builtin_clzs(0xf) == BITSIZE(short) - 4 ? 1 : -1]; char clz9[__builtin_clzs(0xfff) == BITSIZE(short) - 12 ? 1 : -1]; + + int clz10 = __builtin_clzg((unsigned char)0); + char clz11[__builtin_clzg((unsigned char)0, 42) == 42 ? 1 : -1]; + char clz12[__builtin_clzg((unsigned char)0x1) == BITSIZE(char) - 1 ? 1 : -1]; + char clz13[__builtin_clzg((unsigned char)0x1, 42) == BITSIZE(char) - 1 ? 1 : -1]; + char clz14[__builtin_clzg((unsigned char)0xf) == BITSIZE(char) - 4 ? 1 : -1]; + char clz15[__builtin_clzg((unsigned char)0xf, 42) == BITSIZE(char) - 4 ? 1 : -1]; + char clz16[__builtin_clzg((unsigned char)(1 << (BITSIZE(char) - 1))) == 0 ? 1 : -1]; + char clz17[__builtin_clzg((unsigned char)(1 << (BITSIZE(char) - 1)), 42) == 0 ? 1 : -1]; + int clz18 = __builtin_clzg((unsigned short)0); + char clz19[__builtin_clzg((unsigned short)0, 42) == 42 ? 1 : -1]; + char clz20[__builtin_clzg((unsigned short)0x1) == BITSIZE(short) - 1 ? 1 : -1]; + char clz21[__builtin_clzg((unsigned short)0x1, 42) == BITSIZE(short) - 1 ? 1 : -1]; + char clz22[__builtin_clzg((unsigned short)0xf) == BITSIZE(short) - 4 ? 1 : -1]; + char clz23[__builtin_clzg((unsigned short)0xf, 42) == BITSIZE(short) - 4 ? 1 : -1]; + char clz24[__builtin_clzg((unsigned short)(1 << (BITSIZE(short) - 1))) == 0 ? 1 : -1]; + char clz25[__builtin_clzg((unsigned short)(1 << (BITSIZE(short) - 1)), 42) == 0 ? 1 : -1]; + int clz26 = __builtin_clzg(0U); + char clz27[__builtin_clzg(0U, 42) == 42 ? 1 : -1]; + char clz28[__builtin_clzg(0x1U) == BITSIZE(int) - 1 ? 1 : -1]; + char clz29[__builtin_clzg(0x1U, 42) == BITSIZE(int) - 1 ? 1 : -1]; + char clz30[__builtin_clzg(0xfU) == BITSIZE(int) - 4 ? 1 : -1]; + char clz31[__builtin_clzg(0xfU, 42) == BITSIZE(int) - 4 ? 1 : -1]; + char clz32[__builtin_clzg(1U << (BITSIZE(int) - 1)) == 0 ? 1 : -1]; + char clz33[__builtin_clzg(1U << (BITSIZE(int) - 1), 42) == 0 ? 1 : -1]; + int clz34 = __builtin_clzg(0UL); + char clz35[__builtin_clzg(0UL, 42) == 42 ? 1 : -1]; + char clz36[__builtin_clzg(0x1UL) == BITSIZE(long) - 1 ? 1 : -1]; + char clz37[__builtin_clzg(0x1UL, 42) == BITSIZE(long) - 1 ? 1 : -1]; + char clz38[__builtin_clzg(0xfUL) == BITSIZE(long) - 4 ? 1 : -1]; + char clz39[__builtin_clzg(0xfUL, 42) == BITSIZE(long) - 4 ? 1 : -1]; + char clz40[__builtin_clzg(1UL << (BITSIZE(long) - 1)) == 0 ? 1 : -1]; + char clz41[__builtin_clzg(1UL << (BITSIZE(long) - 1), 42) == 0 ? 1 : -1]; + int clz42 = __builtin_clzg(0ULL); + char clz43[__builtin_clzg(0ULL, 42) == 42 ? 1 : -1]; + char clz44[__builtin_clzg(0x1ULL) == BITSIZE(long long) - 1 ? 1 : -1]; + char clz45[__builtin_clzg(0x1ULL, 42) == BITSIZE(long long) - 1 ? 1 : -1]; + char clz46[__builtin_clzg(0xfULL) == BITSIZE(long long) - 4 ? 1 : -1]; + char clz47[__builtin_clzg(0xfULL, 42) == BITSIZE(long long) - 4 ? 1 : -1]; + char clz48[__builtin_clzg(1ULL << (BITSIZE(long long) - 1)) == 0 ? 1 : -1]; + char clz49[__builtin_clzg(1ULL << (BITSIZE(long long) - 1), 42) == 0 ? 1 : -1]; +#ifdef __SIZEOF_INT128__ + // int clz50 = __builtin_clzg((unsigned __int128)0); + char clz51[__builtin_clzg((unsigned __int128)0, 42) == 42 ? 1 : -1]; + char clz52[__builtin_clzg((unsigned __int128)0x1) == BITSIZE(__int128) - 1 ? 1 : -1]; + char clz53[__builtin_clzg((unsigned __int128)0x1, 42) == BITSIZE(__int128) - 1 ? 1 : -1]; + char clz54[__builtin_clzg((unsigned __int128)0xf) == BITSIZE(__int128) - 4 ? 1 : -1]; + char clz55[__builtin_clzg((unsigned __int128)0xf, 42) == BITSIZE(__int128) - 4 ? 1 : -1]; +#endif +#ifndef __AVR__ + // int clz58 = __builtin_clzg((unsigned _BitInt(128))0); + char clz59[__builtin_clzg((unsigned _BitInt(128))0, 42) == 42 ? 1 : -1]; + char clz60[__builtin_clzg((unsigned _BitInt(128))0x1) == BITSIZE(_BitInt(128)) - 1 ? 1 : -1]; + char clz61[__builtin_clzg((unsigned _BitInt(128))0x1, 42) == BITSIZE(_BitInt(128)) - 1 ? 1 : -1]; + char clz62[__builtin_clzg((unsigned _BitInt(128))0xf) == BITSIZE(_BitInt(128)) - 4 ? 1 : -1]; + char clz63[__builtin_clzg((unsigned _BitInt(128))0xf, 42) == BITSIZE(_BitInt(128)) - 4 ? 1 : -1]; +#endif } namespace ctz { @@ -502,6 +562,66 @@ namespace ctz { char ctz5[__builtin_ctzl(0x10L) == 4 ? 1 : -1]; char ctz6[__builtin_ctzll(0x100LL) == 8 ? 1 : -1]; char ctz7[__builtin_ctzs(1 << (BITSIZE(short) - 1)) == BITSIZE(short) - 1 ? 1 : -1]; + int ctz8 = __builtin_ctzg((unsigned char)0); + char ctz9[__builtin_ctzg((unsigned char)0, 42) == 42 ? 1 : -1]; + char ctz10[__builtin_ctzg((unsigned char)0x1) == 0 ? 1 : -1]; + char ctz11[__builtin_ctzg((unsigned char)0x1, 42) == 0 ? 1 : -1]; + char ctz12[__builtin_ctzg((unsigned char)0x10) == 4 ? 1 : -1]; + char ctz13[__builtin_ctzg((unsigned char)0x10, 42) == 4 ? 1 : -1]; + char ctz14[__builtin_ctzg((unsigned char)(1 << (BITSIZE(char) - 1))) == BITSIZE(char) - 1 ? 1 : -1]; + char ctz15[__builtin_ctzg((unsigned char)(1 << (BITSIZE(char) - 1)), 42) == BITSIZE(char) - 1 ? 1 : -1]; + int ctz16 = __builtin_ctzg((unsigned short)0); + char ctz17[__builtin_ctzg((unsigned short)0, 42) == 42 ? 1 : -1]; + char ctz18[__builtin_ctzg((unsigned short)0x1) == 0 ? 1 : -1]; + char ctz19[__builtin_ctzg((unsigned short)0x1, 42) == 0 ? 1 : -1]; + char ctz20[__builtin_ctzg((unsigned short)0x10) == 4 ? 1 : -1]; + char ctz21[__builtin_ctzg((unsigned short)0x10, 42) == 4 ? 1 : -1]; + char ctz22[__builtin_ctzg((unsigned short)(1 << (BITSIZE(short) - 1))) == BITSIZE(short) - 1 ? 1 : -1]; + char ctz23[__builtin_ctzg((unsigned short)(1 << (BITSIZE(short) - 1)), 42) == BITSIZE(short) - 1 ? 1 : -1]; + int ctz24 = __builtin_ctzg(0U); + char ctz25[__builtin_ctzg(0U, 42) == 42 ? 1 : -1]; + char ctz26[__builtin_ctzg(0x1U) == 0 ? 1 : -1]; + char ctz27[__builtin_ctzg(0x1U, 42) == 0 ? 1 : -1]; + char ctz28[__builtin_ctzg(0x10U) == 4 ? 1 : -1]; + char ctz29[__builtin_ctzg(0x10U, 42) == 4 ? 1 : -1]; + char ctz30[__builtin_ctzg(1U << (BITSIZE(int) - 1)) == BITSIZE(int) - 1 ? 1 : -1]; + char ctz31[__builtin_ctzg(1U << (BITSIZE(int) - 1), 42) == BITSIZE(int) - 1 ? 1 : -1]; + int ctz32 = __builtin_ctzg(0UL); + char ctz33[__builtin_ctzg(0UL, 42) == 42 ? 1 : -1]; + char ctz34[__builtin_ctzg(0x1UL) == 0 ? 1 : -1]; + char ctz35[__builtin_ctzg(0x1UL, 42) == 0 ? 1 : -1]; + char ctz36[__builtin_ctzg(0x10UL) == 4 ? 1 : -1]; + char ctz37[__builtin_ctzg(0x10UL, 42) == 4 ? 1 : -1]; + char ctz38[__builtin_ctzg(1UL << (BITSIZE(long) - 1)) == BITSIZE(long) - 1 ? 1 : -1]; + char ctz39[__builtin_ctzg(1UL << (BITSIZE(long) - 1), 42) == BITSIZE(long) - 1 ? 1 : -1]; + int ctz40 = __builtin_ctzg(0ULL); + char ctz41[__builtin_ctzg(0ULL, 42) == 42 ? 1 : -1]; + char ctz42[__builtin_ctzg(0x1ULL) == 0 ? 1 : -1]; + char ctz43[__builtin_ctzg(0x1ULL, 42) == 0 ? 1 : -1]; + char ctz44[__builtin_ctzg(0x10ULL) == 4 ? 1 : -1]; + char ctz45[__builtin_ctzg(0x10ULL, 42) == 4 ? 1 : -1]; + char ctz46[__builtin_ctzg(1ULL << (BITSIZE(long long) - 1)) == BITSIZE(long long) - 1 ? 1 : -1]; + char ctz47[__builtin_ctzg(1ULL << (BITSIZE(long long) - 1), 42) == BITSIZE(long long) - 1 ? 1 : -1]; +#ifdef __SIZEOF_INT128__ + // int ctz48 = __builtin_ctzg((unsigned __int128)0); + char ctz49[__builtin_ctzg((unsigned __int128)0, 42) == 42 ? 1 : -1]; + char ctz50[__builtin_ctzg((unsigned __int128)0x1) == 0 ? 1 : -1]; + char ctz51[__builtin_ctzg((unsigned __int128)0x1, 42) == 0 ? 1 : -1]; + char ctz52[__builtin_ctzg((unsigned __int128)0x10) == 4 ? 1 : -1]; + char ctz53[__builtin_ctzg((unsigned __int128)0x10, 42) == 4 ? 1 : -1]; + char ctz54[__builtin_ctzg((unsigned __int128)1 << (BITSIZE(__int128) - 1)) == BITSIZE(__int128) - 1 ? 1 : -1]; + char ctz55[__builtin_ctzg((unsigned __int128)1 << (BITSIZE(__int128) - 1), 42) == BITSIZE(__int128) - 1 ? 1 : -1]; +#endif +#ifndef __AVR__ + // int ctz56 = __builtin_ctzg((unsigned _BitInt(128))0); + char ctz57[__builtin_ctzg((unsigned _BitInt(128))0, 42) == 42 ? 1 : -1]; + char ctz58[__builtin_ctzg((unsigned _BitInt(128))0x1) == 0 ? 1 : -1]; + char ctz59[__builtin_ctzg((unsigned _BitInt(128))0x1, 42) == 0 ? 1 : -1]; + char ctz60[__builtin_ctzg((unsigned _BitInt(128))0x10) == 4 ? 1 : -1]; + char ctz61[__builtin_ctzg((unsigned _BitInt(128))0x10, 42) == 4 ? 1 : -1]; + char ctz62[__builtin_ctzg((unsigned _BitInt(128))1 << (BITSIZE(_BitInt(128)) - 1)) == BITSIZE(_BitInt(128)) - 1 ? 1 : -1]; + char ctz63[__builtin_ctzg((unsigned _BitInt(128))1 << (BITSIZE(_BitInt(128)) - 1), 42) == BITSIZE(_BitInt(128)) - 1 ? 1 : -1]; +#endif } namespace bswap { -- GitLab From 1709eac58fee8f559cd70cfce9e7f09192dcb1bc Mon Sep 17 00:00:00 2001 From: Timm Baeder Date: Wed, 10 Apr 2024 12:53:54 +0200 Subject: [PATCH 383/695] [clang][Interp] Integral pointers (#84159) This turns the current `Pointer` class into a discriminated union of `BlockPointer` and `IntPointer`. The former is what `Pointer` currently is while the latter is just an integer value and an optional `Descriptor*`. The `Pointer` then has type check functions like `isBlockPointer()`/`isIntegralPointer()`/`asBlockPointer()`/`asIntPointer()`, which can be used to access its data. Right now, the `IntPointer` and `BlockPointer` structs do not have any methods of their own and everything is instead implemented in Pointer (like it was before) and the functions now just either assert for the right type or decide what to do based on it. This also implements bitcasts by decaying the pointer to an integral pointer. `test/AST/Interp/const-eval.c` is a new test testing all kinds of stuff related to this. It still has a few tests `#ifdef`-ed out but that mostly depends on other unimplemented things like `__builtin_constant_p`. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 81 ++++- clang/lib/AST/Interp/ByteCodeStmtGen.cpp | 2 +- clang/lib/AST/Interp/Descriptor.h | 1 + clang/lib/AST/Interp/FunctionPointer.h | 10 +- clang/lib/AST/Interp/Interp.cpp | 5 + clang/lib/AST/Interp/Interp.h | 85 +++-- clang/lib/AST/Interp/InterpBlock.cpp | 4 +- clang/lib/AST/Interp/Opcodes.td | 12 + clang/lib/AST/Interp/Pointer.cpp | 168 +++++++--- clang/lib/AST/Interp/Pointer.h | 383 +++++++++++++++++------ clang/lib/AST/Interp/PrimType.h | 4 + clang/test/AST/Interp/c.c | 18 ++ clang/test/AST/Interp/const-eval.c | 192 ++++++++++++ clang/test/AST/Interp/functions.cpp | 15 + 14 files changed, 798 insertions(+), 182 deletions(-) create mode 100644 clang/test/AST/Interp/const-eval.c diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index acff63cd9dc0..84bacd457c85 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -173,10 +173,18 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { return this->emitCastFloatingIntegral(*ToT, CE); } - case CK_NullToPointer: + case CK_NullToPointer: { if (DiscardResult) return true; - return this->emitNull(classifyPrim(CE->getType()), CE); + + const Descriptor *Desc = nullptr; + const QualType PointeeType = CE->getType()->getPointeeType(); + if (!PointeeType.isNull()) { + if (std::optional T = classify(PointeeType)) + Desc = P.createDescriptor(SubExpr, *T); + } + return this->emitNull(classifyPrim(CE->getType()), Desc, CE); + } case CK_PointerToIntegral: { if (DiscardResult) @@ -199,6 +207,41 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { return true; } + case CK_IntegralToPointer: { + QualType IntType = SubExpr->getType(); + assert(IntType->isIntegralOrEnumerationType()); + if (!this->visit(SubExpr)) + return false; + // FIXME: I think the discard is wrong since the int->ptr cast might cause a + // diagnostic. + PrimType T = classifyPrim(IntType); + if (DiscardResult) + return this->emitPop(T, CE); + + QualType PtrType = CE->getType(); + assert(PtrType->isPointerType()); + + const Descriptor *Desc; + if (std::optional T = classify(PtrType->getPointeeType())) + Desc = P.createDescriptor(SubExpr, *T); + else if (PtrType->getPointeeType()->isVoidType()) + Desc = nullptr; + else + Desc = P.createDescriptor(CE, PtrType->getPointeeType().getTypePtr(), + Descriptor::InlineDescMD, true, false, + /*IsMutable=*/false, nullptr); + + if (!this->emitGetIntPtr(T, Desc, CE)) + return false; + + PrimType DestPtrT = classifyPrim(PtrType); + if (DestPtrT == PT_Ptr) + return true; + + // In case we're converting the integer to a non-Pointer. + return this->emitDecayPtr(PT_Ptr, DestPtrT, CE); + } + case CK_AtomicToNonAtomic: case CK_ConstructorConversion: case CK_FunctionToPointerDecay: @@ -207,13 +250,31 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { case CK_UserDefinedConversion: return this->delegate(SubExpr); - case CK_BitCast: + case CK_BitCast: { + // Reject bitcasts to atomic types. if (CE->getType()->isAtomicType()) { if (!this->discard(SubExpr)) return false; return this->emitInvalidCast(CastKind::Reinterpret, CE); } - return this->delegate(SubExpr); + + if (DiscardResult) + return this->discard(SubExpr); + + std::optional FromT = classify(SubExpr->getType()); + std::optional ToT = classifyPrim(CE->getType()); + if (!FromT || !ToT) + return false; + + assert(isPtrType(*FromT)); + assert(isPtrType(*ToT)); + if (FromT == ToT) + return this->delegate(SubExpr); + + if (!this->visit(SubExpr)) + return false; + return this->emitDecayPtr(*FromT, *ToT, CE); + } case CK_IntegralToBoolean: case CK_IntegralCast: { @@ -245,7 +306,7 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { if (!this->visit(SubExpr)) return false; - if (!this->emitNull(PtrT, CE)) + if (!this->emitNull(PtrT, nullptr, CE)) return false; return this->emitNE(PtrT, CE); @@ -455,7 +516,7 @@ bool ByteCodeExprGen::VisitBinaryOperator(const BinaryOperator *BO) { // Pointer arithmetic special case. if (BO->getOpcode() == BO_Add || BO->getOpcode() == BO_Sub) { - if (T == PT_Ptr || (LT == PT_Ptr && RT == PT_Ptr)) + if (isPtrType(*T) || (isPtrType(*LT) && isPtrType(*RT))) return this->VisitPointerArithBinOp(BO); } @@ -2354,7 +2415,7 @@ bool ByteCodeExprGen::visitBool(const Expr *E) { // Convert pointers to bool. if (T == PT_Ptr || T == PT_FnPtr) { - if (!this->emitNull(*T, E)) + if (!this->emitNull(*T, nullptr, E)) return false; return this->emitNE(*T, E); } @@ -2394,9 +2455,9 @@ bool ByteCodeExprGen::visitZeroInitializer(PrimType T, QualType QT, case PT_IntAPS: return this->emitZeroIntAPS(Ctx.getBitWidth(QT), E); case PT_Ptr: - return this->emitNullPtr(E); + return this->emitNullPtr(nullptr, E); case PT_FnPtr: - return this->emitNullFnPtr(E); + return this->emitNullFnPtr(nullptr, E); case PT_Float: { return this->emitConstFloat(APFloat::getZero(Ctx.getFloatSemantics(QT)), E); } @@ -2980,7 +3041,7 @@ bool ByteCodeExprGen::VisitCXXNullPtrLiteralExpr( if (DiscardResult) return true; - return this->emitNullPtr(E); + return this->emitNullPtr(nullptr, E); } template diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index 675063e74898..55a06f37a0c3 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -110,7 +110,7 @@ bool ByteCodeStmtGen::emitLambdaStaticInvokerBody( // one here, and we don't need one either because the lambda cannot have // any captures, as verified above. Emit a null pointer. This is then // special-cased when interpreting to not emit any misleading diagnostics. - if (!this->emitNullPtr(MD)) + if (!this->emitNullPtr(nullptr, MD)) return false; // Forward all arguments from the static invoker to the lambda call operator. diff --git a/clang/lib/AST/Interp/Descriptor.h b/clang/lib/AST/Interp/Descriptor.h index 4e257361ad14..c386fc8ac7b0 100644 --- a/clang/lib/AST/Interp/Descriptor.h +++ b/clang/lib/AST/Interp/Descriptor.h @@ -168,6 +168,7 @@ public: const Decl *asDecl() const { return Source.dyn_cast(); } const Expr *asExpr() const { return Source.dyn_cast(); } + const DeclTy &getSource() const { return Source; } const ValueDecl *asValueDecl() const { return dyn_cast_if_present(asDecl()); diff --git a/clang/lib/AST/Interp/FunctionPointer.h b/clang/lib/AST/Interp/FunctionPointer.h index 2ff691b1cd3e..e7fad8161fd9 100644 --- a/clang/lib/AST/Interp/FunctionPointer.h +++ b/clang/lib/AST/Interp/FunctionPointer.h @@ -22,7 +22,11 @@ private: const Function *Func; public: - FunctionPointer() : Func(nullptr) {} + // FIXME: We might want to track the fact that the Function pointer + // has been created from an integer and is most likely garbage anyway. + FunctionPointer(int IntVal = 0, const Descriptor *Desc = nullptr) + : Func(reinterpret_cast(IntVal)) {} + FunctionPointer(const Function *Func) : Func(Func) { assert(Func); } const Function *getFunction() const { return Func; } @@ -53,6 +57,10 @@ public: return toAPValue().getAsString(Ctx, Func->getDecl()->getType()); } + uint64_t getIntegerRepresentation() const { + return static_cast(reinterpret_cast(Func)); + } + ComparisonCategoryResult compare(const FunctionPointer &RHS) const { if (Func == RHS.Func) return ComparisonCategoryResult::Equal; diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 0ce64a572c26..e5e2c932f500 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -282,6 +282,8 @@ bool CheckConstant(InterpState &S, CodePtr OpPC, const Descriptor *Desc) { } static bool CheckConstant(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { + if (Ptr.isIntegralPointer()) + return true; return CheckConstant(S, OpPC, Ptr.getDeclDesc()); } @@ -335,6 +337,9 @@ bool CheckConst(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { return true; } + if (!Ptr.isBlockPointer()) + return false; + const QualType Ty = Ptr.getType(); const SourceInfo &Loc = S.Current->getSource(OpPC); S.FFDiag(Loc, diag::note_constexpr_modify_const_type) << Ty; diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 2c733c90f5f2..c7012aa4ec68 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -804,8 +804,7 @@ inline bool CmpHelperEQ(InterpState &S, CodePtr OpPC, CompareFn Fn) { for (const auto &P : {LHS, RHS}) { if (P.isZero()) continue; - if (const ValueDecl *VD = P.getDeclDesc()->asValueDecl(); - VD && VD->isWeak()) { + if (P.isWeak()) { const SourceInfo &Loc = S.Current->getSource(OpPC); S.FFDiag(Loc, diag::note_constexpr_pointer_weak_comparison) << P.toDiagnosticString(S.getCtx()); @@ -824,9 +823,9 @@ inline bool CmpHelperEQ(InterpState &S, CodePtr OpPC, CompareFn Fn) { // element in the same array are NOT equal. They have the same Base value, // but a different Offset. This is a pretty rare case, so we fix this here // by comparing pointers to the first elements. - if (!LHS.isDummy() && LHS.isArrayRoot()) + if (!LHS.isZero() && !LHS.isDummy() && LHS.isArrayRoot()) VL = LHS.atIndex(0).getByteOffset(); - if (!RHS.isDummy() && RHS.isArrayRoot()) + if (!RHS.isZero() && !RHS.isDummy() && RHS.isArrayRoot()) VR = RHS.atIndex(0).getByteOffset(); S.Stk.push(BoolT::from(Fn(Compare(VL, VR)))); @@ -1387,6 +1386,8 @@ bool Load(InterpState &S, CodePtr OpPC) { const Pointer &Ptr = S.Stk.peek(); if (!CheckLoad(S, OpPC, Ptr)) return false; + if (!Ptr.isBlockPointer()) + return false; S.Stk.push(Ptr.deref()); return true; } @@ -1396,6 +1397,8 @@ bool LoadPop(InterpState &S, CodePtr OpPC) { const Pointer &Ptr = S.Stk.pop(); if (!CheckLoad(S, OpPC, Ptr)) return false; + if (!Ptr.isBlockPointer()) + return false; S.Stk.push(Ptr.deref()); return true; } @@ -1534,8 +1537,12 @@ bool OffsetHelper(InterpState &S, CodePtr OpPC, const T &Offset, return true; } - if (!CheckNull(S, OpPC, Ptr, CSK_ArrayIndex)) - return false; + if (!CheckNull(S, OpPC, Ptr, CSK_ArrayIndex)) { + // The CheckNull will have emitted a note already, but we only + // abort in C++, since this is fine in C. + if (S.getLangOpts().CPlusPlus) + return false; + } // Arrays of unknown bounds cannot have pointers into them. if (!CheckArray(S, OpPC, Ptr)) @@ -1561,23 +1568,25 @@ bool OffsetHelper(InterpState &S, CodePtr OpPC, const T &Offset, Invalid = true; }; - T MaxOffset = T::from(MaxIndex - Index, Offset.bitWidth()); - if constexpr (Op == ArithOp::Add) { - // If the new offset would be negative, bail out. - if (Offset.isNegative() && (Offset.isMin() || -Offset > Index)) - DiagInvalidOffset(); - - // If the new offset would be out of bounds, bail out. - if (Offset.isPositive() && Offset > MaxOffset) - DiagInvalidOffset(); - } else { - // If the new offset would be negative, bail out. - if (Offset.isPositive() && Index < Offset) - DiagInvalidOffset(); - - // If the new offset would be out of bounds, bail out. - if (Offset.isNegative() && (Offset.isMin() || -Offset > MaxOffset)) - DiagInvalidOffset(); + if (Ptr.isBlockPointer()) { + T MaxOffset = T::from(MaxIndex - Index, Offset.bitWidth()); + if constexpr (Op == ArithOp::Add) { + // If the new offset would be negative, bail out. + if (Offset.isNegative() && (Offset.isMin() || -Offset > Index)) + DiagInvalidOffset(); + + // If the new offset would be out of bounds, bail out. + if (Offset.isPositive() && Offset > MaxOffset) + DiagInvalidOffset(); + } else { + // If the new offset would be negative, bail out. + if (Offset.isPositive() && Index < Offset) + DiagInvalidOffset(); + + // If the new offset would be out of bounds, bail out. + if (Offset.isNegative() && (Offset.isMin() || -Offset > MaxOffset)) + DiagInvalidOffset(); + } } if (Invalid && !Ptr.isDummy() && S.getLangOpts().CPlusPlus) @@ -1661,6 +1670,11 @@ inline bool SubPtr(InterpState &S, CodePtr OpPC) { const Pointer &LHS = S.Stk.pop(); const Pointer &RHS = S.Stk.pop(); + if (RHS.isZero()) { + S.Stk.push(T::from(LHS.getIndex())); + return true; + } + if (!Pointer::hasSameBase(LHS, RHS) && S.getLangOpts().CPlusPlus) { // TODO: Diagnose. return false; @@ -1839,8 +1853,9 @@ static inline bool ZeroIntAPS(InterpState &S, CodePtr OpPC, uint32_t BitWidth) { } template ::T> -inline bool Null(InterpState &S, CodePtr OpPC) { - S.Stk.push(); +inline bool Null(InterpState &S, CodePtr OpPC, const Descriptor *Desc) { + // Note: Desc can be null. + S.Stk.push(0, Desc); return true; } @@ -2244,6 +2259,14 @@ inline bool GetFnPtr(InterpState &S, CodePtr OpPC, const Function *Func) { return true; } +template ::T> +inline bool GetIntPtr(InterpState &S, CodePtr OpPC, const Descriptor *Desc) { + const T &IntVal = S.Stk.pop(); + + S.Stk.push(static_cast(IntVal), Desc); + return true; +} + /// Just emit a diagnostic. The expression that caused emission of this /// op is not valid in a constant context. inline bool Invalid(InterpState &S, CodePtr OpPC) { @@ -2300,6 +2323,18 @@ inline bool CheckNonNullArg(InterpState &S, CodePtr OpPC) { return false; } +/// OldPtr -> Integer -> NewPtr. +template +inline bool DecayPtr(InterpState &S, CodePtr OpPC) { + static_assert(isPtrType(TIn) && isPtrType(TOut)); + using FromT = typename PrimConv::T; + using ToT = typename PrimConv::T; + + const FromT &OldPtr = S.Stk.pop(); + S.Stk.push(ToT(OldPtr.getIntegerRepresentation(), nullptr)); + return true; +} + //===----------------------------------------------------------------------===// // Read opcode arguments //===----------------------------------------------------------------------===// diff --git a/clang/lib/AST/Interp/InterpBlock.cpp b/clang/lib/AST/Interp/InterpBlock.cpp index a62128d9cfae..9b33d1b778fb 100644 --- a/clang/lib/AST/Interp/InterpBlock.cpp +++ b/clang/lib/AST/Interp/InterpBlock.cpp @@ -73,7 +73,7 @@ void Block::replacePointer(Pointer *Old, Pointer *New) { removePointer(Old); addPointer(New); - Old->Pointee = nullptr; + Old->PointeeStorage.BS.Pointee = nullptr; #ifndef NDEBUG assert(!hasPointer(Old)); @@ -104,7 +104,7 @@ DeadBlock::DeadBlock(DeadBlock *&Root, Block *Blk) // Transfer pointers. B.Pointers = Blk->Pointers; for (Pointer *P = Blk->Pointers; P; P = P->Next) - P->Pointee = &B; + P->PointeeStorage.BS.Pointee = &B; } void DeadBlock::free() { diff --git a/clang/lib/AST/Interp/Opcodes.td b/clang/lib/AST/Interp/Opcodes.td index 6e79a03203d2..e17be3afd257 100644 --- a/clang/lib/AST/Interp/Opcodes.td +++ b/clang/lib/AST/Interp/Opcodes.td @@ -59,6 +59,7 @@ def ArgCastKind : ArgType { let Name = "CastKind"; } def ArgCallExpr : ArgType { let Name = "const CallExpr *"; } def ArgOffsetOfExpr : ArgType { let Name = "const OffsetOfExpr *"; } def ArgDeclRef : ArgType { let Name = "const DeclRefExpr *"; } +def ArgDesc : ArgType { let Name = "const Descriptor *"; } def ArgCCI : ArgType { let Name = "const ComparisonCategoryInfo *"; } //===----------------------------------------------------------------------===// @@ -272,6 +273,7 @@ def ZeroIntAPS : Opcode { // [] -> [Pointer] def Null : Opcode { let Types = [PtrTypeClass]; + let Args = [ArgDesc]; let HasGroup = 1; } @@ -530,6 +532,11 @@ def GetFnPtr : Opcode { let Args = [ArgFunction]; } +def GetIntPtr : Opcode { + let Types = [AluTypeClass]; + let Args = [ArgDesc]; + let HasGroup = 1; +} //===----------------------------------------------------------------------===// // Binary operators. @@ -662,6 +669,11 @@ def CastPointerIntegral : Opcode { let HasGroup = 1; } +def DecayPtr : Opcode { + let Types = [PtrTypeClass, PtrTypeClass]; + let HasGroup = 1; +} + //===----------------------------------------------------------------------===// // Comparison opcodes. //===----------------------------------------------------------------------===// diff --git a/clang/lib/AST/Interp/Pointer.cpp b/clang/lib/AST/Interp/Pointer.cpp index cddcd6b0151e..e163e658d462 100644 --- a/clang/lib/AST/Interp/Pointer.cpp +++ b/clang/lib/AST/Interp/Pointer.cpp @@ -26,60 +26,95 @@ Pointer::Pointer(Block *Pointee) Pointer::Pointer(Block *Pointee, unsigned BaseAndOffset) : Pointer(Pointee, BaseAndOffset, BaseAndOffset) {} -Pointer::Pointer(const Pointer &P) : Pointer(P.Pointee, P.Base, P.Offset) {} +Pointer::Pointer(const Pointer &P) + : Offset(P.Offset), PointeeStorage(P.PointeeStorage), + StorageKind(P.StorageKind) { -Pointer::Pointer(Pointer &&P) - : Pointee(P.Pointee), Base(P.Base), Offset(P.Offset) { - if (Pointee) - Pointee->replacePointer(&P, this); + if (isBlockPointer() && PointeeStorage.BS.Pointee) + PointeeStorage.BS.Pointee->addPointer(this); } Pointer::Pointer(Block *Pointee, unsigned Base, unsigned Offset) - : Pointee(Pointee), Base(Base), Offset(Offset) { + : Offset(Offset), StorageKind(Storage::Block) { assert((Base == RootPtrMark || Base % alignof(void *) == 0) && "wrong base"); + + PointeeStorage.BS = {Pointee, Base}; + if (Pointee) Pointee->addPointer(this); } +Pointer::Pointer(Pointer &&P) + : Offset(P.Offset), PointeeStorage(P.PointeeStorage), + StorageKind(P.StorageKind) { + + if (StorageKind == Storage::Block && PointeeStorage.BS.Pointee) + PointeeStorage.BS.Pointee->replacePointer(&P, this); +} + Pointer::~Pointer() { - if (Pointee) { - Pointee->removePointer(this); - Pointee->cleanup(); + if (isIntegralPointer()) + return; + + if (PointeeStorage.BS.Pointee) { + PointeeStorage.BS.Pointee->removePointer(this); + PointeeStorage.BS.Pointee->cleanup(); } } void Pointer::operator=(const Pointer &P) { - Block *Old = Pointee; - if (Pointee) - Pointee->removePointer(this); + if (!this->isIntegralPointer() || !P.isBlockPointer()) + assert(P.StorageKind == StorageKind); - Offset = P.Offset; - Base = P.Base; + bool WasBlockPointer = isBlockPointer(); + StorageKind = P.StorageKind; + if (StorageKind == Storage::Block) { + Block *Old = PointeeStorage.BS.Pointee; + if (WasBlockPointer && PointeeStorage.BS.Pointee) + PointeeStorage.BS.Pointee->removePointer(this); - Pointee = P.Pointee; - if (Pointee) - Pointee->addPointer(this); + Offset = P.Offset; + PointeeStorage.BS = P.PointeeStorage.BS; + + if (PointeeStorage.BS.Pointee) + PointeeStorage.BS.Pointee->addPointer(this); - if (Old) - Old->cleanup(); + if (WasBlockPointer && Old) + Old->cleanup(); + + } else if (StorageKind == Storage::Int) { + PointeeStorage.Int = P.PointeeStorage.Int; + } else { + assert(false && "Unhandled storage kind"); + } } void Pointer::operator=(Pointer &&P) { - Block *Old = Pointee; + if (!this->isIntegralPointer() || !P.isBlockPointer()) + assert(P.StorageKind == StorageKind); - if (Pointee) - Pointee->removePointer(this); + bool WasBlockPointer = isBlockPointer(); + StorageKind = P.StorageKind; + if (StorageKind == Storage::Block) { + Block *Old = PointeeStorage.BS.Pointee; + if (WasBlockPointer && PointeeStorage.BS.Pointee) + PointeeStorage.BS.Pointee->removePointer(this); - Offset = P.Offset; - Base = P.Base; + Offset = P.Offset; + PointeeStorage.BS = P.PointeeStorage.BS; - Pointee = P.Pointee; - if (Pointee) - Pointee->replacePointer(&P, this); + if (PointeeStorage.BS.Pointee) + PointeeStorage.BS.Pointee->addPointer(this); - if (Old) - Old->cleanup(); + if (WasBlockPointer && Old) + Old->cleanup(); + + } else if (StorageKind == Storage::Int) { + PointeeStorage.Int = P.PointeeStorage.Int; + } else { + assert(false && "Unhandled storage kind"); + } } APValue Pointer::toAPValue() const { @@ -88,6 +123,11 @@ APValue Pointer::toAPValue() const { if (isZero()) return APValue(static_cast(nullptr), CharUnits::Zero(), Path, /*IsOnePastEnd=*/false, /*IsNullPtr=*/true); + if (isIntegralPointer()) + return APValue(static_cast(nullptr), + CharUnits::fromQuantity(asIntPointer().Value + this->Offset), + Path, + /*IsOnePastEnd=*/false, /*IsNullPtr=*/false); // Build the lvalue base from the block. const Descriptor *Desc = getDeclDesc(); @@ -137,19 +177,52 @@ APValue Pointer::toAPValue() const { return APValue(Base, Offset, Path, IsOnePastEnd, /*IsNullPtr=*/false); } +void Pointer::print(llvm::raw_ostream &OS) const { + OS << PointeeStorage.BS.Pointee << " ("; + if (isBlockPointer()) { + OS << "Block) {"; + + if (PointeeStorage.BS.Base == RootPtrMark) + OS << "rootptr, "; + else + OS << PointeeStorage.BS.Base << ", "; + + if (Offset == PastEndMark) + OS << "pastend, "; + else + OS << Offset << ", "; + + if (isBlockPointer() && PointeeStorage.BS.Pointee) + OS << PointeeStorage.BS.Pointee->getSize(); + else + OS << "nullptr"; + } else { + OS << "Int) {"; + OS << PointeeStorage.Int.Value << ", " << PointeeStorage.Int.Desc; + } + OS << "}"; +} + std::string Pointer::toDiagnosticString(const ASTContext &Ctx) const { - if (!Pointee) + if (isZero()) return "nullptr"; + if (isIntegralPointer()) + return (Twine("&(") + Twine(asIntPointer().Value + Offset) + ")").str(); + return toAPValue().getAsString(Ctx, getType()); } bool Pointer::isInitialized() const { - assert(Pointee && "Cannot check if null pointer was initialized"); + if (isIntegralPointer()) + return true; + + assert(PointeeStorage.BS.Pointee && + "Cannot check if null pointer was initialized"); const Descriptor *Desc = getFieldDesc(); assert(Desc); if (Desc->isPrimitiveArray()) { - if (isStatic() && Base == 0) + if (isStatic() && PointeeStorage.BS.Base == 0) return true; InitMapPtr &IM = getInitMap(); @@ -164,17 +237,20 @@ bool Pointer::isInitialized() const { } // Field has its bit in an inline descriptor. - return Base == 0 || getInlineDesc()->IsInitialized; + return PointeeStorage.BS.Base == 0 || getInlineDesc()->IsInitialized; } void Pointer::initialize() const { - assert(Pointee && "Cannot initialize null pointer"); + if (isIntegralPointer()) + return; + + assert(PointeeStorage.BS.Pointee && "Cannot initialize null pointer"); const Descriptor *Desc = getFieldDesc(); assert(Desc); if (Desc->isPrimitiveArray()) { // Primitive global arrays don't have an initmap. - if (isStatic() && Base == 0) + if (isStatic() && PointeeStorage.BS.Base == 0) return; // Nothing to do for these. @@ -200,13 +276,15 @@ void Pointer::initialize() const { } // Field has its bit in an inline descriptor. - assert(Base != 0 && "Only composite fields can be initialised"); + assert(PointeeStorage.BS.Base != 0 && + "Only composite fields can be initialised"); getInlineDesc()->IsInitialized = true; } void Pointer::activate() const { // Field has its bit in an inline descriptor. - assert(Base != 0 && "Only composite fields can be initialised"); + assert(PointeeStorage.BS.Base != 0 && + "Only composite fields can be initialised"); getInlineDesc()->IsActive = true; } @@ -215,11 +293,23 @@ void Pointer::deactivate() const { } bool Pointer::hasSameBase(const Pointer &A, const Pointer &B) { - return A.Pointee == B.Pointee; + // Two null pointers always have the same base. + if (A.isZero() && B.isZero()) + return true; + + if (A.isIntegralPointer() && B.isIntegralPointer()) + return true; + + if (A.isIntegralPointer() || B.isIntegralPointer()) + return A.getSource() == B.getSource(); + + return A.asBlockPointer().Pointee == B.asBlockPointer().Pointee; } bool Pointer::hasSameArray(const Pointer &A, const Pointer &B) { - return hasSameBase(A, B) && A.Base == B.Base && A.getFieldDesc()->IsArray; + return hasSameBase(A, B) && + A.PointeeStorage.BS.Base == B.PointeeStorage.BS.Base && + A.getFieldDesc()->IsArray; } std::optional Pointer::toRValue(const Context &Ctx) const { diff --git a/clang/lib/AST/Interp/Pointer.h b/clang/lib/AST/Interp/Pointer.h index fffb4aba492f..fcd00aac62f9 100644 --- a/clang/lib/AST/Interp/Pointer.h +++ b/clang/lib/AST/Interp/Pointer.h @@ -28,11 +28,26 @@ class Block; class DeadBlock; class Pointer; class Context; +template class Integral; enum PrimType : unsigned; class Pointer; inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const Pointer &P); +struct BlockPointer { + /// The block the pointer is pointing to. + Block *Pointee; + /// Start of the current subfield. + unsigned Base; +}; + +struct IntPointer { + const Descriptor *Desc; + uint64_t Value; +}; + +enum class Storage { Block, Int }; + /// A pointer to a memory block, live or dead. /// /// This object can be allocated into interpreter stack frames. If pointing to @@ -68,11 +83,20 @@ private: static constexpr unsigned RootPtrMark = ~0u; public: - Pointer() {} + Pointer() { + StorageKind = Storage::Int; + PointeeStorage.Int.Value = 0; + PointeeStorage.Int.Desc = nullptr; + } Pointer(Block *B); Pointer(Block *B, unsigned BaseAndOffset); Pointer(const Pointer &P); Pointer(Pointer &&P); + Pointer(uint64_t Address, const Descriptor *Desc, unsigned Offset = 0) + : Offset(Offset), StorageKind(Storage::Int) { + PointeeStorage.Int.Value = Address; + PointeeStorage.Int.Desc = Desc; + } ~Pointer(); void operator=(const Pointer &P); @@ -80,21 +104,30 @@ public: /// Equality operators are just for tests. bool operator==(const Pointer &P) const { - return Pointee == P.Pointee && Base == P.Base && Offset == P.Offset; - } + if (P.StorageKind != StorageKind) + return false; + if (isIntegralPointer()) + return P.asIntPointer().Value == asIntPointer().Value && + Offset == P.Offset; - bool operator!=(const Pointer &P) const { - return Pointee != P.Pointee || Base != P.Base || Offset != P.Offset; + assert(isBlockPointer()); + return P.asBlockPointer().Pointee == asBlockPointer().Pointee && + P.asBlockPointer().Base == asBlockPointer().Base && + Offset == P.Offset; } + bool operator!=(const Pointer &P) const { return !(P == *this); } + /// Converts the pointer to an APValue. APValue toAPValue() const; /// Converts the pointer to a string usable in diagnostics. std::string toDiagnosticString(const ASTContext &Ctx) const; - unsigned getIntegerRepresentation() const { - return reinterpret_cast(Pointee) + Offset; + uint64_t getIntegerRepresentation() const { + if (isIntegralPointer()) + return asIntPointer().Value + (Offset * elemSize()); + return reinterpret_cast(asBlockPointer().Pointee) + Offset; } /// Converts the pointer to an APValue that is an rvalue. @@ -102,20 +135,27 @@ public: /// Offsets a pointer inside an array. [[nodiscard]] Pointer atIndex(unsigned Idx) const { - if (Base == RootPtrMark) - return Pointer(Pointee, RootPtrMark, getDeclDesc()->getSize()); + if (isIntegralPointer()) + return Pointer(asIntPointer().Value, asIntPointer().Desc, Idx); + + if (asBlockPointer().Base == RootPtrMark) + return Pointer(asBlockPointer().Pointee, RootPtrMark, + getDeclDesc()->getSize()); unsigned Off = Idx * elemSize(); if (getFieldDesc()->ElemDesc) Off += sizeof(InlineDescriptor); else Off += sizeof(InitMapPtr); - return Pointer(Pointee, Base, Base + Off); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, + asBlockPointer().Base + Off); } /// Creates a pointer to a field. [[nodiscard]] Pointer atField(unsigned Off) const { unsigned Field = Offset + Off; - return Pointer(Pointee, Field, Field); + if (isIntegralPointer()) + return Pointer(asIntPointer().Value + Field, asIntPointer().Desc); + return Pointer(asBlockPointer().Pointee, Field, Field); } /// Subtract the given offset from the current Base and Offset @@ -123,44 +163,49 @@ public: [[nodiscard]] Pointer atFieldSub(unsigned Off) const { assert(Offset >= Off); unsigned O = Offset - Off; - return Pointer(Pointee, O, O); + return Pointer(asBlockPointer().Pointee, O, O); } /// Restricts the scope of an array element pointer. [[nodiscard]] Pointer narrow() const { + if (!isBlockPointer()) + return *this; + assert(isBlockPointer()); // Null pointers cannot be narrowed. if (isZero() || isUnknownSizeArray()) return *this; // Pointer to an array of base types - enter block. - if (Base == RootPtrMark) - return Pointer(Pointee, sizeof(InlineDescriptor), + if (asBlockPointer().Base == RootPtrMark) + return Pointer(asBlockPointer().Pointee, sizeof(InlineDescriptor), Offset == 0 ? Offset : PastEndMark); // Pointer is one past end - magic offset marks that. if (isOnePastEnd()) - return Pointer(Pointee, Base, PastEndMark); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, + PastEndMark); // Primitive arrays are a bit special since they do not have inline // descriptors. If Offset != Base, then the pointer already points to // an element and there is nothing to do. Otherwise, the pointer is // adjusted to the first element of the array. if (inPrimitiveArray()) { - if (Offset != Base) + if (Offset != asBlockPointer().Base) return *this; - return Pointer(Pointee, Base, Offset + sizeof(InitMapPtr)); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, + Offset + sizeof(InitMapPtr)); } // Pointer is to a field or array element - enter it. - if (Offset != Base) - return Pointer(Pointee, Offset, Offset); + if (Offset != asBlockPointer().Base) + return Pointer(asBlockPointer().Pointee, Offset, Offset); // Enter the first element of an array. if (!getFieldDesc()->isArray()) return *this; - const unsigned NewBase = Base + sizeof(InlineDescriptor); - return Pointer(Pointee, NewBase, NewBase); + const unsigned NewBase = asBlockPointer().Base + sizeof(InlineDescriptor); + return Pointer(asBlockPointer().Pointee, NewBase, NewBase); } /// Expands a pointer to the containing array, undoing narrowing. @@ -172,72 +217,109 @@ public: Adjust = sizeof(InitMapPtr); else Adjust = sizeof(InlineDescriptor); - return Pointer(Pointee, Base, Base + getSize() + Adjust); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, + asBlockPointer().Base + getSize() + Adjust); } // Do not step out of array elements. - if (Base != Offset) + if (asBlockPointer().Base != Offset) return *this; // If at base, point to an array of base types. - if (Base == 0 || Base == sizeof(InlineDescriptor)) - return Pointer(Pointee, RootPtrMark, 0); + if (asBlockPointer().Base == 0 || + asBlockPointer().Base == sizeof(InlineDescriptor)) + return Pointer(asBlockPointer().Pointee, RootPtrMark, 0); // Step into the containing array, if inside one. - unsigned Next = Base - getInlineDesc()->Offset; + unsigned Next = asBlockPointer().Base - getInlineDesc()->Offset; const Descriptor *Desc = Next == 0 ? getDeclDesc() : getDescriptor(Next)->Desc; if (!Desc->IsArray) return *this; - return Pointer(Pointee, Next, Offset); + return Pointer(asBlockPointer().Pointee, Next, Offset); } /// Checks if the pointer is null. - bool isZero() const { return Pointee == nullptr; } + bool isZero() const { + if (Offset != 0) + return false; + + if (isBlockPointer()) + return asBlockPointer().Pointee == nullptr; + assert(isIntegralPointer()); + return asIntPointer().Value == 0; + } /// Checks if the pointer is live. - bool isLive() const { return Pointee && !Pointee->IsDead; } + bool isLive() const { + if (isIntegralPointer()) + return true; + return asBlockPointer().Pointee && !asBlockPointer().Pointee->IsDead; + } /// Checks if the item is a field in an object. bool isField() const { + if (isIntegralPointer()) + return false; + + unsigned Base = asBlockPointer().Base; return Base != 0 && Base != sizeof(InlineDescriptor) && Base != RootPtrMark && getFieldDesc()->asDecl(); } /// Accessor for information about the declaration site. const Descriptor *getDeclDesc() const { - assert(Pointee); - return Pointee->Desc; + if (isIntegralPointer()) + return asIntPointer().Desc; + + assert(isBlockPointer()); + assert(asBlockPointer().Pointee); + return asBlockPointer().Pointee->Desc; } SourceLocation getDeclLoc() const { return getDeclDesc()->getLocation(); } + /// Returns the expression or declaration the pointer has been created for. + DeclTy getSource() const { + if (isBlockPointer()) + return getDeclDesc()->getSource(); + + assert(isIntegralPointer()); + return asIntPointer().Desc ? asIntPointer().Desc->getSource() : DeclTy(); + } + /// Returns a pointer to the object of which this pointer is a field. [[nodiscard]] Pointer getBase() const { - if (Base == RootPtrMark) { + if (asBlockPointer().Base == RootPtrMark) { assert(Offset == PastEndMark && "cannot get base of a block"); - return Pointer(Pointee, Base, 0); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, 0); } - unsigned NewBase = Base - getInlineDesc()->Offset; - return Pointer(Pointee, NewBase, NewBase); + unsigned NewBase = asBlockPointer().Base - getInlineDesc()->Offset; + return Pointer(asBlockPointer().Pointee, NewBase, NewBase); } /// Returns the parent array. [[nodiscard]] Pointer getArray() const { - if (Base == RootPtrMark) { + if (asBlockPointer().Base == RootPtrMark) { assert(Offset != 0 && Offset != PastEndMark && "not an array element"); - return Pointer(Pointee, Base, 0); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, 0); } - assert(Offset != Base && "not an array element"); - return Pointer(Pointee, Base, Base); + assert(Offset != asBlockPointer().Base && "not an array element"); + return Pointer(asBlockPointer().Pointee, asBlockPointer().Base, + asBlockPointer().Base); } /// Accessors for information about the innermost field. const Descriptor *getFieldDesc() const { - if (Base == 0 || Base == sizeof(InlineDescriptor) || Base == RootPtrMark) + if (isIntegralPointer()) + return asIntPointer().Desc; + if (isBlockPointer() && + (asBlockPointer().Base == 0 || + asBlockPointer().Base == sizeof(InlineDescriptor) || + asBlockPointer().Base == RootPtrMark)) return getDeclDesc(); return getInlineDesc()->Desc; } /// Returns the type of the innermost field. QualType getType() const { - if (inPrimitiveArray() && Offset != Base) { + if (inPrimitiveArray() && Offset != asBlockPointer().Base) { // Unfortunately, complex types are not array types in clang, but they are // for us. if (const auto *AT = getFieldDesc()->getType()->getAsArrayTypeUnsafe()) @@ -248,58 +330,104 @@ public: return getFieldDesc()->getType(); } - [[nodiscard]] Pointer getDeclPtr() const { return Pointer(Pointee); } + [[nodiscard]] Pointer getDeclPtr() const { + return Pointer(asBlockPointer().Pointee); + } /// Returns the element size of the innermost field. size_t elemSize() const { - if (Base == RootPtrMark) + if (isIntegralPointer()) { + if (!asIntPointer().Desc) + return 1; + return asIntPointer().Desc->getElemSize(); + } + + if (asBlockPointer().Base == RootPtrMark) return getDeclDesc()->getSize(); return getFieldDesc()->getElemSize(); } /// Returns the total size of the innermost field. - size_t getSize() const { return getFieldDesc()->getSize(); } + size_t getSize() const { + assert(isBlockPointer()); + return getFieldDesc()->getSize(); + } /// Returns the offset into an array. unsigned getOffset() const { assert(Offset != PastEndMark && "invalid offset"); - if (Base == RootPtrMark) + if (asBlockPointer().Base == RootPtrMark) return Offset; unsigned Adjust = 0; - if (Offset != Base) { + if (Offset != asBlockPointer().Base) { if (getFieldDesc()->ElemDesc) Adjust = sizeof(InlineDescriptor); else Adjust = sizeof(InitMapPtr); } - return Offset - Base - Adjust; + return Offset - asBlockPointer().Base - Adjust; } /// Whether this array refers to an array, but not /// to the first element. - bool isArrayRoot() const { return inArray() && Offset == Base; } + bool isArrayRoot() const { + return inArray() && Offset == asBlockPointer().Base; + } /// Checks if the innermost field is an array. - bool inArray() const { return getFieldDesc()->IsArray; } + bool inArray() const { + if (isBlockPointer()) + return getFieldDesc()->IsArray; + return false; + } /// Checks if the structure is a primitive array. - bool inPrimitiveArray() const { return getFieldDesc()->isPrimitiveArray(); } + bool inPrimitiveArray() const { + if (isBlockPointer()) + return getFieldDesc()->isPrimitiveArray(); + return false; + } /// Checks if the structure is an array of unknown size. bool isUnknownSizeArray() const { + if (!isBlockPointer()) + return false; // If this points inside a dummy block, return true. // FIXME: This might change in the future. If it does, we need // to set the proper Ctor/Dtor functions for dummy Descriptors. - if (Base != 0 && Base != sizeof(InlineDescriptor) && isDummy()) + if (asBlockPointer().Base != 0 && + asBlockPointer().Base != sizeof(InlineDescriptor) && isDummy()) return true; return getFieldDesc()->isUnknownSizeArray(); } /// Checks if the pointer points to an array. - bool isArrayElement() const { return inArray() && Base != Offset; } + bool isArrayElement() const { + if (isBlockPointer()) + return inArray() && asBlockPointer().Base != Offset; + return false; + } /// Pointer points directly to a block. bool isRoot() const { - return (Base == 0 || Base == RootPtrMark) && Offset == 0; + return (asBlockPointer().Base == 0 || + asBlockPointer().Base == RootPtrMark) && + Offset == 0; } /// If this pointer has an InlineDescriptor we can use to initialize. - bool canBeInitialized() const { return Pointee && Base > 0; } + bool canBeInitialized() const { + if (!isBlockPointer()) + return false; + + return asBlockPointer().Pointee && asBlockPointer().Base > 0; + } + + [[nodiscard]] const BlockPointer &asBlockPointer() const { + assert(isBlockPointer()); + return PointeeStorage.BS; + } + [[nodiscard]] const IntPointer &asIntPointer() const { + assert(isIntegralPointer()); + return PointeeStorage.Int; + } + bool isBlockPointer() const { return StorageKind == Storage::Block; } + bool isIntegralPointer() const { return StorageKind == Storage::Int; } /// Returns the record descriptor of a class. const Record *getRecord() const { return getFieldDesc()->ElemRecord; } @@ -315,71 +443,119 @@ public: bool isUnion() const; /// Checks if the storage is extern. - bool isExtern() const { return Pointee && Pointee->isExtern(); } + bool isExtern() const { + if (isBlockPointer()) + return asBlockPointer().Pointee && asBlockPointer().Pointee->isExtern(); + return false; + } /// Checks if the storage is static. bool isStatic() const { - assert(Pointee); - return Pointee->isStatic(); + if (isIntegralPointer()) + return true; + assert(asBlockPointer().Pointee); + return asBlockPointer().Pointee->isStatic(); } /// Checks if the storage is temporary. bool isTemporary() const { - assert(Pointee); - return Pointee->isTemporary(); + if (isBlockPointer()) { + assert(asBlockPointer().Pointee); + return asBlockPointer().Pointee->isTemporary(); + } + return false; } /// Checks if the storage is a static temporary. bool isStaticTemporary() const { return isStatic() && isTemporary(); } /// Checks if the field is mutable. bool isMutable() const { - return Base != 0 && Base != sizeof(InlineDescriptor) && + if (!isBlockPointer()) + return false; + return asBlockPointer().Base != 0 && + asBlockPointer().Base != sizeof(InlineDescriptor) && getInlineDesc()->IsFieldMutable; } + + bool isWeak() const { + if (isIntegralPointer()) + return false; + + assert(isBlockPointer()); + if (const ValueDecl *VD = getDeclDesc()->asValueDecl()) + return VD->isWeak(); + return false; + } /// Checks if an object was initialized. bool isInitialized() const; /// Checks if the object is active. bool isActive() const { - return Base == 0 || Base == sizeof(InlineDescriptor) || + if (!isBlockPointer()) + return true; + return asBlockPointer().Base == 0 || + asBlockPointer().Base == sizeof(InlineDescriptor) || getInlineDesc()->IsActive; } /// Checks if a structure is a base class. bool isBaseClass() const { return isField() && getInlineDesc()->IsBase; } /// Checks if the pointer points to a dummy value. bool isDummy() const { - if (!Pointee) + if (!isBlockPointer()) return false; + + if (!asBlockPointer().Pointee) + return false; + return getDeclDesc()->isDummy(); } /// Checks if an object or a subfield is mutable. bool isConst() const { - return (Base == 0 || Base == sizeof(InlineDescriptor)) + if (isIntegralPointer()) + return true; + return (asBlockPointer().Base == 0 || + asBlockPointer().Base == sizeof(InlineDescriptor)) ? getDeclDesc()->IsConst : getInlineDesc()->IsConst; } /// Returns the declaration ID. std::optional getDeclID() const { - assert(Pointee); - return Pointee->getDeclID(); + if (isBlockPointer()) { + assert(asBlockPointer().Pointee); + return asBlockPointer().Pointee->getDeclID(); + } + return std::nullopt; } /// Returns the byte offset from the start. unsigned getByteOffset() const { + if (isIntegralPointer()) + return asIntPointer().Value + Offset; return Offset; } /// Returns the number of elements. - unsigned getNumElems() const { return getSize() / elemSize(); } + unsigned getNumElems() const { + if (isIntegralPointer()) + return ~unsigned(0); + return getSize() / elemSize(); + } - const Block *block() const { return Pointee; } + const Block *block() const { return asBlockPointer().Pointee; } /// Returns the index into an array. int64_t getIndex() const { + if (!isBlockPointer()) + return 0; + + if (isZero()) + return 0; + if (isElementPastEnd()) return 1; // narrow()ed element in a composite array. - if (Base > sizeof(InlineDescriptor) && Base == Offset) + if (asBlockPointer().Base > sizeof(InlineDescriptor) && + asBlockPointer().Base == Offset) return 0; if (auto ElemSize = elemSize()) @@ -389,7 +565,10 @@ public: /// Checks if the index is one past end. bool isOnePastEnd() const { - if (!Pointee) + if (isIntegralPointer()) + return false; + + if (!asBlockPointer().Pointee) return false; return isElementPastEnd() || getSize() == getOffset(); } @@ -400,20 +579,25 @@ public: /// Dereferences the pointer, if it's live. template T &deref() const { assert(isLive() && "Invalid pointer"); - assert(Pointee); + assert(isBlockPointer()); + assert(asBlockPointer().Pointee); + assert(Offset + sizeof(T) <= + asBlockPointer().Pointee->getDescriptor()->getAllocSize()); + if (isArrayRoot()) - return *reinterpret_cast(Pointee->rawData() + Base + - sizeof(InitMapPtr)); + return *reinterpret_cast(asBlockPointer().Pointee->rawData() + + asBlockPointer().Base + sizeof(InitMapPtr)); - assert(Offset + sizeof(T) <= Pointee->getDescriptor()->getAllocSize()); - return *reinterpret_cast(Pointee->rawData() + Offset); + return *reinterpret_cast(asBlockPointer().Pointee->rawData() + Offset); } /// Dereferences a primitive element. template T &elem(unsigned I) const { assert(I < getNumElems()); - assert(Pointee); - return reinterpret_cast(Pointee->data() + sizeof(InitMapPtr))[I]; + assert(isBlockPointer()); + assert(asBlockPointer().Pointee); + return reinterpret_cast(asBlockPointer().Pointee->data() + + sizeof(InitMapPtr))[I]; } /// Initializes a field. @@ -442,24 +626,7 @@ public: static bool hasSameArray(const Pointer &A, const Pointer &B); /// Prints the pointer. - void print(llvm::raw_ostream &OS) const { - OS << Pointee << " {"; - if (Base == RootPtrMark) - OS << "rootptr, "; - else - OS << Base << ", "; - - if (Offset == PastEndMark) - OS << "pastend, "; - else - OS << Offset << ", "; - - if (Pointee) - OS << Pointee->getSize(); - else - OS << "nullptr"; - OS << "}"; - } + void print(llvm::raw_ostream &OS) const; private: friend class Block; @@ -469,33 +636,41 @@ private: Pointer(Block *Pointee, unsigned Base, unsigned Offset); /// Returns the embedded descriptor preceding a field. - InlineDescriptor *getInlineDesc() const { return getDescriptor(Base); } + InlineDescriptor *getInlineDesc() const { + return getDescriptor(asBlockPointer().Base); + } /// Returns a descriptor at a given offset. InlineDescriptor *getDescriptor(unsigned Offset) const { assert(Offset != 0 && "Not a nested pointer"); - assert(Pointee); - return reinterpret_cast(Pointee->rawData() + Offset) - + assert(isBlockPointer()); + assert(!isZero()); + return reinterpret_cast( + asBlockPointer().Pointee->rawData() + Offset) - 1; } /// Returns a reference to the InitMapPtr which stores the initialization map. InitMapPtr &getInitMap() const { - assert(Pointee); - return *reinterpret_cast(Pointee->rawData() + Base); + assert(isBlockPointer()); + assert(!isZero()); + return *reinterpret_cast(asBlockPointer().Pointee->rawData() + + asBlockPointer().Base); } - /// The block the pointer is pointing to. - Block *Pointee = nullptr; - /// Start of the current subfield. - unsigned Base = 0; - /// Offset into the block. + /// Offset into the storage. unsigned Offset = 0; /// Previous link in the pointer chain. Pointer *Prev = nullptr; /// Next link in the pointer chain. Pointer *Next = nullptr; + + union { + BlockPointer BS; + IntPointer Int; + } PointeeStorage; + Storage StorageKind = Storage::Int; }; inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const Pointer &P) { diff --git a/clang/lib/AST/Interp/PrimType.h b/clang/lib/AST/Interp/PrimType.h index 2bc83b334643..05a094d0c5b1 100644 --- a/clang/lib/AST/Interp/PrimType.h +++ b/clang/lib/AST/Interp/PrimType.h @@ -46,6 +46,10 @@ enum PrimType : unsigned { PT_FnPtr, }; +inline constexpr bool isPtrType(PrimType T) { + return T == PT_Ptr || T == PT_FnPtr; +} + enum class CastKind : uint8_t { Reinterpret, Atomic, diff --git a/clang/test/AST/Interp/c.c b/clang/test/AST/Interp/c.c index 10e23839f2ba..cdecd3e83a99 100644 --- a/clang/test/AST/Interp/c.c +++ b/clang/test/AST/Interp/c.c @@ -209,3 +209,21 @@ const struct StrA * const sb = &sa; const struct StrA sc = *sb; _Static_assert(sc.a == 12, ""); // pedantic-ref-warning {{GNU extension}} \ // pedantic-expected-warning {{GNU extension}} + +_Static_assert(((void*)0 + 1) != (void*)0, ""); // pedantic-expected-warning {{arithmetic on a pointer to void is a GNU extension}} \ + // pedantic-expected-warning {{not an integer constant expression}} \ + // pedantic-expected-note {{cannot perform pointer arithmetic on null pointer}} \ + // pedantic-ref-warning {{arithmetic on a pointer to void is a GNU extension}} \ + // pedantic-ref-warning {{not an integer constant expression}} \ + // pedantic-ref-note {{cannot perform pointer arithmetic on null pointer}} + +typedef __INTPTR_TYPE__ intptr_t; +int array[(intptr_t)(int*)1]; // ref-warning {{variable length array folded to constant array}} \ + // pedantic-ref-warning {{variable length array folded to constant array}} \ + // expected-warning {{variable length array folded to constant array}} \ + // pedantic-expected-warning {{variable length array folded to constant array}} + +int castViaInt[*(int*)(unsigned long)"test"]; // ref-error {{variable length array}} \ + // pedantic-ref-error {{variable length array}} \ + // expected-error {{variable length array}} \ + // pedantic-expected-error {{variable length array}} diff --git a/clang/test/AST/Interp/const-eval.c b/clang/test/AST/Interp/const-eval.c new file mode 100644 index 000000000000..72c0833a0f63 --- /dev/null +++ b/clang/test/AST/Interp/const-eval.c @@ -0,0 +1,192 @@ +// RUN: %clang_cc1 -fsyntax-only -verify=both,ref -triple x86_64-linux %s -Wno-tautological-pointer-compare -Wno-pointer-to-int-cast +// RUN: %clang_cc1 -fsyntax-only -verify=both,expected -triple x86_64-linux %s -Wno-tautological-pointer-compare -Wno-pointer-to-int-cast -fexperimental-new-constant-interpreter -DNEW_INTERP +// RUN: %clang_cc1 -fsyntax-only -verify=both,ref -triple powerpc64-ibm-aix-xcoff %s -Wno-tautological-pointer-compare -Wno-pointer-to-int-cast +// RUN: %clang_cc1 -fsyntax-only -verify=both,expected -triple powerpc64-ibm-aix-xcoff %s -Wno-tautological-pointer-compare -Wno-pointer-to-int-cast -fexperimental-new-constant-interpreter -DNEW_INTERP + +/// This is a version of test/Sema/const-eval.c with the +/// tests commented out that the new constant expression interpreter does +/// not support yet. They are all marked with the NEW_INTERP define: +/// +/// - builtin_constant_p +/// - unions + + +#define EVAL_EXPR(testno, expr) enum { test##testno = (expr) }; struct check_positive##testno { int a[test##testno]; }; +int x; +EVAL_EXPR(1, (_Bool)&x) +EVAL_EXPR(2, (int)(1.0+(double)4)) +EVAL_EXPR(3, (int)(1.0+(float)4.0)) +EVAL_EXPR(4, (_Bool)(1 ? (void*)&x : 0)) +EVAL_EXPR(5, (_Bool)(int[]){0}) +struct y {int x,y;}; +EVAL_EXPR(6, (int)(1+(struct y*)0)) +_Static_assert((long)&((struct y*)0)->y > 0, ""); +EVAL_EXPR(7, (int)&((struct y*)0)->y) +EVAL_EXPR(8, (_Bool)"asdf") +EVAL_EXPR(9, !!&x) +EVAL_EXPR(10, ((void)1, 12)) +void g0(void); +EVAL_EXPR(11, (g0(), 12)) // both-error {{not an integer constant expression}} +EVAL_EXPR(12, 1.0&&2.0) +EVAL_EXPR(13, x || 3.0) // both-error {{not an integer constant expression}} + +unsigned int l_19 = 1; +EVAL_EXPR(14, (1 ^ l_19) && 1); // both-error {{not an integer constant expression}} + +void f(void) +{ + int a; + EVAL_EXPR(15, (_Bool)&a); +} + +_Complex float g16 = (1.0f + 1.0fi); + +// ?: in constant expressions. +int g17[(3?:1) - 2]; + +EVAL_EXPR(18, ((int)((void*)10 + 10)) == 20 ? 1 : -1); + +struct s { + int a[(int)-1.0f]; // both-error {{array size is negative}} +}; + +EVAL_EXPR(19, ((int)&*(char*)10 == 10 ? 1 : -1)); + +#ifndef NEW_INTERP +EVAL_EXPR(20, __builtin_constant_p(*((int*) 10))); +#endif + +EVAL_EXPR(21, (__imag__ 2i) == 2 ? 1 : -1); + +EVAL_EXPR(22, (__real__ (2i+3)) == 3 ? 1 : -1); + +int g23[(int)(1.0 / 1.0)] = { 1 }; // both-warning {{folded to constant array}} +int g24[(int)(1.0 / 1.0)] = { 1 , 2 }; // both-warning {{folded to constant array}} \ + // both-warning {{excess elements in array initializer}} +int g25[(int)(1.0 + 1.0)], g26 = sizeof(g25); // both-warning {{folded to constant array}} + +EVAL_EXPR(26, (_Complex double)0 ? -1 : 1) +EVAL_EXPR(27, (_Complex int)0 ? -1 : 1) +EVAL_EXPR(28, (_Complex double)1 ? 1 : -1) +EVAL_EXPR(29, (_Complex int)1 ? 1 : -1) + +// PR4027 +struct a { int x, y; }; +static struct a V2 = (struct a)(struct a){ 1, 2}; +static const struct a V1 = (struct a){ 1, 2}; + +EVAL_EXPR(30, (int)(_Complex float)((1<<30)-1) == (1<<30) ? 1 : -1) +EVAL_EXPR(31, (int*)0 == (int*)0 ? 1 : -1) +EVAL_EXPR(32, (int*)0 != (int*)0 ? -1 : 1) +EVAL_EXPR(33, (void*)0 - (void*)0 == 0 ? 1 : -1) + +void foo(void) {} +EVAL_EXPR(34, (foo == (void *)0) ? -1 : 1) + +// No PR. Mismatched bitwidths lead to a crash on second evaluation. +const _Bool constbool = 0; +EVAL_EXPR(35, constbool) +EVAL_EXPR(36, constbool) + +EVAL_EXPR(37, ((void)1,2.0) == 2.0 ? 1 : -1) +EVAL_EXPR(38, __builtin_expect(1,1) == 1 ? 1 : -1) + +// PR7884 +EVAL_EXPR(39, __real__(1.f) == 1 ? 1 : -1) +EVAL_EXPR(40, __imag__(1.f) == 0 ? 1 : -1) + +// From gcc testsuite +EVAL_EXPR(41, (int)(1+(_Complex unsigned)2)) + +void rdar8875946(void) { + double _Complex P; + float _Complex P2 = 3.3f + P; +} + +double d = (d = 0.0); // both-error {{not a compile-time constant}} +double d2 = ++d; // both-error {{not a compile-time constant}} + +int n = 2; +int intLvalue[*(int*)((long)&n ?: 1)] = { 1, 2 }; // both-error {{variable length array}} + +union u { int a; char b[4]; }; +char c = ((union u)(123456)).b[0]; // both-error {{not a compile-time constant}} + +#ifndef NEW_INTERP +extern const int weak_int __attribute__((weak)); +const int weak_int = 42; +int weak_int_test = weak_int; // both-error {{not a compile-time constant}} +#endif + +int literalVsNull1 = "foo" == 0; +int literalVsNull2 = 0 == "foo"; + +// PR11385. +int castViaInt[*(int*)(unsigned long)"test"]; // both-error {{variable length array}} + +// PR11391. +#ifndef NEW_INTERP +struct PR11391 { _Complex float f; } pr11391; +EVAL_EXPR(42, __builtin_constant_p(pr11391.f = 1)) +#endif + +// PR12043 +float varfloat; +const float constfloat = 0; +EVAL_EXPR(43, varfloat && constfloat) // both-error {{not an integer constant expression}} +EVAL_EXPR(45, ((char*)-1) + 1 == 0 ? 1 : -1) +EVAL_EXPR(46, ((char*)-1) + 1 < (char*) -1 ? 1 : -1) +EVAL_EXPR(47, &x < &x + 1 ? 1 : -1) +EVAL_EXPR(48, &x != &x - 1 ? 1 : -1) +EVAL_EXPR(49, &x < &x - 100 ? 1 : -1) // ref-error {{not an integer constant expression}} + +/// FIXME: Rejecting this is correct, BUT when converting the innermost pointer +/// to an integer, we do not preserve the information where it came from. So when we later +/// create a pointer from it, it also doesn't have that information, which means +/// hasSameBase() for those two pointers will return false. And in those cases, we emit +/// the diagnostic: +/// comparison between '&Test50' and '&(631578)' has unspecified value +extern struct Test50S Test50; +EVAL_EXPR(50, &Test50 < (struct Test50S*)((unsigned long)&Test50 + 10)) // both-error {{not an integer constant expression}} \ + // expected-note {{comparison between}} + +EVAL_EXPR(51, 0 != (float)1e99) + +// PR21945 +void PR21945(void) { int i = (({}), 0l); } + +void PR24622(void); +struct PR24622 {} pr24622; +EVAL_EXPR(52, &pr24622 == (void *)&PR24622); + +// We evaluate these by providing 2s' complement semantics in constant +// expressions, like we do for integers. +void *PR28739a = (__int128)(unsigned long)-1 + &PR28739a; // both-warning {{the pointer incremented by 18446744073709551615 refers past the last possible element for an array in 64-bit address space containing 64-bit (8-byte) elements (max possible 2305843009213693952 elements)}} + +void *PR28739b = &PR28739b + (__int128)(unsigned long)-1; // both-warning {{refers past the last possible element}} +__int128 PR28739c = (&PR28739c + (__int128)(unsigned long)-1) - &PR28739c; // both-warning {{refers past the last possible element}} +void *PR28739d = &(&PR28739d)[(__int128)(unsigned long)-1]; // both-warning {{refers past the last possible element}} + +struct PR35214_X { + int k; + int arr[]; +}; +int PR35214_x; +int PR35214_y = ((struct PR35214_X *)&PR35214_x)->arr[1]; // both-error {{not a compile-time constant}} +#ifndef NEW_INTERP +int *PR35214_z = &((struct PR35214_X *)&PR35214_x)->arr[1]; // ok, &PR35214_x + 2 +#endif + +/// From const-eval-64.c +EVAL_EXPR(53, ((char*)-1LL) + 1 == 0 ? 1 : -1) +EVAL_EXPR(54, ((char*)-1LL) + 1 < (char*) -1 ? 1 : -1) + +/// === Additions === +#if __SIZEOF_INT__ == 4 +typedef __INTPTR_TYPE__ intptr_t; +const intptr_t A = (intptr_t)(((int*) 0) + 1); +const intptr_t B = (intptr_t)(((char*)0) + 3); +_Static_assert(A > B, ""); +#else +#error :( +#endif diff --git a/clang/test/AST/Interp/functions.cpp b/clang/test/AST/Interp/functions.cpp index 67fd9036d81e..4fb3c816000a 100644 --- a/clang/test/AST/Interp/functions.cpp +++ b/clang/test/AST/Interp/functions.cpp @@ -185,6 +185,21 @@ namespace FunctionReturnType { constexpr int (*invalidFnPtr)() = m; static_assert(invalidFnPtr() == 5, ""); // both-error {{not an integral constant expression}} \ // both-note {{non-constexpr function 'm'}} + + +namespace ToBool { + void mismatched(int x) {} + typedef void (*callback_t)(int); + void foo() { + callback_t callback = (callback_t)mismatched; // warns + /// Casts a function pointer to a boolean and then back to a function pointer. + /// This is extracted from test/Sema/callingconv-cast.c + callback = (callback_t)!mismatched; // both-warning {{address of function 'mismatched' will always evaluate to 'true'}} \ + // both-note {{prefix with the address-of operator to silence this warning}} + } +} + + } namespace Comparison { -- GitLab From 89ba7e183e6e2c64370ed1b963e54c06352211db Mon Sep 17 00:00:00 2001 From: Utkarsh Saxena Date: Wed, 10 Apr 2024 12:59:24 +0200 Subject: [PATCH 384/695] [codegen] Emit missing cleanups for stmt-expr and coro suspensions [take-2] (#85398) Fixes https://github.com/llvm/llvm-project/issues/63818 for control flow out of an expressions. #### Background A control flow could happen in the middle of an expression due to stmt-expr and coroutine suspensions. Due to branch-in-expr, we missed running cleanups for the temporaries constructed in the expression before the branch. Previously, these cleanups were only added as `EHCleanup` during the expression and as normal expression after the full expression. Examples of such deferred cleanups include: `ParenList/InitList`: Cleanups for fields are performed by the destructor of the object being constructed. `Array init`: Cleanup for elements of an array is included in the array cleanup. `Lifetime-extended temporaries`: reference-binding temporaries in braced-init are lifetime extended to the parent scope. `Lambda capture init`: init in the lambda capture list is destroyed by the lambda object. --- #### In this PR In this PR, we change some of the `EHCleanups` cleanups to `NormalAndEHCleanups` to make sure these are emitted when we see a branch inside an expression (through statement expressions or coroutine suspensions). These are supposed to be deactivated after full expression and destroyed later as part of the destructor of the aggregate or array being constructed. To simplify deactivating cleanups, we add two utilities as well: * `DeferredDeactivationCleanupStack`: A stack to remember cleanups with deferred deactivation. * `CleanupDeactivationScope`: RAII for deactivating cleanups added to the above stack. --- #### Deactivating normal cleanups These were previously `EHCleanups` and not `Normal` and **deactivation** of **required** `Normal` cleanups had some bugs. These specifically include deactivating `Normal` cleanups which are not the top of `EHStack` [source1](https://github.com/llvm/llvm-project/blob/92b56011e6b61e7dc1628c0431ece432f282b3cb/clang/lib/CodeGen/CGCleanup.cpp#L1319), [2](https://github.com/llvm/llvm-project/blob/92b56011e6b61e7dc1628c0431ece432f282b3cb/clang/lib/CodeGen/CGCleanup.cpp#L722-L746). This has not been part of our test suite (maybe it was never required before statement expressions). In this PR, we also fix the emission of required-deactivated-normal cleanups. --- clang/lib/CodeGen/CGCleanup.cpp | 12 +- clang/lib/CodeGen/CGCleanup.h | 57 ++- clang/lib/CodeGen/CGDecl.cpp | 58 ++- clang/lib/CodeGen/CGExpr.cpp | 12 +- clang/lib/CodeGen/CGExprAgg.cpp | 87 ++--- clang/lib/CodeGen/CGExprCXX.cpp | 38 +- clang/lib/CodeGen/CodeGenFunction.cpp | 6 + clang/lib/CodeGen/CodeGenFunction.h | 96 ++++- .../CodeGenCXX/control-flow-in-stmt-expr.cpp | 364 ++++++++++++++++++ .../coro-suspend-cleanups.cpp | 93 +++++ 10 files changed, 716 insertions(+), 107 deletions(-) create mode 100644 clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp create mode 100644 clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp diff --git a/clang/lib/CodeGen/CGCleanup.cpp b/clang/lib/CodeGen/CGCleanup.cpp index e6f8e6873004..5bf48bc22a54 100644 --- a/clang/lib/CodeGen/CGCleanup.cpp +++ b/clang/lib/CodeGen/CGCleanup.cpp @@ -667,7 +667,8 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { // - whether there's a fallthrough llvm::BasicBlock *FallthroughSource = Builder.GetInsertBlock(); - bool HasFallthrough = (FallthroughSource != nullptr && IsActive); + bool HasFallthrough = + FallthroughSource != nullptr && (IsActive || HasExistingBranches); // Branch-through fall-throughs leave the insertion point set to the // end of the last cleanup, which points to the current scope. The @@ -692,7 +693,11 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { // If we have a prebranched fallthrough into an inactive normal // cleanup, rewrite it so that it leads to the appropriate place. - if (Scope.isNormalCleanup() && HasPrebranchedFallthrough && !IsActive) { + if (Scope.isNormalCleanup() && HasPrebranchedFallthrough && + !RequiresNormalCleanup) { + // FIXME: Come up with a program which would need forwarding prebranched + // fallthrough and add tests. Otherwise delete this and assert against it. + assert(!IsActive); llvm::BasicBlock *prebranchDest; // If the prebranch is semantically branching through the next @@ -765,6 +770,7 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { EmitSehCppScopeEnd(); } destroyOptimisticNormalEntry(*this, Scope); + Scope.MarkEmitted(); EHStack.popCleanup(); } else { // If we have a fallthrough and no other need for the cleanup, @@ -781,6 +787,7 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { } destroyOptimisticNormalEntry(*this, Scope); + Scope.MarkEmitted(); EHStack.popCleanup(); EmitCleanup(*this, Fn, cleanupFlags, NormalActiveFlag); @@ -916,6 +923,7 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { } // IV. Pop the cleanup and emit it. + Scope.MarkEmitted(); EHStack.popCleanup(); assert(EHStack.hasNormalCleanups() == HasEnclosingCleanups); diff --git a/clang/lib/CodeGen/CGCleanup.h b/clang/lib/CodeGen/CGCleanup.h index 03e4a29d7b3d..c73c97146abc 100644 --- a/clang/lib/CodeGen/CGCleanup.h +++ b/clang/lib/CodeGen/CGCleanup.h @@ -16,8 +16,11 @@ #include "EHScopeStack.h" #include "Address.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/IR/Instruction.h" namespace llvm { class BasicBlock; @@ -266,6 +269,51 @@ class alignas(8) EHCleanupScope : public EHScope { }; mutable struct ExtInfo *ExtInfo; + /// Erases auxillary allocas and their usages for an unused cleanup. + /// Cleanups should mark these allocas as 'used' if the cleanup is + /// emitted, otherwise these instructions would be erased. + struct AuxillaryAllocas { + SmallVector AuxAllocas; + bool used = false; + + // Records a potentially unused instruction to be erased later. + void Add(llvm::AllocaInst *Alloca) { AuxAllocas.push_back(Alloca); } + + // Mark all recorded instructions as used. These will not be erased later. + void MarkUsed() { + used = true; + AuxAllocas.clear(); + } + + ~AuxillaryAllocas() { + if (used) + return; + llvm::SetVector Uses; + for (auto *Inst : llvm::reverse(AuxAllocas)) + CollectUses(Inst, Uses); + // Delete uses in the reverse order of insertion. + for (auto *I : llvm::reverse(Uses)) + I->eraseFromParent(); + } + + private: + void CollectUses(llvm::Instruction *I, + llvm::SetVector &Uses) { + if (!I || !Uses.insert(I)) + return; + for (auto *User : I->users()) + CollectUses(cast(User), Uses); + } + }; + mutable struct AuxillaryAllocas *AuxAllocas; + + AuxillaryAllocas &getAuxillaryAllocas() { + if (!AuxAllocas) { + AuxAllocas = new struct AuxillaryAllocas(); + } + return *AuxAllocas; + } + /// The number of fixups required by enclosing scopes (not including /// this one). If this is the top cleanup scope, all the fixups /// from this index onwards belong to this scope. @@ -298,7 +346,7 @@ public: EHScopeStack::stable_iterator enclosingEH) : EHScope(EHScope::Cleanup, enclosingEH), EnclosingNormal(enclosingNormal), NormalBlock(nullptr), - ActiveFlag(Address::invalid()), ExtInfo(nullptr), + ActiveFlag(Address::invalid()), ExtInfo(nullptr), AuxAllocas(nullptr), FixupDepth(fixupDepth) { CleanupBits.IsNormalCleanup = isNormal; CleanupBits.IsEHCleanup = isEH; @@ -312,8 +360,15 @@ public: } void Destroy() { + if (AuxAllocas) + delete AuxAllocas; delete ExtInfo; } + void AddAuxAllocas(llvm::SmallVector Allocas) { + for (auto *Alloca : Allocas) + getAuxillaryAllocas().Add(Alloca); + } + void MarkEmitted() { getAuxillaryAllocas().MarkUsed(); } // Objects of EHCleanupScope are not destructed. Use Destroy(). ~EHCleanupScope() = delete; diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index 267f2e40a7bb..4f4013292b1f 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -19,6 +19,7 @@ #include "CodeGenFunction.h" #include "CodeGenModule.h" #include "ConstantEmitter.h" +#include "EHScopeStack.h" #include "PatternInit.h" #include "TargetInfo.h" #include "clang/AST/ASTContext.h" @@ -2201,6 +2202,24 @@ void CodeGenFunction::pushDestroy(CleanupKind cleanupKind, Address addr, destroyer, useEHCleanupForArray); } +// Pushes a destroy and defers its deactivation until its +// CleanupDeactivationScope is exited. +void CodeGenFunction::pushDestroyAndDeferDeactivation( + QualType::DestructionKind dtorKind, Address addr, QualType type) { + assert(dtorKind && "cannot push destructor for trivial type"); + + CleanupKind cleanupKind = getCleanupKind(dtorKind); + pushDestroyAndDeferDeactivation( + cleanupKind, addr, type, getDestroyer(dtorKind), cleanupKind & EHCleanup); +} + +void CodeGenFunction::pushDestroyAndDeferDeactivation( + CleanupKind cleanupKind, Address addr, QualType type, Destroyer *destroyer, + bool useEHCleanupForArray) { + pushCleanupAndDeferDeactivation( + cleanupKind, addr, type, destroyer, useEHCleanupForArray); +} + void CodeGenFunction::pushStackRestore(CleanupKind Kind, Address SPMem) { EHStack.pushCleanup(Kind, SPMem); } @@ -2217,16 +2236,19 @@ void CodeGenFunction::pushLifetimeExtendedDestroy(CleanupKind cleanupKind, // If we're not in a conditional branch, we don't need to bother generating a // conditional cleanup. if (!isInConditionalBranch()) { - // Push an EH-only cleanup for the object now. // FIXME: When popping normal cleanups, we need to keep this EH cleanup // around in case a temporary's destructor throws an exception. - if (cleanupKind & EHCleanup) - EHStack.pushCleanup( - static_cast(cleanupKind & ~NormalCleanup), addr, type, - destroyer, useEHCleanupForArray); + // Add the cleanup to the EHStack. After the full-expr, this would be + // deactivated before being popped from the stack. + pushDestroyAndDeferDeactivation(cleanupKind, addr, type, destroyer, + useEHCleanupForArray); + + // Since this is lifetime-extended, push it once again to the EHStack after + // the full expression. return pushCleanupAfterFullExprWithActiveFlag( - cleanupKind, Address::invalid(), addr, type, destroyer, useEHCleanupForArray); + cleanupKind, Address::invalid(), addr, type, destroyer, + useEHCleanupForArray); } // Otherwise, we should only destroy the object if it's been initialized. @@ -2241,13 +2263,12 @@ void CodeGenFunction::pushLifetimeExtendedDestroy(CleanupKind cleanupKind, Address ActiveFlag = createCleanupActiveFlag(); SavedType SavedAddr = saveValueInCond(addr); - if (cleanupKind & EHCleanup) { - EHStack.pushCleanup( - static_cast(cleanupKind & ~NormalCleanup), SavedAddr, type, - destroyer, useEHCleanupForArray); - initFullExprCleanupWithFlag(ActiveFlag); - } + pushCleanupAndDeferDeactivation( + cleanupKind, SavedAddr, type, destroyer, useEHCleanupForArray); + initFullExprCleanupWithFlag(ActiveFlag); + // Since this is lifetime-extended, push it once again to the EHStack after + // the full expression. pushCleanupAfterFullExprWithActiveFlag( cleanupKind, ActiveFlag, SavedAddr, type, destroyer, useEHCleanupForArray); @@ -2442,9 +2463,9 @@ namespace { }; } // end anonymous namespace -/// pushIrregularPartialArrayCleanup - Push an EH cleanup to destroy -/// already-constructed elements of the given array. The cleanup -/// may be popped with DeactivateCleanupBlock or PopCleanupBlock. +/// pushIrregularPartialArrayCleanup - Push a NormalAndEHCleanup to +/// destroy already-constructed elements of the given array. The cleanup may be +/// popped with DeactivateCleanupBlock or PopCleanupBlock. /// /// \param elementType - the immediate element type of the array; /// possibly still an array type @@ -2453,10 +2474,9 @@ void CodeGenFunction::pushIrregularPartialArrayCleanup(llvm::Value *arrayBegin, QualType elementType, CharUnits elementAlign, Destroyer *destroyer) { - pushFullExprCleanup(EHCleanup, - arrayBegin, arrayEndPointer, - elementType, elementAlign, - destroyer); + pushFullExprCleanup( + NormalAndEHCleanup, arrayBegin, arrayEndPointer, elementType, + elementAlign, destroyer); } /// pushRegularPartialArrayCleanup - Push an EH cleanup to destroy diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index cf696a1c9f56..c85a339f5e3f 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -115,10 +115,16 @@ RawAddress CodeGenFunction::CreateTempAlloca(llvm::Type *Ty, CharUnits Align, llvm::AllocaInst *CodeGenFunction::CreateTempAlloca(llvm::Type *Ty, const Twine &Name, llvm::Value *ArraySize) { + llvm::AllocaInst *Alloca; if (ArraySize) - return Builder.CreateAlloca(Ty, ArraySize, Name); - return new llvm::AllocaInst(Ty, CGM.getDataLayout().getAllocaAddrSpace(), - ArraySize, Name, AllocaInsertPt); + Alloca = Builder.CreateAlloca(Ty, ArraySize, Name); + else + Alloca = new llvm::AllocaInst(Ty, CGM.getDataLayout().getAllocaAddrSpace(), + ArraySize, Name, AllocaInsertPt); + if (Allocas) { + Allocas->Add(Alloca); + } + return Alloca; } /// CreateDefaultAlignTempAlloca - This creates an alloca with the diff --git a/clang/lib/CodeGen/CGExprAgg.cpp b/clang/lib/CodeGen/CGExprAgg.cpp index 1b9287ea2393..560a9e2c5ead 100644 --- a/clang/lib/CodeGen/CGExprAgg.cpp +++ b/clang/lib/CodeGen/CGExprAgg.cpp @@ -15,6 +15,7 @@ #include "CodeGenFunction.h" #include "CodeGenModule.h" #include "ConstantEmitter.h" +#include "EHScopeStack.h" #include "TargetInfo.h" #include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" @@ -24,6 +25,7 @@ #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Instruction.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Intrinsics.h" using namespace clang; @@ -558,24 +560,27 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType, // For that, we'll need an EH cleanup. QualType::DestructionKind dtorKind = elementType.isDestructedType(); Address endOfInit = Address::invalid(); - EHScopeStack::stable_iterator cleanup; - llvm::Instruction *cleanupDominator = nullptr; - if (CGF.needsEHCleanup(dtorKind)) { + CodeGenFunction::CleanupDeactivationScope deactivation(CGF); + + if (dtorKind) { + CodeGenFunction::AllocaTrackerRAII allocaTracker(CGF); // In principle we could tell the cleanup where we are more // directly, but the control flow can get so varied here that it // would actually be quite complex. Therefore we go through an // alloca. + llvm::Instruction *dominatingIP = + Builder.CreateFlagLoad(llvm::ConstantInt::getNullValue(CGF.Int8PtrTy)); endOfInit = CGF.CreateTempAlloca(begin->getType(), CGF.getPointerAlign(), "arrayinit.endOfInit"); - cleanupDominator = Builder.CreateStore(begin, endOfInit); + Builder.CreateStore(begin, endOfInit); CGF.pushIrregularPartialArrayCleanup(begin, endOfInit, elementType, elementAlign, CGF.getDestroyer(dtorKind)); - cleanup = CGF.EHStack.stable_begin(); + cast(*CGF.EHStack.find(CGF.EHStack.stable_begin())) + .AddAuxAllocas(allocaTracker.Take()); - // Otherwise, remember that we didn't need a cleanup. - } else { - dtorKind = QualType::DK_none; + CGF.DeferredDeactivationCleanupStack.push_back( + {CGF.EHStack.stable_begin(), dominatingIP}); } llvm::Value *one = llvm::ConstantInt::get(CGF.SizeTy, 1); @@ -671,9 +676,6 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType, CGF.EmitBlock(endBB); } - - // Leave the partial-array cleanup if we entered one. - if (dtorKind) CGF.DeactivateCleanupBlock(cleanup, cleanupDominator); } //===----------------------------------------------------------------------===// @@ -1374,9 +1376,8 @@ AggExprEmitter::VisitLambdaExpr(LambdaExpr *E) { LValue SlotLV = CGF.MakeAddrLValue(Slot.getAddress(), E->getType()); // We'll need to enter cleanup scopes in case any of the element - // initializers throws an exception. - SmallVector Cleanups; - llvm::Instruction *CleanupDominator = nullptr; + // initializers throws an exception or contains branch out of the expressions. + CodeGenFunction::CleanupDeactivationScope scope(CGF); CXXRecordDecl::field_iterator CurField = E->getLambdaClass()->field_begin(); for (LambdaExpr::const_capture_init_iterator i = E->capture_init_begin(), @@ -1395,28 +1396,12 @@ AggExprEmitter::VisitLambdaExpr(LambdaExpr *E) { if (QualType::DestructionKind DtorKind = CurField->getType().isDestructedType()) { assert(LV.isSimple()); - if (CGF.needsEHCleanup(DtorKind)) { - if (!CleanupDominator) - CleanupDominator = CGF.Builder.CreateAlignedLoad( - CGF.Int8Ty, - llvm::Constant::getNullValue(CGF.Int8PtrTy), - CharUnits::One()); // placeholder - - CGF.pushDestroy(EHCleanup, LV.getAddress(CGF), CurField->getType(), - CGF.getDestroyer(DtorKind), false); - Cleanups.push_back(CGF.EHStack.stable_begin()); - } + if (DtorKind) + CGF.pushDestroyAndDeferDeactivation( + NormalAndEHCleanup, LV.getAddress(CGF), CurField->getType(), + CGF.getDestroyer(DtorKind), false); } } - - // Deactivate all the partial cleanups in reverse order, which - // generally means popping them. - for (unsigned i = Cleanups.size(); i != 0; --i) - CGF.DeactivateCleanupBlock(Cleanups[i-1], CleanupDominator); - - // Destroy the placeholder if we made one. - if (CleanupDominator) - CleanupDominator->eraseFromParent(); } void AggExprEmitter::VisitExprWithCleanups(ExprWithCleanups *E) { @@ -1705,14 +1690,7 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( // We'll need to enter cleanup scopes in case any of the element // initializers throws an exception. SmallVector cleanups; - llvm::Instruction *cleanupDominator = nullptr; - auto addCleanup = [&](const EHScopeStack::stable_iterator &cleanup) { - cleanups.push_back(cleanup); - if (!cleanupDominator) // create placeholder once needed - cleanupDominator = CGF.Builder.CreateAlignedLoad( - CGF.Int8Ty, llvm::Constant::getNullValue(CGF.Int8PtrTy), - CharUnits::One()); - }; + CodeGenFunction::CleanupDeactivationScope DeactivateCleanups(CGF); unsigned curInitIndex = 0; @@ -1735,10 +1713,8 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( CGF.EmitAggExpr(InitExprs[curInitIndex++], AggSlot); if (QualType::DestructionKind dtorKind = - Base.getType().isDestructedType()) { - CGF.pushDestroy(dtorKind, V, Base.getType()); - addCleanup(CGF.EHStack.stable_begin()); - } + Base.getType().isDestructedType()) + CGF.pushDestroyAndDeferDeactivation(dtorKind, V, Base.getType()); } } @@ -1813,10 +1789,10 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( if (QualType::DestructionKind dtorKind = field->getType().isDestructedType()) { assert(LV.isSimple()); - if (CGF.needsEHCleanup(dtorKind)) { - CGF.pushDestroy(EHCleanup, LV.getAddress(CGF), field->getType(), - CGF.getDestroyer(dtorKind), false); - addCleanup(CGF.EHStack.stable_begin()); + if (dtorKind) { + CGF.pushDestroyAndDeferDeactivation( + NormalAndEHCleanup, LV.getAddress(CGF), field->getType(), + CGF.getDestroyer(dtorKind), false); pushedCleanup = true; } } @@ -1829,17 +1805,6 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( if (GEP->use_empty()) GEP->eraseFromParent(); } - - // Deactivate all the partial cleanups in reverse order, which - // generally means popping them. - assert((cleanupDominator || cleanups.empty()) && - "Missing cleanupDominator before deactivating cleanup blocks"); - for (unsigned i = cleanups.size(); i != 0; --i) - CGF.DeactivateCleanupBlock(cleanups[i-1], cleanupDominator); - - // Destroy the placeholder if we made one. - if (cleanupDominator) - cleanupDominator->eraseFromParent(); } void AggExprEmitter::VisitArrayInitLoopExpr(const ArrayInitLoopExpr *E, diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index a4fb673284ce..a88b29b326bb 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -1008,8 +1008,8 @@ void CodeGenFunction::EmitNewArrayInitializer( const Expr *Init = E->getInitializer(); Address EndOfInit = Address::invalid(); QualType::DestructionKind DtorKind = ElementType.isDestructedType(); - EHScopeStack::stable_iterator Cleanup; - llvm::Instruction *CleanupDominator = nullptr; + CleanupDeactivationScope deactivation(*this); + bool pushedCleanup = false; CharUnits ElementSize = getContext().getTypeSizeInChars(ElementType); CharUnits ElementAlign = @@ -1105,19 +1105,24 @@ void CodeGenFunction::EmitNewArrayInitializer( } // Enter a partial-destruction Cleanup if necessary. - if (needsEHCleanup(DtorKind)) { + if (DtorKind) { + AllocaTrackerRAII AllocaTracker(*this); // In principle we could tell the Cleanup where we are more // directly, but the control flow can get so varied here that it // would actually be quite complex. Therefore we go through an // alloca. + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::ConstantInt::getNullValue(Int8PtrTy)); EndOfInit = CreateTempAlloca(BeginPtr.getType(), getPointerAlign(), "array.init.end"); - CleanupDominator = - Builder.CreateStore(BeginPtr.emitRawPointer(*this), EndOfInit); pushIrregularPartialArrayCleanup(BeginPtr.emitRawPointer(*this), EndOfInit, ElementType, ElementAlign, getDestroyer(DtorKind)); - Cleanup = EHStack.stable_begin(); + cast(*EHStack.find(EHStack.stable_begin())) + .AddAuxAllocas(AllocaTracker.Take()); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); + pushedCleanup = true; } CharUnits StartAlign = CurPtr.getAlignment(); @@ -1164,9 +1169,6 @@ void CodeGenFunction::EmitNewArrayInitializer( // initialization. llvm::ConstantInt *ConstNum = dyn_cast(NumElements); if (ConstNum && ConstNum->getZExtValue() <= InitListElements) { - // If there was a Cleanup, deactivate it. - if (CleanupDominator) - DeactivateCleanupBlock(Cleanup, CleanupDominator); return; } @@ -1281,13 +1283,14 @@ void CodeGenFunction::EmitNewArrayInitializer( Builder.CreateStore(CurPtr.emitRawPointer(*this), EndOfInit); // Enter a partial-destruction Cleanup if necessary. - if (!CleanupDominator && needsEHCleanup(DtorKind)) { - llvm::Value *BeginPtrRaw = BeginPtr.emitRawPointer(*this); - llvm::Value *CurPtrRaw = CurPtr.emitRawPointer(*this); - pushRegularPartialArrayCleanup(BeginPtrRaw, CurPtrRaw, ElementType, + if (!pushedCleanup && needsEHCleanup(DtorKind)) { + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::ConstantInt::getNullValue(Int8PtrTy)); + pushRegularPartialArrayCleanup(BeginPtr.emitRawPointer(*this), + CurPtr.emitRawPointer(*this), ElementType, ElementAlign, getDestroyer(DtorKind)); - Cleanup = EHStack.stable_begin(); - CleanupDominator = Builder.CreateUnreachable(); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); } // Emit the initializer into this element. @@ -1295,10 +1298,7 @@ void CodeGenFunction::EmitNewArrayInitializer( AggValueSlot::DoesNotOverlap); // Leave the Cleanup if we entered one. - if (CleanupDominator) { - DeactivateCleanupBlock(Cleanup, CleanupDominator); - CleanupDominator->eraseFromParent(); - } + deactivation.ForceDeactivate(); // Advance to the next element by adjusting the pointer type as necessary. llvm::Value *NextPtr = Builder.CreateConstInBoundsGEP1_32( diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index 6474d6c8c1d1..a2d746bb8f4f 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -91,6 +91,8 @@ CodeGenFunction::CodeGenFunction(CodeGenModule &cgm, bool suppressNewContext) CodeGenFunction::~CodeGenFunction() { assert(LifetimeExtendedCleanupStack.empty() && "failed to emit a cleanup"); + assert(DeferredDeactivationCleanupStack.empty() && + "missed to deactivate a cleanup"); if (getLangOpts().OpenMP && CurFn) CGM.getOpenMPRuntime().functionFinished(*this); @@ -346,6 +348,10 @@ static void EmitIfUsed(CodeGenFunction &CGF, llvm::BasicBlock *BB) { void CodeGenFunction::FinishFunction(SourceLocation EndLoc) { assert(BreakContinueStack.empty() && "mismatched push/pop in break/continue stack!"); + assert(LifetimeExtendedCleanupStack.empty() && + "mismatched push/pop of cleanups in EHStack!"); + assert(DeferredDeactivationCleanupStack.empty() && + "mismatched activate/deactivate of cleanups!"); bool OnlySimpleReturnStmts = NumSimpleReturnExprs > 0 && NumSimpleReturnExprs == NumReturnExprs diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index ff1873325d40..c49e9fd00c8d 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -39,6 +39,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Frontend/OpenMP/OMPIRBuilder.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/ValueHandle.h" #include "llvm/Support/Debug.h" #include "llvm/Transforms/Utils/SanitizerStats.h" @@ -670,6 +671,51 @@ public: EHScopeStack EHStack; llvm::SmallVector LifetimeExtendedCleanupStack; + + // A stack of cleanups which were added to EHStack but have to be deactivated + // later before being popped or emitted. These are usually deactivated on + // exiting a `CleanupDeactivationScope` scope. For instance, after a + // full-expr. + // + // These are specially useful for correctly emitting cleanups while + // encountering branches out of expression (through stmt-expr or coroutine + // suspensions). + struct DeferredDeactivateCleanup { + EHScopeStack::stable_iterator Cleanup; + llvm::Instruction *DominatingIP; + }; + llvm::SmallVector DeferredDeactivationCleanupStack; + + // Enters a new scope for capturing cleanups which are deferred to be + // deactivated, all of which will be deactivated once the scope is exited. + struct CleanupDeactivationScope { + CodeGenFunction &CGF; + size_t OldDeactivateCleanupStackSize; + bool Deactivated; + CleanupDeactivationScope(CodeGenFunction &CGF) + : CGF(CGF), OldDeactivateCleanupStackSize( + CGF.DeferredDeactivationCleanupStack.size()), + Deactivated(false) {} + + void ForceDeactivate() { + assert(!Deactivated && "Deactivating already deactivated scope"); + auto &Stack = CGF.DeferredDeactivationCleanupStack; + for (size_t I = Stack.size(); I > OldDeactivateCleanupStackSize; I--) { + CGF.DeactivateCleanupBlock(Stack[I - 1].Cleanup, + Stack[I - 1].DominatingIP); + Stack[I - 1].DominatingIP->eraseFromParent(); + } + Stack.resize(OldDeactivateCleanupStackSize); + Deactivated = true; + } + + ~CleanupDeactivationScope() { + if (Deactivated) + return; + ForceDeactivate(); + } + }; + llvm::SmallVector SEHTryEpilogueStack; llvm::Instruction *CurrentFuncletPad = nullptr; @@ -875,6 +921,19 @@ public: new (Buffer + sizeof(Header) + sizeof(T)) RawAddress(ActiveFlag); } + // Push a cleanup onto EHStack and deactivate it later. It is usually + // deactivated when exiting a `CleanupDeactivationScope` (for example: after a + // full expression). + template + void pushCleanupAndDeferDeactivation(CleanupKind Kind, As... A) { + // Placeholder dominating IP for this cleanup. + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::Constant::getNullValue(Int8PtrTy)); + EHStack.pushCleanup(Kind, A...); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); + } + /// Set up the last cleanup that was pushed as a conditional /// full-expression cleanup. void initFullExprCleanup() { @@ -926,6 +985,7 @@ public: class RunCleanupsScope { EHScopeStack::stable_iterator CleanupStackDepth, OldCleanupScopeDepth; size_t LifetimeExtendedCleanupStackSize; + CleanupDeactivationScope DeactivateCleanups; bool OldDidCallStackSave; protected: bool PerformCleanup; @@ -940,8 +1000,7 @@ public: public: /// Enter a new cleanup scope. explicit RunCleanupsScope(CodeGenFunction &CGF) - : PerformCleanup(true), CGF(CGF) - { + : DeactivateCleanups(CGF), PerformCleanup(true), CGF(CGF) { CleanupStackDepth = CGF.EHStack.stable_begin(); LifetimeExtendedCleanupStackSize = CGF.LifetimeExtendedCleanupStack.size(); @@ -971,6 +1030,7 @@ public: void ForceCleanup(std::initializer_list ValuesToReload = {}) { assert(PerformCleanup && "Already forced cleanup"); CGF.DidCallStackSave = OldDidCallStackSave; + DeactivateCleanups.ForceDeactivate(); CGF.PopCleanupBlocks(CleanupStackDepth, LifetimeExtendedCleanupStackSize, ValuesToReload); PerformCleanup = false; @@ -2160,6 +2220,11 @@ public: Address addr, QualType type); void pushDestroy(CleanupKind kind, Address addr, QualType type, Destroyer *destroyer, bool useEHCleanupForArray); + void pushDestroyAndDeferDeactivation(QualType::DestructionKind dtorKind, + Address addr, QualType type); + void pushDestroyAndDeferDeactivation(CleanupKind cleanupKind, Address addr, + QualType type, Destroyer *destroyer, + bool useEHCleanupForArray); void pushLifetimeExtendedDestroy(CleanupKind kind, Address addr, QualType type, Destroyer *destroyer, bool useEHCleanupForArray); @@ -2698,6 +2763,33 @@ public: TBAAAccessInfo *TBAAInfo = nullptr); LValue EmitLoadOfPointerLValue(Address Ptr, const PointerType *PtrTy); +private: + struct AllocaTracker { + void Add(llvm::AllocaInst *I) { Allocas.push_back(I); } + llvm::SmallVector Take() { return std::move(Allocas); } + + private: + llvm::SmallVector Allocas; + }; + AllocaTracker *Allocas = nullptr; + +public: + // Captures all the allocas created during the scope of its RAII object. + struct AllocaTrackerRAII { + AllocaTrackerRAII(CodeGenFunction &CGF) + : CGF(CGF), OldTracker(CGF.Allocas) { + CGF.Allocas = &Tracker; + } + ~AllocaTrackerRAII() { CGF.Allocas = OldTracker; } + + llvm::SmallVector Take() { return Tracker.Take(); } + + private: + CodeGenFunction &CGF; + AllocaTracker *OldTracker; + AllocaTracker Tracker; + }; + /// CreateTempAlloca - This creates an alloca and inserts it into the entry /// block if \p ArraySize is nullptr, otherwise inserts it at the current /// insertion point of the builder. The caller is responsible for setting an diff --git a/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp b/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp new file mode 100644 index 000000000000..ffde1bd6a724 --- /dev/null +++ b/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp @@ -0,0 +1,364 @@ +// RUN: %clang_cc1 --std=c++20 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s + +struct Printy { + Printy(const char *name) : name(name) {} + ~Printy() {} + const char *name; +}; + +int foo() { return 2; } + +struct Printies { + Printy a; + Printy b; + Printy c; +}; + +void ParenInit() { + // CHECK-LABEL: define dso_local void @_Z9ParenInitv() + // CHECK: [[CLEANUP_DEST:%.+]] = alloca i32, align 4 + Printies ps(Printy("a"), + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + if (foo()) return; + // CHECK: if.then: + // CHECK-NEXT: store i32 1, ptr [[CLEANUP_DEST]], align 4 + // CHECK-NEXT: br label %cleanup + Printy("b"); + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + ({ + if (foo()) return; + // CHECK: if.then{{.*}}: + // CHECK-NEXT: store i32 1, ptr [[CLEANUP_DEST]], align 4 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %cleanup + Printy("c"); + // CHECK: if.end{{.*}}: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %return + })); + // CHECK: cleanup: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %return +} + +void break_in_stmt_expr() { + // Verify that the "break" in "if.then".calls dtor before jumping to "for.end". + + // CHECK-LABEL: define dso_local void @_Z18break_in_stmt_exprv() + Printies p{Printy("a"), + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + for (;;) { + Printies ps{ + Printy("b"), + // CHECK: for.cond: + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + if (foo()) { + break; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %for.end + } + Printy("c"); + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("d")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %for.cond + } + Printy("e"); + // CHECK: for.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("f")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev +} + +void goto_in_stmt_expr() { + // Verify that: + // - correct branch fixups for deactivated normal cleanups are generated correctly. + + // CHECK-LABEL: define dso_local void @_Z17goto_in_stmt_exprv() + // CHECK: [[CLEANUP_DEST_SLOT:%cleanup.dest.slot.*]] = alloca i32, align 4 + { + Printies p1{Printy("a"), // CHECK: call void @_ZN6PrintyC1EPKc + ({ + { + Printies p2{Printy("b"), + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + if (foo() == 1) { + goto in; + // CHECK: if.then: + // CHECK-NEXT: store i32 2, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: br label %[[CLEANUP1:.+]] + } + if (foo() == 2) { + goto out; + // CHECK: if.then{{.*}}: + // CHECK-NEXT: store i32 3, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: br label %[[CLEANUP1]] + } + Printy("c"); + // CHECK: if.end{{.*}}: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("d")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %in + + } + in: + Printy("e"); + // CHECK: in: ; preds = %if.end{{.*}}, %[[CLEANUP1]] + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("f")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %out + } +out: + return; + // CHECK: out: + // CHECK-NEXT: ret void + + // CHECK: [[CLEANUP1]]: ; preds = %if.then{{.*}}, %if.then + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: %cleanup.dest = load i32, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: switch i32 %cleanup.dest, label %[[CLEANUP2:.+]] [ + // CHECK-NEXT: i32 2, label %in + // CHECK-NEXT: ] + + // CHECK: [[CLEANUP2]]: ; preds = %[[CLEANUP1]] + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: %cleanup.dest{{.*}} = load i32, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: switch i32 %cleanup.dest{{.*}}, label %unreachable [ + // CHECK-NEXT: i32 3, label %out + // CHECK-NEXT: ] +} + +void ArrayInit() { + // Printy arr[4] = {ctorA, ctorB, stmt-exprC, stmt-exprD}; + // Verify that: + // - We do the necessary stores for array cleanups (endOfInit and last constructed element). + // - We update the array init element correctly for ctorA, ctorB and stmt-exprC. + // - stmt-exprC and stmt-exprD share the array body dtor code (see %cleanup). + + // CHECK-LABEL: define dso_local void @_Z9ArrayInitv() + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + // CHECK: %cleanup.dest.slot = alloca i32, align 4 + // CHECK: %arrayinit.begin = getelementptr inbounds [4 x %struct.Printy], ptr %arr, i64 0, i64 0 + // CHECK: store ptr %arrayinit.begin, ptr %arrayinit.endOfInit, align 8 + Printy arr[4] = { + Printy("a"), + // CHECK: call void @_ZN6PrintyC1EPKc(ptr noundef nonnull align 8 dereferenceable(8) %arrayinit.begin, ptr noundef @.str) + // CHECK: [[ARRAYINIT_ELEMENT1:%.+]] = getelementptr inbounds %struct.Printy, ptr %arrayinit.begin, i64 1 + // CHECK: store ptr [[ARRAYINIT_ELEMENT1]], ptr %arrayinit.endOfInit, align 8 + Printy("b"), + // CHECK: call void @_ZN6PrintyC1EPKc(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT1]], ptr noundef @.str.1) + // CHECK: [[ARRAYINIT_ELEMENT2:%.+]] = getelementptr inbounds %struct.Printy, ptr [[ARRAYINIT_ELEMENT1]], i64 1 + // CHECK: store ptr [[ARRAYINIT_ELEMENT2]], ptr %arrayinit.endOfInit, align 8 + ({ + // CHECK: br i1 {{.*}}, label %if.then, label %if.end + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: store i32 1, ptr %cleanup.dest.slot, align 4 + // CHECK-NEXT: br label %cleanup + } + // CHECK: if.end: + Printy("c"); + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: %arrayinit.element2 = getelementptr inbounds %struct.Printy, ptr %arrayinit.element1, i64 1 + // CHECK-NEXT: store ptr %arrayinit.element2, ptr %arrayinit.endOfInit, align 8 + }), + ({ + // CHECK: br i1 {{%.+}} label %[[IF_THEN2:.+]], label %[[IF_END2:.+]] + if (foo()) { + return; + // CHECK: [[IF_THEN2]]: + // CHECK-NEXT: store i32 1, ptr %cleanup.dest.slot, align 4 + // CHECK-NEXT: br label %cleanup + } + // CHECK: [[IF_END2]]: + Printy("d"); + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: %array.begin = getelementptr inbounds [4 x %struct.Printy], ptr %arr, i32 0, i32 0 + // CHECK-NEXT: %0 = getelementptr inbounds %struct.Printy, ptr %array.begin, i64 4 + // CHECK-NEXT: br label %[[ARRAY_DESTROY_BODY1:.+]] + }), + }; + + // CHECK: [[ARRAY_DESTROY_BODY1]]: + // CHECK-NEXT: %arraydestroy.elementPast{{.*}} = phi ptr [ %0, %[[IF_END2]] ], [ %arraydestroy.element{{.*}}, %[[ARRAY_DESTROY_BODY1]] ] + // CHECK-NEXT: %arraydestroy.element{{.*}} = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast{{.*}}, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: %arraydestroy.done{{.*}} = icmp eq ptr %arraydestroy.element{{.*}}, %array.begin + // CHECK-NEXT: br i1 %arraydestroy.done{{.*}}, label %[[ARRAY_DESTROY_DONE1:.+]], label %[[ARRAY_DESTROY_BODY1]] + + // CHECK: [[ARRAY_DESTROY_DONE1]]: + // CHECK-NEXT: ret void + + // CHECK: cleanup: + // CHECK-NEXT: %1 = load ptr, ptr %arrayinit.endOfInit, align 8 + // CHECK-NEXT: %arraydestroy.isempty = icmp eq ptr %arrayinit.begin, %1 + // CHECK-NEXT: br i1 %arraydestroy.isempty, label %[[ARRAY_DESTROY_DONE2:.+]], label %[[ARRAY_DESTROY_BODY2:.+]] + + // CHECK: [[ARRAY_DESTROY_BODY2]]: + // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %1, %cleanup ], [ %arraydestroy.element, %[[ARRAY_DESTROY_BODY2]] ] + // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %arrayinit.begin + // CHECK-NEXT: br i1 %arraydestroy.done, label %[[ARRAY_DESTROY_DONE2]], label %[[ARRAY_DESTROY_BODY2]] + + // CHECK: [[ARRAY_DESTROY_DONE2]]: + // CHECK-NEXT: br label %[[ARRAY_DESTROY_DONE1]] +} + +void ArraySubobjects() { + struct S { + Printy arr1[2]; + Printy arr2[2]; + Printy p; + }; + // CHECK-LABEL: define dso_local void @_Z15ArraySubobjectsv() + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + S s{{Printy("a"), Printy("b")}, + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: call void @_ZN6PrintyC1EPKc + {Printy("a"), + // CHECK: [[ARRAYINIT_BEGIN:%.+]] = getelementptr inbounds [2 x %struct.Printy] + // CHECK: store ptr [[ARRAYINIT_BEGIN]], ptr %arrayinit.endOfInit, align 8 + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: [[ARRAYINIT_ELEMENT:%.+]] = getelementptr inbounds %struct.Printy + // CHECK: store ptr [[ARRAYINIT_ELEMENT]], ptr %arrayinit.endOfInit, align 8 + ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: [[V0:%.+]] = load ptr, ptr %arrayinit.endOfInit, align 8 + // CHECK-NEXT: %arraydestroy.isempty = icmp eq ptr [[ARRAYINIT_BEGIN]], [[V0]] + // CHECK-NEXT: br i1 %arraydestroy.isempty, label %[[ARRAY_DESTROY_DONE:.+]], label %[[ARRAY_DESTROY_BODY:.+]] + } + Printy("b"); + }) + }, + Printy("c") + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZZ15ArraySubobjectsvEN1SD1Ev + // CHECK-NEXT: br label %return + }; + // CHECK: return: + // CHECK-NEXT: ret void + + // CHECK: [[ARRAY_DESTROY_BODY]]: + // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %0, %if.then ], [ %arraydestroy.element, %[[ARRAY_DESTROY_BODY]] ] + // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, [[ARRAYINIT_BEGIN]] + // CHECK-NEXT: br i1 %arraydestroy.done, label %[[ARRAY_DESTROY_DONE]], label %[[ARRAY_DESTROY_BODY]] + + // CHECK: [[ARRAY_DESTROY_DONE]] + // CHECK-NEXT: [[ARRAY_BEGIN:%.+]] = getelementptr inbounds [2 x %struct.Printy], ptr %arr1, i32 0, i32 0 + // CHECK-NEXT: [[V1:%.+]] = getelementptr inbounds %struct.Printy, ptr [[ARRAY_BEGIN]], i64 2 + // CHECK-NEXT: br label %[[ARRAY_DESTROY_BODY2:.+]] + + // CHECK: [[ARRAY_DESTROY_BODY2]]: + // CHECK-NEXT: %arraydestroy.elementPast5 = phi ptr [ %1, %[[ARRAY_DESTROY_DONE]] ], [ %arraydestroy.element6, %[[ARRAY_DESTROY_BODY2]] ] + // CHECK-NEXT: %arraydestroy.element6 = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast5, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element6) + // CHECK-NEXT: %arraydestroy.done7 = icmp eq ptr %arraydestroy.element6, [[ARRAY_BEGIN]] + // CHECK-NEXT: br i1 %arraydestroy.done7, label %[[ARRAY_DESTROY_DONE2:.+]], label %[[ARRAY_DESTROY_BODY2]] + + + // CHECK: [[ARRAY_DESTROY_DONE2]]: + // CHECK-NEXT: br label %return +} + +void LambdaInit() { + // CHECK-LABEL: define dso_local void @_Z10LambdaInitv() + auto S = [a = Printy("a"), b = ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %return + } + Printy("b"); + })]() { return a; }; +} + +void LifetimeExtended() { + // CHECK-LABEL: define dso_local void @_Z16LifetimeExtendedv + struct PrintyRefBind { + const Printy &a; + const Printy &b; + }; + PrintyRefBind ps = {Printy("a"), ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %return + } + Printy("b"); + })}; +} + +void NewArrayInit() { + // CHECK-LABEL: define dso_local void @_Z12NewArrayInitv() + // CHECK: %array.init.end = alloca ptr, align 8 + // CHECK: store ptr %0, ptr %array.init.end, align 8 + Printy *array = new Printy[3]{ + "a", + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: store ptr %array.exp.next, ptr %array.init.end, align 8 + "b", + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: store ptr %array.exp.next1, ptr %array.init.end, align 8 + ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK: br i1 %arraydestroy.isempty, label %arraydestroy.done{{.*}}, label %arraydestroy.body + } + "b"; + // CHECK: if.end: + // CHECK: call void @_ZN6PrintyC1EPKc + })}; + // CHECK: arraydestroy.body: + // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %{{.*}}, %if.then ], [ %arraydestroy.element, %arraydestroy.body ] + // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %0 + // CHECK-NEXT: br i1 %arraydestroy.done, label %arraydestroy.done{{.*}}, label %arraydestroy.body + + // CHECK: arraydestroy.done{{.*}}: ; preds = %arraydestroy.body, %if.then + // CHECK-NEXT: br label %return +} + +void ArrayInitWithContinue() { + // CHECK-LABEL: @_Z21ArrayInitWithContinuev + // Verify that we start to emit the array destructor. + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + for (int i = 0; i < 1; ++i) { + Printy arr[2] = {"a", ({ + if (foo()) { + continue; + } + "b"; + })}; + } +} diff --git a/clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp b/clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp new file mode 100644 index 000000000000..06cc2069dbe9 --- /dev/null +++ b/clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp @@ -0,0 +1,93 @@ +// RUN: %clang_cc1 --std=c++20 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s + +#include "Inputs/coroutine.h" + +struct Printy { + Printy(const char *name) : name(name) {} + ~Printy() {} + const char *name; +}; + +struct coroutine { + struct promise_type; + std::coroutine_handle handle; + ~coroutine() { + if (handle) handle.destroy(); + } +}; + +struct coroutine::promise_type { + coroutine get_return_object() { + return {std::coroutine_handle::from_promise(*this)}; + } + std::suspend_never initial_suspend() noexcept { return {}; } + std::suspend_always final_suspend() noexcept { return {}; } + void return_void() {} + void unhandled_exception() {} +}; + +struct Awaiter : std::suspend_always { + Printy await_resume() { return {"awaited"}; } +}; + +int foo() { return 2; } + +coroutine ArrayInitCoro() { + // Verify that: + // - We do the necessary stores for array cleanups. + // - Array cleanups are called by await.cleanup. + // - We activate the cleanup after the first element and deactivate it in await.ready (see cleanup.isactive). + + // CHECK-LABEL: define dso_local void @_Z13ArrayInitCorov + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + // CHECK: %cleanup.isactive = alloca i1, align 1 + Printy arr[2] = { + Printy("a"), + // CHECK: %arrayinit.begin = getelementptr inbounds [2 x %struct.Printy], ptr %arr.reload.addr, i64 0, i64 0 + // CHECK-NEXT: %arrayinit.begin.spill.addr = getelementptr inbounds %_Z13ArrayInitCorov.Frame, ptr %0, i32 0, i32 10 + // CHECK-NEXT: store ptr %arrayinit.begin, ptr %arrayinit.begin.spill.addr, align 8 + // CHECK-NEXT: store i1 true, ptr %cleanup.isactive.reload.addr, align 1 + // CHECK-NEXT: store ptr %arrayinit.begin, ptr %arrayinit.endOfInit.reload.addr, align 8 + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc(ptr noundef nonnull align 8 dereferenceable(8) %arrayinit.begin, ptr noundef @.str) + // CHECK-NEXT: %arrayinit.element = getelementptr inbounds %struct.Printy, ptr %arrayinit.begin, i64 1 + // CHECK-NEXT: %arrayinit.element.spill.addr = getelementptr inbounds %_Z13ArrayInitCorov.Frame, ptr %0, i32 0, i32 11 + // CHECK-NEXT: store ptr %arrayinit.element, ptr %arrayinit.element.spill.addr, align 8 + // CHECK-NEXT: store ptr %arrayinit.element, ptr %arrayinit.endOfInit.reload.addr, align 8 + co_await Awaiter{} + // CHECK-NEXT: @_ZNSt14suspend_always11await_readyEv + // CHECK-NEXT: br i1 %{{.+}}, label %await.ready, label %CoroSave30 + }; + // CHECK: await.cleanup: ; preds = %AfterCoroSuspend{{.*}} + // CHECK-NEXT: br label %cleanup{{.*}}.from.await.cleanup + + // CHECK: cleanup{{.*}}.from.await.cleanup: ; preds = %await.cleanup + // CHECK: br label %cleanup{{.*}} + + // CHECK: await.ready: + // CHECK-NEXT: %arrayinit.element.reload.addr = getelementptr inbounds %_Z13ArrayInitCorov.Frame, ptr %0, i32 0, i32 11 + // CHECK-NEXT: %arrayinit.element.reload = load ptr, ptr %arrayinit.element.reload.addr, align 8 + // CHECK-NEXT: call void @_ZN7Awaiter12await_resumeEv + // CHECK-NEXT: store i1 false, ptr %cleanup.isactive.reload.addr, align 1 + // CHECK-NEXT: br label %cleanup{{.*}}.from.await.ready + + // CHECK: cleanup{{.*}}: ; preds = %cleanup{{.*}}.from.await.ready, %cleanup{{.*}}.from.await.cleanup + // CHECK: %cleanup.is_active = load i1, ptr %cleanup.isactive.reload.addr, align 1 + // CHECK-NEXT: br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done + + // CHECK: cleanup.action: + // CHECK: %arraydestroy.isempty = icmp eq ptr %arrayinit.begin.reload{{.*}}, %{{.*}} + // CHECK-NEXT: br i1 %arraydestroy.isempty, label %arraydestroy.done{{.*}}, label %arraydestroy.body.from.cleanup.action + // Ignore rest of the array cleanup. +} + +coroutine ArrayInitWithCoReturn() { + // CHECK-LABEL: define dso_local void @_Z21ArrayInitWithCoReturnv + // Verify that we start to emit the array destructor. + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + Printy arr[2] = {"a", ({ + if (foo()) { + co_return; + } + "b"; + })}; +} -- GitLab From a0651db490328a972185e44ff637970b3456406b Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Wed, 10 Apr 2024 19:23:32 +0800 Subject: [PATCH 385/695] [clang][Sema] Avoid guessing unexpanded packs' size in getFullyPackExpandedSize (#87768) There has been an optimization for `SizeOfPackExprs` since c5452ed9, in which we overlooked a case where the template arguments were not yet formed into a `PackExpansionType` at the token annotation stage. This led to a problem in that a template involving such expressions may lose its nature of being dependent, causing some false-positive diagnostics. Fixes https://github.com/llvm/llvm-project/issues/84220 --- clang/docs/ReleaseNotes.rst | 1 + clang/lib/Sema/SemaTemplateVariadic.cpp | 11 ++++++++++ clang/test/SemaTemplate/alias-templates.cpp | 23 +++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index f96cebbde3d8..6bff80ed4d21 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -526,6 +526,7 @@ Bug Fixes to C++ Support - Fix crash when inheriting from a cv-qualified type. Fixes: (`#35603 `_) - Fix a crash when the using enum declaration uses an anonymous enumeration. Fixes (#GH86790). +- Handled an edge case in ``getFullyPackExpandedSize`` so that we now avoid a false-positive diagnostic. (#GH84220) - Clang now correctly tracks type dependence of by-value captures in lambdas with an explicit object parameter. Fixes (#GH70604), (#GH79754), (#GH84163), (#GH84425), (#GH86054), (#GH86398), and (#GH86399). diff --git a/clang/lib/Sema/SemaTemplateVariadic.cpp b/clang/lib/Sema/SemaTemplateVariadic.cpp index 903fbfd18e77..4909414c0c78 100644 --- a/clang/lib/Sema/SemaTemplateVariadic.cpp +++ b/clang/lib/Sema/SemaTemplateVariadic.cpp @@ -1243,6 +1243,17 @@ std::optional Sema::getFullyPackExpandedSize(TemplateArgument Arg) { // expanded this pack expansion into the enclosing pack if we could. if (Elem.isPackExpansion()) return std::nullopt; + // Don't guess the size of unexpanded packs. The pack within a template + // argument may have yet to be of a PackExpansion type before we see the + // ellipsis in the annotation stage. + // + // This doesn't mean we would invalidate the optimization: Arg can be an + // unexpanded pack regardless of Elem's dependence. For instance, + // A TemplateArgument that contains either a SubstTemplateTypeParmPackType + // or SubstNonTypeTemplateParmPackExpr is always considered Unexpanded, but + // the underlying TemplateArgument thereof may not. + if (Elem.containsUnexpandedParameterPack()) + return std::nullopt; } return Pack.pack_size(); } diff --git a/clang/test/SemaTemplate/alias-templates.cpp b/clang/test/SemaTemplate/alias-templates.cpp index 8d7cc6118610..ab5cad72faf1 100644 --- a/clang/test/SemaTemplate/alias-templates.cpp +++ b/clang/test/SemaTemplate/alias-templates.cpp @@ -236,6 +236,29 @@ namespace PR14858 { void test_q(int (&a)[5]) { Q().f(&a); } } +namespace PR84220 { + +template class list {}; + +template struct foo_impl { + template using f = int; +}; + +template +using foo = typename foo_impl::template f; + +// We call getFullyPackExpandedSize at the annotation stage +// before parsing the ellipsis next to the foo. This happens before +// a PackExpansionType is formed for foo. +// getFullyPackExpandedSize shouldn't determine the value here. Otherwise, +// foo_impl would lose its dependency despite the template +// arguments being unsubstituted. +template using test = list...>; + +test a; + +} + namespace redecl { template using A = int; template using A = int; -- GitLab From 8d206f51497fdf1ceebd6430b2f7d31ef735d0dc Mon Sep 17 00:00:00 2001 From: Edwin Vane Date: Wed, 10 Apr 2024 07:40:35 -0400 Subject: [PATCH 386/695] [clang-tidy] Allow renaming macro arguments (#87792) Although the identifier-naming.cpp lit test expected macro arguments not to be renamed, the code seemed to already allow it. The code was simply not being exercised because a SourceManager argument wasn't being provided. With this change, renaming of macro arguments that expand to renamable decls is permitted. --- .../utils/RenamerClangTidyCheck.cpp | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 2 +- .../readability/identifier-naming.cpp | 23 +++++++++++++++---- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp index 69b7d40ef628..ad8048e2a92b 100644 --- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp +++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp @@ -489,7 +489,7 @@ void RenamerClangTidyCheck::checkNamedDecl(const NamedDecl *Decl, } Failure.Info = std::move(Info); - addUsage(Decl, Range); + addUsage(Decl, Range, &SourceMgr); } void RenamerClangTidyCheck::check(const MatchFinder::MatchResult &Result) { diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index a7193e90c38d..b66be44e9f8a 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -268,7 +268,7 @@ Changes in existing checks ` check in `GetConfigPerFile` mode by resolving symbolic links to header files. Fixed handling of Hungarian Prefix when configured to `LowerCase`. Added support for renaming designated - initializers. + initializers. Added support for renaming macro arguments. - Improved :doc:`readability-implicit-bool-conversion ` check to provide diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp index 57ef4aae5ddb..99149fe86ace 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/identifier-naming.cpp @@ -108,10 +108,12 @@ USER_NS::object g_s2; // NO warnings or fixes expected as USER_NS and object are declared in a header file SYSTEM_MACRO(var1); -// NO warnings or fixes expected as var1 is from macro expansion +// CHECK-MESSAGES: :[[@LINE-1]]:14: warning: invalid case style for global variable 'var1' [readability-identifier-naming] +// CHECK-FIXES: {{^}}SYSTEM_MACRO(g_var1); USER_MACRO(var2); -// NO warnings or fixes expected as var2 is declared in a macro expansion +// CHECK-MESSAGES: :[[@LINE-1]]:12: warning: invalid case style for global variable 'var2' [readability-identifier-naming] +// CHECK-FIXES: {{^}}USER_MACRO(g_var2); #define BLA int FOO_bar BLA; @@ -602,9 +604,20 @@ static void static_Function() { // CHECK-FIXES: {{^}}#define MY_TEST_MACRO(X) X() void MY_TEST_Macro(function) {} -// CHECK-FIXES: {{^}}void MY_TEST_MACRO(function) {} -} -} +// CHECK-MESSAGES: :[[@LINE-1]]:20: warning: invalid case style for global function 'function' [readability-identifier-naming] +// CHECK-FIXES: {{^}}void MY_TEST_MACRO(Function) {} + +#define MY_CAT_IMPL(l, r) l ## r +#define MY_CAT(l, r) MY_CAT_IMPL(l, r) +#define MY_MACRO2(foo) int MY_CAT(awesome_, MY_CAT(foo, __COUNTER__)) = 0 +#define MY_MACRO3(foo) int MY_CAT(awesome_, foo) = 0 +MY_MACRO2(myglob); +MY_MACRO3(myglob); +// No suggestions should occur even though the resulting decl of awesome_myglob# +// or awesome_myglob are not entirely within a macro argument. + +} // namespace InlineNamespace +} // namespace FOO_NS template struct a { // CHECK-MESSAGES: :[[@LINE-1]]:32: warning: invalid case style for struct 'a' -- GitLab From f2ade91a9fe7c222ea919748d30b74397911ecc8 Mon Sep 17 00:00:00 2001 From: Jeff Niu Date: Wed, 10 Apr 2024 14:11:45 +0200 Subject: [PATCH 387/695] [mlir] Optimize getting properties on concrete ops (#88259) This makes retrieving properties on concrete operations faster by removing a branch when it is known that the operation must have properties. --- mlir/include/mlir/IR/OpDefinition.h | 2 +- mlir/include/mlir/IR/Operation.h | 9 +++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/mlir/include/mlir/IR/OpDefinition.h b/mlir/include/mlir/IR/OpDefinition.h index c177ae3594d1..2d1dee2303e8 100644 --- a/mlir/include/mlir/IR/OpDefinition.h +++ b/mlir/include/mlir/IR/OpDefinition.h @@ -1965,7 +1965,7 @@ public: if constexpr (!hasProperties()) return getEmptyProperties(); return *getOperation() - ->getPropertiesStorage() + ->getPropertiesStorageUnsafe() .template as *>(); } diff --git a/mlir/include/mlir/IR/Operation.h b/mlir/include/mlir/IR/Operation.h index 3ffd3517fe5a..c52a6fcac10c 100644 --- a/mlir/include/mlir/IR/Operation.h +++ b/mlir/include/mlir/IR/Operation.h @@ -895,8 +895,7 @@ public: /// Returns the properties storage. OpaqueProperties getPropertiesStorage() { if (propertiesStorageSize) - return { - reinterpret_cast(getTrailingObjects())}; + return getPropertiesStorageUnsafe(); return {nullptr}; } OpaqueProperties getPropertiesStorage() const { @@ -905,6 +904,12 @@ public: getTrailingObjects()))}; return {nullptr}; } + /// Returns the properties storage without checking whether properties are + /// present. + OpaqueProperties getPropertiesStorageUnsafe() { + return { + reinterpret_cast(getTrailingObjects())}; + } /// Return the properties converted to an attribute. /// This is expensive, and mostly useful when dealing with unregistered -- GitLab From 94ed57dab64ccb248a342a91957f390209c5c7ce Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 10 Apr 2024 13:30:29 +0100 Subject: [PATCH 388/695] [PhaseOrdering] Add test for #85551. Add test for missed hoisting of checks from std::span https://github.com/llvm/llvm-project/issues/85551 --- .../AArch64/hoist-runtime-checks.ll | 143 ++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll index c6c9a52167d5..a140e17a0dd1 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll @@ -91,8 +91,151 @@ for.end: ; preds = %for.cond.cleanup ret i32 %9 } +%"class.std::__1::span" = type { ptr, i64 } +%"class.std::__1::__wrap_iter" = type { ptr } + +define dso_local noundef i32 @sum_prefix_with_sum(ptr %s.coerce0, i64 %s.coerce1, i64 noundef %n) { +; CHECK-LABEL: define dso_local noundef i32 @sum_prefix_with_sum( +; CHECK-SAME: ptr nocapture readonly [[S_COERCE0:%.*]], i64 [[S_COERCE1:%.*]], i64 noundef [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP5_NOT:%.*]] = icmp eq i64 [[N]], 0 +; CHECK-NEXT: br i1 [[CMP5_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]] +; CHECK: for.body.preheader: +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1 +; CHECK-NEXT: [[DOTNOT_NOT:%.*]] = icmp ult i64 [[TMP0]], [[S_COERCE1]] +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: [[RET_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[SPAN_CHECKED_ACCESS_EXIT:%.*]] ] +; CHECK-NEXT: ret i32 [[RET_0_LCSSA]] +; CHECK: for.body: +; CHECK-NEXT: [[I_07:%.*]] = phi i64 [ [[INC:%.*]], [[SPAN_CHECKED_ACCESS_EXIT]] ], [ 0, [[FOR_BODY_PREHEADER]] ] +; CHECK-NEXT: [[RET_06:%.*]] = phi i32 [ [[ADD]], [[SPAN_CHECKED_ACCESS_EXIT]] ], [ 0, [[FOR_BODY_PREHEADER]] ] +; CHECK-NEXT: br i1 [[DOTNOT_NOT]], label [[SPAN_CHECKED_ACCESS_EXIT]], label [[COND_FALSE_I:%.*]], !prof [[PROF0:![0-9]+]] +; CHECK: cond.false.i: +; CHECK-NEXT: tail call void @llvm.trap() +; CHECK-NEXT: unreachable +; CHECK: span_checked_access.exit: +; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds i32, ptr [[S_COERCE0]], i64 [[I_07]] +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_I]], align 4 +; CHECK-NEXT: [[ADD]] = add nsw i32 [[TMP7]], [[RET_06]] +; CHECK-NEXT: [[INC]] = add nuw i64 [[I_07]], 1 +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] +; +entry: + %s = alloca %"class.std::__1::span", align 8 + %n.addr = alloca i64, align 8 + %ret = alloca i32, align 4 + %i = alloca i64, align 8 + %0 = getelementptr inbounds { ptr, i64 }, ptr %s, i32 0, i32 0 + store ptr %s.coerce0, ptr %0, align 8 + %1 = getelementptr inbounds { ptr, i64 }, ptr %s, i32 0, i32 1 + store i64 %s.coerce1, ptr %1, align 8 + store i64 %n, ptr %n.addr, align 8 + call void @llvm.lifetime.start.p0(i64 4, ptr %ret) #7 + store i32 0, ptr %ret, align 4 + call void @llvm.lifetime.start.p0(i64 8, ptr %i) #7 + store i64 0, ptr %i, align 8 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %2 = load i64, ptr %i, align 8 + %3 = load i64, ptr %n.addr, align 8 + %cmp = icmp ult i64 %2, %3 + br i1 %cmp, label %for.body, label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond + call void @llvm.lifetime.end.p0(i64 8, ptr %i) #7 + br label %for.end + +for.body: ; preds = %for.cond + %4 = load i64, ptr %i, align 8 + %call = call noundef nonnull align 4 dereferenceable(4) ptr @span_checked_access(ptr noundef nonnull align 8 dereferenceable(16) %s, i64 noundef %4) #7 + %5 = load i32, ptr %call, align 4 + %6 = load i32, ptr %ret, align 4 + %add = add nsw i32 %6, %5 + store i32 %add, ptr %ret, align 4 + br label %for.inc + +for.inc: ; preds = %for.body + %7 = load i64, ptr %i, align 8 + %inc = add i64 %7, 1 + store i64 %inc, ptr %i, align 8 + br label %for.cond + +for.end: ; preds = %for.cond.cleanup + %8 = load i32, ptr %ret, align 4 + call void @llvm.lifetime.end.p0(i64 4, ptr %ret) + ret i32 %8 +} + +define hidden noundef nonnull align 4 dereferenceable(4) ptr @span_checked_access(ptr noundef nonnull align 8 dereferenceable(16) %this, i64 noundef %__idx) { +; CHECK-LABEL: define hidden noundef nonnull align 4 dereferenceable(4) ptr @span_checked_access( +; CHECK-SAME: ptr nocapture noundef nonnull readonly align 8 dereferenceable(16) [[THIS:%.*]], i64 noundef [[__IDX:%.*]]) local_unnamed_addr #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[__SIZE__I:%.*]] = getelementptr inbounds i8, ptr [[THIS]], i64 8 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[__SIZE__I]], align 8 +; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP0]], [[__IDX]] +; CHECK-NEXT: br i1 [[CMP]], label [[COND_END:%.*]], label [[COND_FALSE:%.*]], !prof [[PROF0]] +; CHECK: cond.false: +; CHECK-NEXT: tail call void @llvm.trap() +; CHECK-NEXT: unreachable +; CHECK: cond.end: +; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[THIS]], align 8 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[__IDX]] +; CHECK-NEXT: ret ptr [[ARRAYIDX]] +; +entry: + %this.addr = alloca ptr, align 8 + %__idx.addr = alloca i64, align 8 + store ptr %this, ptr %this.addr, align 8 + store i64 %__idx, ptr %__idx.addr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 + %0 = load i64, ptr %__idx.addr, align 8 + %call = call noundef i64 @span_access(ptr noundef nonnull align 8 dereferenceable(16) %this1) + %cmp = icmp ult i64 %0, %call + %conv = zext i1 %cmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + br label %cond.end + +cond.false: ; preds = %entry + call void @llvm.trap() + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %__data_ = getelementptr inbounds %"class.std::__1::span", ptr %this1, i32 0, i32 0 + %1 = load ptr, ptr %__data_, align 8 + %2 = load i64, ptr %__idx.addr, align 8 + %arrayidx = getelementptr inbounds i32, ptr %1, i64 %2 + ret ptr %arrayidx +} + +define hidden noundef i64 @span_access(ptr noundef nonnull align 8 dereferenceable(16) %this) { +; CHECK-LABEL: define hidden noundef i64 @span_access( +; CHECK-SAME: ptr nocapture noundef nonnull readonly align 8 dereferenceable(16) [[THIS:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[__SIZE_:%.*]] = getelementptr inbounds i8, ptr [[THIS]], i64 8 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[__SIZE_]], align 8 +; CHECK-NEXT: ret i64 [[TMP0]] +; +entry: + %this.addr = alloca ptr, align 8 + store ptr %this, ptr %this.addr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 + %__size_ = getelementptr inbounds %"class.std::__1::span", ptr %this1, i32 0, i32 1 + %0 = load i64, ptr %__size_, align 8 + ret i64 %0 +} + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) declare void @llvm.trap() declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 2000, i32 1} +;. -- GitLab From a2bdbc6f0da2a9d0cecb23c64bd20423b3fd0340 Mon Sep 17 00:00:00 2001 From: Jacek Caban Date: Wed, 10 Apr 2024 14:37:18 +0200 Subject: [PATCH 389/695] [LLD][COFF] Check machine types in ICF::equalsConstant. (#88140) Avoid replacing replacing a chunk with one from a different type. It's mostly a concern for ARM64X, where we don't want to merge aarch64 and arm64ec chunks, but it may also in theory happen between arm64ec and x86_64 chunks. --- lld/COFF/ICF.cpp | 2 +- lld/test/COFF/arm64x-icf.s | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 lld/test/COFF/arm64x-icf.s diff --git a/lld/COFF/ICF.cpp b/lld/COFF/ICF.cpp index 013ffcfb3d5d..b899a2532423 100644 --- a/lld/COFF/ICF.cpp +++ b/lld/COFF/ICF.cpp @@ -178,7 +178,7 @@ bool ICF::equalsConstant(const SectionChunk *a, const SectionChunk *b) { a->getSectionName() == b->getSectionName() && a->header->SizeOfRawData == b->header->SizeOfRawData && a->checksum == b->checksum && a->getContents() == b->getContents() && - assocEquals(a, b); + a->getMachine() == b->getMachine() && assocEquals(a, b); } // Compare "moving" part of two sections, namely relocation targets. diff --git a/lld/test/COFF/arm64x-icf.s b/lld/test/COFF/arm64x-icf.s new file mode 100644 index 000000000000..c8df21d3e496 --- /dev/null +++ b/lld/test/COFF/arm64x-icf.s @@ -0,0 +1,37 @@ +// REQUIRES: aarch64 +// RUN: split-file %s %t.dir && cd %t.dir + +// RUN: llvm-mc -filetype=obj -triple=arm64ec-windows func-arm64ec.s -o func-arm64ec.obj +// RUN: llvm-mc -filetype=obj -triple=aarch64-windows func-arm64.s -o func-arm64.obj +// RUN: lld-link -machine:arm64x -dll -noentry -out:out.dll func-arm64ec.obj func-arm64.obj +// RUN: llvm-objdump -d out.dll | FileCheck %s + +// CHECK: 0000000180001000 <.text>: +// CHECK-NEXT: 180001000: 52800020 mov w0, #0x1 // =1 +// CHECK-NEXT: 180001004: d65f03c0 ret +// CHECK-NEXT: ... +// CHECK-NEXT: 180002000: 52800020 mov w0, #0x1 // =1 +// CHECK-NEXT: 180002004: d65f03c0 ret + + +#--- func-arm64.s + .section .text,"xr",discard,func + .globl func + .p2align 2 +func: + mov w0, #1 + ret + + .data + .rva func + +#--- func-arm64ec.s + .section .text,"xr",discard,"#func" + .globl "#func" + .p2align 2 +"#func": + mov w0, #1 + ret + + .data + .rva "#func" -- GitLab From b47e439559ad03a1b32614f573aad66f145a634d Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Wed, 10 Apr 2024 08:38:49 -0400 Subject: [PATCH 390/695] Revert "[Clang][Sema] Fix crash when 'this' is used in a dependent class scope function template specialization that instantiates to a static member function" (#88264) Reverts llvm/llvm-project#87541 --- clang/docs/ReleaseNotes.rst | 2 - clang/include/clang/Sema/Sema.h | 8 +--- clang/lib/Sema/SemaExpr.cpp | 5 +-- clang/lib/Sema/SemaExprCXX.cpp | 44 ++++++------------- clang/lib/Sema/SemaExprMember.cpp | 42 +++++------------- .../lib/Sema/SemaTemplateInstantiateDecl.cpp | 8 ---- clang/lib/Sema/TreeTransform.h | 7 ++- ...ms-function-specialization-class-scope.cpp | 44 ++----------------- 8 files changed, 36 insertions(+), 124 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 6bff80ed4d21..f5359afe1f09 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -520,8 +520,6 @@ Bug Fixes to C++ Support - Fix an issue caused by not handling invalid cases when substituting into the parameter mapping of a constraint. Fixes (#GH86757). - Fixed a bug that prevented member function templates of class templates declared with a deduced return type from being explicitly specialized for a given implicit instantiation of the class template. -- Fixed a crash when ``this`` is used in a dependent class scope function template specialization - that instantiates to a static member function. - Fix crash when inheriting from a cv-qualified type. Fixes: (`#35603 `_) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index f311f9f37434..9769d3690066 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -5439,8 +5439,7 @@ public: ExprResult BuildDeclarationNameExpr(const CXXScopeSpec &SS, LookupResult &R, bool NeedsADL, - bool AcceptInvalidDecl = false, - bool NeedUnresolved = false); + bool AcceptInvalidDecl = false); ExprResult BuildDeclarationNameExpr( const CXXScopeSpec &SS, const DeclarationNameInfo &NameInfo, NamedDecl *D, NamedDecl *FoundD = nullptr, @@ -6592,10 +6591,7 @@ public: SourceLocation RParenLoc); //// ActOnCXXThis - Parse 'this' pointer. - ExprResult ActOnCXXThis(SourceLocation Loc); - - /// Check whether the type of 'this' is valid in the current context. - bool CheckCXXThisType(SourceLocation Loc, QualType Type); + ExprResult ActOnCXXThis(SourceLocation loc); /// Build a CXXThisExpr and mark it referenced in the current context. Expr *BuildCXXThisExpr(SourceLocation Loc, QualType Type, bool IsImplicit); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 45acbf197ea6..594c11788f4e 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -3442,11 +3442,10 @@ static bool ShouldLookupResultBeMultiVersionOverload(const LookupResult &R) { ExprResult Sema::BuildDeclarationNameExpr(const CXXScopeSpec &SS, LookupResult &R, bool NeedsADL, - bool AcceptInvalidDecl, - bool NeedUnresolved) { + bool AcceptInvalidDecl) { // If this is a single, fully-resolved result and we don't need ADL, // just build an ordinary singleton decl ref. - if (!NeedUnresolved && !NeedsADL && R.isSingleResult() && + if (!NeedsADL && R.isSingleResult() && !R.getAsSingle() && !ShouldLookupResultBeMultiVersionOverload(R)) return BuildDeclarationNameExpr(SS, R.getLookupNameInfo(), R.getFoundDecl(), diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 9822477260e5..7b9b8f149d9e 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -1415,42 +1415,26 @@ bool Sema::CheckCXXThisCapture(SourceLocation Loc, const bool Explicit, } ExprResult Sema::ActOnCXXThis(SourceLocation Loc) { - // C++20 [expr.prim.this]p1: - // The keyword this names a pointer to the object for which an - // implicit object member function is invoked or a non-static - // data member's initializer is evaluated. + /// C++ 9.3.2: In the body of a non-static member function, the keyword this + /// is a non-lvalue expression whose value is the address of the object for + /// which the function is called. QualType ThisTy = getCurrentThisType(); - if (CheckCXXThisType(Loc, ThisTy)) - return ExprError(); + if (ThisTy.isNull()) { + DeclContext *DC = getFunctionLevelDeclContext(); - return BuildCXXThisExpr(Loc, ThisTy, /*IsImplicit=*/false); -} + if (const auto *Method = dyn_cast(DC); + Method && Method->isExplicitObjectMemberFunction()) { + return Diag(Loc, diag::err_invalid_this_use) << 1; + } -bool Sema::CheckCXXThisType(SourceLocation Loc, QualType Type) { - if (!Type.isNull()) - return false; + if (isLambdaCallWithExplicitObjectParameter(CurContext)) + return Diag(Loc, diag::err_invalid_this_use) << 1; - // C++20 [expr.prim.this]p3: - // If a declaration declares a member function or member function template - // of a class X, the expression this is a prvalue of type - // "pointer to cv-qualifier-seq X" wherever X is the current class between - // the optional cv-qualifier-seq and the end of the function-definition, - // member-declarator, or declarator. It shall not appear within the - // declaration of either a static member function or an explicit object - // member function of the current class (although its type and value - // category are defined within such member functions as they are within - // an implicit object member function). - DeclContext *DC = getFunctionLevelDeclContext(); - if (const auto *Method = dyn_cast(DC); - Method && Method->isExplicitObjectMemberFunction()) { - Diag(Loc, diag::err_invalid_this_use) << 1; - } else if (isLambdaCallWithExplicitObjectParameter(CurContext)) { - Diag(Loc, diag::err_invalid_this_use) << 1; - } else { - Diag(Loc, diag::err_invalid_this_use) << 0; + return Diag(Loc, diag::err_invalid_this_use) << 0; } - return true; + + return BuildCXXThisExpr(Loc, ThisTy, /*IsImplicit=*/false); } Expr *Sema::BuildCXXThisExpr(SourceLocation Loc, QualType Type, diff --git a/clang/lib/Sema/SemaExprMember.cpp b/clang/lib/Sema/SemaExprMember.cpp index 8cd2288d279c..32998ae60eaf 100644 --- a/clang/lib/Sema/SemaExprMember.cpp +++ b/clang/lib/Sema/SemaExprMember.cpp @@ -61,10 +61,6 @@ enum IMAKind { /// The reference is a contextually-permitted abstract member reference. IMA_Abstract, - /// Whether the context is static is dependent on the enclosing template (i.e. - /// in a dependent class scope explicit specialization). - IMA_Dependent, - /// The reference may be to an unresolved using declaration and the /// context is not an instance method. IMA_Unresolved_StaticOrExplicitContext, @@ -95,18 +91,10 @@ static IMAKind ClassifyImplicitMemberAccess(Sema &SemaRef, DeclContext *DC = SemaRef.getFunctionLevelDeclContext(); - bool couldInstantiateToStatic = false; - bool isStaticOrExplicitContext = SemaRef.CXXThisTypeOverride.isNull(); - - if (auto *MD = dyn_cast(DC)) { - if (MD->isImplicitObjectMemberFunction()) { - isStaticOrExplicitContext = false; - // A dependent class scope function template explicit specialization - // that is neither declared 'static' nor with an explicit object - // parameter could instantiate to a static or non-static member function. - couldInstantiateToStatic = MD->getDependentSpecializationInfo(); - } - } + bool isStaticOrExplicitContext = + SemaRef.CXXThisTypeOverride.isNull() && + (!isa(DC) || cast(DC)->isStatic() || + cast(DC)->isExplicitObjectMemberFunction()); if (R.isUnresolvableResult()) return isStaticOrExplicitContext ? IMA_Unresolved_StaticOrExplicitContext @@ -135,9 +123,6 @@ static IMAKind ClassifyImplicitMemberAccess(Sema &SemaRef, if (Classes.empty()) return IMA_Static; - if (couldInstantiateToStatic) - return IMA_Dependent; - // C++11 [expr.prim.general]p12: // An id-expression that denotes a non-static data member or non-static // member function of a class can only be used: @@ -283,30 +268,27 @@ ExprResult Sema::BuildPossibleImplicitMemberExpr( const CXXScopeSpec &SS, SourceLocation TemplateKWLoc, LookupResult &R, const TemplateArgumentListInfo *TemplateArgs, const Scope *S, UnresolvedLookupExpr *AsULE) { - switch (IMAKind Classification = ClassifyImplicitMemberAccess(*this, R)) { + switch (ClassifyImplicitMemberAccess(*this, R)) { case IMA_Instance: + return BuildImplicitMemberExpr(SS, TemplateKWLoc, R, TemplateArgs, true, S); + case IMA_Mixed: case IMA_Mixed_Unrelated: case IMA_Unresolved: - return BuildImplicitMemberExpr( - SS, TemplateKWLoc, R, TemplateArgs, - /*IsKnownInstance=*/Classification == IMA_Instance, S); + return BuildImplicitMemberExpr(SS, TemplateKWLoc, R, TemplateArgs, false, + S); + case IMA_Field_Uneval_Context: Diag(R.getNameLoc(), diag::warn_cxx98_compat_non_static_member_use) << R.getLookupNameInfo().getName(); [[fallthrough]]; case IMA_Static: case IMA_Abstract: - case IMA_Dependent: case IMA_Mixed_StaticOrExplicitContext: case IMA_Unresolved_StaticOrExplicitContext: if (TemplateArgs || TemplateKWLoc.isValid()) - return BuildTemplateIdExpr(SS, TemplateKWLoc, R, /*RequiresADL=*/false, - TemplateArgs); - return AsULE ? AsULE - : BuildDeclarationNameExpr( - SS, R, /*NeedsADL=*/false, /*AcceptInvalidDecl=*/false, - /*NeedUnresolved=*/Classification == IMA_Dependent); + return BuildTemplateIdExpr(SS, TemplateKWLoc, R, false, TemplateArgs); + return AsULE ? AsULE : BuildDeclarationNameExpr(SS, R, false); case IMA_Error_StaticOrExplicitContext: case IMA_Error_Unrelated: diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp index 8248b10814fe..127a432367b9 100644 --- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp @@ -5093,14 +5093,6 @@ void Sema::InstantiateFunctionDefinition(SourceLocation PointOfInstantiation, EnterExpressionEvaluationContext EvalContext( *this, Sema::ExpressionEvaluationContext::PotentiallyEvaluated); - Qualifiers ThisTypeQuals; - CXXRecordDecl *ThisContext = nullptr; - if (CXXMethodDecl *Method = dyn_cast(Function)) { - ThisContext = Method->getParent(); - ThisTypeQuals = Method->getMethodQualifiers(); - } - CXXThisScopeRAII ThisScope(*this, ThisContext, ThisTypeQuals); - // Introduce a new scope where local variable instantiations will be // recorded, unless we're actually a member function within a local // class, in which case we need to merge our results with the parent diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 13d7b00430d5..d4d2fa61d65e 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -3307,13 +3307,12 @@ public: /// Build a new C++ "this" expression. /// - /// By default, performs semantic analysis to build a new "this" expression. - /// Subclasses may override this routine to provide different behavior. + /// By default, builds a new "this" expression without performing any + /// semantic analysis. Subclasses may override this routine to provide + /// different behavior. ExprResult RebuildCXXThisExpr(SourceLocation ThisLoc, QualType ThisType, bool isImplicit) { - if (getSema().CheckCXXThisType(ThisLoc, ThisType)) - return ExprError(); return getSema().BuildCXXThisExpr(ThisLoc, ThisType, isImplicit); } diff --git a/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp b/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp index 6977623a0816..dcab9bfaeabc 100644 --- a/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp +++ b/clang/test/SemaTemplate/ms-function-specialization-class-scope.cpp @@ -1,6 +1,7 @@ -// RUN: %clang_cc1 -fms-extensions -fsyntax-only -Wno-unused-value -verify %s -// RUN: %clang_cc1 -fms-extensions -fdelayed-template-parsing -fsyntax-only -Wno-unused-value -verify %s +// RUN: %clang_cc1 -fms-extensions -fsyntax-only -verify %s +// RUN: %clang_cc1 -fms-extensions -fdelayed-template-parsing -fsyntax-only -verify %s +// expected-no-diagnostics class A { public: template A(U p) {} @@ -75,42 +76,3 @@ struct S { int f<0>(int); }; } - -namespace UsesThis { - template - struct A { - int x; - - template - static void f(); - - template<> - void f() { - this->x; // expected-error {{invalid use of 'this' outside of a non-static member function}} - x; // expected-error {{invalid use of member 'x' in static member function}} - A::x; // expected-error {{invalid use of member 'x' in static member function}} - +x; // expected-error {{invalid use of member 'x' in static member function}} - +A::x; // expected-error {{invalid use of member 'x' in static member function}} - } - - template - void g(); - - template<> - void g() { - this->x; - x; - A::x; - +x; - +A::x; - } - - template - static auto h() -> A*; - - template<> - auto h() -> decltype(this); // expected-error {{'this' cannot be used in a static member function declaration}} - }; - - template struct A; // expected-note 2{{in instantiation of}} -} -- GitLab From 1ca01958310f2956abd72ece1652c3218bcf27e1 Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Wed, 10 Apr 2024 08:41:22 -0400 Subject: [PATCH 391/695] [Clang][AST][NFC] Fix printing of dependent PackIndexTypes (#88146) Dependent `PackIndexType`s currently print the memory address of the index `Expr*` rather than pretty printing the expression. This patch fixes that. --- clang/lib/AST/TypePrinter.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp index 075c8aba11fc..9602f448e942 100644 --- a/clang/lib/AST/TypePrinter.cpp +++ b/clang/lib/AST/TypePrinter.cpp @@ -1213,10 +1213,13 @@ void TypePrinter::printDecltypeBefore(const DecltypeType *T, raw_ostream &OS) { void TypePrinter::printPackIndexingBefore(const PackIndexingType *T, raw_ostream &OS) { - if (T->hasSelectedType()) + if (T->hasSelectedType()) { OS << T->getSelectedType(); - else - OS << T->getPattern() << "...[" << T->getIndexExpr() << "]"; + } else { + OS << T->getPattern() << "...["; + T->getIndexExpr()->printPretty(OS, nullptr, Policy); + OS << "]"; + } spaceBeforePlaceHolder(OS); } -- GitLab From 49ef12a08c4c7d7ae4765929e72fe2320a12b08c Mon Sep 17 00:00:00 2001 From: Johannes Reifferscheid Date: Wed, 10 Apr 2024 14:55:56 +0200 Subject: [PATCH 392/695] Fix complex log1p accuracy with large abs values. (#88260) This ports https://github.com/openxla/xla/pull/10503 by @pearu. The new implementation matches mpmath's results for most inputs, see caveats in the linked pull request. In addition to the filecheck test here, the accuracy was tested with XLA's complex_unary_op_test and its MLIR emitters. --- .../ComplexToStandard/ComplexToStandard.cpp | 50 ++++++++++--------- .../convert-to-standard.mlir | 48 +++++++++++------- 2 files changed, 57 insertions(+), 41 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 9c3c4d96a301..0aa1de5fa5d9 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -570,37 +570,39 @@ struct Log1pOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { auto type = cast(adaptor.getComplex().getType()); auto elementType = cast(type.getElementType()); - arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); + arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); mlir::ImplicitLocOpBuilder b(op.getLoc(), rewriter); - Value real = b.create(elementType, adaptor.getComplex()); - Value imag = b.create(elementType, adaptor.getComplex()); + Value real = b.create(adaptor.getComplex()); + Value imag = b.create(adaptor.getComplex()); Value half = b.create(elementType, b.getFloatAttr(elementType, 0.5)); Value one = b.create(elementType, b.getFloatAttr(elementType, 1)); - Value two = b.create(elementType, - b.getFloatAttr(elementType, 2)); - - // log1p(a+bi) = .5*log((a+1)^2+b^2) + i*atan2(b, a + 1) - // log((a+1)+bi) = .5*log(a*a + 2*a + 1 + b*b) + i*atan2(b, a+1) - // log((a+1)+bi) = .5*log1p(a*a + 2*a + b*b) + i*atan2(b, a+1) - Value sumSq = b.create(real, real, fmf.getValue()); - sumSq = b.create( - sumSq, b.create(real, two, fmf.getValue()), - fmf.getValue()); - sumSq = b.create( - sumSq, b.create(imag, imag, fmf.getValue()), - fmf.getValue()); - Value logSumSq = - b.create(elementType, sumSq, fmf.getValue()); - Value resultReal = b.create(logSumSq, half, fmf.getValue()); - - Value realPlusOne = b.create(real, one, fmf.getValue()); - - Value resultImag = - b.create(elementType, imag, realPlusOne, fmf.getValue()); + Value realPlusOne = b.create(real, one, fmf); + Value absRealPlusOne = b.create(realPlusOne, fmf); + Value absImag = b.create(imag, fmf); + + Value maxAbs = b.create(absRealPlusOne, absImag, fmf); + Value minAbs = b.create(absRealPlusOne, absImag, fmf); + + Value maxAbsOfRealPlusOneAndImagMinusOne = b.create( + b.create(arith::CmpFPredicate::OGT, realPlusOne, absImag, + fmf), + real, b.create(maxAbs, one, fmf)); + Value minMaxRatio = b.create(minAbs, maxAbs, fmf); + Value logOfMaxAbsOfRealPlusOneAndImag = + b.create(maxAbsOfRealPlusOneAndImagMinusOne, fmf); + Value logOfSqrtPart = b.create( + b.create(minMaxRatio, minMaxRatio, fmf), fmf); + Value r = b.create( + b.create(half, logOfSqrtPart, fmf), + logOfMaxAbsOfRealPlusOneAndImag, fmf); + Value resultReal = b.create( + b.create(arith::CmpFPredicate::UNO, r, r, fmf), minAbs, + r); + Value resultImag = b.create(imag, realPlusOne, fmf); rewriter.replaceOpWithNewOp(op, type, resultReal, resultImag); return success(); diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index f5d9499eadda..43918904a09f 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -300,15 +300,22 @@ func.func @complex_log1p(%arg: complex) -> complex { // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32 -// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] : f32 -// CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] : f32 -// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] : f32 -// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] : f32 -// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] : f32 -// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] : f32 -// CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] : f32 // CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] : f32 +// CHECK: %[[ABS_REAL_PLUS_ONE:.*]] = math.absf %[[REAL_PLUS_ONE]] : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 +// CHECK: %[[CMPF:.*]] = arith.cmpf ogt, %[[REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MAX_MINUS_ONE:.*]] = arith.subf %[[MAX]], %cst_0 : f32 +// CHECK: %[[SELECT:.*]] = arith.select %[[CMPF]], %0, %[[MAX_MINUS_ONE]] : f32 +// CHECK: %[[MIN_MAX_RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[LOG_1:.*]] = math.log1p %[[SELECT]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[MIN_MAX_RATIO]], %[[MIN_MAX_RATIO]] : f32 +// CHECK: %[[LOG_SQ:.*]] = math.log1p %[[RATIO_SQ]] : f32 +// CHECK: %[[HALF_LOG_SQ:.*]] = arith.mulf %cst, %[[LOG_SQ]] : f32 +// CHECK: %[[R:.*]] = arith.addf %[[HALF_LOG_SQ]], %[[LOG_1]] : f32 +// CHECK: %[[ISNAN:.*]] = arith.cmpf uno, %[[R]], %[[R]] : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[ISNAN]], %[[MIN]], %[[R]] : f32 // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex @@ -963,15 +970,22 @@ func.func @complex_log1p_with_fmf(%arg: complex) -> complex { // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32 -// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] fastmath : f32 -// CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] fastmath : f32 -// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] fastmath : f32 -// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] fastmath : f32 -// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] fastmath : f32 -// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] fastmath : f32 -// CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] fastmath : f32 -// CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] fastmath : f32 +// CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] fastmath : f32 +// CHECK: %[[ABS_REAL_PLUS_ONE:.*]] = math.absf %[[REAL_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[CMPF:.*]] = arith.cmpf ogt, %[[REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MAX_MINUS_ONE:.*]] = arith.subf %[[MAX]], %cst_0 fastmath : f32 +// CHECK: %[[SELECT:.*]] = arith.select %[[CMPF]], %0, %[[MAX_MINUS_ONE]] : f32 +// CHECK: %[[MIN_MAX_RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[LOG_1:.*]] = math.log1p %[[SELECT]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[MIN_MAX_RATIO]], %[[MIN_MAX_RATIO]] fastmath : f32 +// CHECK: %[[LOG_SQ:.*]] = math.log1p %[[RATIO_SQ]] fastmath : f32 +// CHECK: %[[HALF_LOG_SQ:.*]] = arith.mulf %cst, %[[LOG_SQ]] fastmath : f32 +// CHECK: %[[R:.*]] = arith.addf %[[HALF_LOG_SQ]], %[[LOG_1]] fastmath : f32 +// CHECK: %[[ISNAN:.*]] = arith.cmpf uno, %[[R]], %[[R]] fastmath : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[ISNAN]], %[[MIN]], %[[R]] : f32 // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] fastmath : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex -- GitLab From 54a9f0007cb4f19d2e9df30405c5027229f5def0 Mon Sep 17 00:00:00 2001 From: annamthomas Date: Wed, 10 Apr 2024 09:02:23 -0400 Subject: [PATCH 393/695] [SCEV] Fix BinomialCoefficient Iteration to fit in W bits (#88010) BinomialCoefficient computes the value of W-bit IV at iteration It of a loop. When W is 1, we can call multiplicative inverse on 0 which triggers an assert since 1b76120. Since the arithmetic is supposed to wrap if It or K does not fit in W bits, do the truncation into W bits after we do the shift. Fixes #87798 --- llvm/lib/Analysis/ScalarEvolution.cpp | 6 +- llvm/test/Analysis/ScalarEvolution/pr87798.ll | 68 +++++++++++++++++++ 2 files changed, 70 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Analysis/ScalarEvolution/pr87798.ll diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp index e030b9fc7dac..9fcce797f559 100644 --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -928,11 +928,9 @@ static const SCEV *BinomialCoefficient(const SCEV *It, unsigned K, APInt OddFactorial(W, 1); unsigned T = 1; for (unsigned i = 3; i <= K; ++i) { - APInt Mult(W, i); - unsigned TwoFactors = Mult.countr_zero(); + unsigned TwoFactors = countr_zero(i); T += TwoFactors; - Mult.lshrInPlace(TwoFactors); - OddFactorial *= Mult; + OddFactorial *= (i >> TwoFactors); } // We need at least W + T bits for the multiplication step diff --git a/llvm/test/Analysis/ScalarEvolution/pr87798.ll b/llvm/test/Analysis/ScalarEvolution/pr87798.ll new file mode 100644 index 000000000000..acd445993e47 --- /dev/null +++ b/llvm/test/Analysis/ScalarEvolution/pr87798.ll @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -disable-output -passes='print' -verify-scev < %s 2>&1 | FileCheck %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2" +target triple = "x86_64-unknown-linux-gnu" + +; print is used to compute SCEVs for all values in the +; function. +; We should not crash on multiplicative inverse called within SCEV's binomial +; coefficient function. + +define i32 @pr87798() { +; CHECK-LABEL: 'pr87798' +; CHECK-NEXT: Classifying expressions for: @pr87798 +; CHECK-NEXT: %phi = phi i32 [ 0, %bb ], [ %add4, %bb1 ] +; CHECK-NEXT: --> {0,+,0,+,0,+,2,+,3}<%bb1> U: full-set S: full-set Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %phi2 = phi i32 [ 0, %bb ], [ %add, %bb1 ] +; CHECK-NEXT: --> {0,+,0,+,1}<%bb1> U: full-set S: full-set Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %phi3 = phi i32 [ 0, %bb ], [ %add5, %bb1 ] +; CHECK-NEXT: --> {0,+,1}<%bb1> U: [0,1) S: [0,1) Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %add = add i32 %phi2, %phi3 +; CHECK-NEXT: --> {0,+,1,+,1}<%bb1> U: full-set S: full-set Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %mul = mul i32 %phi2, %phi3 +; CHECK-NEXT: --> {0,+,0,+,2,+,3}<%bb1> U: full-set S: full-set Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %add4 = add i32 %mul, %phi +; CHECK-NEXT: --> {0,+,0,+,2,+,5,+,3}<%bb1> U: full-set S: full-set Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %and = and i32 %phi, 1 +; CHECK-NEXT: --> (zext i1 {false,+,false,+,false,+,false,+,true}<%bb1> to i32) U: [0,2) S: [0,2) Exits: 0 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %add5 = add i32 %phi3, 1 +; CHECK-NEXT: --> {1,+,1}<%bb1> U: [1,2) S: [1,2) Exits: 1 LoopDispositions: { %bb1: Computable } +; CHECK-NEXT: %phi9 = phi i32 [ %and, %bb1 ] +; CHECK-NEXT: --> (zext i1 {false,+,false,+,false,+,false,+,true}<%bb1> to i32) U: [0,2) S: [0,2) --> 0 U: [0,1) S: [0,1) +; CHECK-NEXT: %zext = zext i32 %phi9 to i64 +; CHECK-NEXT: --> poison U: full-set S: full-set +; CHECK-NEXT: Determining loop execution counts for: @pr87798 +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: Loop %bb1: backedge-taken count is i1 false +; CHECK-NEXT: Loop %bb1: constant max backedge-taken count is i1 false +; CHECK-NEXT: Loop %bb1: symbolic max backedge-taken count is i1 false +; CHECK-NEXT: Loop %bb1: Trip multiple is 1 +; +bb: + br label %bb1 + +bb1: ; preds = %bb1, %bb + %phi = phi i32 [ 0, %bb ], [ %add4, %bb1 ] + %phi2 = phi i32 [ 0, %bb ], [ %add, %bb1 ] + %phi3 = phi i32 [ 0, %bb ], [ %add5, %bb1 ] + %add = add i32 %phi2, %phi3 + %mul = mul i32 %phi2, %phi3 + %add4 = add i32 %mul, %phi + %and = and i32 %phi, 1 + %add5 = add i32 %phi3, 1 + br i1 true, label %preheader, label %bb1 + +preheader: ; preds = %bb1 + %phi9 = phi i32 [ %and, %bb1 ] + br label %loop + +loop: ; preds = %preheader, %loop + br label %loop + +bb7: ; No predecessors! + %zext = zext i32 %phi9 to i64 + ret i32 0 +} -- GitLab From 938a73422e0b964eba16f272acdfae1d0281772c Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 4 Apr 2024 13:30:57 -0700 Subject: [PATCH 394/695] [SLP][NFC]Walk over entries, not single values. Better to walk over SLP nodes rather than single values. Matching a value to a node is not a 1-to-1 relation, one value may be part of several nodes and compiler may get wrong node, when trying to map it. Currently there are no such issues detected, but they may appear in future. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 339 +++++++++--------- 1 file changed, 167 insertions(+), 172 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index c3dcf73b0b76..22ef9b5fb994 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -2325,19 +2325,17 @@ public: ~BoUpSLP(); private: - /// Determine if a vectorized value \p V in can be demoted to - /// a smaller type with a truncation. We collect the values that will be - /// demoted in ToDemote and additional roots that require investigating in - /// Roots. - /// \param DemotedConsts list of Instruction/OperandIndex pairs that are - /// constant and to be demoted. Required to correctly identify constant nodes - /// to be demoted. - bool collectValuesToDemote( - Value *V, bool IsProfitableToDemoteRoot, unsigned &BitWidth, - SmallVectorImpl &ToDemote, - DenseMap> &DemotedConsts, - DenseSet &Visited, unsigned &MaxDepthLevel, - bool &IsProfitableToDemote, bool IsTruncRoot) const; + /// Determine if a node \p E in can be demoted to a smaller type with a + /// truncation. We collect the entries that will be demoted in ToDemote. + /// \param E Node for analysis + /// \param ToDemote indices of the nodes to be demoted. + bool collectValuesToDemote(const TreeEntry &E, bool IsProfitableToDemoteRoot, + unsigned &BitWidth, + SmallVectorImpl &ToDemote, + DenseSet &Visited, + unsigned &MaxDepthLevel, + bool &IsProfitableToDemote, + bool IsTruncRoot) const; /// Check if the operands on the edges \p Edges of the \p UserTE allows /// reordering (i.e. the operands can be reordered because they have only one @@ -14126,20 +14124,17 @@ unsigned BoUpSLP::getVectorElementSize(Value *V) { return Width; } -// Determine if a value V in a vectorizable expression Expr can be demoted to a -// smaller type with a truncation. We collect the values that will be demoted -// in ToDemote and additional roots that require investigating in Roots. bool BoUpSLP::collectValuesToDemote( - Value *V, bool IsProfitableToDemoteRoot, unsigned &BitWidth, - SmallVectorImpl &ToDemote, - DenseMap> &DemotedConsts, - DenseSet &Visited, unsigned &MaxDepthLevel, - bool &IsProfitableToDemote, bool IsTruncRoot) const { + const TreeEntry &E, bool IsProfitableToDemoteRoot, unsigned &BitWidth, + SmallVectorImpl &ToDemote, DenseSet &Visited, + unsigned &MaxDepthLevel, bool &IsProfitableToDemote, + bool IsTruncRoot) const { // We can always demote constants. - if (isa(V)) + if (all_of(E.Scalars, IsaPred)) return true; - if (DL->getTypeSizeInBits(V->getType()) == BitWidth) { + unsigned OrigBitWidth = DL->getTypeSizeInBits(E.Scalars.front()->getType()); + if (OrigBitWidth == BitWidth) { MaxDepthLevel = 1; return true; } @@ -14150,7 +14145,6 @@ bool BoUpSLP::collectValuesToDemote( auto IsPotentiallyTruncated = [&](Value *V, unsigned &BitWidth) -> bool { if (MultiNodeScalars.contains(V)) return false; - uint32_t OrigBitWidth = DL->getTypeSizeInBits(V->getType()); if (OrigBitWidth > BitWidth) { APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); if (MaskedValueIsZero(V, Mask, SimplifyQuery(*DL))) @@ -14168,47 +14162,50 @@ bool BoUpSLP::collectValuesToDemote( BitWidth = std::max(BitWidth, BitWidth1); return BitWidth > 0 && OrigBitWidth >= (BitWidth * 2); }; - auto FinalAnalysis = [&](const TreeEntry *ITE = nullptr) { + using namespace std::placeholders; + auto FinalAnalysis = [&]() { if (!IsProfitableToDemote) return false; - return (ITE && ITE->UserTreeIndices.size() > 1) || - IsPotentiallyTruncated(V, BitWidth); + bool Res = all_of( + E.Scalars, std::bind(IsPotentiallyTruncated, _1, std::ref(BitWidth))); + // Gather demoted constant operands. + if (Res && E.State == TreeEntry::NeedToGather && + all_of(E.Scalars, IsaPred)) + ToDemote.push_back(E.Idx); + return Res; }; // TODO: improve handling of gathered values and others. - auto *I = dyn_cast(V); - const TreeEntry *ITE = I ? getTreeEntry(I) : nullptr; - if (!ITE || !Visited.insert(I).second || MultiNodeScalars.contains(I) || - all_of(I->users(), [&](User *U) { - return isa(U) && !getTreeEntry(U); + if (E.State == TreeEntry::NeedToGather || !Visited.insert(&E).second || + any_of(E.Scalars, [&](Value *V) { + return all_of(V->users(), [&](User *U) { + return isa(U) && !getTreeEntry(U); + }); })) return FinalAnalysis(); - if (!all_of(I->users(), - [=](User *U) { - return getTreeEntry(U) || - (UserIgnoreList && UserIgnoreList->contains(U)) || - (U->getType()->isSized() && - !U->getType()->isScalableTy() && - DL->getTypeSizeInBits(U->getType()) <= BitWidth); - }) && - !IsPotentiallyTruncated(I, BitWidth)) + if (any_of(E.Scalars, [&](Value *V) { + return !all_of(V->users(), [=](User *U) { + return getTreeEntry(U) || + (UserIgnoreList && UserIgnoreList->contains(U)) || + (U->getType()->isSized() && !U->getType()->isScalableTy() && + DL->getTypeSizeInBits(U->getType()) <= BitWidth); + }) && !IsPotentiallyTruncated(V, BitWidth); + })) return false; - unsigned Start = 0; - unsigned End = I->getNumOperands(); - - auto ProcessOperands = [&](ArrayRef Operands, bool &NeedToExit) { + auto ProcessOperands = [&](ArrayRef Operands, + bool &NeedToExit) { NeedToExit = false; unsigned InitLevel = MaxDepthLevel; - for (Value *IncValue : Operands) { + for (const TreeEntry *Op : Operands) { unsigned Level = InitLevel; - if (!collectValuesToDemote(IncValue, IsProfitableToDemoteRoot, BitWidth, - ToDemote, DemotedConsts, Visited, Level, - IsProfitableToDemote, IsTruncRoot)) { + if (!collectValuesToDemote(*Op, IsProfitableToDemoteRoot, BitWidth, + ToDemote, Visited, Level, IsProfitableToDemote, + IsTruncRoot)) { if (!IsProfitableToDemote) return false; NeedToExit = true; - if (!FinalAnalysis(ITE)) + if (!FinalAnalysis()) return false; continue; } @@ -14220,7 +14217,6 @@ bool BoUpSLP::collectValuesToDemote( [&](function_ref Checker, bool &NeedToExit) { // Try all bitwidth < OrigBitWidth. NeedToExit = false; - uint32_t OrigBitWidth = DL->getTypeSizeInBits(I->getType()); unsigned BestFailBitwidth = 0; for (; BitWidth < OrigBitWidth; BitWidth *= 2) { if (Checker(BitWidth, OrigBitWidth)) @@ -14241,18 +14237,20 @@ bool BoUpSLP::collectValuesToDemote( return false; }; auto TryProcessInstruction = - [&](Instruction *I, const TreeEntry &ITE, unsigned &BitWidth, - ArrayRef Operands = std::nullopt, + [&](unsigned &BitWidth, + ArrayRef Operands = std::nullopt, function_ref Checker = {}) { if (Operands.empty()) { if (!IsTruncRoot) MaxDepthLevel = 1; - (void)IsPotentiallyTruncated(V, BitWidth); + (void)for_each(E.Scalars, std::bind(IsPotentiallyTruncated, _1, + std::ref(BitWidth))); } else { // Several vectorized uses? Check if we can truncate it, otherwise - // exit. - if (ITE.UserTreeIndices.size() > 1 && - !IsPotentiallyTruncated(I, BitWidth)) + if (E.UserTreeIndices.size() > 1 && + !all_of(E.Scalars, std::bind(IsPotentiallyTruncated, _1, + std::ref(BitWidth)))) return false; bool NeedToExit = false; if (Checker && !AttemptCheckBitwidth(Checker, NeedToExit)) @@ -14266,26 +14264,22 @@ bool BoUpSLP::collectValuesToDemote( } ++MaxDepthLevel; - // Gather demoted constant operands. - for (unsigned Idx : seq(Start, End)) - if (isa(I->getOperand(Idx))) - DemotedConsts.try_emplace(I).first->getSecond().push_back(Idx); - // Record the value that we can demote. - ToDemote.push_back(V); + // Record the entry that we can demote. + ToDemote.push_back(E.Idx); return IsProfitableToDemote; }; - switch (I->getOpcode()) { + switch (E.getOpcode()) { // We can always demote truncations and extensions. Since truncations can // seed additional demotion, we save the truncated value. case Instruction::Trunc: if (IsProfitableToDemoteRoot) IsProfitableToDemote = true; - return TryProcessInstruction(I, *ITE, BitWidth); + return TryProcessInstruction(BitWidth); case Instruction::ZExt: case Instruction::SExt: IsProfitableToDemote = true; - return TryProcessInstruction(I, *ITE, BitWidth); + return TryProcessInstruction(BitWidth); // We can demote certain binary operations if we can demote both of their // operands. @@ -14295,112 +14289,128 @@ bool BoUpSLP::collectValuesToDemote( case Instruction::And: case Instruction::Or: case Instruction::Xor: { - return TryProcessInstruction(I, *ITE, BitWidth, - {I->getOperand(0), I->getOperand(1)}); + return TryProcessInstruction( + BitWidth, {getOperandEntry(&E, 0), getOperandEntry(&E, 1)}); } case Instruction::Shl: { // If we are truncating the result of this SHL, and if it's a shift of an // inrange amount, we can always perform a SHL in a smaller type. auto ShlChecker = [&](unsigned BitWidth, unsigned) { - KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL); - return AmtKnownBits.getMaxValue().ult(BitWidth); + return all_of(E.Scalars, [&](Value *V) { + auto *I = cast(V); + KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL); + return AmtKnownBits.getMaxValue().ult(BitWidth); + }); }; return TryProcessInstruction( - I, *ITE, BitWidth, {I->getOperand(0), I->getOperand(1)}, ShlChecker); + BitWidth, {getOperandEntry(&E, 0), getOperandEntry(&E, 1)}, ShlChecker); } case Instruction::LShr: { // If this is a truncate of a logical shr, we can truncate it to a smaller // lshr iff we know that the bits we would otherwise be shifting in are // already zeros. auto LShrChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) { - KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL); - APInt ShiftedBits = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); - return AmtKnownBits.getMaxValue().ult(BitWidth) && - MaskedValueIsZero(I->getOperand(0), ShiftedBits, - SimplifyQuery(*DL)); + return all_of(E.Scalars, [&](Value *V) { + auto *I = cast(V); + KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL); + APInt ShiftedBits = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); + return AmtKnownBits.getMaxValue().ult(BitWidth) && + MaskedValueIsZero(I->getOperand(0), ShiftedBits, + SimplifyQuery(*DL)); + }); }; return TryProcessInstruction( - I, *ITE, BitWidth, {I->getOperand(0), I->getOperand(1)}, LShrChecker); + BitWidth, {getOperandEntry(&E, 0), getOperandEntry(&E, 1)}, + LShrChecker); } case Instruction::AShr: { // If this is a truncate of an arithmetic shr, we can truncate it to a // smaller ashr iff we know that all the bits from the sign bit of the // original type and the sign bit of the truncate type are similar. auto AShrChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) { - KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL); - unsigned ShiftedBits = OrigBitWidth - BitWidth; - return AmtKnownBits.getMaxValue().ult(BitWidth) && - ShiftedBits < - ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, nullptr, DT); + return all_of(E.Scalars, [&](Value *V) { + auto *I = cast(V); + KnownBits AmtKnownBits = computeKnownBits(I->getOperand(1), *DL); + unsigned ShiftedBits = OrigBitWidth - BitWidth; + return AmtKnownBits.getMaxValue().ult(BitWidth) && + ShiftedBits < ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, + nullptr, DT); + }); }; return TryProcessInstruction( - I, *ITE, BitWidth, {I->getOperand(0), I->getOperand(1)}, AShrChecker); + BitWidth, {getOperandEntry(&E, 0), getOperandEntry(&E, 1)}, + AShrChecker); } case Instruction::UDiv: case Instruction::URem: { // UDiv and URem can be truncated if all the truncated bits are zero. auto Checker = [&](unsigned BitWidth, unsigned OrigBitWidth) { assert(BitWidth <= OrigBitWidth && "Unexpected bitwidths!"); - APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); - return MaskedValueIsZero(I->getOperand(0), Mask, SimplifyQuery(*DL)) && - MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)); + return all_of(E.Scalars, [&](Value *V) { + auto *I = cast(V); + APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); + return MaskedValueIsZero(I->getOperand(0), Mask, SimplifyQuery(*DL)) && + MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)); + }); }; - return TryProcessInstruction(I, *ITE, BitWidth, - {I->getOperand(0), I->getOperand(1)}, Checker); + return TryProcessInstruction( + BitWidth, {getOperandEntry(&E, 0), getOperandEntry(&E, 1)}, Checker); } // We can demote selects if we can demote their true and false values. case Instruction::Select: { - Start = 1; - auto *SI = cast(I); - return TryProcessInstruction(I, *ITE, BitWidth, - {SI->getTrueValue(), SI->getFalseValue()}); + return TryProcessInstruction( + BitWidth, {getOperandEntry(&E, 1), getOperandEntry(&E, 2)}); } // We can demote phis if we can demote all their incoming operands. Note that // we don't need to worry about cycles since we ensure single use above. case Instruction::PHI: { - PHINode *PN = cast(I); - SmallVector Ops(PN->incoming_values().begin(), - PN->incoming_values().end()); - return TryProcessInstruction(I, *ITE, BitWidth, Ops); + const unsigned NumOps = E.getNumOperands(); + SmallVector Ops(NumOps); + transform(seq(0, NumOps), Ops.begin(), + std::bind(&BoUpSLP::getOperandEntry, this, &E, _1)); + + return TryProcessInstruction(BitWidth, Ops); } case Instruction::Call: { - auto *IC = dyn_cast(I); + auto *IC = dyn_cast(E.getMainOp()); if (!IC) break; Intrinsic::ID ID = getVectorIntrinsicIDForCall(IC, TLI); if (ID != Intrinsic::abs && ID != Intrinsic::smin && ID != Intrinsic::smax && ID != Intrinsic::umin && ID != Intrinsic::umax) break; - SmallVector Operands(1, I->getOperand(0)); + SmallVector Operands(1, getOperandEntry(&E, 0)); function_ref CallChecker; auto CompChecker = [&](unsigned BitWidth, unsigned OrigBitWidth) { assert(BitWidth <= OrigBitWidth && "Unexpected bitwidths!"); - if (ID == Intrinsic::umin || ID == Intrinsic::umax) { - APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); - return MaskedValueIsZero(I->getOperand(0), Mask, SimplifyQuery(*DL)) && - MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)); - } - assert((ID == Intrinsic::smin || ID == Intrinsic::smax) && - "Expected min/max intrinsics only."); - unsigned SignBits = OrigBitWidth - BitWidth; - return SignBits <= ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, - nullptr, DT) && - SignBits <= - ComputeNumSignBits(I->getOperand(1), *DL, 0, AC, nullptr, DT); + return all_of(E.Scalars, [&](Value *V) { + auto *I = cast(V); + if (ID == Intrinsic::umin || ID == Intrinsic::umax) { + APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); + return MaskedValueIsZero(I->getOperand(0), Mask, + SimplifyQuery(*DL)) && + MaskedValueIsZero(I->getOperand(1), Mask, SimplifyQuery(*DL)); + } + assert((ID == Intrinsic::smin || ID == Intrinsic::smax) && + "Expected min/max intrinsics only."); + unsigned SignBits = OrigBitWidth - BitWidth; + return SignBits <= ComputeNumSignBits(I->getOperand(0), *DL, 0, AC, + nullptr, DT) && + SignBits <= ComputeNumSignBits(I->getOperand(1), *DL, 0, AC, + nullptr, DT); + }); }; - End = 1; if (ID != Intrinsic::abs) { - Operands.push_back(I->getOperand(1)); - End = 2; + Operands.push_back(getOperandEntry(&E, 1)); CallChecker = CompChecker; } InstructionCost BestCost = std::numeric_limits::max(); unsigned BestBitWidth = BitWidth; - unsigned VF = ITE->Scalars.size(); + unsigned VF = E.Scalars.size(); // Choose the best bitwidth based on cost estimations. auto Checker = [&](unsigned BitWidth, unsigned) { unsigned MinBW = PowerOf2Ceil(BitWidth); @@ -14419,7 +14429,7 @@ bool BoUpSLP::collectValuesToDemote( [[maybe_unused]] bool NeedToExit; (void)AttemptCheckBitwidth(Checker, NeedToExit); BitWidth = BestBitWidth; - return TryProcessInstruction(I, *ITE, BitWidth, Operands, CallChecker); + return TryProcessInstruction(BitWidth, Operands, CallChecker); } // Otherwise, conservatively give up. @@ -14473,26 +14483,27 @@ void BoUpSLP::computeMinimumValueSizes() { ++NodeIdx; } - // Analyzed in reduction already and not profitable - exit. + // Analyzed the reduction already and not profitable - exit. if (AnalyzedMinBWVals.contains(VectorizableTree[NodeIdx]->Scalars.front())) return; - SmallVector ToDemote; - DenseMap> DemotedConsts; - auto ComputeMaxBitWidth = [&](ArrayRef TreeRoot, unsigned VF, - bool IsTopRoot, bool IsProfitableToDemoteRoot, - unsigned Opcode, unsigned Limit, - bool IsTruncRoot, bool IsSignedCmp) { + SmallVector ToDemote; + auto ComputeMaxBitWidth = [&](const TreeEntry &E, bool IsTopRoot, + bool IsProfitableToDemoteRoot, unsigned Opcode, + unsigned Limit, bool IsTruncRoot, + bool IsSignedCmp) { ToDemote.clear(); - auto *TreeRootIT = dyn_cast(TreeRoot[0]->getType()); + unsigned VF = E.getVectorFactor(); + auto *TreeRootIT = dyn_cast(E.Scalars.front()->getType()); if (!TreeRootIT || !Opcode) return 0u; - if (AnalyzedMinBWVals.contains(TreeRoot.front())) + if (any_of(E.Scalars, + [&](Value *V) { return AnalyzedMinBWVals.contains(V); })) return 0u; - unsigned NumParts = TTI->getNumberOfParts( - FixedVectorType::get(TreeRoot.front()->getType(), VF)); + unsigned NumParts = + TTI->getNumberOfParts(FixedVectorType::get(TreeRootIT, VF)); // The maximum bit width required to represent all the values that can be // demoted without loss of precision. It would be safe to truncate the roots @@ -14505,14 +14516,14 @@ void BoUpSLP::computeMinimumValueSizes() { // True. // Determine if the sign bit of all the roots is known to be zero. If not, // IsKnownPositive is set to False. - bool IsKnownPositive = !IsSignedCmp && all_of(TreeRoot, [&](Value *R) { + bool IsKnownPositive = !IsSignedCmp && all_of(E.Scalars, [&](Value *R) { KnownBits Known = computeKnownBits(R, *DL); return Known.isNonNegative(); }); // We first check if all the bits of the roots are demanded. If they're not, // we can truncate the roots to this narrower type. - for (auto *Root : TreeRoot) { + for (Value *Root : E.Scalars) { unsigned NumSignBits = ComputeNumSignBits(Root, *DL, 0, AC, nullptr, DT); TypeSize NumTypeBits = DL->getTypeSizeInBits(Root->getType()); unsigned BitWidth1 = NumTypeBits - NumSignBits; @@ -14557,23 +14568,22 @@ void BoUpSLP::computeMinimumValueSizes() { // Conservatively determine if we can actually truncate the roots of the // expression. Collect the values that can be demoted in ToDemote and // additional roots that require investigating in Roots. - for (auto *Root : TreeRoot) { - DenseSet Visited; - unsigned MaxDepthLevel = IsTruncRoot ? Limit : 1; - bool NeedToDemote = IsProfitableToDemote; - - if (!collectValuesToDemote(Root, IsProfitableToDemoteRoot, MaxBitWidth, - ToDemote, DemotedConsts, Visited, - MaxDepthLevel, NeedToDemote, IsTruncRoot) || - (MaxDepthLevel <= Limit && - !(((Opcode == Instruction::SExt || Opcode == Instruction::ZExt) && - (!IsTopRoot || !(IsStoreOrInsertElt || UserIgnoreList) || - DL->getTypeSizeInBits(Root->getType()) / - DL->getTypeSizeInBits( - cast(Root)->getOperand(0)->getType()) > - 2))))) - return 0u; - } + DenseSet Visited; + unsigned MaxDepthLevel = IsTruncRoot ? Limit : 1; + bool NeedToDemote = IsProfitableToDemote; + + if (!collectValuesToDemote(E, IsProfitableToDemoteRoot, MaxBitWidth, + ToDemote, Visited, MaxDepthLevel, NeedToDemote, + IsTruncRoot) || + (MaxDepthLevel <= Limit && + !(((Opcode == Instruction::SExt || Opcode == Instruction::ZExt) && + (!IsTopRoot || !(IsStoreOrInsertElt || UserIgnoreList) || + DL->getTypeSizeInBits(TreeRootIT) / + DL->getTypeSizeInBits(cast(E.Scalars.front()) + ->getOperand(0) + ->getType()) > + 2))))) + return 0u; // Round MaxBitWidth up to the next power-of-two. MaxBitWidth = bit_ceil(MaxBitWidth); @@ -14624,8 +14634,8 @@ void BoUpSLP::computeMinimumValueSizes() { VectorizableTree.front()->Scalars.front()->getType())) Limit = 3; unsigned MaxBitWidth = ComputeMaxBitWidth( - TreeRoot, VectorizableTree[NodeIdx]->getVectorFactor(), IsTopRoot, - IsProfitableToDemoteRoot, Opcode, Limit, IsTruncRoot, IsSignedCmp); + *VectorizableTree[NodeIdx].get(), IsTopRoot, IsProfitableToDemoteRoot, + Opcode, Limit, IsTruncRoot, IsSignedCmp); if (ReductionBitWidth != 0 && (IsTopRoot || !RootDemotes.empty())) { if (MaxBitWidth != 0 && ReductionBitWidth < MaxBitWidth) ReductionBitWidth = bit_ceil(MaxBitWidth); @@ -14634,13 +14644,15 @@ void BoUpSLP::computeMinimumValueSizes() { } for (unsigned Idx : RootDemotes) { - Value *V = VectorizableTree[Idx]->Scalars.front(); - uint32_t OrigBitWidth = DL->getTypeSizeInBits(V->getType()); - if (OrigBitWidth > MaxBitWidth) { - APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, MaxBitWidth); - if (MaskedValueIsZero(V, Mask, SimplifyQuery(*DL))) - ToDemote.push_back(V); - } + if (all_of(VectorizableTree[Idx]->Scalars, [&](Value *V) { + uint32_t OrigBitWidth = DL->getTypeSizeInBits(V->getType()); + if (OrigBitWidth > MaxBitWidth) { + APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, MaxBitWidth); + return MaskedValueIsZero(V, Mask, SimplifyQuery(*DL)); + } + return false; + })) + ToDemote.push_back(Idx); } RootDemotes.clear(); IsTopRoot = false; @@ -14687,9 +14699,8 @@ void BoUpSLP::computeMinimumValueSizes() { // Finally, map the values we can demote to the maximum bit with we // computed. - for (Value *Scalar : ToDemote) { - TreeEntry *TE = getTreeEntry(Scalar); - assert(TE && "Expected vectorized scalar."); + for (unsigned Idx : ToDemote) { + TreeEntry *TE = VectorizableTree[Idx].get(); if (MinBWs.contains(TE)) continue; bool IsSigned = TE->getOpcode() == Instruction::SExt || @@ -14697,22 +14708,6 @@ void BoUpSLP::computeMinimumValueSizes() { return !isKnownNonNegative(R, SimplifyQuery(*DL)); }); MinBWs.try_emplace(TE, MaxBitWidth, IsSigned); - const auto *I = cast(Scalar); - auto DCIt = DemotedConsts.find(I); - if (DCIt != DemotedConsts.end()) { - for (unsigned Idx : DCIt->getSecond()) { - // Check that all instructions operands are demoted. - const TreeEntry *CTE = getOperandEntry(TE, Idx); - if (all_of(TE->Scalars, - [&](Value *V) { - auto SIt = DemotedConsts.find(cast(V)); - return SIt != DemotedConsts.end() && - is_contained(SIt->getSecond(), Idx); - }) || - all_of(CTE->Scalars, IsaPred)) - MinBWs.try_emplace(CTE, MaxBitWidth, IsSigned); - } - } } } } -- GitLab From 50d368aee981738cd05f3d16f5d1cfc122c9b0ab Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Apr 2024 09:07:43 -0500 Subject: [PATCH 395/695] [LinkerWrapper] Relax ordering of static libraries for offloading (#87532) Summary: The linker wrapper attempts to maintain consistent semantics with existing host invocations. Static libraries by default only extract if there are non-weak symbols that remain undefined. However, we have situations between linkers that put different meanings on ordering. The ld.bfd linker requires static libraries to be defined after the symbols, while `ld.lld` relaxes this rule. The linker wrapper went with the former as it's the easier solution, however this has caused a lot of issues as I've had to explain this rule to several people, it also make it difficult to include things like `libc` in the OpenMP runtime because it would sometimes be linked before or after. This patch reworks the logic to more or less perform the following logic for static libraries. 1. Split library / object inputs. 2. Include every object input and record its undefined symbols 3. Repeatedly try to extract static libraries to resolve these symbols. If a file is extracted we need to check every library again to resolve any new undefined symbols. This allows the following to work and will cause fewer issues when replacing HIP, which does `--whole-archive` so it's very likely the old logic will regress. ```console $ clang -lfoo main.c -fopenmp --offload-arch=native ``` --- clang/test/Driver/linker-wrapper-libs.c | 4 + .../ClangLinkerWrapper.cpp | 121 ++++++++++++------ 2 files changed, 83 insertions(+), 42 deletions(-) diff --git a/clang/test/Driver/linker-wrapper-libs.c b/clang/test/Driver/linker-wrapper-libs.c index 9a78200d7d3c..119e30685718 100644 --- a/clang/test/Driver/linker-wrapper-libs.c +++ b/clang/test/Driver/linker-wrapper-libs.c @@ -44,6 +44,8 @@ int bar() { return weak; } // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o -fembed-offload-object=%t.out // RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ // RUN: --linker-path=/usr/bin/ld %t.o %t.a -o a.out 2>&1 \ +// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ +// RUN: --linker-path=/usr/bin/ld %t.a %t.o -o a.out 2>&1 \ // RUN: | FileCheck %s --check-prefix=LIBRARY-RESOLVES // LIBRARY-RESOLVES: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa -mcpu=gfx1030 {{.*}}.o {{.*}}.o @@ -66,6 +68,8 @@ int bar() { return weak; } // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o -fembed-offload-object=%t.out // RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ // RUN: --linker-path=/usr/bin/ld %t.o %t.a -o a.out 2>&1 \ +// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ +// RUN: --linker-path=/usr/bin/ld %t.a %t.o -o a.out 2>&1 \ // RUN: | FileCheck %s --check-prefix=LIBRARY-GLOBAL // LIBRARY-GLOBAL: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa -mcpu=gfx1030 {{.*}}.o {{.*}}.o diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 73e695a67093..a1879fc7712d 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -1448,9 +1448,9 @@ getDeviceInput(const ArgList &Args) { StringSaver Saver(Alloc); // Try to extract device code from the linker input files. - DenseMap> InputFiles; - DenseMap> Syms; bool WholeArchive = Args.hasArg(OPT_wholearchive_flag) ? true : false; + SmallVector ObjectFilesToExtract; + SmallVector ArchiveFilesToExtract; for (const opt::Arg *Arg : Args.filtered( OPT_INPUT, OPT_library, OPT_whole_archive, OPT_no_whole_archive)) { if (Arg->getOption().matches(OPT_whole_archive) || @@ -1486,50 +1486,87 @@ getDeviceInput(const ArgList &Args) { if (Error Err = extractOffloadBinaries(Buffer, Binaries)) return std::move(Err); - // We only extract archive members that are needed. - bool IsArchive = identify_magic(Buffer.getBuffer()) == file_magic::archive; - bool Extracted = true; - while (Extracted) { - Extracted = false; - for (OffloadFile &Binary : Binaries) { - // If the binary was previously extracted it will be set to null. - if (!Binary.getBinary()) + for (auto &OffloadFile : Binaries) { + if (identify_magic(Buffer.getBuffer()) == file_magic::archive && + !WholeArchive) + ArchiveFilesToExtract.emplace_back(std::move(OffloadFile)); + else + ObjectFilesToExtract.emplace_back(std::move(OffloadFile)); + } + } + + // Link all standard input files and update the list of symbols. + DenseMap> InputFiles; + DenseMap> Syms; + for (OffloadFile &Binary : ObjectFilesToExtract) { + if (!Binary.getBinary()) + continue; + + SmallVector CompatibleTargets = {Binary}; + for (const auto &[ID, Input] : InputFiles) + if (object::areTargetsCompatible(Binary, ID)) + CompatibleTargets.emplace_back(ID); + + for (const auto &[Index, ID] : llvm::enumerate(CompatibleTargets)) { + Expected ExtractOrErr = getSymbols( + Binary.getBinary()->getImage(), Binary.getBinary()->getOffloadKind(), + /*IsArchive=*/false, Saver, Syms[ID]); + if (!ExtractOrErr) + return ExtractOrErr.takeError(); + + // If another target needs this binary it must be copied instead. + if (Index == CompatibleTargets.size() - 1) + InputFiles[ID].emplace_back(std::move(Binary)); + else + InputFiles[ID].emplace_back(Binary.copy()); + } + } + + // Archive members only extract if they define needed symbols. We do this + // after every regular input file so that libraries may be included out of + // order. This follows 'ld.lld' semantics which are more lenient. + bool Extracted = true; + while (Extracted) { + Extracted = false; + for (OffloadFile &Binary : ArchiveFilesToExtract) { + // If the binary was previously extracted it will be set to null. + if (!Binary.getBinary()) + continue; + + SmallVector CompatibleTargets = {Binary}; + for (const auto &[ID, Input] : InputFiles) + if (object::areTargetsCompatible(Binary, ID)) + CompatibleTargets.emplace_back(ID); + + for (const auto &[Index, ID] : llvm::enumerate(CompatibleTargets)) { + // Only extract an if we have an an object matching this target. + if (!InputFiles.count(ID)) continue; - SmallVector CompatibleTargets = {Binary}; - for (const auto &[ID, Input] : InputFiles) - if (object::areTargetsCompatible(Binary, ID)) - CompatibleTargets.emplace_back(ID); - - for (const auto &[Index, ID] : llvm::enumerate(CompatibleTargets)) { - // Only extract an if we have an an object matching this target. - if (IsArchive && !WholeArchive && !InputFiles.count(ID)) - continue; - - Expected ExtractOrErr = getSymbols( - Binary.getBinary()->getImage(), - Binary.getBinary()->getOffloadKind(), IsArchive, Saver, Syms[ID]); - if (!ExtractOrErr) - return ExtractOrErr.takeError(); - - Extracted = !WholeArchive && *ExtractOrErr; - - // Skip including the file if it is an archive that does not resolve - // any symbols. - if (IsArchive && !WholeArchive && !Extracted) - continue; - - // If another target needs this binary it must be copied instead. - if (Index == CompatibleTargets.size() - 1) - InputFiles[ID].emplace_back(std::move(Binary)); - else - InputFiles[ID].emplace_back(Binary.copy()); - } + Expected ExtractOrErr = + getSymbols(Binary.getBinary()->getImage(), + Binary.getBinary()->getOffloadKind(), /*IsArchive=*/true, + Saver, Syms[ID]); + if (!ExtractOrErr) + return ExtractOrErr.takeError(); - // If we extracted any files we need to check all the symbols again. - if (Extracted) - break; + Extracted = *ExtractOrErr; + + // Skip including the file if it is an archive that does not resolve + // any symbols. + if (!Extracted) + continue; + + // If another target needs this binary it must be copied instead. + if (Index == CompatibleTargets.size() - 1) + InputFiles[ID].emplace_back(std::move(Binary)); + else + InputFiles[ID].emplace_back(Binary.copy()); } + + // If we extracted any files we need to check all the symbols again. + if (Extracted) + break; } } -- GitLab From 6b35cbee3f577d9ee55f7277affa0fe194859b25 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Wed, 10 Apr 2024 18:09:39 +0400 Subject: [PATCH 396/695] [clang] Introduce `SemaSYCL` (#88086) This patch moves SYCL-related `Sema` functions into new `SemaSYCL` class, following the recent example of OpenACC and HLSL. This is a part of the effort to split `Sema`. Additional context can be found in #82217, #84184, #87634. --- clang/include/clang/Sema/Sema.h | 55 ++++-------------------- clang/include/clang/Sema/SemaSYCL.h | 65 +++++++++++++++++++++++++++++ clang/lib/Parse/ParseExpr.cpp | 5 ++- clang/lib/Sema/Sema.cpp | 6 ++- clang/lib/Sema/SemaExpr.cpp | 22 ---------- clang/lib/Sema/SemaSYCL.cpp | 52 +++++++++++++++++------ clang/lib/Sema/TreeTransform.h | 4 +- 7 files changed, 121 insertions(+), 88 deletions(-) create mode 100644 clang/include/clang/Sema/SemaSYCL.h diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 9769d3690066..e3e255a0dd76 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -184,6 +184,7 @@ class PseudoObjectExpr; class QualType; class SemaHLSL; class SemaOpenACC; +class SemaSYCL; class StandardConversionSequence; class Stmt; class StringLiteral; @@ -467,7 +468,6 @@ class Sema final : public SemaBase { // 37. Name Lookup for RISC-V Vector Intrinsic (SemaRISCVVectorLookup.cpp) // 38. CUDA (SemaCUDA.cpp) // 39. OpenMP Directives and Clauses (SemaOpenMP.cpp) - // 40. SYCL Constructs (SemaSYCL.cpp) /// \name Semantic Analysis /// Implementations are in Sema.cpp @@ -974,6 +974,11 @@ public: return *OpenACCPtr; } + SemaSYCL &SYCL() { + assert(SYCLPtr); + return *SYCLPtr; + } + protected: friend class Parser; friend class InitializationSequence; @@ -1006,6 +1011,7 @@ private: std::unique_ptr HLSLPtr; std::unique_ptr OpenACCPtr; + std::unique_ptr SYCLPtr; ///@} @@ -5455,15 +5461,6 @@ public: ExprResult ActOnPredefinedExpr(SourceLocation Loc, tok::TokenKind Kind); ExprResult ActOnIntegerConstant(SourceLocation Loc, uint64_t Val); - ExprResult BuildSYCLUniqueStableNameExpr(SourceLocation OpLoc, - SourceLocation LParen, - SourceLocation RParen, - TypeSourceInfo *TSI); - ExprResult ActOnSYCLUniqueStableNameExpr(SourceLocation OpLoc, - SourceLocation LParen, - SourceLocation RParen, - ParsedType ParsedTy); - bool CheckLoopHintExpr(Expr *E, SourceLocation Loc); ExprResult ActOnNumericConstant(const Token &Tok, Scope *UDLScope = nullptr); @@ -14516,44 +14513,6 @@ private: OpenMPDirectiveKind CancelRegion); ///@} - - // - // - // ------------------------------------------------------------------------- - // - // - - /// \name SYCL Constructs - /// Implementations are in SemaSYCL.cpp - ///@{ - -public: - /// Creates a SemaDiagnosticBuilder that emits the diagnostic if the current - /// context is "used as device code". - /// - /// - If CurLexicalContext is a kernel function or it is known that the - /// function will be emitted for the device, emits the diagnostics - /// immediately. - /// - If CurLexicalContext is a function and we are compiling - /// for the device, but we don't know that this function will be codegen'ed - /// for devive yet, creates a diagnostic which is emitted if and when we - /// realize that the function will be codegen'ed. - /// - /// Example usage: - /// - /// Diagnose __float128 type usage only from SYCL device code if the current - /// target doesn't support it - /// if (!S.Context.getTargetInfo().hasFloat128Type() && - /// S.getLangOpts().SYCLIsDevice) - /// SYCLDiagIfDeviceCode(Loc, diag::err_type_unsupported) << "__float128"; - SemaDiagnosticBuilder SYCLDiagIfDeviceCode(SourceLocation Loc, - unsigned DiagID); - - void deepTypeCheckForSYCLDevice(SourceLocation UsedAt, - llvm::DenseSet Visited, - ValueDecl *DeclToCheck); - - ///@} }; DeductionFailureInfo diff --git a/clang/include/clang/Sema/SemaSYCL.h b/clang/include/clang/Sema/SemaSYCL.h new file mode 100644 index 000000000000..f0dcb92ee9ab --- /dev/null +++ b/clang/include/clang/Sema/SemaSYCL.h @@ -0,0 +1,65 @@ +//===----- SemaSYCL.h ------- Semantic Analysis for SYCL constructs -------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// \file +/// This file declares semantic analysis for SYCL constructs. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_SEMA_SEMASYCL_H +#define LLVM_CLANG_SEMA_SEMASYCL_H + +#include "clang/AST/Decl.h" +#include "clang/AST/Type.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Sema/Ownership.h" +#include "clang/Sema/SemaBase.h" +#include "llvm/ADT/DenseSet.h" + +namespace clang { + +class SemaSYCL : public SemaBase { +public: + SemaSYCL(Sema &S); + + /// Creates a SemaDiagnosticBuilder that emits the diagnostic if the current + /// context is "used as device code". + /// + /// - If CurLexicalContext is a kernel function or it is known that the + /// function will be emitted for the device, emits the diagnostics + /// immediately. + /// - If CurLexicalContext is a function and we are compiling + /// for the device, but we don't know yet that this function will be + /// codegen'ed for the devive, creates a diagnostic which is emitted if and + /// when we realize that the function will be codegen'ed. + /// + /// Example usage: + /// + /// Diagnose __float128 type usage only from SYCL device code if the current + /// target doesn't support it + /// if (!S.Context.getTargetInfo().hasFloat128Type() && + /// S.getLangOpts().SYCLIsDevice) + /// DiagIfDeviceCode(Loc, diag::err_type_unsupported) << "__float128"; + SemaDiagnosticBuilder DiagIfDeviceCode(SourceLocation Loc, unsigned DiagID); + + void deepTypeCheckForDevice(SourceLocation UsedAt, + llvm::DenseSet Visited, + ValueDecl *DeclToCheck); + + ExprResult BuildUniqueStableNameExpr(SourceLocation OpLoc, + SourceLocation LParen, + SourceLocation RParen, + TypeSourceInfo *TSI); + ExprResult ActOnUniqueStableNameExpr(SourceLocation OpLoc, + SourceLocation LParen, + SourceLocation RParen, + ParsedType ParsedTy); +}; + +} // namespace clang + +#endif // LLVM_CLANG_SEMA_SEMASYCL_H diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index ae23cb432c43..d08e675604d1 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -30,6 +30,7 @@ #include "clang/Sema/EnterExpressionEvaluationContext.h" #include "clang/Sema/ParsedTemplate.h" #include "clang/Sema/Scope.h" +#include "clang/Sema/SemaSYCL.h" #include "clang/Sema/TypoCorrection.h" #include "llvm/ADT/SmallVector.h" #include @@ -2490,8 +2491,8 @@ ExprResult Parser::ParseSYCLUniqueStableNameExpression() { if (T.consumeClose()) return ExprError(); - return Actions.ActOnSYCLUniqueStableNameExpr(OpLoc, T.getOpenLocation(), - T.getCloseLocation(), Ty.get()); + return Actions.SYCL().ActOnUniqueStableNameExpr( + OpLoc, T.getOpenLocation(), T.getCloseLocation(), Ty.get()); } /// Parse a sizeof or alignof expression. diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 04eadb5f3b8a..801b03a63dbc 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -45,6 +45,7 @@ #include "clang/Sema/SemaHLSL.h" #include "clang/Sema/SemaInternal.h" #include "clang/Sema/SemaOpenACC.h" +#include "clang/Sema/SemaSYCL.h" #include "clang/Sema/TemplateDeduction.h" #include "clang/Sema/TemplateInstCallback.h" #include "clang/Sema/TypoCorrection.h" @@ -201,6 +202,7 @@ Sema::Sema(Preprocessor &pp, ASTContext &ctxt, ASTConsumer &consumer, CurScope(nullptr), Ident_super(nullptr), HLSLPtr(std::make_unique(*this)), OpenACCPtr(std::make_unique(*this)), + SYCLPtr(std::make_unique(*this)), MSPointerToMemberRepresentationMethod( LangOpts.getMSPointerToMemberRepresentationMethod()), MSStructPragmaOn(false), VtorDispStack(LangOpts.getVtorDispMode()), @@ -1903,7 +1905,7 @@ Sema::targetDiag(SourceLocation Loc, unsigned DiagID, const FunctionDecl *FD) { : CUDADiagIfHostCode(Loc, DiagID); if (getLangOpts().SYCLIsDevice) - return SYCLDiagIfDeviceCode(Loc, DiagID); + return SYCL().DiagIfDeviceCode(Loc, DiagID); return SemaDiagnosticBuilder(SemaDiagnosticBuilder::K_Immediate, Loc, DiagID, FD, *this); @@ -1919,7 +1921,7 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation Loc, ValueDecl *D) { // constant byte size like zero length arrays. So, do a deep check for SYCL. if (D && LangOpts.SYCLIsDevice) { llvm::DenseSet Visited; - deepTypeCheckForSYCLDevice(Loc, Visited, D); + SYCL().deepTypeCheckForDevice(Loc, Visited, D); } Decl *C = cast(getCurLexicalContext()); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index 594c11788f4e..4d4ef9b16381 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -3794,28 +3794,6 @@ ExprResult Sema::BuildPredefinedExpr(SourceLocation Loc, SL); } -ExprResult Sema::BuildSYCLUniqueStableNameExpr(SourceLocation OpLoc, - SourceLocation LParen, - SourceLocation RParen, - TypeSourceInfo *TSI) { - return SYCLUniqueStableNameExpr::Create(Context, OpLoc, LParen, RParen, TSI); -} - -ExprResult Sema::ActOnSYCLUniqueStableNameExpr(SourceLocation OpLoc, - SourceLocation LParen, - SourceLocation RParen, - ParsedType ParsedTy) { - TypeSourceInfo *TSI = nullptr; - QualType Ty = GetTypeFromParser(ParsedTy, &TSI); - - if (Ty.isNull()) - return ExprError(); - if (!TSI) - TSI = Context.getTrivialTypeSourceInfo(Ty, LParen); - - return BuildSYCLUniqueStableNameExpr(OpLoc, LParen, RParen, TSI); -} - ExprResult Sema::ActOnPredefinedExpr(SourceLocation Loc, tok::TokenKind Kind) { return BuildPredefinedExpr(Loc, getPredefinedExprKind(Kind)); } diff --git a/clang/lib/Sema/SemaSYCL.cpp b/clang/lib/Sema/SemaSYCL.cpp index 18ebaa13346a..18f6d8f03047 100644 --- a/clang/lib/Sema/SemaSYCL.cpp +++ b/clang/lib/Sema/SemaSYCL.cpp @@ -8,6 +8,7 @@ // This implements Semantic Analysis for SYCL constructs. //===----------------------------------------------------------------------===// +#include "clang/Sema/SemaSYCL.h" #include "clang/AST/Mangle.h" #include "clang/Sema/Sema.h" #include "clang/Sema/SemaDiagnostic.h" @@ -18,28 +19,30 @@ using namespace clang; // SYCL device specific diagnostics implementation // ----------------------------------------------------------------------------- -Sema::SemaDiagnosticBuilder Sema::SYCLDiagIfDeviceCode(SourceLocation Loc, +SemaSYCL::SemaSYCL(Sema &S) : SemaBase(S) {} + +Sema::SemaDiagnosticBuilder SemaSYCL::DiagIfDeviceCode(SourceLocation Loc, unsigned DiagID) { assert(getLangOpts().SYCLIsDevice && "Should only be called during SYCL compilation"); - FunctionDecl *FD = dyn_cast(getCurLexicalContext()); + FunctionDecl *FD = dyn_cast(SemaRef.getCurLexicalContext()); SemaDiagnosticBuilder::Kind DiagKind = [this, FD] { if (!FD) return SemaDiagnosticBuilder::K_Nop; - if (getEmissionStatus(FD) == Sema::FunctionEmissionStatus::Emitted) + if (SemaRef.getEmissionStatus(FD) == Sema::FunctionEmissionStatus::Emitted) return SemaDiagnosticBuilder::K_ImmediateWithCallStack; return SemaDiagnosticBuilder::K_Deferred; }(); - return SemaDiagnosticBuilder(DiagKind, Loc, DiagID, FD, *this); + return SemaDiagnosticBuilder(DiagKind, Loc, DiagID, FD, SemaRef); } -static bool isZeroSizedArray(Sema &SemaRef, QualType Ty) { - if (const auto *CAT = SemaRef.getASTContext().getAsConstantArrayType(Ty)) +static bool isZeroSizedArray(SemaSYCL &S, QualType Ty) { + if (const auto *CAT = S.getASTContext().getAsConstantArrayType(Ty)) return CAT->isZeroSize(); return false; } -void Sema::deepTypeCheckForSYCLDevice(SourceLocation UsedAt, +void SemaSYCL::deepTypeCheckForDevice(SourceLocation UsedAt, llvm::DenseSet Visited, ValueDecl *DeclToCheck) { assert(getLangOpts().SYCLIsDevice && @@ -51,18 +54,18 @@ void Sema::deepTypeCheckForSYCLDevice(SourceLocation UsedAt, auto Check = [&](QualType TypeToCheck, const ValueDecl *D) { bool ErrorFound = false; if (isZeroSizedArray(*this, TypeToCheck)) { - SYCLDiagIfDeviceCode(UsedAt, diag::err_typecheck_zero_array_size) << 1; + DiagIfDeviceCode(UsedAt, diag::err_typecheck_zero_array_size) << 1; ErrorFound = true; } // Checks for other types can also be done here. if (ErrorFound) { if (NeedToEmitNotes) { if (auto *FD = dyn_cast(D)) - SYCLDiagIfDeviceCode(FD->getLocation(), - diag::note_illegal_field_declared_here) + DiagIfDeviceCode(FD->getLocation(), + diag::note_illegal_field_declared_here) << FD->getType()->isPointerType() << FD->getType(); else - SYCLDiagIfDeviceCode(D->getLocation(), diag::note_declared_at); + DiagIfDeviceCode(D->getLocation(), diag::note_declared_at); } } @@ -93,8 +96,8 @@ void Sema::deepTypeCheckForSYCLDevice(SourceLocation UsedAt, auto EmitHistory = [&]() { // The first element is always nullptr. for (uint64_t Index = 1; Index < History.size(); ++Index) { - SYCLDiagIfDeviceCode(History[Index]->getLocation(), - diag::note_within_field_of_type) + DiagIfDeviceCode(History[Index]->getLocation(), + diag::note_within_field_of_type) << History[Index]->getType(); } }; @@ -130,3 +133,26 @@ void Sema::deepTypeCheckForSYCLDevice(SourceLocation UsedAt, } } while (!StackForRecursion.empty()); } + +ExprResult SemaSYCL::BuildUniqueStableNameExpr(SourceLocation OpLoc, + SourceLocation LParen, + SourceLocation RParen, + TypeSourceInfo *TSI) { + return SYCLUniqueStableNameExpr::Create(getASTContext(), OpLoc, LParen, + RParen, TSI); +} + +ExprResult SemaSYCL::ActOnUniqueStableNameExpr(SourceLocation OpLoc, + SourceLocation LParen, + SourceLocation RParen, + ParsedType ParsedTy) { + TypeSourceInfo *TSI = nullptr; + QualType Ty = SemaRef.GetTypeFromParser(ParsedTy, &TSI); + + if (Ty.isNull()) + return ExprError(); + if (!TSI) + TSI = getASTContext().getTrivialTypeSourceInfo(Ty, LParen); + + return BuildUniqueStableNameExpr(OpLoc, LParen, RParen, TSI); +} diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index d4d2fa61d65e..79d60588ae53 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -40,6 +40,7 @@ #include "clang/Sema/SemaDiagnostic.h" #include "clang/Sema/SemaInternal.h" #include "clang/Sema/SemaOpenACC.h" +#include "clang/Sema/SemaSYCL.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/Support/ErrorHandling.h" #include @@ -2632,7 +2633,8 @@ public: SourceLocation LParen, SourceLocation RParen, TypeSourceInfo *TSI) { - return getSema().BuildSYCLUniqueStableNameExpr(OpLoc, LParen, RParen, TSI); + return getSema().SYCL().BuildUniqueStableNameExpr(OpLoc, LParen, RParen, + TSI); } /// Build a new predefined expression. -- GitLab From 0c7b92a42a36563dfd28e3a828e87f4f3a6e4311 Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Wed, 10 Apr 2024 07:10:24 -0700 Subject: [PATCH 397/695] [OpenACC] Implement Default clause for Compute Constructs (#88135) As a followup to my previous commits, this is an implementation of a single clause, in this case the 'default' clause. This implements all semantic analysis for it on compute clauses, and continues to leave it rejected for all others (some as 'doesnt appertain', others as 'not implemented' as appropriate). This also implements and tests the TreeTransform as requested in the previous patch. --- clang/include/clang/AST/OpenACCClause.h | 38 ++++++++++ .../clang/Basic/DiagnosticSemaKinds.td | 4 + clang/include/clang/Basic/OpenACCKinds.h | 23 ++++++ clang/include/clang/Sema/SemaOpenACC.h | 19 ++++- clang/lib/AST/OpenACCClause.cpp | 19 +++++ clang/lib/AST/StmtProfile.cpp | 5 ++ clang/lib/AST/TextNodeDumper.cpp | 11 +++ clang/lib/Parse/ParseOpenACC.cpp | 8 +- clang/lib/Sema/SemaOpenACC.cpp | 65 ++++++++++++++-- clang/lib/Sema/TreeTransform.h | 42 ++++++++++- clang/lib/Serialization/ASTReader.cpp | 7 +- clang/lib/Serialization/ASTWriter.cpp | 7 +- clang/test/ParserOpenACC/parse-clauses.c | 20 ++--- .../SemaOpenACC/compute-construct-ast.cpp | 14 +++- .../compute-construct-clause-ast.cpp | 74 +++++++++++++++++++ .../compute-construct-default-clause.c | 55 ++++++++++++++ .../compute-construct-default-clause.cpp | 39 ++++++++++ 17 files changed, 417 insertions(+), 33 deletions(-) create mode 100644 clang/test/SemaOpenACC/compute-construct-clause-ast.cpp create mode 100644 clang/test/SemaOpenACC/compute-construct-default-clause.c create mode 100644 clang/test/SemaOpenACC/compute-construct-default-clause.cpp diff --git a/clang/include/clang/AST/OpenACCClause.h b/clang/include/clang/AST/OpenACCClause.h index 06a0098bbda4..27e4e1a12c98 100644 --- a/clang/include/clang/AST/OpenACCClause.h +++ b/clang/include/clang/AST/OpenACCClause.h @@ -51,6 +51,36 @@ public: SourceLocation getLParenLoc() const { return LParenLoc; } }; +/// A 'default' clause, has the optional 'none' or 'present' argument. +class OpenACCDefaultClause : public OpenACCClauseWithParams { + friend class ASTReaderStmt; + friend class ASTWriterStmt; + + OpenACCDefaultClauseKind DefaultClauseKind; + +protected: + OpenACCDefaultClause(OpenACCDefaultClauseKind K, SourceLocation BeginLoc, + SourceLocation LParenLoc, SourceLocation EndLoc) + : OpenACCClauseWithParams(OpenACCClauseKind::Default, BeginLoc, LParenLoc, + EndLoc), + DefaultClauseKind(K) { + assert((DefaultClauseKind == OpenACCDefaultClauseKind::None || + DefaultClauseKind == OpenACCDefaultClauseKind::Present) && + "Invalid Clause Kind"); + } + +public: + OpenACCDefaultClauseKind getDefaultClauseKind() const { + return DefaultClauseKind; + } + + static OpenACCDefaultClause *Create(const ASTContext &C, + OpenACCDefaultClauseKind K, + SourceLocation BeginLoc, + SourceLocation LParenLoc, + SourceLocation EndLoc); +}; + template class OpenACCClauseVisitor { Impl &getDerived() { return static_cast(*this); } @@ -66,6 +96,8 @@ public: switch (C->getClauseKind()) { case OpenACCClauseKind::Default: + VisitOpenACCDefaultClause(*cast(C)); + return; case OpenACCClauseKind::Finalize: case OpenACCClauseKind::IfPresent: case OpenACCClauseKind::Seq: @@ -112,6 +144,10 @@ public: } llvm_unreachable("Invalid Clause kind"); } + + void VisitOpenACCDefaultClause(const OpenACCDefaultClause &Clause) { + return getDerived().VisitOpenACCDefaultClause(Clause); + } }; class OpenACCClausePrinter final @@ -128,6 +164,8 @@ public: } } OpenACCClausePrinter(raw_ostream &OS) : OS(OS) {} + + void VisitOpenACCDefaultClause(const OpenACCDefaultClause &Clause); }; } // namespace clang diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 64c58ab36338..059a8f58da5d 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -12265,6 +12265,10 @@ def err_acc_construct_appertainment "be used in a statement context">; def err_acc_clause_appertainment : Error<"OpenACC '%1' clause is not valid on '%0' directive">; +def err_acc_duplicate_clause_disallowed + : Error<"OpenACC '%1' clause cannot appear more than once on a '%0' " + "directive">; +def note_acc_previous_clause_here : Note<"previous clause is here">; def err_acc_branch_in_out_compute_construct : Error<"invalid %select{branch|return|throw}0 %select{out of|into}1 " "OpenACC Compute Construct">; diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index 95fc35a5bedb..e191e9e0a5a1 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -419,6 +419,29 @@ enum class OpenACCDefaultClauseKind { Invalid, }; +template +inline StreamTy &printOpenACCDefaultClauseKind(StreamTy &Out, + OpenACCDefaultClauseKind K) { + switch (K) { + case OpenACCDefaultClauseKind::None: + return Out << "none"; + case OpenACCDefaultClauseKind::Present: + return Out << "present"; + case OpenACCDefaultClauseKind::Invalid: + return Out << ""; + } +} + +inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &Out, + OpenACCDefaultClauseKind K) { + return printOpenACCDefaultClauseKind(Out, K); +} + +inline llvm::raw_ostream &operator<<(llvm::raw_ostream &Out, + OpenACCDefaultClauseKind K) { + return printOpenACCDefaultClauseKind(Out, K); +} + enum class OpenACCReductionOperator { /// '+'. Addition, diff --git a/clang/include/clang/Sema/SemaOpenACC.h b/clang/include/clang/Sema/SemaOpenACC.h index 45929e4a9db3..27aaee164a28 100644 --- a/clang/include/clang/Sema/SemaOpenACC.h +++ b/clang/include/clang/Sema/SemaOpenACC.h @@ -19,6 +19,7 @@ #include "clang/Basic/SourceLocation.h" #include "clang/Sema/Ownership.h" #include "clang/Sema/SemaBase.h" +#include namespace clang { class OpenACCClause; @@ -35,7 +36,11 @@ public: SourceRange ClauseRange; SourceLocation LParenLoc; - // TODO OpenACC: Add variant here to store details of individual clauses. + struct DefaultDetails { + OpenACCDefaultClauseKind DefaultClauseKind; + }; + + std::variant Details; public: OpenACCParsedClause(OpenACCDirectiveKind DirKind, @@ -52,8 +57,20 @@ public: SourceLocation getEndLoc() const { return ClauseRange.getEnd(); } + OpenACCDefaultClauseKind getDefaultClauseKind() const { + assert(ClauseKind == OpenACCClauseKind::Default && + "Parsed clause is not a default clause"); + return std::get(Details).DefaultClauseKind; + } + void setLParenLoc(SourceLocation EndLoc) { LParenLoc = EndLoc; } void setEndLoc(SourceLocation EndLoc) { ClauseRange.setEnd(EndLoc); } + + void setDefaultDetails(OpenACCDefaultClauseKind DefKind) { + assert(ClauseKind == OpenACCClauseKind::Default && + "Parsed clause is not a default clause"); + Details = DefaultDetails{DefKind}; + } }; SemaOpenACC(Sema &S); diff --git a/clang/lib/AST/OpenACCClause.cpp b/clang/lib/AST/OpenACCClause.cpp index e1db872f25c3..c83128b60e3a 100644 --- a/clang/lib/AST/OpenACCClause.cpp +++ b/clang/lib/AST/OpenACCClause.cpp @@ -15,3 +15,22 @@ #include "clang/AST/ASTContext.h" using namespace clang; + +OpenACCDefaultClause *OpenACCDefaultClause::Create(const ASTContext &C, + OpenACCDefaultClauseKind K, + SourceLocation BeginLoc, + SourceLocation LParenLoc, + SourceLocation EndLoc) { + void *Mem = + C.Allocate(sizeof(OpenACCDefaultClause), alignof(OpenACCDefaultClause)); + + return new (Mem) OpenACCDefaultClause(K, BeginLoc, LParenLoc, EndLoc); +} + +//===----------------------------------------------------------------------===// +// OpenACC clauses printing methods +//===----------------------------------------------------------------------===// +void OpenACCClausePrinter::VisitOpenACCDefaultClause( + const OpenACCDefaultClause &C) { + OS << "default(" << C.getDefaultClauseKind() << ")"; +} diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index bec8bc71f555..be3dd4b673cf 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -2456,7 +2456,12 @@ public: Visit(Clause); } } + void VisitOpenACCDefaultClause(const OpenACCDefaultClause &Clause); }; + +/// Nothing to do here, there are no sub-statements. +void OpenACCClauseProfiler::VisitOpenACCDefaultClause( + const OpenACCDefaultClause &Clause) {} } // namespace void StmtProfiler::VisitOpenACCComputeConstruct( diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp index 431f5d8bdb2b..085a7f51ce99 100644 --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -390,6 +390,17 @@ void TextNodeDumper::Visit(const OpenACCClause *C) { { ColorScope Color(OS, ShowColors, AttrColor); OS << C->getClauseKind(); + + // Handle clauses with parens for types that have no children, likely + // because there is no sub expression. + switch (C->getClauseKind()) { + case OpenACCClauseKind::Default: + OS << '(' << cast(C)->getDefaultClauseKind() << ')'; + break; + default: + // Nothing to do here. + break; + } } dumpPointer(C); dumpSourceRange(SourceRange(C->getBeginLoc(), C->getEndLoc())); diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index f434e1542c80..59a4a5f53467 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -831,9 +831,13 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( ConsumeToken(); - if (getOpenACCDefaultClauseKind(DefKindTok) == - OpenACCDefaultClauseKind::Invalid) + OpenACCDefaultClauseKind DefKind = + getOpenACCDefaultClauseKind(DefKindTok); + + if (DefKind == OpenACCDefaultClauseKind::Invalid) Diag(DefKindTok, diag::err_acc_invalid_default_clause_kind); + else + ParsedClause.setDefaultDetails(DefKind); break; } diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index 2ba1e49b5739..b6afb80b873e 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -39,11 +39,27 @@ bool diagnoseConstructAppertainment(SemaOpenACC &S, OpenACCDirectiveKind K, bool doesClauseApplyToDirective(OpenACCDirectiveKind DirectiveKind, OpenACCClauseKind ClauseKind) { - // FIXME: For each clause as we implement them, we can add the - // 'legalization' list here. - - // Do nothing so we can go to the 'unimplemented' diagnostic instead. - return true; + switch (ClauseKind) { + // FIXME: For each clause as we implement them, we can add the + // 'legalization' list here. + case OpenACCClauseKind::Default: + switch (DirectiveKind) { + case OpenACCDirectiveKind::Parallel: + case OpenACCDirectiveKind::Serial: + case OpenACCDirectiveKind::Kernels: + case OpenACCDirectiveKind::ParallelLoop: + case OpenACCDirectiveKind::SerialLoop: + case OpenACCDirectiveKind::KernelsLoop: + case OpenACCDirectiveKind::Data: + return true; + default: + return false; + } + default: + // Do nothing so we can go to the 'unimplemented' diagnostic instead. + return true; + } + llvm_unreachable("Invalid clause kind"); } } // namespace @@ -63,8 +79,43 @@ SemaOpenACC::ActOnClause(ArrayRef ExistingClauses, return nullptr; } - // TODO OpenACC: Switch over the clauses we implement here and 'create' - // them. + switch (Clause.getClauseKind()) { + case OpenACCClauseKind::Default: { + // Restrictions only properly implemented on 'compute' constructs, and + // 'compute' constructs are the only construct that can do anything with + // this yet, so skip/treat as unimplemented in this case. + if (Clause.getDirectiveKind() != OpenACCDirectiveKind::Parallel && + Clause.getDirectiveKind() != OpenACCDirectiveKind::Serial && + Clause.getDirectiveKind() != OpenACCDirectiveKind::Kernels) + break; + + // Don't add an invalid clause to the AST. + if (Clause.getDefaultClauseKind() == OpenACCDefaultClauseKind::Invalid) + return nullptr; + + // OpenACC 3.3, Section 2.5.4: + // At most one 'default' clause may appear, and it must have a value of + // either 'none' or 'present'. + // Second half of the sentence is diagnosed during parsing. + auto Itr = llvm::find_if(ExistingClauses, [](const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Default; + }); + + if (Itr != ExistingClauses.end()) { + SemaRef.Diag(Clause.getBeginLoc(), + diag::err_acc_duplicate_clause_disallowed) + << Clause.getDirectiveKind() << Clause.getClauseKind(); + SemaRef.Diag((*Itr)->getBeginLoc(), diag::note_acc_previous_clause_here); + return nullptr; + } + + return OpenACCDefaultClause::Create( + getASTContext(), Clause.getDefaultClauseKind(), Clause.getBeginLoc(), + Clause.getLParenLoc(), Clause.getEndLoc()); + } + default: + break; + } Diag(Clause.getBeginLoc(), diag::warn_acc_clause_unimplemented) << Clause.getClauseKind(); diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 79d60588ae53..33a9356e82f4 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -4035,6 +4035,11 @@ private: llvm::SmallVector TransformOpenACCClauseList(OpenACCDirectiveKind DirKind, ArrayRef OldClauses); + + OpenACCClause * + TransformOpenACCClause(ArrayRef ExistingClauses, + OpenACCDirectiveKind DirKind, + const OpenACCClause *OldClause); }; template @@ -11075,13 +11080,44 @@ OMPClause *TreeTransform::TransformOMPXBareClause(OMPXBareClause *C) { //===----------------------------------------------------------------------===// // OpenACC transformation //===----------------------------------------------------------------------===// +template +OpenACCClause *TreeTransform::TransformOpenACCClause( + ArrayRef ExistingClauses, + OpenACCDirectiveKind DirKind, const OpenACCClause *OldClause) { + + SemaOpenACC::OpenACCParsedClause ParsedClause( + DirKind, OldClause->getClauseKind(), OldClause->getBeginLoc()); + ParsedClause.setEndLoc(OldClause->getEndLoc()); + + if (const auto *WithParms = dyn_cast(OldClause)) + ParsedClause.setLParenLoc(WithParms->getLParenLoc()); + + switch (OldClause->getClauseKind()) { + case OpenACCClauseKind::Default: + // There is nothing to do here as nothing dependent can appear in this + // clause. So just set the values so Sema can set the right value. + ParsedClause.setDefaultDetails( + cast(OldClause)->getDefaultClauseKind()); + break; + default: + assert(false && "Unhandled OpenACC clause in TreeTransform"); + return nullptr; + } + + return getSema().OpenACC().ActOnClause(ExistingClauses, ParsedClause); +} + template llvm::SmallVector TreeTransform::TransformOpenACCClauseList( OpenACCDirectiveKind DirKind, ArrayRef OldClauses) { - // TODO OpenACC: Ensure we loop through the list and transform the individual - // clauses. - return {}; + llvm::SmallVector TransformedClauses; + for (const auto *Clause : OldClauses) { + if (OpenACCClause *TransformedClause = getDerived().TransformOpenACCClause( + TransformedClauses, DirKind, Clause)) + TransformedClauses.push_back(TransformedClause); + } + return TransformedClauses; } template diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index fa5bb9f2d543..679302e7a838 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -11763,7 +11763,12 @@ OpenACCClause *ASTRecordReader::readOpenACCClause() { [[maybe_unused]] SourceLocation EndLoc = readSourceLocation(); switch (ClauseKind) { - case OpenACCClauseKind::Default: + case OpenACCClauseKind::Default: { + SourceLocation LParenLoc = readSourceLocation(); + OpenACCDefaultClauseKind DCK = readEnum(); + return OpenACCDefaultClause::Create(getContext(), DCK, BeginLoc, LParenLoc, + EndLoc); + } case OpenACCClauseKind::Finalize: case OpenACCClauseKind::IfPresent: case OpenACCClauseKind::Seq: diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index baf03f69d730..4cd74b1ba9d7 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -7406,7 +7406,12 @@ void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { writeSourceLocation(C->getEndLoc()); switch (C->getClauseKind()) { - case OpenACCClauseKind::Default: + case OpenACCClauseKind::Default: { + const auto *DC = cast(C); + writeSourceLocation(DC->getLParenLoc()); + writeEnum(DC->getDefaultClauseKind()); + return; + } case OpenACCClauseKind::Finalize: case OpenACCClauseKind::IfPresent: case OpenACCClauseKind::Seq: diff --git a/clang/test/ParserOpenACC/parse-clauses.c b/clang/test/ParserOpenACC/parse-clauses.c index b58b332ad324..b363a0cb1362 100644 --- a/clang/test/ParserOpenACC/parse-clauses.c +++ b/clang/test/ParserOpenACC/parse-clauses.c @@ -173,45 +173,37 @@ void DefaultClause() { #pragma acc serial default), seq for(;;){} - // expected-error@+2{{expected identifier}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+1{{expected identifier}} #pragma acc serial default() for(;;){} - // expected-error@+3{{expected identifier}} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{expected identifier}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial default() seq for(;;){} - // expected-error@+3{{expected identifier}} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{expected identifier}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial default(), seq for(;;){} - // expected-error@+2{{invalid value for 'default' clause; expected 'present' or 'none'}} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+1{{invalid value for 'default' clause; expected 'present' or 'none'}} #pragma acc serial default(invalid) for(;;){} - // expected-error@+3{{invalid value for 'default' clause; expected 'present' or 'none'}} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{invalid value for 'default' clause; expected 'present' or 'none'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial default(auto) seq for(;;){} - // expected-error@+3{{invalid value for 'default' clause; expected 'present' or 'none'}} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} + // expected-error@+2{{invalid value for 'default' clause; expected 'present' or 'none'}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial default(invalid), seq for(;;){} - // expected-warning@+1{{OpenACC clause 'default' not yet implemented, clause ignored}} #pragma acc serial default(none) for(;;){} - // expected-warning@+2{{OpenACC clause 'default' not yet implemented, clause ignored}} // expected-warning@+1{{OpenACC clause 'seq' not yet implemented, clause ignored}} #pragma acc serial default(present), seq for(;;){} diff --git a/clang/test/SemaOpenACC/compute-construct-ast.cpp b/clang/test/SemaOpenACC/compute-construct-ast.cpp index 55c080838a18..e632522f877b 100644 --- a/clang/test/SemaOpenACC/compute-construct-ast.cpp +++ b/clang/test/SemaOpenACC/compute-construct-ast.cpp @@ -12,14 +12,16 @@ void NormalFunc() { // CHECK-LABEL: NormalFunc // CHECK-NEXT: CompoundStmt // CHECK-NEXT: OpenACCComputeConstruct {{.*}}parallel + // CHECK-NEXT: default(none) // CHECK-NEXT: CompoundStmt -#pragma acc parallel +#pragma acc parallel default(none) { #pragma acc parallel // CHECK-NEXT: OpenACCComputeConstruct {{.*}}parallel // CHECK-NEXT: OpenACCComputeConstruct {{.*}}parallel + // CHECK-NEXT: default(present) // CHECK-NEXT: CompoundStmt -#pragma acc parallel +#pragma acc parallel default(present) {} } // FIXME: Add a test once we have clauses for this. @@ -50,12 +52,12 @@ void NormalFunc() { template void TemplFunc() { -#pragma acc parallel +#pragma acc parallel default(none) { typename T::type I; } -#pragma acc serial +#pragma acc serial default(present) { typename T::type I; } @@ -72,10 +74,12 @@ void TemplFunc() { // CHECK-NEXT: FunctionDecl // CHECK-NEXT: CompoundStmt // CHECK-NEXT: OpenACCComputeConstruct {{.*}}parallel + // CHECK-NEXT: default(none) // CHECK-NEXT: CompoundStmt // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl{{.*}} I 'typename T::type' // CHECK-NEXT: OpenACCComputeConstruct {{.*}}serial + // CHECK-NEXT: default(present) // CHECK-NEXT: CompoundStmt // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl{{.*}} I 'typename T::type' @@ -91,10 +95,12 @@ void TemplFunc() { // CHECK-NEXT: CXXRecord // CHECK-NEXT: CompoundStmt // CHECK-NEXT: OpenACCComputeConstruct {{.*}}parallel + // CHECK-NEXT: default(none) // CHECK-NEXT: CompoundStmt // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl{{.*}} I 'typename S::type':'int' // CHECK-NEXT: OpenACCComputeConstruct {{.*}}serial + // CHECK-NEXT: default(present) // CHECK-NEXT: CompoundStmt // CHECK-NEXT: DeclStmt // CHECK-NEXT: VarDecl{{.*}} I 'typename S::type':'int' diff --git a/clang/test/SemaOpenACC/compute-construct-clause-ast.cpp b/clang/test/SemaOpenACC/compute-construct-clause-ast.cpp new file mode 100644 index 000000000000..bd8010344502 --- /dev/null +++ b/clang/test/SemaOpenACC/compute-construct-clause-ast.cpp @@ -0,0 +1,74 @@ +// RUN: %clang_cc1 %s -fopenacc -ast-dump | FileCheck %s + +// Test this with PCH. +// RUN: %clang_cc1 %s -fopenacc -emit-pch -o %t %s +// RUN: %clang_cc1 %s -fopenacc -include-pch %t -ast-dump-all | FileCheck %s + +#ifndef PCH_HELPER +#define PCH_HELPER +void NormalFunc() { + // CHECK: FunctionDecl{{.*}}NormalFunc + // CHECK-NEXT: CompoundStmt +#pragma acc parallel default(none) + while(true); + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: default(none) + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: NullStmt + +#pragma acc serial default(present) + while(true); + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}serial + // CHECK-NEXT: default(present) + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: NullStmt +} + +template +void TemplFunc() { + // CHECK: FunctionTemplateDecl{{.*}}TemplFunc + // CHECK-NEXT: TemplateTypeParmDecl + + // Match the prototype: + // CHECK-NEXT: FunctionDecl{{.*}}TemplFunc + // CHECK-NEXT: CompoundStmt + +#pragma acc kernels default(none) + while(true); + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}kernels + // CHECK-NEXT: default(none) + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: NullStmt + +#pragma acc parallel default(present) + while(true); + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: default(present) + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: NullStmt + + // Match the instantiation: + // CHECK: FunctionDecl{{.*}}TemplFunc{{.*}}implicit_instantiation + // CHECK-NEXT: TemplateArgument type 'int' + // CHECK-NEXT: BuiltinType + // CHECK-NEXT: CompoundStmt + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}kernels + // CHECK-NEXT: default(none) + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: NullStmt + // CHECK-NEXT: OpenACCComputeConstruct{{.*}}parallel + // CHECK-NEXT: default(present) + // CHECK-NEXT: WhileStmt + // CHECK-NEXT: CXXBoolLiteralExpr + // CHECK-NEXT: NullStmt +} + +void Instantiate() { + TemplFunc(); +} +#endif diff --git a/clang/test/SemaOpenACC/compute-construct-default-clause.c b/clang/test/SemaOpenACC/compute-construct-default-clause.c new file mode 100644 index 000000000000..b1235fcca1f6 --- /dev/null +++ b/clang/test/SemaOpenACC/compute-construct-default-clause.c @@ -0,0 +1,55 @@ +// RUN: %clang_cc1 %s -fopenacc -verify + +void SingleOnly() { + #pragma acc parallel default(none) + while(0); + + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+2{{OpenACC 'default' clause cannot appear more than once on a 'serial' directive}} + // expected-note@+1{{previous clause is here}} + #pragma acc serial default(present) seq default(none) + while(0); + + // expected-warning@+5{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+4{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+2{{OpenACC 'default' clause cannot appear more than once on a 'kernels' directive}} + // expected-note@+1{{previous clause is here}} + #pragma acc kernels seq default(present) seq default(none) seq + while(0); + + // expected-warning@+6{{OpenACC construct 'parallel loop' not yet implemented}} + // expected-warning@+5{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+4{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+2{{OpenACC clause 'default' not yet implemented}} + // expected-warning@+1{{OpenACC clause 'default' not yet implemented}} + #pragma acc parallel loop seq default(present) seq default(none) seq + while(0); + + // expected-warning@+3{{OpenACC construct 'serial loop' not yet implemented}} + // expected-warning@+2{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+1{{expected '('}} + #pragma acc serial loop seq default seq default(none) seq + while(0); + + // expected-warning@+2{{OpenACC construct 'kernels loop' not yet implemented}} + // expected-warning@+1{{OpenACC clause 'default' not yet implemented}} + #pragma acc kernels loop default(none) + while(0); + + // expected-warning@+2{{OpenACC construct 'data' not yet implemented}} + // expected-warning@+1{{OpenACC clause 'default' not yet implemented}} + #pragma acc data default(none) + while(0); + + // expected-warning@+2{{OpenACC construct 'loop' not yet implemented}} + // expected-error@+1{{OpenACC 'default' clause is not valid on 'loop' directive}} + #pragma acc loop default(none) + while(0); + + // expected-warning@+2{{OpenACC construct 'wait' not yet implemented}} + // expected-error@+1{{OpenACC 'default' clause is not valid on 'wait' directive}} + #pragma acc wait default(none) + while(0); +} diff --git a/clang/test/SemaOpenACC/compute-construct-default-clause.cpp b/clang/test/SemaOpenACC/compute-construct-default-clause.cpp new file mode 100644 index 000000000000..2c3e711ffd08 --- /dev/null +++ b/clang/test/SemaOpenACC/compute-construct-default-clause.cpp @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 %s -fopenacc -verify + +template +void SingleOnly() { + #pragma acc parallel default(none) + while(false); + + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+2{{OpenACC 'default' clause cannot appear more than once on a 'parallel' directive}} + // expected-note@+1{{previous clause is here}} + #pragma acc parallel default(present) seq default(none) + while(false); + + // expected-warning@+5{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+4{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+2{{OpenACC 'default' clause cannot appear more than once on a 'serial' directive}} + // expected-note@+1{{previous clause is here}} + #pragma acc serial seq default(present) seq default(none) seq + while(false); + + // expected-warning@+5{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+4{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+2{{OpenACC 'default' clause cannot appear more than once on a 'kernels' directive}} + // expected-note@+1{{previous clause is here}} + #pragma acc kernels seq default(present) seq default(none) seq + while(false); + + // expected-warning@+3{{OpenACC clause 'seq' not yet implemented}} + // expected-warning@+2{{OpenACC clause 'seq' not yet implemented}} + // expected-error@+1{{expected '('}} + #pragma acc parallel seq default(none) seq default seq + while(false); +} + +void Instantiate() { + SingleOnly(); +} -- GitLab From 5ae9ffbd18fd93edbbc8efebe140aeb24cd763c2 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Wed, 10 Apr 2024 07:16:52 -0700 Subject: [PATCH 398/695] [RISCV] Address review comment from 88062 As pointed out by Fraser, KillSrcReg is always false at this point in code, and having the inconcistency on whether we check the flag between the if and else blocks is confusing. --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 46e79272d60e..84af6eec40ee 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -210,8 +210,7 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB, unsigned Opc = NumOfVReg == 2 ? RISCV::SH1ADD : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD); BuildMI(MBB, II, DL, TII->get(Opc), DestReg) - .addReg(ScratchReg, RegState::Kill) - .addReg(SrcReg, getKillRegState(KillSrcReg)) + .addReg(ScratchReg, RegState::Kill).addReg(SrcReg) .setMIFlag(Flag); } else { TII->mulImm(MF, MBB, II, DL, ScratchReg, NumOfVReg, Flag); -- GitLab From a8f9f85ab0114deb0f6adae2b578bc39c62c19b3 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Apr 2024 10:00:48 -0500 Subject: [PATCH 399/695] [Libomptarget][NFC] Fix unused variable warnings Summary: This patch fixes a few warnings that would show up while building. --- openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp | 4 ++-- openmp/libomptarget/src/interface.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp index a0fdde951b74..00650b801b42 100644 --- a/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp @@ -1885,8 +1885,8 @@ struct AMDGPUDeviceTy : public GenericDeviceTy, AMDGenericDeviceTy { // Get the frequency of the steady clock. If the attribute is missing // assume running on an older libhsa and default to 0, omp_get_wtime // will be inaccurate but otherwise programs can still run. - if (auto Err = getDeviceAttrRaw(HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY, - ClockFrequency)) + if (getDeviceAttrRaw(HSA_AMD_AGENT_INFO_TIMESTAMP_FREQUENCY, + ClockFrequency) != HSA_STATUS_SUCCESS) ClockFrequency = 0; // Load the grid values dependending on the wavefront. diff --git a/openmp/libomptarget/src/interface.cpp b/openmp/libomptarget/src/interface.cpp index b562ba8818c3..557703632c62 100644 --- a/openmp/libomptarget/src/interface.cpp +++ b/openmp/libomptarget/src/interface.cpp @@ -495,7 +495,7 @@ EXTERN void __tgt_target_nowait_query(void **AsyncHandle) { if (QueryCounter.isAboveThreshold()) AsyncInfo->SyncType = AsyncInfoTy::SyncTy::BLOCKING; - if (const int Rc = AsyncInfo->synchronize()) + if (AsyncInfo->synchronize()) FATAL_MESSAGE0(1, "Error while querying the async queue for completion.\n"); // If there are device operations still pending, return immediately without // deallocating the handle and increase the current thread query count. -- GitLab From 2bf48892ab0ce5d53126c7b114070bba18521501 Mon Sep 17 00:00:00 2001 From: "Yaxun (Sam) Liu" Date: Wed, 10 Apr 2024 11:16:00 -0400 Subject: [PATCH 400/695] [HIP] document difference with CUDA (#86838) --- clang/docs/HIPSupport.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/clang/docs/HIPSupport.rst b/clang/docs/HIPSupport.rst index 543c82cf9024..5ba84c2f6705 100644 --- a/clang/docs/HIPSupport.rst +++ b/clang/docs/HIPSupport.rst @@ -208,6 +208,20 @@ Host Code Compilation - These relocatable objects are then linked together. - Host code within a TU can call host functions and launch kernels from another TU. +Syntax Difference with CUDA +=========================== + +Clang's front end, used for both CUDA and HIP programming models, shares the same parsing and semantic analysis mechanisms. This includes the resolution of overloads concerning device and host functions. While there exists a comprehensive documentation on the syntax differences between Clang and NVCC for CUDA at `Dialect Differences Between Clang and NVCC `_, it is important to note that these differences also apply to HIP code compilation. + +Predefined Macros for Differentiation +------------------------------------- + +To facilitate differentiation between HIP and CUDA code, as well as between device and host compilations within HIP, Clang defines specific macros: + +- ``__HIP__`` : This macro is defined only when compiling HIP code. It can be used to conditionally compile code specific to HIP, enabling developers to write portable code that can be compiled for both CUDA and HIP. + +- ``__HIP_DEVICE_COMPILE__`` : Defined exclusively during HIP device compilation, this macro allows for conditional compilation of device-specific code. It provides a mechanism to segregate device and host code, ensuring that each can be optimized for their respective execution environments. + Function Pointers Support ========================= -- GitLab From 6ca5a410d26262f06f954e91200eefe0cbfb7fb8 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 10 Apr 2024 08:16:43 -0700 Subject: [PATCH 401/695] [SLP]Fix PR87358: broken module, Instruction does not dominate all uses. If the first node is a gather node with extractelement instructions, still need to put the vector value after all instructions, not after the very first one. --- .../lib/Transforms/Vectorize/SLPVectorizer.cpp | 10 +++++++--- .../X86/extractlements-gathered-first-node.ll | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 22ef9b5fb994..6b758f63a796 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -10736,9 +10736,13 @@ Instruction &BoUpSLP::getLastInstructionInBundle(const TreeEntry *E) { [](Value *V) { return !isa(V) && isa(V); })) || - all_of(E->Scalars, [](Value *V) { - return !isVectorLikeInstWithConstOps(V) && isUsedOutsideBlock(V); - })) + all_of(E->Scalars, + [](Value *V) { + return !isVectorLikeInstWithConstOps(V) && + isUsedOutsideBlock(V); + }) || + (E->State == TreeEntry::NeedToGather && E->Idx == 0 && + all_of(E->Scalars, IsaPred))) Res.second = FindLastInst(); else Res.second = FindFirstInst(); diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll new file mode 100644 index 000000000000..57fa83b1ccdd --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/extractlements-gathered-first-node.ll @@ -0,0 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -slp-threshold=-99999 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + +define void @test() { +; CHECK-LABEL: define void @test() { +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> zeroinitializer, i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> zeroinitializer, i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> , i32 [[TMP1]], i32 1 +; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i32 [[TMP0]], [[TMP1]] +; CHECK-NEXT: ret void +; +bb: + %0 = extractelement <4 x i32> zeroinitializer, i32 0 + %1 = extractelement <2 x i32> zeroinitializer, i32 0 + %icmp = icmp ult i32 %0, %1 + ret void +} -- GitLab From 7f1b9adfc8d86c77ee87a268b3d30e0eda8ed493 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Apr 2024 08:39:56 -0700 Subject: [PATCH 402/695] [RISCV] Add MachineCombiner to fold (sh3add Z, (add X, (slli Y, 6))) -> (sh3add (sh3add Y, Z), X). (#87884) This improves a pattern that occurs in 531.deepsjeng_r. Reducing the dynamic instruction count by 0.5%. This may be possible to improve in SelectionDAG, but given the special cases around shXadd formation, it's not obvious it can be done in a robust way without adding multiple special cases. I've used a GEP with 2 indices because that mostly closely resembles the motivating case. Most of the test cases are the simplest GEP case. One test has a logical right shift on an index which is closer to the deepsjeng code. This requires special handling in isel to reverse a DAGCombiner canonicalization that turns a pair of shifts into (srl (and X, C1), C2). --- .../llvm/CodeGen/MachineCombinerPattern.h | 2 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 151 ++++++++++++++++++ llvm/test/CodeGen/RISCV/rv64zba.ll | 40 ++--- 3 files changed, 169 insertions(+), 24 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h index 89eed7463bd7..41b73eaae029 100644 --- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h +++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h @@ -175,6 +175,8 @@ enum class MachineCombinerPattern { FMADD_XA, FMSUB, FNMSUB, + SHXADD_ADD_SLLI_OP1, + SHXADD_ADD_SLLI_OP2, // X86 VNNI DPWSSD, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index be63bc936ae8..6b75efe684d9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1775,6 +1775,86 @@ static bool getFPPatterns(MachineInstr &Root, return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce); } +/// Utility routine that checks if \param MO is defined by an +/// \param CombineOpc instruction in the basic block \param MBB +static const MachineInstr *canCombine(const MachineBasicBlock &MBB, + const MachineOperand &MO, + unsigned CombineOpc) { + const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); + const MachineInstr *MI = nullptr; + + if (MO.isReg() && MO.getReg().isVirtual()) + MI = MRI.getUniqueVRegDef(MO.getReg()); + // And it needs to be in the trace (otherwise, it won't have a depth). + if (!MI || MI->getParent() != &MBB || MI->getOpcode() != CombineOpc) + return nullptr; + // Must only used by the user we combine with. + if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg())) + return nullptr; + + return MI; +} + +/// Utility routine that checks if \param MO is defined by a SLLI in \param +/// MBB that can be combined by splitting across 2 SHXADD instructions. The +/// first SHXADD shift amount is given by \param OuterShiftAmt. +static bool canCombineShiftIntoShXAdd(const MachineBasicBlock &MBB, + const MachineOperand &MO, + unsigned OuterShiftAmt) { + const MachineInstr *ShiftMI = canCombine(MBB, MO, RISCV::SLLI); + if (!ShiftMI) + return false; + + unsigned InnerShiftAmt = ShiftMI->getOperand(2).getImm(); + if (InnerShiftAmt < OuterShiftAmt || (InnerShiftAmt - OuterShiftAmt) > 3) + return false; + + return true; +} + +// Returns the shift amount from a SHXADD instruction. Returns 0 if the +// instruction is not a SHXADD. +static unsigned getSHXADDShiftAmount(unsigned Opc) { + switch (Opc) { + default: + return 0; + case RISCV::SH1ADD: + return 1; + case RISCV::SH2ADD: + return 2; + case RISCV::SH3ADD: + return 3; + } +} + +// Look for opportunities to combine (sh3add Z, (add X, (slli Y, 5))) into +// (sh3add (sh2add Y, Z), X). +static bool +getSHXADDPatterns(const MachineInstr &Root, + SmallVectorImpl &Patterns) { + unsigned ShiftAmt = getSHXADDShiftAmount(Root.getOpcode()); + if (!ShiftAmt) + return false; + + const MachineBasicBlock &MBB = *Root.getParent(); + + const MachineInstr *AddMI = canCombine(MBB, Root.getOperand(2), RISCV::ADD); + if (!AddMI) + return false; + + bool Found = false; + if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(1), ShiftAmt)) { + Patterns.push_back(MachineCombinerPattern::SHXADD_ADD_SLLI_OP1); + Found = true; + } + if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(2), ShiftAmt)) { + Patterns.push_back(MachineCombinerPattern::SHXADD_ADD_SLLI_OP2); + Found = true; + } + + return Found; +} + bool RISCVInstrInfo::getMachineCombinerPatterns( MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const { @@ -1782,6 +1862,9 @@ bool RISCVInstrInfo::getMachineCombinerPatterns( if (getFPPatterns(Root, Patterns, DoRegPressureReduce)) return true; + if (getSHXADDPatterns(Root, Patterns)) + return true; + return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns, DoRegPressureReduce); } @@ -1864,6 +1947,68 @@ static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev, DelInstrs.push_back(&Root); } +// Combine patterns like (sh3add Z, (add X, (slli Y, 5))) to +// (sh3add (sh2add Y, Z), X) if the shift amount can be split across two +// shXadd instructions. The outer shXadd keeps its original opcode. +static void +genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx, + SmallVectorImpl &InsInstrs, + SmallVectorImpl &DelInstrs, + DenseMap &InstrIdxForVirtReg) { + MachineFunction *MF = Root.getMF(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); + + unsigned OuterShiftAmt = getSHXADDShiftAmount(Root.getOpcode()); + assert(OuterShiftAmt != 0 && "Unexpected opcode"); + + MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); + MachineInstr *ShiftMI = + MRI.getUniqueVRegDef(AddMI->getOperand(AddOpIdx).getReg()); + + unsigned InnerShiftAmt = ShiftMI->getOperand(2).getImm(); + assert(InnerShiftAmt > OuterShiftAmt && "Unexpected shift amount"); + + unsigned InnerOpc; + switch (InnerShiftAmt - OuterShiftAmt) { + default: + llvm_unreachable("Unexpected shift amount"); + case 0: + InnerOpc = RISCV::ADD; + break; + case 1: + InnerOpc = RISCV::SH1ADD; + break; + case 2: + InnerOpc = RISCV::SH2ADD; + break; + case 3: + InnerOpc = RISCV::SH3ADD; + break; + } + + const MachineOperand &X = AddMI->getOperand(3 - AddOpIdx); + const MachineOperand &Y = ShiftMI->getOperand(1); + const MachineOperand &Z = Root.getOperand(1); + + Register NewVR = MRI.createVirtualRegister(&RISCV::GPRRegClass); + + auto MIB1 = BuildMI(*MF, MIMetadata(Root), TII->get(InnerOpc), NewVR) + .addReg(Y.getReg(), getKillRegState(Y.isKill())) + .addReg(Z.getReg(), getKillRegState(Z.isKill())); + auto MIB2 = BuildMI(*MF, MIMetadata(Root), TII->get(Root.getOpcode()), + Root.getOperand(0).getReg()) + .addReg(NewVR, RegState::Kill) + .addReg(X.getReg(), getKillRegState(X.isKill())); + + InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); + InsInstrs.push_back(MIB1); + InsInstrs.push_back(MIB2); + DelInstrs.push_back(ShiftMI); + DelInstrs.push_back(AddMI); + DelInstrs.push_back(&Root); +} + void RISCVInstrInfo::genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl &InsInstrs, @@ -1887,6 +2032,12 @@ void RISCVInstrInfo::genAlternativeCodeSequence( combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs); return; } + case MachineCombinerPattern::SHXADD_ADD_SLLI_OP1: + genShXAddAddShift(Root, 1, InsInstrs, DelInstrs, InstrIdxForVirtReg); + return; + case MachineCombinerPattern::SHXADD_ADD_SLLI_OP2: + genShXAddAddShift(Root, 2, InsInstrs, DelInstrs, InstrIdxForVirtReg); + return; } } diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index 7e32253c8653..067addc819f7 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -1404,9 +1404,8 @@ define i64 @sh6_sh3_add2(i64 noundef %x, i64 noundef %y, i64 noundef %z) { ; ; RV64ZBA-LABEL: sh6_sh3_add2: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: slli a1, a1, 6 -; RV64ZBA-NEXT: add a0, a1, a0 -; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: sh3add a1, a1, a2 +; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: ret entry: %shl = shl i64 %z, 3 @@ -2111,9 +2110,8 @@ define i64 @array_index_sh1_sh3(ptr %p, i64 %idx1, i64 %idx2) { ; ; RV64ZBA-LABEL: array_index_sh1_sh3: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: slli a1, a1, 4 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: sh1add a1, a1, a2 +; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: ld a0, 0(a0) ; RV64ZBA-NEXT: ret %a = getelementptr inbounds [2 x i64], ptr %p, i64 %idx1, i64 %idx2 @@ -2174,9 +2172,8 @@ define i32 @array_index_sh2_sh2(ptr %p, i64 %idx1, i64 %idx2) { ; ; RV64ZBA-LABEL: array_index_sh2_sh2: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: slli a1, a1, 4 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh2add a0, a2, a0 +; RV64ZBA-NEXT: sh2add a1, a1, a2 +; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: lw a0, 0(a0) ; RV64ZBA-NEXT: ret %a = getelementptr inbounds [4 x i32], ptr %p, i64 %idx1, i64 %idx2 @@ -2196,9 +2193,8 @@ define i64 @array_index_sh2_sh3(ptr %p, i64 %idx1, i64 %idx2) { ; ; RV64ZBA-LABEL: array_index_sh2_sh3: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: slli a1, a1, 5 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: sh2add a1, a1, a2 +; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: ld a0, 0(a0) ; RV64ZBA-NEXT: ret %a = getelementptr inbounds [4 x i64], ptr %p, i64 %idx1, i64 %idx2 @@ -2238,9 +2234,8 @@ define i16 @array_index_sh3_sh1(ptr %p, i64 %idx1, i64 %idx2) { ; ; RV64ZBA-LABEL: array_index_sh3_sh1: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: slli a1, a1, 4 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh1add a0, a2, a0 +; RV64ZBA-NEXT: sh3add a1, a1, a2 +; RV64ZBA-NEXT: sh1add a0, a1, a0 ; RV64ZBA-NEXT: lh a0, 0(a0) ; RV64ZBA-NEXT: ret %a = getelementptr inbounds [8 x i16], ptr %p, i64 %idx1, i64 %idx2 @@ -2260,9 +2255,8 @@ define i32 @array_index_sh3_sh2(ptr %p, i64 %idx1, i64 %idx2) { ; ; RV64ZBA-LABEL: array_index_sh3_sh2: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: slli a1, a1, 5 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh2add a0, a2, a0 +; RV64ZBA-NEXT: sh3add a1, a1, a2 +; RV64ZBA-NEXT: sh2add a0, a1, a0 ; RV64ZBA-NEXT: lw a0, 0(a0) ; RV64ZBA-NEXT: ret %a = getelementptr inbounds [8 x i32], ptr %p, i64 %idx1, i64 %idx2 @@ -2282,9 +2276,8 @@ define i64 @array_index_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) { ; ; RV64ZBA-LABEL: array_index_sh3_sh3: ; RV64ZBA: # %bb.0: -; RV64ZBA-NEXT: slli a1, a1, 6 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: sh3add a1, a1, a2 +; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: ld a0, 0(a0) ; RV64ZBA-NEXT: ret %a = getelementptr inbounds [8 x i64], ptr %p, i64 %idx1, i64 %idx2 @@ -2308,9 +2301,8 @@ define i64 @array_index_lshr_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) { ; RV64ZBA-LABEL: array_index_lshr_sh3_sh3: ; RV64ZBA: # %bb.0: ; RV64ZBA-NEXT: srli a1, a1, 58 -; RV64ZBA-NEXT: slli a1, a1, 6 -; RV64ZBA-NEXT: add a0, a0, a1 -; RV64ZBA-NEXT: sh3add a0, a2, a0 +; RV64ZBA-NEXT: sh3add a1, a1, a2 +; RV64ZBA-NEXT: sh3add a0, a1, a0 ; RV64ZBA-NEXT: ld a0, 0(a0) ; RV64ZBA-NEXT: ret %shr = lshr i64 %idx1, 58 -- GitLab From f9f4aba547f50e6dcb2d9345b51fe4883bb64d8d Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Tue, 9 Apr 2024 12:45:05 -0500 Subject: [PATCH 403/695] [InstCombine] Add tests for non-zero/knownbits of `vector_reduce_{s,u}{min,max}`; NFC --- .../vector-reduce-min-max-known.ll | 295 ++++++++++++++++++ 1 file changed, 295 insertions(+) create mode 100644 llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll diff --git a/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll b/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll new file mode 100644 index 000000000000..a02ebcca8090 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll @@ -0,0 +1,295 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -passes=instcombine -S | FileCheck %s + +define i1 @vec_reduce_umax_non_zero(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umax_non_zero( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nuw <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_umax_non_zero_fail(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umax_non_zero_fail( +; CHECK-NEXT: [[X:%.*]] = add nsw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nsw <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_umin_non_zero(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umin_non_zero( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nuw <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_umin_non_zero_fail(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umin_non_zero_fail( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nuw <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_smax_non_zero0(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smax_non_zero0( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nuw <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_smax_non_zero1(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smax_non_zero1( +; CHECK-NEXT: [[X0:%.*]] = and <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[X0]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <4 x i8> %xx, + %x = or <4 x i8> %x0, + %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_smax_non_zero_fail(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smax_non_zero_fail( +; CHECK-NEXT: [[X0:%.*]] = and <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[X0]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <4 x i8> %xx, + %x = add nuw <4 x i8> %x0, + %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_smin_non_zero0(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smin_non_zero0( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nuw <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_smin_non_zero1(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smin_non_zero1( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i1 @vec_reduce_smin_non_zero_fail(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smin_non_zero_fail( +; CHECK-NEXT: [[X0:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[X:%.*]] = add <4 x i8> [[X0]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = or <4 x i8> %xx, + %x = add <4 x i8> %x0, + %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) + %r = icmp eq i8 %v, 0 + ret i1 %r +} + +define i8 @vec_reduce_umax_known0(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umax_known0( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = and i8 %v, 1 + ret i8 %r +} + +define i8 @vec_reduce_umax_known1(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umax_known1( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], -128 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = and i8 %v, 128 + ret i8 %r +} + +define i8 @vec_reduce_umax_known_fail0(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umax_known_fail0( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = and i8 %v, 1 + ret i8 %r +} + +define i8 @vec_reduce_umax_known_fail1(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umax_known_fail1( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = and i8 %v, 1 + ret i8 %r +} + +define i8 @vec_reduce_umin_known0(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umin_known0( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) + %r = and i8 %v, 1 + ret i8 %r +} + +define i8 @vec_reduce_umin_known1(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umin_known1( +; CHECK-NEXT: [[X:%.*]] = and <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], -128 +; CHECK-NEXT: ret i8 [[R]] +; + %x = and <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) + %r = and i8 %v, 128 + ret i8 %r +} + +define i8 @vec_reduce_umin_known_fail0(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umin_known_fail0( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 +; CHECK-NEXT: ret i8 [[R]] +; + %x0 = and <4 x i8> %xx, + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) + %r = and i8 %v, 1 + ret i8 %r +} + +define i8 @vec_reduce_umin_known_fail1(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_umin_known_fail1( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) + %r = and i8 %v, 1 + ret i8 %r +} + +define i8 @vec_reduce_smax_known(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smax_known( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 4 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x) + %r = and i8 %v, 4 + ret i8 %r +} + +define i8 @vec_reduce_smax_known_fail(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smax_known_fail( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 4 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) + %r = and i8 %v, 4 + ret i8 %r +} + +define i8 @vec_reduce_smin_known(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smin_known( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 8 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) + %r = and i8 %v, 8 + ret i8 %r +} + +define i8 @vec_reduce_smin_known_fail(<4 x i8> %xx) { +; CHECK-LABEL: @vec_reduce_smin_known_fail( +; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) +; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 8 +; CHECK-NEXT: ret i8 [[R]] +; + %x = or <4 x i8> %xx, + %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) + %r = and i8 %v, 8 + ret i8 %r +} -- GitLab From 77d668451ad2e6370eb595c171779429e9becdf2 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Tue, 9 Apr 2024 11:58:38 -0500 Subject: [PATCH 404/695] [ValueTracking] Add support for `vector_reduce_{s,u}{min,max}` in `isKnownNonZero` Previously missing, proofs for all implementations: https://alive2.llvm.org/ce/z/G8wpmG --- llvm/lib/Analysis/ValueTracking.cpp | 6 ++++++ .../InstCombine/vector-reduce-min-max-known.ll | 15 +++------------ 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index ca48cfe77381..869a94d81f4d 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2824,6 +2824,12 @@ static bool isKnownNonZeroFromOperator(const Operator *I, return isNonZeroAdd(DemandedElts, Depth, Q, BitWidth, II->getArgOperand(0), II->getArgOperand(1), /*NSW=*/true, /* NUW=*/false); + // umin/smin/smax/smin of all non-zero elements is always non-zero. + case Intrinsic::vector_reduce_umax: + case Intrinsic::vector_reduce_umin: + case Intrinsic::vector_reduce_smax: + case Intrinsic::vector_reduce_smin: + return isKnownNonZero(II->getArgOperand(0), Depth, Q); case Intrinsic::umax: case Intrinsic::uadd_sat: return isKnownNonZero(II->getArgOperand(1), DemandedElts, Depth, Q) || diff --git a/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll b/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll index a02ebcca8090..29c08b17ef88 100644 --- a/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll +++ b/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll @@ -29,10 +29,7 @@ define i1 @vec_reduce_umax_non_zero_fail(<4 x i8> %xx) { define i1 @vec_reduce_umin_non_zero(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_umin_non_zero( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x = add nuw <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) @@ -55,10 +52,7 @@ define i1 @vec_reduce_umin_non_zero_fail(<4 x i8> %xx) { define i1 @vec_reduce_smax_non_zero0(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_smax_non_zero0( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x = add nuw <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x) @@ -98,10 +92,7 @@ define i1 @vec_reduce_smax_non_zero_fail(<4 x i8> %xx) { define i1 @vec_reduce_smin_non_zero0(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_smin_non_zero0( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x = add nuw <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) -- GitLab From 41c52217b003ce9435ae534251b0d0d035495262 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Tue, 9 Apr 2024 11:58:48 -0500 Subject: [PATCH 405/695] [ValueTracking] Add support for `vector_reduce_{s,u}{min,max}` in `computeKnownBits` Previously missing. We compute by just applying the reduce function on the knownbits of each element. Closes #88169 --- llvm/lib/Analysis/ValueTracking.cpp | 8 ++++++++ .../vector-reduce-min-max-known.ll | 20 ++++--------------- 2 files changed, 12 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 869a94d81f4d..4120876889de 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -1621,6 +1621,14 @@ static void computeKnownBitsFromOperator(const Operator *I, computeKnownBits(I->getOperand(1), Known2, Depth + 1, Q); Known = KnownBits::ssub_sat(Known, Known2); break; + // for min/max reduce, any bit common to each element in the input vec + // is set in the output. + case Intrinsic::vector_reduce_umax: + case Intrinsic::vector_reduce_umin: + case Intrinsic::vector_reduce_smax: + case Intrinsic::vector_reduce_smin: + computeKnownBits(I->getOperand(0), Known, Depth + 1, Q); + break; case Intrinsic::umin: computeKnownBits(I->getOperand(0), Known, Depth + 1, Q); computeKnownBits(I->getOperand(1), Known2, Depth + 1, Q); diff --git a/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll b/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll index 29c08b17ef88..65d000835326 100644 --- a/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll +++ b/llvm/test/Transforms/InstCombine/vector-reduce-min-max-known.ll @@ -130,10 +130,7 @@ define i1 @vec_reduce_smin_non_zero_fail(<4 x i8> %xx) { define i8 @vec_reduce_umax_known0(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_umax_known0( -; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umax.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 -; CHECK-NEXT: ret i8 [[R]] +; CHECK-NEXT: ret i8 1 ; %x = or <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.umax(<4 x i8> %x) @@ -182,10 +179,7 @@ define i8 @vec_reduce_umax_known_fail1(<4 x i8> %xx) { define i8 @vec_reduce_umin_known0(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_umin_known0( -; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.umin.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 1 -; CHECK-NEXT: ret i8 [[R]] +; CHECK-NEXT: ret i8 1 ; %x = or <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.umin(<4 x i8> %x) @@ -235,10 +229,7 @@ define i8 @vec_reduce_umin_known_fail1(<4 x i8> %xx) { define i8 @vec_reduce_smax_known(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_smax_known( -; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smax.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 4 -; CHECK-NEXT: ret i8 [[R]] +; CHECK-NEXT: ret i8 4 ; %x = or <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.smax(<4 x i8> %x) @@ -261,10 +252,7 @@ define i8 @vec_reduce_smax_known_fail(<4 x i8> %xx) { define i8 @vec_reduce_smin_known(<4 x i8> %xx) { ; CHECK-LABEL: @vec_reduce_smin_known( -; CHECK-NEXT: [[X:%.*]] = or <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[X]]) -; CHECK-NEXT: [[R:%.*]] = and i8 [[V]], 8 -; CHECK-NEXT: ret i8 [[R]] +; CHECK-NEXT: ret i8 8 ; %x = or <4 x i8> %xx, %v = call i8 @llvm.vector.reduce.smin(<4 x i8> %x) -- GitLab From a02b3c01820090d4208146b51372587251fdce61 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:36:35 -0500 Subject: [PATCH 406/695] [ValueTracking] Add tests for overflow detection functions is `isKnownNonZero`; NFC --- .../test/Transforms/InstCombine/known-bits.ll | 381 ++++++++++++++++++ 1 file changed, 381 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll index 769f7661fc8d..ddd5970ccabd 100644 --- a/llvm/test/Transforms/InstCombine/known-bits.ll +++ b/llvm/test/Transforms/InstCombine/known-bits.ll @@ -630,5 +630,386 @@ define i8 @or_ne_bits_must_be_unset2_fail(i8 %x, i8 %y) { ret i8 %r } +declare void @use.i1(i1) +declare void @use.i8(i8) + +declare void @use.2xi1(<2 x i1>) + +define i1 @extract_value_uadd(<2 x i8> %xx, <2 x i8> %yy) { +; CHECK-LABEL: @extract_value_uadd( +; CHECK-NEXT: [[X0:%.*]] = and <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y0:%.*]] = and <2 x i8> [[YY:%.*]], +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], +; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 +; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) +; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i64 0 +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <2 x i8> %xx, + %y0 = and <2 x i8> %yy, + %x = add nuw <2 x i8> %x0, + %y = add nuw <2 x i8> %y0, + + %add_uov = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow(<2 x i8> %x, <2 x i8> %y) + %add = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 0 + %uov = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 1 + call void @use.2xi1(<2 x i1> %uov) + %add_ele = extractelement <2 x i8> %add, i32 0 + %r = icmp eq i8 %add_ele, 0 + ret i1 %r +} + +define i1 @extract_value_uadd2(<2 x i8> %xx, <2 x i8> %yy) { +; CHECK-LABEL: @extract_value_uadd2( +; CHECK-NEXT: [[X0:%.*]] = and <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y0:%.*]] = and <2 x i8> [[YY:%.*]], +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], +; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 +; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) +; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i64 1 +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <2 x i8> %xx, + %y0 = and <2 x i8> %yy, + %x = add nuw <2 x i8> %x0, + %y = add nuw <2 x i8> %y0, + + %add_uov = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow(<2 x i8> %x, <2 x i8> %y) + %add = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 0 + %uov = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 1 + call void @use.2xi1(<2 x i1> %uov) + %add_ele = extractelement <2 x i8> %add, i32 1 + %r = icmp eq i8 %add_ele, 0 + ret i1 %r +} + +define i1 @extract_value_uadd_fail(<2 x i8> %xx, <2 x i8> %yy) { +; CHECK-LABEL: @extract_value_uadd_fail( +; CHECK-NEXT: [[X0:%.*]] = and <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y0:%.*]] = and <2 x i8> [[YY:%.*]], +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], +; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 +; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) +; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i64 1 +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <2 x i8> %xx, + %y0 = and <2 x i8> %yy, + %x = add nuw <2 x i8> %x0, + %y = add nuw <2 x i8> %y0, + + %add_uov = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow(<2 x i8> %x, <2 x i8> %y) + %add = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 0 + %uov = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 1 + call void @use.2xi1(<2 x i1> %uov) + %add_ele = extractelement <2 x i8> %add, i32 1 + %r = icmp eq i8 %add_ele, 0 + ret i1 %r +} + +define i1 @extract_value_uadd_fail2(<2 x i8> %xx, <2 x i8> %yy, i32 %idx) { +; CHECK-LABEL: @extract_value_uadd_fail2( +; CHECK-NEXT: [[X0:%.*]] = and <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y0:%.*]] = and <2 x i8> [[YY:%.*]], +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], +; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 +; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) +; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i32 [[IDX:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <2 x i8> %xx, + %y0 = and <2 x i8> %yy, + %x = add nuw <2 x i8> %x0, + %y = add nuw <2 x i8> %y0, + + %add_uov = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow(<2 x i8> %x, <2 x i8> %y) + %add = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 0 + %uov = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 1 + call void @use.2xi1(<2 x i1> %uov) + %add_ele = extractelement <2 x i8> %add, i32 %idx + %r = icmp eq i8 %add_ele, 0 + ret i1 %r +} + +define i1 @extract_value_uadd_fail3(<2 x i8> %xx, <2 x i8> %yy) { +; CHECK-LABEL: @extract_value_uadd_fail3( +; CHECK-NEXT: [[X0:%.*]] = and <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y0:%.*]] = and <2 x i8> [[YY:%.*]], +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], +; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 +; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) +; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i64 0 +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and <2 x i8> %xx, + %y0 = and <2 x i8> %yy, + %x = add nuw <2 x i8> %x0, + %y = add nuw <2 x i8> %y0, + + %add_uov = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow(<2 x i8> %x, <2 x i8> %y) + %add = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 0 + %uov = extractvalue { <2 x i8>, <2 x i1> } %add_uov, 1 + call void @use.2xi1(<2 x i1> %uov) + %add_ele = extractelement <2 x i8> %add, i32 0 + %r = icmp eq i8 %add_ele, 0 + ret i1 %r +} + +define i1 @extract_value_sadd(i8 %xx, i8 %yy) { +; CHECK-LABEL: @extract_value_sadd( +; CHECK-NEXT: [[X:%.*]] = add nuw i8 [[XX:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[X_LEMMA:%.*]] = icmp sgt i8 [[X]], -1 +; CHECK-NEXT: [[Y_LEMMA:%.*]] = icmp sgt i8 [[Y]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[X_LEMMA]]) +; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LEMMA]]) +; CHECK-NEXT: [[ADD_SOV:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { i8, i1 } [[ADD_SOV]], 0 +; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[ADD_SOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nuw i8 %xx, 1 + %y = add nuw i8 %yy, 1 + %x_lemma = icmp ult i8 %x, 128 + %y_lemma = icmp ult i8 %y, 128 + call void @llvm.assume(i1 %x_lemma) + call void @llvm.assume(i1 %y_lemma) + + %add_sov = call { i8, i1 } @llvm.sadd.with.overflow(i8 %x, i8 %y) + %add = extractvalue { i8, i1 } %add_sov, 0 + %sov = extractvalue { i8, i1 } %add_sov, 1 + call void @use.i1(i1 %sov) + %r = icmp eq i8 %add, 0 + ret i1 %r +} + +define i1 @extract_value_sadd_fail(i8 %xx, i8 %yy) { +; CHECK-LABEL: @extract_value_sadd_fail( +; CHECK-NEXT: [[X:%.*]] = add i8 [[XX:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[ADD_SOV:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: [[ADD:%.*]] = extractvalue { i8, i1 } [[ADD_SOV]], 0 +; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[ADD_SOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add i8 %xx, 1 + %y = add i8 %yy, 1 + + %add_sov = call { i8, i1 } @llvm.sadd.with.overflow(i8 %x, i8 %y) + %add = extractvalue { i8, i1 } %add_sov, 0 + %sov = extractvalue { i8, i1 } %add_sov, 1 + call void @use.i1(i1 %sov) + %r = icmp eq i8 %add, 0 + ret i1 %r +} + +define i1 @extract_value_usub(i8 %x, i8 %zz) { +; CHECK-LABEL: @extract_value_usub( +; CHECK-NEXT: [[Z:%.*]] = add nuw i8 [[ZZ:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add i8 [[Z]], [[X:%.*]] +; CHECK-NEXT: [[SUB_UOV:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: [[SUB:%.*]] = extractvalue { i8, i1 } [[SUB_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { i8, i1 } [[SUB_UOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[UOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[SUB]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[SUB]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %z = add nuw i8 %zz, 1 + %y = add i8 %x, %z + + %sub_uov = call { i8, i1 } @llvm.usub.with.overflow(i8 %x, i8 %y) + %sub = extractvalue { i8, i1 } %sub_uov, 0 + %uov = extractvalue { i8, i1 } %sub_uov, 1 + call void @use.i1(i1 %uov) + call void @use.i8(i8 %sub) + %r = icmp eq i8 %sub, 0 + ret i1 %r +} + +define i1 @extract_value_usub_fail(i8 %x, i8 %z) { +; CHECK-LABEL: @extract_value_usub_fail( +; CHECK-NEXT: [[Y:%.*]] = add i8 [[X:%.*]], [[Z:%.*]] +; CHECK-NEXT: [[SUB_UOV:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: [[SUB:%.*]] = extractvalue { i8, i1 } [[SUB_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { i8, i1 } [[SUB_UOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[UOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[SUB]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[SUB]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %y = add i8 %x, %z + %sub_uov = call { i8, i1 } @llvm.usub.with.overflow(i8 %x, i8 %y) + %sub = extractvalue { i8, i1 } %sub_uov, 0 + %uov = extractvalue { i8, i1 } %sub_uov, 1 + call void @use.i1(i1 %uov) + call void @use.i8(i8 %sub) + %r = icmp eq i8 %sub, 0 + ret i1 %r +} + +define i1 @extract_value_ssub(i8 %x, i8 %zz) { +; CHECK-LABEL: @extract_value_ssub( +; CHECK-NEXT: [[Z:%.*]] = add nuw i8 [[ZZ:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add i8 [[Z]], [[X:%.*]] +; CHECK-NEXT: [[SUB_SOV:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[Y]], i8 [[X]]) +; CHECK-NEXT: [[SUB:%.*]] = extractvalue { i8, i1 } [[SUB_SOV]], 0 +; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[SUB_SOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[SUB]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[SUB]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %z = add nuw i8 %zz, 1 + %y = add i8 %x, %z + + %sub_sov = call { i8, i1 } @llvm.ssub.with.overflow(i8 %y, i8 %x) + %sub = extractvalue { i8, i1 } %sub_sov, 0 + %sov = extractvalue { i8, i1 } %sub_sov, 1 + call void @use.i1(i1 %sov) + call void @use.i8(i8 %sub) + %r = icmp eq i8 %sub, 0 + ret i1 %r +} + +define i1 @extract_value_ssub_fail(i8 %x) { +; CHECK-LABEL: @extract_value_ssub_fail( +; CHECK-NEXT: [[SUB_SOV:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 10, i8 [[X:%.*]]) +; CHECK-NEXT: [[SUB:%.*]] = extractvalue { i8, i1 } [[SUB_SOV]], 0 +; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[SUB_SOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[SUB]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[SUB]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %sub_sov = call { i8, i1 } @llvm.ssub.with.overflow(i8 10, i8 %x) + %sub = extractvalue { i8, i1 } %sub_sov, 0 + %sov = extractvalue { i8, i1 } %sub_sov, 1 + call void @use.i1(i1 %sov) + call void @use.i8(i8 %sub) + %r = icmp eq i8 %sub, 0 + ret i1 %r +} + +define i1 @extract_value_umul(i8 %xx, i8 %yy) { +; CHECK-LABEL: @extract_value_umul( +; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[MUL_UOV:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i8, i1 } [[MUL_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { i8, i1 } [[MUL_UOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[UOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[MUL]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[MUL]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = or i8 %xx, 1 + %y = add nuw i8 %yy, 1 + + %mul_uov = call { i8, i1 } @llvm.umul.with.overflow(i8 %x, i8 %y) + %mul = extractvalue { i8, i1 } %mul_uov, 0 + %uov = extractvalue { i8, i1 } %mul_uov, 1 + call void @use.i1(i1 %uov) + call void @use.i8(i8 %mul) + %r = icmp eq i8 %mul, 0 + ret i1 %r +} + +define i1 @extract_value_umul_fail(i8 %xx, i8 %yy) { +; CHECK-LABEL: @extract_value_umul_fail( +; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], 2 +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[MUL_UOV:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[X]], i8 [[Y]]) +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i8, i1 } [[MUL_UOV]], 0 +; CHECK-NEXT: [[UOV:%.*]] = extractvalue { i8, i1 } [[MUL_UOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[UOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[MUL]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[MUL]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = or i8 %xx, 2 + %y = add nuw i8 %yy, 1 + + %mul_uov = call { i8, i1 } @llvm.umul.with.overflow(i8 %x, i8 %y) + %mul = extractvalue { i8, i1 } %mul_uov, 0 + %uov = extractvalue { i8, i1 } %mul_uov, 1 + call void @use.i1(i1 %uov) + call void @use.i8(i8 %mul) + %r = icmp eq i8 %mul, 0 + ret i1 %r +} + +define i1 @extract_value_smul(i8 %xx, i8 %yy) { +; CHECK-LABEL: @extract_value_smul( +; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[MUL_SOV:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[Y]], i8 [[X]]) +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i8, i1 } [[MUL_SOV]], 0 +; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[MUL_SOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[MUL]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[MUL]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = or i8 %xx, 1 + %y = add nuw i8 %yy, 1 + + %mul_sov = call { i8, i1 } @llvm.smul.with.overflow(i8 %y, i8 %x) + %mul = extractvalue { i8, i1 } %mul_sov, 0 + %sov = extractvalue { i8, i1 } %mul_sov, 1 + call void @use.i1(i1 %sov) + call void @use.i8(i8 %mul) + %r = icmp eq i8 %mul, 0 + ret i1 %r +} + +define i1 @extract_value_smul_fail(i8 %xx, i8 %yy) { +; CHECK-LABEL: @extract_value_smul_fail( +; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], 1 +; CHECK-NEXT: [[Y:%.*]] = add i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[MUL_SOV:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[Y]], i8 [[X]]) +; CHECK-NEXT: [[MUL:%.*]] = extractvalue { i8, i1 } [[MUL_SOV]], 0 +; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[MUL_SOV]], 1 +; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) +; CHECK-NEXT: call void @use.i8(i8 [[MUL]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[MUL]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = or i8 %xx, 1 + %y = add i8 %yy, 1 + + %mul_sov = call { i8, i1 } @llvm.smul.with.overflow(i8 %y, i8 %x) + %mul = extractvalue { i8, i1 } %mul_sov, 0 + %sov = extractvalue { i8, i1 } %mul_sov, 1 + call void @use.i1(i1 %sov) + call void @use.i8(i8 %mul) + %r = icmp eq i8 %mul, 0 + ret i1 %r +} + declare void @use(i1) declare void @sink(i8) -- GitLab From f0a487d7e2085e21f3691393070f54110d889fb6 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 15:33:18 -0500 Subject: [PATCH 407/695] [ValueTracking] Split `isNonZero(mul)` logic to a helper; NFC --- llvm/lib/Analysis/ValueTracking.cpp | 57 ++++++++++++++++------------- 1 file changed, 31 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 4120876889de..2c9ea8aa3851 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2471,6 +2471,34 @@ static bool isNonZeroSub(const APInt &DemandedElts, unsigned Depth, return ::isKnownNonEqual(X, Y, Depth, Q); } +static bool isNonZeroMul(const APInt &DemandedElts, unsigned Depth, + const SimplifyQuery &Q, unsigned BitWidth, Value *X, + Value *Y, bool NSW, bool NUW) { + // If X and Y are non-zero then so is X * Y as long as the multiplication + // does not overflow. + if (NSW || NUW) + return isKnownNonZero(X, DemandedElts, Depth, Q) && + isKnownNonZero(Y, DemandedElts, Depth, Q); + + // If either X or Y is odd, then if the other is non-zero the result can't + // be zero. + KnownBits XKnown = computeKnownBits(X, DemandedElts, Depth, Q); + if (XKnown.One[0]) + return isKnownNonZero(Y, DemandedElts, Depth, Q); + + KnownBits YKnown = computeKnownBits(Y, DemandedElts, Depth, Q); + if (YKnown.One[0]) + return XKnown.isNonZero() || isKnownNonZero(X, DemandedElts, Depth, Q); + + // If there exists any subset of X (sX) and subset of Y (sY) s.t sX * sY is + // non-zero, then X * Y is non-zero. We can find sX and sY by just taking + // the lowest known One of X and Y. If they are non-zero, the result + // must be non-zero. We can check if LSB(X) * LSB(Y) != 0 by doing + // X.CountLeadingZeros + Y.CountLeadingZeros < BitWidth. + return (XKnown.countMaxTrailingZeros() + YKnown.countMaxTrailingZeros()) < + BitWidth; +} + static bool isNonZeroShift(const Operator *I, const APInt &DemandedElts, unsigned Depth, const SimplifyQuery &Q, const KnownBits &KnownVal) { @@ -2666,33 +2694,10 @@ static bool isKnownNonZeroFromOperator(const Operator *I, Q.IIQ.hasNoUnsignedWrap(BO)); } case Instruction::Mul: { - // If X and Y are non-zero then so is X * Y as long as the multiplication - // does not overflow. const OverflowingBinaryOperator *BO = cast(I); - if (Q.IIQ.hasNoSignedWrap(BO) || Q.IIQ.hasNoUnsignedWrap(BO)) - return isKnownNonZero(I->getOperand(0), DemandedElts, Depth, Q) && - isKnownNonZero(I->getOperand(1), DemandedElts, Depth, Q); - - // If either X or Y is odd, then if the other is non-zero the result can't - // be zero. - KnownBits XKnown = - computeKnownBits(I->getOperand(0), DemandedElts, Depth, Q); - if (XKnown.One[0]) - return isKnownNonZero(I->getOperand(1), DemandedElts, Depth, Q); - - KnownBits YKnown = - computeKnownBits(I->getOperand(1), DemandedElts, Depth, Q); - if (YKnown.One[0]) - return XKnown.isNonZero() || - isKnownNonZero(I->getOperand(0), DemandedElts, Depth, Q); - - // If there exists any subset of X (sX) and subset of Y (sY) s.t sX * sY is - // non-zero, then X * Y is non-zero. We can find sX and sY by just taking - // the lowest known One of X and Y. If they are non-zero, the result - // must be non-zero. We can check if LSB(X) * LSB(Y) != 0 by doing - // X.CountLeadingZeros + Y.CountLeadingZeros < BitWidth. - return (XKnown.countMaxTrailingZeros() + YKnown.countMaxTrailingZeros()) < - BitWidth; + return isNonZeroMul(DemandedElts, Depth, Q, BitWidth, I->getOperand(0), + I->getOperand(1), Q.IIQ.hasNoSignedWrap(BO), + Q.IIQ.hasNoUnsignedWrap(BO)); } case Instruction::Select: { // (C ? X : Y) != 0 if X != 0 and Y != 0. -- GitLab From 37ca6fa1e26e86c85c544023b18695be420e80dd Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 15:35:17 -0500 Subject: [PATCH 408/695] [ValueTracking] Add support for overflow detection functions is `isKnownNonZero` Adds support for: `{s,u}{add,sub,mul}.with.overflow` The logic is identical to the the non-overflow binops, we where just missing the cases. Closes #87701 --- llvm/lib/Analysis/ValueTracking.cpp | 23 ++++++++++++++++ .../test/Transforms/InstCombine/known-bits.ll | 26 +++++-------------- 2 files changed, 30 insertions(+), 19 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 2c9ea8aa3851..b32dc493ace9 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2798,6 +2798,29 @@ static bool isKnownNonZeroFromOperator(const Operator *I, // handled in isKnownNonZero. return false; } + case Instruction::ExtractValue: { + const WithOverflowInst *WO; + if (match(I, m_ExtractValue<0>(m_WithOverflowInst(WO)))) { + switch (WO->getBinaryOp()) { + default: + break; + case Instruction::Add: + return isNonZeroAdd(DemandedElts, Depth, Q, BitWidth, + WO->getArgOperand(0), WO->getArgOperand(1), + /*NSW=*/false, + /*NUW=*/false); + case Instruction::Sub: + return isNonZeroSub(DemandedElts, Depth, Q, BitWidth, + WO->getArgOperand(0), WO->getArgOperand(1)); + case Instruction::Mul: + return isNonZeroMul(DemandedElts, Depth, Q, BitWidth, + WO->getArgOperand(0), WO->getArgOperand(1), + /*NSW=*/false, /*NUW=*/false); + break; + } + } + break; + } case Instruction::Call: case Instruction::Invoke: { const auto *Call = cast(I); diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll index ddd5970ccabd..e27e4a3eddfb 100644 --- a/llvm/test/Transforms/InstCombine/known-bits.ll +++ b/llvm/test/Transforms/InstCombine/known-bits.ll @@ -642,12 +642,9 @@ define i1 @extract_value_uadd(<2 x i8> %xx, <2 x i8> %yy) { ; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], ; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], ; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) -; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 ; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 ; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) -; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i64 0 -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x0 = and <2 x i8> %xx, %y0 = and <2 x i8> %yy, @@ -670,12 +667,9 @@ define i1 @extract_value_uadd2(<2 x i8> %xx, <2 x i8> %yy) { ; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[X0]], ; CHECK-NEXT: [[Y:%.*]] = add nuw <2 x i8> [[Y0]], ; CHECK-NEXT: [[ADD_UOV:%.*]] = call { <2 x i8>, <2 x i1> } @llvm.uadd.with.overflow.v2i8(<2 x i8> [[X]], <2 x i8> [[Y]]) -; CHECK-NEXT: [[ADD:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 0 ; CHECK-NEXT: [[UOV:%.*]] = extractvalue { <2 x i8>, <2 x i1> } [[ADD_UOV]], 1 ; CHECK-NEXT: call void @use.2xi1(<2 x i1> [[UOV]]) -; CHECK-NEXT: [[ADD_ELE:%.*]] = extractelement <2 x i8> [[ADD]], i64 1 -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD_ELE]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x0 = and <2 x i8> %xx, %y0 = and <2 x i8> %yy, @@ -784,11 +778,9 @@ define i1 @extract_value_sadd(i8 %xx, i8 %yy) { ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LEMMA]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LEMMA]]) ; CHECK-NEXT: [[ADD_SOV:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[X]], i8 [[Y]]) -; CHECK-NEXT: [[ADD:%.*]] = extractvalue { i8, i1 } [[ADD_SOV]], 0 ; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[ADD_SOV]], 1 ; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[ADD]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x = add nuw i8 %xx, 1 %y = add nuw i8 %yy, 1 @@ -836,8 +828,7 @@ define i1 @extract_value_usub(i8 %x, i8 %zz) { ; CHECK-NEXT: [[UOV:%.*]] = extractvalue { i8, i1 } [[SUB_UOV]], 1 ; CHECK-NEXT: call void @use.i1(i1 [[UOV]]) ; CHECK-NEXT: call void @use.i8(i8 [[SUB]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[SUB]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %z = add nuw i8 %zz, 1 %y = add i8 %x, %z @@ -881,8 +872,7 @@ define i1 @extract_value_ssub(i8 %x, i8 %zz) { ; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[SUB_SOV]], 1 ; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) ; CHECK-NEXT: call void @use.i8(i8 [[SUB]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[SUB]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %z = add nuw i8 %zz, 1 %y = add i8 %x, %z @@ -924,8 +914,7 @@ define i1 @extract_value_umul(i8 %xx, i8 %yy) { ; CHECK-NEXT: [[UOV:%.*]] = extractvalue { i8, i1 } [[MUL_UOV]], 1 ; CHECK-NEXT: call void @use.i1(i1 [[UOV]]) ; CHECK-NEXT: call void @use.i8(i8 [[MUL]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[MUL]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x = or i8 %xx, 1 %y = add nuw i8 %yy, 1 @@ -972,8 +961,7 @@ define i1 @extract_value_smul(i8 %xx, i8 %yy) { ; CHECK-NEXT: [[SOV:%.*]] = extractvalue { i8, i1 } [[MUL_SOV]], 1 ; CHECK-NEXT: call void @use.i1(i1 [[SOV]]) ; CHECK-NEXT: call void @use.i8(i8 [[MUL]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[MUL]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x = or i8 %xx, 1 %y = add nuw i8 %yy, 1 -- GitLab From 2ff82c2c6490a1478e4311f60f1ce80af0957403 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Tue, 9 Apr 2024 12:36:03 -0500 Subject: [PATCH 409/695] [ValueTracking] Add tests for improving `isKnownNonZero` of `smax`; NFC --- .../Transforms/InstSimplify/known-non-zero.ll | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/llvm/test/Transforms/InstSimplify/known-non-zero.ll b/llvm/test/Transforms/InstSimplify/known-non-zero.ll index b647f11af446..6ebc4e0f31a9 100644 --- a/llvm/test/Transforms/InstSimplify/known-non-zero.ll +++ b/llvm/test/Transforms/InstSimplify/known-non-zero.ll @@ -166,3 +166,18 @@ A: B: ret i1 0 } + +define i1 @smax_non_zero(i8 %xx, i8 %y) { +; CHECK-LABEL: @smax_non_zero( +; CHECK-NEXT: [[X0:%.*]] = and i8 [[XX:%.*]], 63 +; CHECK-NEXT: [[X:%.*]] = add i8 [[X0]], 1 +; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.smax.i8(i8 [[X]], i8 [[Y:%.*]]) +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x0 = and i8 %xx, 63 + %x = add i8 %x0, 1 + %v = call i8 @llvm.smax.i8(i8 %x, i8 %y) + %r = icmp eq i8 %v, 0 + ret i1 %r +} -- GitLab From f1ee458ddb45c9887b3df583ce9a4ba12aae8b3b Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Tue, 9 Apr 2024 11:58:03 -0500 Subject: [PATCH 410/695] [ValueTracking] improve `isKnownNonZero` precision for `smax` Instead of relying on known-bits for strictly positive, use the `isKnownPositive` API. This will use `isKnownNonZero` which is more accurate. Closes #88170 --- llvm/lib/Analysis/ValueTracking.cpp | 41 ++++++++++++++----- .../Transforms/InstSimplify/known-non-zero.ll | 6 +-- 2 files changed, 32 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index b32dc493ace9..5ef1969893b4 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2870,23 +2870,44 @@ static bool isKnownNonZeroFromOperator(const Operator *I, case Intrinsic::uadd_sat: return isKnownNonZero(II->getArgOperand(1), DemandedElts, Depth, Q) || isKnownNonZero(II->getArgOperand(0), DemandedElts, Depth, Q); - case Intrinsic::smin: case Intrinsic::smax: { - auto KnownOpImpliesNonZero = [&](const KnownBits &K) { - return II->getIntrinsicID() == Intrinsic::smin - ? K.isNegative() - : K.isStrictlyPositive(); + // If either arg is strictly positive the result is non-zero. Otherwise + // the result is non-zero if both ops are non-zero. + auto IsNonZero = [&](Value *Op, std::optional &OpNonZero, + const KnownBits &OpKnown) { + if (!OpNonZero.has_value()) + OpNonZero = OpKnown.isNonZero() || + isKnownNonZero(Op, DemandedElts, Depth, Q); + return *OpNonZero; }; - KnownBits XKnown = + // Avoid re-computing isKnownNonZero. + std::optional Op0NonZero, Op1NonZero; + KnownBits Op1Known = + computeKnownBits(II->getArgOperand(1), DemandedElts, Depth, Q); + if (Op1Known.isNonNegative() && + IsNonZero(II->getArgOperand(1), Op1NonZero, Op1Known)) + return true; + KnownBits Op0Known = computeKnownBits(II->getArgOperand(0), DemandedElts, Depth, Q); - if (KnownOpImpliesNonZero(XKnown)) + if (Op0Known.isNonNegative() && + IsNonZero(II->getArgOperand(0), Op0NonZero, Op0Known)) return true; - KnownBits YKnown = + return IsNonZero(II->getArgOperand(1), Op1NonZero, Op1Known) && + IsNonZero(II->getArgOperand(0), Op0NonZero, Op0Known); + } + case Intrinsic::smin: { + // If either arg is negative the result is non-zero. Otherwise + // the result is non-zero if both ops are non-zero. + KnownBits Op1Known = computeKnownBits(II->getArgOperand(1), DemandedElts, Depth, Q); - if (KnownOpImpliesNonZero(YKnown)) + if (Op1Known.isNegative()) + return true; + KnownBits Op0Known = + computeKnownBits(II->getArgOperand(0), DemandedElts, Depth, Q); + if (Op0Known.isNegative()) return true; - if (XKnown.isNonZero() && YKnown.isNonZero()) + if (Op1Known.isNonZero() && Op0Known.isNonZero()) return true; } [[fallthrough]]; diff --git a/llvm/test/Transforms/InstSimplify/known-non-zero.ll b/llvm/test/Transforms/InstSimplify/known-non-zero.ll index 6ebc4e0f31a9..51f80f62c2f3 100644 --- a/llvm/test/Transforms/InstSimplify/known-non-zero.ll +++ b/llvm/test/Transforms/InstSimplify/known-non-zero.ll @@ -169,11 +169,7 @@ B: define i1 @smax_non_zero(i8 %xx, i8 %y) { ; CHECK-LABEL: @smax_non_zero( -; CHECK-NEXT: [[X0:%.*]] = and i8 [[XX:%.*]], 63 -; CHECK-NEXT: [[X:%.*]] = add i8 [[X0]], 1 -; CHECK-NEXT: [[V:%.*]] = call i8 @llvm.smax.i8(i8 [[X]], i8 [[Y:%.*]]) -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[V]], 0 -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %x0 = and i8 %xx, 63 %x = add i8 %x0, 1 -- GitLab From 7d60232b38b66138dae1b31027d73ee5b9df5c58 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 10 Apr 2024 10:41:20 -0500 Subject: [PATCH 411/695] [flang][Frontend] Implement printing defined macros via -dM (#87627) This should work the same way as in clang. --- clang/docs/tools/clang-formatted-files.txt | 4 +- clang/include/clang/Driver/Options.td | 2 +- clang/lib/Driver/ToolChains/Flang.cpp | 5 +- .../flang/Frontend/PreprocessorOptions.h | 3 + flang/include/flang/Parser/parsing.h | 3 + .../flang}/Parser/preprocessor.h | 15 +++- .../flang}/Parser/token-sequence.h | 4 +- flang/lib/Frontend/CompilerInvocation.cpp | 1 + flang/lib/Frontend/FrontendActions.cpp | 4 +- flang/lib/Parser/parsing.cpp | 17 +++-- flang/lib/Parser/preprocessor.cpp | 68 +++++++++++++++++-- flang/lib/Parser/prescan.cpp | 4 +- flang/lib/Parser/prescan.h | 2 +- flang/lib/Parser/token-sequence.cpp | 3 +- flang/test/Driver/driver-help-hidden.f90 | 1 + flang/test/Driver/driver-help.f90 | 2 + flang/test/Preprocessing/show-macros1.F90 | 14 ++++ flang/test/Preprocessing/show-macros2.F90 | 6 ++ flang/test/Preprocessing/show-macros3.F90 | 9 +++ 19 files changed, 139 insertions(+), 28 deletions(-) rename flang/{lib => include/flang}/Parser/preprocessor.h (88%) rename flang/{lib => include/flang}/Parser/token-sequence.h (97%) create mode 100644 flang/test/Preprocessing/show-macros1.F90 create mode 100644 flang/test/Preprocessing/show-macros2.F90 create mode 100644 flang/test/Preprocessing/show-macros3.F90 diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt index 70687c23b15e..8fd4fed25a32 100644 --- a/clang/docs/tools/clang-formatted-files.txt +++ b/clang/docs/tools/clang-formatted-files.txt @@ -2147,8 +2147,10 @@ flang/include/flang/Parser/message.h flang/include/flang/Parser/parse-state.h flang/include/flang/Parser/parse-tree-visitor.h flang/include/flang/Parser/parsing.h +flang/include/flang/Parser/preprocessor.h flang/include/flang/Parser/provenance.h flang/include/flang/Parser/source.h +flang/include/flang/Parser/token-sequence.h flang/include/flang/Parser/tools.h flang/include/flang/Parser/unparse.h flang/include/flang/Parser/user-state.h @@ -2319,7 +2321,6 @@ flang/lib/Parser/openmp-parsers.cpp flang/lib/Parser/parse-tree.cpp flang/lib/Parser/parsing.cpp flang/lib/Parser/preprocessor.cpp -flang/lib/Parser/preprocessor.h flang/lib/Parser/prescan.cpp flang/lib/Parser/prescan.h flang/lib/Parser/program-parsers.cpp @@ -2328,7 +2329,6 @@ flang/lib/Parser/source.cpp flang/lib/Parser/stmt-parser.h flang/lib/Parser/token-parsers.h flang/lib/Parser/token-sequence.cpp -flang/lib/Parser/token-sequence.h flang/lib/Parser/tools.cpp flang/lib/Parser/type-parser-implementation.h flang/lib/Parser/type-parsers.h diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index f745e573eb26..0a74e6c75f95 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -1449,7 +1449,7 @@ def dD : Flag<["-"], "dD">, Group, Visibility<[ClangOption, CC1Option]> def dI : Flag<["-"], "dI">, Group, Visibility<[ClangOption, CC1Option]>, HelpText<"Print include directives in -E mode in addition to normal output">, MarshallingInfoFlag>; -def dM : Flag<["-"], "dM">, Group, Visibility<[ClangOption, CC1Option]>, +def dM : Flag<["-"], "dM">, Group, Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Print macro definitions in -E mode instead of normal output">; def dead__strip : Flag<["-"], "dead_strip">; def dependency_file : Separate<["-"], "dependency-file">, diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 2c83f70eb788..9699443603d3 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -679,7 +679,10 @@ void Flang::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back(Args.MakeArgString(TripleStr)); if (isa(JA)) { - CmdArgs.push_back("-E"); + CmdArgs.push_back("-E"); + if (Args.getLastArg(options::OPT_dM)) { + CmdArgs.push_back("-dM"); + } } else if (isa(JA) || isa(JA)) { if (JA.getType() == types::TY_Nothing) { CmdArgs.push_back("-fsyntax-only"); diff --git a/flang/include/flang/Frontend/PreprocessorOptions.h b/flang/include/flang/Frontend/PreprocessorOptions.h index b2e9ac0e963b..13a91ee9a184 100644 --- a/flang/include/flang/Frontend/PreprocessorOptions.h +++ b/flang/include/flang/Frontend/PreprocessorOptions.h @@ -56,6 +56,9 @@ struct PreprocessorOptions { // -fno-reformat: Emit cooked character stream as -E output bool noReformat{false}; + // -dM: Show macro definitions with -dM -E + bool showMacros{false}; + void addMacroDef(llvm::StringRef name) { macros.emplace_back(std::string(name), false); } diff --git a/flang/include/flang/Parser/parsing.h b/flang/include/flang/Parser/parsing.h index e80d8f724ac8..4d329c189cb8 100644 --- a/flang/include/flang/Parser/parsing.h +++ b/flang/include/flang/Parser/parsing.h @@ -15,6 +15,7 @@ #include "parse-tree.h" #include "provenance.h" #include "flang/Common/Fortran-features.h" +#include "flang/Parser/preprocessor.h" #include "llvm/Support/raw_ostream.h" #include #include @@ -59,6 +60,7 @@ public: const SourceFile *Prescan(const std::string &path, Options); void EmitPreprocessedSource( llvm::raw_ostream &, bool lineDirectives = true) const; + void EmitPreprocessorMacros(llvm::raw_ostream &) const; void DumpCookedChars(llvm::raw_ostream &) const; void DumpProvenance(llvm::raw_ostream &) const; void DumpParsingLog(llvm::raw_ostream &) const; @@ -83,6 +85,7 @@ private: const char *finalRestingPlace_{nullptr}; std::optional parseTree_; ParsingLog log_; + Preprocessor preprocessor_{allCooked_.allSources()}; }; } // namespace Fortran::parser #endif // FORTRAN_PARSER_PARSING_H_ diff --git a/flang/lib/Parser/preprocessor.h b/flang/include/flang/Parser/preprocessor.h similarity index 88% rename from flang/lib/Parser/preprocessor.h rename to flang/include/flang/Parser/preprocessor.h index b61f1577727b..630d5273d427 100644 --- a/flang/lib/Parser/preprocessor.h +++ b/flang/include/flang/Parser/preprocessor.h @@ -15,9 +15,10 @@ // performed, so that special compiler command options &/or source file name // extensions for preprocessing will not be necessary. -#include "token-sequence.h" #include "flang/Parser/char-block.h" #include "flang/Parser/provenance.h" +#include "flang/Parser/token-sequence.h" +#include "llvm/Support/raw_ostream.h" #include #include #include @@ -39,7 +40,7 @@ public: Definition(const std::string &predefined, AllSources &); bool isFunctionLike() const { return isFunctionLike_; } - std::size_t argumentCount() const { return argumentCount_; } + std::size_t argumentCount() const { return argNames_.size(); } bool isVariadic() const { return isVariadic_; } bool isDisabled() const { return isDisabled_; } bool isPredefined() const { return isPredefined_; } @@ -49,15 +50,21 @@ public: TokenSequence Apply(const std::vector &args, Prescanner &); + void Print(llvm::raw_ostream &out, const char *macroName = "") const; + private: static TokenSequence Tokenize(const std::vector &argNames, const TokenSequence &token, std::size_t firstToken, std::size_t tokens); + // For a given token, return the index of the argument to which the token + // corresponds, or `argumentCount` if the token does not correspond to any + // argument. + std::size_t GetArgumentIndex(const CharBlock &token) const; bool isFunctionLike_{false}; - std::size_t argumentCount_{0}; bool isVariadic_{false}; bool isDisabled_{false}; bool isPredefined_{false}; + std::vector argNames_; TokenSequence replacement_; }; @@ -89,6 +96,8 @@ public: // Implements a preprocessor directive. void Directive(const TokenSequence &, Prescanner &); + void PrintMacros(llvm::raw_ostream &out) const; + private: enum class IsElseActive { No, Yes }; enum class CanDeadElseAppear { No, Yes }; diff --git a/flang/lib/Parser/token-sequence.h b/flang/include/flang/Parser/token-sequence.h similarity index 97% rename from flang/lib/Parser/token-sequence.h rename to flang/include/flang/Parser/token-sequence.h index 3df403d41e63..849240d8ec62 100644 --- a/flang/lib/Parser/token-sequence.h +++ b/flang/include/flang/Parser/token-sequence.h @@ -42,8 +42,8 @@ public: } TokenSequence(TokenSequence &&that) : start_{std::move(that.start_)}, nextStart_{that.nextStart_}, - char_{std::move(that.char_)}, provenances_{ - std::move(that.provenances_)} {} + char_{std::move(that.char_)}, + provenances_{std::move(that.provenances_)} {} TokenSequence(const std::string &s, Provenance p) { Put(s, p); } TokenSequence &operator=(const TokenSequence &that) { diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index c830c7af2462..8ce6ab7baf48 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -772,6 +772,7 @@ static void parsePreprocessorArgs(Fortran::frontend::PreprocessorOptions &opts, opts.noReformat = args.hasArg(clang::driver::options::OPT_fno_reformat); opts.noLineDirectives = args.hasArg(clang::driver::options::OPT_P); + opts.showMacros = args.hasArg(clang::driver::options::OPT_dM); } /// Parses all semantic related arguments and populates the variables diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 849b3c8e4dc0..8f251997ed40 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -399,7 +399,9 @@ void PrintPreprocessedAction::executeAction() { // Format or dump the prescanner's output CompilerInstance &ci = this->getInstance(); - if (ci.getInvocation().getPreprocessorOpts().noReformat) { + if (ci.getInvocation().getPreprocessorOpts().showMacros) { + ci.getParsing().EmitPreprocessorMacros(outForPP); + } else if (ci.getInvocation().getPreprocessorOpts().noReformat) { ci.getParsing().DumpCookedChars(outForPP); } else { ci.getParsing().EmitPreprocessedSource( diff --git a/flang/lib/Parser/parsing.cpp b/flang/lib/Parser/parsing.cpp index a55d33bf6b91..43a898ff120c 100644 --- a/flang/lib/Parser/parsing.cpp +++ b/flang/lib/Parser/parsing.cpp @@ -7,10 +7,10 @@ //===----------------------------------------------------------------------===// #include "flang/Parser/parsing.h" -#include "preprocessor.h" #include "prescan.h" #include "type-parsers.h" #include "flang/Parser/message.h" +#include "flang/Parser/preprocessor.h" #include "flang/Parser/provenance.h" #include "flang/Parser/source.h" #include "llvm/Support/raw_ostream.h" @@ -60,20 +60,19 @@ const SourceFile *Parsing::Prescan(const std::string &path, Options options) { } } - Preprocessor preprocessor{allSources}; if (!options.predefinitions.empty()) { - preprocessor.DefineStandardMacros(); + preprocessor_.DefineStandardMacros(); for (const auto &predef : options.predefinitions) { if (predef.second) { - preprocessor.Define(predef.first, *predef.second); + preprocessor_.Define(predef.first, *predef.second); } else { - preprocessor.Undefine(predef.first); + preprocessor_.Undefine(predef.first); } } } currentCooked_ = &allCooked_.NewCookedSource(); Prescanner prescanner{ - messages_, *currentCooked_, preprocessor, options.features}; + messages_, *currentCooked_, preprocessor_, options.features}; prescanner.set_fixedForm(options.isFixedForm) .set_fixedFormColumnLimit(options.fixedFormColumns) .AddCompilerDirectiveSentinel("dir$"); @@ -87,7 +86,7 @@ const SourceFile *Parsing::Prescan(const std::string &path, Options options) { if (options.features.IsEnabled(LanguageFeature::CUDA)) { prescanner.AddCompilerDirectiveSentinel("$cuf"); prescanner.AddCompilerDirectiveSentinel("@cuf"); - preprocessor.Define("_CUDA", "1"); + preprocessor_.Define("_CUDA", "1"); } ProvenanceRange range{allSources.AddIncludedFile( *sourceFile, ProvenanceRange{}, options.isModuleFile)}; @@ -107,6 +106,10 @@ const SourceFile *Parsing::Prescan(const std::string &path, Options options) { return sourceFile; } +void Parsing::EmitPreprocessorMacros(llvm::raw_ostream &out) const { + preprocessor_.PrintMacros(out); +} + void Parsing::EmitPreprocessedSource( llvm::raw_ostream &out, bool lineDirectives) const { const std::string *sourcePath{nullptr}; diff --git a/flang/lib/Parser/preprocessor.cpp b/flang/lib/Parser/preprocessor.cpp index 515b8f62daf9..2fba28b0c0c7 100644 --- a/flang/lib/Parser/preprocessor.cpp +++ b/flang/lib/Parser/preprocessor.cpp @@ -6,7 +6,8 @@ // //===----------------------------------------------------------------------===// -#include "preprocessor.h" +#include "flang/Parser/preprocessor.h" + #include "prescan.h" #include "flang/Common/idioms.h" #include "flang/Parser/characters.h" @@ -21,6 +22,7 @@ #include #include #include +#include namespace Fortran::parser { @@ -31,8 +33,7 @@ Definition::Definition( Definition::Definition(const std::vector &argNames, const TokenSequence &repl, std::size_t firstToken, std::size_t tokens, bool isVariadic) - : isFunctionLike_{true}, - argumentCount_(argNames.size()), isVariadic_{isVariadic}, + : isFunctionLike_{true}, isVariadic_{isVariadic}, argNames_{argNames}, replacement_{Tokenize(argNames, repl, firstToken, tokens)} {} Definition::Definition(const std::string &predefined, AllSources &sources) @@ -46,6 +47,37 @@ bool Definition::set_isDisabled(bool disable) { return was; } +void Definition::Print(llvm::raw_ostream &out, const char *macroName) const { + if (!isFunctionLike_) { + // If it's not a function-like macro, then just print the replacement. + out << ' ' << replacement_.ToString(); + return; + } + + size_t argCount{argumentCount()}; + + out << '('; + for (size_t i{0}; i != argCount; ++i) { + if (i != 0) { + out << ", "; + } + out << argNames_[i]; + } + if (isVariadic_) { + out << ", ..."; + } + out << ") "; + + for (size_t i{0}, e{replacement_.SizeInTokens()}; i != e; ++i) { + std::string tok{replacement_.TokenAt(i).ToString()}; + if (size_t idx{GetArgumentIndex(tok)}; idx < argCount) { + out << argNames_[idx]; + } else { + out << tok; + } + } +} + static bool IsLegalIdentifierStart(const CharBlock &cpl) { return cpl.size() > 0 && IsLegalIdentifierStart(cpl[0]); } @@ -73,6 +105,13 @@ TokenSequence Definition::Tokenize(const std::vector &argNames, return result; } +std::size_t Definition::GetArgumentIndex(const CharBlock &token) const { + if (token.size() >= 2 && token[0] == '~') { + return static_cast(token[1] - 'A'); + } + return argumentCount(); +} + static TokenSequence Stringify( const TokenSequence &tokens, AllSources &allSources) { TokenSequence result; @@ -159,7 +198,7 @@ TokenSequence Definition::Apply( continue; } if (bytes == 2 && token[0] == '~') { // argument substitution - std::size_t index = token[1] - 'A'; + std::size_t index{GetArgumentIndex(token)}; if (index >= args.size()) { continue; } @@ -202,8 +241,8 @@ TokenSequence Definition::Apply( Provenance commaProvenance{ prescanner.preprocessor().allSources().CompilerInsertionProvenance( ',')}; - for (std::size_t k{argumentCount_}; k < args.size(); ++k) { - if (k > argumentCount_) { + for (std::size_t k{argumentCount()}; k < args.size(); ++k) { + if (k > argumentCount()) { result.Put(","s, commaProvenance); } result.Put(args[k]); @@ -212,7 +251,7 @@ TokenSequence Definition::Apply( j + 2 < tokens && replacement_.TokenAt(j + 1).OnlyNonBlank() == '(' && parenthesesNesting == 0) { parenthesesNesting = 1; - skipping = args.size() == argumentCount_; + skipping = args.size() == argumentCount(); ++j; } else { if (parenthesesNesting > 0) { @@ -713,6 +752,21 @@ void Preprocessor::Directive(const TokenSequence &dir, Prescanner &prescanner) { } } +void Preprocessor::PrintMacros(llvm::raw_ostream &out) const { + // std::set is ordered. Use that to print the macros in an + // alphabetical order. + std::set macroNames; + for (const auto &[name, _] : definitions_) { + macroNames.insert(name.ToString()); + } + + for (const std::string &name : macroNames) { + out << "#define " << name; + definitions_.at(name).Print(out, name.c_str()); + out << '\n'; + } +} + CharBlock Preprocessor::SaveTokenAsName(const CharBlock &t) { names_.push_back(t.ToString()); return {names_.back().data(), names_.back().size()}; diff --git a/flang/lib/Parser/prescan.cpp b/flang/lib/Parser/prescan.cpp index e9b23172ed2e..96db3955299f 100644 --- a/flang/lib/Parser/prescan.cpp +++ b/flang/lib/Parser/prescan.cpp @@ -7,12 +7,12 @@ //===----------------------------------------------------------------------===// #include "prescan.h" -#include "preprocessor.h" -#include "token-sequence.h" #include "flang/Common/idioms.h" #include "flang/Parser/characters.h" #include "flang/Parser/message.h" +#include "flang/Parser/preprocessor.h" #include "flang/Parser/source.h" +#include "flang/Parser/token-sequence.h" #include "llvm/Support/raw_ostream.h" #include #include diff --git a/flang/lib/Parser/prescan.h b/flang/lib/Parser/prescan.h index 7442b5d22633..581980001bcc 100644 --- a/flang/lib/Parser/prescan.h +++ b/flang/lib/Parser/prescan.h @@ -16,11 +16,11 @@ // fixed form character literals on truncated card images, file // inclusion, and driving the Fortran source preprocessor. -#include "token-sequence.h" #include "flang/Common/Fortran-features.h" #include "flang/Parser/characters.h" #include "flang/Parser/message.h" #include "flang/Parser/provenance.h" +#include "flang/Parser/token-sequence.h" #include #include #include diff --git a/flang/lib/Parser/token-sequence.cpp b/flang/lib/Parser/token-sequence.cpp index 799d13a42366..d0254ecd5aae 100644 --- a/flang/lib/Parser/token-sequence.cpp +++ b/flang/lib/Parser/token-sequence.cpp @@ -6,7 +6,8 @@ // //===----------------------------------------------------------------------===// -#include "token-sequence.h" +#include "flang/Parser/token-sequence.h" + #include "prescan.h" #include "flang/Parser/characters.h" #include "flang/Parser/message.h" diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 index 48f48f5384fd..35b188ad3a9e 100644 --- a/flang/test/Driver/driver-help-hidden.f90 +++ b/flang/test/Driver/driver-help-hidden.f90 @@ -21,6 +21,7 @@ ! CHECK-NEXT: -ccc-print-phases Dump list of actions to perform ! CHECK-NEXT: -cpp Enable predefined and command line preprocessor macros ! CHECK-NEXT: -c Only run preprocess, compile, and assemble steps +! CHECK-NEXT: -dM Print macro definitions in -E mode instead of normal output ! CHECK-NEXT: -dumpmachine Display the compiler's target processor ! CHECK-NEXT: -dumpversion Display the version of the compiler ! CHECK-NEXT: -D = Define to (or 1 if omitted) diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90 index 38f74395a678..d4dab55f40e8 100644 --- a/flang/test/Driver/driver-help.f90 +++ b/flang/test/Driver/driver-help.f90 @@ -17,6 +17,7 @@ ! HELP-NEXT: -### Print (but do not run) the commands to run for this compilation ! HELP-NEXT: -cpp Enable predefined and command line preprocessor macros ! HELP-NEXT: -c Only run preprocess, compile, and assemble steps +! HELP-NEXT: -dM Print macro definitions in -E mode instead of normal output ! HELP-NEXT: -dumpmachine Display the compiler's target processor ! HELP-NEXT: -dumpversion Display the version of the compiler ! HELP-NEXT: -D = Define to (or 1 if omitted) @@ -155,6 +156,7 @@ ! HELP-FC1-NEXT:OPTIONS: ! HELP-FC1-NEXT: -cpp Enable predefined and command line preprocessor macros ! HELP-FC1-NEXT: --dependent-lib= Add dependent library +! HELP-FC1-NEXT: -dM Print macro definitions in -E mode instead of normal output ! HELP-FC1-NEXT: -D = Define to (or 1 if omitted) ! HELP-FC1-NEXT: -emit-fir Build the parse tree, then lower it to FIR ! HELP-FC1-NEXT: -emit-hlfir Build the parse tree, then lower it to HLFIR diff --git a/flang/test/Preprocessing/show-macros1.F90 b/flang/test/Preprocessing/show-macros1.F90 new file mode 100644 index 000000000000..8e3d59a7849f --- /dev/null +++ b/flang/test/Preprocessing/show-macros1.F90 @@ -0,0 +1,14 @@ +! RUN: %flang -dM -E -o - %s | FileCheck %s + +! Check the default macros. Omit certain ones such as __LINE__ +! or __FILE__, or target-specific ones, like __x86_64__. + +! Macros are printed in the alphabetical order. + +! CHECK: #define __DATE__ +! CHECK: #define __TIME__ +! CHECK: #define __flang__ +! CHECK: #define __flang_major__ +! CHECK: #define __flang_minor__ +! CHECK: #define __flang_patchlevel__ + diff --git a/flang/test/Preprocessing/show-macros2.F90 b/flang/test/Preprocessing/show-macros2.F90 new file mode 100644 index 000000000000..baf52ba8161f --- /dev/null +++ b/flang/test/Preprocessing/show-macros2.F90 @@ -0,0 +1,6 @@ +! RUN: %flang -DFOO -DBAR=FOO -dM -E -o - %s | FileCheck %s + +! Check command line definitions + +! CHECK: #define BAR FOO +! CHECK: #define FOO 1 diff --git a/flang/test/Preprocessing/show-macros3.F90 b/flang/test/Preprocessing/show-macros3.F90 new file mode 100644 index 000000000000..951a1ec5ba16 --- /dev/null +++ b/flang/test/Preprocessing/show-macros3.F90 @@ -0,0 +1,9 @@ +! RUN: %flang -dM -E -o - %s | FileCheck %s + +! Variadic macro +#define FOO1(X, Y, ...) bar(bar(X, Y), __VA_ARGS__) +! CHECK: #define FOO1(X, Y, ...) bar(bar(X, Y), __VA_ARGS__) + +! Macro with an unused parameter +#define FOO2(X, Y, Z) (X + Z) +! CHECK: #define FOO2(X, Y, Z) (X + Z) -- GitLab From 52aaa8a87960a7d342c5e6b7d5af82c76c8cc45d Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Wed, 10 Apr 2024 10:46:53 -0500 Subject: [PATCH 412/695] [clang][test] Avoid writing to a potentially write-protected dir (#88258) This test just checks for the stdout/stderr of clang, but it incidentally tries to write to `a.out` in the current directory, which may be write protected. Typically one would write `clang -o %t.o` for a writeable dir, but since we only care about stdout/stderr, throw away the object file and just write to /dev/null instead. --- clang/test/Driver/lld-repro.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/clang/test/Driver/lld-repro.c b/clang/test/Driver/lld-repro.c index 9457dd334b5b..61904c0e6df3 100644 --- a/clang/test/Driver/lld-repro.c +++ b/clang/test/Driver/lld-repro.c @@ -4,12 +4,12 @@ // RUN: echo "-nostartfiles -nostdlib -fuse-ld=lld -gen-reproducer=error -fcrash-diagnostics-dir=%t" \ // RUN: | sed -e 's/\\/\\\\/g' > %t.rsp -// RUN: not %clang %s @%t.rsp -fcrash-diagnostics=all 2>&1 \ +// RUN: not %clang %s @%t.rsp -fcrash-diagnostics=all -o /dev/null 2>&1 \ // RUN: | FileCheck %s // Test that the reproducer can still be created even when the input source cannot be preprocessed // again, like when reading from stdin. -// RUN: not %clang -x c - @%t.rsp -fcrash-diagnostics=all 2>&1 < %s \ +// RUN: not %clang -x c - @%t.rsp -fcrash-diagnostics=all -o /dev/null 2>&1 < %s \ // RUN: | FileCheck %s // check that we still get lld's output @@ -20,9 +20,9 @@ // CHECK-NEXT: note: diagnostic msg: // CHECK: ******************** -// RUN: not %clang %s @%t.rsp -fcrash-diagnostics=compiler 2>&1 \ +// RUN: not %clang %s @%t.rsp -fcrash-diagnostics=compiler -o /dev/null 2>&1 \ // RUN: | FileCheck %s --check-prefix=NO-LINKER -// RUN: not %clang %s @%t.rsp 2>&1 \ +// RUN: not %clang %s @%t.rsp -o /dev/null 2>&1 \ // RUN: | FileCheck %s --check-prefix=NO-LINKER // NO-LINKER-NOT: Preprocessed source(s) and associated run script(s) are located at: -- GitLab From 0ad663ead1242e908a8c5005f35e72747d136a3b Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Wed, 10 Apr 2024 17:51:02 +0200 Subject: [PATCH 413/695] [libc++] Removes Clang-16 support. (#87810) With the release of Clang-18 we no longer officially support Clang-16. --- libcxx/include/__algorithm/simd_utils.h | 2 +- libcxx/include/__config | 4 ++-- libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp | 2 +- .../range.utility/range.utility.conv/to_deduction.pass.cpp | 2 +- .../format/format.arguments/format.arg/visit.pass.cpp | 2 +- .../format.arguments/format.arg/visit.return_type.pass.cpp | 2 +- .../format.arg/visit_format_arg.deprecated.verify.cpp | 2 +- .../variant/variant.visit.member/robust_against_adl.pass.cpp | 2 +- .../std/utilities/variant/variant.visit.member/visit.pass.cpp | 2 +- .../variant/variant.visit.member/visit_return_type.pass.cpp | 2 +- 10 files changed, 11 insertions(+), 11 deletions(-) diff --git a/libcxx/include/__algorithm/simd_utils.h b/libcxx/include/__algorithm/simd_utils.h index 989a1957987e..8d540ae2cce8 100644 --- a/libcxx/include/__algorithm/simd_utils.h +++ b/libcxx/include/__algorithm/simd_utils.h @@ -27,7 +27,7 @@ _LIBCPP_PUSH_MACROS #include <__undef_macros> // TODO: Find out how altivec changes things and allow vectorizations there too. -#if _LIBCPP_STD_VER >= 14 && defined(_LIBCPP_CLANG_VER) && _LIBCPP_CLANG_VER >= 1700 && !defined(__ALTIVEC__) +#if _LIBCPP_STD_VER >= 14 && defined(_LIBCPP_CLANG_VER) && !defined(__ALTIVEC__) # define _LIBCPP_HAS_ALGORITHM_VECTOR_UTILS 1 #else # define _LIBCPP_HAS_ALGORITHM_VECTOR_UTILS 0 diff --git a/libcxx/include/__config b/libcxx/include/__config index 8550b1da4a27..d98b54926bbe 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -44,8 +44,8 @@ // Warn if a compiler version is used that is not supported anymore // LLVM RELEASE Update the minimum compiler versions # if defined(_LIBCPP_CLANG_VER) -# if _LIBCPP_CLANG_VER < 1600 -# warning "Libc++ only supports Clang 16 and later" +# if _LIBCPP_CLANG_VER < 1700 +# warning "Libc++ only supports Clang 17 and later" # endif # elif defined(_LIBCPP_APPLE_CLANG_VER) # if _LIBCPP_APPLE_CLANG_VER < 1500 diff --git a/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp b/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp index 479c1b93fcab..640365889efa 100644 --- a/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp +++ b/libcxx/test/libcxx/gdb/gdb_pretty_printer_test.sh.cpp @@ -12,7 +12,7 @@ // UNSUPPORTED: c++03 // TODO: Investigate these failures which break the CI. -// UNSUPPORTED: clang-16, clang-17, clang-18, clang-19 +// UNSUPPORTED: clang-17, clang-18, clang-19 // TODO: Investigate this failure on GCC 13 (in Ubuntu Jammy) // UNSUPPORTED: gcc-13 diff --git a/libcxx/test/std/ranges/range.utility/range.utility.conv/to_deduction.pass.cpp b/libcxx/test/std/ranges/range.utility/range.utility.conv/to_deduction.pass.cpp index f84cedbc122a..58307bd88d0f 100644 --- a/libcxx/test/std/ranges/range.utility/range.utility.conv/to_deduction.pass.cpp +++ b/libcxx/test/std/ranges/range.utility/range.utility.conv/to_deduction.pass.cpp @@ -9,7 +9,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 // There is a bug in older versions of Clang that causes trouble with constraints in classes like // `ContainerWithDirectCtr`. -// XFAIL: clang-16, apple-clang-15 +// XFAIL: apple-clang-15 // template class C, input_range R, class... Args> // constexpr auto to(R&& r, Args&&... args); // Since C++23 diff --git a/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.pass.cpp b/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.pass.cpp index 994ccc70a38d..284b03c32cd0 100644 --- a/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.pass.cpp +++ b/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 // UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME // The tested functionality needs deducing this. -// UNSUPPORTED: clang-16 || clang-17 +// UNSUPPORTED: clang-17 // XFAIL: apple-clang // diff --git a/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.return_type.pass.cpp b/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.return_type.pass.cpp index b2c40d160454..4c60cb0e9ae1 100644 --- a/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.return_type.pass.cpp +++ b/libcxx/test/std/utilities/format/format.arguments/format.arg/visit.return_type.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 // UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME // The tested functionality needs deducing this. -// UNSUPPORTED: clang-16 || clang-17 +// UNSUPPORTED: clang-17 // XFAIL: apple-clang // diff --git a/libcxx/test/std/utilities/format/format.arguments/format.arg/visit_format_arg.deprecated.verify.cpp b/libcxx/test/std/utilities/format/format.arguments/format.arg/visit_format_arg.deprecated.verify.cpp index acd9228369e6..6a3896c8965c 100644 --- a/libcxx/test/std/utilities/format/format.arguments/format.arg/visit_format_arg.deprecated.verify.cpp +++ b/libcxx/test/std/utilities/format/format.arguments/format.arg/visit_format_arg.deprecated.verify.cpp @@ -7,7 +7,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 // UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME -// UNSUPPORTED: clang-16 || clang-17 +// UNSUPPORTED: clang-17 // XFAIL: apple-clang // diff --git a/libcxx/test/std/utilities/variant/variant.visit.member/robust_against_adl.pass.cpp b/libcxx/test/std/utilities/variant/variant.visit.member/robust_against_adl.pass.cpp index c54f2b722d46..bea6d949924b 100644 --- a/libcxx/test/std/utilities/variant/variant.visit.member/robust_against_adl.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.visit.member/robust_against_adl.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 // The tested functionality needs deducing this. -// UNSUPPORTED: clang-16 || clang-17 +// UNSUPPORTED: clang-17 // XFAIL: apple-clang // diff --git a/libcxx/test/std/utilities/variant/variant.visit.member/visit.pass.cpp b/libcxx/test/std/utilities/variant/variant.visit.member/visit.pass.cpp index d0c909985bbb..857e85d00857 100644 --- a/libcxx/test/std/utilities/variant/variant.visit.member/visit.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.visit.member/visit.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 // The tested functionality needs deducing this. -// UNSUPPORTED: clang-16 || clang-17 +// UNSUPPORTED: clang-17 // XFAIL: apple-clang // diff --git a/libcxx/test/std/utilities/variant/variant.visit.member/visit_return_type.pass.cpp b/libcxx/test/std/utilities/variant/variant.visit.member/visit_return_type.pass.cpp index 3312197d8df9..2c1cbb06e706 100644 --- a/libcxx/test/std/utilities/variant/variant.visit.member/visit_return_type.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.visit.member/visit_return_type.pass.cpp @@ -8,7 +8,7 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17, c++20, c++23 // The tested functionality needs deducing this. -// UNSUPPORTED: clang-16 || clang-17 +// UNSUPPORTED: clang-17 // XFAIL: apple-clang // -- GitLab From fc3dff9b4637bb5960fe70add90cd27e6842d58b Mon Sep 17 00:00:00 2001 From: Jan Svoboda Date: Wed, 10 Apr 2024 09:08:01 -0700 Subject: [PATCH 414/695] [clang][modules] Stop eagerly reading files with diagnostic pragmas (#87442) This makes it so that the importer doesn't need to stat all input files of a module that contain diagnostic pragmas, reducing file system traffic. --- clang/lib/Serialization/ASTReader.cpp | 2 -- clang/test/Modules/home-is-cwd-search-paths.c | 34 +++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 clang/test/Modules/home-is-cwd-search-paths.c diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 679302e7a838..2e73a0a71401 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -6626,8 +6626,6 @@ void ASTReader::ReadPragmaDiagnosticMappings(DiagnosticsEngine &Diag) { "Invalid data, missing pragma diagnostic states"); FileID FID = ReadFileID(F, Record, Idx); assert(FID.isValid() && "invalid FileID for transition"); - // FIXME: Remove this once we don't need the side-effects. - (void)SourceMgr.getSLocEntryOrNull(FID); unsigned Transitions = Record[Idx++]; // Note that we don't need to set up Parent/ParentOffset here, because diff --git a/clang/test/Modules/home-is-cwd-search-paths.c b/clang/test/Modules/home-is-cwd-search-paths.c new file mode 100644 index 000000000000..0b8954e691bc --- /dev/null +++ b/clang/test/Modules/home-is-cwd-search-paths.c @@ -0,0 +1,34 @@ +// This test demonstrates how -fmodule-map-file-home-is-cwd with -fmodules-embed-all-files +// extend the importer search paths by relying on the side effects of pragma diagnostic +// mappings deserialization. + +// RUN: rm -rf %t +// RUN: split-file %s %t + +//--- dir1/a.modulemap +module a { header "a.h" } +//--- dir1/a.h +#include "search.h" +// The first compilation is configured such that -I search does contain the search.h header. +//--- dir1/search/search.h +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wparentheses" +#pragma clang diagnostic pop +// RUN: cd %t/dir1 && %clang_cc1 -fmodules -I search \ +// RUN: -emit-module -fmodule-name=a a.modulemap -o %t/a.pcm \ +// RUN: -fmodules-embed-all-files -fmodule-map-file-home-is-cwd + +//--- dir2/b.modulemap +module b { header "b.h" } +//--- dir2/b.h +#include "search.h" // expected-error{{'search.h' file not found}} +// The second compilation is configured such that -I search is an empty directory. +// However, since b.pcm simply embeds the headers as "search/search.h", this compilation +// ends up seeing it too. This relies solely on ASTReader::ReadPragmaDiagnosticMappings() +// eagerly reading the corresponding INPUT_FILE record before header search happens. +// Removing the eager deserialization makes this header invisible and so does removing +// the pragma directives. +// RUN: mkdir %t/dir2/search +// RUN: cd %t/dir2 && %clang_cc1 -fmodules -I search \ +// RUN: -emit-module -fmodule-name=b b.modulemap -o %t/b.pcm \ +// RUN: -fmodule-file=%t/a.pcm -verify -- GitLab From 51786eb5bfc30e7eff998323a9ce433ec4620383 Mon Sep 17 00:00:00 2001 From: Jan Svoboda Date: Wed, 10 Apr 2024 09:08:40 -0700 Subject: [PATCH 415/695] [clang][modules] Only compute affecting module maps with implicit search (#87849) When writing out a PCM, we compute the set of module maps that did affect the compilation and we strip the rest to make the output independent of them. The most common way to read a module map that is not affecting is with implicit module map search. The other option is to pass a bunch of unnecessary `-fmodule-map-file=` arguments on the command-line, in which case the client should probably not give those to Clang anyway. This makes serialization of explicit modules faster, mostly due to reduced file system traffic. --- clang/lib/Serialization/ASTWriter.cpp | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index 4cd74b1ba9d7..d2afe378bb0c 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -163,8 +163,13 @@ static TypeCode getTypeCodeForTypeClass(Type::TypeClass id) { namespace { -std::set GetAffectingModuleMaps(const Preprocessor &PP, - Module *RootModule) { +std::optional> +GetAffectingModuleMaps(const Preprocessor &PP, Module *RootModule) { + // Without implicit module map search, there's no good reason to know about + // any module maps that are not affecting. + if (!PP.getHeaderSearchInfo().getHeaderSearchOpts().ImplicitModuleMaps) + return std::nullopt; + SmallVector ModulesToProcess{RootModule}; const HeaderSearch &HS = PP.getHeaderSearchInfo(); @@ -4735,8 +4740,16 @@ void ASTWriter::computeNonAffectingInputFiles() { if (!Cache->OrigEntry) continue; - if (!isModuleMap(File.getFileCharacteristic()) || - llvm::is_contained(AffectingModuleMaps, *Cache->OrigEntry)) + // Don't prune anything other than module maps. + if (!isModuleMap(File.getFileCharacteristic())) + continue; + + // Don't prune module maps if all are guaranteed to be affecting. + if (!AffectingModuleMaps) + continue; + + // Don't prune module maps that are affecting. + if (llvm::is_contained(*AffectingModuleMaps, *Cache->OrigEntry)) continue; IsSLocAffecting[I] = false; -- GitLab From 323d3ab2574ba9d371926bb1b5c67dbe7b2b4ec3 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Apr 2024 09:08:50 -0700 Subject: [PATCH 416/695] [RISCV] Optimize undef Even vector in getWideningInterleave. (#88221) We recently optimized the code when the Odd vector was undef to fix a poison bug. There are additional optimizations we can do if the even vector is undef. With Zvbb, we can use a single vwsll. Without Zvbb, we can use a vzext.vf2 and a vsll. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 13 ++++++++++-- .../CodeGen/RISCV/rvv/vector-interleave.ll | 20 +++++++++++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 6e97575c167c..944d8b6de895 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4638,8 +4638,17 @@ static SDValue getWideningInterleave(SDValue EvenV, SDValue OddV, Subtarget.getXLenVT())); Interleaved = DAG.getNode(RISCVISD::VWSLL_VL, DL, WideContainerVT, OddV, OffsetVec, Passthru, Mask, VL); - Interleaved = DAG.getNode(RISCVISD::VWADDU_W_VL, DL, WideContainerVT, - Interleaved, EvenV, Passthru, Mask, VL); + if (!EvenV.isUndef()) + Interleaved = DAG.getNode(RISCVISD::VWADDU_W_VL, DL, WideContainerVT, + Interleaved, EvenV, Passthru, Mask, VL); + } else if (EvenV.isUndef()) { + Interleaved = + DAG.getNode(RISCVISD::VZEXT_VL, DL, WideContainerVT, OddV, Mask, VL); + + SDValue OffsetVec = + DAG.getConstant(VecVT.getScalarSizeInBits(), DL, WideContainerVT); + Interleaved = DAG.getNode(RISCVISD::SHL_VL, DL, WideContainerVT, + Interleaved, OffsetVec, Passthru, Mask, VL); } else { // FIXME: We should freeze the odd vector here. We already handled the case // of provably undef/poison above. diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll index 0992c9fe495f..4b6ad0f27214 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll @@ -674,6 +674,26 @@ define @vector_interleave_nxv8i32_nxv4i32_poison( %res } +define @vector_interleave_nxv8i32_nxv4i32_poison2( %a) { +; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32_poison2: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma +; CHECK-NEXT: vzext.vf2 v12, v8 +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: vsll.vx v8, v12, a0 +; CHECK-NEXT: ret +; +; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32_poison2: +; ZVBB: # %bb.0: +; ZVBB-NEXT: li a0, 32 +; ZVBB-NEXT: vsetvli a1, zero, e32, m2, ta, ma +; ZVBB-NEXT: vwsll.vx v12, v8, a0 +; ZVBB-NEXT: vmv4r.v v8, v12 +; ZVBB-NEXT: ret + %res = call @llvm.experimental.vector.interleave2.nxv8i32( poison, %a) + ret %res +} + declare @llvm.experimental.vector.interleave2.nxv64f16(, ) declare @llvm.experimental.vector.interleave2.nxv32f32(, ) declare @llvm.experimental.vector.interleave2.nxv16f64(, ) -- GitLab From e72c949c15208ba3dd53a9cebfee02734965a678 Mon Sep 17 00:00:00 2001 From: Evgenii Stepanov Date: Wed, 10 Apr 2024 09:12:25 -0700 Subject: [PATCH 417/695] [msan] Overflow intrinsics. (#88210) --- .../Instrumentation/MemorySanitizer.cpp | 24 ++++ .../MemorySanitizer/overflow.ll | 103 ++++++------------ 2 files changed, 59 insertions(+), 68 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 46b9181c8922..ee3531bbd68d 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -3715,8 +3715,32 @@ struct MemorySanitizerVisitor : public InstVisitor { setOrigin(&I, getOrigin(&I, 0)); } + void handleArithmeticWithOverflow(IntrinsicInst &I) { + IRBuilder<> IRB(&I); + Value *Shadow0 = getShadow(&I, 0); + Value *Shadow1 = getShadow(&I, 1); + Value *ShadowElt0 = IRB.CreateOr(Shadow0, Shadow1); + Value *ShadowElt1 = + IRB.CreateICmpNE(ShadowElt0, getCleanShadow(ShadowElt0)); + + Value *Shadow = PoisonValue::get(getShadowTy(&I)); + Shadow = IRB.CreateInsertValue(Shadow, ShadowElt0, 0); + Shadow = IRB.CreateInsertValue(Shadow, ShadowElt1, 1); + + setShadow(&I, Shadow); + setOriginForNaryOp(I); + } + void visitIntrinsicInst(IntrinsicInst &I) { switch (I.getIntrinsicID()) { + case Intrinsic::uadd_with_overflow: + case Intrinsic::sadd_with_overflow: + case Intrinsic::usub_with_overflow: + case Intrinsic::ssub_with_overflow: + case Intrinsic::umul_with_overflow: + case Intrinsic::smul_with_overflow: + handleArithmeticWithOverflow(I); + break; case Intrinsic::abs: handleAbsIntrinsic(I); break; diff --git a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll index b1304faec3df..0cfae0008263 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/overflow.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/overflow.ll @@ -10,16 +10,12 @@ define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) @@ -32,16 +28,12 @@ define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) @@ -54,16 +46,12 @@ define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b) @@ -75,16 +63,12 @@ define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b) @@ -96,16 +80,12 @@ define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b) @@ -117,16 +97,12 @@ define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 { ; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] -; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 4: +; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]]) -; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { i64, i1 } [[RES]] ; %res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b) @@ -139,18 +115,12 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 -; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0 -; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] -; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] -; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] -; CHECK-NEXT: unreachable -; CHECK: 6: +; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { <4 x i32>, <4 x i1> } poison, <4 x i32> [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { <4 x i32>, <4 x i1> } [[TMP5]], <4 x i1> [[TMP4]], 1 ; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]]) -; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store { <4 x i32>, <4 x i1> } [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]] ; %res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b) @@ -158,6 +128,3 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32 } attributes #0 = { sanitize_memory } -;. -; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000} -;. -- GitLab From 43b2b2ebce635bec1e3c060092ea75db858ee3fd Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Wed, 10 Apr 2024 18:25:16 +0200 Subject: [PATCH 418/695] Revert "Fix complex log1p accuracy with large abs values." (#88290) Reverts llvm/llvm-project#88260 The test fails on the GCC7 buildbot. --- .../ComplexToStandard/ComplexToStandard.cpp | 50 +++++++++---------- .../convert-to-standard.mlir | 48 +++++++----------- 2 files changed, 41 insertions(+), 57 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 0aa1de5fa5d9..9c3c4d96a301 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -570,39 +570,37 @@ struct Log1pOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { auto type = cast(adaptor.getComplex().getType()); auto elementType = cast(type.getElementType()); - arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); + arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); mlir::ImplicitLocOpBuilder b(op.getLoc(), rewriter); - Value real = b.create(adaptor.getComplex()); - Value imag = b.create(adaptor.getComplex()); + Value real = b.create(elementType, adaptor.getComplex()); + Value imag = b.create(elementType, adaptor.getComplex()); Value half = b.create(elementType, b.getFloatAttr(elementType, 0.5)); Value one = b.create(elementType, b.getFloatAttr(elementType, 1)); - Value realPlusOne = b.create(real, one, fmf); - Value absRealPlusOne = b.create(realPlusOne, fmf); - Value absImag = b.create(imag, fmf); - - Value maxAbs = b.create(absRealPlusOne, absImag, fmf); - Value minAbs = b.create(absRealPlusOne, absImag, fmf); - - Value maxAbsOfRealPlusOneAndImagMinusOne = b.create( - b.create(arith::CmpFPredicate::OGT, realPlusOne, absImag, - fmf), - real, b.create(maxAbs, one, fmf)); - Value minMaxRatio = b.create(minAbs, maxAbs, fmf); - Value logOfMaxAbsOfRealPlusOneAndImag = - b.create(maxAbsOfRealPlusOneAndImagMinusOne, fmf); - Value logOfSqrtPart = b.create( - b.create(minMaxRatio, minMaxRatio, fmf), fmf); - Value r = b.create( - b.create(half, logOfSqrtPart, fmf), - logOfMaxAbsOfRealPlusOneAndImag, fmf); - Value resultReal = b.create( - b.create(arith::CmpFPredicate::UNO, r, r, fmf), minAbs, - r); - Value resultImag = b.create(imag, realPlusOne, fmf); + Value two = b.create(elementType, + b.getFloatAttr(elementType, 2)); + + // log1p(a+bi) = .5*log((a+1)^2+b^2) + i*atan2(b, a + 1) + // log((a+1)+bi) = .5*log(a*a + 2*a + 1 + b*b) + i*atan2(b, a+1) + // log((a+1)+bi) = .5*log1p(a*a + 2*a + b*b) + i*atan2(b, a+1) + Value sumSq = b.create(real, real, fmf.getValue()); + sumSq = b.create( + sumSq, b.create(real, two, fmf.getValue()), + fmf.getValue()); + sumSq = b.create( + sumSq, b.create(imag, imag, fmf.getValue()), + fmf.getValue()); + Value logSumSq = + b.create(elementType, sumSq, fmf.getValue()); + Value resultReal = b.create(logSumSq, half, fmf.getValue()); + + Value realPlusOne = b.create(real, one, fmf.getValue()); + + Value resultImag = + b.create(elementType, imag, realPlusOne, fmf.getValue()); rewriter.replaceOpWithNewOp(op, type, resultReal, resultImag); return success(); diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index 43918904a09f..f5d9499eadda 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -300,22 +300,15 @@ func.func @complex_log1p(%arg: complex) -> complex { // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32 +// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] : f32 +// CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] : f32 +// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] : f32 +// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] : f32 +// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] : f32 +// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] : f32 // CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] : f32 -// CHECK: %[[ABS_REAL_PLUS_ONE:.*]] = math.absf %[[REAL_PLUS_ONE]] : f32 -// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] : f32 -// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 -// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 -// CHECK: %[[CMPF:.*]] = arith.cmpf ogt, %[[REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 -// CHECK: %[[MAX_MINUS_ONE:.*]] = arith.subf %[[MAX]], %cst_0 : f32 -// CHECK: %[[SELECT:.*]] = arith.select %[[CMPF]], %0, %[[MAX_MINUS_ONE]] : f32 -// CHECK: %[[MIN_MAX_RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 -// CHECK: %[[LOG_1:.*]] = math.log1p %[[SELECT]] : f32 -// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[MIN_MAX_RATIO]], %[[MIN_MAX_RATIO]] : f32 -// CHECK: %[[LOG_SQ:.*]] = math.log1p %[[RATIO_SQ]] : f32 -// CHECK: %[[HALF_LOG_SQ:.*]] = arith.mulf %cst, %[[LOG_SQ]] : f32 -// CHECK: %[[R:.*]] = arith.addf %[[HALF_LOG_SQ]], %[[LOG_1]] : f32 -// CHECK: %[[ISNAN:.*]] = arith.cmpf uno, %[[R]], %[[R]] : f32 -// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[ISNAN]], %[[MIN]], %[[R]] : f32 // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex @@ -970,22 +963,15 @@ func.func @complex_log1p_with_fmf(%arg: complex) -> complex { // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] fastmath : f32 -// CHECK: %[[ABS_REAL_PLUS_ONE:.*]] = math.absf %[[REAL_PLUS_ONE]] fastmath : f32 -// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 -// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 -// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 -// CHECK: %[[CMPF:.*]] = arith.cmpf ogt, %[[REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 -// CHECK: %[[MAX_MINUS_ONE:.*]] = arith.subf %[[MAX]], %cst_0 fastmath : f32 -// CHECK: %[[SELECT:.*]] = arith.select %[[CMPF]], %0, %[[MAX_MINUS_ONE]] : f32 -// CHECK: %[[MIN_MAX_RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 -// CHECK: %[[LOG_1:.*]] = math.log1p %[[SELECT]] fastmath : f32 -// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[MIN_MAX_RATIO]], %[[MIN_MAX_RATIO]] fastmath : f32 -// CHECK: %[[LOG_SQ:.*]] = math.log1p %[[RATIO_SQ]] fastmath : f32 -// CHECK: %[[HALF_LOG_SQ:.*]] = arith.mulf %cst, %[[LOG_SQ]] fastmath : f32 -// CHECK: %[[R:.*]] = arith.addf %[[HALF_LOG_SQ]], %[[LOG_1]] fastmath : f32 -// CHECK: %[[ISNAN:.*]] = arith.cmpf uno, %[[R]], %[[R]] fastmath : f32 -// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[ISNAN]], %[[MIN]], %[[R]] : f32 +// CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32 +// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] fastmath : f32 +// CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] fastmath : f32 +// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] fastmath : f32 +// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] fastmath : f32 +// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] fastmath : f32 +// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] fastmath : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] fastmath : f32 +// CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] fastmath : f32 // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] fastmath : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex -- GitLab From 48c5c70fdd3bec2929e2e903e3bf4494a65f7a92 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Wed, 10 Apr 2024 09:23:23 -0700 Subject: [PATCH 419/695] [NFC] Update SemaRef.Diag to just Diag in OpenACC implementation I missed these two in my last patch as the two patches crossed in review, so correct this now. --- clang/lib/Sema/SemaOpenACC.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index b6afb80b873e..a6f4453e525d 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -102,10 +102,10 @@ SemaOpenACC::ActOnClause(ArrayRef ExistingClauses, }); if (Itr != ExistingClauses.end()) { - SemaRef.Diag(Clause.getBeginLoc(), + Diag(Clause.getBeginLoc(), diag::err_acc_duplicate_clause_disallowed) << Clause.getDirectiveKind() << Clause.getClauseKind(); - SemaRef.Diag((*Itr)->getBeginLoc(), diag::note_acc_previous_clause_here); + Diag((*Itr)->getBeginLoc(), diag::note_acc_previous_clause_here); return nullptr; } -- GitLab From 3d468566eb395995ac54fcf90d3afb9b9f822eb3 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Wed, 10 Apr 2024 09:37:01 -0700 Subject: [PATCH 420/695] [NFC] Remove unneeded 'maybe_unused' attributes This was added while we only had a partial implementation of clauses, so we don't need these anymore. --- clang/lib/Serialization/ASTReader.cpp | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 2e73a0a71401..0ca7f6600eee 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -11754,11 +11754,8 @@ void ASTRecordReader::readOMPChildren(OMPChildren *Data) { OpenACCClause *ASTRecordReader::readOpenACCClause() { OpenACCClauseKind ClauseKind = readEnum(); - // TODO OpenACC: We don't have these used anywhere, but eventually we should - // be constructing the Clauses with them, so these attributes can go away at - // that point. - [[maybe_unused]] SourceLocation BeginLoc = readSourceLocation(); - [[maybe_unused]] SourceLocation EndLoc = readSourceLocation(); + SourceLocation BeginLoc = readSourceLocation(); + SourceLocation EndLoc = readSourceLocation(); switch (ClauseKind) { case OpenACCClauseKind::Default: { -- GitLab From f388a3a446ef2566d73b6a73ba300738f8c2c002 Mon Sep 17 00:00:00 2001 From: Aart Bik Date: Wed, 10 Apr 2024 09:42:12 -0700 Subject: [PATCH 421/695] [mlir][sparse] update doc and examples of the [dis]assemble operations (#88213) The doc and examples of the [dis]assemble operations did not reflect all the recent changes on order of the operands. Also clarified some of the text. --- .../SparseTensor/IR/SparseTensorOps.td | 89 +++++++++---------- mlir/test/Dialect/SparseTensor/invalid.mlir | 6 +- mlir/test/Dialect/SparseTensor/roundtrip.mlir | 14 +-- .../Dialect/SparseTensor/CPU/sparse_pack.mlir | 10 ++- 4 files changed, 61 insertions(+), 58 deletions(-) diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td index 5df8a176459b..0cfc64f9988a 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorOps.td @@ -58,37 +58,35 @@ def SparseTensor_AssembleOp : SparseTensor_Op<"assemble", [Pure]>, Arguments<(ins Variadic>:$levels, TensorOf<[AnyType]>:$values)>, Results<(outs AnySparseTensor: $result)> { - let summary = "Returns a sparse tensor assembled from the given values and levels"; + let summary = "Returns a sparse tensor assembled from the given levels and values"; let description = [{ - Assembles the values and per-level coordinate or postion arrays into a sparse tensor. - The order and types of provided levels must be consistent with the actual storage - layout of the returned sparse tensor described below. + Assembles the per-level position and coordinate arrays together with + the values arrays into a sparse tensor. The order and types of the + provided levels must be consistent with the actual storage layout of + the returned sparse tensor described below. - - `values : tensor` - supplies the value for each stored element in the sparse tensor. - `levels: [tensor, ...]` - each supplies the sparse tensor coordinates scheme in the sparse tensor for - the corresponding level as specifed by `sparse_tensor::StorageLayout`. - - This operation can be used to assemble a sparse tensor from external - sources; e.g., when passing two numpy arrays from Python. - - Disclaimer: This is the user's responsibility to provide input that can be - correctly interpreted by the sparsifier, which does not perform - any sanity test during runtime to verify data integrity. + supplies the sparse tensor position and coordinate arrays + of the sparse tensor for the corresponding level as specifed by + `sparse_tensor::StorageLayout`. + - `values : tensor` + supplies the values array for the stored elements in the sparse tensor. - TODO: The returned tensor is allowed (in principle) to have non-identity - dimOrdering/higherOrdering mappings. However, the current implementation - does not yet support them. + This operation can be used to assemble a sparse tensor from an + external source; e.g., by passing numpy arrays from Python. It + is the user's responsibility to provide input that can be correctly + interpreted by the sparsifier, which does not perform any sanity + test to verify data integrity. Example: ```mlir - %values = arith.constant dense<[ 1.1, 2.2, 3.3 ]> : tensor<3xf64> - %coordinates = arith.constant dense<[[0,0], [1,2], [1,3]]> : tensor<3x2xindex> - %st = sparse_tensor.assemble %values, %coordinates - : tensor<3xf64>, tensor<3x2xindex> to tensor<3x4xf64, #COO> + %pos = arith.constant dense<[0, 3]> : tensor<2xindex> + %index = arith.constant dense<[[0,0], [1,2], [1,3]]> : tensor<3x2xindex> + %values = arith.constant dense<[ 1.1, 2.2, 3.3 ]> : tensor<3xf64> + %s = sparse_tensor.assemble (%pos, %index), %values + : (tensor<2xindex>, tensor<3x2xindex>), tensor<3xf64> to tensor<3x4xf64, #COO> // yields COO format |1.1, 0.0, 0.0, 0.0| // of 3x4 matrix |0.0, 0.0, 2.2, 3.3| // |0.0, 0.0, 0.0, 0.0| @@ -96,8 +94,8 @@ def SparseTensor_AssembleOp : SparseTensor_Op<"assemble", [Pure]>, }]; let assemblyFormat = - "` ` `(` $levels `)` `,` $values attr-dict" - " `:` `(` type($levels) `)` `,` type($values) `to` type($result)"; + "` ` `(` $levels `)` `,` $values attr-dict `:`" + " `(` type($levels) `)` `,` type($values) `to` type($result)"; let hasVerifier = 1; } @@ -110,21 +108,20 @@ def SparseTensor_DisassembleOp : SparseTensor_Op<"disassemble", [Pure, SameVaria TensorOf<[AnyType]>:$ret_values, Variadic:$lvl_lens, AnyIndexingScalarLike:$val_len)> { - let summary = "Returns the (values, coordinates) pair disassembled from the input tensor"; + let summary = "Copies the levels and values of the given sparse tensor"; let description = [{ The disassemble operation is the inverse of `sparse_tensor::assemble`. - It returns the values and per-level position and coordinate array to the - user from the sparse tensor along with the actual length of the memory used - in each returned buffer. This operation can be used for returning an - disassembled MLIR sparse tensor to frontend; e.g., returning two numpy arrays - to Python. - - Disclaimer: This is the user's responsibility to allocate large enough buffers - to hold the sparse tensor. The sparsifier simply copies each fields - of the sparse tensor into the user-supplied buffer without bound checking. + It copies the per-level position and coordinate arrays together with + the values array of the given sparse tensor into the user-supplied buffers + along with the actual length of the memory used in each returned buffer. - TODO: the current implementation does not yet support non-identity mappings. + This operation can be used for returning a disassembled MLIR sparse tensor; + e.g., copying the sparse tensor contents into pre-allocated numpy arrays + back to Python. It is the user's responsibility to allocate large enough + buffers of the appropriate types to hold the sparse tensor contents. + The sparsifier simply copies all fields of the sparse tensor into the + user-supplied buffers without any sanity test to verify data integrity. Example: @@ -132,26 +129,26 @@ def SparseTensor_DisassembleOp : SparseTensor_Op<"disassemble", [Pure, SameVaria // input COO format |1.1, 0.0, 0.0, 0.0| // of 3x4 matrix |0.0, 0.0, 2.2, 3.3| // |0.0, 0.0, 0.0, 0.0| - %v, %p, %c, %v_len, %p_len, %c_len = - sparse_tensor.disassemble %sp : tensor<3x4xf64, #COO> - out_lvls(%op, %oi) : tensor<2xindex>, tensor<3x2xindex>, - out_vals(%od) : tensor<3xf64> -> - tensor<3xf64>, (tensor<2xindex>, tensor<3x2xindex>), index, (index, index) - // %v = arith.constant dense<[ 1.1, 2.2, 3.3 ]> : tensor<3xf64> + %p, %c, %v, %p_len, %c_len, %v_len = + sparse_tensor.disassemble %s : tensor<3x4xf64, #COO> + out_lvls(%op, %oi : tensor<2xindex>, tensor<3x2xindex>) + out_vals(%od : tensor<3xf64>) -> + (tensor<2xindex>, tensor<3x2xindex>), tensor<3xf64>, (index, index), index // %p = arith.constant dense<[ 0, 3 ]> : tensor<2xindex> // %c = arith.constant dense<[[0,0], [1,2], [1,3]]> : tensor<3x2xindex> - // %v_len = 3 + // %v = arith.constant dense<[ 1.1, 2.2, 3.3 ]> : tensor<3xf64> // %p_len = 2 // %c_len = 6 (3x2) + // %v_len = 3 ``` }]; let assemblyFormat = - "$tensor `:` type($tensor) " + "$tensor attr-dict `:` type($tensor)" "`out_lvls` `(` $out_levels `:` type($out_levels) `)` " - "`out_vals` `(` $out_values `:` type($out_values) `)` attr-dict" - "`->` `(` type($ret_levels) `)` `,` type($ret_values) `,` " - "`(` type($lvl_lens) `)` `,` type($val_len)"; + "`out_vals` `(` $out_values `:` type($out_values) `)` `->`" + "`(` type($ret_levels) `)` `,` type($ret_values) `,` " + "`(` type($lvl_lens) `)` `,` type($val_len)"; let hasVerifier = 1; } diff --git a/mlir/test/Dialect/SparseTensor/invalid.mlir b/mlir/test/Dialect/SparseTensor/invalid.mlir index 18851f29d8ea..7f5c05190fc9 100644 --- a/mlir/test/Dialect/SparseTensor/invalid.mlir +++ b/mlir/test/Dialect/SparseTensor/invalid.mlir @@ -60,7 +60,7 @@ func.func @invalid_pack_mis_position(%values: tensor<6xf64>, %coordinates: tenso func.func @invalid_unpack_type(%sp: tensor<100xf32, #SparseVector>, %values: tensor<6xf64>, %pos: tensor<2xi32>, %coordinates: tensor<6x1xi32>) { // expected-error@+1 {{input/output element-types don't match}} - %rv, %rp, %rc, %vl, %pl, %cl = sparse_tensor.disassemble %sp : tensor<100xf32, #SparseVector> + %rp, %rc, %rv, %pl, %cl, %vl = sparse_tensor.disassemble %sp : tensor<100xf32, #SparseVector> out_lvls(%pos, %coordinates : tensor<2xi32>, tensor<6x1xi32>) out_vals(%values : tensor<6xf64>) -> (tensor<2xi32>, tensor<6x1xi32>), tensor<6xf64>, (index, index), index @@ -73,7 +73,7 @@ func.func @invalid_unpack_type(%sp: tensor<100xf32, #SparseVector>, %values: ten func.func @invalid_unpack_type(%sp: tensor<100x2xf64, #SparseVector>, %values: tensor<6xf64>, %pos: tensor<2xi32>, %coordinates: tensor<6x3xi32>) { // expected-error@+1 {{input/output trailing COO level-ranks don't match}} - %rv, %rp, %rc, %vl, %pl, %cl = sparse_tensor.disassemble %sp : tensor<100x2xf64, #SparseVector> + %rp, %rc, %rv, %pl, %cl, %vl = sparse_tensor.disassemble %sp : tensor<100x2xf64, #SparseVector> out_lvls(%pos, %coordinates : tensor<2xi32>, tensor<6x3xi32> ) out_vals(%values : tensor<6xf64>) -> (tensor<2xi32>, tensor<6x3xi32>), tensor<6xf64>, (index, index), index @@ -86,7 +86,7 @@ func.func @invalid_unpack_type(%sp: tensor<100x2xf64, #SparseVector>, %values: t func.func @invalid_unpack_mis_position(%sp: tensor<2x100xf64, #CSR>, %values: tensor<6xf64>, %coordinates: tensor<6xi32>) { // expected-error@+1 {{inconsistent number of fields between input/output}} - %rv, %rc, %vl, %pl = sparse_tensor.disassemble %sp : tensor<2x100xf64, #CSR> + %rc, %rv, %cl, %vl = sparse_tensor.disassemble %sp : tensor<2x100xf64, #CSR> out_lvls(%coordinates : tensor<6xi32>) out_vals(%values : tensor<6xf64>) -> (tensor<6xi32>), tensor<6xf64>, (index), index diff --git a/mlir/test/Dialect/SparseTensor/roundtrip.mlir b/mlir/test/Dialect/SparseTensor/roundtrip.mlir index a47a3d5119f9..12f69c1d37b9 100644 --- a/mlir/test/Dialect/SparseTensor/roundtrip.mlir +++ b/mlir/test/Dialect/SparseTensor/roundtrip.mlir @@ -33,21 +33,21 @@ func.func @sparse_pack(%pos: tensor<2xi32>, %index: tensor<6x1xi32>, %data: tens #SparseVector = #sparse_tensor.encoding<{map = (d0) -> (d0 : compressed), crdWidth=32}> // CHECK-LABEL: func @sparse_unpack( // CHECK-SAME: %[[T:.*]]: tensor<100xf64, # -// CHECK-SAME: %[[OD:.*]]: tensor<6xf64> -// CHECK-SAME: %[[OP:.*]]: tensor<2xindex> -// CHECK-SAME: %[[OI:.*]]: tensor<6x1xi32> +// CHECK-SAME: %[[OP:.*]]: tensor<2xindex>, +// CHECK-SAME: %[[OI:.*]]: tensor<6x1xi32>, +// CHECK-SAME: %[[OD:.*]]: tensor<6xf64>) // CHECK: %[[P:.*]]:2, %[[D:.*]], %[[PL:.*]]:2, %[[DL:.*]] = sparse_tensor.disassemble %[[T]] // CHECK: return %[[P]]#0, %[[P]]#1, %[[D]] func.func @sparse_unpack(%sp : tensor<100xf64, #SparseVector>, - %od : tensor<6xf64>, %op : tensor<2xindex>, - %oi : tensor<6x1xi32>) + %oi : tensor<6x1xi32>, + %od : tensor<6xf64>) -> (tensor<2xindex>, tensor<6x1xi32>, tensor<6xf64>) { - %rp, %ri, %rd, %vl, %pl, %cl = sparse_tensor.disassemble %sp : tensor<100xf64, #SparseVector> + %rp, %ri, %d, %rpl, %ril, %dl = sparse_tensor.disassemble %sp : tensor<100xf64, #SparseVector> out_lvls(%op, %oi : tensor<2xindex>, tensor<6x1xi32>) out_vals(%od : tensor<6xf64>) -> (tensor<2xindex>, tensor<6x1xi32>), tensor<6xf64>, (index, index), index - return %rp, %ri, %rd : tensor<2xindex>, tensor<6x1xi32>, tensor<6xf64> + return %rp, %ri, %d : tensor<2xindex>, tensor<6x1xi32>, tensor<6xf64> } // ----- diff --git a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir index 7ecccad212cd..5415625ff05d 100644 --- a/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir +++ b/mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir @@ -231,7 +231,7 @@ module { %od = tensor.empty() : tensor<3xf64> %op = tensor.empty() : tensor<2xi32> %oi = tensor.empty() : tensor<3x2xi32> - %p, %i, %d, %dl, %pl, %il = sparse_tensor.disassemble %s5 : tensor<10x10xf64, #SortedCOOI32> + %p, %i, %d, %pl, %il, %dl = sparse_tensor.disassemble %s5 : tensor<10x10xf64, #SortedCOOI32> out_lvls(%op, %oi : tensor<2xi32>, tensor<3x2xi32>) out_vals(%od : tensor<3xf64>) -> (tensor<2xi32>, tensor<3x2xi32>), tensor<3xf64>, (i32, i64), index @@ -244,10 +244,13 @@ module { %vi = vector.transfer_read %i[%c0, %c0], %i0 : tensor<3x2xi32>, vector<3x2xi32> vector.print %vi : vector<3x2xi32> + // CHECK-NEXT: 3 + vector.print %dl : index + %d_csr = tensor.empty() : tensor<4xf64> %p_csr = tensor.empty() : tensor<3xi32> %i_csr = tensor.empty() : tensor<3xi32> - %rp_csr, %ri_csr, %rd_csr, %ld_csr, %lp_csr, %li_csr = sparse_tensor.disassemble %csr : tensor<2x2xf64, #CSR> + %rp_csr, %ri_csr, %rd_csr, %lp_csr, %li_csr, %ld_csr = sparse_tensor.disassemble %csr : tensor<2x2xf64, #CSR> out_lvls(%p_csr, %i_csr : tensor<3xi32>, tensor<3xi32>) out_vals(%d_csr : tensor<4xf64>) -> (tensor<3xi32>, tensor<3xi32>), tensor<4xf64>, (i32, i64), index @@ -256,6 +259,9 @@ module { %vd_csr = vector.transfer_read %rd_csr[%c0], %f0 : tensor<4xf64>, vector<3xf64> vector.print %vd_csr : vector<3xf64> + // CHECK-NEXT: 3 + vector.print %ld_csr : index + %bod = tensor.empty() : tensor<6xf64> %bop = tensor.empty() : tensor<4xindex> %boi = tensor.empty() : tensor<6x2xindex> -- GitLab From 798e04f93769318db857b27f51020e7115e00301 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 10 Apr 2024 17:50:13 +0100 Subject: [PATCH 422/695] Fix MSVC "not all control paths return a value" warning. NFC. --- clang/include/clang/Basic/OpenACCKinds.h | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/include/clang/Basic/OpenACCKinds.h b/clang/include/clang/Basic/OpenACCKinds.h index e191e9e0a5a1..3414df999917 100644 --- a/clang/include/clang/Basic/OpenACCKinds.h +++ b/clang/include/clang/Basic/OpenACCKinds.h @@ -430,6 +430,7 @@ inline StreamTy &printOpenACCDefaultClauseKind(StreamTy &Out, case OpenACCDefaultClauseKind::Invalid: return Out << ""; } + llvm_unreachable("Unknown OpenACCDefaultClauseKind enum"); } inline const StreamingDiagnostic &operator<<(const StreamingDiagnostic &Out, -- GitLab From 335d5d5f47b883055e676ffe5f981469a5f5f4f6 Mon Sep 17 00:00:00 2001 From: Vyacheslav Levytskyy Date: Wed, 10 Apr 2024 19:04:31 +0200 Subject: [PATCH 423/695] [SPIRV] Tweak parsing of base type name in builtins (#88255) This PR is a small improvement of parsing of base type name in builtins, allowing to understand `unsigned ...` types. The test case that fails without the fix is attached. --- llvm/lib/Target/SPIRV/SPIRVUtils.cpp | 16 ++++++++++++---- llvm/test/CodeGen/SPIRV/SampledImageRetType.ll | 9 +++++++++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp index c87c1293c622..299a4341193b 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp @@ -374,13 +374,21 @@ Type *parseBasicTypeName(StringRef TypeName, LLVMContext &Ctx) { return Type::getVoidTy(Ctx); else if (TypeName.consume_front("bool")) return Type::getIntNTy(Ctx, 1); - else if (TypeName.consume_front("char") || TypeName.consume_front("uchar")) + else if (TypeName.consume_front("char") || + TypeName.consume_front("unsigned char") || + TypeName.consume_front("uchar")) return Type::getInt8Ty(Ctx); - else if (TypeName.consume_front("short") || TypeName.consume_front("ushort")) + else if (TypeName.consume_front("short") || + TypeName.consume_front("unsigned short") || + TypeName.consume_front("ushort")) return Type::getInt16Ty(Ctx); - else if (TypeName.consume_front("int") || TypeName.consume_front("uint")) + else if (TypeName.consume_front("int") || + TypeName.consume_front("unsigned int") || + TypeName.consume_front("uint")) return Type::getInt32Ty(Ctx); - else if (TypeName.consume_front("long") || TypeName.consume_front("ulong")) + else if (TypeName.consume_front("long") || + TypeName.consume_front("unsigned long") || + TypeName.consume_front("ulong")) return Type::getInt64Ty(Ctx); else if (TypeName.consume_front("half")) return Type::getHalfTy(Ctx); diff --git a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll index 1aa3af83bcd2..7af5876a023e 100644 --- a/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll +++ b/llvm/test/CodeGen/SPIRV/SampledImageRetType.ll @@ -8,6 +8,8 @@ declare dso_local spir_func ptr addrspace(4) @_Z20__spirv_SampledImageI14ocl_ima declare dso_local spir_func <4 x float> @_Z30__spirv_ImageSampleExplicitLodIPvDv4_fiET0_T_T1_if(ptr addrspace(4) %0, i32 %1, i32 %2, float %3) local_unnamed_addr +declare dso_local spir_func <4 x i32> @_Z30__spirv_ImageSampleExplicitLodI32__spirv_SampledImage__image1d_roDv4_jfET0_T_T1_if(target("spirv.SampledImage", void, 0, 0, 0, 0, 0, 0, 0) %0, float %1, i32 %2, float %3) local_unnamed_addr + @__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(2) constant <3 x i64>, align 32 define weak_odr dso_local spir_kernel void @_ZTS17image_kernel_readILi1EE(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 0), target("spirv.Sampler")) { @@ -25,3 +27,10 @@ define weak_odr dso_local spir_kernel void @_ZTS17image_kernel_readILi1EE(target ret void } + +define weak_odr dso_local spir_kernel void @foo_lod(target("spirv.SampledImage", void, 0, 0, 0, 0, 0, 0, 0) %_arg) { + %lod = call spir_func <4 x i32> @_Z30__spirv_ImageSampleExplicitLodI32__spirv_SampledImage__image1d_roDv4_jfET0_T_T1_if(target("spirv.SampledImage", void, 0, 0, 0, 0, 0, 0, 0) %_arg, float 0x3FE7FFEB00000000, i32 2, float 0.000000e+00) +; CHECK: %[[#sampled_image_lod:]] = OpFunctionParameter %[[#sampled_image_t]] +; CHECK: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#sampled_image_lod]] %[[#]] {{.*}} %[[#]] + ret void +} -- GitLab From 4dcf33b6c2806216dfe8c5e1e3582a45516dbc69 Mon Sep 17 00:00:00 2001 From: David Green Date: Wed, 10 Apr 2024 18:13:57 +0100 Subject: [PATCH 424/695] [AArch64] Cleanup and GISel coverage for lrint tests. NFC --- llvm/test/CodeGen/AArch64/lrint-conv.ll | 66 ++++++++++++++--------- llvm/test/CodeGen/AArch64/vector-lrint.ll | 39 ++++++++++---- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/lrint-conv.ll b/llvm/test/CodeGen/AArch64/lrint-conv.ll index 80f1e8b8fc18..b61d6f04b400 100644 --- a/llvm/test/CodeGen/AArch64/lrint-conv.ll +++ b/llvm/test/CodeGen/AArch64/lrint-conv.ll @@ -1,64 +1,78 @@ -; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s -; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64 | FileCheck %s --check-prefixes=FALLBACK,CHECK +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc < %s -mtriple=aarch64 | FileCheck %s +; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI + +; CHECK-GI: warning: Instruction selection used fallback path for testmswl +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsll -; CHECK-LABEL: testmsws: -; CHECK: frintx [[REG:s[0-9]]], s0 -; CHECK-NEXT: fcvtzs x0, [[REG]] -; CHECK: ret -; FALLBACK-NOT: remark{{.*}}testmsws define i32 @testmsws(float %x) { +; CHECK-LABEL: testmsws: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: frintx s0, s0 +; CHECK-NEXT: fcvtzs x0, s0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.lrint.i64.f32(float %x) %conv = trunc i64 %0 to i32 ret i32 %conv } -; CHECK-LABEL: testmsxs: -; CHECK: frintx [[REG:s[0-9]]], s0 -; CHECK-NEXT: fcvtzs x0, [[REG]] -; CHECK-NEXT: ret -; FALLBACK-NOT: remark{{.*}}testmsxs define i64 @testmsxs(float %x) { +; CHECK-LABEL: testmsxs: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: frintx s0, s0 +; CHECK-NEXT: fcvtzs x0, s0 +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.lrint.i64.f32(float %x) ret i64 %0 } -; CHECK-LABEL: testmswd: -; CHECK: frintx [[REG:d[0-9]]], d0 -; CHECK-NEXT: fcvtzs x0, [[REG]] -; CHECK: ret -; FALLBACK-NOT: remark{{.*}}testmswd define i32 @testmswd(double %x) { +; CHECK-LABEL: testmswd: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: frintx d0, d0 +; CHECK-NEXT: fcvtzs x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.lrint.i64.f64(double %x) %conv = trunc i64 %0 to i32 ret i32 %conv } -; CHECK-LABEL: testmsxd: -; CHECK: frintx [[REG:d[0-9]]], d0 -; CHECK-NEXT: fcvtzs x0, [[REG]] -; CHECK-NEXT: ret -; FALLBACK-NOT: remark{{.*}}testmsxd define i64 @testmsxd(double %x) { +; CHECK-LABEL: testmsxd: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: frintx d0, d0 +; CHECK-NEXT: fcvtzs x0, d0 +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.lrint.i64.f64(double %x) ret i64 %0 } -; CHECK-LABEL: testmswl: -; CHECK: bl lrintl define dso_local i32 @testmswl(fp128 %x) { +; CHECK-LABEL: testmswl: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: bl lrintl +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x) %conv = trunc i64 %0 to i32 ret i32 %conv } -; CHECK-LABEL: testmsll: -; CHECK: b lrintl define dso_local i64 @testmsll(fp128 %x) { +; CHECK-LABEL: testmsll: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: b lrintl entry: %0 = tail call i64 @llvm.lrint.i64.f128(fp128 %x) ret i64 %0 diff --git a/llvm/test/CodeGen/AArch64/vector-lrint.ll b/llvm/test/CodeGen/AArch64/vector-lrint.ll index 9c46cf69cb0b..b7fcd11ba8d1 100644 --- a/llvm/test/CodeGen/AArch64/vector-lrint.ll +++ b/llvm/test/CodeGen/AArch64/vector-lrint.ll @@ -1,6 +1,20 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+neon | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=aarch64 -mattr=+neon | FileCheck %s +; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD +; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI + +; CHECK-GI: warning: Instruction selection used fallback path for lrint_v1f16 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f16 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f16 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f16 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16i64_v16f16 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v32i64_v32f16 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f32 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f32 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f32 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v16i64_v16f32 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v2f64 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v4f64 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for lrint_v8f64 define <1 x i64> @lrint_v1f16(<1 x half> %x) { ; CHECK-LABEL: lrint_v1f16: @@ -372,13 +386,20 @@ define <32 x i64> @lrint_v32i64_v32f16(<32 x half> %x) { declare <32 x i64> @llvm.lrint.v32i64.v32f16(<32 x half>) define <1 x i64> @lrint_v1f32(<1 x float> %x) { -; CHECK-LABEL: lrint_v1f32: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: frintx s0, s0 -; CHECK-NEXT: fcvtzs x8, s0 -; CHECK-NEXT: fmov d0, x8 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: lrint_v1f32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: frintx s0, s0 +; CHECK-SD-NEXT: fcvtzs x8, s0 +; CHECK-SD-NEXT: fmov d0, x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: lrint_v1f32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: frintx s0, s0 +; CHECK-GI-NEXT: fcvtzs x8, s0 +; CHECK-GI-NEXT: fmov d0, x8 +; CHECK-GI-NEXT: ret %a = call <1 x i64> @llvm.lrint.v1i64.v1f32(<1 x float> %x) ret <1 x i64> %a } -- GitLab From 04bf1a4090c535e3a1033ab9a8ef92068166461f Mon Sep 17 00:00:00 2001 From: Kojo Acquah Date: Wed, 10 Apr 2024 10:18:47 -0700 Subject: [PATCH 425/695] Update `LowerContractionToSMMLAPattern` to ingnore matvec (#88288) Patterns in `LowerContractionToSMMLAPattern` are designed to handle vector-to-matrix multiplication but not matrix-to-vector. This leads to the following error when processing `rhs` with rank < 2: ``` iree-compile: /usr/local/google/home/kooljblack/code/iree-build/llvm-project/tools/mlir/include/mlir/IR/BuiltinTypeInterfaces.h.inc:268: int64_t mlir::detail::ShapedTypeTrait::getDimSize(unsigned int) const [ConcreteType = mlir::VectorType]: Assertion `idx < getRank() && "invalid index for shaped type"' failed. ``` Updates to explicitly check the rhs rank and fail cases that cannot process. --- .../Transforms/LowerContractionToSMMLAPattern.cpp | 3 +++ mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToSMMLAPattern.cpp b/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToSMMLAPattern.cpp index 13740225749e..3ae894692089 100644 --- a/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToSMMLAPattern.cpp +++ b/mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToSMMLAPattern.cpp @@ -54,6 +54,9 @@ public: // Note: RHS is not transposed. mlir::VectorType lhsType = op.getLhsType(); mlir::VectorType rhsType = op.getRhsType(); + // Avoid 0-D vectors and 1-D rhs: + if (!lhsType.hasRank() || !rhsType.hasRank() || rhsType.getRank() < 2) + return failure(); auto dimM = lhsType.getRank() == 1 ? 1 : lhsType.getDimSize(0); auto dimN = rhsType.getDimSize(0); auto dimK = rhsType.getDimSize(1); diff --git a/mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir b/mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir index 46c4026d13b6..c276a5b0c2a1 100644 --- a/mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir +++ b/mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir @@ -258,3 +258,14 @@ func.func @test_lower_vector_arm_neon_vecmat_unroll_leading_dim(%lhs: vector<1x8 %res = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind} %lhs_extsi, %rhs_extsi, %acc : vector<1x8xi32>, vector<8x8xi32> into vector<1x8xi32> return %res : vector<1x8xi32> } + +// ----- + +// CHECK-LABEL: func.func @test_lower_vector_arm_neon_matvec +// CHECK-NOT: arm_neon.intr.smmla +func.func @test_lower_vector_arm_neon_matvec(%lhs: vector<8x8xi8>, %rhs: vector<8xi8>, %acc : vector<8xi32>) -> vector<8xi32> { + %rhs_extsi= arith.extsi %rhs : vector<8xi8> to vector<8xi32> + %lhs_extsi = arith.extsi %lhs : vector<8x8xi8> to vector<8x8xi32> + %res = vector.contract {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,affine_map<(d0, d1) -> (d1)>, affine_map<(d0, d1) -> (d0)>], iterator_types = ["parallel", "reduction"], kind = #vector.kind} %lhs_extsi, %rhs_extsi, %acc : vector<8x8xi32>, vector<8xi32> into vector<8xi32> + return %res : vector<8xi32> +} -- GitLab From c54afe5c33ca6159841d909fb8fe20e5d4e0069b Mon Sep 17 00:00:00 2001 From: higher-performance <113926381+higher-performance@users.noreply.github.com> Date: Wed, 10 Apr 2024 13:24:19 -0400 Subject: [PATCH 426/695] Fix quadratic slowdown in AST matcher parent map generation (#87824) Avoids the need to linearly re-scan all seen parent nodes to check for duplicates, which previously caused a slowdown for ancestry checks in Clang AST matchers. Fixes: #86881 --- clang/docs/ReleaseNotes.rst | 3 +++ clang/lib/AST/ParentMapContext.cpp | 25 ++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index f5359afe1f09..c4a4893aec5c 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -646,6 +646,9 @@ Fixed Point Support in Clang AST Matchers ------------ +- Fixes a long-standing performance issue in parent map generation for + ancestry-based matchers such as ``hasParent`` and ``hasAncestor``, making + them significantly faster. - ``isInStdNamespace`` now supports Decl declared with ``extern "C++"``. - Add ``isExplicitObjectMemberFunction``. - Fixed ``forEachArgumentWithParam`` and ``forEachArgumentWithParamType`` to diff --git a/clang/lib/AST/ParentMapContext.cpp b/clang/lib/AST/ParentMapContext.cpp index 21cfd5b1de6e..9723c0cfa83b 100644 --- a/clang/lib/AST/ParentMapContext.cpp +++ b/clang/lib/AST/ParentMapContext.cpp @@ -61,7 +61,26 @@ class ParentMapContext::ParentMap { template friend struct ::MatchParents; /// Contains parents of a node. - using ParentVector = llvm::SmallVector; + class ParentVector { + public: + ParentVector() = default; + explicit ParentVector(size_t N, const DynTypedNode &Value) { + Items.reserve(N); + for (; N > 0; --N) + push_back(Value); + } + bool contains(const DynTypedNode &Value) { + return Seen.contains(Value); + } + void push_back(const DynTypedNode &Value) { + if (!Value.getMemoizationData() || Seen.insert(Value).second) + Items.push_back(Value); + } + llvm::ArrayRef view() const { return Items; } + private: + llvm::SmallVector Items; + llvm::SmallDenseSet Seen; + }; /// Maps from a node to its parents. This is used for nodes that have /// pointer identity only, which are more common and we can save space by @@ -99,7 +118,7 @@ class ParentMapContext::ParentMap { return llvm::ArrayRef(); } if (const auto *V = I->second.template dyn_cast()) { - return llvm::ArrayRef(*V); + return V->view(); } return getSingleDynTypedNodeFromParentMap(I->second); } @@ -252,7 +271,7 @@ public: const auto *S = It->second.dyn_cast(); if (!S) { if (auto *Vec = It->second.dyn_cast()) - return llvm::ArrayRef(*Vec); + return Vec->view(); return getSingleDynTypedNodeFromParentMap(It->second); } const auto *P = dyn_cast(S); -- GitLab From f27f3697108470c3e995cf3cb454641c22ec1fa9 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Apr 2024 10:28:54 -0700 Subject: [PATCH 427/695] [RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069) This code was trying to save temporary argument registers in interrupt handler functions that contain calls. With the exception that all FP registers are saved including the normally callee saved registers. If all of the callees use an FP ABI and the interrupt handler doesn't touch the normally callee saved FP registers, we don't need to save them. It doesn't appear that we need to special case functions with calls. The normal callee saved register handling will already check each of the calls and consider a register clobbered if the call doesn't explicitly say it is preserved. All of the test changes are from the removal of the FP callee saved registers. There are tests for interrupt handlers with F and D extension that use ilp32 or lp64 ABIs that are not affected by this change. They still save the FP callee saved registers as they should. gcc appears to have a bug where the D extension being enabled with the ilp32f or lp64f ABI does not save the FP callee saved regs. The callee would only save/restore the lower 32 bits and clobber the upper bits. LLVM saves the FP callee saved regs in this case and there is an unchanged test for it. The unnecessary save/restore was raised in this thread https://discourse.llvm.org/t/has-bugs-when-optimizing-save-restore-csrs-by-changing-csr-xlen-f32-interrupt/78200/1 --- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 40 - .../CodeGen/RISCV/interrupt-attr-nocall.ll | 318 ++--- llvm/test/CodeGen/RISCV/interrupt-attr.ll | 1272 +++++++---------- 3 files changed, 675 insertions(+), 955 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 39075c81b292..71672ed7b4ae 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -1001,46 +1001,6 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, // Mark BP as used if function has dedicated base pointer. if (hasBP(MF)) SavedRegs.set(RISCVABI::getBPReg()); - - // If interrupt is enabled and there are calls in the handler, - // unconditionally save all Caller-saved registers and - // all FP registers, regardless whether they are used. - MachineFrameInfo &MFI = MF.getFrameInfo(); - auto &Subtarget = MF.getSubtarget(); - - if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) { - - static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ - RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ - RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */ - RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, - RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31 /* t3-t6 */ - }; - - for (auto Reg : CSRegs) - SavedRegs.set(Reg); - - // According to psABI, if ilp32e/lp64e ABIs are used with an ISA that - // has any of the registers x16-x31 and f0-f31, then these registers are - // considered temporaries, so we should also save x16-x31 here. - if (STI.getTargetABI() == RISCVABI::ABI_ILP32E || - STI.getTargetABI() == RISCVABI::ABI_LP64E) { - for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) - SavedRegs.set(Reg); - } - - if (Subtarget.hasStdExtF()) { - - // If interrupt is enabled, this list contains all FP registers. - const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs(); - - for (unsigned i = 0; Regs[i]; ++i) - if (RISCV::FPR16RegClass.contains(Regs[i]) || - RISCV::FPR32RegClass.contains(Regs[i]) || - RISCV::FPR64RegClass.contains(Regs[i])) - SavedRegs.set(Regs[i]); - } - } } std::pair diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll index 263743d39a8e..fa6ac96b57b1 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll @@ -412,51 +412,39 @@ define void @foo_double() nounwind #0 { ; ; CHECK-RV32IF-LABEL: foo_double: ; CHECK-RV32IF: # %bb.0: -; CHECK-RV32IF-NEXT: addi sp, sp, -192 -; CHECK-RV32IF-NEXT: sw ra, 188(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t0, 184(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t1, 180(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t2, 176(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a0, 172(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a1, 168(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a2, 164(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a3, 160(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a4, 156(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a5, 152(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a6, 148(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a7, 144(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t3, 140(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t4, 136(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t5, 132(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t6, 128(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs0, 92(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs1, 88(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa1, 80(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa2, 76(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa3, 72(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa4, 68(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa6, 60(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa7, 56(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs2, 52(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs3, 48(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs4, 44(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs5, 40(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs6, 36(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs7, 32(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs8, 28(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs9, 24(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs10, 20(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs11, 16(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: addi sp, sp, -144 +; CHECK-RV32IF-NEXT: sw ra, 140(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t0, 136(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t1, 132(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t2, 128(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a0, 124(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a1, 120(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a2, 116(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a3, 112(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a4, 108(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a5, 104(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a6, 100(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a7, 96(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t3, 92(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t4, 88(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t5, 84(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t6, 80(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft1, 72(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft2, 68(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft3, 64(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft4, 60(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft5, 56(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft6, 52(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft7, 48(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa1, 40(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa2, 36(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa3, 32(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa4, 28(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa6, 20(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa7, 16(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft8, 12(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill @@ -471,55 +459,43 @@ define void @foo_double() nounwind #0 { ; CHECK-RV32IF-NEXT: lui a2, %hi(g) ; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) -; CHECK-RV32IF-NEXT: lw ra, 188(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t0, 184(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t1, 180(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t2, 176(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a0, 172(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a1, 168(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a2, 164(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a3, 160(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a4, 156(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a5, 152(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a6, 148(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a7, 144(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t3, 140(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t4, 136(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t5, 132(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t6, 128(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs0, 92(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs1, 88(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa1, 80(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa2, 76(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa3, 72(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa4, 68(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa6, 60(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa7, 56(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs2, 52(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs3, 48(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs4, 44(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs5, 40(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs6, 36(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs7, 32(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs8, 28(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs9, 24(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs10, 20(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs11, 16(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw ra, 140(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t0, 136(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t1, 132(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t2, 128(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a0, 124(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a1, 120(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a2, 116(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a3, 112(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a4, 108(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a5, 104(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a6, 100(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a7, 96(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t3, 92(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t4, 88(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t5, 84(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t6, 80(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft1, 72(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft2, 68(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft3, 64(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft4, 60(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft5, 56(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft6, 52(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft7, 48(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa1, 40(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa2, 36(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa3, 32(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa4, 28(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa6, 20(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa7, 16(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft8, 12(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft9, 8(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft10, 4(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft11, 0(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: addi sp, sp, 192 +; CHECK-RV32IF-NEXT: addi sp, sp, 144 ; CHECK-RV32IF-NEXT: mret ; ; CHECK-RV32IFD-LABEL: foo_double: @@ -604,57 +580,45 @@ define void @foo_fp_double() nounwind #1 { ; ; CHECK-RV32IF-LABEL: foo_fp_double: ; CHECK-RV32IF: # %bb.0: -; CHECK-RV32IF-NEXT: addi sp, sp, -208 -; CHECK-RV32IF-NEXT: sw ra, 204(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t0, 200(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t1, 196(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t2, 192(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw s0, 188(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a0, 184(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a1, 180(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a2, 176(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a3, 172(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a4, 168(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a5, 164(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a6, 160(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw a7, 156(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t3, 152(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t4, 148(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t5, 144(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: sw t6, 140(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft0, 136(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft1, 132(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft2, 128(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft3, 124(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft4, 120(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft5, 116(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs0, 104(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs1, 100(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa1, 92(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa2, 88(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa3, 84(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa4, 80(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa6, 72(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fa7, 68(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs2, 64(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs3, 60(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs4, 56(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs5, 52(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs6, 48(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs7, 44(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs8, 40(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs9, 36(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs10, 32(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: fsw fs11, 28(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: addi sp, sp, -160 +; CHECK-RV32IF-NEXT: sw ra, 156(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t0, 152(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t1, 148(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t2, 144(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw s0, 140(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a0, 136(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a1, 132(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a2, 128(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a3, 124(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a4, 120(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a5, 116(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a6, 112(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw a7, 108(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t3, 104(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t4, 100(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t5, 96(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: sw t6, 92(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft1, 84(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft2, 80(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft3, 76(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft4, 72(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft5, 68(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft6, 64(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw ft7, 60(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa1, 52(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa2, 48(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa3, 44(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa4, 40(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa6, 32(sp) # 4-byte Folded Spill +; CHECK-RV32IF-NEXT: fsw fa7, 28(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft8, 24(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft9, 20(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft10, 16(sp) # 4-byte Folded Spill ; CHECK-RV32IF-NEXT: fsw ft11, 12(sp) # 4-byte Folded Spill -; CHECK-RV32IF-NEXT: addi s0, sp, 208 +; CHECK-RV32IF-NEXT: addi s0, sp, 160 ; CHECK-RV32IF-NEXT: lui a1, %hi(h) ; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1) ; CHECK-RV32IF-NEXT: lw a1, %lo(h+4)(a1) @@ -665,56 +629,44 @@ define void @foo_fp_double() nounwind #1 { ; CHECK-RV32IF-NEXT: lui a2, %hi(g) ; CHECK-RV32IF-NEXT: sw a1, %lo(g+4)(a2) ; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2) -; CHECK-RV32IF-NEXT: lw ra, 204(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t0, 200(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t1, 196(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t2, 192(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw s0, 188(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a0, 184(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a1, 180(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a2, 176(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a3, 172(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a4, 168(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a5, 164(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a6, 160(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw a7, 156(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t3, 152(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t4, 148(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t5, 144(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: lw t6, 140(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft0, 136(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft1, 132(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft2, 128(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft3, 124(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft4, 120(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft5, 116(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs0, 104(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs1, 100(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa1, 92(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa2, 88(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa3, 84(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa4, 80(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa6, 72(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fa7, 68(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs2, 64(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs3, 60(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs4, 56(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs5, 52(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs6, 48(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs7, 44(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs8, 40(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs9, 36(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs10, 32(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: flw fs11, 28(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw ra, 156(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t0, 152(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t1, 148(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t2, 144(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw s0, 140(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a0, 136(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a1, 132(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a2, 128(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a3, 124(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a4, 120(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a5, 116(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a6, 112(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw a7, 108(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t3, 104(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t4, 100(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t5, 96(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: lw t6, 92(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft1, 84(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft2, 80(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft3, 76(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft4, 72(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft5, 68(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft6, 64(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw ft7, 60(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa1, 52(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa2, 48(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa3, 44(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa4, 40(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa6, 32(sp) # 4-byte Folded Reload +; CHECK-RV32IF-NEXT: flw fa7, 28(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft8, 24(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft9, 20(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft10, 16(sp) # 4-byte Folded Reload ; CHECK-RV32IF-NEXT: flw ft11, 12(sp) # 4-byte Folded Reload -; CHECK-RV32IF-NEXT: addi sp, sp, 208 +; CHECK-RV32IF-NEXT: addi sp, sp, 160 ; CHECK-RV32IF-NEXT: mret ; ; CHECK-RV32IFD-LABEL: foo_fp_double: diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr.ll b/llvm/test/CodeGen/RISCV/interrupt-attr.ll index 50c789f8f86d..739c9d8d0b0a 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr.ll @@ -115,208 +115,160 @@ define void @foo_with_call() #1 { ; ; CHECK-RV32-F-LABEL: foo_with_call: ; CHECK-RV32-F: # %bb.0: -; CHECK-RV32-F-NEXT: addi sp, sp, -192 -; CHECK-RV32-F-NEXT: sw ra, 188(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t0, 184(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t1, 180(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t2, 176(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a0, 172(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a1, 168(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a2, 164(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a3, 160(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a4, 156(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a5, 152(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a6, 148(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a7, 144(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t3, 140(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t4, 136(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t5, 132(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t6, 128(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs0, 92(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs1, 88(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa1, 80(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa2, 76(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa3, 72(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa4, 68(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa6, 60(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa7, 56(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs2, 52(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs3, 48(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs4, 44(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs5, 40(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs6, 36(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs7, 32(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs8, 28(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs9, 24(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs10, 20(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs11, 16(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: addi sp, sp, -144 +; CHECK-RV32-F-NEXT: sw ra, 140(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t0, 136(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t1, 132(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t2, 128(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a0, 124(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a1, 120(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a2, 116(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a3, 112(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a4, 108(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a5, 104(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a6, 100(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a7, 96(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t3, 92(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t4, 88(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t5, 84(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t6, 80(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft1, 72(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft2, 68(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft3, 64(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft4, 60(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft5, 56(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft6, 52(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft7, 48(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa1, 40(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa2, 36(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa3, 32(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa4, 28(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa6, 20(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa7, 16(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft8, 12(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft11, 0(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: call otherfoo -; CHECK-RV32-F-NEXT: lw ra, 188(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t0, 184(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t1, 180(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t2, 176(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a0, 172(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a1, 168(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a2, 164(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a3, 160(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a4, 156(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a5, 152(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a6, 148(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a7, 144(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t3, 140(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t4, 136(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t5, 132(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t6, 128(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs0, 92(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs1, 88(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa1, 80(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa2, 76(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa3, 72(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa4, 68(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa6, 60(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa7, 56(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs2, 52(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs3, 48(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs4, 44(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs5, 40(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs6, 36(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs7, 32(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs8, 28(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs9, 24(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs10, 20(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs11, 16(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t0, 136(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t1, 132(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t2, 128(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a0, 124(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a1, 120(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a2, 116(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a3, 112(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a4, 108(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a5, 104(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a6, 100(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a7, 96(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t3, 92(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t4, 88(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t5, 84(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t6, 80(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft1, 72(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft2, 68(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft3, 64(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft4, 60(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft5, 56(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft6, 52(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft7, 48(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa1, 40(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa2, 36(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa3, 32(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa4, 28(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa6, 20(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa7, 16(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft8, 12(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft9, 8(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft10, 4(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft11, 0(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: addi sp, sp, 192 +; CHECK-RV32-F-NEXT: addi sp, sp, 144 ; CHECK-RV32-F-NEXT: mret ; ; CHECK-RV32-FD-LABEL: foo_with_call: ; CHECK-RV32-FD: # %bb.0: -; CHECK-RV32-FD-NEXT: addi sp, sp, -320 -; CHECK-RV32-FD-NEXT: sw ra, 316(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t0, 312(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t1, 308(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t2, 304(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a0, 300(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a1, 296(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a2, 292(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a3, 288(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a4, 284(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a5, 280(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a6, 276(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a7, 272(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t3, 268(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t4, 264(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t5, 260(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t6, 256(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs0, 184(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs1, 176(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa1, 160(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa2, 152(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa3, 144(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa4, 136(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa6, 120(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa7, 112(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs2, 104(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs3, 96(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs4, 88(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs5, 80(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs6, 72(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs7, 64(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs8, 56(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs9, 48(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs10, 40(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs11, 32(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: addi sp, sp, -224 +; CHECK-RV32-FD-NEXT: sw ra, 220(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t0, 216(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t1, 212(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t2, 208(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a0, 204(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a1, 200(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a2, 196(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a3, 192(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a4, 188(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a5, 184(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a6, 180(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a7, 176(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t3, 172(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t4, 168(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t5, 164(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t6, 160(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft1, 144(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft2, 136(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft3, 128(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft4, 120(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft5, 112(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft6, 104(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft7, 96(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa1, 80(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa2, 72(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa3, 64(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa4, 56(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa6, 40(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa7, 32(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft8, 24(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: call otherfoo -; CHECK-RV32-FD-NEXT: lw ra, 316(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t0, 312(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t1, 308(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t2, 304(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a0, 300(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a1, 296(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a2, 292(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a3, 288(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a4, 284(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a5, 280(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a6, 276(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a7, 272(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t3, 268(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t4, 264(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t5, 260(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t6, 256(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs0, 184(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs1, 176(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa1, 160(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa2, 152(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa3, 144(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa4, 136(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa6, 120(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa7, 112(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs2, 104(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs3, 96(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs4, 88(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs5, 80(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs6, 72(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs7, 64(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs8, 56(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs9, 48(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs10, 40(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs11, 32(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw ra, 220(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t0, 216(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t1, 212(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t2, 208(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a0, 204(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a1, 200(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a2, 196(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a3, 192(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a4, 188(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a5, 184(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a6, 180(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a7, 176(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t3, 172(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t4, 168(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t5, 164(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t6, 160(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft1, 144(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft2, 136(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft3, 128(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft4, 120(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft5, 112(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft6, 104(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft7, 96(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa1, 80(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa2, 72(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa3, 64(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa4, 56(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa6, 40(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa7, 32(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft8, 24(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft9, 16(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft10, 8(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft11, 0(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: addi sp, sp, 320 +; CHECK-RV32-FD-NEXT: addi sp, sp, 224 ; CHECK-RV32-FD-NEXT: mret ; ; CHECK-RV32-F-ILP3-LABEL: foo_with_call: @@ -846,208 +798,160 @@ define void @foo_with_call() #1 { ; ; CHECK-RV64-F-LABEL: foo_with_call: ; CHECK-RV64-F: # %bb.0: -; CHECK-RV64-F-NEXT: addi sp, sp, -256 -; CHECK-RV64-F-NEXT: sd ra, 248(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t0, 240(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t1, 232(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t2, 224(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a0, 216(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a1, 208(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a2, 200(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a3, 192(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a4, 184(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a5, 176(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a6, 168(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a7, 160(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t3, 152(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t4, 144(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t5, 136(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t6, 128(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft1, 120(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft2, 116(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft3, 112(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft4, 108(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft5, 104(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft6, 100(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft7, 96(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs0, 92(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs1, 88(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa0, 84(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa1, 80(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa2, 76(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa3, 72(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa4, 68(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa5, 64(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa6, 60(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa7, 56(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs2, 52(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs3, 48(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs4, 44(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs5, 40(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs6, 36(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs7, 32(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs8, 28(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs9, 24(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs10, 20(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs11, 16(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: addi sp, sp, -208 +; CHECK-RV64-F-NEXT: sd ra, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t0, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t1, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t2, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a0, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a1, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a2, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a3, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a4, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a5, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a6, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a7, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t3, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t4, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t5, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t6, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft1, 72(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft2, 68(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft3, 64(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft4, 60(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft5, 56(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft6, 52(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft7, 48(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa0, 44(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa1, 40(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa2, 36(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa3, 32(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa4, 28(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa5, 24(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa6, 20(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa7, 16(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft8, 12(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft9, 8(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft10, 4(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft11, 0(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: call otherfoo -; CHECK-RV64-F-NEXT: ld ra, 248(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t0, 240(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t1, 232(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t2, 224(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a0, 216(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a1, 208(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a2, 200(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a3, 192(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a4, 184(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a5, 176(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a6, 168(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a7, 160(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t3, 152(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t4, 144(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t5, 136(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t6, 128(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft1, 120(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft2, 116(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft3, 112(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft4, 108(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft5, 104(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft6, 100(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft7, 96(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs0, 92(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs1, 88(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa0, 84(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa1, 80(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa2, 76(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa3, 72(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa4, 68(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa5, 64(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa6, 60(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa7, 56(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs2, 52(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs3, 48(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs4, 44(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs5, 40(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs6, 36(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs7, 32(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs8, 28(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs9, 24(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs10, 20(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs11, 16(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: ld ra, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t0, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t1, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t2, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a0, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a1, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a2, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a3, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a4, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a5, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a6, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a7, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t3, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t4, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t5, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t6, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft1, 72(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft2, 68(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft3, 64(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft4, 60(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft5, 56(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft6, 52(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft7, 48(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa0, 44(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa1, 40(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa2, 36(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa3, 32(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa4, 28(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa5, 24(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa6, 20(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa7, 16(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft8, 12(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft9, 8(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft10, 4(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft11, 0(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: addi sp, sp, 256 +; CHECK-RV64-F-NEXT: addi sp, sp, 208 ; CHECK-RV64-F-NEXT: mret ; ; CHECK-RV64-FD-LABEL: foo_with_call: ; CHECK-RV64-FD: # %bb.0: -; CHECK-RV64-FD-NEXT: addi sp, sp, -384 -; CHECK-RV64-FD-NEXT: sd ra, 376(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t0, 368(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t1, 360(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t2, 352(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a0, 344(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a1, 336(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a2, 328(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a3, 320(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a4, 312(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a5, 304(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a6, 296(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a7, 288(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t3, 280(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t4, 272(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t5, 264(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t6, 256(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft1, 240(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft2, 232(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft3, 224(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft4, 216(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft5, 208(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft6, 200(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft7, 192(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs0, 184(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs1, 176(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa0, 168(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa1, 160(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa2, 152(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa3, 144(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa4, 136(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa5, 128(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa6, 120(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa7, 112(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs2, 104(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs3, 96(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs4, 88(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs5, 80(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs6, 72(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs7, 64(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs8, 56(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs9, 48(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs10, 40(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs11, 32(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: addi sp, sp, -288 +; CHECK-RV64-FD-NEXT: sd ra, 280(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t0, 272(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t1, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t2, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a0, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a1, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a2, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a3, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a4, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a5, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a6, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a7, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t3, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t4, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t5, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t6, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft1, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft2, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft3, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft4, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft5, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft6, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft7, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa0, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa1, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa2, 72(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa3, 64(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa4, 56(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa5, 48(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa6, 40(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa7, 32(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft8, 24(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft9, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft10, 8(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft11, 0(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: call otherfoo -; CHECK-RV64-FD-NEXT: ld ra, 376(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t0, 368(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t1, 360(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t2, 352(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a0, 344(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a1, 336(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a2, 328(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a3, 320(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a4, 312(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a5, 304(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a6, 296(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a7, 288(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t3, 280(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t4, 272(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t5, 264(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t6, 256(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft1, 240(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft2, 232(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft3, 224(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft4, 216(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft5, 208(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft6, 200(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft7, 192(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs0, 184(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs1, 176(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa0, 168(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa1, 160(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa2, 152(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa3, 144(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa4, 136(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa5, 128(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa6, 120(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa7, 112(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs2, 104(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs3, 96(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs4, 88(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs5, 80(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs6, 72(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs7, 64(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs8, 56(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs9, 48(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs10, 40(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs11, 32(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld ra, 280(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t0, 272(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t1, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t2, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a0, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a1, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a2, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a3, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a4, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a5, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a6, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a7, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t3, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t4, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t5, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t6, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft1, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft2, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft3, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft4, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft5, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft6, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft7, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa0, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa1, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa2, 72(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa3, 64(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa4, 56(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa5, 48(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa6, 40(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa7, 32(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft8, 24(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft9, 16(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft10, 8(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft11, 0(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: addi sp, sp, 384 +; CHECK-RV64-FD-NEXT: addi sp, sp, 288 ; CHECK-RV64-FD-NEXT: mret ; ; CHECK-RV64-F-LP64-LABEL: foo_with_call: @@ -1711,214 +1615,166 @@ define void @foo_fp_with_call() #2 { ; ; CHECK-RV32-F-LABEL: foo_fp_with_call: ; CHECK-RV32-F: # %bb.0: -; CHECK-RV32-F-NEXT: addi sp, sp, -208 -; CHECK-RV32-F-NEXT: sw ra, 204(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t0, 200(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t1, 196(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t2, 192(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw s0, 188(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a0, 184(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a1, 180(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a2, 176(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a3, 172(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a4, 168(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a5, 164(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a6, 160(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw a7, 156(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t3, 152(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t4, 148(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t5, 144(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: sw t6, 140(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft0, 136(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft1, 132(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft2, 128(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft3, 124(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft4, 120(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft5, 116(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft6, 112(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw ft7, 108(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs0, 104(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs1, 100(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa0, 96(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa1, 92(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa2, 88(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa3, 84(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa4, 80(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa5, 76(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa6, 72(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fa7, 68(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs2, 64(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs3, 60(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs4, 56(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs5, 52(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs6, 48(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs7, 44(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs8, 40(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs9, 36(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs10, 32(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: fsw fs11, 28(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: addi sp, sp, -160 +; CHECK-RV32-F-NEXT: sw ra, 156(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t0, 152(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t1, 148(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t2, 144(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw s0, 140(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a0, 136(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a1, 132(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a2, 128(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a3, 124(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a4, 120(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a5, 116(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a6, 112(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw a7, 108(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t3, 104(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t4, 100(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t5, 96(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: sw t6, 92(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft0, 88(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft1, 84(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft2, 80(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft3, 76(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft4, 72(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft5, 68(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft6, 64(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw ft7, 60(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa0, 56(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa1, 52(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa2, 48(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa3, 44(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa4, 40(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa5, 36(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa6, 32(sp) # 4-byte Folded Spill +; CHECK-RV32-F-NEXT: fsw fa7, 28(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft8, 24(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft9, 20(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft10, 16(sp) # 4-byte Folded Spill ; CHECK-RV32-F-NEXT: fsw ft11, 12(sp) # 4-byte Folded Spill -; CHECK-RV32-F-NEXT: addi s0, sp, 208 +; CHECK-RV32-F-NEXT: addi s0, sp, 160 ; CHECK-RV32-F-NEXT: call otherfoo -; CHECK-RV32-F-NEXT: lw ra, 204(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t0, 200(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t1, 196(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t2, 192(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw s0, 188(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a0, 184(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a1, 180(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a2, 176(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a3, 172(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a4, 168(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a5, 164(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a6, 160(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw a7, 156(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t3, 152(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t4, 148(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t5, 144(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: lw t6, 140(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft0, 136(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft1, 132(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft2, 128(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft3, 124(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft4, 120(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft5, 116(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft6, 112(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw ft7, 108(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs0, 104(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs1, 100(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa0, 96(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa1, 92(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa2, 88(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa3, 84(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa4, 80(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa5, 76(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa6, 72(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fa7, 68(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs2, 64(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs3, 60(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs4, 56(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs5, 52(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs6, 48(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs7, 44(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs8, 40(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs9, 36(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs10, 32(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: flw fs11, 28(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw ra, 156(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t0, 152(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t1, 148(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t2, 144(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw s0, 140(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a0, 136(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a1, 132(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a2, 128(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a3, 124(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a4, 120(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a5, 116(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a6, 112(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw a7, 108(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t3, 104(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t4, 100(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t5, 96(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: lw t6, 92(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft0, 88(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft1, 84(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft2, 80(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft3, 76(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft4, 72(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft5, 68(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft6, 64(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw ft7, 60(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa0, 56(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa1, 52(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa2, 48(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa3, 44(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa4, 40(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa5, 36(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa6, 32(sp) # 4-byte Folded Reload +; CHECK-RV32-F-NEXT: flw fa7, 28(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft8, 24(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft9, 20(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft10, 16(sp) # 4-byte Folded Reload ; CHECK-RV32-F-NEXT: flw ft11, 12(sp) # 4-byte Folded Reload -; CHECK-RV32-F-NEXT: addi sp, sp, 208 +; CHECK-RV32-F-NEXT: addi sp, sp, 160 ; CHECK-RV32-F-NEXT: mret ; ; CHECK-RV32-FD-LABEL: foo_fp_with_call: ; CHECK-RV32-FD: # %bb.0: -; CHECK-RV32-FD-NEXT: addi sp, sp, -336 -; CHECK-RV32-FD-NEXT: sw ra, 332(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t0, 328(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t1, 324(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t2, 320(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw s0, 316(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a0, 312(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a1, 308(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a2, 304(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a3, 300(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a4, 296(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a5, 292(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a6, 288(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw a7, 284(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t3, 280(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t4, 276(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t5, 272(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: sw t6, 268(sp) # 4-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs0, 192(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs1, 184(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa1, 168(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa2, 160(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa3, 152(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa4, 144(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa6, 128(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fa7, 120(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs2, 112(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs3, 104(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs4, 96(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs5, 88(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs6, 80(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs7, 72(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs8, 64(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs9, 56(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs10, 48(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: fsd fs11, 40(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: addi sp, sp, -240 +; CHECK-RV32-FD-NEXT: sw ra, 236(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t0, 232(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t1, 228(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t2, 224(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw s0, 220(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a0, 216(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a1, 212(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a2, 208(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a3, 204(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a4, 200(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a5, 196(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a6, 192(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw a7, 188(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t3, 184(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t4, 180(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t5, 176(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: sw t6, 172(sp) # 4-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft1, 152(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft2, 144(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft3, 136(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft4, 128(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft5, 120(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft6, 112(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd ft7, 104(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa1, 88(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa2, 80(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa3, 72(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa4, 64(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa6, 48(sp) # 8-byte Folded Spill +; CHECK-RV32-FD-NEXT: fsd fa7, 40(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft8, 32(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft9, 24(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill ; CHECK-RV32-FD-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill -; CHECK-RV32-FD-NEXT: addi s0, sp, 336 +; CHECK-RV32-FD-NEXT: addi s0, sp, 240 ; CHECK-RV32-FD-NEXT: call otherfoo -; CHECK-RV32-FD-NEXT: lw ra, 332(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t0, 328(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t1, 324(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t2, 320(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw s0, 316(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a0, 312(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a1, 308(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a2, 304(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a3, 300(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a4, 296(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a5, 292(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a6, 288(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw a7, 284(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t3, 280(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t4, 276(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t5, 272(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: lw t6, 268(sp) # 4-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs0, 192(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs1, 184(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa1, 168(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa2, 160(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa3, 152(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa4, 144(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa6, 128(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fa7, 120(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs2, 112(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs3, 104(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs4, 96(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs5, 88(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs6, 80(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs7, 72(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs8, 64(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs9, 56(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs10, 48(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: fld fs11, 40(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw ra, 236(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t0, 232(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t1, 228(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t2, 224(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw s0, 220(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a0, 216(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a1, 212(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a2, 208(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a3, 204(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a4, 200(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a5, 196(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a6, 192(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw a7, 188(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t3, 184(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t4, 180(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t5, 176(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: lw t6, 172(sp) # 4-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft1, 152(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft2, 144(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft3, 136(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft4, 128(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft5, 120(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft6, 112(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld ft7, 104(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa1, 88(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa2, 80(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa3, 72(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa4, 64(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa6, 48(sp) # 8-byte Folded Reload +; CHECK-RV32-FD-NEXT: fld fa7, 40(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft8, 32(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft9, 24(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft10, 16(sp) # 8-byte Folded Reload ; CHECK-RV32-FD-NEXT: fld ft11, 8(sp) # 8-byte Folded Reload -; CHECK-RV32-FD-NEXT: addi sp, sp, 336 +; CHECK-RV32-FD-NEXT: addi sp, sp, 240 ; CHECK-RV32-FD-NEXT: mret ; ; CHECK-RV32-F-ILP3-LABEL: foo_fp_with_call: @@ -2469,214 +2325,166 @@ define void @foo_fp_with_call() #2 { ; ; CHECK-RV64-F-LABEL: foo_fp_with_call: ; CHECK-RV64-F: # %bb.0: -; CHECK-RV64-F-NEXT: addi sp, sp, -272 -; CHECK-RV64-F-NEXT: sd ra, 264(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t0, 256(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t1, 248(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t2, 240(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd s0, 232(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a0, 224(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a1, 216(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a2, 208(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a3, 200(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a4, 192(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a5, 184(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a6, 176(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd a7, 168(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t3, 160(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t4, 152(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t5, 144(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: sd t6, 136(sp) # 8-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft1, 128(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft2, 124(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft3, 120(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft4, 116(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft5, 112(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft6, 108(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw ft7, 104(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs0, 100(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs1, 96(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa0, 92(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa1, 88(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa2, 84(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa3, 80(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa4, 76(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa5, 72(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa6, 68(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fa7, 64(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs2, 60(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs3, 56(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs4, 52(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs5, 48(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs6, 44(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs7, 40(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs8, 36(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs9, 32(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs10, 28(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: fsw fs11, 24(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: addi sp, sp, -224 +; CHECK-RV64-F-NEXT: sd ra, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t0, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t1, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t2, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd s0, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a0, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a1, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a2, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a3, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a4, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a5, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a6, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd a7, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t3, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t4, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t5, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: sd t6, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft1, 80(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft2, 76(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft3, 72(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft4, 68(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft5, 64(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft6, 60(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw ft7, 56(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa0, 52(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa1, 48(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa2, 44(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa3, 40(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa4, 36(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa5, 32(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa6, 28(sp) # 4-byte Folded Spill +; CHECK-RV64-F-NEXT: fsw fa7, 24(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft8, 20(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft9, 16(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft10, 12(sp) # 4-byte Folded Spill ; CHECK-RV64-F-NEXT: fsw ft11, 8(sp) # 4-byte Folded Spill -; CHECK-RV64-F-NEXT: addi s0, sp, 272 +; CHECK-RV64-F-NEXT: addi s0, sp, 224 ; CHECK-RV64-F-NEXT: call otherfoo -; CHECK-RV64-F-NEXT: ld ra, 264(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t0, 256(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t1, 248(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t2, 240(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld s0, 232(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a0, 224(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a1, 216(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a2, 208(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a3, 200(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a4, 192(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a5, 184(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a6, 176(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld a7, 168(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t3, 160(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t4, 152(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t5, 144(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: ld t6, 136(sp) # 8-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft1, 128(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft2, 124(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft3, 120(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft4, 116(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft5, 112(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft6, 108(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw ft7, 104(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs0, 100(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs1, 96(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa0, 92(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa1, 88(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa2, 84(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa3, 80(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa4, 76(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa5, 72(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa6, 68(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fa7, 64(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs2, 60(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs3, 56(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs4, 52(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs5, 48(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs6, 44(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs7, 40(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs8, 36(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs9, 32(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs10, 28(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: flw fs11, 24(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: ld ra, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t0, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t1, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t2, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld s0, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a0, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a1, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a2, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a3, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a4, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a5, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a6, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld a7, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t3, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t4, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t5, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: ld t6, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft1, 80(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft2, 76(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft3, 72(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft4, 68(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft5, 64(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft6, 60(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw ft7, 56(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa0, 52(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa1, 48(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa2, 44(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa3, 40(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa4, 36(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa5, 32(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa6, 28(sp) # 4-byte Folded Reload +; CHECK-RV64-F-NEXT: flw fa7, 24(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft8, 20(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft9, 16(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft10, 12(sp) # 4-byte Folded Reload ; CHECK-RV64-F-NEXT: flw ft11, 8(sp) # 4-byte Folded Reload -; CHECK-RV64-F-NEXT: addi sp, sp, 272 +; CHECK-RV64-F-NEXT: addi sp, sp, 224 ; CHECK-RV64-F-NEXT: mret ; ; CHECK-RV64-FD-LABEL: foo_fp_with_call: ; CHECK-RV64-FD: # %bb.0: -; CHECK-RV64-FD-NEXT: addi sp, sp, -400 -; CHECK-RV64-FD-NEXT: sd ra, 392(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t0, 384(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t1, 376(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t2, 368(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd s0, 360(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a0, 352(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a1, 344(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a2, 336(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a3, 328(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a4, 320(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a5, 312(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a6, 304(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd a7, 296(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t3, 288(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t4, 280(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t5, 272(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: sd t6, 264(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft1, 248(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft2, 240(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft3, 232(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft4, 224(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft5, 216(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft6, 208(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd ft7, 200(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs0, 192(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs1, 184(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa0, 176(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa1, 168(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa2, 160(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa3, 152(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa4, 144(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa5, 136(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa6, 128(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fa7, 120(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs2, 112(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs3, 104(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs4, 96(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs5, 88(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs6, 80(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs7, 72(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs8, 64(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs9, 56(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs10, 48(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: fsd fs11, 40(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: addi sp, sp, -304 +; CHECK-RV64-FD-NEXT: sd ra, 296(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t0, 288(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t1, 280(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t2, 272(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd s0, 264(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a0, 256(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a1, 248(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a2, 240(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a3, 232(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a4, 224(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a5, 216(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a6, 208(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd a7, 200(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t3, 192(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t4, 184(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t5, 176(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: sd t6, 168(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft1, 152(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft2, 144(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft3, 136(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft4, 128(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft5, 120(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft6, 112(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd ft7, 104(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa0, 96(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa1, 88(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa2, 80(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa3, 72(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa4, 64(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa5, 56(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa6, 48(sp) # 8-byte Folded Spill +; CHECK-RV64-FD-NEXT: fsd fa7, 40(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft8, 32(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft9, 24(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft10, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-FD-NEXT: fsd ft11, 8(sp) # 8-byte Folded Spill -; CHECK-RV64-FD-NEXT: addi s0, sp, 400 +; CHECK-RV64-FD-NEXT: addi s0, sp, 304 ; CHECK-RV64-FD-NEXT: call otherfoo -; CHECK-RV64-FD-NEXT: ld ra, 392(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t0, 384(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t1, 376(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t2, 368(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld s0, 360(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a0, 352(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a1, 344(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a2, 336(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a3, 328(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a4, 320(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a5, 312(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a6, 304(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld a7, 296(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t3, 288(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t4, 280(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t5, 272(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: ld t6, 264(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft1, 248(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft2, 240(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft3, 232(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft4, 224(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft5, 216(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft6, 208(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld ft7, 200(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs0, 192(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs1, 184(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa0, 176(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa1, 168(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa2, 160(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa3, 152(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa4, 144(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa5, 136(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa6, 128(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fa7, 120(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs2, 112(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs3, 104(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs4, 96(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs5, 88(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs6, 80(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs7, 72(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs8, 64(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs9, 56(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs10, 48(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: fld fs11, 40(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld ra, 296(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t0, 288(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t1, 280(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t2, 272(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld s0, 264(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a0, 256(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a1, 248(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a2, 240(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a3, 232(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a4, 224(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a5, 216(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a6, 208(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld a7, 200(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t3, 192(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t4, 184(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t5, 176(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: ld t6, 168(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft1, 152(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft2, 144(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft3, 136(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft4, 128(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft5, 120(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft6, 112(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld ft7, 104(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa0, 96(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa1, 88(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa2, 80(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa3, 72(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa4, 64(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa5, 56(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa6, 48(sp) # 8-byte Folded Reload +; CHECK-RV64-FD-NEXT: fld fa7, 40(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft8, 32(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft9, 24(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft10, 16(sp) # 8-byte Folded Reload ; CHECK-RV64-FD-NEXT: fld ft11, 8(sp) # 8-byte Folded Reload -; CHECK-RV64-FD-NEXT: addi sp, sp, 400 +; CHECK-RV64-FD-NEXT: addi sp, sp, 304 ; CHECK-RV64-FD-NEXT: mret ; ; CHECK-RV64-F-LP64-LABEL: foo_fp_with_call: -- GitLab From 86842e1f724fba5abae50ce438553895e69b8141 Mon Sep 17 00:00:00 2001 From: Jun Wang Date: Wed, 10 Apr 2024 10:47:04 -0700 Subject: [PATCH 428/695] [AMDGPU] New clang option for emitting a waitcnt instruction after each memory instruction (#79236) This patch introduces a new command-line option for clang, namely, amdgpu-precise-mem-op (or precise-memory in the backend). When this option is specified, a waitcnt instruction is generated after each memory load/store instruction. The counter values are always 0, but which counters are involved depends on the memory instruction. --------- Co-authored-by: Jun Wang --- clang/include/clang/Driver/Options.td | 3 + clang/lib/Driver/ToolChains/AMDGPU.cpp | 4 + clang/test/Driver/amdgpu-features.c | 6 + llvm/lib/Target/AMDGPU/AMDGPU.td | 4 + llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 + llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 8 + .../insert_waitcnt_for_precise_memory.ll | 1658 +++++++++++++++++ 7 files changed, 1686 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 0a74e6c75f95..7ac36222644a 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4912,6 +4912,9 @@ defm tgsplit : SimpleMFlag<"tgsplit", "Enable", "Disable", defm wavefrontsize64 : SimpleMFlag<"wavefrontsize64", "Specify wavefront size 64", "Specify wavefront size 32", " mode (AMDGPU only)">; +defm amdgpu_precise_memory_op + : SimpleMFlag<"amdgpu-precise-memory-op", "Enable", "Disable", + " precise memory mode (AMDGPU only)">; defm unsafe_fp_atomics : BoolMOption<"unsafe-fp-atomics", TargetOpts<"AllowAMDGPUUnsafeFPAtomics">, DefaultFalse, diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index e122379e860e..4e6362a0f406 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -670,6 +670,10 @@ void amdgpu::getAMDGPUTargetFeatures(const Driver &D, options::OPT_mno_wavefrontsize64, false)) Features.push_back("+wavefrontsize64"); + if (Args.hasFlag(options::OPT_mamdgpu_precise_memory_op, + options::OPT_mno_amdgpu_precise_memory_op, false)) + Features.push_back("+precise-memory"); + handleTargetFeaturesGroup(D, Triple, Args, Features, options::OPT_m_amdgpu_Features_Group); } diff --git a/clang/test/Driver/amdgpu-features.c b/clang/test/Driver/amdgpu-features.c index a516bc6b7ff2..864744db203e 100644 --- a/clang/test/Driver/amdgpu-features.c +++ b/clang/test/Driver/amdgpu-features.c @@ -32,3 +32,9 @@ // RUN: %clang -### -target amdgcn -mcpu=gfx1010 -mno-cumode %s 2>&1 | FileCheck --check-prefix=NO-CUMODE %s // NO-CUMODE: "-target-feature" "-cumode" + +// RUN: %clang -### -target amdgcn -mcpu=gfx1010 -mamdgpu-precise-memory-op %s 2>&1 | FileCheck --check-prefix=PREC-MEM %s +// PREC-MEM: "-target-feature" "+precise-memory" + +// RUN: %clang -### -target amdgcn -mcpu=gfx1010 -mno-amdgpu-precise-memory-op %s 2>&1 | FileCheck --check-prefix=NO-PREC-MEM %s +// NO-PREC-MEM-NOT: {{".*precise-memory"}} diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 37dcfef3b2a3..9b0955015999 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -168,6 +168,10 @@ def FeatureCuMode : SubtargetFeature<"cumode", "Enable CU wavefront execution mode" >; +def FeaturePreciseMemory + : SubtargetFeature<"precise-memory", "EnablePreciseMemory", + "true", "Enable precise memory mode">; + def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug", "SGPRInitBug", "true", diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index e24a18a2842f..04ff53a6647b 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -87,6 +87,7 @@ protected: bool EnableTgSplit = false; bool EnableCuMode = false; bool TrapHandler = false; + bool EnablePreciseMemory = false; // Used as options. bool EnableLoadStoreOpt = false; @@ -599,6 +600,8 @@ public: return EnableCuMode; } + bool isPreciseMemoryEnabled() const { return EnablePreciseMemory; } + bool hasFlatAddressSpace() const { return FlatAddressSpace; } diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index bb499c5c8c57..556ec3e231ff 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -2305,6 +2305,14 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, } #endif + if (ST->isPreciseMemoryEnabled() && Inst.mayLoadOrStore()) { + AMDGPU::Waitcnt Wait = WCG->getAllZeroWaitcnt( + Inst.mayStore() && !SIInstrInfo::isAtomicRet(Inst)); + ScoreBrackets.simplifyWaitcnt(Wait); + Modified |= generateWaitcnt(Wait, std::next(Inst.getIterator()), Block, + ScoreBrackets, /*OldWaitcntInstr=*/nullptr); + } + LLVM_DEBUG({ Inst.print(dbgs()); ScoreBrackets.dump(); diff --git a/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll new file mode 100644 index 000000000000..df03e8937037 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/insert_waitcnt_for_precise_memory.ll @@ -0,0 +1,1658 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+precise-memory < %s | FileCheck %s -check-prefixes=GFX9 +; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -mattr=+precise-memory < %s | FileCheck %s -check-prefixes=GFX90A +; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+precise-memory < %s | FileCheck %s -check-prefixes=GFX10 +; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-flat-scratch,+precise-memory < %s | FileCheck --check-prefixes=GFX9-FLATSCR %s +; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+precise-memory < %s | FileCheck %s -check-prefixes=GFX11 +; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+precise-memory < %s | FileCheck %s -check-prefixes=GFX12 + +; from atomicrmw-expand.ll +; covers flat_load, flat_atomic (atomic with return) +; +define void @syncscope_workgroup_nortn(ptr %addr, float %val) { +; GFX9-LABEL: syncscope_workgroup_nortn: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: flat_load_dword v4, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], 0 +; GFX9-NEXT: .LBB0_1: ; %atomicrmw.start +; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX9-NEXT: v_add_f32_e32 v3, v4, v2 +; GFX9-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4 +; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_cbranch_execnz .LBB0_1 +; GFX9-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-LABEL: syncscope_workgroup_nortn: +; GFX90A: ; %bb.0: +; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-NEXT: flat_load_dword v5, v[0:1] +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX90A-NEXT: s_mov_b64 s[4:5], 0 +; GFX90A-NEXT: .LBB0_1: ; %atomicrmw.start +; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX90A-NEXT: v_add_f32_e32 v4, v5, v2 +; GFX90A-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] glc +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5 +; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX90A-NEXT: v_mov_b32_e32 v5, v3 +; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX90A-NEXT: s_cbranch_execnz .LBB0_1 +; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX90A-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: syncscope_workgroup_nortn: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: flat_load_dword v4, v[0:1] +; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: .LBB0_1: ; %atomicrmw.start +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_add_f32_e32 v3, v4, v2 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc +; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-NEXT: buffer_gl0_inv +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4 +; GFX10-NEXT: v_mov_b32_e32 v4, v3 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB0_1 +; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-FLATSCR-LABEL: syncscope_workgroup_nortn: +; GFX9-FLATSCR: ; %bb.0: +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: flat_load_dword v4, v[0:1] +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: s_mov_b64 s[0:1], 0 +; GFX9-FLATSCR-NEXT: .LBB0_1: ; %atomicrmw.start +; GFX9-FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX9-FLATSCR-NEXT: v_add_f32_e32 v3, v4, v2 +; GFX9-FLATSCR-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4 +; GFX9-FLATSCR-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v4, v3 +; GFX9-FLATSCR-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX9-FLATSCR-NEXT: s_cbranch_execnz .LBB0_1 +; GFX9-FLATSCR-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX9-FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-FLATSCR-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: syncscope_workgroup_nortn: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: flat_load_b32 v4, v[0:1] +; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: .LBB0_1: ; %atomicrmw.start +; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_add_f32_e32 v3, v4, v2 +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] glc +; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-NEXT: buffer_gl0_inv +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4 +; GFX11-NEXT: v_mov_b32_e32 v4, v3 +; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_cbranch_execnz .LBB0_1 +; GFX11-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: syncscope_workgroup_nortn: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: flat_load_b32 v4, v[0:1] +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_mov_b32 s0, 0 +; GFX12-NEXT: .LBB0_1: ; %atomicrmw.start +; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_add_f32_e32 v3, v4, v2 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: flat_atomic_cmpswap_b32 v3, v[0:1], v[3:4] th:TH_ATOMIC_RETURN +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: global_inv scope:SCOPE_SE +; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v3, v4 +; GFX12-NEXT: v_mov_b32_e32 v4, v3 +; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 +; GFX12-NEXT: s_cbranch_execnz .LBB0_1 +; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst + ret void +} + +; from atomicrmw-nand.ll +; covers global_atomic (atomic with return), global_load +; +define i32 @atomic_nand_i32_global(ptr addrspace(1) %ptr) nounwind { +; GFX9-LABEL: atomic_nand_i32_global: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v2, v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_mov_b64 s[4:5], 0 +; GFX9-NEXT: .LBB1_1: ; %atomicrmw.start +; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX9-NEXT: v_mov_b32_e32 v3, v2 +; GFX9-NEXT: v_not_b32_e32 v2, v3 +; GFX9-NEXT: v_or_b32_e32 v2, -5, v2 +; GFX9-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX9-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_cbranch_execnz .LBB1_1 +; GFX9-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-LABEL: atomic_nand_i32_global: +; GFX90A: ; %bb.0: +; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-NEXT: global_load_dword v2, v[0:1], off +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_mov_b64 s[4:5], 0 +; GFX90A-NEXT: .LBB1_1: ; %atomicrmw.start +; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX90A-NEXT: v_mov_b32_e32 v3, v2 +; GFX90A-NEXT: v_not_b32_e32 v2, v3 +; GFX90A-NEXT: v_or_b32_e32 v2, -5, v2 +; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: buffer_invl2 +; GFX90A-NEXT: buffer_wbinvl1_vol +; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX90A-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX90A-NEXT: s_andn2_b64 exec, exec, s[4:5] +; GFX90A-NEXT: s_cbranch_execnz .LBB1_1 +; GFX90A-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX90A-NEXT: v_mov_b32_e32 v0, v2 +; GFX90A-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: atomic_nand_i32_global: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dword v2, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: s_mov_b32 s4, 0 +; GFX10-NEXT: .LBB1_1: ; %atomicrmw.start +; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX10-NEXT: v_mov_b32_e32 v3, v2 +; GFX10-NEXT: v_not_b32_e32 v2, v3 +; GFX10-NEXT: v_or_b32_e32 v2, -5, v2 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: buffer_gl1_inv +; GFX10-NEXT: buffer_gl0_inv +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX10-NEXT: s_or_b32 s4, vcc_lo, s4 +; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: s_cbranch_execnz .LBB1_1 +; GFX10-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX10-NEXT: v_mov_b32_e32 v0, v2 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-FLATSCR-LABEL: atomic_nand_i32_global: +; GFX9-FLATSCR: ; %bb.0: +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: global_load_dword v2, v[0:1], off +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_mov_b64 s[0:1], 0 +; GFX9-FLATSCR-NEXT: .LBB1_1: ; %atomicrmw.start +; GFX9-FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v3, v2 +; GFX9-FLATSCR-NEXT: v_not_b32_e32 v2, v3 +; GFX9-FLATSCR-NEXT: v_or_b32_e32 v2, -5, v2 +; GFX9-FLATSCR-NEXT: global_atomic_cmpswap v2, v[0:1], v[2:3], off glc +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: buffer_wbinvl1_vol +; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3 +; GFX9-FLATSCR-NEXT: s_or_b64 s[0:1], vcc, s[0:1] +; GFX9-FLATSCR-NEXT: s_andn2_b64 exec, exec, s[0:1] +; GFX9-FLATSCR-NEXT: s_cbranch_execnz .LBB1_1 +; GFX9-FLATSCR-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX9-FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, v2 +; GFX9-FLATSCR-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: atomic_nand_i32_global: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: global_load_b32 v2, v[0:1], off +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_mov_b32 s0, 0 +; GFX11-NEXT: .LBB1_1: ; %atomicrmw.start +; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX11-NEXT: v_mov_b32_e32 v3, v2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_not_b32_e32 v2, v3 +; GFX11-NEXT: v_or_b32_e32 v2, -5, v2 +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: buffer_gl1_inv +; GFX11-NEXT: buffer_gl0_inv +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: s_cbranch_execnz .LBB1_1 +; GFX11-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX11-NEXT: v_mov_b32_e32 v0, v2 +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: atomic_nand_i32_global: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: global_load_b32 v2, v[0:1], off +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_mov_b32 s0, 0 +; GFX12-NEXT: .LBB1_1: ; %atomicrmw.start +; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 +; GFX12-NEXT: v_mov_b32_e32 v3, v2 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX12-NEXT: v_not_b32_e32 v2, v3 +; GFX12-NEXT: v_or_b32_e32 v2, -5, v2 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: global_atomic_cmpswap_b32 v2, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: global_inv scope:SCOPE_SYS +; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v3 +; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0 +; GFX12-NEXT: s_cbranch_execnz .LBB1_1 +; GFX12-NEXT: ; %bb.2: ; %atomicrmw.end +; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s0 +; GFX12-NEXT: v_mov_b32_e32 v0, v2 +; GFX12-NEXT: s_setpc_b64 s[30:31] + %result = atomicrmw nand ptr addrspace(1) %ptr, i32 4 seq_cst + ret i32 %result +} + +; from call-argument-types.ll +; covers scratch_load, scratch_store, buffer_load, buffer_store +; +declare hidden void @byval_align16_f64_arg(<32 x i32>, ptr addrspace(5) byval(double) align 16) +define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) { +; GFX9-LABEL: tail_call_byval_align16: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:28 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_getpc_b64 s[16:17] +; GFX9-NEXT: s_add_u32 s16, s16, byval_align16_f64_arg@rel32@lo+4 +; GFX9-NEXT: s_addc_u32 s17, s17, byval_align16_f64_arg@rel32@hi+12 +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:20 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:24 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[16:17] +; +; GFX90A-LABEL: tail_call_byval_align16: +; GFX90A: ; %bb.0: ; %entry +; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:28 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:24 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: buffer_load_dword v34, off, s[0:3], s32 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_getpc_b64 s[16:17] +; GFX90A-NEXT: s_add_u32 s16, s16, byval_align16_f64_arg@rel32@lo+4 +; GFX90A-NEXT: s_addc_u32 s17, s17, byval_align16_f64_arg@rel32@hi+12 +; GFX90A-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:20 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:16 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: buffer_store_dword v34, off, s[0:3], s32 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_setpc_b64 s[16:17] +; +; GFX10-LABEL: tail_call_byval_align16: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:28 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:24 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: s_getpc_b64 s[16:17] +; GFX10-NEXT: s_add_u32 s16, s16, byval_align16_f64_arg@rel32@lo+4 +; GFX10-NEXT: s_addc_u32 s17, s17, byval_align16_f64_arg@rel32@hi+12 +; GFX10-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:20 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:16 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: buffer_store_dword v34, off, s[0:3], s32 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_setpc_b64 s[16:17] +; +; GFX9-FLATSCR-LABEL: tail_call_byval_align16: +; GFX9-FLATSCR: ; %bb.0: ; %entry +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: scratch_load_dword v32, off, s32 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_getpc_b64 s[0:1] +; GFX9-FLATSCR-NEXT: s_add_u32 s0, s0, byval_align16_f64_arg@rel32@lo+4 +; GFX9-FLATSCR-NEXT: s_addc_u32 s1, s1, byval_align16_f64_arg@rel32@hi+12 +; GFX9-FLATSCR-NEXT: scratch_store_dword off, v32, s32 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: scratch_load_dwordx2 v[32:33], off, s32 offset:24 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: scratch_store_dwordx2 off, v[32:33], s32 offset:16 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_setpc_b64 s[0:1] +; +; GFX11-LABEL: tail_call_byval_align16: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: scratch_load_b32 v32, off, s32 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: s_getpc_b64 s[0:1] +; GFX11-NEXT: s_add_u32 s0, s0, byval_align16_f64_arg@rel32@lo+4 +; GFX11-NEXT: s_addc_u32 s1, s1, byval_align16_f64_arg@rel32@hi+12 +; GFX11-NEXT: scratch_store_b32 off, v32, s32 +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: scratch_load_b64 v[32:33], off, s32 offset:24 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: scratch_store_b64 off, v[32:33], s32 offset:16 +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_setpc_b64 s[0:1] +; +; GFX12-LABEL: tail_call_byval_align16: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: scratch_load_b32 v32, off, s32 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: s_getpc_b64 s[0:1] +; GFX12-NEXT: s_sext_i32_i16 s1, s1 +; GFX12-NEXT: s_add_co_u32 s0, s0, byval_align16_f64_arg@rel32@lo+8 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, byval_align16_f64_arg@rel32@hi+16 +; GFX12-NEXT: scratch_store_b32 off, v32, s32 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: scratch_load_b64 v[32:33], off, s32 offset:24 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: scratch_store_b64 off, v[32:33], s32 offset:16 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_setpc_b64 s[0:1] +entry: + %alloca = alloca double, align 8, addrspace(5) + tail call void @byval_align16_f64_arg(<32 x i32> %val, ptr addrspace(5) byval(double) align 16 %alloca) + ret void +} + +; from udiv.ll +; covers s_load +; +define amdgpu_kernel void @udiv_i32(ptr addrspace(1) %out, i32 %x, i32 %y) { +; GFX9-LABEL: udiv_i32: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3 +; GFX9-NEXT: s_sub_i32 s4, 0, s3 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s5, v0 +; GFX9-NEXT: s_mul_i32 s4, s4, s5 +; GFX9-NEXT: s_mul_hi_u32 s4, s5, s4 +; GFX9-NEXT: s_add_i32 s5, s5, s4 +; GFX9-NEXT: s_mul_hi_u32 s4, s2, s5 +; GFX9-NEXT: s_mul_i32 s5, s4, s3 +; GFX9-NEXT: s_sub_i32 s2, s2, s5 +; GFX9-NEXT: s_add_i32 s6, s4, 1 +; GFX9-NEXT: s_sub_i32 s5, s2, s3 +; GFX9-NEXT: s_cmp_ge_u32 s2, s3 +; GFX9-NEXT: s_cselect_b32 s4, s6, s4 +; GFX9-NEXT: s_cselect_b32 s2, s5, s2 +; GFX9-NEXT: s_add_i32 s5, s4, 1 +; GFX9-NEXT: s_cmp_ge_u32 s2, s3 +; GFX9-NEXT: s_cselect_b32 s2, s5, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: global_store_dword v1, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: udiv_i32: +; GFX90A: ; %bb.0: +; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: v_mov_b32_e32 v1, 0 +; GFX90A-NEXT: v_cvt_f32_u32_e32 v0, s3 +; GFX90A-NEXT: s_sub_i32 s4, 0, s3 +; GFX90A-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX90A-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX90A-NEXT: v_readfirstlane_b32 s5, v0 +; GFX90A-NEXT: s_mul_i32 s4, s4, s5 +; GFX90A-NEXT: s_mul_hi_u32 s4, s5, s4 +; GFX90A-NEXT: s_add_i32 s5, s5, s4 +; GFX90A-NEXT: s_mul_hi_u32 s4, s2, s5 +; GFX90A-NEXT: s_mul_i32 s5, s4, s3 +; GFX90A-NEXT: s_sub_i32 s2, s2, s5 +; GFX90A-NEXT: s_add_i32 s6, s4, 1 +; GFX90A-NEXT: s_sub_i32 s5, s2, s3 +; GFX90A-NEXT: s_cmp_ge_u32 s2, s3 +; GFX90A-NEXT: s_cselect_b32 s4, s6, s4 +; GFX90A-NEXT: s_cselect_b32 s2, s5, s2 +; GFX90A-NEXT: s_add_i32 s5, s4, 1 +; GFX90A-NEXT: s_cmp_ge_u32 s2, s3 +; GFX90A-NEXT: s_cselect_b32 s2, s5, s4 +; GFX90A-NEXT: v_mov_b32_e32 v0, s2 +; GFX90A-NEXT: global_store_dword v1, v0, s[0:1] +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: udiv_i32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s3 +; GFX10-NEXT: s_sub_i32 s5, 0, s3 +; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX10-NEXT: v_readfirstlane_b32 s4, v0 +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: s_mul_i32 s5, s5, s4 +; GFX10-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX10-NEXT: s_add_i32 s4, s4, s5 +; GFX10-NEXT: s_mul_hi_u32 s4, s2, s4 +; GFX10-NEXT: s_mul_i32 s5, s4, s3 +; GFX10-NEXT: s_sub_i32 s2, s2, s5 +; GFX10-NEXT: s_add_i32 s5, s4, 1 +; GFX10-NEXT: s_sub_i32 s6, s2, s3 +; GFX10-NEXT: s_cmp_ge_u32 s2, s3 +; GFX10-NEXT: s_cselect_b32 s4, s5, s4 +; GFX10-NEXT: s_cselect_b32 s2, s6, s2 +; GFX10-NEXT: s_add_i32 s5, s4, 1 +; GFX10-NEXT: s_cmp_ge_u32 s2, s3 +; GFX10-NEXT: s_cselect_b32 s2, s5, s4 +; GFX10-NEXT: v_mov_b32_e32 v1, s2 +; GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: udiv_i32: +; GFX9-FLATSCR: ; %bb.0: +; GFX9-FLATSCR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-FLATSCR-NEXT: v_cvt_f32_u32_e32 v0, s3 +; GFX9-FLATSCR-NEXT: s_sub_i32 s4, 0, s3 +; GFX9-FLATSCR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX9-FLATSCR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX9-FLATSCR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-FLATSCR-NEXT: v_readfirstlane_b32 s5, v0 +; GFX9-FLATSCR-NEXT: s_mul_i32 s4, s4, s5 +; GFX9-FLATSCR-NEXT: s_mul_hi_u32 s4, s5, s4 +; GFX9-FLATSCR-NEXT: s_add_i32 s5, s5, s4 +; GFX9-FLATSCR-NEXT: s_mul_hi_u32 s4, s2, s5 +; GFX9-FLATSCR-NEXT: s_mul_i32 s5, s4, s3 +; GFX9-FLATSCR-NEXT: s_sub_i32 s2, s2, s5 +; GFX9-FLATSCR-NEXT: s_add_i32 s6, s4, 1 +; GFX9-FLATSCR-NEXT: s_sub_i32 s5, s2, s3 +; GFX9-FLATSCR-NEXT: s_cmp_ge_u32 s2, s3 +; GFX9-FLATSCR-NEXT: s_cselect_b32 s4, s6, s4 +; GFX9-FLATSCR-NEXT: s_cselect_b32 s2, s5, s2 +; GFX9-FLATSCR-NEXT: s_add_i32 s5, s4, 1 +; GFX9-FLATSCR-NEXT: s_cmp_ge_u32 s2, s3 +; GFX9-FLATSCR-NEXT: s_cselect_b32 s2, s5, s4 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-FLATSCR-NEXT: global_store_dword v1, v0, s[0:1] +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: udiv_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s3 +; GFX11-NEXT: s_sub_i32 s5, 0, s3 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_readfirstlane_b32 s4, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: s_mul_i32 s5, s5, s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX11-NEXT: s_add_i32 s4, s4, s5 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_hi_u32 s4, s2, s4 +; GFX11-NEXT: s_mul_i32 s5, s4, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_sub_i32 s2, s2, s5 +; GFX11-NEXT: s_add_i32 s5, s4, 1 +; GFX11-NEXT: s_sub_i32 s6, s2, s3 +; GFX11-NEXT: s_cmp_ge_u32 s2, s3 +; GFX11-NEXT: s_cselect_b32 s4, s5, s4 +; GFX11-NEXT: s_cselect_b32 s2, s6, s2 +; GFX11-NEXT: s_add_i32 s5, s4, 1 +; GFX11-NEXT: s_cmp_ge_u32 s2, s3 +; GFX11-NEXT: s_cselect_b32 s2, s5, s4 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v1, s2 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: udiv_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_cvt_f32_u32 s4, s3 +; GFX12-NEXT: s_sub_co_i32 s5, 0, s3 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1) +; GFX12-NEXT: v_rcp_iflag_f32_e32 v0, s4 +; GFX12-NEXT: v_readfirstlane_b32 s4, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) +; GFX12-NEXT: s_mul_f32 s4, s4, 0x4f7ffffe +; GFX12-NEXT: s_cvt_u32_f32 s4, s4 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s5, s5, s4 +; GFX12-NEXT: s_mul_hi_u32 s5, s4, s5 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_add_co_i32 s4, s4, s5 +; GFX12-NEXT: s_mul_hi_u32 s4, s2, s4 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s5, s4, s3 +; GFX12-NEXT: s_sub_co_i32 s2, s2, s5 +; GFX12-NEXT: s_add_co_i32 s5, s4, 1 +; GFX12-NEXT: s_sub_co_i32 s6, s2, s3 +; GFX12-NEXT: s_cmp_ge_u32 s2, s3 +; GFX12-NEXT: s_cselect_b32 s4, s5, s4 +; GFX12-NEXT: s_cselect_b32 s2, s6, s2 +; GFX12-NEXT: s_add_co_i32 s5, s4, 1 +; GFX12-NEXT: s_cmp_ge_u32 s2, s3 +; GFX12-NEXT: s_cselect_b32 s2, s5, s4 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm + %r = udiv i32 %x, %y + store i32 %r, ptr addrspace(1) %out + ret void +} + +declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) + +; from smrd.ll +; covers s_buffer_load +; +define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 { +; GFX9-LABEL: smrd_sgpr_offset: +; GFX9: ; %bb.0: ; %main_body +; GFX9-NEXT: s_buffer_load_dword s0, s[0:3], s4 offset:0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: ; return to shader part epilog +; +; GFX90A-LABEL: smrd_sgpr_offset: +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: s_buffer_load_dword s0, s[0:3], s4 offset:0x0 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: v_mov_b32_e32 v0, s0 +; GFX90A-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: smrd_sgpr_offset: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_buffer_load_dword s0, s[0:3], s4 offset:0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX9-FLATSCR-LABEL: smrd_sgpr_offset: +; GFX9-FLATSCR: ; %bb.0: ; %main_body +; GFX9-FLATSCR-NEXT: s_mov_b32 s11, s5 +; GFX9-FLATSCR-NEXT: s_mov_b32 s10, s4 +; GFX9-FLATSCR-NEXT: s_mov_b32 s9, s3 +; GFX9-FLATSCR-NEXT: s_mov_b32 s8, s2 +; GFX9-FLATSCR-NEXT: s_buffer_load_dword s0, s[8:11], s6 offset:0x0 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-FLATSCR-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: smrd_sgpr_offset: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_buffer_load_b32 s0, s[0:3], s4 offset:0x0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: smrd_sgpr_offset: +; GFX12: ; %bb.0: ; %main_body +; GFX12-NEXT: s_buffer_load_b32 s0, s[0:3], s4 offset:0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_mov_b32_e32 v0, s0 +; GFX12-NEXT: ; return to shader part epilog +main_body: + %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 0) + ret float %r +} + +; from atomic_load_add.ll +; covers s_load, ds_add (atomic without return) +; +define amdgpu_kernel void @atomic_add_local(ptr addrspace(3) %local) { +; GFX9-LABEL: atomic_add_local: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_mov_b64 s[2:3], exec +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: s_cbranch_execz .LBB5_2 +; GFX9-NEXT: ; %bb.1: +; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bcnt1_i32_b64 s1, s[2:3] +; GFX9-NEXT: s_mul_i32 s1, s1, 5 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: ds_add_u32 v0, v1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: .LBB5_2: +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: atomic_add_local: +; GFX90A: ; %bb.0: +; GFX90A-NEXT: s_mov_b64 s[2:3], exec +; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX90A-NEXT: s_cbranch_execz .LBB5_2 +; GFX90A-NEXT: ; %bb.1: +; GFX90A-NEXT: s_load_dword s0, s[0:1], 0x24 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_bcnt1_i32_b64 s1, s[2:3] +; GFX90A-NEXT: s_mul_i32 s1, s1, 5 +; GFX90A-NEXT: v_mov_b32_e32 v1, s1 +; GFX90A-NEXT: v_mov_b32_e32 v0, s0 +; GFX90A-NEXT: ds_add_u32 v0, v1 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: .LBB5_2: +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: atomic_add_local: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s2, exec_lo +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB5_2 +; GFX10-NEXT: ; %bb.1: +; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_bcnt1_i32_b32 s1, s2 +; GFX10-NEXT: s_mul_i32 s1, s1, 5 +; GFX10-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ds_add_u32 v0, v1 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: buffer_gl0_inv +; GFX10-NEXT: .LBB5_2: +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: atomic_add_local: +; GFX9-FLATSCR: ; %bb.0: +; GFX9-FLATSCR-NEXT: s_mov_b64 s[2:3], exec +; GFX9-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-FLATSCR-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-FLATSCR-NEXT: s_cbranch_execz .LBB5_2 +; GFX9-FLATSCR-NEXT: ; %bb.1: +; GFX9-FLATSCR-NEXT: s_load_dword s0, s[0:1], 0x24 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: s_bcnt1_i32_b64 s1, s[2:3] +; GFX9-FLATSCR-NEXT: s_mul_i32 s1, s1, 5 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-FLATSCR-NEXT: ds_add_u32 v0, v1 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: .LBB5_2: +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: atomic_add_local: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s2, exec_lo +; GFX11-NEXT: s_mov_b32 s3, exec_lo +; GFX11-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB5_2 +; GFX11-NEXT: ; %bb.1: +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_bcnt1_i32_b32 s1, s2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_i32 s1, s1, 5 +; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0 +; GFX11-NEXT: ds_add_u32 v0, v1 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: buffer_gl0_inv +; GFX11-NEXT: .LBB5_2: +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: atomic_add_local: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mov_b32 s2, exec_lo +; GFX12-NEXT: s_mov_b32 s3, exec_lo +; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX12-NEXT: s_cbranch_execz .LBB5_2 +; GFX12-NEXT: ; %bb.1: +; GFX12-NEXT: s_load_b32 s0, s[0:1], 0x24 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_bcnt1_i32_b32 s1, s2 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s1, s1, 5 +; GFX12-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0 +; GFX12-NEXT: ds_add_u32 v0, v1 +; GFX12-NEXT: s_wait_dscnt 0x0 +; GFX12-NEXT: global_inv scope:SCOPE_SE +; GFX12-NEXT: .LBB5_2: +; GFX12-NEXT: s_endpgm + %unused = atomicrmw volatile add ptr addrspace(3) %local, i32 5 seq_cst + ret void +} + +; from flat_atomics_i32_system.ll +; covers flat_atomic_swap (atomic without return) +; +define void @flat_atomic_xchg_i32_noret(ptr %ptr, i32 %in) { +; GFX9-LABEL: flat_atomic_xchg_i32_noret: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: flat_atomic_swap v[0:1], v2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX90A-LABEL: flat_atomic_xchg_i32_noret: +; GFX90A: ; %bb.0: +; GFX90A-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX90A-NEXT: buffer_wbl2 +; GFX90A-NEXT: flat_atomic_swap v[0:1], v2 +; GFX90A-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX90A-NEXT: buffer_invl2 +; GFX90A-NEXT: buffer_wbinvl1_vol +; GFX90A-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: flat_atomic_xchg_i32_noret: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: flat_atomic_swap v[0:1], v2 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: buffer_gl1_inv +; GFX10-NEXT: buffer_gl0_inv +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-FLATSCR-LABEL: flat_atomic_xchg_i32_noret: +; GFX9-FLATSCR: ; %bb.0: +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: flat_atomic_swap v[0:1], v2 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-FLATSCR-NEXT: buffer_wbinvl1_vol +; GFX9-FLATSCR-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: flat_atomic_xchg_i32_noret: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: flat_atomic_swap_b32 v[0:1], v2 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: buffer_gl1_inv +; GFX11-NEXT: buffer_gl0_inv +; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX12-LABEL: flat_atomic_xchg_i32_noret: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX12-NEXT: s_wait_expcnt 0x0 +; GFX12-NEXT: s_wait_samplecnt 0x0 +; GFX12-NEXT: s_wait_bvhcnt 0x0 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: flat_atomic_swap_b32 v[0:1], v2 +; GFX12-NEXT: s_wait_storecnt_dscnt 0x0 +; GFX12-NEXT: global_inv scope:SCOPE_SYS +; GFX12-NEXT: s_setpc_b64 s[30:31] + %tmp0 = atomicrmw xchg ptr %ptr, i32 %in seq_cst + ret void +} + +; from atomic_load_add.ll +; covers s_load, ds_add_rtn (atomic with return) +; +define amdgpu_kernel void @atomic_add_ret_local(ptr addrspace(1) %out, ptr addrspace(3) %local) { +; GFX9-LABEL: atomic_add_ret_local: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_mov_b64 s[4:5], exec +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: s_cbranch_execz .LBB7_2 +; GFX9-NEXT: ; %bb.1: +; GFX9-NEXT: s_load_dword s6, s[0:1], 0x2c +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-NEXT: s_mul_i32 s4, s4, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: .LBB7_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX9-NEXT: global_store_dword v2, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: atomic_add_ret_local: +; GFX90A: ; %bb.0: +; GFX90A-NEXT: s_mov_b64 s[4:5], exec +; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX90A-NEXT: ; implicit-def: $vgpr1 +; GFX90A-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX90A-NEXT: s_cbranch_execz .LBB7_2 +; GFX90A-NEXT: ; %bb.1: +; GFX90A-NEXT: s_load_dword s6, s[0:1], 0x2c +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX90A-NEXT: s_mul_i32 s4, s4, 5 +; GFX90A-NEXT: v_mov_b32_e32 v2, s4 +; GFX90A-NEXT: v_mov_b32_e32 v1, s6 +; GFX90A-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: .LBB7_2: +; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: v_readfirstlane_b32 s2, v1 +; GFX90A-NEXT: v_mov_b32_e32 v2, 0 +; GFX90A-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX90A-NEXT: global_store_dword v2, v0, s[0:1] +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: atomic_add_ret_local: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s3, exec_lo +; GFX10-NEXT: ; implicit-def: $vgpr1 +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB7_2 +; GFX10-NEXT: ; %bb.1: +; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX10-NEXT: s_mul_i32 s3, s3, 5 +; GFX10-NEXT: v_mov_b32_e32 v2, s3 +; GFX10-NEXT: v_mov_b32_e32 v1, s4 +; GFX10-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: buffer_gl0_inv +; GFX10-NEXT: .LBB7_2: +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s2, v1 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: atomic_add_ret_local: +; GFX9-FLATSCR: ; %bb.0: +; GFX9-FLATSCR-NEXT: s_mov_b64 s[4:5], exec +; GFX9-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1 +; GFX9-FLATSCR-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-FLATSCR-NEXT: s_cbranch_execz .LBB7_2 +; GFX9-FLATSCR-NEXT: ; %bb.1: +; GFX9-FLATSCR-NEXT: s_load_dword s6, s[0:1], 0x2c +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-FLATSCR-NEXT: s_mul_i32 s4, s4, 5 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-FLATSCR-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: .LBB7_2: +; GFX9-FLATSCR-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-FLATSCR-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX9-FLATSCR-NEXT: global_store_dword v2, v0, s[0:1] +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: atomic_add_ret_local: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s3, exec_lo +; GFX11-NEXT: s_mov_b32 s2, exec_lo +; GFX11-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB7_2 +; GFX11-NEXT: ; %bb.1: +; GFX11-NEXT: s_load_b32 s4, s[0:1], 0x2c +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_i32 s3, s3, 5 +; GFX11-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v1, s4 +; GFX11-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: buffer_gl0_inv +; GFX11-NEXT: .LBB7_2: +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: atomic_add_ret_local: +; GFX12: ; %bb.0: +; GFX12-NEXT: s_mov_b32 s3, exec_lo +; GFX12-NEXT: s_mov_b32 s2, exec_lo +; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX12-NEXT: ; implicit-def: $vgpr1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX12-NEXT: s_cbranch_execz .LBB7_2 +; GFX12-NEXT: ; %bb.1: +; GFX12-NEXT: s_load_b32 s4, s[0:1], 0x2c +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s3, s3, 5 +; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mov_b32 v1, s4 +; GFX12-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX12-NEXT: s_wait_dscnt 0x0 +; GFX12-NEXT: global_inv scope:SCOPE_SE +; GFX12-NEXT: .LBB7_2: +; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_readfirstlane_b32 s2, v1 +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX12-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm + %val = atomicrmw volatile add ptr addrspace(3) %local, i32 5 seq_cst + store i32 %val, ptr addrspace(1) %out + ret void +} + +declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32 immarg) + +; from atomic_optimizations_buffer.ll +; covers buffer_atomic (atomic with return) +; +define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace(8) %inout) { +; GFX9-LABEL: add_i32_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_mov_b64 s[4:5], exec +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: s_cbranch_execz .LBB8_2 +; GFX9-NEXT: ; %bb.1: +; GFX9-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-NEXT: s_mul_i32 s4, s4, 5 +; GFX9-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: .LBB8_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX9-NEXT: global_store_dword v2, v0, s[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: add_i32_constant: +; GFX90A: ; %bb.0: ; %entry +; GFX90A-NEXT: s_mov_b64 s[4:5], exec +; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX90A-NEXT: ; implicit-def: $vgpr1 +; GFX90A-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX90A-NEXT: s_cbranch_execz .LBB8_2 +; GFX90A-NEXT: ; %bb.1: +; GFX90A-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX90A-NEXT: s_mul_i32 s4, s4, 5 +; GFX90A-NEXT: v_mov_b32_e32 v1, s4 +; GFX90A-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: .LBB8_2: +; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: v_readfirstlane_b32 s2, v1 +; GFX90A-NEXT: v_mov_b32_e32 v2, 0 +; GFX90A-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX90A-NEXT: global_store_dword v2, v0, s[0:1] +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: add_i32_constant: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s3, exec_lo +; GFX10-NEXT: ; implicit-def: $vgpr1 +; GFX10-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX10-NEXT: s_cbranch_execz .LBB8_2 +; GFX10-NEXT: ; %bb.1: +; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX10-NEXT: s_mul_i32 s3, s3, 5 +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: buffer_atomic_add v1, off, s[4:7], 0 glc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: .LBB8_2: +; GFX10-NEXT: s_waitcnt_depctr 0xffe3 +; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: v_readfirstlane_b32 s2, v1 +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: add_i32_constant: +; GFX9-FLATSCR: ; %bb.0: ; %entry +; GFX9-FLATSCR-NEXT: s_mov_b64 s[4:5], exec +; GFX9-FLATSCR-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-FLATSCR-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-FLATSCR-NEXT: ; implicit-def: $vgpr1 +; GFX9-FLATSCR-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-FLATSCR-NEXT: s_cbranch_execz .LBB8_2 +; GFX9-FLATSCR-NEXT: ; %bb.1: +; GFX9-FLATSCR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x34 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-FLATSCR-NEXT: s_mul_i32 s4, s4, 5 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, s4 +; GFX9-FLATSCR-NEXT: buffer_atomic_add v1, off, s[8:11], 0 glc +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: .LBB8_2: +; GFX9-FLATSCR-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-FLATSCR-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX9-FLATSCR-NEXT: global_store_dword v2, v0, s[0:1] +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: add_i32_constant: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s3, exec_lo +; GFX11-NEXT: s_mov_b32 s2, exec_lo +; GFX11-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX11-NEXT: ; implicit-def: $vgpr1 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX11-NEXT: s_cbranch_execz .LBB8_2 +; GFX11-NEXT: ; %bb.1: +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_i32 s3, s3, 5 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], 0 glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: .LBB8_2: +; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_readfirstlane_b32 s2, v1 +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: add_i32_constant: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: s_mov_b32 s3, exec_lo +; GFX12-NEXT: s_mov_b32 s2, exec_lo +; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, s3, 0 +; GFX12-NEXT: ; implicit-def: $vgpr1 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_cmpx_eq_u32_e32 0, v0 +; GFX12-NEXT: s_cbranch_execz .LBB8_2 +; GFX12-NEXT: ; %bb.1: +; GFX12-NEXT: s_load_b128 s[4:7], s[0:1], 0x34 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: s_mul_i32 s3, s3, 5 +; GFX12-NEXT: v_mov_b32_e32 v1, s3 +; GFX12-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: .LBB8_2: +; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: v_readfirstlane_b32 s2, v1 +; GFX12-NEXT: v_mov_b32_e32 v1, 0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX12-NEXT: global_store_b32 v1, v0, s[0:1] +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm +entry: + %old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0) + store i32 %old, ptr addrspace(1) %out + ret void +} + +declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) + +; from llvm.amdgcn.image.load.a16.ll +; covers image_load +; +define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { +; GFX9-LABEL: load.f32.1d: +; GFX9: ; %bb.0: ; %main_body +; GFX9-NEXT: image_load v0, v0, s[0:7] dmask:0x1 unorm a16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX90A-LABEL: load.f32.1d: +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: image_load v0, v0, s[0:7] dmask:0x1 unorm a16 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: load.f32.1d: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX9-FLATSCR-LABEL: load.f32.1d: +; GFX9-FLATSCR: ; %bb.0: ; %main_body +; GFX9-FLATSCR-NEXT: s_mov_b32 s11, s9 +; GFX9-FLATSCR-NEXT: s_mov_b32 s10, s8 +; GFX9-FLATSCR-NEXT: s_mov_b32 s9, s7 +; GFX9-FLATSCR-NEXT: s_mov_b32 s8, s6 +; GFX9-FLATSCR-NEXT: s_mov_b32 s7, s5 +; GFX9-FLATSCR-NEXT: s_mov_b32 s6, s4 +; GFX9-FLATSCR-NEXT: s_mov_b32 s5, s3 +; GFX9-FLATSCR-NEXT: s_mov_b32 s4, s2 +; GFX9-FLATSCR-NEXT: image_load v0, v0, s[4:11] dmask:0x1 unorm a16 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: load.f32.1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: load.f32.1d: +; GFX12: ; %bb.0: ; %main_body +; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: ; return to shader part epilog +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret <4 x float> %v +} + +declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) + +; from llvm.amdgcn.image.store.a16.ll +; covers image_store +; +define amdgpu_ps void @store_f32_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) { +; GFX9-LABEL: store_f32_1d: +; GFX9: ; %bb.0: ; %main_body +; GFX9-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: store_f32_1d: +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: v_mov_b32_e32 v5, v4 +; GFX90A-NEXT: v_mov_b32_e32 v4, v3 +; GFX90A-NEXT: v_mov_b32_e32 v3, v2 +; GFX90A-NEXT: v_mov_b32_e32 v2, v1 +; GFX90A-NEXT: image_store v[2:5], v0, s[0:7] dmask:0x1 unorm a16 +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: store_f32_1d: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: store_f32_1d: +; GFX9-FLATSCR: ; %bb.0: ; %main_body +; GFX9-FLATSCR-NEXT: s_mov_b32 s11, s9 +; GFX9-FLATSCR-NEXT: s_mov_b32 s10, s8 +; GFX9-FLATSCR-NEXT: s_mov_b32 s9, s7 +; GFX9-FLATSCR-NEXT: s_mov_b32 s8, s6 +; GFX9-FLATSCR-NEXT: s_mov_b32 s7, s5 +; GFX9-FLATSCR-NEXT: s_mov_b32 s6, s4 +; GFX9-FLATSCR-NEXT: s_mov_b32 s5, s3 +; GFX9-FLATSCR-NEXT: s_mov_b32 s4, s2 +; GFX9-FLATSCR-NEXT: image_store v[1:4], v0, s[4:11] dmask:0x1 unorm a16 +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: store_f32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm a16 +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: store_f32_1d: +; GFX12: ; %bb.0: ; %main_body +; GFX12-NEXT: image_store v[1:4], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D a16 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: s_endpgm + +main_body: + %x = extractelement <2 x i16> %coords, i32 0 + call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0) + ret void +} + +declare i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32, i32, <8 x i32>, i32, i32) + +; from llvm.amdgcn.image.atomic.dim.ll +; covers image_atomic (atomic with return) +; +define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { +; GFX9-LABEL: atomic_swap_1d: +; GFX9: ; %bb.0: ; %main_body +; GFX9-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 unorm glc +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX90A-LABEL: atomic_swap_1d: +; GFX90A: ; %bb.0: ; %main_body +; GFX90A-NEXT: v_mov_b32_e32 v2, v1 +; GFX90A-NEXT: image_atomic_swap v0, v2, s[0:7] dmask:0x1 unorm glc +; GFX90A-NEXT: s_waitcnt vmcnt(0) +; GFX90A-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: atomic_swap_1d: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX9-FLATSCR-LABEL: atomic_swap_1d: +; GFX9-FLATSCR: ; %bb.0: ; %main_body +; GFX9-FLATSCR-NEXT: s_mov_b32 s11, s9 +; GFX9-FLATSCR-NEXT: s_mov_b32 s10, s8 +; GFX9-FLATSCR-NEXT: s_mov_b32 s9, s7 +; GFX9-FLATSCR-NEXT: s_mov_b32 s8, s6 +; GFX9-FLATSCR-NEXT: s_mov_b32 s7, s5 +; GFX9-FLATSCR-NEXT: s_mov_b32 s6, s4 +; GFX9-FLATSCR-NEXT: s_mov_b32 s5, s3 +; GFX9-FLATSCR-NEXT: s_mov_b32 s4, s2 +; GFX9-FLATSCR-NEXT: image_atomic_swap v0, v1, s[4:11] dmask:0x1 unorm glc +; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) +; GFX9-FLATSCR-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: atomic_swap_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: atomic_swap_1d: +; GFX12: ; %bb.0: ; %main_body +; GFX12-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN +; GFX12-NEXT: s_wait_loadcnt 0x0 +; GFX12-NEXT: ; return to shader part epilog +main_body: + %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) + %out = bitcast i32 %v to float + ret float %out +} + +; from lds-bounds.ll +; covers ds_write_b64 (atomic without return) +@compute_lds = external addrspace(3) global [512 x i32], align 16 +; +define amdgpu_cs void @store_aligned(ptr addrspace(3) %ptr) #0 { +; GFX9-LABEL: store_aligned: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v1, 42 +; GFX9-NEXT: v_mov_b32_e32 v2, 43 +; GFX9-NEXT: ds_write_b64 v0, v[1:2] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: store_aligned: +; GFX90A: ; %bb.0: ; %entry +; GFX90A-NEXT: v_mov_b32_e32 v2, 42 +; GFX90A-NEXT: v_mov_b32_e32 v3, 43 +; GFX90A-NEXT: ds_write_b64 v0, v[2:3] +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: store_aligned: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v1, 42 +; GFX10-NEXT: v_mov_b32_e32 v2, 43 +; GFX10-NEXT: ds_write_b64 v0, v[1:2] +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: store_aligned: +; GFX9-FLATSCR: ; %bb.0: ; %entry +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 42 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 43 +; GFX9-FLATSCR-NEXT: ds_write_b64 v0, v[1:2] +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: store_aligned: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_dual_mov_b32 v1, 42 :: v_dual_mov_b32 v2, 43 +; GFX11-NEXT: ds_store_b64 v0, v[1:2] +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: store_aligned: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: v_dual_mov_b32 v1, 42 :: v_dual_mov_b32 v2, 43 +; GFX12-NEXT: ds_store_b64 v0, v[1:2] +; GFX12-NEXT: s_wait_dscnt 0x0 +; GFX12-NEXT: s_endpgm +entry: + %ptr.gep.1 = getelementptr i32, ptr addrspace(3) %ptr, i32 1 + + store i32 42, ptr addrspace(3) %ptr, align 8 + store i32 43, ptr addrspace(3) %ptr.gep.1 + ret void +} + + +; from lds-bounds.ll +; covers ds_read_b64 +; +define amdgpu_cs <2 x float> @load_aligned(ptr addrspace(3) %ptr) #0 { +; GFX9-LABEL: load_aligned: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: ds_read_b64 v[0:1], v0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX90A-LABEL: load_aligned: +; GFX90A: ; %bb.0: ; %entry +; GFX90A-NEXT: ds_read_b64 v[0:1], v0 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: load_aligned: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: ds_read_b64 v[0:1], v0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX9-FLATSCR-LABEL: load_aligned: +; GFX9-FLATSCR: ; %bb.0: ; %entry +; GFX9-FLATSCR-NEXT: ds_read_b64 v[0:1], v0 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: load_aligned: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: ds_load_b64 v[0:1], v0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: load_aligned: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: ds_load_b64 v[0:1], v0 +; GFX12-NEXT: s_wait_dscnt 0x0 +; GFX12-NEXT: ; return to shader part epilog +entry: + %ptr.gep.1 = getelementptr i32, ptr addrspace(3) %ptr, i32 1 + + %v.0 = load i32, ptr addrspace(3) %ptr, align 8 + %v.1 = load i32, ptr addrspace(3) %ptr.gep.1 + + %r.0 = insertelement <2 x i32> poison, i32 %v.0, i32 0 + %r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1 + %bc = bitcast <2 x i32> %r.1 to <2 x float> + ret <2 x float> %bc +} + +; from lds-bounds.ll +; covers ds_write2_b32 +; +define amdgpu_cs void @store_global_const_idx() #0 { +; GFX9-LABEL: store_global_const_idx: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v1, 42 +; GFX9-NEXT: v_mov_b32_e32 v2, 43 +; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset0:3 offset1:4 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_endpgm +; +; GFX90A-LABEL: store_global_const_idx: +; GFX90A: ; %bb.0: ; %entry +; GFX90A-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX90A-NEXT: v_mov_b32_e32 v1, 42 +; GFX90A-NEXT: v_mov_b32_e32 v2, 43 +; GFX90A-NEXT: ds_write2_b32 v0, v1, v2 offset0:3 offset1:4 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: s_endpgm +; +; GFX10-LABEL: store_global_const_idx: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX10-NEXT: v_mov_b32_e32 v1, 42 +; GFX10-NEXT: v_mov_b32_e32 v2, 43 +; GFX10-NEXT: ds_write2_b32 v0, v1, v2 offset0:3 offset1:4 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_endpgm +; +; GFX9-FLATSCR-LABEL: store_global_const_idx: +; GFX9-FLATSCR: ; %bb.0: ; %entry +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v1, 42 +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v2, 43 +; GFX9-FLATSCR-NEXT: ds_write2_b32 v0, v1, v2 offset0:3 offset1:4 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: s_endpgm +; +; GFX11-LABEL: store_global_const_idx: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_dual_mov_b32 v0, compute_lds@abs32@lo :: v_dual_mov_b32 v1, 42 +; GFX11-NEXT: v_mov_b32_e32 v2, 43 +; GFX11-NEXT: ds_store_2addr_b32 v0, v1, v2 offset0:3 offset1:4 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_endpgm +; +; GFX12-LABEL: store_global_const_idx: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: v_dual_mov_b32 v0, compute_lds@abs32@lo :: v_dual_mov_b32 v1, 42 +; GFX12-NEXT: v_mov_b32_e32 v2, 43 +; GFX12-NEXT: ds_store_2addr_b32 v0, v1, v2 offset0:3 offset1:4 +; GFX12-NEXT: s_wait_dscnt 0x0 +; GFX12-NEXT: s_endpgm +entry: + %ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 3 + %ptr.b = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 4 + + store i32 42, ptr addrspace(3) %ptr.a + store i32 43, ptr addrspace(3) %ptr.b + ret void +} + +; from lds-bounds.ll +; covers ds_read2_b32 +; +define amdgpu_cs <2 x float> @load_global_const_idx() #0 { +; GFX9-LABEL: load_global_const_idx: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX9-NEXT: ds_read2_b32 v[0:1], v0 offset0:3 offset1:4 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: ; return to shader part epilog +; +; GFX90A-LABEL: load_global_const_idx: +; GFX90A: ; %bb.0: ; %entry +; GFX90A-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX90A-NEXT: ds_read2_b32 v[0:1], v0 offset0:3 offset1:4 +; GFX90A-NEXT: s_waitcnt lgkmcnt(0) +; GFX90A-NEXT: ; return to shader part epilog +; +; GFX10-LABEL: load_global_const_idx: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX10-NEXT: ds_read2_b32 v[0:1], v0 offset0:3 offset1:4 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX9-FLATSCR-LABEL: load_global_const_idx: +; GFX9-FLATSCR: ; %bb.0: ; %entry +; GFX9-FLATSCR-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX9-FLATSCR-NEXT: ds_read2_b32 v[0:1], v0 offset0:3 offset1:4 +; GFX9-FLATSCR-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-FLATSCR-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: load_global_const_idx: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX11-NEXT: ds_load_2addr_b32 v[0:1], v0 offset0:3 offset1:4 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; +; GFX12-LABEL: load_global_const_idx: +; GFX12: ; %bb.0: ; %entry +; GFX12-NEXT: v_mov_b32_e32 v0, compute_lds@abs32@lo +; GFX12-NEXT: ds_load_2addr_b32 v[0:1], v0 offset0:3 offset1:4 +; GFX12-NEXT: s_wait_dscnt 0x0 +; GFX12-NEXT: ; return to shader part epilog +entry: + %ptr.a = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 3 + %ptr.b = getelementptr [512 x i32], ptr addrspace(3) @compute_lds, i32 0, i32 4 + + %v.0 = load i32, ptr addrspace(3) %ptr.a + %v.1 = load i32, ptr addrspace(3) %ptr.b + + %r.0 = insertelement <2 x i32> poison, i32 %v.0, i32 0 + %r.1 = insertelement <2 x i32> %r.0, i32 %v.1, i32 1 + %bc = bitcast <2 x i32> %r.1 to <2 x float> + ret <2 x float> %bc +} + -- GitLab From 4d80dff819d1164775d0d55fc68bffedb90ba53c Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 10 Apr 2024 13:56:18 -0400 Subject: [PATCH 429/695] int -> uintptr_t to silence diagnostics 'int' may not be sufficiently large to store a pointer representation anyway, so this is also a correctness fix. --- clang/lib/AST/Interp/FunctionPointer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/AST/Interp/FunctionPointer.h b/clang/lib/AST/Interp/FunctionPointer.h index e7fad8161fd9..f61f9ded0bf0 100644 --- a/clang/lib/AST/Interp/FunctionPointer.h +++ b/clang/lib/AST/Interp/FunctionPointer.h @@ -24,7 +24,7 @@ private: public: // FIXME: We might want to track the fact that the Function pointer // has been created from an integer and is most likely garbage anyway. - FunctionPointer(int IntVal = 0, const Descriptor *Desc = nullptr) + FunctionPointer(uintptr_t IntVal = 0, const Descriptor *Desc = nullptr) : Func(reinterpret_cast(IntVal)) {} FunctionPointer(const Function *Func) : Func(Func) { assert(Func); } -- GitLab From 21009f466ece9f21b18e1bb03bd74b566188bae5 Mon Sep 17 00:00:00 2001 From: martinboehme Date: Wed, 10 Apr 2024 20:03:35 +0200 Subject: [PATCH 430/695] [clang][dataflow] Propagate locations from result objects to initializers. (#87320) Previously, we were propagating storage locations the other way around, i.e. from initializers to result objects, using `RecordValue::getLoc()`. This gave the wrong behavior in some cases -- see the newly added or fixed tests in this patch. In addition, this patch now unblocks removing the `RecordValue` class entirely, as we no longer need `RecordValue::getLoc()`. With this patch, the test `TransferTest.DifferentReferenceLocInJoin` started to fail because the framework now always uses the same storge location for a `MaterializeTemporaryExpr`, meaning that the code under test no longer set up the desired state where a variable of reference type is mapped to two different storage locations in environments being joined. Rather than trying to modify this test to set up the test condition again, I have chosen to replace the test with an equivalent test in DataflowEnvironmentTest.cpp that sets up the test condition directly; because this test is more direct, it will also be less brittle in the face of future changes. --- .../FlowSensitive/DataflowEnvironment.h | 64 ++- .../FlowSensitive/DataflowEnvironment.cpp | 405 +++++++++++++----- clang/lib/Analysis/FlowSensitive/Transfer.cpp | 176 ++++---- .../TypeErasedDataflowAnalysis.cpp | 13 +- .../FlowSensitive/DataflowEnvironmentTest.cpp | 43 ++ .../Analysis/FlowSensitive/TransferTest.cpp | 172 +++++--- 6 files changed, 590 insertions(+), 283 deletions(-) diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index 9a65f76cdf56..706664d7db1c 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -30,6 +30,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" +#include #include #include @@ -344,17 +345,6 @@ public: /// location of the result object to pass in `this`, even though prvalues are /// otherwise not associated with storage locations. /// - /// FIXME: Currently, this simply returns a stable storage location for `E`, - /// but this doesn't do the right thing in scenarios like the following: - /// ``` - /// MyClass c = some_condition()? MyClass(foo) : MyClass(bar); - /// ``` - /// Here, `MyClass(foo)` and `MyClass(bar)` will have two different storage - /// locations, when in fact their storage locations should be the same. - /// Eventually, we want to propagate storage locations from result objects - /// down to the prvalues that initialize them, similar to the way that this is - /// done in Clang's CodeGen. - /// /// Requirements: /// `E` must be a prvalue of record type. RecordStorageLocation & @@ -462,7 +452,13 @@ public: /// Initializes the fields (including synthetic fields) of `Loc` with values, /// unless values of the field type are not supported or we hit one of the /// limits at which we stop producing values. - void initializeFieldsWithValues(RecordStorageLocation &Loc); + /// If `Type` is provided, initializes only those fields that are modeled for + /// `Type`; this is intended for use in cases where `Loc` is a derived type + /// and we only want to initialize the fields of a base type. + void initializeFieldsWithValues(RecordStorageLocation &Loc, QualType Type); + void initializeFieldsWithValues(RecordStorageLocation &Loc) { + initializeFieldsWithValues(Loc, Loc.getType()); + } /// Assigns `Val` as the value of `Loc` in the environment. void setValue(const StorageLocation &Loc, Value &Val); @@ -653,6 +649,9 @@ public: LLVM_DUMP_METHOD void dump(raw_ostream &OS) const; private: + using PrValueToResultObject = + llvm::DenseMap; + // The copy-constructor is for use in fork() only. Environment(const Environment &) = default; @@ -682,8 +681,10 @@ private: /// Initializes the fields (including synthetic fields) of `Loc` with values, /// unless values of the field type are not supported or we hit one of the /// limits at which we stop producing values (controlled by `Visited`, - /// `Depth`, and `CreatedValuesCount`). - void initializeFieldsWithValues(RecordStorageLocation &Loc, + /// `Depth`, and `CreatedValuesCount`). If `Type` is different from + /// `Loc.getType()`, initializes only those fields that are modeled for + /// `Type`. + void initializeFieldsWithValues(RecordStorageLocation &Loc, QualType Type, llvm::DenseSet &Visited, int Depth, int &CreatedValuesCount); @@ -702,22 +703,45 @@ private: /// and functions referenced in `FuncDecl`. `FuncDecl` must have a body. void initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl); + static PrValueToResultObject + buildResultObjectMap(DataflowAnalysisContext *DACtx, + const FunctionDecl *FuncDecl, + RecordStorageLocation *ThisPointeeLoc, + RecordStorageLocation *LocForRecordReturnVal); + // `DACtx` is not null and not owned by this object. DataflowAnalysisContext *DACtx; - // FIXME: move the fields `CallStack`, `ReturnVal`, `ReturnLoc` and - // `ThisPointeeLoc` into a separate call-context object, shared between - // environments in the same call. + // FIXME: move the fields `CallStack`, `ResultObjectMap`, `ReturnVal`, + // `ReturnLoc` and `ThisPointeeLoc` into a separate call-context object, + // shared between environments in the same call. // https://github.com/llvm/llvm-project/issues/59005 // `DeclContext` of the block being analysed if provided. std::vector CallStack; - // Value returned by the function (if it has non-reference return type). + // Maps from prvalues of record type to their result objects. Shared between + // all environments for the same function. + // FIXME: It's somewhat unsatisfactory that we have to use a `shared_ptr` + // here, though the cost is acceptable: The overhead of a `shared_ptr` is + // incurred when it is copied, and this happens only relatively rarely (when + // we fork the environment). The need for a `shared_ptr` will go away once we + // introduce a shared call-context object (see above). + std::shared_ptr ResultObjectMap; + + // The following three member variables handle various different types of + // return values. + // - If the return type is not a reference and not a record: Value returned + // by the function. Value *ReturnVal = nullptr; - // Storage location of the reference returned by the function (if it has - // reference return type). + // - If the return type is a reference: Storage location of the reference + // returned by the function. StorageLocation *ReturnLoc = nullptr; + // - If the return type is a record or the function being analyzed is a + // constructor: Storage location into which the return value should be + // constructed. + RecordStorageLocation *LocForRecordReturnVal = nullptr; + // The storage location of the `this` pointee. Should only be null if the // function being analyzed is only a function and not a method. RecordStorageLocation *ThisPointeeLoc = nullptr; diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 1bfa7ebcfd50..6c796b4ad923 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -15,6 +15,7 @@ #include "clang/Analysis/FlowSensitive/DataflowEnvironment.h" #include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" +#include "clang/AST/RecursiveASTVisitor.h" #include "clang/AST/Type.h" #include "clang/Analysis/FlowSensitive/DataflowLattice.h" #include "clang/Analysis/FlowSensitive/Value.h" @@ -26,6 +27,8 @@ #include #include +#define DEBUG_TYPE "dataflow" + namespace clang { namespace dataflow { @@ -354,6 +357,8 @@ getFieldsGlobalsAndFuncs(const Stmt &S, FieldSet &Fields, for (auto *Child : S.children()) if (Child != nullptr) getFieldsGlobalsAndFuncs(*Child, Fields, Vars, Funcs); + if (const auto *DefaultArg = dyn_cast(&S)) + getFieldsGlobalsAndFuncs(*DefaultArg->getExpr(), Fields, Vars, Funcs); if (const auto *DefaultInit = dyn_cast(&S)) getFieldsGlobalsAndFuncs(*DefaultInit->getExpr(), Fields, Vars, Funcs); @@ -386,6 +391,186 @@ getFieldsGlobalsAndFuncs(const Stmt &S, FieldSet &Fields, } } +namespace { + +// Visitor that builds a map from record prvalues to result objects. +// This traverses the body of the function to be analyzed; for each result +// object that it encounters, it propagates the storage location of the result +// object to all record prvalues that can initialize it. +class ResultObjectVisitor : public RecursiveASTVisitor { +public: + // `ResultObjectMap` will be filled with a map from record prvalues to result + // object. If the function being analyzed returns a record by value, + // `LocForRecordReturnVal` is the location to which this record should be + // written; otherwise, it is null. + explicit ResultObjectVisitor( + llvm::DenseMap &ResultObjectMap, + RecordStorageLocation *LocForRecordReturnVal, + DataflowAnalysisContext &DACtx) + : ResultObjectMap(ResultObjectMap), + LocForRecordReturnVal(LocForRecordReturnVal), DACtx(DACtx) {} + + bool shouldVisitImplicitCode() { return true; } + + bool shouldVisitLambdaBody() const { return false; } + + // Traverse all member and base initializers of `Ctor`. This function is not + // called by `RecursiveASTVisitor`; it should be called manually if we are + // analyzing a constructor. `ThisPointeeLoc` is the storage location that + // `this` points to. + void TraverseConstructorInits(const CXXConstructorDecl *Ctor, + RecordStorageLocation *ThisPointeeLoc) { + assert(ThisPointeeLoc != nullptr); + for (const CXXCtorInitializer *Init : Ctor->inits()) { + Expr *InitExpr = Init->getInit(); + if (FieldDecl *Field = Init->getMember(); + Field != nullptr && Field->getType()->isRecordType()) { + PropagateResultObject(InitExpr, cast( + ThisPointeeLoc->getChild(*Field))); + } else if (Init->getBaseClass()) { + PropagateResultObject(InitExpr, ThisPointeeLoc); + } + + // Ensure that any result objects within `InitExpr` (e.g. temporaries) + // are also propagated to the prvalues that initialize them. + TraverseStmt(InitExpr); + + // If this is a `CXXDefaultInitExpr`, also propagate any result objects + // within the default expression. + if (auto *DefaultInit = dyn_cast(InitExpr)) + TraverseStmt(DefaultInit->getExpr()); + } + } + + bool TraverseBindingDecl(BindingDecl *BD) { + // `RecursiveASTVisitor` doesn't traverse holding variables for + // `BindingDecl`s by itself, so we need to tell it to. + if (VarDecl *HoldingVar = BD->getHoldingVar()) + TraverseDecl(HoldingVar); + return RecursiveASTVisitor::TraverseBindingDecl(BD); + } + + bool VisitVarDecl(VarDecl *VD) { + if (VD->getType()->isRecordType() && VD->hasInit()) + PropagateResultObject( + VD->getInit(), + &cast(DACtx.getStableStorageLocation(*VD))); + return true; + } + + bool VisitMaterializeTemporaryExpr(MaterializeTemporaryExpr *MTE) { + if (MTE->getType()->isRecordType()) + PropagateResultObject( + MTE->getSubExpr(), + &cast(DACtx.getStableStorageLocation(*MTE))); + return true; + } + + bool VisitReturnStmt(ReturnStmt *Return) { + Expr *RetValue = Return->getRetValue(); + if (RetValue != nullptr && RetValue->getType()->isRecordType() && + RetValue->isPRValue()) + PropagateResultObject(RetValue, LocForRecordReturnVal); + return true; + } + + bool VisitExpr(Expr *E) { + // Clang's AST can have record-type prvalues without a result object -- for + // example as full-expressions contained in a compound statement or as + // arguments of call expressions. We notice this if we get here and a + // storage location has not yet been associated with `E`. In this case, + // treat this as if it was a `MaterializeTemporaryExpr`. + if (E->isPRValue() && E->getType()->isRecordType() && + !ResultObjectMap.contains(E)) + PropagateResultObject( + E, &cast(DACtx.getStableStorageLocation(*E))); + return true; + } + + // Assigns `Loc` as the result object location of `E`, then propagates the + // location to all lower-level prvalues that initialize the same object as + // `E` (or one of its base classes or member variables). + void PropagateResultObject(Expr *E, RecordStorageLocation *Loc) { + if (!E->isPRValue() || !E->getType()->isRecordType()) { + assert(false); + // Ensure we don't propagate the result object if we hit this in a + // release build. + return; + } + + ResultObjectMap[E] = Loc; + + // The following AST node kinds are "original initializers": They are the + // lowest-level AST node that initializes a given object, and nothing + // below them can initialize the same object (or part of it). + if (isa(E) || isa(E) || isa(E) || + isa(E) || isa(E) || + isa(E)) { + return; + } + + if (auto *InitList = dyn_cast(E)) { + if (!InitList->isSemanticForm()) + return; + if (InitList->isTransparent()) { + PropagateResultObject(InitList->getInit(0), Loc); + return; + } + + RecordInitListHelper InitListHelper(InitList); + + for (auto [Base, Init] : InitListHelper.base_inits()) { + assert(Base->getType().getCanonicalType() == + Init->getType().getCanonicalType()); + + // Storage location for the base class is the same as that of the + // derived class because we "flatten" the object hierarchy and put all + // fields in `RecordStorageLocation` of the derived class. + PropagateResultObject(Init, Loc); + } + + for (auto [Field, Init] : InitListHelper.field_inits()) { + // Fields of non-record type are handled in + // `TransferVisitor::VisitInitListExpr()`. + if (!Field->getType()->isRecordType()) + continue; + PropagateResultObject( + Init, cast(Loc->getChild(*Field))); + } + return; + } + + if (auto *Op = dyn_cast(E); Op && Op->isCommaOp()) { + PropagateResultObject(Op->getRHS(), Loc); + return; + } + + if (auto *Cond = dyn_cast(E)) { + PropagateResultObject(Cond->getTrueExpr(), Loc); + PropagateResultObject(Cond->getFalseExpr(), Loc); + return; + } + + // All other expression nodes that propagate a record prvalue should have + // exactly one child. + SmallVector Children(E->child_begin(), E->child_end()); + LLVM_DEBUG({ + if (Children.size() != 1) + E->dump(); + }); + assert(Children.size() == 1); + for (Stmt *S : Children) + PropagateResultObject(cast(S), Loc); + } + +private: + llvm::DenseMap &ResultObjectMap; + RecordStorageLocation *LocForRecordReturnVal; + DataflowAnalysisContext &DACtx; +}; + +} // namespace + Environment::Environment(DataflowAnalysisContext &DACtx) : DACtx(&DACtx), FlowConditionToken(DACtx.arena().makeFlowConditionToken()) {} @@ -401,17 +586,23 @@ void Environment::initialize() { if (DeclCtx == nullptr) return; - if (const auto *FuncDecl = dyn_cast(DeclCtx)) { - assert(FuncDecl->doesThisDeclarationHaveABody()); + const auto *FuncDecl = dyn_cast(DeclCtx); + if (FuncDecl == nullptr) + return; + + assert(FuncDecl->doesThisDeclarationHaveABody()); - initFieldsGlobalsAndFuncs(FuncDecl); + initFieldsGlobalsAndFuncs(FuncDecl); - for (const auto *ParamDecl : FuncDecl->parameters()) { - assert(ParamDecl != nullptr); - setStorageLocation(*ParamDecl, createObject(*ParamDecl, nullptr)); - } + for (const auto *ParamDecl : FuncDecl->parameters()) { + assert(ParamDecl != nullptr); + setStorageLocation(*ParamDecl, createObject(*ParamDecl, nullptr)); } + if (FuncDecl->getReturnType()->isRecordType()) + LocForRecordReturnVal = &cast( + createStorageLocation(FuncDecl->getReturnType())); + if (const auto *MethodDecl = dyn_cast(DeclCtx)) { auto *Parent = MethodDecl->getParent(); assert(Parent != nullptr); @@ -444,6 +635,12 @@ void Environment::initialize() { initializeFieldsWithValues(ThisLoc); } } + + // We do this below the handling of `CXXMethodDecl` above so that we can + // be sure that the storage location for `this` has been set. + ResultObjectMap = std::make_shared( + buildResultObjectMap(DACtx, FuncDecl, getThisPointeeStorageLocation(), + LocForRecordReturnVal)); } // FIXME: Add support for resetting globals after function calls to enable @@ -484,13 +681,18 @@ void Environment::initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl) { if (getStorageLocation(*D) != nullptr) continue; - setStorageLocation(*D, createObject(*D)); + // We don't run transfer functions on the initializers of global variables, + // so they won't be associated with a value or storage location. We + // therefore intentionally don't pass an initializer to `createObject()`; + // in particular, this ensures that `createObject()` will initialize the + // fields of record-type variables with values. + setStorageLocation(*D, createObject(*D, nullptr)); } for (const FunctionDecl *FD : Funcs) { if (getStorageLocation(*FD) != nullptr) continue; - auto &Loc = createStorageLocation(FD->getType()); + auto &Loc = createStorageLocation(*FD); setStorageLocation(*FD, Loc); } } @@ -519,6 +721,9 @@ Environment Environment::pushCall(const CallExpr *Call) const { } } + if (Call->getType()->isRecordType() && Call->isPRValue()) + Env.LocForRecordReturnVal = &Env.getResultObjectLocation(*Call); + Env.pushCallInternal(Call->getDirectCallee(), llvm::ArrayRef(Call->getArgs(), Call->getNumArgs())); @@ -529,6 +734,7 @@ Environment Environment::pushCall(const CXXConstructExpr *Call) const { Environment Env(*this); Env.ThisPointeeLoc = &Env.getResultObjectLocation(*Call); + Env.LocForRecordReturnVal = &Env.getResultObjectLocation(*Call); Env.pushCallInternal(Call->getConstructor(), llvm::ArrayRef(Call->getArgs(), Call->getNumArgs())); @@ -557,6 +763,10 @@ void Environment::pushCallInternal(const FunctionDecl *FuncDecl, const VarDecl *Param = *ParamIt; setStorageLocation(*Param, createObject(*Param, Args[ArgIndex])); } + + ResultObjectMap = std::make_shared( + buildResultObjectMap(DACtx, FuncDecl, getThisPointeeStorageLocation(), + LocForRecordReturnVal)); } void Environment::popCall(const CallExpr *Call, const Environment &CalleeEnv) { @@ -600,6 +810,9 @@ bool Environment::equivalentTo(const Environment &Other, if (ReturnLoc != Other.ReturnLoc) return false; + if (LocForRecordReturnVal != Other.LocForRecordReturnVal) + return false; + if (ThisPointeeLoc != Other.ThisPointeeLoc) return false; @@ -623,8 +836,10 @@ LatticeEffect Environment::widen(const Environment &PrevEnv, assert(DACtx == PrevEnv.DACtx); assert(ReturnVal == PrevEnv.ReturnVal); assert(ReturnLoc == PrevEnv.ReturnLoc); + assert(LocForRecordReturnVal == PrevEnv.LocForRecordReturnVal); assert(ThisPointeeLoc == PrevEnv.ThisPointeeLoc); assert(CallStack == PrevEnv.CallStack); + assert(ResultObjectMap == PrevEnv.ResultObjectMap); auto Effect = LatticeEffect::Unchanged; @@ -656,12 +871,16 @@ Environment Environment::join(const Environment &EnvA, const Environment &EnvB, Environment::ValueModel &Model, ExprJoinBehavior ExprBehavior) { assert(EnvA.DACtx == EnvB.DACtx); + assert(EnvA.LocForRecordReturnVal == EnvB.LocForRecordReturnVal); assert(EnvA.ThisPointeeLoc == EnvB.ThisPointeeLoc); assert(EnvA.CallStack == EnvB.CallStack); + assert(EnvA.ResultObjectMap == EnvB.ResultObjectMap); Environment JoinedEnv(*EnvA.DACtx); JoinedEnv.CallStack = EnvA.CallStack; + JoinedEnv.ResultObjectMap = EnvA.ResultObjectMap; + JoinedEnv.LocForRecordReturnVal = EnvA.LocForRecordReturnVal; JoinedEnv.ThisPointeeLoc = EnvA.ThisPointeeLoc; if (EnvA.ReturnVal == nullptr || EnvB.ReturnVal == nullptr) { @@ -730,6 +949,12 @@ StorageLocation &Environment::createStorageLocation(const Expr &E) { void Environment::setStorageLocation(const ValueDecl &D, StorageLocation &Loc) { assert(!DeclToLoc.contains(&D)); + // The only kinds of declarations that may have a "variable" storage location + // are declarations of reference type and `BindingDecl`. For all other + // declaration, the storage location should be the stable storage location + // returned by `createStorageLocation()`. + assert(D.getType()->isReferenceType() || isa(D) || + &Loc == &createStorageLocation(D)); DeclToLoc[&D] = &Loc; } @@ -791,50 +1016,29 @@ Environment::getResultObjectLocation(const Expr &RecordPRValue) const { assert(RecordPRValue.getType()->isRecordType()); assert(RecordPRValue.isPRValue()); - // Returns a storage location that we can use if assertions fail. - auto FallbackForAssertFailure = - [this, &RecordPRValue]() -> RecordStorageLocation & { + assert(ResultObjectMap != nullptr); + RecordStorageLocation *Loc = ResultObjectMap->lookup(&RecordPRValue); + assert(Loc != nullptr); + // In release builds, use the "stable" storage location if the map lookup + // failed. + if (Loc == nullptr) return cast( DACtx->getStableStorageLocation(RecordPRValue)); - }; - - if (isOriginalRecordConstructor(RecordPRValue)) { - auto *Val = cast_or_null(getValue(RecordPRValue)); - // The builtin transfer function should have created a `RecordValue` for all - // original record constructors. - assert(Val); - if (!Val) - return FallbackForAssertFailure(); - return Val->getLoc(); - } - - if (auto *Op = dyn_cast(&RecordPRValue); - Op && Op->isCommaOp()) { - return getResultObjectLocation(*Op->getRHS()); - } - - // All other expression nodes that propagate a record prvalue should have - // exactly one child. - llvm::SmallVector children(RecordPRValue.child_begin(), - RecordPRValue.child_end()); - assert(children.size() == 1); - if (children.empty()) - return FallbackForAssertFailure(); - - return getResultObjectLocation(*cast(children[0])); + return *Loc; } PointerValue &Environment::getOrCreateNullPointerValue(QualType PointeeType) { return DACtx->getOrCreateNullPointerValue(PointeeType); } -void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc) { +void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, + QualType Type) { llvm::DenseSet Visited; int CreatedValuesCount = 0; - initializeFieldsWithValues(Loc, Visited, 0, CreatedValuesCount); + initializeFieldsWithValues(Loc, Type, Visited, 0, CreatedValuesCount); if (CreatedValuesCount > MaxCompositeValueSize) { - llvm::errs() << "Attempting to initialize a huge value of type: " - << Loc.getType() << '\n'; + llvm::errs() << "Attempting to initialize a huge value of type: " << Type + << '\n'; } } @@ -848,8 +1052,7 @@ void Environment::setValue(const Expr &E, Value &Val) { const Expr &CanonE = ignoreCFGOmittedNodes(E); if (auto *RecordVal = dyn_cast(&Val)) { - assert(isOriginalRecordConstructor(CanonE) || - &RecordVal->getLoc() == &getResultObjectLocation(CanonE)); + assert(&RecordVal->getLoc() == &getResultObjectLocation(CanonE)); (void)RecordVal; } @@ -928,7 +1131,8 @@ Value *Environment::createValueUnlessSelfReferential( if (Type->isRecordType()) { CreatedValuesCount++; auto &Loc = cast(createStorageLocation(Type)); - initializeFieldsWithValues(Loc, Visited, Depth, CreatedValuesCount); + initializeFieldsWithValues(Loc, Loc.getType(), Visited, Depth, + CreatedValuesCount); return &refreshRecordValue(Loc, *this); } @@ -960,6 +1164,7 @@ Environment::createLocAndMaybeValue(QualType Ty, } void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, + QualType Type, llvm::DenseSet &Visited, int Depth, int &CreatedValuesCount) { @@ -967,8 +1172,8 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, if (FieldType->isRecordType()) { auto &FieldRecordLoc = cast(FieldLoc); setValue(FieldRecordLoc, create(FieldRecordLoc)); - initializeFieldsWithValues(FieldRecordLoc, Visited, Depth + 1, - CreatedValuesCount); + initializeFieldsWithValues(FieldRecordLoc, FieldRecordLoc.getType(), + Visited, Depth + 1, CreatedValuesCount); } else { if (!Visited.insert(FieldType.getCanonicalType()).second) return; @@ -979,7 +1184,7 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, } }; - for (const auto &[Field, FieldLoc] : Loc.children()) { + for (const FieldDecl *Field : DACtx->getModeledFields(Type)) { assert(Field != nullptr); QualType FieldType = Field->getType(); @@ -988,14 +1193,12 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, &createLocAndMaybeValue(FieldType, Visited, Depth + 1, CreatedValuesCount)); } else { + StorageLocation *FieldLoc = Loc.getChild(*Field); assert(FieldLoc != nullptr); initField(FieldType, *FieldLoc); } } - for (const auto &[FieldName, FieldLoc] : Loc.synthetic_fields()) { - assert(FieldLoc != nullptr); - QualType FieldType = FieldLoc->getType(); - + for (const auto &[FieldName, FieldType] : DACtx->getSyntheticFields(Type)) { // Synthetic fields cannot have reference type, so we don't need to deal // with this case. assert(!FieldType->isReferenceType()); @@ -1022,38 +1225,36 @@ StorageLocation &Environment::createObjectInternal(const ValueDecl *D, return createObjectInternal(D, Ty.getNonReferenceType(), nullptr); } - Value *Val = nullptr; - if (InitExpr) { - // In the (few) cases where an expression is intentionally - // "uninterpreted", `InitExpr` is not associated with a value. There are - // two ways to handle this situation: propagate the status, so that - // uninterpreted initializers result in uninterpreted variables, or - // provide a default value. We choose the latter so that later refinements - // of the variable can be used for reasoning about the surrounding code. - // For this reason, we let this case be handled by the `createValue()` - // call below. - // - // FIXME. If and when we interpret all language cases, change this to - // assert that `InitExpr` is interpreted, rather than supplying a - // default value (assuming we don't update the environment API to return - // references). - Val = getValue(*InitExpr); - - if (!Val && isa(InitExpr) && - InitExpr->getType()->isPointerType()) - Val = &getOrCreateNullPointerValue(InitExpr->getType()->getPointeeType()); - } - if (!Val) - Val = createValue(Ty); - - if (Ty->isRecordType()) - return cast(Val)->getLoc(); - StorageLocation &Loc = D ? createStorageLocation(*D) : createStorageLocation(Ty); - if (Val) - setValue(Loc, *Val); + if (Ty->isRecordType()) { + auto &RecordLoc = cast(Loc); + if (!InitExpr) + initializeFieldsWithValues(RecordLoc); + refreshRecordValue(RecordLoc, *this); + } else { + Value *Val = nullptr; + if (InitExpr) + // In the (few) cases where an expression is intentionally + // "uninterpreted", `InitExpr` is not associated with a value. There are + // two ways to handle this situation: propagate the status, so that + // uninterpreted initializers result in uninterpreted variables, or + // provide a default value. We choose the latter so that later refinements + // of the variable can be used for reasoning about the surrounding code. + // For this reason, we let this case be handled by the `createValue()` + // call below. + // + // FIXME. If and when we interpret all language cases, change this to + // assert that `InitExpr` is interpreted, rather than supplying a + // default value (assuming we don't update the environment API to return + // references). + Val = getValue(*InitExpr); + if (!Val) + Val = createValue(Ty); + if (Val) + setValue(Loc, *Val); + } return Loc; } @@ -1072,6 +1273,8 @@ bool Environment::allows(const Formula &F) const { void Environment::dump(raw_ostream &OS) const { llvm::DenseMap LocToName; + if (LocForRecordReturnVal != nullptr) + LocToName[LocForRecordReturnVal] = "(returned record)"; if (ThisPointeeLoc != nullptr) LocToName[ThisPointeeLoc] = "this"; @@ -1102,6 +1305,9 @@ void Environment::dump(raw_ostream &OS) const { if (auto Iter = LocToName.find(ReturnLoc); Iter != LocToName.end()) OS << " (" << Iter->second << ")"; OS << "\n"; + } else if (Func->getReturnType()->isRecordType() || + isa(Func)) { + OS << "LocForRecordReturnVal: " << LocForRecordReturnVal << "\n"; } else if (!Func->getReturnType()->isVoidType()) { if (ReturnVal == nullptr) OS << "ReturnVal: nullptr\n"; @@ -1122,6 +1328,22 @@ void Environment::dump() const { dump(llvm::dbgs()); } +Environment::PrValueToResultObject Environment::buildResultObjectMap( + DataflowAnalysisContext *DACtx, const FunctionDecl *FuncDecl, + RecordStorageLocation *ThisPointeeLoc, + RecordStorageLocation *LocForRecordReturnVal) { + assert(FuncDecl->doesThisDeclarationHaveABody()); + + PrValueToResultObject Map; + + ResultObjectVisitor Visitor(Map, LocForRecordReturnVal, *DACtx); + if (const auto *Ctor = dyn_cast(FuncDecl)) + Visitor.TraverseConstructorInits(Ctor, ThisPointeeLoc); + Visitor.TraverseStmt(FuncDecl->getBody()); + + return Map; +} + RecordStorageLocation *getImplicitObjectLocation(const CXXMemberCallExpr &MCE, const Environment &Env) { Expr *ImplicitObject = MCE.getImplicitObjectArgument(); @@ -1216,24 +1438,11 @@ RecordValue &refreshRecordValue(RecordStorageLocation &Loc, Environment &Env) { RecordValue &refreshRecordValue(const Expr &Expr, Environment &Env) { assert(Expr.getType()->isRecordType()); - if (Expr.isPRValue()) { - if (auto *ExistingVal = Env.get(Expr)) { - auto &NewVal = Env.create(ExistingVal->getLoc()); - Env.setValue(Expr, NewVal); - Env.setValue(NewVal.getLoc(), NewVal); - return NewVal; - } + if (Expr.isPRValue()) + refreshRecordValue(Env.getResultObjectLocation(Expr), Env); - auto &NewVal = *cast(Env.createValue(Expr.getType())); - Env.setValue(Expr, NewVal); - return NewVal; - } - - if (auto *Loc = Env.get(Expr)) { - auto &NewVal = Env.create(*Loc); - Env.setValue(*Loc, NewVal); - return NewVal; - } + if (auto *Loc = Env.get(Expr)) + refreshRecordValue(*Loc, Env); auto &NewVal = *cast(Env.createValue(Expr.getType())); Env.setStorageLocation(Expr, NewVal.getLoc()); diff --git a/clang/lib/Analysis/FlowSensitive/Transfer.cpp b/clang/lib/Analysis/FlowSensitive/Transfer.cpp index 0a2e8368d541..88a9c0eccbeb 100644 --- a/clang/lib/Analysis/FlowSensitive/Transfer.cpp +++ b/clang/lib/Analysis/FlowSensitive/Transfer.cpp @@ -460,11 +460,9 @@ public: // So make sure we have a value if we didn't propagate one above. if (S->isPRValue() && S->getType()->isRecordType()) { if (Env.getValue(*S) == nullptr) { - Value *Val = Env.createValue(S->getType()); - // We're guaranteed to always be able to create a value for record - // types. - assert(Val != nullptr); - Env.setValue(*S, *Val); + auto &Loc = Env.getResultObjectLocation(*S); + Env.initializeFieldsWithValues(Loc); + refreshRecordValue(Loc, Env); } } } @@ -472,6 +470,13 @@ public: void VisitCXXDefaultInitExpr(const CXXDefaultInitExpr *S) { const Expr *InitExpr = S->getExpr(); assert(InitExpr != nullptr); + + // If this is a prvalue of record type, the handler for `*InitExpr` (if one + // exists) will initialize the result object; there is no value to propgate + // here. + if (S->getType()->isRecordType() && S->isPRValue()) + return; + propagateValueOrStorageLocation(*InitExpr, *S, Env); } @@ -479,6 +484,17 @@ public: const CXXConstructorDecl *ConstructorDecl = S->getConstructor(); assert(ConstructorDecl != nullptr); + // `CXXConstructExpr` can have array type if default-initializing an array + // of records. We don't handle this specifically beyond potentially inlining + // the call. + if (!S->getType()->isRecordType()) { + transferInlineCall(S, ConstructorDecl); + return; + } + + RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); + Env.setValue(*S, refreshRecordValue(Loc, Env)); + if (ConstructorDecl->isCopyOrMoveConstructor()) { // It is permissible for a copy/move constructor to have additional // parameters as long as they have default arguments defined for them. @@ -491,24 +507,14 @@ public: if (ArgLoc == nullptr) return; - if (S->isElidable()) { - if (Value *Val = Env.getValue(*ArgLoc)) - Env.setValue(*S, *Val); - } else { - auto &Val = *cast(Env.createValue(S->getType())); - Env.setValue(*S, Val); - copyRecord(*ArgLoc, Val.getLoc(), Env); - } + // Even if the copy/move constructor call is elidable, we choose to copy + // the record in all cases (which isn't wrong, just potentially not + // optimal). + copyRecord(*ArgLoc, Loc, Env); return; } - // `CXXConstructExpr` can have array type if default-initializing an array - // of records, and we currently can't create values for arrays. So check if - // we've got a record type. - if (S->getType()->isRecordType()) { - auto &InitialVal = *cast(Env.createValue(S->getType())); - Env.setValue(*S, InitialVal); - } + Env.initializeFieldsWithValues(Loc, S->getType()); transferInlineCall(S, ConstructorDecl); } @@ -551,19 +557,15 @@ public: if (S->isGLValue()) { Env.setStorageLocation(*S, *LocDst); } else if (S->getType()->isRecordType()) { - // Make sure that we have a `RecordValue` for this expression so that - // `Environment::getResultObjectLocation()` is able to return a location - // for it. - if (Env.getValue(*S) == nullptr) - refreshRecordValue(*S, Env); + // Assume that the assignment returns the assigned value. + copyRecord(*LocDst, Env.getResultObjectLocation(*S), Env); } return; } - // CXXOperatorCallExpr can be prvalues. Call `VisitCallExpr`() to create - // a `RecordValue` for them so that `Environment::getResultObjectLocation()` - // can return a value. + // `CXXOperatorCallExpr` can be a prvalue. Call `VisitCallExpr`() to + // initialize the prvalue's fields with values. VisitCallExpr(S); } @@ -580,11 +582,6 @@ public: } } - void VisitCXXTemporaryObjectExpr(const CXXTemporaryObjectExpr *S) { - if (Value *Val = Env.createValue(S->getType())) - Env.setValue(*S, *Val); - } - void VisitCallExpr(const CallExpr *S) { // Of clang's builtins, only `__builtin_expect` is handled explicitly, since // others (like trap, debugtrap, and unreachable) are handled by CFG @@ -612,13 +609,14 @@ public: } else if (const FunctionDecl *F = S->getDirectCallee()) { transferInlineCall(S, F); - // If this call produces a prvalue of record type, make sure that we have - // a `RecordValue` for it. This is required so that - // `Environment::getResultObjectLocation()` is able to return a location - // for this `CallExpr`. + // If this call produces a prvalue of record type, initialize its fields + // with values. if (S->getType()->isRecordType() && S->isPRValue()) - if (Env.getValue(*S) == nullptr) - refreshRecordValue(*S, Env); + if (Env.getValue(*S) == nullptr) { + RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); + Env.initializeFieldsWithValues(Loc); + Env.setValue(*S, refreshRecordValue(Loc, Env)); + } } } @@ -666,8 +664,10 @@ public: // `getLogicOperatorSubExprValue()`. if (S->isGLValue()) Env.setStorageLocation(*S, Env.createObject(S->getType())); - else if (Value *Val = Env.createValue(S->getType())) - Env.setValue(*S, *Val); + else if (!S->getType()->isRecordType()) { + if (Value *Val = Env.createValue(S->getType())) + Env.setValue(*S, *Val); + } } void VisitInitListExpr(const InitListExpr *S) { @@ -688,71 +688,51 @@ public: return; } - llvm::DenseMap FieldLocs; - RecordInitListHelper InitListHelper(S); + RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); + Env.setValue(*S, refreshRecordValue(Loc, Env)); - for (auto [Base, Init] : InitListHelper.base_inits()) { - assert(Base->getType().getCanonicalType() == - Init->getType().getCanonicalType()); - auto *BaseVal = Env.get(*Init); - if (!BaseVal) - BaseVal = cast(Env.createValue(Init->getType())); - // Take ownership of the fields of the `RecordValue` for the base class - // and incorporate them into the "flattened" set of fields for the - // derived class. - auto Children = BaseVal->getLoc().children(); - FieldLocs.insert(Children.begin(), Children.end()); - } + // Initialization of base classes and fields of record type happens when we + // visit the nested `CXXConstructExpr` or `InitListExpr` for that base class + // or field. We therefore only need to deal with fields of non-record type + // here. - for (auto [Field, Init] : InitListHelper.field_inits()) { - assert( - // The types are same, or - Field->getType().getCanonicalType().getUnqualifiedType() == - Init->getType().getCanonicalType().getUnqualifiedType() || - // The field's type is T&, and initializer is T - (Field->getType()->isReferenceType() && - Field->getType().getCanonicalType()->getPointeeType() == - Init->getType().getCanonicalType())); - auto& Loc = Env.createObject(Field->getType(), Init); - FieldLocs.insert({Field, &Loc}); - } + RecordInitListHelper InitListHelper(S); - // In the case of a union, we don't in general have initializers for all - // of the fields. Create storage locations for the remaining fields (but - // don't associate them with values). - if (Type->isUnionType()) { - for (const FieldDecl *Field : - Env.getDataflowAnalysisContext().getModeledFields(Type)) { - if (auto [it, inserted] = FieldLocs.insert({Field, nullptr}); inserted) - it->second = &Env.createStorageLocation(Field->getType()); + for (auto [Field, Init] : InitListHelper.field_inits()) { + if (Field->getType()->isRecordType()) + continue; + if (Field->getType()->isReferenceType()) { + assert(Field->getType().getCanonicalType()->getPointeeType() == + Init->getType().getCanonicalType()); + Loc.setChild(*Field, &Env.createObject(Field->getType(), Init)); + continue; } + assert(Field->getType().getCanonicalType().getUnqualifiedType() == + Init->getType().getCanonicalType().getUnqualifiedType()); + StorageLocation *FieldLoc = Loc.getChild(*Field); + // Locations for non-reference fields must always be non-null. + assert(FieldLoc != nullptr); + Value *Val = Env.getValue(*Init); + if (Val == nullptr && isa(Init) && + Init->getType()->isPointerType()) + Val = + &Env.getOrCreateNullPointerValue(Init->getType()->getPointeeType()); + if (Val == nullptr) + Val = Env.createValue(Field->getType()); + if (Val != nullptr) + Env.setValue(*FieldLoc, *Val); } - // Check that we satisfy the invariant that a `RecordStorageLoation` - // contains exactly the set of modeled fields for that type. - // `ModeledFields` includes fields from all the bases, but only the - // modeled ones. However, if a class type is initialized with an - // `InitListExpr`, all fields in the class, including those from base - // classes, are included in the set of modeled fields. The code above - // should therefore populate exactly the modeled fields. - assert(containsSameFields( - Env.getDataflowAnalysisContext().getModeledFields(Type), FieldLocs)); - - RecordStorageLocation::SyntheticFieldMap SyntheticFieldLocs; - for (const auto &Entry : - Env.getDataflowAnalysisContext().getSyntheticFields(Type)) { - SyntheticFieldLocs.insert( - {Entry.getKey(), &Env.createObject(Entry.getValue())}); + for (const auto &[FieldName, FieldLoc] : Loc.synthetic_fields()) { + QualType FieldType = FieldLoc->getType(); + if (FieldType->isRecordType()) { + Env.initializeFieldsWithValues(*cast(FieldLoc)); + } else { + if (Value *Val = Env.createValue(FieldType)) + Env.setValue(*FieldLoc, *Val); + } } - auto &Loc = Env.getDataflowAnalysisContext().createRecordStorageLocation( - Type, std::move(FieldLocs), std::move(SyntheticFieldLocs)); - RecordValue &RecordVal = Env.create(Loc); - - Env.setValue(Loc, RecordVal); - - Env.setValue(*S, RecordVal); - // FIXME: Implement array initialization. } diff --git a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp index 595f70f819dd..1b73c5d68301 100644 --- a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp +++ b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp @@ -369,17 +369,10 @@ builtinTransferInitializer(const CFGInitializer &Elt, ParentLoc->setChild(*Member, InitExprLoc); } else if (auto *InitExprVal = Env.getValue(*InitExpr)) { assert(MemberLoc != nullptr); - if (Member->getType()->isRecordType()) { - auto *InitValStruct = cast(InitExprVal); - // FIXME: Rather than performing a copy here, we should really be - // initializing the field in place. This would require us to propagate the - // storage location of the field to the AST node that creates the - // `RecordValue`. - copyRecord(InitValStruct->getLoc(), - *cast(MemberLoc), Env); - } else { + // Record-type initializers construct themselves directly into the result + // object, so there is no need to handle them here. + if (!Member->getType()->isRecordType()) Env.setValue(*MemberLoc, *InitExprVal); - } } } diff --git a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp index 465a8e21690c..cc20623f881f 100644 --- a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp @@ -24,6 +24,7 @@ namespace { using namespace clang; using namespace dataflow; +using ::clang::dataflow::test::findValueDecl; using ::clang::dataflow::test::getFieldValue; using ::testing::Contains; using ::testing::IsNull; @@ -199,6 +200,48 @@ TEST_F(EnvironmentTest, JoinRecords) { } } +TEST_F(EnvironmentTest, DifferentReferenceLocInJoin) { + // This tests the case where the storage location for a reference-type + // variable is different for two states being joined. We used to believe this + // could not happen and therefore had an assertion disallowing this; this test + // exists to demonstrate that we can handle this condition without a failing + // assertion. See also the discussion here: + // https://discourse.llvm.org/t/70086/6 + + using namespace ast_matchers; + + std::string Code = R"cc( + void f(int &ref) {} + )cc"; + + auto Unit = + tooling::buildASTFromCodeWithArgs(Code, {"-fsyntax-only", "-std=c++11"}); + auto &Context = Unit->getASTContext(); + + ASSERT_EQ(Context.getDiagnostics().getClient()->getNumErrors(), 0U); + + const ValueDecl *Ref = findValueDecl(Context, "ref"); + + Environment Env1(DAContext); + StorageLocation &Loc1 = Env1.createStorageLocation(Context.IntTy); + Env1.setStorageLocation(*Ref, Loc1); + + Environment Env2(DAContext); + StorageLocation &Loc2 = Env2.createStorageLocation(Context.IntTy); + Env2.setStorageLocation(*Ref, Loc2); + + EXPECT_NE(&Loc1, &Loc2); + + Environment::ValueModel Model; + Environment EnvJoined = + Environment::join(Env1, Env2, Model, Environment::DiscardExprState); + + // Joining environments with different storage locations for the same + // declaration results in the declaration being removed from the joined + // environment. + EXPECT_EQ(EnvJoined.getStorageLocation(*Ref), nullptr); +} + TEST_F(EnvironmentTest, InitGlobalVarsFun) { using namespace ast_matchers; diff --git a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp index ca055a462a28..00dafb2988c6 100644 --- a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp @@ -1582,10 +1582,9 @@ TEST(TransferTest, FieldsDontHaveValuesInConstructorWithBaseClass) { [](const llvm::StringMap> &Results, ASTContext &ASTCtx) { const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - // FIXME: The field of the base class should already have been - // initialized with a value by the base constructor. This test documents - // the current buggy behavior. - EXPECT_EQ(getFieldValue(Env.getThisPointeeStorageLocation(), "BaseVal", + // The field of the base class should already have been initialized with + // a value by the base constructor. + EXPECT_NE(getFieldValue(Env.getThisPointeeStorageLocation(), "BaseVal", ASTCtx, Env), nullptr); EXPECT_EQ(getFieldValue(Env.getThisPointeeStorageLocation(), "Val", @@ -2998,8 +2997,12 @@ TEST(TransferTest, ResultObjectLocation) { TEST(TransferTest, ResultObjectLocationForDefaultArgExpr) { std::string Code = R"( - struct S {}; - void funcWithDefaultArg(S s = S()); + struct Inner {}; + struct Outer { + Inner I = {}; + }; + + void funcWithDefaultArg(Outer O = {}); void target() { funcWithDefaultArg(); // [[p]] @@ -3058,13 +3061,7 @@ TEST(TransferTest, ResultObjectLocationForDefaultInitExpr) { RecordStorageLocation &Loc = Env.getResultObjectLocation(*DefaultInit); - // FIXME: The result object location for the `CXXDefaultInitExpr` should - // be the location of the member variable being initialized, but we - // don't do this correctly yet; see also comments in - // `builtinTransferInitializer()`. - // For the time being, we just document the current erroneous behavior - // here (this should be `EXPECT_EQ` when the behavior is fixed). - EXPECT_NE(&Loc, Env.getThisPointeeStorageLocation()->getChild(*SField)); + EXPECT_EQ(&Loc, Env.getThisPointeeStorageLocation()->getChild(*SField)); }); } @@ -3101,6 +3098,79 @@ TEST(TransferTest, ResultObjectLocationForCXXOperatorCallExpr) { }); } +TEST(TransferTest, ResultObjectLocationForStdInitializerListExpr) { + std::string Code = R"( + namespace std { + template + struct initializer_list {}; + } // namespace std + + void target() { + std::initializer_list list = {1}; + // [[p]] + } + )"; + + using ast_matchers::cxxStdInitializerListExpr; + using ast_matchers::match; + using ast_matchers::selectFirst; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + auto *StdInitList = selectFirst( + "std_init_list", + match(cxxStdInitializerListExpr().bind("std_init_list"), ASTCtx)); + ASSERT_NE(StdInitList, nullptr); + + EXPECT_EQ(&Env.getResultObjectLocation(*StdInitList), + &getLocForDecl(ASTCtx, Env, "list")); + }); +} + +TEST(TransferTest, ResultObjectLocationPropagatesThroughConditionalOperator) { + std::string Code = R"( + struct A { + A(int); + }; + + void target(bool b) { + A a = b ? A(0) : A(1); + (void)0; // [[p]] + } + )"; + using ast_matchers::cxxConstructExpr; + using ast_matchers::equals; + using ast_matchers::hasArgument; + using ast_matchers::integerLiteral; + using ast_matchers::match; + using ast_matchers::selectFirst; + using ast_matchers::traverse; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + auto *ConstructExpr0 = selectFirst( + "construct", + match(cxxConstructExpr(hasArgument(0, integerLiteral(equals(0)))) + .bind("construct"), + ASTCtx)); + auto *ConstructExpr1 = selectFirst( + "construct", + match(cxxConstructExpr(hasArgument(0, integerLiteral(equals(1)))) + .bind("construct"), + ASTCtx)); + + auto &ALoc = getLocForDecl(ASTCtx, Env, "a"); + EXPECT_EQ(&Env.getResultObjectLocation(*ConstructExpr0), &ALoc); + EXPECT_EQ(&Env.getResultObjectLocation(*ConstructExpr1), &ALoc); + }); +} + TEST(TransferTest, StaticCast) { std::string Code = R"( void target(int Foo) { @@ -5886,6 +5956,38 @@ TEST(TransferTest, ContextSensitiveReturnRecord) { {BuiltinOptions{ContextSensitiveOptions{}}}); } +TEST(TransferTest, ContextSensitiveReturnSelfReferentialRecord) { + std::string Code = R"( + struct S { + S() { self = this; } + S *self; + }; + + S makeS() { + // RVO guarantees that this will be constructed directly into `MyS`. + return S(); + } + + void target() { + S MyS = makeS(); + // [[p]] + } + )"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + auto &MySLoc = getLocForDecl(ASTCtx, Env, "MyS"); + + auto *SelfVal = + cast(getFieldValue(&MySLoc, "self", ASTCtx, Env)); + EXPECT_EQ(&SelfVal->getPointeeLoc(), &MySLoc); + }, + {BuiltinOptions{ContextSensitiveOptions{}}}); +} + TEST(TransferTest, ContextSensitiveMethodLiteral) { std::string Code = R"( class MyClass { @@ -6830,50 +6932,6 @@ TEST(TransferTest, LambdaCaptureThis) { }); } -TEST(TransferTest, DifferentReferenceLocInJoin) { - // This test triggers a case where the storage location for a reference-type - // variable is different for two states being joined. We used to believe this - // could not happen and therefore had an assertion disallowing this; this test - // exists to demonstrate that we can handle this condition without a failing - // assertion. See also the discussion here: - // https://discourse.llvm.org/t/70086/6 - std::string Code = R"( - namespace std { - template struct initializer_list { - const T* begin(); - const T* end(); - }; - } - - void target(char* p, char* end) { - while (p != end) { - if (*p == ' ') { - p++; - continue; - } - - auto && range = {1, 2}; - for (auto b = range.begin(), e = range.end(); b != e; ++b) { - } - (void)0; - // [[p]] - } - } - )"; - runDataflow( - Code, - [](const llvm::StringMap> &Results, - ASTContext &ASTCtx) { - const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - - // Joining environments with different storage locations for the same - // declaration results in the declaration being removed from the joined - // environment. - const ValueDecl *VD = findValueDecl(ASTCtx, "range"); - ASSERT_EQ(Env.getStorageLocation(*VD), nullptr); - }); -} - // This test verifies correct modeling of a relational dependency that goes // through unmodeled functions (the simple `cond()` in this case). TEST(TransferTest, ConditionalRelation) { -- GitLab From b9a3551c905573df456ee52fa1051e49fa956c65 Mon Sep 17 00:00:00 2001 From: "Kevin P. Neal" Date: Wed, 10 Apr 2024 11:28:43 -0400 Subject: [PATCH 431/695] [FPEnv][BitcodeReader] Correct strictfp test. Correct a strictfp test to follow the rules documented in the LangRef: https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics This test needed the strictfp attribute added to a function definition. Test changes verified with D146845. --- llvm/unittests/Bitcode/BitReaderTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/unittests/Bitcode/BitReaderTest.cpp b/llvm/unittests/Bitcode/BitReaderTest.cpp index 3e449f905778..22cc5e749280 100644 --- a/llvm/unittests/Bitcode/BitReaderTest.cpp +++ b/llvm/unittests/Bitcode/BitReaderTest.cpp @@ -160,7 +160,7 @@ TEST(BitReaderTest, MaterializeConstrainedFPStrictFP) { LLVMContext Context; std::unique_ptr M = getLazyModuleFromAssembly( Context, Mem, - "define double @foo(double %a) {\n" + "define double @foo(double %a) strictfp {\n" " %result = call double @llvm.experimental.constrained.sqrt.f64(double " "%a, metadata !\"round.tonearest\", metadata !\"fpexcept.strict\") " "strictfp\n" -- GitLab From c1d3f39ae98535777c957aab3611d2abc97b2815 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:36:58 -0500 Subject: [PATCH 432/695] [ValueTracking] Add tests for `shufflevector` in `isKnownNonZero` --- .../Transforms/InstSimplify/known-non-zero.ll | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/llvm/test/Transforms/InstSimplify/known-non-zero.ll b/llvm/test/Transforms/InstSimplify/known-non-zero.ll index 51f80f62c2f3..9486708369b7 100644 --- a/llvm/test/Transforms/InstSimplify/known-non-zero.ll +++ b/llvm/test/Transforms/InstSimplify/known-non-zero.ll @@ -177,3 +177,135 @@ define i1 @smax_non_zero(i8 %xx, i8 %y) { %r = icmp eq i8 %v, 0 ret i1 %r } + +define <4 x i1> @shuf_nonzero_both(<4 x i8> %xx, <4 x i8> %yy) { +; CHECK-LABEL: @shuf_nonzero_both( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <4 x i8> [[YY:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + %y = add nuw <4 x i8> %yy, + + %shuf = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_both_fail(<4 x i8> %xx, <4 x i8> %yy) { +; CHECK-LABEL: @shuf_nonzero_both_fail( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw <4 x i8> [[YY:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + %y = add nuw <4 x i8> %yy, + + %shuf = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_both_fail2(<4 x i8> %xx, <4 x i8> %yy) { +; CHECK-LABEL: @shuf_nonzero_both_fail2( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add <4 x i8> [[YY:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + %y = add <4 x i8> %yy, + + %shuf = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_lhs(<4 x i8> %xx) { +; CHECK-LABEL: @shuf_nonzero_lhs( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> poison, <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + + %shuf = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_lhs2(<4 x i8> %xx) { +; CHECK-LABEL: @shuf_nonzero_lhs2( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> poison, <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + + %shuf = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_lhs2_fail(<4 x i8> %xx) { +; CHECK-LABEL: @shuf_nonzero_lhs2_fail( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> poison, <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + + %shuf = shufflevector <4 x i8> %x, <4 x i8> poison, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_rhs(<4 x i8> %xx) { +; CHECK-LABEL: @shuf_nonzero_rhs( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> poison, <4 x i8> [[X]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + + %shuf = shufflevector <4 x i8> poison, <4 x i8> %x, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_rhs2(<4 x i8> %xx) { +; CHECK-LABEL: @shuf_nonzero_rhs2( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> poison, <4 x i8> [[X]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + + %shuf = shufflevector <4 x i8> poison, <4 x i8> %x, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} + +define <4 x i1> @shuf_nonzero_rhs2_fail(<4 x i8> %xx) { +; CHECK-LABEL: @shuf_nonzero_rhs2_fail( +; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> poison, <4 x i8> [[X]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %x = add nuw <4 x i8> %xx, + + %shuf = shufflevector <4 x i8> poison, <4 x i8> %x, <4 x i32> + %r = icmp eq <4 x i8> %shuf, zeroinitializer + ret <4 x i1> %r +} -- GitLab From 87528bfefbb50ed6560b9b8482fc7c9f86ca34cd Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 15:33:55 -0500 Subject: [PATCH 433/695] [ValueTracking] Add support for `shufflevector` in `isKnownNonZero` Shuffles don't modify the data, so if all elements that end up in the destination are non-zero the result is non-zero. Closes #87702 --- llvm/lib/Analysis/ValueTracking.cpp | 15 +++++++++++ .../Transforms/InstSimplify/known-non-zero.ll | 26 ++++--------------- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 5ef1969893b4..b3029f440ca2 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2777,6 +2777,21 @@ static bool isKnownNonZeroFromOperator(const Operator *I, } } break; + case Instruction::ShuffleVector: { + auto *Shuf = dyn_cast(I); + if (!Shuf) + break; + APInt DemandedLHS, DemandedRHS; + // For undef elements, we don't know anything about the common state of + // the shuffle result. + if (!getShuffleDemandedElts(Shuf, DemandedElts, DemandedLHS, DemandedRHS)) + break; + // If demanded elements for both vecs are non-zero, the shuffle is non-zero. + return (DemandedRHS.isZero() || + isKnownNonZero(Shuf->getOperand(1), DemandedRHS, Depth, Q)) && + (DemandedLHS.isZero() || + isKnownNonZero(Shuf->getOperand(0), DemandedLHS, Depth, Q)); + } case Instruction::Freeze: return isKnownNonZero(I->getOperand(0), Depth, Q) && isGuaranteedNotToBePoison(I->getOperand(0), Q.AC, Q.CxtI, Q.DT, diff --git a/llvm/test/Transforms/InstSimplify/known-non-zero.ll b/llvm/test/Transforms/InstSimplify/known-non-zero.ll index 9486708369b7..c443dc68d0c1 100644 --- a/llvm/test/Transforms/InstSimplify/known-non-zero.ll +++ b/llvm/test/Transforms/InstSimplify/known-non-zero.ll @@ -180,11 +180,7 @@ define i1 @smax_non_zero(i8 %xx, i8 %y) { define <4 x i1> @shuf_nonzero_both(<4 x i8> %xx, <4 x i8> %yy) { ; CHECK-LABEL: @shuf_nonzero_both( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[Y:%.*]] = add nuw <4 x i8> [[YY:%.*]], -; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[Y]], <4 x i32> -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer -; CHECK-NEXT: ret <4 x i1> [[R]] +; CHECK-NEXT: ret <4 x i1> zeroinitializer ; %x = add nuw <4 x i8> %xx, %y = add nuw <4 x i8> %yy, @@ -228,10 +224,7 @@ define <4 x i1> @shuf_nonzero_both_fail2(<4 x i8> %xx, <4 x i8> %yy) { define <4 x i1> @shuf_nonzero_lhs(<4 x i8> %xx) { ; CHECK-LABEL: @shuf_nonzero_lhs( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> poison, <4 x i32> -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer -; CHECK-NEXT: ret <4 x i1> [[R]] +; CHECK-NEXT: ret <4 x i1> zeroinitializer ; %x = add nuw <4 x i8> %xx, @@ -242,10 +235,7 @@ define <4 x i1> @shuf_nonzero_lhs(<4 x i8> %xx) { define <4 x i1> @shuf_nonzero_lhs2(<4 x i8> %xx) { ; CHECK-LABEL: @shuf_nonzero_lhs2( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> poison, <4 x i32> -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer -; CHECK-NEXT: ret <4 x i1> [[R]] +; CHECK-NEXT: ret <4 x i1> zeroinitializer ; %x = add nuw <4 x i8> %xx, @@ -270,10 +260,7 @@ define <4 x i1> @shuf_nonzero_lhs2_fail(<4 x i8> %xx) { define <4 x i1> @shuf_nonzero_rhs(<4 x i8> %xx) { ; CHECK-LABEL: @shuf_nonzero_rhs( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> poison, <4 x i8> [[X]], <4 x i32> -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer -; CHECK-NEXT: ret <4 x i1> [[R]] +; CHECK-NEXT: ret <4 x i1> zeroinitializer ; %x = add nuw <4 x i8> %xx, @@ -284,10 +271,7 @@ define <4 x i1> @shuf_nonzero_rhs(<4 x i8> %xx) { define <4 x i1> @shuf_nonzero_rhs2(<4 x i8> %xx) { ; CHECK-LABEL: @shuf_nonzero_rhs2( -; CHECK-NEXT: [[X:%.*]] = add nuw <4 x i8> [[XX:%.*]], -; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> poison, <4 x i8> [[X]], <4 x i32> -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[SHUF]], zeroinitializer -; CHECK-NEXT: ret <4 x i1> [[R]] +; CHECK-NEXT: ret <4 x i1> zeroinitializer ; %x = add nuw <4 x i8> %xx, -- GitLab From 8a28b9b8ec1686426a4b43c8431570eaa1da77d9 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:37:14 -0500 Subject: [PATCH 434/695] [ValueTracking] Add tests for `insertelement` in `isKnownNonZero`; NFC --- .../Transforms/InstSimplify/known-non-zero.ll | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/llvm/test/Transforms/InstSimplify/known-non-zero.ll b/llvm/test/Transforms/InstSimplify/known-non-zero.ll index c443dc68d0c1..1417e86ee678 100644 --- a/llvm/test/Transforms/InstSimplify/known-non-zero.ll +++ b/llvm/test/Transforms/InstSimplify/known-non-zero.ll @@ -293,3 +293,99 @@ define <4 x i1> @shuf_nonzero_rhs2_fail(<4 x i8> %xx) { %r = icmp eq <4 x i8> %shuf, zeroinitializer ret <4 x i1> %r } + +define <2 x i1> @insert_nonzero0(<2 x i8> %xx, i8 %yy) { +; CHECK-LABEL: @insert_nonzero0( +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 1 +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %x = add nuw <2 x i8> %xx, + %y = add nuw i8 %yy, 1 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 1 + %r = icmp eq <2 x i8> %ins, zeroinitializer + ret <2 x i1> %r +} + +define <2 x i1> @insert_nonzero1(<2 x i8> %xx, i8 %yy) { +; CHECK-LABEL: @insert_nonzero1( +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 0 +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %x = add nuw <2 x i8> %xx, + %y = add nuw i8 %yy, 1 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 0 + %r = icmp eq <2 x i8> %ins, zeroinitializer + ret <2 x i1> %r +} + +define <2 x i1> @insert_nonzero_fail(<2 x i8> %xx, i8 %yy) { +; CHECK-LABEL: @insert_nonzero_fail( +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 0 +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %x = add nuw <2 x i8> %xx, + %y = add nuw i8 %yy, 1 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 0 + %r = icmp eq <2 x i8> %ins, zeroinitializer + ret <2 x i1> %r +} + +define <2 x i1> @insert_nonzero_fail2(<2 x i8> %xx, i8 %yy) { +; CHECK-LABEL: @insert_nonzero_fail2( +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 0 +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %x = add nuw <2 x i8> %xx, + %y = add i8 %yy, 1 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 0 + %r = icmp eq <2 x i8> %ins, zeroinitializer + ret <2 x i1> %r +} + +define <2 x i1> @insert_nonzero_any_idx(<2 x i8> %xx, i8 %yy, i32 %idx) { +; CHECK-LABEL: @insert_nonzero_any_idx( +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %x = add nuw <2 x i8> %xx, + %y = add nuw i8 %yy, 1 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 %idx + %r = icmp eq <2 x i8> %ins, zeroinitializer + ret <2 x i1> %r +} + +define <2 x i1> @insert_nonzero_any_idx_fail(<2 x i8> %xx, i8 %yy, i32 %idx) { +; CHECK-LABEL: @insert_nonzero_any_idx_fail( +; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %x = add nuw <2 x i8> %xx, + %y = add nuw i8 %yy, 1 + + %ins = insertelement <2 x i8> %x, i8 %y, i32 %idx + %r = icmp eq <2 x i8> %ins, zeroinitializer + ret <2 x i1> %r +} -- GitLab From 9c545a14c09051b011358854655c1f466d656e79 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 15:34:28 -0500 Subject: [PATCH 435/695] [ValueTracking] Add support for `insertelement` in `isKnownNonZero` Inserts don't modify the data, so if all elements that end up in the destination are non-zero the result is non-zero. Closes #87703 --- llvm/lib/Analysis/ValueTracking.cpp | 23 +++++++++++++++++++ .../Transforms/InstSimplify/known-non-zero.ll | 18 +++------------ 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index b3029f440ca2..9f16eaf9e099 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2763,6 +2763,29 @@ static bool isKnownNonZeroFromOperator(const Operator *I, return isKnownNonZero(U.get(), DemandedElts, NewDepth, RecQ); }); } + case Instruction::InsertElement: { + if (isa(I->getType())) + break; + + const Value *Vec = I->getOperand(0); + const Value *Elt = I->getOperand(1); + auto *CIdx = dyn_cast(I->getOperand(2)); + + unsigned NumElts = DemandedElts.getBitWidth(); + APInt DemandedVecElts = DemandedElts; + bool SkipElt = false; + // If we know the index we are inserting too, clear it from Vec check. + if (CIdx && CIdx->getValue().ult(NumElts)) { + DemandedVecElts.clearBit(CIdx->getZExtValue()); + SkipElt = !DemandedElts[CIdx->getZExtValue()]; + } + + // Result is zero if Elt is non-zero and rest of the demanded elts in Vec + // are non-zero. + return (SkipElt || isKnownNonZero(Elt, Depth, Q)) && + (DemandedVecElts.isZero() || + isKnownNonZero(Vec, DemandedVecElts, Depth, Q)); + } case Instruction::ExtractElement: if (const auto *EEI = dyn_cast(I)) { const Value *Vec = EEI->getVectorOperand(); diff --git a/llvm/test/Transforms/InstSimplify/known-non-zero.ll b/llvm/test/Transforms/InstSimplify/known-non-zero.ll index 1417e86ee678..d9b8f5eed323 100644 --- a/llvm/test/Transforms/InstSimplify/known-non-zero.ll +++ b/llvm/test/Transforms/InstSimplify/known-non-zero.ll @@ -296,11 +296,7 @@ define <4 x i1> @shuf_nonzero_rhs2_fail(<4 x i8> %xx) { define <2 x i1> @insert_nonzero0(<2 x i8> %xx, i8 %yy) { ; CHECK-LABEL: @insert_nonzero0( -; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], -; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 -; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 1 -; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[R]] +; CHECK-NEXT: ret <2 x i1> zeroinitializer ; %x = add nuw <2 x i8> %xx, %y = add nuw i8 %yy, 1 @@ -312,11 +308,7 @@ define <2 x i1> @insert_nonzero0(<2 x i8> %xx, i8 %yy) { define <2 x i1> @insert_nonzero1(<2 x i8> %xx, i8 %yy) { ; CHECK-LABEL: @insert_nonzero1( -; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], -; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 -; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 0 -; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[R]] +; CHECK-NEXT: ret <2 x i1> zeroinitializer ; %x = add nuw <2 x i8> %xx, %y = add nuw i8 %yy, 1 @@ -360,11 +352,7 @@ define <2 x i1> @insert_nonzero_fail2(<2 x i8> %xx, i8 %yy) { define <2 x i1> @insert_nonzero_any_idx(<2 x i8> %xx, i8 %yy, i32 %idx) { ; CHECK-LABEL: @insert_nonzero_any_idx( -; CHECK-NEXT: [[X:%.*]] = add nuw <2 x i8> [[XX:%.*]], -; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 -; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> [[X]], i8 [[Y]], i32 [[IDX:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[INS]], zeroinitializer -; CHECK-NEXT: ret <2 x i1> [[R]] +; CHECK-NEXT: ret <2 x i1> zeroinitializer ; %x = add nuw <2 x i8> %xx, %y = add nuw i8 %yy, 1 -- GitLab From 195d278d502308655edb1e9ff1c6f0c9256d0d15 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:41:47 -0500 Subject: [PATCH 436/695] [ValueTracking] Add tests for `xor`/`disjoint or` in `getInvertibleOperands`; NFC --- llvm/test/Transforms/InstSimplify/icmp.ll | 94 ++++++++++++++++++++++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/llvm/test/Transforms/InstSimplify/icmp.ll b/llvm/test/Transforms/InstSimplify/icmp.ll index 3109768bdfe0..a66f7cb879ef 100644 --- a/llvm/test/Transforms/InstSimplify/icmp.ll +++ b/llvm/test/Transforms/InstSimplify/icmp.ll @@ -270,7 +270,7 @@ define i1 @load_ptr(ptr %p) { define i1 @load_ptr_null_valid(ptr %p) null_pointer_is_valid { ; CHECK-LABEL: @load_ptr_null_valid( -; CHECK-NEXT: [[LOAD_P:%.*]] = load ptr, ptr [[P:%.*]], align 8, !dereferenceable !0 +; CHECK-NEXT: [[LOAD_P:%.*]] = load ptr, ptr [[P:%.*]], align 8, !dereferenceable [[META0:![0-9]+]] ; CHECK-NEXT: [[R:%.*]] = icmp ne ptr [[LOAD_P]], null ; CHECK-NEXT: ret i1 [[R]] ; @@ -278,3 +278,95 @@ define i1 @load_ptr_null_valid(ptr %p) null_pointer_is_valid { %r = icmp ne ptr %load_p, null ret i1 %r } + +define i1 @non_eq_disjoint_or_common_op(i8 %x, i8 %y, i8 %ww, i8 %a) { +; CHECK-LABEL: @non_eq_disjoint_or_common_op( +; CHECK-NEXT: [[W:%.*]] = add nuw i8 [[WW:%.*]], 1 +; CHECK-NEXT: [[Z:%.*]] = add i8 [[Y:%.*]], [[W]] +; CHECK-NEXT: [[XY:%.*]] = or disjoint i8 [[X:%.*]], [[Y]] +; CHECK-NEXT: [[XZ:%.*]] = or disjoint i8 [[X]], [[Z]] +; CHECK-NEXT: [[AXY:%.*]] = add i8 [[A:%.*]], [[XY]] +; CHECK-NEXT: [[AXZ:%.*]] = add i8 [[A]], [[XZ]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AXY]], [[AXZ]] +; CHECK-NEXT: ret i1 [[R]] +; + %w = add nuw i8 %ww, 1 + %z = add i8 %y, %w + + %xy = or disjoint i8 %x, %y + %xz = or disjoint i8 %x, %z + + %axy = add i8 %a, %xy + %axz = add i8 %a, %xz + %r = icmp eq i8 %axy, %axz + ret i1 %r +} + +define i1 @non_eq_disjoint_or_common_op_fail(i8 %x, i8 %y, i8 %ww, i8 %a) { +; CHECK-LABEL: @non_eq_disjoint_or_common_op_fail( +; CHECK-NEXT: [[W:%.*]] = add nuw i8 [[WW:%.*]], 1 +; CHECK-NEXT: [[Z:%.*]] = add i8 [[Y:%.*]], [[W]] +; CHECK-NEXT: [[XY:%.*]] = or i8 [[X:%.*]], [[Y]] +; CHECK-NEXT: [[XZ:%.*]] = or disjoint i8 [[X]], [[Z]] +; CHECK-NEXT: [[AXY:%.*]] = add i8 [[A:%.*]], [[XY]] +; CHECK-NEXT: [[AXZ:%.*]] = add i8 [[A]], [[XZ]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AXY]], [[AXZ]] +; CHECK-NEXT: ret i1 [[R]] +; + %w = add nuw i8 %ww, 1 + %z = add i8 %y, %w + + %xy = or i8 %x, %y + %xz = or disjoint i8 %x, %z + + %axy = add i8 %a, %xy + %axz = add i8 %a, %xz + %r = icmp eq i8 %axy, %axz + ret i1 %r +} + +define i1 @non_eq_xor_common_op(i8 %x, i8 %y, i8 %ww, i8 %a) { +; CHECK-LABEL: @non_eq_xor_common_op( +; CHECK-NEXT: [[W:%.*]] = add nuw i8 [[WW:%.*]], 1 +; CHECK-NEXT: [[Z:%.*]] = add i8 [[Y:%.*]], [[W]] +; CHECK-NEXT: [[XY:%.*]] = xor i8 [[Y]], [[X:%.*]] +; CHECK-NEXT: [[XZ:%.*]] = xor i8 [[X]], [[Z]] +; CHECK-NEXT: [[AXY:%.*]] = add i8 [[A:%.*]], [[XY]] +; CHECK-NEXT: [[AXZ:%.*]] = add i8 [[A]], [[XZ]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AXY]], [[AXZ]] +; CHECK-NEXT: ret i1 [[R]] +; + %w = add nuw i8 %ww, 1 + %z = add i8 %y, %w + + %xy = xor i8 %y, %x + %xz = xor i8 %x, %z + + %axy = add i8 %a, %xy + %axz = add i8 %a, %xz + %r = icmp eq i8 %axy, %axz + ret i1 %r +} + +define i1 @non_eq_xor_common_op_fail(i8 %x, i8 %y, i8 %ww, i8 %a) { +; CHECK-LABEL: @non_eq_xor_common_op_fail( +; CHECK-NEXT: [[W:%.*]] = add nsw i8 [[WW:%.*]], 1 +; CHECK-NEXT: [[Z:%.*]] = add i8 [[Y:%.*]], [[W]] +; CHECK-NEXT: [[XY:%.*]] = xor i8 [[Y]], [[X:%.*]] +; CHECK-NEXT: [[XZ:%.*]] = xor i8 [[X]], [[Z]] +; CHECK-NEXT: [[AXY:%.*]] = add i8 [[A:%.*]], [[XY]] +; CHECK-NEXT: [[AXZ:%.*]] = add i8 [[A]], [[XZ]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AXY]], [[AXZ]] +; CHECK-NEXT: ret i1 [[R]] +; + %w = add nsw i8 %ww, 1 + %z = add i8 %y, %w + + %xy = xor i8 %y, %x + %xz = xor i8 %x, %z + + %axy = add i8 %a, %xy + %axz = add i8 %a, %xz + %r = icmp eq i8 %axy, %axz + ret i1 %r +} -- GitLab From 0c57a2e4b4e5a6e5dda78a313fc8d8e3c91797f5 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 17:40:03 -0500 Subject: [PATCH 437/695] [ValueTracking] Add support for `xor`/`disjoint or` in `getInvertibleOperands` This strengthens our `isKnownNonEqual` logic with some fairly trivial cases. Proofs: https://alive2.llvm.org/ce/z/4pxRTj Closes #87705 --- llvm/lib/Analysis/ValueTracking.cpp | 15 ++++++++++++++- llvm/test/Transforms/InstSimplify/icmp.ll | 18 ++---------------- 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 9f16eaf9e099..f3ea73b2f0ec 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -3106,7 +3106,20 @@ getInvertibleOperands(const Operator *Op1, switch (Op1->getOpcode()) { default: break; - case Instruction::Add: + case Instruction::Or: + if (!cast(Op1)->isDisjoint() || + !cast(Op2)->isDisjoint()) + break; + [[fallthrough]]; + case Instruction::Xor: + case Instruction::Add: { + Value *Other; + if (match(Op2, m_c_BinOp(m_Specific(Op1->getOperand(0)), m_Value(Other)))) + return std::make_pair(Op1->getOperand(1), Other); + if (match(Op2, m_c_BinOp(m_Specific(Op1->getOperand(1)), m_Value(Other)))) + return std::make_pair(Op1->getOperand(0), Other); + break; + } case Instruction::Sub: if (Op1->getOperand(0) == Op2->getOperand(0)) return getOperands(1); diff --git a/llvm/test/Transforms/InstSimplify/icmp.ll b/llvm/test/Transforms/InstSimplify/icmp.ll index a66f7cb879ef..d17990981154 100644 --- a/llvm/test/Transforms/InstSimplify/icmp.ll +++ b/llvm/test/Transforms/InstSimplify/icmp.ll @@ -281,14 +281,7 @@ define i1 @load_ptr_null_valid(ptr %p) null_pointer_is_valid { define i1 @non_eq_disjoint_or_common_op(i8 %x, i8 %y, i8 %ww, i8 %a) { ; CHECK-LABEL: @non_eq_disjoint_or_common_op( -; CHECK-NEXT: [[W:%.*]] = add nuw i8 [[WW:%.*]], 1 -; CHECK-NEXT: [[Z:%.*]] = add i8 [[Y:%.*]], [[W]] -; CHECK-NEXT: [[XY:%.*]] = or disjoint i8 [[X:%.*]], [[Y]] -; CHECK-NEXT: [[XZ:%.*]] = or disjoint i8 [[X]], [[Z]] -; CHECK-NEXT: [[AXY:%.*]] = add i8 [[A:%.*]], [[XY]] -; CHECK-NEXT: [[AXZ:%.*]] = add i8 [[A]], [[XZ]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AXY]], [[AXZ]] -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %w = add nuw i8 %ww, 1 %z = add i8 %y, %w @@ -327,14 +320,7 @@ define i1 @non_eq_disjoint_or_common_op_fail(i8 %x, i8 %y, i8 %ww, i8 %a) { define i1 @non_eq_xor_common_op(i8 %x, i8 %y, i8 %ww, i8 %a) { ; CHECK-LABEL: @non_eq_xor_common_op( -; CHECK-NEXT: [[W:%.*]] = add nuw i8 [[WW:%.*]], 1 -; CHECK-NEXT: [[Z:%.*]] = add i8 [[Y:%.*]], [[W]] -; CHECK-NEXT: [[XY:%.*]] = xor i8 [[Y]], [[X:%.*]] -; CHECK-NEXT: [[XZ:%.*]] = xor i8 [[X]], [[Z]] -; CHECK-NEXT: [[AXY:%.*]] = add i8 [[A:%.*]], [[XY]] -; CHECK-NEXT: [[AXZ:%.*]] = add i8 [[A]], [[XZ]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AXY]], [[AXZ]] -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %w = add nuw i8 %ww, 1 %z = add i8 %y, %w -- GitLab From 2646790155f73d6cfb28ec0ee472056740e4658e Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 21:41:53 -0500 Subject: [PATCH 438/695] [ValueTracking] Add tests for `xor`/`disjoint or` in `isKnownNonZero`; NFC --- llvm/test/Transforms/InstSimplify/icmp.ll | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/llvm/test/Transforms/InstSimplify/icmp.ll b/llvm/test/Transforms/InstSimplify/icmp.ll index d17990981154..530dc16144eb 100644 --- a/llvm/test/Transforms/InstSimplify/icmp.ll +++ b/llvm/test/Transforms/InstSimplify/icmp.ll @@ -356,3 +356,71 @@ define i1 @non_eq_xor_common_op_fail(i8 %x, i8 %y, i8 %ww, i8 %a) { %r = icmp eq i8 %axy, %axz ret i1 %r } + +define i1 @non_eq_disjoint_or(i8 %x, i8 %yy, i8 %w) { +; CHECK-LABEL: @non_eq_disjoint_or( +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[LHS:%.*]] = add i8 [[X:%.*]], [[W:%.*]] +; CHECK-NEXT: [[VAL:%.*]] = or disjoint i8 [[Y]], [[W]] +; CHECK-NEXT: [[RHS:%.*]] = add i8 [[X]], [[VAL]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[LHS]], [[RHS]] +; CHECK-NEXT: ret i1 [[R]] +; + %y = add nuw i8 %yy, 1 + %lhs = add i8 %x, %w + %val = or disjoint i8 %y, %w + %rhs = add i8 %x, %val + %r = icmp eq i8 %lhs, %rhs + ret i1 %r +} + +define i1 @non_eq_or_fail(i8 %x, i8 %yy, i8 %w) { +; CHECK-LABEL: @non_eq_or_fail( +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[LHS:%.*]] = add i8 [[X:%.*]], [[W:%.*]] +; CHECK-NEXT: [[VAL:%.*]] = or i8 [[Y]], [[W]] +; CHECK-NEXT: [[RHS:%.*]] = add i8 [[X]], [[VAL]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[LHS]], [[RHS]] +; CHECK-NEXT: ret i1 [[R]] +; + %y = add nuw i8 %yy, 1 + %lhs = add i8 %x, %w + %val = or i8 %y, %w + %rhs = add i8 %x, %val + %r = icmp eq i8 %lhs, %rhs + ret i1 %r +} + +define i1 @non_eq_xor(i8 %x, i8 %yy, i8 %w) { +; CHECK-LABEL: @non_eq_xor( +; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[LHS:%.*]] = add i8 [[X:%.*]], [[W:%.*]] +; CHECK-NEXT: [[VAL:%.*]] = xor i8 [[Y]], [[W]] +; CHECK-NEXT: [[RHS:%.*]] = add i8 [[X]], [[VAL]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[LHS]], [[RHS]] +; CHECK-NEXT: ret i1 [[R]] +; + %y = add nuw i8 %yy, 1 + %lhs = add i8 %x, %w + %val = xor i8 %y, %w + %rhs = add i8 %x, %val + %r = icmp eq i8 %lhs, %rhs + ret i1 %r +} + +define i1 @non_eq_xor_fail(i8 %x, i8 %yy, i8 %w) { +; CHECK-LABEL: @non_eq_xor_fail( +; CHECK-NEXT: [[Y:%.*]] = add nsw i8 [[YY:%.*]], 1 +; CHECK-NEXT: [[LHS:%.*]] = add i8 [[X:%.*]], [[W:%.*]] +; CHECK-NEXT: [[VAL:%.*]] = xor i8 [[Y]], [[W]] +; CHECK-NEXT: [[RHS:%.*]] = add i8 [[X]], [[VAL]] +; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[LHS]], [[RHS]] +; CHECK-NEXT: ret i1 [[R]] +; + %y = add nsw i8 %yy, 1 + %lhs = add i8 %x, %w + %val = xor i8 %y, %w + %rhs = add i8 %x, %val + %r = icmp eq i8 %lhs, %rhs + ret i1 %r +} -- GitLab From 81cdd35c0c8db22bfdd1f06cb2118d17fd99fc07 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Wed, 3 Apr 2024 17:41:45 -0500 Subject: [PATCH 439/695] [ValueTracking] Add support for `xor`/`disjoint or` in `isKnownNonZero` Handles cases like `X ^ Y == X` / `X disjoint| Y == X`. Both of these cases have identical logic to the existing `add` case, so just converting the `add` code to a more general helper. Proofs: https://alive2.llvm.org/ce/z/Htm7pe Closes #87706 --- llvm/lib/Analysis/ValueTracking.cpp | 40 +++++++++++++++-------- llvm/test/Transforms/InstSimplify/icmp.ll | 14 ++------ 2 files changed, 29 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index f3ea73b2f0ec..3a10de72a275 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -3207,20 +3207,33 @@ getInvertibleOperands(const Operator *Op1, return std::nullopt; } -/// Return true if V2 == V1 + X, where X is known non-zero. -static bool isAddOfNonZero(const Value *V1, const Value *V2, unsigned Depth, - const SimplifyQuery &Q) { +/// Return true if V1 == (binop V2, X), where X is known non-zero. +/// Only handle a small subset of binops where (binop V2, X) with non-zero X +/// implies V2 != V1. +static bool isModifyingBinopOfNonZero(const Value *V1, const Value *V2, + unsigned Depth, const SimplifyQuery &Q) { const BinaryOperator *BO = dyn_cast(V1); - if (!BO || BO->getOpcode() != Instruction::Add) + if (!BO) return false; - Value *Op = nullptr; - if (V2 == BO->getOperand(0)) - Op = BO->getOperand(1); - else if (V2 == BO->getOperand(1)) - Op = BO->getOperand(0); - else - return false; - return isKnownNonZero(Op, Depth + 1, Q); + switch (BO->getOpcode()) { + default: + break; + case Instruction::Or: + if (!cast(V1)->isDisjoint()) + break; + [[fallthrough]]; + case Instruction::Xor: + case Instruction::Add: + Value *Op = nullptr; + if (V2 == BO->getOperand(0)) + Op = BO->getOperand(1); + else if (V2 == BO->getOperand(1)) + Op = BO->getOperand(0); + else + return false; + return isKnownNonZero(Op, Depth + 1, Q); + } + return false; } /// Return true if V2 == V1 * C, where V1 is known non-zero, C is not 0/1 and @@ -3380,7 +3393,8 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2, unsigned Depth, }; } - if (isAddOfNonZero(V1, V2, Depth, Q) || isAddOfNonZero(V2, V1, Depth, Q)) + if (isModifyingBinopOfNonZero(V1, V2, Depth, Q) || + isModifyingBinopOfNonZero(V2, V1, Depth, Q)) return true; if (isNonEqualMul(V1, V2, Depth, Q) || isNonEqualMul(V2, V1, Depth, Q)) diff --git a/llvm/test/Transforms/InstSimplify/icmp.ll b/llvm/test/Transforms/InstSimplify/icmp.ll index 530dc16144eb..c94922197096 100644 --- a/llvm/test/Transforms/InstSimplify/icmp.ll +++ b/llvm/test/Transforms/InstSimplify/icmp.ll @@ -359,12 +359,7 @@ define i1 @non_eq_xor_common_op_fail(i8 %x, i8 %y, i8 %ww, i8 %a) { define i1 @non_eq_disjoint_or(i8 %x, i8 %yy, i8 %w) { ; CHECK-LABEL: @non_eq_disjoint_or( -; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 -; CHECK-NEXT: [[LHS:%.*]] = add i8 [[X:%.*]], [[W:%.*]] -; CHECK-NEXT: [[VAL:%.*]] = or disjoint i8 [[Y]], [[W]] -; CHECK-NEXT: [[RHS:%.*]] = add i8 [[X]], [[VAL]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[LHS]], [[RHS]] -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %y = add nuw i8 %yy, 1 %lhs = add i8 %x, %w @@ -393,12 +388,7 @@ define i1 @non_eq_or_fail(i8 %x, i8 %yy, i8 %w) { define i1 @non_eq_xor(i8 %x, i8 %yy, i8 %w) { ; CHECK-LABEL: @non_eq_xor( -; CHECK-NEXT: [[Y:%.*]] = add nuw i8 [[YY:%.*]], 1 -; CHECK-NEXT: [[LHS:%.*]] = add i8 [[X:%.*]], [[W:%.*]] -; CHECK-NEXT: [[VAL:%.*]] = xor i8 [[Y]], [[W]] -; CHECK-NEXT: [[RHS:%.*]] = add i8 [[X]], [[VAL]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[LHS]], [[RHS]] -; CHECK-NEXT: ret i1 [[R]] +; CHECK-NEXT: ret i1 false ; %y = add nuw i8 %yy, 1 %lhs = add i8 %x, %w -- GitLab From 2b00a73f62605fcaeaedd358ba8b55fad06571aa Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Wed, 10 Apr 2024 14:33:56 -0400 Subject: [PATCH 440/695] [SLP]Buildvector for alternate instructions with non-profitable gather operands. If the operands of the potentially alternate node are going to produce buildvector sequences, which result in more instructions, than the original code, then suhinstructions should be vectorized as alternate node, better to end up with the buildvector node. Left column - experimental, Right - reference. Metric: size..text Program size..text results results0 diff test-suite :: SingleSource/Benchmarks/Adobe-C++/loop_unroll.test 413680.00 416272.00 0.6% test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 12351788.00 12354844.00 0.0% test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 664901.00 664949.00 0.0% test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 664901.00 664949.00 0.0% test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test 1171371.00 1171355.00 -0.0% test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 1036396.00 1036284.00 -0.0% test-suite :: MultiSource/Benchmarks/MiBench/consumer-jpeg/consumer-jpeg.test 111280.00 111248.00 -0.0% test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 1392113.00 1391361.00 -0.1% test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 1392113.00 1391361.00 -0.1% test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test 281676.00 281452.00 -0.1% test-suite :: MultiSource/Benchmarks/VersaBench/ecbdes/ecbdes.test 3025.00 3019.00 -0.2% test-suite :: MultiSource/Benchmarks/Prolangs-C/plot2fig/plot2fig.test 6351.00 6335.00 -0.3% Metric: SLP.NumVectorInstructions Program SLP.NumVectorInstructions results results0 diff test-suite :: MultiSource/Benchmarks/VersaBench/ecbdes/ecbdes.test 15.00 16.00 6.7% test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 1703.00 1707.00 0.2% test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 1703.00 1707.00 0.2% test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 26241.00 26239.00 -0.0% test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 11761.00 11754.00 -0.1% test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test 824.00 822.00 -0.2% test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 5668.00 5654.00 -0.2% test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 5668.00 5654.00 -0.2% test-suite :: External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r.test 792.00 790.00 -0.3% test-suite :: External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s.test 792.00 790.00 -0.3% test-suite :: MultiSource/Benchmarks/FreeBench/pifft/pifft.test 1389.00 1384.00 -0.4% test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 596.00 590.00 -1.0% test-suite :: MultiSource/Benchmarks/Prolangs-C/plot2fig/plot2fig.test 6.00 5.00 -16.7% Metric: exec_time Program exec_time results results0 diff test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 99.14 100.00 0.9% Other changes are not significant (less than 0.1% percent with exectime less 5 secs). SingleSource/Benchmarks/Adobe-C++/loop_unroll - same small patterns remain scalar, smaller code. External/SPEC/CFP2017rate/526.blender_r/526.blender_r - many small changes, some extra stores gets vectorized. External/SPEC/CINT2017speed/625.x264_s/625.x264_s External/SPEC/CINT2017rate/525.x264_r/525.x264_r x264 has one change in a loop body, in function ssim_end4, some code remain scalar, resulting in less code size. External/SPEC/CFP2017rate/511.povray_r/511.povray_r - some extra code gets vectorized, looks like some other patterns were matched. MultiSource/Benchmarks/7zip/7zip-benchmark - extra stores were vectorized (looks like the graphs become profitable) MultiSource/Benchmarks/MiBench/consumer-jpeg/consumer-jpeg - small changes in vectorized code (some small part remain scalar). External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s Many changes cause by the fact that the code of one function becomes smaller (onvertLCHabToRGB) and this functions gets inlined after that. MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc - some small changes here and there, some extra code is vectorized, some remain scalar (2 x vectors) MultiSource/Benchmarks/VersaBench/ecbdes/ecbdes - emits 2 scalars + 2 insertelems instead of insert, broadcast, alt code (3 instructions, total 5 insts) MultiSource/Benchmarks/Prolangs-C/plot2fig/plot2fig - small graph becomes profitable and gets vectorized. External/SPEC/CINT2017rate/502.gcc_r/502.gcc_r External/SPEC/CINT2017speed/602.gcc_s/602.gcc_s Some small graph becomes profitable and gets vectorized. MultiSource/Benchmarks/FreeBench/pifft/pifft - no changes in final code. Reviewers: RKSimon, dtcxzyw Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/84978 --- .../Transforms/Vectorize/SLPVectorizer.cpp | 128 ++++++++++++++++++ .../AArch64/extractelements-to-shuffle.ll | 40 +++--- .../X86/ext-int-reduced-not-operand.ll | 9 +- .../X86/gather-move-out-of-loop.ll | 10 +- ...gathered-delayed-nodes-with-reused-user.ll | 18 ++- .../non-scheduled-inst-reused-as-last-inst.ll | 12 +- .../X86/reorder_with_external_users.ll | 16 +-- .../SLPVectorizer/alternate-non-profitable.ll | 36 +++-- 8 files changed, 192 insertions(+), 77 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 6b758f63a796..4ac719af6029 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -2995,6 +2995,15 @@ private: return ScalarToTreeEntry.lookup(V); } + /// Check that the operand node of alternate node does not generate + /// buildvector sequence. If it is, then probably not worth it to build + /// alternate shuffle, if number of buildvector operands + alternate + /// instruction > than the number of buildvector instructions. + /// \param S the instructions state of the analyzed values. + /// \param VL list of the instructions with alternate opcodes. + bool areAltOperandsProfitable(const InstructionsState &S, + ArrayRef VL) const; + /// Checks if the specified list of the instructions/values can be vectorized /// and fills required data before actual scheduling of the instructions. TreeEntry::EntryState getScalarsVectorizationState( @@ -5777,6 +5786,117 @@ static bool isAlternateInstruction(const Instruction *I, const Instruction *AltOp, const TargetLibraryInfo &TLI); +bool BoUpSLP::areAltOperandsProfitable(const InstructionsState &S, + ArrayRef VL) const { + unsigned Opcode0 = S.getOpcode(); + unsigned Opcode1 = S.getAltOpcode(); + // The opcode mask selects between the two opcodes. + SmallBitVector OpcodeMask(VL.size(), false); + for (unsigned Lane : seq(0, VL.size())) + if (cast(VL[Lane])->getOpcode() == Opcode1) + OpcodeMask.set(Lane); + // If this pattern is supported by the target then consider it profitable. + if (TTI->isLegalAltInstr(FixedVectorType::get(S.MainOp->getType(), VL.size()), + Opcode0, Opcode1, OpcodeMask)) + return true; + SmallVector Operands; + for (unsigned I : seq(0, S.MainOp->getNumOperands())) { + Operands.emplace_back(); + // Prepare the operand vector. + for (Value *V : VL) + Operands.back().push_back(cast(V)->getOperand(I)); + } + if (Operands.size() == 2) { + // Try find best operands candidates. + for (unsigned I : seq(0, VL.size() - 1)) { + SmallVector> Candidates(3); + Candidates[0] = std::make_pair(Operands[0][I], Operands[0][I + 1]); + Candidates[1] = std::make_pair(Operands[0][I], Operands[1][I + 1]); + Candidates[2] = std::make_pair(Operands[1][I], Operands[0][I + 1]); + std::optional Res = findBestRootPair(Candidates); + switch (Res.value_or(0)) { + case 0: + break; + case 1: + std::swap(Operands[0][I + 1], Operands[1][I + 1]); + break; + case 2: + std::swap(Operands[0][I], Operands[1][I]); + break; + default: + llvm_unreachable("Unexpected index."); + } + } + } + DenseSet UniqueOpcodes; + constexpr unsigned NumAltInsts = 3; // main + alt + shuffle. + unsigned NonInstCnt = 0; + // Estimate number of instructions, required for the vectorized node and for + // the buildvector node. + unsigned UndefCnt = 0; + // Count the number of extra shuffles, required for vector nodes. + unsigned ExtraShuffleInsts = 0; + // Check that operands do not contain same values and create either perfect + // diamond match or shuffled match. + if (Operands.size() == 2) { + // Do not count same operands twice. + if (Operands.front() == Operands.back()) { + Operands.erase(Operands.begin()); + } else if (!allConstant(Operands.front()) && + all_of(Operands.front(), [&](Value *V) { + return is_contained(Operands.back(), V); + })) { + Operands.erase(Operands.begin()); + ++ExtraShuffleInsts; + } + } + const Loop *L = LI->getLoopFor(S.MainOp->getParent()); + // Vectorize node, if: + // 1. at least single operand is constant or splat. + // 2. Operands have many loop invariants (the instructions are not loop + // invariants). + // 3. At least single unique operands is supposed to vectorized. + return none_of(Operands, + [&](ArrayRef Op) { + if (allConstant(Op) || + (!isSplat(Op) && allSameBlock(Op) && allSameType(Op) && + getSameOpcode(Op, *TLI).MainOp)) + return false; + DenseMap Uniques; + for (Value *V : Op) { + if (isa(V) || + getTreeEntry(V) || (L && L->isLoopInvariant(V))) { + if (isa(V)) + ++UndefCnt; + continue; + } + auto Res = Uniques.try_emplace(V, 0); + // Found first duplicate - need to add shuffle. + if (!Res.second && Res.first->second == 1) + ++ExtraShuffleInsts; + ++Res.first->getSecond(); + if (auto *I = dyn_cast(V)) + UniqueOpcodes.insert(I->getOpcode()); + else if (Res.second) + ++NonInstCnt; + } + return none_of(Uniques, [&](const auto &P) { + return P.first->hasNUsesOrMore(P.second + 1) && + none_of(P.first->users(), [&](User *U) { + return getTreeEntry(U) || Uniques.contains(U); + }); + }); + }) || + // Do not vectorize node, if estimated number of vector instructions is + // more than estimated number of buildvector instructions. Number of + // vector operands is number of vector instructions + number of vector + // instructions for operands (buildvectors). Number of buildvector + // instructions is just number_of_operands * number_of_scalars. + (UndefCnt < (VL.size() - 1) * S.MainOp->getNumOperands() && + (UniqueOpcodes.size() + NonInstCnt + ExtraShuffleInsts + + NumAltInsts) < S.MainOp->getNumOperands() * VL.size()); +} + BoUpSLP::TreeEntry::EntryState BoUpSLP::getScalarsVectorizationState( InstructionsState &S, ArrayRef VL, bool IsScatterVectorizeUserTE, OrdersType &CurrentOrder, SmallVectorImpl &PointerOps) const { @@ -6074,6 +6194,14 @@ BoUpSLP::TreeEntry::EntryState BoUpSLP::getScalarsVectorizationState( LLVM_DEBUG(dbgs() << "SLP: ShuffleVector are not vectorized.\n"); return TreeEntry::NeedToGather; } + if (!areAltOperandsProfitable(S, VL)) { + LLVM_DEBUG( + dbgs() + << "SLP: ShuffleVector not vectorized, operands are buildvector and " + "the whole alt sequence is not profitable.\n"); + return TreeEntry::NeedToGather; + } + return TreeEntry::Vectorize; } default: diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll index d2711d0546c0..283cc07dfb9b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/extractelements-to-shuffle.ll @@ -104,16 +104,16 @@ define void @dist_vec(ptr nocapture noundef readonly %pA, ptr nocapture noundef ; CHECK-NEXT: [[AND95:%.*]] = and i32 [[B_0278]], 1 ; CHECK-NEXT: [[SHR96]] = lshr i32 [[A_0279]], 1 ; CHECK-NEXT: [[SHR97]] = lshr i32 [[B_0278]], 1 -; CHECK-NEXT: [[TMP22:%.*]] = insertelement <2 x i32> poison, i32 [[AND94]], i32 0 -; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <2 x i32> [[TMP22]], <2 x i32> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP24:%.*]] = icmp eq <2 x i32> [[TMP23]], zeroinitializer -; CHECK-NEXT: [[TMP25:%.*]] = icmp ne <2 x i32> [[TMP23]], zeroinitializer -; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <2 x i1> [[TMP24]], <2 x i1> [[TMP25]], <4 x i32> -; CHECK-NEXT: [[TMP27:%.*]] = insertelement <2 x i32> poison, i32 [[AND95]], i32 0 -; CHECK-NEXT: [[TMP28:%.*]] = shufflevector <2 x i32> [[TMP27]], <2 x i32> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP29:%.*]] = icmp ne <2 x i32> [[TMP28]], zeroinitializer -; CHECK-NEXT: [[TMP30:%.*]] = icmp eq <2 x i32> [[TMP28]], zeroinitializer -; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <2 x i1> [[TMP29]], <2 x i1> [[TMP30]], <4 x i32> +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND94]], 0 +; CHECK-NEXT: [[TOBOOL98:%.*]] = icmp ne i32 [[AND95]], 0 +; CHECK-NEXT: [[TOBOOL100:%.*]] = icmp eq i32 [[AND94]], 0 +; CHECK-NEXT: [[TOBOOL103:%.*]] = icmp eq i32 [[AND95]], 0 +; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL100]], i32 0 +; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i1> [[TMP22]], i1 [[TOBOOL]], i32 1 +; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <4 x i1> [[TMP23]], <4 x i1> poison, <4 x i32> +; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL98]], i32 0 +; CHECK-NEXT: [[TMP27:%.*]] = insertelement <4 x i1> [[TMP25]], i1 [[TOBOOL103]], i32 1 +; CHECK-NEXT: [[TMP31:%.*]] = shufflevector <4 x i1> [[TMP27]], <4 x i1> poison, <4 x i32> ; CHECK-NEXT: [[TMP32:%.*]] = select <4 x i1> [[TMP26]], <4 x i1> [[TMP31]], <4 x i1> zeroinitializer ; CHECK-NEXT: [[TMP33:%.*]] = zext <4 x i1> [[TMP32]] to <4 x i32> ; CHECK-NEXT: [[TMP34]] = add <4 x i32> [[TMP21]], [[TMP33]] @@ -149,16 +149,16 @@ define void @dist_vec(ptr nocapture noundef readonly %pA, ptr nocapture noundef ; CHECK-NEXT: [[AND134:%.*]] = and i32 [[B_1300]], 1 ; CHECK-NEXT: [[SHR135]] = lshr i32 [[A_1301]], 1 ; CHECK-NEXT: [[SHR136]] = lshr i32 [[B_1300]], 1 -; CHECK-NEXT: [[TMP39:%.*]] = insertelement <2 x i32> poison, i32 [[AND133]], i32 0 -; CHECK-NEXT: [[TMP40:%.*]] = shufflevector <2 x i32> [[TMP39]], <2 x i32> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP41:%.*]] = icmp eq <2 x i32> [[TMP40]], zeroinitializer -; CHECK-NEXT: [[TMP42:%.*]] = icmp ne <2 x i32> [[TMP40]], zeroinitializer -; CHECK-NEXT: [[TMP43:%.*]] = shufflevector <2 x i1> [[TMP41]], <2 x i1> [[TMP42]], <4 x i32> -; CHECK-NEXT: [[TMP44:%.*]] = insertelement <2 x i32> poison, i32 [[AND134]], i32 0 -; CHECK-NEXT: [[TMP45:%.*]] = shufflevector <2 x i32> [[TMP44]], <2 x i32> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP46:%.*]] = icmp ne <2 x i32> [[TMP45]], zeroinitializer -; CHECK-NEXT: [[TMP47:%.*]] = icmp eq <2 x i32> [[TMP45]], zeroinitializer -; CHECK-NEXT: [[TMP48:%.*]] = shufflevector <2 x i1> [[TMP46]], <2 x i1> [[TMP47]], <4 x i32> +; CHECK-NEXT: [[TOBOOL137:%.*]] = icmp ne i32 [[AND133]], 0 +; CHECK-NEXT: [[TOBOOL139:%.*]] = icmp ne i32 [[AND134]], 0 +; CHECK-NEXT: [[TOBOOL144:%.*]] = icmp eq i32 [[AND133]], 0 +; CHECK-NEXT: [[TOBOOL147:%.*]] = icmp eq i32 [[AND134]], 0 +; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL144]], i32 0 +; CHECK-NEXT: [[TMP41:%.*]] = insertelement <4 x i1> [[TMP40]], i1 [[TOBOOL137]], i32 1 +; CHECK-NEXT: [[TMP43:%.*]] = shufflevector <4 x i1> [[TMP41]], <4 x i1> poison, <4 x i32> +; CHECK-NEXT: [[TMP42:%.*]] = insertelement <4 x i1> poison, i1 [[TOBOOL139]], i32 0 +; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i1> [[TMP42]], i1 [[TOBOOL147]], i32 1 +; CHECK-NEXT: [[TMP48:%.*]] = shufflevector <4 x i1> [[TMP39]], <4 x i1> poison, <4 x i32> ; CHECK-NEXT: [[TMP49:%.*]] = select <4 x i1> [[TMP43]], <4 x i1> [[TMP48]], <4 x i1> zeroinitializer ; CHECK-NEXT: [[TMP50:%.*]] = zext <4 x i1> [[TMP49]] to <4 x i32> ; CHECK-NEXT: [[TMP51]] = add <4 x i32> [[TMP38]], [[TMP50]] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll b/llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll index 05534fa961ee..b76e26e0fd57 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/ext-int-reduced-not-operand.ll @@ -9,13 +9,8 @@ define i64 @wombat() { ; CHECK-NEXT: br label [[BB2]] ; CHECK: bb2: ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ 0, [[BB1:%.*]] ] -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[PHI]], i32 0 -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i1> -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i64 -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1 -; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[PHI]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[PHI]] to i64 ; CHECK-NEXT: [[OR:%.*]] = or i64 [[TMP4]], [[TMP6]] ; CHECK-NEXT: ret i64 [[OR]] ; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll index 78fc3a60f051..3c3dea3f1ea8 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/gather-move-out-of-loop.ll @@ -4,14 +4,12 @@ define void @test(i16 %0) { ; CHECK-LABEL: @test( ; CHECK-NEXT: for.body92.preheader: -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> , i16 [[TMP0:%.*]], i32 1 -; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i32> -; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> , <4 x i32> [[TMP5]], <4 x i32> ; CHECK-NEXT: br label [[FOR_BODY92:%.*]] ; CHECK: for.body92: +; CHECK-NEXT: [[CONV177_I:%.*]] = sext i16 0 to i32 +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[TMP0:%.*]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i32> , i32 [[CONV177_I]], i32 0 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[TMP2]], i32 [[TMP1]], i32 2 ; CHECK-NEXT: [[TMP7:%.*]] = add nsw <4 x i32> zeroinitializer, [[TMP6]] ; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr undef, align 8 ; CHECK-NEXT: br label [[FOR_BODY92]] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll b/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll index 16ede231c200..19a8aa9b6181 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/gathered-delayed-nodes-with-reused-user.ll @@ -6,21 +6,19 @@ define i64 @foo() { ; CHECK-NEXT: bb: ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: bb1: -; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i64> [ [[TMP5:%.*]], [[BB3]] ] +; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ [[ADD:%.*]], [[BB3]] ] +; CHECK-NEXT: [[PHI2:%.*]] = phi i64 [ [[TMP9:%.*]], [[BB3]] ] ; CHECK-NEXT: ret i64 0 ; CHECK: bb3: ; CHECK-NEXT: [[PHI5:%.*]] = phi i64 [ 0, [[BB:%.*]] ], [ 0, [[BB3]] ] ; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i64> [ zeroinitializer, [[BB]] ], [ [[TMP7:%.*]], [[BB3]] ] -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> , i64 [[PHI5]], i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP5]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> , <2 x i32> -; CHECK-NEXT: [[TMP7]] = add <2 x i64> [[TMP6]], [[TMP2]] -; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[TMP7]], i32 1 -; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 [[TMP8]] -; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1 +; CHECK-NEXT: [[ADD]] = add i64 [[TMP3]], [[TMP2]] +; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr i64, ptr addrspace(1) null, i64 0 +; CHECK-NEXT: [[TMP9]] = or i64 [[PHI5]], 0 ; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i64 [[TMP9]], 0 +; CHECK-NEXT: [[TMP7]] = insertelement <2 x i64> , i64 [[ADD]], i32 0 ; CHECK-NEXT: br i1 false, label [[BB3]], label [[BB1:%.*]] ; bb: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll b/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll index 3a9eca2bf2e6..59cd1c0ccddf 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/non-scheduled-inst-reused-as-last-inst.ll @@ -4,22 +4,22 @@ define void @foo() { ; CHECK-LABEL: define void @foo() { ; CHECK-NEXT: bb: -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i32> , i32 0, i32 0 ; CHECK-NEXT: br label [[BB1:%.*]] ; CHECK: bb1: ; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x i32> [ zeroinitializer, [[BB:%.*]] ], [ [[TMP6:%.*]], [[BB4:%.*]] ] -; CHECK-NEXT: [[TMP2:%.*]] = shl <2 x i32> [[TMP1]], [[TMP0]] -; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i32> [[TMP1]], [[TMP0]] -; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> -; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> [[TMP1]], <2 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[TMP2]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[SHL]], i32 0 ; CHECK-NEXT: [[TMP6]] = or <2 x i32> [[TMP5]], zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i32 0 ; CHECK-NEXT: [[CALL:%.*]] = call i64 null(i32 [[TMP7]]) ; CHECK-NEXT: br label [[BB4]] ; CHECK: bb4: +; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i32> [[TMP6]], i32 1 ; CHECK-NEXT: br i1 false, label [[BB5:%.*]], label [[BB1]] ; CHECK: bb5: -; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i32> [ [[TMP4]], [[BB4]] ] +; CHECK-NEXT: [[PHI6:%.*]] = phi i32 [ [[SHL]], [[BB4]] ] +; CHECK-NEXT: [[PHI7:%.*]] = phi i32 [ [[TMP8]], [[BB4]] ] ; CHECK-NEXT: ret void ; bb: diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll index 09b3d25fd6dc..93258f2975f3 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_with_external_users.ll @@ -112,10 +112,10 @@ define void @addsub_and_external_users(ptr %A, ptr %ptr) { ; CHECK-NEXT: bb1: ; CHECK-NEXT: [[LD:%.*]] = load double, ptr undef, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LD]], i32 0 -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP1:%.*]] = fsub <2 x double> [[SHUFFLE]], -; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x double> [[SHUFFLE]], -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[TMP1]], +; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP6]], <2 x i32> ; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], ; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <2 x i32> @@ -159,10 +159,10 @@ define void @subadd_and_external_users(ptr %A, ptr %ptr) { ; CHECK-NEXT: bb1: ; CHECK-NEXT: [[LD:%.*]] = load double, ptr undef, align 8 ; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[LD]], i32 0 -; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x double> [[SHUFFLE]], -; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[SHUFFLE]], -; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP0]], <2 x double> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[TMP1]], +; CHECK-NEXT: [[TMP6:%.*]] = fadd <2 x double> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP6]], <2 x i32> ; CHECK-NEXT: [[TMP4:%.*]] = fdiv <2 x double> [[TMP3]], ; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP4]], ; CHECK-NEXT: store <2 x double> [[TMP5]], ptr [[A:%.*]], align 8 diff --git a/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll b/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll index c6e2cf5543e1..287b623f6369 100644 --- a/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll +++ b/llvm/test/Transforms/SLPVectorizer/alternate-non-profitable.ll @@ -33,11 +33,10 @@ define <2 x float> @replace_through_casts(i16 %inp) { ; CHECK-LABEL: define <2 x float> @replace_through_casts( ; CHECK-SAME: i16 [[INP:%.*]]) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i16 [[INP]], -10 -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i16> [[TMP1]], i16 [[ADD]], i32 1 -; CHECK-NEXT: [[TMP3:%.*]] = uitofp <2 x i16> [[TMP2]] to <2 x float> -; CHECK-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP2]] to <2 x float> -; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> [[TMP4]], <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = uitofp i16 [[INP]] to float +; CHECK-NEXT: [[TMP2:%.*]] = sitofp i16 [[ADD]] to float +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i64 0 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x float> [[TMP3]], float [[TMP2]], i64 1 ; CHECK-NEXT: ret <2 x float> [[R]] ; %add = add nsw i16 %inp, -10 @@ -118,11 +117,10 @@ define <2 x i32> @replace_through_int_casts(i16 %inp, <2 x i16> %dead) { ; CHECK-LABEL: define <2 x i32> @replace_through_int_casts( ; CHECK-SAME: i16 [[INP:%.*]], <2 x i16> [[DEAD:%.*]]) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i16 [[INP]], -10 -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i16> [[TMP1]], i16 [[ADD]], i32 1 -; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32> -; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[INP]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = sext i16 [[ADD]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP1]], i64 0 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP2]], i64 1 ; CHECK-NEXT: ret <2 x i32> [[R]] ; %add = add nsw i16 %inp, -10 @@ -136,11 +134,10 @@ define <2 x i32> @replace_through_int_casts(i16 %inp, <2 x i16> %dead) { define <2 x i32> @replace_through_int_casts_ele0_only(i16 %inp, <2 x i16> %dead) { ; CHECK-LABEL: define <2 x i32> @replace_through_int_casts_ele0_only( ; CHECK-SAME: i16 [[INP:%.*]], <2 x i16> [[DEAD:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i16> poison, i16 [[INP]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i32> -; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[INP]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[INP]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> poison, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i64 1 ; CHECK-NEXT: ret <2 x i32> [[R]] ; %2 = sext i16 %inp to i32 @@ -174,11 +171,10 @@ define <2 x i8> @replace_through_binop_preserve_flags(i8 %inp, <2 x i8> %d, <2 x ; CHECK-LABEL: define <2 x i8> @replace_through_binop_preserve_flags( ; CHECK-SAME: i8 [[INP:%.*]], <2 x i8> [[D:%.*]], <2 x i8> [[ANY:%.*]]) { ; CHECK-NEXT: [[ADD:%.*]] = xor i8 [[INP]], 5 -; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[INP]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[ADD]], i32 1 -; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i8> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = add nsw <2 x i8> [[TMP2]], -; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i8> [[TMP3]], <2 x i8> [[TMP4]], <2 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[INP]], 123 +; CHECK-NEXT: [[TMP2:%.*]] = add nsw i8 [[ADD]], 1 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i8> poison, i8 [[TMP1]], i64 0 +; CHECK-NEXT: [[R:%.*]] = insertelement <2 x i8> [[TMP3]], i8 [[TMP2]], i64 1 ; CHECK-NEXT: ret <2 x i8> [[R]] ; %add = xor i8 %inp, 5 -- GitLab From 0a1317564a6b437760d96f0a227a3c910875428d Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Wed, 10 Apr 2024 20:34:58 +0200 Subject: [PATCH 441/695] [libc++] Adds a global private constructor tag. (#87920) This removes the similar tags used in the chrono tzdb implementation. Fixes: https://github.com/llvm/llvm-project/issues/85432 --- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__chrono/leap_second.h | 4 +-- libcxx/include/__chrono/time_zone_link.h | 4 +-- libcxx/include/__locale | 12 ++++---- libcxx/include/__stop_token/stop_callback.h | 9 +++--- .../__utility/private_constructor_tag.h | 28 +++++++++++++++++++ libcxx/include/module.modulemap | 21 +++++++------- libcxx/src/CMakeLists.txt | 2 -- libcxx/src/include/tzdb/leap_second_private.h | 27 ------------------ .../src/include/tzdb/time_zone_link_private.h | 27 ------------------ libcxx/src/locale.cpp | 2 +- libcxx/src/tzdb.cpp | 6 ++-- .../private_constructor_tag.compile.pass.cpp | 19 +++++++++++++ .../time.zone.leap/assign.copy.pass.cpp | 2 -- .../time.zone.leap/cons.copy.pass.cpp | 2 -- .../time.zone.leap/members/date.pass.cpp | 2 -- .../time.zone.leap/members/value.pass.cpp | 2 -- .../nonmembers/comparison.pass.cpp | 2 -- libcxx/test/support/test_chrono_leap_second.h | 9 ++---- libcxx/utils/generate_iwyu_mapping.py | 1 + 20 files changed, 79 insertions(+), 103 deletions(-) create mode 100644 libcxx/include/__utility/private_constructor_tag.h delete mode 100644 libcxx/src/include/tzdb/leap_second_private.h delete mode 100644 libcxx/src/include/tzdb/time_zone_link_private.h create mode 100644 libcxx/test/libcxx/utilities/utility/private_constructor_tag.compile.pass.cpp diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index a4a58a787ee9..d4e8c196a9a8 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -863,6 +863,7 @@ set(files __utility/pair.h __utility/piecewise_construct.h __utility/priority_tag.h + __utility/private_constructor_tag.h __utility/rel_ops.h __utility/small_buffer.h __utility/swap.h diff --git a/libcxx/include/__chrono/leap_second.h b/libcxx/include/__chrono/leap_second.h index 4e67cc2d6527..557abc15ff18 100644 --- a/libcxx/include/__chrono/leap_second.h +++ b/libcxx/include/__chrono/leap_second.h @@ -22,6 +22,7 @@ # include <__compare/ordering.h> # include <__compare/three_way_comparable.h> # include <__config> +# include <__utility/private_constructor_tag.h> # if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -35,9 +36,8 @@ namespace chrono { class leap_second { public: - struct __constructor_tag; [[nodiscard]] - _LIBCPP_HIDE_FROM_ABI explicit constexpr leap_second(__constructor_tag&&, sys_seconds __date, seconds __value) + _LIBCPP_HIDE_FROM_ABI explicit constexpr leap_second(__private_constructor_tag, sys_seconds __date, seconds __value) : __date_(__date), __value_(__value) {} _LIBCPP_HIDE_FROM_ABI leap_second(const leap_second&) = default; diff --git a/libcxx/include/__chrono/time_zone_link.h b/libcxx/include/__chrono/time_zone_link.h index 17e915d2677a..c76ddeff9f96 100644 --- a/libcxx/include/__chrono/time_zone_link.h +++ b/libcxx/include/__chrono/time_zone_link.h @@ -18,6 +18,7 @@ # include <__compare/strong_order.h> # include <__config> +# include <__utility/private_constructor_tag.h> # include # include @@ -37,9 +38,8 @@ namespace chrono { class time_zone_link { public: - struct __constructor_tag; _LIBCPP_NODISCARD_EXT - _LIBCPP_HIDE_FROM_ABI explicit time_zone_link(__constructor_tag&&, string_view __name, string_view __target) + _LIBCPP_HIDE_FROM_ABI explicit time_zone_link(__private_constructor_tag, string_view __name, string_view __target) : __name_{__name}, __target_{__target} {} _LIBCPP_HIDE_FROM_ABI time_zone_link(time_zone_link&&) = default; diff --git a/libcxx/include/__locale b/libcxx/include/__locale index fab87f0d6a27..36ac099d650e 100644 --- a/libcxx/include/__locale +++ b/libcxx/include/__locale @@ -16,6 +16,7 @@ #include <__mutex/once_flag.h> #include <__type_traits/make_unsigned.h> #include <__utility/no_destroy.h> +#include <__utility/private_constructor_tag.h> #include #include #include @@ -97,8 +98,7 @@ private: template friend struct __no_destroy; - struct __private_tag {}; - _LIBCPP_HIDE_FROM_ABI explicit locale(__private_tag, __imp* __loc) : __locale_(__loc) {} + _LIBCPP_HIDE_FROM_ABI explicit locale(__private_constructor_tag, __imp* __loc) : __locale_(__loc) {} void __install_ctor(const locale&, facet*, long); static locale& __global(); @@ -1248,10 +1248,10 @@ extern template class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname; #endif -extern template class _LIBCPP_DEPRECATED_IN_CXX20 _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS - codecvt_byname; // deprecated in C++20 -extern template class _LIBCPP_DEPRECATED_IN_CXX20 _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS - codecvt_byname; // deprecated in C++20 +extern template class _LIBCPP_DEPRECATED_IN_CXX20 +_LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname; // deprecated in C++20 +extern template class _LIBCPP_DEPRECATED_IN_CXX20 +_LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname; // deprecated in C++20 #ifndef _LIBCPP_HAS_NO_CHAR8_T extern template class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname; // C++20 extern template class _LIBCPP_EXTERN_TEMPLATE_TYPE_VIS codecvt_byname; // C++20 diff --git a/libcxx/include/__stop_token/stop_callback.h b/libcxx/include/__stop_token/stop_callback.h index 9e5b0338d466..7b526820f98a 100644 --- a/libcxx/include/__stop_token/stop_callback.h +++ b/libcxx/include/__stop_token/stop_callback.h @@ -21,6 +21,7 @@ #include <__type_traits/is_nothrow_constructible.h> #include <__utility/forward.h> #include <__utility/move.h> +#include <__utility/private_constructor_tag.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -49,13 +50,13 @@ public: requires constructible_from<_Callback, _Cb> _LIBCPP_HIDE_FROM_ABI explicit stop_callback(const stop_token& __st, _Cb&& __cb) noexcept(is_nothrow_constructible_v<_Callback, _Cb>) - : stop_callback(__private_tag{}, __st.__state_, std::forward<_Cb>(__cb)) {} + : stop_callback(__private_constructor_tag{}, __st.__state_, std::forward<_Cb>(__cb)) {} template requires constructible_from<_Callback, _Cb> _LIBCPP_HIDE_FROM_ABI explicit stop_callback(stop_token&& __st, _Cb&& __cb) noexcept(is_nothrow_constructible_v<_Callback, _Cb>) - : stop_callback(__private_tag{}, std::move(__st.__state_), std::forward<_Cb>(__cb)) {} + : stop_callback(__private_constructor_tag{}, std::move(__st.__state_), std::forward<_Cb>(__cb)) {} _LIBCPP_HIDE_FROM_ABI ~stop_callback() { if (__state_) { @@ -74,10 +75,8 @@ private: friend __stop_callback_base; - struct __private_tag {}; - template - _LIBCPP_HIDE_FROM_ABI explicit stop_callback(__private_tag, _StatePtr&& __state, _Cb&& __cb) noexcept( + _LIBCPP_HIDE_FROM_ABI explicit stop_callback(__private_constructor_tag, _StatePtr&& __state, _Cb&& __cb) noexcept( is_nothrow_constructible_v<_Callback, _Cb>) : __stop_callback_base([](__stop_callback_base* __cb_base) noexcept { // stop callback is supposed to only be called once diff --git a/libcxx/include/__utility/private_constructor_tag.h b/libcxx/include/__utility/private_constructor_tag.h new file mode 100644 index 000000000000..462cab48c9ed --- /dev/null +++ b/libcxx/include/__utility/private_constructor_tag.h @@ -0,0 +1,28 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP__UTILITY_PRIVATE_CONSTRUCTOR_TAG_H +#define _LIBCPP__UTILITY_PRIVATE_CONSTRUCTOR_TAG_H + +#include <__config> + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +_LIBCPP_BEGIN_NAMESPACE_STD + +// This tag allows defining non-standard exposition-only constructors while +// preventing users from being able to use them, since this reserved-name tag +// needs to be used. +struct __private_constructor_tag {}; + +_LIBCPP_END_NAMESPACE_STD + +#endif // _LIBCPP__UTILITY_PRIVATE_CONSTRUCTOR_TAG_H diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index 011a4818ab9d..9c0f0ddd20c9 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -2090,18 +2090,19 @@ module std_private_utility_pair [system] { export std_private_type_traits_is_nothrow_move_assignable export std_private_utility_pair_fwd } -module std_private_utility_pair_fwd [system] { header "__fwd/pair.h" } -module std_private_utility_piecewise_construct [system] { header "__utility/piecewise_construct.h" } -module std_private_utility_priority_tag [system] { header "__utility/priority_tag.h" } -module std_private_utility_rel_ops [system] { header "__utility/rel_ops.h" } -module std_private_utility_small_buffer [system] { header "__utility/small_buffer.h" } -module std_private_utility_swap [system] { +module std_private_utility_pair_fwd [system] { header "__fwd/pair.h" } +module std_private_utility_piecewise_construct [system] { header "__utility/piecewise_construct.h" } +module std_private_utility_priority_tag [system] { header "__utility/priority_tag.h" } +module std_private_utility_private_constructor_tag [system] { header "__utility/private_constructor_tag.h" } +module std_private_utility_rel_ops [system] { header "__utility/rel_ops.h" } +module std_private_utility_small_buffer [system] { header "__utility/small_buffer.h" } +module std_private_utility_swap [system] { header "__utility/swap.h" export std_private_type_traits_is_swappable } -module std_private_utility_to_underlying [system] { header "__utility/to_underlying.h" } -module std_private_utility_unreachable [system] { header "__utility/unreachable.h" } +module std_private_utility_to_underlying [system] { header "__utility/to_underlying.h" } +module std_private_utility_unreachable [system] { header "__utility/unreachable.h" } -module std_private_variant_monostate [system] { header "__variant/monostate.h" } +module std_private_variant_monostate [system] { header "__variant/monostate.h" } -module std_private_vector_fwd [system] { header "__fwd/vector.h" } +module std_private_vector_fwd [system] { header "__fwd/vector.h" } diff --git a/libcxx/src/CMakeLists.txt b/libcxx/src/CMakeLists.txt index 16ccb80ba332..208500ec14fc 100644 --- a/libcxx/src/CMakeLists.txt +++ b/libcxx/src/CMakeLists.txt @@ -334,8 +334,6 @@ endif() if (LIBCXX_ENABLE_LOCALIZATION AND LIBCXX_ENABLE_FILESYSTEM AND LIBCXX_ENABLE_TIME_ZONE_DATABASE) list(APPEND LIBCXX_EXPERIMENTAL_SOURCES - include/tzdb/leap_second_private.h - include/tzdb/time_zone_link_private.h include/tzdb/time_zone_private.h include/tzdb/types_private.h include/tzdb/tzdb_list_private.h diff --git a/libcxx/src/include/tzdb/leap_second_private.h b/libcxx/src/include/tzdb/leap_second_private.h deleted file mode 100644 index 7a811ab19759..000000000000 --- a/libcxx/src/include/tzdb/leap_second_private.h +++ /dev/null @@ -1,27 +0,0 @@ -// -*- C++ -*- -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// For information see https://libcxx.llvm.org/DesignDocs/TimeZone.html - -#ifndef _LIBCPP_SRC_INCLUDE_TZDB_LEAP_SECOND_PRIVATE_H -#define _LIBCPP_SRC_INCLUDE_TZDB_LEAP_SECOND_PRIVATE_H - -#include - -_LIBCPP_BEGIN_NAMESPACE_STD - -namespace chrono { - -struct leap_second::__constructor_tag {}; - -} // namespace chrono - -_LIBCPP_END_NAMESPACE_STD - -#endif // _LIBCPP_SRC_INCLUDE_TZDB_LEAP_SECOND_PRIVATE_H diff --git a/libcxx/src/include/tzdb/time_zone_link_private.h b/libcxx/src/include/tzdb/time_zone_link_private.h deleted file mode 100644 index 139237625274..000000000000 --- a/libcxx/src/include/tzdb/time_zone_link_private.h +++ /dev/null @@ -1,27 +0,0 @@ -// -*- C++ -*- -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// For information see https://libcxx.llvm.org/DesignDocs/TimeZone.html - -#ifndef _LIBCPP_SRC_INCLUDE_TZDB_TIME_ZONE_LINK_PRIVATE_H -#define _LIBCPP_SRC_INCLUDE_TZDB_TIME_ZONE_LINK_PRIVATE_H - -#include - -_LIBCPP_BEGIN_NAMESPACE_STD - -namespace chrono { - -struct time_zone_link::__constructor_tag {}; - -} // namespace chrono - -_LIBCPP_END_NAMESPACE_STD - -#endif // _LIBCPP_SRC_INCLUDE_TZDB_TIME_ZONE_LINK_PRIVATE_H diff --git a/libcxx/src/locale.cpp b/libcxx/src/locale.cpp index 7fdd5be181ed..1ca88e30f63a 100644 --- a/libcxx/src/locale.cpp +++ b/libcxx/src/locale.cpp @@ -497,7 +497,7 @@ constinit __no_destroy locale::__imp::classic_locale_imp_(__uninitialized_tag{}); // initialized below in classic() const locale& locale::classic() { - static const __no_destroy classic_locale(__private_tag{}, [] { + static const __no_destroy classic_locale(__private_constructor_tag{}, [] { // executed exactly once on first initialization of `classic_locale` locale::__imp::classic_locale_imp_.__emplace(1u); return &locale::__imp::classic_locale_imp_.__get(); diff --git a/libcxx/src/tzdb.cpp b/libcxx/src/tzdb.cpp index 8909ecd026ad..d521d810523e 100644 --- a/libcxx/src/tzdb.cpp +++ b/libcxx/src/tzdb.cpp @@ -15,8 +15,6 @@ #include #include -#include "include/tzdb/leap_second_private.h" -#include "include/tzdb/time_zone_link_private.h" #include "include/tzdb/time_zone_private.h" #include "include/tzdb/types_private.h" #include "include/tzdb/tzdb_list_private.h" @@ -582,7 +580,7 @@ static void __parse_link(tzdb& __tzdb, istream& __input) { string __name = chrono::__parse_string(__input); chrono::__skip_line(__input); - __tzdb.links.emplace_back(time_zone_link::__constructor_tag{}, std::move(__name), std::move(__target)); + __tzdb.links.emplace_back(std::__private_constructor_tag{}, std::move(__name), std::move(__target)); } static void __parse_tzdata(tzdb& __db, __tz::__rules_storage_type& __rules, istream& __input) { @@ -649,7 +647,7 @@ static void __parse_leap_seconds(vector& __leap_seconds, istream&& seconds __value{chrono::__parse_integral(__input, false)}; chrono::__skip_line(__input); - __leap_seconds.emplace_back(leap_second::__constructor_tag{}, __date, __value); + __leap_seconds.emplace_back(std::__private_constructor_tag{}, __date, __value); } } diff --git a/libcxx/test/libcxx/utilities/utility/private_constructor_tag.compile.pass.cpp b/libcxx/test/libcxx/utilities/utility/private_constructor_tag.compile.pass.cpp new file mode 100644 index 000000000000..097e05f29ceb --- /dev/null +++ b/libcxx/test/libcxx/utilities/utility/private_constructor_tag.compile.pass.cpp @@ -0,0 +1,19 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// struct __private_constructor_tag{}; + +// The private constructor tag is intended to be a trivial type that can easily +// be used to mark a constructor exposition-only. +// +// Tests whether the type is trivial. + +#include <__utility/private_constructor_tag.h> +#include + +static_assert(std::is_trivial::value, ""); diff --git a/libcxx/test/std/time/time.zone/time.zone.leap/assign.copy.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.leap/assign.copy.pass.cpp index 4d91e73f38e4..6918ed6be5c1 100644 --- a/libcxx/test/std/time/time.zone/time.zone.leap/assign.copy.pass.cpp +++ b/libcxx/test/std/time/time.zone/time.zone.leap/assign.copy.pass.cpp @@ -27,8 +27,6 @@ #include #include -// Add the include path required by test_chrono_leap_second.h when using libc++. -// ADDITIONAL_COMPILE_FLAGS(stdlib=libc++): -I %{libcxx-dir}/src/include #include "test_chrono_leap_second.h" constexpr bool test() { diff --git a/libcxx/test/std/time/time.zone/time.zone.leap/cons.copy.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.leap/cons.copy.pass.cpp index e2419b7d1f09..3dad08968d12 100644 --- a/libcxx/test/std/time/time.zone/time.zone.leap/cons.copy.pass.cpp +++ b/libcxx/test/std/time/time.zone/time.zone.leap/cons.copy.pass.cpp @@ -25,8 +25,6 @@ #include #include -// Add the include path required by test_chrono_leap_second.h when using libc++. -// ADDITIONAL_COMPILE_FLAGS(stdlib=libc++): -I %{libcxx-dir}/src/include #include "test_chrono_leap_second.h" constexpr bool test() { diff --git a/libcxx/test/std/time/time.zone/time.zone.leap/members/date.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.leap/members/date.pass.cpp index 23f95eccfdec..6f9fe1c47d35 100644 --- a/libcxx/test/std/time/time.zone/time.zone.leap/members/date.pass.cpp +++ b/libcxx/test/std/time/time.zone/time.zone.leap/members/date.pass.cpp @@ -23,8 +23,6 @@ #include "test_macros.h" -// Add the include path required by test_chrono_leap_second.h when using libc++. -// ADDITIONAL_COMPILE_FLAGS(stdlib=libc++): -I %{libcxx-dir}/src/include #include "test_chrono_leap_second.h" constexpr void test(const std::chrono::leap_second leap_second, std::chrono::sys_seconds expected) { diff --git a/libcxx/test/std/time/time.zone/time.zone.leap/members/value.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.leap/members/value.pass.cpp index 844c74d002ac..652e51ef0bf1 100644 --- a/libcxx/test/std/time/time.zone/time.zone.leap/members/value.pass.cpp +++ b/libcxx/test/std/time/time.zone/time.zone.leap/members/value.pass.cpp @@ -23,8 +23,6 @@ #include "test_macros.h" -// Add the include path required by test_chrono_leap_second.h when using libc++. -// ADDITIONAL_COMPILE_FLAGS(stdlib=libc++): -I %{libcxx-dir}/src/include #include "test_chrono_leap_second.h" constexpr void test(const std::chrono::leap_second leap_second, std::chrono::seconds expected) { diff --git a/libcxx/test/std/time/time.zone/time.zone.leap/nonmembers/comparison.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.leap/nonmembers/comparison.pass.cpp index ac8b780af854..bf6855ea63df 100644 --- a/libcxx/test/std/time/time.zone/time.zone.leap/nonmembers/comparison.pass.cpp +++ b/libcxx/test/std/time/time.zone/time.zone.leap/nonmembers/comparison.pass.cpp @@ -50,8 +50,6 @@ #include "test_macros.h" #include "test_comparisons.h" -// Add the include path required by test_chrono_leap_second.h when using libc++. -// ADDITIONAL_COMPILE_FLAGS(stdlib=libc++): -I %{libcxx-dir}/src/include #include "test_chrono_leap_second.h" constexpr void test_comparison(const std::chrono::leap_second lhs, const std::chrono::leap_second rhs) { diff --git a/libcxx/test/support/test_chrono_leap_second.h b/libcxx/test/support/test_chrono_leap_second.h index 485f68d91b1a..be5ce760bfe9 100644 --- a/libcxx/test/support/test_chrono_leap_second.h +++ b/libcxx/test/support/test_chrono_leap_second.h @@ -32,16 +32,11 @@ #ifdef _LIBCPP_VERSION -// In order to find this include the calling test needs to provide this path in -// the search path. Typically this looks like: -// ADDITIONAL_COMPILE_FLAGS(stdlib=libc++): -I %{libcxx-dir}/src/include -// where the number of `../` sequences depends on the subdirectory level of the -// test. -# include "tzdb/leap_second_private.h" // Header in the dylib +# include <__utility/private_constructor_tag.h> inline constexpr std::chrono::leap_second test_leap_second_create(const std::chrono::sys_seconds& date, const std::chrono::seconds& value) { - return std::chrono::leap_second{std::chrono::leap_second::__constructor_tag{}, date, value}; + return std::chrono::leap_second{std::__private_constructor_tag{}, date, value}; } #else // _LIBCPP_VERSION diff --git a/libcxx/utils/generate_iwyu_mapping.py b/libcxx/utils/generate_iwyu_mapping.py index 8ab7b86299ed..2265438ab49c 100644 --- a/libcxx/utils/generate_iwyu_mapping.py +++ b/libcxx/utils/generate_iwyu_mapping.py @@ -11,6 +11,7 @@ def IWYU_mapping(header: str) -> typing.Optional[typing.List[str]]: "__debug_utils/.+", "__fwd/get[.]h", "__support/.+", + "__utility/private_constructor_tag.h", ] if any(re.match(pattern, header) for pattern in ignore): return None -- GitLab From f81879c0f70ee5a1cf1d5b716dfd49d1a271cc2d Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Apr 2024 13:35:04 -0500 Subject: [PATCH 442/695] [Libomptarget] Add RPC-based printf implementation for OpenMP #85638 Summary: Relanding after reverting, only applies to AMDGPU for now. This patch adds an implementation of printf that's provided by the GPU C library runtime. This pritnf currently implemented using the same wrapper handling that OpenMP sets up. This will be removed once we have proper varargs support. This printf differs from the one CUDA offers in that it is synchronous and uses a finite size. Additionally we support pretty much every format specifier except the %n option. Depends on #85331 --- openmp/libomptarget/DeviceRTL/CMakeLists.txt | 5 +++++ openmp/libomptarget/DeviceRTL/src/LibC.cpp | 15 ++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/openmp/libomptarget/DeviceRTL/CMakeLists.txt b/openmp/libomptarget/DeviceRTL/CMakeLists.txt index 2509f1276cce..2e7f28df24d6 100644 --- a/openmp/libomptarget/DeviceRTL/CMakeLists.txt +++ b/openmp/libomptarget/DeviceRTL/CMakeLists.txt @@ -122,6 +122,11 @@ set(clang_opt_flags -O3 -mllvm -openmp-opt-disable -DSHARED_SCRATCHPAD_SIZE=512 set(link_opt_flags -O3 -openmp-opt-disable -attributor-enable=module -vectorize-slp=false ) set(link_export_flag -passes=internalize -internalize-public-api-file=${source_directory}/exports) +# If the user built with the GPU C library enabled we will use that instead. +if(${LIBOMPTARGET_GPU_LIBC_SUPPORT}) + list(APPEND clang_opt_flags -DOMPTARGET_HAS_LIBC) +endif() + # Prepend -I to each list element set (LIBOMPTARGET_LLVM_INCLUDE_DIRS_DEVICERTL "${LIBOMPTARGET_LLVM_INCLUDE_DIRS}") list(TRANSFORM LIBOMPTARGET_LLVM_INCLUDE_DIRS_DEVICERTL PREPEND "-I") diff --git a/openmp/libomptarget/DeviceRTL/src/LibC.cpp b/openmp/libomptarget/DeviceRTL/src/LibC.cpp index af675b97256f..e587c3057f5b 100644 --- a/openmp/libomptarget/DeviceRTL/src/LibC.cpp +++ b/openmp/libomptarget/DeviceRTL/src/LibC.cpp @@ -25,13 +25,26 @@ int32_t omp_vprintf(const char *Format, void *Arguments, uint32_t) { } // namespace impl #pragma omp end declare variant -// We do not have a vprintf implementation for AMD GPU yet so we use a stub. #pragma omp begin declare variant match(device = {arch(amdgcn)}) + +#ifdef OMPTARGET_HAS_LIBC +// TODO: Remove this handling once we have varargs support. +extern "C" struct FILE *stdout; +extern "C" int32_t rpc_fprintf(FILE *, const char *, void *, uint64_t); + +namespace impl { +int32_t omp_vprintf(const char *Format, void *Arguments, uint32_t Size) { + return rpc_fprintf(stdout, Format, Arguments, Size); +} +} // namespace impl +#else +// We do not have a vprintf implementation for AMD GPU so we use a stub. namespace impl { int32_t omp_vprintf(const char *Format, void *Arguments, uint32_t) { return -1; } } // namespace impl +#endif #pragma omp end declare variant extern "C" { -- GitLab From fad14707b73d6387e6276507e1c5726e67f08cd6 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Wed, 10 Apr 2024 14:07:18 -0500 Subject: [PATCH 443/695] [libc] Add note to use `LIBC_GPU_BUILD=ON` as another form Summary: This is a shorthand to enable GPU support so it should be listed in the docs. --- libc/docs/gpu/building.rst | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/libc/docs/gpu/building.rst b/libc/docs/gpu/building.rst index 6d94134a407d..d3e64c6d4243 100644 --- a/libc/docs/gpu/building.rst +++ b/libc/docs/gpu/building.rst @@ -33,7 +33,8 @@ The simplest way to build the GPU libc is to use the existing LLVM runtimes support. This will automatically handle bootstrapping an up-to-date ``clang`` compiler and using it to build the C library. The following CMake invocation will instruct it to build the ``libc`` runtime targeting both AMD and NVIDIA -GPUs. +GPUs. The ``LIBC_GPU_BUILD`` option can also be enabled to add the relevant +arguments automatically. .. code-block:: sh @@ -234,6 +235,10 @@ standard runtime build. This flag controls whether or not the libc build will generate its own headers. This must always be on when targeting the GPU. +**LIBC_GPU_BUILD**:BOOL + Shorthand for enabling GPU support. Equivalent to enabling support for both + AMDGPU and NVPTX builds for ``libc``. + **LIBC_GPU_TEST_ARCHITECTURE**:STRING Sets the architecture used to build the GPU tests for, such as ``gfx90a`` or ``sm_80`` for AMD and NVIDIA GPUs respectively. The default behavior is to -- GitLab From ca6b8469c16edfe1713e9050dca3cd68bd585410 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 10 Apr 2024 12:20:28 -0700 Subject: [PATCH 444/695] [ELF] Avoid unneeded config->isLE and config->wordsize. NFC --- lld/ELF/SyntheticSections.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index 550659464a44..d8791e83dc9e 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -2769,7 +2769,8 @@ readPubNamesAndTypes(const LLDDwarfObj &obj, SmallVector ret; for (const LLDDWARFSection *pub : {&pubNames, &pubTypes}) { - DWARFDataExtractor data(obj, *pub, config->isLE, config->wordsize); + DWARFDataExtractor data(obj, *pub, ELFT::Endianness == endianness::little, + ELFT::Is64Bits ? 8 : 4); DWARFDebugPubTable table; table.extract(data, /*GnuStyle=*/true, [&](Error e) { warn(toString(pub->sec) + ": " + toString(std::move(e))); @@ -3744,8 +3745,9 @@ template void elf::writeEhdr(uint8_t *buf, Partition &part) { memcpy(buf, "\177ELF", 4); auto *eHdr = reinterpret_cast(buf); - eHdr->e_ident[EI_CLASS] = config->is64 ? ELFCLASS64 : ELFCLASS32; - eHdr->e_ident[EI_DATA] = config->isLE ? ELFDATA2LSB : ELFDATA2MSB; + eHdr->e_ident[EI_CLASS] = ELFT::Is64Bits ? ELFCLASS64 : ELFCLASS32; + eHdr->e_ident[EI_DATA] = + ELFT::Endianness == endianness::little ? ELFDATA2LSB : ELFDATA2MSB; eHdr->e_ident[EI_VERSION] = EV_CURRENT; eHdr->e_ident[EI_OSABI] = config->osabi; eHdr->e_ident[EI_ABIVERSION] = getAbiVersion(); -- GitLab From e3ef4612c18845876cda9a13c3435e102f74a3aa Mon Sep 17 00:00:00 2001 From: shamithoke <152091883+shamithoke@users.noreply.github.com> Date: Thu, 11 Apr 2024 00:52:44 +0530 Subject: [PATCH 445/695] Perform bitreverse using AVX512 GFNI for i32 and i64. (#81764) Currently, the lowering operation for bitreverse using Intel AVX512 GFNI only supports byte vectors Extend the operation to i32 and i64. --------- Co-authored-by: shami --- llvm/lib/Target/X86/X86ISelLowering.cpp | 22 ++ llvm/test/CodeGen/X86/bitreverse.ll | 281 ++++----------------- llvm/test/CodeGen/X86/vector-bitreverse.ll | 46 +--- 3 files changed, 84 insertions(+), 265 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 010f9c30ab40..52be35aafb0f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1496,6 +1496,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::TRUNCATE, MVT::v32i32, Custom); setOperationAction(ISD::TRUNCATE, MVT::v32i64, Custom); + if (Subtarget.hasGFNI()) { + setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); + setOperationAction(ISD::BITREVERSE, MVT::i64, Custom); + } + for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { setOperationAction(ISD::SETCC, VT, Custom); setOperationAction(ISD::CTPOP, VT, Custom); @@ -31332,6 +31337,23 @@ static SDValue LowerBITREVERSE(SDValue Op, const X86Subtarget &Subtarget, if (VT.is256BitVector() && !Subtarget.hasInt256()) return splitVectorIntUnary(Op, DAG, DL); + // Lower i32/i64 to GFNI as vXi8 BITREVERSE + BSWAP + if (!VT.isVector()) { + + assert((VT.getScalarType() == MVT::i32) || + (VT.getScalarType() == MVT::i64)); + + MVT VecVT = MVT::getVectorVT(VT, 128 / VT.getSizeInBits()); + SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In); + Res = DAG.getNode(ISD::BITREVERSE, DL, MVT::v16i8, + DAG.getBitcast(MVT::v16i8, Res)); + Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, + DAG.getBitcast(VecVT, Res), DAG.getIntPtrConstant(0, DL)); + return DAG.getNode(ISD::BSWAP, DL, VT, Res); + } + + assert(VT.isVector() && VT.getSizeInBits() >= 128); + // Lower vXi16/vXi32/vXi64 as BSWAP + vXi8 BITREVERSE. if (VT.getScalarType() != MVT::i8) { MVT ByteVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8); diff --git a/llvm/test/CodeGen/X86/bitreverse.ll b/llvm/test/CodeGen/X86/bitreverse.ll index 26b1d64874e5..704563ab1bbf 100644 --- a/llvm/test/CodeGen/X86/bitreverse.ll +++ b/llvm/test/CodeGen/X86/bitreverse.ll @@ -172,26 +172,10 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; ; GFNI-LABEL: test_bitreverse_i64: ; GFNI: # %bb.0: -; GFNI-NEXT: bswapq %rdi -; GFNI-NEXT: movq %rdi, %rax -; GFNI-NEXT: shrq $4, %rax -; GFNI-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F -; GFNI-NEXT: andq %rcx, %rax -; GFNI-NEXT: andq %rcx, %rdi -; GFNI-NEXT: shlq $4, %rdi -; GFNI-NEXT: orq %rax, %rdi -; GFNI-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 -; GFNI-NEXT: movq %rdi, %rcx -; GFNI-NEXT: andq %rax, %rcx -; GFNI-NEXT: shrq $2, %rdi -; GFNI-NEXT: andq %rax, %rdi -; GFNI-NEXT: leaq (%rdi,%rcx,4), %rax -; GFNI-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 -; GFNI-NEXT: movq %rax, %rdx -; GFNI-NEXT: andq %rcx, %rdx -; GFNI-NEXT: shrq %rax -; GFNI-NEXT: andq %rcx, %rax -; GFNI-NEXT: leaq (%rax,%rdx,2), %rax +; GFNI-NEXT: vmovq %rdi, %xmm0 +; GFNI-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 +; GFNI-NEXT: vmovq %xmm0, %rax +; GFNI-NEXT: bswapq %rax ; GFNI-NEXT: retq %b = call i64 @llvm.bitreverse.i64(i64 %a) ret i64 %b @@ -253,24 +237,10 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; ; GFNI-LABEL: test_bitreverse_i32: ; GFNI: # %bb.0: -; GFNI-NEXT: # kill: def $edi killed $edi def $rdi -; GFNI-NEXT: bswapl %edi -; GFNI-NEXT: movl %edi, %eax -; GFNI-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; GFNI-NEXT: shll $4, %eax -; GFNI-NEXT: shrl $4, %edi -; GFNI-NEXT: andl $252645135, %edi # imm = 0xF0F0F0F -; GFNI-NEXT: orl %eax, %edi -; GFNI-NEXT: movl %edi, %eax -; GFNI-NEXT: andl $858993459, %eax # imm = 0x33333333 -; GFNI-NEXT: shrl $2, %edi -; GFNI-NEXT: andl $858993459, %edi # imm = 0x33333333 -; GFNI-NEXT: leal (%rdi,%rax,4), %eax -; GFNI-NEXT: movl %eax, %ecx -; GFNI-NEXT: andl $1431655765, %ecx # imm = 0x55555555 -; GFNI-NEXT: shrl %eax -; GFNI-NEXT: andl $1431655765, %eax # imm = 0x55555555 -; GFNI-NEXT: leal (%rax,%rcx,2), %eax +; GFNI-NEXT: vmovd %edi, %xmm0 +; GFNI-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 +; GFNI-NEXT: vmovd %xmm0, %eax +; GFNI-NEXT: bswapl %eax ; GFNI-NEXT: retq %b = call i32 @llvm.bitreverse.i32(i32 %a) ret i32 %b @@ -335,24 +305,10 @@ define i24 @test_bitreverse_i24(i24 %a) nounwind { ; ; GFNI-LABEL: test_bitreverse_i24: ; GFNI: # %bb.0: -; GFNI-NEXT: # kill: def $edi killed $edi def $rdi -; GFNI-NEXT: bswapl %edi -; GFNI-NEXT: movl %edi, %eax -; GFNI-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; GFNI-NEXT: shll $4, %eax -; GFNI-NEXT: shrl $4, %edi -; GFNI-NEXT: andl $252645135, %edi # imm = 0xF0F0F0F -; GFNI-NEXT: orl %eax, %edi -; GFNI-NEXT: movl %edi, %eax -; GFNI-NEXT: andl $858993459, %eax # imm = 0x33333333 -; GFNI-NEXT: shrl $2, %edi -; GFNI-NEXT: andl $858993459, %edi # imm = 0x33333333 -; GFNI-NEXT: leal (%rdi,%rax,4), %eax -; GFNI-NEXT: movl %eax, %ecx -; GFNI-NEXT: andl $1431655680, %ecx # imm = 0x55555500 -; GFNI-NEXT: shrl %eax -; GFNI-NEXT: andl $1431655680, %eax # imm = 0x55555500 -; GFNI-NEXT: leal (%rax,%rcx,2), %eax +; GFNI-NEXT: vmovd %edi, %xmm0 +; GFNI-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0 +; GFNI-NEXT: vmovd %xmm0, %eax +; GFNI-NEXT: bswapl %eax ; GFNI-NEXT: shrl $8, %eax ; GFNI-NEXT: retq %b = call i24 @llvm.bitreverse.i24(i24 %a) @@ -1412,196 +1368,67 @@ define i528 @large_promotion(i528 %A) nounwind { ; ; GFNI-LABEL: large_promotion: ; GFNI: # %bb.0: -; GFNI-NEXT: pushq %r15 ; GFNI-NEXT: pushq %r14 -; GFNI-NEXT: pushq %r13 -; GFNI-NEXT: pushq %r12 ; GFNI-NEXT: pushq %rbx ; GFNI-NEXT: movq %rdi, %rax -; GFNI-NEXT: movq {{[0-9]+}}(%rsp), %r12 -; GFNI-NEXT: movq {{[0-9]+}}(%rsp), %r15 -; GFNI-NEXT: movq {{[0-9]+}}(%rsp), %rbx -; GFNI-NEXT: movq {{[0-9]+}}(%rsp), %rdi +; GFNI-NEXT: vpbroadcastq {{.*#+}} xmm0 = [9241421688590303745,9241421688590303745] +; GFNI-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %r10 +; GFNI-NEXT: bswapq %r10 +; GFNI-NEXT: vmovq %r9, %xmm1 +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %rdi ; GFNI-NEXT: bswapq %rdi -; GFNI-NEXT: movq %rdi, %r10 -; GFNI-NEXT: shrq $4, %r10 -; GFNI-NEXT: movabsq $1085102592571150095, %r11 # imm = 0xF0F0F0F0F0F0F0F -; GFNI-NEXT: andq %r11, %r10 -; GFNI-NEXT: andq %r11, %rdi -; GFNI-NEXT: shlq $4, %rdi -; GFNI-NEXT: orq %r10, %rdi -; GFNI-NEXT: movabsq $3689348814741910323, %r10 # imm = 0x3333333333333333 -; GFNI-NEXT: movq %rdi, %r14 -; GFNI-NEXT: andq %r10, %r14 -; GFNI-NEXT: shrq $2, %rdi -; GFNI-NEXT: andq %r10, %rdi -; GFNI-NEXT: leaq (%rdi,%r14,4), %rdi -; GFNI-NEXT: movabsq $6148820866244280320, %r14 # imm = 0x5555000000000000 -; GFNI-NEXT: movq %rdi, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %rdi -; GFNI-NEXT: andq %r14, %rdi -; GFNI-NEXT: leaq (%rdi,%r13,2), %rdi -; GFNI-NEXT: bswapq %rbx -; GFNI-NEXT: movq %rbx, %r14 -; GFNI-NEXT: shrq $4, %r14 -; GFNI-NEXT: andq %r11, %r14 -; GFNI-NEXT: andq %r11, %rbx -; GFNI-NEXT: shlq $4, %rbx -; GFNI-NEXT: orq %r14, %rbx -; GFNI-NEXT: movq %rbx, %r14 -; GFNI-NEXT: andq %r10, %r14 -; GFNI-NEXT: shrq $2, %rbx -; GFNI-NEXT: andq %r10, %rbx -; GFNI-NEXT: leaq (%rbx,%r14,4), %rbx -; GFNI-NEXT: movabsq $6148914691236517205, %r14 # imm = 0x5555555555555555 -; GFNI-NEXT: movq %rbx, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %rbx -; GFNI-NEXT: andq %r14, %rbx -; GFNI-NEXT: leaq (%rbx,%r13,2), %rbx -; GFNI-NEXT: shrdq $48, %rbx, %rdi -; GFNI-NEXT: bswapq %r15 -; GFNI-NEXT: movq %r15, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %r15 -; GFNI-NEXT: shlq $4, %r15 -; GFNI-NEXT: orq %r13, %r15 -; GFNI-NEXT: movq %r15, %r13 -; GFNI-NEXT: andq %r10, %r13 -; GFNI-NEXT: shrq $2, %r15 -; GFNI-NEXT: andq %r10, %r15 -; GFNI-NEXT: leaq (%r15,%r13,4), %r15 -; GFNI-NEXT: movq %r15, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %r15 -; GFNI-NEXT: andq %r14, %r15 -; GFNI-NEXT: leaq (%r15,%r13,2), %r15 -; GFNI-NEXT: shrdq $48, %r15, %rbx -; GFNI-NEXT: bswapq %r12 -; GFNI-NEXT: movq %r12, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %r12 -; GFNI-NEXT: shlq $4, %r12 -; GFNI-NEXT: orq %r13, %r12 -; GFNI-NEXT: movq %r12, %r13 -; GFNI-NEXT: andq %r10, %r13 -; GFNI-NEXT: shrq $2, %r12 -; GFNI-NEXT: andq %r10, %r12 -; GFNI-NEXT: leaq (%r12,%r13,4), %r12 -; GFNI-NEXT: movq %r12, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %r12 -; GFNI-NEXT: andq %r14, %r12 -; GFNI-NEXT: leaq (%r12,%r13,2), %r12 -; GFNI-NEXT: shrdq $48, %r12, %r15 -; GFNI-NEXT: bswapq %r9 -; GFNI-NEXT: movq %r9, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %r9 -; GFNI-NEXT: shlq $4, %r9 -; GFNI-NEXT: orq %r13, %r9 -; GFNI-NEXT: movq %r9, %r13 -; GFNI-NEXT: andq %r10, %r13 -; GFNI-NEXT: shrq $2, %r9 -; GFNI-NEXT: andq %r10, %r9 -; GFNI-NEXT: leaq (%r9,%r13,4), %r9 -; GFNI-NEXT: movq %r9, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %r9 -; GFNI-NEXT: andq %r14, %r9 -; GFNI-NEXT: leaq (%r9,%r13,2), %r9 -; GFNI-NEXT: shrdq $48, %r9, %r12 +; GFNI-NEXT: vmovq %r8, %xmm1 +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %r8 ; GFNI-NEXT: bswapq %r8 -; GFNI-NEXT: movq %r8, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %r8 -; GFNI-NEXT: shlq $4, %r8 -; GFNI-NEXT: orq %r13, %r8 -; GFNI-NEXT: movq %r8, %r13 -; GFNI-NEXT: andq %r10, %r13 -; GFNI-NEXT: shrq $2, %r8 -; GFNI-NEXT: andq %r10, %r8 -; GFNI-NEXT: leaq (%r8,%r13,4), %r8 -; GFNI-NEXT: movq %r8, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %r8 -; GFNI-NEXT: andq %r14, %r8 -; GFNI-NEXT: leaq (%r8,%r13,2), %r8 -; GFNI-NEXT: shrdq $48, %r8, %r9 +; GFNI-NEXT: movq %r8, %r9 +; GFNI-NEXT: shldq $16, %rdi, %r9 +; GFNI-NEXT: shldq $16, %r10, %rdi +; GFNI-NEXT: vmovq %rcx, %xmm1 +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %rcx ; GFNI-NEXT: bswapq %rcx -; GFNI-NEXT: movq %rcx, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %rcx -; GFNI-NEXT: shlq $4, %rcx -; GFNI-NEXT: orq %r13, %rcx -; GFNI-NEXT: movq %rcx, %r13 -; GFNI-NEXT: andq %r10, %r13 -; GFNI-NEXT: shrq $2, %rcx -; GFNI-NEXT: andq %r10, %rcx -; GFNI-NEXT: leaq (%rcx,%r13,4), %rcx -; GFNI-NEXT: movq %rcx, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %rcx -; GFNI-NEXT: andq %r14, %rcx -; GFNI-NEXT: leaq (%rcx,%r13,2), %rcx ; GFNI-NEXT: shrdq $48, %rcx, %r8 +; GFNI-NEXT: vmovq %rdx, %xmm1 +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %rdx ; GFNI-NEXT: bswapq %rdx -; GFNI-NEXT: movq %rdx, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %rdx -; GFNI-NEXT: shlq $4, %rdx -; GFNI-NEXT: orq %r13, %rdx -; GFNI-NEXT: movq %rdx, %r13 -; GFNI-NEXT: andq %r10, %r13 -; GFNI-NEXT: shrq $2, %rdx -; GFNI-NEXT: andq %r10, %rdx -; GFNI-NEXT: leaq (%rdx,%r13,4), %rdx -; GFNI-NEXT: movq %rdx, %r13 -; GFNI-NEXT: andq %r14, %r13 -; GFNI-NEXT: shrq %rdx -; GFNI-NEXT: andq %r14, %rdx -; GFNI-NEXT: leaq (%rdx,%r13,2), %rdx ; GFNI-NEXT: shrdq $48, %rdx, %rcx +; GFNI-NEXT: vmovq %rsi, %xmm1 +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %rsi ; GFNI-NEXT: bswapq %rsi -; GFNI-NEXT: movq %rsi, %r13 -; GFNI-NEXT: shrq $4, %r13 -; GFNI-NEXT: andq %r11, %r13 -; GFNI-NEXT: andq %r11, %rsi -; GFNI-NEXT: shlq $4, %rsi -; GFNI-NEXT: orq %r13, %rsi -; GFNI-NEXT: movq %rsi, %r11 -; GFNI-NEXT: andq %r10, %r11 -; GFNI-NEXT: shrq $2, %rsi -; GFNI-NEXT: andq %r10, %rsi -; GFNI-NEXT: leaq (%rsi,%r11,4), %rsi -; GFNI-NEXT: movq %rsi, %r10 -; GFNI-NEXT: andq %r14, %r10 -; GFNI-NEXT: shrq %rsi -; GFNI-NEXT: andq %r14, %rsi -; GFNI-NEXT: leaq (%rsi,%r10,2), %rsi ; GFNI-NEXT: shrdq $48, %rsi, %rdx +; GFNI-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %r11 +; GFNI-NEXT: bswapq %r11 +; GFNI-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm1 +; GFNI-NEXT: vmovq %xmm1, %rbx +; GFNI-NEXT: bswapq %rbx +; GFNI-NEXT: shrdq $48, %rbx, %r11 +; GFNI-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; GFNI-NEXT: vgf2p8affineqb $0, %xmm0, %xmm1, %xmm0 +; GFNI-NEXT: vmovq %xmm0, %r14 +; GFNI-NEXT: bswapq %r14 +; GFNI-NEXT: shrdq $48, %r14, %rbx +; GFNI-NEXT: shrdq $48, %r10, %r14 ; GFNI-NEXT: shrq $48, %rsi +; GFNI-NEXT: movq %r14, 16(%rax) +; GFNI-NEXT: movq %rbx, 8(%rax) +; GFNI-NEXT: movq %r11, (%rax) ; GFNI-NEXT: movq %rdx, 56(%rax) ; GFNI-NEXT: movq %rcx, 48(%rax) ; GFNI-NEXT: movq %r8, 40(%rax) ; GFNI-NEXT: movq %r9, 32(%rax) -; GFNI-NEXT: movq %r12, 24(%rax) -; GFNI-NEXT: movq %r15, 16(%rax) -; GFNI-NEXT: movq %rbx, 8(%rax) -; GFNI-NEXT: movq %rdi, (%rax) +; GFNI-NEXT: movq %rdi, 24(%rax) ; GFNI-NEXT: movw %si, 64(%rax) ; GFNI-NEXT: popq %rbx -; GFNI-NEXT: popq %r12 -; GFNI-NEXT: popq %r13 ; GFNI-NEXT: popq %r14 -; GFNI-NEXT: popq %r15 ; GFNI-NEXT: retq %Z = call i528 @llvm.bitreverse.i528(i528 %A) ret i528 %Z diff --git a/llvm/test/CodeGen/X86/vector-bitreverse.ll b/llvm/test/CodeGen/X86/vector-bitreverse.ll index d3f357cd1795..1c5326d35bb0 100644 --- a/llvm/test/CodeGen/X86/vector-bitreverse.ll +++ b/llvm/test/CodeGen/X86/vector-bitreverse.ll @@ -276,24 +276,10 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; ; GFNIAVX-LABEL: test_bitreverse_i32: ; GFNIAVX: # %bb.0: -; GFNIAVX-NEXT: # kill: def $edi killed $edi def $rdi -; GFNIAVX-NEXT: bswapl %edi -; GFNIAVX-NEXT: movl %edi, %eax -; GFNIAVX-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; GFNIAVX-NEXT: shll $4, %eax -; GFNIAVX-NEXT: shrl $4, %edi -; GFNIAVX-NEXT: andl $252645135, %edi # imm = 0xF0F0F0F -; GFNIAVX-NEXT: orl %eax, %edi -; GFNIAVX-NEXT: movl %edi, %eax -; GFNIAVX-NEXT: andl $858993459, %eax # imm = 0x33333333 -; GFNIAVX-NEXT: shrl $2, %edi -; GFNIAVX-NEXT: andl $858993459, %edi # imm = 0x33333333 -; GFNIAVX-NEXT: leal (%rdi,%rax,4), %eax -; GFNIAVX-NEXT: movl %eax, %ecx -; GFNIAVX-NEXT: andl $1431655765, %ecx # imm = 0x55555555 -; GFNIAVX-NEXT: shrl %eax -; GFNIAVX-NEXT: andl $1431655765, %eax # imm = 0x55555555 -; GFNIAVX-NEXT: leal (%rax,%rcx,2), %eax +; GFNIAVX-NEXT: vmovd %edi, %xmm0 +; GFNIAVX-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; GFNIAVX-NEXT: vmovd %xmm0, %eax +; GFNIAVX-NEXT: bswapl %eax ; GFNIAVX-NEXT: retq %b = call i32 @llvm.bitreverse.i32(i32 %a) ret i32 %b @@ -381,26 +367,10 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; ; GFNIAVX-LABEL: test_bitreverse_i64: ; GFNIAVX: # %bb.0: -; GFNIAVX-NEXT: bswapq %rdi -; GFNIAVX-NEXT: movq %rdi, %rax -; GFNIAVX-NEXT: shrq $4, %rax -; GFNIAVX-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F -; GFNIAVX-NEXT: andq %rcx, %rax -; GFNIAVX-NEXT: andq %rcx, %rdi -; GFNIAVX-NEXT: shlq $4, %rdi -; GFNIAVX-NEXT: orq %rax, %rdi -; GFNIAVX-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 -; GFNIAVX-NEXT: movq %rdi, %rcx -; GFNIAVX-NEXT: andq %rax, %rcx -; GFNIAVX-NEXT: shrq $2, %rdi -; GFNIAVX-NEXT: andq %rax, %rdi -; GFNIAVX-NEXT: leaq (%rdi,%rcx,4), %rax -; GFNIAVX-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 -; GFNIAVX-NEXT: movq %rax, %rdx -; GFNIAVX-NEXT: andq %rcx, %rdx -; GFNIAVX-NEXT: shrq %rax -; GFNIAVX-NEXT: andq %rcx, %rax -; GFNIAVX-NEXT: leaq (%rax,%rdx,2), %rax +; GFNIAVX-NEXT: vmovq %rdi, %xmm0 +; GFNIAVX-NEXT: vgf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; GFNIAVX-NEXT: vmovq %xmm0, %rax +; GFNIAVX-NEXT: bswapq %rax ; GFNIAVX-NEXT: retq %b = call i64 @llvm.bitreverse.i64(i64 %a) ret i64 %b -- GitLab From 7549b45825a05fc24fcdbacf006461165aa042cb Mon Sep 17 00:00:00 2001 From: martinboehme Date: Wed, 10 Apr 2024 21:27:10 +0200 Subject: [PATCH 446/695] Revert "[clang][dataflow] Propagate locations from result objects to initializers." (#88315) Reverts llvm/llvm-project#87320 This is causing buildbots to fail because `isOriginalRecordConstructor()` is now unused. --- .../FlowSensitive/DataflowEnvironment.h | 64 +-- .../FlowSensitive/DataflowEnvironment.cpp | 405 +++++------------- clang/lib/Analysis/FlowSensitive/Transfer.cpp | 176 ++++---- .../TypeErasedDataflowAnalysis.cpp | 13 +- .../FlowSensitive/DataflowEnvironmentTest.cpp | 43 -- .../Analysis/FlowSensitive/TransferTest.cpp | 172 +++----- 6 files changed, 283 insertions(+), 590 deletions(-) diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index 706664d7db1c..9a65f76cdf56 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -30,7 +30,6 @@ #include "llvm/ADT/MapVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" -#include #include #include @@ -345,6 +344,17 @@ public: /// location of the result object to pass in `this`, even though prvalues are /// otherwise not associated with storage locations. /// + /// FIXME: Currently, this simply returns a stable storage location for `E`, + /// but this doesn't do the right thing in scenarios like the following: + /// ``` + /// MyClass c = some_condition()? MyClass(foo) : MyClass(bar); + /// ``` + /// Here, `MyClass(foo)` and `MyClass(bar)` will have two different storage + /// locations, when in fact their storage locations should be the same. + /// Eventually, we want to propagate storage locations from result objects + /// down to the prvalues that initialize them, similar to the way that this is + /// done in Clang's CodeGen. + /// /// Requirements: /// `E` must be a prvalue of record type. RecordStorageLocation & @@ -452,13 +462,7 @@ public: /// Initializes the fields (including synthetic fields) of `Loc` with values, /// unless values of the field type are not supported or we hit one of the /// limits at which we stop producing values. - /// If `Type` is provided, initializes only those fields that are modeled for - /// `Type`; this is intended for use in cases where `Loc` is a derived type - /// and we only want to initialize the fields of a base type. - void initializeFieldsWithValues(RecordStorageLocation &Loc, QualType Type); - void initializeFieldsWithValues(RecordStorageLocation &Loc) { - initializeFieldsWithValues(Loc, Loc.getType()); - } + void initializeFieldsWithValues(RecordStorageLocation &Loc); /// Assigns `Val` as the value of `Loc` in the environment. void setValue(const StorageLocation &Loc, Value &Val); @@ -649,9 +653,6 @@ public: LLVM_DUMP_METHOD void dump(raw_ostream &OS) const; private: - using PrValueToResultObject = - llvm::DenseMap; - // The copy-constructor is for use in fork() only. Environment(const Environment &) = default; @@ -681,10 +682,8 @@ private: /// Initializes the fields (including synthetic fields) of `Loc` with values, /// unless values of the field type are not supported or we hit one of the /// limits at which we stop producing values (controlled by `Visited`, - /// `Depth`, and `CreatedValuesCount`). If `Type` is different from - /// `Loc.getType()`, initializes only those fields that are modeled for - /// `Type`. - void initializeFieldsWithValues(RecordStorageLocation &Loc, QualType Type, + /// `Depth`, and `CreatedValuesCount`). + void initializeFieldsWithValues(RecordStorageLocation &Loc, llvm::DenseSet &Visited, int Depth, int &CreatedValuesCount); @@ -703,45 +702,22 @@ private: /// and functions referenced in `FuncDecl`. `FuncDecl` must have a body. void initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl); - static PrValueToResultObject - buildResultObjectMap(DataflowAnalysisContext *DACtx, - const FunctionDecl *FuncDecl, - RecordStorageLocation *ThisPointeeLoc, - RecordStorageLocation *LocForRecordReturnVal); - // `DACtx` is not null and not owned by this object. DataflowAnalysisContext *DACtx; - // FIXME: move the fields `CallStack`, `ResultObjectMap`, `ReturnVal`, - // `ReturnLoc` and `ThisPointeeLoc` into a separate call-context object, - // shared between environments in the same call. + // FIXME: move the fields `CallStack`, `ReturnVal`, `ReturnLoc` and + // `ThisPointeeLoc` into a separate call-context object, shared between + // environments in the same call. // https://github.com/llvm/llvm-project/issues/59005 // `DeclContext` of the block being analysed if provided. std::vector CallStack; - // Maps from prvalues of record type to their result objects. Shared between - // all environments for the same function. - // FIXME: It's somewhat unsatisfactory that we have to use a `shared_ptr` - // here, though the cost is acceptable: The overhead of a `shared_ptr` is - // incurred when it is copied, and this happens only relatively rarely (when - // we fork the environment). The need for a `shared_ptr` will go away once we - // introduce a shared call-context object (see above). - std::shared_ptr ResultObjectMap; - - // The following three member variables handle various different types of - // return values. - // - If the return type is not a reference and not a record: Value returned - // by the function. + // Value returned by the function (if it has non-reference return type). Value *ReturnVal = nullptr; - // - If the return type is a reference: Storage location of the reference - // returned by the function. + // Storage location of the reference returned by the function (if it has + // reference return type). StorageLocation *ReturnLoc = nullptr; - // - If the return type is a record or the function being analyzed is a - // constructor: Storage location into which the return value should be - // constructed. - RecordStorageLocation *LocForRecordReturnVal = nullptr; - // The storage location of the `this` pointee. Should only be null if the // function being analyzed is only a function and not a method. RecordStorageLocation *ThisPointeeLoc = nullptr; diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 6c796b4ad923..1bfa7ebcfd50 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -15,7 +15,6 @@ #include "clang/Analysis/FlowSensitive/DataflowEnvironment.h" #include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" -#include "clang/AST/RecursiveASTVisitor.h" #include "clang/AST/Type.h" #include "clang/Analysis/FlowSensitive/DataflowLattice.h" #include "clang/Analysis/FlowSensitive/Value.h" @@ -27,8 +26,6 @@ #include #include -#define DEBUG_TYPE "dataflow" - namespace clang { namespace dataflow { @@ -357,8 +354,6 @@ getFieldsGlobalsAndFuncs(const Stmt &S, FieldSet &Fields, for (auto *Child : S.children()) if (Child != nullptr) getFieldsGlobalsAndFuncs(*Child, Fields, Vars, Funcs); - if (const auto *DefaultArg = dyn_cast(&S)) - getFieldsGlobalsAndFuncs(*DefaultArg->getExpr(), Fields, Vars, Funcs); if (const auto *DefaultInit = dyn_cast(&S)) getFieldsGlobalsAndFuncs(*DefaultInit->getExpr(), Fields, Vars, Funcs); @@ -391,186 +386,6 @@ getFieldsGlobalsAndFuncs(const Stmt &S, FieldSet &Fields, } } -namespace { - -// Visitor that builds a map from record prvalues to result objects. -// This traverses the body of the function to be analyzed; for each result -// object that it encounters, it propagates the storage location of the result -// object to all record prvalues that can initialize it. -class ResultObjectVisitor : public RecursiveASTVisitor { -public: - // `ResultObjectMap` will be filled with a map from record prvalues to result - // object. If the function being analyzed returns a record by value, - // `LocForRecordReturnVal` is the location to which this record should be - // written; otherwise, it is null. - explicit ResultObjectVisitor( - llvm::DenseMap &ResultObjectMap, - RecordStorageLocation *LocForRecordReturnVal, - DataflowAnalysisContext &DACtx) - : ResultObjectMap(ResultObjectMap), - LocForRecordReturnVal(LocForRecordReturnVal), DACtx(DACtx) {} - - bool shouldVisitImplicitCode() { return true; } - - bool shouldVisitLambdaBody() const { return false; } - - // Traverse all member and base initializers of `Ctor`. This function is not - // called by `RecursiveASTVisitor`; it should be called manually if we are - // analyzing a constructor. `ThisPointeeLoc` is the storage location that - // `this` points to. - void TraverseConstructorInits(const CXXConstructorDecl *Ctor, - RecordStorageLocation *ThisPointeeLoc) { - assert(ThisPointeeLoc != nullptr); - for (const CXXCtorInitializer *Init : Ctor->inits()) { - Expr *InitExpr = Init->getInit(); - if (FieldDecl *Field = Init->getMember(); - Field != nullptr && Field->getType()->isRecordType()) { - PropagateResultObject(InitExpr, cast( - ThisPointeeLoc->getChild(*Field))); - } else if (Init->getBaseClass()) { - PropagateResultObject(InitExpr, ThisPointeeLoc); - } - - // Ensure that any result objects within `InitExpr` (e.g. temporaries) - // are also propagated to the prvalues that initialize them. - TraverseStmt(InitExpr); - - // If this is a `CXXDefaultInitExpr`, also propagate any result objects - // within the default expression. - if (auto *DefaultInit = dyn_cast(InitExpr)) - TraverseStmt(DefaultInit->getExpr()); - } - } - - bool TraverseBindingDecl(BindingDecl *BD) { - // `RecursiveASTVisitor` doesn't traverse holding variables for - // `BindingDecl`s by itself, so we need to tell it to. - if (VarDecl *HoldingVar = BD->getHoldingVar()) - TraverseDecl(HoldingVar); - return RecursiveASTVisitor::TraverseBindingDecl(BD); - } - - bool VisitVarDecl(VarDecl *VD) { - if (VD->getType()->isRecordType() && VD->hasInit()) - PropagateResultObject( - VD->getInit(), - &cast(DACtx.getStableStorageLocation(*VD))); - return true; - } - - bool VisitMaterializeTemporaryExpr(MaterializeTemporaryExpr *MTE) { - if (MTE->getType()->isRecordType()) - PropagateResultObject( - MTE->getSubExpr(), - &cast(DACtx.getStableStorageLocation(*MTE))); - return true; - } - - bool VisitReturnStmt(ReturnStmt *Return) { - Expr *RetValue = Return->getRetValue(); - if (RetValue != nullptr && RetValue->getType()->isRecordType() && - RetValue->isPRValue()) - PropagateResultObject(RetValue, LocForRecordReturnVal); - return true; - } - - bool VisitExpr(Expr *E) { - // Clang's AST can have record-type prvalues without a result object -- for - // example as full-expressions contained in a compound statement or as - // arguments of call expressions. We notice this if we get here and a - // storage location has not yet been associated with `E`. In this case, - // treat this as if it was a `MaterializeTemporaryExpr`. - if (E->isPRValue() && E->getType()->isRecordType() && - !ResultObjectMap.contains(E)) - PropagateResultObject( - E, &cast(DACtx.getStableStorageLocation(*E))); - return true; - } - - // Assigns `Loc` as the result object location of `E`, then propagates the - // location to all lower-level prvalues that initialize the same object as - // `E` (or one of its base classes or member variables). - void PropagateResultObject(Expr *E, RecordStorageLocation *Loc) { - if (!E->isPRValue() || !E->getType()->isRecordType()) { - assert(false); - // Ensure we don't propagate the result object if we hit this in a - // release build. - return; - } - - ResultObjectMap[E] = Loc; - - // The following AST node kinds are "original initializers": They are the - // lowest-level AST node that initializes a given object, and nothing - // below them can initialize the same object (or part of it). - if (isa(E) || isa(E) || isa(E) || - isa(E) || isa(E) || - isa(E)) { - return; - } - - if (auto *InitList = dyn_cast(E)) { - if (!InitList->isSemanticForm()) - return; - if (InitList->isTransparent()) { - PropagateResultObject(InitList->getInit(0), Loc); - return; - } - - RecordInitListHelper InitListHelper(InitList); - - for (auto [Base, Init] : InitListHelper.base_inits()) { - assert(Base->getType().getCanonicalType() == - Init->getType().getCanonicalType()); - - // Storage location for the base class is the same as that of the - // derived class because we "flatten" the object hierarchy and put all - // fields in `RecordStorageLocation` of the derived class. - PropagateResultObject(Init, Loc); - } - - for (auto [Field, Init] : InitListHelper.field_inits()) { - // Fields of non-record type are handled in - // `TransferVisitor::VisitInitListExpr()`. - if (!Field->getType()->isRecordType()) - continue; - PropagateResultObject( - Init, cast(Loc->getChild(*Field))); - } - return; - } - - if (auto *Op = dyn_cast(E); Op && Op->isCommaOp()) { - PropagateResultObject(Op->getRHS(), Loc); - return; - } - - if (auto *Cond = dyn_cast(E)) { - PropagateResultObject(Cond->getTrueExpr(), Loc); - PropagateResultObject(Cond->getFalseExpr(), Loc); - return; - } - - // All other expression nodes that propagate a record prvalue should have - // exactly one child. - SmallVector Children(E->child_begin(), E->child_end()); - LLVM_DEBUG({ - if (Children.size() != 1) - E->dump(); - }); - assert(Children.size() == 1); - for (Stmt *S : Children) - PropagateResultObject(cast(S), Loc); - } - -private: - llvm::DenseMap &ResultObjectMap; - RecordStorageLocation *LocForRecordReturnVal; - DataflowAnalysisContext &DACtx; -}; - -} // namespace - Environment::Environment(DataflowAnalysisContext &DACtx) : DACtx(&DACtx), FlowConditionToken(DACtx.arena().makeFlowConditionToken()) {} @@ -586,23 +401,17 @@ void Environment::initialize() { if (DeclCtx == nullptr) return; - const auto *FuncDecl = dyn_cast(DeclCtx); - if (FuncDecl == nullptr) - return; - - assert(FuncDecl->doesThisDeclarationHaveABody()); + if (const auto *FuncDecl = dyn_cast(DeclCtx)) { + assert(FuncDecl->doesThisDeclarationHaveABody()); - initFieldsGlobalsAndFuncs(FuncDecl); + initFieldsGlobalsAndFuncs(FuncDecl); - for (const auto *ParamDecl : FuncDecl->parameters()) { - assert(ParamDecl != nullptr); - setStorageLocation(*ParamDecl, createObject(*ParamDecl, nullptr)); + for (const auto *ParamDecl : FuncDecl->parameters()) { + assert(ParamDecl != nullptr); + setStorageLocation(*ParamDecl, createObject(*ParamDecl, nullptr)); + } } - if (FuncDecl->getReturnType()->isRecordType()) - LocForRecordReturnVal = &cast( - createStorageLocation(FuncDecl->getReturnType())); - if (const auto *MethodDecl = dyn_cast(DeclCtx)) { auto *Parent = MethodDecl->getParent(); assert(Parent != nullptr); @@ -635,12 +444,6 @@ void Environment::initialize() { initializeFieldsWithValues(ThisLoc); } } - - // We do this below the handling of `CXXMethodDecl` above so that we can - // be sure that the storage location for `this` has been set. - ResultObjectMap = std::make_shared( - buildResultObjectMap(DACtx, FuncDecl, getThisPointeeStorageLocation(), - LocForRecordReturnVal)); } // FIXME: Add support for resetting globals after function calls to enable @@ -681,18 +484,13 @@ void Environment::initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl) { if (getStorageLocation(*D) != nullptr) continue; - // We don't run transfer functions on the initializers of global variables, - // so they won't be associated with a value or storage location. We - // therefore intentionally don't pass an initializer to `createObject()`; - // in particular, this ensures that `createObject()` will initialize the - // fields of record-type variables with values. - setStorageLocation(*D, createObject(*D, nullptr)); + setStorageLocation(*D, createObject(*D)); } for (const FunctionDecl *FD : Funcs) { if (getStorageLocation(*FD) != nullptr) continue; - auto &Loc = createStorageLocation(*FD); + auto &Loc = createStorageLocation(FD->getType()); setStorageLocation(*FD, Loc); } } @@ -721,9 +519,6 @@ Environment Environment::pushCall(const CallExpr *Call) const { } } - if (Call->getType()->isRecordType() && Call->isPRValue()) - Env.LocForRecordReturnVal = &Env.getResultObjectLocation(*Call); - Env.pushCallInternal(Call->getDirectCallee(), llvm::ArrayRef(Call->getArgs(), Call->getNumArgs())); @@ -734,7 +529,6 @@ Environment Environment::pushCall(const CXXConstructExpr *Call) const { Environment Env(*this); Env.ThisPointeeLoc = &Env.getResultObjectLocation(*Call); - Env.LocForRecordReturnVal = &Env.getResultObjectLocation(*Call); Env.pushCallInternal(Call->getConstructor(), llvm::ArrayRef(Call->getArgs(), Call->getNumArgs())); @@ -763,10 +557,6 @@ void Environment::pushCallInternal(const FunctionDecl *FuncDecl, const VarDecl *Param = *ParamIt; setStorageLocation(*Param, createObject(*Param, Args[ArgIndex])); } - - ResultObjectMap = std::make_shared( - buildResultObjectMap(DACtx, FuncDecl, getThisPointeeStorageLocation(), - LocForRecordReturnVal)); } void Environment::popCall(const CallExpr *Call, const Environment &CalleeEnv) { @@ -810,9 +600,6 @@ bool Environment::equivalentTo(const Environment &Other, if (ReturnLoc != Other.ReturnLoc) return false; - if (LocForRecordReturnVal != Other.LocForRecordReturnVal) - return false; - if (ThisPointeeLoc != Other.ThisPointeeLoc) return false; @@ -836,10 +623,8 @@ LatticeEffect Environment::widen(const Environment &PrevEnv, assert(DACtx == PrevEnv.DACtx); assert(ReturnVal == PrevEnv.ReturnVal); assert(ReturnLoc == PrevEnv.ReturnLoc); - assert(LocForRecordReturnVal == PrevEnv.LocForRecordReturnVal); assert(ThisPointeeLoc == PrevEnv.ThisPointeeLoc); assert(CallStack == PrevEnv.CallStack); - assert(ResultObjectMap == PrevEnv.ResultObjectMap); auto Effect = LatticeEffect::Unchanged; @@ -871,16 +656,12 @@ Environment Environment::join(const Environment &EnvA, const Environment &EnvB, Environment::ValueModel &Model, ExprJoinBehavior ExprBehavior) { assert(EnvA.DACtx == EnvB.DACtx); - assert(EnvA.LocForRecordReturnVal == EnvB.LocForRecordReturnVal); assert(EnvA.ThisPointeeLoc == EnvB.ThisPointeeLoc); assert(EnvA.CallStack == EnvB.CallStack); - assert(EnvA.ResultObjectMap == EnvB.ResultObjectMap); Environment JoinedEnv(*EnvA.DACtx); JoinedEnv.CallStack = EnvA.CallStack; - JoinedEnv.ResultObjectMap = EnvA.ResultObjectMap; - JoinedEnv.LocForRecordReturnVal = EnvA.LocForRecordReturnVal; JoinedEnv.ThisPointeeLoc = EnvA.ThisPointeeLoc; if (EnvA.ReturnVal == nullptr || EnvB.ReturnVal == nullptr) { @@ -949,12 +730,6 @@ StorageLocation &Environment::createStorageLocation(const Expr &E) { void Environment::setStorageLocation(const ValueDecl &D, StorageLocation &Loc) { assert(!DeclToLoc.contains(&D)); - // The only kinds of declarations that may have a "variable" storage location - // are declarations of reference type and `BindingDecl`. For all other - // declaration, the storage location should be the stable storage location - // returned by `createStorageLocation()`. - assert(D.getType()->isReferenceType() || isa(D) || - &Loc == &createStorageLocation(D)); DeclToLoc[&D] = &Loc; } @@ -1016,29 +791,50 @@ Environment::getResultObjectLocation(const Expr &RecordPRValue) const { assert(RecordPRValue.getType()->isRecordType()); assert(RecordPRValue.isPRValue()); - assert(ResultObjectMap != nullptr); - RecordStorageLocation *Loc = ResultObjectMap->lookup(&RecordPRValue); - assert(Loc != nullptr); - // In release builds, use the "stable" storage location if the map lookup - // failed. - if (Loc == nullptr) + // Returns a storage location that we can use if assertions fail. + auto FallbackForAssertFailure = + [this, &RecordPRValue]() -> RecordStorageLocation & { return cast( DACtx->getStableStorageLocation(RecordPRValue)); - return *Loc; + }; + + if (isOriginalRecordConstructor(RecordPRValue)) { + auto *Val = cast_or_null(getValue(RecordPRValue)); + // The builtin transfer function should have created a `RecordValue` for all + // original record constructors. + assert(Val); + if (!Val) + return FallbackForAssertFailure(); + return Val->getLoc(); + } + + if (auto *Op = dyn_cast(&RecordPRValue); + Op && Op->isCommaOp()) { + return getResultObjectLocation(*Op->getRHS()); + } + + // All other expression nodes that propagate a record prvalue should have + // exactly one child. + llvm::SmallVector children(RecordPRValue.child_begin(), + RecordPRValue.child_end()); + assert(children.size() == 1); + if (children.empty()) + return FallbackForAssertFailure(); + + return getResultObjectLocation(*cast(children[0])); } PointerValue &Environment::getOrCreateNullPointerValue(QualType PointeeType) { return DACtx->getOrCreateNullPointerValue(PointeeType); } -void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, - QualType Type) { +void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc) { llvm::DenseSet Visited; int CreatedValuesCount = 0; - initializeFieldsWithValues(Loc, Type, Visited, 0, CreatedValuesCount); + initializeFieldsWithValues(Loc, Visited, 0, CreatedValuesCount); if (CreatedValuesCount > MaxCompositeValueSize) { - llvm::errs() << "Attempting to initialize a huge value of type: " << Type - << '\n'; + llvm::errs() << "Attempting to initialize a huge value of type: " + << Loc.getType() << '\n'; } } @@ -1052,7 +848,8 @@ void Environment::setValue(const Expr &E, Value &Val) { const Expr &CanonE = ignoreCFGOmittedNodes(E); if (auto *RecordVal = dyn_cast(&Val)) { - assert(&RecordVal->getLoc() == &getResultObjectLocation(CanonE)); + assert(isOriginalRecordConstructor(CanonE) || + &RecordVal->getLoc() == &getResultObjectLocation(CanonE)); (void)RecordVal; } @@ -1131,8 +928,7 @@ Value *Environment::createValueUnlessSelfReferential( if (Type->isRecordType()) { CreatedValuesCount++; auto &Loc = cast(createStorageLocation(Type)); - initializeFieldsWithValues(Loc, Loc.getType(), Visited, Depth, - CreatedValuesCount); + initializeFieldsWithValues(Loc, Visited, Depth, CreatedValuesCount); return &refreshRecordValue(Loc, *this); } @@ -1164,7 +960,6 @@ Environment::createLocAndMaybeValue(QualType Ty, } void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, - QualType Type, llvm::DenseSet &Visited, int Depth, int &CreatedValuesCount) { @@ -1172,8 +967,8 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, if (FieldType->isRecordType()) { auto &FieldRecordLoc = cast(FieldLoc); setValue(FieldRecordLoc, create(FieldRecordLoc)); - initializeFieldsWithValues(FieldRecordLoc, FieldRecordLoc.getType(), - Visited, Depth + 1, CreatedValuesCount); + initializeFieldsWithValues(FieldRecordLoc, Visited, Depth + 1, + CreatedValuesCount); } else { if (!Visited.insert(FieldType.getCanonicalType()).second) return; @@ -1184,7 +979,7 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, } }; - for (const FieldDecl *Field : DACtx->getModeledFields(Type)) { + for (const auto &[Field, FieldLoc] : Loc.children()) { assert(Field != nullptr); QualType FieldType = Field->getType(); @@ -1193,12 +988,14 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, &createLocAndMaybeValue(FieldType, Visited, Depth + 1, CreatedValuesCount)); } else { - StorageLocation *FieldLoc = Loc.getChild(*Field); assert(FieldLoc != nullptr); initField(FieldType, *FieldLoc); } } - for (const auto &[FieldName, FieldType] : DACtx->getSyntheticFields(Type)) { + for (const auto &[FieldName, FieldLoc] : Loc.synthetic_fields()) { + assert(FieldLoc != nullptr); + QualType FieldType = FieldLoc->getType(); + // Synthetic fields cannot have reference type, so we don't need to deal // with this case. assert(!FieldType->isReferenceType()); @@ -1225,36 +1022,38 @@ StorageLocation &Environment::createObjectInternal(const ValueDecl *D, return createObjectInternal(D, Ty.getNonReferenceType(), nullptr); } + Value *Val = nullptr; + if (InitExpr) { + // In the (few) cases where an expression is intentionally + // "uninterpreted", `InitExpr` is not associated with a value. There are + // two ways to handle this situation: propagate the status, so that + // uninterpreted initializers result in uninterpreted variables, or + // provide a default value. We choose the latter so that later refinements + // of the variable can be used for reasoning about the surrounding code. + // For this reason, we let this case be handled by the `createValue()` + // call below. + // + // FIXME. If and when we interpret all language cases, change this to + // assert that `InitExpr` is interpreted, rather than supplying a + // default value (assuming we don't update the environment API to return + // references). + Val = getValue(*InitExpr); + + if (!Val && isa(InitExpr) && + InitExpr->getType()->isPointerType()) + Val = &getOrCreateNullPointerValue(InitExpr->getType()->getPointeeType()); + } + if (!Val) + Val = createValue(Ty); + + if (Ty->isRecordType()) + return cast(Val)->getLoc(); + StorageLocation &Loc = D ? createStorageLocation(*D) : createStorageLocation(Ty); - if (Ty->isRecordType()) { - auto &RecordLoc = cast(Loc); - if (!InitExpr) - initializeFieldsWithValues(RecordLoc); - refreshRecordValue(RecordLoc, *this); - } else { - Value *Val = nullptr; - if (InitExpr) - // In the (few) cases where an expression is intentionally - // "uninterpreted", `InitExpr` is not associated with a value. There are - // two ways to handle this situation: propagate the status, so that - // uninterpreted initializers result in uninterpreted variables, or - // provide a default value. We choose the latter so that later refinements - // of the variable can be used for reasoning about the surrounding code. - // For this reason, we let this case be handled by the `createValue()` - // call below. - // - // FIXME. If and when we interpret all language cases, change this to - // assert that `InitExpr` is interpreted, rather than supplying a - // default value (assuming we don't update the environment API to return - // references). - Val = getValue(*InitExpr); - if (!Val) - Val = createValue(Ty); - if (Val) - setValue(Loc, *Val); - } + if (Val) + setValue(Loc, *Val); return Loc; } @@ -1273,8 +1072,6 @@ bool Environment::allows(const Formula &F) const { void Environment::dump(raw_ostream &OS) const { llvm::DenseMap LocToName; - if (LocForRecordReturnVal != nullptr) - LocToName[LocForRecordReturnVal] = "(returned record)"; if (ThisPointeeLoc != nullptr) LocToName[ThisPointeeLoc] = "this"; @@ -1305,9 +1102,6 @@ void Environment::dump(raw_ostream &OS) const { if (auto Iter = LocToName.find(ReturnLoc); Iter != LocToName.end()) OS << " (" << Iter->second << ")"; OS << "\n"; - } else if (Func->getReturnType()->isRecordType() || - isa(Func)) { - OS << "LocForRecordReturnVal: " << LocForRecordReturnVal << "\n"; } else if (!Func->getReturnType()->isVoidType()) { if (ReturnVal == nullptr) OS << "ReturnVal: nullptr\n"; @@ -1328,22 +1122,6 @@ void Environment::dump() const { dump(llvm::dbgs()); } -Environment::PrValueToResultObject Environment::buildResultObjectMap( - DataflowAnalysisContext *DACtx, const FunctionDecl *FuncDecl, - RecordStorageLocation *ThisPointeeLoc, - RecordStorageLocation *LocForRecordReturnVal) { - assert(FuncDecl->doesThisDeclarationHaveABody()); - - PrValueToResultObject Map; - - ResultObjectVisitor Visitor(Map, LocForRecordReturnVal, *DACtx); - if (const auto *Ctor = dyn_cast(FuncDecl)) - Visitor.TraverseConstructorInits(Ctor, ThisPointeeLoc); - Visitor.TraverseStmt(FuncDecl->getBody()); - - return Map; -} - RecordStorageLocation *getImplicitObjectLocation(const CXXMemberCallExpr &MCE, const Environment &Env) { Expr *ImplicitObject = MCE.getImplicitObjectArgument(); @@ -1438,11 +1216,24 @@ RecordValue &refreshRecordValue(RecordStorageLocation &Loc, Environment &Env) { RecordValue &refreshRecordValue(const Expr &Expr, Environment &Env) { assert(Expr.getType()->isRecordType()); - if (Expr.isPRValue()) - refreshRecordValue(Env.getResultObjectLocation(Expr), Env); + if (Expr.isPRValue()) { + if (auto *ExistingVal = Env.get(Expr)) { + auto &NewVal = Env.create(ExistingVal->getLoc()); + Env.setValue(Expr, NewVal); + Env.setValue(NewVal.getLoc(), NewVal); + return NewVal; + } - if (auto *Loc = Env.get(Expr)) - refreshRecordValue(*Loc, Env); + auto &NewVal = *cast(Env.createValue(Expr.getType())); + Env.setValue(Expr, NewVal); + return NewVal; + } + + if (auto *Loc = Env.get(Expr)) { + auto &NewVal = Env.create(*Loc); + Env.setValue(*Loc, NewVal); + return NewVal; + } auto &NewVal = *cast(Env.createValue(Expr.getType())); Env.setStorageLocation(Expr, NewVal.getLoc()); diff --git a/clang/lib/Analysis/FlowSensitive/Transfer.cpp b/clang/lib/Analysis/FlowSensitive/Transfer.cpp index 88a9c0eccbeb..0a2e8368d541 100644 --- a/clang/lib/Analysis/FlowSensitive/Transfer.cpp +++ b/clang/lib/Analysis/FlowSensitive/Transfer.cpp @@ -460,9 +460,11 @@ public: // So make sure we have a value if we didn't propagate one above. if (S->isPRValue() && S->getType()->isRecordType()) { if (Env.getValue(*S) == nullptr) { - auto &Loc = Env.getResultObjectLocation(*S); - Env.initializeFieldsWithValues(Loc); - refreshRecordValue(Loc, Env); + Value *Val = Env.createValue(S->getType()); + // We're guaranteed to always be able to create a value for record + // types. + assert(Val != nullptr); + Env.setValue(*S, *Val); } } } @@ -470,13 +472,6 @@ public: void VisitCXXDefaultInitExpr(const CXXDefaultInitExpr *S) { const Expr *InitExpr = S->getExpr(); assert(InitExpr != nullptr); - - // If this is a prvalue of record type, the handler for `*InitExpr` (if one - // exists) will initialize the result object; there is no value to propgate - // here. - if (S->getType()->isRecordType() && S->isPRValue()) - return; - propagateValueOrStorageLocation(*InitExpr, *S, Env); } @@ -484,17 +479,6 @@ public: const CXXConstructorDecl *ConstructorDecl = S->getConstructor(); assert(ConstructorDecl != nullptr); - // `CXXConstructExpr` can have array type if default-initializing an array - // of records. We don't handle this specifically beyond potentially inlining - // the call. - if (!S->getType()->isRecordType()) { - transferInlineCall(S, ConstructorDecl); - return; - } - - RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); - Env.setValue(*S, refreshRecordValue(Loc, Env)); - if (ConstructorDecl->isCopyOrMoveConstructor()) { // It is permissible for a copy/move constructor to have additional // parameters as long as they have default arguments defined for them. @@ -507,14 +491,24 @@ public: if (ArgLoc == nullptr) return; - // Even if the copy/move constructor call is elidable, we choose to copy - // the record in all cases (which isn't wrong, just potentially not - // optimal). - copyRecord(*ArgLoc, Loc, Env); + if (S->isElidable()) { + if (Value *Val = Env.getValue(*ArgLoc)) + Env.setValue(*S, *Val); + } else { + auto &Val = *cast(Env.createValue(S->getType())); + Env.setValue(*S, Val); + copyRecord(*ArgLoc, Val.getLoc(), Env); + } return; } - Env.initializeFieldsWithValues(Loc, S->getType()); + // `CXXConstructExpr` can have array type if default-initializing an array + // of records, and we currently can't create values for arrays. So check if + // we've got a record type. + if (S->getType()->isRecordType()) { + auto &InitialVal = *cast(Env.createValue(S->getType())); + Env.setValue(*S, InitialVal); + } transferInlineCall(S, ConstructorDecl); } @@ -557,15 +551,19 @@ public: if (S->isGLValue()) { Env.setStorageLocation(*S, *LocDst); } else if (S->getType()->isRecordType()) { - // Assume that the assignment returns the assigned value. - copyRecord(*LocDst, Env.getResultObjectLocation(*S), Env); + // Make sure that we have a `RecordValue` for this expression so that + // `Environment::getResultObjectLocation()` is able to return a location + // for it. + if (Env.getValue(*S) == nullptr) + refreshRecordValue(*S, Env); } return; } - // `CXXOperatorCallExpr` can be a prvalue. Call `VisitCallExpr`() to - // initialize the prvalue's fields with values. + // CXXOperatorCallExpr can be prvalues. Call `VisitCallExpr`() to create + // a `RecordValue` for them so that `Environment::getResultObjectLocation()` + // can return a value. VisitCallExpr(S); } @@ -582,6 +580,11 @@ public: } } + void VisitCXXTemporaryObjectExpr(const CXXTemporaryObjectExpr *S) { + if (Value *Val = Env.createValue(S->getType())) + Env.setValue(*S, *Val); + } + void VisitCallExpr(const CallExpr *S) { // Of clang's builtins, only `__builtin_expect` is handled explicitly, since // others (like trap, debugtrap, and unreachable) are handled by CFG @@ -609,14 +612,13 @@ public: } else if (const FunctionDecl *F = S->getDirectCallee()) { transferInlineCall(S, F); - // If this call produces a prvalue of record type, initialize its fields - // with values. + // If this call produces a prvalue of record type, make sure that we have + // a `RecordValue` for it. This is required so that + // `Environment::getResultObjectLocation()` is able to return a location + // for this `CallExpr`. if (S->getType()->isRecordType() && S->isPRValue()) - if (Env.getValue(*S) == nullptr) { - RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); - Env.initializeFieldsWithValues(Loc); - Env.setValue(*S, refreshRecordValue(Loc, Env)); - } + if (Env.getValue(*S) == nullptr) + refreshRecordValue(*S, Env); } } @@ -664,10 +666,8 @@ public: // `getLogicOperatorSubExprValue()`. if (S->isGLValue()) Env.setStorageLocation(*S, Env.createObject(S->getType())); - else if (!S->getType()->isRecordType()) { - if (Value *Val = Env.createValue(S->getType())) - Env.setValue(*S, *Val); - } + else if (Value *Val = Env.createValue(S->getType())) + Env.setValue(*S, *Val); } void VisitInitListExpr(const InitListExpr *S) { @@ -688,51 +688,71 @@ public: return; } - RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); - Env.setValue(*S, refreshRecordValue(Loc, Env)); - - // Initialization of base classes and fields of record type happens when we - // visit the nested `CXXConstructExpr` or `InitListExpr` for that base class - // or field. We therefore only need to deal with fields of non-record type - // here. - + llvm::DenseMap FieldLocs; RecordInitListHelper InitListHelper(S); + for (auto [Base, Init] : InitListHelper.base_inits()) { + assert(Base->getType().getCanonicalType() == + Init->getType().getCanonicalType()); + auto *BaseVal = Env.get(*Init); + if (!BaseVal) + BaseVal = cast(Env.createValue(Init->getType())); + // Take ownership of the fields of the `RecordValue` for the base class + // and incorporate them into the "flattened" set of fields for the + // derived class. + auto Children = BaseVal->getLoc().children(); + FieldLocs.insert(Children.begin(), Children.end()); + } + for (auto [Field, Init] : InitListHelper.field_inits()) { - if (Field->getType()->isRecordType()) - continue; - if (Field->getType()->isReferenceType()) { - assert(Field->getType().getCanonicalType()->getPointeeType() == - Init->getType().getCanonicalType()); - Loc.setChild(*Field, &Env.createObject(Field->getType(), Init)); - continue; - } - assert(Field->getType().getCanonicalType().getUnqualifiedType() == - Init->getType().getCanonicalType().getUnqualifiedType()); - StorageLocation *FieldLoc = Loc.getChild(*Field); - // Locations for non-reference fields must always be non-null. - assert(FieldLoc != nullptr); - Value *Val = Env.getValue(*Init); - if (Val == nullptr && isa(Init) && - Init->getType()->isPointerType()) - Val = - &Env.getOrCreateNullPointerValue(Init->getType()->getPointeeType()); - if (Val == nullptr) - Val = Env.createValue(Field->getType()); - if (Val != nullptr) - Env.setValue(*FieldLoc, *Val); + assert( + // The types are same, or + Field->getType().getCanonicalType().getUnqualifiedType() == + Init->getType().getCanonicalType().getUnqualifiedType() || + // The field's type is T&, and initializer is T + (Field->getType()->isReferenceType() && + Field->getType().getCanonicalType()->getPointeeType() == + Init->getType().getCanonicalType())); + auto& Loc = Env.createObject(Field->getType(), Init); + FieldLocs.insert({Field, &Loc}); } - for (const auto &[FieldName, FieldLoc] : Loc.synthetic_fields()) { - QualType FieldType = FieldLoc->getType(); - if (FieldType->isRecordType()) { - Env.initializeFieldsWithValues(*cast(FieldLoc)); - } else { - if (Value *Val = Env.createValue(FieldType)) - Env.setValue(*FieldLoc, *Val); + // In the case of a union, we don't in general have initializers for all + // of the fields. Create storage locations for the remaining fields (but + // don't associate them with values). + if (Type->isUnionType()) { + for (const FieldDecl *Field : + Env.getDataflowAnalysisContext().getModeledFields(Type)) { + if (auto [it, inserted] = FieldLocs.insert({Field, nullptr}); inserted) + it->second = &Env.createStorageLocation(Field->getType()); } } + // Check that we satisfy the invariant that a `RecordStorageLoation` + // contains exactly the set of modeled fields for that type. + // `ModeledFields` includes fields from all the bases, but only the + // modeled ones. However, if a class type is initialized with an + // `InitListExpr`, all fields in the class, including those from base + // classes, are included in the set of modeled fields. The code above + // should therefore populate exactly the modeled fields. + assert(containsSameFields( + Env.getDataflowAnalysisContext().getModeledFields(Type), FieldLocs)); + + RecordStorageLocation::SyntheticFieldMap SyntheticFieldLocs; + for (const auto &Entry : + Env.getDataflowAnalysisContext().getSyntheticFields(Type)) { + SyntheticFieldLocs.insert( + {Entry.getKey(), &Env.createObject(Entry.getValue())}); + } + + auto &Loc = Env.getDataflowAnalysisContext().createRecordStorageLocation( + Type, std::move(FieldLocs), std::move(SyntheticFieldLocs)); + RecordValue &RecordVal = Env.create(Loc); + + Env.setValue(Loc, RecordVal); + + Env.setValue(*S, RecordVal); + // FIXME: Implement array initialization. } diff --git a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp index 1b73c5d68301..595f70f819dd 100644 --- a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp +++ b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp @@ -369,10 +369,17 @@ builtinTransferInitializer(const CFGInitializer &Elt, ParentLoc->setChild(*Member, InitExprLoc); } else if (auto *InitExprVal = Env.getValue(*InitExpr)) { assert(MemberLoc != nullptr); - // Record-type initializers construct themselves directly into the result - // object, so there is no need to handle them here. - if (!Member->getType()->isRecordType()) + if (Member->getType()->isRecordType()) { + auto *InitValStruct = cast(InitExprVal); + // FIXME: Rather than performing a copy here, we should really be + // initializing the field in place. This would require us to propagate the + // storage location of the field to the AST node that creates the + // `RecordValue`. + copyRecord(InitValStruct->getLoc(), + *cast(MemberLoc), Env); + } else { Env.setValue(*MemberLoc, *InitExprVal); + } } } diff --git a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp index cc20623f881f..465a8e21690c 100644 --- a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp @@ -24,7 +24,6 @@ namespace { using namespace clang; using namespace dataflow; -using ::clang::dataflow::test::findValueDecl; using ::clang::dataflow::test::getFieldValue; using ::testing::Contains; using ::testing::IsNull; @@ -200,48 +199,6 @@ TEST_F(EnvironmentTest, JoinRecords) { } } -TEST_F(EnvironmentTest, DifferentReferenceLocInJoin) { - // This tests the case where the storage location for a reference-type - // variable is different for two states being joined. We used to believe this - // could not happen and therefore had an assertion disallowing this; this test - // exists to demonstrate that we can handle this condition without a failing - // assertion. See also the discussion here: - // https://discourse.llvm.org/t/70086/6 - - using namespace ast_matchers; - - std::string Code = R"cc( - void f(int &ref) {} - )cc"; - - auto Unit = - tooling::buildASTFromCodeWithArgs(Code, {"-fsyntax-only", "-std=c++11"}); - auto &Context = Unit->getASTContext(); - - ASSERT_EQ(Context.getDiagnostics().getClient()->getNumErrors(), 0U); - - const ValueDecl *Ref = findValueDecl(Context, "ref"); - - Environment Env1(DAContext); - StorageLocation &Loc1 = Env1.createStorageLocation(Context.IntTy); - Env1.setStorageLocation(*Ref, Loc1); - - Environment Env2(DAContext); - StorageLocation &Loc2 = Env2.createStorageLocation(Context.IntTy); - Env2.setStorageLocation(*Ref, Loc2); - - EXPECT_NE(&Loc1, &Loc2); - - Environment::ValueModel Model; - Environment EnvJoined = - Environment::join(Env1, Env2, Model, Environment::DiscardExprState); - - // Joining environments with different storage locations for the same - // declaration results in the declaration being removed from the joined - // environment. - EXPECT_EQ(EnvJoined.getStorageLocation(*Ref), nullptr); -} - TEST_F(EnvironmentTest, InitGlobalVarsFun) { using namespace ast_matchers; diff --git a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp index 00dafb2988c6..ca055a462a28 100644 --- a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp @@ -1582,9 +1582,10 @@ TEST(TransferTest, FieldsDontHaveValuesInConstructorWithBaseClass) { [](const llvm::StringMap> &Results, ASTContext &ASTCtx) { const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - // The field of the base class should already have been initialized with - // a value by the base constructor. - EXPECT_NE(getFieldValue(Env.getThisPointeeStorageLocation(), "BaseVal", + // FIXME: The field of the base class should already have been + // initialized with a value by the base constructor. This test documents + // the current buggy behavior. + EXPECT_EQ(getFieldValue(Env.getThisPointeeStorageLocation(), "BaseVal", ASTCtx, Env), nullptr); EXPECT_EQ(getFieldValue(Env.getThisPointeeStorageLocation(), "Val", @@ -2997,12 +2998,8 @@ TEST(TransferTest, ResultObjectLocation) { TEST(TransferTest, ResultObjectLocationForDefaultArgExpr) { std::string Code = R"( - struct Inner {}; - struct Outer { - Inner I = {}; - }; - - void funcWithDefaultArg(Outer O = {}); + struct S {}; + void funcWithDefaultArg(S s = S()); void target() { funcWithDefaultArg(); // [[p]] @@ -3061,7 +3058,13 @@ TEST(TransferTest, ResultObjectLocationForDefaultInitExpr) { RecordStorageLocation &Loc = Env.getResultObjectLocation(*DefaultInit); - EXPECT_EQ(&Loc, Env.getThisPointeeStorageLocation()->getChild(*SField)); + // FIXME: The result object location for the `CXXDefaultInitExpr` should + // be the location of the member variable being initialized, but we + // don't do this correctly yet; see also comments in + // `builtinTransferInitializer()`. + // For the time being, we just document the current erroneous behavior + // here (this should be `EXPECT_EQ` when the behavior is fixed). + EXPECT_NE(&Loc, Env.getThisPointeeStorageLocation()->getChild(*SField)); }); } @@ -3098,79 +3101,6 @@ TEST(TransferTest, ResultObjectLocationForCXXOperatorCallExpr) { }); } -TEST(TransferTest, ResultObjectLocationForStdInitializerListExpr) { - std::string Code = R"( - namespace std { - template - struct initializer_list {}; - } // namespace std - - void target() { - std::initializer_list list = {1}; - // [[p]] - } - )"; - - using ast_matchers::cxxStdInitializerListExpr; - using ast_matchers::match; - using ast_matchers::selectFirst; - runDataflow( - Code, - [](const llvm::StringMap> &Results, - ASTContext &ASTCtx) { - const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - - auto *StdInitList = selectFirst( - "std_init_list", - match(cxxStdInitializerListExpr().bind("std_init_list"), ASTCtx)); - ASSERT_NE(StdInitList, nullptr); - - EXPECT_EQ(&Env.getResultObjectLocation(*StdInitList), - &getLocForDecl(ASTCtx, Env, "list")); - }); -} - -TEST(TransferTest, ResultObjectLocationPropagatesThroughConditionalOperator) { - std::string Code = R"( - struct A { - A(int); - }; - - void target(bool b) { - A a = b ? A(0) : A(1); - (void)0; // [[p]] - } - )"; - using ast_matchers::cxxConstructExpr; - using ast_matchers::equals; - using ast_matchers::hasArgument; - using ast_matchers::integerLiteral; - using ast_matchers::match; - using ast_matchers::selectFirst; - using ast_matchers::traverse; - runDataflow( - Code, - [](const llvm::StringMap> &Results, - ASTContext &ASTCtx) { - const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - - auto *ConstructExpr0 = selectFirst( - "construct", - match(cxxConstructExpr(hasArgument(0, integerLiteral(equals(0)))) - .bind("construct"), - ASTCtx)); - auto *ConstructExpr1 = selectFirst( - "construct", - match(cxxConstructExpr(hasArgument(0, integerLiteral(equals(1)))) - .bind("construct"), - ASTCtx)); - - auto &ALoc = getLocForDecl(ASTCtx, Env, "a"); - EXPECT_EQ(&Env.getResultObjectLocation(*ConstructExpr0), &ALoc); - EXPECT_EQ(&Env.getResultObjectLocation(*ConstructExpr1), &ALoc); - }); -} - TEST(TransferTest, StaticCast) { std::string Code = R"( void target(int Foo) { @@ -5956,38 +5886,6 @@ TEST(TransferTest, ContextSensitiveReturnRecord) { {BuiltinOptions{ContextSensitiveOptions{}}}); } -TEST(TransferTest, ContextSensitiveReturnSelfReferentialRecord) { - std::string Code = R"( - struct S { - S() { self = this; } - S *self; - }; - - S makeS() { - // RVO guarantees that this will be constructed directly into `MyS`. - return S(); - } - - void target() { - S MyS = makeS(); - // [[p]] - } - )"; - runDataflow( - Code, - [](const llvm::StringMap> &Results, - ASTContext &ASTCtx) { - const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - - auto &MySLoc = getLocForDecl(ASTCtx, Env, "MyS"); - - auto *SelfVal = - cast(getFieldValue(&MySLoc, "self", ASTCtx, Env)); - EXPECT_EQ(&SelfVal->getPointeeLoc(), &MySLoc); - }, - {BuiltinOptions{ContextSensitiveOptions{}}}); -} - TEST(TransferTest, ContextSensitiveMethodLiteral) { std::string Code = R"( class MyClass { @@ -6932,6 +6830,50 @@ TEST(TransferTest, LambdaCaptureThis) { }); } +TEST(TransferTest, DifferentReferenceLocInJoin) { + // This test triggers a case where the storage location for a reference-type + // variable is different for two states being joined. We used to believe this + // could not happen and therefore had an assertion disallowing this; this test + // exists to demonstrate that we can handle this condition without a failing + // assertion. See also the discussion here: + // https://discourse.llvm.org/t/70086/6 + std::string Code = R"( + namespace std { + template struct initializer_list { + const T* begin(); + const T* end(); + }; + } + + void target(char* p, char* end) { + while (p != end) { + if (*p == ' ') { + p++; + continue; + } + + auto && range = {1, 2}; + for (auto b = range.begin(), e = range.end(); b != e; ++b) { + } + (void)0; + // [[p]] + } + } + )"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + // Joining environments with different storage locations for the same + // declaration results in the declaration being removed from the joined + // environment. + const ValueDecl *VD = findValueDecl(ASTCtx, "range"); + ASSERT_EQ(Env.getStorageLocation(*VD), nullptr); + }); +} + // This test verifies correct modeling of a relational dependency that goes // through unmodeled functions (the simple `cond()` in this case). TEST(TransferTest, ConditionalRelation) { -- GitLab From a6d1366b736cad85b3bb9fbdda340e07488d6cde Mon Sep 17 00:00:00 2001 From: erichkeane Date: Wed, 10 Apr 2024 12:41:26 -0700 Subject: [PATCH 447/695] [NFC] Remove a pair of incorrect comments from ParseOpenACC We attempt to continue parsing, but the comment says the opposite. Just remove the inaccurate comments in this patch. --- clang/lib/Parse/ParseOpenACC.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/clang/lib/Parse/ParseOpenACC.cpp b/clang/lib/Parse/ParseOpenACC.cpp index 59a4a5f53467..b487a1968d1e 100644 --- a/clang/lib/Parse/ParseOpenACC.cpp +++ b/clang/lib/Parse/ParseOpenACC.cpp @@ -843,8 +843,7 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( } case OpenACCClauseKind::If: { ExprResult CondExpr = ParseOpenACCConditionalExpr(*this); - // An invalid expression can be just about anything, so just give up on - // this clause list. + if (CondExpr.isInvalid()) { Parens.skipToEnd(); return OpenACCCanContinue(); @@ -966,8 +965,7 @@ Parser::OpenACCClauseParseResult Parser::ParseOpenACCClauseParams( case OpenACCClauseKind::Self: { assert(DirKind != OpenACCDirectiveKind::Update); ExprResult CondExpr = ParseOpenACCConditionalExpr(*this); - // An invalid expression can be just about anything, so just give up on - // this clause list. + if (CondExpr.isInvalid()) { Parens.skipToEnd(); return OpenACCCanContinue(); -- GitLab From b3792ae42a4adda5cb51d53f3d6a4b9b025b11fd Mon Sep 17 00:00:00 2001 From: Xing Xue Date: Wed, 10 Apr 2024 16:06:31 -0400 Subject: [PATCH 448/695] [OpenMP][AIX] Fix test config for AIX (#88272) This patch fixes the test config so that it works for `tasking/omp50_taskdep_depobj.c` which uses different flags to test with compiler's `omp.h`. * set test environment variable `OBJECT_MODE` to `64` if it is set explicitly to `64` in the AIX environment. `OBJECT_MODE` is default to `32` and is recognized by AIX compilers and toolchain. In this way, we don't need to set `-m64` for all compiler flags for 64-bit mode * add option `-Wl,-bmaxdata` to 32-bit `test_openmp_flags` used by `tasking/omp50_taskdep_depobj.c` --- openmp/runtime/test/lit.cfg | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openmp/runtime/test/lit.cfg b/openmp/runtime/test/lit.cfg index e27e52bb4289..e8f7f3470580 100644 --- a/openmp/runtime/test/lit.cfg +++ b/openmp/runtime/test/lit.cfg @@ -112,13 +112,15 @@ if config.operating_system == 'AIX': config.available_features.add("aix") object_mode = os.environ.get('OBJECT_MODE', '32') if object_mode == '64': - config.test_flags += " -m64" + # Set OBJECT_MODE to 64 for LIT test if it is explicitly set. + config.environment['OBJECT_MODE'] = os.environ['OBJECT_MODE'] elif object_mode == '32': # Set user data area to 2GB since the default size 256MB in 32-bit mode # is not sufficient to run LIT tests on systems that have a lot of # CPUs when creating one worker thread for each CPU and each worker # thread uses 4MB stack size. config.test_flags += " -Wl,-bmaxdata:0x80000000" + config.test_openmp_flags += " -Wl,-bmaxdata:0x80000000" if 'Linux' in config.operating_system: config.available_features.add("linux") -- GitLab From a12836647e08c4ad203b9834ac55892fa0b9f2d3 Mon Sep 17 00:00:00 2001 From: David Pagan Date: Wed, 10 Apr 2024 13:09:17 -0700 Subject: [PATCH 449/695] [OpenMP][CodeGen] Improved codegen for combined loop directives (#87278) IR for 'target teams loop' is now dependent on suitability of associated loop-nest. If a loop-nest: - does not contain a function call, or - the -fopenmp-assume-no-nested-parallelism has been specified, - or the call is to an OpenMP API AND - does not contain nested loop bind(parallel) directives then it can be emitted as 'target teams distribute parallel for', which is the current default. Otherwise, it is emitted as 'target teams distribute'. Added debug output indicating how 'target teams loop' was emitted. Flag is -mllvm -debug-only=target-teams-loop-codegen Added LIT tests explicitly verifying 'target teams loop' emitted as a parallel loop and a distribute loop. Updated other 'loop' related tests as needed to reflect change in IR. - These updates account for most of the changed files and additions/deletions. --- clang/include/clang/AST/StmtOpenMP.h | 11 +- clang/lib/AST/StmtOpenMP.cpp | 3 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 15 +- clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp | 7 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 87 +- clang/lib/Sema/SemaOpenMP.cpp | 86 +- clang/lib/Serialization/ASTReaderStmt.cpp | 1 + clang/lib/Serialization/ASTWriterStmt.cpp | 1 + ...vptx_target_teams_generic_loop_codegen.cpp | 48 +- ...eams_generic_loop_generic_mode_codegen.cpp | 397 +- .../target_teams_generic_loop_codegen.cpp | 1132 +---- ...ams_generic_loop_codegen_as_distribute.cpp | 587 +++ ...s_generic_loop_codegen_as_parallel_for.cpp | 3998 +++++++++++++++++ .../target_teams_generic_loop_if_codegen.cpp | 710 +-- ...get_teams_generic_loop_private_codegen.cpp | 1438 +----- .../OpenMP/teams_generic_loop_codegen-1.cpp | 1360 +----- .../OpenMP/teams_generic_loop_codegen.cpp | 630 +-- .../teams_generic_loop_collapse_codegen.cpp | 808 +--- .../teams_generic_loop_private_codegen.cpp | 685 +-- .../teams_generic_loop_reduction_codegen.cpp | 785 +--- 20 files changed, 5886 insertions(+), 6903 deletions(-) create mode 100644 clang/test/OpenMP/target_teams_generic_loop_codegen_as_distribute.cpp create mode 100644 clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp diff --git a/clang/include/clang/AST/StmtOpenMP.h b/clang/include/clang/AST/StmtOpenMP.h index 3cb3c1014d73..f735fa5643ae 100644 --- a/clang/include/clang/AST/StmtOpenMP.h +++ b/clang/include/clang/AST/StmtOpenMP.h @@ -6109,6 +6109,8 @@ public: class OMPTargetTeamsGenericLoopDirective final : public OMPLoopDirective { friend class ASTStmtReader; friend class OMPExecutableDirective; + /// true if loop directive's associated loop can be a parallel for. + bool CanBeParallelFor = false; /// Build directive with the given start and end location. /// /// \param StartLoc Starting location of the directive kind. @@ -6131,6 +6133,9 @@ class OMPTargetTeamsGenericLoopDirective final : public OMPLoopDirective { llvm::omp::OMPD_target_teams_loop, SourceLocation(), SourceLocation(), CollapsedNum) {} + /// Set whether associated loop can be a parallel for. + void setCanBeParallelFor(bool ParFor) { CanBeParallelFor = ParFor; } + public: /// Creates directive with a list of \p Clauses. /// @@ -6145,7 +6150,7 @@ public: static OMPTargetTeamsGenericLoopDirective * Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc, unsigned CollapsedNum, ArrayRef Clauses, - Stmt *AssociatedStmt, const HelperExprs &Exprs); + Stmt *AssociatedStmt, const HelperExprs &Exprs, bool CanBeParallelFor); /// Creates an empty directive with the place /// for \a NumClauses clauses. @@ -6159,6 +6164,10 @@ public: unsigned CollapsedNum, EmptyShell); + /// Return true if current loop directive's associated loop can be a + /// parallel for. + bool canBeParallelFor() const { return CanBeParallelFor; } + static bool classof(const Stmt *T) { return T->getStmtClass() == OMPTargetTeamsGenericLoopDirectiveClass; } diff --git a/clang/lib/AST/StmtOpenMP.cpp b/clang/lib/AST/StmtOpenMP.cpp index 426b35848cb5..d8519b2071e6 100644 --- a/clang/lib/AST/StmtOpenMP.cpp +++ b/clang/lib/AST/StmtOpenMP.cpp @@ -2431,7 +2431,7 @@ OMPTeamsGenericLoopDirective::CreateEmpty(const ASTContext &C, OMPTargetTeamsGenericLoopDirective *OMPTargetTeamsGenericLoopDirective::Create( const ASTContext &C, SourceLocation StartLoc, SourceLocation EndLoc, unsigned CollapsedNum, ArrayRef Clauses, Stmt *AssociatedStmt, - const HelperExprs &Exprs) { + const HelperExprs &Exprs, bool CanBeParallelFor) { auto *Dir = createDirective( C, Clauses, AssociatedStmt, numLoopChildren(CollapsedNum, OMPD_target_teams_loop), StartLoc, EndLoc, @@ -2473,6 +2473,7 @@ OMPTargetTeamsGenericLoopDirective *OMPTargetTeamsGenericLoopDirective::Create( Dir->setCombinedNextUpperBound(Exprs.DistCombinedFields.NUB); Dir->setCombinedDistCond(Exprs.DistCombinedFields.DistCond); Dir->setCombinedParForInDistCond(Exprs.DistCombinedFields.ParForInDistCond); + Dir->setCanBeParallelFor(CanBeParallelFor); return Dir; } diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 8eb10584699f..2ae11e129c75 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -2656,11 +2656,12 @@ void CGOpenMPRuntime::emitForStaticFinish(CodeGenFunction &CGF, // Call __kmpc_for_static_fini(ident_t *loc, kmp_int32 tid); llvm::Value *Args[] = { emitUpdateLocation(CGF, Loc, - isOpenMPDistributeDirective(DKind) + isOpenMPDistributeDirective(DKind) || + (DKind == OMPD_target_teams_loop) ? OMP_IDENT_WORK_DISTRIBUTE - : isOpenMPLoopDirective(DKind) - ? OMP_IDENT_WORK_LOOP - : OMP_IDENT_WORK_SECTIONS), + : isOpenMPLoopDirective(DKind) + ? OMP_IDENT_WORK_LOOP + : OMP_IDENT_WORK_SECTIONS), getThreadID(CGF, Loc)}; auto DL = ApplyDebugLocation::CreateDefaultArtificial(CGF, Loc); if (isOpenMPDistributeDirective(DKind) && @@ -8885,7 +8886,8 @@ getNestedDistributeDirective(ASTContext &Ctx, const OMPExecutableDirective &D) { OpenMPDirectiveKind DKind = NestedDir->getDirectiveKind(); switch (D.getDirectiveKind()) { case OMPD_target: - // For now, just treat 'target teams loop' as if it's distributed. + // For now, treat 'target' with nested 'teams loop' as if it's + // distributed (target teams distribute). if (isOpenMPDistributeDirective(DKind) || DKind == OMPD_teams_loop) return NestedDir; if (DKind == OMPD_teams) { @@ -9369,7 +9371,8 @@ llvm::Value *CGOpenMPRuntime::emitTargetNumIterationsCall( SizeEmitter) { OpenMPDirectiveKind Kind = D.getDirectiveKind(); const OMPExecutableDirective *TD = &D; - // Get nested teams distribute kind directive, if any. + // Get nested teams distribute kind directive, if any. For now, treat + // 'target_teams_loop' as if it's really a target_teams_distribute. if ((!isOpenMPDistributeDirective(Kind) || !isOpenMPTeamsDirective(Kind)) && Kind != OMPD_target_teams_loop) TD = getNestedDistributeDirective(CGM.getContext(), D); diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp index 5baac8f0e3e2..59ba03c6b862 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp @@ -646,7 +646,6 @@ static bool supportsSPMDExecutionMode(ASTContext &Ctx, case OMPD_target: case OMPD_target_teams: return hasNestedSPMDDirective(Ctx, D); - case OMPD_target_teams_loop: case OMPD_target_parallel_loop: case OMPD_target_parallel: case OMPD_target_parallel_for: @@ -658,6 +657,12 @@ static bool supportsSPMDExecutionMode(ASTContext &Ctx, return true; case OMPD_target_teams_distribute: return false; + case OMPD_target_teams_loop: + // Whether this is true or not depends on how the directive will + // eventually be emitted. + if (auto *TTLD = dyn_cast(&D)) + return TTLD->canBeParallelFor(); + return false; case OMPD_parallel: case OMPD_for: case OMPD_parallel_for: diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index e6d504bcdeca..3bf99366b69c 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -24,6 +24,7 @@ #include "clang/AST/StmtVisitor.h" #include "clang/Basic/OpenMPKinds.h" #include "clang/Basic/PrettyStackTrace.h" +#include "clang/Basic/SourceManager.h" #include "llvm/ADT/SmallSet.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/Frontend/OpenMP/OMPConstants.h" @@ -34,11 +35,14 @@ #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Metadata.h" #include "llvm/Support/AtomicOrdering.h" +#include "llvm/Support/Debug.h" #include using namespace clang; using namespace CodeGen; using namespace llvm::omp; +#define TTL_CODEGEN_TYPE "target-teams-loop-codegen" + static const VarDecl *getBaseDecl(const Expr *Ref); namespace { @@ -1432,9 +1436,12 @@ void CodeGenFunction::EmitOMPReductionClauseFinal( *this, D.getBeginLoc(), isOpenMPWorksharingDirective(D.getDirectiveKind())); } + bool TeamsLoopCanBeParallel = false; + if (auto *TTLD = dyn_cast(&D)) + TeamsLoopCanBeParallel = TTLD->canBeParallelFor(); bool WithNowait = D.getSingleClause() || isOpenMPParallelDirective(D.getDirectiveKind()) || - ReductionKind == OMPD_simd; + TeamsLoopCanBeParallel || ReductionKind == OMPD_simd; bool SimpleReduction = ReductionKind == OMPD_simd; // Emit nowait reduction if nowait clause is present or directive is a // parallel directive (it always has implicit barrier). @@ -7928,11 +7935,9 @@ void CodeGenFunction::EmitOMPParallelGenericLoopDirective( void CodeGenFunction::EmitOMPTeamsGenericLoopDirective( const OMPTeamsGenericLoopDirective &S) { // To be consistent with current behavior of 'target teams loop', emit - // 'teams loop' as if its constituent constructs are 'distribute, - // 'parallel, and 'for'. + // 'teams loop' as if its constituent constructs are 'teams' and 'distribute'. auto &&CodeGenDistribute = [&S](CodeGenFunction &CGF, PrePostActionTy &) { - CGF.EmitOMPDistributeLoop(S, emitInnerParallelForWhenCombined, - S.getDistInc()); + CGF.EmitOMPDistributeLoop(S, emitOMPLoopBodyWithStopPoint, S.getInc()); }; // Emit teams region as a standalone region. @@ -7946,15 +7951,33 @@ void CodeGenFunction::EmitOMPTeamsGenericLoopDirective( CodeGenDistribute); CGF.EmitOMPReductionClauseFinal(S, /*ReductionKind=*/OMPD_teams); }; - emitCommonOMPTeamsDirective(*this, S, OMPD_distribute_parallel_for, CodeGen); + emitCommonOMPTeamsDirective(*this, S, OMPD_distribute, CodeGen); emitPostUpdateForReductionClause(*this, S, [](CodeGenFunction &) { return nullptr; }); } -static void -emitTargetTeamsGenericLoopRegion(CodeGenFunction &CGF, - const OMPTargetTeamsGenericLoopDirective &S, - PrePostActionTy &Action) { +static void emitTargetTeamsLoopCodegenStatus(CodeGenFunction &CGF, + std::string StatusMsg, + const OMPExecutableDirective &D) { +#ifndef NDEBUG + bool IsDevice = CGF.CGM.getLangOpts().OpenMPIsTargetDevice; + if (IsDevice) + StatusMsg += ": DEVICE"; + else + StatusMsg += ": HOST"; + SourceLocation L = D.getBeginLoc(); + auto &SM = CGF.getContext().getSourceManager(); + PresumedLoc PLoc = SM.getPresumedLoc(L); + const char *FileName = PLoc.isValid() ? PLoc.getFilename() : nullptr; + unsigned LineNo = + PLoc.isValid() ? PLoc.getLine() : SM.getExpansionLineNumber(L); + llvm::dbgs() << StatusMsg << ": " << FileName << ": " << LineNo << "\n"; +#endif +} + +static void emitTargetTeamsGenericLoopRegionAsParallel( + CodeGenFunction &CGF, PrePostActionTy &Action, + const OMPTargetTeamsGenericLoopDirective &S) { Action.Enter(CGF); // Emit 'teams loop' as if its constituent constructs are 'distribute, // 'parallel, and 'for'. @@ -7974,19 +7997,50 @@ emitTargetTeamsGenericLoopRegion(CodeGenFunction &CGF, CGF, OMPD_distribute, CodeGenDistribute, /*HasCancel=*/false); CGF.EmitOMPReductionClauseFinal(S, /*ReductionKind=*/OMPD_teams); }; - + DEBUG_WITH_TYPE(TTL_CODEGEN_TYPE, + emitTargetTeamsLoopCodegenStatus( + CGF, TTL_CODEGEN_TYPE " as parallel for", S)); emitCommonOMPTeamsDirective(CGF, S, OMPD_distribute_parallel_for, CodeGenTeams); emitPostUpdateForReductionClause(CGF, S, [](CodeGenFunction &) { return nullptr; }); } -/// Emit combined directive 'target teams loop' as if its constituent -/// constructs are 'target', 'teams', 'distribute', 'parallel', and 'for'. +static void emitTargetTeamsGenericLoopRegionAsDistribute( + CodeGenFunction &CGF, PrePostActionTy &Action, + const OMPTargetTeamsGenericLoopDirective &S) { + Action.Enter(CGF); + // Emit 'teams loop' as if its constituent construct is 'distribute'. + auto &&CodeGenDistribute = [&S](CodeGenFunction &CGF, PrePostActionTy &) { + CGF.EmitOMPDistributeLoop(S, emitOMPLoopBodyWithStopPoint, S.getInc()); + }; + + // Emit teams region as a standalone region. + auto &&CodeGen = [&S, &CodeGenDistribute](CodeGenFunction &CGF, + PrePostActionTy &Action) { + Action.Enter(CGF); + CodeGenFunction::OMPPrivateScope PrivateScope(CGF); + CGF.EmitOMPReductionClauseInit(S, PrivateScope); + (void)PrivateScope.Privatize(); + CGF.CGM.getOpenMPRuntime().emitInlinedDirective( + CGF, OMPD_distribute, CodeGenDistribute, /*HasCancel=*/false); + CGF.EmitOMPReductionClauseFinal(S, /*ReductionKind=*/OMPD_teams); + }; + DEBUG_WITH_TYPE(TTL_CODEGEN_TYPE, + emitTargetTeamsLoopCodegenStatus( + CGF, TTL_CODEGEN_TYPE " as distribute", S)); + emitCommonOMPTeamsDirective(CGF, S, OMPD_distribute, CodeGen); + emitPostUpdateForReductionClause(CGF, S, + [](CodeGenFunction &) { return nullptr; }); +} + void CodeGenFunction::EmitOMPTargetTeamsGenericLoopDirective( const OMPTargetTeamsGenericLoopDirective &S) { auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { - emitTargetTeamsGenericLoopRegion(CGF, S, Action); + if (S.canBeParallelFor()) + emitTargetTeamsGenericLoopRegionAsParallel(CGF, Action, S); + else + emitTargetTeamsGenericLoopRegionAsDistribute(CGF, Action, S); }; emitCommonOMPTargetDirective(*this, S, CodeGen); } @@ -7996,7 +8050,10 @@ void CodeGenFunction::EmitOMPTargetTeamsGenericLoopDeviceFunction( const OMPTargetTeamsGenericLoopDirective &S) { // Emit SPMD target parallel loop region as a standalone region. auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &Action) { - emitTargetTeamsGenericLoopRegion(CGF, S, Action); + if (S.canBeParallelFor()) + emitTargetTeamsGenericLoopRegionAsParallel(CGF, Action, S); + else + emitTargetTeamsGenericLoopRegionAsDistribute(CGF, Action, S); }; llvm::Function *Fn; llvm::Constant *Addr; diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 0ba54a3a9cae..c814535ad6bd 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -4478,6 +4478,8 @@ void Sema::ActOnOpenMPRegionStart(OpenMPDirectiveKind DKind, Scope *CurScope) { Params); break; } + // For 'target teams loop', collect all captured regions so codegen can + // later decide the best IR to emit given the associated loop-nest. case OMPD_target_teams_loop: case OMPD_target_teams_distribute_parallel_for: case OMPD_target_teams_distribute_parallel_for_simd: { @@ -6135,6 +6137,79 @@ processImplicitMapsWithDefaultMappers(Sema &S, DSAStackTy *Stack, } } +namespace { +/// A 'teams loop' with a nested 'loop bind(parallel)' or generic function +/// call in the associated loop-nest cannot be a 'parallel for'. +class TeamsLoopChecker final : public ConstStmtVisitor { + Sema &SemaRef; + +public: + bool teamsLoopCanBeParallelFor() const { return TeamsLoopCanBeParallelFor; } + + // Is there a nested OpenMP loop bind(parallel) + void VisitOMPExecutableDirective(const OMPExecutableDirective *D) { + if (D->getDirectiveKind() == llvm::omp::Directive::OMPD_loop) { + if (const auto *C = D->getSingleClause()) + if (C->getBindKind() == OMPC_BIND_parallel) { + TeamsLoopCanBeParallelFor = false; + // No need to continue visiting any more + return; + } + } + for (const Stmt *Child : D->children()) + if (Child) + Visit(Child); + } + + void VisitCallExpr(const CallExpr *C) { + // Function calls inhibit parallel loop translation of 'target teams loop' + // unless the assume-no-nested-parallelism flag has been specified. + // OpenMP API runtime library calls do not inhibit parallel loop + // translation, regardless of the assume-no-nested-parallelism. + if (C) { + bool IsOpenMPAPI = false; + auto *FD = dyn_cast_or_null(C->getCalleeDecl()); + if (FD) { + std::string Name = FD->getNameInfo().getAsString(); + IsOpenMPAPI = Name.find("omp_") == 0; + } + TeamsLoopCanBeParallelFor = + IsOpenMPAPI || SemaRef.getLangOpts().OpenMPNoNestedParallelism; + if (!TeamsLoopCanBeParallelFor) + return; + } + for (const Stmt *Child : C->children()) + if (Child) + Visit(Child); + } + + void VisitCapturedStmt(const CapturedStmt *S) { + if (!S) + return; + Visit(S->getCapturedDecl()->getBody()); + } + + void VisitStmt(const Stmt *S) { + if (!S) + return; + for (const Stmt *Child : S->children()) + if (Child) + Visit(Child); + } + explicit TeamsLoopChecker(Sema &SemaRef) + : SemaRef(SemaRef), TeamsLoopCanBeParallelFor(true) {} + +private: + bool TeamsLoopCanBeParallelFor; +}; +} // namespace + +static bool teamsLoopCanBeParallelFor(Stmt *AStmt, Sema &SemaRef) { + TeamsLoopChecker Checker(SemaRef); + Checker.Visit(AStmt); + return Checker.teamsLoopCanBeParallelFor(); +} + bool Sema::mapLoopConstruct(llvm::SmallVector &ClausesWithoutBind, ArrayRef Clauses, OpenMPBindClauseKind &BindKind, @@ -10895,7 +10970,8 @@ StmtResult Sema::ActOnOpenMPTargetTeamsGenericLoopDirective( setFunctionHasBranchProtectedScope(); return OMPTargetTeamsGenericLoopDirective::Create( - Context, StartLoc, EndLoc, NestedLoopCount, Clauses, AStmt, B); + Context, StartLoc, EndLoc, NestedLoopCount, Clauses, AStmt, B, + teamsLoopCanBeParallelFor(AStmt, *this)); } StmtResult Sema::ActOnOpenMPParallelGenericLoopDirective( @@ -15645,6 +15721,12 @@ static OpenMPDirectiveKind getOpenMPCaptureRegionForClause( if (NameModifier == OMPD_unknown || NameModifier == OMPD_parallel) CaptureRegion = OMPD_target; break; + case OMPD_teams_loop: + case OMPD_target_teams_loop: + // For [target] teams loop, assume capture region is 'teams' so it's + // available for codegen later to use if/when necessary. + CaptureRegion = OMPD_teams; + break; case OMPD_target_teams_distribute_parallel_for_simd: if (OpenMPVersion >= 50 && (NameModifier == OMPD_unknown || NameModifier == OMPD_simd)) { @@ -15652,7 +15734,6 @@ static OpenMPDirectiveKind getOpenMPCaptureRegionForClause( break; } [[fallthrough]]; - case OMPD_target_teams_loop: case OMPD_target_teams_distribute_parallel_for: // If this clause applies to the nested 'parallel' region, capture within // the 'teams' region, otherwise do not capture. @@ -15775,7 +15856,6 @@ static OpenMPDirectiveKind getOpenMPCaptureRegionForClause( case OMPD_declare_target: case OMPD_end_declare_target: case OMPD_loop: - case OMPD_teams_loop: case OMPD_teams: case OMPD_tile: case OMPD_unroll: diff --git a/clang/lib/Serialization/ASTReaderStmt.cpp b/clang/lib/Serialization/ASTReaderStmt.cpp index 3ddb15b10f48..ca0460800898 100644 --- a/clang/lib/Serialization/ASTReaderStmt.cpp +++ b/clang/lib/Serialization/ASTReaderStmt.cpp @@ -2769,6 +2769,7 @@ void ASTStmtReader::VisitOMPTeamsGenericLoopDirective( void ASTStmtReader::VisitOMPTargetTeamsGenericLoopDirective( OMPTargetTeamsGenericLoopDirective *D) { VisitOMPLoopDirective(D); + D->setCanBeParallelFor(Record.readBool()); } void ASTStmtReader::VisitOMPParallelGenericLoopDirective( diff --git a/clang/lib/Serialization/ASTWriterStmt.cpp b/clang/lib/Serialization/ASTWriterStmt.cpp index ddee5db2b69e..e3816181e2b2 100644 --- a/clang/lib/Serialization/ASTWriterStmt.cpp +++ b/clang/lib/Serialization/ASTWriterStmt.cpp @@ -2821,6 +2821,7 @@ void ASTStmtWriter::VisitOMPTeamsGenericLoopDirective( void ASTStmtWriter::VisitOMPTargetTeamsGenericLoopDirective( OMPTargetTeamsGenericLoopDirective *D) { VisitOMPLoopDirective(D); + Record.writeBool(D->canBeParallelFor()); Code = serialization::STMT_OMP_TARGET_TEAMS_GENERIC_LOOP_DIRECTIVE; } diff --git a/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp index 5226b7498e4c..c89c6eb65706 100644 --- a/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp @@ -320,23 +320,31 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33 -// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]]) // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK1: user_code.entry: // CHECK1-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK1-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -344,11 +352,12 @@ int bar(int n){ // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -360,6 +369,7 @@ int bar(int n){ // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4 @@ -1566,23 +1576,31 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33 -// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 // CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]]) // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK2: user_code.entry: // CHECK2-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK2-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 +// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK2-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -1590,11 +1608,12 @@ int bar(int n){ // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined -// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1606,6 +1625,7 @@ int bar(int n){ // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK2-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4 @@ -2801,23 +2821,31 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33 -// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4:[0-9]+]] { +// CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 // CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]]) // CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 // CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] // CHECK3: user_code.entry: // CHECK3-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) +// CHECK3-NEXT: [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 +// CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 +// CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK3-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]] +// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]] // CHECK3-NEXT: call void @__kmpc_target_deinit() // CHECK3-NEXT: ret void // CHECK3: worker.exit: @@ -2825,11 +2853,12 @@ int bar(int n){ // // // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { +// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4 +// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -2841,6 +2870,7 @@ int bar(int n){ // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4 +// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4 diff --git a/clang/test/OpenMP/nvptx_target_teams_generic_loop_generic_mode_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_generic_loop_generic_mode_codegen.cpp index ca2670f0cd64..f0effa760dcd 100644 --- a/clang/test/OpenMP/nvptx_target_teams_generic_loop_generic_mode_codegen.cpp +++ b/clang/test/OpenMP/nvptx_target_teams_generic_loop_generic_mode_codegen.cpp @@ -30,17 +30,20 @@ int main(int argc, char **argv) { #endif // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_environment, ptr [[DYN_PTR]]) // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 @@ -50,9 +53,14 @@ int main(int argc, char **argv) { // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[ARGC_CASTED]], align 4 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8 +// CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK1-NEXT: call void @__kmpc_target_deinit() // CHECK1-NEXT: ret void // CHECK1: worker.exit: @@ -60,56 +68,55 @@ int main(int argc, char **argv) { // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[ARGC_CASTED:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8 +// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 -// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK1-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK1: omp.precond.then: // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK1: cond.true: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 // CHECK1-NEXT: br label [[COND_END:%.*]] // CHECK1: cond.false: // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -122,177 +129,54 @@ int main(int argc, char **argv) { // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 -// CHECK1-NEXT: store i32 [[TMP18]], ptr [[ARGC_CASTED]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[ARGC_CASTED]], align 8 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr -// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 -// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr -// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2 -// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr -// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8 -// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 -// CHECK1-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]] -// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]] -// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK1: cond.true10: -// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: br label [[COND_END12:%.*]] -// CHECK1: cond.false11: -// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END12]] -// CHECK1: cond.end12: -// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ] -// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4 -// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]]) -// CHECK1-NEXT: br label [[OMP_PRECOND_END]] -// CHECK1: omp.precond.end: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined_omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[ARGC_ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[ARGC]], ptr [[ARGC_ADDR]], align 8 -// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 -// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK1: omp.precond.then: -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32 -// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]] +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 -// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[I4]]) #[[ATTR5:[0-9]+]] -// CHECK1-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP0]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[I4]]) #[[ATTR4:[0-9]+]] +// CHECK1-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP0]]) #[[ATTR4]] // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] -// CHECK1-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARGC_ADDR]]) #[[ATTR5]] +// CHECK1-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARGC_ADDR]]) #[[ATTR4]] // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] // CHECK1-NEXT: store i32 [[ADD10]], ptr [[TMP0]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP15]], 1 // CHECK1-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP16]]) +// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 +// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) // CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1: omp.precond.end: // CHECK1-NEXT: ret void // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24 -// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 // CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_kernel_environment, ptr [[DYN_PTR]]) // CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 @@ -302,9 +186,14 @@ int main(int argc, char **argv) { // CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP3]], ptr [[ARGC_CASTED]], align 4 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARGC_CASTED]], align 4 +// CHECK2-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 +// CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP5]] to i1 +// CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK2-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4 -// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]] +// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]] // CHECK2-NEXT: call void @__kmpc_target_deinit() // CHECK2-NEXT: ret void // CHECK2: worker.exit: @@ -312,56 +201,55 @@ int main(int argc, char **argv) { // // // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined -// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1:[0-9]+]] { +// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { // CHECK2-NEXT: entry: // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 // CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 +// CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[ARGC_CASTED:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4 +// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4 // CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 // CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 +// CHECK2-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[SUB3:%.*]] = sub nsw i32 [[DIV]], 1 +// CHECK2-NEXT: store i32 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] // CHECK2: omp.precond.then: // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4 // CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() // CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] -// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 +// CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] +// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK2: cond.true: -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 +// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4 // CHECK2-NEXT: br label [[COND_END:%.*]] // CHECK2: cond.false: // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 @@ -374,155 +262,34 @@ int main(int argc, char **argv) { // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK2: omp.inner.for.cond: // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]] -// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[TMP16]], ptr [[ARGC_CASTED]], align 4 -// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARGC_CASTED]], align 4 -// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0 -// CHECK2-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr -// CHECK2-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 4 -// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1 -// CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr -// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4 -// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2 -// CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr -// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4 -// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3 -// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP24]], align 4 -// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 -// CHECK2-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4) -// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]] -// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]] -// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]] -// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] -// CHECK2: cond.true10: -// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK2-NEXT: br label [[COND_END12:%.*]] -// CHECK2: cond.false11: -// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: br label [[COND_END12]] -// CHECK2: cond.end12: -// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ] -// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK2-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK2: omp.inner.for.end: -// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK2: omp.loop.exit: -// CHECK2-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4 -// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP39]]) -// CHECK2-NEXT: br label [[OMP_PRECOND_END]] -// CHECK2: omp.precond.end: -// CHECK2-NEXT: ret void -// -// -// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l24_omp_outlined_omp_outlined -// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[ARGC:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR1]] { -// CHECK2-NEXT: entry: -// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK2-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK2-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK2-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4 -// CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 -// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 -// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK2-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] -// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK2: omp.precond.then: -// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4 -// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4 -// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 -// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK2: omp.inner.for.cond: -// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK2-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] -// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK2-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] +// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK2: omp.inner.for.body: -// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1 +// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 -// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[I3]]) #[[ATTR5:[0-9]+]] -// CHECK2-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP0]]) #[[ATTR5]] -// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[CALL]], [[CALL5]] -// CHECK2-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARGC_ADDR]]) #[[ATTR5]] -// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD6]], [[CALL7]] -// CHECK2-NEXT: store i32 [[ADD8]], ptr [[TMP0]], align 4 +// CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 +// CHECK2-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[I4]]) #[[ATTR4:[0-9]+]] +// CHECK2-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP0]]) #[[ATTR4]] +// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] +// CHECK2-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARGC_ADDR]]) #[[ATTR4]] +// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] +// CHECK2-NEXT: store i32 [[ADD10]], ptr [[TMP0]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK2: omp.inner.for.inc: -// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK2-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK2: omp.inner.for.end: // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK2: omp.loop.exit: -// CHECK2-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP16]]) +// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 +// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) // CHECK2-NEXT: br label [[OMP_PRECOND_END]] // CHECK2: omp.precond.end: // CHECK2-NEXT: ret void diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen.cpp index 22cf534bf0ba..3f752ac663f4 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_codegen.cpp @@ -28,1118 +28,6 @@ int foo() { return 0; } #endif -// IR-PCH-HOST-LABEL: define {{[^@]+}}@_Z3foov -// IR-PCH-HOST-SAME: () #[[ATTR0:[0-9]+]] { -// IR-PCH-HOST-NEXT: entry: -// IR-PCH-HOST-NEXT: [[I:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[J:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[SUM:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-PCH-HOST-NEXT: [[J_CASTED:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[TMP0:%.*]] = load i32, ptr [[J]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP0]], ptr [[J_CASTED]], align 4 -// IR-PCH-HOST-NEXT: [[TMP1:%.*]] = load i64, ptr [[J_CASTED]], align 8 -// IR-PCH-HOST-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22(i64 [[TMP1]], ptr [[SUM]]) #[[ATTR2:[0-9]+]] -// IR-PCH-HOST-NEXT: ret i32 0 -// IR-PCH-HOST-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22 -// IR-PCH-HOST-SAME: (i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1:[0-9]+]] { -// IR-PCH-HOST-NEXT: entry: -// IR-PCH-HOST-NEXT: [[J_ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[J_CASTED:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: store i64 [[J]], ptr [[J_ADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP1:%.*]] = load i32, ptr [[J_ADDR]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP1]], ptr [[J_CASTED]], align 4 -// IR-PCH-HOST-NEXT: [[TMP2:%.*]] = load i64, ptr [[J_CASTED]], align 8 -// IR-PCH-HOST-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 2, ptr @.omp_outlined., i64 [[TMP2]], ptr [[TMP0]]) -// IR-PCH-HOST-NEXT: ret void -// IR-PCH-HOST-LABEL: define {{[^@]+}}@.omp_outlined. -// IR-PCH-HOST-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1]] { -// IR-PCH-HOST-NEXT: entry: -// IR-PCH-HOST-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[J_ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[SUM1:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-PCH-HOST-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[J3:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[I:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[J4:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[J_CASTED:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// IR-PCH-HOST-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: store i64 [[J]], ptr [[J_ADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM1]], i32 0, i32 0, i32 0 -// IR-PCH-HOST-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP1]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] -// IR-PCH-HOST: omp.arrayinit.body: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// IR-PCH-HOST-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP1]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] -// IR-PCH-HOST: omp.arrayinit.done: -// IR-PCH-HOST-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-PCH-HOST-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-HOST-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// IR-PCH-HOST-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-HOST-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// IR-PCH-HOST-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP3]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-PCH-HOST-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-HOST-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// IR-PCH-HOST-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// IR-PCH-HOST: cond.true: -// IR-PCH-HOST-NEXT: br label [[COND_END:%.*]] -// IR-PCH-HOST: cond.false: -// IR-PCH-HOST-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-HOST-NEXT: br label [[COND_END]] -// IR-PCH-HOST: cond.end: -// IR-PCH-HOST-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// IR-PCH-HOST-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-HOST-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// IR-PCH-HOST-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-PCH-HOST: omp.inner.for.cond: -// IR-PCH-HOST-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// IR-PCH-HOST-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-HOST-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// IR-PCH-HOST-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-PCH-HOST: omp.inner.for.body: -// IR-PCH-HOST-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-PCH-HOST-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// IR-PCH-HOST-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-HOST-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -// IR-PCH-HOST-NEXT: [[TMP13:%.*]] = load i32, ptr [[J3]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP13]], ptr [[J_CASTED]], align 4 -// IR-PCH-HOST-NEXT: [[TMP14:%.*]] = load i64, ptr [[J_CASTED]], align 8 -// IR-PCH-HOST-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 4, ptr @.omp_outlined..1, i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP14]], ptr [[SUM1]]) -// IR-PCH-HOST-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-PCH-HOST: omp.inner.for.inc: -// IR-PCH-HOST-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// IR-PCH-HOST-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// IR-PCH-HOST-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] -// IR-PCH-HOST-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// IR-PCH-HOST-NEXT: br label [[OMP_INNER_FOR_COND]] -// IR-PCH-HOST: omp.inner.for.end: -// IR-PCH-HOST-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-PCH-HOST: omp.loop.exit: -// IR-PCH-HOST-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4 -// IR-PCH-HOST-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP18]]) -// IR-PCH-HOST-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-HOST-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0 -// IR-PCH-HOST-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// IR-PCH-HOST: .omp.lastprivate.then: -// IR-PCH-HOST-NEXT: store i32 10, ptr [[J3]], align 4 -// IR-PCH-HOST-NEXT: [[TMP21:%.*]] = load i32, ptr [[J3]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP21]], ptr [[J_ADDR]], align 4 -// IR-PCH-HOST-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// IR-PCH-HOST: .omp.lastprivate.done: -// IR-PCH-HOST-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// IR-PCH-HOST-NEXT: store ptr [[SUM1]], ptr [[TMP22]], align 8 -// IR-PCH-HOST-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 -// IR-PCH-HOST-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @.omp.reduction.reduction_func.2, ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-HOST-NEXT: switch i32 [[TMP25]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// IR-PCH-HOST-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// IR-PCH-HOST-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// IR-PCH-HOST-NEXT: ] -// IR-PCH-HOST: .omp.reduction.case1: -// IR-PCH-HOST-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP0]], [[TMP26]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR-PCH-HOST: omp.arraycpy.body: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi ptr [ [[TMP0]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], align 4 -// IR-PCH-HOST-NEXT: [[TMP28:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// IR-PCH-HOST-NEXT: store i32 [[ADD7]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP26]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH-HOST: omp.arraycpy.done10: -// IR-PCH-HOST-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-HOST-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR-PCH-HOST: .omp.reduction.case2: -// IR-PCH-HOST-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_ISEMPTY11:%.*]] = icmp eq ptr [[TMP0]], [[TMP29]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY11]], label [[OMP_ARRAYCPY_DONE18:%.*]], label [[OMP_ARRAYCPY_BODY12:%.*]] -// IR-PCH-HOST: omp.arraycpy.body12: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST13:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY12]] ] -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[TMP0]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT15:%.*]], [[OMP_ARRAYCPY_BODY12]] ] -// IR-PCH-HOST-NEXT: [[TMP30:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], align 4 -// IR-PCH-HOST-NEXT: [[TMP31:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 [[TMP30]] monotonic, align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT15]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT16]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT15]], [[TMP29]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY12]] -// IR-PCH-HOST: omp.arraycpy.done18: -// IR-PCH-HOST-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-HOST-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR-PCH-HOST: .omp.reduction.default: -// IR-PCH-HOST-NEXT: ret void -// IR-PCH-HOST-LABEL: define {{[^@]+}}@.omp_outlined..1 -// IR-PCH-HOST-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1]] { -// IR-PCH-HOST-NEXT: entry: -// IR-PCH-HOST-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[J_ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-HOST-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[J3:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[SUM4:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-PCH-HOST-NEXT: [[I:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[J5:%.*]] = alloca i32, align 4 -// IR-PCH-HOST-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// IR-PCH-HOST-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// IR-PCH-HOST-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// IR-PCH-HOST-NEXT: store i64 [[J]], ptr [[J_ADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR]], align 8 -// IR-PCH-HOST-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// IR-PCH-HOST-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// IR-PCH-HOST-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// IR-PCH-HOST-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// IR-PCH-HOST-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// IR-PCH-HOST-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// IR-PCH-HOST-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-HOST-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4]], i32 0, i32 0, i32 0 -// IR-PCH-HOST-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] -// IR-PCH-HOST: omp.arrayinit.body: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// IR-PCH-HOST-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] -// IR-PCH-HOST: omp.arrayinit.done: -// IR-PCH-HOST-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 -// IR-PCH-HOST-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-PCH-HOST-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// IR-PCH-HOST-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 99 -// IR-PCH-HOST-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// IR-PCH-HOST: cond.true: -// IR-PCH-HOST-NEXT: br label [[COND_END:%.*]] -// IR-PCH-HOST: cond.false: -// IR-PCH-HOST-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// IR-PCH-HOST-NEXT: br label [[COND_END]] -// IR-PCH-HOST: cond.end: -// IR-PCH-HOST-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] -// IR-PCH-HOST-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// IR-PCH-HOST-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4 -// IR-PCH-HOST-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-PCH-HOST: omp.inner.for.cond: -// IR-PCH-HOST-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] -// IR-PCH-HOST-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] -// IR-PCH-HOST-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-PCH-HOST: omp.inner.for.body: -// IR-PCH-HOST-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP11]], 10 -// IR-PCH-HOST-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// IR-PCH-HOST-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// IR-PCH-HOST-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP13]], 10 -// IR-PCH-HOST-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 10 -// IR-PCH-HOST-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], [[MUL8]] -// IR-PCH-HOST-NEXT: [[MUL9:%.*]] = mul nsw i32 [[SUB]], 1 -// IR-PCH-HOST-NEXT: [[ADD10:%.*]] = add nsw i32 0, [[MUL9]] -// IR-PCH-HOST-NEXT: store i32 [[ADD10]], ptr [[J3]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// IR-PCH-HOST-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4]], i64 0, i64 [[IDXPROM]] -// IR-PCH-HOST-NEXT: [[TMP16:%.*]] = load i32, ptr [[J3]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 -// IR-PCH-HOST-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// IR-PCH-HOST-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP14]] -// IR-PCH-HOST-NEXT: store i32 [[ADD13]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// IR-PCH-HOST: omp.body.continue: -// IR-PCH-HOST-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-PCH-HOST: omp.inner.for.inc: -// IR-PCH-HOST-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP18]], 1 -// IR-PCH-HOST-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-HOST-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// IR-PCH-HOST: omp.inner.for.end: -// IR-PCH-HOST-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-PCH-HOST: omp.loop.exit: -// IR-PCH-HOST-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 -// IR-PCH-HOST-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP20]]) -// IR-PCH-HOST-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// IR-PCH-HOST-NEXT: store ptr [[SUM4]], ptr [[TMP21]], align 8 -// IR-PCH-HOST-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// IR-PCH-HOST-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-HOST-NEXT: switch i32 [[TMP24]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// IR-PCH-HOST-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// IR-PCH-HOST-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// IR-PCH-HOST-NEXT: ] -// IR-PCH-HOST: .omp.reduction.case1: -// IR-PCH-HOST-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP0]], [[TMP25]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE19:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR-PCH-HOST: omp.arraycpy.body: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM4]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[TMP0]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[TMP26:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// IR-PCH-HOST-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// IR-PCH-HOST-NEXT: store i32 [[ADD16]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP25]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_DONE19]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH-HOST: omp.arraycpy.done19: -// IR-PCH-HOST-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-HOST-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR-PCH-HOST: .omp.reduction.case2: -// IR-PCH-HOST-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_ISEMPTY20:%.*]] = icmp eq ptr [[TMP0]], [[TMP28]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY20]], label [[OMP_ARRAYCPY_DONE27:%.*]], label [[OMP_ARRAYCPY_BODY21:%.*]] -// IR-PCH-HOST: omp.arraycpy.body21: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST22:%.*]] = phi ptr [ [[SUM4]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT25:%.*]], [[OMP_ARRAYCPY_BODY21]] ] -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST23:%.*]] = phi ptr [ [[TMP0]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY21]] ] -// IR-PCH-HOST-NEXT: [[TMP29:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST22]], align 4 -// IR-PCH-HOST-NEXT: [[TMP30:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST23]], i32 [[TMP29]] monotonic, align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT24]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST23]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT25]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST22]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE26:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT24]], [[TMP28]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_DONE27]], label [[OMP_ARRAYCPY_BODY21]] -// IR-PCH-HOST: omp.arraycpy.done27: -// IR-PCH-HOST-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-HOST-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR-PCH-HOST: .omp.reduction.default: -// IR-PCH-HOST-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-HOST-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 -// IR-PCH-HOST-NEXT: br i1 [[TMP32]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// IR-PCH-HOST: .omp.lastprivate.then: -// IR-PCH-HOST-NEXT: store i32 10, ptr [[J3]], align 4 -// IR-PCH-HOST-NEXT: [[TMP33:%.*]] = load i32, ptr [[J3]], align 4 -// IR-PCH-HOST-NEXT: store i32 [[TMP33]], ptr [[J_ADDR]], align 4 -// IR-PCH-HOST-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// IR-PCH-HOST: .omp.lastprivate.done: -// IR-PCH-HOST-NEXT: ret void -// IR-PCH-HOST-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func -// IR-PCH-HOST-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// IR-PCH-HOST-NEXT: entry: -// IR-PCH-HOST-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// IR-PCH-HOST-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// IR-PCH-HOST-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// IR-PCH-HOST-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// IR-PCH-HOST-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// IR-PCH-HOST-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// IR-PCH-HOST-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR-PCH-HOST: omp.arraycpy.body: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// IR-PCH-HOST-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH-HOST: omp.arraycpy.done2: -// IR-PCH-HOST-NEXT: ret void -// IR-PCH-HOST-LABEL: define {{[^@]+}}@.omp.reduction.reduction_func.2 -// IR-PCH-HOST-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { -// IR-PCH-HOST-NEXT: entry: -// IR-PCH-HOST-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// IR-PCH-HOST-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// IR-PCH-HOST-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// IR-PCH-HOST-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// IR-PCH-HOST-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// IR-PCH-HOST-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// IR-PCH-HOST-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// IR-PCH-HOST-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// IR-PCH-HOST-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// IR-PCH-HOST-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 100 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR-PCH-HOST: omp.arraycpy.body: -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-HOST-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// IR-PCH-HOST-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-HOST-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// IR-PCH-HOST-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH-HOST: omp.arraycpy.done2: -// IR-PCH-HOST-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l23 -// CHECK-SAME: (i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[J_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[J_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J_ADDR]] to ptr -// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr -// CHECK-NEXT: [[J_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J_CASTED]] to ptr -// CHECK-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr -// CHECK-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr -// CHECK-NEXT: store i64 [[J]], ptr [[J_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr), i8 2, i1 false) -// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1 -// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] -// CHECK: user_code.entry: -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[J_ADDR_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP3]], ptr [[J_CASTED_ASCAST]], align 4 -// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[J_CASTED_ASCAST]], align 8 -// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 -// CHECK-NEXT: call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]] -// CHECK-NEXT: call void @__kmpc_target_deinit(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i8 2) -// CHECK-NEXT: ret void -// CHECK: worker.exit: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[J_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[SUM1:%.*]] = alloca [10 x [10 x i32]], align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[_TMP2:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J3:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J4:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J_CASTED:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// CHECK-NEXT: [[J_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J_ADDR]] to ptr -// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr -// CHECK-NEXT: [[SUM1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM1]] to ptr -// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// CHECK-NEXT: [[TMP2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP2]] to ptr -// CHECK-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr -// CHECK-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr -// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// CHECK-NEXT: [[J3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J3]] to ptr -// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr -// CHECK-NEXT: [[J4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J4]] to ptr -// CHECK-NEXT: [[J_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J_CASTED]] to ptr -// CHECK-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr -// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[J]], ptr [[J_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM1_ASCAST]], i32 0, i32 0, i32 0 -// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 100 -// CHECK-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP1]] -// CHECK-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] -// CHECK: omp.arrayinit.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP1]] -// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] -// CHECK: omp.arrayinit.done: -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() -// CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP3]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK: cond.true: -// CHECK-NEXT: br label [[COND_END:%.*]] -// CHECK: cond.false: -// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: br label [[COND_END]] -// CHECK: cond.end: -// CHECK-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK: omp.inner.for.cond: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP7]], 100 -// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK: omp.inner.for.body: -// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[J3_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP12]], ptr [[J_CASTED_ASCAST]], align 4 -// CHECK-NEXT: [[TMP13:%.*]] = load i64, ptr [[J_CASTED_ASCAST]], align 8 -// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP9]] to ptr -// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8 -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 -// CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP11]] to ptr -// CHECK-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 -// CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP13]] to ptr -// CHECK-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8 -// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 -// CHECK-NEXT: store ptr [[SUM1_ASCAST]], ptr [[TMP20]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP22]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__.1, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4) -// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK: omp.inner.for.inc: -// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] -// CHECK-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] -// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[CMP8:%.*]] = icmp sgt i32 [[TMP29]], 99 -// CHECK-NEXT: br i1 [[CMP8]], label [[COND_TRUE9:%.*]], label [[COND_FALSE10:%.*]] -// CHECK: cond.true9: -// CHECK-NEXT: br label [[COND_END11:%.*]] -// CHECK: cond.false10: -// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: br label [[COND_END11]] -// CHECK: cond.end11: -// CHECK-NEXT: [[COND12:%.*]] = phi i32 [ 99, [[COND_TRUE9]] ], [ [[TMP30]], [[COND_FALSE10]] ] -// CHECK-NEXT: store i32 [[COND12]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP31]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK: omp.inner.for.end: -// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK: omp.loop.exit: -// CHECK-NEXT: [[TMP32:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[TMP32]], align 4 -// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP33]]) -// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 -// CHECK-NEXT: br i1 [[TMP35]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK: .omp.lastprivate.then: -// CHECK-NEXT: store i32 10, ptr [[J3_ASCAST]], align 4 -// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[J3_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP36]], ptr [[J_ADDR_ASCAST]], align 4 -// CHECK-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK: .omp.lastprivate.done: -// CHECK-NEXT: [[TMP37:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP37]], align 4 -// CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: store ptr [[SUM1_ASCAST]], ptr [[TMP39]], align 8 -// CHECK-NEXT: [[TMP40:%.*]] = load ptr, ptr addrspace(1) @"_openmp_teams_reductions_buffer_$_$ptr", align 8 -// CHECK-NEXT: [[TMP41:%.*]] = call i32 @__kmpc_nvptx_teams_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP38]], ptr [[TMP40]], i32 1024, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func.3, ptr @_omp_reduction_inter_warp_copy_func.4, ptr @_omp_reduction_list_to_global_copy_func, ptr @_omp_reduction_list_to_global_reduce_func, ptr @_omp_reduction_global_to_list_copy_func, ptr @_omp_reduction_global_to_list_reduce_func) -// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i32 [[TMP41]], 1 -// CHECK-NEXT: br i1 [[TMP42]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] -// CHECK: .omp.reduction.then: -// CHECK-NEXT: [[TMP43:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP0]], [[TMP43]] -// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE17:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM1_ASCAST]], [[DOTOMP_REDUCTION_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST13:%.*]] = phi ptr [ [[TMP0]], [[DOTOMP_REDUCTION_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT15:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST13]], align 4 -// CHECK-NEXT: [[TMP45:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// CHECK-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP44]], [[TMP45]] -// CHECK-NEXT: store i32 [[ADD14]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST13]], align 4 -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT15]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST13]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE16:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT15]], [[TMP43]] -// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE16]], label [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_BODY]] -// CHECK: omp.arraycpy.done17: -// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] -// CHECK: .omp.reduction.done: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@__omp_outlined__.1 -// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[J_ADDR:%.*]] = alloca i64, align 8, addrspace(5) -// CHECK-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[_TMP1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J3:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[SUM4:%.*]] = alloca [10 x [10 x i32]], align 4, addrspace(5) -// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[J5:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr -// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr -// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr -// CHECK-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr -// CHECK-NEXT: [[J_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J_ADDR]] to ptr -// CHECK-NEXT: [[SUM_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM_ADDR]] to ptr -// CHECK-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr -// CHECK-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr -// CHECK-NEXT: [[TMP1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP1]] to ptr -// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr -// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr -// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr -// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr -// CHECK-NEXT: [[J3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J3]] to ptr -// CHECK-NEXT: [[SUM4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SUM4]] to ptr -// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr -// CHECK-NEXT: [[J5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J5]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr -// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i64 [[J]], ptr [[J_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SUM_ADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 99, ptr [[DOTOMP_UB_ASCAST]], align 4 -// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB_ASCAST]], align 4 -// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 -// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4_ASCAST]], i32 0, i32 0, i32 0 -// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 100 -// CHECK-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]] -// CHECK-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] -// CHECK: omp.arrayinit.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// CHECK-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]] -// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] -// CHECK: omp.arrayinit.done: -// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4 -// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) -// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV_ASCAST]], align 4 -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK: omp.inner.for.cond: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] -// CHECK-NEXT: [[CONV6:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV6]], [[TMP8]] -// CHECK-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK: omp.inner.for.body: -// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP9]], 10 -// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK-NEXT: store i32 [[ADD]], ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP11]], 10 -// CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 10 -// CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP10]], [[MUL8]] -// CHECK-NEXT: [[MUL9:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK-NEXT: [[ADD10:%.*]] = add nsw i32 0, [[MUL9]] -// CHECK-NEXT: store i32 [[ADD10]], ptr [[J3_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[I_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4_ASCAST]], i64 0, i64 [[IDXPROM]] -// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[J3_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP15]], [[TMP12]] -// CHECK-NEXT: store i32 [[ADD13]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK: omp.body.continue: -// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK: omp.inner.for.inc: -// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV_ASCAST]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] -// CHECK: omp.inner.for.end: -// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK: omp.loop.exit: -// CHECK-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 -// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP19]]) -// CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: store ptr [[SUM4_ASCAST]], ptr [[TMP22]], align 8 -// CHECK-NEXT: [[TMP23:%.*]] = call i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP21]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr @_omp_reduction_shuffle_and_reduce_func, ptr @_omp_reduction_inter_warp_copy_func) -// CHECK-NEXT: [[TMP24:%.*]] = icmp eq i32 [[TMP23]], 1 -// CHECK-NEXT: br i1 [[TMP24]], label [[DOTOMP_REDUCTION_THEN:%.*]], label [[DOTOMP_REDUCTION_DONE:%.*]] -// CHECK: .omp.reduction.then: -// CHECK-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 -// CHECK-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP0]], [[TMP25]] -// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE19:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// CHECK: omp.arraycpy.body: -// CHECK-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM4_ASCAST]], [[DOTOMP_REDUCTION_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[TMP0]], [[DOTOMP_REDUCTION_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// CHECK-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// CHECK-NEXT: store i32 [[ADD16]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// CHECK-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// CHECK-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP25]] -// CHECK-NEXT: br i1 [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_DONE19]], label [[OMP_ARRAYCPY_BODY]] -// CHECK: omp.arraycpy.done19: -// CHECK-NEXT: br label [[DOTOMP_REDUCTION_DONE]] -// CHECK: .omp.reduction.done: -// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 -// CHECK-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 -// CHECK-NEXT: br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// CHECK: .omp.lastprivate.then: -// CHECK-NEXT: store i32 10, ptr [[J3_ASCAST]], align 4 -// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[J3_ASCAST]], align 4 -// CHECK-NEXT: store i32 [[TMP30]], ptr [[J_ADDR_ASCAST]], align 4 -// CHECK-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// CHECK: .omp.lastprivate.done: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) -// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca [10 x [10 x i32]], align 4, addrspace(5) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr -// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 -// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 -// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 -// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 -// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 -// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 -// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP9]], i64 1 -// CHECK-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]] -// CHECK: .shuffle.pre_cond: -// CHECK-NEXT: [[TMP12:%.*]] = phi ptr [ [[TMP9]], [[ENTRY:%.*]] ], [ [[TMP23:%.*]], [[DOTSHUFFLE_THEN:%.*]] ] -// CHECK-NEXT: [[TMP13:%.*]] = phi ptr [ [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], [[ENTRY]] ], [ [[TMP24:%.*]], [[DOTSHUFFLE_THEN]] ] -// CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP11]] to i64 -// CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP12]] to i64 -// CHECK-NEXT: [[TMP16:%.*]] = sub i64 [[TMP14]], [[TMP15]] -// CHECK-NEXT: [[TMP17:%.*]] = sdiv exact i64 [[TMP16]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) -// CHECK-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP17]], 7 -// CHECK-NEXT: br i1 [[TMP18]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]] -// CHECK: .shuffle.then: -// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP12]], align 4 -// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_warp_size() -// CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16 -// CHECK-NEXT: [[TMP22:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP19]], i16 [[TMP6]], i16 [[TMP21]]) -// CHECK-NEXT: store i64 [[TMP22]], ptr [[TMP13]], align 4 -// CHECK-NEXT: [[TMP23]] = getelementptr i64, ptr [[TMP12]], i64 1 -// CHECK-NEXT: [[TMP24]] = getelementptr i64, ptr [[TMP13]], i64 1 -// CHECK-NEXT: br label [[DOTSHUFFLE_PRE_COND]] -// CHECK: .shuffle.exit: -// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 -// CHECK-NEXT: [[TMP25:%.*]] = icmp eq i16 [[TMP7]], 0 -// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i16 [[TMP7]], 1 -// CHECK-NEXT: [[TMP27:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] -// CHECK-NEXT: [[TMP28:%.*]] = and i1 [[TMP26]], [[TMP27]] -// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP7]], 2 -// CHECK-NEXT: [[TMP30:%.*]] = and i16 [[TMP5]], 1 -// CHECK-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP30]], 0 -// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP29]], [[TMP31]] -// CHECK-NEXT: [[TMP33:%.*]] = icmp sgt i16 [[TMP6]], 0 -// CHECK-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]] -// CHECK-NEXT: [[TMP35:%.*]] = or i1 [[TMP25]], [[TMP28]] -// CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP35]], [[TMP34]] -// CHECK-NEXT: br i1 [[TMP36]], label [[THEN:%.*]], label [[ELSE:%.*]] -// CHECK: then: -// CHECK-NEXT: call void @"_omp$reduction$reduction_func"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR2]] -// CHECK-NEXT: br label [[IFCONT:%.*]] -// CHECK: else: -// CHECK-NEXT: br label [[IFCONT]] -// CHECK: ifcont: -// CHECK-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP7]], 1 -// CHECK-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] -// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]] -// CHECK-NEXT: br i1 [[TMP39]], label [[THEN4:%.*]], label [[ELSE5:%.*]] -// CHECK: then4: -// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[TMP41:%.*]] = load ptr, ptr [[TMP40]], align 8 -// CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 -// CHECK-NEXT: [[TMP43:%.*]] = load ptr, ptr [[TMP42]], align 8 -// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP43]], ptr align 4 [[TMP41]], i64 400, i1 false) -// CHECK-NEXT: br label [[IFCONT6:%.*]] -// CHECK: else5: -// CHECK-NEXT: br label [[IFCONT6]] -// CHECK: ifcont6: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTCNT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCNT_ADDR]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() -// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() -// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 63 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() -// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 6 -// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 0, ptr [[DOTCNT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: br label [[PRECOND:%.*]] -// CHECK: precond: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCNT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 [[TMP7]], 100 -// CHECK-NEXT: br i1 [[TMP8]], label [[BODY:%.*]], label [[EXIT:%.*]] -// CHECK: body: -// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4:[0-9]+]] to ptr), i32 [[TMP2]]) -// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 -// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] -// CHECK: then: -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP6]], i64 0, i64 0 -// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i32 [[TMP7]] -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] -// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK-NEXT: store volatile i32 [[TMP13]], ptr addrspace(3) [[TMP12]], align 4 -// CHECK-NEXT: br label [[IFCONT:%.*]] -// CHECK: else: -// CHECK-NEXT: br label [[IFCONT]] -// CHECK: ifcont: -// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP2]]) -// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP14]] -// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.*]], label [[ELSE3:%.*]] -// CHECK: then2: -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]] -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP6]], i64 0, i64 0 -// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP17]], i32 [[TMP7]] -// CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr addrspace(3) [[TMP15]], align 4 -// CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4 -// CHECK-NEXT: br label [[IFCONT4:%.*]] -// CHECK: else3: -// CHECK-NEXT: br label [[IFCONT4]] -// CHECK: ifcont4: -// CHECK-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK-NEXT: store i32 [[TMP20]], ptr [[DOTCNT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: br label [[PRECOND]] -// CHECK: exit: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_shuffle_and_reduce_func.3 -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i16 noundef signext [[TMP1:%.*]], i16 noundef signext [[TMP2:%.*]], i16 noundef signext [[TMP3:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i16, align 2, addrspace(5) -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca i16, align 2, addrspace(5) -// CHECK-NEXT: [[DOTADDR3:%.*]] = alloca i16, align 2, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT:%.*]] = alloca [10 x [10 x i32]], align 4, addrspace(5) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr -// CHECK-NEXT: [[DOTADDR3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR3]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_ELEMENT_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_ELEMENT]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i16 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 2 -// CHECK-NEXT: store i16 [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 2 -// CHECK-NEXT: store i16 [[TMP3]], ptr [[DOTADDR3_ASCAST]], align 2 -// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[DOTADDR1_ASCAST]], align 2 -// CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr [[DOTADDR2_ASCAST]], align 2 -// CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr [[DOTADDR3_ASCAST]], align 2 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 -// CHECK-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP9]], i64 1 -// CHECK-NEXT: br label [[DOTSHUFFLE_PRE_COND:%.*]] -// CHECK: .shuffle.pre_cond: -// CHECK-NEXT: [[TMP12:%.*]] = phi ptr [ [[TMP9]], [[ENTRY:%.*]] ], [ [[TMP23:%.*]], [[DOTSHUFFLE_THEN:%.*]] ] -// CHECK-NEXT: [[TMP13:%.*]] = phi ptr [ [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], [[ENTRY]] ], [ [[TMP24:%.*]], [[DOTSHUFFLE_THEN]] ] -// CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP11]] to i64 -// CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP12]] to i64 -// CHECK-NEXT: [[TMP16:%.*]] = sub i64 [[TMP14]], [[TMP15]] -// CHECK-NEXT: [[TMP17:%.*]] = sdiv exact i64 [[TMP16]], ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64) -// CHECK-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP17]], 7 -// CHECK-NEXT: br i1 [[TMP18]], label [[DOTSHUFFLE_THEN]], label [[DOTSHUFFLE_EXIT:%.*]] -// CHECK: .shuffle.then: -// CHECK-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP12]], align 4 -// CHECK-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_get_warp_size() -// CHECK-NEXT: [[TMP21:%.*]] = trunc i32 [[TMP20]] to i16 -// CHECK-NEXT: [[TMP22:%.*]] = call i64 @__kmpc_shuffle_int64(i64 [[TMP19]], i16 [[TMP6]], i16 [[TMP21]]) -// CHECK-NEXT: store i64 [[TMP22]], ptr [[TMP13]], align 4 -// CHECK-NEXT: [[TMP23]] = getelementptr i64, ptr [[TMP12]], i64 1 -// CHECK-NEXT: [[TMP24]] = getelementptr i64, ptr [[TMP13]], i64 1 -// CHECK-NEXT: br label [[DOTSHUFFLE_PRE_COND]] -// CHECK: .shuffle.exit: -// CHECK-NEXT: store ptr [[DOTOMP_REDUCTION_ELEMENT_ASCAST]], ptr [[TMP10]], align 8 -// CHECK-NEXT: [[TMP25:%.*]] = icmp eq i16 [[TMP7]], 0 -// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i16 [[TMP7]], 1 -// CHECK-NEXT: [[TMP27:%.*]] = icmp ult i16 [[TMP5]], [[TMP6]] -// CHECK-NEXT: [[TMP28:%.*]] = and i1 [[TMP26]], [[TMP27]] -// CHECK-NEXT: [[TMP29:%.*]] = icmp eq i16 [[TMP7]], 2 -// CHECK-NEXT: [[TMP30:%.*]] = and i16 [[TMP5]], 1 -// CHECK-NEXT: [[TMP31:%.*]] = icmp eq i16 [[TMP30]], 0 -// CHECK-NEXT: [[TMP32:%.*]] = and i1 [[TMP29]], [[TMP31]] -// CHECK-NEXT: [[TMP33:%.*]] = icmp sgt i16 [[TMP6]], 0 -// CHECK-NEXT: [[TMP34:%.*]] = and i1 [[TMP32]], [[TMP33]] -// CHECK-NEXT: [[TMP35:%.*]] = or i1 [[TMP25]], [[TMP28]] -// CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP35]], [[TMP34]] -// CHECK-NEXT: br i1 [[TMP36]], label [[THEN:%.*]], label [[ELSE:%.*]] -// CHECK: then: -// CHECK-NEXT: call void @"_omp$reduction$reduction_func.2"(ptr [[TMP4]], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]]) #[[ATTR2]] -// CHECK-NEXT: br label [[IFCONT:%.*]] -// CHECK: else: -// CHECK-NEXT: br label [[IFCONT]] -// CHECK: ifcont: -// CHECK-NEXT: [[TMP37:%.*]] = icmp eq i16 [[TMP7]], 1 -// CHECK-NEXT: [[TMP38:%.*]] = icmp uge i16 [[TMP5]], [[TMP6]] -// CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]] -// CHECK-NEXT: br i1 [[TMP39]], label [[THEN4:%.*]], label [[ELSE5:%.*]] -// CHECK: then4: -// CHECK-NEXT: [[TMP40:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_REMOTE_REDUCE_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[TMP41:%.*]] = load ptr, ptr [[TMP40]], align 8 -// CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP4]], i64 0, i64 0 -// CHECK-NEXT: [[TMP43:%.*]] = load ptr, ptr [[TMP42]], align 8 -// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP43]], ptr align 4 [[TMP41]], i64 400, i1 false) -// CHECK-NEXT: br label [[IFCONT6:%.*]] -// CHECK: else5: -// CHECK-NEXT: br label [[IFCONT6]] -// CHECK: ifcont6: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_inter_warp_copy_func.4 -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTCNT_ADDR:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTCNT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCNT_ADDR]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() -// CHECK-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() -// CHECK-NEXT: [[NVPTX_LANE_ID:%.*]] = and i32 [[TMP4]], 63 -// CHECK-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_get_hardware_thread_id_in_block() -// CHECK-NEXT: [[NVPTX_WARP_ID:%.*]] = ashr i32 [[TMP5]], 6 -// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 0, ptr [[DOTCNT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: br label [[PRECOND:%.*]] -// CHECK: precond: -// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCNT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 [[TMP7]], 100 -// CHECK-NEXT: br i1 [[TMP8]], label [[BODY:%.*]], label [[EXIT:%.*]] -// CHECK: body: -// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP2]]) -// CHECK-NEXT: [[WARP_MASTER:%.*]] = icmp eq i32 [[NVPTX_LANE_ID]], 0 -// CHECK-NEXT: br i1 [[WARP_MASTER]], label [[THEN:%.*]], label [[ELSE:%.*]] -// CHECK: then: -// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP6]], i64 0, i64 0 -// CHECK-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP9]], align 8 -// CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP10]], i32 [[TMP7]] -// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[NVPTX_WARP_ID]] -// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK-NEXT: store volatile i32 [[TMP13]], ptr addrspace(3) [[TMP12]], align 4 -// CHECK-NEXT: br label [[IFCONT:%.*]] -// CHECK: else: -// CHECK-NEXT: br label [[IFCONT]] -// CHECK: ifcont: -// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP2]]) -// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[IS_ACTIVE_THREAD:%.*]] = icmp ult i32 [[TMP3]], [[TMP14]] -// CHECK-NEXT: br i1 [[IS_ACTIVE_THREAD]], label [[THEN2:%.*]], label [[ELSE3:%.*]] -// CHECK: then2: -// CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [64 x i32], ptr addrspace(3) @__openmp_nvptx_data_transfer_temporary_storage, i64 0, i32 [[TMP3]] -// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP6]], i64 0, i64 0 -// CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP16]], align 8 -// CHECK-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP17]], i32 [[TMP7]] -// CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr addrspace(3) [[TMP15]], align 4 -// CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP18]], align 4 -// CHECK-NEXT: br label [[IFCONT4:%.*]] -// CHECK: else3: -// CHECK-NEXT: br label [[IFCONT4]] -// CHECK: ifcont4: -// CHECK-NEXT: [[TMP20:%.*]] = add nsw i32 [[TMP7]], 1 -// CHECK-NEXT: store i32 [[TMP20]], ptr [[DOTCNT_ADDR_ASCAST]], align 4 -// CHECK-NEXT: br label [[PRECOND]] -// CHECK: exit: -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_copy_func -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK-NEXT: [[SUM:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1024 x [10 x [10 x i32]]], ptr [[SUM]], i32 0, i32 [[TMP5]] -// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP8]], ptr align 4 [[TMP7]], i64 400, i1 false) -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_list_to_global_reduce_func -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[SUM:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1024 x [10 x [10 x i32]]], ptr [[SUM]], i32 0, i32 [[TMP4]] -// CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8 -// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: call void @"_omp$reduction$reduction_func.2"(ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], ptr [[TMP7]]) #[[ATTR2]] -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_copy_func -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK-NEXT: [[SUM:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP4]], i32 0, i32 0 -// CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1024 x [10 x [10 x i32]]], ptr [[SUM]], i32 0, i32 [[TMP5]] -// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP7]], ptr align 128 [[TMP8]], i64 400, i1 false) -// CHECK-NEXT: ret void -// CHECK-LABEL: define {{[^@]+}}@_omp_reduction_global_to_list_reduce_func -// CHECK-SAME: (ptr noundef [[TMP0:%.*]], i32 noundef [[TMP1:%.*]], ptr noundef [[TMP2:%.*]]) #[[ATTR3]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5) -// CHECK-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8, addrspace(5) -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8, addrspace(5) -// CHECK-NEXT: [[DOTADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR]] to ptr -// CHECK-NEXT: [[DOTADDR1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR1]] to ptr -// CHECK-NEXT: [[DOTADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTADDR2]] to ptr -// CHECK-NEXT: [[DOTOMP_REDUCTION_RED_LIST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_REDUCTION_RED_LIST]] to ptr -// CHECK-NEXT: store ptr [[TMP0]], ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: store i32 [[TMP1]], ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR_ASCAST]], align 8 -// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTADDR1_ASCAST]], align 4 -// CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]], i64 0, i64 0 -// CHECK-NEXT: [[SUM:%.*]] = getelementptr inbounds [[STRUCT__GLOBALIZED_LOCALS_TY:%.*]], ptr [[TMP3]], i32 0, i32 0 -// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1024 x [10 x [10 x i32]]], ptr [[SUM]], i32 0, i32 [[TMP4]] -// CHECK-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8 -// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2_ASCAST]], align 8 -// CHECK-NEXT: call void @"_omp$reduction$reduction_func.2"(ptr [[TMP7]], ptr [[DOTOMP_REDUCTION_RED_LIST_ASCAST]]) #[[ATTR2]] -// CHECK-NEXT: ret void // IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22 // IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR0:[0-9]+]] { // IR-GPU-NEXT: entry: @@ -2015,7 +903,7 @@ int foo() { // IR-NEXT: store ptr [[SUM1]], ptr [[TMP22]], align 8 // IR-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 -// IR-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// IR-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: switch i32 [[TMP25]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // IR-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // IR-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] @@ -2036,7 +924,7 @@ int foo() { // IR-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP26]] // IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] // IR: omp.arraycpy.done10: -// IR-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) +// IR-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR: .omp.reduction.case2: // IR-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 @@ -2052,7 +940,6 @@ int foo() { // IR-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT15]], [[TMP29]] // IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY12]] // IR: omp.arraycpy.done18: -// IR-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR: .omp.reduction.default: // IR-NEXT: ret void @@ -2171,7 +1058,7 @@ int foo() { // IR-NEXT: store ptr [[SUM4]], ptr [[TMP21]], align 8 // IR-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// IR-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// IR-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: switch i32 [[TMP24]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // IR-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // IR-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] @@ -2192,7 +1079,7 @@ int foo() { // IR-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP25]] // IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_DONE19]], label [[OMP_ARRAYCPY_BODY]] // IR: omp.arraycpy.done19: -// IR-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) +// IR-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR: .omp.reduction.case2: // IR-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 @@ -2208,7 +1095,6 @@ int foo() { // IR-NEXT: [[OMP_ARRAYCPY_DONE26:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT24]], [[TMP28]] // IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_DONE27]], label [[OMP_ARRAYCPY_BODY21]] // IR: omp.arraycpy.done27: -// IR-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR: .omp.reduction.default: // IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 @@ -2412,7 +1298,7 @@ int foo() { // IR-PCH-NEXT: store ptr [[SUM1]], ptr [[TMP22]], align 8 // IR-PCH-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // IR-PCH-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 -// IR-PCH-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3:[0-9]+]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// IR-PCH-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: switch i32 [[TMP25]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // IR-PCH-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // IR-PCH-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] @@ -2433,7 +1319,7 @@ int foo() { // IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP26]] // IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] // IR-PCH: omp.arraycpy.done10: -// IR-PCH-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) +// IR-PCH-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR-PCH: .omp.reduction.case2: // IR-PCH-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 @@ -2449,7 +1335,6 @@ int foo() { // IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT15]], [[TMP29]] // IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY12]] // IR-PCH: omp.arraycpy.done18: -// IR-PCH-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR-PCH: .omp.reduction.default: // IR-PCH-NEXT: ret void @@ -2568,7 +1453,7 @@ int foo() { // IR-PCH-NEXT: store ptr [[SUM4]], ptr [[TMP21]], align 8 // IR-PCH-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// IR-PCH-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce(ptr @[[GLOB3]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// IR-PCH-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l22.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: switch i32 [[TMP24]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // IR-PCH-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // IR-PCH-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] @@ -2589,7 +1474,7 @@ int foo() { // IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP25]] // IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_DONE19]], label [[OMP_ARRAYCPY_BODY]] // IR-PCH: omp.arraycpy.done19: -// IR-PCH-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) +// IR-PCH-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR-PCH: .omp.reduction.case2: // IR-PCH-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP0]], i64 100 @@ -2605,7 +1490,6 @@ int foo() { // IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE26:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT24]], [[TMP28]] // IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_DONE27]], label [[OMP_ARRAYCPY_BODY21]] // IR-PCH: omp.arraycpy.done27: -// IR-PCH-NEXT: call void @__kmpc_end_reduce(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR-PCH: .omp.reduction.default: // IR-PCH-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen_as_distribute.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_distribute.cpp new file mode 100644 index 000000000000..f3bbbc6229ab --- /dev/null +++ b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_distribute.cpp @@ -0,0 +1,587 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --version 2 +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=IR-GPU + +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR + +// Check same results after serialization round-trip +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH +extern int foo(int i); + +// expected-no-diagnostics + +#ifndef HEADER +#define HEADER +int N = 100000; +int main() +{ + int i; + int a[N]; + int b[N]; + + // Presence of call. Cannot use 'parallel for', must use 'distribute' when + // assume-no-neseted-parallelism isn't specified. + #pragma omp target teams loop + for (i=0; i < N; i++) { + for (int j=0; j < N; j++) { + a[i] = b[i] * N + foo(j); + } + } + return 0; +} +#endif +// IR-GPU-LABEL: define weak_odr protected amdgpu_kernel void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 +// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_kernel_environment to ptr), ptr [[DYN_PTR]]) +// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// IR-GPU: user_code.entry: +// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] +// IR-GPU-NEXT: call void @__kmpc_target_deinit() +// IR-GPU-NEXT: ret void +// IR-GPU: worker.exit: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1:[0-9]+]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I5:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[I5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I5]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-GPU-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-GPU: cond.true: +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END:%.*]] +// IR-GPU: cond.false: +// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END]] +// IR-GPU: cond.end: +// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-GPU-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-GPU-NEXT: store i32 [[ADD]], ptr [[I5_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[FOR_COND:%.*]] +// IR-GPU: for.cond: +// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP18]], [[TMP19]] +// IR-GPU-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR-GPU: for.body: +// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[I5_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP21]], [[TMP22]] +// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP23]]) #[[ATTR4:[0-9]+]] +// IR-GPU-NEXT: [[ADD10:%.*]] = add nsw i32 [[MUL9]], [[CALL]] +// IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[I5_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP24]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM11]] +// IR-GPU-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4 +// IR-GPU-NEXT: br label [[FOR_INC:%.*]] +// IR-GPU: for.inc: +// IR-GPU-NEXT: [[TMP25:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[INC:%.*]] = add nsw i32 [[TMP25]], 1 +// IR-GPU-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] +// IR-GPU: for.end: +// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-GPU: omp.body.continue: +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP26]], 1 +// IR-GPU-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP28]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-LABEL: define dso_local noundef i32 @main +// IR-SAME: () #[[ATTR0:[0-9]+]] { +// IR-NEXT: entry: +// IR-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// IR-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// IR-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// IR-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// IR-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 +// IR-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// IR-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP4]], align 16 +// IR-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27(i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3:[0-9]+]] +// IR-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// IR-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP7]]) +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4 +// IR-NEXT: ret i32 [[TMP8]] +// +// +// IR-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 +// IR-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// IR-NEXT: entry: +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NEXT: ret void +// +// +// IR-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I5:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: omp.precond.then: +// IR-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD]], ptr [[I5]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: br label [[FOR_COND:%.*]] +// IR: for.cond: +// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP18]], [[TMP19]] +// IR-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR: for.body: +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[I5]], align 4 +// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP21]], [[TMP22]] +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP23]]) +// IR-NEXT: [[ADD10:%.*]] = add nsw i32 [[MUL9]], [[CALL]] +// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[I5]], align 4 +// IR-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP24]] to i64 +// IR-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM11]] +// IR-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4 +// IR-NEXT: br label [[FOR_INC:%.*]] +// IR: for.inc: +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP25]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[J]], align 4 +// IR-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// IR: for.end: +// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR: omp.body.continue: +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP26]], 1 +// IR-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP28]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-PCH-LABEL: define dso_local noundef i32 @main +// IR-PCH-SAME: () #[[ATTR0:[0-9]+]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// IR-PCH-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// IR-PCH-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// IR-PCH-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 +// IR-PCH-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// IR-PCH-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP4]], align 16 +// IR-PCH-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27(i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3:[0-9]+]] +// IR-PCH-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// IR-PCH-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP7]]) +// IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4 +// IR-PCH-NEXT: ret i32 [[TMP8]] +// +// +// IR-PCH-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 +// IR-PCH-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define internal void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I5:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-PCH-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-PCH-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-PCH-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-PCH-NEXT: store i32 [[ADD]], ptr [[I5]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NEXT: br label [[FOR_COND:%.*]] +// IR-PCH: for.cond: +// IR-PCH-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP18]], [[TMP19]] +// IR-PCH-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR-PCH: for.body: +// IR-PCH-NEXT: [[TMP20:%.*]] = load i32, ptr [[I5]], align 4 +// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-PCH-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: [[MUL9:%.*]] = mul nsw i32 [[TMP21]], [[TMP22]] +// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP23]]) +// IR-PCH-NEXT: [[ADD10:%.*]] = add nsw i32 [[MUL9]], [[CALL]] +// IR-PCH-NEXT: [[TMP24:%.*]] = load i32, ptr [[I5]], align 4 +// IR-PCH-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP24]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM11]] +// IR-PCH-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4 +// IR-PCH-NEXT: br label [[FOR_INC:%.*]] +// IR-PCH: for.inc: +// IR-PCH-NEXT: [[TMP25:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[INC:%.*]] = add nsw i32 [[TMP25]], 1 +// IR-PCH-NEXT: store i32 [[INC]], ptr [[J]], align 4 +// IR-PCH-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] +// IR-PCH: for.end: +// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-PCH: omp.body.continue: +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP26]], 1 +// IR-PCH-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP28]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp new file mode 100644 index 000000000000..7c7cdc53fa2d --- /dev/null +++ b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp @@ -0,0 +1,3998 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// REQUIRES: amdgpu-registered-target + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=IR-GPU + +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=IR + +// Check same results after serialization round-trip +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -emit-pch -o %t %s +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH + + +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-assume-no-nested-parallelism -DNESTED -emit-llvm-bc %s -o %t-ppc-host.bc +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-assume-no-nested-parallelism -DNESTED -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=IR-GPU-NESTED + +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-assume-no-nested-parallelism -DNESTED -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-NESTED + +// Check same results after serialization round-trip +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -fopenmp-assume-no-nested-parallelism -DNESTED -emit-pch -o %t %s +// RUN: %clang_cc1 -verify -triple x86_64-pc-linux-gnu -fopenmp -include-pch %t -fopenmp-assume-no-nested-parallelism -DNESTED -emit-llvm %s -o - | FileCheck %s --check-prefix=IR-PCH-NESTED + +// expected-no-diagnostics + +#ifndef NESTED +extern int omp_get_num_teams(void); +#endif + +#ifndef HEADER +#define HEADER +extern int foo(int i); + +int N = 100000; +int main() +{ + int a[N]; + int b[N]; + +#ifndef NESTED + // Should be transformed into 'target teams distribute parallel for' + #pragma omp target teams loop + for (int j = 0; j != N; j++) + a[j]=b[j]; + + // Should be transformed into 'target teams distribute parallel for' + #pragma omp target teams loop collapse(2) + for (int i = 0; i < N; i++) { + for (int j = 0; j < N; j++) { + a[i] = b[i] * N + j; + } + } + + int nt = 0; + // Should be transformed into 'target teams distribute parallel for' + #pragma omp target teams loop num_teams(32) + for (int i=0; i < N; i++) { + if (!nt) nt = omp_get_num_teams(); + for (int j=0; j < N; j++) + a[j] = b[j] * N + nt; + } +#else + // Should be transformed into 'target teams distribute parallel for' + // even with function call because of assume-no-nested-parallelism. + #pragma omp target teams loop collapse(2) + for (int i = 0; i < N; i++) { + for (int j = 0; j < N; j++) { + a[i] = b[i] * N + foo(j); + } + } +#endif + return 0; +} +#endif +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 +// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_kernel_environment to ptr), ptr [[DYN_PTR]]) +// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// IR-GPU: user_code.entry: +// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] +// IR-GPU-NEXT: call void @__kmpc_target_deinit() +// IR-GPU-NEXT: ret void +// IR-GPU: worker.exit: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1:[0-9]+]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J5:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[J5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J5]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-GPU-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-GPU: cond.true: +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END:%.*]] +// IR-GPU: cond.false: +// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END]] +// IR-GPU: cond.end: +// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// IR-GPU-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// IR-GPU-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP21]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// IR-GPU-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr +// IR-GPU-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8 +// IR-GPU-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// IR-GPU-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr +// IR-GPU-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8 +// IR-GPU-NEXT: [[TMP27:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// IR-GPU-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP22]] to ptr +// IR-GPU-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8 +// IR-GPU-NEXT: [[TMP29:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// IR-GPU-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP0]] to ptr +// IR-GPU-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8 +// IR-GPU-NEXT: [[TMP31:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 +// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP31]], align 8 +// IR-GPU-NEXT: [[TMP32:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 +// IR-GPU-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP2]] to ptr +// IR-GPU-NEXT: store ptr [[TMP33]], ptr [[TMP32]], align 8 +// IR-GPU-NEXT: [[TMP34:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6 +// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP34]], align 8 +// IR-GPU-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4 +// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP36]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7) +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]] +// IR-GPU-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP39]], [[TMP40]] +// IR-GPU-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP41]], [[TMP42]] +// IR-GPU-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], [[TMP44]] +// IR-GPU-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// IR-GPU: cond.true12: +// IR-GPU-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END14:%.*]] +// IR-GPU: cond.false13: +// IR-GPU-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END14]] +// IR-GPU: cond.end14: +// IR-GPU-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP45]], [[COND_TRUE12]] ], [ [[TMP46]], [[COND_FALSE13]] ] +// IR-GPU-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP47]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP48:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP49]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J6:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[J6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J6]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// IR-GPU-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CMP8:%.*]] = icmp ule i64 [[CONV7]], [[TMP14]] +// IR-GPU-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-GPU-NEXT: store i32 [[ADD]], ptr [[J6_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[J6_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[J6_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM9]] +// IR-GPU-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX10]], align 4 +// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-GPU: omp.body.continue: +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] +// IR-GPU-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 +// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP22]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 +// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_kernel_environment to ptr), ptr [[DYN_PTR]]) +// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// IR-GPU: user_code.entry: +// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] +// IR-GPU-NEXT: call void @__kmpc_target_deinit() +// IR-GPU-NEXT: ret void +// IR-GPU: worker.exit: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[_TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I11:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J12:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[TMP3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP3]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_5]] to ptr +// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[I11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I11]] to ptr +// IR-GPU-NEXT: [[J12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J12]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-GPU-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-GPU-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-GPU-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-GPU-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: land.lhs.true: +// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-GPU-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[CONV13:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64 +// IR-GPU-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP12]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 [[CONV13]]) +// IR-GPU-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] +// IR-GPU-NEXT: br i1 [[CMP14]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-GPU: cond.true: +// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[COND_END:%.*]] +// IR-GPU: cond.false: +// IR-GPU-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[COND_END]] +// IR-GPU: cond.end: +// IR-GPU-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// IR-GPU-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP19]], 1 +// IR-GPU-NEXT: [[CMP15:%.*]] = icmp slt i64 [[TMP18]], [[ADD]] +// IR-GPU-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP22]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP24:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// IR-GPU-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP20]] to ptr +// IR-GPU-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 +// IR-GPU-NEXT: [[TMP26:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// IR-GPU-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP21]] to ptr +// IR-GPU-NEXT: store ptr [[TMP27]], ptr [[TMP26]], align 8 +// IR-GPU-NEXT: [[TMP28:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// IR-GPU-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP23]] to ptr +// IR-GPU-NEXT: store ptr [[TMP29]], ptr [[TMP28]], align 8 +// IR-GPU-NEXT: [[TMP30:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// IR-GPU-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP0]] to ptr +// IR-GPU-NEXT: store ptr [[TMP31]], ptr [[TMP30]], align 8 +// IR-GPU-NEXT: [[TMP32:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 +// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP32]], align 8 +// IR-GPU-NEXT: [[TMP33:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 +// IR-GPU-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP2]] to ptr +// IR-GPU-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 8 +// IR-GPU-NEXT: [[TMP35:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6 +// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP35]], align 8 +// IR-GPU-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 +// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP37]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7) +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NEXT: [[ADD16:%.*]] = add nsw i64 [[TMP38]], [[TMP39]] +// IR-GPU-NEXT: store i64 [[ADD16]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP40]], [[TMP41]] +// IR-GPU-NEXT: store i64 [[ADD17]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP42]], [[TMP43]] +// IR-GPU-NEXT: store i64 [[ADD18]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: [[CMP19:%.*]] = icmp sgt i64 [[TMP44]], [[TMP45]] +// IR-GPU-NEXT: br i1 [[CMP19]], label [[COND_TRUE20:%.*]], label [[COND_FALSE21:%.*]] +// IR-GPU: cond.true20: +// IR-GPU-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[COND_END22:%.*]] +// IR-GPU: cond.false21: +// IR-GPU-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[COND_END22]] +// IR-GPU: cond.end22: +// IR-GPU-NEXT: [[COND23:%.*]] = phi i64 [ [[TMP46]], [[COND_TRUE20]] ], [ [[TMP47]], [[COND_FALSE21]] ] +// IR-GPU-NEXT: store i64 [[COND23]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP48]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP49:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP50]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[_TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I11:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J12:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[TMP3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP3]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_5]] to ptr +// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[I11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I11]] to ptr +// IR-GPU-NEXT: [[J12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J12]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-GPU-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-GPU-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-GPU-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-GPU-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: land.lhs.true: +// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-GPU-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i64 0, ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// IR-GPU-NEXT: call void @__kmpc_for_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP14]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 1) +// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CMP13:%.*]] = icmp ule i64 [[TMP16]], [[TMP17]] +// IR-GPU-NEXT: br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP19]], 0 +// IR-GPU-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// IR-GPU-NEXT: [[MUL16:%.*]] = mul nsw i32 1, [[DIV15]] +// IR-GPU-NEXT: [[CONV17:%.*]] = sext i32 [[MUL16]] to i64 +// IR-GPU-NEXT: [[DIV18:%.*]] = sdiv i64 [[TMP18]], [[CONV17]] +// IR-GPU-NEXT: [[MUL19:%.*]] = mul nsw i64 [[DIV18]], 1 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL19]] +// IR-GPU-NEXT: [[CONV20:%.*]] = trunc i64 [[ADD]] to i32 +// IR-GPU-NEXT: store i32 [[CONV20]], ptr [[I11_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB21:%.*]] = sub nsw i32 [[TMP22]], 0 +// IR-GPU-NEXT: [[DIV22:%.*]] = sdiv i32 [[SUB21]], 1 +// IR-GPU-NEXT: [[MUL23:%.*]] = mul nsw i32 1, [[DIV22]] +// IR-GPU-NEXT: [[CONV24:%.*]] = sext i32 [[MUL23]] to i64 +// IR-GPU-NEXT: [[DIV25:%.*]] = sdiv i64 [[TMP21]], [[CONV24]] +// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-GPU-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// IR-GPU-NEXT: [[MUL28:%.*]] = mul nsw i32 1, [[DIV27]] +// IR-GPU-NEXT: [[CONV29:%.*]] = sext i32 [[MUL28]] to i64 +// IR-GPU-NEXT: [[MUL30:%.*]] = mul nsw i64 [[DIV25]], [[CONV29]] +// IR-GPU-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP20]], [[MUL30]] +// IR-GPU-NEXT: [[MUL32:%.*]] = mul nsw i64 [[SUB31]], 1 +// IR-GPU-NEXT: [[ADD33:%.*]] = add nsw i64 0, [[MUL32]] +// IR-GPU-NEXT: [[CONV34:%.*]] = trunc i64 [[ADD33]] to i32 +// IR-GPU-NEXT: store i32 [[CONV34]], ptr [[J12_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[I11_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-GPU-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NEXT: [[TMP26:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL35:%.*]] = mul nsw i32 [[TMP25]], [[TMP26]] +// IR-GPU-NEXT: [[TMP27:%.*]] = load i32, ptr [[J12_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD36:%.*]] = add nsw i32 [[MUL35]], [[TMP27]] +// IR-GPU-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP28]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM37]] +// IR-GPU-NEXT: store i32 [[ADD36]], ptr [[ARRAYIDX38]], align 4 +// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-GPU: omp.body.continue: +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP29]], [[TMP30]] +// IR-GPU-NEXT: store i64 [[ADD39]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 +// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP32]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 +// IR-GPU-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR4:[0-9]+]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[NT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NT_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[NT_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NT_CASTED]] to ptr +// IR-GPU-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// IR-GPU-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[NT]], ptr [[NT_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_kernel_environment to ptr), ptr [[DYN_PTR]]) +// IR-GPU-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// IR-GPU-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// IR-GPU: user_code.entry: +// IR-GPU-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr)) +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP8]], ptr [[NT_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[NT_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2]] +// IR-GPU-NEXT: call void @__kmpc_target_deinit() +// IR-GPU-NEXT: ret void +// IR-GPU: worker.exit: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I5:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [8 x ptr], align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[NT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NT_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[I5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I5]] to ptr +// IR-GPU-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NEXT: [[NT_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NT_CASTED]] to ptr +// IR-GPU-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[NT]], ptr [[NT_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]]) +// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-GPU-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-GPU: cond.true: +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END:%.*]] +// IR-GPU: cond.false: +// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END]] +// IR-GPU: cond.end: +// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1 +// IR-GPU-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]] +// IR-GPU-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP21]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP23]], ptr [[NT_CASTED_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP24:%.*]] = load i64, ptr [[NT_CASTED_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// IR-GPU-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP18]] to ptr +// IR-GPU-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8 +// IR-GPU-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// IR-GPU-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP20]] to ptr +// IR-GPU-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8 +// IR-GPU-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// IR-GPU-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP22]] to ptr +// IR-GPU-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8 +// IR-GPU-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// IR-GPU-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP24]] to ptr +// IR-GPU-NEXT: store ptr [[TMP32]], ptr [[TMP31]], align 8 +// IR-GPU-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 +// IR-GPU-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP0]] to ptr +// IR-GPU-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 8 +// IR-GPU-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 +// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP35]], align 8 +// IR-GPU-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6 +// IR-GPU-NEXT: [[TMP37:%.*]] = inttoptr i64 [[TMP2]] to ptr +// IR-GPU-NEXT: store ptr [[TMP37]], ptr [[TMP36]], align 8 +// IR-GPU-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 7 +// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP38]], align 8 +// IR-GPU-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4 +// IR-GPU-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP40]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 8) +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP41]], [[TMP42]] +// IR-GPU-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP43]], [[TMP44]] +// IR-GPU-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP45]], [[TMP46]] +// IR-GPU-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP47]], [[TMP48]] +// IR-GPU-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]] +// IR-GPU: cond.true12: +// IR-GPU-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END14:%.*]] +// IR-GPU: cond.false13: +// IR-GPU-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[COND_END14]] +// IR-GPU: cond.end14: +// IR-GPU-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP49]], [[COND_TRUE12]] ], [ [[TMP50]], [[COND_FALSE13]] ] +// IR-GPU-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4 +// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP53]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined +// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-NEXT: entry: +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[I6:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// IR-GPU-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// IR-GPU-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NEXT: [[NT_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[NT_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr +// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NEXT: [[I6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I6]] to ptr +// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[NT]], ptr [[NT_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU: omp.precond.then: +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// IR-GPU-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1) +// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4 +// IR-GPU-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU: omp.inner.for.cond: +// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64 +// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[CMP8:%.*]] = icmp ule i64 [[CONV7]], [[TMP14]] +// IR-GPU-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU: omp.inner.for.body: +// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 +// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-GPU-NEXT: store i32 [[ADD]], ptr [[I6_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0 +// IR-GPU-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] +// IR-GPU: if.then: +// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() #[[ATTR6:[0-9]+]] +// IR-GPU-NEXT: store i32 [[CALL]], ptr [[NT_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[IF_END]] +// IR-GPU: if.end: +// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[FOR_COND:%.*]] +// IR-GPU: for.cond: +// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP17]], [[TMP18]] +// IR-GPU-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR-GPU: for.body: +// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP20]], [[TMP21]] +// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD11:%.*]] = add nsw i32 [[MUL10]], [[TMP22]] +// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP23]] to i64 +// IR-GPU-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM12]] +// IR-GPU-NEXT: store i32 [[ADD11]], ptr [[ARRAYIDX13]], align 4 +// IR-GPU-NEXT: br label [[FOR_INC:%.*]] +// IR-GPU: for.inc: +// IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: [[INC:%.*]] = add nsw i32 [[TMP24]], 1 +// IR-GPU-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] +// IR-GPU: for.end: +// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-GPU: omp.body.continue: +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU: omp.inner.for.inc: +// IR-GPU-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4 +// IR-GPU-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// IR-GPU-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV_ASCAST]], align 4 +// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU: omp.inner.for.end: +// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU: omp.loop.exit: +// IR-GPU-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 +// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP28]]) +// IR-GPU-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU: omp.precond.end: +// IR-GPU-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@main +// IR-SAME: () #[[ATTR0:[0-9]+]] { +// IR-NEXT: entry: +// IR-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// IR-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// IR-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: [[N_CASTED2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT:%.*]] = alloca i32, align 4 +// IR-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-NEXT: [[TMP0:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// IR-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// IR-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// IR-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 +// IR-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// IR-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP4]], align 16 +// IR-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41(i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3:[0-9]+]] +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[N_CASTED2]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load i64, ptr [[N_CASTED2]], align 8 +// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46(i64 [[TMP8]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3]] +// IR-NEXT: store i32 0, ptr [[NT]], align 4 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr @N, align 4 +// IR-NEXT: store i32 [[TMP9]], ptr [[N_CASTED3]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED3]], align 8 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[NT]], align 4 +// IR-NEXT: store i32 [[TMP11]], ptr [[NT_CASTED]], align 4 +// IR-NEXT: [[TMP12:%.*]] = load i64, ptr [[NT_CASTED]], align 8 +// IR-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3]] +// IR-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// IR-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]]) +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 +// IR-NEXT: ret i32 [[TMP14]] +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 +// IR-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// IR-NEXT: entry: +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J5:%.*]] = alloca i32, align 4 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: omp.precond.then: +// IR-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP21]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// IR-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J6:%.*]] = alloca i32, align 4 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: omp.precond.then: +// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// IR-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// IR-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// IR-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// IR-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD]], ptr [[J6]], align 4 +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[J6]], align 4 +// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[J6]], align 4 +// IR-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP22]] to i64 +// IR-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM9]] +// IR-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX10]], align 4 +// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR: omp.body.continue: +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], 1 +// IR-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP25]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 +// IR-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: land.lhs.true: +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR: omp.precond.then: +// IR-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP12]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] +// IR-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// IR-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP18]], [[TMP19]] +// IR-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP22]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined.omp_outlined, i64 [[TMP20]], i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8 +// IR-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP24]], [[TMP25]] +// IR-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: land.lhs.true: +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR: omp.precond.then: +// IR-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// IR-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8 +// IR-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB]], align 8 +// IR-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB]], align 8 +// IR-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2]], i32 [[TMP14]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]] +// IR-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// IR-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// IR-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// IR-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP20]], [[TMP21]] +// IR-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// IR-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// IR-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// IR-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP22]], [[CONV18]] +// IR-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// IR-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// IR-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// IR-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4 +// IR-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP26]], 0 +// IR-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// IR-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// IR-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// IR-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP25]], [[CONV25]] +// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP27]], 0 +// IR-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// IR-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// IR-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// IR-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// IR-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP24]], [[MUL31]] +// IR-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// IR-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// IR-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// IR-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4 +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11]], align 4 +// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP28]] to i64 +// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-NEXT: [[TMP30:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP30]] +// IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[J12]], align 4 +// IR-NEXT: [[ADD37:%.*]] = add nsw i32 [[MUL36]], [[TMP31]] +// IR-NEXT: [[TMP32:%.*]] = load i32, ptr [[I11]], align 4 +// IR-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP32]] to i64 +// IR-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM38]] +// IR-NEXT: store i32 [[ADD37]], ptr [[ARRAYIDX39]], align 4 +// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR: omp.body.continue: +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP33]], 1 +// IR-NEXT: store i64 [[ADD40]], ptr [[DOTOMP_IV]], align 8 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP35]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 +// IR-SAME: (i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[NT]], ptr [[NT_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 32, i32 0) +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[NT_CASTED]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load i64, ptr [[NT_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined, i64 [[TMP6]], i64 [[TMP8]], i64 [[TMP1]], ptr [[TMP2]], i64 [[TMP3]], ptr [[TMP4]]) +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I5:%.*]] = alloca i32, align 4 +// IR-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[NT]], ptr [[NT_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: omp.precond.then: +// IR-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP21]], ptr [[N_CASTED]], align 4 +// IR-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP23]], ptr [[NT_CASTED]], align 4 +// IR-NEXT: [[TMP24:%.*]] = load i64, ptr [[NT_CASTED]], align 8 +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// IR-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP28]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined +// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NEXT: entry: +// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NEXT: [[I6:%.*]] = alloca i32, align 4 +// IR-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NEXT: store i64 [[NT]], ptr [[NT_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR: omp.precond.then: +// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// IR-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// IR-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// IR-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR: cond.true: +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-NEXT: br label [[COND_END:%.*]] +// IR: cond.false: +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: br label [[COND_END]] +// IR: cond.end: +// IR-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR: omp.inner.for.cond: +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// IR-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR: omp.inner.for.body: +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD]], ptr [[I6]], align 4 +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP20]], 0 +// IR-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] +// IR: if.then: +// IR-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() +// IR-NEXT: store i32 [[CALL]], ptr [[NT_ADDR]], align 4 +// IR-NEXT: br label [[IF_END]] +// IR: if.end: +// IR-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NEXT: br label [[FOR_COND:%.*]] +// IR: for.cond: +// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] +// IR-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR: for.body: +// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP24]], [[TMP25]] +// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-NEXT: [[ADD11:%.*]] = add nsw i32 [[MUL10]], [[TMP26]] +// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP27]] to i64 +// IR-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM12]] +// IR-NEXT: store i32 [[ADD11]], ptr [[ARRAYIDX13]], align 4 +// IR-NEXT: br label [[FOR_INC:%.*]] +// IR: for.inc: +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[J]], align 4 +// IR-NEXT: [[INC:%.*]] = add nsw i32 [[TMP28]], 1 +// IR-NEXT: store i32 [[INC]], ptr [[J]], align 4 +// IR-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// IR: for.end: +// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR: omp.body.continue: +// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR: omp.inner.for.inc: +// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 +// IR-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR: omp.inner.for.end: +// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR: omp.loop.exit: +// IR-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP31]]) +// IR-NEXT: br label [[OMP_PRECOND_END]] +// IR: omp.precond.end: +// IR-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@main +// IR-PCH-SAME: () #[[ATTR0:[0-9]+]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[N_CASTED2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[N_CASTED3:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// IR-PCH-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// IR-PCH-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// IR-PCH-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 +// IR-PCH-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// IR-PCH-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP4]], align 16 +// IR-PCH-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41(i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3:[0-9]+]] +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[N_CASTED2]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load i64, ptr [[N_CASTED2]], align 8 +// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46(i64 [[TMP8]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3]] +// IR-PCH-NEXT: store i32 0, ptr [[NT]], align 4 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NEXT: store i32 [[TMP9]], ptr [[N_CASTED3]], align 4 +// IR-PCH-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED3]], align 8 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[NT]], align 4 +// IR-PCH-NEXT: store i32 [[TMP11]], ptr [[NT_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP12:%.*]] = load i64, ptr [[NT_CASTED]], align 8 +// IR-PCH-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55(i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3]] +// IR-PCH-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-PCH-NEXT: [[TMP13:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// IR-PCH-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP13]]) +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4 +// IR-PCH-NEXT: ret i32 [[TMP14]] +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 +// IR-PCH-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J5:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-PCH-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-PCH-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-PCH-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// IR-PCH-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP21]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], [[TMP24]] +// IR-PCH-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41.omp_outlined.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J6:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-PCH-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// IR-PCH-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// IR-PCH-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// IR-PCH-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-PCH-NEXT: store i32 [[ADD]], ptr [[J6]], align 4 +// IR-PCH-NEXT: [[TMP20:%.*]] = load i32, ptr [[J6]], align 4 +// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-PCH-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i32, ptr [[J6]], align 4 +// IR-PCH-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP22]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM9]] +// IR-PCH-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX10]], align 4 +// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-PCH: omp.body.continue: +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP23]], 1 +// IR-PCH-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP25]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46 +// IR-PCH-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-PCH-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-PCH-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-PCH-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-PCH-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: land.lhs.true: +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-PCH-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-PCH-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP12]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-PCH-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] +// IR-PCH-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-PCH-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP18]], [[TMP19]] +// IR-PCH-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-PCH-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP22]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined.omp_outlined, i64 [[TMP20]], i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP24]], [[TMP25]] +// IR-PCH-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46.omp_outlined.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-PCH-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-PCH-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-PCH-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-PCH-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: land.lhs.true: +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-PCH-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// IR-PCH-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB]], align 8 +// IR-PCH-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2]], i32 [[TMP14]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-PCH-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]] +// IR-PCH-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// IR-PCH-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP20]], [[TMP21]] +// IR-PCH-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-PCH-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// IR-PCH-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// IR-PCH-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// IR-PCH-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP22]], [[CONV18]] +// IR-PCH-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// IR-PCH-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// IR-PCH-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4 +// IR-PCH-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP26]], 0 +// IR-PCH-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// IR-PCH-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// IR-PCH-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// IR-PCH-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP25]], [[CONV25]] +// IR-PCH-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP27]], 0 +// IR-PCH-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// IR-PCH-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// IR-PCH-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// IR-PCH-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// IR-PCH-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP24]], [[MUL31]] +// IR-PCH-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// IR-PCH-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// IR-PCH-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// IR-PCH-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4 +// IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11]], align 4 +// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP28]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-PCH-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-PCH-NEXT: [[TMP30:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP30]] +// IR-PCH-NEXT: [[TMP31:%.*]] = load i32, ptr [[J12]], align 4 +// IR-PCH-NEXT: [[ADD37:%.*]] = add nsw i32 [[MUL36]], [[TMP31]] +// IR-PCH-NEXT: [[TMP32:%.*]] = load i32, ptr [[I11]], align 4 +// IR-PCH-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP32]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM38]] +// IR-PCH-NEXT: store i32 [[ADD37]], ptr [[ARRAYIDX39]], align 4 +// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-PCH: omp.body.continue: +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP33]], 1 +// IR-PCH-NEXT: store i64 [[ADD40]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP35]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55 +// IR-PCH-SAME: (i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[NT]], ptr [[NT_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 32, i32 0) +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[NT_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load i64, ptr [[NT_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined, i64 [[TMP6]], i64 [[TMP8]], i64 [[TMP1]], ptr [[TMP2]], i64 [[TMP3]], ptr [[TMP4]]) +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I5:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[NT]], ptr [[NT_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-PCH-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] +// IR-PCH-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] +// IR-PCH-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// IR-PCH-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 +// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// IR-PCH-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +// IR-PCH-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP21]], ptr [[N_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP23]], ptr [[NT_CASTED]], align 4 +// IR-PCH-NEXT: [[TMP24:%.*]] = load i64, ptr [[NT_CASTED]], align 8 +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 8, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined, i64 [[TMP18]], i64 [[TMP20]], i64 [[TMP22]], i64 [[TMP24]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP25]], [[TMP26]] +// IR-PCH-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP28]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// +// +// IR-PCH-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55.omp_outlined.omp_outlined +// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NEXT: entry: +// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[I6:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[NT]], ptr [[NT_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1 +// IR-PCH-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]] +// IR-PCH-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH: omp.precond.then: +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32 +// IR-PCH-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32 +// IR-PCH-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 +// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: [[CMP7:%.*]] = icmp sgt i32 [[TMP12]], [[TMP13]] +// IR-PCH-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH: cond.true: +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4 +// IR-PCH-NEXT: br label [[COND_END:%.*]] +// IR-PCH: cond.false: +// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: br label [[COND_END]] +// IR-PCH: cond.end: +// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] +// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 +// IR-PCH-NEXT: store i32 [[TMP16]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH: omp.inner.for.cond: +// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// IR-PCH-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]] +// IR-PCH-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH: omp.inner.for.body: +// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-PCH-NEXT: store i32 [[ADD]], ptr [[I6]], align 4 +// IR-PCH-NEXT: [[TMP20:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-PCH-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP20]], 0 +// IR-PCH-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]] +// IR-PCH: if.then: +// IR-PCH-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() +// IR-PCH-NEXT: store i32 [[CALL]], ptr [[NT_ADDR]], align 4 +// IR-PCH-NEXT: br label [[IF_END]] +// IR-PCH: if.end: +// IR-PCH-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NEXT: br label [[FOR_COND:%.*]] +// IR-PCH: for.cond: +// IR-PCH-NEXT: [[TMP21:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]] +// IR-PCH-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] +// IR-PCH: for.body: +// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-PCH-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-PCH-NEXT: [[TMP25:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP24]], [[TMP25]] +// IR-PCH-NEXT: [[TMP26:%.*]] = load i32, ptr [[NT_ADDR]], align 4 +// IR-PCH-NEXT: [[ADD11:%.*]] = add nsw i32 [[MUL10]], [[TMP26]] +// IR-PCH-NEXT: [[TMP27:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP27]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM12]] +// IR-PCH-NEXT: store i32 [[ADD11]], ptr [[ARRAYIDX13]], align 4 +// IR-PCH-NEXT: br label [[FOR_INC:%.*]] +// IR-PCH: for.inc: +// IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[J]], align 4 +// IR-PCH-NEXT: [[INC:%.*]] = add nsw i32 [[TMP28]], 1 +// IR-PCH-NEXT: store i32 [[INC]], ptr [[J]], align 4 +// IR-PCH-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] +// IR-PCH: for.end: +// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-PCH: omp.body.continue: +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH: omp.inner.for.inc: +// IR-PCH-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 +// IR-PCH-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH: omp.inner.for.end: +// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH: omp.loop.exit: +// IR-PCH-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP31]]) +// IR-PCH-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH: omp.precond.end: +// IR-PCH-NEXT: ret void +// +// +// IR-GPU-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 +// IR-GPU-NESTED-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR0:[0-9]+]] { +// IR-GPU-NESTED-NEXT: entry: +// IR-GPU-NESTED-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DYN_PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DYN_PTR_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NESTED-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTZERO_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTZERO_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTTHREADID_TEMP__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_target_init(ptr addrspacecast (ptr addrspace(1) @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_kernel_environment to ptr), ptr [[DYN_PTR]]) +// IR-GPU-NESTED-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP4]], -1 +// IR-GPU-NESTED-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]] +// IR-GPU-NESTED: user_code.entry: +// IR-GPU-NESTED-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1:[0-9]+]] to ptr)) +// IR-GPU-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP6]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTTHREADID_TEMP__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_omp_outlined(ptr [[DOTTHREADID_TEMP__ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]] +// IR-GPU-NESTED-NEXT: call void @__kmpc_target_deinit() +// IR-GPU-NESTED-NEXT: ret void +// IR-GPU-NESTED: worker.exit: +// IR-GPU-NESTED-NEXT: ret void +// +// +// IR-GPU-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_omp_outlined +// IR-GPU-NESTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1:[0-9]+]] { +// IR-GPU-NESTED-NEXT: entry: +// IR-GPU-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[_TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[I11:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[J12:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [7 x ptr], align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NESTED-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NESTED-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NESTED-NEXT: [[TMP3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP3]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_5]] to ptr +// IR-GPU-NESTED-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NESTED-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_COMB_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_LB]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_COMB_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_COMB_UB]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NESTED-NEXT: [[I11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I11]] to ptr +// IR-GPU-NESTED-NEXT: [[J12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J12]] to ptr +// IR-GPU-NESTED-NEXT: [[N_CASTED_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_CASTED]] to ptr +// IR-GPU-NESTED-NEXT: [[CAPTURED_VARS_ADDRS_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[CAPTURED_VARS_ADDRS]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-GPU-NESTED-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NESTED-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-GPU-NESTED-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-GPU-NESTED-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-GPU-NESTED-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-GPU-NESTED-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-GPU-NESTED-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-GPU-NESTED-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU-NESTED: land.lhs.true: +// IR-GPU-NESTED-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-GPU-NESTED: omp.precond.then: +// IR-GPU-NESTED-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block() +// IR-GPU-NESTED-NEXT: [[CONV13:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64 +// IR-GPU-NESTED-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// IR-GPU-NESTED-NEXT: call void @__kmpc_distribute_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP12]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 [[CONV13]]) +// IR-GPU-NESTED-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP14]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-GPU-NESTED: cond.true: +// IR-GPU-NESTED-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[COND_END:%.*]] +// IR-GPU-NESTED: cond.false: +// IR-GPU-NESTED-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[COND_END]] +// IR-GPU-NESTED: cond.end: +// IR-GPU-NESTED-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// IR-GPU-NESTED-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU-NESTED: omp.inner.for.cond: +// IR-GPU-NESTED-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP19]], 1 +// IR-GPU-NESTED-NEXT: [[CMP15:%.*]] = icmp slt i64 [[TMP18]], [[ADD]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU-NESTED: omp.inner.for.body: +// IR-GPU-NESTED-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP22]], ptr [[N_CASTED_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP24:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0 +// IR-GPU-NESTED-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP20]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP26:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1 +// IR-GPU-NESTED-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP21]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[TMP27]], ptr [[TMP26]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP28:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2 +// IR-GPU-NESTED-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP23]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[TMP29]], ptr [[TMP28]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP30:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3 +// IR-GPU-NESTED-NEXT: [[TMP31:%.*]] = inttoptr i64 [[TMP0]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[TMP31]], ptr [[TMP30]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP32:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4 +// IR-GPU-NESTED-NEXT: store ptr [[TMP1]], ptr [[TMP32]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP33:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5 +// IR-GPU-NESTED-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP2]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP35:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6 +// IR-GPU-NESTED-NEXT: store ptr [[TMP3]], ptr [[TMP35]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP36:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP37:%.*]] = load i32, ptr [[TMP36]], align 4 +// IR-GPU-NESTED-NEXT: call void @__kmpc_parallel_51(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP37]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7) +// IR-GPU-NESTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU-NESTED: omp.inner.for.inc: +// IR-GPU-NESTED-NEXT: [[TMP38:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[ADD16:%.*]] = add nsw i64 [[TMP38]], [[TMP39]] +// IR-GPU-NESTED-NEXT: store i64 [[ADD16]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP40:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP40]], [[TMP41]] +// IR-GPU-NESTED-NEXT: store i64 [[ADD17]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP42:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP43:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP42]], [[TMP43]] +// IR-GPU-NESTED-NEXT: store i64 [[ADD18]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP44:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP45:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[CMP19:%.*]] = icmp sgt i64 [[TMP44]], [[TMP45]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP19]], label [[COND_TRUE20:%.*]], label [[COND_FALSE21:%.*]] +// IR-GPU-NESTED: cond.true20: +// IR-GPU-NESTED-NEXT: [[TMP46:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[COND_END22:%.*]] +// IR-GPU-NESTED: cond.false21: +// IR-GPU-NESTED-NEXT: [[TMP47:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[COND_END22]] +// IR-GPU-NESTED: cond.end22: +// IR-GPU-NESTED-NEXT: [[COND23:%.*]] = phi i64 [ [[TMP46]], [[COND_TRUE20]] ], [ [[TMP47]], [[COND_FALSE21]] ] +// IR-GPU-NESTED-NEXT: store i64 [[COND23]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP48:%.*]] = load i64, ptr [[DOTOMP_COMB_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP48]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU-NESTED: omp.inner.for.end: +// IR-GPU-NESTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU-NESTED: omp.loop.exit: +// IR-GPU-NESTED-NEXT: [[TMP49:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4 +// IR-GPU-NESTED-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP50]]) +// IR-GPU-NESTED-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU-NESTED: omp.precond.end: +// IR-GPU-NESTED-NEXT: ret void +// +// +// IR-GPU-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64_omp_outlined_omp_outlined +// IR-GPU-NESTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR1]] { +// IR-GPU-NESTED-NEXT: entry: +// IR-GPU-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[TMP:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[_TMP3:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[I11:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[J12:%.*]] = alloca i32, align 4, addrspace(5) +// IR-GPU-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTPREVIOUS_UB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_UB__ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[N_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[VLA_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[A_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[VLA_ADDR2_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA_ADDR2]] to ptr +// IR-GPU-NESTED-NEXT: [[B_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[B_ADDR]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_IV_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IV]] to ptr +// IR-GPU-NESTED-NEXT: [[TMP_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[TMP]] to ptr +// IR-GPU-NESTED-NEXT: [[TMP3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[_TMP3]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_4]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTCAPTURE_EXPR_5_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_5]] to ptr +// IR-GPU-NESTED-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr +// IR-GPU-NESTED-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr +// IR-GPU-NESTED-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr +// IR-GPU-NESTED-NEXT: [[I11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I11]] to ptr +// IR-GPU-NESTED-NEXT: [[J12_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J12]] to ptr +// IR-GPU-NESTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-GPU-NESTED-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-GPU-NESTED-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-GPU-NESTED-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-GPU-NESTED-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-GPU-NESTED-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-GPU-NESTED-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-GPU-NESTED-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-GPU-NESTED-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[I_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[J_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-GPU-NESTED: land.lhs.true: +// IR-GPU-NESTED-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-GPU-NESTED: omp.precond.then: +// IR-GPU-NESTED-NEXT: store i64 0, ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// IR-GPU-NESTED-NEXT: call void @__kmpc_for_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP14]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 1) +// IR-GPU-NESTED-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_LB_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-GPU-NESTED: omp.inner.for.cond: +// IR-GPU-NESTED-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[CMP13:%.*]] = icmp ule i64 [[TMP16]], [[TMP17]] +// IR-GPU-NESTED-NEXT: br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-GPU-NESTED: omp.inner.for.body: +// IR-GPU-NESTED-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP19]], 0 +// IR-GPU-NESTED-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 +// IR-GPU-NESTED-NEXT: [[MUL16:%.*]] = mul nsw i32 1, [[DIV15]] +// IR-GPU-NESTED-NEXT: [[CONV17:%.*]] = sext i32 [[MUL16]] to i64 +// IR-GPU-NESTED-NEXT: [[DIV18:%.*]] = sdiv i64 [[TMP18]], [[CONV17]] +// IR-GPU-NESTED-NEXT: [[MUL19:%.*]] = mul nsw i64 [[DIV18]], 1 +// IR-GPU-NESTED-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL19]] +// IR-GPU-NESTED-NEXT: [[CONV20:%.*]] = trunc i64 [[ADD]] to i32 +// IR-GPU-NESTED-NEXT: store i32 [[CONV20]], ptr [[I11_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB21:%.*]] = sub nsw i32 [[TMP22]], 0 +// IR-GPU-NESTED-NEXT: [[DIV22:%.*]] = sdiv i32 [[SUB21]], 1 +// IR-GPU-NESTED-NEXT: [[MUL23:%.*]] = mul nsw i32 1, [[DIV22]] +// IR-GPU-NESTED-NEXT: [[CONV24:%.*]] = sext i32 [[MUL23]] to i64 +// IR-GPU-NESTED-NEXT: [[DIV25:%.*]] = sdiv i64 [[TMP21]], [[CONV24]] +// IR-GPU-NESTED-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[SUB26:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-GPU-NESTED-NEXT: [[DIV27:%.*]] = sdiv i32 [[SUB26]], 1 +// IR-GPU-NESTED-NEXT: [[MUL28:%.*]] = mul nsw i32 1, [[DIV27]] +// IR-GPU-NESTED-NEXT: [[CONV29:%.*]] = sext i32 [[MUL28]] to i64 +// IR-GPU-NESTED-NEXT: [[MUL30:%.*]] = mul nsw i64 [[DIV25]], [[CONV29]] +// IR-GPU-NESTED-NEXT: [[SUB31:%.*]] = sub nsw i64 [[TMP20]], [[MUL30]] +// IR-GPU-NESTED-NEXT: [[MUL32:%.*]] = mul nsw i64 [[SUB31]], 1 +// IR-GPU-NESTED-NEXT: [[ADD33:%.*]] = add nsw i64 0, [[MUL32]] +// IR-GPU-NESTED-NEXT: [[CONV34:%.*]] = trunc i64 [[ADD33]] to i32 +// IR-GPU-NESTED-NEXT: store i32 [[CONV34]], ptr [[J12_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP24:%.*]] = load i32, ptr [[I11_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 +// IR-GPU-NESTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-GPU-NESTED-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-GPU-NESTED-NEXT: [[TMP26:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[MUL35:%.*]] = mul nsw i32 [[TMP25]], [[TMP26]] +// IR-GPU-NESTED-NEXT: [[TMP27:%.*]] = load i32, ptr [[J12_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP27]]) #[[ATTR5:[0-9]+]] +// IR-GPU-NESTED-NEXT: [[ADD36:%.*]] = add nsw i32 [[MUL35]], [[CALL]] +// IR-GPU-NESTED-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11_ASCAST]], align 4 +// IR-GPU-NESTED-NEXT: [[IDXPROM37:%.*]] = sext i32 [[TMP28]] to i64 +// IR-GPU-NESTED-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM37]] +// IR-GPU-NESTED-NEXT: store i32 [[ADD36]], ptr [[ARRAYIDX38]], align 4 +// IR-GPU-NESTED-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-GPU-NESTED: omp.body.continue: +// IR-GPU-NESTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-GPU-NESTED: omp.inner.for.inc: +// IR-GPU-NESTED-NEXT: [[TMP29:%.*]] = load i64, ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_STRIDE_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP29]], [[TMP30]] +// IR-GPU-NESTED-NEXT: store i64 [[ADD39]], ptr [[DOTOMP_IV_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-GPU-NESTED: omp.inner.for.end: +// IR-GPU-NESTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-GPU-NESTED: omp.loop.exit: +// IR-GPU-NESTED-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8 +// IR-GPU-NESTED-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 +// IR-GPU-NESTED-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP32]]) +// IR-GPU-NESTED-NEXT: br label [[OMP_PRECOND_END]] +// IR-GPU-NESTED: omp.precond.end: +// IR-GPU-NESTED-NEXT: ret void +// +// +// IR-NESTED-LABEL: define {{[^@]+}}@main +// IR-NESTED-SAME: () #[[ATTR0:[0-9]+]] { +// IR-NESTED-NEXT: entry: +// IR-NESTED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-NESTED-NEXT: [[TMP0:%.*]] = load i32, ptr @N, align 4 +// IR-NESTED-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// IR-NESTED-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// IR-NESTED-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// IR-NESTED-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 +// IR-NESTED-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load i32, ptr @N, align 4 +// IR-NESTED-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// IR-NESTED-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP4]], align 16 +// IR-NESTED-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// IR-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr @N, align 4 +// IR-NESTED-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-NESTED-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NESTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3:[0-9]+]] +// IR-NESTED-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-NESTED-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// IR-NESTED-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP7]]) +// IR-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4 +// IR-NESTED-NEXT: ret i32 [[TMP8]] +// +// +// IR-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 +// IR-NESTED-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// IR-NESTED-NEXT: entry: +// IR-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-NESTED-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NESTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NESTED-NEXT: ret void +// +// +// IR-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined +// IR-NESTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NESTED-NEXT: entry: +// IR-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NESTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NESTED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-NESTED-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NESTED-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-NESTED-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-NESTED-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-NESTED-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-NESTED-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-NESTED-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-NESTED-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NESTED-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NESTED-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-NESTED-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-NESTED: land.lhs.true: +// IR-NESTED-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-NESTED-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-NESTED: omp.precond.then: +// IR-NESTED-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-NESTED-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NESTED-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-NESTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NESTED-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// IR-NESTED-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP12]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-NESTED-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NESTED-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] +// IR-NESTED-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-NESTED: cond.true: +// IR-NESTED-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: br label [[COND_END:%.*]] +// IR-NESTED: cond.false: +// IR-NESTED-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NESTED-NEXT: br label [[COND_END]] +// IR-NESTED: cond.end: +// IR-NESTED-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// IR-NESTED-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NESTED-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-NESTED-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-NESTED: omp.inner.for.cond: +// IR-NESTED-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NESTED-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP18]], [[TMP19]] +// IR-NESTED-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-NESTED: omp.inner.for.body: +// IR-NESTED-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-NESTED-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-NESTED-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: store i32 [[TMP22]], ptr [[N_CASTED]], align 4 +// IR-NESTED-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-NESTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined.omp_outlined, i64 [[TMP20]], i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-NESTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-NESTED: omp.inner.for.inc: +// IR-NESTED-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8 +// IR-NESTED-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP24]], [[TMP25]] +// IR-NESTED-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-NESTED: omp.inner.for.end: +// IR-NESTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-NESTED: omp.loop.exit: +// IR-NESTED-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 +// IR-NESTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]]) +// IR-NESTED-NEXT: br label [[OMP_PRECOND_END]] +// IR-NESTED: omp.precond.end: +// IR-NESTED-NEXT: ret void +// +// +// IR-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined.omp_outlined +// IR-NESTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-NESTED-NEXT: entry: +// IR-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-NESTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-NESTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-NESTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NESTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NESTED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-NESTED-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-NESTED-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-NESTED-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-NESTED-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-NESTED-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-NESTED-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-NESTED-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-NESTED-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: store i32 0, ptr [[I]], align 4 +// IR-NESTED-NEXT: store i32 0, ptr [[J]], align 4 +// IR-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-NESTED-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-NESTED-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-NESTED: land.lhs.true: +// IR-NESTED-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-NESTED-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-NESTED: omp.precond.then: +// IR-NESTED-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// IR-NESTED-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8 +// IR-NESTED-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-NESTED-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB]], align 8 +// IR-NESTED-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB]], align 8 +// IR-NESTED-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-NESTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NESTED-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// IR-NESTED-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2:[0-9]+]], i32 [[TMP14]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-NESTED-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-NESTED-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]] +// IR-NESTED-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-NESTED: cond.true: +// IR-NESTED-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-NESTED-NEXT: br label [[COND_END:%.*]] +// IR-NESTED: cond.false: +// IR-NESTED-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-NESTED-NEXT: br label [[COND_END]] +// IR-NESTED: cond.end: +// IR-NESTED-NEXT: [[COND:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// IR-NESTED-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// IR-NESTED-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// IR-NESTED-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-NESTED: omp.inner.for.cond: +// IR-NESTED-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-NESTED-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP20]], [[TMP21]] +// IR-NESTED-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-NESTED: omp.inner.for.body: +// IR-NESTED-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-NESTED-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// IR-NESTED-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// IR-NESTED-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// IR-NESTED-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP22]], [[CONV18]] +// IR-NESTED-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// IR-NESTED-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// IR-NESTED-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// IR-NESTED-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4 +// IR-NESTED-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP26]], 0 +// IR-NESTED-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// IR-NESTED-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// IR-NESTED-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// IR-NESTED-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP25]], [[CONV25]] +// IR-NESTED-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-NESTED-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP27]], 0 +// IR-NESTED-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// IR-NESTED-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// IR-NESTED-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// IR-NESTED-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// IR-NESTED-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP24]], [[MUL31]] +// IR-NESTED-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// IR-NESTED-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// IR-NESTED-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// IR-NESTED-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4 +// IR-NESTED-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11]], align 4 +// IR-NESTED-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP28]] to i64 +// IR-NESTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-NESTED-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-NESTED-NEXT: [[TMP30:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-NESTED-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP30]] +// IR-NESTED-NEXT: [[TMP31:%.*]] = load i32, ptr [[J12]], align 4 +// IR-NESTED-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP31]]) +// IR-NESTED-NEXT: [[ADD37:%.*]] = add nsw i32 [[MUL36]], [[CALL]] +// IR-NESTED-NEXT: [[TMP32:%.*]] = load i32, ptr [[I11]], align 4 +// IR-NESTED-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP32]] to i64 +// IR-NESTED-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM38]] +// IR-NESTED-NEXT: store i32 [[ADD37]], ptr [[ARRAYIDX39]], align 4 +// IR-NESTED-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-NESTED: omp.body.continue: +// IR-NESTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-NESTED: omp.inner.for.inc: +// IR-NESTED-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP33]], 1 +// IR-NESTED-NEXT: store i64 [[ADD40]], ptr [[DOTOMP_IV]], align 8 +// IR-NESTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-NESTED: omp.inner.for.end: +// IR-NESTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-NESTED: omp.loop.exit: +// IR-NESTED-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NESTED-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4 +// IR-NESTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP35]]) +// IR-NESTED-NEXT: br label [[OMP_PRECOND_END]] +// IR-NESTED: omp.precond.end: +// IR-NESTED-NEXT: ret void +// +// +// IR-PCH-NESTED-LABEL: define {{[^@]+}}@main +// IR-PCH-NESTED-SAME: () #[[ATTR0:[0-9]+]] { +// IR-PCH-NESTED-NEXT: entry: +// IR-PCH-NESTED-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0() +// IR-PCH-NESTED-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8 +// IR-PCH-NESTED-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP1]], align 16 +// IR-PCH-NESTED-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 +// IR-PCH-NESTED-NEXT: [[VLA1:%.*]] = alloca i32, i64 [[TMP4]], align 16 +// IR-PCH-NESTED-NEXT: store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr @N, align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP5]], ptr [[N_CASTED]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP6:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NESTED-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP6]], i64 [[TMP1]], ptr [[VLA]], i64 [[TMP4]], ptr [[VLA1]]) #[[ATTR3:[0-9]+]] +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[RETVAL]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP7:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8 +// IR-PCH-NESTED-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP7]]) +// IR-PCH-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4 +// IR-PCH-NESTED-NEXT: ret i32 [[TMP8]] +// +// +// IR-PCH-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64 +// IR-PCH-NESTED-SAME: (i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] { +// IR-PCH-NESTED-NEXT: entry: +// IR-PCH-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NESTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NESTED-NEXT: ret void +// +// +// IR-PCH-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined +// IR-PCH-NESTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NESTED-NEXT: entry: +// IR-PCH-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-PCH-NESTED-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NESTED-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-PCH-NESTED-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-PCH-NESTED-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-PCH-NESTED-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-PCH-NESTED-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-PCH-NESTED-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-PCH-NESTED-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NESTED-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH-NESTED: land.lhs.true: +// IR-PCH-NESTED-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-PCH-NESTED: omp.precond.then: +// IR-PCH-NESTED-NEXT: store i64 0, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NESTED-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 +// IR-PCH-NESTED-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP12]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-PCH-NESTED-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH-NESTED: cond.true: +// IR-PCH-NESTED-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: br label [[COND_END:%.*]] +// IR-PCH-NESTED: cond.false: +// IR-PCH-NESTED-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NESTED-NEXT: br label [[COND_END]] +// IR-PCH-NESTED: cond.end: +// IR-PCH-NESTED-NEXT: [[COND:%.*]] = phi i64 [ [[TMP15]], [[COND_TRUE]] ], [ [[TMP16]], [[COND_FALSE]] ] +// IR-PCH-NESTED-NEXT: store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[TMP17]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH-NESTED: omp.inner.for.cond: +// IR-PCH-NESTED-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP18]], [[TMP19]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH-NESTED: omp.inner.for.body: +// IR-PCH-NESTED-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP22:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP22]], ptr [[N_CASTED]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP23:%.*]] = load i64, ptr [[N_CASTED]], align 8 +// IR-PCH-NESTED-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined.omp_outlined, i64 [[TMP20]], i64 [[TMP21]], i64 [[TMP23]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) +// IR-PCH-NESTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH-NESTED: omp.inner.for.inc: +// IR-PCH-NESTED-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8 +// IR-PCH-NESTED-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP24]], [[TMP25]] +// IR-PCH-NESTED-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH-NESTED: omp.inner.for.end: +// IR-PCH-NESTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH-NESTED: omp.loop.exit: +// IR-PCH-NESTED-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4 +// IR-PCH-NESTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP27]]) +// IR-PCH-NESTED-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH-NESTED: omp.precond.end: +// IR-PCH-NESTED-NEXT: ret void +// +// +// IR-PCH-NESTED-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined.omp_outlined +// IR-PCH-NESTED-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] { +// IR-PCH-NESTED-NEXT: entry: +// IR-PCH-NESTED-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[TMP:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[I:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[J:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 +// IR-PCH-NESTED-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[I11:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: [[J12:%.*]] = alloca i32, align 4 +// IR-PCH-NESTED-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NESTED-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0 +// IR-PCH-NESTED-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 +// IR-PCH-NESTED-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 +// IR-PCH-NESTED-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP7]], 0 +// IR-PCH-NESTED-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 +// IR-PCH-NESTED-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 +// IR-PCH-NESTED-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] +// IR-PCH-NESTED-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 +// IR-PCH-NESTED-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[I]], align 4 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[J]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 +// IR-PCH-NESTED-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP8]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] +// IR-PCH-NESTED: land.lhs.true: +// IR-PCH-NESTED-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP9]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] +// IR-PCH-NESTED: omp.precond.then: +// IR-PCH-NESTED-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_LB]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NESTED-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 +// IR-PCH-NESTED-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// IR-PCH-NESTED-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2:[0-9]+]], i32 [[TMP14]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) +// IR-PCH-NESTED-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP15]], [[TMP16]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] +// IR-PCH-NESTED: cond.true: +// IR-PCH-NESTED-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 +// IR-PCH-NESTED-NEXT: br label [[COND_END:%.*]] +// IR-PCH-NESTED: cond.false: +// IR-PCH-NESTED-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NESTED-NEXT: br label [[COND_END]] +// IR-PCH-NESTED: cond.end: +// IR-PCH-NESTED-NEXT: [[COND:%.*]] = phi i64 [ [[TMP17]], [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] +// IR-PCH-NESTED-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 +// IR-PCH-NESTED-NEXT: store i64 [[TMP19]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] +// IR-PCH-NESTED: omp.inner.for.cond: +// IR-PCH-NESTED-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 +// IR-PCH-NESTED-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP20]], [[TMP21]] +// IR-PCH-NESTED-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// IR-PCH-NESTED: omp.inner.for.body: +// IR-PCH-NESTED-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP23]], 0 +// IR-PCH-NESTED-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// IR-PCH-NESTED-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// IR-PCH-NESTED-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// IR-PCH-NESTED-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP22]], [[CONV18]] +// IR-PCH-NESTED-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// IR-PCH-NESTED-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// IR-PCH-NESTED-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// IR-PCH-NESTED-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP26]], 0 +// IR-PCH-NESTED-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// IR-PCH-NESTED-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// IR-PCH-NESTED-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// IR-PCH-NESTED-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP25]], [[CONV25]] +// IR-PCH-NESTED-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// IR-PCH-NESTED-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP27]], 0 +// IR-PCH-NESTED-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// IR-PCH-NESTED-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// IR-PCH-NESTED-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// IR-PCH-NESTED-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// IR-PCH-NESTED-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP24]], [[MUL31]] +// IR-PCH-NESTED-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// IR-PCH-NESTED-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// IR-PCH-NESTED-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// IR-PCH-NESTED-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP28:%.*]] = load i32, ptr [[I11]], align 4 +// IR-PCH-NESTED-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP28]] to i64 +// IR-PCH-NESTED-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]] +// IR-PCH-NESTED-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +// IR-PCH-NESTED-NEXT: [[TMP30:%.*]] = load i32, ptr [[N_ADDR]], align 4 +// IR-PCH-NESTED-NEXT: [[MUL36:%.*]] = mul nsw i32 [[TMP29]], [[TMP30]] +// IR-PCH-NESTED-NEXT: [[TMP31:%.*]] = load i32, ptr [[J12]], align 4 +// IR-PCH-NESTED-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP31]]) +// IR-PCH-NESTED-NEXT: [[ADD37:%.*]] = add nsw i32 [[MUL36]], [[CALL]] +// IR-PCH-NESTED-NEXT: [[TMP32:%.*]] = load i32, ptr [[I11]], align 4 +// IR-PCH-NESTED-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP32]] to i64 +// IR-PCH-NESTED-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM38]] +// IR-PCH-NESTED-NEXT: store i32 [[ADD37]], ptr [[ARRAYIDX39]], align 4 +// IR-PCH-NESTED-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-PCH-NESTED: omp.body.continue: +// IR-PCH-NESTED-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] +// IR-PCH-NESTED: omp.inner.for.inc: +// IR-PCH-NESTED-NEXT: [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: [[ADD40:%.*]] = add nsw i64 [[TMP33]], 1 +// IR-PCH-NESTED-NEXT: store i64 [[ADD40]], ptr [[DOTOMP_IV]], align 8 +// IR-PCH-NESTED-NEXT: br label [[OMP_INNER_FOR_COND]] +// IR-PCH-NESTED: omp.inner.for.end: +// IR-PCH-NESTED-NEXT: br label [[OMP_LOOP_EXIT:%.*]] +// IR-PCH-NESTED: omp.loop.exit: +// IR-PCH-NESTED-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NESTED-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4 +// IR-PCH-NESTED-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP35]]) +// IR-PCH-NESTED-NEXT: br label [[OMP_PRECOND_END]] +// IR-PCH-NESTED: omp.precond.end: +// IR-PCH-NESTED-NEXT: ret void +// diff --git a/clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp index 1edcbfe2d777..e1a6aad65b79 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_if_codegen.cpp @@ -332,78 +332,8 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9gtid_testv_l51.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: call void @_Z9gtid_testv() @@ -411,14 +341,14 @@ int main() { // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: ret void // // @@ -586,78 +516,8 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l76.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: call void @_Z3fn4v() @@ -665,14 +525,14 @@ int main() { // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: ret void // // @@ -695,7 +555,6 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 @@ -725,82 +584,8 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined.omp_outlined(ptr [[TMP11]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: call void @_Z3fn5v() @@ -808,14 +593,14 @@ int main() { // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: ret void // // @@ -847,7 +632,6 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 @@ -878,30 +662,18 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 -// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP11]] to i1 -// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] -// CHECK1: omp_if.then: -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_IF_END:%.*]] -// CHECK1: omp_if.else: -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.omp_outlined.omp_outlined(ptr [[TMP12]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) -// CHECK1-NEXT: br label [[OMP_IF_END]] -// CHECK1: omp_if.end: +// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK1-NEXT: call void @_Z3fn6v() +// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -910,85 +682,19 @@ int main() { // CHECK1-NEXT: ret void // // -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l90.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { +// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ +// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { // CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: call void @_Z3fn6v() -// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK1: omp.body.continue: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiEiT_ -// CHECK1-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0]] comdat { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 -// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[KERNEL_ARGS2:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8 +// CHECK1-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 +// CHECK1-NEXT: [[KERNEL_ARGS5:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 // CHECK1-NEXT: store i32 [[ARG]], ptr [[ARG_ADDR]], align 4 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0 // CHECK1-NEXT: store i32 3, ptr [[TMP0]], align 4 @@ -1026,44 +732,61 @@ int main() { // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64() #[[ATTR2]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARG_ADDR]], align 4 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 -// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK1-NEXT: [[TMP16:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK1-NEXT: [[TOBOOL1:%.*]] = trunc i8 [[TMP16]] to i1 +// CHECK1-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL1]] to i8 +// CHECK1-NEXT: store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK1-NEXT: [[TMP18:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1 +// CHECK1-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP18]] to i1 +// CHECK1-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] // CHECK1: omp_if.then: -// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 0 -// CHECK1-NEXT: store i32 3, ptr [[TMP16]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 1 -// CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 2 -// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8 -// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 3 -// CHECK1-NEXT: store ptr null, ptr [[TMP19]], align 8 -// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 4 -// CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8 -// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 5 +// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP19]], align 8 +// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: store i64 [[TMP17]], ptr [[TMP20]], align 8 +// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 6 -// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8 -// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 7 -// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8 -// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 8 -// CHECK1-NEXT: store i64 100, ptr [[TMP24]], align 8 -// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 9 -// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8 -// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 10 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4 -// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 11 -// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4 -// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS2]], i32 0, i32 12 -// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4 -// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, ptr [[KERNEL_ARGS2]]) -// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 -// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] -// CHECK1: omp_offload.failed3: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68() #[[ATTR2]] -// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] -// CHECK1: omp_offload.cont4: +// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 0 +// CHECK1-NEXT: store i32 3, ptr [[TMP24]], align 4 +// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 1 +// CHECK1-NEXT: store i32 1, ptr [[TMP25]], align 4 +// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 2 +// CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 8 +// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 3 +// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP27]], align 8 +// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 4 +// CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP28]], align 8 +// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 5 +// CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP29]], align 8 +// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 6 +// CHECK1-NEXT: store ptr null, ptr [[TMP30]], align 8 +// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 7 +// CHECK1-NEXT: store ptr null, ptr [[TMP31]], align 8 +// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 8 +// CHECK1-NEXT: store i64 100, ptr [[TMP32]], align 8 +// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 9 +// CHECK1-NEXT: store i64 0, ptr [[TMP33]], align 8 +// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 10 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 +// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 11 +// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP35]], align 4 +// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS5]], i32 0, i32 12 +// CHECK1-NEXT: store i32 0, ptr [[TMP36]], align 4 +// CHECK1-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.region_id, ptr [[KERNEL_ARGS5]]) +// CHECK1-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 +// CHECK1-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] +// CHECK1: omp_offload.failed6: +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP17]]) #[[ATTR2]] +// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]] +// CHECK1: omp_offload.cont7: // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] // CHECK1: omp_if.else: -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68() #[[ATTR2]] +// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68(i64 [[TMP17]]) #[[ATTR2]] // CHECK1-NEXT: br label [[OMP_IF_END]] // CHECK1: omp_if.end: // CHECK1-NEXT: ret i32 0 @@ -1117,78 +840,8 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l60.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: call void @_Z3fn1v() @@ -1196,14 +849,14 @@ int main() { // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: ret void // // @@ -1226,7 +879,6 @@ int main() { // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 @@ -1256,82 +908,8 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void @__kmpc_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) -// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4 -// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64.omp_outlined.omp_outlined(ptr [[TMP11]], ptr [[DOTBOUND_ZERO_ADDR]], i64 [[TMP8]], i64 [[TMP10]]) #[[ATTR2]] -// CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(ptr @[[GLOB3]], i32 [[TMP1]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l64.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: call void @_Z3fn2v() @@ -1339,29 +917,38 @@ int main() { // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68 -// CHECK1-SAME: () #[[ATTR1]] { +// CHECK1-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.omp_outlined) +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 +// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 +// CHECK1-NEXT: [[TMP0:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1 +// CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP0]] to i1 +// CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 +// CHECK1-NEXT: store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1 +// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8 +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.omp_outlined, i64 [[TMP1]]) // CHECK1-NEXT: ret void // // // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { +// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 +// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 @@ -1371,6 +958,7 @@ int main() { // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 +// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 // CHECK1-NEXT: store i32 99, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 @@ -1398,78 +986,8 @@ int main() { // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiEiT__l68.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 99 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: call void @_Z3fn3v() @@ -1477,13 +995,13 @@ int main() { // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 +// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK1-NEXT: ret void // diff --git a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp index 99416f76e409..9b3d77f5b0ad 100644 --- a/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp +++ b/clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp @@ -326,7 +326,7 @@ int main() { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -340,7 +340,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK1-NEXT: ret void // // @@ -403,149 +403,48 @@ int main() { // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 -// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done3: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 -// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK1: arrayctor.loop: -// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 -// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK1: omp.inner.for.cond.cleanup: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4 +// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done8: +// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK1: arraydestroy.done7: // CHECK1-NEXT: ret void // // @@ -596,7 +495,7 @@ int main() { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -645,7 +544,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 // CHECK1-SAME: () #[[ATTR4]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK1-NEXT: ret void // // @@ -711,149 +610,45 @@ int main() { // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 -// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done5: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 -// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK1: arrayctor.loop: -// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 -// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK1: omp.inner.for.cond.cleanup: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) +// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done9: +// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK1: arraydestroy.done8: // CHECK1-NEXT: ret void // // @@ -1059,7 +854,7 @@ int main() { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -1073,7 +868,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK3-NEXT: ret void // // @@ -1136,138 +931,41 @@ int main() { // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK3: omp.inner.for.cond.cleanup: -// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] @@ -1323,7 +1021,7 @@ int main() { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -1372,7 +1070,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80 // CHECK3-SAME: () #[[ATTR4]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK3-NEXT: ret void // // @@ -1438,138 +1136,38 @@ int main() { // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done5: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK3: omp.inner.for.cond.cleanup: -// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] @@ -1760,7 +1358,7 @@ int main() { // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104 // CHECK5-SAME: () #[[ATTR4:[0-9]+]] { // CHECK5-NEXT: entry: -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) +// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) // CHECK5-NEXT: ret void // // @@ -1781,6 +1379,7 @@ int main() { // CHECK5-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 @@ -1812,17 +1411,29 @@ int main() { // CHECK5-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) +// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK5-NEXT: store i32 1, ptr [[G]], align 4 +// CHECK5-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK5-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 +// CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 4 +// CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK5-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 +// CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK5-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK5-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 +// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 +// CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 +// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) +// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK5: omp.body.continue: // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK5-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK5: omp.inner.for.end: // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -1831,98 +1442,8 @@ int main() { // CHECK5-NEXT: ret void // // -// CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined -// CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK5-NEXT: entry: -// CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 -// CHECK5-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK5-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK5-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK5-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 -// CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK5: cond.true: -// CHECK5-NEXT: br label [[COND_END:%.*]] -// CHECK5: cond.false: -// CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: br label [[COND_END]] -// CHECK5: cond.end: -// CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK5-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK5: omp.inner.for.cond: -// CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK5-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK5: omp.inner.for.body: -// CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK5-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK5-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 -// CHECK5-NEXT: store i32 2, ptr [[SIVAR]], align 4 -// CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 -// CHECK5-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 -// CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK5-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK5-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 -// CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 -// CHECK5-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 -// CHECK5-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) -// CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK5: omp.body.continue: -// CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK5: omp.inner.for.inc: -// CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK5-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 -// CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK5: omp.inner.for.end: -// CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK5: omp.loop.exit: -// CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) -// CHECK5-NEXT: ret void -// -// -// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp -// CHECK5-SAME: () #[[ATTR0]] { +// CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp +// CHECK5-SAME: () #[[ATTR0]] { // CHECK5-NEXT: entry: // CHECK5-NEXT: call void @__cxx_global_var_init() // CHECK5-NEXT: call void @__cxx_global_var_init.1() @@ -1935,7 +1456,7 @@ int main() { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK13-NEXT: ret void // // @@ -1998,35 +1519,48 @@ int main() { // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK13-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK13-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK13-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) +// CHECK13-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK13-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done3: +// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK13: arraydestroy.done7: // CHECK13-NEXT: ret void // // @@ -2040,120 +1574,6 @@ int main() { // CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined -// CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK13-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 -// CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK13-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4 -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done8: -// CHECK13-NEXT: ret void -// -// // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: @@ -2169,7 +1589,7 @@ int main() { // CHECK13-NEXT: entry: // CHECK13-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK13-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) +// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK13-NEXT: ret void // // @@ -2235,17 +1655,27 @@ int main() { // CHECK13: omp.inner.for.cond.cleanup: // CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK13-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) +// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 +// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) +// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// CHECK13: omp.body.continue: // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK13-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK13: omp.inner.for.end: // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] @@ -2254,16 +1684,16 @@ int main() { // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 // CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 +// CHECK13-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK13-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK13: arraydestroy.body: // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done5: +// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK13: arraydestroy.done8: // CHECK13-NEXT: ret void // // @@ -2277,120 +1707,6 @@ int main() { // CHECK13-NEXT: ret void // // -// CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined -// CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK13-NEXT: entry: -// CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK13-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK13-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK13-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 -// CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK13-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK13-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK13-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK13-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK13-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK13-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 -// CHECK13-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK13: arrayctor.loop: -// CHECK13-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK13-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 -// CHECK13-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK13-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK13: arrayctor.cont: -// CHECK13-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK13-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 -// CHECK13-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK13-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK13: cond.true: -// CHECK13-NEXT: br label [[COND_END:%.*]] -// CHECK13: cond.false: -// CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: br label [[COND_END]] -// CHECK13: cond.end: -// CHECK13-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK13-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK13: omp.inner.for.cond: -// CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK13-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK13-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK13: omp.inner.for.cond.cleanup: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK13: omp.inner.for.body: -// CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 -// CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) -// CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// CHECK13: omp.body.continue: -// CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK13: omp.inner.for.inc: -// CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK13-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 -// CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK13: omp.inner.for.end: -// CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK13: omp.loop.exit: -// CHECK13-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK13-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK13-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 -// CHECK13-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK13: arraydestroy.body: -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK13-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK13-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK13-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK13-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK13: arraydestroy.done9: -// CHECK13-NEXT: ret void -// -// // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat { // CHECK13-NEXT: entry: @@ -2449,7 +1765,7 @@ int main() { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) +// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined) // CHECK15-NEXT: ret void // // @@ -2512,148 +1828,41 @@ int main() { // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] -// CHECK15-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done3: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined -// CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK15-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK15-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] -// CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 -// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK15-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] // CHECK15-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) -// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] +// CHECK15-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) +// CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]] // CHECK15-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 +// CHECK15-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] @@ -2662,6 +1871,16 @@ int main() { // CHECK15-NEXT: ret void // // +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: ret void +// +// // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: @@ -2677,7 +1896,7 @@ int main() { // CHECK15-NEXT: entry: // CHECK15-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4 // CHECK15-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) +// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined) // CHECK15-NEXT: ret void // // @@ -2743,148 +1962,38 @@ int main() { // CHECK15: omp.inner.for.cond.cleanup: // CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK15-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) -// CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK15-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK15: omp.inner.for.end: -// CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 -// CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] -// CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK15-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK15: arraydestroy.done5: -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev -// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] -// CHECK15-NEXT: ret void -// -// -// CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined -// CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK15-NEXT: entry: -// CHECK15-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK15-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK15-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK15-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 -// CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK15-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store ptr undef, ptr [[_TMP1]], align 4 -// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK15-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK15-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 -// CHECK15-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK15: arrayctor.loop: -// CHECK15-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]] -// CHECK15-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 -// CHECK15-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK15-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK15: arrayctor.cont: -// CHECK15-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] -// CHECK15-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK15-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK15: cond.true: -// CHECK15-NEXT: br label [[COND_END:%.*]] -// CHECK15: cond.false: -// CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: br label [[COND_END]] -// CHECK15: cond.end: -// CHECK15-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK15-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK15-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK15: omp.inner.for.cond: // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK15-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK15-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK15: omp.inner.for.cond.cleanup: -// CHECK15-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK15: omp.inner.for.body: -// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] -// CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 -// CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK15: omp.inner.for.inc: -// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK15-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK15: omp.inner.for.end: // CHECK15-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK15: omp.loop.exit: -// CHECK15-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) +// CHECK15-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK15-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK15-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 +// CHECK15-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK15-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK15: arraydestroy.body: -// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK15-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK15-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK15-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]] // CHECK15-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] @@ -2893,6 +2002,16 @@ int main() { // CHECK15-NEXT: ret void // // +// CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev +// CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { +// CHECK15-NEXT: entry: +// CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 +// CHECK15-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 +// CHECK15-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] +// CHECK15-NEXT: ret void +// +// // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { // CHECK15-NEXT: entry: @@ -2951,7 +2070,7 @@ int main() { // CHECK17-NEXT: entry: // CHECK17-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined) // CHECK17-NEXT: ret void // // @@ -2972,6 +2091,7 @@ int main() { // CHECK17-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK17-NEXT: store ptr undef, ptr [[_TMP1]], align 8 @@ -3003,111 +2123,33 @@ int main() { // CHECK17-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 -// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: // CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK17-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 +// CHECK17-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK17-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK17-NEXT: store i32 2, ptr [[SIVAR]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 -// CHECK17-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 -// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 -// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 -// CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 +// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK17-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 +// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK17-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 +// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2 +// CHECK17-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 // CHECK17-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK17-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK17-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp b/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp index d4a98f07fe24..23c5c9db9c70 100644 --- a/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp +++ b/clang/test/OpenMP/teams_generic_loop_codegen-1.cpp @@ -278,7 +278,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store [3 x i32] [[TMP28]], ptr [[TMP40]], align 4 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4 -// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 [[TMP21]], i32 [[TMP22]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 [[TMP21]], i32 [[TMP22]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -338,7 +338,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP69]], align 4 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS15]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP70]], align 4 -// CHECK1-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.region_id, ptr [[KERNEL_ARGS15]]) +// CHECK1-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.region_id, ptr [[KERNEL_ARGS15]]) // CHECK1-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0 // CHECK1-NEXT: br i1 [[TMP72]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] // CHECK1: omp_offload.failed16: @@ -356,7 +356,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK1-NEXT: store i64 [[TE]], ptr [[TE_ADDR]], align 8 // CHECK1-NEXT: store i64 [[TH]], ptr [[TH_ADDR]], align 8 // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 @@ -364,8 +364,8 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TE_ADDR]], align 4 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TH_ADDR]], align 4 -// CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined, ptr [[N_ADDR]], ptr [[TMP1]]) +// CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined, ptr [[N_ADDR]], ptr [[TMP1]]) // CHECK1-NEXT: ret void // // @@ -434,126 +434,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP0]], ptr [[TMP1]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: br label [[OMP_PRECOND_END]] -// CHECK1: omp.precond.end: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 -// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK1: omp.precond.then: -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) // CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1: omp.precond.end: // CHECK1-NEXT: ret void @@ -567,7 +469,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8 // CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined, ptr [[N_ADDR]], ptr [[TMP0]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined, ptr [[N_ADDR]], ptr [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -636,126 +538,28 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined.omp_outlined, i64 [[TMP16]], i64 [[TMP18]], ptr [[TMP0]], ptr [[TMP1]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]]) -// CHECK1-NEXT: br label [[OMP_PRECOND_END]] -// CHECK1: omp.precond.end: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 -// CHECK1-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 -// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK1: omp.precond.then: -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP6]] to i32 -// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 +// CHECK1-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) +// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) // CHECK1-NEXT: br label [[OMP_PRECOND_END]] // CHECK1: omp.precond.end: // CHECK1-NEXT: ret void @@ -865,7 +669,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store [3 x i32] [[TMP28]], ptr [[TMP40]], align 4 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 4 -// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 [[TMP21]], i32 [[TMP22]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 [[TMP21]], i32 [[TMP22]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -925,7 +729,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP69]], align 4 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS15]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP70]], align 4 -// CHECK3-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.region_id, ptr [[KERNEL_ARGS15]]) +// CHECK3-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.region_id, ptr [[KERNEL_ARGS15]]) // CHECK3-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0 // CHECK3-NEXT: br i1 [[TMP72]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] // CHECK3: omp_offload.failed16: @@ -943,7 +747,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK3-NEXT: store i32 [[TE]], ptr [[TE_ADDR]], align 4 // CHECK3-NEXT: store i32 [[TH]], ptr [[TH_ADDR]], align 4 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 @@ -951,8 +755,8 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TE_ADDR]], align 4 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TH_ADDR]], align 4 -// CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined, ptr [[N_ADDR]], ptr [[TMP1]]) +// CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined, ptr [[N_ADDR]], ptr [[TMP1]]) // CHECK3-NEXT: ret void // // @@ -1021,121 +825,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[TMP0]], ptr [[TMP1]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK3-NEXT: br label [[OMP_PRECOND_END]] -// CHECK3: omp.precond.end: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l28.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 -// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK3: omp.precond.then: -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) +// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) // CHECK3-NEXT: br label [[OMP_PRECOND_END]] // CHECK3: omp.precond.end: // CHECK3-NEXT: ret void @@ -1149,7 +859,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4 // CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined, ptr [[N_ADDR]], ptr [[TMP0]]) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined, ptr [[N_ADDR]], ptr [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -1218,121 +928,27 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined.omp_outlined, i32 [[TMP15]], i32 [[TMP16]], ptr [[TMP0]], ptr [[TMP1]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) -// CHECK3-NEXT: br label [[OMP_PRECOND_END]] -// CHECK3: omp.precond.end: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z21teams_argument_globali_l34.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[A:%.*]]) #[[ATTR1]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 -// CHECK3-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0 -// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]] -// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK3: omp.precond.then: -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] -// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP19]], 1 +// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], 1 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) +// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) // CHECK3-NEXT: br label [[OMP_PRECOND_END]] // CHECK3: omp.precond.end: // CHECK3-NEXT: ret void @@ -1424,7 +1040,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK9-NEXT: store i32 0, ptr [[TMP35]], align 4 -// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.region_id, ptr [[KERNEL_ARGS]]) +// CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.region_id, ptr [[KERNEL_ARGS]]) // CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: @@ -1449,7 +1065,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined, ptr [[N_ADDR]], i64 [[TMP0]], ptr [[TMP1]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined, ptr [[N_ADDR]], i64 [[TMP0]], ptr [[TMP1]]) // CHECK9-NEXT: ret void // // @@ -1521,129 +1137,28 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK9-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK9-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK9-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP22]]) +// CHECK9-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) // CHECK9-NEXT: br label [[OMP_PRECOND_END]] // CHECK9: omp.precond.end: // CHECK9-NEXT: ret void @@ -1735,7 +1250,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK11-NEXT: store i32 0, ptr [[TMP35]], align 4 -// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.region_id, ptr [[KERNEL_ARGS]]) +// CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.region_id, ptr [[KERNEL_ARGS]]) // CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: @@ -1760,7 +1275,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined, ptr [[N_ADDR]], i32 [[TMP0]], ptr [[TMP1]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined, ptr [[N_ADDR]], i32 [[TMP0]], ptr [[TMP1]]) // CHECK11-NEXT: ret void // // @@ -1832,124 +1347,27 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined.omp_outlined, i32 [[TMP16]], i32 [[TMP17]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK11-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z15teams_local_argv_l72.omp_outlined.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK11-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 -// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP19]] +// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP17]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP22]]) +// CHECK11-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) // CHECK11-NEXT: br label [[OMP_PRECOND_END]] // CHECK11: omp.precond.end: // CHECK11-NEXT: ret void @@ -2009,7 +1427,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK17-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK17-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.region_id, ptr [[KERNEL_ARGS]]) +// CHECK17-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.region_id, ptr [[KERNEL_ARGS]]) // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK17-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK17: omp_offload.failed: @@ -2028,7 +1446,7 @@ int main (int argc, char **argv) { // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined, ptr [[TMP0]]) +// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined, ptr [[TMP0]]) // CHECK17-NEXT: ret void // // @@ -2041,135 +1459,62 @@ int main (int argc, char **argv) { // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 122, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 -// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK17: cond.true: -// CHECK17-NEXT: br label [[COND_END:%.*]] -// CHECK17: cond.false: -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: br label [[COND_END]] -// CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] -// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK17-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[TMP0]]) -// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK17-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK17: omp.inner.for.end: -// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK17-NEXT: ret void -// -// -// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined.omp_outlined -// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { -// CHECK17-NEXT: entry: -// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 +// CHECK17-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 // CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 // CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 122, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK17-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK17-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK17-NEXT: store i32 122, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 +// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4 +// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) +// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 122 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] // CHECK17: cond.true: // CHECK17-NEXT: br label [[COND_END:%.*]] // CHECK17: cond.false: -// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 +// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 // CHECK17-NEXT: br label [[COND_END]] // CHECK17: cond.end: -// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK17-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] +// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 +// CHECK17-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] // CHECK17: omp.inner.for.cond: -// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] +// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 +// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] +// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK17: omp.inner.for.body: -// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK17: omp.inner.for.inc: -// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK17-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK17-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK17: omp.inner.for.end: // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK17: omp.loop.exit: -// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK17-NEXT: ret void // // @@ -2227,7 +1572,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK19-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK19-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.region_id, ptr [[KERNEL_ARGS]]) +// CHECK19-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.region_id, ptr [[KERNEL_ARGS]]) // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK19-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK19: omp_offload.failed: @@ -2246,7 +1591,7 @@ int main (int argc, char **argv) { // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined, ptr [[TMP0]]) +// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined, ptr [[TMP0]]) // CHECK19-NEXT: ret void // // @@ -2294,95 +1639,26 @@ int main (int argc, char **argv) { // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[TMP0]]) -// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK19-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK19: omp.inner.for.end: -// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK19-NEXT: ret void -// -// -// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l108.omp_outlined.omp_outlined -// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { -// CHECK19-NEXT: entry: -// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 122, ptr [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 122 -// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK19: cond.true: -// CHECK19-NEXT: br label [[COND_END:%.*]] -// CHECK19: cond.false: -// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: br label [[COND_END]] -// CHECK19: cond.end: -// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 122, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK19-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK19: omp.inner.for.cond: // CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK19: omp.inner.for.body: -// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK19: omp.inner.for.inc: -// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK19-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK19: omp.inner.for.end: // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK19: omp.loop.exit: -// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK19-NEXT: ret void // // @@ -2478,7 +1754,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 // CHECK25-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK25-NEXT: store i32 0, ptr [[TMP35]], align 4 -// CHECK25-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.region_id, ptr [[KERNEL_ARGS]]) +// CHECK25-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.region_id, ptr [[KERNEL_ARGS]]) // CHECK25-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK25-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK25: omp_offload.failed: @@ -2505,7 +1781,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined, ptr [[N_ADDR]], i64 [[TMP0]], ptr [[TMP1]]) +// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined, ptr [[N_ADDR]], i64 [[TMP0]], ptr [[TMP1]]) // CHECK25-NEXT: ret void // // @@ -2577,129 +1853,28 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK25-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64 -// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined.omp_outlined, i64 [[TMP17]], i64 [[TMP19]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]]) -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] -// CHECK25-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]]) -// CHECK25-NEXT: br label [[OMP_PRECOND_END]] -// CHECK25: omp.precond.end: -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined.omp_outlined -// CHECK25-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I4:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 -// CHECK25-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK25-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK25-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK25-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK25-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK25-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK25-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK25-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK25: omp.precond.then: -// CHECK25-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = trunc i64 [[TMP7]] to i32 -// CHECK25-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP8]] to i32 -// CHECK25-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK25-NEXT: br i1 [[CMP5]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: // CHECK25-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK25-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// CHECK25-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 -// CHECK25-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 +// CHECK25-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 +// CHECK25-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[IDXPROM]] // CHECK25-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 -// CHECK25-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 +// CHECK25-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25: omp.loop.exit: -// CHECK25-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP22]]) +// CHECK25-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK25-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK25-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) // CHECK25-NEXT: br label [[OMP_PRECOND_END]] // CHECK25: omp.precond.end: // CHECK25-NEXT: ret void @@ -2778,7 +1953,7 @@ int main (int argc, char **argv) { // CHECK25-NEXT: store [3 x i32] [[TMP18]], ptr [[TMP30]], align 4 // CHECK25-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK25-NEXT: store i32 0, ptr [[TMP31]], align 4 -// CHECK25-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 [[TMP15]], i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.region_id, ptr [[KERNEL_ARGS]]) +// CHECK25-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP15]], i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.region_id, ptr [[KERNEL_ARGS]]) // CHECK25-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK25-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK25: omp_offload.failed: @@ -2794,15 +1969,15 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[TE_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[TH_ADDR:%.*]] = alloca i64, align 8 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK25-NEXT: store i64 [[TE]], ptr [[TE_ADDR]], align 8 // CHECK25-NEXT: store i64 [[TH]], ptr [[TH_ADDR]], align 8 // CHECK25-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK25-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, ptr [[TE_ADDR]], align 4 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, ptr [[TH_ADDR]], align 4 -// CHECK25-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined, ptr [[TMP1]]) +// CHECK25-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined, ptr [[TMP1]]) // CHECK25-NEXT: ret void // // @@ -2850,99 +2025,26 @@ int main (int argc, char **argv) { // CHECK25-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK25-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK25-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK25-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[TMP0]]) -// CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK25-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK25: omp.inner.for.end: -// CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK25-NEXT: ret void -// -// -// CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined.omp_outlined -// CHECK25-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK25-NEXT: entry: -// CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK25-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK25-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK25-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK25-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK25-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK25-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK25-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK25-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK25-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK25-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK25-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK25-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK25-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK25-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK25: cond.true: -// CHECK25-NEXT: br label [[COND_END:%.*]] -// CHECK25: cond.false: -// CHECK25-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: br label [[COND_END]] -// CHECK25: cond.end: -// CHECK25-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK25-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK25-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK25: omp.inner.for.cond: // CHECK25-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK25-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK25-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK25: omp.inner.for.body: -// CHECK25-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK25-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK25-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK25-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK25-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] // CHECK25-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: // CHECK25-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK25: omp.inner.for.inc: -// CHECK25-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 -// CHECK25-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK25-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 +// CHECK25-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK25-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK25: omp.inner.for.end: // CHECK25-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK25: omp.loop.exit: -// CHECK25-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK25-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK25-NEXT: ret void // // @@ -3038,7 +2140,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4 // CHECK27-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK27-NEXT: store i32 0, ptr [[TMP35]], align 4 -// CHECK27-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.region_id, ptr [[KERNEL_ARGS]]) +// CHECK27-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.region_id, ptr [[KERNEL_ARGS]]) // CHECK27-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 // CHECK27-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK27: omp_offload.failed: @@ -3065,7 +2167,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined, ptr [[N_ADDR]], i32 [[TMP0]], ptr [[TMP1]]) +// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined, ptr [[N_ADDR]], i32 [[TMP0]], ptr [[TMP1]]) // CHECK27-NEXT: ret void // // @@ -3137,124 +2239,27 @@ int main (int argc, char **argv) { // CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] // CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined.omp_outlined, i32 [[TMP16]], i32 [[TMP17]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]]) -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] -// CHECK27-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]]) -// CHECK27-NEXT: br label [[OMP_PRECOND_END]] -// CHECK27: omp.precond.end: -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l161.omp_outlined.omp_outlined -// CHECK27-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I3:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 -// CHECK27-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK27-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK27-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], 0 -// CHECK27-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK27-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 -// CHECK27-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP5]] -// CHECK27-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK27: omp.precond.then: -// CHECK27-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP10]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP11]], [[TMP12]] -// CHECK27-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4 -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: // CHECK27-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] -// CHECK27-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 -// CHECK27-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP19]] +// CHECK27-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP17]] // CHECK27-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP20]], 1 +// CHECK27-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], 1 // CHECK27-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK27: omp.loop.exit: -// CHECK27-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP22]]) +// CHECK27-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK27-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 +// CHECK27-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]]) // CHECK27-NEXT: br label [[OMP_PRECOND_END]] // CHECK27: omp.precond.end: // CHECK27-NEXT: ret void @@ -3333,7 +2338,7 @@ int main (int argc, char **argv) { // CHECK27-NEXT: store [3 x i32] [[TMP18]], ptr [[TMP30]], align 4 // CHECK27-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK27-NEXT: store i32 0, ptr [[TMP31]], align 4 -// CHECK27-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 [[TMP15]], i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.region_id, ptr [[KERNEL_ARGS]]) +// CHECK27-NEXT: [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP15]], i32 [[TMP16]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.region_id, ptr [[KERNEL_ARGS]]) // CHECK27-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 // CHECK27-NEXT: br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK27: omp_offload.failed: @@ -3349,15 +2354,15 @@ int main (int argc, char **argv) { // CHECK27-NEXT: [[TE_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[TH_ADDR:%.*]] = alloca i32, align 4 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]]) +// CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) // CHECK27-NEXT: store i32 [[TE]], ptr [[TE_ADDR]], align 4 // CHECK27-NEXT: store i32 [[TH]], ptr [[TH_ADDR]], align 4 // CHECK27-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 4 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[TE_ADDR]], align 4 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, ptr [[TH_ADDR]], align 4 -// CHECK27-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) -// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined, ptr [[TMP1]]) +// CHECK27-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) +// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined, ptr [[TMP1]]) // CHECK27-NEXT: ret void // // @@ -3405,93 +2410,24 @@ int main (int argc, char **argv) { // CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK27-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[TMP0]]) -// CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK27-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK27: omp.inner.for.end: -// CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK27-NEXT: ret void -// -// -// CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10EEiT__l150.omp_outlined.omp_outlined -// CHECK27-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[A:%.*]]) #[[ATTR2]] { -// CHECK27-NEXT: entry: -// CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK27-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK27-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK27-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK27-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK27-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK27-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK27-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK27-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK27-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK27-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK27-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 9 -// CHECK27-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK27: cond.true: -// CHECK27-NEXT: br label [[COND_END:%.*]] -// CHECK27: cond.false: -// CHECK27-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: br label [[COND_END]] -// CHECK27: cond.end: -// CHECK27-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK27-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK27-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK27: omp.inner.for.cond: // CHECK27-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK27-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK27-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK27: omp.inner.for.body: -// CHECK27-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK27-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK27-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK27-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] // CHECK27-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: // CHECK27-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK27: omp.inner.for.inc: -// CHECK27-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK27-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK27-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4 // CHECK27-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK27: omp.inner.for.end: // CHECK27-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK27: omp.loop.exit: -// CHECK27-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK27-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK27-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_generic_loop_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_codegen.cpp index 2499fbb6811c..85dcae26970b 100644 --- a/clang/test/OpenMP/teams_generic_loop_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_codegen.cpp @@ -29,7 +29,7 @@ int foo() { // IR-NEXT: [[I:%.*]] = alloca i32, align 4 // IR-NEXT: [[J:%.*]] = alloca i32, align 4 // IR-NEXT: [[SUM:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 2, ptr @_Z3foov.omp_outlined, ptr [[J]], ptr [[SUM]]) +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @_Z3foov.omp_outlined, ptr [[J]], ptr [[SUM]]) // IR-NEXT: ret i32 0 // // @@ -96,277 +96,100 @@ int foo() { // IR-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // IR-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // IR: omp.inner.for.body: -// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 4, ptr @_Z3foov.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[J3]], ptr [[SUM1]]) +// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 +// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[DIV6:%.*]] = sdiv i32 [[TMP12]], 10 +// IR-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 10 +// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL7]] +// IR-NEXT: [[MUL8:%.*]] = mul nsw i32 [[SUB]], 1 +// IR-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] +// IR-NEXT: store i32 [[ADD9]], ptr [[J3]], align 4 +// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 +// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 +// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM1]], i64 0, i64 [[IDXPROM]] +// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[J3]], align 4 +// IR-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 +// IR-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM10]] +// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 +// IR-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP16]], [[TMP13]] +// IR-NEXT: store i32 [[ADD12]], ptr [[ARRAYIDX11]], align 4 +// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR: omp.body.continue: // IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // IR: omp.inner.for.inc: -// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// IR-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1 +// IR-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 // IR-NEXT: br label [[OMP_INNER_FOR_COND]] // IR: omp.inner.for.end: // IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // IR: omp.loop.exit: -// IR-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP17]]) -// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// IR-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// IR-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 +// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) +// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// IR-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // IR: .omp.lastprivate.then: // IR-NEXT: store i32 10, ptr [[J3]], align 4 -// IR-NEXT: [[TMP20:%.*]] = load i32, ptr [[J3]], align 4 -// IR-NEXT: store i32 [[TMP20]], ptr [[TMP0]], align 4 +// IR-NEXT: [[TMP22:%.*]] = load i32, ptr [[J3]], align 4 +// IR-NEXT: store i32 [[TMP22]], ptr [[TMP0]], align 4 // IR-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // IR: .omp.lastprivate.done: -// IR-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// IR-NEXT: store ptr [[SUM1]], ptr [[TMP21]], align 8 -// IR-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// IR-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z3foov.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// IR-NEXT: switch i32 [[TMP24]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// IR-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// IR-NEXT: store ptr [[SUM1]], ptr [[TMP23]], align 8 +// IR-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 +// IR-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP25]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z3foov.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// IR-NEXT: switch i32 [[TMP26]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // IR-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // IR-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // IR-NEXT: ] // IR: .omp.reduction.case1: -// IR-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP25]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// IR-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 +// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP27]] +// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE18:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // IR: omp.arraycpy.body: // IR-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-NEXT: [[TMP26:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], align 4 -// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// IR-NEXT: store i32 [[ADD7]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], align 4 -// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 +// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], align 4 +// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// IR-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// IR-NEXT: store i32 [[ADD15]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], align 4 +// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT16]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 // IR-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP25]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// IR: omp.arraycpy.done10: -// IR-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) -// IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR: .omp.reduction.case2: -// IR-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY11:%.*]] = icmp eq ptr [[TMP1]], [[TMP28]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY11]], label [[OMP_ARRAYCPY_DONE18:%.*]], label [[OMP_ARRAYCPY_BODY12:%.*]] -// IR: omp.arraycpy.body12: -// IR-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST13:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY12]] ] -// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT15:%.*]], [[OMP_ARRAYCPY_BODY12]] ] -// IR-NEXT: [[TMP29:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], align 4 -// IR-NEXT: [[TMP30:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 [[TMP29]] monotonic, align 4 -// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT15]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT16]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT15]], [[TMP28]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY12]] +// IR-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT16]], [[TMP27]] +// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY]] // IR: omp.arraycpy.done18: -// IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR: .omp.reduction.default: -// IR-NEXT: ret void -// -// -// IR-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp_outlined -// IR-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1]] { -// IR-NEXT: entry: -// IR-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// IR-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// IR-NEXT: [[J_ADDR:%.*]] = alloca ptr, align 8 -// IR-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8 -// IR-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// IR-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// IR-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// IR-NEXT: [[J3:%.*]] = alloca i32, align 4 -// IR-NEXT: [[SUM4:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-NEXT: [[I:%.*]] = alloca i32, align 4 -// IR-NEXT: [[J5:%.*]] = alloca i32, align 4 -// IR-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// IR-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// IR-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// IR-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// IR-NEXT: store ptr [[J]], ptr [[J_ADDR]], align 8 -// IR-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR]], align 8 -// IR-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J_ADDR]], align 8 -// IR-NEXT: [[TMP1:%.*]] = load ptr, ptr [[SUM_ADDR]], align 8 -// IR-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// IR-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// IR-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// IR-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 -// IR-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// IR-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// IR-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// IR-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// IR-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// IR-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4]], i32 0, i32 0, i32 0 -// IR-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 100 -// IR-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] -// IR-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] -// IR: omp.arrayinit.body: -// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// IR-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] -// IR: omp.arrayinit.done: -// IR-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 -// IR-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// IR-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 99 -// IR-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// IR: cond.true: -// IR-NEXT: br label [[COND_END:%.*]] -// IR: cond.false: -// IR-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// IR-NEXT: br label [[COND_END]] -// IR: cond.end: -// IR-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// IR-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// IR-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 -// IR-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR: omp.inner.for.cond: -// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] -// IR-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// IR-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR: omp.inner.for.body: -// IR-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP12]], 10 -// IR-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// IR-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// IR-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP14]], 10 -// IR-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 10 -// IR-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP13]], [[MUL8]] -// IR-NEXT: [[MUL9:%.*]] = mul nsw i32 [[SUB]], 1 -// IR-NEXT: [[ADD10:%.*]] = add nsw i32 0, [[MUL9]] -// IR-NEXT: store i32 [[ADD10]], ptr [[J3]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// IR-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4]], i64 0, i64 [[IDXPROM]] -// IR-NEXT: [[TMP17:%.*]] = load i32, ptr [[J3]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// IR-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// IR-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP18]], [[TMP15]] -// IR-NEXT: store i32 [[ADD13]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// IR: omp.body.continue: -// IR-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR: omp.inner.for.inc: -// IR-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP19]], 1 -// IR-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// IR: omp.inner.for.end: -// IR-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR: omp.loop.exit: -// IR-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// IR-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// IR-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// IR-NEXT: store ptr [[SUM4]], ptr [[TMP22]], align 8 -// IR-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 -// IR-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z3foov.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// IR-NEXT: switch i32 [[TMP25]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// IR-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// IR-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// IR-NEXT: ] -// IR: .omp.reduction.case1: -// IR-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP26]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE19:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR: omp.arraycpy.body: -// IR-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM4]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// IR-NEXT: [[TMP28:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// IR-NEXT: store i32 [[ADD16]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP26]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_DONE19]], label [[OMP_ARRAYCPY_BODY]] -// IR: omp.arraycpy.done19: -// IR-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) +// IR-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP25]], ptr @.gomp_critical_user_.reduction.var) // IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR: .omp.reduction.case2: -// IR-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY20:%.*]] = icmp eq ptr [[TMP1]], [[TMP29]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY20]], label [[OMP_ARRAYCPY_DONE27:%.*]], label [[OMP_ARRAYCPY_BODY21:%.*]] -// IR: omp.arraycpy.body21: -// IR-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST22:%.*]] = phi ptr [ [[SUM4]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT25:%.*]], [[OMP_ARRAYCPY_BODY21]] ] -// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST23:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY21]] ] -// IR-NEXT: [[TMP30:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST22]], align 4 -// IR-NEXT: [[TMP31:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST23]], i32 [[TMP30]] monotonic, align 4 -// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT24]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST23]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT25]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST22]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_DONE26:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT24]], [[TMP29]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_DONE27]], label [[OMP_ARRAYCPY_BODY21]] -// IR: omp.arraycpy.done27: +// IR-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 +// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY19:%.*]] = icmp eq ptr [[TMP1]], [[TMP30]] +// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY19]], label [[OMP_ARRAYCPY_DONE26:%.*]], label [[OMP_ARRAYCPY_BODY20:%.*]] +// IR: omp.arraycpy.body20: +// IR-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST21:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY20]] ] +// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST22:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT23:%.*]], [[OMP_ARRAYCPY_BODY20]] ] +// IR-NEXT: [[TMP31:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], align 4 +// IR-NEXT: [[TMP32:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 [[TMP31]] monotonic, align 4 +// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 +// IR-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT24]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 +// IR-NEXT: [[OMP_ARRAYCPY_DONE25:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT23]], [[TMP30]] +// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE25]], label [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_BODY20]] +// IR: omp.arraycpy.done26: // IR-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR: .omp.reduction.default: -// IR-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// IR-NEXT: br i1 [[TMP33]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// IR: .omp.lastprivate.then: -// IR-NEXT: store i32 10, ptr [[J3]], align 4 -// IR-NEXT: [[TMP34:%.*]] = load i32, ptr [[J3]], align 4 -// IR-NEXT: store i32 [[TMP34]], ptr [[TMP0]], align 4 -// IR-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// IR: .omp.lastprivate.done: -// IR-NEXT: ret void -// -// -// IR-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp_outlined.omp.reduction.reduction_func -// IR-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// IR-NEXT: entry: -// IR-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// IR-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// IR-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// IR-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// IR-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// IR-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// IR-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// IR-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// IR-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// IR-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// IR-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 100 -// IR-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR: omp.arraycpy.body: -// IR-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// IR-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// IR-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] -// IR: omp.arraycpy.done2: // IR-NEXT: ret void // // // IR-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp.reduction.reduction_func -// IR-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { +// IR-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // IR-NEXT: entry: // IR-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // IR-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -402,7 +225,7 @@ int foo() { // IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[J:%.*]] = alloca i32, align 4 // IR-PCH-NEXT: [[SUM:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 2, ptr @_Z3foov.omp_outlined, ptr [[J]], ptr [[SUM]]) +// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 2, ptr @_Z3foov.omp_outlined, ptr [[J]], ptr [[SUM]]) // IR-PCH-NEXT: ret i32 0 // // @@ -469,277 +292,100 @@ int foo() { // IR-PCH-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] // IR-PCH-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // IR-PCH: omp.inner.for.body: -// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// IR-PCH-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// IR-PCH-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 -// IR-PCH-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 4, ptr @_Z3foov.omp_outlined.omp_outlined, i64 [[TMP11]], i64 [[TMP13]], ptr [[J3]], ptr [[SUM1]]) +// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 10 +// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 +// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] +// IR-PCH-NEXT: store i32 [[ADD]], ptr [[I]], align 4 +// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[DIV6:%.*]] = sdiv i32 [[TMP12]], 10 +// IR-PCH-NEXT: [[MUL7:%.*]] = mul nsw i32 [[DIV6]], 10 +// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL7]] +// IR-PCH-NEXT: [[MUL8:%.*]] = mul nsw i32 [[SUB]], 1 +// IR-PCH-NEXT: [[ADD9:%.*]] = add nsw i32 0, [[MUL8]] +// IR-PCH-NEXT: store i32 [[ADD9]], ptr [[J3]], align 4 +// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 +// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 +// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM1]], i64 0, i64 [[IDXPROM]] +// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[J3]], align 4 +// IR-PCH-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP15]] to i64 +// IR-PCH-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM10]] +// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 +// IR-PCH-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP16]], [[TMP13]] +// IR-PCH-NEXT: store i32 [[ADD12]], ptr [[ARRAYIDX11]], align 4 +// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] +// IR-PCH: omp.body.continue: // IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // IR-PCH: omp.inner.for.inc: -// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// IR-PCH-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// IR-PCH-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], 1 +// IR-PCH-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4 // IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]] // IR-PCH: omp.inner.for.end: // IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // IR-PCH: omp.loop.exit: -// IR-PCH-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP17]]) -// IR-PCH-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 -// IR-PCH-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] +// IR-PCH-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 +// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]]) +// IR-PCH-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 +// IR-PCH-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 +// IR-PCH-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] // IR-PCH: .omp.lastprivate.then: // IR-PCH-NEXT: store i32 10, ptr [[J3]], align 4 -// IR-PCH-NEXT: [[TMP20:%.*]] = load i32, ptr [[J3]], align 4 -// IR-PCH-NEXT: store i32 [[TMP20]], ptr [[TMP0]], align 4 +// IR-PCH-NEXT: [[TMP22:%.*]] = load i32, ptr [[J3]], align 4 +// IR-PCH-NEXT: store i32 [[TMP22]], ptr [[TMP0]], align 4 // IR-PCH-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] // IR-PCH: .omp.lastprivate.done: -// IR-PCH-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// IR-PCH-NEXT: store ptr [[SUM1]], ptr [[TMP21]], align 8 -// IR-PCH-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4 -// IR-PCH-NEXT: [[TMP24:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP23]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z3foov.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-NEXT: switch i32 [[TMP24]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// IR-PCH-NEXT: [[TMP23:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// IR-PCH-NEXT: store ptr [[SUM1]], ptr [[TMP23]], align 8 +// IR-PCH-NEXT: [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// IR-PCH-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4 +// IR-PCH-NEXT: [[TMP26:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP25]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z3foov.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// IR-PCH-NEXT: switch i32 [[TMP26]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // IR-PCH-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // IR-PCH-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // IR-PCH-NEXT: ] // IR-PCH: .omp.reduction.case1: -// IR-PCH-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP25]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] +// IR-PCH-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP27]] +// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE18:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] // IR-PCH: omp.arraycpy.body: // IR-PCH-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST6:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT8:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-NEXT: [[TMP26:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], align 4 -// IR-PCH-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP26]], [[TMP27]] -// IR-PCH-NEXT: store i32 [[ADD7]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], align 4 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT8]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST6]], i32 1 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY]] ] +// IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], align 4 +// IR-PCH-NEXT: [[TMP29:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 +// IR-PCH-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] +// IR-PCH-NEXT: store i32 [[ADD15]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], align 4 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT16]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 // IR-PCH-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE9:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT8]], [[TMP25]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH: omp.arraycpy.done10: -// IR-PCH-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP23]], ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR-PCH: .omp.reduction.case2: -// IR-PCH-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY11:%.*]] = icmp eq ptr [[TMP1]], [[TMP28]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY11]], label [[OMP_ARRAYCPY_DONE18:%.*]], label [[OMP_ARRAYCPY_BODY12:%.*]] -// IR-PCH: omp.arraycpy.body12: -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST13:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT16:%.*]], [[OMP_ARRAYCPY_BODY12]] ] -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST14:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT15:%.*]], [[OMP_ARRAYCPY_BODY12]] ] -// IR-PCH-NEXT: [[TMP29:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], align 4 -// IR-PCH-NEXT: [[TMP30:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 [[TMP29]] monotonic, align 4 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT15]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST14]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT16]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST13]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT15]], [[TMP28]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY12]] +// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE17:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT16]], [[TMP27]] +// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE17]], label [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_BODY]] // IR-PCH: omp.arraycpy.done18: -// IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// IR-PCH: .omp.reduction.default: -// IR-PCH-NEXT: ret void -// -// -// IR-PCH-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp_outlined -// IR-PCH-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[J:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[SUM:%.*]]) #[[ATTR1]] { -// IR-PCH-NEXT: entry: -// IR-PCH-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// IR-PCH-NEXT: [[J_ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-NEXT: [[SUM_ADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[J3:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[SUM4:%.*]] = alloca [10 x [10 x i32]], align 16 -// IR-PCH-NEXT: [[I:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[J5:%.*]] = alloca i32, align 4 -// IR-PCH-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// IR-PCH-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// IR-PCH-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// IR-PCH-NEXT: store ptr [[J]], ptr [[J_ADDR]], align 8 -// IR-PCH-NEXT: store ptr [[SUM]], ptr [[SUM_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP0:%.*]] = load ptr, ptr [[J_ADDR]], align 8 -// IR-PCH-NEXT: [[TMP1:%.*]] = load ptr, ptr [[SUM_ADDR]], align 8 -// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// IR-PCH-NEXT: store i32 99, ptr [[DOTOMP_UB]], align 4 -// IR-PCH-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// IR-PCH-NEXT: [[CONV:%.*]] = trunc i64 [[TMP2]] to i32 -// IR-PCH-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// IR-PCH-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP3]] to i32 -// IR-PCH-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// IR-PCH-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// IR-PCH-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// IR-PCH-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4]], i32 0, i32 0, i32 0 -// IR-PCH-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i64 100 -// IR-PCH-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYINIT_ISEMPTY]], label [[OMP_ARRAYINIT_DONE:%.*]], label [[OMP_ARRAYINIT_BODY:%.*]] -// IR-PCH: omp.arrayinit.body: -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYINIT_BODY]] ] -// IR-PCH-NEXT: store i32 0, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP4]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYINIT_DONE]], label [[OMP_ARRAYINIT_BODY]] -// IR-PCH: omp.arrayinit.done: -// IR-PCH-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 -// IR-PCH-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// IR-PCH-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// IR-PCH-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 99 -// IR-PCH-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// IR-PCH: cond.true: -// IR-PCH-NEXT: br label [[COND_END:%.*]] -// IR-PCH: cond.false: -// IR-PCH-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// IR-PCH-NEXT: br label [[COND_END]] -// IR-PCH: cond.end: -// IR-PCH-NEXT: [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] -// IR-PCH-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// IR-PCH-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4 -// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// IR-PCH: omp.inner.for.cond: -// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] -// IR-PCH-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]] -// IR-PCH-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// IR-PCH: omp.inner.for.body: -// IR-PCH-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP12]], 10 -// IR-PCH-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 -// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] -// IR-PCH-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[DIV7:%.*]] = sdiv i32 [[TMP14]], 10 -// IR-PCH-NEXT: [[MUL8:%.*]] = mul nsw i32 [[DIV7]], 10 -// IR-PCH-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP13]], [[MUL8]] -// IR-PCH-NEXT: [[MUL9:%.*]] = mul nsw i32 [[SUB]], 1 -// IR-PCH-NEXT: [[ADD10:%.*]] = add nsw i32 0, [[MUL9]] -// IR-PCH-NEXT: store i32 [[ADD10]], ptr [[J3]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// IR-PCH-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[SUM4]], i64 0, i64 [[IDXPROM]] -// IR-PCH-NEXT: [[TMP17:%.*]] = load i32, ptr [[J3]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// IR-PCH-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] -// IR-PCH-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP18]], [[TMP15]] -// IR-PCH-NEXT: store i32 [[ADD13]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] -// IR-PCH: omp.body.continue: -// IR-PCH-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// IR-PCH: omp.inner.for.inc: -// IR-PCH-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP19]], 1 -// IR-PCH-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] -// IR-PCH-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] -// IR-PCH: omp.inner.for.end: -// IR-PCH-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// IR-PCH: omp.loop.exit: -// IR-PCH-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 -// IR-PCH-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP21]]) -// IR-PCH-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// IR-PCH-NEXT: store ptr [[SUM4]], ptr [[TMP22]], align 8 -// IR-PCH-NEXT: [[TMP23:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// IR-PCH-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4 -// IR-PCH-NEXT: [[TMP25:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP24]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @_Z3foov.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// IR-PCH-NEXT: switch i32 [[TMP25]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// IR-PCH-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// IR-PCH-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// IR-PCH-NEXT: ] -// IR-PCH: .omp.reduction.case1: -// IR-PCH-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP1]], [[TMP26]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE19:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR-PCH: omp.arraycpy.body: -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[SUM4]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST15:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE1]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT17:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-NEXT: [[TMP27:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// IR-PCH-NEXT: [[TMP28:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP27]], [[TMP28]] -// IR-PCH-NEXT: store i32 [[ADD16]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], align 4 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT17]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST15]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE18:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT17]], [[TMP26]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE18]], label [[OMP_ARRAYCPY_DONE19]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH: omp.arraycpy.done19: -// IR-PCH-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP24]], ptr @.gomp_critical_user_.reduction.var) +// IR-PCH-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP25]], ptr @.gomp_critical_user_.reduction.var) // IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR-PCH: .omp.reduction.case2: -// IR-PCH-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY20:%.*]] = icmp eq ptr [[TMP1]], [[TMP29]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY20]], label [[OMP_ARRAYCPY_DONE27:%.*]], label [[OMP_ARRAYCPY_BODY21:%.*]] -// IR-PCH: omp.arraycpy.body21: -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST22:%.*]] = phi ptr [ [[SUM4]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT25:%.*]], [[OMP_ARRAYCPY_BODY21]] ] -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST23:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY21]] ] -// IR-PCH-NEXT: [[TMP30:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST22]], align 4 -// IR-PCH-NEXT: [[TMP31:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST23]], i32 [[TMP30]] monotonic, align 4 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT24]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST23]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT25]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST22]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE26:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT24]], [[TMP29]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_DONE27]], label [[OMP_ARRAYCPY_BODY21]] -// IR-PCH: omp.arraycpy.done27: +// IR-PCH-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP1]], i64 100 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY19:%.*]] = icmp eq ptr [[TMP1]], [[TMP30]] +// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY19]], label [[OMP_ARRAYCPY_DONE26:%.*]], label [[OMP_ARRAYCPY_BODY20:%.*]] +// IR-PCH: omp.arraycpy.body20: +// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST21:%.*]] = phi ptr [ [[SUM1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT24:%.*]], [[OMP_ARRAYCPY_BODY20]] ] +// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST22:%.*]] = phi ptr [ [[TMP1]], [[DOTOMP_REDUCTION_CASE2]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT23:%.*]], [[OMP_ARRAYCPY_BODY20]] ] +// IR-PCH-NEXT: [[TMP31:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], align 4 +// IR-PCH-NEXT: [[TMP32:%.*]] = atomicrmw add ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 [[TMP31]] monotonic, align 4 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT23]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST22]], i32 1 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT24]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST21]], i32 1 +// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE25:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT23]], [[TMP30]] +// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE25]], label [[OMP_ARRAYCPY_DONE26]], label [[OMP_ARRAYCPY_BODY20]] +// IR-PCH: omp.arraycpy.done26: // IR-PCH-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // IR-PCH: .omp.reduction.default: -// IR-PCH-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4 -// IR-PCH-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 -// IR-PCH-NEXT: br i1 [[TMP33]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]] -// IR-PCH: .omp.lastprivate.then: -// IR-PCH-NEXT: store i32 10, ptr [[J3]], align 4 -// IR-PCH-NEXT: [[TMP34:%.*]] = load i32, ptr [[J3]], align 4 -// IR-PCH-NEXT: store i32 [[TMP34]], ptr [[TMP0]], align 4 -// IR-PCH-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]] -// IR-PCH: .omp.lastprivate.done: -// IR-PCH-NEXT: ret void -// -// -// IR-PCH-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp_outlined.omp.reduction.reduction_func -// IR-PCH-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// IR-PCH-NEXT: entry: -// IR-PCH-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// IR-PCH-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// IR-PCH-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// IR-PCH-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// IR-PCH-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// IR-PCH-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// IR-PCH-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// IR-PCH-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// IR-PCH-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// IR-PCH-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// IR-PCH-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i64 100 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[TMP7]], [[TMP8]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE2:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] -// IR-PCH: omp.arraycpy.body: -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[TMP7]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] -// IR-PCH-NEXT: [[TMP9:%.*]] = load i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-NEXT: [[TMP10:%.*]] = load i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], align 4 -// IR-PCH-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// IR-PCH-NEXT: store i32 [[ADD]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], align 4 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr i32, ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 -// IR-PCH-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]] -// IR-PCH-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE2]], label [[OMP_ARRAYCPY_BODY]] -// IR-PCH: omp.arraycpy.done2: // IR-PCH-NEXT: ret void // // // IR-PCH-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp.reduction.reduction_func -// IR-PCH-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { +// IR-PCH-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // IR-PCH-NEXT: entry: // IR-PCH-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // IR-PCH-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 diff --git a/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp index c0c04986f147..901b6552a22b 100644 --- a/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_collapse_codegen.cpp @@ -157,7 +157,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -177,7 +177,7 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]]) // CHECK1-NEXT: ret void // // @@ -227,114 +227,39 @@ int main (int argc, char **argv) { // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[TMP0]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 +// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 456 -// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 456 -// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] -// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[J]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 +// CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 +// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 +// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK1-NEXT: ret void // // @@ -393,7 +318,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -413,7 +338,7 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]]) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]]) // CHECK3-NEXT: ret void // // @@ -463,108 +388,37 @@ int main (int argc, char **argv) { // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[TMP0]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 56087 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 456 +// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 456 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456 -// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] +// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP13]] -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK3-NEXT: ret void // // @@ -693,7 +547,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP47]], align 4 // CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK9-NEXT: store i32 0, ptr [[TMP48]], align 4 -// CHECK9-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]]) +// CHECK9-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]]) // CHECK9-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 // CHECK9-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: @@ -725,7 +579,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]]) // CHECK9-NEXT: ret void // // @@ -820,178 +674,58 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined.omp_outlined, i64 [[TMP21]], i64 [[TMP22]], ptr [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], i64 [[TMP3]], ptr [[TMP4]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP23]], [[TMP24]] -// CHECK9-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]]) -// CHECK9-NEXT: br label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.end: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 8 -// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK9-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[J]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK9: land.lhs.true: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK9: omp.precond.then: -// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP13]], ptr [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK9-NEXT: store i64 [[TMP20]], ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] -// CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP24]], 0 +// CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] // CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 -// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP23]], [[CONV18]] +// CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 // CHECK9-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4 -// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP27]], 0 +// CHECK9-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 -// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP26]], [[CONV25]] -// CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP28]], 0 +// CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] +// CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] // CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] -// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP25]], [[MUL31]] +// CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 // CHECK9-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4 -// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[I11]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP29]] to i64 -// CHECK9-NEXT: [[TMP30:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP30]] -// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[J12]], align 4 -// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 +// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[I11]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP27]] to i64 +// CHECK9-NEXT: [[TMP28:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP28]] +// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[J12]], align 4 +// CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP29]] to i64 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM36]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX37]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP32]], 1 +// CHECK9-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP30]], 1 // CHECK9-NEXT: store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP34]]) +// CHECK9-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK9-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 +// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP32]]) // CHECK9-NEXT: br label [[OMP_PRECOND_END]] // CHECK9: omp.precond.end: // CHECK9-NEXT: ret void @@ -1043,7 +777,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]]) +// CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]]) // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK9: omp_offload.failed: @@ -1059,7 +793,7 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]]) // CHECK9-NEXT: ret void // // @@ -1109,113 +843,38 @@ int main (int argc, char **argv) { // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[TMP0]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP12]], 2 -// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 2 -// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL5]] -// CHECK9-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1 -// CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]] -// CHECK9-NEXT: store i32 [[ADD7]], ptr [[J]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 +// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] +// CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 +// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] +// CHECK9-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] -// CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 +// CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 +// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK9-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK9-NEXT: ret void // // @@ -1343,7 +1002,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK11-NEXT: store i32 0, ptr [[TMP47]], align 4 -// CHECK11-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]]) +// CHECK11-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.region_id, ptr [[KERNEL_ARGS]]) // CHECK11-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0 // CHECK11-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: @@ -1375,7 +1034,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined, ptr [[N_ADDR]], ptr [[M_ADDR]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]]) // CHECK11-NEXT: ret void // // @@ -1470,180 +1129,56 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32 -// CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined.omp_outlined, i32 [[TMP22]], i32 [[TMP24]], ptr [[TMP0]], ptr [[TMP1]], i32 [[TMP2]], i32 [[TMP3]], ptr [[TMP4]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP25]], [[TMP26]] -// CHECK11-NEXT: store i64 [[ADD]], ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP28]]) -// CHECK11-NEXT: br label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.end: -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l83.omp_outlined.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[M_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I13:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J14:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store ptr [[N]], ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: store ptr [[M]], ptr [[M_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[N_ADDR]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[M_ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP1]], align 4 -// CHECK11-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP7]], 0 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 -// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64 -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP8]], 0 -// CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1 -// CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64 -// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]] -// CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1 -// CHECK11-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i32 0, ptr [[I]], align 4 -// CHECK11-NEXT: store i32 0, ptr [[J]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] -// CHECK11: land.lhs.true: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP10]] -// CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] -// CHECK11: omp.precond.then: -// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[CONV11:%.*]] = zext i32 [[TMP12]] to i64 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: [[CONV12:%.*]] = zext i32 [[TMP13]] to i64 -// CHECK11-NEXT: store i64 [[CONV11]], ptr [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[CONV12]], ptr [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 -// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB2:[0-9]+]], i32 [[TMP15]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1) -// CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: [[CMP15:%.*]] = icmp sgt i64 [[TMP16]], [[TMP17]] -// CHECK11-NEXT: br i1 [[CMP15]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8 -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP18]], [[COND_TRUE]] ], [ [[TMP19]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[TMP20:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8 -// CHECK11-NEXT: store i64 [[TMP20]], ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: // CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8 -// CHECK11-NEXT: [[CMP16:%.*]] = icmp sle i64 [[TMP21]], [[TMP22]] -// CHECK11-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: +// CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP22]], 0 +// CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1 +// CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]] +// CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64 +// CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP21]], [[CONV18]] +// CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1 +// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]] +// CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32 +// CHECK11-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP24]], 0 -// CHECK11-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 -// CHECK11-NEXT: [[MUL19:%.*]] = mul nsw i32 1, [[DIV18]] -// CHECK11-NEXT: [[CONV20:%.*]] = sext i32 [[MUL19]] to i64 -// CHECK11-NEXT: [[DIV21:%.*]] = sdiv i64 [[TMP23]], [[CONV20]] -// CHECK11-NEXT: [[MUL22:%.*]] = mul nsw i64 [[DIV21]], 1 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL22]] -// CHECK11-NEXT: [[CONV23:%.*]] = trunc i64 [[ADD]] to i32 -// CHECK11-NEXT: store i32 [[CONV23]], ptr [[I13]], align 4 -// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP27]], 0 -// CHECK11-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1 -// CHECK11-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]] -// CHECK11-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64 -// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i64 [[TMP26]], [[CONV27]] -// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 -// CHECK11-NEXT: [[SUB29:%.*]] = sub nsw i32 [[TMP28]], 0 -// CHECK11-NEXT: [[DIV30:%.*]] = sdiv i32 [[SUB29]], 1 -// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i32 1, [[DIV30]] -// CHECK11-NEXT: [[CONV32:%.*]] = sext i32 [[MUL31]] to i64 -// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[DIV28]], [[CONV32]] -// CHECK11-NEXT: [[SUB34:%.*]] = sub nsw i64 [[TMP25]], [[MUL33]] -// CHECK11-NEXT: [[MUL35:%.*]] = mul nsw i64 [[SUB34]], 1 -// CHECK11-NEXT: [[ADD36:%.*]] = add nsw i64 0, [[MUL35]] -// CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 -// CHECK11-NEXT: store i32 [[CONV37]], ptr [[J14]], align 4 -// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[I13]], align 4 -// CHECK11-NEXT: [[TMP30:%.*]] = mul nsw i32 [[TMP29]], [[TMP3]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 [[TMP30]] -// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[J14]], align 4 -// CHECK11-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP31]] -// CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX38]], align 4 +// CHECK11-NEXT: [[TMP24:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP25]], 0 +// CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1 +// CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]] +// CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64 +// CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP24]], [[CONV25]] +// CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4 +// CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP26]], 0 +// CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1 +// CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]] +// CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64 +// CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]] +// CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP23]], [[MUL31]] +// CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1 +// CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]] +// CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32 +// CHECK11-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4 +// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[I11]], align 4 +// CHECK11-NEXT: [[TMP28:%.*]] = mul nsw i32 [[TMP27]], [[TMP3]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i32 [[TMP28]] +// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[J12]], align 4 +// CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP29]] +// CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX36]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 -// CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[TMP32]], 1 -// CHECK11-NEXT: store i64 [[ADD39]], ptr [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8 +// CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP30]], 1 +// CHECK11-NEXT: store i64 [[ADD37]], ptr [[DOTOMP_IV]], align 8 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: [[TMP33:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP33]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP34]]) +// CHECK11-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4 +// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP32]]) // CHECK11-NEXT: br label [[OMP_PRECOND_END]] // CHECK11: omp.precond.end: // CHECK11-NEXT: ret void @@ -1695,7 +1230,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4 -// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]]) +// CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.region_id, ptr [[KERNEL_ARGS]]) // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 // CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK11: omp_offload.failed: @@ -1711,7 +1246,7 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]]) +// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined, ptr [[TMP0]]) // CHECK11-NEXT: ret void // // @@ -1761,106 +1296,35 @@ int main (int argc, char **argv) { // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[TMP0]]) -// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK11-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK11: omp.inner.for.end: -// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK11-NEXT: ret void -// -// -// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l69.omp_outlined.omp_outlined -// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] { -// CHECK11-NEXT: entry: -// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4 -// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 -// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 19 -// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK11: cond.true: -// CHECK11-NEXT: br label [[COND_END:%.*]] -// CHECK11: cond.false: -// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: br label [[COND_END]] -// CHECK11: cond.end: -// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK11-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK11: omp.inner.for.cond: // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK11: omp.inner.for.body: -// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 2 +// CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP12]], 2 +// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2 -// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL4]] +// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]] // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 -// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP13]] -// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK11: omp.inner.for.inc: -// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK11-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK11: omp.inner.for.end: // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK11: omp.loop.exit: -// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) +// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) // CHECK11-NEXT: ret void // diff --git a/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp index 303bce8c648c..e955db129d1d 100644 --- a/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_private_codegen.cpp @@ -288,7 +288,7 @@ int main() { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -302,7 +302,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) // CHECK1-NEXT: ret void // // @@ -365,149 +365,48 @@ int main() { // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2 -// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done3: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK1-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2 -// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK1: arrayctor.loop: -// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1 -// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK1: omp.inner.for.cond.cleanup: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[SIVAR]], align 4 +// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) +// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done8: +// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] +// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK1: arraydestroy.done7: // CHECK1-NEXT: ret void // // @@ -558,7 +457,7 @@ int main() { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -607,7 +506,7 @@ int main() { // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 // CHECK1-SAME: () #[[ATTR4]] { // CHECK1-NEXT: entry: -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) // CHECK1-NEXT: ret void // // @@ -673,149 +572,45 @@ int main() { // CHECK1: omp.inner.for.cond.cleanup: // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2 -// CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 -// CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done5: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK1-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK1-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK1-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2 -// CHECK1-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK1: arrayctor.loop: -// CHECK1-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK1-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1 -// CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK1: arrayctor.cont: -// CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK1-NEXT: store ptr [[VAR]], ptr [[_TMP3]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK1: omp.inner.for.cond.cleanup: -// CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] -// CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] -// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) +// CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) +// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2 +// CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2 // CHECK1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK1: arraydestroy.body: -// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]] -// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK1: arraydestroy.done9: +// CHECK1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]] +// CHECK1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]] +// CHECK1: arraydestroy.done8: // CHECK1-NEXT: ret void // // @@ -1021,7 +816,7 @@ int main() { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -1035,7 +830,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined) // CHECK3-NEXT: ret void // // @@ -1098,138 +893,41 @@ int main() { // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done3: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l96.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4 -// CHECK3-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK3: omp.inner.for.cond.cleanup: -// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]] +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1 +// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]]) +// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]]) // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 +// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP16]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK3-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]] @@ -1285,7 +983,7 @@ int main() { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -1334,7 +1032,7 @@ int main() { // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56 // CHECK3-SAME: () #[[ATTR4]] { // CHECK3-NEXT: entry: -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined) // CHECK3-NEXT: ret void // // @@ -1400,138 +1098,38 @@ int main() { // CHECK3: omp.inner.for.cond.cleanup: // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]]) -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2 -// CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] -// CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 -// CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] -// CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]] -// CHECK3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]] -// CHECK3: arraydestroy.done5: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[_TMP1:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 -// CHECK3-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 -// CHECK3-NEXT: [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 -// CHECK3-NEXT: [[_TMP2:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr undef, ptr [[_TMP1]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2 -// CHECK3-NEXT: br label [[ARRAYCTOR_LOOP:%.*]] -// CHECK3: arrayctor.loop: -// CHECK3-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ] -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) -// CHECK3-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1 -// CHECK3-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] -// CHECK3-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] -// CHECK3: arrayctor.cont: -// CHECK3-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) -// CHECK3-NEXT: store ptr [[VAR]], ptr [[_TMP2]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] -// CHECK3: omp.inner.for.cond.cleanup: -// CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] -// CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] -// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 +// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]]) +// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4 +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]]) // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 +// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2 // CHECK3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] // CHECK3: arraydestroy.body: -// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] +// CHECK3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] // CHECK3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 // CHECK3-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]] // CHECK3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]] @@ -1726,7 +1324,7 @@ int main() { // CHECK9-NEXT: [[TMP:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8 // CHECK9-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined) // CHECK9-NEXT: ret void // // @@ -1747,6 +1345,7 @@ int main() { // CHECK9-NEXT: [[_TMP2:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 @@ -1778,112 +1377,34 @@ int main() { // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP1:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[G1:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[_TMP3:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[SIVAR:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store ptr undef, ptr [[_TMP1]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store ptr [[G1]], ptr [[_TMP3]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] -// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: store i32 1, ptr [[G]], align 4 -// CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK9-NEXT: store volatile i32 1, ptr [[TMP10]], align 4 +// CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: store volatile i32 1, ptr [[TMP8]], align 4 // CHECK9-NEXT: store i32 2, ptr [[SIVAR]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store ptr [[G]], ptr [[TMP11]], align 8 -// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 -// CHECK9-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8 -// CHECK9-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8 -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 -// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP14]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK9-NEXT: store ptr [[G]], ptr [[TMP9]], align 8 +// CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1 +// CHECK9-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8 +// CHECK9-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8 +// CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2 +// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[TMP12]], align 8 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]]) +// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]]) // CHECK9-NEXT: ret void // // diff --git a/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp b/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp index d80c003c0109..f0067cb93d9b 100644 --- a/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp +++ b/clang/test/OpenMP/teams_generic_loop_reduction_codegen.cpp @@ -141,7 +141,7 @@ int main() { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -157,7 +157,7 @@ int main() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) // CHECK1-NEXT: ret void // // @@ -208,165 +208,50 @@ int main() { // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK1-NEXT: ] -// CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 -// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK1: .omp.reduction.default: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[SIVAR2]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK1-NEXT: ret void -// -// // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 @@ -435,7 +320,7 @@ int main() { // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK1: omp_offload.failed: @@ -450,7 +335,7 @@ int main() { // CHECK1-NEXT: entry: // CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 // CHECK1-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) // CHECK1-NEXT: ret void // // @@ -501,163 +386,48 @@ int main() { // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[T_VAR1]]) -// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK1: omp.inner.for.end: -// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK1-NEXT: ] -// CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 -// CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK1: .omp.reduction.default: -// CHECK1-NEXT: ret void -// -// -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK1-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK1-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: store i32 0, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK1: cond.true: -// CHECK1-NEXT: br label [[COND_END:%.*]] -// CHECK1: cond.false: -// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: br label [[COND_END]] -// CHECK1: cond.end: -// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK1: omp.inner.for.cond: // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK1: omp.inner.for.body: -// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK1-NEXT: store i32 [[ADD4]], ptr [[T_VAR2]], align 4 +// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK1-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK1: omp.inner.for.inc: -// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1 -// CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 +// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK1: omp.inner.for.end: // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK1: omp.loop.exit: -// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP14]], align 8 -// CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK1-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) +// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK1-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 8 +// CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK1-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK1-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK1-NEXT: ] // CHECK1: .omp.reduction.case1: -// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK1-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] +// CHECK1-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 +// CHECK1-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.case2: -// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 +// CHECK1-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 // CHECK1-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK1: .omp.reduction.default: // CHECK1-NEXT: ret void // // -// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func -// CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { -// CHECK1-NEXT: entry: -// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] -// CHECK1-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK1-NEXT: ret void -// -// // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func // CHECK1-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK1-NEXT: entry: @@ -726,7 +496,7 @@ int main() { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -742,7 +512,7 @@ int main() { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined, ptr [[SIVAR_ADDR]]) // CHECK3-NEXT: ret void // // @@ -793,161 +563,50 @@ int main() { // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[SIVAR1]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK3-NEXT: ] -// CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 -// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK3: .omp.reduction.default: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[SIVAR1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] // CHECK3-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[SIVAR1]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp_outlined.omp.reduction.reduction_func -// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 -// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK3-NEXT: ret void -// -// // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68.omp_outlined.omp.reduction.reduction_func -// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { +// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 @@ -1016,7 +675,7 @@ int main() { // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12 // CHECK3-NEXT: store i32 0, ptr [[TMP19]], align 4 -// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB4]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) +// CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]]) // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] // CHECK3: omp_offload.failed: @@ -1031,7 +690,7 @@ int main() { // CHECK3-NEXT: entry: // CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 // CHECK3-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) +// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]]) // CHECK3-NEXT: ret void // // @@ -1082,159 +741,48 @@ int main() { // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined, i32 [[TMP8]], i32 [[TMP9]], ptr [[T_VAR1]]) -// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP10]], [[TMP11]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK3: omp.inner.for.end: -// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 4 -// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK3-NEXT: ] -// CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] -// CHECK3-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 -// CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK3: .omp.reduction.default: -// CHECK3-NEXT: ret void -// -// -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined -// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR_ADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[T_VAR1:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK3-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 4 -// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4 -// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK3-NEXT: store i32 0, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK3: cond.true: -// CHECK3-NEXT: br label [[COND_END:%.*]] -// CHECK3: cond.false: -// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: br label [[COND_END]] -// CHECK3: cond.end: -// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK3: omp.inner.for.cond: // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK3: omp.inner.for.body: -// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] +// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] // CHECK3-NEXT: store i32 [[ADD3]], ptr [[T_VAR1]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK3: omp.inner.for.inc: -// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1 +// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK3: omp.inner.for.end: // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK3: omp.loop.exit: -// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 -// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP14]], align 4 -// CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK3-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) +// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i32 0, i32 0 +// CHECK3-NEXT: store ptr [[T_VAR1]], ptr [[TMP12]], align 4 +// CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], i32 1, i32 4, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: switch i32 [[TMP13]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK3-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK3-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK3-NEXT: ] // CHECK3: .omp.reduction.case1: -// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] +// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]] // CHECK3-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 -// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK3-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.case2: -// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK3-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 +// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR1]], align 4 +// CHECK3-NEXT: [[TMP17:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP16]] monotonic, align 4 // CHECK3-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK3: .omp.reduction.default: // CHECK3-NEXT: ret void // // -// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp_outlined.omp.reduction.reduction_func -// CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { -// CHECK3-NEXT: entry: -// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4 -// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4 -// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4 -// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 4 -// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4 -// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 4 -// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i32 0, i32 0 -// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4 -// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] -// CHECK3-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK3-NEXT: ret void -// -// // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined.omp.reduction.reduction_func // CHECK3-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR3]] { // CHECK3-NEXT: entry: @@ -1270,7 +818,7 @@ int main() { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca i64, align 8 // CHECK9-NEXT: store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB4:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined, ptr [[SIVAR_ADDR]]) +// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined, ptr [[SIVAR_ADDR]]) // CHECK9-NEXT: ret void // // @@ -1288,6 +836,7 @@ int main() { // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 +// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 // CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 @@ -1321,169 +870,53 @@ int main() { // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] // CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], ptr [[SIVAR1]]) -// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] -// CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] -// CHECK9: omp.inner.for.end: -// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] -// CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) -// CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP14]], align 8 -// CHECK9-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP15]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ -// CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] -// CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] -// CHECK9-NEXT: ] -// CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]] -// CHECK9-NEXT: store i32 [[ADD3]], ptr [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR1]], align 4 -// CHECK9-NEXT: [[TMP19:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP18]] monotonic, align 4 -// CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] -// CHECK9: .omp.reduction.default: -// CHECK9-NEXT: ret void -// -// -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined -// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 -// CHECK9-NEXT: [[SIVAR_ADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[SIVAR2:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 -// CHECK9-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 -// CHECK9-NEXT: [[DOTOMP_REDUCTION_RED_LIST:%.*]] = alloca [1 x ptr], align 8 -// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32 -// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8 -// CHECK9-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32 -// CHECK9-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK9-NEXT: store i32 0, ptr [[SIVAR2]], align 4 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4 -// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1) -// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1 -// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] -// CHECK9: cond.true: -// CHECK9-NEXT: br label [[COND_END:%.*]] -// CHECK9: cond.false: -// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: br label [[COND_END]] -// CHECK9: cond.end: -// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] -// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4 -// CHECK9-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] -// CHECK9: omp.inner.for.cond: // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4 -// CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] -// CHECK9: omp.inner.for.body: -// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1 +// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 -// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]] -// CHECK9-NEXT: store i32 [[ADD4]], ptr [[SIVAR2]], align 4 -// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 -// CHECK9-NEXT: store ptr [[SIVAR2]], ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 +// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] +// CHECK9-NEXT: store i32 [[ADD3]], ptr [[SIVAR1]], align 4 +// CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 +// CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP11]], align 8 // CHECK9-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] // CHECK9: omp.inner.for.inc: -// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 -// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1 -// CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4 +// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 +// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] // CHECK9: omp.inner.for.end: // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] // CHECK9: omp.loop.exit: -// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP4]]) -// CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 -// CHECK9-NEXT: store ptr [[SIVAR2]], ptr [[TMP15]], align 8 -// CHECK9-NEXT: [[TMP16:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) -// CHECK9-NEXT: switch i32 [[TMP16]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ +// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]]) +// CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 +// CHECK9-NEXT: store ptr [[SIVAR1]], ptr [[TMP13]], align 8 +// CHECK9-NEXT: [[TMP14:%.*]] = call i32 @__kmpc_reduce_nowait(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]], i32 1, i64 8, ptr [[DOTOMP_REDUCTION_RED_LIST]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp.reduction.reduction_func, ptr @.gomp_critical_user_.reduction.var) +// CHECK9-NEXT: switch i32 [[TMP14]], label [[DOTOMP_REDUCTION_DEFAULT:%.*]] [ // CHECK9-NEXT: i32 1, label [[DOTOMP_REDUCTION_CASE1:%.*]] // CHECK9-NEXT: i32 2, label [[DOTOMP_REDUCTION_CASE2:%.*]] // CHECK9-NEXT: ] // CHECK9: .omp.reduction.case1: -// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP0]], align 4 -// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]] -// CHECK9-NEXT: store i32 [[ADD6]], ptr [[TMP0]], align 4 -// CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB3]], i32 [[TMP4]], ptr @.gomp_critical_user_.reduction.var) +// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP0]], align 4 +// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]] +// CHECK9-NEXT: store i32 [[ADD5]], ptr [[TMP0]], align 4 +// CHECK9-NEXT: call void @__kmpc_end_reduce_nowait(ptr @[[GLOB2]], i32 [[TMP2]], ptr @.gomp_critical_user_.reduction.var) // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK9: .omp.reduction.case2: -// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[SIVAR2]], align 4 -// CHECK9-NEXT: [[TMP20:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP19]] monotonic, align 4 +// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR1]], align 4 +// CHECK9-NEXT: [[TMP18:%.*]] = atomicrmw add ptr [[TMP0]], i32 [[TMP17]] monotonic, align 4 // CHECK9-NEXT: br label [[DOTOMP_REDUCTION_DEFAULT]] // CHECK9: .omp.reduction.default: // CHECK9-NEXT: ret void // // -// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp_outlined.omp.reduction.reduction_func -// CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { -// CHECK9-NEXT: entry: -// CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -// CHECK9-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK9-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8 -// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8 -// CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP3]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 -// CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[TMP2]], i64 0, i64 0 -// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8 -// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4 -// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 -// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP9]] -// CHECK9-NEXT: store i32 [[ADD]], ptr [[TMP7]], align 4 -// CHECK9-NEXT: ret void -// -// // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined.omp.reduction.reduction_func -// CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4]] { +// CHECK9-SAME: (ptr noundef [[TMP0:%.*]], ptr noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] { // CHECK9-NEXT: entry: // CHECK9-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK9-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8 -- GitLab From d347235bddbeba2a72d94ebe9d8f98dc675c3776 Mon Sep 17 00:00:00 2001 From: Christopher Di Bella Date: Wed, 10 Apr 2024 13:15:22 -0700 Subject: [PATCH 450/695] [Flang] responds to Clang Tidy feedback (#87847) Line 267: performance-unnecessary-copy-initialization Line 592: readability-container-size-empty --- clang/lib/Driver/ToolChains/Flang.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 9699443603d3..b00068c8098b 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -264,7 +264,7 @@ static void addVSDefines(const ToolChain &TC, const ArgList &Args, CmdArgs.push_back(Args.MakeArgString("-D_MSC_FULL_VER=" + Twine(ver))); CmdArgs.push_back(Args.MakeArgString("-D_WIN32")); - llvm::Triple triple = TC.getTriple(); + const llvm::Triple &triple = TC.getTriple(); if (triple.isAArch64()) { CmdArgs.push_back("-D_M_ARM64=1"); } else if (triple.isX86() && triple.isArch32Bit()) { @@ -589,7 +589,7 @@ static void addFloatingPointOptions(const Driver &D, const ArgList &Args, if (!HonorINFs && !HonorNaNs && AssociativeMath && ReciprocalMath && ApproxFunc && !SignedZeros && - (FPContract == "fast" || FPContract == "")) { + (FPContract == "fast" || FPContract.empty())) { CmdArgs.push_back("-ffast-math"); return; } -- GitLab From 05093e243859a371f96ffa1c320a4b51579c3da7 Mon Sep 17 00:00:00 2001 From: Farzon Lotfi <1802579+farzonl@users.noreply.github.com> Date: Wed, 10 Apr 2024 16:27:44 -0400 Subject: [PATCH 451/695] [Spirv][HLSL] Add OpAll lowering and float vec support (#87952) The main point of this change was to add support for HLSL's all intrinsic. In the process of doing that I found a few issues around creating an `OpConstantComposite` via `buildZerosVal`. First the current code didn't support floats so the process of adding `buildZerosValF` meant I needed a float version of `getOrCreateIntConstVector`. After doing so I renamed both versions to `getOrCreateConstVector`. That meant I needed to create a float type version of `getOrCreateIntCompositeOrNull`. Luckily the type information was low for this function so was able to split it out into a helpwe and rename `getOrCreateIntCompositeOrNull` to `getOrCreateCompositeOrNull` With the exception of type handling differences of the code and Null vs 0 Constant Op codes these functions should be identical. To handle scalar floats I could not use `buildConstantFP` like this PR did: https://github.com/llvm/llvm-project/commit/0a2aaab5aba46#diff-733a189c5a8c3211f3a04fd6e719952a3fa231eadd8a7f11e6ecf1e584d57411R1603 because that would create too many superfluous registers (that causes problems in the validator), I had to create a float version of `getOrCreateConstInt` which I called `getOrCreateConstFP`. similar problems with doing it like this: https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp#L1540. `buildZerosValF` also has a use of a function `getZeroFP`. This is because half, float, and double scalar values of 0 would collide in `SPIRVDuplicatesTracker CT` if you use `APFloat(0.0f)`. `getORCreateConstFP` needed its own version of `getOrCreateConstIntReg` which I called `getOrCreateConstFloatReg` The one difference in this function is `getOrCreateConstFloatReg` returns a bit width so we don't have to call `getScalarOrVectorBitWidth` twice ie when it is used again in `getOrCreateConstFP` for `OpConstantF` `addNumImm`. `getOrCreateConstFloatReg` needed an `assignFloatTypeToVReg` helper which called a `getOrCreateSPIRVFloatType` helper. There was no equivalent IntegerType::get for floats so I handled this with a switch statement on bit widths to get the right LLVM float type. Finally, there is the use of `bool ZeroAsNull = STI.isOpenCLEnv();` This is partly a cosmetic change. When Zeros are treated as nulls, we don't create `OpConstantComposite` vectors which is something we do in the DXCs SPIRV backend. The DXC SPIRV backend also does not use `OpConstantNull`. Finally, I needed a means to test the behavior of the OpConstantNull and `OpConstantComposite` changes and this was one way I could do that via the same tests. --- llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 218 +++++++++++++++--- llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 42 +++- .../Target/SPIRV/SPIRVInstructionSelector.cpp | 98 +++++++- .../test/CodeGen/SPIRV/hlsl-intrinsics/all.ll | 187 +++++++++++++++ 4 files changed, 506 insertions(+), 39 deletions(-) create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp index 9592f3e81b40..70197e948c65 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp @@ -20,7 +20,12 @@ #include "SPIRVSubtarget.h" #include "SPIRVTargetMachine.h" #include "SPIRVUtils.h" +#include "llvm/ADT/APInt.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/Type.h" #include "llvm/IR/TypedPointerType.h" +#include "llvm/Support/Casting.h" +#include using namespace llvm; SPIRVGlobalRegistry::SPIRVGlobalRegistry(unsigned PointerSize) @@ -35,6 +40,15 @@ SPIRVType *SPIRVGlobalRegistry::assignIntTypeToVReg(unsigned BitWidth, return SpirvType; } +SPIRVType * +SPIRVGlobalRegistry::assignFloatTypeToVReg(unsigned BitWidth, Register VReg, + MachineInstr &I, + const SPIRVInstrInfo &TII) { + SPIRVType *SpirvType = getOrCreateSPIRVFloatType(BitWidth, I, TII); + assignSPIRVTypeToVReg(SpirvType, VReg, *CurMF); + return SpirvType; +} + SPIRVType *SPIRVGlobalRegistry::assignVectTypeToVReg( SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII) { @@ -151,6 +165,8 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType, Register Res = DT.find(CI, CurMF); if (!Res.isValid()) { unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32; + // TODO: handle cases where the type is not 32bit wide + // TODO: https://github.com/llvm/llvm-project/issues/88129 LLT LLTy = LLT::scalar(32); Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); @@ -164,9 +180,83 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType, return std::make_tuple(Res, CI, NewInstr); } +std::tuple +SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType, + MachineIRBuilder *MIRBuilder, + MachineInstr *I, + const SPIRVInstrInfo *TII) { + const Type *LLVMFloatTy; + LLVMContext &Ctx = CurMF->getFunction().getContext(); + unsigned BitWidth = 32; + if (SpvType) + LLVMFloatTy = getTypeForSPIRVType(SpvType); + else { + LLVMFloatTy = Type::getFloatTy(Ctx); + if (MIRBuilder) + SpvType = getOrCreateSPIRVType(LLVMFloatTy, *MIRBuilder); + } + bool NewInstr = false; + // Find a constant in DT or build a new one. + auto *const CI = ConstantFP::get(Ctx, Val); + Register Res = DT.find(CI, CurMF); + if (!Res.isValid()) { + if (SpvType) + BitWidth = getScalarOrVectorBitWidth(SpvType); + // TODO: handle cases where the type is not 32bit wide + // TODO: https://github.com/llvm/llvm-project/issues/88129 + LLT LLTy = LLT::scalar(32); + Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); + CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass); + if (MIRBuilder) + assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder); + else + assignFloatTypeToVReg(BitWidth, Res, *I, *TII); + DT.add(CI, CurMF, Res); + NewInstr = true; + } + return std::make_tuple(Res, CI, NewInstr, BitWidth); +} + +Register SPIRVGlobalRegistry::getOrCreateConstFP(APFloat Val, MachineInstr &I, + SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull) { + assert(SpvType); + ConstantFP *CI; + Register Res; + bool New; + unsigned BitWidth; + std::tie(Res, CI, New, BitWidth) = + getOrCreateConstFloatReg(Val, SpvType, nullptr, &I, &TII); + // If we have found Res register which is defined by the passed G_CONSTANT + // machine instruction, a new constant instruction should be created. + if (!New && (!I.getOperand(0).isReg() || Res != I.getOperand(0).getReg())) + return Res; + MachineInstrBuilder MIB; + MachineBasicBlock &BB = *I.getParent(); + // In OpenCL OpConstantNull - Scalar floating point: +0.0 (all bits 0) + if (Val.isPosZero() && ZeroAsNull) { + MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) + .addDef(Res) + .addUse(getSPIRVTypeID(SpvType)); + } else { + MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantF)) + .addDef(Res) + .addUse(getSPIRVTypeID(SpvType)); + addNumImm( + APInt(BitWidth, CI->getValueAPF().bitcastToAPInt().getZExtValue()), + MIB); + } + const auto &ST = CurMF->getSubtarget(); + constrainSelectedInstRegOperands(*MIB, *ST.getInstrInfo(), + *ST.getRegisterInfo(), *ST.getRegBankInfo()); + return Res; +} + Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, - const SPIRVInstrInfo &TII) { + const SPIRVInstrInfo &TII, + bool ZeroAsNull) { assert(SpvType); ConstantInt *CI; Register Res; @@ -179,7 +269,7 @@ Register SPIRVGlobalRegistry::getOrCreateConstInt(uint64_t Val, MachineInstr &I, return Res; MachineInstrBuilder MIB; MachineBasicBlock &BB = *I.getParent(); - if (Val) { + if (Val || !ZeroAsNull) { MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) .addDef(Res) .addUse(getSPIRVTypeID(SpvType)); @@ -270,21 +360,46 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val, return Res; } -Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( - uint64_t Val, MachineInstr &I, SPIRVType *SpvType, +Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val, + MachineInstr &I, + SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + unsigned BitWidth) { + SPIRVType *Type = SpvType; + if (SpvType->getOpcode() == SPIRV::OpTypeVector || + SpvType->getOpcode() == SPIRV::OpTypeArray) { + auto EleTypeReg = SpvType->getOperand(1).getReg(); + Type = getSPIRVTypeForVReg(EleTypeReg); + } + if (Type->getOpcode() == SPIRV::OpTypeFloat) { + SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII); + return getOrCreateConstFP(dyn_cast(Val)->getValue(), I, + SpvBaseType, TII); + } + assert(Type->getOpcode() == SPIRV::OpTypeInt); + SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII); + return getOrCreateConstInt(Val->getUniqueInteger().getSExtValue(), I, + SpvBaseType, TII); +} + +Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull( + Constant *Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII, Constant *CA, unsigned BitWidth, - unsigned ElemCnt) { + unsigned ElemCnt, bool ZeroAsNull) { // Find a constant vector in DT or build a new one. Register Res = DT.find(CA, CurMF); + // If no values are attached, the composite is null constant. + bool IsNull = Val->isNullValue() && ZeroAsNull; if (!Res.isValid()) { - SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII); // SpvScalConst should be created before SpvVecConst to avoid undefined ID // error on validation. // TODO: can moved below once sorting of types/consts/defs is implemented. Register SpvScalConst; - if (Val) - SpvScalConst = getOrCreateConstInt(Val, I, SpvBaseType, TII); - // TODO: maybe use bitwidth of base type. + if (!IsNull) + SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth); + + // TODO: handle cases where the type is not 32bit wide + // TODO: https://github.com/llvm/llvm-project/issues/88129 LLT LLTy = LLT::scalar(32); Register SpvVecConst = CurMF->getRegInfo().createGenericVirtualRegister(LLTy); @@ -293,7 +408,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( DT.add(CA, CurMF, SpvVecConst); MachineInstrBuilder MIB; MachineBasicBlock &BB = *I.getParent(); - if (Val) { + if (!IsNull) { MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantComposite)) .addDef(SpvVecConst) .addUse(getSPIRVTypeID(SpvType)); @@ -313,20 +428,42 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( return Res; } -Register -SPIRVGlobalRegistry::getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, - SPIRVType *SpvType, - const SPIRVInstrInfo &TII) { +Register SPIRVGlobalRegistry::getOrCreateConstVector(uint64_t Val, + MachineInstr &I, + SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull) { const Type *LLVMTy = getTypeForSPIRVType(SpvType); assert(LLVMTy->isVectorTy()); const FixedVectorType *LLVMVecTy = cast(LLVMTy); Type *LLVMBaseTy = LLVMVecTy->getElementType(); - const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val); - auto ConstVec = - ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstInt); + assert(LLVMBaseTy->isIntegerTy()); + auto *ConstVal = ConstantInt::get(LLVMBaseTy, Val); + auto *ConstVec = + ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstVal); unsigned BW = getScalarOrVectorBitWidth(SpvType); - return getOrCreateIntCompositeOrNull(Val, I, SpvType, TII, ConstVec, BW, - SpvType->getOperand(2).getImm()); + return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW, + SpvType->getOperand(2).getImm(), + ZeroAsNull); +} + +Register SPIRVGlobalRegistry::getOrCreateConstVector(APFloat Val, + MachineInstr &I, + SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull) { + const Type *LLVMTy = getTypeForSPIRVType(SpvType); + assert(LLVMTy->isVectorTy()); + const FixedVectorType *LLVMVecTy = cast(LLVMTy); + Type *LLVMBaseTy = LLVMVecTy->getElementType(); + assert(LLVMBaseTy->isFloatingPointTy()); + auto *ConstVal = ConstantFP::get(LLVMBaseTy, Val); + auto *ConstVec = + ConstantVector::getSplat(LLVMVecTy->getElementCount(), ConstVal); + unsigned BW = getScalarOrVectorBitWidth(SpvType); + return getOrCreateCompositeOrNull(ConstVal, I, SpvType, TII, ConstVec, BW, + SpvType->getOperand(2).getImm(), + ZeroAsNull); } Register @@ -337,13 +474,13 @@ SPIRVGlobalRegistry::getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, assert(LLVMTy->isArrayTy()); const ArrayType *LLVMArrTy = cast(LLVMTy); Type *LLVMBaseTy = LLVMArrTy->getElementType(); - const auto ConstInt = ConstantInt::get(LLVMBaseTy, Val); - auto ConstArr = + auto *ConstInt = ConstantInt::get(LLVMBaseTy, Val); + auto *ConstArr = ConstantArray::get(const_cast(LLVMArrTy), {ConstInt}); SPIRVType *SpvBaseTy = getSPIRVTypeForVReg(SpvType->getOperand(1).getReg()); unsigned BW = getScalarOrVectorBitWidth(SpvBaseTy); - return getOrCreateIntCompositeOrNull(Val, I, SpvType, TII, ConstArr, BW, - LLVMArrTy->getNumElements()); + return getOrCreateCompositeOrNull(ConstInt, I, SpvType, TII, ConstArr, BW, + LLVMArrTy->getNumElements()); } Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull( @@ -1093,14 +1230,16 @@ SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy, return SpirvType; } -SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType( - unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) { - Type *LLVMTy = IntegerType::get(CurMF->getFunction().getContext(), BitWidth); +SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(unsigned BitWidth, + MachineInstr &I, + const SPIRVInstrInfo &TII, + unsigned SPIRVOPcode, + Type *LLVMTy) { Register Reg = DT.find(LLVMTy, CurMF); if (Reg.isValid()) return getSPIRVTypeForVReg(Reg); MachineBasicBlock &BB = *I.getParent(); - auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeInt)) + auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRVOPcode)) .addDef(createTypeVReg(CurMF->getRegInfo())) .addImm(BitWidth) .addImm(0); @@ -1108,6 +1247,31 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType( return finishCreatingSPIRVType(LLVMTy, MIB); } +SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType( + unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) { + Type *LLVMTy = IntegerType::get(CurMF->getFunction().getContext(), BitWidth); + return getOrCreateSPIRVType(BitWidth, I, TII, SPIRV::OpTypeInt, LLVMTy); +} +SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVFloatType( + unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII) { + LLVMContext &Ctx = CurMF->getFunction().getContext(); + Type *LLVMTy; + switch (BitWidth) { + case 16: + LLVMTy = Type::getHalfTy(Ctx); + break; + case 32: + LLVMTy = Type::getFloatTy(Ctx); + break; + case 64: + LLVMTy = Type::getDoubleTy(Ctx); + break; + default: + llvm_unreachable("Bit width is of unexpected size."); + } + return getOrCreateSPIRVType(BitWidth, I, TII, SPIRV::OpTypeFloat, LLVMTy); +} + SPIRVType * SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder) { return getOrCreateSPIRVType( diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h index 37f575e884ef..2e3e69456ac2 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h +++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h @@ -20,6 +20,7 @@ #include "SPIRVDuplicatesTracker.h" #include "SPIRVInstrInfo.h" #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/IR/Constant.h" namespace llvm { using SPIRVType = const MachineInstr; @@ -234,6 +235,8 @@ public: bool EmitIR = true); SPIRVType *assignIntTypeToVReg(unsigned BitWidth, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII); + SPIRVType *assignFloatTypeToVReg(unsigned BitWidth, Register VReg, + MachineInstr &I, const SPIRVInstrInfo &TII); SPIRVType *assignVectTypeToVReg(SPIRVType *BaseType, unsigned NumElements, Register VReg, MachineInstr &I, const SPIRVInstrInfo &TII); @@ -372,12 +375,20 @@ private: std::tuple getOrCreateConstIntReg( uint64_t Val, SPIRVType *SpvType, MachineIRBuilder *MIRBuilder, MachineInstr *I = nullptr, const SPIRVInstrInfo *TII = nullptr); + std::tuple getOrCreateConstFloatReg( + APFloat Val, SPIRVType *SpvType, MachineIRBuilder *MIRBuilder, + MachineInstr *I = nullptr, const SPIRVInstrInfo *TII = nullptr); SPIRVType *finishCreatingSPIRVType(const Type *LLVMTy, SPIRVType *SpirvType); - Register getOrCreateIntCompositeOrNull(uint64_t Val, MachineInstr &I, - SPIRVType *SpvType, - const SPIRVInstrInfo &TII, - Constant *CA, unsigned BitWidth, - unsigned ElemCnt); + Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I, + SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + unsigned BitWidth); + Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I, + SPIRVType *SpvType, + const SPIRVInstrInfo &TII, Constant *CA, + unsigned BitWidth, unsigned ElemCnt, + bool ZeroAsNull = true); + Register getOrCreateIntCompositeOrNull(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType, bool EmitIR, @@ -388,12 +399,20 @@ public: Register buildConstantInt(uint64_t Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType = nullptr, bool EmitIR = true); Register getOrCreateConstInt(uint64_t Val, MachineInstr &I, - SPIRVType *SpvType, const SPIRVInstrInfo &TII); + SPIRVType *SpvType, const SPIRVInstrInfo &TII, + bool ZeroAsNull = true); + Register getOrCreateConstFP(APFloat Val, MachineInstr &I, SPIRVType *SpvType, + const SPIRVInstrInfo &TII, + bool ZeroAsNull = true); Register buildConstantFP(APFloat Val, MachineIRBuilder &MIRBuilder, SPIRVType *SpvType = nullptr); - Register getOrCreateConsIntVector(uint64_t Val, MachineInstr &I, - SPIRVType *SpvType, - const SPIRVInstrInfo &TII); + + Register getOrCreateConstVector(uint64_t Val, MachineInstr &I, + SPIRVType *SpvType, const SPIRVInstrInfo &TII, + bool ZeroAsNull = true); + Register getOrCreateConstVector(APFloat Val, MachineInstr &I, + SPIRVType *SpvType, const SPIRVInstrInfo &TII, + bool ZeroAsNull = true); Register getOrCreateConsIntArray(uint64_t Val, MachineInstr &I, SPIRVType *SpvType, const SPIRVInstrInfo &TII); @@ -423,6 +442,11 @@ public: MachineIRBuilder &MIRBuilder); SPIRVType *getOrCreateSPIRVIntegerType(unsigned BitWidth, MachineInstr &I, const SPIRVInstrInfo &TII); + SPIRVType *getOrCreateSPIRVType(unsigned BitWidth, MachineInstr &I, + const SPIRVInstrInfo &TII, + unsigned SPIRVOPcode, Type *LLVMTy); + SPIRVType *getOrCreateSPIRVFloatType(unsigned BitWidth, MachineInstr &I, + const SPIRVInstrInfo &TII); SPIRVType *getOrCreateSPIRVBoolType(MachineIRBuilder &MIRBuilder); SPIRVType *getOrCreateSPIRVBoolType(MachineInstr &I, const SPIRVInstrInfo &TII); diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 45a70da7f869..c1c0fc4b7dd4 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/IR/IntrinsicsSPIRV.h" #include "llvm/Support/Debug.h" @@ -144,6 +145,9 @@ private: bool selectAddrSpaceCast(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; + bool selectAll(Register ResVReg, const SPIRVType *ResType, + MachineInstr &I) const; + bool selectBitreverse(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; @@ -229,6 +233,7 @@ private: const SPIRVType *ResType = nullptr) const; Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const; + Register buildZerosValF(const SPIRVType *ResType, MachineInstr &I) const; Register buildOnesVal(bool AllOnes, const SPIRVType *ResType, MachineInstr &I) const; @@ -1155,6 +1160,65 @@ static unsigned getBoolCmpOpcode(unsigned PredNum) { } } +bool SPIRVInstructionSelector::selectAll(Register ResVReg, + const SPIRVType *ResType, + MachineInstr &I) const { + assert(I.getNumOperands() == 3); + assert(I.getOperand(2).isReg()); + MachineBasicBlock &BB = *I.getParent(); + Register InputRegister = I.getOperand(2).getReg(); + SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); + + if (!InputType) + report_fatal_error("Input Type could not be determined."); + + bool IsBoolTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeBool); + bool IsVectorTy = InputType->getOpcode() == SPIRV::OpTypeVector; + if (IsBoolTy && !IsVectorTy) { + assert(ResVReg == I.getOperand(0).getReg()); + return BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(TargetOpcode::COPY)) + .addDef(ResVReg) + .addUse(InputRegister) + .constrainAllUses(TII, TRI, RBI); + } + + bool IsFloatTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeFloat); + unsigned SpirvNotEqualId = + IsFloatTy ? SPIRV::OpFOrdNotEqual : SPIRV::OpINotEqual; + SPIRVType *SpvBoolScalarTy = GR.getOrCreateSPIRVBoolType(I, TII); + SPIRVType *SpvBoolTy = SpvBoolScalarTy; + Register NotEqualReg = ResVReg; + + if (IsVectorTy) { + NotEqualReg = IsBoolTy ? InputRegister + : MRI->createVirtualRegister(&SPIRV::IDRegClass); + const unsigned NumElts = InputType->getOperand(2).getImm(); + SpvBoolTy = GR.getOrCreateSPIRVVectorType(SpvBoolTy, NumElts, I, TII); + } + + if (!IsBoolTy) { + Register ConstZeroReg = + IsFloatTy ? buildZerosValF(InputType, I) : buildZerosVal(InputType, I); + + BuildMI(BB, I, I.getDebugLoc(), TII.get(SpirvNotEqualId)) + .addDef(NotEqualReg) + .addUse(GR.getSPIRVTypeID(SpvBoolTy)) + .addUse(InputRegister) + .addUse(ConstZeroReg) + .constrainAllUses(TII, TRI, RBI); + } + + if (!IsVectorTy) + return true; + + return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAll)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(SpvBoolScalarTy)) + .addUse(NotEqualReg) + .constrainAllUses(TII, TRI, RBI); +} + bool SPIRVInstructionSelector::selectBitreverse(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { @@ -1391,9 +1455,35 @@ bool SPIRVInstructionSelector::selectFCmp(Register ResVReg, Register SPIRVInstructionSelector::buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const { + // OpenCL uses nulls for Zero. In HLSL we don't use null constants. + bool ZeroAsNull = STI.isOpenCLEnv(); + if (ResType->getOpcode() == SPIRV::OpTypeVector) + return GR.getOrCreateConstVector(0UL, I, ResType, TII, ZeroAsNull); + return GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull); +} + +static APFloat getZeroFP(const Type *LLVMFloatTy) { + if (!LLVMFloatTy) + return APFloat::getZero(APFloat::IEEEsingle()); + switch (LLVMFloatTy->getScalarType()->getTypeID()) { + case Type::HalfTyID: + return APFloat::getZero(APFloat::IEEEhalf()); + default: + case Type::FloatTyID: + return APFloat::getZero(APFloat::IEEEsingle()); + case Type::DoubleTyID: + return APFloat::getZero(APFloat::IEEEdouble()); + } +} + +Register SPIRVInstructionSelector::buildZerosValF(const SPIRVType *ResType, + MachineInstr &I) const { + // OpenCL uses nulls for Zero. In HLSL we don't use null constants. + bool ZeroAsNull = STI.isOpenCLEnv(); + APFloat VZero = getZeroFP(GR.getTypeForSPIRVType(ResType)); if (ResType->getOpcode() == SPIRV::OpTypeVector) - return GR.getOrCreateConsIntVector(0, I, ResType, TII); - return GR.getOrCreateConstInt(0, I, ResType, TII); + return GR.getOrCreateConstVector(VZero, I, ResType, TII, ZeroAsNull); + return GR.getOrCreateConstFP(VZero, I, ResType, TII, ZeroAsNull); } Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes, @@ -1403,7 +1493,7 @@ Register SPIRVInstructionSelector::buildOnesVal(bool AllOnes, APInt One = AllOnes ? APInt::getAllOnes(BitWidth) : APInt::getOneBitSet(BitWidth, 0); if (ResType->getOpcode() == SPIRV::OpTypeVector) - return GR.getOrCreateConsIntVector(One.getZExtValue(), I, ResType, TII); + return GR.getOrCreateConstVector(One.getZExtValue(), I, ResType, TII); return GR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); } @@ -1785,6 +1875,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, break; case Intrinsic::spv_thread_id: return selectSpvThreadId(ResVReg, ResType, I); + case Intrinsic::spv_all: + return selectAll(ResVReg, ResType, I); case Intrinsic::spv_lifetime_start: case Intrinsic::spv_lifetime_end: { unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll new file mode 100644 index 000000000000..ef8d463cbd81 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll @@ -0,0 +1,187 @@ +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} +; Make sure spirv operation function calls for all are generated. + +; CHECK-HLSL-DAG: OpMemoryModel Logical GLSL450 +; CHECK-OCL-DAG: OpMemoryModel Physical32 OpenCL +; CHECK-DAG: OpName %[[#all_bool_arg:]] "a" +; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#bool:]] = OpTypeBool +; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 0 +; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64 +; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16 +; CHECK-DAG: %[[#vec4_bool:]] = OpTypeVector %[[#bool]] 4 +; CHECK-DAG: %[[#vec4_16:]] = OpTypeVector %[[#int_16]] 4 +; CHECK-DAG: %[[#vec4_32:]] = OpTypeVector %[[#int_32]] 4 +; CHECK-DAG: %[[#vec4_64:]] = OpTypeVector %[[#int_64]] 4 +; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4 +; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4 +; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4 + +; CHECK-HLSL-DAG: %[[#const_i64_0:]] = OpConstant %[[#int_64]] 0 +; CHECK-HLSL-DAG: %[[#const_i32_0:]] = OpConstant %[[#int_32]] 0 +; CHECK-HLSL-DAG: %[[#const_i16_0:]] = OpConstant %[[#int_16]] 0 +; CHECK-HLSL-DAG: %[[#const_f64_0:]] = OpConstant %[[#float_64]] 0 +; CHECK-HLSL-DAG: %[[#const_f32_0:]] = OpConstant %[[#float_32:]] 0 +; CHECK-HLSL-DAG: %[[#const_f16_0:]] = OpConstant %[[#float_16:]] 0 +; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantComposite %[[#vec4_16:]] %[[#const_i16_0:]] %[[#const_i16_0:]] %[[#const_i16_0:]] %[[#const_i16_0:]] +; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantComposite %[[#vec4_32:]] %[[#const_i32_0:]] %[[#const_i32_0:]] %[[#const_i32_0:]] %[[#const_i32_0:]] +; CHECK-HLSL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantComposite %[[#vec4_64:]] %[[#const_i64_0:]] %[[#const_i64_0:]] %[[#const_i64_0:]] %[[#const_i64_0:]] +; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantComposite %[[#vec4_float_16:]] %[[#const_f16_0:]] %[[#const_f16_0:]] %[[#const_f16_0:]] %[[#const_f16_0:]] +; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantComposite %[[#vec4_float_32:]] %[[#const_f32_0:]] %[[#const_f32_0:]] %[[#const_f32_0:]] %[[#const_f32_0:]] +; CHECK-HLSL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantComposite %[[#vec4_float_64:]] %[[#const_f64_0:]] %[[#const_f64_0:]] %[[#const_f64_0:]] %[[#const_f64_0:]] + +; CHECK-OCL-DAG: %[[#const_i64_0:]] = OpConstantNull %[[#int_64]] +; CHECK-OCL-DAG: %[[#const_i32_0:]] = OpConstantNull %[[#int_32]] +; CHECK-OCL-DAG: %[[#const_i16_0:]] = OpConstantNull %[[#int_16]] +; CHECK-OCL-DAG: %[[#const_f64_0:]] = OpConstantNull %[[#float_64]] +; CHECK-OCL-DAG: %[[#const_f32_0:]] = OpConstantNull %[[#float_32:]] +; CHECK-OCL-DAG: %[[#const_f16_0:]] = OpConstantNull %[[#float_16:]] +; CHECK-OCL-DAG: %[[#vec4_const_zeros_i16:]] = OpConstantNull %[[#vec4_16:]] +; CHECK-OCL-DAG: %[[#vec4_const_zeros_i32:]] = OpConstantNull %[[#vec4_32:]] +; CHECK-OCL-DAG: %[[#vec4_const_zeros_i64:]] = OpConstantNull %[[#vec4_64:]] +; CHECK-OCL-DAG: %[[#vec4_const_zeros_f16:]] = OpConstantNull %[[#vec4_float_16:]] +; CHECK-OCL-DAG: %[[#vec4_const_zeros_f32:]] = OpConstantNull %[[#vec4_float_32:]] +; CHECK-OCL-DAG: %[[#vec4_const_zeros_f64:]] = OpConstantNull %[[#vec4_float_64:]] + +define noundef i1 @all_int64_t(i64 noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i64_0:]] + %hlsl.all = call i1 @llvm.spv.all.i64(i64 %p0) + ret i1 %hlsl.all +} + + +define noundef i1 @all_int(i32 noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i32_0:]] + %hlsl.all = call i1 @llvm.spv.all.i32(i32 %p0) + ret i1 %hlsl.all +} + + +define noundef i1 @all_int16_t(i16 noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpINotEqual %[[#bool:]] %[[#arg0:]] %[[#const_i16_0:]] + %hlsl.all = call i1 @llvm.spv.all.i16(i16 %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_double(double noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f64_0:]] + %hlsl.all = call i1 @llvm.spv.all.f64(double %p0) + ret i1 %hlsl.all +} + + +define noundef i1 @all_float(float noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f32_0:]] + %hlsl.all = call i1 @llvm.spv.all.f32(float %p0) + ret i1 %hlsl.all +} + + +define noundef i1 @all_half(half noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpFOrdNotEqual %[[#bool:]] %[[#arg0:]] %[[#const_f16_0:]] + %hlsl.all = call i1 @llvm.spv.all.f16(half %p0) + ret i1 %hlsl.all +} + + +define noundef i1 @all_bool4(<4 x i1> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#]] = OpAll %[[#vec4_bool:]] %[[#arg0:]] + %hlsl.all = call i1 @llvm.spv.all.v4i1(<4 x i1> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_short4(<4 x i16> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#shortVecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i16:]] + ; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#shortVecNotEq:]] + %hlsl.all = call i1 @llvm.spv.all.v4i16(<4 x i16> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_int4(<4 x i32> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#i32VecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i32:]] + ; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#i32VecNotEq:]] + %hlsl.all = call i1 @llvm.spv.all.v4i32(<4 x i32> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_int64_t4(<4 x i64> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#i64VecNotEq:]] = OpINotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_i64:]] + ; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#i64VecNotEq]] + %hlsl.all = call i1 @llvm.spv.all.v4i64(<4 x i64> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_half4(<4 x half> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#f16VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f16:]] + ; CHECK: %[[#]] = OpAll %[[#bool]] %[[#f16VecNotEq:]] + %hlsl.all = call i1 @llvm.spv.all.v4f16(<4 x half> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_float4(<4 x float> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#f32VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f32:]] + ; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#f32VecNotEq:]] + %hlsl.all = call i1 @llvm.spv.all.v4f32(<4 x float> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_double4(<4 x double> noundef %p0) { +entry: + ; CHECK: %[[#arg0:]] = OpFunctionParameter %[[#]] + ; CHECK: %[[#f64VecNotEq:]] = OpFOrdNotEqual %[[#vec4_bool:]] %[[#arg0:]] %[[#vec4_const_zeros_f64:]] + ; CHECK: %[[#]] = OpAll %[[#bool:]] %[[#f64VecNotEq:]] + %hlsl.all = call i1 @llvm.spv.all.v4f64(<4 x double> %p0) + ret i1 %hlsl.all +} + +define noundef i1 @all_bool(i1 noundef %a) { +entry: + ; CHECK: %[[#all_bool_arg:]] = OpFunctionParameter %[[#bool:]] + ; CHECK: OpReturnValue %[[#all_bool_arg:]] + %hlsl.all = call i1 @llvm.spv.all.i1(i1 %a) + ret i1 %hlsl.all +} + +declare i1 @llvm.spv.all.v4f16(<4 x half>) +declare i1 @llvm.spv.all.v4f32(<4 x float>) +declare i1 @llvm.spv.all.v4f64(<4 x double>) +declare i1 @llvm.spv.all.v4i1(<4 x i1>) +declare i1 @llvm.spv.all.v4i16(<4 x i16>) +declare i1 @llvm.spv.all.v4i32(<4 x i32>) +declare i1 @llvm.spv.all.v4i64(<4 x i64>) +declare i1 @llvm.spv.all.i1(i1) +declare i1 @llvm.spv.all.i16(i16) +declare i1 @llvm.spv.all.i32(i32) +declare i1 @llvm.spv.all.i64(i64) +declare i1 @llvm.spv.all.f16(half) +declare i1 @llvm.spv.all.f32(float) +declare i1 @llvm.spv.all.f64(double) -- GitLab From c258f573981336cd9f87f89e59c6c2117e5d44ec Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 10 Apr 2024 13:42:51 -0700 Subject: [PATCH 452/695] [ELF] Move createSyntheticSections from Writer.cpp to SyntheticSections.cpp. NFC SyntheticSections.cpp is more appropriate. This change enables elimination of many explicit template instantiations. Due to `make>(*strtab)` in Arch/ARM.cpp, we do not remove explicit template instantiations for SymbolTableSection. --- lld/ELF/SyntheticSections.cpp | 367 +++++++++++++++++++++++++++++----- lld/ELF/SyntheticSections.h | 4 + lld/ELF/Writer.cpp | 292 --------------------------- lld/ELF/Writer.h | 3 - 4 files changed, 317 insertions(+), 349 deletions(-) diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp index d8791e83dc9e..0d7f393a9f3f 100644 --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -3870,6 +3870,27 @@ void InStruct::reset() { symTabShndx.reset(); } +static bool needsInterpSection() { + return !config->relocatable && !config->shared && + !config->dynamicLinker.empty() && script->needsInterpSection(); +} + +bool elf::hasMemtag() { + return config->emachine == EM_AARCH64 && + config->androidMemtagMode != ELF::NT_MEMTAG_LEVEL_NONE; +} + +// Fully static executables don't support MTE globals at this point in time, as +// we currently rely on: +// - A dynamic loader to process relocations, and +// - Dynamic entries. +// This restriction could be removed in future by re-using some of the ideas +// that ifuncs use in fully static executables. +bool elf::canHaveMemtagGlobals() { + return hasMemtag() && + (config->relocatable || config->shared || needsInterpSection()); +} + constexpr char kMemtagAndroidNoteName[] = "Android"; void MemtagAndroidNote::writeTo(uint8_t *buf) { static_assert( @@ -3985,31 +4006,304 @@ size_t MemtagGlobalDescriptors::getSize() const { return createMemtagGlobalDescriptors(symbols); } +static OutputSection *findSection(StringRef name) { + for (SectionCommand *cmd : script->sectionCommands) + if (auto *osd = dyn_cast(cmd)) + if (osd->osec.name == name) + return &osd->osec; + return nullptr; +} + +static Defined *addOptionalRegular(StringRef name, SectionBase *sec, + uint64_t val, uint8_t stOther = STV_HIDDEN) { + Symbol *s = symtab.find(name); + if (!s || s->isDefined() || s->isCommon()) + return nullptr; + + s->resolve(Defined{ctx.internalFile, StringRef(), STB_GLOBAL, stOther, + STT_NOTYPE, val, + /*size=*/0, sec}); + s->isUsedInRegularObj = true; + return cast(s); +} + +template void elf::createSyntheticSections() { + // Initialize all pointers with NULL. This is needed because + // you can call lld::elf::main more than once as a library. + Out::tlsPhdr = nullptr; + Out::preinitArray = nullptr; + Out::initArray = nullptr; + Out::finiArray = nullptr; + + // Add the .interp section first because it is not a SyntheticSection. + // The removeUnusedSyntheticSections() function relies on the + // SyntheticSections coming last. + if (needsInterpSection()) { + for (size_t i = 1; i <= partitions.size(); ++i) { + InputSection *sec = createInterpSection(); + sec->partition = i; + ctx.inputSections.push_back(sec); + } + } + + auto add = [](SyntheticSection &sec) { ctx.inputSections.push_back(&sec); }; + + in.shStrTab = std::make_unique(".shstrtab", false); + + Out::programHeaders = make("", 0, SHF_ALLOC); + Out::programHeaders->addralign = config->wordsize; + + if (config->strip != StripPolicy::All) { + in.strTab = std::make_unique(".strtab", false); + in.symTab = std::make_unique>(*in.strTab); + in.symTabShndx = std::make_unique(); + } + + in.bss = std::make_unique(".bss", 0, 1); + add(*in.bss); + + // If there is a SECTIONS command and a .data.rel.ro section name use name + // .data.rel.ro.bss so that we match in the .data.rel.ro output section. + // This makes sure our relro is contiguous. + bool hasDataRelRo = script->hasSectionsCommand && findSection(".data.rel.ro"); + in.bssRelRo = std::make_unique( + hasDataRelRo ? ".data.rel.ro.bss" : ".bss.rel.ro", 0, 1); + add(*in.bssRelRo); + + // Add MIPS-specific sections. + if (config->emachine == EM_MIPS) { + if (!config->shared && config->hasDynSymTab) { + in.mipsRldMap = std::make_unique(); + add(*in.mipsRldMap); + } + if ((in.mipsAbiFlags = MipsAbiFlagsSection::create())) + add(*in.mipsAbiFlags); + if ((in.mipsOptions = MipsOptionsSection::create())) + add(*in.mipsOptions); + if ((in.mipsReginfo = MipsReginfoSection::create())) + add(*in.mipsReginfo); + } + + StringRef relaDynName = config->isRela ? ".rela.dyn" : ".rel.dyn"; + + const unsigned threadCount = config->threadCount; + for (Partition &part : partitions) { + auto add = [&](SyntheticSection &sec) { + sec.partition = part.getNumber(); + ctx.inputSections.push_back(&sec); + }; + + if (!part.name.empty()) { + part.elfHeader = std::make_unique>(); + part.elfHeader->name = part.name; + add(*part.elfHeader); + + part.programHeaders = + std::make_unique>(); + add(*part.programHeaders); + } + + if (config->buildId != BuildIdKind::None) { + part.buildId = std::make_unique(); + add(*part.buildId); + } + + part.dynStrTab = std::make_unique(".dynstr", true); + part.dynSymTab = + std::make_unique>(*part.dynStrTab); + part.dynamic = std::make_unique>(); + + if (hasMemtag()) { + part.memtagAndroidNote = std::make_unique(); + add(*part.memtagAndroidNote); + if (canHaveMemtagGlobals()) { + part.memtagGlobalDescriptors = + std::make_unique(); + add(*part.memtagGlobalDescriptors); + } + } + + if (config->androidPackDynRelocs) + part.relaDyn = std::make_unique>( + relaDynName, threadCount); + else + part.relaDyn = std::make_unique>( + relaDynName, config->zCombreloc, threadCount); + + if (config->hasDynSymTab) { + add(*part.dynSymTab); + + part.verSym = std::make_unique(); + add(*part.verSym); + + if (!namedVersionDefs().empty()) { + part.verDef = std::make_unique(); + add(*part.verDef); + } + + part.verNeed = std::make_unique>(); + add(*part.verNeed); + + if (config->gnuHash) { + part.gnuHashTab = std::make_unique(); + add(*part.gnuHashTab); + } + + if (config->sysvHash) { + part.hashTab = std::make_unique(); + add(*part.hashTab); + } + + add(*part.dynamic); + add(*part.dynStrTab); + } + add(*part.relaDyn); + + if (config->relrPackDynRelocs) { + part.relrDyn = std::make_unique>(threadCount); + add(*part.relrDyn); + } + + if (!config->relocatable) { + if (config->ehFrameHdr) { + part.ehFrameHdr = std::make_unique(); + add(*part.ehFrameHdr); + } + part.ehFrame = std::make_unique(); + add(*part.ehFrame); + + if (config->emachine == EM_ARM) { + // This section replaces all the individual .ARM.exidx InputSections. + part.armExidx = std::make_unique(); + add(*part.armExidx); + } + } + + if (!config->packageMetadata.empty()) { + part.packageMetadataNote = std::make_unique(); + add(*part.packageMetadataNote); + } + } + + if (partitions.size() != 1) { + // Create the partition end marker. This needs to be in partition number 255 + // so that it is sorted after all other partitions. It also has other + // special handling (see createPhdrs() and combineEhSections()). + in.partEnd = + std::make_unique(".part.end", config->maxPageSize, 1); + in.partEnd->partition = 255; + add(*in.partEnd); + + in.partIndex = std::make_unique(); + addOptionalRegular("__part_index_begin", in.partIndex.get(), 0); + addOptionalRegular("__part_index_end", in.partIndex.get(), + in.partIndex->getSize()); + add(*in.partIndex); + } + + // Add .got. MIPS' .got is so different from the other archs, + // it has its own class. + if (config->emachine == EM_MIPS) { + in.mipsGot = std::make_unique(); + add(*in.mipsGot); + } else { + in.got = std::make_unique(); + add(*in.got); + } + + if (config->emachine == EM_PPC) { + in.ppc32Got2 = std::make_unique(); + add(*in.ppc32Got2); + } + + if (config->emachine == EM_PPC64) { + in.ppc64LongBranchTarget = std::make_unique(); + add(*in.ppc64LongBranchTarget); + } + + in.gotPlt = std::make_unique(); + add(*in.gotPlt); + in.igotPlt = std::make_unique(); + add(*in.igotPlt); + // Add .relro_padding if DATA_SEGMENT_RELRO_END is used; otherwise, add the + // section in the absence of PHDRS/SECTIONS commands. + if (config->zRelro && + ((script->phdrsCommands.empty() && !script->hasSectionsCommand) || + script->seenRelroEnd)) { + in.relroPadding = std::make_unique(); + add(*in.relroPadding); + } + + if (config->emachine == EM_ARM) { + in.armCmseSGSection = std::make_unique(); + add(*in.armCmseSGSection); + } + + // _GLOBAL_OFFSET_TABLE_ is defined relative to either .got.plt or .got. Treat + // it as a relocation and ensure the referenced section is created. + if (ElfSym::globalOffsetTable && config->emachine != EM_MIPS) { + if (target->gotBaseSymInGotPlt) + in.gotPlt->hasGotPltOffRel = true; + else + in.got->hasGotOffRel = true; + } + + // We always need to add rel[a].plt to output if it has entries. + // Even for static linking it can contain R_[*]_IRELATIVE relocations. + in.relaPlt = std::make_unique>( + config->isRela ? ".rela.plt" : ".rel.plt", /*sort=*/false, + /*threadCount=*/1); + add(*in.relaPlt); + + if ((config->emachine == EM_386 || config->emachine == EM_X86_64) && + (config->andFeatures & GNU_PROPERTY_X86_FEATURE_1_IBT)) { + in.ibtPlt = std::make_unique(); + add(*in.ibtPlt); + } + + if (config->emachine == EM_PPC) + in.plt = std::make_unique(); + else + in.plt = std::make_unique(); + add(*in.plt); + in.iplt = std::make_unique(); + add(*in.iplt); + + if (config->andFeatures || !ctx.aarch64PauthAbiCoreInfo.empty()) + add(*make()); + + if (config->gdbIndex) { + in.gdbIndex = GdbIndexSection::create(); + add(*in.gdbIndex); + } + + // .note.GNU-stack is always added when we are creating a re-linkable + // object file. Other linkers are using the presence of this marker + // section to control the executable-ness of the stack area, but that + // is irrelevant these days. Stack area should always be non-executable + // by default. So we emit this section unconditionally. + if (config->relocatable) + add(*make()); + + if (in.symTab) + add(*in.symTab); + if (in.symTabShndx) + add(*in.symTabShndx); + add(*in.shStrTab); + if (in.strTab) + add(*in.strTab); +} + InStruct elf::in; std::vector elf::partitions; Partition *elf::mainPart; -template std::unique_ptr GdbIndexSection::create(); -template std::unique_ptr GdbIndexSection::create(); -template std::unique_ptr GdbIndexSection::create(); -template std::unique_ptr GdbIndexSection::create(); - template void elf::splitSections(); template void elf::splitSections(); template void elf::splitSections(); template void elf::splitSections(); -template class elf::MipsAbiFlagsSection; -template class elf::MipsAbiFlagsSection; -template class elf::MipsAbiFlagsSection; -template class elf::MipsAbiFlagsSection; - -template class elf::MipsOptionsSection; -template class elf::MipsOptionsSection; -template class elf::MipsOptionsSection; -template class elf::MipsOptionsSection; - template void EhFrameSection::iterateFDEWithLSDA( function_ref); template void EhFrameSection::iterateFDEWithLSDA( @@ -4019,41 +4313,11 @@ template void EhFrameSection::iterateFDEWithLSDA( template void EhFrameSection::iterateFDEWithLSDA( function_ref); -template class elf::MipsReginfoSection; -template class elf::MipsReginfoSection; -template class elf::MipsReginfoSection; -template class elf::MipsReginfoSection; - -template class elf::DynamicSection; -template class elf::DynamicSection; -template class elf::DynamicSection; -template class elf::DynamicSection; - -template class elf::RelocationSection; -template class elf::RelocationSection; -template class elf::RelocationSection; -template class elf::RelocationSection; - -template class elf::AndroidPackedRelocationSection; -template class elf::AndroidPackedRelocationSection; -template class elf::AndroidPackedRelocationSection; -template class elf::AndroidPackedRelocationSection; - -template class elf::RelrSection; -template class elf::RelrSection; -template class elf::RelrSection; -template class elf::RelrSection; - template class elf::SymbolTableSection; template class elf::SymbolTableSection; template class elf::SymbolTableSection; template class elf::SymbolTableSection; -template class elf::VersionNeedSection; -template class elf::VersionNeedSection; -template class elf::VersionNeedSection; -template class elf::VersionNeedSection; - template void elf::writeEhdr(uint8_t *Buf, Partition &Part); template void elf::writeEhdr(uint8_t *Buf, Partition &Part); template void elf::writeEhdr(uint8_t *Buf, Partition &Part); @@ -4064,12 +4328,7 @@ template void elf::writePhdrs(uint8_t *Buf, Partition &Part); template void elf::writePhdrs(uint8_t *Buf, Partition &Part); template void elf::writePhdrs(uint8_t *Buf, Partition &Part); -template class elf::PartitionElfHeaderSection; -template class elf::PartitionElfHeaderSection; -template class elf::PartitionElfHeaderSection; -template class elf::PartitionElfHeaderSection; - -template class elf::PartitionProgramHeadersSection; -template class elf::PartitionProgramHeadersSection; -template class elf::PartitionProgramHeadersSection; -template class elf::PartitionProgramHeadersSection; +template void elf::createSyntheticSections(); +template void elf::createSyntheticSections(); +template void elf::createSyntheticSections(); +template void elf::createSyntheticSections(); diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h index 68b4cdb1dde0..759b78668f54 100644 --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -1284,11 +1284,15 @@ private: SmallVector symbols; }; +template void createSyntheticSections(); InputSection *createInterpSection(); MergeInputSection *createCommentSection(); template void splitSections(); void combineEhSections(); +bool hasMemtag(); +bool canHaveMemtagGlobals(); + template void writeEhdr(uint8_t *buf, Partition &part); template void writePhdrs(uint8_t *buf, Partition &part); diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 021b9bb0d5e2..d2a9e872dab9 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -91,11 +91,6 @@ private: }; } // anonymous namespace -static bool needsInterpSection() { - return !config->relocatable && !config->shared && - !config->dynamicLinker.empty() && script->needsInterpSection(); -} - template void elf::writeResult() { Writer().run(); } @@ -297,22 +292,6 @@ static void demoteSymbolsAndComputeIsPreemptible() { } } -bool elf::hasMemtag() { - return config->emachine == EM_AARCH64 && - config->androidMemtagMode != ELF::NT_MEMTAG_LEVEL_NONE; -} - -// Fully static executables don't support MTE globals at this point in time, as -// we currently rely on: -// - A dynamic loader to process relocations, and -// - Dynamic entries. -// This restriction could be removed in future by re-using some of the ideas -// that ifuncs use in fully static executables. -bool elf::canHaveMemtagGlobals() { - return hasMemtag() && - (config->relocatable || config->shared || needsInterpSection()); -} - static OutputSection *findSection(StringRef name, unsigned partition = 1) { for (SectionCommand *cmd : script->sectionCommands) if (auto *osd = dyn_cast(cmd)) @@ -321,272 +300,6 @@ static OutputSection *findSection(StringRef name, unsigned partition = 1) { return nullptr; } -template void elf::createSyntheticSections() { - // Initialize all pointers with NULL. This is needed because - // you can call lld::elf::main more than once as a library. - Out::tlsPhdr = nullptr; - Out::preinitArray = nullptr; - Out::initArray = nullptr; - Out::finiArray = nullptr; - - // Add the .interp section first because it is not a SyntheticSection. - // The removeUnusedSyntheticSections() function relies on the - // SyntheticSections coming last. - if (needsInterpSection()) { - for (size_t i = 1; i <= partitions.size(); ++i) { - InputSection *sec = createInterpSection(); - sec->partition = i; - ctx.inputSections.push_back(sec); - } - } - - auto add = [](SyntheticSection &sec) { ctx.inputSections.push_back(&sec); }; - - in.shStrTab = std::make_unique(".shstrtab", false); - - Out::programHeaders = make("", 0, SHF_ALLOC); - Out::programHeaders->addralign = config->wordsize; - - if (config->strip != StripPolicy::All) { - in.strTab = std::make_unique(".strtab", false); - in.symTab = std::make_unique>(*in.strTab); - in.symTabShndx = std::make_unique(); - } - - in.bss = std::make_unique(".bss", 0, 1); - add(*in.bss); - - // If there is a SECTIONS command and a .data.rel.ro section name use name - // .data.rel.ro.bss so that we match in the .data.rel.ro output section. - // This makes sure our relro is contiguous. - bool hasDataRelRo = script->hasSectionsCommand && findSection(".data.rel.ro"); - in.bssRelRo = std::make_unique( - hasDataRelRo ? ".data.rel.ro.bss" : ".bss.rel.ro", 0, 1); - add(*in.bssRelRo); - - // Add MIPS-specific sections. - if (config->emachine == EM_MIPS) { - if (!config->shared && config->hasDynSymTab) { - in.mipsRldMap = std::make_unique(); - add(*in.mipsRldMap); - } - if ((in.mipsAbiFlags = MipsAbiFlagsSection::create())) - add(*in.mipsAbiFlags); - if ((in.mipsOptions = MipsOptionsSection::create())) - add(*in.mipsOptions); - if ((in.mipsReginfo = MipsReginfoSection::create())) - add(*in.mipsReginfo); - } - - StringRef relaDynName = config->isRela ? ".rela.dyn" : ".rel.dyn"; - - const unsigned threadCount = config->threadCount; - for (Partition &part : partitions) { - auto add = [&](SyntheticSection &sec) { - sec.partition = part.getNumber(); - ctx.inputSections.push_back(&sec); - }; - - if (!part.name.empty()) { - part.elfHeader = std::make_unique>(); - part.elfHeader->name = part.name; - add(*part.elfHeader); - - part.programHeaders = - std::make_unique>(); - add(*part.programHeaders); - } - - if (config->buildId != BuildIdKind::None) { - part.buildId = std::make_unique(); - add(*part.buildId); - } - - part.dynStrTab = std::make_unique(".dynstr", true); - part.dynSymTab = - std::make_unique>(*part.dynStrTab); - part.dynamic = std::make_unique>(); - - if (hasMemtag()) { - part.memtagAndroidNote = std::make_unique(); - add(*part.memtagAndroidNote); - if (canHaveMemtagGlobals()) { - part.memtagGlobalDescriptors = - std::make_unique(); - add(*part.memtagGlobalDescriptors); - } - } - - if (config->androidPackDynRelocs) - part.relaDyn = std::make_unique>( - relaDynName, threadCount); - else - part.relaDyn = std::make_unique>( - relaDynName, config->zCombreloc, threadCount); - - if (config->hasDynSymTab) { - add(*part.dynSymTab); - - part.verSym = std::make_unique(); - add(*part.verSym); - - if (!namedVersionDefs().empty()) { - part.verDef = std::make_unique(); - add(*part.verDef); - } - - part.verNeed = std::make_unique>(); - add(*part.verNeed); - - if (config->gnuHash) { - part.gnuHashTab = std::make_unique(); - add(*part.gnuHashTab); - } - - if (config->sysvHash) { - part.hashTab = std::make_unique(); - add(*part.hashTab); - } - - add(*part.dynamic); - add(*part.dynStrTab); - } - add(*part.relaDyn); - - if (config->relrPackDynRelocs) { - part.relrDyn = std::make_unique>(threadCount); - add(*part.relrDyn); - } - - if (!config->relocatable) { - if (config->ehFrameHdr) { - part.ehFrameHdr = std::make_unique(); - add(*part.ehFrameHdr); - } - part.ehFrame = std::make_unique(); - add(*part.ehFrame); - - if (config->emachine == EM_ARM) { - // This section replaces all the individual .ARM.exidx InputSections. - part.armExidx = std::make_unique(); - add(*part.armExidx); - } - } - - if (!config->packageMetadata.empty()) { - part.packageMetadataNote = std::make_unique(); - add(*part.packageMetadataNote); - } - } - - if (partitions.size() != 1) { - // Create the partition end marker. This needs to be in partition number 255 - // so that it is sorted after all other partitions. It also has other - // special handling (see createPhdrs() and combineEhSections()). - in.partEnd = - std::make_unique(".part.end", config->maxPageSize, 1); - in.partEnd->partition = 255; - add(*in.partEnd); - - in.partIndex = std::make_unique(); - addOptionalRegular("__part_index_begin", in.partIndex.get(), 0); - addOptionalRegular("__part_index_end", in.partIndex.get(), - in.partIndex->getSize()); - add(*in.partIndex); - } - - // Add .got. MIPS' .got is so different from the other archs, - // it has its own class. - if (config->emachine == EM_MIPS) { - in.mipsGot = std::make_unique(); - add(*in.mipsGot); - } else { - in.got = std::make_unique(); - add(*in.got); - } - - if (config->emachine == EM_PPC) { - in.ppc32Got2 = std::make_unique(); - add(*in.ppc32Got2); - } - - if (config->emachine == EM_PPC64) { - in.ppc64LongBranchTarget = std::make_unique(); - add(*in.ppc64LongBranchTarget); - } - - in.gotPlt = std::make_unique(); - add(*in.gotPlt); - in.igotPlt = std::make_unique(); - add(*in.igotPlt); - // Add .relro_padding if DATA_SEGMENT_RELRO_END is used; otherwise, add the - // section in the absence of PHDRS/SECTIONS commands. - if (config->zRelro && ((script->phdrsCommands.empty() && - !script->hasSectionsCommand) || script->seenRelroEnd)) { - in.relroPadding = std::make_unique(); - add(*in.relroPadding); - } - - if (config->emachine == EM_ARM) { - in.armCmseSGSection = std::make_unique(); - add(*in.armCmseSGSection); - } - - // _GLOBAL_OFFSET_TABLE_ is defined relative to either .got.plt or .got. Treat - // it as a relocation and ensure the referenced section is created. - if (ElfSym::globalOffsetTable && config->emachine != EM_MIPS) { - if (target->gotBaseSymInGotPlt) - in.gotPlt->hasGotPltOffRel = true; - else - in.got->hasGotOffRel = true; - } - - // We always need to add rel[a].plt to output if it has entries. - // Even for static linking it can contain R_[*]_IRELATIVE relocations. - in.relaPlt = std::make_unique>( - config->isRela ? ".rela.plt" : ".rel.plt", /*sort=*/false, - /*threadCount=*/1); - add(*in.relaPlt); - - if ((config->emachine == EM_386 || config->emachine == EM_X86_64) && - (config->andFeatures & GNU_PROPERTY_X86_FEATURE_1_IBT)) { - in.ibtPlt = std::make_unique(); - add(*in.ibtPlt); - } - - if (config->emachine == EM_PPC) - in.plt = std::make_unique(); - else - in.plt = std::make_unique(); - add(*in.plt); - in.iplt = std::make_unique(); - add(*in.iplt); - - if (config->andFeatures || !ctx.aarch64PauthAbiCoreInfo.empty()) - add(*make()); - - if (config->gdbIndex) { - in.gdbIndex = GdbIndexSection::create(); - add(*in.gdbIndex); - } - - // .note.GNU-stack is always added when we are creating a re-linkable - // object file. Other linkers are using the presence of this marker - // section to control the executable-ness of the stack area, but that - // is irrelevant these days. Stack area should always be non-executable - // by default. So we emit this section unconditionally. - if (config->relocatable) - add(*make()); - - if (in.symTab) - add(*in.symTab); - if (in.symTabShndx) - add(*in.symTabShndx); - add(*in.shStrTab); - if (in.strTab) - add(*in.strTab); -} - // The main function of the writer. template void Writer::run() { // Now that we have a complete set of output sections. This function @@ -3114,11 +2827,6 @@ template void Writer::writeBuildId() { part.buildId->writeBuildId(output); } -template void elf::createSyntheticSections(); -template void elf::createSyntheticSections(); -template void elf::createSyntheticSections(); -template void elf::createSyntheticSections(); - template void elf::writeResult(); template void elf::writeResult(); template void elf::writeResult(); diff --git a/lld/ELF/Writer.h b/lld/ELF/Writer.h index aac8176d9098..7aa06dbcb131 100644 --- a/lld/ELF/Writer.h +++ b/lld/ELF/Writer.h @@ -17,7 +17,6 @@ namespace lld::elf { class InputFile; class OutputSection; void copySectionsIntoPartitions(); -template void createSyntheticSections(); template void writeResult(); // This describes a program header entry. @@ -57,8 +56,6 @@ bool isMipsN32Abi(const InputFile *f); bool isMicroMips(); bool isMipsR6(); -bool hasMemtag(); -bool canHaveMemtagGlobals(); } // namespace lld::elf #endif -- GitLab From 8cfa72ade9f2f7df81a008efea84f833b73494b9 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Wed, 10 Apr 2024 13:51:23 -0700 Subject: [PATCH 453/695] [libc] fix typo in hdr/CMakeLists Fixes #87896 --- libc/hdr/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 4ca7db5e98d6..5a1acd9d17ab 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -38,5 +38,5 @@ add_proxy_header_library( fenv_macros.h FULL_BUILD_DEPENDS libc.include.llvm-libc-macros.fenv_macros - libc.incude.fenv + libc.include.fenv ) -- GitLab From fb771fe315654231f613a5501ebd538f036c78b6 Mon Sep 17 00:00:00 2001 From: Jeff Niu Date: Wed, 10 Apr 2024 23:34:48 +0200 Subject: [PATCH 454/695] [mlir] Slightly optimize bytecode op numbering (#88310) If the bytecode encoding supports properties, then the dictionary attribute is always the raw dictionary attribute of the operation, regardless of what it contains. Otherwise, get the dictionary attribute from the op: if the op does not have properties, then it returns the raw dictionary, otherwise it returns the combined inherent and discardable attributes. --- mlir/lib/Bytecode/Writer/IRNumbering.cpp | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/mlir/lib/Bytecode/Writer/IRNumbering.cpp b/mlir/lib/Bytecode/Writer/IRNumbering.cpp index f36c9ef060b6..d2144dd7f334 100644 --- a/mlir/lib/Bytecode/Writer/IRNumbering.cpp +++ b/mlir/lib/Bytecode/Writer/IRNumbering.cpp @@ -424,22 +424,22 @@ void IRNumberingState::number(Operation &op) { number(result.getType()); } - // Only number the operation's dictionary if it isn't empty. - DictionaryAttr dictAttr = op.getDiscardableAttrDictionary(); // Prior to a version with native property encoding, or when properties are // not used, we need to number also the merged dictionary containing both the // inherent and discardable attribute. - if (config.getDesiredBytecodeVersion() < - bytecode::kNativePropertiesEncoding || - !op.getPropertiesStorage()) { + DictionaryAttr dictAttr; + if (config.getDesiredBytecodeVersion() >= bytecode::kNativePropertiesEncoding) + dictAttr = op.getRawDictionaryAttrs(); + else dictAttr = op.getAttrDictionary(); - } + // Only number the operation's dictionary if it isn't empty. if (!dictAttr.empty()) number(dictAttr); // Visit the operation properties (if any) to make sure referenced attributes // are numbered. - if (config.getDesiredBytecodeVersion() >= bytecode::kNativePropertiesEncoding && + if (config.getDesiredBytecodeVersion() >= + bytecode::kNativePropertiesEncoding && op.getPropertiesStorageSize()) { if (op.isRegistered()) { // Operation that have properties *must* implement this interface. -- GitLab From af7c196fb8d10f58a704b5a8d142feacf2f0236d Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Wed, 10 Apr 2024 14:45:49 -0700 Subject: [PATCH 455/695] [lldb][sbdebugger] Move SBDebugger Broadcast bit enum into lldb-enumerations.h (#87409) When the `eBroadcastBitProgressCategory` bit was originally added to Debugger.h and SBDebugger.h, each corresponding bit was added in order of the other bits that were previously there. Since `Debugger.h` has an enum bit that `SBDebugger.h` does not, this meant that their offsets did not match. Instead of trying to keep the bit offsets in sync between the two, it's preferable to just move SBDebugger's enum into the main enumerations header and use the bits from there. This also requires that API tests using the bits from SBDebugger update their usage. --- lldb/include/lldb/API/SBDebugger.h | 7 ------- lldb/include/lldb/lldb-enumerations.h | 8 ++++++++ .../diagnostic_reporting/TestDiagnosticReporting.py | 2 +- .../progress_reporting/TestProgressReporting.py | 2 +- .../clang_modules/TestClangModuleBuildProgress.py | 2 +- lldb/test/API/macosx/rosetta/TestRosetta.py | 2 +- 6 files changed, 12 insertions(+), 11 deletions(-) diff --git a/lldb/include/lldb/API/SBDebugger.h b/lldb/include/lldb/API/SBDebugger.h index 62b2f91f5076..cf5409a12a05 100644 --- a/lldb/include/lldb/API/SBDebugger.h +++ b/lldb/include/lldb/API/SBDebugger.h @@ -42,13 +42,6 @@ public: class LLDB_API SBDebugger { public: - FLAGS_ANONYMOUS_ENUM(){ - eBroadcastBitProgress = (1 << 0), - eBroadcastBitWarning = (1 << 1), - eBroadcastBitError = (1 << 2), - eBroadcastBitProgressCategory = (1 << 3), - }; - SBDebugger(); SBDebugger(const lldb::SBDebugger &rhs); diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index 646f7bfda984..f3b07ea6d203 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -1339,6 +1339,14 @@ enum AddressMaskRange { eAddressMaskRangeAll = eAddressMaskRangeAny, }; +/// Used by the debugger to indicate which events are being broadcasted. +enum DebuggerBroadcastBit { + eBroadcastBitProgress = (1 << 0), + eBroadcastBitWarning = (1 << 1), + eBroadcastBitError = (1 << 2), + eBroadcastBitProgressCategory = (1 << 3), +}; + } // namespace lldb #endif // LLDB_LLDB_ENUMERATIONS_H diff --git a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py index 36a3be695628..6353e3e8cbed 100644 --- a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py +++ b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py @@ -15,7 +15,7 @@ class TestDiagnosticReporting(TestBase): self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( self.broadcaster, - lldb.SBDebugger.eBroadcastBitWarning | lldb.SBDebugger.eBroadcastBitError, + lldb.eBroadcastBitWarning | lldb.eBroadcastBitError, ) def test_dwarf_symbol_loading_diagnostic_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py index 9af53845ca1b..98988d7624da 100644 --- a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py +++ b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py @@ -13,7 +13,7 @@ class TestProgressReporting(TestBase): TestBase.setUp(self) self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( - self.broadcaster, lldb.SBDebugger.eBroadcastBitProgress + self.broadcaster, lldb.eBroadcastBitProgress ) def test_dwarf_symbol_loading_progress_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py index 228f676aedf6..33c7c269c081 100644 --- a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py +++ b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py @@ -34,7 +34,7 @@ class TestCase(TestBase): # other unrelated progress events. broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.SBDebugger.eBroadcastBitProgress + broadcaster, lldb.eBroadcastBitProgress ) # Trigger module builds. diff --git a/lldb/test/API/macosx/rosetta/TestRosetta.py b/lldb/test/API/macosx/rosetta/TestRosetta.py index ce40de475ef1..669db95a1624 100644 --- a/lldb/test/API/macosx/rosetta/TestRosetta.py +++ b/lldb/test/API/macosx/rosetta/TestRosetta.py @@ -49,7 +49,7 @@ class TestRosetta(TestBase): if rosetta_debugserver_installed(): broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.SBDebugger.eBroadcastBitWarning + broadcaster, lldb.eBroadcastBitWarning ) target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( -- GitLab From 2fdfea088c8d78119b74116b94bc6729ce0e3efe Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 10 Apr 2024 14:50:54 -0700 Subject: [PATCH 456/695] [AMDGPU] Add v2i32 to the VS_64 types. NFCI. (#88318) I am trying to use VOP3Inst with intrinsic taking v2i32 operand and it fails to create patterm without it. --- llvm/lib/Target/AMDGPU/SIInstructions.td | 8 ++++---- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 04f3a2f57605..d6d49889656b 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -2087,7 +2087,7 @@ def : GCNPat < def : GCNPat < (DivergentUnaryFrag (v2f32 VReg_64:$src)), (V_PK_ADD_F32 11 /* OP_SEL_1 | NEG_LO | HEG_HI */, VReg_64:$src, - 11 /* OP_SEL_1 | NEG_LO | HEG_HI */, 0, + 11 /* OP_SEL_1 | NEG_LO | HEG_HI */, (i64 0), 0, 0, 0, 0, 0) > { let SubtargetPredicate = HasPackedFP32Ops; @@ -2999,7 +2999,7 @@ def : GCNPat< let SubtargetPredicate = HasPackedFP32Ops in { def : GCNPat< (fcanonicalize (v2f32 (VOP3PMods v2f32:$src, i32:$src_mods))), - (V_PK_MUL_F32 0, CONST.FP32_ONE, $src_mods, $src) + (V_PK_MUL_F32 0, (i64 CONST.FP32_ONE), $src_mods, $src) >; } @@ -3007,7 +3007,7 @@ def : GCNPat< let SubtargetPredicate = isNotGFX12Plus in { def : GCNPat< (fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))), - (V_MUL_F64_e64 0, CONST.FP64_ONE, $src_mods, $src) + (V_MUL_F64_e64 0, (i64 CONST.FP64_ONE), $src_mods, $src) >; } } // End AddedComplexity = -5 @@ -3369,7 +3369,7 @@ def : GCNPat < SRCMODS.NONE, (V_FRACT_F64_e64 $mods, $x), SRCMODS.NONE, - (V_MOV_B64_PSEUDO 0x3fefffffffffffff)), + (V_MOV_B64_PSEUDO (i64 0x3fefffffffffffff))), $x, (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, (i32 3 /*NaN*/)))) >; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index cb6591bf6244..01ed565bb756 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -1046,7 +1046,7 @@ def VS_32_Lo128 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2 let HasSGPR = 1; } -def VS_64 : SIRegisterClass<"AMDGPU", [i64, f64, v2f32], 32, (add VReg_64, SReg_64)> { +def VS_64 : SIRegisterClass<"AMDGPU", VReg_64.RegTypes, 32, (add VReg_64, SReg_64)> { let isAllocatable = 0; let HasVGPR = 1; let HasSGPR = 1; -- GitLab From 9f6d08f2566a26144ea1753f80aebb1f2ecfdc63 Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Wed, 10 Apr 2024 14:54:30 -0700 Subject: [PATCH 457/695] Revert "[lldb][sbdebugger] Move SBDebugger Broadcast bit enum into lldb-enumerations.h" (#88324) Reverts llvm/llvm-project#87409 due a missed update to the broadcast bit causing a build failure on the x86_64 Debian buildbot. --- lldb/include/lldb/API/SBDebugger.h | 7 +++++++ lldb/include/lldb/lldb-enumerations.h | 8 -------- .../diagnostic_reporting/TestDiagnosticReporting.py | 2 +- .../progress_reporting/TestProgressReporting.py | 2 +- .../clang_modules/TestClangModuleBuildProgress.py | 2 +- lldb/test/API/macosx/rosetta/TestRosetta.py | 2 +- 6 files changed, 11 insertions(+), 12 deletions(-) diff --git a/lldb/include/lldb/API/SBDebugger.h b/lldb/include/lldb/API/SBDebugger.h index cf5409a12a05..62b2f91f5076 100644 --- a/lldb/include/lldb/API/SBDebugger.h +++ b/lldb/include/lldb/API/SBDebugger.h @@ -42,6 +42,13 @@ public: class LLDB_API SBDebugger { public: + FLAGS_ANONYMOUS_ENUM(){ + eBroadcastBitProgress = (1 << 0), + eBroadcastBitWarning = (1 << 1), + eBroadcastBitError = (1 << 2), + eBroadcastBitProgressCategory = (1 << 3), + }; + SBDebugger(); SBDebugger(const lldb::SBDebugger &rhs); diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index f3b07ea6d203..646f7bfda984 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -1339,14 +1339,6 @@ enum AddressMaskRange { eAddressMaskRangeAll = eAddressMaskRangeAny, }; -/// Used by the debugger to indicate which events are being broadcasted. -enum DebuggerBroadcastBit { - eBroadcastBitProgress = (1 << 0), - eBroadcastBitWarning = (1 << 1), - eBroadcastBitError = (1 << 2), - eBroadcastBitProgressCategory = (1 << 3), -}; - } // namespace lldb #endif // LLDB_LLDB_ENUMERATIONS_H diff --git a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py index 6353e3e8cbed..36a3be695628 100644 --- a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py +++ b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py @@ -15,7 +15,7 @@ class TestDiagnosticReporting(TestBase): self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( self.broadcaster, - lldb.eBroadcastBitWarning | lldb.eBroadcastBitError, + lldb.SBDebugger.eBroadcastBitWarning | lldb.SBDebugger.eBroadcastBitError, ) def test_dwarf_symbol_loading_diagnostic_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py index 98988d7624da..9af53845ca1b 100644 --- a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py +++ b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py @@ -13,7 +13,7 @@ class TestProgressReporting(TestBase): TestBase.setUp(self) self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( - self.broadcaster, lldb.eBroadcastBitProgress + self.broadcaster, lldb.SBDebugger.eBroadcastBitProgress ) def test_dwarf_symbol_loading_progress_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py index 33c7c269c081..228f676aedf6 100644 --- a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py +++ b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py @@ -34,7 +34,7 @@ class TestCase(TestBase): # other unrelated progress events. broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.eBroadcastBitProgress + broadcaster, lldb.SBDebugger.eBroadcastBitProgress ) # Trigger module builds. diff --git a/lldb/test/API/macosx/rosetta/TestRosetta.py b/lldb/test/API/macosx/rosetta/TestRosetta.py index 669db95a1624..ce40de475ef1 100644 --- a/lldb/test/API/macosx/rosetta/TestRosetta.py +++ b/lldb/test/API/macosx/rosetta/TestRosetta.py @@ -49,7 +49,7 @@ class TestRosetta(TestBase): if rosetta_debugserver_installed(): broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.eBroadcastBitWarning + broadcaster, lldb.SBDebugger.eBroadcastBitWarning ) target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( -- GitLab From d8f1e5d2894f7f4edc2e85e63def456c7f430f34 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Apr 2024 15:07:16 -0700 Subject: [PATCH 458/695] [APInt] Remove accumulator initialization from tcMultiply and tcFullMultiply. NFCI (#88202) The tcMultiplyPart routine has a flag that says whether to add to the accumulator or overwrite it. By using the overwrite mode on the first iteration we don't need to initialize the accumulator to zero. Note, the initialization in tcFullMultiply was only initializing the first rhsParts of dst. tcMultiplyPart always overwrites the rhsParts+1 part that just contains the last carry. The first write to each part of dst past rhsParts is a carry write so that's how the upper part of dst is initialized. --- llvm/lib/Support/APInt.cpp | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp index 8825025ec321..18feca4c0553 100644 --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -2585,11 +2585,13 @@ int APInt::tcMultiply(WordType *dst, const WordType *lhs, assert(dst != lhs && dst != rhs); int overflow = 0; - tcSet(dst, 0, parts); - for (unsigned i = 0; i < parts; i++) - overflow |= tcMultiplyPart(&dst[i], lhs, rhs[i], 0, parts, - parts - i, true); + for (unsigned i = 0; i < parts; i++) { + // Don't accumulate on the first iteration so we don't need to initalize + // dst to 0. + overflow |= + tcMultiplyPart(&dst[i], lhs, rhs[i], 0, parts, parts - i, i != 0); + } return overflow; } @@ -2605,10 +2607,11 @@ void APInt::tcFullMultiply(WordType *dst, const WordType *lhs, assert(dst != lhs && dst != rhs); - tcSet(dst, 0, rhsParts); - - for (unsigned i = 0; i < lhsParts; i++) - tcMultiplyPart(&dst[i], rhs, lhs[i], 0, rhsParts, rhsParts + 1, true); + for (unsigned i = 0; i < lhsParts; i++) { + // Don't accumulate on the first iteration so we don't need to initalize + // dst to 0. + tcMultiplyPart(&dst[i], rhs, lhs[i], 0, rhsParts, rhsParts + 1, i != 0); + } } // If RHS is zero LHS and REMAINDER are left unchanged, return one. -- GitLab From a9d4ddd98a0bc495126027122fdca751b6841ceb Mon Sep 17 00:00:00 2001 From: Oskar Wirga Date: Wed, 10 Apr 2024 15:37:27 -0700 Subject: [PATCH 459/695] [MergeFuncs/CFI] Ensure all type metadata is propogated for CFI (#88218) I noticed that we weren't propagating ALL type metadata that was attached to CFI functions: # BEFORE ``` ; Function Attrs: minsize nounwind optsize ssp uwtable(sync) define internal void @foo(ptr nocapture noundef readonly %0) #0 !dbg !62311 !type !34028 !type !34029 !type !34030 ... fn merging ; Function Attrs: minsize nounwind optsize ssp uwtable(sync) define internal void @foo(ptr nocapture noundef readonly %0) #0 !type !34028 ``` # AFTER ``` ; Function Attrs: minsize nounwind optsize ssp uwtable(sync) define internal void @foo(ptr nocapture noundef readonly %0) #0 !dbg !62311 !type !34028 !type !34029 !type !34030 ... fn merging ; Function Attrs: minsize nounwind optsize ssp uwtable(sync) define internal void @foo(ptr nocapture noundef readonly %0) #0 !type !type !34028 !type !34029 !type !34030 ``` This patch makes sure that the entire vector of metadata is copied over. --- llvm/lib/Transforms/IPO/MergeFunctions.cpp | 12 +++++---- .../Transforms/MergeFunc/cfi-thunk-merging.ll | 26 +++++++++---------- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Transforms/IPO/MergeFunctions.cpp b/llvm/lib/Transforms/IPO/MergeFunctions.cpp index 05a3b169aaaf..b50a700e0903 100644 --- a/llvm/lib/Transforms/IPO/MergeFunctions.cpp +++ b/llvm/lib/Transforms/IPO/MergeFunctions.cpp @@ -712,11 +712,13 @@ static bool canCreateThunkFor(Function *F) { return true; } -/// Copy metadata from one function to another. -static void copyMetadataIfPresent(Function *From, Function *To, StringRef Key) { - if (MDNode *MD = From->getMetadata(Key)) { - To->setMetadata(Key, MD); - } +/// Copy all metadata of a specific kind from one function to another. +static void copyMetadataIfPresent(Function *From, Function *To, + StringRef Kind) { + SmallVector MDs; + From->getMetadata(Kind, MDs); + for (MDNode *MD : MDs) + To->addMetadata(Kind, *MD); } // Replace G with a simple tail call to bitcast(F). Also (unless diff --git a/llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll b/llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll index d35d77728273..562cc1a973d8 100644 --- a/llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll +++ b/llvm/test/Transforms/MergeFunc/cfi-thunk-merging.ll @@ -98,7 +98,7 @@ attributes #3 = { noreturn nounwind } !4 = !{i64 0, !"_ZTSFiiE.generalized"} !5 = !{} ; CHECK-LABEL: define dso_local i32 @f -; CHECK-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] !type !2 !type !3 { +; CHECK-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] !type [[META2:![0-9]+]] !type [[META3:![0-9]+]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -119,7 +119,7 @@ attributes #3 = { noreturn nounwind } ; ; ; CHECK-LABEL: define dso_local i32 @g -; CHECK-SAME: (i32 noundef [[B:%.*]]) #[[ATTR0]] !type !2 !type !3 { +; CHECK-SAME: (i32 noundef [[B:%.*]]) #[[ATTR0]] !type [[META2]] !type [[META3]] { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 ; CHECK-NEXT: [[FP:%.*]] = alloca ptr, align 8 @@ -130,11 +130,11 @@ attributes #3 = { noreturn nounwind } ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], ptr @f, ptr @f_thunk ; CHECK-NEXT: store ptr [[COND]], ptr [[FP]], align 8 ; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr [[FP]], align 8 -; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.type.test(ptr [[TMP2]], metadata !"_ZTSFiiE"), !nosanitize !4 -; CHECK-NEXT: br i1 [[TMP3]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize !4 +; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.type.test(ptr [[TMP2]], metadata !"_ZTSFiiE"), !nosanitize [[META4:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP3]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META4]] ; CHECK: trap: -; CHECK-NEXT: call void @llvm.ubsantrap(i8 2) #[[ATTR3:[0-9]+]], !nosanitize !4 -; CHECK-NEXT: unreachable, !nosanitize !4 +; CHECK-NEXT: call void @llvm.ubsantrap(i8 2) #[[ATTR3:[0-9]+]], !nosanitize [[META4]] +; CHECK-NEXT: unreachable, !nosanitize [[META4]] ; CHECK: cont: ; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4 ; CHECK-NEXT: [[CALL:%.*]] = call i32 [[TMP2]](i32 noundef [[TMP4]]) @@ -142,13 +142,13 @@ attributes #3 = { noreturn nounwind } ; ; ; CHECK-LABEL: define dso_local i32 @f_thunk -; CHECK-SAME: (i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !type !2 { +; CHECK-SAME: (i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !type [[META2]] !type [[META3]] { ; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]] ; CHECK-NEXT: ret i32 [[TMP2]] ; ; ; LOWERTYPETESTS-LABEL: define dso_local i32 @f -; LOWERTYPETESTS-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] !type !2 !type !3 { +; LOWERTYPETESTS-SAME: (i32 noundef [[ARG:%.*]]) #[[ATTR0:[0-9]+]] !type [[META2:![0-9]+]] !type [[META3:![0-9]+]] { ; LOWERTYPETESTS-NEXT: entry: ; LOWERTYPETESTS-NEXT: [[ARG_ADDR:%.*]] = alloca i32, align 4 ; LOWERTYPETESTS-NEXT: [[A:%.*]] = alloca i32, align 4 @@ -169,7 +169,7 @@ attributes #3 = { noreturn nounwind } ; ; ; LOWERTYPETESTS-LABEL: define dso_local i32 @g -; LOWERTYPETESTS-SAME: (i32 noundef [[B:%.*]]) #[[ATTR0]] !type !2 !type !3 { +; LOWERTYPETESTS-SAME: (i32 noundef [[B:%.*]]) #[[ATTR0]] !type [[META2]] !type [[META3]] { ; LOWERTYPETESTS-NEXT: entry: ; LOWERTYPETESTS-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 ; LOWERTYPETESTS-NEXT: [[FP:%.*]] = alloca ptr, align 8 @@ -186,10 +186,10 @@ attributes #3 = { noreturn nounwind } ; LOWERTYPETESTS-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 61 ; LOWERTYPETESTS-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] ; LOWERTYPETESTS-NEXT: [[TMP8:%.*]] = icmp ule i64 [[TMP7]], 1 -; LOWERTYPETESTS-NEXT: br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize !4 +; LOWERTYPETESTS-NEXT: br i1 [[TMP8]], label [[CONT:%.*]], label [[TRAP:%.*]], !nosanitize [[META4:![0-9]+]] ; LOWERTYPETESTS: trap: -; LOWERTYPETESTS-NEXT: call void @llvm.ubsantrap(i8 2) #[[ATTR4:[0-9]+]], !nosanitize !4 -; LOWERTYPETESTS-NEXT: unreachable, !nosanitize !4 +; LOWERTYPETESTS-NEXT: call void @llvm.ubsantrap(i8 2) #[[ATTR4:[0-9]+]], !nosanitize [[META4]] +; LOWERTYPETESTS-NEXT: unreachable, !nosanitize [[META4]] ; LOWERTYPETESTS: cont: ; LOWERTYPETESTS-NEXT: [[TMP9:%.*]] = load i32, ptr [[B_ADDR]], align 4 ; LOWERTYPETESTS-NEXT: [[CALL:%.*]] = call i32 [[TMP2]](i32 noundef [[TMP9]]) @@ -197,7 +197,7 @@ attributes #3 = { noreturn nounwind } ; ; ; LOWERTYPETESTS-LABEL: define dso_local i32 @f_thunk -; LOWERTYPETESTS-SAME: (i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !type !2 { +; LOWERTYPETESTS-SAME: (i32 noundef [[TMP0:%.*]]) #[[ATTR0]] !type [[META2]] !type [[META3]] { ; LOWERTYPETESTS-NEXT: [[TMP2:%.*]] = tail call i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]] ; LOWERTYPETESTS-NEXT: ret i32 [[TMP2]] ; -- GitLab From 8136ac1c42dcfdd070f0bcba0f06424093df22db Mon Sep 17 00:00:00 2001 From: Daniel Chen Date: Wed, 10 Apr 2024 19:22:38 -0400 Subject: [PATCH 460/695] [Flang] Define c_int_fast16_t and c_int_fast32_t for PowerPC. (#88292) On Linux, PowerPC defines `int_fast16_t` and `int_fast32_t` as `long`. Need to update the corresponding type, `c_int_fast16_t` and `c_int_fast32_t` in `iso_c_binding` module so they are interoparable. --- flang/lib/Frontend/CompilerInvocation.cpp | 17 +++++++++-------- flang/module/iso_c_binding.f90 | 8 ++++++++ .../test/Driver/predefined-macros-powerpc2.f90 | 13 +++++++++++++ 3 files changed, 30 insertions(+), 8 deletions(-) create mode 100644 flang/test/Driver/predefined-macros-powerpc2.f90 diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index 8ce6ab7baf48..e432c5a30275 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -1333,6 +1333,15 @@ void CompilerInvocation::setDefaultPredefinitions() { } llvm::Triple targetTriple{llvm::Triple(this->targetOpts.triple)}; + if (targetTriple.isPPC()) { + // '__powerpc__' is a generic macro for any PowerPC cases. e.g. Max integer + // size. + fortranOptions.predefinitions.emplace_back("__powerpc__", "1"); + } + if (targetTriple.isOSLinux()) { + fortranOptions.predefinitions.emplace_back("__linux__", "1"); + } + switch (targetTriple.getArch()) { default: break; @@ -1340,14 +1349,6 @@ void CompilerInvocation::setDefaultPredefinitions() { fortranOptions.predefinitions.emplace_back("__x86_64__", "1"); fortranOptions.predefinitions.emplace_back("__x86_64", "1"); break; - case llvm::Triple::ArchType::ppc: - case llvm::Triple::ArchType::ppcle: - case llvm::Triple::ArchType::ppc64: - case llvm::Triple::ArchType::ppc64le: - // '__powerpc__' is a generic macro for any PowerPC cases. e.g. Max integer - // size. - fortranOptions.predefinitions.emplace_back("__powerpc__", "1"); - break; } } diff --git a/flang/module/iso_c_binding.f90 b/flang/module/iso_c_binding.f90 index 1661fd5a6dcf..eb0f8f2ef59a 100644 --- a/flang/module/iso_c_binding.f90 +++ b/flang/module/iso_c_binding.f90 @@ -58,9 +58,17 @@ module iso_c_binding c_int_least8_t = c_int8_t, & c_int_fast8_t = c_int8_t, & c_int_least16_t = c_int16_t, & +#if defined(__linux__) && defined(__powerpc__) + c_int_fast16_t = c_long, & +#else c_int_fast16_t = c_int16_t, & +#endif c_int_least32_t = c_int32_t, & +#if defined(__linux__) && defined(__powerpc__) + c_int_fast32_t = c_long, & +#else c_int_fast32_t = c_int32_t, & +#endif c_int_least64_t = c_int64_t, & c_int_fast64_t = c_int64_t, & c_int_least128_t = c_int128_t, & diff --git a/flang/test/Driver/predefined-macros-powerpc2.f90 b/flang/test/Driver/predefined-macros-powerpc2.f90 new file mode 100644 index 000000000000..6e10235e21f8 --- /dev/null +++ b/flang/test/Driver/predefined-macros-powerpc2.f90 @@ -0,0 +1,13 @@ +! Test predefined macro for PowerPC architecture + +! RUN: %flang_fc1 -triple ppc64le-unknown-linux -cpp -E %s | FileCheck %s +! REQUIRES: target=powerpc{{.*}} + +! CHECK: integer :: var1 = 1 +! CHECK: integer :: var2 = 1 + +#if defined(__linux__) && defined(__powerpc__) + integer :: var1 = __powerpc__ + integer :: var2 = __linux__ +#endif +end program -- GitLab From acb7ddc5cf2f23416f65dcdc6c7fd08850ad961d Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Wed, 10 Apr 2024 16:24:02 -0700 Subject: [PATCH 461/695] [WebAssembly] Remove threadlocal.address when disabling TLS (#88209) Remove `llvm.threadlocal.address` intrinsic usage when disabling TLS. This fixes errors revealed by the stricter IR verification introduced in PR #87841. --- .../WebAssembly/WebAssemblyTargetMachine.cpp | 11 ++++++++ .../WebAssembly/tls-general-dynamic.ll | 26 +++++++++++++------ .../CodeGen/WebAssembly/tls-local-exec.ll | 17 ++++++++---- 3 files changed, 41 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 70685b2e3bb2..769ee765e190 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -291,6 +291,17 @@ private: bool Stripped = false; for (auto &GV : M.globals()) { if (GV.isThreadLocal()) { + // replace `@llvm.threadlocal.address.pX(GV)` with `GV`. + for (Use &U : make_early_inc_range(GV.uses())) { + if (IntrinsicInst *II = dyn_cast(U.getUser())) { + if (II->getIntrinsicID() == Intrinsic::threadlocal_address && + II->getArgOperand(0) == &GV) { + II->replaceAllUsesWith(&GV); + II->eraseFromParent(); + } + } + } + Stripped = true; GV.setThreadLocal(false); } diff --git a/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll b/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll index 46ab62dfaaa2..006b73922d2b 100644 --- a/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll +++ b/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll @@ -14,7 +14,9 @@ define i32 @address_of_tls() { ; NO-TLS-NEXT: i32.const tls ; NO-TLS-NEXT: return - ret i32 ptrtoint(ptr @tls to i32) + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + %r = ptrtoint ptr %p to i32 + ret i32 %r } ; CHECK-LABEL: address_of_tls_external: @@ -25,7 +27,9 @@ define i32 @address_of_tls_external() { ; NO-TLS-NEXT: i32.const tls_external ; NO-TLS-NEXT: return - ret i32 ptrtoint(ptr @tls_external to i32) + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls_external) + %r = ptrtoint ptr %p to i32 + ret i32 %r } ; CHECK-LABEL: ptr_to_tls: @@ -38,7 +42,8 @@ define ptr @ptr_to_tls() { ; NO-TLS-NEXT: i32.const tls ; NO-TLS-NEXT: return - ret ptr @tls + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + ret ptr %p } ; CHECK-LABEL: ptr_to_tls_external: @@ -49,7 +54,8 @@ define ptr @ptr_to_tls_external() { ; NO-TLS-NEXT: i32.const tls_external ; NO-TLS-NEXT: return - ret ptr @tls_external + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls_external) + ret ptr %p } ; CHECK-LABEL: tls_load: @@ -64,7 +70,8 @@ define i32 @tls_load() { ; NO-TLS-NEXT: i32.const 0 ; NO-TLS-NEXT: i32.load tls ; NO-TLS-NEXT: return - %tmp = load i32, ptr @tls, align 4 + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + %tmp = load i32, ptr %p, align 4 ret i32 %tmp } @@ -78,7 +85,8 @@ define i32 @tls_load_external() { ; NO-TLS-NEXT: i32.const 0 ; NO-TLS-NEXT: i32.load tls_external ; NO-TLS-NEXT: return - %tmp = load i32, ptr @tls_external, align 4 + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls_external) + %tmp = load i32, ptr %p, align 4 ret i32 %tmp } @@ -94,7 +102,8 @@ define void @tls_store(i32 %x) { ; NO-TLS-NEXT: i32.const 0 ; NO-TLS-NEXT: i32.store tls ; NO-TLS-NEXT: return - store i32 %x, ptr @tls, align 4 + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + store i32 %x, ptr %p, align 4 ret void } @@ -108,7 +117,8 @@ define void @tls_store_external(i32 %x) { ; NO-TLS-NEXT: i32.const 0 ; NO-TLS-NEXT: i32.store tls_external ; NO-TLS-NEXT: return - store i32 %x, ptr @tls_external, align 4 + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls_external) + store i32 %x, ptr %p, align 4 ret void } diff --git a/llvm/test/CodeGen/WebAssembly/tls-local-exec.ll b/llvm/test/CodeGen/WebAssembly/tls-local-exec.ll index 3aa044c34789..dc0d40c7973a 100644 --- a/llvm/test/CodeGen/WebAssembly/tls-local-exec.ll +++ b/llvm/test/CodeGen/WebAssembly/tls-local-exec.ll @@ -20,7 +20,9 @@ define i32 @address_of_tls() { ; NO-TLS-NEXT: i32.const tls ; NO-TLS-NEXT: return - ret i32 ptrtoint(ptr @tls to i32) + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + %r = ptrtoint ptr %p to i32 + ret i32 %r } ; CHECK-LABEL: address_of_tls_external: @@ -33,7 +35,9 @@ define i32 @address_of_tls_external() { ; NO-TLS-NEXT: i32.const tls_external ; NO-TLS-NEXT: return - ret i32 ptrtoint(ptr @tls_external to i32) + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls_external) + %r = ptrtoint ptr %p to i32 + ret i32 %r } ; CHECK-LABEL: ptr_to_tls: @@ -46,7 +50,8 @@ define ptr @ptr_to_tls() { ; NO-TLS-NEXT: i32.const tls ; NO-TLS-NEXT: return - ret ptr @tls + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + ret ptr %p } ; CHECK-LABEL: tls_load: @@ -61,7 +66,8 @@ define i32 @tls_load() { ; NO-TLS-NEXT: i32.const 0 ; NO-TLS-NEXT: i32.load tls ; NO-TLS-NEXT: return - %tmp = load i32, ptr @tls, align 4 + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + %tmp = load i32, ptr %p, align 4 ret i32 %tmp } @@ -77,7 +83,8 @@ define void @tls_store(i32 %x) { ; NO-TLS-NEXT: i32.const 0 ; NO-TLS-NEXT: i32.store tls ; NO-TLS-NEXT: return - store i32 %x, ptr @tls, align 4 + %p = call ptr @llvm.threadlocal.address.p0(ptr @tls) + store i32 %x, ptr %p, align 4 ret void } -- GitLab From d927d1867fa760836538beef2c4531c1a0b04e24 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Wed, 10 Apr 2024 16:30:42 -0700 Subject: [PATCH 462/695] [UBSAN] Emit optimization remarks (#88304) --- llvm/lib/IR/DiagnosticInfo.cpp | 6 ++- .../Instrumentation/LowerAllowCheckPass.cpp | 46 +++++++++++++++++-- .../lower-builtin-allow-check-remarks.ll | 24 ++++++++++ 3 files changed, 70 insertions(+), 6 deletions(-) create mode 100644 llvm/test/Transforms/lower-builtin-allow-check-remarks.ll diff --git a/llvm/lib/IR/DiagnosticInfo.cpp b/llvm/lib/IR/DiagnosticInfo.cpp index 342c4cbbc39d..31971b179fb4 100644 --- a/llvm/lib/IR/DiagnosticInfo.cpp +++ b/llvm/lib/IR/DiagnosticInfo.cpp @@ -179,8 +179,12 @@ DiagnosticInfoOptimizationBase::Argument::Argument(StringRef Key, else if (isa(V)) { raw_string_ostream OS(Val); V->printAsOperand(OS, /*PrintType=*/false); - } else if (auto *I = dyn_cast(V)) + } else if (auto *I = dyn_cast(V)) { Val = I->getOpcodeName(); + } else if (auto *MD = dyn_cast(V)) { + if (auto *S = dyn_cast(MD->getMetadata())) + Val = S->getString(); + } } DiagnosticInfoOptimizationBase::Argument::Argument(StringRef Key, const Type *T) diff --git a/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp b/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp index cdc8318f088c..465fa41b6c66 100644 --- a/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp +++ b/llvm/lib/Transforms/Instrumentation/LowerAllowCheckPass.cpp @@ -10,11 +10,16 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/Analysis/ProfileSummaryInfo.h" #include "llvm/IR/Constant.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Intrinsics.h" +#include "llvm/IR/Metadata.h" #include "llvm/Support/RandomNumberGenerator.h" #include #include @@ -35,13 +40,41 @@ static cl::opt STATISTIC(NumChecksTotal, "Number of checks"); STATISTIC(NumChecksRemoved, "Number of removed checks"); +struct RemarkInfo { + ore::NV Kind; + ore::NV F; + ore::NV BB; + explicit RemarkInfo(IntrinsicInst *II) + : Kind("Kind", II->getArgOperand(0)), + F("Function", II->getParent()->getParent()), + BB("Block", II->getParent()->getName()) {} +}; + +static void emitRemark(IntrinsicInst *II, OptimizationRemarkEmitter &ORE, + bool Removed) { + if (Removed) { + ORE.emit([&]() { + RemarkInfo Info(II); + return OptimizationRemark(DEBUG_TYPE, "Removed", II) + << "Removed check: Kind=" << Info.Kind << " F=" << Info.F + << " BB=" << Info.BB; + }); + } else { + ORE.emit([&]() { + RemarkInfo Info(II); + return OptimizationRemarkMissed(DEBUG_TYPE, "Allowed", II) + << "Allowed check: Kind=" << Info.Kind << " F=" << Info.F + << " BB=" << Info.BB; + }); + } +} + static bool removeUbsanTraps(Function &F, const BlockFrequencyInfo &BFI, - const ProfileSummaryInfo *PSI) { + const ProfileSummaryInfo *PSI, + OptimizationRemarkEmitter &ORE) { SmallVector, 16> ReplaceWithValue; std::unique_ptr Rng; - // TODO: - // https://github.com/llvm/llvm-project/pull/84858#discussion_r1520603139 auto ShouldRemove = [&](bool IsHot) { if (!RandomRate.getNumOccurrences()) return IsHot; @@ -75,6 +108,7 @@ static bool removeUbsanTraps(Function &F, const BlockFrequencyInfo &BFI, }); if (ToRemove) ++NumChecksRemoved; + emitRemark(II, ORE, ToRemove); break; } default: @@ -99,9 +133,11 @@ PreservedAnalyses LowerAllowCheckPass::run(Function &F, ProfileSummaryInfo *PSI = MAMProxy.getCachedResult(*F.getParent()); BlockFrequencyInfo &BFI = AM.getResult(F); + OptimizationRemarkEmitter &ORE = + AM.getResult(F); - return removeUbsanTraps(F, BFI, PSI) ? PreservedAnalyses::none() - : PreservedAnalyses::all(); + return removeUbsanTraps(F, BFI, PSI, ORE) ? PreservedAnalyses::none() + : PreservedAnalyses::all(); } bool LowerAllowCheckPass::IsRequested() { diff --git a/llvm/test/Transforms/lower-builtin-allow-check-remarks.ll b/llvm/test/Transforms/lower-builtin-allow-check-remarks.ll new file mode 100644 index 000000000000..3422ab1b56d3 --- /dev/null +++ b/llvm/test/Transforms/lower-builtin-allow-check-remarks.ll @@ -0,0 +1,24 @@ +; RUN: opt < %s -passes='require,function(lower-allow-check)' -lower-allow-check-random-rate=1 -pass-remarks=lower-allow-check -pass-remarks-missed=lower-allow-check -S 2>&1 | FileCheck %s +; RUN: opt < %s -passes='require,function(lower-allow-check)' -lower-allow-check-random-rate=0 -pass-remarks=lower-allow-check -pass-remarks-missed=lower-allow-check -S 2>&1 | FileCheck %s --check-prefixes=REMOVE + +; CHECK: remark: :0:0: Allowed check: Kind=test_check F=test_runtime BB=entry1 +; CHECK: remark: :0:0: Allowed check: Kind=7 F=test_ubsan BB=entry2 + +; REMOVE: remark: :0:0: Removed check: Kind=test_check F=test_runtime BB=entry1 +; REMOVE: remark: :0:0: Removed check: Kind=7 F=test_ubsan BB=entry2 + +target triple = "x86_64-pc-linux-gnu" + +define i1 @test_runtime() local_unnamed_addr { +entry1: + %allow = call i1 @llvm.allow.runtime.check(metadata !"test_check") + ret i1 %allow +} + +declare i1 @llvm.allow.runtime.check(metadata) nounwind + +define i1 @test_ubsan() local_unnamed_addr { +entry2: + %allow = call i1 @llvm.allow.ubsan.check(i8 7) + ret i1 %allow +} -- GitLab From 6ef4450705473e5cccb025219e8980999f456b71 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Thu, 11 Apr 2024 07:37:12 +0800 Subject: [PATCH 463/695] [clang] Fix -Wunused-function in CGStmtOpenMP.cpp (NFC) llvm-project/clang/lib/CodeGen/CGStmtOpenMP.cpp:7959:13: error: unused function 'emitTargetTeamsLoopCodegenStatus' [-Werror,-Wunused-function] static void emitTargetTeamsLoopCodegenStatus(CodeGenFunction &CGF, ^ 1 error generated. --- clang/lib/CodeGen/CGStmtOpenMP.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index 3bf99366b69c..a0a8a07c76ba 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -7956,10 +7956,10 @@ void CodeGenFunction::EmitOMPTeamsGenericLoopDirective( [](CodeGenFunction &) { return nullptr; }); } +#ifndef NDEBUG static void emitTargetTeamsLoopCodegenStatus(CodeGenFunction &CGF, std::string StatusMsg, const OMPExecutableDirective &D) { -#ifndef NDEBUG bool IsDevice = CGF.CGM.getLangOpts().OpenMPIsTargetDevice; if (IsDevice) StatusMsg += ": DEVICE"; @@ -7972,8 +7972,8 @@ static void emitTargetTeamsLoopCodegenStatus(CodeGenFunction &CGF, unsigned LineNo = PLoc.isValid() ? PLoc.getLine() : SM.getExpansionLineNumber(L); llvm::dbgs() << StatusMsg << ": " << FileName << ": " << LineNo << "\n"; -#endif } +#endif static void emitTargetTeamsGenericLoopRegionAsParallel( CodeGenFunction &CGF, PrePostActionTy &Action, -- GitLab From 19e516fbed809af094ce195a6a5baa2e1f30f3cd Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 10 Apr 2024 23:35:52 +0000 Subject: [PATCH 464/695] [gn build] Port 1fda1776e32b --- llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 66e8084d5808..53dc5b92c2d9 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -361,6 +361,7 @@ if (current_toolchain == default_toolchain) { "__chrono/parser_std_format_spec.h", "__chrono/statically_widen.h", "__chrono/steady_clock.h", + "__chrono/sys_info.h", "__chrono/system_clock.h", "__chrono/time_point.h", "__chrono/time_zone.h", -- GitLab From 402706668362fee8f9a9d29fb6d4628df4d4fc42 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 10 Apr 2024 23:35:53 +0000 Subject: [PATCH 465/695] [gn build] Port 59e66c515a47 --- llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 53dc5b92c2d9..c3eda6878090 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -466,6 +466,7 @@ if (current_toolchain == default_toolchain) { "__format/formatter_pointer.h", "__format/formatter_string.h", "__format/formatter_tuple.h", + "__format/indic_conjunct_break_table.h", "__format/parser_std_format_spec.h", "__format/range_default_formatter.h", "__format/range_formatter.h", -- GitLab From 233edab8765686bd44611f9f7319d3ffbc12fbab Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 10 Apr 2024 23:35:54 +0000 Subject: [PATCH 466/695] [gn build] Port 5d7d6ad663f8 --- llvm/utils/gn/secondary/clang/unittests/AST/Interp/BUILD.gn | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/utils/gn/secondary/clang/unittests/AST/Interp/BUILD.gn b/llvm/utils/gn/secondary/clang/unittests/AST/Interp/BUILD.gn index dd47a3d2d345..fcdb9a5b1aeb 100644 --- a/llvm/utils/gn/secondary/clang/unittests/AST/Interp/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/unittests/AST/Interp/BUILD.gn @@ -9,5 +9,8 @@ unittest("InterpTests") { "//clang/lib/Testing", "//clang/lib/Tooling", ] - sources = [ "Descriptor.cpp" ] + sources = [ + "Descriptor.cpp", + "toAPValue.cpp", + ] } -- GitLab From 9786a3b4cf9d050a6f87358e3295da3d32fade5c Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 10 Apr 2024 23:36:17 +0000 Subject: [PATCH 467/695] [gn build] Port 0a1317564a6b --- llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 + llvm/utils/gn/secondary/libcxx/src/BUILD.gn | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index c3eda6878090..4270bae57ff2 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -932,6 +932,7 @@ if (current_toolchain == default_toolchain) { "__utility/pair.h", "__utility/piecewise_construct.h", "__utility/priority_tag.h", + "__utility/private_constructor_tag.h", "__utility/rel_ops.h", "__utility/small_buffer.h", "__utility/swap.h", diff --git a/llvm/utils/gn/secondary/libcxx/src/BUILD.gn b/llvm/utils/gn/secondary/libcxx/src/BUILD.gn index 90f6f5d0f145..5da8db4574a0 100644 --- a/llvm/utils/gn/secondary/libcxx/src/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/src/BUILD.gn @@ -315,8 +315,6 @@ if (libcxx_enable_experimental) { sources = [ "experimental/keep.cpp" ] if (libcxx_enable_filesystem && libcxx_enable_time_zone_database) { sources += [ - "include/tzdb/leap_second_private.h", - "include/tzdb/time_zone_link_private.h", "include/tzdb/time_zone_private.h", "include/tzdb/types_private.h", "include/tzdb/tzdb_list_private.h", -- GitLab From be10070f91b86a6f126d2451852242bfcb2cd366 Mon Sep 17 00:00:00 2001 From: Arthur Eubanks Date: Wed, 10 Apr 2024 23:41:51 +0000 Subject: [PATCH 468/695] Revert "[Driver] Ensure ToolChain::LibraryPaths is not empty for non-Darwin" This reverts commit ccdebbae4d77d3efc236af92c22941de5d437e01. Causes test failures in the presence of Android runtime libraries in resource-dir. See comments on https://github.com/llvm/llvm-project/pull/87866. --- clang/lib/Driver/ToolChain.cpp | 8 +---- clang/test/Driver/arm-compiler-rt.c | 14 ++++----- clang/test/Driver/cl-link.c | 16 +++++----- clang/test/Driver/compiler-rt-unwind.c | 6 ++-- clang/test/Driver/coverage-ld.c | 8 ++--- clang/test/Driver/instrprof-ld.c | 16 +++++----- clang/test/Driver/linux-ld.c | 6 ++-- clang/test/Driver/mingw-sanitizers.c | 16 +++++----- clang/test/Driver/msp430-toolchain.c | 4 +-- .../Driver/print-libgcc-file-name-clangrt.c | 12 ++++---- clang/test/Driver/print-runtime-dir.c | 6 ++++ clang/test/Driver/riscv32-toolchain-extra.c | 6 ++-- clang/test/Driver/riscv32-toolchain.c | 6 ++-- clang/test/Driver/riscv64-toolchain-extra.c | 6 ++-- clang/test/Driver/riscv64-toolchain.c | 6 ++-- clang/test/Driver/sanitizer-ld.c | 30 +++++++++---------- clang/test/Driver/wasm-toolchain.c | 18 +++++------ clang/test/Driver/wasm-toolchain.cpp | 16 +++++----- clang/test/Driver/windows-cross.c | 18 +++++------ clang/test/Driver/zos-ld.c | 12 ++++---- .../test/Driver/msvc-dependent-lib-flags.f90 | 8 ++--- 21 files changed, 119 insertions(+), 119 deletions(-) diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 237092ed07e5..03450fc0f57b 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -796,13 +796,7 @@ ToolChain::getTargetSubDirPath(StringRef BaseDir) const { std::optional ToolChain::getRuntimePath() const { SmallString<128> P(D.ResourceDir); llvm::sys::path::append(P, "lib"); - if (auto Ret = getTargetSubDirPath(P)) - return Ret; - // Darwin does not use per-target runtime directory. - if (Triple.isOSDarwin()) - return {}; - llvm::sys::path::append(P, Triple.str()); - return std::string(P); + return getTargetSubDirPath(P); } std::optional ToolChain::getStdlibPath() const { diff --git a/clang/test/Driver/arm-compiler-rt.c b/clang/test/Driver/arm-compiler-rt.c index cb6c29f48a78..5e9e528400d0 100644 --- a/clang/test/Driver/arm-compiler-rt.c +++ b/clang/test/Driver/arm-compiler-rt.c @@ -10,47 +10,47 @@ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABI -// ARM-GNUEABI: "{{.*[/\\]}}libclang_rt.builtins.a" +// ARM-GNUEABI: "{{.*[/\\]}}libclang_rt.builtins-arm.a" // RUN: %clang -target arm-linux-gnueabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -mfloat-abi=hard -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABI-ABI -// ARM-GNUEABI-ABI: "{{.*[/\\]}}libclang_rt.builtins.a" +// ARM-GNUEABI-ABI: "{{.*[/\\]}}libclang_rt.builtins-armhf.a" // RUN: %clang -target arm-linux-gnueabihf \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABIHF -// ARM-GNUEABIHF: "{{.*[/\\]}}libclang_rt.builtins.a" +// ARM-GNUEABIHF: "{{.*[/\\]}}libclang_rt.builtins-armhf.a" // RUN: %clang -target arm-linux-gnueabihf \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -mfloat-abi=soft -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-GNUEABIHF-ABI -// ARM-GNUEABIHF-ABI: "{{.*[/\\]}}libclang_rt.builtins.a" +// ARM-GNUEABIHF-ABI: "{{.*[/\\]}}libclang_rt.builtins-arm.a" // RUN: %clang -target arm-windows-itanium \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-WINDOWS -// ARM-WINDOWS: "{{.*[/\\]}}clang_rt.builtins.lib" +// ARM-WINDOWS: "{{.*[/\\]}}clang_rt.builtins-arm.lib" // RUN: %clang -target arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-ANDROID -// ARM-ANDROID: "{{.*[/\\]}}libclang_rt.builtins.a" +// ARM-ANDROID: "{{.*[/\\]}}libclang_rt.builtins-arm-android.a" // RUN: not %clang --target=arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -rtlib=compiler-rt -mfloat-abi=hard -### %s 2>&1 \ // RUN: | FileCheck %s -check-prefix ARM-ANDROIDHF -// ARM-ANDROIDHF: "{{.*[/\\]}}libclang_rt.builtins.a" +// ARM-ANDROIDHF: "{{.*[/\\]}}libclang_rt.builtins-armhf-android.a" diff --git a/clang/test/Driver/cl-link.c b/clang/test/Driver/cl-link.c index ffd0b5ac4bad..444f0c01b3f9 100644 --- a/clang/test/Driver/cl-link.c +++ b/clang/test/Driver/cl-link.c @@ -13,20 +13,20 @@ // ASAN: link.exe // ASAN: "-debug" // ASAN: "-incremental:no" -// ASAN: "{{[^"]*}}clang_rt.asan.lib" -// ASAN: "-wholearchive:{{.*}}clang_rt.asan.lib" -// ASAN: "{{[^"]*}}clang_rt.asan_cxx.lib" -// ASAN: "-wholearchive:{{.*}}clang_rt.asan_cxx.lib" +// ASAN: "{{[^"]*}}clang_rt.asan-i386.lib" +// ASAN: "-wholearchive:{{.*}}clang_rt.asan-i386.lib" +// ASAN: "{{[^"]*}}clang_rt.asan_cxx-i386.lib" +// ASAN: "-wholearchive:{{.*}}clang_rt.asan_cxx-i386.lib" // ASAN: "{{.*}}cl-link{{.*}}.obj" // RUN: %clang_cl -m32 -arch:IA32 --target=i386-pc-win32 /MD /Tc%s -fuse-ld=link -### -fsanitize=address 2>&1 | FileCheck --check-prefix=ASAN-MD %s // ASAN-MD: link.exe // ASAN-MD: "-debug" // ASAN-MD: "-incremental:no" -// ASAN-MD: "{{.*}}clang_rt.asan_dynamic.lib" -// ASAN-MD: "{{[^"]*}}clang_rt.asan_dynamic_runtime_thunk.lib" +// ASAN-MD: "{{.*}}clang_rt.asan_dynamic-i386.lib" +// ASAN-MD: "{{[^"]*}}clang_rt.asan_dynamic_runtime_thunk-i386.lib" // ASAN-MD: "-include:___asan_seh_interceptor" -// ASAN-MD: "-wholearchive:{{.*}}clang_rt.asan_dynamic_runtime_thunk.lib" +// ASAN-MD: "-wholearchive:{{.*}}clang_rt.asan_dynamic_runtime_thunk-i386.lib" // ASAN-MD: "{{.*}}cl-link{{.*}}.obj" // RUN: %clang_cl /LD -fuse-ld=link -### /Tc%s 2>&1 | FileCheck --check-prefix=DLL %s @@ -40,7 +40,7 @@ // ASAN-DLL: "-dll" // ASAN-DLL: "-debug" // ASAN-DLL: "-incremental:no" -// ASAN-DLL: "{{.*}}clang_rt.asan_dll_thunk.lib" +// ASAN-DLL: "{{.*}}clang_rt.asan_dll_thunk-i386.lib" // ASAN-DLL: "{{.*}}cl-link{{.*}}.obj" // RUN: %clang_cl /Zi /Tc%s -fuse-ld=link -### 2>&1 | FileCheck --check-prefix=DEBUG %s diff --git a/clang/test/Driver/compiler-rt-unwind.c b/clang/test/Driver/compiler-rt-unwind.c index c5040d7fd900..7f4e3f22ab19 100644 --- a/clang/test/Driver/compiler-rt-unwind.c +++ b/clang/test/Driver/compiler-rt-unwind.c @@ -98,14 +98,14 @@ // RUN: --target=x86_64-w64-mingw32 -rtlib=compiler-rt --unwindlib=libunwind \ // RUN: -shared-libgcc \ // RUN: | FileCheck --check-prefix=MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT %s -// MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins.a" +// MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins-x86_64.a" // MINGW-RTLIB-COMPILER-RT-SHARED-UNWINDLIB-COMPILER-RT-SAME: "-l:libunwind.dll.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-w64-mingw32 -rtlib=compiler-rt --unwindlib=libunwind \ // RUN: -static-libgcc \ // RUN: | FileCheck --check-prefix=MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT %s -// MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins.a" +// MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins-x86_64.a" // MINGW-RTLIB-COMPILER-RT-STATIC-UNWINDLIB-COMPILER-RT-SAME: "-l:libunwind.a" // // RUN: %clang -### %s 2>&1 \ @@ -114,5 +114,5 @@ // RUN: %clangxx -### %s 2>&1 \ // RUN: --target=x86_64-w64-mingw32 -rtlib=compiler-rt --unwindlib=libunwind \ // RUN: | FileCheck --check-prefix=MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT %s -// MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins.a" +// MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT: "{{.*}}libclang_rt.builtins-x86_64.a" // MINGW-RTLIB-COMPILER-RT-UNWINDLIB-COMPILER-RT-SAME: "-lunwind" diff --git a/clang/test/Driver/coverage-ld.c b/clang/test/Driver/coverage-ld.c index be1d8320ab8b..acb08eb5db59 100644 --- a/clang/test/Driver/coverage-ld.c +++ b/clang/test/Driver/coverage-ld.c @@ -33,7 +33,7 @@ // RUN: | FileCheck --check-prefix=CHECK-FREEBSD-X86-64 %s // // CHECK-FREEBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-freebsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}freebsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-netbsd --coverage -fuse-ld=ld \ @@ -42,7 +42,7 @@ // RUN: | FileCheck --check-prefix=CHECK-NETBSD-X86-64 %s // CHECK-NETBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-netbsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}netbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-openbsd --coverage -fuse-ld=ld \ @@ -51,7 +51,7 @@ // RUN: | FileCheck --check-prefix=CHECK-OPENBSD-X86-64 %s // CHECK-OPENBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-openbsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}openbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=arm-linux-androideabi --coverage -fuse-ld=ld \ @@ -60,4 +60,4 @@ // RUN: | FileCheck --check-prefix=CHECK-ANDROID-ARM %s // // CHECK-ANDROID-ARM: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" -// CHECK-ANDROID-ARM: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}arm-unknown-linux-android{{/|\\\\}}libclang_rt.profile.a" +// CHECK-ANDROID-ARM: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}linux{{/|\\\\}}libclang_rt.profile-arm-android.a" diff --git a/clang/test/Driver/instrprof-ld.c b/clang/test/Driver/instrprof-ld.c index a96bba4a1e76..674580b349d4 100644 --- a/clang/test/Driver/instrprof-ld.c +++ b/clang/test/Driver/instrprof-ld.c @@ -34,7 +34,7 @@ // RUN: | FileCheck --check-prefix=CHECK-FREEBSD-X86-64 %s // // CHECK-FREEBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-freebsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-FREEBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}freebsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-netbsd -fprofile-instr-generate -fuse-ld=ld \ @@ -43,7 +43,7 @@ // RUN: | FileCheck --check-prefix=CHECK-NETBSD-X86-64 %s // CHECK-NETBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-netbsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-NETBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}netbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-openbsd -fprofile-instr-generate -fuse-ld=ld \ @@ -52,7 +52,7 @@ // RUN: | FileCheck --check-prefix=CHECK-OPENBSD-X86-64 %s // CHECK-OPENBSD-X86-64: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-openbsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-OPENBSD-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}openbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -72,7 +72,7 @@ // RUN: | FileCheck --check-prefix=CHECK-LINUX-X86-64-SHARED %s // // CHECK-LINUX-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-LINUX-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{.*}}x86_64-unknown-linux{{.*}}libclang_rt.profile.a" {{.*}} "-lc" +// CHECK-LINUX-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{.*}}linux{{.*}}libclang_rt.profile.a" {{.*}} "-lc" // // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -82,7 +82,7 @@ // RUN: | FileCheck --check-prefix=CHECK-FREEBSD-X86-64-SHARED %s // // CHECK-FREEBSD-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-FREEBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-freebsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-FREEBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}freebsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -92,7 +92,7 @@ // RUN: | FileCheck --check-prefix=CHECK-NETBSD-X86-64-SHARED %s // CHECK-NETBSD-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-NETBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-netbsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-NETBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}netbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // RUN: %clang -### %s 2>&1 \ // RUN: -shared \ @@ -102,7 +102,7 @@ // RUN: | FileCheck --check-prefix=CHECK-OPENBSD-X86-64-SHARED %s // CHECK-OPENBSD-X86-64-SHARED: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-OPENBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-openbsd{{/|\\\\}}libclang_rt.profile.a" +// CHECK-OPENBSD-X86-64-SHARED: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}openbsd{{/|\\\\}}libclang_rt.profile-x86_64.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-apple-darwin14 -fprofile-instr-generate -fuse-ld=ld \ @@ -174,7 +174,7 @@ // RUN: | FileCheck --check-prefix=CHECK-MINGW-X86-64 %s // // CHECK-MINGW-X86-64: "{{(.*[^.0-9A-Z_a-z])?}}ld{{(.exe)?}}" -// CHECK-MINGW-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-windows-gnu{{/|\\\\}}libclang_rt.profile.a" +// CHECK-MINGW-X86-64: "{{.*}}/Inputs/resource_dir{{/|\\\\}}lib{{/|\\\\}}windows{{/|\\\\}}libclang_rt.profile-x86_64.a" // Test instrumented profiling dependent-lib flags // diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c index e5c556367385..4020b138dc8f 100644 --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -99,9 +99,9 @@ // CHECK-LD-RT-ANDROID: "--eh-frame-hdr" // CHECK-LD-RT-ANDROID: "-m" "armelf_linux_eabi" // CHECK-LD-RT-ANDROID: "-dynamic-linker" -// CHECK-LD-RT-ANDROID: libclang_rt.builtins.a" +// CHECK-LD-RT-ANDROID: libclang_rt.builtins-arm-android.a" // CHECK-LD-RT-ANDROID: "-lc" -// CHECK-LD-RT-ANDROID: libclang_rt.builtins.a" +// CHECK-LD-RT-ANDROID: libclang_rt.builtins-arm-android.a" // // RUN: %clang -### %s -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ @@ -264,7 +264,7 @@ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-CLANG-ANDROID-STATIC %s // CHECK-CLANG-ANDROID-STATIC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" -// CHECK-CLANG-ANDROID-STATIC: "--start-group" "{{[^"]*}}{{/|\\\\}}libclang_rt.builtins.a" "-l:libunwind.a" "-lc" "--end-group" +// CHECK-CLANG-ANDROID-STATIC: "--start-group" "{{[^"]*}}{{/|\\\\}}libclang_rt.builtins-aarch64-android.a" "-l:libunwind.a" "-lc" "--end-group" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ diff --git a/clang/test/Driver/mingw-sanitizers.c b/clang/test/Driver/mingw-sanitizers.c index 2325f8f0f1f2..d165648a8fdf 100644 --- a/clang/test/Driver/mingw-sanitizers.c +++ b/clang/test/Driver/mingw-sanitizers.c @@ -4,17 +4,17 @@ // // ASAN-ALL-NOT:"-l{{[^"]+"]}}" // ASAN-ALL-NOT:"[[INPUT]]" -// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" -// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" +// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic-i386.dll.a" +// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic-x86_64.dll.a" // ASAN-ALL: "-lcomponent" // ASAN-ALL: "[[INPUT]]" -// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" -// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" +// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic-i386.dll.a" +// ASAN-I686: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-i386.a" // ASAN-I686: "--require-defined" "___asan_seh_interceptor" -// ASAN-I686: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" "--no-whole-archive" -// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic.dll.a" -// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" +// ASAN-I686: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-i386.a" "--no-whole-archive" +// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic-x86_64.dll.a" +// ASAN-X86_64: "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-x86_64.a" // ASAN-X86_64: "--require-defined" "__asan_seh_interceptor" -// ASAN-X86_64: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk.a" "--no-whole-archive" +// ASAN-X86_64: "--whole-archive" "{{[^"]*}}libclang_rt.asan_dynamic_runtime_thunk-x86_64.a" "--no-whole-archive" // RUN: %clang -target x86_64-windows-gnu %s -### -fsanitize=vptr diff --git a/clang/test/Driver/msp430-toolchain.c b/clang/test/Driver/msp430-toolchain.c index 3c3042b482ef..ef6780c38f2e 100644 --- a/clang/test/Driver/msp430-toolchain.c +++ b/clang/test/Driver/msp430-toolchain.c @@ -103,8 +103,8 @@ // LIBS-COMPILER-RT-POS: "{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430{{/|\\\\}}crtbegin_no_eh.o" // LIBS-COMPILER-RT-POS: "-L{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430" // LIBS-COMPILER-RT-POS: "-L{{.*}}/Inputs/basic_msp430_tree{{/|\\\\}}msp430-elf{{/|\\\\}}lib/430" -// LIBS-COMPILER-RT-POS: "{{[^"]*}}libclang_rt.builtins.a" "--start-group" "-lmul_none" "-lc" "{{[^"]*}}libclang_rt.builtins.a" "-lcrt" "-lnosys" "--end-group" "{{[^"]*}}libclang_rt.builtins.a" -// LIBS-COMPILER-RT-POS: "{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430{{/|\\\\}}crtend_no_eh.o" "{{[^"]*}}libclang_rt.builtins.a" +// LIBS-COMPILER-RT-POS: "{{[^"]*}}libclang_rt.builtins-msp430.a" "--start-group" "-lmul_none" "-lc" "{{[^"]*}}libclang_rt.builtins-msp430.a" "-lcrt" "-lnosys" "--end-group" "{{[^"]*}}libclang_rt.builtins-msp430.a" +// LIBS-COMPILER-RT-POS: "{{.*}}/Inputs/basic_msp430_tree/lib/gcc/msp430-elf/8.3.1/430{{/|\\\\}}crtend_no_eh.o" "{{[^"]*}}libclang_rt.builtins-msp430.a" // LIBS-COMPILER-RT-NEG-NOT: crtbegin.o // LIBS-COMPILER-RT-NEG-NOT: -lssp_nonshared // LIBS-COMPILER-RT-NEG-NOT: -lssp diff --git a/clang/test/Driver/print-libgcc-file-name-clangrt.c b/clang/test/Driver/print-libgcc-file-name-clangrt.c index a902eedc8520..ed740e0d2917 100644 --- a/clang/test/Driver/print-libgcc-file-name-clangrt.c +++ b/clang/test/Driver/print-libgcc-file-name-clangrt.c @@ -5,14 +5,14 @@ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-X8664 %s -// CHECK-CLANGRT-X8664: libclang_rt.builtins.a +// CHECK-CLANGRT-X8664: libclang_rt.builtins-x86_64.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=i386-pc-linux \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-I386 %s -// CHECK-CLANGRT-I386: libclang_rt.builtins.a +// CHECK-CLANGRT-I386: libclang_rt.builtins-i386.a // Check whether alternate arch values map to the correct library. // @@ -27,28 +27,28 @@ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARM %s -// CHECK-CLANGRT-ARM: libclang_rt.builtins.a +// CHECK-CLANGRT-ARM: libclang_rt.builtins-arm.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARM-ANDROID %s -// CHECK-CLANGRT-ARM-ANDROID: libclang_rt.builtins.a +// CHECK-CLANGRT-ARM-ANDROID: libclang_rt.builtins-arm-android.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=arm-linux-gnueabihf \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARMHF %s -// CHECK-CLANGRT-ARMHF: libclang_rt.builtins.a +// CHECK-CLANGRT-ARMHF: libclang_rt.builtins-armhf.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=arm-linux-gnueabi -mfloat-abi=hard \ // RUN: --sysroot=%S/Inputs/resource_dir_with_arch_subdir \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_arch_subdir 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-CLANGRT-ARM-ABI %s -// CHECK-CLANGRT-ARM-ABI: libclang_rt.builtins.a +// CHECK-CLANGRT-ARM-ABI: libclang_rt.builtins-armhf.a // RUN: %clang -rtlib=compiler-rt -print-libgcc-file-name \ // RUN: --target=armv7m-none-eabi \ diff --git a/clang/test/Driver/print-runtime-dir.c b/clang/test/Driver/print-runtime-dir.c index ac1ff7e634b8..550ffef1aaf6 100644 --- a/clang/test/Driver/print-runtime-dir.c +++ b/clang/test/Driver/print-runtime-dir.c @@ -1,3 +1,9 @@ +// Default directory layout +// RUN: %clang -print-runtime-dir --target=x86_64-pc-windows-msvc \ +// RUN: -resource-dir=%S/Inputs/resource_dir \ +// RUN: | FileCheck --check-prefix=PRINT-RUNTIME-DIR -DFILE=%S/Inputs/resource_dir %s +// PRINT-RUNTIME-DIR: [[FILE]]{{/|\\}}lib{{/|\\}}windows + // Per-target directory layout // RUN: %clang -print-runtime-dir --target=x86_64-pc-windows-msvc \ // RUN: -resource-dir=%S/Inputs/resource_dir_with_per_target_subdir \ diff --git a/clang/test/Driver/riscv32-toolchain-extra.c b/clang/test/Driver/riscv32-toolchain-extra.c index aab6b36f3cfc..2d38aa3b545f 100644 --- a/clang/test/Driver/riscv32-toolchain-extra.c +++ b/clang/test/Driver/riscv32-toolchain-extra.c @@ -29,8 +29,8 @@ // C-RV32-BAREMETAL-ILP32-NOGCC: "-internal-isystem" "{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/include" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/bin/riscv32-unknown-elf-ld" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib/crt0.o" -// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/clang_rt.crtbegin.o" +// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/lib/clang_rt.crtbegin-riscv32.o" // C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/bin/../riscv32-unknown-elf/lib" // C-RV32-BAREMETAL-ILP32-NOGCC: "--start-group" "-lc" "-lgloss" "--end-group" -// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/libclang_rt.builtins.a" -// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/riscv32-unknown-unknown-elf/clang_rt.crtend.o" +// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/lib/libclang_rt.builtins-riscv32.a" +// C-RV32-BAREMETAL-ILP32-NOGCC: "{{.*}}/riscv32-nogcc/{{.*}}/lib/clang_rt.crtend-riscv32.o" diff --git a/clang/test/Driver/riscv32-toolchain.c b/clang/test/Driver/riscv32-toolchain.c index 322a6ca2840f..bb2533cdf1bc 100644 --- a/clang/test/Driver/riscv32-toolchain.c +++ b/clang/test/Driver/riscv32-toolchain.c @@ -195,9 +195,9 @@ // RUN: --target=riscv32-unknown-elf --rtlib=compiler-rt --unwindlib=compiler-rt 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV32-RTLIB-COMPILERRT-ILP32 %s // C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}crt0.o" -// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtbegin.o" -// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins.a" -// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend.o" +// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtbegin-riscv32.o" +// C-RV32-RTLIB-COMPILERRT-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins-riscv32.a" +// C-RV32-RTLIB-COMPILERRT-ILP32: "{{.*}}clang_rt.crtend-riscv32.o" // RUN: %clang -### %s --target=riscv32 \ // RUN: --gcc-toolchain=%S/Inputs/basic_riscv32_tree --sysroot= \ diff --git a/clang/test/Driver/riscv64-toolchain-extra.c b/clang/test/Driver/riscv64-toolchain-extra.c index d8d9b5844167..a6ec9b16cc5c 100644 --- a/clang/test/Driver/riscv64-toolchain-extra.c +++ b/clang/test/Driver/riscv64-toolchain-extra.c @@ -29,8 +29,8 @@ // C-RV64-BAREMETAL-LP64-NOGCC: "-internal-isystem" "{{.*}}/riscv64-nogcc/bin/../riscv64-unknown-elf/include" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/bin/riscv64-unknown-elf-ld" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/bin/../riscv64-unknown-elf/lib/crt0.o" -// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/riscv64-unknown-unknown-elf/clang_rt.crtbegin.o" +// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/lib/clang_rt.crtbegin-riscv64.o" // C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/bin/../riscv64-unknown-elf/lib" // C-RV64-BAREMETAL-LP64-NOGCC: "--start-group" "-lc" "-lgloss" "--end-group" -// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/riscv64-unknown-unknown-elf/libclang_rt.builtins.a" -// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/riscv64-unknown-unknown-elf/clang_rt.crtend.o" +// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/lib/libclang_rt.builtins-riscv64.a" +// C-RV64-BAREMETAL-LP64-NOGCC: "{{.*}}/riscv64-nogcc/{{.*}}/lib/clang_rt.crtend-riscv64.o" diff --git a/clang/test/Driver/riscv64-toolchain.c b/clang/test/Driver/riscv64-toolchain.c index b3216de30754..381ee58c470c 100644 --- a/clang/test/Driver/riscv64-toolchain.c +++ b/clang/test/Driver/riscv64-toolchain.c @@ -151,9 +151,9 @@ // RUN: --target=riscv64-unknown-elf --rtlib=compiler-rt --unwindlib=compiler-rt 2>&1 \ // RUN: | FileCheck -check-prefix=C-RV64-RTLIB-COMPILERRT-LP64 %s // C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}crt0.o" -// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtbegin.o" -// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins.a" -// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend.o" +// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtbegin-riscv64.o" +// C-RV64-RTLIB-COMPILERRT-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "{{.*}}libclang_rt.builtins-riscv64.a" +// C-RV64-RTLIB-COMPILERRT-LP64: "{{.*}}clang_rt.crtend-riscv64.o" // RUN: %clang -### %s --target=riscv64 \ // RUN: --gcc-toolchain=%S/Inputs/basic_riscv64_tree --sysroot= \ diff --git a/clang/test/Driver/sanitizer-ld.c b/clang/test/Driver/sanitizer-ld.c index 1d52fc126095..53e536d77292 100644 --- a/clang/test/Driver/sanitizer-ld.c +++ b/clang/test/Driver/sanitizer-ld.c @@ -111,7 +111,7 @@ // CHECK-ASAN-FREEBSD: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-FREEBSD-NOT: "-lc" // CHECK-ASAN-FREEBSD-NOT: libclang_rt.asan_cxx -// CHECK-ASAN-FREEBSD: freebsd{{/|\\+}}libclang_rt.asan.a" +// CHECK-ASAN-FREEBSD: freebsd{{/|\\+}}libclang_rt.asan-i386.a" // CHECK-ASAN-FREEBSD-NOT: libclang_rt.asan_cxx // CHECK-ASAN-FREEBSD-NOT: "--dynamic-list" // CHECK-ASAN-FREEBSD: "--export-dynamic" @@ -135,8 +135,8 @@ // // CHECK-ASAN-LINUX-CXX: "{{(.*[^-.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-LINUX-CXX-NOT: "-lc" -// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan.a" "--no-whole-archive" -// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan_cxx.a" "--no-whole-archive" +// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan-i386.a" "--no-whole-archive" +// CHECK-ASAN-LINUX-CXX: "--whole-archive" "{{.*}}libclang_rt.asan_cxx-i386.a" "--no-whole-archive" // CHECK-ASAN-LINUX-CXX-NOT: "--dynamic-list" // CHECK-ASAN-LINUX-CXX: "--export-dynamic" // CHECK-ASAN-LINUX-CXX: stdc++ @@ -163,7 +163,7 @@ // // CHECK-ASAN-ARM: "{{(.*[^.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-ARM-NOT: "-lc" -// CHECK-ASAN-ARM: libclang_rt.asan.a" +// CHECK-ASAN-ARM: libclang_rt.asan-arm.a" // // RUN: %clang -### %s 2>&1 \ // RUN: --target=armv7l-linux-gnueabi -fuse-ld=ld -fsanitize=address \ @@ -172,7 +172,7 @@ // // CHECK-ASAN-ARMv7: "{{(.*[^.0-9A-Z_a-z])?}}ld{{(.exe)?}}" // CHECK-ASAN-ARMv7-NOT: "-lc" -// CHECK-ASAN-ARMv7: libclang_rt.asan.a" +// CHECK-ASAN-ARMv7: libclang_rt.asan-arm.a" // RUN: %clang -### %s 2>&1 \ // RUN: --target=arm-linux-androideabi -fuse-ld=ld -fsanitize=address \ @@ -184,7 +184,7 @@ // CHECK-ASAN-ANDROID-NOT: "-lc" // CHECK-ASAN-ANDROID-NOT: "-lpthread" // CHECK-ASAN-ANDROID-NOT: "-lresolv" -// CHECK-ASAN-ANDROID: libclang_rt.asan.so" +// CHECK-ASAN-ANDROID: libclang_rt.asan-arm-android.so" // CHECK-ASAN-ANDROID-NOT: "-lpthread" // CHECK-ASAN-ANDROID-NOT: "-lresolv" @@ -195,7 +195,7 @@ // RUN: | FileCheck --check-prefix=CHECK-ASAN-ANDROID-STATICLIBASAN %s // // CHECK-ASAN-ANDROID-STATICLIBASAN: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" -// CHECK-ASAN-ANDROID-STATICLIBASAN: libclang_rt.asan.a" +// CHECK-ASAN-ANDROID-STATICLIBASAN: libclang_rt.asan-arm-android.a" // CHECK-ASAN-ANDROID-STATICLIBASAN-NOT: "-lpthread" // CHECK-ASAN-ANDROID-STATICLIBASAN-NOT: "-lrt" // CHECK-ASAN-ANDROID-STATICLIBASAN-NOT: "-lresolv" @@ -210,7 +210,7 @@ // CHECK-UBSAN-ANDROID-NOT: "-lc" // CHECK-UBSAN-ANDROID-NOT: "-lpthread" // CHECK-UBSAN-ANDROID-NOT: "-lresolv" -// CHECK-UBSAN-ANDROID: libclang_rt.ubsan_standalone.so" +// CHECK-UBSAN-ANDROID: libclang_rt.ubsan_standalone-arm-android.so" // CHECK-UBSAN-ANDROID-NOT: "-lpthread" // CHECK-UBSAN-ANDROID-NOT: "-lresolv" @@ -221,7 +221,7 @@ // RUN: | FileCheck --check-prefix=CHECK-UBSAN-ANDROID-STATICLIBASAN %s // // CHECK-UBSAN-ANDROID-STATICLIBASAN: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" -// CHECK-UBSAN-ANDROID-STATICLIBASAN: libclang_rt.ubsan_standalone.a" +// CHECK-UBSAN-ANDROID-STATICLIBASAN: libclang_rt.ubsan_standalone-arm-android.a" // CHECK-UBSAN-ANDROID-STATICLIBASAN-NOT: "-lpthread" // CHECK-UBSAN-ANDROID-STATICLIBASAN-NOT: "-lrt" // CHECK-UBSAN-ANDROID-STATICLIBASAN-NOT: "-lresolv" @@ -237,7 +237,7 @@ // CHECK-ASAN-ANDROID-X86-NOT: "-lc" // CHECK-ASAN-ANDROID-X86-NOT: "-lpthread" // CHECK-ASAN-ANDROID-X86-NOT: "-lresolv" -// CHECK-ASAN-ANDROID-X86: libclang_rt.asan.so" +// CHECK-ASAN-ANDROID-X86: libclang_rt.asan-i686-android.so" // CHECK-ASAN-ANDROID-X86-NOT: "-lpthread" // CHECK-ASAN-ANDROID-X86-NOT: "-lresolv" // @@ -257,7 +257,7 @@ // // CHECK-ASAN-ANDROID-SHARED: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" // CHECK-ASAN-ANDROID-SHARED-NOT: "-lc" -// CHECK-ASAN-ANDROID-SHARED: libclang_rt.asan.so" +// CHECK-ASAN-ANDROID-SHARED: libclang_rt.asan-arm-android.so" // CHECK-ASAN-ANDROID-SHARED-NOT: "-lpthread" // CHECK-ASAN-ANDROID-SHARED-NOT: "-lresolv" @@ -347,7 +347,7 @@ // CHECK-UBSAN-LINUX: "{{.*}}ld{{(.exe)?}}" // CHECK-UBSAN-LINUX-NOT: libclang_rt.asan // CHECK-UBSAN-LINUX-NOT: libclang_rt.ubsan_standalone_cxx -// CHECK-UBSAN-LINUX: "--whole-archive" "{{.*}}libclang_rt.ubsan_standalone.a" "--no-whole-archive" +// CHECK-UBSAN-LINUX: "--whole-archive" "{{.*}}libclang_rt.ubsan_standalone-x32.a" "--no-whole-archive" // CHECK-UBSAN-LINUX-NOT: libclang_rt.asan // CHECK-UBSAN-LINUX-NOT: libclang_rt.ubsan_standalone_cxx // CHECK-UBSAN-LINUX-NOT: "-lstdc++" @@ -678,7 +678,7 @@ // RUN: --sysroot=%S/Inputs/basic_android_tree \ // RUN: | FileCheck --check-prefix=CHECK-CFI-CROSS-DSO-DIAG-ANDROID %s // CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{.*}}ld{{(.exe)?}}" -// CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{[^"]*}}libclang_rt.ubsan_standalone.so" +// CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "{{[^"]*}}libclang_rt.ubsan_standalone-aarch64-android.so" // CHECK-CFI-CROSS-DSO-DIAG-ANDROID: "--export-dynamic-symbol=__cfi_check" // RUN: %clangxx -fsanitize=address -### %s 2>&1 \ @@ -929,7 +929,7 @@ // CHECK-SCUDO-ANDROID: "-pie" // CHECK-SCUDO-ANDROID-NOT: "-lpthread" // CHECK-SCUDO-ANDROID-NOT: "-lresolv" -// CHECK-SCUDO-ANDROID: libclang_rt.scudo_standalone.so" +// CHECK-SCUDO-ANDROID: libclang_rt.scudo_standalone-arm-android.so" // CHECK-SCUDO-ANDROID-NOT: "-lpthread" // CHECK-SCUDO-ANDROID-NOT: "-lresolv" @@ -940,7 +940,7 @@ // RUN: | FileCheck --check-prefix=CHECK-SCUDO-ANDROID-STATIC %s // CHECK-SCUDO-ANDROID-STATIC: "{{(.*[^.0-9A-Z_a-z])?}}ld.lld{{(.exe)?}}" // CHECK-SCUDO-ANDROID-STATIC: "-pie" -// CHECK-SCUDO-ANDROID-STATIC: "--whole-archive" "{{.*}}libclang_rt.scudo_standalone.a" "--no-whole-archive" +// CHECK-SCUDO-ANDROID-STATIC: "--whole-archive" "{{.*}}libclang_rt.scudo_standalone-arm-android.a" "--no-whole-archive" // CHECK-SCUDO-ANDROID-STATIC-NOT: "-lstdc++" // CHECK-SCUDO-ANDROID-STATIC-NOT: "-lpthread" // CHECK-SCUDO-ANDROID-STATIC-NOT: "-lrt" diff --git a/clang/test/Driver/wasm-toolchain.c b/clang/test/Driver/wasm-toolchain.c index dabf0ac2433b..88590a3ba4c4 100644 --- a/clang/test/Driver/wasm-toolchain.c +++ b/clang/test/Driver/wasm-toolchain.c @@ -17,42 +17,42 @@ // RUN: %clang -### --target=wasm32-unknown-unknown --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK %s // LINK: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C link command-line with optimization with unknown OS. // RUN: %clang -### -O2 --target=wasm32-unknown-unknown --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT %s // LINK_OPT: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C link command-line with known OS. // RUN: %clang -### --target=wasm32-wasi --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN %s // LINK_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // -shared should be passed through to `wasm-ld` and include crt1-reactor.o with a known OS. // RUN: %clang -### -shared -mexec-model=reactor --target=wasm32-wasi --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN_SHARED %s // LINK_KNOWN_SHARED: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN_SHARED: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_KNOWN_SHARED: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // -shared should be passed through to `wasm-ld` and include crt1-reactor.o with an unknown OS. // RUN: %clang -### -shared -mexec-model=reactor --target=wasm32-unknown-unknown --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_UNKNOWN_SHARED %s // LINK_UNKNOWN_SHARED: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_UNKNOWN_SHARED: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_UNKNOWN_SHARED: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "-shared" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C link command-line with optimization with known OS. // RUN: %clang -### -O2 --target=wasm32-wasi --sysroot=/foo %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_KNOWN %s // LINK_OPT_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C compile command-line with known OS. @@ -180,12 +180,12 @@ // RUN: %clang -### %s --target=wasm32-unknown-unknown --sysroot=%s/no-sysroot-there -mexec-model=command 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-COMMAND %s // CHECK-COMMAND: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// CHECK-COMMAND: wasm-ld{{.*}}" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// CHECK-COMMAND: wasm-ld{{.*}}" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // RUN: %clang -### %s --target=wasm32-unknown-unknown --sysroot=%s/no-sysroot-there -mexec-model=reactor 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-REACTOR %s // CHECK-REACTOR: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// CHECK-REACTOR: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// CHECK-REACTOR: wasm-ld{{.*}}" "crt1-reactor.o" "--entry" "_initialize" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // -fPIC implies +mutable-globals @@ -204,7 +204,7 @@ // RUN: %clang -### -O2 --target=wasm32-wasip2 %s --sysroot /foo 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_WASIP2 %s // LINK_WASIP2: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_WASIP2: wasm-component-ld{{.*}}" "-L/foo/lib/wasm32-wasip2" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_WASIP2: wasm-component-ld{{.*}}" "-L/foo/lib/wasm32-wasip2" "crt1.o" "[[temp]]" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // Test that on `wasm32-wasip2` the `wasm-component-ld` programs is told where // to find `wasm-ld` by default. diff --git a/clang/test/Driver/wasm-toolchain.cpp b/clang/test/Driver/wasm-toolchain.cpp index ba1c55b33edc..4af011097021 100644 --- a/clang/test/Driver/wasm-toolchain.cpp +++ b/clang/test/Driver/wasm-toolchain.cpp @@ -17,48 +17,48 @@ // RUN: %clangxx -### --target=wasm32-unknown-unknown --sysroot=/foo --stdlib=libc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK %s // LINK: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // RUN: %clangxx -### --target=wasm32-unknown-unknown --sysroot=/foo --stdlib=libstdc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_STDCXX %s // LINK_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C++ link command-line with optimization with unknown OS. // RUN: %clangxx -### -O2 --target=wasm32-unknown-unknown --sysroot=/foo %s --stdlib=libc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT %s // LINK_OPT: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_OPT: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // RUN: %clangxx -### -O2 --target=wasm32-unknown-unknown --sysroot=/foo %s --stdlib=libstdc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_STDCXX %s // LINK_OPT_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_OPT_STDCXX: wasm-ld{{.*}}" "-L/foo/lib" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C++ link command-line with known OS. // RUN: %clangxx -### --target=wasm32-wasi --sysroot=/foo --stdlib=libc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN %s // LINK_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // RUN: %clangxx -### --target=wasm32-wasi --sysroot=/foo --stdlib=libstdc++ %s 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_KNOWN_STDCXX %s // LINK_KNOWN_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C++ link command-line with optimization with known OS. // RUN: %clangxx -### -O2 --target=wasm32-wasi --sysroot=/foo %s --stdlib=libc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_KNOWN %s // LINK_OPT_KNOWN: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_OPT_KNOWN: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lc++" "-lc++abi" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // RUN: %clangxx -### -O2 --target=wasm32-wasi --sysroot=/foo %s --stdlib=libstdc++ 2>&1 \ // RUN: | FileCheck -check-prefix=LINK_OPT_KNOWN_STDCXX %s // LINK_OPT_KNOWN_STDCXX: "-cc1" {{.*}} "-o" "[[temp:[^"]*]]" -// LINK_OPT_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins.a" "-o" "a.out" +// LINK_OPT_KNOWN_STDCXX: wasm-ld{{.*}}" "-L/foo/lib/wasm32-wasi" "crt1.o" "[[temp]]" "-lstdc++" "-lc" "{{.*[/\\]}}libclang_rt.builtins-wasm32.a" "-o" "a.out" // A basic C++ compile command-line with known OS. diff --git a/clang/test/Driver/windows-cross.c b/clang/test/Driver/windows-cross.c index f6e831f00e13..75490b992d78 100644 --- a/clang/test/Driver/windows-cross.c +++ b/clang/test/Driver/windows-cross.c @@ -11,32 +11,32 @@ // RUN: %clang -### -target armv7-windows-itanium --sysroot %s/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -rtlib=compiler-rt -stdlib=libstdc++ -o /dev/null %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-RTLIB -// CHECK-RTLIB: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" +// CHECK-RTLIB: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -rtlib=compiler-rt -stdlib=libc++ -o /dev/null %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-C-LIBCXX -// CHECK-C-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" +// CHECK-C-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" // RUN: %clangxx -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -rtlib=compiler-rt -stdlib=libc++ -o /dev/null %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-LIBCXX -// CHECK-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lc++" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" +// CHECK-LIBCXX: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-Bdynamic" "--entry" "mainCRTStartup" "--allow-multiple-definition" "-o" "{{[^"]*}}" "{{.*}}.o" "-lc++" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SHARED -// CHECK-SHARED: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" +// CHECK-SHARED: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -static -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SHARED-STATIC -// CHECK-SHARED-STATIC: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bstatic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" +// CHECK-SHARED-STATIC: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bstatic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %s/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -nostartfiles -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-NOSTARTFILES -// CHECK-NOSTARTFILES: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins.lib" +// CHECK-NOSTARTFILES: {{[/\\]}}ld" "--sysroot={{.*}}/Inputs/Windows/ARM/8.1" "-m" "thumb2pe" "-shared" "-Bdynamic" "--enable-auto-image-base" "--entry" "_DllMainCRTStartup" "--allow-multiple-definition" "-o" "shared.dll" "--out-implib" "shared.lib" "{{.*}}.o" "-lmsvcrt" "{{.*[\\/]}}clang_rt.builtins-arm.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=ld -shared -rtlib=compiler-rt -stdlib=libc++ -nostartfiles -nodefaultlibs -o shared.dll %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-STANDALONE @@ -52,19 +52,19 @@ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-ADDRESS // CHECK-SANITIZE-ADDRESS: "-fsanitize=address" -// CHECK-SANITIZE-ADDRESS: "{{.*}}clang_rt.asan_dll_thunk.lib" +// CHECK-SANITIZE-ADDRESS: "{{.*}}clang_rt.asan_dll_thunk-arm.lib" // RUN: %clang -### -target armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=lld-link2 -o test.exe -fsanitize=address -x c++ %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-ADDRESS-EXE // CHECK-SANITIZE-ADDRESS-EXE: "-fsanitize=address" -// CHECK-SANITIZE-ADDRESS-EXE: "{{.*}}clang_rt.asan_dynamic.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk.lib" "--undefined" "__asan_seh_interceptor" +// CHECK-SANITIZE-ADDRESS-EXE: "{{.*}}clang_rt.asan_dynamic-arm.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk-arm.lib" "--undefined" "__asan_seh_interceptor" // RUN: %clang -### -target i686-windows-itanium -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=lld-link2 -o test.exe -fsanitize=address -x c++ %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-ADDRESS-EXE-X86 // CHECK-SANITIZE-ADDRESS-EXE-X86: "-fsanitize=address" -// CHECK-SANITIZE-ADDRESS-EXE-X86: "{{.*}}clang_rt.asan_dynamic.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk.lib" "--undefined" "___asan_seh_interceptor" +// CHECK-SANITIZE-ADDRESS-EXE-X86: "{{.*}}clang_rt.asan_dynamic-i386.lib" "{{.*}}clang_rt.asan_dynamic_runtime_thunk-i386.lib" "--undefined" "___asan_seh_interceptor" // RUN: not %clang -### --target=armv7-windows-itanium --sysroot %S/Inputs/Windows/ARM/8.1 -B %S/Inputs/Windows/ARM/8.1/usr/bin -fuse-ld=lld-link2 -shared -o shared.dll -fsanitize=tsan -x c++ %s 2>&1 \ // RUN: | FileCheck %s --check-prefix CHECK-SANITIZE-TSAN diff --git a/clang/test/Driver/zos-ld.c b/clang/test/Driver/zos-ld.c index 87d169936e12..4d4decdd0e65 100644 --- a/clang/test/Driver/zos-ld.c +++ b/clang/test/Driver/zos-ld.c @@ -14,7 +14,7 @@ // C-LD-SAME: "-S" "//'SYS1.CSSLIB'" // C-LD-SAME: "//'CEE.SCEELIB(CELQS001)'" // C-LD-SAME: "//'CEE.SCEELIB(CELQS003)'" -// C-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" +// C-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" // 2. General C link for dll // RUN: %clang -### --shared --target=s390x-ibm-zos %s 2>&1 \ @@ -30,7 +30,7 @@ // C-LD-DLL-SAME: "-S" "//'SYS1.CSSLIB'" // C-LD-DLL-SAME: "//'CEE.SCEELIB(CELQS001)'" // C-LD-DLL-SAME: "//'CEE.SCEELIB(CELQS003)'" -// C-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" +// C-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" // 3. General C++ link for executable // RUN: %clangxx -### --target=s390x-ibm-zos %s 2>&1 \ @@ -52,7 +52,7 @@ // CXX-LD-SAME: "//'CEE.SCEELIB(CRTDQCXA)'" // CXX-LD-SAME: "//'CEE.SCEELIB(CRTDQXLA)'" // CXX-LD-SAME: "//'CEE.SCEELIB(CRTDQUNW)'" -// CXX-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" +// CXX-LD-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" // 4. General C++ link for dll // RUN: %clangxx -### --shared --target=s390x-ibm-zos %s 2>&1 \ @@ -74,7 +74,7 @@ // CXX-LD-DLL-SAME: "//'CEE.SCEELIB(CRTDQCXA)'" // CXX-LD-DLL-SAME: "//'CEE.SCEELIB(CRTDQXLA)'" // CXX-LD-DLL-SAME: "//'CEE.SCEELIB(CRTDQUNW)'" -// CXX-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" +// CXX-LD-DLL-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" // 5. C++ link for executable w/ -mzos-hlq-le=, -mzos-hlq-csslib= // RUN: %clangxx -### --target=s390x-ibm-zos %s 2>&1 \ @@ -97,7 +97,7 @@ // CXX-LD5-SAME: "//'AAAA.SCEELIB(CRTDQCXA)'" // CXX-LD5-SAME: "//'AAAA.SCEELIB(CRTDQXLA)'" // CXX-LD5-SAME: "//'AAAA.SCEELIB(CRTDQUNW)'" -// CXX-LD5-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" +// CXX-LD5-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" // 6. C++ link for executable w/ -mzos-hlq-clang= // RUN: %clangxx -### --target=s390x-ibm-zos %s 2>&1 \ @@ -120,4 +120,4 @@ // CXX-LD6-SAME: "//'AAAA.SCEELIB(CRTDQCXA)'" // CXX-LD6-SAME: "//'AAAA.SCEELIB(CRTDQXLA)'" // CXX-LD6-SAME: "//'AAAA.SCEELIB(CRTDQUNW)'" -// CXX-LD6-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}s390x-ibm-zos{{/|\\\\}}libclang_rt.builtins.a" +// CXX-LD6-SAME: "[[RESOURCE_DIR]]{{/|\\\\}}lib{{/|\\\\}}zos{{/|\\\\}}libclang_rt.builtins-s390x.a" diff --git a/flang/test/Driver/msvc-dependent-lib-flags.f90 b/flang/test/Driver/msvc-dependent-lib-flags.f90 index 643dbe9e949c..7c1f962e339f 100644 --- a/flang/test/Driver/msvc-dependent-lib-flags.f90 +++ b/flang/test/Driver/msvc-dependent-lib-flags.f90 @@ -4,7 +4,7 @@ ! RUN: %flang -### --target=aarch64-windows-msvc -fms-runtime-lib=dll_dbg %S/Inputs/hello.f90 -v 2>&1 | FileCheck %s --check-prefixes=MSVC-DLL-DEBUG ! MSVC: -fc1 -! MSVC-SAME: --dependent-lib=clang_rt.builtins.lib +! MSVC-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib ! MSVC-SAME: -D_MT ! MSVC-SAME: --dependent-lib=libcmt ! MSVC-SAME: --dependent-lib=Fortran_main.static.lib @@ -12,7 +12,7 @@ ! MSVC-SAME: --dependent-lib=FortranDecimal.static.lib ! MSVC-DEBUG: -fc1 -! MSVC-DEBUG-SAME: --dependent-lib=clang_rt.builtins.lib +! MSVC-DEBUG-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib ! MSVC-DEBUG-SAME: -D_MT ! MSVC-DEBUG-SAME: -D_DEBUG ! MSVC-DEBUG-SAME: --dependent-lib=libcmtd @@ -21,7 +21,7 @@ ! MSVC-DEBUG-SAME: --dependent-lib=FortranDecimal.static_dbg.lib ! MSVC-DLL: -fc1 -! MSVC-DLL-SAME: --dependent-lib=clang_rt.builtins.lib +! MSVC-DLL-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib ! MSVC-DLL-SAME: -D_MT ! MSVC-DLL-SAME: -D_DLL ! MSVC-DLL-SAME: --dependent-lib=msvcrt @@ -30,7 +30,7 @@ ! MSVC-DLL-SAME: --dependent-lib=FortranDecimal.dynamic.lib ! MSVC-DLL-DEBUG: -fc1 -! MSVC-DLL-DEBUG-SAME: --dependent-lib=clang_rt.builtins.lib +! MSVC-DLL-DEBUG-SAME: --dependent-lib=clang_rt.builtins-aarch64.lib ! MSVC-DLL-DEBUG-SAME: -D_MT ! MSVC-DLL-DEBUG-SAME: -D_DEBUG ! MSVC-DLL-DEBUG-SAME: -D_DLL -- GitLab From fca51911d4668b3a6b79eb956327eb81fad3f40c Mon Sep 17 00:00:00 2001 From: Bill Wendling <5993918+bwendling@users.noreply.github.com> Date: Thu, 11 Apr 2024 00:33:40 +0000 Subject: [PATCH 469/695] [NFC][Clang] Improve const correctness for IdentifierInfo (#79365) The IdentifierInfo isn't typically modified. Use 'const' wherever possible. --- clang/include/clang/AST/ASTContext.h | 4 +- clang/include/clang/AST/Decl.h | 37 +++--- clang/include/clang/AST/DeclObjC.h | 89 +++++++------- clang/include/clang/AST/DeclTemplate.h | 8 +- clang/include/clang/AST/ExprCXX.h | 10 +- clang/include/clang/AST/ExternalASTSource.h | 2 +- clang/include/clang/AST/NestedNameSpecifier.h | 6 +- clang/include/clang/Analysis/SelectorExtras.h | 4 +- clang/include/clang/Basic/IdentifierTable.h | 25 ++-- .../clang/Lex/ExternalPreprocessorSource.h | 2 +- clang/include/clang/Lex/MacroInfo.h | 8 +- clang/include/clang/Lex/Preprocessor.h | 9 +- clang/include/clang/Parse/Parser.h | 16 +-- .../include/clang/Sema/CodeCompleteConsumer.h | 9 +- clang/include/clang/Sema/DeclSpec.h | 23 ++-- clang/include/clang/Sema/ParsedTemplate.h | 7 +- clang/include/clang/Sema/Sema.h | 89 +++++++------- clang/include/clang/Serialization/ASTReader.h | 10 +- clang/lib/ARCMigrate/ObjCMT.cpp | 7 +- clang/lib/ARCMigrate/TransAPIUses.cpp | 2 +- clang/lib/AST/ASTContext.cpp | 11 +- clang/lib/AST/ASTImporter.cpp | 6 +- clang/lib/AST/Decl.cpp | 18 +-- clang/lib/AST/DeclObjC.cpp | 94 ++++++--------- clang/lib/AST/DeclTemplate.cpp | 14 +-- clang/lib/AST/NSAPI.cpp | 104 ++++++---------- clang/lib/AST/NestedNameSpecifier.cpp | 18 +-- clang/lib/AST/SelectorLocationsKind.cpp | 4 +- clang/lib/AST/StmtPrinter.cpp | 4 +- clang/lib/AST/StmtProfile.cpp | 6 +- clang/lib/Analysis/ObjCNoReturn.cpp | 5 +- clang/lib/Basic/IdentifierTable.cpp | 16 +-- clang/lib/CodeGen/CGBlocks.cpp | 4 +- clang/lib/CodeGen/CGCUDANV.cpp | 2 +- clang/lib/CodeGen/CGDecl.cpp | 4 +- clang/lib/CodeGen/CGObjC.cpp | 23 ++-- clang/lib/CodeGen/CGObjCMac.cpp | 13 +- clang/lib/CodeGen/CodeGenFunction.cpp | 2 +- clang/lib/CodeGen/CodeGenModule.cpp | 6 +- .../Frontend/Rewrite/RewriteModernObjC.cpp | 2 +- clang/lib/Lex/HeaderSearch.cpp | 3 +- clang/lib/Lex/MacroInfo.cpp | 2 +- clang/lib/Lex/PPLexerChange.cpp | 9 +- clang/lib/Lex/PPMacroExpansion.cpp | 4 +- clang/lib/Lex/Preprocessor.cpp | 2 +- clang/lib/Parse/ParseDecl.cpp | 2 +- clang/lib/Parse/ParseDeclCXX.cpp | 2 +- clang/lib/Parse/ParseExprCXX.cpp | 5 +- clang/lib/Parse/ParseObjc.cpp | 12 +- clang/lib/Parse/ParseTemplate.cpp | 4 +- clang/lib/Sema/CodeCompleteConsumer.cpp | 3 +- clang/lib/Sema/Sema.cpp | 5 +- clang/lib/Sema/SemaCodeComplete.cpp | 112 +++++++++--------- clang/lib/Sema/SemaDecl.cpp | 21 ++-- clang/lib/Sema/SemaDeclCXX.cpp | 9 +- clang/lib/Sema/SemaDeclObjC.cpp | 23 ++-- clang/lib/Sema/SemaExprCXX.cpp | 24 ++-- clang/lib/Sema/SemaExprObjC.cpp | 17 ++- clang/lib/Sema/SemaObjCProperty.cpp | 4 +- clang/lib/Sema/SemaOpenMP.cpp | 2 +- clang/lib/Sema/SemaPseudoObject.cpp | 48 ++++---- clang/lib/Sema/SemaStmt.cpp | 8 +- clang/lib/Sema/SemaTemplate.cpp | 35 +++--- clang/lib/Serialization/ASTCommon.cpp | 2 +- clang/lib/Serialization/ASTReader.cpp | 14 +-- clang/lib/Serialization/ASTWriter.cpp | 18 +-- .../Checkers/CheckObjCDealloc.cpp | 4 +- .../Checkers/LocalizationChecker.cpp | 108 ++++++++--------- .../Checkers/NullabilityChecker.cpp | 3 +- .../Checkers/ObjCMissingSuperCallChecker.cpp | 2 +- .../Checkers/ObjCSuperDeallocChecker.cpp | 4 +- clang/tools/libclang/CIndexCodeCompletion.cpp | 10 +- .../Plugins/ExpressionParser/Clang/ASTUtils.h | 2 +- .../ExpressionParser/Clang/ClangASTSource.cpp | 7 +- .../AppleObjCRuntime/AppleObjCDeclVendor.cpp | 4 +- .../TypeSystem/Clang/TypeSystemClang.cpp | 11 +- 76 files changed, 602 insertions(+), 666 deletions(-) diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index 08f71051e6cb..28f8d67811f0 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -3411,13 +3411,13 @@ const StreamingDiagnostic &operator<<(const StreamingDiagnostic &DB, /// Utility function for constructing a nullary selector. inline Selector GetNullarySelector(StringRef name, ASTContext &Ctx) { - IdentifierInfo* II = &Ctx.Idents.get(name); + const IdentifierInfo *II = &Ctx.Idents.get(name); return Ctx.Selectors.getSelector(0, &II); } /// Utility function for constructing an unary selector. inline Selector GetUnarySelector(StringRef name, ASTContext &Ctx) { - IdentifierInfo* II = &Ctx.Idents.get(name); + const IdentifierInfo *II = &Ctx.Idents.get(name); return Ctx.Selectors.getSelector(1, &II); } diff --git a/clang/include/clang/AST/Decl.h b/clang/include/clang/AST/Decl.h index 5f1f83bb0028..ed6790acdfc7 100644 --- a/clang/include/clang/AST/Decl.h +++ b/clang/include/clang/AST/Decl.h @@ -1731,7 +1731,7 @@ public: static ImplicitParamDecl *CreateDeserialized(ASTContext &C, unsigned ID); ImplicitParamDecl(ASTContext &C, DeclContext *DC, SourceLocation IdLoc, - IdentifierInfo *Id, QualType Type, + const IdentifierInfo *Id, QualType Type, ImplicitParamKind ParamKind) : VarDecl(ImplicitParam, C, DC, IdLoc, IdLoc, Id, Type, /*TInfo=*/nullptr, SC_None) { @@ -1765,7 +1765,7 @@ public: protected: ParmVarDecl(Kind DK, ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, QualType T, + SourceLocation IdLoc, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, StorageClass S, Expr *DefArg) : VarDecl(DK, C, DC, StartLoc, IdLoc, Id, T, TInfo, S) { assert(ParmVarDeclBits.HasInheritedDefaultArg == false); @@ -1777,10 +1777,10 @@ protected: public: static ParmVarDecl *Create(ASTContext &C, DeclContext *DC, - SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, - QualType T, TypeSourceInfo *TInfo, - StorageClass S, Expr *DefArg); + SourceLocation StartLoc, SourceLocation IdLoc, + const IdentifierInfo *Id, QualType T, + TypeSourceInfo *TInfo, StorageClass S, + Expr *DefArg); static ParmVarDecl *CreateDeserialized(ASTContext &C, unsigned ID); @@ -3095,7 +3095,7 @@ class FieldDecl : public DeclaratorDecl, public Mergeable { protected: FieldDecl(Kind DK, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, QualType T, + SourceLocation IdLoc, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, Expr *BW, bool Mutable, InClassInitStyle InitStyle) : DeclaratorDecl(DK, DC, IdLoc, Id, T, TInfo, StartLoc), BitField(false), @@ -3111,7 +3111,7 @@ public: static FieldDecl *Create(const ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, QualType T, + const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, Expr *BW, bool Mutable, InClassInitStyle InitStyle); @@ -3332,8 +3332,9 @@ public: friend class ASTDeclReader; static IndirectFieldDecl *Create(ASTContext &C, DeclContext *DC, - SourceLocation L, IdentifierInfo *Id, - QualType T, llvm::MutableArrayRef CH); + SourceLocation L, const IdentifierInfo *Id, + QualType T, + llvm::MutableArrayRef CH); static IndirectFieldDecl *CreateDeserialized(ASTContext &C, unsigned ID); @@ -3381,9 +3382,9 @@ class TypeDecl : public NamedDecl { void anchor() override; protected: - TypeDecl(Kind DK, DeclContext *DC, SourceLocation L, IdentifierInfo *Id, + TypeDecl(Kind DK, DeclContext *DC, SourceLocation L, const IdentifierInfo *Id, SourceLocation StartL = SourceLocation()) - : NamedDecl(DK, DC, L, Id), LocStart(StartL) {} + : NamedDecl(DK, DC, L, Id), LocStart(StartL) {} public: // Low-level accessor. If you just want the type defined by this node, @@ -3425,7 +3426,7 @@ class TypedefNameDecl : public TypeDecl, public Redeclarable { protected: TypedefNameDecl(Kind DK, ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, TypeSourceInfo *TInfo) + const IdentifierInfo *Id, TypeSourceInfo *TInfo) : TypeDecl(DK, DC, IdLoc, Id, StartLoc), redeclarable_base(C), MaybeModedTInfo(TInfo, 0) {} @@ -3512,13 +3513,14 @@ private: /// type specifier. class TypedefDecl : public TypedefNameDecl { TypedefDecl(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, TypeSourceInfo *TInfo) + SourceLocation IdLoc, const IdentifierInfo *Id, + TypeSourceInfo *TInfo) : TypedefNameDecl(Typedef, C, DC, StartLoc, IdLoc, Id, TInfo) {} public: static TypedefDecl *Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, TypeSourceInfo *TInfo); + const IdentifierInfo *Id, TypeSourceInfo *TInfo); static TypedefDecl *CreateDeserialized(ASTContext &C, unsigned ID); SourceRange getSourceRange() const override LLVM_READONLY; @@ -3535,14 +3537,15 @@ class TypeAliasDecl : public TypedefNameDecl { TypeAliasTemplateDecl *Template; TypeAliasDecl(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, TypeSourceInfo *TInfo) + SourceLocation IdLoc, const IdentifierInfo *Id, + TypeSourceInfo *TInfo) : TypedefNameDecl(TypeAlias, C, DC, StartLoc, IdLoc, Id, TInfo), Template(nullptr) {} public: static TypeAliasDecl *Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, TypeSourceInfo *TInfo); + const IdentifierInfo *Id, TypeSourceInfo *TInfo); static TypeAliasDecl *CreateDeserialized(ASTContext &C, unsigned ID); SourceRange getSourceRange() const override LLVM_READONLY; diff --git a/clang/include/clang/AST/DeclObjC.h b/clang/include/clang/AST/DeclObjC.h index f8f894b4b10d..b8d17dd06d15 100644 --- a/clang/include/clang/AST/DeclObjC.h +++ b/clang/include/clang/AST/DeclObjC.h @@ -772,7 +772,7 @@ private: // Synthesize ivar for this property ObjCIvarDecl *PropertyIvarDecl = nullptr; - ObjCPropertyDecl(DeclContext *DC, SourceLocation L, IdentifierInfo *Id, + ObjCPropertyDecl(DeclContext *DC, SourceLocation L, const IdentifierInfo *Id, SourceLocation AtLocation, SourceLocation LParenLocation, QualType T, TypeSourceInfo *TSI, PropertyControl propControl) : NamedDecl(ObjCProperty, DC, L, Id), AtLoc(AtLocation), @@ -782,10 +782,12 @@ private: PropertyImplementation(propControl) {} public: - static ObjCPropertyDecl * - Create(ASTContext &C, DeclContext *DC, SourceLocation L, IdentifierInfo *Id, - SourceLocation AtLocation, SourceLocation LParenLocation, QualType T, - TypeSourceInfo *TSI, PropertyControl propControl = None); + static ObjCPropertyDecl *Create(ASTContext &C, DeclContext *DC, + SourceLocation L, const IdentifierInfo *Id, + SourceLocation AtLocation, + SourceLocation LParenLocation, QualType T, + TypeSourceInfo *TSI, + PropertyControl propControl = None); static ObjCPropertyDecl *CreateDeserialized(ASTContext &C, unsigned ID); @@ -952,7 +954,7 @@ class ObjCContainerDecl : public NamedDecl, public DeclContext { void anchor() override; public: - ObjCContainerDecl(Kind DK, DeclContext *DC, IdentifierInfo *Id, + ObjCContainerDecl(Kind DK, DeclContext *DC, const IdentifierInfo *Id, SourceLocation nameLoc, SourceLocation atStartLoc); // Iterator access to instance/class properties. @@ -1240,7 +1242,7 @@ class ObjCInterfaceDecl : public ObjCContainerDecl llvm::PointerIntPair Data; ObjCInterfaceDecl(const ASTContext &C, DeclContext *DC, SourceLocation AtLoc, - IdentifierInfo *Id, ObjCTypeParamList *typeParamList, + const IdentifierInfo *Id, ObjCTypeParamList *typeParamList, SourceLocation CLoc, ObjCInterfaceDecl *PrevDecl, bool IsInternal); @@ -1271,13 +1273,11 @@ class ObjCInterfaceDecl : public ObjCContainerDecl } public: - static ObjCInterfaceDecl *Create(const ASTContext &C, DeclContext *DC, - SourceLocation atLoc, - IdentifierInfo *Id, - ObjCTypeParamList *typeParamList, - ObjCInterfaceDecl *PrevDecl, - SourceLocation ClassLoc = SourceLocation(), - bool isInternal = false); + static ObjCInterfaceDecl * + Create(const ASTContext &C, DeclContext *DC, SourceLocation atLoc, + const IdentifierInfo *Id, ObjCTypeParamList *typeParamList, + ObjCInterfaceDecl *PrevDecl, + SourceLocation ClassLoc = SourceLocation(), bool isInternal = false); static ObjCInterfaceDecl *CreateDeserialized(const ASTContext &C, unsigned ID); @@ -1338,7 +1338,8 @@ public: ObjCImplementationDecl *getImplementation() const; void setImplementation(ObjCImplementationDecl *ImplD); - ObjCCategoryDecl *FindCategoryDeclaration(IdentifierInfo *CategoryId) const; + ObjCCategoryDecl * + FindCategoryDeclaration(const IdentifierInfo *CategoryId) const; // Get the local instance/class method declared in a category. ObjCMethodDecl *getCategoryInstanceMethod(Selector Sel) const; @@ -1794,9 +1795,9 @@ public: data().CategoryList = category; } - ObjCPropertyDecl - *FindPropertyVisibleInPrimaryClass(IdentifierInfo *PropertyId, - ObjCPropertyQueryKind QueryKind) const; + ObjCPropertyDecl * + FindPropertyVisibleInPrimaryClass(const IdentifierInfo *PropertyId, + ObjCPropertyQueryKind QueryKind) const; void collectPropertiesToImplement(PropertyMap &PM) const override; @@ -1954,8 +1955,8 @@ public: private: ObjCIvarDecl(ObjCContainerDecl *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, - QualType T, TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, + SourceLocation IdLoc, const IdentifierInfo *Id, QualType T, + TypeSourceInfo *TInfo, AccessControl ac, Expr *BW, bool synthesized) : FieldDecl(ObjCIvar, DC, StartLoc, IdLoc, Id, T, TInfo, BW, /*Mutable=*/false, /*HasInit=*/ICIS_NoInit), @@ -1964,10 +1965,9 @@ private: public: static ObjCIvarDecl *Create(ASTContext &C, ObjCContainerDecl *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, QualType T, - TypeSourceInfo *TInfo, - AccessControl ac, Expr *BW = nullptr, - bool synthesized=false); + const IdentifierInfo *Id, QualType T, + TypeSourceInfo *TInfo, AccessControl ac, + Expr *BW = nullptr, bool synthesized = false); static ObjCIvarDecl *CreateDeserialized(ASTContext &C, unsigned ID); @@ -2343,7 +2343,7 @@ class ObjCCategoryDecl : public ObjCContainerDecl { ObjCCategoryDecl(DeclContext *DC, SourceLocation AtLoc, SourceLocation ClassNameLoc, SourceLocation CategoryNameLoc, - IdentifierInfo *Id, ObjCInterfaceDecl *IDecl, + const IdentifierInfo *Id, ObjCInterfaceDecl *IDecl, ObjCTypeParamList *typeParamList, SourceLocation IvarLBraceLoc = SourceLocation(), SourceLocation IvarRBraceLoc = SourceLocation()); @@ -2354,15 +2354,13 @@ public: friend class ASTDeclReader; friend class ASTDeclWriter; - static ObjCCategoryDecl *Create(ASTContext &C, DeclContext *DC, - SourceLocation AtLoc, - SourceLocation ClassNameLoc, - SourceLocation CategoryNameLoc, - IdentifierInfo *Id, - ObjCInterfaceDecl *IDecl, - ObjCTypeParamList *typeParamList, - SourceLocation IvarLBraceLoc=SourceLocation(), - SourceLocation IvarRBraceLoc=SourceLocation()); + static ObjCCategoryDecl * + Create(ASTContext &C, DeclContext *DC, SourceLocation AtLoc, + SourceLocation ClassNameLoc, SourceLocation CategoryNameLoc, + const IdentifierInfo *Id, ObjCInterfaceDecl *IDecl, + ObjCTypeParamList *typeParamList, + SourceLocation IvarLBraceLoc = SourceLocation(), + SourceLocation IvarRBraceLoc = SourceLocation()); static ObjCCategoryDecl *CreateDeserialized(ASTContext &C, unsigned ID); ObjCInterfaceDecl *getClassInterface() { return ClassInterface; } @@ -2472,10 +2470,9 @@ class ObjCImplDecl : public ObjCContainerDecl { void anchor() override; protected: - ObjCImplDecl(Kind DK, DeclContext *DC, - ObjCInterfaceDecl *classInterface, - IdentifierInfo *Id, - SourceLocation nameLoc, SourceLocation atStartLoc) + ObjCImplDecl(Kind DK, DeclContext *DC, ObjCInterfaceDecl *classInterface, + const IdentifierInfo *Id, SourceLocation nameLoc, + SourceLocation atStartLoc) : ObjCContainerDecl(DK, DC, Id, nameLoc, atStartLoc), ClassInterface(classInterface) {} @@ -2543,12 +2540,12 @@ class ObjCCategoryImplDecl : public ObjCImplDecl { // Category name location SourceLocation CategoryNameLoc; - ObjCCategoryImplDecl(DeclContext *DC, IdentifierInfo *Id, + ObjCCategoryImplDecl(DeclContext *DC, const IdentifierInfo *Id, ObjCInterfaceDecl *classInterface, SourceLocation nameLoc, SourceLocation atStartLoc, SourceLocation CategoryNameLoc) - : ObjCImplDecl(ObjCCategoryImpl, DC, classInterface, Id, - nameLoc, atStartLoc), + : ObjCImplDecl(ObjCCategoryImpl, DC, classInterface, Id, nameLoc, + atStartLoc), CategoryNameLoc(CategoryNameLoc) {} void anchor() override; @@ -2557,12 +2554,10 @@ public: friend class ASTDeclReader; friend class ASTDeclWriter; - static ObjCCategoryImplDecl *Create(ASTContext &C, DeclContext *DC, - IdentifierInfo *Id, - ObjCInterfaceDecl *classInterface, - SourceLocation nameLoc, - SourceLocation atStartLoc, - SourceLocation CategoryNameLoc); + static ObjCCategoryImplDecl * + Create(ASTContext &C, DeclContext *DC, const IdentifierInfo *Id, + ObjCInterfaceDecl *classInterface, SourceLocation nameLoc, + SourceLocation atStartLoc, SourceLocation CategoryNameLoc); static ObjCCategoryImplDecl *CreateDeserialized(ASTContext &C, unsigned ID); ObjCCategoryDecl *getCategoryDecl() const; diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h index e3b6a7efb112..cb598cb81840 100644 --- a/clang/include/clang/AST/DeclTemplate.h +++ b/clang/include/clang/AST/DeclTemplate.h @@ -1389,14 +1389,14 @@ class NonTypeTemplateParmDecl final NonTypeTemplateParmDecl(DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, unsigned D, unsigned P, - IdentifierInfo *Id, QualType T, + const IdentifierInfo *Id, QualType T, bool ParameterPack, TypeSourceInfo *TInfo) : DeclaratorDecl(NonTypeTemplateParm, DC, IdLoc, Id, T, TInfo, StartLoc), TemplateParmPosition(D, P), ParameterPack(ParameterPack) {} NonTypeTemplateParmDecl(DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, unsigned D, unsigned P, - IdentifierInfo *Id, QualType T, + const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, ArrayRef ExpandedTypes, ArrayRef ExpandedTInfos); @@ -1404,12 +1404,12 @@ class NonTypeTemplateParmDecl final public: static NonTypeTemplateParmDecl * Create(const ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, unsigned D, unsigned P, IdentifierInfo *Id, + SourceLocation IdLoc, unsigned D, unsigned P, const IdentifierInfo *Id, QualType T, bool ParameterPack, TypeSourceInfo *TInfo); static NonTypeTemplateParmDecl * Create(const ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, unsigned D, unsigned P, IdentifierInfo *Id, + SourceLocation IdLoc, unsigned D, unsigned P, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, ArrayRef ExpandedTypes, ArrayRef ExpandedTInfos); diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h index 7eb99a75e1fc..d28e5c3a78ee 100644 --- a/clang/include/clang/AST/ExprCXX.h +++ b/clang/include/clang/AST/ExprCXX.h @@ -2559,7 +2559,7 @@ public: class PseudoDestructorTypeStorage { /// Either the type source information or the name of the type, if /// it couldn't be resolved due to type-dependence. - llvm::PointerUnion Type; + llvm::PointerUnion Type; /// The starting source location of the pseudo-destructor type. SourceLocation Location; @@ -2567,7 +2567,7 @@ class PseudoDestructorTypeStorage { public: PseudoDestructorTypeStorage() = default; - PseudoDestructorTypeStorage(IdentifierInfo *II, SourceLocation Loc) + PseudoDestructorTypeStorage(const IdentifierInfo *II, SourceLocation Loc) : Type(II), Location(Loc) {} PseudoDestructorTypeStorage(TypeSourceInfo *Info); @@ -2576,8 +2576,8 @@ public: return Type.dyn_cast(); } - IdentifierInfo *getIdentifier() const { - return Type.dyn_cast(); + const IdentifierInfo *getIdentifier() const { + return Type.dyn_cast(); } SourceLocation getLocation() const { return Location; } @@ -2708,7 +2708,7 @@ public: /// In a dependent pseudo-destructor expression for which we do not /// have full type information on the destroyed type, provides the name /// of the destroyed type. - IdentifierInfo *getDestroyedTypeIdentifier() const { + const IdentifierInfo *getDestroyedTypeIdentifier() const { return DestroyedType.getIdentifier(); } diff --git a/clang/include/clang/AST/ExternalASTSource.h b/clang/include/clang/AST/ExternalASTSource.h index 8e573965b0a3..230c83943c22 100644 --- a/clang/include/clang/AST/ExternalASTSource.h +++ b/clang/include/clang/AST/ExternalASTSource.h @@ -138,7 +138,7 @@ public: virtual CXXBaseSpecifier *GetExternalCXXBaseSpecifiers(uint64_t Offset); /// Update an out-of-date identifier. - virtual void updateOutOfDateIdentifier(IdentifierInfo &II) {} + virtual void updateOutOfDateIdentifier(const IdentifierInfo &II) {} /// Find all declarations with the given name in the given context, /// and add them to the context by calling SetExternalVisibleDeclsForName diff --git a/clang/include/clang/AST/NestedNameSpecifier.h b/clang/include/clang/AST/NestedNameSpecifier.h index 3b6cf9721185..7b0c21b9e7cf 100644 --- a/clang/include/clang/AST/NestedNameSpecifier.h +++ b/clang/include/clang/AST/NestedNameSpecifier.h @@ -124,7 +124,7 @@ public: /// cannot be resolved. static NestedNameSpecifier *Create(const ASTContext &Context, NestedNameSpecifier *Prefix, - IdentifierInfo *II); + const IdentifierInfo *II); /// Builds a nested name specifier that names a namespace. static NestedNameSpecifier *Create(const ASTContext &Context, @@ -134,7 +134,7 @@ public: /// Builds a nested name specifier that names a namespace alias. static NestedNameSpecifier *Create(const ASTContext &Context, NestedNameSpecifier *Prefix, - NamespaceAliasDecl *Alias); + const NamespaceAliasDecl *Alias); /// Builds a nested name specifier that names a type. static NestedNameSpecifier *Create(const ASTContext &Context, @@ -148,7 +148,7 @@ public: /// nested name specifier, e.g., in "x->Base::f", the "x" has a dependent /// type. static NestedNameSpecifier *Create(const ASTContext &Context, - IdentifierInfo *II); + const IdentifierInfo *II); /// Returns the nested name specifier representing the global /// scope. diff --git a/clang/include/clang/Analysis/SelectorExtras.h b/clang/include/clang/Analysis/SelectorExtras.h index 1e1daf5706bb..ac2c2519beae 100644 --- a/clang/include/clang/Analysis/SelectorExtras.h +++ b/clang/include/clang/Analysis/SelectorExtras.h @@ -15,10 +15,10 @@ namespace clang { template static inline Selector getKeywordSelector(ASTContext &Ctx, - IdentifierInfos *... IIs) { + const IdentifierInfos *...IIs) { static_assert(sizeof...(IdentifierInfos) > 0, "keyword selectors must have at least one argument"); - SmallVector II({&Ctx.Idents.get(IIs)...}); + SmallVector II({&Ctx.Idents.get(IIs)...}); return Ctx.Selectors.getSelector(II.size(), &II[0]); } diff --git a/clang/include/clang/Basic/IdentifierTable.h b/clang/include/clang/Basic/IdentifierTable.h index a091639bfa25..a893e6f4d3d3 100644 --- a/clang/include/clang/Basic/IdentifierTable.h +++ b/clang/include/clang/Basic/IdentifierTable.h @@ -913,12 +913,13 @@ class alignas(IdentifierInfoAlignment) MultiKeywordSelector public: // Constructor for keyword selectors. - MultiKeywordSelector(unsigned nKeys, IdentifierInfo **IIV) + MultiKeywordSelector(unsigned nKeys, const IdentifierInfo **IIV) : DeclarationNameExtra(nKeys) { assert((nKeys > 1) && "not a multi-keyword selector"); // Fill in the trailing keyword array. - IdentifierInfo **KeyInfo = reinterpret_cast(this + 1); + const IdentifierInfo **KeyInfo = + reinterpret_cast(this + 1); for (unsigned i = 0; i != nKeys; ++i) KeyInfo[i] = IIV[i]; } @@ -928,7 +929,7 @@ public: using DeclarationNameExtra::getNumArgs; - using keyword_iterator = IdentifierInfo *const *; + using keyword_iterator = const IdentifierInfo *const *; keyword_iterator keyword_begin() const { return reinterpret_cast(this + 1); @@ -938,7 +939,7 @@ public: return keyword_begin() + getNumArgs(); } - IdentifierInfo *getIdentifierInfoForSlot(unsigned i) const { + const IdentifierInfo *getIdentifierInfoForSlot(unsigned i) const { assert(i < getNumArgs() && "getIdentifierInfoForSlot(): illegal index"); return keyword_begin()[i]; } @@ -991,10 +992,10 @@ class Selector { /// Do not reorder or add any arguments to this template /// without thoroughly understanding how tightly coupled these classes are. llvm::PointerIntPair< - llvm::PointerUnion, 2> + llvm::PointerUnion, 2> InfoPtr; - Selector(IdentifierInfo *II, unsigned nArgs) { + Selector(const IdentifierInfo *II, unsigned nArgs) { assert(nArgs < 2 && "nArgs not equal to 0/1"); InfoPtr.setPointerAndInt(II, nArgs + 1); } @@ -1006,8 +1007,8 @@ class Selector { InfoPtr.setPointerAndInt(SI, MultiArg & 0b11); } - IdentifierInfo *getAsIdentifierInfo() const { - return InfoPtr.getPointer().dyn_cast(); + const IdentifierInfo *getAsIdentifierInfo() const { + return InfoPtr.getPointer().dyn_cast(); } MultiKeywordSelector *getMultiKeywordSelector() const { @@ -1075,7 +1076,7 @@ public: /// /// \returns the uniqued identifier for this slot, or NULL if this slot has /// no corresponding identifier. - IdentifierInfo *getIdentifierInfoForSlot(unsigned argIndex) const; + const IdentifierInfo *getIdentifierInfoForSlot(unsigned argIndex) const; /// Retrieve the name at a given position in the selector. /// @@ -1132,13 +1133,13 @@ public: /// /// \p NumArgs indicates whether this is a no argument selector "foo", a /// single argument selector "foo:" or multi-argument "foo:bar:". - Selector getSelector(unsigned NumArgs, IdentifierInfo **IIV); + Selector getSelector(unsigned NumArgs, const IdentifierInfo **IIV); - Selector getUnarySelector(IdentifierInfo *ID) { + Selector getUnarySelector(const IdentifierInfo *ID) { return Selector(ID, 1); } - Selector getNullarySelector(IdentifierInfo *ID) { + Selector getNullarySelector(const IdentifierInfo *ID) { return Selector(ID, 0); } diff --git a/clang/include/clang/Lex/ExternalPreprocessorSource.h b/clang/include/clang/Lex/ExternalPreprocessorSource.h index 685941b66bd8..677584186037 100644 --- a/clang/include/clang/Lex/ExternalPreprocessorSource.h +++ b/clang/include/clang/Lex/ExternalPreprocessorSource.h @@ -31,7 +31,7 @@ public: virtual void ReadDefinedMacros() = 0; /// Update an out-of-date identifier. - virtual void updateOutOfDateIdentifier(IdentifierInfo &II) = 0; + virtual void updateOutOfDateIdentifier(const IdentifierInfo &II) = 0; /// Return the identifier associated with the given ID number. /// diff --git a/clang/include/clang/Lex/MacroInfo.h b/clang/include/clang/Lex/MacroInfo.h index 1237fc62eb6c..19a706216d50 100644 --- a/clang/include/clang/Lex/MacroInfo.h +++ b/clang/include/clang/Lex/MacroInfo.h @@ -515,7 +515,7 @@ class ModuleMacro : public llvm::FoldingSetNode { friend class Preprocessor; /// The name defined by the macro. - IdentifierInfo *II; + const IdentifierInfo *II; /// The body of the #define, or nullptr if this is a #undef. MacroInfo *Macro; @@ -529,7 +529,7 @@ class ModuleMacro : public llvm::FoldingSetNode { /// The number of modules whose macros are directly overridden by this one. unsigned NumOverrides; - ModuleMacro(Module *OwningModule, IdentifierInfo *II, MacroInfo *Macro, + ModuleMacro(Module *OwningModule, const IdentifierInfo *II, MacroInfo *Macro, ArrayRef Overrides) : II(II), Macro(Macro), OwningModule(OwningModule), NumOverrides(Overrides.size()) { @@ -539,7 +539,7 @@ class ModuleMacro : public llvm::FoldingSetNode { public: static ModuleMacro *create(Preprocessor &PP, Module *OwningModule, - IdentifierInfo *II, MacroInfo *Macro, + const IdentifierInfo *II, MacroInfo *Macro, ArrayRef Overrides); void Profile(llvm::FoldingSetNodeID &ID) const { @@ -553,7 +553,7 @@ public: } /// Get the name of the macro. - IdentifierInfo *getName() const { return II; } + const IdentifierInfo *getName() const { return II; } /// Get the ID of the module that exports this macro. Module *getOwningModule() const { return OwningModule; } diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 0836b7d439bb..e89b4a2c5230 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -836,7 +836,7 @@ private: ModuleMacroInfo *getModuleInfo(Preprocessor &PP, const IdentifierInfo *II) const { if (II->isOutOfDate()) - PP.updateOutOfDateIdentifier(const_cast(*II)); + PP.updateOutOfDateIdentifier(*II); // FIXME: Find a spare bit on IdentifierInfo and store a // HasModuleMacros flag. if (!II->hasMacroDefinition() || @@ -1162,7 +1162,7 @@ private: /// skipped. llvm::DenseMap RecordedSkippedRanges; - void updateOutOfDateIdentifier(IdentifierInfo &II) const; + void updateOutOfDateIdentifier(const IdentifierInfo &II) const; public: Preprocessor(std::shared_ptr PPOpts, @@ -1432,14 +1432,15 @@ public: MacroDirective *MD); /// Register an exported macro for a module and identifier. - ModuleMacro *addModuleMacro(Module *Mod, IdentifierInfo *II, MacroInfo *Macro, + ModuleMacro *addModuleMacro(Module *Mod, const IdentifierInfo *II, + MacroInfo *Macro, ArrayRef Overrides, bool &IsNew); ModuleMacro *getModuleMacro(Module *Mod, const IdentifierInfo *II); /// Get the list of leaf (non-overridden) module macros for a name. ArrayRef getLeafModuleMacros(const IdentifierInfo *II) const { if (II->isOutOfDate()) - updateOutOfDateIdentifier(const_cast(*II)); + updateOutOfDateIdentifier(*II); auto I = LeafModuleMacros.find(II); if (I != LeafModuleMacros.end()) return I->second; diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 8bc929b1dfe4..3a055c10ffb3 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -329,7 +329,7 @@ class Parser : public CodeCompletionHandler { }; /// Identifiers which have been declared within a tentative parse. - SmallVector TentativelyDeclaredIdentifiers; + SmallVector TentativelyDeclaredIdentifiers; /// Tracker for '<' tokens that might have been intended to be treated as an /// angle bracket instead of a less-than comparison. @@ -1927,15 +1927,11 @@ private: bool EnteringContext, IdentifierInfo &II, CXXScopeSpec &SS); - bool ParseOptionalCXXScopeSpecifier(CXXScopeSpec &SS, - ParsedType ObjectType, - bool ObjectHasErrors, - bool EnteringContext, - bool *MayBePseudoDestructor = nullptr, - bool IsTypename = false, - IdentifierInfo **LastII = nullptr, - bool OnlyNamespace = false, - bool InUsingDeclaration = false); + bool ParseOptionalCXXScopeSpecifier( + CXXScopeSpec &SS, ParsedType ObjectType, bool ObjectHasErrors, + bool EnteringContext, bool *MayBePseudoDestructor = nullptr, + bool IsTypename = false, const IdentifierInfo **LastII = nullptr, + bool OnlyNamespace = false, bool InUsingDeclaration = false); //===--------------------------------------------------------------------===// // C++11 5.1.2: Lambda expressions diff --git a/clang/include/clang/Sema/CodeCompleteConsumer.h b/clang/include/clang/Sema/CodeCompleteConsumer.h index a2028e40f83d..0924dc27af82 100644 --- a/clang/include/clang/Sema/CodeCompleteConsumer.h +++ b/clang/include/clang/Sema/CodeCompleteConsumer.h @@ -362,7 +362,7 @@ private: QualType BaseType; /// The identifiers for Objective-C selector parts. - ArrayRef SelIdents; + ArrayRef SelIdents; /// The scope specifier that comes before the completion token e.g. /// "a::b::" @@ -378,8 +378,9 @@ public: : CCKind(CCKind), IsUsingDeclaration(false), SelIdents(std::nullopt) {} /// Construct a new code-completion context of the given kind. - CodeCompletionContext(Kind CCKind, QualType T, - ArrayRef SelIdents = std::nullopt) + CodeCompletionContext( + Kind CCKind, QualType T, + ArrayRef SelIdents = std::nullopt) : CCKind(CCKind), IsUsingDeclaration(false), SelIdents(SelIdents) { if (CCKind == CCC_DotMemberAccess || CCKind == CCC_ArrowMemberAccess || CCKind == CCC_ObjCPropertyAccess || CCKind == CCC_ObjCClassMessage || @@ -406,7 +407,7 @@ public: QualType getBaseType() const { return BaseType; } /// Retrieve the Objective-C selector identifiers. - ArrayRef getSelIdents() const { return SelIdents; } + ArrayRef getSelIdents() const { return SelIdents; } /// Determines whether we want C++ constructors as results within this /// context. diff --git a/clang/include/clang/Sema/DeclSpec.h b/clang/include/clang/Sema/DeclSpec.h index a17615970748..c9eecdafe62c 100644 --- a/clang/include/clang/Sema/DeclSpec.h +++ b/clang/include/clang/Sema/DeclSpec.h @@ -1049,7 +1049,7 @@ public: union { /// When Kind == IK_Identifier, the parsed identifier, or when /// Kind == IK_UserLiteralId, the identifier suffix. - IdentifierInfo *Identifier; + const IdentifierInfo *Identifier; /// When Kind == IK_OperatorFunctionId, the overloaded operator /// that we parsed. @@ -1111,7 +1111,7 @@ public: /// \param IdLoc the location of the parsed identifier. void setIdentifier(const IdentifierInfo *Id, SourceLocation IdLoc) { Kind = UnqualifiedIdKind::IK_Identifier; - Identifier = const_cast(Id); + Identifier = Id; StartLocation = EndLocation = IdLoc; } @@ -1154,9 +1154,9 @@ public: /// /// \param IdLoc the location of the identifier. void setLiteralOperatorId(const IdentifierInfo *Id, SourceLocation OpLoc, - SourceLocation IdLoc) { + SourceLocation IdLoc) { Kind = UnqualifiedIdKind::IK_LiteralOperatorId; - Identifier = const_cast(Id); + Identifier = Id; StartLocation = OpLoc; EndLocation = IdLoc; } @@ -1225,7 +1225,7 @@ public: /// \param Id the identifier. void setImplicitSelfParam(const IdentifierInfo *Id) { Kind = UnqualifiedIdKind::IK_ImplicitSelfParam; - Identifier = const_cast(Id); + Identifier = Id; StartLocation = EndLocation = SourceLocation(); } @@ -1327,7 +1327,7 @@ struct DeclaratorChunk { /// Parameter type lists will have type info (if the actions module provides /// it), but may have null identifier info: e.g. for 'void foo(int X, int)'. struct ParamInfo { - IdentifierInfo *Ident; + const IdentifierInfo *Ident; SourceLocation IdentLoc; Decl *Param; @@ -1339,11 +1339,10 @@ struct DeclaratorChunk { std::unique_ptr DefaultArgTokens; ParamInfo() = default; - ParamInfo(IdentifierInfo *ident, SourceLocation iloc, - Decl *param, + ParamInfo(const IdentifierInfo *ident, SourceLocation iloc, Decl *param, std::unique_ptr DefArgTokens = nullptr) - : Ident(ident), IdentLoc(iloc), Param(param), - DefaultArgTokens(std::move(DefArgTokens)) {} + : Ident(ident), IdentLoc(iloc), Param(param), + DefaultArgTokens(std::move(DefArgTokens)) {} }; struct TypeAndRange { @@ -2326,7 +2325,7 @@ public: return BindingGroup.isSet(); } - IdentifierInfo *getIdentifier() const { + const IdentifierInfo *getIdentifier() const { if (Name.getKind() == UnqualifiedIdKind::IK_Identifier) return Name.Identifier; @@ -2335,7 +2334,7 @@ public: SourceLocation getIdentifierLoc() const { return Name.StartLocation; } /// Set the name of this declarator to be the given identifier. - void SetIdentifier(IdentifierInfo *Id, SourceLocation IdLoc) { + void SetIdentifier(const IdentifierInfo *Id, SourceLocation IdLoc) { Name.setIdentifier(Id, IdLoc); } diff --git a/clang/include/clang/Sema/ParsedTemplate.h b/clang/include/clang/Sema/ParsedTemplate.h index 65182d57246a..ac4dbbf294ca 100644 --- a/clang/include/clang/Sema/ParsedTemplate.h +++ b/clang/include/clang/Sema/ParsedTemplate.h @@ -159,7 +159,7 @@ namespace clang { SourceLocation TemplateNameLoc; /// FIXME: Temporarily stores the name of a specialization - IdentifierInfo *Name; + const IdentifierInfo *Name; /// FIXME: Temporarily stores the overloaded operator kind. OverloadedOperatorKind Operator; @@ -197,7 +197,7 @@ namespace clang { /// appends it to List. static TemplateIdAnnotation * Create(SourceLocation TemplateKWLoc, SourceLocation TemplateNameLoc, - IdentifierInfo *Name, OverloadedOperatorKind OperatorKind, + const IdentifierInfo *Name, OverloadedOperatorKind OperatorKind, ParsedTemplateTy OpaqueTemplateName, TemplateNameKind TemplateKind, SourceLocation LAngleLoc, SourceLocation RAngleLoc, ArrayRef TemplateArgs, bool ArgsInvalid, @@ -236,7 +236,8 @@ namespace clang { TemplateIdAnnotation(const TemplateIdAnnotation &) = delete; TemplateIdAnnotation(SourceLocation TemplateKWLoc, - SourceLocation TemplateNameLoc, IdentifierInfo *Name, + SourceLocation TemplateNameLoc, + const IdentifierInfo *Name, OverloadedOperatorKind OperatorKind, ParsedTemplateTy OpaqueTemplateName, TemplateNameKind TemplateKind, diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index e3e255a0dd76..0ee4f3c8e127 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -568,7 +568,7 @@ public: /// Invent a new identifier for parameters of abbreviated templates. IdentifierInfo * - InventAbbreviatedTemplateParameterTypeName(IdentifierInfo *ParamName, + InventAbbreviatedTemplateParameterTypeName(const IdentifierInfo *ParamName, unsigned Index); void emitAndClearUnusedLocalTypedefWarnings(); @@ -2958,9 +2958,9 @@ public: SourceLocation NameLoc, TypeSourceInfo *TSInfo); ParmVarDecl *CheckParameter(DeclContext *DC, SourceLocation StartLoc, - SourceLocation NameLoc, IdentifierInfo *Name, - QualType T, TypeSourceInfo *TSInfo, - StorageClass SC); + SourceLocation NameLoc, + const IdentifierInfo *Name, QualType T, + TypeSourceInfo *TSInfo, StorageClass SC); // Contexts where using non-trivial C union types can be disallowed. This is // passed to err_non_trivial_c_union_in_invalid_context. @@ -3365,7 +3365,7 @@ public: /// variable. void DiagnoseUnusedButSetDecl(const VarDecl *VD, DiagReceiverTy DiagReceiver); - ObjCInterfaceDecl *getObjCInterfaceDecl(IdentifierInfo *&Id, + ObjCInterfaceDecl *getObjCInterfaceDecl(const IdentifierInfo *&Id, SourceLocation IdLoc, bool TypoCorrection = false); @@ -3442,8 +3442,9 @@ public: /// VerifyBitField - verifies that a bit field expression is an ICE and has /// the correct width, and that the field type is valid. /// Returns false on success. - ExprResult VerifyBitField(SourceLocation FieldLoc, IdentifierInfo *FieldName, - QualType FieldTy, bool IsMsStruct, Expr *BitWidth); + ExprResult VerifyBitField(SourceLocation FieldLoc, + const IdentifierInfo *FieldName, QualType FieldTy, + bool IsMsStruct, Expr *BitWidth); /// IsValueInFlagEnum - Determine if a value is allowed as part of a flag /// enum. If AllowMask is true, then we also allow the complement of a valid @@ -4638,7 +4639,8 @@ public: VarDecl *BuildExceptionDeclaration(Scope *S, TypeSourceInfo *TInfo, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id); + SourceLocation IdLoc, + const IdentifierInfo *Id); Decl *ActOnExceptionDeclarator(Scope *S, Declarator &D); @@ -6555,12 +6557,12 @@ public: ParsedType getInheritingConstructorName(CXXScopeSpec &SS, SourceLocation NameLoc, - IdentifierInfo &Name); + const IdentifierInfo &Name); - ParsedType getConstructorName(IdentifierInfo &II, SourceLocation NameLoc, - Scope *S, CXXScopeSpec &SS, - bool EnteringContext); - ParsedType getDestructorName(IdentifierInfo &II, SourceLocation NameLoc, + ParsedType getConstructorName(const IdentifierInfo &II, + SourceLocation NameLoc, Scope *S, + CXXScopeSpec &SS, bool EnteringContext); + ParsedType getDestructorName(const IdentifierInfo &II, SourceLocation NameLoc, Scope *S, CXXScopeSpec &SS, ParsedType ObjectType, bool EnteringContext); @@ -6960,7 +6962,7 @@ public: concepts::Requirement *ActOnTypeRequirement(SourceLocation TypenameKWLoc, CXXScopeSpec &SS, SourceLocation NameLoc, - IdentifierInfo *TypeName, + const IdentifierInfo *TypeName, TemplateIdAnnotation *TemplateId); concepts::Requirement *ActOnCompoundRequirement(Expr *E, SourceLocation NoexceptLoc); @@ -9116,7 +9118,7 @@ public: TypeResult ActOnTemplateIdType(Scope *S, CXXScopeSpec &SS, SourceLocation TemplateKWLoc, - TemplateTy Template, IdentifierInfo *TemplateII, + TemplateTy Template, const IdentifierInfo *TemplateII, SourceLocation TemplateIILoc, SourceLocation LAngleLoc, ASTTemplateArgsPtr TemplateArgs, SourceLocation RAngleLoc, bool IsCtorOrDtorName = false, bool IsClassName = false, @@ -9457,7 +9459,7 @@ public: TypeResult ActOnTypenameType(Scope *S, SourceLocation TypenameLoc, const CXXScopeSpec &SS, SourceLocation TemplateLoc, - TemplateTy TemplateName, IdentifierInfo *TemplateII, + TemplateTy TemplateName, const IdentifierInfo *TemplateII, SourceLocation TemplateIILoc, SourceLocation LAngleLoc, ASTTemplateArgsPtr TemplateArgs, SourceLocation RAngleLoc); @@ -9535,14 +9537,15 @@ public: Decl *ActOnConceptDefinition(Scope *S, MultiTemplateParamsArg TemplateParameterLists, - IdentifierInfo *Name, SourceLocation NameLoc, - Expr *ConstraintExpr); + const IdentifierInfo *Name, + SourceLocation NameLoc, Expr *ConstraintExpr); void CheckConceptRedefinition(ConceptDecl *NewDecl, LookupResult &Previous, bool &AddToScope); TypeResult ActOnDependentTag(Scope *S, unsigned TagSpec, TagUseKind TUK, - const CXXScopeSpec &SS, IdentifierInfo *Name, + const CXXScopeSpec &SS, + const IdentifierInfo *Name, SourceLocation TagLoc, SourceLocation NameLoc); void MarkAsLateParsedTemplate(FunctionDecl *FD, Decl *FnD, @@ -11988,22 +11991,22 @@ public: SkipBodyInfo *SkipBody); ObjCCategoryDecl *ActOnStartCategoryInterface( - SourceLocation AtInterfaceLoc, IdentifierInfo *ClassName, + SourceLocation AtInterfaceLoc, const IdentifierInfo *ClassName, SourceLocation ClassLoc, ObjCTypeParamList *typeParamList, - IdentifierInfo *CategoryName, SourceLocation CategoryLoc, + const IdentifierInfo *CategoryName, SourceLocation CategoryLoc, Decl *const *ProtoRefs, unsigned NumProtoRefs, const SourceLocation *ProtoLocs, SourceLocation EndProtoLoc, const ParsedAttributesView &AttrList); ObjCImplementationDecl *ActOnStartClassImplementation( - SourceLocation AtClassImplLoc, IdentifierInfo *ClassName, - SourceLocation ClassLoc, IdentifierInfo *SuperClassname, + SourceLocation AtClassImplLoc, const IdentifierInfo *ClassName, + SourceLocation ClassLoc, const IdentifierInfo *SuperClassname, SourceLocation SuperClassLoc, const ParsedAttributesView &AttrList); ObjCCategoryImplDecl *ActOnStartCategoryImplementation( - SourceLocation AtCatImplLoc, IdentifierInfo *ClassName, - SourceLocation ClassLoc, IdentifierInfo *CatName, SourceLocation CatLoc, - const ParsedAttributesView &AttrList); + SourceLocation AtCatImplLoc, const IdentifierInfo *ClassName, + SourceLocation ClassLoc, const IdentifierInfo *CatName, + SourceLocation CatLoc, const ParsedAttributesView &AttrList); DeclGroupPtrTy ActOnFinishObjCImplementation(Decl *ObjCImpDecl, ArrayRef Decls); @@ -12186,11 +12189,13 @@ public: bool CheckObjCDeclScope(Decl *D); void ActOnDefs(Scope *S, Decl *TagD, SourceLocation DeclStart, - IdentifierInfo *ClassName, SmallVectorImpl &Decls); + const IdentifierInfo *ClassName, + SmallVectorImpl &Decls); VarDecl *BuildObjCExceptionDecl(TypeSourceInfo *TInfo, QualType ExceptionType, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, bool Invalid = false); + const IdentifierInfo *Id, + bool Invalid = false); Decl *ActOnObjCExceptionDecl(Scope *S, Declarator &D); @@ -12307,8 +12312,8 @@ public: SourceLocation SuperLoc, QualType SuperType, bool Super); - ExprResult ActOnClassPropertyRefExpr(IdentifierInfo &receiverName, - IdentifierInfo &propertyName, + ExprResult ActOnClassPropertyRefExpr(const IdentifierInfo &receiverName, + const IdentifierInfo &propertyName, SourceLocation receiverNameLoc, SourceLocation propertyNameLoc); @@ -12783,18 +12788,18 @@ public: bool IsParameter); void CodeCompleteObjCMessageReceiver(Scope *S); void CodeCompleteObjCSuperMessage(Scope *S, SourceLocation SuperLoc, - ArrayRef SelIdents, + ArrayRef SelIdents, bool AtArgumentExpression); void CodeCompleteObjCClassMessage(Scope *S, ParsedType Receiver, - ArrayRef SelIdents, + ArrayRef SelIdents, bool AtArgumentExpression, bool IsSuper = false); - void CodeCompleteObjCInstanceMessage(Scope *S, Expr *Receiver, - ArrayRef SelIdents, - bool AtArgumentExpression, - ObjCInterfaceDecl *Super = nullptr); + void CodeCompleteObjCInstanceMessage( + Scope *S, Expr *Receiver, ArrayRef SelIdents, + bool AtArgumentExpression, ObjCInterfaceDecl *Super = nullptr); void CodeCompleteObjCForCollection(Scope *S, DeclGroupPtrTy IterationVar); - void CodeCompleteObjCSelector(Scope *S, ArrayRef SelIdents); + void CodeCompleteObjCSelector(Scope *S, + ArrayRef SelIdents); void CodeCompleteObjCProtocolReferences(ArrayRef Protocols); void CodeCompleteObjCProtocolDecl(Scope *S); @@ -12814,11 +12819,11 @@ public: void CodeCompleteObjCMethodDecl(Scope *S, std::optional IsInstanceMethod, ParsedType ReturnType); - void CodeCompleteObjCMethodDeclSelector(Scope *S, bool IsInstanceMethod, - bool AtParameterName, - ParsedType ReturnType, - ArrayRef SelIdents); - void CodeCompleteObjCClassPropertyRefExpr(Scope *S, IdentifierInfo &ClassName, + void CodeCompleteObjCMethodDeclSelector( + Scope *S, bool IsInstanceMethod, bool AtParameterName, + ParsedType ReturnType, ArrayRef SelIdents); + void CodeCompleteObjCClassPropertyRefExpr(Scope *S, + const IdentifierInfo &ClassName, SourceLocation ClassNameLoc, bool IsBaseExprStatement); void CodeCompletePreprocessorDirective(bool InConditional); diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h index 1911252b34cd..5fd55a519c6b 100644 --- a/clang/include/clang/Serialization/ASTReader.h +++ b/clang/include/clang/Serialization/ASTReader.h @@ -1082,12 +1082,12 @@ private: /// The set of lookup results that we have faked in order to support /// merging of partially deserialized decls but that we have not yet removed. - llvm::SmallMapVector, 16> - PendingFakeLookupResults; + llvm::SmallMapVector, 16> + PendingFakeLookupResults; /// The generation number of each identifier, which keeps track of /// the last time we loaded information about this identifier. - llvm::DenseMap IdentifierGeneration; + llvm::DenseMap IdentifierGeneration; /// Contains declarations and definitions that could be /// "interesting" to the ASTConsumer, when we get that AST consumer. @@ -2330,10 +2330,10 @@ public: void ReadDefinedMacros() override; /// Update an out-of-date identifier. - void updateOutOfDateIdentifier(IdentifierInfo &II) override; + void updateOutOfDateIdentifier(const IdentifierInfo &II) override; /// Note that this identifier is up-to-date. - void markIdentifierUpToDate(IdentifierInfo *II); + void markIdentifierUpToDate(const IdentifierInfo *II); /// Load all external visible decls in the given DeclContext. void completeVisibleDeclsMap(const DeclContext *DC) override; diff --git a/clang/lib/ARCMigrate/ObjCMT.cpp b/clang/lib/ARCMigrate/ObjCMT.cpp index 0786c81516b2..b9dcfb8951b3 100644 --- a/clang/lib/ARCMigrate/ObjCMT.cpp +++ b/clang/lib/ARCMigrate/ObjCMT.cpp @@ -1144,7 +1144,7 @@ static bool IsValidIdentifier(ASTContext &Ctx, return false; std::string NameString = Name; NameString[0] = toLowercase(NameString[0]); - IdentifierInfo *II = &Ctx.Idents.get(NameString); + const IdentifierInfo *II = &Ctx.Idents.get(NameString); return II->getTokenID() == tok::identifier; } @@ -1166,7 +1166,7 @@ bool ObjCMigrateASTConsumer::migrateProperty(ASTContext &Ctx, if (OIT_Family != OIT_None) return false; - IdentifierInfo *getterName = GetterSelector.getIdentifierInfoForSlot(0); + const IdentifierInfo *getterName = GetterSelector.getIdentifierInfoForSlot(0); Selector SetterSelector = SelectorTable::constructSetterSelector(PP.getIdentifierTable(), PP.getSelectorTable(), @@ -1311,7 +1311,8 @@ void ObjCMigrateASTConsumer::migrateFactoryMethod(ASTContext &Ctx, std::string StringLoweredClassName = LoweredClassName.lower(); LoweredClassName = StringLoweredClassName; - IdentifierInfo *MethodIdName = OM->getSelector().getIdentifierInfoForSlot(0); + const IdentifierInfo *MethodIdName = + OM->getSelector().getIdentifierInfoForSlot(0); // Handle method with no name at its first selector slot; e.g. + (id):(int)x. if (!MethodIdName) return; diff --git a/clang/lib/ARCMigrate/TransAPIUses.cpp b/clang/lib/ARCMigrate/TransAPIUses.cpp index 638850dcf9ec..8f5d4f4bde06 100644 --- a/clang/lib/ARCMigrate/TransAPIUses.cpp +++ b/clang/lib/ARCMigrate/TransAPIUses.cpp @@ -41,7 +41,7 @@ public: getReturnValueSel = sels.getUnarySelector(&ids.get("getReturnValue")); setReturnValueSel = sels.getUnarySelector(&ids.get("setReturnValue")); - IdentifierInfo *selIds[2]; + const IdentifierInfo *selIds[2]; selIds[0] = &ids.get("getArgument"); selIds[1] = &ids.get("atIndex"); getArgumentSel = sels.getSelector(2, selIds); diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index f7f55dc4e7a9..2fa6aedca4c6 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -6929,16 +6929,13 @@ ASTContext::getCanonicalNestedNameSpecifier(NestedNameSpecifier *NNS) const { // typedef typename T::type T1; // typedef typename T1::type T2; if (const auto *DNT = T->getAs()) - return NestedNameSpecifier::Create( - *this, DNT->getQualifier(), - const_cast(DNT->getIdentifier())); + return NestedNameSpecifier::Create(*this, DNT->getQualifier(), + DNT->getIdentifier()); if (const auto *DTST = T->getAs()) - return NestedNameSpecifier::Create(*this, DTST->getQualifier(), true, - const_cast(T)); + return NestedNameSpecifier::Create(*this, DTST->getQualifier(), true, T); // TODO: Set 'Template' parameter to true for other template types. - return NestedNameSpecifier::Create(*this, nullptr, false, - const_cast(T)); + return NestedNameSpecifier::Create(*this, nullptr, false, T); } case NestedNameSpecifier::Global: diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 45d4c9600537..d5ec5ee40915 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -8383,8 +8383,8 @@ ASTNodeImporter::VisitCXXPseudoDestructorExpr(CXXPseudoDestructorExpr *E) { return std::move(Err); PseudoDestructorTypeStorage Storage; - if (IdentifierInfo *FromII = E->getDestroyedTypeIdentifier()) { - IdentifierInfo *ToII = Importer.Import(FromII); + if (const IdentifierInfo *FromII = E->getDestroyedTypeIdentifier()) { + const IdentifierInfo *ToII = Importer.Import(FromII); ExpectedSLoc ToDestroyedTypeLocOrErr = import(E->getDestroyedTypeLoc()); if (!ToDestroyedTypeLocOrErr) return ToDestroyedTypeLocOrErr.takeError(); @@ -10194,7 +10194,7 @@ Expected ASTImporter::Import(Selector FromSel) { if (FromSel.isNull()) return Selector{}; - SmallVector Idents; + SmallVector Idents; Idents.push_back(Import(FromSel.getIdentifierInfoForSlot(0))); for (unsigned I = 1, N = FromSel.getNumArgs(); I < N; ++I) Idents.push_back(Import(FromSel.getIdentifierInfoForSlot(I))); diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp index 131f82985e90..60e0a3aecf6c 100644 --- a/clang/lib/AST/Decl.cpp +++ b/clang/lib/AST/Decl.cpp @@ -2913,10 +2913,10 @@ VarDecl::setInstantiationOfStaticDataMember(VarDecl *VD, //===----------------------------------------------------------------------===// ParmVarDecl *ParmVarDecl::Create(ASTContext &C, DeclContext *DC, - SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, - QualType T, TypeSourceInfo *TInfo, - StorageClass S, Expr *DefArg) { + SourceLocation StartLoc, SourceLocation IdLoc, + const IdentifierInfo *Id, QualType T, + TypeSourceInfo *TInfo, StorageClass S, + Expr *DefArg) { return new (C, DC) ParmVarDecl(ParmVar, C, DC, StartLoc, IdLoc, Id, T, TInfo, S, DefArg); } @@ -4511,7 +4511,7 @@ unsigned FunctionDecl::getODRHash() { FieldDecl *FieldDecl::Create(const ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, QualType T, + const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, Expr *BW, bool Mutable, InClassInitStyle InitStyle) { return new (C, DC) FieldDecl(Decl::Field, DC, StartLoc, IdLoc, Id, T, TInfo, @@ -5438,7 +5438,7 @@ IndirectFieldDecl::IndirectFieldDecl(ASTContext &C, DeclContext *DC, IndirectFieldDecl * IndirectFieldDecl::Create(ASTContext &C, DeclContext *DC, SourceLocation L, - IdentifierInfo *Id, QualType T, + const IdentifierInfo *Id, QualType T, llvm::MutableArrayRef CH) { return new (C, DC) IndirectFieldDecl(C, DC, L, Id, T, CH); } @@ -5461,7 +5461,8 @@ void TypeDecl::anchor() {} TypedefDecl *TypedefDecl::Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, TypeSourceInfo *TInfo) { + const IdentifierInfo *Id, + TypeSourceInfo *TInfo) { return new (C, DC) TypedefDecl(C, DC, StartLoc, IdLoc, Id, TInfo); } @@ -5511,7 +5512,8 @@ TypedefDecl *TypedefDecl::CreateDeserialized(ASTContext &C, unsigned ID) { TypeAliasDecl *TypeAliasDecl::Create(ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, + SourceLocation IdLoc, + const IdentifierInfo *Id, TypeSourceInfo *TInfo) { return new (C, DC) TypeAliasDecl(C, DC, StartLoc, IdLoc, Id, TInfo); } diff --git a/clang/lib/AST/DeclObjC.cpp b/clang/lib/AST/DeclObjC.cpp index 962f503306a0..32c14938cd58 100644 --- a/clang/lib/AST/DeclObjC.cpp +++ b/clang/lib/AST/DeclObjC.cpp @@ -66,7 +66,8 @@ void ObjCProtocolList::set(ObjCProtocolDecl* const* InList, unsigned Elts, //===----------------------------------------------------------------------===// ObjCContainerDecl::ObjCContainerDecl(Kind DK, DeclContext *DC, - IdentifierInfo *Id, SourceLocation nameLoc, + const IdentifierInfo *Id, + SourceLocation nameLoc, SourceLocation atStartLoc) : NamedDecl(DK, DC, nameLoc, Id), DeclContext(DK) { setAtStartLoc(atStartLoc); @@ -378,10 +379,8 @@ SourceLocation ObjCInterfaceDecl::getSuperClassLoc() const { /// FindPropertyVisibleInPrimaryClass - Finds declaration of the property /// with name 'PropertyId' in the primary class; including those in protocols /// (direct or indirect) used by the primary class. -ObjCPropertyDecl * -ObjCInterfaceDecl::FindPropertyVisibleInPrimaryClass( - IdentifierInfo *PropertyId, - ObjCPropertyQueryKind QueryKind) const { +ObjCPropertyDecl *ObjCInterfaceDecl::FindPropertyVisibleInPrimaryClass( + const IdentifierInfo *PropertyId, ObjCPropertyQueryKind QueryKind) const { // FIXME: Should make sure no callers ever do this. if (!hasDefinition()) return nullptr; @@ -1539,14 +1538,10 @@ void ObjCTypeParamList::gatherDefaultTypeArgs( // ObjCInterfaceDecl //===----------------------------------------------------------------------===// -ObjCInterfaceDecl *ObjCInterfaceDecl::Create(const ASTContext &C, - DeclContext *DC, - SourceLocation atLoc, - IdentifierInfo *Id, - ObjCTypeParamList *typeParamList, - ObjCInterfaceDecl *PrevDecl, - SourceLocation ClassLoc, - bool isInternal){ +ObjCInterfaceDecl *ObjCInterfaceDecl::Create( + const ASTContext &C, DeclContext *DC, SourceLocation atLoc, + const IdentifierInfo *Id, ObjCTypeParamList *typeParamList, + ObjCInterfaceDecl *PrevDecl, SourceLocation ClassLoc, bool isInternal) { auto *Result = new (C, DC) ObjCInterfaceDecl(C, DC, atLoc, Id, typeParamList, ClassLoc, PrevDecl, isInternal); @@ -1564,12 +1559,10 @@ ObjCInterfaceDecl *ObjCInterfaceDecl::CreateDeserialized(const ASTContext &C, return Result; } -ObjCInterfaceDecl::ObjCInterfaceDecl(const ASTContext &C, DeclContext *DC, - SourceLocation AtLoc, IdentifierInfo *Id, - ObjCTypeParamList *typeParamList, - SourceLocation CLoc, - ObjCInterfaceDecl *PrevDecl, - bool IsInternal) +ObjCInterfaceDecl::ObjCInterfaceDecl( + const ASTContext &C, DeclContext *DC, SourceLocation AtLoc, + const IdentifierInfo *Id, ObjCTypeParamList *typeParamList, + SourceLocation CLoc, ObjCInterfaceDecl *PrevDecl, bool IsInternal) : ObjCContainerDecl(ObjCInterface, DC, Id, CLoc, AtLoc), redeclarable_base(C) { setPreviousDecl(PrevDecl); @@ -1751,8 +1744,8 @@ ObjCIvarDecl *ObjCInterfaceDecl::all_declared_ivar_begin() { /// categories for this class and returns it. Name of the category is passed /// in 'CategoryId'. If category not found, return 0; /// -ObjCCategoryDecl * -ObjCInterfaceDecl::FindCategoryDeclaration(IdentifierInfo *CategoryId) const { +ObjCCategoryDecl *ObjCInterfaceDecl::FindCategoryDeclaration( + const IdentifierInfo *CategoryId) const { // FIXME: Should make sure no callers ever do this. if (!hasDefinition()) return nullptr; @@ -1838,10 +1831,10 @@ void ObjCIvarDecl::anchor() {} ObjCIvarDecl *ObjCIvarDecl::Create(ASTContext &C, ObjCContainerDecl *DC, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, - QualType T, TypeSourceInfo *TInfo, - AccessControl ac, Expr *BW, - bool synthesized) { + SourceLocation IdLoc, + const IdentifierInfo *Id, QualType T, + TypeSourceInfo *TInfo, AccessControl ac, + Expr *BW, bool synthesized) { if (DC) { // Ivar's can only appear in interfaces, implementations (via synthesized // properties), and class extensions (via direct declaration, or synthesized @@ -2120,28 +2113,23 @@ void ObjCProtocolDecl::setHasODRHash(bool HasHash) { void ObjCCategoryDecl::anchor() {} -ObjCCategoryDecl::ObjCCategoryDecl(DeclContext *DC, SourceLocation AtLoc, - SourceLocation ClassNameLoc, - SourceLocation CategoryNameLoc, - IdentifierInfo *Id, ObjCInterfaceDecl *IDecl, - ObjCTypeParamList *typeParamList, - SourceLocation IvarLBraceLoc, - SourceLocation IvarRBraceLoc) +ObjCCategoryDecl::ObjCCategoryDecl( + DeclContext *DC, SourceLocation AtLoc, SourceLocation ClassNameLoc, + SourceLocation CategoryNameLoc, const IdentifierInfo *Id, + ObjCInterfaceDecl *IDecl, ObjCTypeParamList *typeParamList, + SourceLocation IvarLBraceLoc, SourceLocation IvarRBraceLoc) : ObjCContainerDecl(ObjCCategory, DC, Id, ClassNameLoc, AtLoc), ClassInterface(IDecl), CategoryNameLoc(CategoryNameLoc), IvarLBraceLoc(IvarLBraceLoc), IvarRBraceLoc(IvarRBraceLoc) { setTypeParamList(typeParamList); } -ObjCCategoryDecl *ObjCCategoryDecl::Create(ASTContext &C, DeclContext *DC, - SourceLocation AtLoc, - SourceLocation ClassNameLoc, - SourceLocation CategoryNameLoc, - IdentifierInfo *Id, - ObjCInterfaceDecl *IDecl, - ObjCTypeParamList *typeParamList, - SourceLocation IvarLBraceLoc, - SourceLocation IvarRBraceLoc) { +ObjCCategoryDecl *ObjCCategoryDecl::Create( + ASTContext &C, DeclContext *DC, SourceLocation AtLoc, + SourceLocation ClassNameLoc, SourceLocation CategoryNameLoc, + const IdentifierInfo *Id, ObjCInterfaceDecl *IDecl, + ObjCTypeParamList *typeParamList, SourceLocation IvarLBraceLoc, + SourceLocation IvarRBraceLoc) { auto *CatDecl = new (C, DC) ObjCCategoryDecl(DC, AtLoc, ClassNameLoc, CategoryNameLoc, Id, IDecl, typeParamList, IvarLBraceLoc, @@ -2190,13 +2178,10 @@ void ObjCCategoryDecl::setTypeParamList(ObjCTypeParamList *TPL) { void ObjCCategoryImplDecl::anchor() {} -ObjCCategoryImplDecl * -ObjCCategoryImplDecl::Create(ASTContext &C, DeclContext *DC, - IdentifierInfo *Id, - ObjCInterfaceDecl *ClassInterface, - SourceLocation nameLoc, - SourceLocation atStartLoc, - SourceLocation CategoryNameLoc) { +ObjCCategoryImplDecl *ObjCCategoryImplDecl::Create( + ASTContext &C, DeclContext *DC, const IdentifierInfo *Id, + ObjCInterfaceDecl *ClassInterface, SourceLocation nameLoc, + SourceLocation atStartLoc, SourceLocation CategoryNameLoc) { if (ClassInterface && ClassInterface->hasDefinition()) ClassInterface = ClassInterface->getDefinition(); return new (C, DC) ObjCCategoryImplDecl(DC, Id, ClassInterface, nameLoc, @@ -2365,14 +2350,11 @@ ObjCCompatibleAliasDecl::CreateDeserialized(ASTContext &C, unsigned ID) { void ObjCPropertyDecl::anchor() {} -ObjCPropertyDecl *ObjCPropertyDecl::Create(ASTContext &C, DeclContext *DC, - SourceLocation L, - IdentifierInfo *Id, - SourceLocation AtLoc, - SourceLocation LParenLoc, - QualType T, - TypeSourceInfo *TSI, - PropertyControl propControl) { +ObjCPropertyDecl * +ObjCPropertyDecl::Create(ASTContext &C, DeclContext *DC, SourceLocation L, + const IdentifierInfo *Id, SourceLocation AtLoc, + SourceLocation LParenLoc, QualType T, + TypeSourceInfo *TSI, PropertyControl propControl) { return new (C, DC) ObjCPropertyDecl(DC, L, Id, AtLoc, LParenLoc, T, TSI, propControl); } diff --git a/clang/lib/AST/DeclTemplate.cpp b/clang/lib/AST/DeclTemplate.cpp index 3c217d6a6a5a..571ed81a42e4 100644 --- a/clang/lib/AST/DeclTemplate.cpp +++ b/clang/lib/AST/DeclTemplate.cpp @@ -715,7 +715,7 @@ void TemplateTypeParmDecl::setTypeConstraint( NonTypeTemplateParmDecl::NonTypeTemplateParmDecl( DeclContext *DC, SourceLocation StartLoc, SourceLocation IdLoc, unsigned D, - unsigned P, IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, + unsigned P, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, ArrayRef ExpandedTypes, ArrayRef ExpandedTInfos) : DeclaratorDecl(NonTypeTemplateParm, DC, IdLoc, Id, T, TInfo, StartLoc), TemplateParmPosition(D, P), ParameterPack(true), @@ -730,12 +730,10 @@ NonTypeTemplateParmDecl::NonTypeTemplateParmDecl( } } -NonTypeTemplateParmDecl * -NonTypeTemplateParmDecl::Create(const ASTContext &C, DeclContext *DC, - SourceLocation StartLoc, SourceLocation IdLoc, - unsigned D, unsigned P, IdentifierInfo *Id, - QualType T, bool ParameterPack, - TypeSourceInfo *TInfo) { +NonTypeTemplateParmDecl *NonTypeTemplateParmDecl::Create( + const ASTContext &C, DeclContext *DC, SourceLocation StartLoc, + SourceLocation IdLoc, unsigned D, unsigned P, const IdentifierInfo *Id, + QualType T, bool ParameterPack, TypeSourceInfo *TInfo) { AutoType *AT = C.getLangOpts().CPlusPlus20 ? T->getContainedAutoType() : nullptr; return new (C, DC, @@ -748,7 +746,7 @@ NonTypeTemplateParmDecl::Create(const ASTContext &C, DeclContext *DC, NonTypeTemplateParmDecl *NonTypeTemplateParmDecl::Create( const ASTContext &C, DeclContext *DC, SourceLocation StartLoc, - SourceLocation IdLoc, unsigned D, unsigned P, IdentifierInfo *Id, + SourceLocation IdLoc, unsigned D, unsigned P, const IdentifierInfo *Id, QualType T, TypeSourceInfo *TInfo, ArrayRef ExpandedTypes, ArrayRef ExpandedTInfos) { AutoType *AT = TInfo->getType()->getContainedAutoType(); diff --git a/clang/lib/AST/NSAPI.cpp b/clang/lib/AST/NSAPI.cpp index 86dee540e9e2..ecc56c13fb75 100644 --- a/clang/lib/AST/NSAPI.cpp +++ b/clang/lib/AST/NSAPI.cpp @@ -56,10 +56,8 @@ Selector NSAPI::getNSStringSelector(NSStringMethodKind MK) const { &Ctx.Idents.get("initWithUTF8String")); break; case NSStr_stringWithCStringEncoding: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("stringWithCString"), - &Ctx.Idents.get("encoding") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("stringWithCString"), + &Ctx.Idents.get("encoding")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -93,10 +91,8 @@ Selector NSAPI::getNSArraySelector(NSArrayMethodKind MK) const { Sel = Ctx.Selectors.getUnarySelector(&Ctx.Idents.get("arrayWithObjects")); break; case NSArr_arrayWithObjectsCount: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("arrayWithObjects"), - &Ctx.Idents.get("count") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("arrayWithObjects"), + &Ctx.Idents.get("count")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -110,10 +106,9 @@ Selector NSAPI::getNSArraySelector(NSArrayMethodKind MK) const { Sel = Ctx.Selectors.getUnarySelector(&Ctx.Idents.get("objectAtIndex")); break; case NSMutableArr_replaceObjectAtIndex: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("replaceObjectAtIndex"), - &Ctx.Idents.get("withObject") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("replaceObjectAtIndex"), + &Ctx.Idents.get("withObject")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -121,18 +116,14 @@ Selector NSAPI::getNSArraySelector(NSArrayMethodKind MK) const { Sel = Ctx.Selectors.getUnarySelector(&Ctx.Idents.get("addObject")); break; case NSMutableArr_insertObjectAtIndex: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("insertObject"), - &Ctx.Idents.get("atIndex") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("insertObject"), + &Ctx.Idents.get("atIndex")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSMutableArr_setObjectAtIndexedSubscript: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("setObject"), - &Ctx.Idents.get("atIndexedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("setObject"), &Ctx.Idents.get("atIndexedSubscript")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -167,27 +158,21 @@ Selector NSAPI::getNSDictionarySelector( &Ctx.Idents.get("dictionaryWithDictionary")); break; case NSDict_dictionaryWithObjectForKey: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("dictionaryWithObject"), - &Ctx.Idents.get("forKey") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("dictionaryWithObject"), &Ctx.Idents.get("forKey")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSDict_dictionaryWithObjectsForKeys: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("dictionaryWithObjects"), - &Ctx.Idents.get("forKeys") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("dictionaryWithObjects"), &Ctx.Idents.get("forKeys")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSDict_dictionaryWithObjectsForKeysCount: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("dictionaryWithObjects"), - &Ctx.Idents.get("forKeys"), - &Ctx.Idents.get("count") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("dictionaryWithObjects"), &Ctx.Idents.get("forKeys"), + &Ctx.Idents.get("count")}; Sel = Ctx.Selectors.getSelector(3, KeyIdents); break; } @@ -204,10 +189,8 @@ Selector NSAPI::getNSDictionarySelector( &Ctx.Idents.get("initWithObjectsAndKeys")); break; case NSDict_initWithObjectsForKeys: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("initWithObjects"), - &Ctx.Idents.get("forKeys") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("initWithObjects"), + &Ctx.Idents.get("forKeys")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -215,26 +198,20 @@ Selector NSAPI::getNSDictionarySelector( Sel = Ctx.Selectors.getUnarySelector(&Ctx.Idents.get("objectForKey")); break; case NSMutableDict_setObjectForKey: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("setObject"), - &Ctx.Idents.get("forKey") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("setObject"), + &Ctx.Idents.get("forKey")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSMutableDict_setObjectForKeyedSubscript: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("setObject"), - &Ctx.Idents.get("forKeyedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("setObject"), &Ctx.Idents.get("forKeyedSubscript")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSMutableDict_setValueForKey: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("setValue"), - &Ctx.Idents.get("forKey") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("setValue"), + &Ctx.Idents.get("forKey")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -264,34 +241,27 @@ Selector NSAPI::getNSSetSelector(NSSetMethodKind MK) const { Sel = Ctx.Selectors.getUnarySelector(&Ctx.Idents.get("addObject")); break; case NSOrderedSet_insertObjectAtIndex: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("insertObject"), - &Ctx.Idents.get("atIndex") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("insertObject"), + &Ctx.Idents.get("atIndex")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSOrderedSet_setObjectAtIndex: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("setObject"), - &Ctx.Idents.get("atIndex") - }; + const IdentifierInfo *KeyIdents[] = {&Ctx.Idents.get("setObject"), + &Ctx.Idents.get("atIndex")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSOrderedSet_setObjectAtIndexedSubscript: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("setObject"), - &Ctx.Idents.get("atIndexedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("setObject"), &Ctx.Idents.get("atIndexedSubscript")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } case NSOrderedSet_replaceObjectAtIndexWithObject: { - IdentifierInfo *KeyIdents[] = { - &Ctx.Idents.get("replaceObjectAtIndex"), - &Ctx.Idents.get("withObject") - }; + const IdentifierInfo *KeyIdents[] = { + &Ctx.Idents.get("replaceObjectAtIndex"), + &Ctx.Idents.get("withObject")}; Sel = Ctx.Selectors.getSelector(2, KeyIdents); break; } @@ -606,7 +576,7 @@ bool NSAPI::isObjCEnumerator(const Expr *E, Selector NSAPI::getOrInitSelector(ArrayRef Ids, Selector &Sel) const { if (Sel.isNull()) { - SmallVector Idents; + SmallVector Idents; for (ArrayRef::const_iterator I = Ids.begin(), E = Ids.end(); I != E; ++I) Idents.push_back(&Ctx.Idents.get(*I)); @@ -617,7 +587,7 @@ Selector NSAPI::getOrInitSelector(ArrayRef Ids, Selector NSAPI::getOrInitNullarySelector(StringRef Id, Selector &Sel) const { if (Sel.isNull()) { - IdentifierInfo *Ident = &Ctx.Idents.get(Id); + const IdentifierInfo *Ident = &Ctx.Idents.get(Id); Sel = Ctx.Selectors.getSelector(0, &Ident); } return Sel; diff --git a/clang/lib/AST/NestedNameSpecifier.cpp b/clang/lib/AST/NestedNameSpecifier.cpp index 36f2c47b3000..785c46e86a77 100644 --- a/clang/lib/AST/NestedNameSpecifier.cpp +++ b/clang/lib/AST/NestedNameSpecifier.cpp @@ -55,16 +55,16 @@ NestedNameSpecifier::FindOrInsert(const ASTContext &Context, return NNS; } -NestedNameSpecifier * -NestedNameSpecifier::Create(const ASTContext &Context, - NestedNameSpecifier *Prefix, IdentifierInfo *II) { +NestedNameSpecifier *NestedNameSpecifier::Create(const ASTContext &Context, + NestedNameSpecifier *Prefix, + const IdentifierInfo *II) { assert(II && "Identifier cannot be NULL"); assert((!Prefix || Prefix->isDependent()) && "Prefix must be dependent"); NestedNameSpecifier Mockup; Mockup.Prefix.setPointer(Prefix); Mockup.Prefix.setInt(StoredIdentifier); - Mockup.Specifier = II; + Mockup.Specifier = const_cast(II); return FindOrInsert(Context, Mockup); } @@ -87,7 +87,7 @@ NestedNameSpecifier::Create(const ASTContext &Context, NestedNameSpecifier * NestedNameSpecifier::Create(const ASTContext &Context, NestedNameSpecifier *Prefix, - NamespaceAliasDecl *Alias) { + const NamespaceAliasDecl *Alias) { assert(Alias && "Namespace alias cannot be NULL"); assert((!Prefix || (Prefix->getAsType() == nullptr && @@ -96,7 +96,7 @@ NestedNameSpecifier::Create(const ASTContext &Context, NestedNameSpecifier Mockup; Mockup.Prefix.setPointer(Prefix); Mockup.Prefix.setInt(StoredDecl); - Mockup.Specifier = Alias; + Mockup.Specifier = const_cast(Alias); return FindOrInsert(Context, Mockup); } @@ -112,13 +112,13 @@ NestedNameSpecifier::Create(const ASTContext &Context, return FindOrInsert(Context, Mockup); } -NestedNameSpecifier * -NestedNameSpecifier::Create(const ASTContext &Context, IdentifierInfo *II) { +NestedNameSpecifier *NestedNameSpecifier::Create(const ASTContext &Context, + const IdentifierInfo *II) { assert(II && "Identifier cannot be NULL"); NestedNameSpecifier Mockup; Mockup.Prefix.setPointer(nullptr); Mockup.Prefix.setInt(StoredIdentifier); - Mockup.Specifier = II; + Mockup.Specifier = const_cast(II); return FindOrInsert(Context, Mockup); } diff --git a/clang/lib/AST/SelectorLocationsKind.cpp b/clang/lib/AST/SelectorLocationsKind.cpp index 2c34c9c60c2b..ebe6324f904c 100644 --- a/clang/lib/AST/SelectorLocationsKind.cpp +++ b/clang/lib/AST/SelectorLocationsKind.cpp @@ -26,7 +26,7 @@ static SourceLocation getStandardSelLoc(unsigned Index, assert(Index == 0); if (EndLoc.isInvalid()) return SourceLocation(); - IdentifierInfo *II = Sel.getIdentifierInfoForSlot(0); + const IdentifierInfo *II = Sel.getIdentifierInfoForSlot(0); unsigned Len = II ? II->getLength() : 0; return EndLoc.getLocWithOffset(-Len); } @@ -34,7 +34,7 @@ static SourceLocation getStandardSelLoc(unsigned Index, assert(Index < NumSelArgs); if (ArgLoc.isInvalid()) return SourceLocation(); - IdentifierInfo *II = Sel.getIdentifierInfoForSlot(Index); + const IdentifierInfo *II = Sel.getIdentifierInfoForSlot(Index); unsigned Len = /* selector id */ (II ? II->getLength() : 0) + /* ':' */ 1; if (WithArgSpace) ++Len; diff --git a/clang/lib/AST/StmtPrinter.cpp b/clang/lib/AST/StmtPrinter.cpp index 2ba93d17f267..5855ab3141ed 100644 --- a/clang/lib/AST/StmtPrinter.cpp +++ b/clang/lib/AST/StmtPrinter.cpp @@ -1447,7 +1447,7 @@ void StmtPrinter::VisitOffsetOfExpr(OffsetOfExpr *Node) { continue; // Field or identifier node. - IdentifierInfo *Id = ON.getFieldName(); + const IdentifierInfo *Id = ON.getFieldName(); if (!Id) continue; @@ -2348,7 +2348,7 @@ void StmtPrinter::VisitCXXPseudoDestructorExpr(CXXPseudoDestructorExpr *E) { E->getQualifier()->print(OS, Policy); OS << "~"; - if (IdentifierInfo *II = E->getDestroyedTypeIdentifier()) + if (const IdentifierInfo *II = E->getDestroyedTypeIdentifier()) OS << II->getName(); else E->getDestroyedType().print(OS, Policy); diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index be3dd4b673cf..01e1d1cc8289 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -61,7 +61,7 @@ namespace { virtual void VisitName(DeclarationName Name, bool TreatAsDecl = false) = 0; /// Visit identifiers that are not in Decl's or Type's. - virtual void VisitIdentifierInfo(IdentifierInfo *II) = 0; + virtual void VisitIdentifierInfo(const IdentifierInfo *II) = 0; /// Visit a nested-name-specifier that occurs within an expression /// or statement. @@ -163,7 +163,7 @@ namespace { ID.AddPointer(Name.getAsOpaquePtr()); } - void VisitIdentifierInfo(IdentifierInfo *II) override { + void VisitIdentifierInfo(const IdentifierInfo *II) override { ID.AddPointer(II); } @@ -211,7 +211,7 @@ namespace { } Hash.AddDeclarationName(Name, TreatAsDecl); } - void VisitIdentifierInfo(IdentifierInfo *II) override { + void VisitIdentifierInfo(const IdentifierInfo *II) override { ID.AddBoolean(II); if (II) { Hash.AddIdentifierInfo(II); diff --git a/clang/lib/Analysis/ObjCNoReturn.cpp b/clang/lib/Analysis/ObjCNoReturn.cpp index 9d7c365c3b99..9e651c29e085 100644 --- a/clang/lib/Analysis/ObjCNoReturn.cpp +++ b/clang/lib/Analysis/ObjCNoReturn.cpp @@ -17,7 +17,8 @@ using namespace clang; -static bool isSubclass(const ObjCInterfaceDecl *Class, IdentifierInfo *II) { +static bool isSubclass(const ObjCInterfaceDecl *Class, + const IdentifierInfo *II) { if (!Class) return false; if (Class->getIdentifier() == II) @@ -30,7 +31,7 @@ ObjCNoReturn::ObjCNoReturn(ASTContext &C) NSExceptionII(&C.Idents.get("NSException")) { // Generate selectors. - SmallVector II; + SmallVector II; // raise:format: II.push_back(&C.Idents.get("raise")); diff --git a/clang/lib/Basic/IdentifierTable.cpp b/clang/lib/Basic/IdentifierTable.cpp index a9b07aca65c0..feea84544d62 100644 --- a/clang/lib/Basic/IdentifierTable.cpp +++ b/clang/lib/Basic/IdentifierTable.cpp @@ -541,7 +541,8 @@ unsigned Selector::getNumArgs() const { return SI->getNumArgs(); } -IdentifierInfo *Selector::getIdentifierInfoForSlot(unsigned argIndex) const { +const IdentifierInfo * +Selector::getIdentifierInfoForSlot(unsigned argIndex) const { if (getIdentifierInfoFlag() < MultiArg) { assert(argIndex == 0 && "illegal keyword index"); return getAsIdentifierInfo(); @@ -553,7 +554,7 @@ IdentifierInfo *Selector::getIdentifierInfoForSlot(unsigned argIndex) const { } StringRef Selector::getNameForSlot(unsigned int argIndex) const { - IdentifierInfo *II = getIdentifierInfoForSlot(argIndex); + const IdentifierInfo *II = getIdentifierInfoForSlot(argIndex); return II ? II->getName() : StringRef(); } @@ -574,7 +575,7 @@ std::string Selector::getAsString() const { return ""; if (getIdentifierInfoFlag() < MultiArg) { - IdentifierInfo *II = getAsIdentifierInfo(); + const IdentifierInfo *II = getAsIdentifierInfo(); if (getNumArgs() == 0) { assert(II && "If the number of arguments is 0 then II is guaranteed to " @@ -608,7 +609,7 @@ static bool startsWithWord(StringRef name, StringRef word) { } ObjCMethodFamily Selector::getMethodFamilyImpl(Selector sel) { - IdentifierInfo *first = sel.getIdentifierInfoForSlot(0); + const IdentifierInfo *first = sel.getIdentifierInfoForSlot(0); if (!first) return OMF_None; StringRef name = first->getName(); @@ -655,7 +656,7 @@ ObjCMethodFamily Selector::getMethodFamilyImpl(Selector sel) { } ObjCInstanceTypeFamily Selector::getInstTypeMethodFamily(Selector sel) { - IdentifierInfo *first = sel.getIdentifierInfoForSlot(0); + const IdentifierInfo *first = sel.getIdentifierInfoForSlot(0); if (!first) return OIT_None; StringRef name = first->getName(); @@ -683,7 +684,7 @@ ObjCInstanceTypeFamily Selector::getInstTypeMethodFamily(Selector sel) { } ObjCStringFormatFamily Selector::getStringFormatFamilyImpl(Selector sel) { - IdentifierInfo *first = sel.getIdentifierInfoForSlot(0); + const IdentifierInfo *first = sel.getIdentifierInfoForSlot(0); if (!first) return SFF_None; StringRef name = first->getName(); @@ -750,7 +751,8 @@ size_t SelectorTable::getTotalMemory() const { return SelTabImpl.Allocator.getTotalMemory(); } -Selector SelectorTable::getSelector(unsigned nKeys, IdentifierInfo **IIV) { +Selector SelectorTable::getSelector(unsigned nKeys, + const IdentifierInfo **IIV) { if (nKeys < 2) return Selector(IIV[0], nKeys); diff --git a/clang/lib/CodeGen/CGBlocks.cpp b/clang/lib/CodeGen/CGBlocks.cpp index 47f063b5501c..2742c39965b2 100644 --- a/clang/lib/CodeGen/CGBlocks.cpp +++ b/clang/lib/CodeGen/CGBlocks.cpp @@ -1447,7 +1447,7 @@ llvm::Function *CodeGenFunction::GenerateBlockFunction( selfTy = getContext().getPointerType(getContext().getAddrSpaceQualType( getContext().VoidTy, LangAS::opencl_generic)); - IdentifierInfo *II = &CGM.getContext().Idents.get(".block_descriptor"); + const IdentifierInfo *II = &CGM.getContext().Idents.get(".block_descriptor"); ImplicitParamDecl SelfDecl(getContext(), const_cast(blockDecl), SourceLocation(), II, selfTy, @@ -2791,7 +2791,7 @@ static void configureBlocksRuntimeObject(CodeGenModule &CGM, auto *GV = cast(C->stripPointerCasts()); if (CGM.getTarget().getTriple().isOSBinFormatCOFF()) { - IdentifierInfo &II = CGM.getContext().Idents.get(C->getName()); + const IdentifierInfo &II = CGM.getContext().Idents.get(C->getName()); TranslationUnitDecl *TUDecl = CGM.getContext().getTranslationUnitDecl(); DeclContext *DC = TranslationUnitDecl::castToDeclContext(TUDecl); diff --git a/clang/lib/CodeGen/CGCUDANV.cpp b/clang/lib/CodeGen/CGCUDANV.cpp index 0cb5b06a519c..370642cb3d53 100644 --- a/clang/lib/CodeGen/CGCUDANV.cpp +++ b/clang/lib/CodeGen/CGCUDANV.cpp @@ -361,7 +361,7 @@ void CGNVCUDARuntime::emitDeviceStubBodyNew(CodeGenFunction &CGF, KernelLaunchAPI = KernelLaunchAPI + "_ptsz"; } auto LaunchKernelName = addPrefixToName(KernelLaunchAPI); - IdentifierInfo &cudaLaunchKernelII = + const IdentifierInfo &cudaLaunchKernelII = CGM.getContext().Idents.get(LaunchKernelName); FunctionDecl *cudaLaunchKernelFD = nullptr; for (auto *Result : DC->lookup(&cudaLaunchKernelII)) { diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index 4f4013292b1f..8bdafa7c569b 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -1384,7 +1384,7 @@ void CodeGenFunction::EmitAndRegisterVariableArrayDimensions( // For each dimension stores its QualType and corresponding // size-expression Value. SmallVector Dimensions; - SmallVector VLAExprNames; + SmallVector VLAExprNames; // Break down the array into individual dimensions. QualType Type1D = D.getType(); @@ -1421,7 +1421,7 @@ void CodeGenFunction::EmitAndRegisterVariableArrayDimensions( MD = llvm::ConstantAsMetadata::get(C); else { // Create an artificial VarDecl to generate debug info for. - IdentifierInfo *NameIdent = VLAExprNames[NameIdx++]; + const IdentifierInfo *NameIdent = VLAExprNames[NameIdx++]; auto QT = getContext().getIntTypeForBitwidth( SizeTy->getScalarSizeInBits(), false); auto *ArtificialDecl = VarDecl::Create( diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp index c7f497a7c845..ee571995ce4c 100644 --- a/clang/lib/CodeGen/CGObjC.cpp +++ b/clang/lib/CodeGen/CGObjC.cpp @@ -1789,11 +1789,10 @@ void CodeGenFunction::EmitObjCForCollectionStmt(const ObjCForCollectionStmt &S){ static const unsigned NumItems = 16; // Fetch the countByEnumeratingWithState:objects:count: selector. - IdentifierInfo *II[] = { - &CGM.getContext().Idents.get("countByEnumeratingWithState"), - &CGM.getContext().Idents.get("objects"), - &CGM.getContext().Idents.get("count") - }; + const IdentifierInfo *II[] = { + &CGM.getContext().Idents.get("countByEnumeratingWithState"), + &CGM.getContext().Idents.get("objects"), + &CGM.getContext().Idents.get("count")}; Selector FastEnumSel = CGM.getContext().Selectors.getSelector(std::size(II), &II[0]); @@ -2720,7 +2719,7 @@ llvm::Value *CodeGenFunction::EmitObjCMRRAutoreleasePoolPush() { CGObjCRuntime &Runtime = CGM.getObjCRuntime(); llvm::Value *Receiver = Runtime.EmitNSAutoreleasePoolClassRef(*this); // [NSAutoreleasePool alloc] - IdentifierInfo *II = &CGM.getContext().Idents.get("alloc"); + const IdentifierInfo *II = &CGM.getContext().Idents.get("alloc"); Selector AllocSel = getContext().Selectors.getSelector(0, &II); CallArgList Args; RValue AllocRV = @@ -2767,7 +2766,7 @@ llvm::Value *CodeGenFunction::EmitObjCAllocInit(llvm::Value *value, /// Produce the code to do a primitive release. /// [tmp drain]; void CodeGenFunction::EmitObjCMRRAutoreleasePoolPop(llvm::Value *Arg) { - IdentifierInfo *II = &CGM.getContext().Idents.get("drain"); + const IdentifierInfo *II = &CGM.getContext().Idents.get("drain"); Selector DrainSel = getContext().Selectors.getSelector(0, &II); CallArgList Args; CGM.getObjCRuntime().GenerateMessageSend(*this, ReturnValueSlot(), @@ -3715,8 +3714,8 @@ CodeGenFunction::GenerateObjCAtomicSetterCopyHelperFunction( if ((HelperFn = CGM.getAtomicSetterHelperFnMap(Ty))) return HelperFn; - IdentifierInfo *II - = &CGM.getContext().Idents.get("__assign_helper_atomic_property_"); + const IdentifierInfo *II = + &CGM.getContext().Idents.get("__assign_helper_atomic_property_"); QualType ReturnTy = C.VoidTy; QualType DestTy = C.getPointerType(Ty); @@ -3813,7 +3812,7 @@ llvm::Constant *CodeGenFunction::GenerateObjCAtomicGetterCopyHelperFunction( if ((HelperFn = CGM.getAtomicGetterHelperFnMap(Ty))) return HelperFn; - IdentifierInfo *II = + const IdentifierInfo *II = &CGM.getContext().Idents.get("__copy_helper_atomic_property_"); QualType ReturnTy = C.VoidTy; @@ -3907,10 +3906,10 @@ llvm::Constant *CodeGenFunction::GenerateObjCAtomicGetterCopyHelperFunction( llvm::Value * CodeGenFunction::EmitBlockCopyAndAutorelease(llvm::Value *Block, QualType Ty) { // Get selectors for retain/autorelease. - IdentifierInfo *CopyID = &getContext().Idents.get("copy"); + const IdentifierInfo *CopyID = &getContext().Idents.get("copy"); Selector CopySelector = getContext().Selectors.getNullarySelector(CopyID); - IdentifierInfo *AutoreleaseID = &getContext().Idents.get("autorelease"); + const IdentifierInfo *AutoreleaseID = &getContext().Idents.get("autorelease"); Selector AutoreleaseSelector = getContext().Selectors.getNullarySelector(AutoreleaseID); diff --git a/clang/lib/CodeGen/CGObjCMac.cpp b/clang/lib/CodeGen/CGObjCMac.cpp index 8a599c10e1ca..042cd5d46da4 100644 --- a/clang/lib/CodeGen/CGObjCMac.cpp +++ b/clang/lib/CodeGen/CGObjCMac.cpp @@ -1555,12 +1555,12 @@ private: // Shamelessly stolen from Analysis/CFRefCount.cpp Selector GetNullarySelector(const char* name) const { - IdentifierInfo* II = &CGM.getContext().Idents.get(name); + const IdentifierInfo *II = &CGM.getContext().Idents.get(name); return CGM.getContext().Selectors.getSelector(0, &II); } Selector GetUnarySelector(const char* name) const { - IdentifierInfo* II = &CGM.getContext().Idents.get(name); + const IdentifierInfo *II = &CGM.getContext().Idents.get(name); return CGM.getContext().Selectors.getSelector(1, &II); } @@ -6268,11 +6268,10 @@ bool CGObjCNonFragileABIMac::isVTableDispatchedSelector(Selector Sel) { VTableDispatchMethods.insert(GetUnarySelector("addObject")); // "countByEnumeratingWithState:objects:count" - IdentifierInfo *KeyIdents[] = { - &CGM.getContext().Idents.get("countByEnumeratingWithState"), - &CGM.getContext().Idents.get("objects"), - &CGM.getContext().Idents.get("count") - }; + const IdentifierInfo *KeyIdents[] = { + &CGM.getContext().Idents.get("countByEnumeratingWithState"), + &CGM.getContext().Idents.get("objects"), + &CGM.getContext().Idents.get("count")}; VTableDispatchMethods.insert( CGM.getContext().Selectors.getSelector(3, KeyIdents)); } diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index a2d746bb8f4f..87766a758311 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -828,7 +828,7 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy, // .cxx_destruct, __destroy_helper_block_ and all of their calees at run time. if (SanOpts.has(SanitizerKind::Thread)) { if (const auto *OMD = dyn_cast_or_null(D)) { - IdentifierInfo *II = OMD->getSelector().getIdentifierInfoForSlot(0); + const IdentifierInfo *II = OMD->getSelector().getIdentifierInfoForSlot(0); if (OMD->getMethodFamily() == OMF_dealloc || OMD->getMethodFamily() == OMF_initialize || (OMD->getSelector().isUnarySelector() && II->isStr(".cxx_destruct"))) { diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 75519be8bba0..b15031dca468 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -6626,7 +6626,7 @@ static bool AllTrivialInitializers(CodeGenModule &CGM, void CodeGenModule::EmitObjCIvarInitializations(ObjCImplementationDecl *D) { // We might need a .cxx_destruct even if we don't have any ivar initializers. if (needsDestructMethod(D)) { - IdentifierInfo *II = &getContext().Idents.get(".cxx_destruct"); + const IdentifierInfo *II = &getContext().Idents.get(".cxx_destruct"); Selector cxxSelector = getContext().Selectors.getSelector(0, &II); ObjCMethodDecl *DTORMethod = ObjCMethodDecl::Create( getContext(), D->getLocation(), D->getLocation(), cxxSelector, @@ -6646,7 +6646,7 @@ void CodeGenModule::EmitObjCIvarInitializations(ObjCImplementationDecl *D) { AllTrivialInitializers(*this, D)) return; - IdentifierInfo *II = &getContext().Idents.get(".cxx_construct"); + const IdentifierInfo *II = &getContext().Idents.get(".cxx_construct"); Selector cxxSelector = getContext().Selectors.getSelector(0, &II); // The constructor returns 'self'. ObjCMethodDecl *CTORMethod = ObjCMethodDecl::Create( @@ -7214,7 +7214,7 @@ void CodeGenModule::EmitStaticExternCAliases() { if (!getTargetCodeGenInfo().shouldEmitStaticExternCAliases()) return; for (auto &I : StaticExternCValues) { - IdentifierInfo *Name = I.first; + const IdentifierInfo *Name = I.first; llvm::GlobalValue *Val = I.second; // If Val is null, that implies there were multiple declarations that each diff --git a/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp b/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp index 1f40db785981..6ae955a2380b 100644 --- a/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp +++ b/clang/lib/Frontend/Rewrite/RewriteModernObjC.cpp @@ -592,7 +592,7 @@ namespace { } bool ImplementationIsNonLazy(const ObjCImplDecl *OD) const { - IdentifierInfo* II = &Context->Idents.get("load"); + const IdentifierInfo *II = &Context->Idents.get("load"); Selector LoadSel = Context->Selectors.getSelector(0, &II); return OD->getClassMethod(LoadSel) != nullptr; } diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index 7dffcf0e941e..f0750e5336b6 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -64,8 +64,7 @@ HeaderFileInfo::getControllingMacro(ExternalPreprocessorSource *External) { if (ControllingMacro->isOutOfDate()) { assert(External && "We must have an external source if we have a " "controlling macro that is out of date."); - External->updateOutOfDateIdentifier( - *const_cast(ControllingMacro)); + External->updateOutOfDateIdentifier(*ControllingMacro); } return ControllingMacro; } diff --git a/clang/lib/Lex/MacroInfo.cpp b/clang/lib/Lex/MacroInfo.cpp index 39bb0f44eff2..dfdf463665f3 100644 --- a/clang/lib/Lex/MacroInfo.cpp +++ b/clang/lib/Lex/MacroInfo.cpp @@ -257,7 +257,7 @@ LLVM_DUMP_METHOD void MacroDirective::dump() const { } ModuleMacro *ModuleMacro::create(Preprocessor &PP, Module *OwningModule, - IdentifierInfo *II, MacroInfo *Macro, + const IdentifierInfo *II, MacroInfo *Macro, ArrayRef Overrides) { void *Mem = PP.getPreprocessorAllocator().Allocate( sizeof(ModuleMacro) + sizeof(ModuleMacro *) * Overrides.size(), diff --git a/clang/lib/Lex/PPLexerChange.cpp b/clang/lib/Lex/PPLexerChange.cpp index 3b1b6df1dbae..2ca2122ac710 100644 --- a/clang/lib/Lex/PPLexerChange.cpp +++ b/clang/lib/Lex/PPLexerChange.cpp @@ -368,8 +368,7 @@ bool Preprocessor::HandleEndOfFile(Token &Result, bool isEndOfMacro) { // Okay, this has a controlling macro, remember in HeaderFileInfo. if (OptionalFileEntryRef FE = CurPPLexer->getFileEntry()) { HeaderInfo.SetFileControllingMacro(*FE, ControllingMacro); - if (MacroInfo *MI = - getMacroInfo(const_cast(ControllingMacro))) + if (MacroInfo *MI = getMacroInfo(ControllingMacro)) MI->setUsedForHeaderGuard(true); if (const IdentifierInfo *DefinedMacro = CurPPLexer->MIOpt.GetDefinedMacro()) { @@ -805,7 +804,7 @@ Module *Preprocessor::LeaveSubmodule(bool ForPragma) { llvm::SmallPtrSet VisitedMacros; for (unsigned I = Info.OuterPendingModuleMacroNames; I != PendingModuleMacroNames.size(); ++I) { - auto *II = const_cast(PendingModuleMacroNames[I]); + const auto *II = PendingModuleMacroNames[I]; if (!VisitedMacros.insert(II).second) continue; @@ -855,8 +854,8 @@ Module *Preprocessor::LeaveSubmodule(bool ForPragma) { // Don't bother creating a module macro if it would represent a #undef // that doesn't override anything. if (Def || !Macro.getOverriddenMacros().empty()) - addModuleMacro(LeavingMod, II, Def, - Macro.getOverriddenMacros(), IsNew); + addModuleMacro(LeavingMod, II, Def, Macro.getOverriddenMacros(), + IsNew); if (!getLangOpts().ModulesLocalVisibility) { // This macro is exposed to the rest of this compilation as a diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp index 516269c0c601..a5f22f01682d 100644 --- a/clang/lib/Lex/PPMacroExpansion.cpp +++ b/clang/lib/Lex/PPMacroExpansion.cpp @@ -129,7 +129,7 @@ void Preprocessor::setLoadedMacroDirective(IdentifierInfo *II, II->setHasMacroDefinition(false); } -ModuleMacro *Preprocessor::addModuleMacro(Module *Mod, IdentifierInfo *II, +ModuleMacro *Preprocessor::addModuleMacro(Module *Mod, const IdentifierInfo *II, MacroInfo *Macro, ArrayRef Overrides, bool &New) { @@ -162,7 +162,7 @@ ModuleMacro *Preprocessor::addModuleMacro(Module *Mod, IdentifierInfo *II, // The new macro is always a leaf macro. LeafMacros.push_back(MM); // The identifier now has defined macros (that may or may not be visible). - II->setHasMacroDefinition(true); + const_cast(II)->setHasMacroDefinition(true); New = true; return MM; diff --git a/clang/lib/Lex/Preprocessor.cpp b/clang/lib/Lex/Preprocessor.cpp index 031ed1e16bb8..0b70192743a3 100644 --- a/clang/lib/Lex/Preprocessor.cpp +++ b/clang/lib/Lex/Preprocessor.cpp @@ -759,7 +759,7 @@ void Preprocessor::HandlePoisonedIdentifier(Token & Identifier) { Diag(Identifier,it->second) << Identifier.getIdentifierInfo(); } -void Preprocessor::updateOutOfDateIdentifier(IdentifierInfo &II) const { +void Preprocessor::updateOutOfDateIdentifier(const IdentifierInfo &II) const { assert(II.isOutOfDate() && "not out of date"); getExternalSource()->updateOutOfDateIdentifier(II); } diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 0aa14b051074..583232f2d610 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -7700,7 +7700,7 @@ void Parser::ParseParameterDeclarationClause( } // Remember this parsed parameter in ParamInfo. - IdentifierInfo *ParmII = ParmDeclarator.getIdentifier(); + const IdentifierInfo *ParmII = ParmDeclarator.getIdentifier(); // DefArgToks is used when the parsing of default arguments needs // to be delayed. diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index 861a25dc5103..477d81cdc2c2 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -616,7 +616,7 @@ bool Parser::ParseUsingDeclarator(DeclaratorContext Context, } // Parse nested-name-specifier. - IdentifierInfo *LastII = nullptr; + const IdentifierInfo *LastII = nullptr; if (ParseOptionalCXXScopeSpecifier(D.SS, /*ObjectType=*/nullptr, /*ObjectHasErrors=*/false, /*EnteringContext=*/false, diff --git a/clang/lib/Parse/ParseExprCXX.cpp b/clang/lib/Parse/ParseExprCXX.cpp index 73c85c585baa..43d6105dcf31 100644 --- a/clang/lib/Parse/ParseExprCXX.cpp +++ b/clang/lib/Parse/ParseExprCXX.cpp @@ -157,7 +157,8 @@ void Parser::CheckForTemplateAndDigraph(Token &Next, ParsedType ObjectType, bool Parser::ParseOptionalCXXScopeSpecifier( CXXScopeSpec &SS, ParsedType ObjectType, bool ObjectHadErrors, bool EnteringContext, bool *MayBePseudoDestructor, bool IsTypename, - IdentifierInfo **LastII, bool OnlyNamespace, bool InUsingDeclaration) { + const IdentifierInfo **LastII, bool OnlyNamespace, + bool InUsingDeclaration) { assert(getLangOpts().CPlusPlus && "Call sites of this function should be guarded by checking for C++"); @@ -2626,7 +2627,7 @@ bool Parser::ParseUnqualifiedIdTemplateId( // UnqualifiedId. // FIXME: Store name for literal operator too. - IdentifierInfo *TemplateII = + const IdentifierInfo *TemplateII = Id.getKind() == UnqualifiedIdKind::IK_Identifier ? Id.Identifier : nullptr; OverloadedOperatorKind OpKind = diff --git a/clang/lib/Parse/ParseObjc.cpp b/clang/lib/Parse/ParseObjc.cpp index 88bab0eb27a3..887d7a36cee7 100644 --- a/clang/lib/Parse/ParseObjc.cpp +++ b/clang/lib/Parse/ParseObjc.cpp @@ -799,11 +799,11 @@ void Parser::ParseObjCInterfaceDeclList(tok::ObjCKeywordKind contextKey, addedToDeclSpec); // Install the property declarator into interfaceDecl. - IdentifierInfo *SelName = + const IdentifierInfo *SelName = OCDS.getGetterName() ? OCDS.getGetterName() : FD.D.getIdentifier(); Selector GetterSel = PP.getSelectorTable().getNullarySelector(SelName); - IdentifierInfo *SetterName = OCDS.getSetterName(); + const IdentifierInfo *SetterName = OCDS.getSetterName(); Selector SetterSel; if (SetterName) SetterSel = PP.getSelectorTable().getSelector(1, &SetterName); @@ -1445,7 +1445,7 @@ Decl *Parser::ParseObjCMethodDecl(SourceLocation mLoc, return Result; } - SmallVector KeyIdents; + SmallVector KeyIdents; SmallVector KeyLocs; SmallVector ArgInfos; ParseScope PrototypeScope(this, Scope::FunctionPrototypeScope | @@ -1541,7 +1541,7 @@ Decl *Parser::ParseObjCMethodDecl(SourceLocation mLoc, Declarator ParmDecl(DS, ParsedAttributesView::none(), DeclaratorContext::Prototype); ParseDeclarator(ParmDecl); - IdentifierInfo *ParmII = ParmDecl.getIdentifier(); + const IdentifierInfo *ParmII = ParmDecl.getIdentifier(); Decl *Param = Actions.ActOnParamDeclarator(getCurScope(), ParmDecl); CParamInfo.push_back(DeclaratorChunk::ParamInfo(ParmII, ParmDecl.getIdentifierLoc(), @@ -3242,7 +3242,7 @@ Parser::ParseObjCMessageExpressionBody(SourceLocation LBracLoc, SourceLocation Loc; IdentifierInfo *selIdent = ParseObjCSelectorPiece(Loc); - SmallVector KeyIdents; + SmallVector KeyIdents; SmallVector KeyLocs; ExprVector KeyExprs; @@ -3642,7 +3642,7 @@ ExprResult Parser::ParseObjCSelectorExpression(SourceLocation AtLoc) { if (Tok.isNot(tok::l_paren)) return ExprError(Diag(Tok, diag::err_expected_lparen_after) << "@selector"); - SmallVector KeyIdents; + SmallVector KeyIdents; SourceLocation sLoc; BalancedDelimiterTracker T(*this, tok::l_paren); diff --git a/clang/lib/Parse/ParseTemplate.cpp b/clang/lib/Parse/ParseTemplate.cpp index d4897f8f6607..03257500426e 100644 --- a/clang/lib/Parse/ParseTemplate.cpp +++ b/clang/lib/Parse/ParseTemplate.cpp @@ -313,7 +313,7 @@ Parser::ParseConceptDefinition(const ParsedTemplateInfo &TemplateInfo, return nullptr; } - IdentifierInfo *Id = Result.Identifier; + const IdentifierInfo *Id = Result.Identifier; SourceLocation IdLoc = Result.getBeginLoc(); DiagnoseAndSkipCXX11Attributes(); @@ -1289,7 +1289,7 @@ bool Parser::AnnotateTemplateIdToken(TemplateTy Template, TemplateNameKind TNK, // later. Tok.setKind(tok::annot_template_id); - IdentifierInfo *TemplateII = + const IdentifierInfo *TemplateII = TemplateName.getKind() == UnqualifiedIdKind::IK_Identifier ? TemplateName.Identifier : nullptr; diff --git a/clang/lib/Sema/CodeCompleteConsumer.cpp b/clang/lib/Sema/CodeCompleteConsumer.cpp index 350bd78b5710..91713d71786e 100644 --- a/clang/lib/Sema/CodeCompleteConsumer.cpp +++ b/clang/lib/Sema/CodeCompleteConsumer.cpp @@ -854,7 +854,8 @@ StringRef CodeCompletionResult::getOrderedName(std::string &Saved) const { if (IdentifierInfo *Id = Name.getAsIdentifierInfo()) return Id->getName(); if (Name.isObjCZeroArgSelector()) - if (IdentifierInfo *Id = Name.getObjCSelector().getIdentifierInfoForSlot(0)) + if (const IdentifierInfo *Id = + Name.getObjCSelector().getIdentifierInfoForSlot(0)) return Id->getName(); Saved = Name.getAsString(); diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 801b03a63dbc..a2ea66f339c8 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -92,9 +92,8 @@ DarwinSDKInfo *Sema::getDarwinSDKInfoForAvailabilityChecking() { return nullptr; } -IdentifierInfo * -Sema::InventAbbreviatedTemplateParameterTypeName(IdentifierInfo *ParamName, - unsigned int Index) { +IdentifierInfo *Sema::InventAbbreviatedTemplateParameterTypeName( + const IdentifierInfo *ParamName, unsigned int Index) { std::string InventedName; llvm::raw_string_ostream OS(InventedName); diff --git a/clang/lib/Sema/SemaCodeComplete.cpp b/clang/lib/Sema/SemaCodeComplete.cpp index 83ebcaf9e765..c335017f243e 100644 --- a/clang/lib/Sema/SemaCodeComplete.cpp +++ b/clang/lib/Sema/SemaCodeComplete.cpp @@ -3691,7 +3691,7 @@ CodeCompletionString *CodeCompletionResult::createCodeCompletionStringForDecl( std::string Keyword; if (Idx > StartParameter) Result.AddChunk(CodeCompletionString::CK_HorizontalSpace); - if (IdentifierInfo *II = Sel.getIdentifierInfoForSlot(Idx)) + if (const IdentifierInfo *II = Sel.getIdentifierInfoForSlot(Idx)) Keyword += II->getName(); Keyword += ":"; if (Idx < StartParameter || AllParametersAreInformative) @@ -3720,7 +3720,7 @@ CodeCompletionString *CodeCompletionResult::createCodeCompletionStringForDecl( Arg = "(" + formatObjCParamQualifiers((*P)->getObjCDeclQualifier(), ParamType); Arg += ParamType.getAsString(Policy) + ")"; - if (IdentifierInfo *II = (*P)->getIdentifier()) + if (const IdentifierInfo *II = (*P)->getIdentifier()) if (DeclaringEntity || AllParametersAreInformative) Arg += II->getName(); } @@ -4500,11 +4500,11 @@ void Sema::CodeCompleteOrdinaryName(Scope *S, Results.data(), Results.size()); } -static void AddClassMessageCompletions(Sema &SemaRef, Scope *S, - ParsedType Receiver, - ArrayRef SelIdents, - bool AtArgumentExpression, bool IsSuper, - ResultBuilder &Results); +static void +AddClassMessageCompletions(Sema &SemaRef, Scope *S, ParsedType Receiver, + ArrayRef SelIdents, + bool AtArgumentExpression, bool IsSuper, + ResultBuilder &Results); void Sema::CodeCompleteDeclSpec(Scope *S, DeclSpec &DS, bool AllowNonIdentifiers, @@ -4928,7 +4928,7 @@ void Sema::CodeCompletePostfixExpression(Scope *S, ExprResult E, /// The set of properties that have already been added, referenced by /// property name. -typedef llvm::SmallPtrSet AddedPropertiesSet; +typedef llvm::SmallPtrSet AddedPropertiesSet; /// Retrieve the container definition, if any? static ObjCContainerDecl *getContainerDef(ObjCContainerDecl *Container) { @@ -5090,7 +5090,7 @@ AddObjCProperties(const CodeCompletionContext &CCContext, PrintingPolicy Policy = getCompletionPrintingPolicy(Results.getSema()); // Adds a method result const auto AddMethod = [&](const ObjCMethodDecl *M) { - IdentifierInfo *Name = M->getSelector().getIdentifierInfoForSlot(0); + const IdentifierInfo *Name = M->getSelector().getIdentifierInfoForSlot(0); if (!Name) return; if (!AddedProperties.insert(Name).second) @@ -5859,10 +5859,10 @@ void Sema::CodeCompleteMemberReferenceExpr(Scope *S, Expr *Base, } void Sema::CodeCompleteObjCClassPropertyRefExpr(Scope *S, - IdentifierInfo &ClassName, + const IdentifierInfo &ClassName, SourceLocation ClassNameLoc, bool IsBaseExprStatement) { - IdentifierInfo *ClassNamePtr = &ClassName; + const IdentifierInfo *ClassNamePtr = &ClassName; ObjCInterfaceDecl *IFace = getObjCInterfaceDecl(ClassNamePtr, ClassNameLoc); if (!IFace) return; @@ -7527,7 +7527,7 @@ enum ObjCMethodKind { }; static bool isAcceptableObjCSelector(Selector Sel, ObjCMethodKind WantKind, - ArrayRef SelIdents, + ArrayRef SelIdents, bool AllowSameLength = true) { unsigned NumSelIdents = SelIdents.size(); if (NumSelIdents > Sel.getNumArgs()) @@ -7554,7 +7554,7 @@ static bool isAcceptableObjCSelector(Selector Sel, ObjCMethodKind WantKind, static bool isAcceptableObjCMethod(ObjCMethodDecl *Method, ObjCMethodKind WantKind, - ArrayRef SelIdents, + ArrayRef SelIdents, bool AllowSameLength = true) { return isAcceptableObjCSelector(Method->getSelector(), WantKind, SelIdents, AllowSameLength); @@ -7586,7 +7586,7 @@ typedef llvm::SmallPtrSet VisitedSelectorSet; /// \param Results the structure into which we'll add results. static void AddObjCMethods(ObjCContainerDecl *Container, bool WantInstanceMethods, ObjCMethodKind WantKind, - ArrayRef SelIdents, + ArrayRef SelIdents, DeclContext *CurContext, VisitedSelectorSet &Selectors, bool AllowSameLength, ResultBuilder &Results, bool InOriginalClass = true, @@ -7819,7 +7819,7 @@ static ObjCInterfaceDecl *GetAssumedMessageSendExprType(Expr *E) { if (Sel.isNull()) return nullptr; - IdentifierInfo *Id = Sel.getIdentifierInfoForSlot(0); + const IdentifierInfo *Id = Sel.getIdentifierInfoForSlot(0); if (!Id) return nullptr; @@ -7895,7 +7895,7 @@ static ObjCInterfaceDecl *GetAssumedMessageSendExprType(Expr *E) { /// this "super" completion. If NULL, no completion was added. static ObjCMethodDecl * AddSuperSendCompletion(Sema &S, bool NeedSuperKeyword, - ArrayRef SelIdents, + ArrayRef SelIdents, ResultBuilder &Results) { ObjCMethodDecl *CurMethod = S.getCurMethodDecl(); if (!CurMethod) @@ -8032,9 +8032,9 @@ void Sema::CodeCompleteObjCMessageReceiver(Scope *S) { Results.data(), Results.size()); } -void Sema::CodeCompleteObjCSuperMessage(Scope *S, SourceLocation SuperLoc, - ArrayRef SelIdents, - bool AtArgumentExpression) { +void Sema::CodeCompleteObjCSuperMessage( + Scope *S, SourceLocation SuperLoc, + ArrayRef SelIdents, bool AtArgumentExpression) { ObjCInterfaceDecl *CDecl = nullptr; if (ObjCMethodDecl *CurMethod = getCurMethodDecl()) { // Figure out which interface we're in. @@ -8059,7 +8059,7 @@ void Sema::CodeCompleteObjCSuperMessage(Scope *S, SourceLocation SuperLoc, } else { // "super" may be the name of a type or variable. Figure out which // it is. - IdentifierInfo *Super = getSuperIdentifier(); + const IdentifierInfo *Super = getSuperIdentifier(); NamedDecl *ND = LookupSingleName(S, Super, SuperLoc, LookupOrdinaryName); if ((CDecl = dyn_cast_or_null(ND))) { // "super" names an interface. Use it. @@ -8127,11 +8127,11 @@ static QualType getPreferredArgumentTypeForMessageSend(ResultBuilder &Results, return PreferredType; } -static void AddClassMessageCompletions(Sema &SemaRef, Scope *S, - ParsedType Receiver, - ArrayRef SelIdents, - bool AtArgumentExpression, bool IsSuper, - ResultBuilder &Results) { +static void +AddClassMessageCompletions(Sema &SemaRef, Scope *S, ParsedType Receiver, + ArrayRef SelIdents, + bool AtArgumentExpression, bool IsSuper, + ResultBuilder &Results) { typedef CodeCompletionResult Result; ObjCInterfaceDecl *CDecl = nullptr; @@ -8202,10 +8202,9 @@ static void AddClassMessageCompletions(Sema &SemaRef, Scope *S, Results.ExitScope(); } -void Sema::CodeCompleteObjCClassMessage(Scope *S, ParsedType Receiver, - ArrayRef SelIdents, - bool AtArgumentExpression, - bool IsSuper) { +void Sema::CodeCompleteObjCClassMessage( + Scope *S, ParsedType Receiver, ArrayRef SelIdents, + bool AtArgumentExpression, bool IsSuper) { QualType T = this->GetTypeFromParser(Receiver); @@ -8237,10 +8236,9 @@ void Sema::CodeCompleteObjCClassMessage(Scope *S, ParsedType Receiver, Results.data(), Results.size()); } -void Sema::CodeCompleteObjCInstanceMessage(Scope *S, Expr *Receiver, - ArrayRef SelIdents, - bool AtArgumentExpression, - ObjCInterfaceDecl *Super) { +void Sema::CodeCompleteObjCInstanceMessage( + Scope *S, Expr *Receiver, ArrayRef SelIdents, + bool AtArgumentExpression, ObjCInterfaceDecl *Super) { typedef CodeCompletionResult Result; Expr *RecExpr = static_cast(Receiver); @@ -8410,8 +8408,8 @@ void Sema::CodeCompleteObjCForCollection(Scope *S, CodeCompleteExpression(S, Data); } -void Sema::CodeCompleteObjCSelector(Scope *S, - ArrayRef SelIdents) { +void Sema::CodeCompleteObjCSelector( + Scope *S, ArrayRef SelIdents) { // If we have an external source, load the entire class method // pool from the AST file. if (ExternalSource) { @@ -9166,8 +9164,8 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // Add -(void)getKey:(type **)buffer range:(NSRange)inRange if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("get") + UpperKey).str(); - IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName), - &Context.Idents.get("range")}; + const IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName), + &Context.Idents.get("range")}; if (KnownSelectors.insert(Selectors.getSelector(2, SelectorIds)).second) { if (ReturnType.isNull()) { @@ -9198,8 +9196,8 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // - (void)insertObject:(type *)object inKeyAtIndex:(NSUInteger)index if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("in") + UpperKey + "AtIndex").str(); - IdentifierInfo *SelectorIds[2] = {&Context.Idents.get("insertObject"), - &Context.Idents.get(SelectorName)}; + const IdentifierInfo *SelectorIds[2] = {&Context.Idents.get("insertObject"), + &Context.Idents.get(SelectorName)}; if (KnownSelectors.insert(Selectors.getSelector(2, SelectorIds)).second) { if (ReturnType.isNull()) { @@ -9228,8 +9226,8 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // - (void)insertKey:(NSArray *)array atIndexes:(NSIndexSet *)indexes if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("insert") + UpperKey).str(); - IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName), - &Context.Idents.get("atIndexes")}; + const IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName), + &Context.Idents.get("atIndexes")}; if (KnownSelectors.insert(Selectors.getSelector(2, SelectorIds)).second) { if (ReturnType.isNull()) { @@ -9258,7 +9256,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("removeObjectFrom") + UpperKey + "AtIndex").str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9279,7 +9277,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // -(void)removeKeyAtIndexes:(NSIndexSet *)indexes if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("remove") + UpperKey + "AtIndexes").str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9301,8 +9299,8 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("replaceObjectIn") + UpperKey + "AtIndex").str(); - IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName), - &Context.Idents.get("withObject")}; + const IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName), + &Context.Idents.get("withObject")}; if (KnownSelectors.insert(Selectors.getSelector(2, SelectorIds)).second) { if (ReturnType.isNull()) { @@ -9332,8 +9330,8 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, std::string SelectorName1 = (Twine("replace") + UpperKey + "AtIndexes").str(); std::string SelectorName2 = (Twine("with") + UpperKey).str(); - IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName1), - &Context.Idents.get(SelectorName2)}; + const IdentifierInfo *SelectorIds[2] = {&Context.Idents.get(SelectorName1), + &Context.Idents.get(SelectorName2)}; if (KnownSelectors.insert(Selectors.getSelector(2, SelectorIds)).second) { if (ReturnType.isNull()) { @@ -9368,7 +9366,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, ->getInterfaceDecl() ->getName() == "NSEnumerator"))) { std::string SelectorName = (Twine("enumeratorOf") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getNullarySelector(SelectorId)) .second) { if (ReturnType.isNull()) { @@ -9387,7 +9385,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, if (IsInstanceMethod && (ReturnType.isNull() || ReturnType->isObjCObjectPointerType())) { std::string SelectorName = (Twine("memberOf") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9417,7 +9415,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("add") + UpperKey + Twine("Object")).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9439,7 +9437,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // - (void)addKey:(NSSet *)objects if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("add") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9461,7 +9459,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("remove") + UpperKey + Twine("Object")).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9483,7 +9481,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // - (void)removeKey:(NSSet *)objects if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("remove") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9504,7 +9502,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, // - (void)intersectKey:(NSSet *)objects if (IsInstanceMethod && ReturnTypeMatchesVoid) { std::string SelectorName = (Twine("intersect") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getUnarySelector(SelectorId)).second) { if (ReturnType.isNull()) { Builder.AddChunk(CodeCompletionString::CK_LeftParen); @@ -9533,7 +9531,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, ->getName() == "NSSet"))) { std::string SelectorName = (Twine("keyPathsForValuesAffecting") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getNullarySelector(SelectorId)) .second) { if (ReturnType.isNull()) { @@ -9554,7 +9552,7 @@ static void AddObjCKeyValueCompletions(ObjCPropertyDecl *Property, ReturnType->isBooleanType())) { std::string SelectorName = (Twine("automaticallyNotifiesObserversOf") + UpperKey).str(); - IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); + const IdentifierInfo *SelectorId = &Context.Idents.get(SelectorName); if (KnownSelectors.insert(Selectors.getNullarySelector(SelectorId)) .second) { if (ReturnType.isNull()) { @@ -9749,7 +9747,7 @@ void Sema::CodeCompleteObjCMethodDecl(Scope *S, void Sema::CodeCompleteObjCMethodDeclSelector( Scope *S, bool IsInstanceMethod, bool AtParameterName, ParsedType ReturnTy, - ArrayRef SelIdents) { + ArrayRef SelIdents) { // If we have an external source, load the entire class method // pool from the AST file. if (ExternalSource) { diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 8472aaeb6bad..5a23179dfbbf 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -2318,7 +2318,7 @@ void Sema::ActOnPopScope(SourceLocation Loc, Scope *S) { /// /// \returns The declaration of the named Objective-C class, or NULL if the /// class could not be found. -ObjCInterfaceDecl *Sema::getObjCInterfaceDecl(IdentifierInfo *&Id, +ObjCInterfaceDecl *Sema::getObjCInterfaceDecl(const IdentifierInfo *&Id, SourceLocation IdLoc, bool DoTypoCorrection) { // The third "scope" argument is 0 since we aren't enabling lazy built-in @@ -15307,7 +15307,7 @@ Decl *Sema::ActOnParamDeclarator(Scope *S, Declarator &D, QualType parmDeclType = TInfo->getType(); // Check for redeclaration of parameters, e.g. int foo(int x, int x); - IdentifierInfo *II = D.getIdentifier(); + const IdentifierInfo *II = D.getIdentifier(); if (II) { LookupResult R(*this, II, D.getIdentifierLoc(), LookupOrdinaryName, ForVisibleRedeclaration); @@ -15459,9 +15459,9 @@ QualType Sema::AdjustParameterTypeForObjCAutoRefCount(QualType T, } ParmVarDecl *Sema::CheckParameter(DeclContext *DC, SourceLocation StartLoc, - SourceLocation NameLoc, IdentifierInfo *Name, - QualType T, TypeSourceInfo *TSInfo, - StorageClass SC) { + SourceLocation NameLoc, + const IdentifierInfo *Name, QualType T, + TypeSourceInfo *TSInfo, StorageClass SC) { // In ARC, infer a lifetime qualifier for appropriate parameter types. if (getLangOpts().ObjCAutoRefCount && T.getObjCLifetime() == Qualifiers::OCL_None && @@ -18551,8 +18551,9 @@ void Sema::ActOnTagDefinitionError(Scope *S, Decl *TagD) { // Note that FieldName may be null for anonymous bitfields. ExprResult Sema::VerifyBitField(SourceLocation FieldLoc, - IdentifierInfo *FieldName, QualType FieldTy, - bool IsMsStruct, Expr *BitWidth) { + const IdentifierInfo *FieldName, + QualType FieldTy, bool IsMsStruct, + Expr *BitWidth) { assert(BitWidth); if (BitWidth->containsErrors()) return ExprError(); @@ -18661,7 +18662,7 @@ FieldDecl *Sema::HandleField(Scope *S, RecordDecl *Record, return nullptr; } - IdentifierInfo *II = D.getIdentifier(); + const IdentifierInfo *II = D.getIdentifier(); SourceLocation Loc = DeclStart; if (II) Loc = D.getIdentifierLoc(); @@ -18762,7 +18763,7 @@ FieldDecl *Sema::CheckFieldDecl(DeclarationName Name, QualType T, SourceLocation TSSL, AccessSpecifier AS, NamedDecl *PrevDecl, Declarator *D) { - IdentifierInfo *II = Name.getAsIdentifierInfo(); + const IdentifierInfo *II = Name.getAsIdentifierInfo(); bool InvalidDecl = false; if (D) InvalidDecl = D->isInvalidType(); @@ -19022,7 +19023,7 @@ TranslateIvarVisibility(tok::ObjCKeywordKind ivarVisibility) { Decl *Sema::ActOnIvar(Scope *S, SourceLocation DeclStart, Declarator &D, Expr *BitWidth, tok::ObjCKeywordKind Visibility) { - IdentifierInfo *II = D.getIdentifier(); + const IdentifierInfo *II = D.getIdentifier(); SourceLocation Loc = DeclStart; if (II) Loc = D.getIdentifierLoc(); diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 068a2e4f04fa..858951580ea4 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -16913,11 +16913,10 @@ Decl *Sema::ActOnEmptyDeclaration(Scope *S, /// Perform semantic analysis for the variable declaration that /// occurs within a C++ catch clause, returning the newly-created /// variable. -VarDecl *Sema::BuildExceptionDeclaration(Scope *S, - TypeSourceInfo *TInfo, +VarDecl *Sema::BuildExceptionDeclaration(Scope *S, TypeSourceInfo *TInfo, SourceLocation StartLoc, SourceLocation Loc, - IdentifierInfo *Name) { + const IdentifierInfo *Name) { bool Invalid = false; QualType ExDeclType = TInfo->getType(); @@ -17062,7 +17061,7 @@ Decl *Sema::ActOnExceptionDeclarator(Scope *S, Declarator &D) { Invalid = true; } - IdentifierInfo *II = D.getIdentifier(); + const IdentifierInfo *II = D.getIdentifier(); if (NamedDecl *PrevDecl = LookupSingleName(S, II, D.getIdentifierLoc(), LookupOrdinaryName, ForVisibleRedeclaration)) { @@ -19158,7 +19157,7 @@ MSPropertyDecl *Sema::HandleMSProperty(Scope *S, RecordDecl *Record, InClassInitStyle InitStyle, AccessSpecifier AS, const ParsedAttr &MSPropertyAttr) { - IdentifierInfo *II = D.getIdentifier(); + const IdentifierInfo *II = D.getIdentifier(); if (!II) { Diag(DeclStart, diag::err_anonymous_property); return nullptr; diff --git a/clang/lib/Sema/SemaDeclObjC.cpp b/clang/lib/Sema/SemaDeclObjC.cpp index 94a245f0f905..74d6f0700b0e 100644 --- a/clang/lib/Sema/SemaDeclObjC.cpp +++ b/clang/lib/Sema/SemaDeclObjC.cpp @@ -1818,9 +1818,9 @@ Sema::ActOnForwardProtocolDeclaration(SourceLocation AtProtocolLoc, } ObjCCategoryDecl *Sema::ActOnStartCategoryInterface( - SourceLocation AtInterfaceLoc, IdentifierInfo *ClassName, + SourceLocation AtInterfaceLoc, const IdentifierInfo *ClassName, SourceLocation ClassLoc, ObjCTypeParamList *typeParamList, - IdentifierInfo *CategoryName, SourceLocation CategoryLoc, + const IdentifierInfo *CategoryName, SourceLocation CategoryLoc, Decl *const *ProtoRefs, unsigned NumProtoRefs, const SourceLocation *ProtoLocs, SourceLocation EndProtoLoc, const ParsedAttributesView &AttrList) { @@ -1916,9 +1916,9 @@ ObjCCategoryDecl *Sema::ActOnStartCategoryInterface( /// category implementation declaration and build an ObjCCategoryImplDecl /// object. ObjCCategoryImplDecl *Sema::ActOnStartCategoryImplementation( - SourceLocation AtCatImplLoc, IdentifierInfo *ClassName, - SourceLocation ClassLoc, IdentifierInfo *CatName, SourceLocation CatLoc, - const ParsedAttributesView &Attrs) { + SourceLocation AtCatImplLoc, const IdentifierInfo *ClassName, + SourceLocation ClassLoc, const IdentifierInfo *CatName, + SourceLocation CatLoc, const ParsedAttributesView &Attrs) { ObjCInterfaceDecl *IDecl = getObjCInterfaceDecl(ClassName, ClassLoc, true); ObjCCategoryDecl *CatIDecl = nullptr; if (IDecl && IDecl->hasDefinition()) { @@ -1982,8 +1982,8 @@ ObjCCategoryImplDecl *Sema::ActOnStartCategoryImplementation( } ObjCImplementationDecl *Sema::ActOnStartClassImplementation( - SourceLocation AtClassImplLoc, IdentifierInfo *ClassName, - SourceLocation ClassLoc, IdentifierInfo *SuperClassname, + SourceLocation AtClassImplLoc, const IdentifierInfo *ClassName, + SourceLocation ClassLoc, const IdentifierInfo *SuperClassname, SourceLocation SuperClassLoc, const ParsedAttributesView &Attrs) { ObjCInterfaceDecl *IDecl = nullptr; // Check for another declaration kind with the same name. @@ -2751,7 +2751,7 @@ static void CheckProtocolMethodDefs( // implemented in the class, we should not issue "Method definition not // found" warnings. // FIXME: Use a general GetUnarySelector method for this. - IdentifierInfo* II = &S.Context.Idents.get("forwardInvocation"); + const IdentifierInfo *II = &S.Context.Idents.get("forwardInvocation"); Selector fISelector = S.Context.Selectors.getSelector(1, &II); if (InsMap.count(fISelector)) // Is IDecl derived from 'NSProxy'? If so, no instance methods @@ -5105,8 +5105,8 @@ bool Sema::CheckObjCDeclScope(Decl *D) { /// Called whenever \@defs(ClassName) is encountered in the source. Inserts the /// instance variables of ClassName into Decls. void Sema::ActOnDefs(Scope *S, Decl *TagD, SourceLocation DeclStart, - IdentifierInfo *ClassName, - SmallVectorImpl &Decls) { + const IdentifierInfo *ClassName, + SmallVectorImpl &Decls) { // Check that ClassName is a valid class ObjCInterfaceDecl *Class = getObjCInterfaceDecl(ClassName, DeclStart); if (!Class) { @@ -5148,8 +5148,7 @@ void Sema::ActOnDefs(Scope *S, Decl *TagD, SourceLocation DeclStart, VarDecl *Sema::BuildObjCExceptionDecl(TypeSourceInfo *TInfo, QualType T, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, - bool Invalid) { + const IdentifierInfo *Id, bool Invalid) { // ISO/IEC TR 18037 S6.7.3: "The type of an object with automatic storage // duration shall not be qualified by an address-space qualifier." // Since all parameters have automatic store duration, they can not have diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index 7b9b8f149d9e..12f42f66e5e2 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -57,7 +57,7 @@ using namespace sema; /// name of the corresponding type. ParsedType Sema::getInheritingConstructorName(CXXScopeSpec &SS, SourceLocation NameLoc, - IdentifierInfo &Name) { + const IdentifierInfo &Name) { NestedNameSpecifier *NNS = SS.getScopeRep(); // Convert the nested-name-specifier into a type. @@ -89,10 +89,9 @@ ParsedType Sema::getInheritingConstructorName(CXXScopeSpec &SS, Context.getTrivialTypeSourceInfo(Type, NameLoc)); } -ParsedType Sema::getConstructorName(IdentifierInfo &II, - SourceLocation NameLoc, - Scope *S, CXXScopeSpec &SS, - bool EnteringContext) { +ParsedType Sema::getConstructorName(const IdentifierInfo &II, + SourceLocation NameLoc, Scope *S, + CXXScopeSpec &SS, bool EnteringContext) { CXXRecordDecl *CurClass = getCurrentClass(S, &SS); assert(CurClass && &II == CurClass->getIdentifier() && "not a constructor name"); @@ -140,9 +139,9 @@ ParsedType Sema::getConstructorName(IdentifierInfo &II, return ParsedType::make(T); } -ParsedType Sema::getDestructorName(IdentifierInfo &II, SourceLocation NameLoc, - Scope *S, CXXScopeSpec &SS, - ParsedType ObjectTypePtr, +ParsedType Sema::getDestructorName(const IdentifierInfo &II, + SourceLocation NameLoc, Scope *S, + CXXScopeSpec &SS, ParsedType ObjectTypePtr, bool EnteringContext) { // Determine where to perform name lookup. @@ -500,7 +499,7 @@ bool Sema::checkLiteralOperatorId(const CXXScopeSpec &SS, // // double operator""_Bq(long double); // OK: not a reserved identifier // double operator"" _Bq(long double); // ill-formed, no diagnostic required - IdentifierInfo *II = Name.Identifier; + const IdentifierInfo *II = Name.Identifier; ReservedIdentifierStatus Status = II->isReserved(PP.getLangOpts()); SourceLocation Loc = Name.getEndLoc(); if (!PP.getSourceManager().isInSystemHeader(Loc)) { @@ -9178,10 +9177,9 @@ concepts::Requirement *Sema::ActOnSimpleRequirement(Expr *E) { /*ReturnTypeRequirement=*/{}); } -concepts::Requirement * -Sema::ActOnTypeRequirement(SourceLocation TypenameKWLoc, CXXScopeSpec &SS, - SourceLocation NameLoc, IdentifierInfo *TypeName, - TemplateIdAnnotation *TemplateId) { +concepts::Requirement *Sema::ActOnTypeRequirement( + SourceLocation TypenameKWLoc, CXXScopeSpec &SS, SourceLocation NameLoc, + const IdentifierInfo *TypeName, TemplateIdAnnotation *TemplateId) { assert(((!TypeName && TemplateId) || (TypeName && !TemplateId)) && "Exactly one of TypeName and TemplateId must be specified."); TypeSourceInfo *TSI = nullptr; diff --git a/clang/lib/Sema/SemaExprObjC.cpp b/clang/lib/Sema/SemaExprObjC.cpp index a8853f634c9c..3148f0db6e20 100644 --- a/clang/lib/Sema/SemaExprObjC.cpp +++ b/clang/lib/Sema/SemaExprObjC.cpp @@ -663,10 +663,8 @@ ExprResult Sema::BuildObjCBoxedExpr(SourceRange SR, Expr *ValueExpr) { } if (!ValueWithBytesObjCTypeMethod) { - IdentifierInfo *II[] = { - &Context.Idents.get("valueWithBytes"), - &Context.Idents.get("objCType") - }; + const IdentifierInfo *II[] = {&Context.Idents.get("valueWithBytes"), + &Context.Idents.get("objCType")}; Selector ValueWithBytesObjCType = Context.Selectors.getSelector(2, II); // Look for the appropriate method within NSValue. @@ -2155,13 +2153,12 @@ HandleExprPropertyRefExpr(const ObjCObjectPointerType *OPT, return ExprError(); } -ExprResult Sema:: -ActOnClassPropertyRefExpr(IdentifierInfo &receiverName, - IdentifierInfo &propertyName, - SourceLocation receiverNameLoc, - SourceLocation propertyNameLoc) { +ExprResult Sema::ActOnClassPropertyRefExpr(const IdentifierInfo &receiverName, + const IdentifierInfo &propertyName, + SourceLocation receiverNameLoc, + SourceLocation propertyNameLoc) { - IdentifierInfo *receiverNamePtr = &receiverName; + const IdentifierInfo *receiverNamePtr = &receiverName; ObjCInterfaceDecl *IFace = getObjCInterfaceDecl(receiverNamePtr, receiverNameLoc); diff --git a/clang/lib/Sema/SemaObjCProperty.cpp b/clang/lib/Sema/SemaObjCProperty.cpp index f9e1ad0121e2..222a65a13dd0 100644 --- a/clang/lib/Sema/SemaObjCProperty.cpp +++ b/clang/lib/Sema/SemaObjCProperty.cpp @@ -419,7 +419,7 @@ Sema::HandlePropertyInClassExtension(Scope *S, ObjCCategoryDecl *CDecl = cast(CurContext); // Diagnose if this property is already in continuation class. DeclContext *DC = CurContext; - IdentifierInfo *PropertyId = FD.D.getIdentifier(); + const IdentifierInfo *PropertyId = FD.D.getIdentifier(); ObjCInterfaceDecl *CCPrimary = CDecl->getClassInterface(); // We need to look in the @interface to see if the @property was @@ -571,7 +571,7 @@ ObjCPropertyDecl *Sema::CreatePropertyDecl(Scope *S, TypeSourceInfo *TInfo, tok::ObjCKeywordKind MethodImplKind, DeclContext *lexicalDC){ - IdentifierInfo *PropertyId = FD.D.getIdentifier(); + const IdentifierInfo *PropertyId = FD.D.getIdentifier(); // Property defaults to 'assign' if it is readwrite, unless this is ARC // and the type is retainable. diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index c814535ad6bd..e9efb4721133 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -7375,7 +7375,7 @@ void Sema::ActOnStartOfFunctionDefinitionInOpenMPDeclareVariantScope( llvm::omp::TraitProperty::implementation_extension_allow_templates)) return; - IdentifierInfo *BaseII = D.getIdentifier(); + const IdentifierInfo *BaseII = D.getIdentifier(); LookupResult Lookup(*this, DeclarationName(BaseII), D.getIdentifierLoc(), LookupOrdinaryName); LookupParsedName(Lookup, S, &D.getCXXScopeSpec()); diff --git a/clang/lib/Sema/SemaPseudoObject.cpp b/clang/lib/Sema/SemaPseudoObject.cpp index 528c261c4a29..82774760b34d 100644 --- a/clang/lib/Sema/SemaPseudoObject.cpp +++ b/clang/lib/Sema/SemaPseudoObject.cpp @@ -613,9 +613,9 @@ bool ObjCPropertyOpBuilder::findGetter() { // Must build the getter selector the hard way. ObjCMethodDecl *setter = RefExpr->getImplicitPropertySetter(); assert(setter && "both setter and getter are null - cannot happen"); - IdentifierInfo *setterName = - setter->getSelector().getIdentifierInfoForSlot(0); - IdentifierInfo *getterName = + const IdentifierInfo *setterName = + setter->getSelector().getIdentifierInfoForSlot(0); + const IdentifierInfo *getterName = &S.Context.Idents.get(setterName->getName().substr(3)); GetterSelector = S.PP.getSelectorTable().getNullarySelector(getterName); @@ -640,9 +640,9 @@ bool ObjCPropertyOpBuilder::findSetter(bool warn) { SetterSelector = setter->getSelector(); return true; } else { - IdentifierInfo *getterName = - RefExpr->getImplicitPropertyGetter()->getSelector() - .getIdentifierInfoForSlot(0); + const IdentifierInfo *getterName = RefExpr->getImplicitPropertyGetter() + ->getSelector() + .getIdentifierInfoForSlot(0); SetterSelector = SelectorTable::constructSetterSelector(S.PP.getIdentifierTable(), S.PP.getSelectorTable(), @@ -667,7 +667,8 @@ bool ObjCPropertyOpBuilder::findSetter(bool warn) { front = isLowercase(front) ? toUppercase(front) : toLowercase(front); SmallString<100> PropertyName = thisPropertyName; PropertyName[0] = front; - IdentifierInfo *AltMember = &S.PP.getIdentifierTable().get(PropertyName); + const IdentifierInfo *AltMember = + &S.PP.getIdentifierTable().get(PropertyName); if (ObjCPropertyDecl *prop1 = IFace->FindPropertyDeclaration( AltMember, prop->getQueryKind())) if (prop != prop1 && (prop1->getSetterMethodDecl() == setter)) { @@ -1126,9 +1127,8 @@ static void CheckKeyForObjCARCConversion(Sema &S, QualType ContainerT, return; // dictionary subscripting. // - (id)objectForKeyedSubscript:(id)key; - IdentifierInfo *KeyIdents[] = { - &S.Context.Idents.get("objectForKeyedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &S.Context.Idents.get("objectForKeyedSubscript")}; Selector GetterSelector = S.Context.Selectors.getSelector(1, KeyIdents); ObjCMethodDecl *Getter = S.LookupMethodInObjectType(GetterSelector, ContainerT, true /*instance*/); @@ -1169,16 +1169,14 @@ bool ObjCSubscriptOpBuilder::findAtIndexGetter() { if (!arrayRef) { // dictionary subscripting. // - (id)objectForKeyedSubscript:(id)key; - IdentifierInfo *KeyIdents[] = { - &S.Context.Idents.get("objectForKeyedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &S.Context.Idents.get("objectForKeyedSubscript")}; AtIndexGetterSelector = S.Context.Selectors.getSelector(1, KeyIdents); } else { // - (id)objectAtIndexedSubscript:(size_t)index; - IdentifierInfo *KeyIdents[] = { - &S.Context.Idents.get("objectAtIndexedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &S.Context.Idents.get("objectAtIndexedSubscript")}; AtIndexGetterSelector = S.Context.Selectors.getSelector(1, KeyIdents); } @@ -1274,18 +1272,16 @@ bool ObjCSubscriptOpBuilder::findAtIndexSetter() { if (!arrayRef) { // dictionary subscripting. // - (void)setObject:(id)object forKeyedSubscript:(id)key; - IdentifierInfo *KeyIdents[] = { - &S.Context.Idents.get("setObject"), - &S.Context.Idents.get("forKeyedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &S.Context.Idents.get("setObject"), + &S.Context.Idents.get("forKeyedSubscript")}; AtIndexSetterSelector = S.Context.Selectors.getSelector(2, KeyIdents); } else { // - (void)setObject:(id)object atIndexedSubscript:(NSInteger)index; - IdentifierInfo *KeyIdents[] = { - &S.Context.Idents.get("setObject"), - &S.Context.Idents.get("atIndexedSubscript") - }; + const IdentifierInfo *KeyIdents[] = { + &S.Context.Idents.get("setObject"), + &S.Context.Idents.get("atIndexedSubscript")}; AtIndexSetterSelector = S.Context.Selectors.getSelector(2, KeyIdents); } AtIndexSetter = S.LookupMethodInObjectType(AtIndexSetterSelector, ResultType, @@ -1474,7 +1470,7 @@ ExprResult MSPropertyOpBuilder::buildGet() { } UnqualifiedId GetterName; - IdentifierInfo *II = RefExpr->getPropertyDecl()->getGetterId(); + const IdentifierInfo *II = RefExpr->getPropertyDecl()->getGetterId(); GetterName.setIdentifier(II, RefExpr->getMemberLoc()); CXXScopeSpec SS; SS.Adopt(RefExpr->getQualifierLoc()); @@ -1503,7 +1499,7 @@ ExprResult MSPropertyOpBuilder::buildSet(Expr *op, SourceLocation sl, } UnqualifiedId SetterName; - IdentifierInfo *II = RefExpr->getPropertyDecl()->getSetterId(); + const IdentifierInfo *II = RefExpr->getPropertyDecl()->getSetterId(); SetterName.setIdentifier(II, RefExpr->getMemberLoc()); CXXScopeSpec SS; SS.Adopt(RefExpr->getQualifierLoc()); diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp index e72397adec24..e53c76e65b03 100644 --- a/clang/lib/Sema/SemaStmt.cpp +++ b/clang/lib/Sema/SemaStmt.cpp @@ -2275,11 +2275,9 @@ Sema::CheckObjCForCollectionOperand(SourceLocation forLoc, Expr *collection) { // Otherwise, if we have any useful type information, check that // the type declares the appropriate method. } else if (iface || !objectType->qual_empty()) { - IdentifierInfo *selectorIdents[] = { - &Context.Idents.get("countByEnumeratingWithState"), - &Context.Idents.get("objects"), - &Context.Idents.get("count") - }; + const IdentifierInfo *selectorIdents[] = { + &Context.Idents.get("countByEnumeratingWithState"), + &Context.Idents.get("objects"), &Context.Idents.get("count")}; Selector selector = Context.Selectors.getSelector(3, &selectorIdents[0]); ObjCMethodDecl *method = nullptr; diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 2013799b5eb8..951e5a31cab3 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -970,7 +970,7 @@ void Sema::translateTemplateArguments(const ASTTemplateArgsPtr &TemplateArgsIn, static void maybeDiagnoseTemplateParameterShadow(Sema &SemaRef, Scope *S, SourceLocation Loc, - IdentifierInfo *Name) { + const IdentifierInfo *Name) { NamedDecl *PrevDecl = SemaRef.LookupSingleName( S, Name, Loc, Sema::LookupOrdinaryName, Sema::ForVisibleRedeclaration); if (PrevDecl && PrevDecl->isTemplateParameter()) @@ -1578,7 +1578,7 @@ NamedDecl *Sema::ActOnNonTypeTemplateParameter(Scope *S, Declarator &D, CheckFunctionOrTemplateParamDeclarator(S, D); - IdentifierInfo *ParamName = D.getIdentifier(); + const IdentifierInfo *ParamName = D.getIdentifier(); bool IsParameterPack = D.hasEllipsis(); NonTypeTemplateParmDecl *Param = NonTypeTemplateParmDecl::Create( Context, Context.getTranslationUnitDecl(), D.getBeginLoc(), @@ -4702,7 +4702,7 @@ bool Sema::resolveAssumedTemplateNameAsType(Scope *S, TemplateName &Name, TypeResult Sema::ActOnTemplateIdType( Scope *S, CXXScopeSpec &SS, SourceLocation TemplateKWLoc, - TemplateTy TemplateD, IdentifierInfo *TemplateII, + TemplateTy TemplateD, const IdentifierInfo *TemplateII, SourceLocation TemplateIILoc, SourceLocation LAngleLoc, ASTTemplateArgsPtr TemplateArgsIn, SourceLocation RAngleLoc, bool IsCtorOrDtorName, bool IsClassName, @@ -9684,10 +9684,9 @@ Decl *Sema::ActOnTemplateDeclarator(Scope *S, return NewDecl; } -Decl *Sema::ActOnConceptDefinition(Scope *S, - MultiTemplateParamsArg TemplateParameterLists, - IdentifierInfo *Name, SourceLocation NameLoc, - Expr *ConstraintExpr) { +Decl *Sema::ActOnConceptDefinition( + Scope *S, MultiTemplateParamsArg TemplateParameterLists, + const IdentifierInfo *Name, SourceLocation NameLoc, Expr *ConstraintExpr) { DeclContext *DC = CurContext; if (!DC->getRedeclContext()->isFileContext()) { @@ -11511,10 +11510,11 @@ DeclResult Sema::ActOnExplicitInstantiation(Scope *S, return (Decl*) nullptr; } -TypeResult -Sema::ActOnDependentTag(Scope *S, unsigned TagSpec, TagUseKind TUK, - const CXXScopeSpec &SS, IdentifierInfo *Name, - SourceLocation TagLoc, SourceLocation NameLoc) { +TypeResult Sema::ActOnDependentTag(Scope *S, unsigned TagSpec, TagUseKind TUK, + const CXXScopeSpec &SS, + const IdentifierInfo *Name, + SourceLocation TagLoc, + SourceLocation NameLoc) { // This has to hold, because SS is expected to be defined. assert(Name && "Expected a name in a dependent tag"); @@ -11574,14 +11574,10 @@ TypeResult Sema::ActOnTypenameType(Scope *S, SourceLocation TypenameLoc, } TypeResult -Sema::ActOnTypenameType(Scope *S, - SourceLocation TypenameLoc, - const CXXScopeSpec &SS, - SourceLocation TemplateKWLoc, - TemplateTy TemplateIn, - IdentifierInfo *TemplateII, - SourceLocation TemplateIILoc, - SourceLocation LAngleLoc, +Sema::ActOnTypenameType(Scope *S, SourceLocation TypenameLoc, + const CXXScopeSpec &SS, SourceLocation TemplateKWLoc, + TemplateTy TemplateIn, const IdentifierInfo *TemplateII, + SourceLocation TemplateIILoc, SourceLocation LAngleLoc, ASTTemplateArgsPtr TemplateArgsIn, SourceLocation RAngleLoc) { if (TypenameLoc.isValid() && S && !S->getTemplateParamParent()) @@ -11657,7 +11653,6 @@ Sema::ActOnTypenameType(Scope *S, return CreateParsedType(T, TSI); } - /// Determine whether this failed name lookup should be treated as being /// disabled by a usage of std::enable_if. static bool isEnableIf(NestedNameSpecifierLoc NNS, const IdentifierInfo &II, diff --git a/clang/lib/Serialization/ASTCommon.cpp b/clang/lib/Serialization/ASTCommon.cpp index 6110e287b7fb..f8d54c0c3989 100644 --- a/clang/lib/Serialization/ASTCommon.cpp +++ b/clang/lib/Serialization/ASTCommon.cpp @@ -284,7 +284,7 @@ unsigned serialization::ComputeHash(Selector Sel) { ++N; unsigned R = 5381; for (unsigned I = 0; I != N; ++I) - if (IdentifierInfo *II = Sel.getIdentifierInfoForSlot(I)) + if (const IdentifierInfo *II = Sel.getIdentifierInfoForSlot(I)) R = llvm::djbHash(II->getName(), R); return R; } diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index 0ca7f6600eee..4f6987f92fc8 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -916,14 +916,14 @@ ASTSelectorLookupTrait::ReadKey(const unsigned char* d, unsigned) { SelectorTable &SelTable = Reader.getContext().Selectors; unsigned N = endian::readNext(d); - IdentifierInfo *FirstII = Reader.getLocalIdentifier( + const IdentifierInfo *FirstII = Reader.getLocalIdentifier( F, endian::readNext(d)); if (N == 0) return SelTable.getNullarySelector(FirstII); else if (N == 1) return SelTable.getUnarySelector(FirstII); - SmallVector Args; + SmallVector Args; Args.push_back(FirstII); for (unsigned I = 1; I != N; ++I) Args.push_back(Reader.getLocalIdentifier( @@ -987,7 +987,7 @@ ASTIdentifierLookupTraitBase::ReadKey(const unsigned char* d, unsigned n) { } /// Whether the given identifier is "interesting". -static bool isInterestingIdentifier(ASTReader &Reader, IdentifierInfo &II, +static bool isInterestingIdentifier(ASTReader &Reader, const IdentifierInfo &II, bool IsModule) { bool IsInteresting = II.getNotableIdentifierID() != tok::NotableIdentifierKind::not_notable || @@ -2229,7 +2229,7 @@ namespace { } // namespace -void ASTReader::updateOutOfDateIdentifier(IdentifierInfo &II) { +void ASTReader::updateOutOfDateIdentifier(const IdentifierInfo &II) { // Note that we are loading an identifier. Deserializing AnIdentifier(this); @@ -2254,11 +2254,11 @@ void ASTReader::updateOutOfDateIdentifier(IdentifierInfo &II) { markIdentifierUpToDate(&II); } -void ASTReader::markIdentifierUpToDate(IdentifierInfo *II) { +void ASTReader::markIdentifierUpToDate(const IdentifierInfo *II) { if (!II) return; - II->setOutOfDate(false); + const_cast(II)->setOutOfDate(false); // Update the generation for this identifier. if (getContext().getLangOpts().Modules) @@ -10168,7 +10168,7 @@ void ASTReader::FinishedDeserializing() { } void ASTReader::pushExternalDeclIntoScope(NamedDecl *D, DeclarationName Name) { - if (IdentifierInfo *II = Name.getAsIdentifierInfo()) { + if (const IdentifierInfo *II = Name.getAsIdentifierInfo()) { // Remove any fake results before adding any real ones. auto It = PendingFakeLookupResults.find(II); if (It != PendingFakeLookupResults.end()) { diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index d2afe378bb0c..ffc53292e391 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -3629,7 +3629,7 @@ class ASTIdentifierTableTrait { } public: - using key_type = IdentifierInfo *; + using key_type = const IdentifierInfo *; using key_type_ref = key_type; using data_type = IdentID; @@ -3661,7 +3661,7 @@ public: } std::pair - EmitKeyDataLength(raw_ostream& Out, IdentifierInfo* II, IdentID ID) { + EmitKeyDataLength(raw_ostream &Out, const IdentifierInfo *II, IdentID ID) { // Record the location of the identifier data. This is used when generating // the mapping from persistent IDs to strings. Writer.SetIdentifierOffset(II, Out.tell()); @@ -3688,13 +3688,12 @@ public: return emitULEBKeyDataLength(KeyLen, DataLen, Out); } - void EmitKey(raw_ostream& Out, const IdentifierInfo* II, - unsigned KeyLen) { + void EmitKey(raw_ostream &Out, const IdentifierInfo *II, unsigned KeyLen) { Out.write(II->getNameStart(), KeyLen); } - void EmitData(raw_ostream& Out, IdentifierInfo* II, - IdentID ID, unsigned) { + void EmitData(raw_ostream &Out, const IdentifierInfo *II, IdentID ID, + unsigned) { using namespace llvm::support; endian::Writer LE(Out, llvm::endianness::little); @@ -3776,13 +3775,14 @@ void ASTWriter::WriteIdentifierTable(Preprocessor &PP, // for identifiers that appear here for the first time. IdentifierOffsets.resize(NextIdentID - FirstIdentID); for (auto IdentIDPair : IdentifierIDs) { - auto *II = const_cast(IdentIDPair.first); + const IdentifierInfo *II = IdentIDPair.first; IdentID ID = IdentIDPair.second; assert(II && "NULL identifier in identifier table"); + // Write out identifiers if either the ID is local or the identifier has // changed since it was loaded. - if (ID >= FirstIdentID || !Chain || !II->isFromAST() - || II->hasChangedSinceDeserialization() || + if (ID >= FirstIdentID || !Chain || !II->isFromAST() || + II->hasChangedSinceDeserialization() || (Trait.needDecls() && II->hasFETokenInfoChangedSinceDeserialization())) Generator.insert(II, ID, Trait); diff --git a/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp b/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp index 978bc0bb082f..b4390f0b85bb 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CheckObjCDealloc.cpp @@ -768,8 +768,8 @@ void ObjCDeallocChecker::initIdentifierInfoAndSelectors( Block_releaseII = &Ctx.Idents.get("_Block_release"); CIFilterII = &Ctx.Idents.get("CIFilter"); - IdentifierInfo *DeallocII = &Ctx.Idents.get("dealloc"); - IdentifierInfo *ReleaseII = &Ctx.Idents.get("release"); + const IdentifierInfo *DeallocII = &Ctx.Idents.get("dealloc"); + const IdentifierInfo *ReleaseII = &Ctx.Idents.get("release"); DeallocSel = Ctx.Selectors.getSelector(0, &DeallocII); ReleaseSel = Ctx.Selectors.getSelector(0, &ReleaseII); } diff --git a/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp index 812d787e2e37..882eb0236a18 100644 --- a/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/LocalizationChecker.cpp @@ -154,11 +154,11 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UISearchDisplayController, setSearchResultsTitle, 0) NEW_RECEIVER(UITabBarItem) - IdentifierInfo *initWithTitleUITabBarItemTag[] = { + const IdentifierInfo *initWithTitleUITabBarItemTag[] = { &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("image"), &Ctx.Idents.get("tag")}; ADD_METHOD(UITabBarItem, initWithTitleUITabBarItemTag, 3, 0) - IdentifierInfo *initWithTitleUITabBarItemImage[] = { + const IdentifierInfo *initWithTitleUITabBarItemImage[] = { &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("image"), &Ctx.Idents.get("selectedImage")}; ADD_METHOD(UITabBarItem, initWithTitleUITabBarItemImage, 3, 0) @@ -171,7 +171,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSStatusItem, setToolTip, 0) NEW_RECEIVER(UITableViewRowAction) - IdentifierInfo *rowActionWithStyleUITableViewRowAction[] = { + const IdentifierInfo *rowActionWithStyleUITableViewRowAction[] = { &Ctx.Idents.get("rowActionWithStyle"), &Ctx.Idents.get("title"), &Ctx.Idents.get("handler")}; ADD_METHOD(UITableViewRowAction, rowActionWithStyleUITableViewRowAction, 3, 1) @@ -183,19 +183,19 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { NEW_RECEIVER(NSButton) ADD_UNARY_METHOD(NSButton, setTitle, 0) ADD_UNARY_METHOD(NSButton, setAlternateTitle, 0) - IdentifierInfo *radioButtonWithTitleNSButton[] = { + const IdentifierInfo *radioButtonWithTitleNSButton[] = { &Ctx.Idents.get("radioButtonWithTitle"), &Ctx.Idents.get("target"), &Ctx.Idents.get("action")}; ADD_METHOD(NSButton, radioButtonWithTitleNSButton, 3, 0) - IdentifierInfo *buttonWithTitleNSButtonImage[] = { + const IdentifierInfo *buttonWithTitleNSButtonImage[] = { &Ctx.Idents.get("buttonWithTitle"), &Ctx.Idents.get("image"), &Ctx.Idents.get("target"), &Ctx.Idents.get("action")}; ADD_METHOD(NSButton, buttonWithTitleNSButtonImage, 4, 0) - IdentifierInfo *checkboxWithTitleNSButton[] = { + const IdentifierInfo *checkboxWithTitleNSButton[] = { &Ctx.Idents.get("checkboxWithTitle"), &Ctx.Idents.get("target"), &Ctx.Idents.get("action")}; ADD_METHOD(NSButton, checkboxWithTitleNSButton, 3, 0) - IdentifierInfo *buttonWithTitleNSButtonTarget[] = { + const IdentifierInfo *buttonWithTitleNSButtonTarget[] = { &Ctx.Idents.get("buttonWithTitle"), &Ctx.Idents.get("target"), &Ctx.Idents.get("action")}; ADD_METHOD(NSButton, buttonWithTitleNSButtonTarget, 3, 0) @@ -215,8 +215,8 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSTabViewItem, setToolTip, 0) NEW_RECEIVER(NSBrowser) - IdentifierInfo *setTitleNSBrowser[] = {&Ctx.Idents.get("setTitle"), - &Ctx.Idents.get("ofColumn")}; + const IdentifierInfo *setTitleNSBrowser[] = {&Ctx.Idents.get("setTitle"), + &Ctx.Idents.get("ofColumn")}; ADD_METHOD(NSBrowser, setTitleNSBrowser, 2, 0) NEW_RECEIVER(UIAccessibilityElement) @@ -225,14 +225,14 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UIAccessibilityElement, setAccessibilityValue, 0) NEW_RECEIVER(UIAlertAction) - IdentifierInfo *actionWithTitleUIAlertAction[] = { + const IdentifierInfo *actionWithTitleUIAlertAction[] = { &Ctx.Idents.get("actionWithTitle"), &Ctx.Idents.get("style"), &Ctx.Idents.get("handler")}; ADD_METHOD(UIAlertAction, actionWithTitleUIAlertAction, 3, 0) NEW_RECEIVER(NSPopUpButton) ADD_UNARY_METHOD(NSPopUpButton, addItemWithTitle, 0) - IdentifierInfo *insertItemWithTitleNSPopUpButton[] = { + const IdentifierInfo *insertItemWithTitleNSPopUpButton[] = { &Ctx.Idents.get("insertItemWithTitle"), &Ctx.Idents.get("atIndex")}; ADD_METHOD(NSPopUpButton, insertItemWithTitleNSPopUpButton, 2, 0) ADD_UNARY_METHOD(NSPopUpButton, removeItemWithTitle, 0) @@ -240,7 +240,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSPopUpButton, setTitle, 0) NEW_RECEIVER(NSTableViewRowAction) - IdentifierInfo *rowActionWithStyleNSTableViewRowAction[] = { + const IdentifierInfo *rowActionWithStyleNSTableViewRowAction[] = { &Ctx.Idents.get("rowActionWithStyle"), &Ctx.Idents.get("title"), &Ctx.Idents.get("handler")}; ADD_METHOD(NSTableViewRowAction, rowActionWithStyleNSTableViewRowAction, 3, 1) @@ -273,10 +273,10 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSTableColumn, setHeaderToolTip, 0) NEW_RECEIVER(NSSegmentedControl) - IdentifierInfo *setLabelNSSegmentedControl[] = { + const IdentifierInfo *setLabelNSSegmentedControl[] = { &Ctx.Idents.get("setLabel"), &Ctx.Idents.get("forSegment")}; ADD_METHOD(NSSegmentedControl, setLabelNSSegmentedControl, 2, 0) - IdentifierInfo *setToolTipNSSegmentedControl[] = { + const IdentifierInfo *setToolTipNSSegmentedControl[] = { &Ctx.Idents.get("setToolTip"), &Ctx.Idents.get("forSegment")}; ADD_METHOD(NSSegmentedControl, setToolTipNSSegmentedControl, 2, 0) @@ -301,8 +301,8 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSAccessibility, setAccessibilityHelp, 0) NEW_RECEIVER(NSMatrix) - IdentifierInfo *setToolTipNSMatrix[] = {&Ctx.Idents.get("setToolTip"), - &Ctx.Idents.get("forCell")}; + const IdentifierInfo *setToolTipNSMatrix[] = {&Ctx.Idents.get("setToolTip"), + &Ctx.Idents.get("forCell")}; ADD_METHOD(NSMatrix, setToolTipNSMatrix, 2, 0) NEW_RECEIVER(NSPrintPanel) @@ -317,13 +317,13 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSSlider, setTitle, 0) NEW_RECEIVER(UIMenuItem) - IdentifierInfo *initWithTitleUIMenuItem[] = {&Ctx.Idents.get("initWithTitle"), - &Ctx.Idents.get("action")}; + const IdentifierInfo *initWithTitleUIMenuItem[] = { + &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("action")}; ADD_METHOD(UIMenuItem, initWithTitleUIMenuItem, 2, 0) ADD_UNARY_METHOD(UIMenuItem, setTitle, 0) NEW_RECEIVER(UIAlertController) - IdentifierInfo *alertControllerWithTitleUIAlertController[] = { + const IdentifierInfo *alertControllerWithTitleUIAlertController[] = { &Ctx.Idents.get("alertControllerWithTitle"), &Ctx.Idents.get("message"), &Ctx.Idents.get("preferredStyle")}; ADD_METHOD(UIAlertController, alertControllerWithTitleUIAlertController, 3, 1) @@ -331,19 +331,19 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UIAlertController, setMessage, 0) NEW_RECEIVER(UIApplicationShortcutItem) - IdentifierInfo *initWithTypeUIApplicationShortcutItemIcon[] = { + const IdentifierInfo *initWithTypeUIApplicationShortcutItemIcon[] = { &Ctx.Idents.get("initWithType"), &Ctx.Idents.get("localizedTitle"), &Ctx.Idents.get("localizedSubtitle"), &Ctx.Idents.get("icon"), &Ctx.Idents.get("userInfo")}; ADD_METHOD(UIApplicationShortcutItem, initWithTypeUIApplicationShortcutItemIcon, 5, 1) - IdentifierInfo *initWithTypeUIApplicationShortcutItem[] = { + const IdentifierInfo *initWithTypeUIApplicationShortcutItem[] = { &Ctx.Idents.get("initWithType"), &Ctx.Idents.get("localizedTitle")}; ADD_METHOD(UIApplicationShortcutItem, initWithTypeUIApplicationShortcutItem, 2, 1) NEW_RECEIVER(UIActionSheet) - IdentifierInfo *initWithTitleUIActionSheet[] = { + const IdentifierInfo *initWithTitleUIActionSheet[] = { &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("delegate"), &Ctx.Idents.get("cancelButtonTitle"), &Ctx.Idents.get("destructiveButtonTitle"), @@ -353,7 +353,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UIActionSheet, setTitle, 0) NEW_RECEIVER(UIAccessibilityCustomAction) - IdentifierInfo *initWithNameUIAccessibilityCustomAction[] = { + const IdentifierInfo *initWithNameUIAccessibilityCustomAction[] = { &Ctx.Idents.get("initWithName"), &Ctx.Idents.get("target"), &Ctx.Idents.get("selector")}; ADD_METHOD(UIAccessibilityCustomAction, @@ -382,7 +382,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { NEW_RECEIVER(NSAttributedString) ADD_UNARY_METHOD(NSAttributedString, initWithString, 0) - IdentifierInfo *initWithStringNSAttributedString[] = { + const IdentifierInfo *initWithStringNSAttributedString[] = { &Ctx.Idents.get("initWithString"), &Ctx.Idents.get("attributes")}; ADD_METHOD(NSAttributedString, initWithStringNSAttributedString, 2, 0) @@ -390,7 +390,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSText, setString, 0) NEW_RECEIVER(UIKeyCommand) - IdentifierInfo *keyCommandWithInputUIKeyCommand[] = { + const IdentifierInfo *keyCommandWithInputUIKeyCommand[] = { &Ctx.Idents.get("keyCommandWithInput"), &Ctx.Idents.get("modifierFlags"), &Ctx.Idents.get("action"), &Ctx.Idents.get("discoverabilityTitle")}; ADD_METHOD(UIKeyCommand, keyCommandWithInputUIKeyCommand, 4, 3) @@ -400,7 +400,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UILabel, setText, 0) NEW_RECEIVER(NSAlert) - IdentifierInfo *alertWithMessageTextNSAlert[] = { + const IdentifierInfo *alertWithMessageTextNSAlert[] = { &Ctx.Idents.get("alertWithMessageText"), &Ctx.Idents.get("defaultButton"), &Ctx.Idents.get("alternateButton"), &Ctx.Idents.get("otherButton"), &Ctx.Idents.get("informativeTextWithFormat")}; @@ -415,13 +415,13 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UIMutableApplicationShortcutItem, setLocalizedSubtitle, 0) NEW_RECEIVER(UIButton) - IdentifierInfo *setTitleUIButton[] = {&Ctx.Idents.get("setTitle"), - &Ctx.Idents.get("forState")}; + const IdentifierInfo *setTitleUIButton[] = {&Ctx.Idents.get("setTitle"), + &Ctx.Idents.get("forState")}; ADD_METHOD(UIButton, setTitleUIButton, 2, 0) NEW_RECEIVER(NSWindow) ADD_UNARY_METHOD(NSWindow, setTitle, 0) - IdentifierInfo *minFrameWidthWithTitleNSWindow[] = { + const IdentifierInfo *minFrameWidthWithTitleNSWindow[] = { &Ctx.Idents.get("minFrameWidthWithTitle"), &Ctx.Idents.get("styleMask")}; ADD_METHOD(NSWindow, minFrameWidthWithTitleNSWindow, 2, 0) ADD_UNARY_METHOD(NSWindow, setMiniwindowTitle, 0) @@ -430,7 +430,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSPathCell, setPlaceholderString, 0) NEW_RECEIVER(UIDocumentMenuViewController) - IdentifierInfo *addOptionWithTitleUIDocumentMenuViewController[] = { + const IdentifierInfo *addOptionWithTitleUIDocumentMenuViewController[] = { &Ctx.Idents.get("addOptionWithTitle"), &Ctx.Idents.get("image"), &Ctx.Idents.get("order"), &Ctx.Idents.get("handler")}; ADD_METHOD(UIDocumentMenuViewController, @@ -442,7 +442,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UINavigationItem, setPrompt, 0) NEW_RECEIVER(UIAlertView) - IdentifierInfo *initWithTitleUIAlertView[] = { + const IdentifierInfo *initWithTitleUIAlertView[] = { &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("message"), &Ctx.Idents.get("delegate"), &Ctx.Idents.get("cancelButtonTitle"), &Ctx.Idents.get("otherButtonTitles")}; @@ -474,11 +474,11 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSProgress, setLocalizedAdditionalDescription, 0) NEW_RECEIVER(NSSegmentedCell) - IdentifierInfo *setLabelNSSegmentedCell[] = {&Ctx.Idents.get("setLabel"), - &Ctx.Idents.get("forSegment")}; + const IdentifierInfo *setLabelNSSegmentedCell[] = { + &Ctx.Idents.get("setLabel"), &Ctx.Idents.get("forSegment")}; ADD_METHOD(NSSegmentedCell, setLabelNSSegmentedCell, 2, 0) - IdentifierInfo *setToolTipNSSegmentedCell[] = {&Ctx.Idents.get("setToolTip"), - &Ctx.Idents.get("forSegment")}; + const IdentifierInfo *setToolTipNSSegmentedCell[] = { + &Ctx.Idents.get("setToolTip"), &Ctx.Idents.get("forSegment")}; ADD_METHOD(NSSegmentedCell, setToolTipNSSegmentedCell, 2, 0) NEW_RECEIVER(NSUndoManager) @@ -487,7 +487,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSUndoManager, redoMenuTitleForUndoActionName, 0) NEW_RECEIVER(NSMenuItem) - IdentifierInfo *initWithTitleNSMenuItem[] = { + const IdentifierInfo *initWithTitleNSMenuItem[] = { &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("action"), &Ctx.Idents.get("keyEquivalent")}; ADD_METHOD(NSMenuItem, initWithTitleNSMenuItem, 3, 0) @@ -495,11 +495,11 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSMenuItem, setToolTip, 0) NEW_RECEIVER(NSPopUpButtonCell) - IdentifierInfo *initTextCellNSPopUpButtonCell[] = { + const IdentifierInfo *initTextCellNSPopUpButtonCell[] = { &Ctx.Idents.get("initTextCell"), &Ctx.Idents.get("pullsDown")}; ADD_METHOD(NSPopUpButtonCell, initTextCellNSPopUpButtonCell, 2, 0) ADD_UNARY_METHOD(NSPopUpButtonCell, addItemWithTitle, 0) - IdentifierInfo *insertItemWithTitleNSPopUpButtonCell[] = { + const IdentifierInfo *insertItemWithTitleNSPopUpButtonCell[] = { &Ctx.Idents.get("insertItemWithTitle"), &Ctx.Idents.get("atIndex")}; ADD_METHOD(NSPopUpButtonCell, insertItemWithTitleNSPopUpButtonCell, 2, 0) ADD_UNARY_METHOD(NSPopUpButtonCell, removeItemWithTitle, 0) @@ -511,11 +511,11 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { NEW_RECEIVER(NSMenu) ADD_UNARY_METHOD(NSMenu, initWithTitle, 0) - IdentifierInfo *insertItemWithTitleNSMenu[] = { + const IdentifierInfo *insertItemWithTitleNSMenu[] = { &Ctx.Idents.get("insertItemWithTitle"), &Ctx.Idents.get("action"), &Ctx.Idents.get("keyEquivalent"), &Ctx.Idents.get("atIndex")}; ADD_METHOD(NSMenu, insertItemWithTitleNSMenu, 4, 0) - IdentifierInfo *addItemWithTitleNSMenu[] = { + const IdentifierInfo *addItemWithTitleNSMenu[] = { &Ctx.Idents.get("addItemWithTitle"), &Ctx.Idents.get("action"), &Ctx.Idents.get("keyEquivalent")}; ADD_METHOD(NSMenu, addItemWithTitleNSMenu, 3, 0) @@ -526,15 +526,15 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { NEW_RECEIVER(NSForm) ADD_UNARY_METHOD(NSForm, addEntry, 0) - IdentifierInfo *insertEntryNSForm[] = {&Ctx.Idents.get("insertEntry"), - &Ctx.Idents.get("atIndex")}; + const IdentifierInfo *insertEntryNSForm[] = {&Ctx.Idents.get("insertEntry"), + &Ctx.Idents.get("atIndex")}; ADD_METHOD(NSForm, insertEntryNSForm, 2, 0) NEW_RECEIVER(NSTextFieldCell) ADD_UNARY_METHOD(NSTextFieldCell, setPlaceholderString, 0) NEW_RECEIVER(NSUserNotificationAction) - IdentifierInfo *actionWithIdentifierNSUserNotificationAction[] = { + const IdentifierInfo *actionWithIdentifierNSUserNotificationAction[] = { &Ctx.Idents.get("actionWithIdentifier"), &Ctx.Idents.get("title")}; ADD_METHOD(NSUserNotificationAction, actionWithIdentifierNSUserNotificationAction, 2, 1) @@ -544,7 +544,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UITextField, setPlaceholder, 0) NEW_RECEIVER(UIBarButtonItem) - IdentifierInfo *initWithTitleUIBarButtonItem[] = { + const IdentifierInfo *initWithTitleUIBarButtonItem[] = { &Ctx.Idents.get("initWithTitle"), &Ctx.Idents.get("style"), &Ctx.Idents.get("target"), &Ctx.Idents.get("action")}; ADD_METHOD(UIBarButtonItem, initWithTitleUIBarButtonItem, 4, 0) @@ -553,16 +553,16 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UIViewController, setTitle, 0) NEW_RECEIVER(UISegmentedControl) - IdentifierInfo *insertSegmentWithTitleUISegmentedControl[] = { + const IdentifierInfo *insertSegmentWithTitleUISegmentedControl[] = { &Ctx.Idents.get("insertSegmentWithTitle"), &Ctx.Idents.get("atIndex"), &Ctx.Idents.get("animated")}; ADD_METHOD(UISegmentedControl, insertSegmentWithTitleUISegmentedControl, 3, 0) - IdentifierInfo *setTitleUISegmentedControl[] = { + const IdentifierInfo *setTitleUISegmentedControl[] = { &Ctx.Idents.get("setTitle"), &Ctx.Idents.get("forSegmentAtIndex")}; ADD_METHOD(UISegmentedControl, setTitleUISegmentedControl, 2, 0) NEW_RECEIVER(NSAccessibilityCustomRotorItemResult) - IdentifierInfo + const IdentifierInfo *initWithItemLoadingTokenNSAccessibilityCustomRotorItemResult[] = { &Ctx.Idents.get("initWithItemLoadingToken"), &Ctx.Idents.get("customLabel")}; @@ -571,7 +571,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSAccessibilityCustomRotorItemResult, setCustomLabel, 0) NEW_RECEIVER(UIContextualAction) - IdentifierInfo *contextualActionWithStyleUIContextualAction[] = { + const IdentifierInfo *contextualActionWithStyleUIContextualAction[] = { &Ctx.Idents.get("contextualActionWithStyle"), &Ctx.Idents.get("title"), &Ctx.Idents.get("handler")}; ADD_METHOD(UIContextualAction, contextualActionWithStyleUIContextualAction, 3, @@ -579,7 +579,7 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(UIContextualAction, setTitle, 0) NEW_RECEIVER(NSAccessibilityCustomRotor) - IdentifierInfo *initWithLabelNSAccessibilityCustomRotor[] = { + const IdentifierInfo *initWithLabelNSAccessibilityCustomRotor[] = { &Ctx.Idents.get("initWithLabel"), &Ctx.Idents.get("itemSearchDelegate")}; ADD_METHOD(NSAccessibilityCustomRotor, initWithLabelNSAccessibilityCustomRotor, 2, 0) @@ -590,11 +590,11 @@ void NonLocalizedStringChecker::initUIMethods(ASTContext &Ctx) const { ADD_UNARY_METHOD(NSWindowTab, setToolTip, 0) NEW_RECEIVER(NSAccessibilityCustomAction) - IdentifierInfo *initWithNameNSAccessibilityCustomAction[] = { + const IdentifierInfo *initWithNameNSAccessibilityCustomAction[] = { &Ctx.Idents.get("initWithName"), &Ctx.Idents.get("handler")}; ADD_METHOD(NSAccessibilityCustomAction, initWithNameNSAccessibilityCustomAction, 2, 0) - IdentifierInfo *initWithNameTargetNSAccessibilityCustomAction[] = { + const IdentifierInfo *initWithNameTargetNSAccessibilityCustomAction[] = { &Ctx.Idents.get("initWithName"), &Ctx.Idents.get("target"), &Ctx.Idents.get("selector")}; ADD_METHOD(NSAccessibilityCustomAction, @@ -618,12 +618,12 @@ void NonLocalizedStringChecker::initLocStringsMethods(ASTContext &Ctx) const { if (!LSM.empty()) return; - IdentifierInfo *LocalizedStringMacro[] = { + const IdentifierInfo *LocalizedStringMacro[] = { &Ctx.Idents.get("localizedStringForKey"), &Ctx.Idents.get("value"), &Ctx.Idents.get("table")}; LSM_INSERT_SELECTOR("NSBundle", LocalizedStringMacro, 3) LSM_INSERT_UNARY("NSDateFormatter", "stringFromDate") - IdentifierInfo *LocalizedStringFromDate[] = { + const IdentifierInfo *LocalizedStringFromDate[] = { &Ctx.Idents.get("localizedStringFromDate"), &Ctx.Idents.get("dateStyle"), &Ctx.Idents.get("timeStyle")}; LSM_INSERT_SELECTOR("NSDateFormatter", LocalizedStringFromDate, 3) @@ -903,7 +903,7 @@ static inline bool isNSStringType(QualType T, ASTContext &Ctx) { if (!Cls) return false; - IdentifierInfo *ClsName = Cls->getIdentifier(); + const IdentifierInfo *ClsName = Cls->getIdentifier(); // FIXME: Should we walk the chain of classes? return ClsName == &Ctx.Idents.get("NSString") || diff --git a/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp index 06f1ad00eaf2..60934e51febe 100644 --- a/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp @@ -1082,7 +1082,8 @@ void NullabilityChecker::checkPostObjCMessage(const ObjCMethodCall &M, M.getMessageKind() == OCM_PropertyAccess && !C.wasInlined) { bool LookupResolved = false; if (const MemRegion *ReceiverRegion = getTrackRegion(M.getReceiverSVal())) { - if (IdentifierInfo *Ident = M.getSelector().getIdentifierInfoForSlot(0)) { + if (const IdentifierInfo *Ident = + M.getSelector().getIdentifierInfoForSlot(0)) { LookupResolved = true; ObjectPropPair Key = std::make_pair(ReceiverRegion, Ident); const ConstrainedPropertyVal *PrevPropVal = diff --git a/clang/lib/StaticAnalyzer/Checkers/ObjCMissingSuperCallChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/ObjCMissingSuperCallChecker.cpp index 598b368e74d4..03dab4f7ada7 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ObjCMissingSuperCallChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ObjCMissingSuperCallChecker.cpp @@ -107,7 +107,7 @@ void ObjCSuperCallChecker::fillSelectors(ASTContext &Ctx, assert(Descriptor.ArgumentCount <= 1); // No multi-argument selectors yet. // Get the selector. - IdentifierInfo *II = &Ctx.Idents.get(Descriptor.SelectorName); + const IdentifierInfo *II = &Ctx.Idents.get(Descriptor.SelectorName); Selector Sel = Ctx.Selectors.getSelector(Descriptor.ArgumentCount, &II); ClassSelectors.insert(Sel); diff --git a/clang/lib/StaticAnalyzer/Checkers/ObjCSuperDeallocChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/ObjCSuperDeallocChecker.cpp index eb40711812e1..a6c4186cb15b 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ObjCSuperDeallocChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ObjCSuperDeallocChecker.cpp @@ -26,8 +26,8 @@ namespace { class ObjCSuperDeallocChecker : public Checker { - mutable IdentifierInfo *IIdealloc = nullptr; - mutable IdentifierInfo *IINSObject = nullptr; + mutable const IdentifierInfo *IIdealloc = nullptr; + mutable const IdentifierInfo *IINSObject = nullptr; mutable Selector SELdealloc; const BugType DoubleSuperDeallocBugType{ diff --git a/clang/tools/libclang/CIndexCodeCompletion.cpp b/clang/tools/libclang/CIndexCodeCompletion.cpp index 3c5f390f6d88..850c004680fd 100644 --- a/clang/tools/libclang/CIndexCodeCompletion.cpp +++ b/clang/tools/libclang/CIndexCodeCompletion.cpp @@ -601,15 +601,15 @@ namespace { AllocatedResults.Contexts = getContextsForContextKind(contextKind, S); AllocatedResults.Selector = ""; - ArrayRef SelIdents = Context.getSelIdents(); - for (ArrayRef::iterator I = SelIdents.begin(), - E = SelIdents.end(); + ArrayRef SelIdents = Context.getSelIdents(); + for (ArrayRef::iterator I = SelIdents.begin(), + E = SelIdents.end(); I != E; ++I) { - if (IdentifierInfo *selIdent = *I) + if (const IdentifierInfo *selIdent = *I) AllocatedResults.Selector += selIdent->getName(); AllocatedResults.Selector += ":"; } - + QualType baseType = Context.getBaseType(); NamedDecl *D = nullptr; diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h b/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h index 95e8a600f838..cefec15a7980 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h +++ b/lldb/source/Plugins/ExpressionParser/Clang/ASTUtils.h @@ -56,7 +56,7 @@ public: return m_Source->GetExternalCXXBaseSpecifiers(Offset); } - void updateOutOfDateIdentifier(clang::IdentifierInfo &II) override { + void updateOutOfDateIdentifier(const clang::IdentifierInfo &II) override { m_Source->updateOutOfDateIdentifier(II); } diff --git a/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp b/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp index a95a9e9f01e3..75493eb10d73 100644 --- a/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp +++ b/lldb/source/Plugins/ExpressionParser/Clang/ClangASTSource.cpp @@ -713,17 +713,18 @@ bool ClangASTSource::FindObjCMethodDeclsWithOrigin( Selector original_selector; if (decl_name.isObjCZeroArgSelector()) { - IdentifierInfo *ident = &original_ctx->Idents.get(decl_name.getAsString()); + const IdentifierInfo *ident = + &original_ctx->Idents.get(decl_name.getAsString()); original_selector = original_ctx->Selectors.getSelector(0, &ident); } else if (decl_name.isObjCOneArgSelector()) { const std::string &decl_name_string = decl_name.getAsString(); std::string decl_name_string_without_colon(decl_name_string.c_str(), decl_name_string.length() - 1); - IdentifierInfo *ident = + const IdentifierInfo *ident = &original_ctx->Idents.get(decl_name_string_without_colon); original_selector = original_ctx->Selectors.getSelector(1, &ident); } else { - SmallVector idents; + SmallVector idents; clang::Selector sel = decl_name.getObjCSelector(); diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp index 5d7c5f38d180..6894cdccaf95 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp @@ -316,7 +316,7 @@ public: const bool HasRelatedResultType = false; const bool for_expression = true; - std::vector selector_components; + std::vector selector_components; const char *name_cursor = name; bool is_zero_argument = true; @@ -335,7 +335,7 @@ public: } } - clang::IdentifierInfo **identifier_infos = selector_components.data(); + const clang::IdentifierInfo **identifier_infos = selector_components.data(); if (!identifier_infos) { return nullptr; } diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 4a1c8d576552..ee634d12b3c4 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -7910,14 +7910,14 @@ bool TypeSystemClang::AddObjCClassProperty( if (property_setter_name) { std::string property_setter_no_colon(property_setter_name, strlen(property_setter_name) - 1); - clang::IdentifierInfo *setter_ident = + const clang::IdentifierInfo *setter_ident = &clang_ast.Idents.get(property_setter_no_colon); setter_sel = clang_ast.Selectors.getSelector(1, &setter_ident); } else if (!(property_attributes & DW_APPLE_PROPERTY_readonly)) { std::string setter_sel_string("set"); setter_sel_string.push_back(::toupper(property_name[0])); setter_sel_string.append(&property_name[1]); - clang::IdentifierInfo *setter_ident = + const clang::IdentifierInfo *setter_ident = &clang_ast.Idents.get(setter_sel_string); setter_sel = clang_ast.Selectors.getSelector(1, &setter_ident); } @@ -7925,11 +7925,12 @@ bool TypeSystemClang::AddObjCClassProperty( property_decl->setPropertyAttributes(ObjCPropertyAttribute::kind_setter); if (property_getter_name != nullptr) { - clang::IdentifierInfo *getter_ident = + const clang::IdentifierInfo *getter_ident = &clang_ast.Idents.get(property_getter_name); getter_sel = clang_ast.Selectors.getSelector(0, &getter_ident); } else { - clang::IdentifierInfo *getter_ident = &clang_ast.Idents.get(property_name); + const clang::IdentifierInfo *getter_ident = + &clang_ast.Idents.get(property_name); getter_sel = clang_ast.Selectors.getSelector(0, &getter_ident); } property_decl->setGetterName(getter_sel); @@ -8091,7 +8092,7 @@ clang::ObjCMethodDecl *TypeSystemClang::AddMethodToObjCObjectType( return nullptr; selector_start++; - llvm::SmallVector selector_idents; + llvm::SmallVector selector_idents; size_t len = 0; const char *start; -- GitLab From 51f1681424f1a8ccf1e3432d71c341e799597171 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Wed, 10 Apr 2024 19:06:29 -0700 Subject: [PATCH 470/695] [clang-format] Don't merge a short block for SBS_Never (#88238) Also fix unit tests. Fixes #87484. --- clang/lib/Format/FormatToken.h | 2 + clang/lib/Format/UnwrappedLineFormatter.cpp | 8 +- clang/lib/Format/UnwrappedLineParser.cpp | 7 +- clang/unittests/Format/BracesRemoverTest.cpp | 4 +- clang/unittests/Format/FormatTest.cpp | 84 +++++++++++++++---- .../Format/FormatTestMacroExpansion.cpp | 7 +- clang/unittests/Format/TokenAnnotatorTest.cpp | 24 ++++++ 7 files changed, 110 insertions(+), 26 deletions(-) diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h index 48b6a9092a8c..f651e6228c20 100644 --- a/clang/lib/Format/FormatToken.h +++ b/clang/lib/Format/FormatToken.h @@ -35,6 +35,8 @@ namespace format { TYPE(BinaryOperator) \ TYPE(BitFieldColon) \ TYPE(BlockComment) \ + /* l_brace of a block that is not the body of a (e.g. loop) statement. */ \ + TYPE(BlockLBrace) \ TYPE(BracedListLBrace) \ /* The colon at the end of a case label. */ \ TYPE(CaseLabelColon) \ diff --git a/clang/lib/Format/UnwrappedLineFormatter.cpp b/clang/lib/Format/UnwrappedLineFormatter.cpp index fb31980ab9f4..4ae54e56331b 100644 --- a/clang/lib/Format/UnwrappedLineFormatter.cpp +++ b/clang/lib/Format/UnwrappedLineFormatter.cpp @@ -796,8 +796,12 @@ private: } } - if (const auto *LastNonComment = Line.getLastNonComment(); - LastNonComment && LastNonComment->is(tok::l_brace)) { + if (Line.endsWith(tok::l_brace)) { + if (Style.AllowShortBlocksOnASingleLine == FormatStyle::SBS_Never && + Line.First->is(TT_BlockLBrace)) { + return 0; + } + if (IsSplitBlock && Line.First == Line.Last && I > AnnotatedLines.begin() && (I[-1]->endsWith(tok::kw_else) || IsCtrlStmt(*I[-1]))) { diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index c1f7e2874beb..603268f771ac 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -395,9 +395,10 @@ bool UnwrappedLineParser::parseLevel(const FormatToken *OpeningBrace, ParseDefault(); continue; } - if (!InRequiresExpression && FormatTok->isNot(TT_MacroBlockBegin) && - tryToParseBracedList()) { - continue; + if (!InRequiresExpression && FormatTok->isNot(TT_MacroBlockBegin)) { + if (tryToParseBracedList()) + continue; + FormatTok->setFinalizedType(TT_BlockLBrace); } parseBlock(); ++StatementCount; diff --git a/clang/unittests/Format/BracesRemoverTest.cpp b/clang/unittests/Format/BracesRemoverTest.cpp index 5155eefb9e08..2e983b887ffc 100644 --- a/clang/unittests/Format/BracesRemoverTest.cpp +++ b/clang/unittests/Format/BracesRemoverTest.cpp @@ -209,7 +209,9 @@ TEST_F(BracesRemoverTest, RemoveBraces) { verifyFormat("if (a) {\n" " b;\n" "} else {\n" - " { c; }\n" + " {\n" + " c;\n" + " }\n" "}", Style); diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index f312a9e21158..4906b3350b5b 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -52,7 +52,13 @@ TEST_F(FormatTest, FormatsUnwrappedLinesAtFirstFormat) { } TEST_F(FormatTest, FormatsNestedBlockStatements) { - verifyFormat("{\n {\n {}\n }\n}", "{{{}}}"); + verifyFormat("{\n" + " {\n" + " {\n" + " }\n" + " }\n" + "}", + "{{{}}}"); } TEST_F(FormatTest, FormatsNestedCall) { @@ -5669,7 +5675,10 @@ TEST_F(FormatTest, LayoutCodeInMacroDefinitions) { getLLVMStyleWithColumns(14)); } -TEST_F(FormatTest, LayoutRemainingTokens) { verifyFormat("{}"); } +TEST_F(FormatTest, LayoutRemainingTokens) { + verifyFormat("{\n" + "}"); +} TEST_F(FormatTest, MacroDefinitionInsideStatement) { verifyFormat("int x,\n" @@ -6577,7 +6586,11 @@ TEST_F(FormatTest, FormatAlignInsidePreprocessorElseBlock) { } TEST_F(FormatTest, FormatHashIfNotAtStartOfLine) { - verifyFormat("{\n { a #c; }\n}"); + verifyFormat("{\n" + " {\n" + " a #c;\n" + " }\n" + "}"); } TEST_F(FormatTest, FormatUnbalancedStructuralElements) { @@ -6937,13 +6950,13 @@ TEST_F(FormatTest, FormatNestedBlocksInMacros) { } TEST_F(FormatTest, PutEmptyBlocksIntoOneLine) { - verifyFormat("{}"); verifyFormat("enum E {};"); verifyFormat("enum E {}"); FormatStyle Style = getLLVMStyle(); Style.SpaceInEmptyBlock = true; verifyFormat("void f() { }", "void f() {}", Style); Style.AllowShortBlocksOnASingleLine = FormatStyle::SBS_Empty; + verifyFormat("{ }", Style); verifyFormat("while (true) { }", "while (true) {}", Style); Style.BreakBeforeBraces = FormatStyle::BS_Custom; Style.BraceWrapping.BeforeElse = false; @@ -11527,10 +11540,18 @@ TEST_F(FormatTest, UnderstandsNewAndDelete) { "void new (link p);\n" "void delete (link p);"); - verifyFormat("{ p->new(); }\n" - "{ p->delete(); }", - "{ p->new (); }\n" - "{ p->delete (); }"); + verifyFormat("{\n" + " p->new();\n" + "}\n" + "{\n" + " p->delete();\n" + "}", + "{\n" + " p->new ();\n" + "}\n" + "{\n" + " p->delete ();\n" + "}"); FormatStyle AfterPlacementOperator = getLLVMStyle(); AfterPlacementOperator.SpaceBeforeParens = FormatStyle::SBPO_Custom; @@ -12352,7 +12373,9 @@ TEST_F(FormatTest, FormatsCasts) { // FIXME: single value wrapped with paren will be treated as cast. verifyFormat("void f(int i = (kValue)*kMask) {}"); - verifyFormat("{ (void)F; }"); + verifyFormat("{\n" + " (void)F;\n" + "}"); // Don't break after a cast's verifyFormat("int aaaaaaaaaaaaaaaaaaaaaaaaaaa =\n" @@ -13575,7 +13598,8 @@ TEST_F(FormatTest, IncorrectAccessSpecifier) { verifyFormat("public\n" "B {}"); verifyFormat("public\n" - "{}"); + "{\n" + "}"); verifyFormat("public\n" "B { int x; }"); } @@ -13632,10 +13656,31 @@ TEST_F(FormatTest, DoesNotTouchUnwrappedLinesWithErrors) { } TEST_F(FormatTest, IncorrectCodeErrorDetection) { - verifyFormat("{\n {}", "{\n{\n}"); - verifyFormat("{\n {}", "{\n {\n}"); - verifyFormat("{\n {}", "{\n {\n }"); - verifyFormat("{\n {}\n}\n}", "{\n {\n }\n }\n}"); + verifyFormat("{\n" + " {\n" + " }", + "{\n" + "{\n" + "}"); + verifyFormat("{\n" + " {\n" + " }", + "{\n" + " {\n" + "}"); + verifyFormat("{\n" + " {\n" + " }"); + verifyFormat("{\n" + " {\n" + " }\n" + "}\n" + "}", + "{\n" + " {\n" + " }\n" + " }\n" + "}"); verifyFormat("{\n" " {\n" @@ -14080,10 +14125,14 @@ TEST_F(FormatTest, FormatsBracedListsInColumnLayout) { "}"); verifyFormat("void foo() {\n" " { // asdf\n" - " { int a; }\n" + " {\n" + " int a;\n" + " }\n" " }\n" " {\n" - " { int b; }\n" + " {\n" + " int b;\n" + " }\n" " }\n" "}"); verifyFormat("namespace n {\n" @@ -14095,7 +14144,8 @@ TEST_F(FormatTest, FormatsBracedListsInColumnLayout) { " }\n" " }\n" " }\n" - " {}\n" + " {\n" + " }\n" "}\n" "} // namespace n"); diff --git a/clang/unittests/Format/FormatTestMacroExpansion.cpp b/clang/unittests/Format/FormatTestMacroExpansion.cpp index 85ab6ea3794e..d391fe3d715c 100644 --- a/clang/unittests/Format/FormatTestMacroExpansion.cpp +++ b/clang/unittests/Format/FormatTestMacroExpansion.cpp @@ -43,9 +43,10 @@ TEST_F(FormatTestMacroExpansion, UnexpandConfiguredMacros) { "STMT", Style); verifyFormat("void f() { ID(a *b); }", Style); - verifyFormat(R"(ID( - { ID(a *b); }); -)", + verifyFormat("ID(\n" + " {\n" + " ID(a *b);\n" + " });", Style); verifyIncompleteFormat("ID3({, ID(a *b),\n" " ;\n" diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index c3153cf6b16f..da02ced8c7a9 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -2856,6 +2856,30 @@ TEST_F(TokenAnnotatorTest, UnderstandsElaboratedTypeSpecifier) { EXPECT_TOKEN(Tokens[7], tok::l_brace, TT_FunctionLBrace); } +TEST_F(TokenAnnotatorTest, BlockLBrace) { + auto Tokens = annotate("{\n" + " {\n" + " foo();\n" + " }\n" + "}"); + ASSERT_EQ(Tokens.size(), 9u) << Tokens; + EXPECT_TOKEN(Tokens[0], tok::l_brace, TT_BlockLBrace); + EXPECT_BRACE_KIND(Tokens[0], BK_Block); + EXPECT_TOKEN(Tokens[1], tok::l_brace, TT_BlockLBrace); + EXPECT_BRACE_KIND(Tokens[1], BK_Block); + + Tokens = annotate("void bar() {\n" + " {\n" + " foo();\n" + " }\n" + "}"); + ASSERT_EQ(Tokens.size(), 13u) << Tokens; + EXPECT_TOKEN(Tokens[4], tok::l_brace, TT_FunctionLBrace); + EXPECT_BRACE_KIND(Tokens[4], BK_Block); + EXPECT_TOKEN(Tokens[5], tok::l_brace, TT_BlockLBrace); + EXPECT_BRACE_KIND(Tokens[5], BK_Block); +} + } // namespace } // namespace format } // namespace clang -- GitLab From 6b46166ef2612d2a58767447b3db8f0343afb552 Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Thu, 11 Apr 2024 02:14:07 +0000 Subject: [PATCH 471/695] [llvm][NFC] Suppress `-Wunused-result` call to `write` Commit 87e6f87fe7e343eb656e9b49d30cbb065c086651 adds a call to `::write()`, which may be annotated w/ `warn_unused_result`, leading to `-Wunused-result` failures. --- llvm/lib/Support/raw_socket_stream.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Support/raw_socket_stream.cpp b/llvm/lib/Support/raw_socket_stream.cpp index 1dcf6352f2cc..14e2308df4d7 100644 --- a/llvm/lib/Support/raw_socket_stream.cpp +++ b/llvm/lib/Support/raw_socket_stream.cpp @@ -265,7 +265,10 @@ void ListeningSocket::shutdown() { // Ensure ::poll returns if shutdown is called by a seperate thread char Byte = 'A'; - ::write(PipeFD[1], &Byte, 1); + ssize_t written = ::write(PipeFD[1], &Byte, 1); + + // Ignore any write() error + (void)written; } ListeningSocket::~ListeningSocket() { -- GitLab From f4509cf284ced95f31dc7eb63144b4bc47899c43 Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Thu, 11 Apr 2024 10:18:29 +0800 Subject: [PATCH 472/695] [X86][MC] Support enc/dec for SETZUCC and promoted SETCC. (#86473) apx-spec: https://cdrdv2.intel.com/v1/dl/getContent/784266 apx-syntax-recommendation: https://cdrdv2.intel.com/v1/dl/getContent/817241 --- .../lib/Target/X86/AsmParser/X86AsmParser.cpp | 1 + .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 2 + llvm/lib/Target/X86/X86InstrAsmAlias.td | 8 +- llvm/lib/Target/X86/X86InstrCMovSetCC.td | 19 +++ llvm/lib/Target/X86/X86InstrControl.td | 24 ++-- .../MC/Disassembler/X86/apx/evex-format.txt | 10 ++ llvm/test/MC/Disassembler/X86/apx/setcc.txt | 130 ++++++++++++++++++ llvm/test/MC/Disassembler/X86/apx/setzucc.txt | 130 ++++++++++++++++++ llvm/test/MC/X86/apx/evex-format-att.s | 10 ++ llvm/test/MC/X86/apx/evex-format-intel.s | 10 ++ llvm/test/MC/X86/apx/setcc-att.s | 101 ++++++++++++++ llvm/test/MC/X86/apx/setcc-intel.s | 98 +++++++++++++ llvm/test/MC/X86/apx/setzucc-att.s | 101 ++++++++++++++ llvm/test/MC/X86/apx/setzucc-intel.s | 98 +++++++++++++ llvm/test/TableGen/x86-fold-tables.inc | 1 + llvm/utils/TableGen/AsmMatcherEmitter.cpp | 13 +- 16 files changed, 736 insertions(+), 20 deletions(-) create mode 100644 llvm/test/MC/Disassembler/X86/apx/setcc.txt create mode 100644 llvm/test/MC/Disassembler/X86/apx/setzucc.txt create mode 100644 llvm/test/MC/X86/apx/setcc-att.s create mode 100644 llvm/test/MC/X86/apx/setcc-intel.s create mode 100644 llvm/test/MC/X86/apx/setzucc-att.s create mode 100644 llvm/test/MC/X86/apx/setzucc-intel.s diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 6401df9f49f0..b05a036fb2f0 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -3287,6 +3287,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // FIXME: Hack to recognize setneb as setne. if (PatchedName.starts_with("set") && PatchedName.ends_with("b") && + PatchedName != "setzub" && PatchedName != "setzunb" && PatchedName != "setb" && PatchedName != "setnb") PatchedName = PatchedName.substr(0, Name.size()-1); diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 92a14226a0dc..a5859f98bae0 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1155,6 +1155,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI, Prefix.setXX2(MI, MemOperand + X86::AddrIndexReg); break; } + case X86II::MRMXmCC: case X86II::MRM0m: case X86II::MRM1m: case X86II::MRM2m: @@ -1282,6 +1283,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI, Prefix.setRR2(MI, CurOp++); break; } + case X86II::MRMXrCC: case X86II::MRM0r: case X86II::MRM1r: case X86II::MRM2r: diff --git a/llvm/lib/Target/X86/X86InstrAsmAlias.td b/llvm/lib/Target/X86/X86InstrAsmAlias.td index 6b15213a2e68..d06a0c79b46b 100644 --- a/llvm/lib/Target/X86/X86InstrAsmAlias.td +++ b/llvm/lib/Target/X86/X86InstrAsmAlias.td @@ -760,7 +760,7 @@ def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}", (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>; -// CMOV SETCC Aliases +// CMOV SETCC SETZUCC Aliases multiclass CMOV_SETCC_Aliases { def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}", (CMOV16rr GR16:$dst, GR16:$src, CC), 0>; @@ -787,8 +787,12 @@ let Predicates = [In64BitMode] in { (CMOV64rr_ND GR64:$dst, GR64:$src1, GR64:$src2, CC), 0>; def : InstAlias<"cmov"#Cond#"{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", (CMOV64rm_ND GR64:$dst, GR64:$src1, i64mem:$src2, CC), 0>; -} + def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCr GR8:$dst, CC), 0>; + def : InstAlias<"setzu"#Cond#"\t$dst", (SETZUCCm i8mem:$dst, CC), 0>; + def : InstAlias<"set"#Cond#"\t$dst", (SETCCr_EVEX GR8:$dst, CC), 0>; + def : InstAlias<"set"#Cond#"\t$dst", (SETCCm_EVEX i8mem:$dst, CC), 0>; +} def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>; def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>; } diff --git a/llvm/lib/Target/X86/X86InstrCMovSetCC.td b/llvm/lib/Target/X86/X86InstrCMovSetCC.td index d41591f68a60..27a0c889a4da 100644 --- a/llvm/lib/Target/X86/X86InstrCMovSetCC.td +++ b/llvm/lib/Target/X86/X86InstrCMovSetCC.td @@ -127,6 +127,25 @@ let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1 in { TB, Sched<[WriteSETCCStore]>; } // Uses = [EFLAGS] +// SetZUCC and promoted SetCC instructions. +let Uses = [EFLAGS], isCodeGenOnly = 1, ForceDisassemble = 1, + hasSideEffects = 0, Predicates = [In64BitMode], Predicates = [HasNDD] in { + def SETZUCCr : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond), + "setzu${cond}\t$dst", []>, + XD, ZU, NoCD8, Sched<[WriteSETCC]>; + def SETCCr_EVEX : I<0x40, MRMXrCC, (outs GR8:$dst), (ins ccode:$cond), + "set${cond}\t$dst", []>, + XD, PL, Sched<[WriteSETCC]>; + let mayStore = 1 in { + def SETZUCCm : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond), + "setzu${cond}\t$dst", []>, + XD, ZU, NoCD8, Sched<[WriteSETCCStore]>; + def SETCCm_EVEX : I<0x40, MRMXmCC, (outs), (ins i8mem:$dst, ccode:$cond), + "set${cond}\t$dst", []>, + XD, PL, Sched<[WriteSETCCStore]>; + } +} + // SALC is an undocumented instruction. Information for this instruction can be found // here http://www.rcollins.org/secrets/opcodes/SALC.html // Set AL if carry. diff --git a/llvm/lib/Target/X86/X86InstrControl.td b/llvm/lib/Target/X86/X86InstrControl.td index 5171c2249dee..62cc758cc594 100644 --- a/llvm/lib/Target/X86/X86InstrControl.td +++ b/llvm/lib/Target/X86/X86InstrControl.td @@ -167,24 +167,24 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { } let Predicates = [Not64BitMode], AsmVariantName = "att" in { - def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), - (ins i16imm:$off, i16imm:$seg), - "ljmp{w}\t$seg, $off", []>, - OpSize16, Sched<[WriteJump]>; def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), "ljmp{l}\t$seg, $off", []>, OpSize32, Sched<[WriteJump]>; + def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), + (ins i16imm:$off, i16imm:$seg), + "ljmp{w}\t$seg, $off", []>, + OpSize16, Sched<[WriteJump]>; } let mayLoad = 1 in { def FARJMP64m : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; + def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; let AsmVariantName = "att" in def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; - def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), - "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; } } @@ -253,21 +253,21 @@ let isCall = 1 in } let Predicates = [Not64BitMode], AsmVariantName = "att" in { - def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), - (ins i16imm:$off, i16imm:$seg), - "lcall{w}\t$seg, $off", []>, - OpSize16, Sched<[WriteJump]>; def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), "lcall{l}\t$seg, $off", []>, OpSize32, Sched<[WriteJump]>; + def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), + (ins i16imm:$off, i16imm:$seg), + "lcall{w}\t$seg, $off", []>, + OpSize16, Sched<[WriteJump]>; } let mayLoad = 1 in { - def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), - "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; + def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; } } diff --git a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt index 1156f5c40992..e9a9f1327a17 100644 --- a/llvm/test/MC/Disassembler/X86/apx/evex-format.txt +++ b/llvm/test/MC/Disassembler/X86/apx/evex-format.txt @@ -215,6 +215,16 @@ # INTEL: sar r17, r16, 123 0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b +## MRMXrCC +# ATT: setzuo %r16b +# INTEL: setzuo r16b +0x62,0xfc,0x7f,0x18,0x40,0xc0 + +## MRMXmCC +# ATT: setzuo (%r16,%r17) +# INTEL: setzuo byte ptr [r16 + r17] +0x62,0xfc,0x7b,0x18,0x40,0x04,0x08 + ## NoCD8 # ATT: {nf} negq 123(%r16) diff --git a/llvm/test/MC/Disassembler/X86/apx/setcc.txt b/llvm/test/MC/Disassembler/X86/apx/setcc.txt new file mode 100644 index 000000000000..1c00acfb7667 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/setcc.txt @@ -0,0 +1,130 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: {evex} seto %al +# INTEL: {evex} seto al +0x62,0xf4,0x7f,0x08,0x40,0xc0 + +# ATT: {evex} setno %al +# INTEL: {evex} setno al +0x62,0xf4,0x7f,0x08,0x41,0xc0 + +# ATT: {evex} setb %al +# INTEL: {evex} setb al +0x62,0xf4,0x7f,0x08,0x42,0xc0 + +# ATT: {evex} setae %al +# INTEL: {evex} setae al +0x62,0xf4,0x7f,0x08,0x43,0xc0 + +# ATT: {evex} sete %al +# INTEL: {evex} sete al +0x62,0xf4,0x7f,0x08,0x44,0xc0 + +# ATT: {evex} setne %al +# INTEL: {evex} setne al +0x62,0xf4,0x7f,0x08,0x45,0xc0 + +# ATT: {evex} setbe %al +# INTEL: {evex} setbe al +0x62,0xf4,0x7f,0x08,0x46,0xc0 + +# ATT: {evex} seta %al +# INTEL: {evex} seta al +0x62,0xf4,0x7f,0x08,0x47,0xc0 + +# ATT: {evex} sets %al +# INTEL: {evex} sets al +0x62,0xf4,0x7f,0x08,0x48,0xc0 + +# ATT: {evex} setns %al +# INTEL: {evex} setns al +0x62,0xf4,0x7f,0x08,0x49,0xc0 + +# ATT: {evex} setp %al +# INTEL: {evex} setp al +0x62,0xf4,0x7f,0x08,0x4a,0xc0 + +# ATT: {evex} setnp %al +# INTEL: {evex} setnp al +0x62,0xf4,0x7f,0x08,0x4b,0xc0 + +# ATT: {evex} setl %al +# INTEL: {evex} setl al +0x62,0xf4,0x7f,0x08,0x4c,0xc0 + +# ATT: {evex} setge %al +# INTEL: {evex} setge al +0x62,0xf4,0x7f,0x08,0x4d,0xc0 + +# ATT: {evex} setle %al +# INTEL: {evex} setle al +0x62,0xf4,0x7f,0x08,0x4e,0xc0 + +# ATT: {evex} setg %al +# INTEL: {evex} setg al +0x62,0xf4,0x7f,0x08,0x4f,0xc0 + +# ATT: {evex} seto (%rax) +# INTEL: {evex} seto byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x40,0x00 + +# ATT: {evex} setno (%rax) +# INTEL: {evex} setno byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x41,0x00 + +# ATT: {evex} setb (%rax) +# INTEL: {evex} setb byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x42,0x00 + +# ATT: {evex} setae (%rax) +# INTEL: {evex} setae byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x43,0x00 + +# ATT: {evex} sete (%rax) +# INTEL: {evex} sete byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x44,0x00 + +# ATT: {evex} setne (%rax) +# INTEL: {evex} setne byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x45,0x00 + +# ATT: {evex} setbe (%rax) +# INTEL: {evex} setbe byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x46,0x00 + +# ATT: {evex} seta (%rax) +# INTEL: {evex} seta byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x47,0x00 + +# ATT: {evex} sets (%rax) +# INTEL: {evex} sets byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x48,0x00 + +# ATT: {evex} setns (%rax) +# INTEL: {evex} setns byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x49,0x00 + +# ATT: {evex} setp (%rax) +# INTEL: {evex} setp byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x4a,0x00 + +# ATT: {evex} setnp (%rax) +# INTEL: {evex} setnp byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x4b,0x00 + +# ATT: {evex} setl (%rax) +# INTEL: {evex} setl byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x4c,0x00 + +# ATT: {evex} setge (%rax) +# INTEL: {evex} setge byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x4d,0x00 + +# ATT: {evex} setle (%rax) +# INTEL: {evex} setle byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x4e,0x00 + +# ATT: {evex} setg (%rax) +# INTEL: {evex} setg byte ptr [rax] +0x62,0xf4,0x7f,0x08,0x4f,0x00 diff --git a/llvm/test/MC/Disassembler/X86/apx/setzucc.txt b/llvm/test/MC/Disassembler/X86/apx/setzucc.txt new file mode 100644 index 000000000000..44aaa4b33cc8 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/setzucc.txt @@ -0,0 +1,130 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: setzuo %al +# INTEL: setzuo al +0x62,0xf4,0x7f,0x18,0x40,0xc0 + +# ATT: setzuno %al +# INTEL: setzuno al +0x62,0xf4,0x7f,0x18,0x41,0xc0 + +# ATT: setzub %al +# INTEL: setzub al +0x62,0xf4,0x7f,0x18,0x42,0xc0 + +# ATT: setzuae %al +# INTEL: setzuae al +0x62,0xf4,0x7f,0x18,0x43,0xc0 + +# ATT: setzue %al +# INTEL: setzue al +0x62,0xf4,0x7f,0x18,0x44,0xc0 + +# ATT: setzune %al +# INTEL: setzune al +0x62,0xf4,0x7f,0x18,0x45,0xc0 + +# ATT: setzube %al +# INTEL: setzube al +0x62,0xf4,0x7f,0x18,0x46,0xc0 + +# ATT: setzua %al +# INTEL: setzua al +0x62,0xf4,0x7f,0x18,0x47,0xc0 + +# ATT: setzus %al +# INTEL: setzus al +0x62,0xf4,0x7f,0x18,0x48,0xc0 + +# ATT: setzuns %al +# INTEL: setzuns al +0x62,0xf4,0x7f,0x18,0x49,0xc0 + +# ATT: setzup %al +# INTEL: setzup al +0x62,0xf4,0x7f,0x18,0x4a,0xc0 + +# ATT: setzunp %al +# INTEL: setzunp al +0x62,0xf4,0x7f,0x18,0x4b,0xc0 + +# ATT: setzul %al +# INTEL: setzul al +0x62,0xf4,0x7f,0x18,0x4c,0xc0 + +# ATT: setzuge %al +# INTEL: setzuge al +0x62,0xf4,0x7f,0x18,0x4d,0xc0 + +# ATT: setzule %al +# INTEL: setzule al +0x62,0xf4,0x7f,0x18,0x4e,0xc0 + +# ATT: setzug %al +# INTEL: setzug al +0x62,0xf4,0x7f,0x18,0x4f,0xc0 + +# ATT: setzuo (%rax) +# INTEL: setzuo byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x40,0x00 + +# ATT: setzuno (%rax) +# INTEL: setzuno byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x41,0x00 + +# ATT: setzub (%rax) +# INTEL: setzub byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x42,0x00 + +# ATT: setzuae (%rax) +# INTEL: setzuae byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x43,0x00 + +# ATT: setzue (%rax) +# INTEL: setzue byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x44,0x00 + +# ATT: setzune (%rax) +# INTEL: setzune byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x45,0x00 + +# ATT: setzube (%rax) +# INTEL: setzube byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x46,0x00 + +# ATT: setzua (%rax) +# INTEL: setzua byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x47,0x00 + +# ATT: setzus (%rax) +# INTEL: setzus byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x48,0x00 + +# ATT: setzuns (%rax) +# INTEL: setzuns byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x49,0x00 + +# ATT: setzup (%rax) +# INTEL: setzup byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x4a,0x00 + +# ATT: setzunp (%rax) +# INTEL: setzunp byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x4b,0x00 + +# ATT: setzul (%rax) +# INTEL: setzul byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x4c,0x00 + +# ATT: setzuge (%rax) +# INTEL: setzuge byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x4d,0x00 + +# ATT: setzule (%rax) +# INTEL: setzule byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x4e,0x00 + +# ATT: setzug (%rax) +# INTEL: setzug byte ptr [rax] +0x62,0xf4,0x7f,0x18,0x4f,0x00 diff --git a/llvm/test/MC/X86/apx/evex-format-att.s b/llvm/test/MC/X86/apx/evex-format-att.s index 36df3f3757dc..e59039ea2d82 100644 --- a/llvm/test/MC/X86/apx/evex-format-att.s +++ b/llvm/test/MC/X86/apx/evex-format-att.s @@ -210,6 +210,16 @@ # CHECK: encoding: [0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b] sarq $123, %r16, %r17 +## MRMXrCC +# CHECK: setzuo %r16b +# CHECK: encoding: [0x62,0xfc,0x7f,0x18,0x40,0xc0] + setzuo %r16b + +## MRMXmCC +# CHECK: setzuo (%r16,%r17) +# CHECK: encoding: [0x62,0xfc,0x7b,0x18,0x40,0x04,0x08] + setzuo (%r16,%r17) + ## NoCD8 # CHECK: {nf} negq 123(%r16) diff --git a/llvm/test/MC/X86/apx/evex-format-intel.s b/llvm/test/MC/X86/apx/evex-format-intel.s index 2b346e0e8580..42d4c0c0081a 100644 --- a/llvm/test/MC/X86/apx/evex-format-intel.s +++ b/llvm/test/MC/X86/apx/evex-format-intel.s @@ -210,6 +210,16 @@ # CHECK: encoding: [0x62,0xfc,0xf4,0x10,0xc1,0xf8,0x7b] sar r17, r16, 123 +## MRMXrCC +# CHECK: setzuo r16b +# CHECK: encoding: [0x62,0xfc,0x7f,0x18,0x40,0xc0] + setzuo r16b + +## MRMXmCC +# CHECK: setzuo byte ptr [r16 + r17] +# CHECK: encoding: [0x62,0xfc,0x7b,0x18,0x40,0x04,0x08] + setzuo byte ptr [r16 + r17] + ## NoCD8 # CHECK: {nf} neg qword ptr [r16 + 123] diff --git a/llvm/test/MC/X86/apx/setcc-att.s b/llvm/test/MC/X86/apx/setcc-att.s new file mode 100644 index 000000000000..b5518081a820 --- /dev/null +++ b/llvm/test/MC/X86/apx/setcc-att.s @@ -0,0 +1,101 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-32: error: +# ERROR-NOT: error: +# CHECK: {evex} seto %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0xc0] + {evex} seto %al +# CHECK: {evex} setno %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0xc0] + {evex} setno %al +# CHECK: {evex} setb %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0xc0] + {evex} setb %al +# CHECK: {evex} setae %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0xc0] + {evex} setae %al +# CHECK: {evex} sete %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0xc0] + {evex} sete %al +# CHECK: {evex} setne %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0xc0] + {evex} setne %al +# CHECK: {evex} setbe %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0xc0] + {evex} setbe %al +# CHECK: {evex} seta %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0xc0] + {evex} seta %al +# CHECK: {evex} sets %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0xc0] + {evex} sets %al +# CHECK: {evex} setns %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0xc0] + {evex} setns %al +# CHECK: {evex} setp %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0xc0] + {evex} setp %al +# CHECK: {evex} setnp %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0xc0] + {evex} setnp %al +# CHECK: {evex} setl %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0xc0] + {evex} setl %al +# CHECK: {evex} setge %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0xc0] + {evex} setge %al +# CHECK: {evex} setle %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0xc0] + {evex} setle %al +# CHECK: {evex} setg %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0xc0] + {evex} setg %al +# CHECK: {evex} seto (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0x00] + {evex} seto (%rax) +# CHECK: {evex} setno (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0x00] + {evex} setno (%rax) +# CHECK: {evex} setb (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0x00] + {evex} setb (%rax) +# CHECK: {evex} setae (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0x00] + {evex} setae (%rax) +# CHECK: {evex} sete (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0x00] + {evex} sete (%rax) +# CHECK: {evex} setne (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0x00] + {evex} setne (%rax) +# CHECK: {evex} setbe (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0x00] + {evex} setbe (%rax) +# CHECK: {evex} seta (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0x00] + {evex} seta (%rax) +# CHECK: {evex} sets (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0x00] + {evex} sets (%rax) +# CHECK: {evex} setns (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0x00] + {evex} setns (%rax) +# CHECK: {evex} setp (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0x00] + {evex} setp (%rax) +# CHECK: {evex} setnp (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0x00] + {evex} setnp (%rax) +# CHECK: {evex} setl (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0x00] + {evex} setl (%rax) +# CHECK: {evex} setge (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0x00] + {evex} setge (%rax) +# CHECK: {evex} setle (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0x00] + {evex} setle (%rax) +# CHECK: {evex} setg (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0x00] + {evex} setgb (%rax) diff --git a/llvm/test/MC/X86/apx/setcc-intel.s b/llvm/test/MC/X86/apx/setcc-intel.s new file mode 100644 index 000000000000..e005c2edb95c --- /dev/null +++ b/llvm/test/MC/X86/apx/setcc-intel.s @@ -0,0 +1,98 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: {evex} seto al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0xc0] + {evex} seto al +# CHECK: {evex} setno al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0xc0] + {evex} setno al +# CHECK: {evex} setb al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0xc0] + {evex} setb al +# CHECK: {evex} setae al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0xc0] + {evex} setae al +# CHECK: {evex} sete al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0xc0] + {evex} sete al +# CHECK: {evex} setne al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0xc0] + {evex} setne al +# CHECK: {evex} setbe al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0xc0] + {evex} setbe al +# CHECK: {evex} seta al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0xc0] + {evex} seta al +# CHECK: {evex} sets al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0xc0] + {evex} sets al +# CHECK: {evex} setns al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0xc0] + {evex} setns al +# CHECK: {evex} setp al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0xc0] + {evex} setp al +# CHECK: {evex} setnp al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0xc0] + {evex} setnp al +# CHECK: {evex} setl al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0xc0] + {evex} setl al +# CHECK: {evex} setge al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0xc0] + {evex} setge al +# CHECK: {evex} setle al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0xc0] + {evex} setle al +# CHECK: {evex} setg al +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0xc0] + {evex} setg al +# CHECK: {evex} seto byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x40,0x00] + {evex} seto byte ptr [rax] +# CHECK: {evex} setno byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x41,0x00] + {evex} setno byte ptr [rax] +# CHECK: {evex} setb byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x42,0x00] + {evex} setb byte ptr [rax] +# CHECK: {evex} setae byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x43,0x00] + {evex} setae byte ptr [rax] +# CHECK: {evex} sete byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x44,0x00] + {evex} sete byte ptr [rax] +# CHECK: {evex} setne byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x45,0x00] + {evex} setne byte ptr [rax] +# CHECK: {evex} setbe byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x46,0x00] + {evex} setbe byte ptr [rax] +# CHECK: {evex} seta byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x47,0x00] + {evex} seta byte ptr [rax] +# CHECK: {evex} sets byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x48,0x00] + {evex} sets byte ptr [rax] +# CHECK: {evex} setns byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x49,0x00] + {evex} setns byte ptr [rax] +# CHECK: {evex} setp byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4a,0x00] + {evex} setp byte ptr [rax] +# CHECK: {evex} setnp byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4b,0x00] + {evex} setnp byte ptr [rax] +# CHECK: {evex} setl byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4c,0x00] + {evex} setl byte ptr [rax] +# CHECK: {evex} setge byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4d,0x00] + {evex} setge byte ptr [rax] +# CHECK: {evex} setle byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4e,0x00] + {evex} setle byte ptr [rax] +# CHECK: {evex} setg byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x08,0x4f,0x00] + {evex} setg byte ptr [rax] diff --git a/llvm/test/MC/X86/apx/setzucc-att.s b/llvm/test/MC/X86/apx/setzucc-att.s new file mode 100644 index 000000000000..b4b7a633fa31 --- /dev/null +++ b/llvm/test/MC/X86/apx/setzucc-att.s @@ -0,0 +1,101 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s +# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR + +# ERROR-COUNT-32: error: +# ERROR-NOT: error: +# CHECK: setzuo %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0xc0] + setzuo %al +# CHECK: setzuno %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc0] + setzuno %al +# CHECK: setzub %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0] + setzub %al +# CHECK: setzuae %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0] + setzuae %al +# CHECK: setzue %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0] + setzue %al +# CHECK: setzune %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0] + setzune %al +# CHECK: setzube %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0xc0] + setzube %al +# CHECK: setzua %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0] + setzua %al +# CHECK: setzus %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc0] + setzus %al +# CHECK: setzuns %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0] + setzuns %al +# CHECK: setzup %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0xc0] + setzup %al +# CHECK: setzunp %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0xc0] + setzunp %al +# CHECK: setzul %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0] + setzul %al +# CHECK: setzuge %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0] + setzuge %al +# CHECK: setzule %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0] + setzule %al +# CHECK: setzug %al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0] + setzug %al +# CHECK: setzuo (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0x00] + setzuo (%rax) +# CHECK: setzuno (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0x00] + setzuno (%rax) +# CHECK: setzub (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0x00] + setzub (%rax) +# CHECK: setzuae (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0x00] + setzuae (%rax) +# CHECK: setzue (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0x00] + setzue (%rax) +# CHECK: setzune (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0x00] + setzune (%rax) +# CHECK: setzube (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0x00] + setzube (%rax) +# CHECK: setzua (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0x00] + setzua (%rax) +# CHECK: setzus (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0x00] + setzus (%rax) +# CHECK: setzuns (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0x00] + setzuns (%rax) +# CHECK: setzup (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0x00] + setzup (%rax) +# CHECK: setzunp (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0x00] + setzunp (%rax) +# CHECK: setzul (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0x00] + setzul (%rax) +# CHECK: setzuge (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0x00] + setzuge (%rax) +# CHECK: setzule (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0x00] + setzule (%rax) +# CHECK: setzug (%rax) +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0x00] + setzug (%rax) diff --git a/llvm/test/MC/X86/apx/setzucc-intel.s b/llvm/test/MC/X86/apx/setzucc-intel.s new file mode 100644 index 000000000000..bdefba6ac8d3 --- /dev/null +++ b/llvm/test/MC/X86/apx/setzucc-intel.s @@ -0,0 +1,98 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: setzuo al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0xc0] + setzuo al +# CHECK: setzuno al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0xc0] + setzuno al +# CHECK: setzub al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0xc0] + setzub al +# CHECK: setzuae al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0xc0] + setzuae al +# CHECK: setzue al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0xc0] + setzue al +# CHECK: setzune al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0xc0] + setzune al +# CHECK: setzube al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0xc0] + setzube al +# CHECK: setzua al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0xc0] + setzua al +# CHECK: setzus al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0xc0] + setzus al +# CHECK: setzuns al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0xc0] + setzuns al +# CHECK: setzup al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0xc0] + setzup al +# CHECK: setzunp al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0xc0] + setzunp al +# CHECK: setzul al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0xc0] + setzul al +# CHECK: setzuge al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0xc0] + setzuge al +# CHECK: setzule al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0xc0] + setzule al +# CHECK: setzug al +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0xc0] + setzug al +# CHECK: setzuo byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x40,0x00] + setzuo byte ptr [rax] +# CHECK: setzuno byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x41,0x00] + setzuno byte ptr [rax] +# CHECK: setzub byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x42,0x00] + setzub byte ptr [rax] +# CHECK: setzuae byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x43,0x00] + setzuae byte ptr [rax] +# CHECK: setzue byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x44,0x00] + setzue byte ptr [rax] +# CHECK: setzune byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x45,0x00] + setzune byte ptr [rax] +# CHECK: setzube byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x46,0x00] + setzube byte ptr [rax] +# CHECK: setzua byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x47,0x00] + setzua byte ptr [rax] +# CHECK: setzus byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x48,0x00] + setzus byte ptr [rax] +# CHECK: setzuns byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x49,0x00] + setzuns byte ptr [rax] +# CHECK: setzup byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4a,0x00] + setzup byte ptr [rax] +# CHECK: setzunp byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4b,0x00] + setzunp byte ptr [rax] +# CHECK: setzul byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4c,0x00] + setzul byte ptr [rax] +# CHECK: setzuge byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4d,0x00] + setzuge byte ptr [rax] +# CHECK: setzule byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4e,0x00] + setzule byte ptr [rax] +# CHECK: setzug byte ptr [rax] +# CHECK: encoding: [0x62,0xf4,0x7f,0x18,0x4f,0x00] + setzug byte ptr [rax] diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 493350d7bd63..6f983d2efabe 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -468,6 +468,7 @@ static const X86FoldTableEntry Table0[] = { {X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD}, {X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD}, {X86::SETCCr, X86::SETCCm, TB_FOLDED_STORE}, + {X86::SETZUCCr, X86::SETZUCCm, TB_FOLDED_STORE}, {X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD}, {X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD}, {X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD}, diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 8b82ce899a48..53d49a2900a1 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -645,12 +645,13 @@ struct MatchableInfo { // vex encoding size is smaller. Since X86InstrSSE.td is included ahead // of X86InstrAVX512.td, the AVX instruction ID is less than AVX512 ID. // We use the ID to sort AVX instruction before AVX512 instruction in - // matching table. - if (TheDef->isSubClassOf("Instruction") && - TheDef->getValueAsBit("HasPositionOrder") && - RHS.TheDef->isSubClassOf("Instruction") && - RHS.TheDef->getValueAsBit("HasPositionOrder")) - return TheDef->getID() < RHS.TheDef->getID(); + // matching table. As well as InstAlias. + if (getResultInst()->TheDef->isSubClassOf("Instruction") && + getResultInst()->TheDef->getValueAsBit("HasPositionOrder") && + RHS.getResultInst()->TheDef->isSubClassOf("Instruction") && + RHS.getResultInst()->TheDef->getValueAsBit("HasPositionOrder")) + return getResultInst()->TheDef->getID() < + RHS.getResultInst()->TheDef->getID(); // Give matches that require more features higher precedence. This is useful // because we cannot define AssemblerPredicates with the negation of -- GitLab From fd50151180498f0de4fe26ff21d3e3b8accc4de0 Mon Sep 17 00:00:00 2001 From: Jianjian Guan Date: Thu, 11 Apr 2024 10:23:26 +0800 Subject: [PATCH 473/695] [RISCV] Only support SPLAT_VECTOR for Zvfhmin when also enable the scalar extension of half fp (#88275) --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +- llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll | 35 +++++++++++++++------ 2 files changed, 28 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 944d8b6de895..1a3ef6feea3e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1063,7 +1063,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR, ISD::SCALAR_TO_VECTOR}, VT, Custom); - setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); + if (Subtarget.hasStdExtZfhminOrZhinxmin()) + setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); // load/store setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom); diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll index 707ef8a94432..1aebd32cefca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll @@ -1,19 +1,36 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfh,+v -target-abi ilp32d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,OPTIMIZED ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfh,+v -target-abi lp64d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,OPTIMIZED ; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfh,+v,+no-optimized-zero-stride-load -target-abi ilp32d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,NOT-OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,NOT-OPTIMIZED ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfh,+v,+no-optimized-zero-stride-load -target-abi lp64d -verify-machineinstrs < %s \ -; RUN: | FileCheck %s --check-prefixes=CHECK,NOT-OPTIMIZED +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH,NOT-OPTIMIZED +; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfhmin,+v -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,OPTIMIZED +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfhmin,+v -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,OPTIMIZED +; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+zvfhmin,+v,+no-optimized-zero-stride-load -target-abi ilp32d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,NOT-OPTIMIZED +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+zvfhmin,+v,+no-optimized-zero-stride-load -target-abi lp64d -verify-machineinstrs < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,NOT-OPTIMIZED define @vsplat_nxv8f16(half %f) { -; CHECK-LABEL: vsplat_nxv8f16: -; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma -; CHECK-NEXT: vfmv.v.f v8, fa0 -; CHECK-NEXT: ret +; ZVFH-LABEL: vsplat_nxv8f16: +; ZVFH: # %bb.0: +; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma +; ZVFH-NEXT: vfmv.v.f v8, fa0 +; ZVFH-NEXT: ret +; +; ZVFHMIN-LABEL: vsplat_nxv8f16: +; ZVFHMIN: # %bb.0: +; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0 +; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma +; ZVFHMIN-NEXT: vfmv.v.f v12, fa5 +; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12 +; ZVFHMIN-NEXT: ret %head = insertelement poison, half %f, i32 0 %splat = shufflevector %head, poison, zeroinitializer ret %splat -- GitLab From 999b9e6ddb4324600a46c8f7006acec81fe3af0f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 10 Apr 2024 19:36:31 -0700 Subject: [PATCH 474/695] [RISCV] Use vector getConstant instead of getSplatVector+getConstant. NFC --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 1a3ef6feea3e..357432081ddb 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4634,9 +4634,7 @@ static SDValue getWideningInterleave(SDValue EvenV, SDValue OddV, } else if (Subtarget.hasStdExtZvbb()) { // Interleaved = (OddV << VecVT.getScalarSizeInBits()) + EvenV. SDValue OffsetVec = - DAG.getSplatVector(VecContainerVT, DL, - DAG.getConstant(VecVT.getScalarSizeInBits(), DL, - Subtarget.getXLenVT())); + DAG.getConstant(VecVT.getScalarSizeInBits(), DL, VecContainerVT); Interleaved = DAG.getNode(RISCVISD::VWSLL_VL, DL, WideContainerVT, OddV, OffsetVec, Passthru, Mask, VL); if (!EvenV.isUndef()) -- GitLab From dda73336ad22bd0b5ecda17040c50fb10fcbe5fb Mon Sep 17 00:00:00 2001 From: Mingming Liu Date: Wed, 10 Apr 2024 19:46:01 -0700 Subject: [PATCH 475/695] [ThinLTO]Record import type in GlobalValueSummary::GVFlags (#87597) The motivating use case is to support import the function declaration across modules to construct call graph edges for indirect calls [1] when importing the function definition costs too much compile time (e.g., the function is too large has no `noinline` attribute). 1. Currently, when the compiled IR module doesn't have a function definition but its postlink combined summary contains the function summary or a global alias summary with this function as aliasee, the function definition will be imported from source module by IRMover. The implementation is in FunctionImporter::importFunctions [2] 2. In order for FunctionImporter to import a declaration of a function, both function summary and alias summary need to carry the def / decl state. Specifically, all existing summary fields doesn't differ across import modules, but the def / decl state of is decided by ``. This change encodes the def/decl state in `GlobalValueSummary::GVFlags`. In the subsequent changes 1. The indexing step `computeImportForModule` [3] will compute the set of definitions and the set of declarations for each module, and passing on the information to bitcode writer. 2. Bitcode writer will look up the def/decl state and sets the state when it writes out the flag value. This is demonstrated in https://github.com/llvm/llvm-project/pull/87600 3. Function importer will read the def/decl state when reading the combined summary to figure out two sets of global values, and IRMover will be updated to import the declaration (aka linkGlobalValuePrototype [4]) into the destination module. - The next change is https://github.com/llvm/llvm-project/pull/87600 [1] mentioned in rfc https://discourse.llvm.org/t/rfc-for-better-call-graph-sort-build-a-more-complete-call-graph-by-adding-more-indirect-call-edges/74029#support-cross-module-function-declaration-import-5 [2] https://github.com/llvm/llvm-project/blob/3b337242ee165554f0017b00671381ec5b1ba855/llvm/lib/Transforms/IPO/FunctionImport.cpp#L1608-L1764 [3] https://github.com/llvm/llvm-project/blob/3b337242ee165554f0017b00671381ec5b1ba855/llvm/lib/Transforms/IPO/FunctionImport.cpp#L856 [4] https://github.com/llvm/llvm-project/blob/3b337242ee165554f0017b00671381ec5b1ba855/llvm/lib/Linker/IRMover.cpp#L605 --- .../CodeGen/thinlto-distributed-cfi-devirt.ll | 2 +- clang/test/CodeGen/thinlto-distributed-cfi.ll | 2 +- clang/test/CodeGen/thinlto-funcattr-prop.ll | 4 +- lld/test/ELF/lto/comdat-nodeduplicate.ll | 8 +- llvm/include/llvm/AsmParser/LLParser.h | 2 + llvm/include/llvm/AsmParser/LLToken.h | 3 + llvm/include/llvm/IR/ModuleSummaryIndex.h | 29 +++++- llvm/include/llvm/IR/ModuleSummaryIndexYAML.h | 11 ++- llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | 12 ++- llvm/lib/AsmParser/LLLexer.cpp | 3 + llvm/lib/AsmParser/LLParser.cpp | 33 ++++++- llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 3 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 2 + llvm/lib/IR/AsmWriter.cpp | 12 +++ llvm/lib/IR/ModuleSummaryIndex.cpp | 4 + .../test/Assembler/thinlto-memprof-summary.ll | 20 ++-- .../thinlto-multiple-summaries-for-guid.ll | 4 +- .../Assembler/thinlto-summary-visibility.ll | 6 +- llvm/test/Assembler/thinlto-summary.ll | 92 ++++++++++--------- llvm/test/Assembler/thinlto-vtable-summary.ll | 4 +- llvm/test/Bitcode/thinlto-alias.ll | 10 +- .../thinlto-func-summary-vtableref-pgo.ll | 2 +- ...ction-summary-callgraph-profile-summary.ll | 18 ++-- ...hinlto-function-summary-callgraph-relbf.ll | 2 +- .../thinlto-function-summary-refgraph.ll | 14 +-- .../thinlto-index-disassembled-by-llvm-dis.ll | 2 +- llvm/test/Bitcode/thinlto-type-tests.ll | 12 +-- llvm/test/Bitcode/thinlto-type-vcalls.ll | 24 ++--- llvm/test/ThinLTO/X86/dot-dumper.ll | 12 +-- .../ThinLTO/X86/funcattrs-prop-maythrow.ll | 8 +- .../ThinLTO/X86/funcimport_alwaysinline.ll | 2 +- llvm/test/ThinLTO/X86/load-store-caching.ll | 4 +- .../Transforms/LowerTypeTests/import-unsat.ll | 1 + .../Inputs/import-indir.yaml | 4 + .../WholeProgramDevirt/import-indir.ll | 9 ++ 35 files changed, 241 insertions(+), 139 deletions(-) diff --git a/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll b/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll index 2309ed717c2a..433fd1fe2043 100644 --- a/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll +++ b/clang/test/CodeGen/thinlto-distributed-cfi-devirt.ll @@ -34,7 +34,7 @@ ; Round trip it through llvm-as ; RUN: llvm-dis %t.o.thinlto.bc -o - | llvm-as -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-DIS ; CHECK-DIS: ^0 = module: (path: "{{.*}}thinlto-distributed-cfi-devirt.ll.tmp.o", hash: ({{.*}}, {{.*}}, {{.*}}, {{.*}}, {{.*}})) -; CHECK-DIS: ^1 = gv: (guid: 8346051122425466633, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 0, canAutoHide: 0), insts: 18, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTests: (^2), typeCheckedLoadVCalls: (vFuncId: (^2, offset: 8), vFuncId: (^2, offset: 0)))))) +; CHECK-DIS: ^1 = gv: (guid: 8346051122425466633, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 18, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTests: (^2), typeCheckedLoadVCalls: (vFuncId: (^2, offset: 8), vFuncId: (^2, offset: 0)))))) ; CHECK-DIS: ^2 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: allOnes, sizeM1BitWidth: 7), wpdResolutions: ((offset: 0, wpdRes: (kind: branchFunnel)), (offset: 8, wpdRes: (kind: singleImpl, singleImplName: "_ZN1A1nEi"))))) ; guid = 7004155349499253778 ; RUN: %clang_cc1 -triple x86_64-grtev4-linux-gnu \ diff --git a/clang/test/CodeGen/thinlto-distributed-cfi.ll b/clang/test/CodeGen/thinlto-distributed-cfi.ll index f5dde2d32a42..47e56c091a61 100644 --- a/clang/test/CodeGen/thinlto-distributed-cfi.ll +++ b/clang/test/CodeGen/thinlto-distributed-cfi.ll @@ -24,7 +24,7 @@ ; Round trip it through llvm-as ; RUN: llvm-dis %t.o.thinlto.bc -o - | llvm-as -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-DIS ; CHECK-DIS: ^0 = module: (path: "{{.*}}thinlto-distributed-cfi.ll.tmp.o", hash: ({{.*}}, {{.*}}, {{.*}}, {{.*}}, {{.*}})) -; CHECK-DIS: ^1 = gv: (guid: 8346051122425466633, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 0, canAutoHide: 0), insts: 7, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), typeIdInfo: (typeTests: (^2))))) +; CHECK-DIS: ^1 = gv: (guid: 8346051122425466633, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 7, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), typeIdInfo: (typeTests: (^2))))) ; CHECK-DIS: ^2 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: single, sizeM1BitWidth: 0))) ; guid = 7004155349499253778 ; RUN: %clang_cc1 -triple x86_64-grtev4-linux-gnu \ diff --git a/clang/test/CodeGen/thinlto-funcattr-prop.ll b/clang/test/CodeGen/thinlto-funcattr-prop.ll index c1274776fe9c..daaa6e2da804 100644 --- a/clang/test/CodeGen/thinlto-funcattr-prop.ll +++ b/clang/test/CodeGen/thinlto-funcattr-prop.ll @@ -15,9 +15,9 @@ ; RUN: llvm-dis %t1.o.1.1.promote.bc -o - | FileCheck %s --check-prefix=CHECK-IR ;; Summary for call_extern. Note that llvm-lto2 writes out the index before propagation occurs so call_extern doesn't have its flags updated. -; CHECK-INDEX: ^2 = gv: (guid: 13959900437860518209, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0), insts: 2, calls: ((callee: ^3))))) +; CHECK-INDEX: ^2 = gv: (guid: 13959900437860518209, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 2, calls: ((callee: ^3))))) ;; Summary for extern -; CHECK-INDEX: ^3 = gv: (guid: 14959766916849974397, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 0, canAutoHide: 0), insts: 1, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) +; CHECK-INDEX: ^3 = gv: (guid: 14959766916849974397, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) ;--- a.ll target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/lld/test/ELF/lto/comdat-nodeduplicate.ll b/lld/test/ELF/lto/comdat-nodeduplicate.ll index eef17d41c5a4..13d4ab394813 100644 --- a/lld/test/ELF/lto/comdat-nodeduplicate.ll +++ b/lld/test/ELF/lto/comdat-nodeduplicate.ll @@ -56,15 +56,15 @@ ; IR_AB-DAG: gv: (name: "__profc_foo", {{.*}} guid = [[PROFC:[0-9]+]] ;; Check extra attributes. b.bc:__profc_foo is prevailing, so it can be internalized. -; IR_AB-DAG: gv: (guid: [[PROFD]], summaries: (variable: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0), -; IR_AB-DAG: gv: (guid: [[PROFC]], summaries: (variable: (module: ^0, flags: (linkage: internal, visibility: hidden, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) +; IR_AB-DAG: gv: (guid: [[PROFD]], summaries: (variable: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0), +; IR_AB-DAG: gv: (guid: [[PROFC]], summaries: (variable: (module: ^0, flags: (linkage: internal, visibility: hidden, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) ; IR_ABC-DAG: gv: (name: "__profd_foo", {{.*}} guid = [[PROFD:[0-9]+]] ; IR_ABC-DAG: gv: (name: "__profc_foo", {{.*}} guid = [[PROFC:[0-9]+]] ;; b.bc:__profc_foo prevails c.bc:__profc_foo, so it is exported and therefore not internalized. -; IR_ABC-DAG: gv: (guid: [[PROFD]], summaries: (variable: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0), -; IR_ABC-DAG: gv: (guid: [[PROFC]], summaries: (variable: (module: ^0, flags: (linkage: weak, visibility: hidden, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) +; IR_ABC-DAG: gv: (guid: [[PROFD]], summaries: (variable: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0), +; IR_ABC-DAG: gv: (guid: [[PROFC]], summaries: (variable: (module: ^0, flags: (linkage: weak, visibility: hidden, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) ;--- a.ll target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/include/llvm/AsmParser/LLParser.h b/llvm/include/llvm/AsmParser/LLParser.h index b4e971fea1a1..b2dcdfad0a04 100644 --- a/llvm/include/llvm/AsmParser/LLParser.h +++ b/llvm/include/llvm/AsmParser/LLParser.h @@ -301,6 +301,8 @@ namespace llvm { bool &DSOLocal); void parseOptionalDSOLocal(bool &DSOLocal); void parseOptionalVisibility(unsigned &Res); + bool parseOptionalImportType(lltok::Kind Kind, + GlobalValueSummary::ImportKind &Res); void parseOptionalDLLStorageClass(unsigned &Res); bool parseOptionalCallingConv(unsigned &CC); bool parseOptionalAlignment(MaybeAlign &Alignment, diff --git a/llvm/include/llvm/AsmParser/LLToken.h b/llvm/include/llvm/AsmParser/LLToken.h index 65ccb1b81b3a..0cbcdcd9ffac 100644 --- a/llvm/include/llvm/AsmParser/LLToken.h +++ b/llvm/include/llvm/AsmParser/LLToken.h @@ -370,6 +370,9 @@ enum Kind { kw_live, kw_dsoLocal, kw_canAutoHide, + kw_importType, + kw_definition, + kw_declaration, kw_function, kw_insts, kw_funcFlags, diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h index d5ff15063671..5d137d4b3553 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndex.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h @@ -432,6 +432,18 @@ public: /// Sububclass discriminator (for dyn_cast<> et al.) enum SummaryKind : unsigned { AliasKind, FunctionKind, GlobalVarKind }; + enum ImportKind : unsigned { + // The global value definition corresponding to the summary should be + // imported from source module + Definition = 0, + + // When its definition doesn't exist in the destination module and not + // imported (e.g., function is too large to be inlined), the global value + // declaration corresponding to the summary should be imported, or the + // attributes from summary should be annotated on the function declaration. + Declaration = 1, + }; + /// Group flags (Linkage, NotEligibleToImport, etc.) as a bitfield. struct GVFlags { /// The linkage type of the associated global value. @@ -472,14 +484,19 @@ public: /// means the symbol was externally visible. unsigned CanAutoHide : 1; + /// This field is written by the ThinLTO indexing step to postlink combined + /// summary. The value is interpreted as 'ImportKind' enum defined above. + unsigned ImportType : 1; + /// Convenience Constructors explicit GVFlags(GlobalValue::LinkageTypes Linkage, GlobalValue::VisibilityTypes Visibility, bool NotEligibleToImport, bool Live, bool IsLocal, - bool CanAutoHide) + bool CanAutoHide, ImportKind ImportType) : Linkage(Linkage), Visibility(Visibility), NotEligibleToImport(NotEligibleToImport), Live(Live), - DSOLocal(IsLocal), CanAutoHide(CanAutoHide) {} + DSOLocal(IsLocal), CanAutoHide(CanAutoHide), + ImportType(static_cast(ImportType)) {} }; private: @@ -564,6 +581,12 @@ public: bool canAutoHide() const { return Flags.CanAutoHide; } + bool shouldImportAsDecl() const { + return Flags.ImportType == GlobalValueSummary::ImportKind::Declaration; + } + + void setImportKind(ImportKind IK) { Flags.ImportType = IK; } + GlobalValue::VisibilityTypes getVisibility() const { return (GlobalValue::VisibilityTypes)Flags.Visibility; } @@ -813,7 +836,7 @@ public: GlobalValue::LinkageTypes::AvailableExternallyLinkage, GlobalValue::DefaultVisibility, /*NotEligibleToImport=*/true, /*Live=*/true, /*IsLocal=*/false, - /*CanAutoHide=*/false), + /*CanAutoHide=*/false, GlobalValueSummary::ImportKind::Definition), /*NumInsts=*/0, FunctionSummary::FFlags{}, /*EntryCount=*/0, std::vector(), std::move(Edges), std::vector(), diff --git a/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h b/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h index 33e57e5f2102..b2747d24c539 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h @@ -138,6 +138,7 @@ template <> struct MappingTraits { struct FunctionSummaryYaml { unsigned Linkage, Visibility; bool NotEligibleToImport, Live, IsLocal, CanAutoHide; + unsigned ImportType; std::vector Refs; std::vector TypeTests; std::vector TypeTestAssumeVCalls, @@ -183,6 +184,7 @@ template <> struct MappingTraits { io.mapOptional("Live", summary.Live); io.mapOptional("Local", summary.IsLocal); io.mapOptional("CanAutoHide", summary.CanAutoHide); + io.mapOptional("ImportType", summary.ImportType); io.mapOptional("Refs", summary.Refs); io.mapOptional("TypeTests", summary.TypeTests); io.mapOptional("TypeTestAssumeVCalls", summary.TypeTestAssumeVCalls); @@ -227,7 +229,8 @@ template <> struct CustomMappingTraits { static_cast(FSum.Linkage), static_cast(FSum.Visibility), FSum.NotEligibleToImport, FSum.Live, FSum.IsLocal, - FSum.CanAutoHide), + FSum.CanAutoHide, + static_cast(FSum.ImportType)), /*NumInsts=*/0, FunctionSummary::FFlags{}, /*EntryCount=*/0, Refs, ArrayRef{}, std::move(FSum.TypeTests), std::move(FSum.TypeTestAssumeVCalls), @@ -251,9 +254,9 @@ template <> struct CustomMappingTraits { static_cast(FSum->flags().NotEligibleToImport), static_cast(FSum->flags().Live), static_cast(FSum->flags().DSOLocal), - static_cast(FSum->flags().CanAutoHide), Refs, - FSum->type_tests(), FSum->type_test_assume_vcalls(), - FSum->type_checked_load_vcalls(), + static_cast(FSum->flags().CanAutoHide), + FSum->flags().ImportType, Refs, FSum->type_tests(), + FSum->type_test_assume_vcalls(), FSum->type_checked_load_vcalls(), FSum->type_test_assume_const_vcalls(), FSum->type_checked_load_const_vcalls()}); } diff --git a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp index 3ad0bab827a5..deda1eebb3b5 100644 --- a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp +++ b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp @@ -635,7 +635,8 @@ static void computeFunctionSummary( HasIndirBranchToBlockAddress || HasIFuncCall; GlobalValueSummary::GVFlags Flags( F.getLinkage(), F.getVisibility(), NotEligibleForImport, - /* Live = */ false, F.isDSOLocal(), F.canBeOmittedFromSymbolTable()); + /* Live = */ false, F.isDSOLocal(), F.canBeOmittedFromSymbolTable(), + GlobalValueSummary::ImportKind::Definition); FunctionSummary::FFlags FunFlags{ F.doesNotAccessMemory(), F.onlyReadsMemory() && !F.doesNotAccessMemory(), F.hasFnAttribute(Attribute::NoRecurse), F.returnDoesNotAlias(), @@ -761,7 +762,8 @@ static void computeVariableSummary(ModuleSummaryIndex &Index, bool NonRenamableLocal = isNonRenamableLocal(V); GlobalValueSummary::GVFlags Flags( V.getLinkage(), V.getVisibility(), NonRenamableLocal, - /* Live = */ false, V.isDSOLocal(), V.canBeOmittedFromSymbolTable()); + /* Live = */ false, V.isDSOLocal(), V.canBeOmittedFromSymbolTable(), + GlobalValueSummary::Definition); VTableFuncList VTableFuncs; // If splitting is not enabled, then we compute the summary information @@ -807,7 +809,8 @@ static void computeAliasSummary(ModuleSummaryIndex &Index, const GlobalAlias &A, bool NonRenamableLocal = isNonRenamableLocal(A); GlobalValueSummary::GVFlags Flags( A.getLinkage(), A.getVisibility(), NonRenamableLocal, - /* Live = */ false, A.isDSOLocal(), A.canBeOmittedFromSymbolTable()); + /* Live = */ false, A.isDSOLocal(), A.canBeOmittedFromSymbolTable(), + GlobalValueSummary::Definition); auto AS = std::make_unique(Flags); auto AliaseeVI = Index.getValueInfo(Aliasee->getGUID()); assert(AliaseeVI && "Alias expects aliasee summary to be available"); @@ -887,7 +890,8 @@ ModuleSummaryIndex llvm::buildModuleSummaryIndex( GlobalValue::InternalLinkage, GlobalValue::DefaultVisibility, /* NotEligibleToImport = */ true, /* Live = */ true, - /* Local */ GV->isDSOLocal(), GV->canBeOmittedFromSymbolTable()); + /* Local */ GV->isDSOLocal(), GV->canBeOmittedFromSymbolTable(), + GlobalValueSummary::Definition); CantBePromoted.insert(GV->getGUID()); // Create the appropriate summary type. if (Function *F = dyn_cast(GV)) { diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index 2301a27731ea..8ded07ffd8bd 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -737,6 +737,9 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(live); KEYWORD(dsoLocal); KEYWORD(canAutoHide); + KEYWORD(importType); + KEYWORD(definition); + KEYWORD(declaration); KEYWORD(function); KEYWORD(insts); KEYWORD(funcFlags); diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index f546e05a5d37..63104129f8c2 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -2083,6 +2083,20 @@ void LLParser::parseOptionalVisibility(unsigned &Res) { Lex.Lex(); } +bool LLParser::parseOptionalImportType(lltok::Kind Kind, + GlobalValueSummary::ImportKind &Res) { + switch (Kind) { + default: + return tokError("unknown import kind. Expect definition or declaration."); + case lltok::kw_definition: + Res = GlobalValueSummary::Definition; + return false; + case lltok::kw_declaration: + Res = GlobalValueSummary::Declaration; + return false; + } +} + /// parseOptionalDLLStorageClass /// ::= /*empty*/ /// ::= 'dllimport' @@ -9230,7 +9244,8 @@ bool LLParser::parseFunctionSummary(std::string Name, GlobalValue::GUID GUID, GlobalValueSummary::GVFlags GVFlags = GlobalValueSummary::GVFlags( GlobalValue::ExternalLinkage, GlobalValue::DefaultVisibility, /*NotEligibleToImport=*/false, - /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false); + /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false, + GlobalValueSummary::Definition); unsigned InstCount; std::vector Calls; FunctionSummary::TypeIdInfo TypeIdInfo; @@ -9317,7 +9332,8 @@ bool LLParser::parseVariableSummary(std::string Name, GlobalValue::GUID GUID, GlobalValueSummary::GVFlags GVFlags = GlobalValueSummary::GVFlags( GlobalValue::ExternalLinkage, GlobalValue::DefaultVisibility, /*NotEligibleToImport=*/false, - /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false); + /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false, + GlobalValueSummary::Definition); GlobalVarSummary::GVarFlags GVarFlags(/*ReadOnly*/ false, /* WriteOnly */ false, /* Constant */ false, @@ -9375,7 +9391,8 @@ bool LLParser::parseAliasSummary(std::string Name, GlobalValue::GUID GUID, GlobalValueSummary::GVFlags GVFlags = GlobalValueSummary::GVFlags( GlobalValue::ExternalLinkage, GlobalValue::DefaultVisibility, /*NotEligibleToImport=*/false, - /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false); + /*Live=*/false, /*IsLocal=*/false, /*CanAutoHide=*/false, + GlobalValueSummary::Definition); if (parseToken(lltok::colon, "expected ':' here") || parseToken(lltok::lparen, "expected '(' here") || parseModuleReference(ModulePath) || @@ -10161,6 +10178,16 @@ bool LLParser::parseGVFlags(GlobalValueSummary::GVFlags &GVFlags) { return true; GVFlags.CanAutoHide = Flag; break; + case lltok::kw_importType: + Lex.Lex(); + if (parseToken(lltok::colon, "expected ':'")) + return true; + GlobalValueSummary::ImportKind IK; + if (parseOptionalImportType(Lex.getKind(), IK)) + return true; + GVFlags.ImportType = static_cast(IK); + Lex.Lex(); + break; default: return error(Lex.getLoc(), "expected gv flag type"); } diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 92c349525aff..fe4f0d6dca6c 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -1141,6 +1141,7 @@ static GlobalValueSummary::GVFlags getDecodedGVSummaryFlags(uint64_t RawFlags, // to getDecodedLinkage() will need to be taken into account here as above. auto Linkage = GlobalValue::LinkageTypes(RawFlags & 0xF); // 4 bits auto Visibility = GlobalValue::VisibilityTypes((RawFlags >> 8) & 3); // 2 bits + auto IK = GlobalValueSummary::ImportKind((RawFlags >> 10) & 1); // 1 bit RawFlags = RawFlags >> 4; bool NotEligibleToImport = (RawFlags & 0x1) || Version < 3; // The Live flag wasn't introduced until version 3. For dead stripping @@ -1151,7 +1152,7 @@ static GlobalValueSummary::GVFlags getDecodedGVSummaryFlags(uint64_t RawFlags, bool AutoHide = (RawFlags & 0x8); return GlobalValueSummary::GVFlags(Linkage, Visibility, NotEligibleToImport, - Live, Local, AutoHide); + Live, Local, AutoHide, IK); } // Decode the flags for GlobalVariable in the summary diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index dd554e422516..6d01e3b4d821 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -1217,6 +1217,8 @@ static uint64_t getEncodedGVSummaryFlags(GlobalValueSummary::GVFlags Flags) { RawFlags |= (Flags.Visibility << 8); // 2 bits + RawFlags |= (Flags.ImportType << 10); // 1 bit + return RawFlags; } diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index b778a14158ef..609de920ba7d 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -3306,6 +3306,16 @@ static const char *getVisibilityName(GlobalValue::VisibilityTypes Vis) { llvm_unreachable("invalid visibility"); } +static const char *getImportTypeName(GlobalValueSummary::ImportKind IK) { + switch (IK) { + case GlobalValueSummary::Definition: + return "definition"; + case GlobalValueSummary::Declaration: + return "declaration"; + } + assert(false && "invalid import kind"); +} + void AssemblyWriter::printFunctionSummary(const FunctionSummary *FS) { Out << ", insts: " << FS->instCount(); if (FS->fflags().anyFlagSet()) @@ -3545,6 +3555,8 @@ void AssemblyWriter::printSummary(const GlobalValueSummary &Summary) { Out << ", live: " << GVFlags.Live; Out << ", dsoLocal: " << GVFlags.DSOLocal; Out << ", canAutoHide: " << GVFlags.CanAutoHide; + Out << ", importType: " + << getImportTypeName(GlobalValueSummary::ImportKind(GVFlags.ImportType)); Out << ")"; if (Summary.getSummaryKind() == GlobalValueSummary::AliasKind) diff --git a/llvm/lib/IR/ModuleSummaryIndex.cpp b/llvm/lib/IR/ModuleSummaryIndex.cpp index 198c730418c7..6713d32fb787 100644 --- a/llvm/lib/IR/ModuleSummaryIndex.cpp +++ b/llvm/lib/IR/ModuleSummaryIndex.cpp @@ -644,6 +644,10 @@ void ModuleSummaryIndex::exportToDot( A.addComment("dsoLocal"); if (Flags.CanAutoHide) A.addComment("canAutoHide"); + if (Flags.ImportType == GlobalValueSummary::ImportKind::Definition) + A.addComment("definition"); + else if (Flags.ImportType == GlobalValueSummary::ImportKind::Declaration) + A.addComment("declaration"); if (GUIDPreservedSymbols.count(SummaryIt.first)) A.addComment("preserved"); diff --git a/llvm/test/Assembler/thinlto-memprof-summary.ll b/llvm/test/Assembler/thinlto-memprof-summary.ll index b72271bb401f..69eafc967c2a 100644 --- a/llvm/test/Assembler/thinlto-memprof-summary.ll +++ b/llvm/test/Assembler/thinlto-memprof-summary.ll @@ -5,20 +5,20 @@ ^0 = module: (path: "thinlto-memprof-summary.o", hash: (1369602428, 2747878711, 259090915, 2507395659, 1141468049)) ;; Function with single alloc, multiple memprof MIBs, no versioning -^1 = gv: (guid: 23, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (none), memProf: ((type: notcold, stackIds: (8632435727821051414)), (type: cold, stackIds: (15025054523792398438, 12345678)), (type: hot, stackIds: (987654321)))))))) +^1 = gv: (guid: 23, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (none), memProf: ((type: notcold, stackIds: (8632435727821051414)), (type: cold, stackIds: (15025054523792398438, 12345678)), (type: hot, stackIds: (987654321)))))))) ;; Function with callsite stack ids calling above function, no versioning -^2 = gv: (guid: 25, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^1)), callsites: ((callee: ^1, clones: (0), stackIds: (8632435727821051414)), (callee: ^1, clones: (0), stackIds: (15025054523792398438, 12345678)), (callee: ^1, clones: (0), stackIds: (23456789)))))) +^2 = gv: (guid: 25, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^1)), callsites: ((callee: ^1, clones: (0), stackIds: (8632435727821051414)), (callee: ^1, clones: (0), stackIds: (15025054523792398438, 12345678)), (callee: ^1, clones: (0), stackIds: (23456789)))))) ;; Function with multiple allocs, multiple memprof MIBs, multiple versions -^3 = gv: (guid: 26, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (cold, notcold), memProf: ((type: notcold, stackIds: (3456789)), (type: cold, stackIds: (456789)))), (versions: (notcold, cold), memProf: ((type: cold, stackIds: (3456789)), (type: notcold, stackIds: (456789)))))))) +^3 = gv: (guid: 26, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (cold, notcold), memProf: ((type: notcold, stackIds: (3456789)), (type: cold, stackIds: (456789)))), (versions: (notcold, cold), memProf: ((type: cold, stackIds: (3456789)), (type: notcold, stackIds: (456789)))))))) ;; Function with callsite stack ids calling above function, multiple versions -^4 = gv: (guid: 27, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^3)), callsites: ((callee: ^3, clones: (0, 1), stackIds: (3456789)), (callee: ^3, clones: (1, 1), stackIds: (456789)))))) +^4 = gv: (guid: 27, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^3)), callsites: ((callee: ^3, clones: (0, 1), stackIds: (3456789)), (callee: ^3, clones: (1, 1), stackIds: (456789)))))) ;; Function with null callsite stack id (can happen in distributed indexes if callsite not imported) -^5 = gv: (guid: 28, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), callsites: ((callee: null, clones: (0), stackIds: (8632435727821051414)))))) +^5 = gv: (guid: 28, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), callsites: ((callee: null, clones: (0), stackIds: (8632435727821051414)))))) ; Make sure we get back from llvm-dis what we put in via llvm-as. ; CHECK: ^0 = module: (path: "thinlto-memprof-summary.o", hash: (1369602428, 2747878711, 259090915, 2507395659, 1141468049)) -; CHECK: ^1 = gv: (guid: 23, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (none), memProf: ((type: notcold, stackIds: (8632435727821051414)), (type: cold, stackIds: (15025054523792398438, 12345678)), (type: hot, stackIds: (987654321)))))))) -; CHECK: ^2 = gv: (guid: 25, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^1)), callsites: ((callee: ^1, clones: (0), stackIds: (8632435727821051414)), (callee: ^1, clones: (0), stackIds: (15025054523792398438, 12345678)), (callee: ^1, clones: (0), stackIds: (23456789)))))) -; CHECK: ^3 = gv: (guid: 26, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (cold, notcold), memProf: ((type: notcold, stackIds: (3456789)), (type: cold, stackIds: (456789)))), (versions: (notcold, cold), memProf: ((type: cold, stackIds: (3456789)), (type: notcold, stackIds: (456789)))))))) -; CHECK: ^4 = gv: (guid: 27, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^3)), callsites: ((callee: ^3, clones: (0, 1), stackIds: (3456789)), (callee: ^3, clones: (1, 1), stackIds: (456789)))))) -; CHECK: ^5 = gv: (guid: 28, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), callsites: ((callee: null, clones: (0), stackIds: (8632435727821051414)))))) +; CHECK: ^1 = gv: (guid: 23, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (none), memProf: ((type: notcold, stackIds: (8632435727821051414)), (type: cold, stackIds: (15025054523792398438, 12345678)), (type: hot, stackIds: (987654321)))))))) +; CHECK: ^2 = gv: (guid: 25, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^1)), callsites: ((callee: ^1, clones: (0), stackIds: (8632435727821051414)), (callee: ^1, clones: (0), stackIds: (15025054523792398438, 12345678)), (callee: ^1, clones: (0), stackIds: (23456789)))))) +; CHECK: ^3 = gv: (guid: 26, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 2, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), allocs: ((versions: (cold, notcold), memProf: ((type: notcold, stackIds: (3456789)), (type: cold, stackIds: (456789)))), (versions: (notcold, cold), memProf: ((type: cold, stackIds: (3456789)), (type: notcold, stackIds: (456789)))))))) +; CHECK: ^4 = gv: (guid: 27, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^3)), callsites: ((callee: ^3, clones: (0, 1), stackIds: (3456789)), (callee: ^3, clones: (1, 1), stackIds: (456789)))))) +; CHECK: ^5 = gv: (guid: 28, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 22, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0), callsites: ((callee: null, clones: (0), stackIds: (8632435727821051414)))))) diff --git a/llvm/test/Assembler/thinlto-multiple-summaries-for-guid.ll b/llvm/test/Assembler/thinlto-multiple-summaries-for-guid.ll index 4f849fa6e6ad..117280a279d0 100644 --- a/llvm/test/Assembler/thinlto-multiple-summaries-for-guid.ll +++ b/llvm/test/Assembler/thinlto-multiple-summaries-for-guid.ll @@ -8,5 +8,5 @@ source_filename = "index.bc" ; CHECK: ^0 = module: (path: "[Regular LTO]", hash: (0, 0, 0, 0, 0)) ^1 = module: (path: "main.bc", hash: (3499594384, 1671013073, 3271036935, 1830411232, 59290952)) ; CHECK-NEXT: ^1 = module: (path: "main.bc", hash: (3499594384, 1671013073, 3271036935, 1830411232, 59290952)) -^2 = gv: (guid: 13351721993301222997, summaries: (function: (module: ^1, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 1), insts: 1), function: (module: ^1, flags: (linkage: available_externally, notEligibleToImport: 1, live: 1, dsoLocal: 1, canAutoHide: 0), insts: 1))) -; CHECK-NEXT: ^2 = gv: (guid: 13351721993301222997, summaries: (function: (module: ^1, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 1), insts: 1), function: (module: ^1, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 1, live: 1, dsoLocal: 1, canAutoHide: 0), insts: 1))) +^2 = gv: (guid: 13351721993301222997, summaries: (function: (module: ^1, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 1), function: (module: ^1, flags: (linkage: available_externally, notEligibleToImport: 1, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 1))) +; CHECK-NEXT: ^2 = gv: (guid: 13351721993301222997, summaries: (function: (module: ^1, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 1), function: (module: ^1, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 1, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 1))) diff --git a/llvm/test/Assembler/thinlto-summary-visibility.ll b/llvm/test/Assembler/thinlto-summary-visibility.ll index 77f652a9e97d..67ddcb961d7a 100644 --- a/llvm/test/Assembler/thinlto-summary-visibility.ll +++ b/llvm/test/Assembler/thinlto-summary-visibility.ll @@ -4,9 +4,9 @@ ^0 = module: (path: "thinlto-summary-visibility1.o", hash: (1369602428, 2747878711, 259090915, 2507395659, 1141468049)) ^1 = module: (path: "thinlto-summary-visibility2.o", hash: (2998369023, 4283347029, 1195487472, 2757298015, 1852134156)) -; CHECK: ^2 = gv: (guid: 2, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10))) -; CHECK-NEXT: ^3 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: external, visibility: protected, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10))) -; CHECK-NEXT: ^4 = gv: (guid: 4, summaries: (function: (module: ^0, flags: (linkage: external, visibility: hidden, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10))) +; CHECK: ^2 = gv: (guid: 2, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 10))) +; CHECK-NEXT: ^3 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: external, visibility: protected, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 10))) +; CHECK-NEXT: ^4 = gv: (guid: 4, summaries: (function: (module: ^0, flags: (linkage: external, visibility: hidden, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 10))) ^2 = gv: (guid: 2, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default), insts: 10))) ^3 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: external, visibility: protected), insts: 10))) diff --git a/llvm/test/Assembler/thinlto-summary.ll b/llvm/test/Assembler/thinlto-summary.ll index 9eb3c6669780..05dad2c7acad 100644 --- a/llvm/test/Assembler/thinlto-summary.ll +++ b/llvm/test/Assembler/thinlto-summary.ll @@ -16,13 +16,13 @@ ^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 10, calls: ((callee: ^15, relbf: 256, tail: 1))))) ; Summaries with different linkage types. -^4 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1), insts: 1))) +^4 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, importType: definition), insts: 1))) ; Make this one an alias with a forward reference to aliasee. -^5 = gv: (guid: 4, summaries: (alias: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1), aliasee: ^14))) +^5 = gv: (guid: 4, summaries: (alias: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, importType: definition), aliasee: ^14))) ^6 = gv: (guid: 5, summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 1))) ^7 = gv: (guid: 6, summaries: (function: (module: ^0, flags: (linkage: linkonce, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 1))) ^8 = gv: (guid: 7, summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 1))) -^9 = gv: (guid: 8, summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 1), insts: 1))) +^9 = gv: (guid: 8, summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 1, importType: definition), insts: 1))) ^10 = gv: (guid: 9, summaries: (function: (module: ^0, flags: (linkage: weak, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 1))) ^11 = gv: (guid: 10, summaries: (variable: (module: ^0, flags: (linkage: common, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), varFlags: (readonly: 0)))) ; Test appending globel variable with reference (tests backward reference on @@ -46,60 +46,64 @@ ^18 = gv: (guid: 17, summaries: (alias: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1), aliasee: ^14))) ; Test all types of TypeIdInfo on function summaries. -^19 = gv: (guid: 18, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 4, typeIdInfo: (typeTests: (^24, ^26))))) -^20 = gv: (guid: 19, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 8, typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (^27, offset: 16)))))) -^21 = gv: (guid: 20, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 5, typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (^25, offset: 16)))))) -^22 = gv: (guid: 21, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 15, typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (^27, offset: 16), args: (42)), (vFuncId: (^27, offset: 24))))))) -^23 = gv: (guid: 22, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 5, typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (^28, offset: 16), args: (42))))))) +^19 = gv: (guid: 18, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 4, typeIdInfo: (typeTests: (^25, ^27))))) +^20 = gv: (guid: 19, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 8, typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (^28, offset: 16)))))) +^21 = gv: (guid: 20, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 5, typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (^26, offset: 16)))))) +^22 = gv: (guid: 21, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 15, typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (^28, offset: 16), args: (42)), (vFuncId: (^28, offset: 24))))))) +^23 = gv: (guid: 22, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0), insts: 5, typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (^29, offset: 16), args: (42))))))) + +; Function summary with an import type of declaration +^24 = gv: (guid: 23, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, importType: declaration), insts: 5))) ; Test TypeId summaries: -^24 = typeid: (name: "_ZTS1C", summary: (typeTestRes: (kind: single, sizeM1BitWidth: 0))) +^25 = typeid: (name: "_ZTS1C", summary: (typeTestRes: (kind: single, sizeM1BitWidth: 0))) ; Test TypeId with other optional fields (alignLog2/sizeM1/bitMask/inlineBits) -^25 = typeid: (name: "_ZTS1B", summary: (typeTestRes: (kind: inline, sizeM1BitWidth: 0, alignLog2: 1, sizeM1: 2, bitMask: 3, inlineBits: 4))) +^26 = typeid: (name: "_ZTS1B", summary: (typeTestRes: (kind: inline, sizeM1BitWidth: 0, alignLog2: 1, sizeM1: 2, bitMask: 3, inlineBits: 4))) ; Test the AllOnes resolution, and all kinds of WholeProgramDevirtResolution ; types, including all optional resolution by argument kinds. -^26 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: allOnes, sizeM1BitWidth: 7), wpdResolutions: ((offset: 0, wpdRes: (kind: branchFunnel)), (offset: 8, wpdRes: (kind: singleImpl, singleImplName: "_ZN1A1nEi")), (offset: 16, wpdRes: (kind: indir, resByArg: (args: (1, 2), byArg: (kind: indir, byte: 2, bit: 3), args: (3), byArg: (kind: uniformRetVal, info: 1), args: (4), byArg: (kind: uniqueRetVal, info: 1), args: (5), byArg: (kind: virtualConstProp))))))) +^27 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: allOnes, sizeM1BitWidth: 7), wpdResolutions: ((offset: 0, wpdRes: (kind: branchFunnel)), (offset: 8, wpdRes: (kind: singleImpl, singleImplName: "_ZN1A1nEi")), (offset: 16, wpdRes: (kind: indir, resByArg: (args: (1, 2), byArg: (kind: indir, byte: 2, bit: 3), args: (3), byArg: (kind: uniformRetVal, info: 1), args: (4), byArg: (kind: uniqueRetVal, info: 1), args: (5), byArg: (kind: virtualConstProp))))))) ; Test the other kinds of type test resoultions -^27 = typeid: (name: "_ZTS1D", summary: (typeTestRes: (kind: byteArray, sizeM1BitWidth: 0))) -^28 = typeid: (name: "_ZTS1E", summary: (typeTestRes: (kind: unsat, sizeM1BitWidth: 0))) -^29 = flags: 8 -^30 = blockcount: 1888 +^28 = typeid: (name: "_ZTS1D", summary: (typeTestRes: (kind: byteArray, sizeM1BitWidth: 0))) +^29 = typeid: (name: "_ZTS1E", summary: (typeTestRes: (kind: unsat, sizeM1BitWidth: 0))) +^30 = flags: 8 +^31 = blockcount: 1888 ; Make sure we get back from llvm-dis essentially what we put in via llvm-as. ; CHECK: ^0 = module: (path: "thinlto-summary1.o", hash: (1369602428, 2747878711, 259090915, 2507395659, 1141468049)) ; CHECK: ^1 = module: (path: "thinlto-summary2.o", hash: (2998369023, 4283347029, 1195487472, 2757298015, 1852134156)) -; CHECK: ^2 = gv: (guid: 1, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10, calls: ((callee: ^15, hotness: hot), (callee: ^17, hotness: cold), (callee: ^16, hotness: none, tail: 1)), refs: (^11, readonly ^13, writeonly ^14)))) +; CHECK: ^2 = gv: (guid: 1, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 10, calls: ((callee: ^15, hotness: hot), (callee: ^17, hotness: cold), (callee: ^16, hotness: none, tail: 1)), refs: (^11, readonly ^13, writeonly ^14)))) ;; relbf is not emitted since this is a combined summary, and that is only ;; emitted for per-module summaries. -; CHECK: ^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 10, calls: ((callee: ^15, tail: 1))))) -; CHECK: ^4 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 1))) -; CHECK: ^5 = gv: (guid: 4, summaries: (alias: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), aliasee: ^14))) -; CHECK: ^6 = gv: (guid: 5, summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; CHECK: ^7 = gv: (guid: 6, summaries: (function: (module: ^0, flags: (linkage: linkonce, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; CHECK: ^8 = gv: (guid: 7, summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; CHECK: ^9 = gv: (guid: 8, summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 1), insts: 1))) -; CHECK: ^10 = gv: (guid: 9, summaries: (function: (module: ^0, flags: (linkage: weak, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; CHECK: ^11 = gv: (guid: 10, summaries: (variable: (module: ^0, flags: (linkage: common, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) -; CHECK: ^12 = gv: (guid: 11, summaries: (variable: (module: ^0, flags: (linkage: appending, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0), refs: (^4)))) -; CHECK: ^13 = gv: (guid: 12, summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 1, writeonly: 0, constant: 0)))) -; CHECK: ^14 = gv: (guid: 13, summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) -; CHECK: ^15 = gv: (guid: 14, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 1, live: 1, dsoLocal: 0, canAutoHide: 0), insts: 1, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) -; CHECK: ^16 = gv: (guid: 15, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1, funcFlags: (readNone: 1, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 1, noUnwind: 1, mayThrow: 1, hasUnknownCall: 1, mustBeUnreachable: 0)))) -; CHECK: ^17 = gv: (guid: 16, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1, funcFlags: (readNone: 0, readOnly: 1, noRecurse: 0, returnDoesNotAlias: 1, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 1), calls: ((callee: ^15))))) -; CHECK: ^18 = gv: (guid: 17, summaries: (alias: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), aliasee: ^14))) -; CHECK: ^19 = gv: (guid: 18, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 4, typeIdInfo: (typeTests: (^24, ^26))))) -; CHECK: ^20 = gv: (guid: 19, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 8, typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (^27, offset: 16)))))) -; CHECK: ^21 = gv: (guid: 20, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (^25, offset: 16)))))) -; CHECK: ^22 = gv: (guid: 21, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 15, typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (^27, offset: 16), args: (42)), (vFuncId: (^27, offset: 24))))))) -; CHECK: ^23 = gv: (guid: 22, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (^28, offset: 16), args: (42))))))) -; CHECK: ^24 = typeid: (name: "_ZTS1C", summary: (typeTestRes: (kind: single, sizeM1BitWidth: 0))) ; guid = 1884921850105019584 -; CHECK: ^25 = typeid: (name: "_ZTS1B", summary: (typeTestRes: (kind: inline, sizeM1BitWidth: 0, alignLog2: 1, sizeM1: 2, bitMask: 3, inlineBits: 4))) ; guid = 6203814149063363976 -; CHECK: ^26 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: allOnes, sizeM1BitWidth: 7), wpdResolutions: ((offset: 0, wpdRes: (kind: branchFunnel)), (offset: 8, wpdRes: (kind: singleImpl, singleImplName: "_ZN1A1nEi")), (offset: 16, wpdRes: (kind: indir, resByArg: (args: (1, 2), byArg: (kind: indir, byte: 2, bit: 3), args: (3), byArg: (kind: uniformRetVal, info: 1), args: (4), byArg: (kind: uniqueRetVal, info: 1), args: (5), byArg: (kind: virtualConstProp))))))) ; guid = 7004155349499253778 -; CHECK: ^27 = typeid: (name: "_ZTS1D", summary: (typeTestRes: (kind: byteArray, sizeM1BitWidth: 0))) ; guid = 9614786172484273522 -; CHECK: ^28 = typeid: (name: "_ZTS1E", summary: (typeTestRes: (kind: unsat, sizeM1BitWidth: 0))) ; guid = 17437243864166745132 -; CHECK: ^29 = flags: 8 -; CHECK: ^30 = blockcount: 1888 +; CHECK: ^3 = gv: (guid: 2, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 10, calls: ((callee: ^15, tail: 1))))) +; CHECK: ^4 = gv: (guid: 3, summaries: (function: (module: ^0, flags: (linkage: internal, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 1))) +; CHECK: ^5 = gv: (guid: 4, summaries: (alias: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), aliasee: ^14))) +; CHECK: ^6 = gv: (guid: 5, summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; CHECK: ^7 = gv: (guid: 6, summaries: (function: (module: ^0, flags: (linkage: linkonce, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; CHECK: ^8 = gv: (guid: 7, summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; CHECK: ^9 = gv: (guid: 8, summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 1, importType: definition), insts: 1))) +; CHECK: ^10 = gv: (guid: 9, summaries: (function: (module: ^0, flags: (linkage: weak, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; CHECK: ^11 = gv: (guid: 10, summaries: (variable: (module: ^0, flags: (linkage: common, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) +; CHECK: ^12 = gv: (guid: 11, summaries: (variable: (module: ^0, flags: (linkage: appending, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0), refs: (^4)))) +; CHECK: ^13 = gv: (guid: 12, summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 1, writeonly: 0, constant: 0)))) +; CHECK: ^14 = gv: (guid: 13, summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0)))) +; CHECK: ^15 = gv: (guid: 14, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 1, live: 1, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 1, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) +; CHECK: ^16 = gv: (guid: 15, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1, funcFlags: (readNone: 1, readOnly: 0, noRecurse: 1, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 1, noUnwind: 1, mayThrow: 1, hasUnknownCall: 1, mustBeUnreachable: 0)))) +; CHECK: ^17 = gv: (guid: 16, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1, funcFlags: (readNone: 0, readOnly: 1, noRecurse: 0, returnDoesNotAlias: 1, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 1), calls: ((callee: ^15))))) +; CHECK: ^18 = gv: (guid: 17, summaries: (alias: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), aliasee: ^14))) +; CHECK: ^19 = gv: (guid: 18, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 4, typeIdInfo: (typeTests: (^25, ^27))))) +; CHECK: ^20 = gv: (guid: 19, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 8, typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (^28, offset: 16)))))) +; CHECK: ^21 = gv: (guid: 20, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (^26, offset: 16)))))) +; CHECK: ^22 = gv: (guid: 21, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 15, typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (^28, offset: 16), args: (42)), (vFuncId: (^28, offset: 24))))))) +; CHECK: ^23 = gv: (guid: 22, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (^29, offset: 16), args: (42))))))) +; CHECK: ^24 = gv: (guid: 23, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: declaration), insts: 5))) +; CHECK: ^25 = typeid: (name: "_ZTS1C", summary: (typeTestRes: (kind: single, sizeM1BitWidth: 0))) ; guid = 1884921850105019584 +; CHECK: ^26 = typeid: (name: "_ZTS1B", summary: (typeTestRes: (kind: inline, sizeM1BitWidth: 0, alignLog2: 1, sizeM1: 2, bitMask: 3, inlineBits: 4))) ; guid = 6203814149063363976 +; CHECK: ^27 = typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: allOnes, sizeM1BitWidth: 7), wpdResolutions: ((offset: 0, wpdRes: (kind: branchFunnel)), (offset: 8, wpdRes: (kind: singleImpl, singleImplName: "_ZN1A1nEi")), (offset: 16, wpdRes: (kind: indir, resByArg: (args: (1, 2), byArg: (kind: indir, byte: 2, bit: 3), args: (3), byArg: (kind: uniformRetVal, info: 1), args: (4), byArg: (kind: uniqueRetVal, info: 1), args: (5), byArg: (kind: virtualConstProp))))))) ; guid = 7004155349499253778 +; CHECK: ^28 = typeid: (name: "_ZTS1D", summary: (typeTestRes: (kind: byteArray, sizeM1BitWidth: 0))) ; guid = 9614786172484273522 +; CHECK: ^29 = typeid: (name: "_ZTS1E", summary: (typeTestRes: (kind: unsat, sizeM1BitWidth: 0))) ; guid = 17437243864166745132 +; CHECK: ^30 = flags: 8 +; CHECK: ^31 = blockcount: 1888 ; Make sure parsing of a non-summary entry containing a ":" does not fail ; after summary parsing, which handles colons differently. diff --git a/llvm/test/Assembler/thinlto-vtable-summary.ll b/llvm/test/Assembler/thinlto-vtable-summary.ll index 5a0ff32a8390..80720287f7a0 100644 --- a/llvm/test/Assembler/thinlto-vtable-summary.ll +++ b/llvm/test/Assembler/thinlto-vtable-summary.ll @@ -29,9 +29,9 @@ declare i32 @_ZN1C1fEi(ptr, i32) ^0 = module: (path: "", hash: (0, 0, 0, 0, 0)) ^1 = gv: (name: "_ZN1A1nEi") ; guid = 1621563287929432257 -^2 = gv: (name: "_ZTV1B", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0, vcall_visibility: 0), vTableFuncs: ((virtFunc: ^3, offset: 16), (virtFunc: ^1, offset: 24)), refs: (^3, ^1)))) ; guid = 5283576821522790367 +^2 = gv: (name: "_ZTV1B", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0, vcall_visibility: 0), vTableFuncs: ((virtFunc: ^3, offset: 16), (virtFunc: ^1, offset: 24)), refs: (^3, ^1)))) ; guid = 5283576821522790367 ^3 = gv: (name: "_ZN1B1fEi") ; guid = 7162046368816414394 -^4 = gv: (name: "_ZTV1C", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 0, writeonly: 0, constant: 0, vcall_visibility: 0), vTableFuncs: ((virtFunc: ^5, offset: 16), (virtFunc: ^1, offset: 24)), refs: (^1, ^5)))) ; guid = 13624023785555846296 +^4 = gv: (name: "_ZTV1C", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 0, writeonly: 0, constant: 0, vcall_visibility: 0), vTableFuncs: ((virtFunc: ^5, offset: 16), (virtFunc: ^1, offset: 24)), refs: (^1, ^5)))) ; guid = 13624023785555846296 ^5 = gv: (name: "_ZN1C1fEi") ; guid = 14876272565662207556 ^6 = typeidCompatibleVTable: (name: "_ZTS1A", summary: ((offset: 16, ^2), (offset: 16, ^4))) ; guid = 7004155349499253778 ^7 = typeidCompatibleVTable: (name: "_ZTS1B", summary: ((offset: 16, ^2))) ; guid = 6203814149063363976 diff --git a/llvm/test/Bitcode/thinlto-alias.ll b/llvm/test/Bitcode/thinlto-alias.ll index eb794f4e631d..5dfff0f79619 100644 --- a/llvm/test/Bitcode/thinlto-alias.ll +++ b/llvm/test/Bitcode/thinlto-alias.ll @@ -53,11 +53,11 @@ entry: declare void @analias(...) ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) -; DIS: ^1 = gv: (name: "analias", summaries: (alias: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), aliasee: ^2))) ; guid = 12695095382722328222 -; DIS: ^2 = gv: (name: "aliasee", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) ; guid = 17407585008595848568 +; DIS: ^1 = gv: (name: "analias", summaries: (alias: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), aliasee: ^2))) ; guid = 12695095382722328222 +; DIS: ^2 = gv: (name: "aliasee", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) ; guid = 17407585008595848568 ; COMBINED-DIS: ^0 = module: (path: "{{.*}}thinlto-alias.ll.tmp.o", hash: (0, 0, 0, 0, 0)) ; COMBINED-DIS: ^1 = module: (path: "{{.*}}thinlto-alias.ll.tmp2.o", hash: (0, 0, 0, 0, 0)) -; COMBINED-DIS: ^2 = gv: (guid: 12695095382722328222, summaries: (alias: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), aliasee: ^4))) -; COMBINED-DIS: ^3 = gv: (guid: 15822663052811949562, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^2))))) -; COMBINED-DIS: ^4 = gv: (guid: 17407585008595848568, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) +; COMBINED-DIS: ^2 = gv: (guid: 12695095382722328222, summaries: (alias: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), aliasee: ^4))) +; COMBINED-DIS: ^3 = gv: (guid: 15822663052811949562, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, calls: ((callee: ^2))))) +; COMBINED-DIS: ^4 = gv: (guid: 17407585008595848568, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) diff --git a/llvm/test/Bitcode/thinlto-func-summary-vtableref-pgo.ll b/llvm/test/Bitcode/thinlto-func-summary-vtableref-pgo.ll index ba3ce9a75ee8..19e228fd5355 100644 --- a/llvm/test/Bitcode/thinlto-func-summary-vtableref-pgo.ll +++ b/llvm/test/Bitcode/thinlto-func-summary-vtableref-pgo.ll @@ -70,5 +70,5 @@ define i32 @_Z4testP4Base(ptr %0) !prof !15 { ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) ; DIS: ^1 = gv: (guid: 1960855528937986108) ; DIS: ^2 = gv: (guid: 5459407273543877811) -; DIS: ^3 = gv: (name: "_Z4testP4Base", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 4, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), calls: ((callee: ^2, hotness: hot)), refs: (readonly ^1)))) ; guid = 15857150948103218965 +; DIS: ^3 = gv: (name: "_Z4testP4Base", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 4, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), calls: ((callee: ^2, hotness: hot)), refs: (readonly ^1)))) ; guid = 15857150948103218965 ; DIS: ^4 = blockcount: 0 diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll index d7679b6f5af2..563fb18107d3 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph-profile-summary.ll @@ -150,16 +150,16 @@ declare void @none3() #1 ; DIS: ^6 = gv: (name: "cold") ; guid = 11668175513417606517 ; DIS: ^7 = gv: (name: "hot4") ; guid = 13161834114071272798 ; DIS: ^8 = gv: (name: "none3") ; guid = 16213681105727317812 -; DIS: ^9 = gv: (name: "hot_function", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 16, calls: ((callee: ^5, hotness: hot), (callee: ^6, hotness: cold), (callee: ^4, hotness: hot), (callee: ^7, hotness: cold), (callee: ^10, hotness: none), (callee: ^3, hotness: hot), (callee: ^2, hotness: none), (callee: ^8, hotness: none), (callee: ^1, hotness: critical))))) ; guid = 17381606045411660303 +; DIS: ^9 = gv: (name: "hot_function", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 16, calls: ((callee: ^5, hotness: hot), (callee: ^6, hotness: cold), (callee: ^4, hotness: hot), (callee: ^7, hotness: cold), (callee: ^10, hotness: none), (callee: ^3, hotness: hot), (callee: ^2, hotness: none), (callee: ^8, hotness: none), (callee: ^1, hotness: critical))))) ; guid = 17381606045411660303 ; DIS: ^10 = gv: (name: "none1") ; guid = 17712061229457633252 ; COMBINED-DIS: ^0 = module: (path: "{{.*}}thinlto-function-summary-callgraph-profile-summary.ll.tmp.o", hash: (0, 0, 0, 0, 0)) ; COMBINED-DIS: ^1 = module: (path: "{{.*}}thinlto-function-summary-callgraph-profile-summary.ll.tmp2.o", hash: (0, 0, 0, 0, 0)) -; COMBINED-DIS: ^2 = gv: (guid: 3741006263754194003, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; COMBINED-DIS: ^3 = gv: (guid: 5026609803865204483, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; COMBINED-DIS: ^4 = gv: (guid: 8117347573235780485, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; COMBINED-DIS: ^5 = gv: (guid: 9453975128311291976, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; COMBINED-DIS: ^6 = gv: (guid: 11668175513417606517, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; COMBINED-DIS: ^7 = gv: (guid: 16213681105727317812, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) -; COMBINED-DIS: ^8 = gv: (guid: 17381606045411660303, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 16, calls: ((callee: ^5, hotness: hot), (callee: ^6, hotness: cold), (callee: ^4, hotness: hot), (callee: ^9, hotness: none), (callee: ^3, hotness: hot), (callee: ^2, hotness: none), (callee: ^7, hotness: none))))) -; COMBINED-DIS: ^9 = gv: (guid: 17712061229457633252, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 1))) +; COMBINED-DIS: ^2 = gv: (guid: 3741006263754194003, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; COMBINED-DIS: ^3 = gv: (guid: 5026609803865204483, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; COMBINED-DIS: ^4 = gv: (guid: 8117347573235780485, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; COMBINED-DIS: ^5 = gv: (guid: 9453975128311291976, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; COMBINED-DIS: ^6 = gv: (guid: 11668175513417606517, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; COMBINED-DIS: ^7 = gv: (guid: 16213681105727317812, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) +; COMBINED-DIS: ^8 = gv: (guid: 17381606045411660303, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 16, calls: ((callee: ^5, hotness: hot), (callee: ^6, hotness: cold), (callee: ^4, hotness: hot), (callee: ^9, hotness: none), (callee: ^3, hotness: hot), (callee: ^2, hotness: none), (callee: ^7, hotness: none))))) +; COMBINED-DIS: ^9 = gv: (guid: 17712061229457633252, summaries: (function: (module: ^1, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 1))) diff --git a/llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll b/llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll index ca4f62907cb0..3c827247a6c9 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-callgraph-relbf.ll @@ -39,5 +39,5 @@ declare void @func(...) #1 ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) ; DIS: ^1 = gv: (name: "func") ; guid = 7289175272376759421 -; DIS: ^2 = gv: (name: "main", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 3, calls: ((callee: ^1, relbf: 256)), refs: (readonly ^3)))) ; guid = 15822663052811949562 +; DIS: ^2 = gv: (name: "main", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 3, calls: ((callee: ^1, relbf: 256)), refs: (readonly ^3)))) ; guid = 15822663052811949562 ; DIS: ^3 = gv: (name: "undefinedglob") ; guid = 18036901804029949403 diff --git a/llvm/test/Bitcode/thinlto-function-summary-refgraph.ll b/llvm/test/Bitcode/thinlto-function-summary-refgraph.ll index fc42b5369644..c76d70b8c4cc 100644 --- a/llvm/test/Bitcode/thinlto-function-summary-refgraph.ll +++ b/llvm/test/Bitcode/thinlto-function-summary-refgraph.ll @@ -148,18 +148,18 @@ entry: ; order, which depends on GUID, and the private function Y GUID will depend ; on the path to the test. ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) -; DIS-DAG: = gv: (name: "Z", summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}}, tail: 1))))) ; guid = 104084381700047393 -; DIS-DAG: = gv: (name: "X", summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ; guid = 1881667236089500162 -; DIS-DAG: = gv: (name: "W", summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, calls: ((callee: ^{{.*}}, tail: 1)), refs: (^{{.*}})))) ; guid = 5790125716599269729 +; DIS-DAG: = gv: (name: "Z", summaries: (function: (module: ^0, flags: (linkage: linkonce_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, calls: ((callee: ^{{.*}}, tail: 1))))) ; guid = 104084381700047393 +; DIS-DAG: = gv: (name: "X", summaries: (function: (module: ^0, flags: (linkage: available_externally, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ; guid = 1881667236089500162 +; DIS-DAG: = gv: (name: "W", summaries: (function: (module: ^0, flags: (linkage: weak_odr, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, calls: ((callee: ^{{.*}}, tail: 1)), refs: (^{{.*}})))) ; guid = 5790125716599269729 ; DIS-DAG: = gv: (name: "foo") ; guid = 6699318081062747564 ; DIS-DAG: = gv: (name: "func") ; guid = 7289175272376759421 ; DIS-DAG: = gv: (name: "func3") ; guid = 11517462787082255043 ; Check that default value of writeonly attribute is zero for constant variables -; DIS-DAG: = gv: (name: "globalvar", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 1, writeonly: 0, constant: 1)))) ; guid = 12887606300320728018 +; DIS-DAG: = gv: (name: "globalvar", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 1, writeonly: 0, constant: 1)))) ; guid = 12887606300320728018 ; DIS-DAG: = gv: (name: "func2") ; guid = 14069196320850861797 ; DIS-DAG: = gv: (name: "llvm.ctpop.i8") ; guid = 15254915475081819833 -; DIS-DAG: = gv: (name: "main", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 9, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ; guid = 15822663052811949562 -; DIS-DAG: = gv: (name: "bar", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), varFlags: (readonly: 1, writeonly: 1, constant: 0), refs: (^{{.*}})))) ; guid = 16434608426314478903 +; DIS-DAG: = gv: (name: "main", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 9, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ; guid = 15822663052811949562 +; DIS-DAG: = gv: (name: "bar", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), varFlags: (readonly: 1, writeonly: 1, constant: 0), refs: (^{{.*}})))) ; guid = 16434608426314478903 ; Don't try to match the exact GUID. Since it is private, the file path ; will get hashed, and that will be test dependent. -; DIS-DAG: = gv: (name: "Y", summaries: (function: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 14, calls: ((callee: ^{{.*}}, tail: 1))))) ; guid = +; DIS-DAG: = gv: (name: "Y", summaries: (function: (module: ^0, flags: (linkage: private, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 14, calls: ((callee: ^{{.*}}, tail: 1))))) ; guid = diff --git a/llvm/test/Bitcode/thinlto-index-disassembled-by-llvm-dis.ll b/llvm/test/Bitcode/thinlto-index-disassembled-by-llvm-dis.ll index 0d6a8e3b4b8d..3a121c2d5d42 100644 --- a/llvm/test/Bitcode/thinlto-index-disassembled-by-llvm-dis.ll +++ b/llvm/test/Bitcode/thinlto-index-disassembled-by-llvm-dis.ll @@ -18,7 +18,7 @@ ; RUN: llvm-dis --print-thinlto-index-only %t.o -o - | FileCheck %s --check-prefix=DIS ; DIS: ^0 = module: (path: "{{.*}}thinlto-index-disassembled-by-llvm-dis.ll.tmp -; DIS: ^1 = gv: (name: "aplusb", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2))) ; guid = +; DIS: ^1 = gv: (name: "aplusb", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2))) ; guid = source_filename = "add.cpp" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/Bitcode/thinlto-type-tests.ll b/llvm/test/Bitcode/thinlto-type-tests.ll index 76021a87c52c..6dc49b849c2f 100644 --- a/llvm/test/Bitcode/thinlto-type-tests.ll +++ b/llvm/test/Bitcode/thinlto-type-tests.ll @@ -37,11 +37,11 @@ declare i1 @llvm.type.test(i8*, metadata) nounwind readnone ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) ; DIS: ^1 = gv: (name: "llvm.type.test") ; guid = 608142985856744218 -; DIS: ^2 = gv: (name: "h", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, typeIdInfo: (typeTests: (16434608426314478903))))) ; guid = 8124147457056772133 -; DIS: ^3 = gv: (name: "g", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 4, typeIdInfo: (typeTests: (6699318081062747564, 16434608426314478903))))) ; guid = 13146401226427987378 -; DIS: ^4 = gv: (name: "f", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, typeIdInfo: (typeTests: (6699318081062747564))))) ; guid = 14740650423002898831 +; DIS: ^2 = gv: (name: "h", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, typeIdInfo: (typeTests: (16434608426314478903))))) ; guid = 8124147457056772133 +; DIS: ^3 = gv: (name: "g", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 4, typeIdInfo: (typeTests: (6699318081062747564, 16434608426314478903))))) ; guid = 13146401226427987378 +; DIS: ^4 = gv: (name: "f", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, typeIdInfo: (typeTests: (6699318081062747564))))) ; guid = 14740650423002898831 ; COMBINED-DIS: ^0 = module: (path: "{{.*}}thinlto-type-tests.ll.tmp.o", hash: (0, 0, 0, 0, 0)) -; COMBINED-DIS: ^1 = gv: (guid: 8124147457056772133, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, typeIdInfo: (typeTests: (16434608426314478903))))) -; COMBINED-DIS: ^2 = gv: (guid: 13146401226427987378, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 4, typeIdInfo: (typeTests: (6699318081062747564, 16434608426314478903))))) -; COMBINED-DIS: ^3 = gv: (guid: 14740650423002898831, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, typeIdInfo: (typeTests: (6699318081062747564))))) +; COMBINED-DIS: ^1 = gv: (guid: 8124147457056772133, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, typeIdInfo: (typeTests: (16434608426314478903))))) +; COMBINED-DIS: ^2 = gv: (guid: 13146401226427987378, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 4, typeIdInfo: (typeTests: (6699318081062747564, 16434608426314478903))))) +; COMBINED-DIS: ^3 = gv: (guid: 14740650423002898831, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, typeIdInfo: (typeTests: (6699318081062747564))))) diff --git a/llvm/test/Bitcode/thinlto-type-vcalls.ll b/llvm/test/Bitcode/thinlto-type-vcalls.ll index ede5b483bfeb..16c93097101d 100644 --- a/llvm/test/Bitcode/thinlto-type-vcalls.ll +++ b/llvm/test/Bitcode/thinlto-type-vcalls.ll @@ -112,19 +112,19 @@ declare {i8*, i1} @llvm.type.checked.load(i8*, i32, metadata) ; DIS: ^0 = module: (path: "{{.*}}", hash: (0, 0, 0, 0, 0)) ; DIS: ^1 = gv: (name: "llvm.type.test") ; guid = 608142985856744218 -; DIS: ^2 = gv: (name: "f1", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 8, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) ; guid = 2072045998141807037 -; DIS: ^3 = gv: (name: "f3", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) ; guid = 4197650231481825559 +; DIS: ^2 = gv: (name: "f1", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 8, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) ; guid = 2072045998141807037 +; DIS: ^3 = gv: (name: "f3", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) ; guid = 4197650231481825559 ; DIS: ^4 = gv: (name: "llvm.type.checked.load") ; guid = 5568222536364573403 ; DIS: ^5 = gv: (name: "llvm.assume") ; guid = 6385187066495850096 -; DIS: ^6 = gv: (name: "f2", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 24), vFuncId: (guid: 16434608426314478903, offset: 32)))))) ; guid = 8471399308421654326 -; DIS: ^7 = gv: (name: "f4", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42)), (vFuncId: (guid: 6699318081062747564, offset: 24), args: (43))))))) ; guid = 10064745020953272174 -; DIS: ^8 = gv: (name: "f5", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42))))))) ; guid = 11686717102184386164 -; DIS: ^9 = gv: (name: "f6", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, typeIdInfo: (typeTests: (7546896869197086323))))) ; guid = 11834966808443348068 +; DIS: ^6 = gv: (name: "f2", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 24), vFuncId: (guid: 16434608426314478903, offset: 32)))))) ; guid = 8471399308421654326 +; DIS: ^7 = gv: (name: "f4", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42)), (vFuncId: (guid: 6699318081062747564, offset: 24), args: (43))))))) ; guid = 10064745020953272174 +; DIS: ^8 = gv: (name: "f5", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42))))))) ; guid = 11686717102184386164 +; DIS: ^9 = gv: (name: "f6", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, typeIdInfo: (typeTests: (7546896869197086323))))) ; guid = 11834966808443348068 ; COMBINED-DIS: ^0 = module: (path: "{{.*}}thinlto-type-vcalls.ll.tmp.o", hash: (0, 0, 0, 0, 0)) -; COMBINED-DIS: ^1 = gv: (guid: 2072045998141807037, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 8, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) -; COMBINED-DIS: ^2 = gv: (guid: 4197650231481825559, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) -; COMBINED-DIS: ^3 = gv: (guid: 8471399308421654326, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 24), vFuncId: (guid: 16434608426314478903, offset: 32)))))) -; COMBINED-DIS: ^4 = gv: (guid: 10064745020953272174, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42)), (vFuncId: (guid: 6699318081062747564, offset: 24), args: (43))))))) -; COMBINED-DIS: ^5 = gv: (guid: 11686717102184386164, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42))))))) -; COMBINED-DIS: ^6 = gv: (guid: 11834966808443348068, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 2, typeIdInfo: (typeTests: (7546896869197086323))))) +; COMBINED-DIS: ^1 = gv: (guid: 2072045998141807037, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 8, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) +; COMBINED-DIS: ^2 = gv: (guid: 4197650231481825559, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadVCalls: (vFuncId: (guid: 6699318081062747564, offset: 16)))))) +; COMBINED-DIS: ^3 = gv: (guid: 8471399308421654326, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeVCalls: (vFuncId: (guid: 6699318081062747564, offset: 24), vFuncId: (guid: 16434608426314478903, offset: 32)))))) +; COMBINED-DIS: ^4 = gv: (guid: 10064745020953272174, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 15, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeTestAssumeConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42)), (vFuncId: (guid: 6699318081062747564, offset: 24), args: (43))))))) +; COMBINED-DIS: ^5 = gv: (guid: 11686717102184386164, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 0, hasUnknownCall: 1, mustBeUnreachable: 0), typeIdInfo: (typeCheckedLoadConstVCalls: ((vFuncId: (guid: 6699318081062747564, offset: 16), args: (42))))))) +; COMBINED-DIS: ^6 = gv: (guid: 11834966808443348068, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 2, typeIdInfo: (typeTests: (7546896869197086323))))) diff --git a/llvm/test/ThinLTO/X86/dot-dumper.ll b/llvm/test/ThinLTO/X86/dot-dumper.ll index 53122160b1b2..149039203a68 100644 --- a/llvm/test/ThinLTO/X86/dot-dumper.ll +++ b/llvm/test/ThinLTO/X86/dot-dumper.ll @@ -20,8 +20,8 @@ ; PERMODULE-NEXT: color = lightgrey; ; PERMODULE-NEXT: label = ""; ; PERMODULE-NEXT: node [style=filled,fillcolor=lightblue]; -; PERMODULE-NEXT: M0_[[MAIN_ALIAS:[0-9]+]] [style="dotted,filled",shape="box",label="main_alias",fillcolor="red"]; // alias, dead -; PERMODULE-NEXT: M0_[[MAIN:[0-9]+]] [shape="record",label="main|extern (inst: 4, ffl: 0000000000)}",fillcolor="red"]; // function, dead +; PERMODULE-NEXT: M0_[[MAIN_ALIAS:[0-9]+]] [style="dotted,filled",shape="box",label="main_alias",fillcolor="red"]; // alias, definition, dead +; PERMODULE-NEXT: M0_[[MAIN:[0-9]+]] [shape="record",label="main|extern (inst: 4, ffl: 0000000000)}",fillcolor="red"]; // function, definition, dead ; PERMODULE-NEXT: // Edges: ; PERMODULE-NEXT: M0_[[MAIN_ALIAS]] -> M0_[[MAIN]] [style=dotted]; // alias ; PERMODULE-NEXT: } @@ -39,8 +39,8 @@ ; COMBINED-NEXT: color = lightgrey; ; COMBINED-NEXT: label = "dot-dumper{{.*}}1.bc"; ; COMBINED-NEXT: node [style=filled,fillcolor=lightblue]; -; COMBINED-NEXT: M0_[[MAIN_ALIAS:[0-9]+]] [style="dotted,filled",shape="box",label="main_alias",fillcolor="red"]; // alias, dead -; COMBINED-NEXT: M0_[[MAIN:[0-9]+]] [shape="record",label="main|extern (inst: 4, ffl: 0000000000)}"]; // function, preserved +; COMBINED-NEXT: M0_[[MAIN_ALIAS:[0-9]+]] [style="dotted,filled",shape="box",label="main_alias",fillcolor="red"]; // alias, definition, dead +; COMBINED-NEXT: M0_[[MAIN:[0-9]+]] [shape="record",label="main|extern (inst: 4, ffl: 0000000000)}"]; // function, definition, preserved ; COMBINED-NEXT: // Edges: ; COMBINED-NEXT: M0_[[MAIN_ALIAS]] -> M0_[[MAIN]] [style=dotted]; // alias ; COMBINED-NEXT: } @@ -50,10 +50,10 @@ ; COMBINED-NEXT: color = lightgrey; ; COMBINED-NEXT: label = "dot-dumper{{.*}}2.bc"; ; COMBINED-NEXT: node [style=filled,fillcolor=lightblue]; -; COMBINED-NEXT: M1_[[FOO:[0-9]+]] [shape="record",label="foo|extern (inst: 4, ffl: 0000100000)}"]; // function +; COMBINED-NEXT: M1_[[FOO:[0-9]+]] [shape="record",label="foo|extern (inst: 4, ffl: 0000100000)}"]; // function, definition ; COMBINED-NEXT: M1_[[A:[0-9]+]] [shape="Mrecord",label="A|extern}"]; // variable, immutable ; COMBINED-NEXT: M1_[[B:[0-9]+]] [shape="Mrecord",label="B|extern}"]; // variable, immutable, constant -; COMBINED-NEXT: M1_{{[0-9]+}} [shape="record",label="bar|extern (inst: 1, ffl: 0000000000)}",fillcolor="red"]; // function, dead +; COMBINED-NEXT: M1_{{[0-9]+}} [shape="record",label="bar|extern (inst: 1, ffl: 0000000000)}",fillcolor="red"]; // function, definition, dead ; COMBINED-NEXT: // Edges: ; COMBINED-NEXT: M1_[[FOO]] -> M1_[[B]] [style=dashed,color=forestgreen]; // const-ref ; COMBINED-NEXT: M1_[[FOO]] -> M1_[[A]] [style=dashed,color=forestgreen]; // const-ref diff --git a/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll b/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll index 6489e952251d..abfe820075bb 100644 --- a/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll +++ b/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll @@ -48,9 +48,9 @@ define void @caller_nounwind() { ; CHECK-DAG: attributes [[ATTR_NOUNWIND]] = { norecurse nounwind } ; CHECK-DAG: attributes [[ATTR_MAYTHROW]] = { norecurse } -; SUMMARY-DAG: = gv: (name: "cleanupret", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 4, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 1, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) -; SUMMARY-DAG: = gv: (name: "resume", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 4, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 1, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) -; SUMMARY-DAG: = gv: (name: "catchret", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 1, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) +; SUMMARY-DAG: = gv: (name: "cleanupret", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 4, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 1, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) +; SUMMARY-DAG: = gv: (name: "resume", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 4, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 1, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) +; SUMMARY-DAG: = gv: (name: "catchret", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 0, canAutoHide: 0, importType: definition), insts: 5, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 0, noUnwind: 0, mayThrow: 1, hasUnknownCall: 0, mustBeUnreachable: 0), calls: ((callee: ^{{.*}})), refs: (^{{.*}})))) ;--- callees.ll target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" @@ -112,4 +112,4 @@ exit: ret void } -attributes #0 = { nounwind } \ No newline at end of file +attributes #0 = { nounwind } diff --git a/llvm/test/ThinLTO/X86/funcimport_alwaysinline.ll b/llvm/test/ThinLTO/X86/funcimport_alwaysinline.ll index 90c708fd2d11..67acc2a2892d 100644 --- a/llvm/test/ThinLTO/X86/funcimport_alwaysinline.ll +++ b/llvm/test/ThinLTO/X86/funcimport_alwaysinline.ll @@ -23,4 +23,4 @@ entry: } attributes #0 = { alwaysinline nounwind uwtable } -; CHECK2: ^2 = gv: (guid: {{.*}}, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0), insts: 1, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 1, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) +; CHECK2: ^2 = gv: (guid: {{.*}}, summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 1, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 1, funcFlags: (readNone: 0, readOnly: 0, noRecurse: 0, returnDoesNotAlias: 0, noInline: 0, alwaysInline: 1, noUnwind: 1, mayThrow: 0, hasUnknownCall: 0, mustBeUnreachable: 0)))) diff --git a/llvm/test/ThinLTO/X86/load-store-caching.ll b/llvm/test/ThinLTO/X86/load-store-caching.ll index 4fb2d4693042..b25308bf1761 100644 --- a/llvm/test/ThinLTO/X86/load-store-caching.ll +++ b/llvm/test/ThinLTO/X86/load-store-caching.ll @@ -22,5 +22,5 @@ entry: } ; CHECK: ^0 = module: -; CHECK-NEXT: ^1 = gv: (name: "obj", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), varFlags: (readonly: 1, writeonly: 1, constant: 0)))) ; guid = -; CHECK-NEXT: ^2 = gv: (name: "foo", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0), insts: 3, refs: (^1)))) ; guid = +; CHECK-NEXT: ^1 = gv: (name: "obj", summaries: (variable: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), varFlags: (readonly: 1, writeonly: 1, constant: 0)))) ; guid = +; CHECK-NEXT: ^2 = gv: (name: "foo", summaries: (function: (module: ^0, flags: (linkage: external, visibility: default, notEligibleToImport: 0, live: 0, dsoLocal: 1, canAutoHide: 0, importType: definition), insts: 3, refs: (^1)))) ; guid = diff --git a/llvm/test/Transforms/LowerTypeTests/import-unsat.ll b/llvm/test/Transforms/LowerTypeTests/import-unsat.ll index 76afe68d2189..f766c2d32416 100644 --- a/llvm/test/Transforms/LowerTypeTests/import-unsat.ll +++ b/llvm/test/Transforms/LowerTypeTests/import-unsat.ll @@ -10,6 +10,7 @@ ; SUMMARY-NEXT: Live: true ; SUMMARY-NEXT: Local: false ; SUMMARY-NEXT: CanAutoHide: false +; SUMMARY-NEXT: ImportType: 0 ; SUMMARY-NEXT: TypeTests: [ 123 ] ; SUMMARY-NEXT: TypeIdMap: ; SUMMARY-NEXT: typeid1: diff --git a/llvm/test/Transforms/WholeProgramDevirt/Inputs/import-indir.yaml b/llvm/test/Transforms/WholeProgramDevirt/Inputs/import-indir.yaml index 30159c5012b0..22533ed636a5 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/Inputs/import-indir.yaml +++ b/llvm/test/Transforms/WholeProgramDevirt/Inputs/import-indir.yaml @@ -2,6 +2,7 @@ GlobalValueMap: 42: - Live: true + ImportType: 0 TypeTestAssumeVCalls: - GUID: 123 Offset: 0 @@ -22,6 +23,9 @@ GlobalValueMap: GUID: 456 Offset: 8 Args: [24, 12] + 43: + - Live: true + ImportType : 1 TypeIdMap: typeid1: WPDRes: diff --git a/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll b/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll index 1d74a5976978..e4d6f1d52b54 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll @@ -10,6 +10,7 @@ ; SUMMARY-NEXT: Live: true ; SUMMARY-NEXT: Local: false ; SUMMARY-NEXT: CanAutoHide: false +; SUMMARY-NEXT: ImportType: 0 ; SUMMARY-NEXT: TypeTestAssumeVCalls: ; SUMMARY-NEXT: - GUID: 123 ; SUMMARY-NEXT: Offset: 0 @@ -30,6 +31,14 @@ ; SUMMARY-NEXT: GUID: 456 ; SUMMARY-NEXT: Offset: 8 ; SUMMARY-NEXT: Args: [ 24, 12 ] +; SUMMARY-NEXT: 43: +; SUMMARY-NEXT: - Linkage: 0 +; SUMMARY-NEXT: Visibility: 0 +; SUMMARY-NEXT: NotEligibleToImport: false +; SUMMARY-NEXT: Live: true +; SUMMARY-NEXT: Local: false +; SUMMARY-NEXT: CanAutoHide: false +; SUMMARY-NEXT: ImportType: 1 ; SUMMARY-NEXT: TypeIdMap: ; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: TTRes: -- GitLab From 75edf0c18c777d69df7cfc6462e5233649bd47d4 Mon Sep 17 00:00:00 2001 From: Chuanqi Xu Date: Thu, 11 Apr 2024 11:05:55 +0800 Subject: [PATCH 476/695] [NFC] [Serialization] Avoid accessing PendingBodies as much as possible The 'HaveBody' parameter in isConsumerInterestedIn is only used for the function decl if it doesn't have a body already. It should be relatively less frequent than the call to isConsumerInterestedIn. So we can delay the computing of `HaveBdoy` to make it more efficient. --- clang/include/clang/Serialization/ASTReader.h | 1 + clang/lib/Serialization/ASTReaderDecl.cpp | 14 ++++++-------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h index 5fd55a519c6b..e8b9f28690d9 100644 --- a/clang/include/clang/Serialization/ASTReader.h +++ b/clang/include/clang/Serialization/ASTReader.h @@ -1492,6 +1492,7 @@ public: getModuleFileLevelDecls(ModuleFile &Mod); private: + bool isConsumerInterestedIn(Decl *D); void PassInterestingDeclsToConsumer(); void PassInterestingDeclToConsumer(Decl *D); diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp index 78448855fba0..9e49a3780ff4 100644 --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -3198,7 +3198,7 @@ inline void ASTReader::LoadedDecl(unsigned Index, Decl *D) { /// This routine should return true for anything that might affect /// code generation, e.g., inline function definitions, Objective-C /// declarations with metadata, etc. -static bool isConsumerInterestedIn(ASTContext &Ctx, Decl *D, bool HasBody) { +bool ASTReader::isConsumerInterestedIn(Decl *D) { // An ObjCMethodDecl is never considered as "interesting" because its // implementation container always is. @@ -3207,7 +3207,7 @@ static bool isConsumerInterestedIn(ASTContext &Ctx, Decl *D, bool HasBody) { if (isPartOfPerModuleInitializer(D)) { auto *M = D->getImportedOwningModule(); if (M && M->Kind == Module::ModuleMapModule && - Ctx.DeclMustBeEmitted(D)) + getContext().DeclMustBeEmitted(D)) return false; } @@ -3222,7 +3222,7 @@ static bool isConsumerInterestedIn(ASTContext &Ctx, Decl *D, bool HasBody) { (Var->isThisDeclarationADefinition() == VarDecl::Definition || OMPDeclareTargetDeclAttr::isDeclareTargetDeclaration(Var)); if (const auto *Func = dyn_cast(D)) - return Func->doesThisDeclarationHaveABody() || HasBody; + return Func->doesThisDeclarationHaveABody() || PendingBodies.count(D); if (auto *ES = D->getASTContext().getExternalSource()) if (ES->hasExternalDefinitions(D) == ExternalASTSource::EK_Never) @@ -4173,7 +4173,7 @@ void ASTReader::PassInterestingDeclsToConsumer() { while (!PotentiallyInterestingDecls.empty()) { Decl *D = PotentiallyInterestingDecls.front(); PotentiallyInterestingDecls.pop_front(); - if (isConsumerInterestedIn(getContext(), D, PendingBodies.count(D))) + if (isConsumerInterestedIn(D)) PassInterestingDeclToConsumer(D); } } @@ -4197,8 +4197,7 @@ void ASTReader::loadDeclUpdateRecords(PendingUpdateRecord &Record) { // the declaration, then we know it was interesting and we skip the call // to isConsumerInterestedIn because it is unsafe to call in the // current ASTReader state. - bool WasInteresting = - Record.JustLoaded || isConsumerInterestedIn(getContext(), D, false); + bool WasInteresting = Record.JustLoaded || isConsumerInterestedIn(D); for (auto &FileAndOffset : UpdateOffsets) { ModuleFile *F = FileAndOffset.first; uint64_t Offset = FileAndOffset.second; @@ -4230,8 +4229,7 @@ void ASTReader::loadDeclUpdateRecords(PendingUpdateRecord &Record) { // We might have made this declaration interesting. If so, remember that // we need to hand it off to the consumer. - if (!WasInteresting && - isConsumerInterestedIn(getContext(), D, PendingBodies.count(D))) { + if (!WasInteresting && isConsumerInterestedIn(D)) { PotentiallyInterestingDecls.push_back(D); WasInteresting = true; } -- GitLab From 026165fad70420d85defb5fc9109c138250058ee Mon Sep 17 00:00:00 2001 From: paperchalice Date: Thu, 11 Apr 2024 11:25:33 +0800 Subject: [PATCH 477/695] [Instrumentation] Support MachineFunction in ChangeReporter (#80946) --- .../llvm/Passes/StandardInstrumentations.h | 13 ++- llvm/lib/Passes/StandardInstrumentations.cpp | 82 ++++++++++++++++--- .../DotCfg/print-changed-dot-cfg.mir | 24 ++++++ llvm/test/Other/change-printer.mir | 21 +++++ 4 files changed, 128 insertions(+), 12 deletions(-) create mode 100644 llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir create mode 100644 llvm/test/Other/change-printer.mir diff --git a/llvm/include/llvm/Passes/StandardInstrumentations.h b/llvm/include/llvm/Passes/StandardInstrumentations.h index 8c6a44876d54..b053e6307a65 100644 --- a/llvm/include/llvm/Passes/StandardInstrumentations.h +++ b/llvm/include/llvm/Passes/StandardInstrumentations.h @@ -18,6 +18,8 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSet.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/OptBisect.h" #include "llvm/IR/PassTimingInfo.h" @@ -33,6 +35,7 @@ namespace llvm { class Module; class Function; +class MachineFunction; class PassInstrumentationCallbacks; /// Instrumentation to print IR before/after passes. @@ -313,6 +316,11 @@ public: B.print(SS, nullptr, true, true); } + BlockDataT(const MachineBasicBlock &B) : Label(B.getName().str()), Data(B) { + raw_string_ostream SS(Body); + B.print(SS); + } + bool operator==(const BlockDataT &That) const { return Body == That.Body; } bool operator!=(const BlockDataT &That) const { return Body != That.Body; } @@ -364,6 +372,7 @@ protected: class EmptyData { public: EmptyData(const BasicBlock &) {} + EmptyData(const MachineBasicBlock &) {} }; // The data saved for comparing functions. @@ -405,7 +414,8 @@ public: protected: // Generate the data for \p F into \p Data. - static bool generateFunctionData(IRDataT &Data, const Function &F); + template + static bool generateFunctionData(IRDataT &Data, const FunctionT &F); const IRDataT &Before; const IRDataT &After; @@ -475,6 +485,7 @@ class DCData { public: // Fill the map with the transitions from basic block \p B. DCData(const BasicBlock &B); + DCData(const MachineBasicBlock &B); // Return an iterator to the names of the successor blocks. StringMap::const_iterator begin() const { diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp index 697988b3fc7c..c5f0c14885d0 100644 --- a/llvm/lib/Passes/StandardInstrumentations.cpp +++ b/llvm/lib/Passes/StandardInstrumentations.cpp @@ -19,7 +19,9 @@ #include "llvm/Analysis/CallGraphSCCPass.h" #include "llvm/Analysis/LazyCallGraph.h" #include "llvm/Analysis/LoopInfo.h" +#include "llvm/CodeGen/MIRPrinter.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/IR/Module.h" @@ -180,6 +182,12 @@ const Module *unwrapModule(Any IR, bool Force = false) { return F->getParent(); } + if (const auto *MF = unwrapIR(IR)) { + if (!Force && !isFunctionInPrintList(MF->getName())) + return nullptr; + return MF->getFunction().getParent(); + } + llvm_unreachable("Unknown IR unit"); } @@ -215,6 +223,12 @@ void printIR(raw_ostream &OS, const Loop *L) { printLoop(const_cast(*L), OS); } +void printIR(raw_ostream &OS, const MachineFunction *MF) { + if (!isFunctionInPrintList(MF->getName())) + return; + MF->print(OS); +} + std::string getIRName(Any IR) { if (unwrapIR(IR)) return "[module]"; @@ -262,6 +276,9 @@ bool shouldPrintIR(Any IR) { if (const auto *L = unwrapIR(IR)) return isFunctionInPrintList(L->getHeader()->getParent()->getName()); + + if (const auto *MF = unwrapIR(IR)) + return isFunctionInPrintList(MF->getName()); llvm_unreachable("Unknown wrapped IR type"); } @@ -275,6 +292,14 @@ void unwrapAndPrint(raw_ostream &OS, Any IR) { auto *M = unwrapModule(IR); assert(M && "should have unwrapped module"); printIR(OS, M); + + if (const auto *MF = unwrapIR(IR)) { + auto &MMI = MF->getMMI(); + for (const auto &F : *M) { + if (auto *MF = MMI.getMachineFunction(F)) + MF->print(OS); + } + } return; } @@ -297,6 +322,11 @@ void unwrapAndPrint(raw_ostream &OS, Any IR) { printIR(OS, L); return; } + + if (const auto *MF = unwrapIR(IR)) { + printIR(OS, MF); + return; + } llvm_unreachable("Unknown wrapped IR type"); } @@ -305,7 +335,8 @@ bool isIgnored(StringRef PassID) { return isSpecialPass(PassID, {"PassManager", "PassAdaptor", "AnalysisManagerProxy", "DevirtSCCRepeatedPass", "ModuleInlinerWrapperPass", - "VerifierPass", "PrintModulePass"}); + "VerifierPass", "PrintModulePass", "PrintMIRPass", + "PrintMIRPreparePass"}); } std::string makeHTMLReady(StringRef SR) { @@ -664,20 +695,38 @@ template void IRComparer::analyzeIR(Any IR, IRDataT &Data) { return; } - const auto *F = unwrapIR(IR); - if (!F) { - const auto *L = unwrapIR(IR); - assert(L && "Unknown IR unit."); - F = L->getHeader()->getParent(); + if (const auto *F = unwrapIR(IR)) { + generateFunctionData(Data, *F); + return; + } + + if (const auto *L = unwrapIR(IR)) { + auto *F = L->getHeader()->getParent(); + generateFunctionData(Data, *F); + return; } - assert(F && "Unknown IR unit."); - generateFunctionData(Data, *F); + + if (const auto *MF = unwrapIR(IR)) { + generateFunctionData(Data, *MF); + return; + } + + llvm_unreachable("Unknown IR unit"); +} + +static bool shouldGenerateData(const Function &F) { + return !F.isDeclaration() && isFunctionInPrintList(F.getName()); +} + +static bool shouldGenerateData(const MachineFunction &MF) { + return isFunctionInPrintList(MF.getName()); } template -bool IRComparer::generateFunctionData(IRDataT &Data, const Function &F) { - if (!F.isDeclaration() && isFunctionInPrintList(F.getName())) { - FuncDataT FD(F.getEntryBlock().getName().str()); +template +bool IRComparer::generateFunctionData(IRDataT &Data, const FunctionT &F) { + if (shouldGenerateData(F)) { + FuncDataT FD(F.front().getName().str()); int I = 0; for (const auto &B : F) { std::string BBName = B.getName().str(); @@ -722,6 +771,12 @@ static SmallString<32> getIRFileDisplayName(Any IR) { ResultStream << "-loop-"; stable_hash LoopNameHash = stable_hash_combine_string(L->getName()); write_hex(ResultStream, LoopNameHash, HexPrintStyle::Lower, MaxHashWidth); + } else if (const auto *MF = unwrapIR(IR)) { + ResultStream << "-machine-function-"; + stable_hash MachineFunctionNameHash = + stable_hash_combine_string(MF->getName()); + write_hex(ResultStream, MachineFunctionNameHash, HexPrintStyle::Lower, + MaxHashWidth); } else { llvm_unreachable("Unknown wrapped IR type"); } @@ -2122,6 +2177,11 @@ DCData::DCData(const BasicBlock &B) { addSuccessorLabel(Succ->getName().str(), ""); } +DCData::DCData(const MachineBasicBlock &B) { + for (const MachineBasicBlock *Succ : successors(&B)) + addSuccessorLabel(Succ->getName().str(), ""); +} + DotCfgChangeReporter::DotCfgChangeReporter(bool Verbose) : ChangeReporter>(Verbose) {} diff --git a/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir b/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir new file mode 100644 index 000000000000..340ece93aa02 --- /dev/null +++ b/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir @@ -0,0 +1,24 @@ +# REQUIRES: x86-registered-target +# Simple functionality check. +# RUN: rm -rf %t && mkdir -p %t +# RUN: llc -filetype=null -print-changed=dot-cfg -passes=no-op-machine-function -dot-cfg-dir=%t %s +# RUN: ls %t/*.pdf %t/passes.html | count 3 + +--- +name: g +body: | + bb.0.entry: + %0:gr32 = MOV32ri 5 + $eax = COPY %0 + RET 0, $eax + +... +--- +name: f +body: | + bb.0.entry: + %0:gr32 = MOV32ri 7 + $eax = COPY %0 + RET 0, $eax + +... diff --git a/llvm/test/Other/change-printer.mir b/llvm/test/Other/change-printer.mir new file mode 100644 index 000000000000..5e57da50e625 --- /dev/null +++ b/llvm/test/Other/change-printer.mir @@ -0,0 +1,21 @@ +# REQUIRES: x86-registered-target +# RUN: llc -mtriple=x86_64-unknown-linux-gnu -filetype=null %s \ +# RUN: -p no-op-machine-function -print-changed 2>&1 | FileCheck %s --check-prefix=CHECK-NO-OP + +# RUN: llc -mtriple=x86_64-unknown-linux-gnu -filetype=null %s \ +# RUN: -p dead-mi-elimination -print-changed 2>&1 | FileCheck %s --check-prefix=CHECK-SIMPLE + +--- +name: test +body: | + bb.0: + %1:gr64 = MOV64ri 0 + %2:gr64 = MOV64ri 0 + $eax = COPY %1 + RET64 implicit $eax +... + +# CHECK-NO-OP: *** IR Dump After NoOpMachineFunctionPass on test omitted because no change *** + +# CHECK-SIMPLE: *** IR Dump After DeadMachineInstructionElimPass on test *** +# CHECK-SIMPLE-NOT: %2:gr64 = MOV64ri 0 -- GitLab From 53003e36e9f4574d06c22611f61f68de32c89c6b Mon Sep 17 00:00:00 2001 From: Sacha Coppey Date: Thu, 11 Apr 2024 06:19:56 +0200 Subject: [PATCH 478/695] [RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337) This patch adds stackmap support for RISC-V with call targets. Based on patch from https://reviews.llvm.org/D129848. --- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 57 ++++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 7 +- llvm/test/CodeGen/RISCV/rv64-patchpoint.ll | 46 ++- .../RISCV/rv64-statepoint-call-lowering-x1.ll | 16 ++ .../RISCV/rv64-statepoint-call-lowering-x2.ll | 23 ++ .../RISCV/rv64-statepoint-call-lowering.ll | 262 ++++++++++++++++++ 7 files changed, 419 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 9982a73ee914..779f179dff61 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -14,6 +14,7 @@ #include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVInstPrinter.h" #include "MCTargetDesc/RISCVMCExpr.h" +#include "MCTargetDesc/RISCVMatInt.h" #include "MCTargetDesc/RISCVTargetStreamer.h" #include "RISCV.h" #include "RISCVMachineFunctionInfo.h" @@ -153,8 +154,35 @@ void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, PatchPointOpers Opers(&MI); + const MachineOperand &CalleeMO = Opers.getCallTarget(); unsigned EncodedBytes = 0; + if (CalleeMO.isImm()) { + uint64_t CallTarget = CalleeMO.getImm(); + if (CallTarget) { + assert((CallTarget & 0xFFFF'FFFF'FFFF) == CallTarget && + "High 16 bits of call target should be zero."); + // Materialize the jump address: + SmallVector Seq; + RISCVMatInt::generateMCInstSeq(CallTarget, *STI, RISCV::X1, Seq); + for (MCInst &Inst : Seq) { + bool Compressed = EmitToStreamer(OutStreamer, Inst); + EncodedBytes += Compressed ? 2 : 4; + } + bool Compressed = EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR) + .addReg(RISCV::X1) + .addReg(RISCV::X1) + .addImm(0)); + EncodedBytes += Compressed ? 2 : 4; + } + } else if (CalleeMO.isGlobal()) { + MCOperand CallTargetMCOp; + lowerOperand(CalleeMO, CallTargetMCOp); + EmitToStreamer(OutStreamer, + MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp)); + EncodedBytes += 8; + } + // Emit padding. unsigned NumBytes = Opers.getNumPatchBytes(); assert(NumBytes >= EncodedBytes && @@ -173,6 +201,35 @@ void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM, assert(PatchBytes % NOPBytes == 0 && "Invalid number of NOP bytes requested!"); emitNops(PatchBytes / NOPBytes); + } else { + // Lower call target and choose correct opcode + const MachineOperand &CallTarget = SOpers.getCallTarget(); + MCOperand CallTargetMCOp; + switch (CallTarget.getType()) { + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ExternalSymbol: + lowerOperand(CallTarget, CallTargetMCOp); + EmitToStreamer( + OutStreamer, + MCInstBuilder(RISCV::PseudoCALL).addOperand(CallTargetMCOp)); + break; + case MachineOperand::MO_Immediate: + CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); + EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JAL) + .addReg(RISCV::X1) + .addOperand(CallTargetMCOp)); + break; + case MachineOperand::MO_Register: + CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); + EmitToStreamer(OutStreamer, MCInstBuilder(RISCV::JALR) + .addReg(RISCV::X1) + .addOperand(CallTargetMCOp) + .addImm(0)); + break; + default: + llvm_unreachable("Unsupported operand type in statepoint call target"); + break; + } } auto &Ctx = OutStreamer.getContext(); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 357432081ddb..3e7bc8c2367d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -17910,6 +17910,17 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, case RISCV::PseudoFROUND_D_IN32X: return emitFROUND(MI, BB, Subtarget); case TargetOpcode::STATEPOINT: + // STATEPOINT is a pseudo instruction which has no implicit defs/uses + // while jal call instruction (where statepoint will be lowered at the end) + // has implicit def. This def is early-clobber as it will be set at + // the moment of the call and earlier than any use is read. + // Add this implicit dead def here as a workaround. + MI.addOperand(*MI.getMF(), + MachineOperand::CreateReg( + RISCV::X1, /*isDef*/ true, + /*isImp*/ true, /*isKill*/ false, /*isDead*/ true, + /*isUndef*/ false, /*isEarlyClobber*/ true)); + [[fallthrough]]; case TargetOpcode::STACKMAP: case TargetOpcode::PATCHPOINT: if (!Subtarget.is64Bit()) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 6b75efe684d9..84d754e3cbcf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1469,9 +1469,12 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { case TargetOpcode::PATCHPOINT: // The size of the patchpoint intrinsic is the number of bytes requested return PatchPointOpers(&MI).getNumPatchBytes(); - case TargetOpcode::STATEPOINT: + case TargetOpcode::STATEPOINT: { // The size of the statepoint intrinsic is the number of bytes requested - return StatepointOpers(&MI).getNumPatchBytes(); + unsigned NumBytes = StatepointOpers(&MI).getNumPatchBytes(); + // No patch bytes means at most a PseudoCall is emitted + return std::max(NumBytes, 8U); + } default: return get(Opcode).getSize(); } diff --git a/llvm/test/CodeGen/RISCV/rv64-patchpoint.ll b/llvm/test/CodeGen/RISCV/rv64-patchpoint.ll index 51c2ae908e84..adf5f9863b79 100644 --- a/llvm/test/CodeGen/RISCV/rv64-patchpoint.ll +++ b/llvm/test/CodeGen/RISCV/rv64-patchpoint.ll @@ -1,12 +1,56 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv64 -debug-entry-values -enable-misched=0 < %s | FileCheck %s +; Trivial patchpoint codegen +; +define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { +; CHECK-LABEL: trivial_patchpoint_codegen: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd s0, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: sd s1, 0(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset s0, -8 +; CHECK-NEXT: .cfi_offset s1, -16 +; CHECK-NEXT: mv s0, a0 +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: lui ra, 3563 +; CHECK-NEXT: addiw ra, ra, -577 +; CHECK-NEXT: slli ra, ra, 12 +; CHECK-NEXT: addi ra, ra, -259 +; CHECK-NEXT: slli ra, ra, 12 +; CHECK-NEXT: addi ra, ra, -1282 +; CHECK-NEXT: jalr ra +; CHECK-NEXT: mv s1, a0 +; CHECK-NEXT: mv a0, s0 +; CHECK-NEXT: mv a1, s1 +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: lui ra, 3563 +; CHECK-NEXT: addiw ra, ra, -577 +; CHECK-NEXT: slli ra, ra, 12 +; CHECK-NEXT: addi ra, ra, -259 +; CHECK-NEXT: slli ra, ra, 12 +; CHECK-NEXT: addi ra, ra, -1281 +; CHECK-NEXT: jalr ra +; CHECK-NEXT: mv a0, s1 +; CHECK-NEXT: ld s0, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: ld s1, 0(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +entry: + %resolveCall2 = inttoptr i64 244837814094590 to i8* + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 28, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %resolveCall3 = inttoptr i64 244837814094591 to i8* + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 28, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) + ret i64 %result +} + ; Test small patchpoints that don't emit calls. define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { ; CHECK-LABEL: small_patchpoint_codegen: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: .cfi_def_cfa_offset 0 -; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: .Ltmp2: ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop diff --git a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll new file mode 100644 index 000000000000..3ba49653cd01 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x1.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple riscv64 -verify-machineinstrs -stop-after=prologepilog < %s | FileCheck %s + +; Check that STATEPOINT instruction has an early clobber implicit def for LR. +target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "riscv64" + +define void @test() "frame-pointer"="all" gc "statepoint-example" { +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(void ()) @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" ()] +; CHECK: STATEPOINT 0, 0, 0, target-flags(riscv-call) @return_i1, 2, 0, 2, 0, 2, 0, 2, 0, 2, 0, 2, 0, csr_ilp32_lp64, implicit-def $x2, implicit-def dead early-clobber $x1 + ret void +} + + +declare void @return_i1() +declare token @llvm.experimental.gc.statepoint.p0(i64, i32, ptr, i32, i32, ...) diff --git a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll new file mode 100644 index 000000000000..9c99f64bcacc --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering-x2.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple riscv64 -verify-machineinstrs -stop-after=prologepilog < %s | FileCheck %s + +; Check that STATEPOINT instruction prefer to use x2 in presense of x8. +target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "riscv64" + +declare void @consume(ptr addrspace(1) %obj) + +define i1 @test(ptr addrspace(1) %a) "frame-pointer"="all" gc "statepoint-example" { +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(i1 ()) @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (ptr addrspace(1) %a)] +; CHECK: STATEPOINT 0, 0, 0, target-flags(riscv-call) @return_i1, 2, 0, 2, 0, 2, 0, 2, 1, 1, 8, $x8, -32, 2, 0, 2, 1, 0, 0 + %call1 = call ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %safepoint_token, i32 0, i32 0) + %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token) + call void @consume(ptr addrspace(1) %call1) + ret i1 %call2 +} + + +declare i1 @return_i1() +declare token @llvm.experimental.gc.statepoint.p0(i64, i32, ptr, i32, i32, ...) +declare ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token, i32, i32) +declare i1 @llvm.experimental.gc.result.i1(token) diff --git a/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll new file mode 100644 index 000000000000..2fa344d4d79a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64-statepoint-call-lowering.ll @@ -0,0 +1,262 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs < %s | FileCheck %s +; A collection of basic functionality tests for statepoint lowering - most +; interesting cornercases are exercised through the x86 tests. + +target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "riscv64" + +%struct = type { i64, i64 } + +declare zeroext i1 @return_i1() +declare zeroext i32 @return_i32() +declare ptr @return_i32ptr() +declare float @return_float() +declare %struct @return_struct() +declare void @varargf(i32, ...) + +define i1 @test_i1_return() gc "statepoint-example" { +; CHECK-LABEL: test_i1_return: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: call return_i1 +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +; This is just checking that a i1 gets lowered normally when there's no extra +; state arguments to the statepoint +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(i1 ()) @return_i1, i32 0, i32 0, i32 0, i32 0) + %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token) + ret i1 %call1 +} + +define i32 @test_i32_return() gc "statepoint-example" { +; CHECK-LABEL: test_i32_return: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: call return_i32 +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(i32 ()) @return_i32, i32 0, i32 0, i32 0, i32 0) + %call1 = call zeroext i32 @llvm.experimental.gc.result.i32(token %safepoint_token) + ret i32 %call1 +} + +define ptr @test_i32ptr_return() gc "statepoint-example" { +; CHECK-LABEL: test_i32ptr_return: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: call return_i32ptr +; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(ptr ()) @return_i32ptr, i32 0, i32 0, i32 0, i32 0) + %call1 = call ptr @llvm.experimental.gc.result.p0(token %safepoint_token) + ret ptr %call1 +} + +define float @test_float_return() gc "statepoint-example" { +; CHECK-LABEL: test_float_return: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: call return_float +; CHECK-NEXT: .Ltmp3: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(float ()) @return_float, i32 0, i32 0, i32 0, i32 0) + %call1 = call float @llvm.experimental.gc.result.f32(token %safepoint_token) + ret float %call1 +} + +define %struct @test_struct_return() gc "statepoint-example" { +; CHECK-LABEL: test_struct_return: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: call return_struct +; CHECK-NEXT: .Ltmp4: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(%struct ()) @return_struct, i32 0, i32 0, i32 0, i32 0) + %call1 = call %struct @llvm.experimental.gc.result.struct(token %safepoint_token) + ret %struct %call1 +} + +define i1 @test_relocate(ptr addrspace(1) %a) gc "statepoint-example" { +; CHECK-LABEL: test_relocate: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: sd a0, 0(sp) +; CHECK-NEXT: call return_i1 +; CHECK-NEXT: .Ltmp5: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +; Check that an ununsed relocate has no code-generation impact +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(i1 ()) @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (ptr addrspace(1) %a)] + %call1 = call ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %safepoint_token, i32 0, i32 0) + %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token) + ret i1 %call2 +} + +define void @test_void_vararg() gc "statepoint-example" { +; CHECK-LABEL: test_void_vararg: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: li a0, 42 +; CHECK-NEXT: li a1, 43 +; CHECK-NEXT: call varargf +; CHECK-NEXT: .Ltmp6: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +; Check a statepoint wrapping a *ptr returning vararg function works +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(void (i32, ...)) @varargf, i32 2, i32 0, i32 42, i32 43, i32 0, i32 0) + ;; if we try to use the result from a statepoint wrapping a + ;; non-void-returning varargf, we will experience a crash. + ret void +} + +define i1 @test_i1_return_patchable() gc "statepoint-example" { +; CHECK-LABEL: test_i1_return_patchable: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: nop +; CHECK-NEXT: .Ltmp7: +; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: ret +; A patchable variant of test_i1_return +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 4, ptr elementtype(i1 ()) null, i32 0, i32 0, i32 0, i32 0) + %call1 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token) + ret i1 %call1 +} + +declare void @consume(ptr addrspace(1) %obj) + +define i1 @test_cross_bb(ptr addrspace(1) %a, i1 %external_cond) gc "statepoint-example" { +; CHECK-LABEL: test_cross_bb: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: .cfi_offset s0, -16 +; CHECK-NEXT: andi s0, a1, 1 +; CHECK-NEXT: sd a0, 8(sp) +; CHECK-NEXT: call return_i1 +; CHECK-NEXT: .Ltmp8: +; CHECK-NEXT: beqz s0, .LBB8_2 +; CHECK-NEXT: # %bb.1: # %left +; CHECK-NEXT: ld a1, 8(sp) +; CHECK-NEXT: mv s0, a0 +; CHECK-NEXT: mv a0, a1 +; CHECK-NEXT: call consume +; CHECK-NEXT: mv a0, s0 +; CHECK-NEXT: j .LBB8_3 +; CHECK-NEXT: .LBB8_2: # %right +; CHECK-NEXT: li a0, 1 +; CHECK-NEXT: .LBB8_3: # %right +; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 32 +; CHECK-NEXT: ret +entry: + %safepoint_token = tail call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(i1 ()) @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (ptr addrspace(1) %a)] + br i1 %external_cond, label %left, label %right + +left: + %call1 = call ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token %safepoint_token, i32 0, i32 0) + %call2 = call zeroext i1 @llvm.experimental.gc.result.i1(token %safepoint_token) + call void @consume(ptr addrspace(1) %call1) + ret i1 %call2 + +right: + ret i1 true +} + +%struct2 = type { i64, i64, i64 } + +declare void @consume_attributes(i32, ptr nest, i32, ptr byval(%struct2)) + +define void @test_attributes(ptr byval(%struct2) %s) gc "statepoint-example" { +; CHECK-LABEL: test_attributes: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill +; CHECK-NEXT: .cfi_offset ra, -8 +; CHECK-NEXT: ld a1, 16(a0) +; CHECK-NEXT: sd a1, 16(sp) +; CHECK-NEXT: ld a1, 8(a0) +; CHECK-NEXT: sd a1, 8(sp) +; CHECK-NEXT: ld a0, 0(a0) +; CHECK-NEXT: sd a0, 0(sp) +; CHECK-NEXT: li a0, 42 +; CHECK-NEXT: li a1, 17 +; CHECK-NEXT: mv a2, sp +; CHECK-NEXT: li t2, 0 +; CHECK-NEXT: call consume_attributes +; CHECK-NEXT: .Ltmp9: +; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 32 +; CHECK-NEXT: ret +entry: +; Check that arguments with attributes are lowered correctly. +; We call a function that has a nest argument and a byval argument. + %statepoint_token = call token (i64, i32, ptr, i32, i32, ...) @llvm.experimental.gc.statepoint.p0(i64 0, i32 0, ptr elementtype(void (i32, ptr, i32, ptr)) @consume_attributes, i32 4, i32 0, i32 42, ptr nest null, i32 17, ptr byval(%struct2) %s, i32 0, i32 0) + ret void +} + +declare token @llvm.experimental.gc.statepoint.p0(i64, i32, ptr, i32, i32, ...) +declare i1 @llvm.experimental.gc.result.i1(token) + +declare i32 @llvm.experimental.gc.result.i32(token) + +declare ptr @llvm.experimental.gc.result.p0(token) + +declare float @llvm.experimental.gc.result.f32(token) + +declare %struct @llvm.experimental.gc.result.struct(token) + + + +declare ptr addrspace(1) @llvm.experimental.gc.relocate.p1(token, i32, i32) -- GitLab From b5640369337e98e573c949080ed4a4061ec6ec9a Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Thu, 11 Apr 2024 12:20:27 +0800 Subject: [PATCH 479/695] [MachineCombiner][NFC] Split target-dependent patterns We split target-dependent MachineCombiner patterns into their target folder. This makes MachineCombiner much more target-independent. Reviewers: davemgreen, asavonic, rotateright, RKSimon, lukel97, LuoYuanke, topperc, mshockwave, asi-sc Reviewed By: topperc, mshockwave Pull Request: https://github.com/llvm/llvm-project/pull/87991 --- .../llvm/CodeGen/MachineCombinerPattern.h | 168 +---- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 25 +- llvm/lib/CodeGen/MachineCombiner.cpp | 72 +-- llvm/lib/CodeGen/TargetInstrInfo.cpp | 19 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 572 +++++++++--------- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 152 ++++- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 77 ++- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 26 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 83 +-- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 23 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 12 +- llvm/lib/Target/X86/X86InstrInfo.h | 15 +- 12 files changed, 642 insertions(+), 602 deletions(-) diff --git a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h index 41b73eaae029..3428c4dde5c7 100644 --- a/llvm/include/llvm/CodeGen/MachineCombinerPattern.h +++ b/llvm/include/llvm/CodeGen/MachineCombinerPattern.h @@ -16,8 +16,16 @@ namespace llvm { +/// The combiner's goal may differ based on which pattern it is attempting +/// to optimize. +enum class CombinerObjective { + MustReduceDepth, // The data dependency chain must be improved. + MustReduceRegisterPressure, // The register pressure must be reduced. + Default // The critical path must not be lengthened. +}; + /// These are instruction patterns matched by the machine combiner pass. -enum class MachineCombinerPattern { +enum MachineCombinerPattern : unsigned { // These are commutative variants for reassociating a computation chain. See // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp. REASSOC_AX_BY, @@ -25,163 +33,7 @@ enum class MachineCombinerPattern { REASSOC_XA_BY, REASSOC_XA_YB, - // These are patterns matched by the PowerPC to reassociate FMA chains. - REASSOC_XY_AMM_BMM, - REASSOC_XMM_AMM_BMM, - - // These are patterns matched by the PowerPC to reassociate FMA and FSUB to - // reduce register pressure. - REASSOC_XY_BCA, - REASSOC_XY_BAC, - - // These are patterns used to reduce the length of dependence chain. - SUBADD_OP1, - SUBADD_OP2, - - // These are multiply-add patterns matched by the AArch64 machine combiner. - MULADDW_OP1, - MULADDW_OP2, - MULSUBW_OP1, - MULSUBW_OP2, - MULADDWI_OP1, - MULSUBWI_OP1, - MULADDX_OP1, - MULADDX_OP2, - MULSUBX_OP1, - MULSUBX_OP2, - MULADDXI_OP1, - MULSUBXI_OP1, - // NEON integers vectors - MULADDv8i8_OP1, - MULADDv8i8_OP2, - MULADDv16i8_OP1, - MULADDv16i8_OP2, - MULADDv4i16_OP1, - MULADDv4i16_OP2, - MULADDv8i16_OP1, - MULADDv8i16_OP2, - MULADDv2i32_OP1, - MULADDv2i32_OP2, - MULADDv4i32_OP1, - MULADDv4i32_OP2, - - MULSUBv8i8_OP1, - MULSUBv8i8_OP2, - MULSUBv16i8_OP1, - MULSUBv16i8_OP2, - MULSUBv4i16_OP1, - MULSUBv4i16_OP2, - MULSUBv8i16_OP1, - MULSUBv8i16_OP2, - MULSUBv2i32_OP1, - MULSUBv2i32_OP2, - MULSUBv4i32_OP1, - MULSUBv4i32_OP2, - - MULADDv4i16_indexed_OP1, - MULADDv4i16_indexed_OP2, - MULADDv8i16_indexed_OP1, - MULADDv8i16_indexed_OP2, - MULADDv2i32_indexed_OP1, - MULADDv2i32_indexed_OP2, - MULADDv4i32_indexed_OP1, - MULADDv4i32_indexed_OP2, - - MULSUBv4i16_indexed_OP1, - MULSUBv4i16_indexed_OP2, - MULSUBv8i16_indexed_OP1, - MULSUBv8i16_indexed_OP2, - MULSUBv2i32_indexed_OP1, - MULSUBv2i32_indexed_OP2, - MULSUBv4i32_indexed_OP1, - MULSUBv4i32_indexed_OP2, - - // Floating Point - FMULADDH_OP1, - FMULADDH_OP2, - FMULSUBH_OP1, - FMULSUBH_OP2, - FMULADDS_OP1, - FMULADDS_OP2, - FMULSUBS_OP1, - FMULSUBS_OP2, - FMULADDD_OP1, - FMULADDD_OP2, - FMULSUBD_OP1, - FMULSUBD_OP2, - FNMULSUBH_OP1, - FNMULSUBS_OP1, - FNMULSUBD_OP1, - FMLAv1i32_indexed_OP1, - FMLAv1i32_indexed_OP2, - FMLAv1i64_indexed_OP1, - FMLAv1i64_indexed_OP2, - FMLAv4f16_OP1, - FMLAv4f16_OP2, - FMLAv8f16_OP1, - FMLAv8f16_OP2, - FMLAv2f32_OP2, - FMLAv2f32_OP1, - FMLAv2f64_OP1, - FMLAv2f64_OP2, - FMLAv4i16_indexed_OP1, - FMLAv4i16_indexed_OP2, - FMLAv8i16_indexed_OP1, - FMLAv8i16_indexed_OP2, - FMLAv2i32_indexed_OP1, - FMLAv2i32_indexed_OP2, - FMLAv2i64_indexed_OP1, - FMLAv2i64_indexed_OP2, - FMLAv4f32_OP1, - FMLAv4f32_OP2, - FMLAv4i32_indexed_OP1, - FMLAv4i32_indexed_OP2, - FMLSv1i32_indexed_OP2, - FMLSv1i64_indexed_OP2, - FMLSv4f16_OP1, - FMLSv4f16_OP2, - FMLSv8f16_OP1, - FMLSv8f16_OP2, - FMLSv2f32_OP1, - FMLSv2f32_OP2, - FMLSv2f64_OP1, - FMLSv2f64_OP2, - FMLSv4i16_indexed_OP1, - FMLSv4i16_indexed_OP2, - FMLSv8i16_indexed_OP1, - FMLSv8i16_indexed_OP2, - FMLSv2i32_indexed_OP1, - FMLSv2i32_indexed_OP2, - FMLSv2i64_indexed_OP1, - FMLSv2i64_indexed_OP2, - FMLSv4f32_OP1, - FMLSv4f32_OP2, - FMLSv4i32_indexed_OP1, - FMLSv4i32_indexed_OP2, - - FMULv2i32_indexed_OP1, - FMULv2i32_indexed_OP2, - FMULv2i64_indexed_OP1, - FMULv2i64_indexed_OP2, - FMULv4i16_indexed_OP1, - FMULv4i16_indexed_OP2, - FMULv4i32_indexed_OP1, - FMULv4i32_indexed_OP2, - FMULv8i16_indexed_OP1, - FMULv8i16_indexed_OP2, - - // RISCV FMADD, FMSUB, FNMSUB patterns - FMADD_AX, - FMADD_XA, - FMSUB, - FNMSUB, - SHXADD_ADD_SLLI_OP1, - SHXADD_ADD_SLLI_OP2, - - // X86 VNNI - DPWSSD, - - FNMADD, + TARGET_PATTERN_START }; } // end namespace llvm diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 9fd0ebe6956f..d4a83e3753d9 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -19,6 +19,7 @@ #include "llvm/ADT/Uniformity.h" #include "llvm/CodeGen/MIRFormatter.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineCombinerPattern.h" #include "llvm/CodeGen/MachineCycleAnalysis.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" @@ -61,7 +62,6 @@ class TargetRegisterClass; class TargetRegisterInfo; class TargetSchedModel; class TargetSubtargetInfo; -enum class MachineCombinerPattern; enum class MachineTraceStrategy; template class SmallVectorImpl; @@ -1191,10 +1191,9 @@ public: /// faster sequence. /// \param Root - Instruction that could be combined with one of its operands /// \param Patterns - Vector of possible combination patterns - virtual bool - getMachineCombinerPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns, - bool DoRegPressureReduce) const; + virtual bool getMachineCombinerPatterns(MachineInstr &Root, + SmallVectorImpl &Patterns, + bool DoRegPressureReduce) const; /// Return true if target supports reassociation of instructions in machine /// combiner pass to reduce register pressure for a given BB. @@ -1206,13 +1205,17 @@ public: /// Fix up the placeholder we may add in genAlternativeCodeSequence(). virtual void - finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, + finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl &InsInstrs) const {} /// Return true when a code sequence can improve throughput. It /// should be called only for instructions in loops. /// \param Pattern - combiner pattern - virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const; + virtual bool isThroughputPattern(unsigned Pattern) const; + + /// Return the objective of a combiner pattern. + /// \param Pattern - combiner pattern + virtual CombinerObjective getCombinerObjective(unsigned Pattern) const; /// Return true if the input \P Inst is part of a chain of dependent ops /// that are suitable for reassociation, otherwise return false. @@ -1256,7 +1259,7 @@ public: /// \param InstIdxForVirtReg - map of virtual register to instruction in /// InsInstr that defines it virtual void genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstIdxForVirtReg) const; @@ -1270,8 +1273,7 @@ public: /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to /// reduce critical path length. - void reassociateOps(MachineInstr &Root, MachineInstr &Prev, - MachineCombinerPattern Pattern, + void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const; @@ -1281,8 +1283,7 @@ public: /// (new root opcode, new prev opcode) that must be used to reassociate \P /// Root and \P Prev accoring to \P Pattern. std::pair - getReassociationOpcodes(MachineCombinerPattern Pattern, - const MachineInstr &Root, + getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const; /// The limit on resource length extension we accept in MachineCombiner Pass. diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index a4c87a7678bd..ac58162bbfb4 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -99,17 +99,16 @@ private: const MachineBasicBlock &MBB); unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot, MachineTraceMetrics::Trace BlockTrace); - bool - improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root, - MachineTraceMetrics::Trace BlockTrace, - SmallVectorImpl &InsInstrs, - SmallVectorImpl &DelInstrs, - DenseMap &InstrIdxForVirtReg, - MachineCombinerPattern Pattern, bool SlackIsAccurate); + bool improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root, + MachineTraceMetrics::Trace BlockTrace, + SmallVectorImpl &InsInstrs, + SmallVectorImpl &DelInstrs, + DenseMap &InstrIdxForVirtReg, + unsigned Pattern, bool SlackIsAccurate); bool reduceRegisterPressure(MachineInstr &Root, MachineBasicBlock *MBB, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, - MachineCombinerPattern Pattern); + unsigned Pattern); bool preservesResourceLen(MachineBasicBlock *MBB, MachineTraceMetrics::Trace BlockTrace, SmallVectorImpl &InsInstrs, @@ -123,7 +122,8 @@ private: MachineTraceMetrics::Trace BlockTrace); void verifyPatternOrder(MachineBasicBlock *MBB, MachineInstr &Root, - SmallVector &Patterns); + SmallVector &Patterns); + CombinerObjective getCombinerObjective(unsigned Pattern); }; } @@ -290,36 +290,17 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot, return NewRootLatency; } -/// The combiner's goal may differ based on which pattern it is attempting -/// to optimize. -enum class CombinerObjective { - MustReduceDepth, // The data dependency chain must be improved. - MustReduceRegisterPressure, // The register pressure must be reduced. - Default // The critical path must not be lengthened. -}; - -static CombinerObjective getCombinerObjective(MachineCombinerPattern P) { +CombinerObjective MachineCombiner::getCombinerObjective(unsigned Pattern) { // TODO: If C++ ever gets a real enum class, make this part of the // MachineCombinerPattern class. - switch (P) { + switch (Pattern) { case MachineCombinerPattern::REASSOC_AX_BY: case MachineCombinerPattern::REASSOC_AX_YB: case MachineCombinerPattern::REASSOC_XA_BY: case MachineCombinerPattern::REASSOC_XA_YB: - case MachineCombinerPattern::REASSOC_XY_AMM_BMM: - case MachineCombinerPattern::REASSOC_XMM_AMM_BMM: - case MachineCombinerPattern::SUBADD_OP1: - case MachineCombinerPattern::SUBADD_OP2: - case MachineCombinerPattern::FMADD_AX: - case MachineCombinerPattern::FMADD_XA: - case MachineCombinerPattern::FMSUB: - case MachineCombinerPattern::FNMSUB: return CombinerObjective::MustReduceDepth; - case MachineCombinerPattern::REASSOC_XY_BCA: - case MachineCombinerPattern::REASSOC_XY_BAC: - return CombinerObjective::MustReduceRegisterPressure; default: - return CombinerObjective::Default; + return TII->getCombinerObjective(Pattern); } } @@ -349,8 +330,7 @@ std::pair MachineCombiner::getLatenciesForInstrSequences( bool MachineCombiner::reduceRegisterPressure( MachineInstr &Root, MachineBasicBlock *MBB, SmallVectorImpl &InsInstrs, - SmallVectorImpl &DelInstrs, - MachineCombinerPattern Pattern) { + SmallVectorImpl &DelInstrs, unsigned Pattern) { // FIXME: for now, we don't do any check for the register pressure patterns. // We treat them as always profitable. But we can do better if we make // RegPressureTracker class be aware of TIE attribute. Then we can get an @@ -368,8 +348,7 @@ bool MachineCombiner::improvesCriticalPathLen( MachineTraceMetrics::Trace BlockTrace, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, - DenseMap &InstrIdxForVirtReg, - MachineCombinerPattern Pattern, + DenseMap &InstrIdxForVirtReg, unsigned Pattern, bool SlackIsAccurate) { // Get depth and latency of NewRoot and Root. unsigned NewRootDepth = @@ -493,13 +472,14 @@ bool MachineCombiner::preservesResourceLen( /// \param Pattern is used to call target hook finalizeInsInstrs /// \param IncrementalUpdate if true, compute instruction depths incrementally, /// otherwise invalidate the trace -static void insertDeleteInstructions( - MachineBasicBlock *MBB, MachineInstr &MI, - SmallVectorImpl &InsInstrs, - SmallVectorImpl &DelInstrs, - MachineTraceMetrics::Ensemble *TraceEnsemble, - SparseSet &RegUnits, const TargetInstrInfo *TII, - MachineCombinerPattern Pattern, bool IncrementalUpdate) { +static void +insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI, + SmallVectorImpl &InsInstrs, + SmallVectorImpl &DelInstrs, + MachineTraceMetrics::Ensemble *TraceEnsemble, + SparseSet &RegUnits, + const TargetInstrInfo *TII, unsigned Pattern, + bool IncrementalUpdate) { // If we want to fix up some placeholder for some target, do it now. // We need this because in genAlternativeCodeSequence, we have not decided the // better pattern InsInstrs or DelInstrs, so we don't want generate some @@ -534,9 +514,9 @@ static void insertDeleteInstructions( // Check that the difference between original and new latency is decreasing for // later patterns. This helps to discover sub-optimal pattern orderings. -void MachineCombiner::verifyPatternOrder( - MachineBasicBlock *MBB, MachineInstr &Root, - SmallVector &Patterns) { +void MachineCombiner::verifyPatternOrder(MachineBasicBlock *MBB, + MachineInstr &Root, + SmallVector &Patterns) { long PrevLatencyDiff = std::numeric_limits::max(); (void)PrevLatencyDiff; // Variable is used in assert only. for (auto P : Patterns) { @@ -590,7 +570,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) { while (BlockIter != MBB->end()) { auto &MI = *BlockIter++; - SmallVector Patterns; + SmallVector Patterns; // The motivating example is: // // MUL Other MUL_op1 MUL_op2 Other diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 9fbd516acea8..7d77e5d1a1ff 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -919,7 +919,7 @@ bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst, // instruction is known to not increase the critical path, then don't match // that pattern. bool TargetInstrInfo::getMachineCombinerPatterns( - MachineInstr &Root, SmallVectorImpl &Patterns, + MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const { bool Commute; if (isReassociationCandidate(Root, Commute)) { @@ -941,13 +941,17 @@ bool TargetInstrInfo::getMachineCombinerPatterns( } /// Return true when a code sequence can improve loop throughput. -bool -TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const { +bool TargetInstrInfo::isThroughputPattern(unsigned Pattern) const { return false; } +CombinerObjective +TargetInstrInfo::getCombinerObjective(unsigned Pattern) const { + return CombinerObjective::Default; +} + std::pair -TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern, +TargetInstrInfo::getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const { bool AssocCommutRoot = isAssociativeAndCommutative(Root); @@ -1036,7 +1040,7 @@ TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern, // Return a pair of boolean flags showing if the new root and new prev operands // must be swapped. See visual example of the rule in // TargetInstrInfo::getReassociationOpcodes. -static std::pair mustSwapOperands(MachineCombinerPattern Pattern) { +static std::pair mustSwapOperands(unsigned Pattern) { switch (Pattern) { default: llvm_unreachable("Unexpected pattern"); @@ -1054,8 +1058,7 @@ static std::pair mustSwapOperands(MachineCombinerPattern Pattern) { /// Attempt the reassociation transformation to reduce critical path length. /// See the above comments before getMachineCombinerPatterns(). void TargetInstrInfo::reassociateOps( - MachineInstr &Root, MachineInstr &Prev, - MachineCombinerPattern Pattern, + MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { @@ -1177,7 +1180,7 @@ void TargetInstrInfo::reassociateOps( } void TargetInstrInfo::genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstIdxForVirtReg) const { diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 9783b3321946..92647cb40525 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -6043,7 +6043,7 @@ bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst, /// Find instructions that can be turned into madd. static bool getMaddPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns) { + SmallVectorImpl &Patterns) { unsigned Opc = Root.getOpcode(); MachineBasicBlock &MBB = *Root.getParent(); bool Found = false; @@ -6064,21 +6064,21 @@ static bool getMaddPatterns(MachineInstr &Root, } auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, - MachineCombinerPattern Pattern) { + unsigned Pattern) { if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { Patterns.push_back(Pattern); Found = true; } }; - auto setVFound = [&](int Opcode, int Operand, MachineCombinerPattern Pattern) { + auto setVFound = [&](int Opcode, int Operand, unsigned Pattern) { if (canCombine(MBB, Root.getOperand(Operand), Opcode)) { Patterns.push_back(Pattern); Found = true; } }; - typedef MachineCombinerPattern MCP; + typedef AArch64MachineCombinerPattern MCP; switch (Opc) { default: @@ -6184,7 +6184,7 @@ static bool getMaddPatterns(MachineInstr &Root, /// Find instructions that can be turned into madd. static bool getFMAPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns) { + SmallVectorImpl &Patterns) { if (!isCombineInstrCandidateFP(Root)) return false; @@ -6192,8 +6192,7 @@ static bool getFMAPatterns(MachineInstr &Root, MachineBasicBlock &MBB = *Root.getParent(); bool Found = false; - auto Match = [&](int Opcode, int Operand, - MachineCombinerPattern Pattern) -> bool { + auto Match = [&](int Opcode, int Operand, unsigned Pattern) -> bool { if (canCombineWithFMUL(MBB, Root.getOperand(Operand), Opcode)) { Patterns.push_back(Pattern); return true; @@ -6201,7 +6200,7 @@ static bool getFMAPatterns(MachineInstr &Root, return false; }; - typedef MachineCombinerPattern MCP; + typedef AArch64MachineCombinerPattern MCP; switch (Root.getOpcode()) { default: @@ -6327,12 +6326,11 @@ static bool getFMAPatterns(MachineInstr &Root, } static bool getFMULPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns) { + SmallVectorImpl &Patterns) { MachineBasicBlock &MBB = *Root.getParent(); bool Found = false; - auto Match = [&](unsigned Opcode, int Operand, - MachineCombinerPattern Pattern) -> bool { + auto Match = [&](unsigned Opcode, int Operand, unsigned Pattern) -> bool { MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); MachineOperand &MO = Root.getOperand(Operand); MachineInstr *MI = nullptr; @@ -6349,7 +6347,7 @@ static bool getFMULPatterns(MachineInstr &Root, return false; }; - typedef MachineCombinerPattern MCP; + typedef AArch64MachineCombinerPattern MCP; switch (Root.getOpcode()) { default: @@ -6380,12 +6378,12 @@ static bool getFMULPatterns(MachineInstr &Root, } static bool getFNEGPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns) { + SmallVectorImpl &Patterns) { unsigned Opc = Root.getOpcode(); MachineBasicBlock &MBB = *Root.getParent(); MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); - auto Match = [&](unsigned Opcode, MachineCombinerPattern Pattern) -> bool { + auto Match = [&](unsigned Opcode, unsigned Pattern) -> bool { MachineOperand &MO = Root.getOperand(1); MachineInstr *MI = MRI.getUniqueVRegDef(MO.getReg()); if (MI != nullptr && (MI->getOpcode() == Opcode) && @@ -6404,9 +6402,9 @@ static bool getFNEGPatterns(MachineInstr &Root, default: break; case AArch64::FNEGDr: - return Match(AArch64::FMADDDrrr, MachineCombinerPattern::FNMADD); + return Match(AArch64::FMADDDrrr, AArch64MachineCombinerPattern::FNMADD); case AArch64::FNEGSr: - return Match(AArch64::FMADDSrrr, MachineCombinerPattern::FNMADD); + return Match(AArch64::FMADDSrrr, AArch64MachineCombinerPattern::FNMADD); } return false; @@ -6415,116 +6413,115 @@ static bool getFNEGPatterns(MachineInstr &Root, /// Return true when a code sequence can improve throughput. It /// should be called only for instructions in loops. /// \param Pattern - combiner pattern -bool AArch64InstrInfo::isThroughputPattern( - MachineCombinerPattern Pattern) const { +bool AArch64InstrInfo::isThroughputPattern(unsigned Pattern) const { switch (Pattern) { default: break; - case MachineCombinerPattern::FMULADDH_OP1: - case MachineCombinerPattern::FMULADDH_OP2: - case MachineCombinerPattern::FMULSUBH_OP1: - case MachineCombinerPattern::FMULSUBH_OP2: - case MachineCombinerPattern::FMULADDS_OP1: - case MachineCombinerPattern::FMULADDS_OP2: - case MachineCombinerPattern::FMULSUBS_OP1: - case MachineCombinerPattern::FMULSUBS_OP2: - case MachineCombinerPattern::FMULADDD_OP1: - case MachineCombinerPattern::FMULADDD_OP2: - case MachineCombinerPattern::FMULSUBD_OP1: - case MachineCombinerPattern::FMULSUBD_OP2: - case MachineCombinerPattern::FNMULSUBH_OP1: - case MachineCombinerPattern::FNMULSUBS_OP1: - case MachineCombinerPattern::FNMULSUBD_OP1: - case MachineCombinerPattern::FMLAv4i16_indexed_OP1: - case MachineCombinerPattern::FMLAv4i16_indexed_OP2: - case MachineCombinerPattern::FMLAv8i16_indexed_OP1: - case MachineCombinerPattern::FMLAv8i16_indexed_OP2: - case MachineCombinerPattern::FMLAv1i32_indexed_OP1: - case MachineCombinerPattern::FMLAv1i32_indexed_OP2: - case MachineCombinerPattern::FMLAv1i64_indexed_OP1: - case MachineCombinerPattern::FMLAv1i64_indexed_OP2: - case MachineCombinerPattern::FMLAv4f16_OP2: - case MachineCombinerPattern::FMLAv4f16_OP1: - case MachineCombinerPattern::FMLAv8f16_OP1: - case MachineCombinerPattern::FMLAv8f16_OP2: - case MachineCombinerPattern::FMLAv2f32_OP2: - case MachineCombinerPattern::FMLAv2f32_OP1: - case MachineCombinerPattern::FMLAv2f64_OP1: - case MachineCombinerPattern::FMLAv2f64_OP2: - case MachineCombinerPattern::FMLAv2i32_indexed_OP1: - case MachineCombinerPattern::FMLAv2i32_indexed_OP2: - case MachineCombinerPattern::FMLAv2i64_indexed_OP1: - case MachineCombinerPattern::FMLAv2i64_indexed_OP2: - case MachineCombinerPattern::FMLAv4f32_OP1: - case MachineCombinerPattern::FMLAv4f32_OP2: - case MachineCombinerPattern::FMLAv4i32_indexed_OP1: - case MachineCombinerPattern::FMLAv4i32_indexed_OP2: - case MachineCombinerPattern::FMLSv4i16_indexed_OP1: - case MachineCombinerPattern::FMLSv4i16_indexed_OP2: - case MachineCombinerPattern::FMLSv8i16_indexed_OP1: - case MachineCombinerPattern::FMLSv8i16_indexed_OP2: - case MachineCombinerPattern::FMLSv1i32_indexed_OP2: - case MachineCombinerPattern::FMLSv1i64_indexed_OP2: - case MachineCombinerPattern::FMLSv2i32_indexed_OP2: - case MachineCombinerPattern::FMLSv2i64_indexed_OP2: - case MachineCombinerPattern::FMLSv4f16_OP1: - case MachineCombinerPattern::FMLSv4f16_OP2: - case MachineCombinerPattern::FMLSv8f16_OP1: - case MachineCombinerPattern::FMLSv8f16_OP2: - case MachineCombinerPattern::FMLSv2f32_OP2: - case MachineCombinerPattern::FMLSv2f64_OP2: - case MachineCombinerPattern::FMLSv4i32_indexed_OP2: - case MachineCombinerPattern::FMLSv4f32_OP2: - case MachineCombinerPattern::FMULv2i32_indexed_OP1: - case MachineCombinerPattern::FMULv2i32_indexed_OP2: - case MachineCombinerPattern::FMULv2i64_indexed_OP1: - case MachineCombinerPattern::FMULv2i64_indexed_OP2: - case MachineCombinerPattern::FMULv4i16_indexed_OP1: - case MachineCombinerPattern::FMULv4i16_indexed_OP2: - case MachineCombinerPattern::FMULv4i32_indexed_OP1: - case MachineCombinerPattern::FMULv4i32_indexed_OP2: - case MachineCombinerPattern::FMULv8i16_indexed_OP1: - case MachineCombinerPattern::FMULv8i16_indexed_OP2: - case MachineCombinerPattern::MULADDv8i8_OP1: - case MachineCombinerPattern::MULADDv8i8_OP2: - case MachineCombinerPattern::MULADDv16i8_OP1: - case MachineCombinerPattern::MULADDv16i8_OP2: - case MachineCombinerPattern::MULADDv4i16_OP1: - case MachineCombinerPattern::MULADDv4i16_OP2: - case MachineCombinerPattern::MULADDv8i16_OP1: - case MachineCombinerPattern::MULADDv8i16_OP2: - case MachineCombinerPattern::MULADDv2i32_OP1: - case MachineCombinerPattern::MULADDv2i32_OP2: - case MachineCombinerPattern::MULADDv4i32_OP1: - case MachineCombinerPattern::MULADDv4i32_OP2: - case MachineCombinerPattern::MULSUBv8i8_OP1: - case MachineCombinerPattern::MULSUBv8i8_OP2: - case MachineCombinerPattern::MULSUBv16i8_OP1: - case MachineCombinerPattern::MULSUBv16i8_OP2: - case MachineCombinerPattern::MULSUBv4i16_OP1: - case MachineCombinerPattern::MULSUBv4i16_OP2: - case MachineCombinerPattern::MULSUBv8i16_OP1: - case MachineCombinerPattern::MULSUBv8i16_OP2: - case MachineCombinerPattern::MULSUBv2i32_OP1: - case MachineCombinerPattern::MULSUBv2i32_OP2: - case MachineCombinerPattern::MULSUBv4i32_OP1: - case MachineCombinerPattern::MULSUBv4i32_OP2: - case MachineCombinerPattern::MULADDv4i16_indexed_OP1: - case MachineCombinerPattern::MULADDv4i16_indexed_OP2: - case MachineCombinerPattern::MULADDv8i16_indexed_OP1: - case MachineCombinerPattern::MULADDv8i16_indexed_OP2: - case MachineCombinerPattern::MULADDv2i32_indexed_OP1: - case MachineCombinerPattern::MULADDv2i32_indexed_OP2: - case MachineCombinerPattern::MULADDv4i32_indexed_OP1: - case MachineCombinerPattern::MULADDv4i32_indexed_OP2: - case MachineCombinerPattern::MULSUBv4i16_indexed_OP1: - case MachineCombinerPattern::MULSUBv4i16_indexed_OP2: - case MachineCombinerPattern::MULSUBv8i16_indexed_OP1: - case MachineCombinerPattern::MULSUBv8i16_indexed_OP2: - case MachineCombinerPattern::MULSUBv2i32_indexed_OP1: - case MachineCombinerPattern::MULSUBv2i32_indexed_OP2: - case MachineCombinerPattern::MULSUBv4i32_indexed_OP1: - case MachineCombinerPattern::MULSUBv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMULADDH_OP1: + case AArch64MachineCombinerPattern::FMULADDH_OP2: + case AArch64MachineCombinerPattern::FMULSUBH_OP1: + case AArch64MachineCombinerPattern::FMULSUBH_OP2: + case AArch64MachineCombinerPattern::FMULADDS_OP1: + case AArch64MachineCombinerPattern::FMULADDS_OP2: + case AArch64MachineCombinerPattern::FMULSUBS_OP1: + case AArch64MachineCombinerPattern::FMULSUBS_OP2: + case AArch64MachineCombinerPattern::FMULADDD_OP1: + case AArch64MachineCombinerPattern::FMULADDD_OP2: + case AArch64MachineCombinerPattern::FMULSUBD_OP1: + case AArch64MachineCombinerPattern::FMULSUBD_OP2: + case AArch64MachineCombinerPattern::FNMULSUBH_OP1: + case AArch64MachineCombinerPattern::FNMULSUBS_OP1: + case AArch64MachineCombinerPattern::FNMULSUBD_OP1: + case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv4f16_OP2: + case AArch64MachineCombinerPattern::FMLAv4f16_OP1: + case AArch64MachineCombinerPattern::FMLAv8f16_OP1: + case AArch64MachineCombinerPattern::FMLAv8f16_OP2: + case AArch64MachineCombinerPattern::FMLAv2f32_OP2: + case AArch64MachineCombinerPattern::FMLAv2f32_OP1: + case AArch64MachineCombinerPattern::FMLAv2f64_OP1: + case AArch64MachineCombinerPattern::FMLAv2f64_OP2: + case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv4f32_OP1: + case AArch64MachineCombinerPattern::FMLAv4f32_OP2: + case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv1i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv1i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv4f16_OP1: + case AArch64MachineCombinerPattern::FMLSv4f16_OP2: + case AArch64MachineCombinerPattern::FMLSv8f16_OP1: + case AArch64MachineCombinerPattern::FMLSv8f16_OP2: + case AArch64MachineCombinerPattern::FMLSv2f32_OP2: + case AArch64MachineCombinerPattern::FMLSv2f64_OP2: + case AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv4f32_OP2: + case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv8i8_OP1: + case AArch64MachineCombinerPattern::MULADDv8i8_OP2: + case AArch64MachineCombinerPattern::MULADDv16i8_OP1: + case AArch64MachineCombinerPattern::MULADDv16i8_OP2: + case AArch64MachineCombinerPattern::MULADDv4i16_OP1: + case AArch64MachineCombinerPattern::MULADDv4i16_OP2: + case AArch64MachineCombinerPattern::MULADDv8i16_OP1: + case AArch64MachineCombinerPattern::MULADDv8i16_OP2: + case AArch64MachineCombinerPattern::MULADDv2i32_OP1: + case AArch64MachineCombinerPattern::MULADDv2i32_OP2: + case AArch64MachineCombinerPattern::MULADDv4i32_OP1: + case AArch64MachineCombinerPattern::MULADDv4i32_OP2: + case AArch64MachineCombinerPattern::MULSUBv8i8_OP1: + case AArch64MachineCombinerPattern::MULSUBv8i8_OP2: + case AArch64MachineCombinerPattern::MULSUBv16i8_OP1: + case AArch64MachineCombinerPattern::MULSUBv16i8_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i16_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i16_OP2: + case AArch64MachineCombinerPattern::MULSUBv8i16_OP1: + case AArch64MachineCombinerPattern::MULSUBv8i16_OP2: + case AArch64MachineCombinerPattern::MULSUBv2i32_OP1: + case AArch64MachineCombinerPattern::MULSUBv2i32_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i32_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i32_OP2: + case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP2: return true; } // end switch (Pattern) return false; @@ -6532,8 +6529,7 @@ bool AArch64InstrInfo::isThroughputPattern( /// Find other MI combine patterns. static bool getMiscPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns) -{ + SmallVectorImpl &Patterns) { // A - (B + C) ==> (A - B) - C or (A - C) - B unsigned Opc = Root.getOpcode(); MachineBasicBlock &MBB = *Root.getParent(); @@ -6557,21 +6553,32 @@ static bool getMiscPatterns(MachineInstr &Root, canCombine(MBB, Root.getOperand(2), AArch64::ADDSWrr) || canCombine(MBB, Root.getOperand(2), AArch64::ADDXrr) || canCombine(MBB, Root.getOperand(2), AArch64::ADDSXrr)) { - Patterns.push_back(MachineCombinerPattern::SUBADD_OP1); - Patterns.push_back(MachineCombinerPattern::SUBADD_OP2); + Patterns.push_back(AArch64MachineCombinerPattern::SUBADD_OP1); + Patterns.push_back(AArch64MachineCombinerPattern::SUBADD_OP2); return true; } return false; } +CombinerObjective +AArch64InstrInfo::getCombinerObjective(unsigned Pattern) const { + switch (Pattern) { + case AArch64MachineCombinerPattern::SUBADD_OP1: + case AArch64MachineCombinerPattern::SUBADD_OP2: + return CombinerObjective::MustReduceDepth; + default: + return TargetInstrInfo::getCombinerObjective(Pattern); + } +} + /// Return true when there is potentially a faster code sequence for an /// instruction chain ending in \p Root. All potential patterns are listed in /// the \p Pattern vector. Pattern should be sorted in priority order since the /// pattern evaluator stops checking as soon as it finds a faster sequence. bool AArch64InstrInfo::getMachineCombinerPatterns( - MachineInstr &Root, SmallVectorImpl &Patterns, + MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const { // Integer patterns if (getMaddPatterns(Root, Patterns)) @@ -6930,7 +6937,7 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI, /// this function generates the instructions that could replace the /// original code sequence void AArch64InstrInfo::genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { @@ -6948,25 +6955,25 @@ void AArch64InstrInfo::genAlternativeCodeSequence( TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg); return; - case MachineCombinerPattern::SUBADD_OP1: + case AArch64MachineCombinerPattern::SUBADD_OP1: // A - (B + C) // ==> (A - B) - C genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 1, InstrIdxForVirtReg); break; - case MachineCombinerPattern::SUBADD_OP2: + case AArch64MachineCombinerPattern::SUBADD_OP2: // A - (B + C) // ==> (A - C) - B genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 2, InstrIdxForVirtReg); break; - case MachineCombinerPattern::MULADDW_OP1: - case MachineCombinerPattern::MULADDX_OP1: + case AArch64MachineCombinerPattern::MULADDW_OP1: + case AArch64MachineCombinerPattern::MULADDX_OP1: // MUL I=A,B,0 // ADD R,I,C // ==> MADD R,A,B,C // --- Create(MADD); - if (Pattern == MachineCombinerPattern::MULADDW_OP1) { + if (Pattern == AArch64MachineCombinerPattern::MULADDW_OP1) { Opc = AArch64::MADDWrrr; RC = &AArch64::GPR32RegClass; } else { @@ -6975,13 +6982,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDW_OP2: - case MachineCombinerPattern::MULADDX_OP2: + case AArch64MachineCombinerPattern::MULADDW_OP2: + case AArch64MachineCombinerPattern::MULADDX_OP2: // MUL I=A,B,0 // ADD R,C,I // ==> MADD R,A,B,C // --- Create(MADD); - if (Pattern == MachineCombinerPattern::MULADDW_OP2) { + if (Pattern == AArch64MachineCombinerPattern::MULADDW_OP2) { Opc = AArch64::MADDWrrr; RC = &AArch64::GPR32RegClass; } else { @@ -6990,8 +6997,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDWI_OP1: - case MachineCombinerPattern::MULADDXI_OP1: { + case AArch64MachineCombinerPattern::MULADDWI_OP1: + case AArch64MachineCombinerPattern::MULADDXI_OP1: { // MUL I=A,B,0 // ADD R,I,Imm // ==> MOV V, Imm @@ -6999,7 +7006,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( // --- Create(MADD); const TargetRegisterClass *OrrRC; unsigned BitSize, OrrOpc, ZeroReg; - if (Pattern == MachineCombinerPattern::MULADDWI_OP1) { + if (Pattern == AArch64MachineCombinerPattern::MULADDWI_OP1) { OrrOpc = AArch64::ORRWri; OrrRC = &AArch64::GPR32spRegClass; BitSize = 32; @@ -7052,8 +7059,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); break; } - case MachineCombinerPattern::MULSUBW_OP1: - case MachineCombinerPattern::MULSUBX_OP1: { + case AArch64MachineCombinerPattern::MULSUBW_OP1: + case AArch64MachineCombinerPattern::MULSUBX_OP1: { // MUL I=A,B,0 // SUB R,I, C // ==> SUB V, 0, C @@ -7061,7 +7068,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( // --- Create(MADD); const TargetRegisterClass *SubRC; unsigned SubOpc, ZeroReg; - if (Pattern == MachineCombinerPattern::MULSUBW_OP1) { + if (Pattern == AArch64MachineCombinerPattern::MULSUBW_OP1) { SubOpc = AArch64::SUBWrr; SubRC = &AArch64::GPR32spRegClass; ZeroReg = AArch64::WZR; @@ -7085,13 +7092,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence( MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); break; } - case MachineCombinerPattern::MULSUBW_OP2: - case MachineCombinerPattern::MULSUBX_OP2: + case AArch64MachineCombinerPattern::MULSUBW_OP2: + case AArch64MachineCombinerPattern::MULSUBX_OP2: // MUL I=A,B,0 // SUB R,C,I // ==> MSUB R,A,B,C (computes C - A*B) // --- Create(MSUB); - if (Pattern == MachineCombinerPattern::MULSUBW_OP2) { + if (Pattern == AArch64MachineCombinerPattern::MULSUBW_OP2) { Opc = AArch64::MSUBWrrr; RC = &AArch64::GPR32RegClass; } else { @@ -7100,8 +7107,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBWI_OP1: - case MachineCombinerPattern::MULSUBXI_OP1: { + case AArch64MachineCombinerPattern::MULSUBWI_OP1: + case AArch64MachineCombinerPattern::MULSUBXI_OP1: { // MUL I=A,B,0 // SUB R,I, Imm // ==> MOV V, -Imm @@ -7109,7 +7116,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( // --- Create(MADD); const TargetRegisterClass *OrrRC; unsigned BitSize, OrrOpc, ZeroReg; - if (Pattern == MachineCombinerPattern::MULSUBWI_OP1) { + if (Pattern == AArch64MachineCombinerPattern::MULSUBWI_OP1) { OrrOpc = AArch64::ORRWri; OrrRC = &AArch64::GPR32spRegClass; BitSize = 32; @@ -7162,318 +7169,318 @@ void AArch64InstrInfo::genAlternativeCodeSequence( break; } - case MachineCombinerPattern::MULADDv8i8_OP1: + case AArch64MachineCombinerPattern::MULADDv8i8_OP1: Opc = AArch64::MLAv8i8; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv8i8_OP2: + case AArch64MachineCombinerPattern::MULADDv8i8_OP2: Opc = AArch64::MLAv8i8; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv16i8_OP1: + case AArch64MachineCombinerPattern::MULADDv16i8_OP1: Opc = AArch64::MLAv16i8; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv16i8_OP2: + case AArch64MachineCombinerPattern::MULADDv16i8_OP2: Opc = AArch64::MLAv16i8; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i16_OP1: + case AArch64MachineCombinerPattern::MULADDv4i16_OP1: Opc = AArch64::MLAv4i16; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i16_OP2: + case AArch64MachineCombinerPattern::MULADDv4i16_OP2: Opc = AArch64::MLAv4i16; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv8i16_OP1: + case AArch64MachineCombinerPattern::MULADDv8i16_OP1: Opc = AArch64::MLAv8i16; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv8i16_OP2: + case AArch64MachineCombinerPattern::MULADDv8i16_OP2: Opc = AArch64::MLAv8i16; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv2i32_OP1: + case AArch64MachineCombinerPattern::MULADDv2i32_OP1: Opc = AArch64::MLAv2i32; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv2i32_OP2: + case AArch64MachineCombinerPattern::MULADDv2i32_OP2: Opc = AArch64::MLAv2i32; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i32_OP1: + case AArch64MachineCombinerPattern::MULADDv4i32_OP1: Opc = AArch64::MLAv4i32; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i32_OP2: + case AArch64MachineCombinerPattern::MULADDv4i32_OP2: Opc = AArch64::MLAv4i32; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv8i8_OP1: + case AArch64MachineCombinerPattern::MULSUBv8i8_OP1: Opc = AArch64::MLAv8i8; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i8, RC); break; - case MachineCombinerPattern::MULSUBv8i8_OP2: + case AArch64MachineCombinerPattern::MULSUBv8i8_OP2: Opc = AArch64::MLSv8i8; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv16i8_OP1: + case AArch64MachineCombinerPattern::MULSUBv16i8_OP1: Opc = AArch64::MLAv16i8; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv16i8, RC); break; - case MachineCombinerPattern::MULSUBv16i8_OP2: + case AArch64MachineCombinerPattern::MULSUBv16i8_OP2: Opc = AArch64::MLSv16i8; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv4i16_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i16_OP1: Opc = AArch64::MLAv4i16; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16, RC); break; - case MachineCombinerPattern::MULSUBv4i16_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i16_OP2: Opc = AArch64::MLSv4i16; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv8i16_OP1: + case AArch64MachineCombinerPattern::MULSUBv8i16_OP1: Opc = AArch64::MLAv8i16; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16, RC); break; - case MachineCombinerPattern::MULSUBv8i16_OP2: + case AArch64MachineCombinerPattern::MULSUBv8i16_OP2: Opc = AArch64::MLSv8i16; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv2i32_OP1: + case AArch64MachineCombinerPattern::MULSUBv2i32_OP1: Opc = AArch64::MLAv2i32; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32, RC); break; - case MachineCombinerPattern::MULSUBv2i32_OP2: + case AArch64MachineCombinerPattern::MULSUBv2i32_OP2: Opc = AArch64::MLSv2i32; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv4i32_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i32_OP1: Opc = AArch64::MLAv4i32; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAccNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32, RC); break; - case MachineCombinerPattern::MULSUBv4i32_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i32_OP2: Opc = AArch64::MLSv4i32; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyAcc(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP1: Opc = AArch64::MLAv4i16_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv4i16_indexed_OP2: Opc = AArch64::MLAv4i16_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP1: Opc = AArch64::MLAv8i16_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv8i16_indexed_OP2: Opc = AArch64::MLAv8i16_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP1: Opc = AArch64::MLAv2i32_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv2i32_indexed_OP2: Opc = AArch64::MLAv2i32_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP1: Opc = AArch64::MLAv4i32_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::MULADDv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULADDv4i32_indexed_OP2: Opc = AArch64::MLAv4i32_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP1: Opc = AArch64::MLAv4i16_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i16, RC); break; - case MachineCombinerPattern::MULSUBv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i16_indexed_OP2: Opc = AArch64::MLSv4i16_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP1: Opc = AArch64::MLAv8i16_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv8i16, RC); break; - case MachineCombinerPattern::MULSUBv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv8i16_indexed_OP2: Opc = AArch64::MLSv8i16_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP1: Opc = AArch64::MLAv2i32_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv2i32, RC); break; - case MachineCombinerPattern::MULSUBv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv2i32_indexed_OP2: Opc = AArch64::MLSv2i32_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::MULSUBv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP1: Opc = AArch64::MLAv4i32_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdxNeg(MF, MRI, TII, Root, InsInstrs, InstrIdxForVirtReg, 1, Opc, AArch64::NEGv4i32, RC); break; - case MachineCombinerPattern::MULSUBv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::MULSUBv4i32_indexed_OP2: Opc = AArch64::MLSv4i32_indexed; RC = &AArch64::FPR128RegClass; MUL = genFusedMultiplyIdx(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; // Floating Point Support - case MachineCombinerPattern::FMULADDH_OP1: + case AArch64MachineCombinerPattern::FMULADDH_OP1: Opc = AArch64::FMADDHrrr; RC = &AArch64::FPR16RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FMULADDS_OP1: + case AArch64MachineCombinerPattern::FMULADDS_OP1: Opc = AArch64::FMADDSrrr; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FMULADDD_OP1: + case AArch64MachineCombinerPattern::FMULADDD_OP1: Opc = AArch64::FMADDDrrr; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FMULADDH_OP2: + case AArch64MachineCombinerPattern::FMULADDH_OP2: Opc = AArch64::FMADDHrrr; RC = &AArch64::FPR16RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::FMULADDS_OP2: + case AArch64MachineCombinerPattern::FMULADDS_OP2: Opc = AArch64::FMADDSrrr; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::FMULADDD_OP2: + case AArch64MachineCombinerPattern::FMULADDD_OP2: Opc = AArch64::FMADDDrrr; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::FMLAv1i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP1: Opc = AArch64::FMLAv1i32_indexed; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv1i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv1i32_indexed_OP2: Opc = AArch64::FMLAv1i32_indexed; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv1i64_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP1: Opc = AArch64::FMLAv1i64_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv1i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv1i64_indexed_OP2: Opc = AArch64::FMLAv1i64_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP1: RC = &AArch64::FPR64RegClass; Opc = AArch64::FMLAv4i16_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv4f16_OP1: + case AArch64MachineCombinerPattern::FMLAv4f16_OP1: RC = &AArch64::FPR64RegClass; Opc = AArch64::FMLAv4f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Accumulator); break; - case MachineCombinerPattern::FMLAv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv4i16_indexed_OP2: RC = &AArch64::FPR64RegClass; Opc = AArch64::FMLAv4i16_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv4f16_OP2: + case AArch64MachineCombinerPattern::FMLAv4f16_OP2: RC = &AArch64::FPR64RegClass; Opc = AArch64::FMLAv4f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Accumulator); break; - case MachineCombinerPattern::FMLAv2i32_indexed_OP1: - case MachineCombinerPattern::FMLAv2f32_OP1: + case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv2f32_OP1: RC = &AArch64::FPR64RegClass; - if (Pattern == MachineCombinerPattern::FMLAv2i32_indexed_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP1) { Opc = AArch64::FMLAv2i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); @@ -7483,10 +7490,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence( FMAInstKind::Accumulator); } break; - case MachineCombinerPattern::FMLAv2i32_indexed_OP2: - case MachineCombinerPattern::FMLAv2f32_OP2: + case AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv2f32_OP2: RC = &AArch64::FPR64RegClass; - if (Pattern == MachineCombinerPattern::FMLAv2i32_indexed_OP2) { + if (Pattern == AArch64MachineCombinerPattern::FMLAv2i32_indexed_OP2) { Opc = AArch64::FMLAv2i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); @@ -7497,35 +7504,35 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; - case MachineCombinerPattern::FMLAv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP1: RC = &AArch64::FPR128RegClass; Opc = AArch64::FMLAv8i16_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv8f16_OP1: + case AArch64MachineCombinerPattern::FMLAv8f16_OP1: RC = &AArch64::FPR128RegClass; Opc = AArch64::FMLAv8f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Accumulator); break; - case MachineCombinerPattern::FMLAv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv8i16_indexed_OP2: RC = &AArch64::FPR128RegClass; Opc = AArch64::FMLAv8i16_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLAv8f16_OP2: + case AArch64MachineCombinerPattern::FMLAv8f16_OP2: RC = &AArch64::FPR128RegClass; Opc = AArch64::FMLAv8f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Accumulator); break; - case MachineCombinerPattern::FMLAv2i64_indexed_OP1: - case MachineCombinerPattern::FMLAv2f64_OP1: + case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv2f64_OP1: RC = &AArch64::FPR128RegClass; - if (Pattern == MachineCombinerPattern::FMLAv2i64_indexed_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP1) { Opc = AArch64::FMLAv2i64_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); @@ -7535,10 +7542,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence( FMAInstKind::Accumulator); } break; - case MachineCombinerPattern::FMLAv2i64_indexed_OP2: - case MachineCombinerPattern::FMLAv2f64_OP2: + case AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv2f64_OP2: RC = &AArch64::FPR128RegClass; - if (Pattern == MachineCombinerPattern::FMLAv2i64_indexed_OP2) { + if (Pattern == AArch64MachineCombinerPattern::FMLAv2i64_indexed_OP2) { Opc = AArch64::FMLAv2i64_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); @@ -7549,10 +7556,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; - case MachineCombinerPattern::FMLAv4i32_indexed_OP1: - case MachineCombinerPattern::FMLAv4f32_OP1: + case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMLAv4f32_OP1: RC = &AArch64::FPR128RegClass; - if (Pattern == MachineCombinerPattern::FMLAv4i32_indexed_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP1) { Opc = AArch64::FMLAv4i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed); @@ -7563,10 +7570,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; - case MachineCombinerPattern::FMLAv4i32_indexed_OP2: - case MachineCombinerPattern::FMLAv4f32_OP2: + case AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLAv4f32_OP2: RC = &AArch64::FPR128RegClass; - if (Pattern == MachineCombinerPattern::FMLAv4i32_indexed_OP2) { + if (Pattern == AArch64MachineCombinerPattern::FMLAv4i32_indexed_OP2) { Opc = AArch64::FMLAv4i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); @@ -7577,70 +7584,70 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; - case MachineCombinerPattern::FMULSUBH_OP1: + case AArch64MachineCombinerPattern::FMULSUBH_OP1: Opc = AArch64::FNMSUBHrrr; RC = &AArch64::FPR16RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FMULSUBS_OP1: + case AArch64MachineCombinerPattern::FMULSUBS_OP1: Opc = AArch64::FNMSUBSrrr; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FMULSUBD_OP1: + case AArch64MachineCombinerPattern::FMULSUBD_OP1: Opc = AArch64::FNMSUBDrrr; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FNMULSUBH_OP1: + case AArch64MachineCombinerPattern::FNMULSUBH_OP1: Opc = AArch64::FNMADDHrrr; RC = &AArch64::FPR16RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FNMULSUBS_OP1: + case AArch64MachineCombinerPattern::FNMULSUBS_OP1: Opc = AArch64::FNMADDSrrr; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FNMULSUBD_OP1: + case AArch64MachineCombinerPattern::FNMULSUBD_OP1: Opc = AArch64::FNMADDDrrr; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); break; - case MachineCombinerPattern::FMULSUBH_OP2: + case AArch64MachineCombinerPattern::FMULSUBH_OP2: Opc = AArch64::FMSUBHrrr; RC = &AArch64::FPR16RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::FMULSUBS_OP2: + case AArch64MachineCombinerPattern::FMULSUBS_OP2: Opc = AArch64::FMSUBSrrr; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::FMULSUBD_OP2: + case AArch64MachineCombinerPattern::FMULSUBD_OP2: Opc = AArch64::FMSUBDrrr; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); break; - case MachineCombinerPattern::FMLSv1i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv1i32_indexed_OP2: Opc = AArch64::FMLSv1i32_indexed; RC = &AArch64::FPR32RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLSv1i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv1i64_indexed_OP2: Opc = AArch64::FMLSv1i64_indexed; RC = &AArch64::FPR64RegClass; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLSv4f16_OP1: - case MachineCombinerPattern::FMLSv4i16_indexed_OP1: { + case AArch64MachineCombinerPattern::FMLSv4f16_OP1: + case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP1: { RC = &AArch64::FPR64RegClass; Register NewVR = MRI.createVirtualRegister(RC); MachineInstrBuilder MIB1 = @@ -7648,7 +7655,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( .add(Root.getOperand(2)); InsInstrs.push_back(MIB1); InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); - if (Pattern == MachineCombinerPattern::FMLSv4f16_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv4f16_OP1) { Opc = AArch64::FMLAv4f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Accumulator, &NewVR); @@ -7659,23 +7666,23 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; } - case MachineCombinerPattern::FMLSv4f16_OP2: + case AArch64MachineCombinerPattern::FMLSv4f16_OP2: RC = &AArch64::FPR64RegClass; Opc = AArch64::FMLSv4f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Accumulator); break; - case MachineCombinerPattern::FMLSv4i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv4i16_indexed_OP2: RC = &AArch64::FPR64RegClass; Opc = AArch64::FMLSv4i16_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLSv2f32_OP2: - case MachineCombinerPattern::FMLSv2i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv2f32_OP2: + case AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP2: RC = &AArch64::FPR64RegClass; - if (Pattern == MachineCombinerPattern::FMLSv2i32_indexed_OP2) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP2) { Opc = AArch64::FMLSv2i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); @@ -7686,8 +7693,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; - case MachineCombinerPattern::FMLSv8f16_OP1: - case MachineCombinerPattern::FMLSv8i16_indexed_OP1: { + case AArch64MachineCombinerPattern::FMLSv8f16_OP1: + case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP1: { RC = &AArch64::FPR128RegClass; Register NewVR = MRI.createVirtualRegister(RC); MachineInstrBuilder MIB1 = @@ -7695,7 +7702,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( .add(Root.getOperand(2)); InsInstrs.push_back(MIB1); InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); - if (Pattern == MachineCombinerPattern::FMLSv8f16_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv8f16_OP1) { Opc = AArch64::FMLAv8f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Accumulator, &NewVR); @@ -7706,23 +7713,23 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; } - case MachineCombinerPattern::FMLSv8f16_OP2: + case AArch64MachineCombinerPattern::FMLSv8f16_OP2: RC = &AArch64::FPR128RegClass; Opc = AArch64::FMLSv8f16; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Accumulator); break; - case MachineCombinerPattern::FMLSv8i16_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv8i16_indexed_OP2: RC = &AArch64::FPR128RegClass; Opc = AArch64::FMLSv8i16_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); break; - case MachineCombinerPattern::FMLSv2f64_OP2: - case MachineCombinerPattern::FMLSv2i64_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv2f64_OP2: + case AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP2: RC = &AArch64::FPR128RegClass; - if (Pattern == MachineCombinerPattern::FMLSv2i64_indexed_OP2) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP2) { Opc = AArch64::FMLSv2i64_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); @@ -7733,10 +7740,10 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; - case MachineCombinerPattern::FMLSv4f32_OP2: - case MachineCombinerPattern::FMLSv4i32_indexed_OP2: + case AArch64MachineCombinerPattern::FMLSv4f32_OP2: + case AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP2: RC = &AArch64::FPR128RegClass; - if (Pattern == MachineCombinerPattern::FMLSv4i32_indexed_OP2) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP2) { Opc = AArch64::FMLSv4i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC, FMAInstKind::Indexed); @@ -7746,8 +7753,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( FMAInstKind::Accumulator); } break; - case MachineCombinerPattern::FMLSv2f32_OP1: - case MachineCombinerPattern::FMLSv2i32_indexed_OP1: { + case AArch64MachineCombinerPattern::FMLSv2f32_OP1: + case AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP1: { RC = &AArch64::FPR64RegClass; Register NewVR = MRI.createVirtualRegister(RC); MachineInstrBuilder MIB1 = @@ -7755,7 +7762,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( .add(Root.getOperand(2)); InsInstrs.push_back(MIB1); InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); - if (Pattern == MachineCombinerPattern::FMLSv2i32_indexed_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv2i32_indexed_OP1) { Opc = AArch64::FMLAv2i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed, &NewVR); @@ -7766,8 +7773,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; } - case MachineCombinerPattern::FMLSv4f32_OP1: - case MachineCombinerPattern::FMLSv4i32_indexed_OP1: { + case AArch64MachineCombinerPattern::FMLSv4f32_OP1: + case AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP1: { RC = &AArch64::FPR128RegClass; Register NewVR = MRI.createVirtualRegister(RC); MachineInstrBuilder MIB1 = @@ -7775,7 +7782,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( .add(Root.getOperand(2)); InsInstrs.push_back(MIB1); InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); - if (Pattern == MachineCombinerPattern::FMLSv4i32_indexed_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv4i32_indexed_OP1) { Opc = AArch64::FMLAv4i32_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed, &NewVR); @@ -7786,8 +7793,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; } - case MachineCombinerPattern::FMLSv2f64_OP1: - case MachineCombinerPattern::FMLSv2i64_indexed_OP1: { + case AArch64MachineCombinerPattern::FMLSv2f64_OP1: + case AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP1: { RC = &AArch64::FPR128RegClass; Register NewVR = MRI.createVirtualRegister(RC); MachineInstrBuilder MIB1 = @@ -7795,7 +7802,7 @@ void AArch64InstrInfo::genAlternativeCodeSequence( .add(Root.getOperand(2)); InsInstrs.push_back(MIB1); InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); - if (Pattern == MachineCombinerPattern::FMLSv2i64_indexed_OP1) { + if (Pattern == AArch64MachineCombinerPattern::FMLSv2i64_indexed_OP1) { Opc = AArch64::FMLAv2i64_indexed; MUL = genFusedMultiply(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC, FMAInstKind::Indexed, &NewVR); @@ -7806,47 +7813,52 @@ void AArch64InstrInfo::genAlternativeCodeSequence( } break; } - case MachineCombinerPattern::FMULv2i32_indexed_OP1: - case MachineCombinerPattern::FMULv2i32_indexed_OP2: { + case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv2i32_indexed_OP2: { unsigned IdxDupOp = - (Pattern == MachineCombinerPattern::FMULv2i32_indexed_OP1) ? 1 : 2; + (Pattern == AArch64MachineCombinerPattern::FMULv2i32_indexed_OP1) ? 1 + : 2; genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv2i32_indexed, &AArch64::FPR128RegClass, MRI); break; } - case MachineCombinerPattern::FMULv2i64_indexed_OP1: - case MachineCombinerPattern::FMULv2i64_indexed_OP2: { + case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv2i64_indexed_OP2: { unsigned IdxDupOp = - (Pattern == MachineCombinerPattern::FMULv2i64_indexed_OP1) ? 1 : 2; + (Pattern == AArch64MachineCombinerPattern::FMULv2i64_indexed_OP1) ? 1 + : 2; genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv2i64_indexed, &AArch64::FPR128RegClass, MRI); break; } - case MachineCombinerPattern::FMULv4i16_indexed_OP1: - case MachineCombinerPattern::FMULv4i16_indexed_OP2: { + case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv4i16_indexed_OP2: { unsigned IdxDupOp = - (Pattern == MachineCombinerPattern::FMULv4i16_indexed_OP1) ? 1 : 2; + (Pattern == AArch64MachineCombinerPattern::FMULv4i16_indexed_OP1) ? 1 + : 2; genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv4i16_indexed, &AArch64::FPR128_loRegClass, MRI); break; } - case MachineCombinerPattern::FMULv4i32_indexed_OP1: - case MachineCombinerPattern::FMULv4i32_indexed_OP2: { + case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv4i32_indexed_OP2: { unsigned IdxDupOp = - (Pattern == MachineCombinerPattern::FMULv4i32_indexed_OP1) ? 1 : 2; + (Pattern == AArch64MachineCombinerPattern::FMULv4i32_indexed_OP1) ? 1 + : 2; genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv4i32_indexed, &AArch64::FPR128RegClass, MRI); break; } - case MachineCombinerPattern::FMULv8i16_indexed_OP1: - case MachineCombinerPattern::FMULv8i16_indexed_OP2: { + case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP1: + case AArch64MachineCombinerPattern::FMULv8i16_indexed_OP2: { unsigned IdxDupOp = - (Pattern == MachineCombinerPattern::FMULv8i16_indexed_OP1) ? 1 : 2; + (Pattern == AArch64MachineCombinerPattern::FMULv8i16_indexed_OP1) ? 1 + : 2; genIndexedMultiply(Root, InsInstrs, IdxDupOp, AArch64::FMULv8i16_indexed, &AArch64::FPR128_loRegClass, MRI); break; } - case MachineCombinerPattern::FNMADD: { + case AArch64MachineCombinerPattern::FNMADD: { MUL = genFNegatedMAD(MF, MRI, TII, Root, InsInstrs); break; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index 2f10f80f4bdf..9a2914891675 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -33,6 +33,146 @@ static const MachineMemOperand::Flags MOStridedAccess = #define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access" +// AArch64 MachineCombiner patterns +enum AArch64MachineCombinerPattern : unsigned { + // These are patterns used to reduce the length of dependence chain. + SUBADD_OP1 = MachineCombinerPattern::TARGET_PATTERN_START, + SUBADD_OP2, + + // These are multiply-add patterns matched by the AArch64 machine combiner. + MULADDW_OP1, + MULADDW_OP2, + MULSUBW_OP1, + MULSUBW_OP2, + MULADDWI_OP1, + MULSUBWI_OP1, + MULADDX_OP1, + MULADDX_OP2, + MULSUBX_OP1, + MULSUBX_OP2, + MULADDXI_OP1, + MULSUBXI_OP1, + // NEON integers vectors + MULADDv8i8_OP1, + MULADDv8i8_OP2, + MULADDv16i8_OP1, + MULADDv16i8_OP2, + MULADDv4i16_OP1, + MULADDv4i16_OP2, + MULADDv8i16_OP1, + MULADDv8i16_OP2, + MULADDv2i32_OP1, + MULADDv2i32_OP2, + MULADDv4i32_OP1, + MULADDv4i32_OP2, + + MULSUBv8i8_OP1, + MULSUBv8i8_OP2, + MULSUBv16i8_OP1, + MULSUBv16i8_OP2, + MULSUBv4i16_OP1, + MULSUBv4i16_OP2, + MULSUBv8i16_OP1, + MULSUBv8i16_OP2, + MULSUBv2i32_OP1, + MULSUBv2i32_OP2, + MULSUBv4i32_OP1, + MULSUBv4i32_OP2, + + MULADDv4i16_indexed_OP1, + MULADDv4i16_indexed_OP2, + MULADDv8i16_indexed_OP1, + MULADDv8i16_indexed_OP2, + MULADDv2i32_indexed_OP1, + MULADDv2i32_indexed_OP2, + MULADDv4i32_indexed_OP1, + MULADDv4i32_indexed_OP2, + + MULSUBv4i16_indexed_OP1, + MULSUBv4i16_indexed_OP2, + MULSUBv8i16_indexed_OP1, + MULSUBv8i16_indexed_OP2, + MULSUBv2i32_indexed_OP1, + MULSUBv2i32_indexed_OP2, + MULSUBv4i32_indexed_OP1, + MULSUBv4i32_indexed_OP2, + + // Floating Point + FMULADDH_OP1, + FMULADDH_OP2, + FMULSUBH_OP1, + FMULSUBH_OP2, + FMULADDS_OP1, + FMULADDS_OP2, + FMULSUBS_OP1, + FMULSUBS_OP2, + FMULADDD_OP1, + FMULADDD_OP2, + FMULSUBD_OP1, + FMULSUBD_OP2, + FNMULSUBH_OP1, + FNMULSUBS_OP1, + FNMULSUBD_OP1, + FMLAv1i32_indexed_OP1, + FMLAv1i32_indexed_OP2, + FMLAv1i64_indexed_OP1, + FMLAv1i64_indexed_OP2, + FMLAv4f16_OP1, + FMLAv4f16_OP2, + FMLAv8f16_OP1, + FMLAv8f16_OP2, + FMLAv2f32_OP2, + FMLAv2f32_OP1, + FMLAv2f64_OP1, + FMLAv2f64_OP2, + FMLAv4i16_indexed_OP1, + FMLAv4i16_indexed_OP2, + FMLAv8i16_indexed_OP1, + FMLAv8i16_indexed_OP2, + FMLAv2i32_indexed_OP1, + FMLAv2i32_indexed_OP2, + FMLAv2i64_indexed_OP1, + FMLAv2i64_indexed_OP2, + FMLAv4f32_OP1, + FMLAv4f32_OP2, + FMLAv4i32_indexed_OP1, + FMLAv4i32_indexed_OP2, + FMLSv1i32_indexed_OP2, + FMLSv1i64_indexed_OP2, + FMLSv4f16_OP1, + FMLSv4f16_OP2, + FMLSv8f16_OP1, + FMLSv8f16_OP2, + FMLSv2f32_OP1, + FMLSv2f32_OP2, + FMLSv2f64_OP1, + FMLSv2f64_OP2, + FMLSv4i16_indexed_OP1, + FMLSv4i16_indexed_OP2, + FMLSv8i16_indexed_OP1, + FMLSv8i16_indexed_OP2, + FMLSv2i32_indexed_OP1, + FMLSv2i32_indexed_OP2, + FMLSv2i64_indexed_OP1, + FMLSv2i64_indexed_OP2, + FMLSv4f32_OP1, + FMLSv4f32_OP2, + FMLSv4i32_indexed_OP1, + FMLSv4i32_indexed_OP2, + + FMULv2i32_indexed_OP1, + FMULv2i32_indexed_OP2, + FMULv2i64_indexed_OP1, + FMULv2i64_indexed_OP2, + FMULv4i16_indexed_OP1, + FMULv4i16_indexed_OP2, + FMULv4i32_indexed_OP1, + FMULv4i32_indexed_OP2, + FMULv8i16_indexed_OP1, + FMULv8i16_indexed_OP2, + + FNMADD, +}; class AArch64InstrInfo final : public AArch64GenInstrInfo { const AArch64RegisterInfo RI; const AArch64Subtarget &Subtarget; @@ -283,17 +423,17 @@ public: const MachineRegisterInfo *MRI) const override; bool optimizeCondBranch(MachineInstr &MI) const override; + CombinerObjective getCombinerObjective(unsigned Pattern) const override; /// Return true when a code sequence can improve throughput. It /// should be called only for instructions in loops. /// \param Pattern - combiner pattern - bool isThroughputPattern(MachineCombinerPattern Pattern) const override; + bool isThroughputPattern(unsigned Pattern) const override; /// Return true when there is potentially a faster code sequence /// for an instruction chain ending in ``Root``. All potential patterns are /// listed in the ``Patterns`` array. - bool - getMachineCombinerPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns, - bool DoRegPressureReduce) const override; + bool getMachineCombinerPatterns(MachineInstr &Root, + SmallVectorImpl &Patterns, + bool DoRegPressureReduce) const override; /// Return true when Inst is associative and commutative so that it can be /// reassociated. If Invert is true, then the inverse of Inst operation must /// be checked. @@ -302,7 +442,7 @@ public: /// When getMachineCombinerPatterns() finds patterns, this function generates /// the instructions that could replace the original code sequence void genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const override; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 5f5eb31a5a85..93874d65531a 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -348,9 +348,9 @@ int16_t PPCInstrInfo::getFMAOpIdxInfo(unsigned Opcode) const { // register with D. After the transformation, A and D must be assigned with // same hardware register due to TIE attribute of FMA instructions. // -bool PPCInstrInfo::getFMAPatterns( - MachineInstr &Root, SmallVectorImpl &Patterns, - bool DoRegPressureReduce) const { +bool PPCInstrInfo::getFMAPatterns(MachineInstr &Root, + SmallVectorImpl &Patterns, + bool DoRegPressureReduce) const { MachineBasicBlock *MBB = Root.getParent(); const MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo(); const TargetRegisterInfo *TRI = &getRegisterInfo(); @@ -476,7 +476,7 @@ bool PPCInstrInfo::getFMAPatterns( if (isLoadFromConstantPool(MULInstrL) && IsUsedOnceR && IsReassociableAddOrSub(*MULInstrR, InfoArrayIdxFSubInst)) { LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BCA\n"); - Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BCA); + Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XY_BCA); return true; } @@ -484,7 +484,7 @@ bool PPCInstrInfo::getFMAPatterns( if ((isLoadFromConstantPool(MULInstrR) && IsUsedOnceL && IsReassociableAddOrSub(*MULInstrL, InfoArrayIdxFSubInst))) { LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_BAC\n"); - Patterns.push_back(MachineCombinerPattern::REASSOC_XY_BAC); + Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XY_BAC); return true; } } @@ -511,12 +511,12 @@ bool PPCInstrInfo::getFMAPatterns( MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA); AddOpIdx = -1; if (IsReassociableFMA(*Leaf, AddOpIdx, MulOpIdx, true)) { - Patterns.push_back(MachineCombinerPattern::REASSOC_XMM_AMM_BMM); + Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM); LLVM_DEBUG(dbgs() << "add pattern REASSOC_XMM_AMM_BMM\n"); return true; } if (IsReassociableAddOrSub(*Leaf, InfoArrayIdxFAddInst)) { - Patterns.push_back(MachineCombinerPattern::REASSOC_XY_AMM_BMM); + Patterns.push_back(PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM); LLVM_DEBUG(dbgs() << "add pattern REASSOC_XY_AMM_BMM\n"); return true; } @@ -524,7 +524,7 @@ bool PPCInstrInfo::getFMAPatterns( } void PPCInstrInfo::finalizeInsInstrs( - MachineInstr &Root, MachineCombinerPattern &P, + MachineInstr &Root, unsigned &Pattern, SmallVectorImpl &InsInstrs) const { assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!"); @@ -542,12 +542,12 @@ void PPCInstrInfo::finalizeInsInstrs( // For now we only need to fix up placeholder for register pressure reduce // patterns. Register ConstReg = 0; - switch (P) { - case MachineCombinerPattern::REASSOC_XY_BCA: + switch (Pattern) { + case PPCMachineCombinerPattern::REASSOC_XY_BCA: ConstReg = TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), MRI); break; - case MachineCombinerPattern::REASSOC_XY_BAC: + case PPCMachineCombinerPattern::REASSOC_XY_BAC: ConstReg = TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx + 1).getReg(), MRI); break; @@ -737,8 +737,21 @@ PPCInstrInfo::getConstantFromConstantPool(MachineInstr *I) const { return nullptr; } +CombinerObjective PPCInstrInfo::getCombinerObjective(unsigned Pattern) const { + switch (Pattern) { + case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM: + case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM: + return CombinerObjective::MustReduceDepth; + case PPCMachineCombinerPattern::REASSOC_XY_BCA: + case PPCMachineCombinerPattern::REASSOC_XY_BAC: + return CombinerObjective::MustReduceRegisterPressure; + default: + return TargetInstrInfo::getCombinerObjective(Pattern); + } +} + bool PPCInstrInfo::getMachineCombinerPatterns( - MachineInstr &Root, SmallVectorImpl &Patterns, + MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const { // Using the machine combiner in this way is potentially expensive, so // restrict to when aggressive optimizations are desired. @@ -753,15 +766,15 @@ bool PPCInstrInfo::getMachineCombinerPatterns( } void PPCInstrInfo::genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { switch (Pattern) { - case MachineCombinerPattern::REASSOC_XY_AMM_BMM: - case MachineCombinerPattern::REASSOC_XMM_AMM_BMM: - case MachineCombinerPattern::REASSOC_XY_BCA: - case MachineCombinerPattern::REASSOC_XY_BAC: + case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM: + case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM: + case PPCMachineCombinerPattern::REASSOC_XY_BCA: + case PPCMachineCombinerPattern::REASSOC_XY_BAC: reassociateFMA(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg); break; default: @@ -773,7 +786,7 @@ void PPCInstrInfo::genAlternativeCodeSequence( } void PPCInstrInfo::reassociateFMA( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { @@ -790,8 +803,8 @@ void PPCInstrInfo::reassociateFMA( assert(Idx >= 0 && "Root must be a FMA instruction"); bool IsILPReassociate = - (Pattern == MachineCombinerPattern::REASSOC_XY_AMM_BMM) || - (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM); + (Pattern == PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM) || + (Pattern == PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM); uint16_t AddOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxAddOpIdx]; uint16_t FirstMulOpIdx = FMAOpIdxInfo[Idx][InfoArrayIdxMULOpIdx]; @@ -801,18 +814,18 @@ void PPCInstrInfo::reassociateFMA( switch (Pattern) { default: llvm_unreachable("not recognized pattern!"); - case MachineCombinerPattern::REASSOC_XY_AMM_BMM: - case MachineCombinerPattern::REASSOC_XMM_AMM_BMM: + case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM: + case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM: Prev = MRI.getUniqueVRegDef(Root.getOperand(AddOpIdx).getReg()); Leaf = MRI.getUniqueVRegDef(Prev->getOperand(AddOpIdx).getReg()); break; - case MachineCombinerPattern::REASSOC_XY_BAC: { + case PPCMachineCombinerPattern::REASSOC_XY_BAC: { Register MULReg = TRI->lookThruCopyLike(Root.getOperand(FirstMulOpIdx).getReg(), &MRI); Leaf = MRI.getVRegDef(MULReg); break; } - case MachineCombinerPattern::REASSOC_XY_BCA: { + case PPCMachineCombinerPattern::REASSOC_XY_BCA: { Register MULReg = TRI->lookThruCopyLike( Root.getOperand(FirstMulOpIdx + 1).getReg(), &MRI); Leaf = MRI.getVRegDef(MULReg); @@ -853,10 +866,10 @@ void PPCInstrInfo::reassociateFMA( if (IsILPReassociate) GetFMAInstrInfo(*Prev, RegM21, RegM22, RegA21, KillM21, KillM22, KillA21); - if (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM) { + if (Pattern == PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM) { GetFMAInstrInfo(*Leaf, RegM11, RegM12, RegA11, KillM11, KillM12, KillA11); GetOperandInfo(Leaf->getOperand(AddOpIdx), RegX, KillX); - } else if (Pattern == MachineCombinerPattern::REASSOC_XY_AMM_BMM) { + } else if (Pattern == PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM) { GetOperandInfo(Leaf->getOperand(1), RegX, KillX); GetOperandInfo(Leaf->getOperand(2), RegY, KillY); } else { @@ -881,7 +894,7 @@ void PPCInstrInfo::reassociateFMA( } Register NewVRD = 0; - if (Pattern == MachineCombinerPattern::REASSOC_XMM_AMM_BMM) { + if (Pattern == PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM) { NewVRD = MRI.createVirtualRegister(RC); InstrIdxForVirtReg.insert(std::make_pair(NewVRD, 2)); } @@ -901,7 +914,7 @@ void PPCInstrInfo::reassociateFMA( switch (Pattern) { default: llvm_unreachable("not recognized pattern!"); - case MachineCombinerPattern::REASSOC_XY_AMM_BMM: { + case PPCMachineCombinerPattern::REASSOC_XY_AMM_BMM: { // Create new instructions for insertion. MachineInstrBuilder MINewB = BuildMI(*MF, Prev->getDebugLoc(), get(FmaOp), NewVRB) @@ -936,7 +949,7 @@ void PPCInstrInfo::reassociateFMA( InsInstrs.push_back(MINewC); break; } - case MachineCombinerPattern::REASSOC_XMM_AMM_BMM: { + case PPCMachineCombinerPattern::REASSOC_XMM_AMM_BMM: { assert(NewVRD && "new FMA register not created!"); // Create new instructions for insertion. MachineInstrBuilder MINewA = @@ -980,11 +993,11 @@ void PPCInstrInfo::reassociateFMA( InsInstrs.push_back(MINewC); break; } - case MachineCombinerPattern::REASSOC_XY_BAC: - case MachineCombinerPattern::REASSOC_XY_BCA: { + case PPCMachineCombinerPattern::REASSOC_XY_BAC: + case PPCMachineCombinerPattern::REASSOC_XY_BCA: { Register VarReg; bool KillVarReg = false; - if (Pattern == MachineCombinerPattern::REASSOC_XY_BCA) { + if (Pattern == PPCMachineCombinerPattern::REASSOC_XY_BCA) { VarReg = RegM31; KillVarReg = KillM31; } else { diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index 045932dc0d3b..1e2687f92c61 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -85,6 +85,19 @@ enum SpillOpcodeKey { SOK_LastOpcodeSpill // This must be last on the enum. }; +// PPC MachineCombiner patterns +enum PPCMachineCombinerPattern : unsigned { + // These are patterns matched by the PowerPC to reassociate FMA chains. + REASSOC_XY_AMM_BMM = MachineCombinerPattern::TARGET_PATTERN_START, + REASSOC_XMM_AMM_BMM, + + // These are patterns matched by the PowerPC to reassociate FMA and FSUB to + // reduce register pressure. + REASSOC_XY_BCA, + REASSOC_XY_BAC, + +}; + // Define list of load and store spill opcodes. #define NoInstr PPC::INSTRUCTION_LIST_END #define Pwr8LoadOpcodes \ @@ -224,7 +237,7 @@ class PPCInstrInfo : public PPCGenInstrInfo { ArrayRef getLoadOpcodesForSpillArray() const; unsigned getSpillIndex(const TargetRegisterClass *RC) const; int16_t getFMAOpIdxInfo(unsigned Opcode) const; - void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, + void reassociateFMA(MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const; @@ -350,7 +363,7 @@ public: /// When getMachineCombinerPatterns() finds patterns, this function generates /// the instructions that could replace the original code sequence void genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const override; @@ -358,15 +371,16 @@ public: /// Return true when there is potentially a faster code sequence for a fma /// chain ending in \p Root. All potential patterns are output in the \p /// P array. - bool getFMAPatterns(MachineInstr &Root, - SmallVectorImpl &P, + bool getFMAPatterns(MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const; + CombinerObjective getCombinerObjective(unsigned Pattern) const override; + /// Return true when there is potentially a faster code sequence /// for an instruction chain ending in . All potential patterns are /// output in the array. bool getMachineCombinerPatterns(MachineInstr &Root, - SmallVectorImpl &P, + SmallVectorImpl &Patterns, bool DoRegPressureReduce) const override; /// On PowerPC, we leverage machine combiner pass to reduce register pressure @@ -380,7 +394,7 @@ public: /// Fixup the placeholders we put in genAlternativeCodeSequence() for /// MachineCombiner. void - finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, + finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl &InsInstrs) const override; bool isAssociativeAndCommutative(const MachineInstr &Inst, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 84d754e3cbcf..d78f5bd9dedf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1560,7 +1560,7 @@ MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy() const { } void RISCVInstrInfo::finalizeInsInstrs( - MachineInstr &Root, MachineCombinerPattern &P, + MachineInstr &Root, unsigned &Pattern, SmallVectorImpl &InsInstrs) const { int16_t FrmOpIdx = RISCV::getNamedOperandIdx(Root.getOpcode(), RISCV::OpName::frm); @@ -1748,10 +1748,9 @@ static bool canCombineFPFusedMultiply(const MachineInstr &Root, return RISCV::hasEqualFRM(Root, *MI); } -static bool -getFPFusedMultiplyPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns, - bool DoRegPressureReduce) { +static bool getFPFusedMultiplyPatterns(MachineInstr &Root, + SmallVectorImpl &Patterns, + bool DoRegPressureReduce) { unsigned Opc = Root.getOpcode(); bool IsFAdd = isFADD(Opc); if (!IsFAdd && !isFSUB(Opc)) @@ -1759,21 +1758,21 @@ getFPFusedMultiplyPatterns(MachineInstr &Root, bool Added = false; if (canCombineFPFusedMultiply(Root, Root.getOperand(1), DoRegPressureReduce)) { - Patterns.push_back(IsFAdd ? MachineCombinerPattern::FMADD_AX - : MachineCombinerPattern::FMSUB); + Patterns.push_back(IsFAdd ? RISCVMachineCombinerPattern::FMADD_AX + : RISCVMachineCombinerPattern::FMSUB); Added = true; } if (canCombineFPFusedMultiply(Root, Root.getOperand(2), DoRegPressureReduce)) { - Patterns.push_back(IsFAdd ? MachineCombinerPattern::FMADD_XA - : MachineCombinerPattern::FNMSUB); + Patterns.push_back(IsFAdd ? RISCVMachineCombinerPattern::FMADD_XA + : RISCVMachineCombinerPattern::FNMSUB); Added = true; } return Added; } static bool getFPPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns, + SmallVectorImpl &Patterns, bool DoRegPressureReduce) { return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce); } @@ -1832,9 +1831,8 @@ static unsigned getSHXADDShiftAmount(unsigned Opc) { // Look for opportunities to combine (sh3add Z, (add X, (slli Y, 5))) into // (sh3add (sh2add Y, Z), X). -static bool -getSHXADDPatterns(const MachineInstr &Root, - SmallVectorImpl &Patterns) { +static bool getSHXADDPatterns(const MachineInstr &Root, + SmallVectorImpl &Patterns) { unsigned ShiftAmt = getSHXADDShiftAmount(Root.getOpcode()); if (!ShiftAmt) return false; @@ -1847,19 +1845,31 @@ getSHXADDPatterns(const MachineInstr &Root, bool Found = false; if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(1), ShiftAmt)) { - Patterns.push_back(MachineCombinerPattern::SHXADD_ADD_SLLI_OP1); + Patterns.push_back(RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP1); Found = true; } if (canCombineShiftIntoShXAdd(MBB, AddMI->getOperand(2), ShiftAmt)) { - Patterns.push_back(MachineCombinerPattern::SHXADD_ADD_SLLI_OP2); + Patterns.push_back(RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2); Found = true; } return Found; } +CombinerObjective RISCVInstrInfo::getCombinerObjective(unsigned Pattern) const { + switch (Pattern) { + case RISCVMachineCombinerPattern::FMADD_AX: + case RISCVMachineCombinerPattern::FMADD_XA: + case RISCVMachineCombinerPattern::FMSUB: + case RISCVMachineCombinerPattern::FNMSUB: + return CombinerObjective::MustReduceDepth; + default: + return TargetInstrInfo::getCombinerObjective(Pattern); + } +} + bool RISCVInstrInfo::getMachineCombinerPatterns( - MachineInstr &Root, SmallVectorImpl &Patterns, + MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const { if (getFPPatterns(Root, Patterns, DoRegPressureReduce)) @@ -1872,8 +1882,7 @@ bool RISCVInstrInfo::getMachineCombinerPatterns( DoRegPressureReduce); } -static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, - MachineCombinerPattern Pattern) { +static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, unsigned Pattern) { switch (RootOpc) { default: llvm_unreachable("Unexpected opcode"); @@ -1884,32 +1893,32 @@ static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, case RISCV::FADD_D: return RISCV::FMADD_D; case RISCV::FSUB_H: - return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_H - : RISCV::FNMSUB_H; + return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_H + : RISCV::FNMSUB_H; case RISCV::FSUB_S: - return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_S - : RISCV::FNMSUB_S; + return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_S + : RISCV::FNMSUB_S; case RISCV::FSUB_D: - return Pattern == MachineCombinerPattern::FMSUB ? RISCV::FMSUB_D - : RISCV::FNMSUB_D; + return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_D + : RISCV::FNMSUB_D; } } -static unsigned getAddendOperandIdx(MachineCombinerPattern Pattern) { +static unsigned getAddendOperandIdx(unsigned Pattern) { switch (Pattern) { default: llvm_unreachable("Unexpected pattern"); - case MachineCombinerPattern::FMADD_AX: - case MachineCombinerPattern::FMSUB: + case RISCVMachineCombinerPattern::FMADD_AX: + case RISCVMachineCombinerPattern::FMSUB: return 2; - case MachineCombinerPattern::FMADD_XA: - case MachineCombinerPattern::FNMSUB: + case RISCVMachineCombinerPattern::FMADD_XA: + case RISCVMachineCombinerPattern::FNMSUB: return 1; } } static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev, - MachineCombinerPattern Pattern, + unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs) { MachineFunction *MF = Root.getMF(); @@ -2013,7 +2022,7 @@ genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx, } void RISCVInstrInfo::genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { @@ -2023,22 +2032,22 @@ void RISCVInstrInfo::genAlternativeCodeSequence( TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg); return; - case MachineCombinerPattern::FMADD_AX: - case MachineCombinerPattern::FMSUB: { + case RISCVMachineCombinerPattern::FMADD_AX: + case RISCVMachineCombinerPattern::FMSUB: { MachineInstr &Prev = *MRI.getVRegDef(Root.getOperand(1).getReg()); combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs); return; } - case MachineCombinerPattern::FMADD_XA: - case MachineCombinerPattern::FNMSUB: { + case RISCVMachineCombinerPattern::FMADD_XA: + case RISCVMachineCombinerPattern::FNMSUB: { MachineInstr &Prev = *MRI.getVRegDef(Root.getOperand(2).getReg()); combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs); return; } - case MachineCombinerPattern::SHXADD_ADD_SLLI_OP1: + case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP1: genShXAddAddShift(Root, 1, InsInstrs, DelInstrs, InstrIdxForVirtReg); return; - case MachineCombinerPattern::SHXADD_ADD_SLLI_OP2: + case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2: genShXAddAddShift(Root, 2, InsInstrs, DelInstrs, InstrIdxForVirtReg); return; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 81d9c9db783c..70fe7da85be0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -49,6 +49,16 @@ unsigned getBrCond(CondCode CC); } // end of namespace RISCVCC +// RISCV MachineCombiner patterns +enum RISCVMachineCombinerPattern : unsigned { + FMADD_AX = MachineCombinerPattern::TARGET_PATTERN_START, + FMADD_XA, + FMSUB, + FNMSUB, + SHXADD_ADD_SLLI_OP1, + SHXADD_ADD_SLLI_OP2, +}; + class RISCVInstrInfo : public RISCVGenInstrInfo { public: @@ -240,17 +250,18 @@ public: MachineTraceStrategy getMachineCombinerTraceStrategy() const override; - bool - getMachineCombinerPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns, - bool DoRegPressureReduce) const override; + CombinerObjective getCombinerObjective(unsigned Pattern) const override; + + bool getMachineCombinerPatterns(MachineInstr &Root, + SmallVectorImpl &Patterns, + bool DoRegPressureReduce) const override; void - finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, + finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl &InsInstrs) const override; void genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const override; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index a5b2e4895ede..510b08f9901a 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -10578,7 +10578,7 @@ void X86InstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB, } bool X86InstrInfo::getMachineCombinerPatterns( - MachineInstr &Root, SmallVectorImpl &Patterns, + MachineInstr &Root, SmallVectorImpl &Patterns, bool DoRegPressureReduce) const { unsigned Opc = Root.getOpcode(); switch (Opc) { @@ -10587,7 +10587,7 @@ bool X86InstrInfo::getMachineCombinerPatterns( case X86::VPDPWSSDYrr: case X86::VPDPWSSDYrm: { if (!Subtarget.hasFastDPWSSD()) { - Patterns.push_back(MachineCombinerPattern::DPWSSD); + Patterns.push_back(X86MachineCombinerPattern::DPWSSD); return true; } break; @@ -10599,8 +10599,8 @@ bool X86InstrInfo::getMachineCombinerPatterns( case X86::VPDPWSSDZr: case X86::VPDPWSSDZm: { if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) { - Patterns.push_back(MachineCombinerPattern::DPWSSD); - return true; + Patterns.push_back(X86MachineCombinerPattern::DPWSSD); + return true; } break; } @@ -10700,7 +10700,7 @@ genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII, } void X86InstrInfo::genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const { @@ -10710,7 +10710,7 @@ void X86InstrInfo::genAlternativeCodeSequence( TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs, DelInstrs, InstrIdxForVirtReg); return; - case MachineCombinerPattern::DPWSSD: + case X86MachineCombinerPattern::DPWSSD: genAlternativeDpCodeSequence(Root, *this, InsInstrs, DelInstrs, InstrIdxForVirtReg); return; diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index e719be0caf3e..5407ede69a91 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -26,6 +26,12 @@ namespace llvm { class X86Subtarget; +// X86 MachineCombiner patterns +enum X86MachineCombinerPattern : unsigned { + // X86 VNNI + DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START, +}; + namespace X86 { enum AsmComments { @@ -607,16 +613,15 @@ protected: std::optional isCopyInstrImpl(const MachineInstr &MI) const override; - bool - getMachineCombinerPatterns(MachineInstr &Root, - SmallVectorImpl &Patterns, - bool DoRegPressureReduce) const override; + bool getMachineCombinerPatterns(MachineInstr &Root, + SmallVectorImpl &Patterns, + bool DoRegPressureReduce) const override; /// When getMachineCombinerPatterns() finds potential patterns, /// this function generates the instructions that could replace the /// original code sequence. void genAlternativeCodeSequence( - MachineInstr &Root, MachineCombinerPattern Pattern, + MachineInstr &Root, unsigned Pattern, SmallVectorImpl &InsInstrs, SmallVectorImpl &DelInstrs, DenseMap &InstrIdxForVirtReg) const override; -- GitLab From efb8cc5ddb03897795dc153a03d0c1548c8ee4a7 Mon Sep 17 00:00:00 2001 From: paperchalice Date: Thu, 11 Apr 2024 12:27:18 +0800 Subject: [PATCH 480/695] [NewPM] Fix print-changed-dot-cfg failure (#88351) Fix failure in #80946. --- llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir b/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir index 340ece93aa02..40603630c613 100644 --- a/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir +++ b/llvm/test/Other/ChangePrinters/DotCfg/print-changed-dot-cfg.mir @@ -1,7 +1,7 @@ # REQUIRES: x86-registered-target # Simple functionality check. # RUN: rm -rf %t && mkdir -p %t -# RUN: llc -filetype=null -print-changed=dot-cfg -passes=no-op-machine-function -dot-cfg-dir=%t %s +# RUN: llc -mtriple=x86_64-pc-linux-gnu -filetype=null -print-changed=dot-cfg -passes=no-op-machine-function -dot-cfg-dir=%t %s # RUN: ls %t/*.pdf %t/passes.html | count 3 --- -- GitLab From 3197f9d8b0efc3efdc531421bd11c16305d9b1ff Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Thu, 11 Apr 2024 12:48:52 +0800 Subject: [PATCH 481/695] [InstSimplify] Make sure the simplified value doesn't generate poison in threadBinOpOverSelect (#87075) Alive2: https://alive2.llvm.org/ce/z/y_Jmdn Fix https://github.com/llvm/llvm-project/issues/87042. --- llvm/lib/Analysis/InstructionSimplify.cpp | 3 +- llvm/test/Transforms/InstSimplify/pr87042.ll | 42 ++++++++++++++++++++ 2 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 llvm/test/Transforms/InstSimplify/pr87042.ll diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 9ff3faff7990..3c943a09a9c2 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -440,7 +440,8 @@ static Value *threadBinOpOverSelect(Instruction::BinaryOps Opcode, Value *LHS, // Check that the simplified value has the form "X op Y" where "op" is the // same as the original operation. Instruction *Simplified = dyn_cast(FV ? FV : TV); - if (Simplified && Simplified->getOpcode() == unsigned(Opcode)) { + if (Simplified && Simplified->getOpcode() == unsigned(Opcode) && + !Simplified->hasPoisonGeneratingFlags()) { // The value that didn't simplify is "UnsimplifiedLHS op UnsimplifiedRHS". // We already know that "op" is the same as for the simplified value. See // if the operands match too. If so, return the simplified value. diff --git a/llvm/test/Transforms/InstSimplify/pr87042.ll b/llvm/test/Transforms/InstSimplify/pr87042.ll new file mode 100644 index 000000000000..800d27c9e650 --- /dev/null +++ b/llvm/test/Transforms/InstSimplify/pr87042.ll @@ -0,0 +1,42 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instsimplify -S | FileCheck %s + +; %or2 cannot be folded into %or1 because %or1 has disjoint. +; TODO: Can we move the logic into InstCombine and drop the disjoint flag? +define i64 @test(i1 %cond, i64 %x) { +; CHECK-LABEL: define i64 @test( +; CHECK-SAME: i1 [[COND:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 +; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND]], i64 [[OR1]], i64 [[X]] +; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SEL1]], 7 +; CHECK-NEXT: ret i64 [[OR2]] +; + %or1 = or disjoint i64 %x, 7 + %sel1 = select i1 %cond, i64 %or1, i64 %x + %or2 = or i64 %sel1, 7 + ret i64 %or2 +} + +define i64 @pr87042(i64 %x) { +; CHECK-LABEL: define i64 @pr87042( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X]], 65535 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[AND1]], 0 +; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 +; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i64 [[OR1]], i64 [[X]] +; CHECK-NEXT: [[AND2:%.*]] = and i64 [[SEL1]], 16776960 +; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 [[AND2]], 0 +; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SEL1]], 7 +; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i64 [[OR2]], i64 [[SEL1]] +; CHECK-NEXT: ret i64 [[SEL2]] +; + %and1 = and i64 %x, 65535 + %cmp1 = icmp eq i64 %and1, 0 + %or1 = or disjoint i64 %x, 7 + %sel1 = select i1 %cmp1, i64 %or1, i64 %x + %and2 = and i64 %sel1, 16776960 + %cmp2 = icmp eq i64 %and2, 0 + %or2 = or i64 %sel1, 7 + %sel2 = select i1 %cmp2, i64 %or2, i64 %sel1 + ret i64 %sel2 +} -- GitLab From 2bede6873dbe7021b306d3e5bec59d0fba2dd26c Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Wed, 10 Apr 2024 22:03:20 -0700 Subject: [PATCH 482/695] [memprof] Rename RawMemProfReader.{cpp,h} to MemProfReader.{cpp,h} (NFC) (#88200) This patch renames RawMemProfReader.{cpp,h} to MemProfReader.{cpp,h}, respectively. Also, it re-creates RawMemProfReader.h just to include MemProfReader.h for compatibility with out-of-tree users. --- llvm/include/llvm/ProfileData/MemProfReader.h | 214 ++++++++++++++++++ .../llvm/ProfileData/RawMemProfReader.h | 207 +---------------- llvm/lib/ProfileData/CMakeLists.txt | 2 +- ...RawMemProfReader.cpp => MemProfReader.cpp} | 6 +- llvm/tools/llvm-profdata/llvm-profdata.cpp | 2 +- llvm/unittests/ProfileData/MemProfTest.cpp | 2 +- .../secondary/llvm/lib/ProfileData/BUILD.gn | 2 +- 7 files changed, 227 insertions(+), 208 deletions(-) create mode 100644 llvm/include/llvm/ProfileData/MemProfReader.h rename llvm/lib/ProfileData/{RawMemProfReader.cpp => MemProfReader.cpp} (99%) diff --git a/llvm/include/llvm/ProfileData/MemProfReader.h b/llvm/include/llvm/ProfileData/MemProfReader.h new file mode 100644 index 000000000000..89f49a20a608 --- /dev/null +++ b/llvm/include/llvm/ProfileData/MemProfReader.h @@ -0,0 +1,214 @@ +//===- MemProfReader.h - Instrumented memory profiling reader ---*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains support for reading MemProf profiling data. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_PROFILEDATA_MEMPROFREADER_H_ +#define LLVM_PROFILEDATA_MEMPROFREADER_H_ + +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/MapVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/DebugInfo/Symbolize/SymbolizableModule.h" +#include "llvm/DebugInfo/Symbolize/Symbolize.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/Object/Binary.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/ProfileData/InstrProfReader.h" +#include "llvm/ProfileData/MemProf.h" +#include "llvm/ProfileData/MemProfData.inc" +#include "llvm/Support/Error.h" +#include "llvm/Support/MemoryBuffer.h" + +#include + +namespace llvm { +namespace memprof { +// A class for memprof profile data populated directly from external +// sources. +class MemProfReader { +public: + // The MemProfReader only holds memory profile information. + InstrProfKind getProfileKind() const { return InstrProfKind::MemProf; } + + using GuidMemProfRecordPair = std::pair; + using Iterator = InstrProfIterator; + Iterator end() { return Iterator(); } + Iterator begin() { + Iter = FunctionProfileData.begin(); + return Iterator(this); + } + + // Return a const reference to the internal Id to Frame mappings. + const llvm::DenseMap &getFrameMapping() const { + return IdToFrame; + } + + // Return a const reference to the internal function profile data. + const llvm::MapVector & + getProfileData() const { + return FunctionProfileData; + } + + virtual Error + readNextRecord(GuidMemProfRecordPair &GuidRecord, + std::function Callback = nullptr) { + if (FunctionProfileData.empty()) + return make_error(instrprof_error::empty_raw_profile); + + if (Iter == FunctionProfileData.end()) + return make_error(instrprof_error::eof); + + if (Callback == nullptr) + Callback = + std::bind(&MemProfReader::idToFrame, this, std::placeholders::_1); + + const IndexedMemProfRecord &IndexedRecord = Iter->second; + GuidRecord = {Iter->first, MemProfRecord(IndexedRecord, Callback)}; + Iter++; + return Error::success(); + } + + // Allow default construction for derived classes which can populate the + // contents after construction. + MemProfReader() = default; + virtual ~MemProfReader() = default; + + // Initialize the MemProfReader with the frame mappings and profile contents. + MemProfReader( + llvm::DenseMap FrameIdMap, + llvm::MapVector ProfData) + : IdToFrame(std::move(FrameIdMap)), + FunctionProfileData(std::move(ProfData)) {} + +protected: + // A helper method to extract the frame from the IdToFrame map. + const Frame &idToFrame(const FrameId Id) const { + auto It = IdToFrame.find(Id); + assert(It != IdToFrame.end() && "Id not found in map."); + return It->getSecond(); + } + // A mapping from FrameId (a hash of the contents) to the frame. + llvm::DenseMap IdToFrame; + // A mapping from function GUID, hash of the canonical function symbol to the + // memprof profile data for that function, i.e allocation and callsite info. + llvm::MapVector FunctionProfileData; + // An iterator to the internal function profile data structure. + llvm::MapVector::iterator Iter; +}; + +// Map from id (recorded from sanitizer stack depot) to virtual addresses for +// each program counter address in the callstack. +using CallStackMap = llvm::DenseMap>; + +// Specializes the MemProfReader class to populate the contents from raw binary +// memprof profiles from instrumentation based profiling. +class RawMemProfReader final : public MemProfReader { +public: + RawMemProfReader(const RawMemProfReader &) = delete; + RawMemProfReader &operator=(const RawMemProfReader &) = delete; + virtual ~RawMemProfReader() override = default; + + // Prints the contents of the profile in YAML format. + void printYAML(raw_ostream &OS); + + // Return true if the \p DataBuffer starts with magic bytes indicating it is + // a raw binary memprof profile. + static bool hasFormat(const MemoryBuffer &DataBuffer); + // Return true if the file at \p Path starts with magic bytes indicating it is + // a raw binary memprof profile. + static bool hasFormat(const StringRef Path); + + // Create a RawMemProfReader after sanity checking the contents of the file at + // \p Path or the \p Buffer. The binary from which the profile has been + // collected is specified via a path in \p ProfiledBinary. + static Expected> + create(const Twine &Path, StringRef ProfiledBinary, bool KeepName = false); + static Expected> + create(std::unique_ptr Buffer, StringRef ProfiledBinary, + bool KeepName = false); + + // Returns a list of build ids recorded in the segment information. + static std::vector peekBuildIds(MemoryBuffer *DataBuffer); + + virtual Error + readNextRecord(GuidMemProfRecordPair &GuidRecord, + std::function Callback) override; + + // Constructor for unittests only. + RawMemProfReader(std::unique_ptr Sym, + llvm::SmallVectorImpl &Seg, + llvm::MapVector &Prof, + CallStackMap &SM, bool KeepName = false) + : SegmentInfo(Seg.begin(), Seg.end()), CallstackProfileData(Prof), + StackMap(SM), KeepSymbolName(KeepName) { + // We don't call initialize here since there is no raw profile to read. The + // test should pass in the raw profile as structured data. + + // If there is an error here then the mock symbolizer has not been + // initialized properly. + if (Error E = symbolizeAndFilterStackFrames(std::move(Sym))) + report_fatal_error(std::move(E)); + if (Error E = mapRawProfileToRecords()) + report_fatal_error(std::move(E)); + } + +private: + RawMemProfReader(object::OwningBinary &&Bin, bool KeepName) + : Binary(std::move(Bin)), KeepSymbolName(KeepName) {} + // Initializes the RawMemProfReader with the contents in `DataBuffer`. + Error initialize(std::unique_ptr DataBuffer); + // Read and parse the contents of the `DataBuffer` as a binary format profile. + Error readRawProfile(std::unique_ptr DataBuffer); + // Initialize the segment mapping information for symbolization. + Error setupForSymbolization(); + // Symbolize and cache all the virtual addresses we encounter in the + // callstacks from the raw profile. Also prune callstack frames which we can't + // symbolize or those that belong to the runtime. For profile entries where + // the entire callstack is pruned, we drop the entry from the profile. + Error symbolizeAndFilterStackFrames( + std::unique_ptr Symbolizer); + // Construct memprof records for each function and store it in the + // `FunctionProfileData` map. A function may have allocation profile data or + // callsite data or both. + Error mapRawProfileToRecords(); + + object::SectionedAddress getModuleOffset(uint64_t VirtualAddress); + + // The profiled binary. + object::OwningBinary Binary; + // The preferred load address of the executable segment. + uint64_t PreferredTextSegmentAddress = 0; + // The base address of the text segment in the process during profiling. + uint64_t ProfiledTextSegmentStart = 0; + // The limit address of the text segment in the process during profiling. + uint64_t ProfiledTextSegmentEnd = 0; + + // The memory mapped segment information for all executable segments in the + // profiled binary (filtered from the raw profile using the build id). + llvm::SmallVector SegmentInfo; + + // A map from callstack id (same as key in CallStackMap below) to the heap + // information recorded for that allocation context. + llvm::MapVector CallstackProfileData; + CallStackMap StackMap; + + // Cached symbolization from PC to Frame. + llvm::DenseMap> SymbolizedFrame; + + // Whether to keep the symbol name for each frame after hashing. + bool KeepSymbolName = false; + // A mapping of the hash to symbol name, only used if KeepSymbolName is true. + llvm::DenseMap GuidToSymbolName; +}; +} // namespace memprof +} // namespace llvm + +#endif // LLVM_PROFILEDATA_MEMPROFREADER_H_ diff --git a/llvm/include/llvm/ProfileData/RawMemProfReader.h b/llvm/include/llvm/ProfileData/RawMemProfReader.h index 6aa5caec65f7..5e06f26fffdc 100644 --- a/llvm/include/llvm/ProfileData/RawMemProfReader.h +++ b/llvm/include/llvm/ProfileData/RawMemProfReader.h @@ -1,6 +1,4 @@ -#ifndef LLVM_PROFILEDATA_RAWMEMPROFREADER_H_ -#define LLVM_PROFILEDATA_RAWMEMPROFREADER_H_ -//===- MemProfReader.h - Instrumented memory profiling reader ---*- C++ -*-===// +//===- RawMemProfReader.h - Instrumented memory profiling reader *- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,207 +6,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains support for reading MemProf profiling data. +// This file just includes MemProfReader.h for compatibility with +// out-of-tree users. // //===----------------------------------------------------------------------===// -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/MapVector.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/DebugInfo/Symbolize/SymbolizableModule.h" -#include "llvm/DebugInfo/Symbolize/Symbolize.h" -#include "llvm/IR/GlobalValue.h" -#include "llvm/Object/Binary.h" -#include "llvm/Object/ObjectFile.h" -#include "llvm/ProfileData/InstrProfReader.h" -#include "llvm/ProfileData/MemProf.h" -#include "llvm/ProfileData/MemProfData.inc" -#include "llvm/Support/Error.h" -#include "llvm/Support/MemoryBuffer.h" - -#include - -namespace llvm { -namespace memprof { -// A class for memprof profile data populated directly from external -// sources. -// TODO: Rename this file to MemProfReader.h to better reflect the contents. -class MemProfReader { -public: - // The MemProfReader only holds memory profile information. - InstrProfKind getProfileKind() const { return InstrProfKind::MemProf; } - - using GuidMemProfRecordPair = std::pair; - using Iterator = InstrProfIterator; - Iterator end() { return Iterator(); } - Iterator begin() { - Iter = FunctionProfileData.begin(); - return Iterator(this); - } - - // Return a const reference to the internal Id to Frame mappings. - const llvm::DenseMap &getFrameMapping() const { - return IdToFrame; - } - - // Return a const reference to the internal function profile data. - const llvm::MapVector & - getProfileData() const { - return FunctionProfileData; - } - - virtual Error - readNextRecord(GuidMemProfRecordPair &GuidRecord, - std::function Callback = nullptr) { - if (FunctionProfileData.empty()) - return make_error(instrprof_error::empty_raw_profile); - - if (Iter == FunctionProfileData.end()) - return make_error(instrprof_error::eof); - - if (Callback == nullptr) - Callback = - std::bind(&MemProfReader::idToFrame, this, std::placeholders::_1); - - const IndexedMemProfRecord &IndexedRecord = Iter->second; - GuidRecord = {Iter->first, MemProfRecord(IndexedRecord, Callback)}; - Iter++; - return Error::success(); - } - - // Allow default construction for derived classes which can populate the - // contents after construction. - MemProfReader() = default; - virtual ~MemProfReader() = default; - - // Initialize the MemProfReader with the frame mappings and profile contents. - MemProfReader( - llvm::DenseMap FrameIdMap, - llvm::MapVector ProfData) - : IdToFrame(std::move(FrameIdMap)), - FunctionProfileData(std::move(ProfData)) {} - -protected: - // A helper method to extract the frame from the IdToFrame map. - const Frame &idToFrame(const FrameId Id) const { - auto It = IdToFrame.find(Id); - assert(It != IdToFrame.end() && "Id not found in map."); - return It->getSecond(); - } - // A mapping from FrameId (a hash of the contents) to the frame. - llvm::DenseMap IdToFrame; - // A mapping from function GUID, hash of the canonical function symbol to the - // memprof profile data for that function, i.e allocation and callsite info. - llvm::MapVector FunctionProfileData; - // An iterator to the internal function profile data structure. - llvm::MapVector::iterator Iter; -}; - -// Map from id (recorded from sanitizer stack depot) to virtual addresses for -// each program counter address in the callstack. -using CallStackMap = llvm::DenseMap>; - -// Specializes the MemProfReader class to populate the contents from raw binary -// memprof profiles from instrumentation based profiling. -class RawMemProfReader final : public MemProfReader { -public: - RawMemProfReader(const RawMemProfReader &) = delete; - RawMemProfReader &operator=(const RawMemProfReader &) = delete; - virtual ~RawMemProfReader() override = default; - - // Prints the contents of the profile in YAML format. - void printYAML(raw_ostream &OS); - - // Return true if the \p DataBuffer starts with magic bytes indicating it is - // a raw binary memprof profile. - static bool hasFormat(const MemoryBuffer &DataBuffer); - // Return true if the file at \p Path starts with magic bytes indicating it is - // a raw binary memprof profile. - static bool hasFormat(const StringRef Path); - - // Create a RawMemProfReader after sanity checking the contents of the file at - // \p Path or the \p Buffer. The binary from which the profile has been - // collected is specified via a path in \p ProfiledBinary. - static Expected> - create(const Twine &Path, StringRef ProfiledBinary, bool KeepName = false); - static Expected> - create(std::unique_ptr Buffer, StringRef ProfiledBinary, - bool KeepName = false); - - // Returns a list of build ids recorded in the segment information. - static std::vector peekBuildIds(MemoryBuffer *DataBuffer); - - virtual Error - readNextRecord(GuidMemProfRecordPair &GuidRecord, - std::function Callback) override; - - // Constructor for unittests only. - RawMemProfReader(std::unique_ptr Sym, - llvm::SmallVectorImpl &Seg, - llvm::MapVector &Prof, - CallStackMap &SM, bool KeepName = false) - : SegmentInfo(Seg.begin(), Seg.end()), CallstackProfileData(Prof), - StackMap(SM), KeepSymbolName(KeepName) { - // We don't call initialize here since there is no raw profile to read. The - // test should pass in the raw profile as structured data. - - // If there is an error here then the mock symbolizer has not been - // initialized properly. - if (Error E = symbolizeAndFilterStackFrames(std::move(Sym))) - report_fatal_error(std::move(E)); - if (Error E = mapRawProfileToRecords()) - report_fatal_error(std::move(E)); - } - -private: - RawMemProfReader(object::OwningBinary &&Bin, bool KeepName) - : Binary(std::move(Bin)), KeepSymbolName(KeepName) {} - // Initializes the RawMemProfReader with the contents in `DataBuffer`. - Error initialize(std::unique_ptr DataBuffer); - // Read and parse the contents of the `DataBuffer` as a binary format profile. - Error readRawProfile(std::unique_ptr DataBuffer); - // Initialize the segment mapping information for symbolization. - Error setupForSymbolization(); - // Symbolize and cache all the virtual addresses we encounter in the - // callstacks from the raw profile. Also prune callstack frames which we can't - // symbolize or those that belong to the runtime. For profile entries where - // the entire callstack is pruned, we drop the entry from the profile. - Error symbolizeAndFilterStackFrames( - std::unique_ptr Symbolizer); - // Construct memprof records for each function and store it in the - // `FunctionProfileData` map. A function may have allocation profile data or - // callsite data or both. - Error mapRawProfileToRecords(); - - object::SectionedAddress getModuleOffset(uint64_t VirtualAddress); - - // The profiled binary. - object::OwningBinary Binary; - // The preferred load address of the executable segment. - uint64_t PreferredTextSegmentAddress = 0; - // The base address of the text segment in the process during profiling. - uint64_t ProfiledTextSegmentStart = 0; - // The limit address of the text segment in the process during profiling. - uint64_t ProfiledTextSegmentEnd = 0; - - // The memory mapped segment information for all executable segments in the - // profiled binary (filtered from the raw profile using the build id). - llvm::SmallVector SegmentInfo; - - // A map from callstack id (same as key in CallStackMap below) to the heap - // information recorded for that allocation context. - llvm::MapVector CallstackProfileData; - CallStackMap StackMap; - - // Cached symbolization from PC to Frame. - llvm::DenseMap> SymbolizedFrame; +#ifndef LLVM_PROFILEDATA_RAWMEMPROFREADER_H_ +#define LLVM_PROFILEDATA_RAWMEMPROFREADER_H_ - // Whether to keep the symbol name for each frame after hashing. - bool KeepSymbolName = false; - // A mapping of the hash to symbol name, only used if KeepSymbolName is true. - llvm::DenseMap GuidToSymbolName; -}; -} // namespace memprof -} // namespace llvm +#include "llvm/ProfileData/MemProfReader.h" #endif // LLVM_PROFILEDATA_RAWMEMPROFREADER_H_ diff --git a/llvm/lib/ProfileData/CMakeLists.txt b/llvm/lib/ProfileData/CMakeLists.txt index 99617a43fee7..408f9ff01ec8 100644 --- a/llvm/lib/ProfileData/CMakeLists.txt +++ b/llvm/lib/ProfileData/CMakeLists.txt @@ -6,8 +6,8 @@ add_llvm_component_library(LLVMProfileData InstrProfWriter.cpp ItaniumManglingCanonicalizer.cpp MemProf.cpp + MemProfReader.cpp ProfileSummaryBuilder.cpp - RawMemProfReader.cpp SampleProf.cpp SampleProfReader.cpp SampleProfWriter.cpp diff --git a/llvm/lib/ProfileData/RawMemProfReader.cpp b/llvm/lib/ProfileData/MemProfReader.cpp similarity index 99% rename from llvm/lib/ProfileData/RawMemProfReader.cpp rename to llvm/lib/ProfileData/MemProfReader.cpp index e93fbc72f54e..4ccec26597c0 100644 --- a/llvm/lib/ProfileData/RawMemProfReader.cpp +++ b/llvm/lib/ProfileData/MemProfReader.cpp @@ -32,7 +32,7 @@ #include "llvm/ProfileData/InstrProf.h" #include "llvm/ProfileData/MemProf.h" #include "llvm/ProfileData/MemProfData.inc" -#include "llvm/ProfileData/RawMemProfReader.h" +#include "llvm/ProfileData/MemProfReader.h" #include "llvm/ProfileData/SampleProf.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Endian.h" @@ -295,8 +295,8 @@ Error RawMemProfReader::initialize(std::unique_ptr DataBuffer) { // Check whether the profiled binary was built with position independent code // (PIC). Perform sanity checks for assumptions we rely on to simplify // symbolization. - auto* Elf64LEObject = llvm::cast(ElfObject); - const llvm::object::ELF64LEFile& ElfFile = Elf64LEObject->getELFFile(); + auto *Elf64LEObject = llvm::cast(ElfObject); + const llvm::object::ELF64LEFile &ElfFile = Elf64LEObject->getELFFile(); auto PHdrsOr = ElfFile.program_headers(); if (!PHdrsOr) return report( diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index 0b78564ccea3..6a70773613b7 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -19,8 +19,8 @@ #include "llvm/ProfileData/InstrProfReader.h" #include "llvm/ProfileData/InstrProfWriter.h" #include "llvm/ProfileData/MemProf.h" +#include "llvm/ProfileData/MemProfReader.h" #include "llvm/ProfileData/ProfileCommon.h" -#include "llvm/ProfileData/RawMemProfReader.h" #include "llvm/ProfileData/SampleProfReader.h" #include "llvm/ProfileData/SampleProfWriter.h" #include "llvm/Support/BalancedPartitioning.h" diff --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp index f1aa6f37aa39..9cf307472d65 100644 --- a/llvm/unittests/ProfileData/MemProfTest.cpp +++ b/llvm/unittests/ProfileData/MemProfTest.cpp @@ -6,7 +6,7 @@ #include "llvm/IR/Value.h" #include "llvm/Object/ObjectFile.h" #include "llvm/ProfileData/MemProfData.inc" -#include "llvm/ProfileData/RawMemProfReader.h" +#include "llvm/ProfileData/MemProfReader.h" #include "llvm/Support/raw_ostream.h" #include "gmock/gmock.h" #include "gtest/gtest.h" diff --git a/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn index 51568ac0472c..9dbfe0f94c1d 100644 --- a/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/ProfileData/BUILD.gn @@ -16,8 +16,8 @@ static_library("ProfileData") { "InstrProfWriter.cpp", "ItaniumManglingCanonicalizer.cpp", "MemProf.cpp", + "MemProfReader.cpp", "ProfileSummaryBuilder.cpp", - "RawMemProfReader.cpp", "SampleProf.cpp", "SampleProfReader.cpp", "SampleProfWriter.cpp", -- GitLab From bd32aaa8c9ec2094f605315b3989adc2a567ca98 Mon Sep 17 00:00:00 2001 From: Cyrill Leutwiler Date: Thu, 11 Apr 2024 07:11:51 +0200 Subject: [PATCH 483/695] [RISCV] Support rv{32, 64}e in the compiler builtins (#88252) Register spills (save/restore) in RISC-V embedded work differently because there are less registers and different stack alignment. [GCC equivalent ](https://github.com/gcc-mirror/gcc/blob/master/libgcc/config/riscv/save-restore.S#L298C16-L336) Follow up from #76777. --------- Signed-off-by: xermicus --- compiler-rt/lib/builtins/riscv/restore.S | 42 ++++++++++++++++++++++++ compiler-rt/lib/builtins/riscv/save.S | 42 ++++++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/compiler-rt/lib/builtins/riscv/restore.S b/compiler-rt/lib/builtins/riscv/restore.S index 73f64a920d66..6f43842c8ca6 100644 --- a/compiler-rt/lib/builtins/riscv/restore.S +++ b/compiler-rt/lib/builtins/riscv/restore.S @@ -22,6 +22,8 @@ #if __riscv_xlen == 32 +#ifndef __riscv_32e + .globl __riscv_restore_12 .type __riscv_restore_12,@function __riscv_restore_12: @@ -86,8 +88,29 @@ __riscv_restore_0: addi sp, sp, 16 ret +#else + + .globl __riscv_restore_2 + .type __riscv_restore_2,@function + .globl __riscv_restore_1 + .type __riscv_restore_1,@function + .globl __riscv_restore_0 + .type __riscv_restore_0,@function +__riscv_restore_2: +__riscv_restore_1: +__riscv_restore_0: + lw s1, 0(sp) + lw s0, 4(sp) + lw ra, 8(sp) + addi sp, sp, 12 + ret + +#endif + #elif __riscv_xlen == 64 +#ifndef __riscv_64e + .globl __riscv_restore_12 .type __riscv_restore_12,@function __riscv_restore_12: @@ -161,6 +184,25 @@ __riscv_restore_0: addi sp, sp, 16 ret +#else + + .globl __riscv_restore_2 + .type __riscv_restore_2,@function + .globl __riscv_restore_1 + .type __riscv_restore_1,@function + .globl __riscv_restore_0 + .type __riscv_restore_0,@function +__riscv_restore_2: +__riscv_restore_1: +__riscv_restore_0: + ld s1, 0(sp) + ld s0, 8(sp) + ld ra, 16(sp) + addi sp, sp, 24 + ret + +#endif + #else # error "xlen must be 32 or 64 for save-restore implementation #endif diff --git a/compiler-rt/lib/builtins/riscv/save.S b/compiler-rt/lib/builtins/riscv/save.S index 85501aeb4c2e..3e044179ff7f 100644 --- a/compiler-rt/lib/builtins/riscv/save.S +++ b/compiler-rt/lib/builtins/riscv/save.S @@ -18,6 +18,8 @@ #if __riscv_xlen == 32 +#ifndef __riscv_32e + .globl __riscv_save_12 .type __riscv_save_12,@function __riscv_save_12: @@ -92,8 +94,29 @@ __riscv_save_0: sw ra, 12(sp) jr t0 +#else + + .globl __riscv_save_2 + .type __riscv_save_2,@function + .globl __riscv_save_1 + .type __riscv_save_1,@function + .globl __riscv_save_0 + .type __riscv_save_0,@function +__riscv_save_2: +__riscv_save_1: +__riscv_save_0: + addi sp, sp, -12 + sw s1, 0(sp) + sw s0, 4(sp) + sw ra, 8(sp) + jr t0 + +#endif + #elif __riscv_xlen == 64 +#ifndef __riscv_64e + .globl __riscv_save_12 .type __riscv_save_12,@function __riscv_save_12: @@ -181,6 +204,25 @@ __riscv_save_0: sd ra, 8(sp) jr t0 +#else + + .globl __riscv_save_2 + .type __riscv_save_2,@function + .globl __riscv_save_1 + .type __riscv_save_1,@function + .globl __riscv_save_0 + .type __riscv_save_0,@function +__riscv_save_2: +__riscv_save_1: +__riscv_save_0: + addi sp, sp, -24 + sd s1, 0(sp) + sd s0, 8(sp) + sd ra, 16(sp) + jr t0 + +#endif + #else # error "xlen must be 32 or 64 for save-restore implementation #endif -- GitLab From 5964c944bfe74cee2872cddb66eff22866cdb6ee Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Wed, 10 Apr 2024 22:25:37 -0700 Subject: [PATCH 484/695] [clangd] Fix test case due to clang-format bug fix (#88352) See commit 51f1681424f1. --- clang-tools-extra/clangd/unittests/HoverTests.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/clang-tools-extra/clangd/unittests/HoverTests.cpp b/clang-tools-extra/clangd/unittests/HoverTests.cpp index 35db757b9c15..5ead74748f55 100644 --- a/clang-tools-extra/clangd/unittests/HoverTests.cpp +++ b/clang-tools-extra/clangd/unittests/HoverTests.cpp @@ -1983,10 +1983,14 @@ TEST(Hover, All) { HI.Kind = index::SymbolKind::Macro; HI.Definition = R"cpp(#define MACRO \ - { return 0; } + { \ + return 0; \ + } // Expands to -{ return 0; })cpp"; +{ + return 0; +})cpp"; }}, { R"cpp(// Forward class declaration -- GitLab From 45146082e693415f37413c656e0a0fd13d0e3136 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Wed, 10 Apr 2024 23:11:24 -0700 Subject: [PATCH 485/695] [ELF] relocateNonAlloc & ICF: replace random access iterators of relocations with input iterators. NFC Also replace one `this->file` with a local variable as some function calls are opaque to the compiler, causing unneeded reload. --- lld/ELF/ICF.cpp | 22 ++++++++++++---------- lld/ELF/InputSection.cpp | 16 ++++++++-------- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/lld/ELF/ICF.cpp b/lld/ELF/ICF.cpp index 2551c2e807b7..bfc605c793a9 100644 --- a/lld/ELF/ICF.cpp +++ b/lld/ELF/ICF.cpp @@ -239,16 +239,17 @@ bool ICF::constantEq(const InputSection *secA, ArrayRef ra, const InputSection *secB, ArrayRef rb) { if (ra.size() != rb.size()) return false; - for (size_t i = 0; i < ra.size(); ++i) { - if (ra[i].r_offset != rb[i].r_offset || - ra[i].getType(config->isMips64EL) != rb[i].getType(config->isMips64EL)) + auto rai = ra.begin(), rae = ra.end(), rbi = rb.begin(); + for (; rai != rae; ++rai, ++rbi) { + if (rai->r_offset != rbi->r_offset || + rai->getType(config->isMips64EL) != rbi->getType(config->isMips64EL)) return false; - uint64_t addA = getAddend(ra[i]); - uint64_t addB = getAddend(rb[i]); + uint64_t addA = getAddend(*rai); + uint64_t addB = getAddend(*rbi); - Symbol &sa = secA->file->getRelocTargetSym(ra[i]); - Symbol &sb = secB->file->getRelocTargetSym(rb[i]); + Symbol &sa = secA->file->getRelocTargetSym(*rai); + Symbol &sb = secB->file->getRelocTargetSym(*rbi); if (&sa == &sb) { if (addA == addB) continue; @@ -336,10 +337,11 @@ bool ICF::variableEq(const InputSection *secA, ArrayRef ra, const InputSection *secB, ArrayRef rb) { assert(ra.size() == rb.size()); - for (size_t i = 0; i < ra.size(); ++i) { + auto rai = ra.begin(), rae = ra.end(), rbi = rb.begin(); + for (; rai != rae; ++rai, ++rbi) { // The two sections must be identical. - Symbol &sa = secA->file->getRelocTargetSym(ra[i]); - Symbol &sb = secB->file->getRelocTargetSym(rb[i]); + Symbol &sa = secA->file->getRelocTargetSym(*rai); + Symbol &sb = secB->file->getRelocTargetSym(*rbi); if (&sa == &sb) continue; diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index c06816bcfd56..c8350652e65a 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -918,8 +918,9 @@ void InputSection::relocateNonAlloc(uint8_t *buf, ArrayRef rels) { break; } - for (size_t i = 0, relsSize = rels.size(); i != relsSize; ++i) { - const RelTy &rel = rels[i]; + const InputFile *f = this->file; + for (auto it = rels.begin(), end = rels.end(); it != end; ++it) { + const RelTy &rel = *it; const RelType type = rel.getType(config->isMips64EL); const uint64_t offset = rel.r_offset; uint8_t *bufLoc = buf + offset; @@ -927,23 +928,22 @@ void InputSection::relocateNonAlloc(uint8_t *buf, ArrayRef rels) { if (!RelTy::IsRela) addend += target.getImplicitAddend(bufLoc, type); - Symbol &sym = this->file->getRelocTargetSym(rel); + Symbol &sym = f->getRelocTargetSym(rel); RelExpr expr = target.getRelExpr(type, sym, bufLoc); if (expr == R_NONE) continue; auto *ds = dyn_cast(&sym); if (emachine == EM_RISCV && type == R_RISCV_SET_ULEB128) { - if (++i < relsSize && - rels[i].getType(/*isMips64EL=*/false) == R_RISCV_SUB_ULEB128 && - rels[i].r_offset == offset) { + if (++it != end && + it->getType(/*isMips64EL=*/false) == R_RISCV_SUB_ULEB128 && + it->r_offset == offset) { uint64_t val; if (!ds && tombstone) { val = *tombstone; } else { val = sym.getVA(addend) - - (this->file->getRelocTargetSym(rels[i]).getVA(0) + - getAddend(rels[i])); + (f->getRelocTargetSym(*it).getVA(0) + getAddend(*it)); } if (overwriteULEB128(bufLoc, val) >= 0x80) errorOrWarn(getLocation(offset) + ": ULEB128 value " + Twine(val) + -- GitLab From 71f1932b842793e5dc7b17051452e8ff2f9219aa Mon Sep 17 00:00:00 2001 From: martinboehme Date: Thu, 11 Apr 2024 08:20:35 +0200 Subject: [PATCH 486/695] [clang][dataflow] Reland #87320: Propagate locations from result objects to initializers. (#88316) This relands #87320 and additionally removes the now-unused function `isOriginalRecordConstructor()`, which was causing buildbots to fail. --- .../FlowSensitive/DataflowEnvironment.h | 64 ++- .../FlowSensitive/DataflowEnvironment.cpp | 427 +++++++++++++----- clang/lib/Analysis/FlowSensitive/Transfer.cpp | 176 ++++---- .../TypeErasedDataflowAnalysis.cpp | 13 +- .../FlowSensitive/DataflowEnvironmentTest.cpp | 43 ++ .../Analysis/FlowSensitive/TransferTest.cpp | 172 ++++--- 6 files changed, 590 insertions(+), 305 deletions(-) diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index 9a65f76cdf56..706664d7db1c 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -30,6 +30,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" +#include #include #include @@ -344,17 +345,6 @@ public: /// location of the result object to pass in `this`, even though prvalues are /// otherwise not associated with storage locations. /// - /// FIXME: Currently, this simply returns a stable storage location for `E`, - /// but this doesn't do the right thing in scenarios like the following: - /// ``` - /// MyClass c = some_condition()? MyClass(foo) : MyClass(bar); - /// ``` - /// Here, `MyClass(foo)` and `MyClass(bar)` will have two different storage - /// locations, when in fact their storage locations should be the same. - /// Eventually, we want to propagate storage locations from result objects - /// down to the prvalues that initialize them, similar to the way that this is - /// done in Clang's CodeGen. - /// /// Requirements: /// `E` must be a prvalue of record type. RecordStorageLocation & @@ -462,7 +452,13 @@ public: /// Initializes the fields (including synthetic fields) of `Loc` with values, /// unless values of the field type are not supported or we hit one of the /// limits at which we stop producing values. - void initializeFieldsWithValues(RecordStorageLocation &Loc); + /// If `Type` is provided, initializes only those fields that are modeled for + /// `Type`; this is intended for use in cases where `Loc` is a derived type + /// and we only want to initialize the fields of a base type. + void initializeFieldsWithValues(RecordStorageLocation &Loc, QualType Type); + void initializeFieldsWithValues(RecordStorageLocation &Loc) { + initializeFieldsWithValues(Loc, Loc.getType()); + } /// Assigns `Val` as the value of `Loc` in the environment. void setValue(const StorageLocation &Loc, Value &Val); @@ -653,6 +649,9 @@ public: LLVM_DUMP_METHOD void dump(raw_ostream &OS) const; private: + using PrValueToResultObject = + llvm::DenseMap; + // The copy-constructor is for use in fork() only. Environment(const Environment &) = default; @@ -682,8 +681,10 @@ private: /// Initializes the fields (including synthetic fields) of `Loc` with values, /// unless values of the field type are not supported or we hit one of the /// limits at which we stop producing values (controlled by `Visited`, - /// `Depth`, and `CreatedValuesCount`). - void initializeFieldsWithValues(RecordStorageLocation &Loc, + /// `Depth`, and `CreatedValuesCount`). If `Type` is different from + /// `Loc.getType()`, initializes only those fields that are modeled for + /// `Type`. + void initializeFieldsWithValues(RecordStorageLocation &Loc, QualType Type, llvm::DenseSet &Visited, int Depth, int &CreatedValuesCount); @@ -702,22 +703,45 @@ private: /// and functions referenced in `FuncDecl`. `FuncDecl` must have a body. void initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl); + static PrValueToResultObject + buildResultObjectMap(DataflowAnalysisContext *DACtx, + const FunctionDecl *FuncDecl, + RecordStorageLocation *ThisPointeeLoc, + RecordStorageLocation *LocForRecordReturnVal); + // `DACtx` is not null and not owned by this object. DataflowAnalysisContext *DACtx; - // FIXME: move the fields `CallStack`, `ReturnVal`, `ReturnLoc` and - // `ThisPointeeLoc` into a separate call-context object, shared between - // environments in the same call. + // FIXME: move the fields `CallStack`, `ResultObjectMap`, `ReturnVal`, + // `ReturnLoc` and `ThisPointeeLoc` into a separate call-context object, + // shared between environments in the same call. // https://github.com/llvm/llvm-project/issues/59005 // `DeclContext` of the block being analysed if provided. std::vector CallStack; - // Value returned by the function (if it has non-reference return type). + // Maps from prvalues of record type to their result objects. Shared between + // all environments for the same function. + // FIXME: It's somewhat unsatisfactory that we have to use a `shared_ptr` + // here, though the cost is acceptable: The overhead of a `shared_ptr` is + // incurred when it is copied, and this happens only relatively rarely (when + // we fork the environment). The need for a `shared_ptr` will go away once we + // introduce a shared call-context object (see above). + std::shared_ptr ResultObjectMap; + + // The following three member variables handle various different types of + // return values. + // - If the return type is not a reference and not a record: Value returned + // by the function. Value *ReturnVal = nullptr; - // Storage location of the reference returned by the function (if it has - // reference return type). + // - If the return type is a reference: Storage location of the reference + // returned by the function. StorageLocation *ReturnLoc = nullptr; + // - If the return type is a record or the function being analyzed is a + // constructor: Storage location into which the return value should be + // constructed. + RecordStorageLocation *LocForRecordReturnVal = nullptr; + // The storage location of the `this` pointee. Should only be null if the // function being analyzed is only a function and not a method. RecordStorageLocation *ThisPointeeLoc = nullptr; diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 1bfa7ebcfd50..bea15ce9bd24 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -15,6 +15,7 @@ #include "clang/Analysis/FlowSensitive/DataflowEnvironment.h" #include "clang/AST/Decl.h" #include "clang/AST/DeclCXX.h" +#include "clang/AST/RecursiveASTVisitor.h" #include "clang/AST/Type.h" #include "clang/Analysis/FlowSensitive/DataflowLattice.h" #include "clang/Analysis/FlowSensitive/Value.h" @@ -26,6 +27,8 @@ #include #include +#define DEBUG_TYPE "dataflow" + namespace clang { namespace dataflow { @@ -354,6 +357,8 @@ getFieldsGlobalsAndFuncs(const Stmt &S, FieldSet &Fields, for (auto *Child : S.children()) if (Child != nullptr) getFieldsGlobalsAndFuncs(*Child, Fields, Vars, Funcs); + if (const auto *DefaultArg = dyn_cast(&S)) + getFieldsGlobalsAndFuncs(*DefaultArg->getExpr(), Fields, Vars, Funcs); if (const auto *DefaultInit = dyn_cast(&S)) getFieldsGlobalsAndFuncs(*DefaultInit->getExpr(), Fields, Vars, Funcs); @@ -386,6 +391,186 @@ getFieldsGlobalsAndFuncs(const Stmt &S, FieldSet &Fields, } } +namespace { + +// Visitor that builds a map from record prvalues to result objects. +// This traverses the body of the function to be analyzed; for each result +// object that it encounters, it propagates the storage location of the result +// object to all record prvalues that can initialize it. +class ResultObjectVisitor : public RecursiveASTVisitor { +public: + // `ResultObjectMap` will be filled with a map from record prvalues to result + // object. If the function being analyzed returns a record by value, + // `LocForRecordReturnVal` is the location to which this record should be + // written; otherwise, it is null. + explicit ResultObjectVisitor( + llvm::DenseMap &ResultObjectMap, + RecordStorageLocation *LocForRecordReturnVal, + DataflowAnalysisContext &DACtx) + : ResultObjectMap(ResultObjectMap), + LocForRecordReturnVal(LocForRecordReturnVal), DACtx(DACtx) {} + + bool shouldVisitImplicitCode() { return true; } + + bool shouldVisitLambdaBody() const { return false; } + + // Traverse all member and base initializers of `Ctor`. This function is not + // called by `RecursiveASTVisitor`; it should be called manually if we are + // analyzing a constructor. `ThisPointeeLoc` is the storage location that + // `this` points to. + void TraverseConstructorInits(const CXXConstructorDecl *Ctor, + RecordStorageLocation *ThisPointeeLoc) { + assert(ThisPointeeLoc != nullptr); + for (const CXXCtorInitializer *Init : Ctor->inits()) { + Expr *InitExpr = Init->getInit(); + if (FieldDecl *Field = Init->getMember(); + Field != nullptr && Field->getType()->isRecordType()) { + PropagateResultObject(InitExpr, cast( + ThisPointeeLoc->getChild(*Field))); + } else if (Init->getBaseClass()) { + PropagateResultObject(InitExpr, ThisPointeeLoc); + } + + // Ensure that any result objects within `InitExpr` (e.g. temporaries) + // are also propagated to the prvalues that initialize them. + TraverseStmt(InitExpr); + + // If this is a `CXXDefaultInitExpr`, also propagate any result objects + // within the default expression. + if (auto *DefaultInit = dyn_cast(InitExpr)) + TraverseStmt(DefaultInit->getExpr()); + } + } + + bool TraverseBindingDecl(BindingDecl *BD) { + // `RecursiveASTVisitor` doesn't traverse holding variables for + // `BindingDecl`s by itself, so we need to tell it to. + if (VarDecl *HoldingVar = BD->getHoldingVar()) + TraverseDecl(HoldingVar); + return RecursiveASTVisitor::TraverseBindingDecl(BD); + } + + bool VisitVarDecl(VarDecl *VD) { + if (VD->getType()->isRecordType() && VD->hasInit()) + PropagateResultObject( + VD->getInit(), + &cast(DACtx.getStableStorageLocation(*VD))); + return true; + } + + bool VisitMaterializeTemporaryExpr(MaterializeTemporaryExpr *MTE) { + if (MTE->getType()->isRecordType()) + PropagateResultObject( + MTE->getSubExpr(), + &cast(DACtx.getStableStorageLocation(*MTE))); + return true; + } + + bool VisitReturnStmt(ReturnStmt *Return) { + Expr *RetValue = Return->getRetValue(); + if (RetValue != nullptr && RetValue->getType()->isRecordType() && + RetValue->isPRValue()) + PropagateResultObject(RetValue, LocForRecordReturnVal); + return true; + } + + bool VisitExpr(Expr *E) { + // Clang's AST can have record-type prvalues without a result object -- for + // example as full-expressions contained in a compound statement or as + // arguments of call expressions. We notice this if we get here and a + // storage location has not yet been associated with `E`. In this case, + // treat this as if it was a `MaterializeTemporaryExpr`. + if (E->isPRValue() && E->getType()->isRecordType() && + !ResultObjectMap.contains(E)) + PropagateResultObject( + E, &cast(DACtx.getStableStorageLocation(*E))); + return true; + } + + // Assigns `Loc` as the result object location of `E`, then propagates the + // location to all lower-level prvalues that initialize the same object as + // `E` (or one of its base classes or member variables). + void PropagateResultObject(Expr *E, RecordStorageLocation *Loc) { + if (!E->isPRValue() || !E->getType()->isRecordType()) { + assert(false); + // Ensure we don't propagate the result object if we hit this in a + // release build. + return; + } + + ResultObjectMap[E] = Loc; + + // The following AST node kinds are "original initializers": They are the + // lowest-level AST node that initializes a given object, and nothing + // below them can initialize the same object (or part of it). + if (isa(E) || isa(E) || isa(E) || + isa(E) || isa(E) || + isa(E)) { + return; + } + + if (auto *InitList = dyn_cast(E)) { + if (!InitList->isSemanticForm()) + return; + if (InitList->isTransparent()) { + PropagateResultObject(InitList->getInit(0), Loc); + return; + } + + RecordInitListHelper InitListHelper(InitList); + + for (auto [Base, Init] : InitListHelper.base_inits()) { + assert(Base->getType().getCanonicalType() == + Init->getType().getCanonicalType()); + + // Storage location for the base class is the same as that of the + // derived class because we "flatten" the object hierarchy and put all + // fields in `RecordStorageLocation` of the derived class. + PropagateResultObject(Init, Loc); + } + + for (auto [Field, Init] : InitListHelper.field_inits()) { + // Fields of non-record type are handled in + // `TransferVisitor::VisitInitListExpr()`. + if (!Field->getType()->isRecordType()) + continue; + PropagateResultObject( + Init, cast(Loc->getChild(*Field))); + } + return; + } + + if (auto *Op = dyn_cast(E); Op && Op->isCommaOp()) { + PropagateResultObject(Op->getRHS(), Loc); + return; + } + + if (auto *Cond = dyn_cast(E)) { + PropagateResultObject(Cond->getTrueExpr(), Loc); + PropagateResultObject(Cond->getFalseExpr(), Loc); + return; + } + + // All other expression nodes that propagate a record prvalue should have + // exactly one child. + SmallVector Children(E->child_begin(), E->child_end()); + LLVM_DEBUG({ + if (Children.size() != 1) + E->dump(); + }); + assert(Children.size() == 1); + for (Stmt *S : Children) + PropagateResultObject(cast(S), Loc); + } + +private: + llvm::DenseMap &ResultObjectMap; + RecordStorageLocation *LocForRecordReturnVal; + DataflowAnalysisContext &DACtx; +}; + +} // namespace + Environment::Environment(DataflowAnalysisContext &DACtx) : DACtx(&DACtx), FlowConditionToken(DACtx.arena().makeFlowConditionToken()) {} @@ -401,17 +586,23 @@ void Environment::initialize() { if (DeclCtx == nullptr) return; - if (const auto *FuncDecl = dyn_cast(DeclCtx)) { - assert(FuncDecl->doesThisDeclarationHaveABody()); + const auto *FuncDecl = dyn_cast(DeclCtx); + if (FuncDecl == nullptr) + return; - initFieldsGlobalsAndFuncs(FuncDecl); + assert(FuncDecl->doesThisDeclarationHaveABody()); - for (const auto *ParamDecl : FuncDecl->parameters()) { - assert(ParamDecl != nullptr); - setStorageLocation(*ParamDecl, createObject(*ParamDecl, nullptr)); - } + initFieldsGlobalsAndFuncs(FuncDecl); + + for (const auto *ParamDecl : FuncDecl->parameters()) { + assert(ParamDecl != nullptr); + setStorageLocation(*ParamDecl, createObject(*ParamDecl, nullptr)); } + if (FuncDecl->getReturnType()->isRecordType()) + LocForRecordReturnVal = &cast( + createStorageLocation(FuncDecl->getReturnType())); + if (const auto *MethodDecl = dyn_cast(DeclCtx)) { auto *Parent = MethodDecl->getParent(); assert(Parent != nullptr); @@ -444,6 +635,12 @@ void Environment::initialize() { initializeFieldsWithValues(ThisLoc); } } + + // We do this below the handling of `CXXMethodDecl` above so that we can + // be sure that the storage location for `this` has been set. + ResultObjectMap = std::make_shared( + buildResultObjectMap(DACtx, FuncDecl, getThisPointeeStorageLocation(), + LocForRecordReturnVal)); } // FIXME: Add support for resetting globals after function calls to enable @@ -484,13 +681,18 @@ void Environment::initFieldsGlobalsAndFuncs(const FunctionDecl *FuncDecl) { if (getStorageLocation(*D) != nullptr) continue; - setStorageLocation(*D, createObject(*D)); + // We don't run transfer functions on the initializers of global variables, + // so they won't be associated with a value or storage location. We + // therefore intentionally don't pass an initializer to `createObject()`; + // in particular, this ensures that `createObject()` will initialize the + // fields of record-type variables with values. + setStorageLocation(*D, createObject(*D, nullptr)); } for (const FunctionDecl *FD : Funcs) { if (getStorageLocation(*FD) != nullptr) continue; - auto &Loc = createStorageLocation(FD->getType()); + auto &Loc = createStorageLocation(*FD); setStorageLocation(*FD, Loc); } } @@ -519,6 +721,9 @@ Environment Environment::pushCall(const CallExpr *Call) const { } } + if (Call->getType()->isRecordType() && Call->isPRValue()) + Env.LocForRecordReturnVal = &Env.getResultObjectLocation(*Call); + Env.pushCallInternal(Call->getDirectCallee(), llvm::ArrayRef(Call->getArgs(), Call->getNumArgs())); @@ -529,6 +734,7 @@ Environment Environment::pushCall(const CXXConstructExpr *Call) const { Environment Env(*this); Env.ThisPointeeLoc = &Env.getResultObjectLocation(*Call); + Env.LocForRecordReturnVal = &Env.getResultObjectLocation(*Call); Env.pushCallInternal(Call->getConstructor(), llvm::ArrayRef(Call->getArgs(), Call->getNumArgs())); @@ -557,6 +763,10 @@ void Environment::pushCallInternal(const FunctionDecl *FuncDecl, const VarDecl *Param = *ParamIt; setStorageLocation(*Param, createObject(*Param, Args[ArgIndex])); } + + ResultObjectMap = std::make_shared( + buildResultObjectMap(DACtx, FuncDecl, getThisPointeeStorageLocation(), + LocForRecordReturnVal)); } void Environment::popCall(const CallExpr *Call, const Environment &CalleeEnv) { @@ -600,6 +810,9 @@ bool Environment::equivalentTo(const Environment &Other, if (ReturnLoc != Other.ReturnLoc) return false; + if (LocForRecordReturnVal != Other.LocForRecordReturnVal) + return false; + if (ThisPointeeLoc != Other.ThisPointeeLoc) return false; @@ -623,8 +836,10 @@ LatticeEffect Environment::widen(const Environment &PrevEnv, assert(DACtx == PrevEnv.DACtx); assert(ReturnVal == PrevEnv.ReturnVal); assert(ReturnLoc == PrevEnv.ReturnLoc); + assert(LocForRecordReturnVal == PrevEnv.LocForRecordReturnVal); assert(ThisPointeeLoc == PrevEnv.ThisPointeeLoc); assert(CallStack == PrevEnv.CallStack); + assert(ResultObjectMap == PrevEnv.ResultObjectMap); auto Effect = LatticeEffect::Unchanged; @@ -656,12 +871,16 @@ Environment Environment::join(const Environment &EnvA, const Environment &EnvB, Environment::ValueModel &Model, ExprJoinBehavior ExprBehavior) { assert(EnvA.DACtx == EnvB.DACtx); + assert(EnvA.LocForRecordReturnVal == EnvB.LocForRecordReturnVal); assert(EnvA.ThisPointeeLoc == EnvB.ThisPointeeLoc); assert(EnvA.CallStack == EnvB.CallStack); + assert(EnvA.ResultObjectMap == EnvB.ResultObjectMap); Environment JoinedEnv(*EnvA.DACtx); JoinedEnv.CallStack = EnvA.CallStack; + JoinedEnv.ResultObjectMap = EnvA.ResultObjectMap; + JoinedEnv.LocForRecordReturnVal = EnvA.LocForRecordReturnVal; JoinedEnv.ThisPointeeLoc = EnvA.ThisPointeeLoc; if (EnvA.ReturnVal == nullptr || EnvB.ReturnVal == nullptr) { @@ -730,6 +949,12 @@ StorageLocation &Environment::createStorageLocation(const Expr &E) { void Environment::setStorageLocation(const ValueDecl &D, StorageLocation &Loc) { assert(!DeclToLoc.contains(&D)); + // The only kinds of declarations that may have a "variable" storage location + // are declarations of reference type and `BindingDecl`. For all other + // declaration, the storage location should be the stable storage location + // returned by `createStorageLocation()`. + assert(D.getType()->isReferenceType() || isa(D) || + &Loc == &createStorageLocation(D)); DeclToLoc[&D] = &Loc; } @@ -764,77 +989,34 @@ StorageLocation *Environment::getStorageLocation(const Expr &E) const { return It == ExprToLoc.end() ? nullptr : &*It->second; } -// Returns whether a prvalue of record type is the one that originally -// constructs the object (i.e. it doesn't propagate it from one of its -// children). -static bool isOriginalRecordConstructor(const Expr &RecordPRValue) { - if (auto *Init = dyn_cast(&RecordPRValue)) - return !Init->isSemanticForm() || !Init->isTransparent(); - return isa(RecordPRValue) || isa(RecordPRValue) || - isa(RecordPRValue) || - isa(RecordPRValue) || - isa(RecordPRValue) || - // The framework currently does not propagate the objects created in - // the two branches of a `ConditionalOperator` because there is no way - // to reconcile their storage locations, which are different. We - // therefore claim that the `ConditionalOperator` is the expression - // that originally constructs the object. - // Ultimately, this will be fixed by propagating locations down from - // the result object, rather than up from the original constructor as - // we do now (see also the FIXME in the documentation for - // `getResultObjectLocation()`). - isa(RecordPRValue); -} - RecordStorageLocation & Environment::getResultObjectLocation(const Expr &RecordPRValue) const { assert(RecordPRValue.getType()->isRecordType()); assert(RecordPRValue.isPRValue()); - // Returns a storage location that we can use if assertions fail. - auto FallbackForAssertFailure = - [this, &RecordPRValue]() -> RecordStorageLocation & { + assert(ResultObjectMap != nullptr); + RecordStorageLocation *Loc = ResultObjectMap->lookup(&RecordPRValue); + assert(Loc != nullptr); + // In release builds, use the "stable" storage location if the map lookup + // failed. + if (Loc == nullptr) return cast( DACtx->getStableStorageLocation(RecordPRValue)); - }; - - if (isOriginalRecordConstructor(RecordPRValue)) { - auto *Val = cast_or_null(getValue(RecordPRValue)); - // The builtin transfer function should have created a `RecordValue` for all - // original record constructors. - assert(Val); - if (!Val) - return FallbackForAssertFailure(); - return Val->getLoc(); - } - - if (auto *Op = dyn_cast(&RecordPRValue); - Op && Op->isCommaOp()) { - return getResultObjectLocation(*Op->getRHS()); - } - - // All other expression nodes that propagate a record prvalue should have - // exactly one child. - llvm::SmallVector children(RecordPRValue.child_begin(), - RecordPRValue.child_end()); - assert(children.size() == 1); - if (children.empty()) - return FallbackForAssertFailure(); - - return getResultObjectLocation(*cast(children[0])); + return *Loc; } PointerValue &Environment::getOrCreateNullPointerValue(QualType PointeeType) { return DACtx->getOrCreateNullPointerValue(PointeeType); } -void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc) { +void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, + QualType Type) { llvm::DenseSet Visited; int CreatedValuesCount = 0; - initializeFieldsWithValues(Loc, Visited, 0, CreatedValuesCount); + initializeFieldsWithValues(Loc, Type, Visited, 0, CreatedValuesCount); if (CreatedValuesCount > MaxCompositeValueSize) { - llvm::errs() << "Attempting to initialize a huge value of type: " - << Loc.getType() << '\n'; + llvm::errs() << "Attempting to initialize a huge value of type: " << Type + << '\n'; } } @@ -848,8 +1030,7 @@ void Environment::setValue(const Expr &E, Value &Val) { const Expr &CanonE = ignoreCFGOmittedNodes(E); if (auto *RecordVal = dyn_cast(&Val)) { - assert(isOriginalRecordConstructor(CanonE) || - &RecordVal->getLoc() == &getResultObjectLocation(CanonE)); + assert(&RecordVal->getLoc() == &getResultObjectLocation(CanonE)); (void)RecordVal; } @@ -928,7 +1109,8 @@ Value *Environment::createValueUnlessSelfReferential( if (Type->isRecordType()) { CreatedValuesCount++; auto &Loc = cast(createStorageLocation(Type)); - initializeFieldsWithValues(Loc, Visited, Depth, CreatedValuesCount); + initializeFieldsWithValues(Loc, Loc.getType(), Visited, Depth, + CreatedValuesCount); return &refreshRecordValue(Loc, *this); } @@ -960,6 +1142,7 @@ Environment::createLocAndMaybeValue(QualType Ty, } void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, + QualType Type, llvm::DenseSet &Visited, int Depth, int &CreatedValuesCount) { @@ -967,8 +1150,8 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, if (FieldType->isRecordType()) { auto &FieldRecordLoc = cast(FieldLoc); setValue(FieldRecordLoc, create(FieldRecordLoc)); - initializeFieldsWithValues(FieldRecordLoc, Visited, Depth + 1, - CreatedValuesCount); + initializeFieldsWithValues(FieldRecordLoc, FieldRecordLoc.getType(), + Visited, Depth + 1, CreatedValuesCount); } else { if (!Visited.insert(FieldType.getCanonicalType()).second) return; @@ -979,7 +1162,7 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, } }; - for (const auto &[Field, FieldLoc] : Loc.children()) { + for (const FieldDecl *Field : DACtx->getModeledFields(Type)) { assert(Field != nullptr); QualType FieldType = Field->getType(); @@ -988,14 +1171,12 @@ void Environment::initializeFieldsWithValues(RecordStorageLocation &Loc, &createLocAndMaybeValue(FieldType, Visited, Depth + 1, CreatedValuesCount)); } else { + StorageLocation *FieldLoc = Loc.getChild(*Field); assert(FieldLoc != nullptr); initField(FieldType, *FieldLoc); } } - for (const auto &[FieldName, FieldLoc] : Loc.synthetic_fields()) { - assert(FieldLoc != nullptr); - QualType FieldType = FieldLoc->getType(); - + for (const auto &[FieldName, FieldType] : DACtx->getSyntheticFields(Type)) { // Synthetic fields cannot have reference type, so we don't need to deal // with this case. assert(!FieldType->isReferenceType()); @@ -1022,38 +1203,36 @@ StorageLocation &Environment::createObjectInternal(const ValueDecl *D, return createObjectInternal(D, Ty.getNonReferenceType(), nullptr); } - Value *Val = nullptr; - if (InitExpr) { - // In the (few) cases where an expression is intentionally - // "uninterpreted", `InitExpr` is not associated with a value. There are - // two ways to handle this situation: propagate the status, so that - // uninterpreted initializers result in uninterpreted variables, or - // provide a default value. We choose the latter so that later refinements - // of the variable can be used for reasoning about the surrounding code. - // For this reason, we let this case be handled by the `createValue()` - // call below. - // - // FIXME. If and when we interpret all language cases, change this to - // assert that `InitExpr` is interpreted, rather than supplying a - // default value (assuming we don't update the environment API to return - // references). - Val = getValue(*InitExpr); - - if (!Val && isa(InitExpr) && - InitExpr->getType()->isPointerType()) - Val = &getOrCreateNullPointerValue(InitExpr->getType()->getPointeeType()); - } - if (!Val) - Val = createValue(Ty); - - if (Ty->isRecordType()) - return cast(Val)->getLoc(); - StorageLocation &Loc = D ? createStorageLocation(*D) : createStorageLocation(Ty); - if (Val) - setValue(Loc, *Val); + if (Ty->isRecordType()) { + auto &RecordLoc = cast(Loc); + if (!InitExpr) + initializeFieldsWithValues(RecordLoc); + refreshRecordValue(RecordLoc, *this); + } else { + Value *Val = nullptr; + if (InitExpr) + // In the (few) cases where an expression is intentionally + // "uninterpreted", `InitExpr` is not associated with a value. There are + // two ways to handle this situation: propagate the status, so that + // uninterpreted initializers result in uninterpreted variables, or + // provide a default value. We choose the latter so that later refinements + // of the variable can be used for reasoning about the surrounding code. + // For this reason, we let this case be handled by the `createValue()` + // call below. + // + // FIXME. If and when we interpret all language cases, change this to + // assert that `InitExpr` is interpreted, rather than supplying a + // default value (assuming we don't update the environment API to return + // references). + Val = getValue(*InitExpr); + if (!Val) + Val = createValue(Ty); + if (Val) + setValue(Loc, *Val); + } return Loc; } @@ -1072,6 +1251,8 @@ bool Environment::allows(const Formula &F) const { void Environment::dump(raw_ostream &OS) const { llvm::DenseMap LocToName; + if (LocForRecordReturnVal != nullptr) + LocToName[LocForRecordReturnVal] = "(returned record)"; if (ThisPointeeLoc != nullptr) LocToName[ThisPointeeLoc] = "this"; @@ -1102,6 +1283,9 @@ void Environment::dump(raw_ostream &OS) const { if (auto Iter = LocToName.find(ReturnLoc); Iter != LocToName.end()) OS << " (" << Iter->second << ")"; OS << "\n"; + } else if (Func->getReturnType()->isRecordType() || + isa(Func)) { + OS << "LocForRecordReturnVal: " << LocForRecordReturnVal << "\n"; } else if (!Func->getReturnType()->isVoidType()) { if (ReturnVal == nullptr) OS << "ReturnVal: nullptr\n"; @@ -1122,6 +1306,22 @@ void Environment::dump() const { dump(llvm::dbgs()); } +Environment::PrValueToResultObject Environment::buildResultObjectMap( + DataflowAnalysisContext *DACtx, const FunctionDecl *FuncDecl, + RecordStorageLocation *ThisPointeeLoc, + RecordStorageLocation *LocForRecordReturnVal) { + assert(FuncDecl->doesThisDeclarationHaveABody()); + + PrValueToResultObject Map; + + ResultObjectVisitor Visitor(Map, LocForRecordReturnVal, *DACtx); + if (const auto *Ctor = dyn_cast(FuncDecl)) + Visitor.TraverseConstructorInits(Ctor, ThisPointeeLoc); + Visitor.TraverseStmt(FuncDecl->getBody()); + + return Map; +} + RecordStorageLocation *getImplicitObjectLocation(const CXXMemberCallExpr &MCE, const Environment &Env) { Expr *ImplicitObject = MCE.getImplicitObjectArgument(); @@ -1216,24 +1416,11 @@ RecordValue &refreshRecordValue(RecordStorageLocation &Loc, Environment &Env) { RecordValue &refreshRecordValue(const Expr &Expr, Environment &Env) { assert(Expr.getType()->isRecordType()); - if (Expr.isPRValue()) { - if (auto *ExistingVal = Env.get(Expr)) { - auto &NewVal = Env.create(ExistingVal->getLoc()); - Env.setValue(Expr, NewVal); - Env.setValue(NewVal.getLoc(), NewVal); - return NewVal; - } + if (Expr.isPRValue()) + refreshRecordValue(Env.getResultObjectLocation(Expr), Env); - auto &NewVal = *cast(Env.createValue(Expr.getType())); - Env.setValue(Expr, NewVal); - return NewVal; - } - - if (auto *Loc = Env.get(Expr)) { - auto &NewVal = Env.create(*Loc); - Env.setValue(*Loc, NewVal); - return NewVal; - } + if (auto *Loc = Env.get(Expr)) + refreshRecordValue(*Loc, Env); auto &NewVal = *cast(Env.createValue(Expr.getType())); Env.setStorageLocation(Expr, NewVal.getLoc()); diff --git a/clang/lib/Analysis/FlowSensitive/Transfer.cpp b/clang/lib/Analysis/FlowSensitive/Transfer.cpp index 0a2e8368d541..88a9c0eccbeb 100644 --- a/clang/lib/Analysis/FlowSensitive/Transfer.cpp +++ b/clang/lib/Analysis/FlowSensitive/Transfer.cpp @@ -460,11 +460,9 @@ public: // So make sure we have a value if we didn't propagate one above. if (S->isPRValue() && S->getType()->isRecordType()) { if (Env.getValue(*S) == nullptr) { - Value *Val = Env.createValue(S->getType()); - // We're guaranteed to always be able to create a value for record - // types. - assert(Val != nullptr); - Env.setValue(*S, *Val); + auto &Loc = Env.getResultObjectLocation(*S); + Env.initializeFieldsWithValues(Loc); + refreshRecordValue(Loc, Env); } } } @@ -472,6 +470,13 @@ public: void VisitCXXDefaultInitExpr(const CXXDefaultInitExpr *S) { const Expr *InitExpr = S->getExpr(); assert(InitExpr != nullptr); + + // If this is a prvalue of record type, the handler for `*InitExpr` (if one + // exists) will initialize the result object; there is no value to propgate + // here. + if (S->getType()->isRecordType() && S->isPRValue()) + return; + propagateValueOrStorageLocation(*InitExpr, *S, Env); } @@ -479,6 +484,17 @@ public: const CXXConstructorDecl *ConstructorDecl = S->getConstructor(); assert(ConstructorDecl != nullptr); + // `CXXConstructExpr` can have array type if default-initializing an array + // of records. We don't handle this specifically beyond potentially inlining + // the call. + if (!S->getType()->isRecordType()) { + transferInlineCall(S, ConstructorDecl); + return; + } + + RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); + Env.setValue(*S, refreshRecordValue(Loc, Env)); + if (ConstructorDecl->isCopyOrMoveConstructor()) { // It is permissible for a copy/move constructor to have additional // parameters as long as they have default arguments defined for them. @@ -491,24 +507,14 @@ public: if (ArgLoc == nullptr) return; - if (S->isElidable()) { - if (Value *Val = Env.getValue(*ArgLoc)) - Env.setValue(*S, *Val); - } else { - auto &Val = *cast(Env.createValue(S->getType())); - Env.setValue(*S, Val); - copyRecord(*ArgLoc, Val.getLoc(), Env); - } + // Even if the copy/move constructor call is elidable, we choose to copy + // the record in all cases (which isn't wrong, just potentially not + // optimal). + copyRecord(*ArgLoc, Loc, Env); return; } - // `CXXConstructExpr` can have array type if default-initializing an array - // of records, and we currently can't create values for arrays. So check if - // we've got a record type. - if (S->getType()->isRecordType()) { - auto &InitialVal = *cast(Env.createValue(S->getType())); - Env.setValue(*S, InitialVal); - } + Env.initializeFieldsWithValues(Loc, S->getType()); transferInlineCall(S, ConstructorDecl); } @@ -551,19 +557,15 @@ public: if (S->isGLValue()) { Env.setStorageLocation(*S, *LocDst); } else if (S->getType()->isRecordType()) { - // Make sure that we have a `RecordValue` for this expression so that - // `Environment::getResultObjectLocation()` is able to return a location - // for it. - if (Env.getValue(*S) == nullptr) - refreshRecordValue(*S, Env); + // Assume that the assignment returns the assigned value. + copyRecord(*LocDst, Env.getResultObjectLocation(*S), Env); } return; } - // CXXOperatorCallExpr can be prvalues. Call `VisitCallExpr`() to create - // a `RecordValue` for them so that `Environment::getResultObjectLocation()` - // can return a value. + // `CXXOperatorCallExpr` can be a prvalue. Call `VisitCallExpr`() to + // initialize the prvalue's fields with values. VisitCallExpr(S); } @@ -580,11 +582,6 @@ public: } } - void VisitCXXTemporaryObjectExpr(const CXXTemporaryObjectExpr *S) { - if (Value *Val = Env.createValue(S->getType())) - Env.setValue(*S, *Val); - } - void VisitCallExpr(const CallExpr *S) { // Of clang's builtins, only `__builtin_expect` is handled explicitly, since // others (like trap, debugtrap, and unreachable) are handled by CFG @@ -612,13 +609,14 @@ public: } else if (const FunctionDecl *F = S->getDirectCallee()) { transferInlineCall(S, F); - // If this call produces a prvalue of record type, make sure that we have - // a `RecordValue` for it. This is required so that - // `Environment::getResultObjectLocation()` is able to return a location - // for this `CallExpr`. + // If this call produces a prvalue of record type, initialize its fields + // with values. if (S->getType()->isRecordType() && S->isPRValue()) - if (Env.getValue(*S) == nullptr) - refreshRecordValue(*S, Env); + if (Env.getValue(*S) == nullptr) { + RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); + Env.initializeFieldsWithValues(Loc); + Env.setValue(*S, refreshRecordValue(Loc, Env)); + } } } @@ -666,8 +664,10 @@ public: // `getLogicOperatorSubExprValue()`. if (S->isGLValue()) Env.setStorageLocation(*S, Env.createObject(S->getType())); - else if (Value *Val = Env.createValue(S->getType())) - Env.setValue(*S, *Val); + else if (!S->getType()->isRecordType()) { + if (Value *Val = Env.createValue(S->getType())) + Env.setValue(*S, *Val); + } } void VisitInitListExpr(const InitListExpr *S) { @@ -688,71 +688,51 @@ public: return; } - llvm::DenseMap FieldLocs; - RecordInitListHelper InitListHelper(S); + RecordStorageLocation &Loc = Env.getResultObjectLocation(*S); + Env.setValue(*S, refreshRecordValue(Loc, Env)); - for (auto [Base, Init] : InitListHelper.base_inits()) { - assert(Base->getType().getCanonicalType() == - Init->getType().getCanonicalType()); - auto *BaseVal = Env.get(*Init); - if (!BaseVal) - BaseVal = cast(Env.createValue(Init->getType())); - // Take ownership of the fields of the `RecordValue` for the base class - // and incorporate them into the "flattened" set of fields for the - // derived class. - auto Children = BaseVal->getLoc().children(); - FieldLocs.insert(Children.begin(), Children.end()); - } + // Initialization of base classes and fields of record type happens when we + // visit the nested `CXXConstructExpr` or `InitListExpr` for that base class + // or field. We therefore only need to deal with fields of non-record type + // here. - for (auto [Field, Init] : InitListHelper.field_inits()) { - assert( - // The types are same, or - Field->getType().getCanonicalType().getUnqualifiedType() == - Init->getType().getCanonicalType().getUnqualifiedType() || - // The field's type is T&, and initializer is T - (Field->getType()->isReferenceType() && - Field->getType().getCanonicalType()->getPointeeType() == - Init->getType().getCanonicalType())); - auto& Loc = Env.createObject(Field->getType(), Init); - FieldLocs.insert({Field, &Loc}); - } + RecordInitListHelper InitListHelper(S); - // In the case of a union, we don't in general have initializers for all - // of the fields. Create storage locations for the remaining fields (but - // don't associate them with values). - if (Type->isUnionType()) { - for (const FieldDecl *Field : - Env.getDataflowAnalysisContext().getModeledFields(Type)) { - if (auto [it, inserted] = FieldLocs.insert({Field, nullptr}); inserted) - it->second = &Env.createStorageLocation(Field->getType()); + for (auto [Field, Init] : InitListHelper.field_inits()) { + if (Field->getType()->isRecordType()) + continue; + if (Field->getType()->isReferenceType()) { + assert(Field->getType().getCanonicalType()->getPointeeType() == + Init->getType().getCanonicalType()); + Loc.setChild(*Field, &Env.createObject(Field->getType(), Init)); + continue; } + assert(Field->getType().getCanonicalType().getUnqualifiedType() == + Init->getType().getCanonicalType().getUnqualifiedType()); + StorageLocation *FieldLoc = Loc.getChild(*Field); + // Locations for non-reference fields must always be non-null. + assert(FieldLoc != nullptr); + Value *Val = Env.getValue(*Init); + if (Val == nullptr && isa(Init) && + Init->getType()->isPointerType()) + Val = + &Env.getOrCreateNullPointerValue(Init->getType()->getPointeeType()); + if (Val == nullptr) + Val = Env.createValue(Field->getType()); + if (Val != nullptr) + Env.setValue(*FieldLoc, *Val); } - // Check that we satisfy the invariant that a `RecordStorageLoation` - // contains exactly the set of modeled fields for that type. - // `ModeledFields` includes fields from all the bases, but only the - // modeled ones. However, if a class type is initialized with an - // `InitListExpr`, all fields in the class, including those from base - // classes, are included in the set of modeled fields. The code above - // should therefore populate exactly the modeled fields. - assert(containsSameFields( - Env.getDataflowAnalysisContext().getModeledFields(Type), FieldLocs)); - - RecordStorageLocation::SyntheticFieldMap SyntheticFieldLocs; - for (const auto &Entry : - Env.getDataflowAnalysisContext().getSyntheticFields(Type)) { - SyntheticFieldLocs.insert( - {Entry.getKey(), &Env.createObject(Entry.getValue())}); + for (const auto &[FieldName, FieldLoc] : Loc.synthetic_fields()) { + QualType FieldType = FieldLoc->getType(); + if (FieldType->isRecordType()) { + Env.initializeFieldsWithValues(*cast(FieldLoc)); + } else { + if (Value *Val = Env.createValue(FieldType)) + Env.setValue(*FieldLoc, *Val); + } } - auto &Loc = Env.getDataflowAnalysisContext().createRecordStorageLocation( - Type, std::move(FieldLocs), std::move(SyntheticFieldLocs)); - RecordValue &RecordVal = Env.create(Loc); - - Env.setValue(Loc, RecordVal); - - Env.setValue(*S, RecordVal); - // FIXME: Implement array initialization. } diff --git a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp index 595f70f819dd..1b73c5d68301 100644 --- a/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp +++ b/clang/lib/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.cpp @@ -369,17 +369,10 @@ builtinTransferInitializer(const CFGInitializer &Elt, ParentLoc->setChild(*Member, InitExprLoc); } else if (auto *InitExprVal = Env.getValue(*InitExpr)) { assert(MemberLoc != nullptr); - if (Member->getType()->isRecordType()) { - auto *InitValStruct = cast(InitExprVal); - // FIXME: Rather than performing a copy here, we should really be - // initializing the field in place. This would require us to propagate the - // storage location of the field to the AST node that creates the - // `RecordValue`. - copyRecord(InitValStruct->getLoc(), - *cast(MemberLoc), Env); - } else { + // Record-type initializers construct themselves directly into the result + // object, so there is no need to handle them here. + if (!Member->getType()->isRecordType()) Env.setValue(*MemberLoc, *InitExprVal); - } } } diff --git a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp index 465a8e21690c..cc20623f881f 100644 --- a/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp @@ -24,6 +24,7 @@ namespace { using namespace clang; using namespace dataflow; +using ::clang::dataflow::test::findValueDecl; using ::clang::dataflow::test::getFieldValue; using ::testing::Contains; using ::testing::IsNull; @@ -199,6 +200,48 @@ TEST_F(EnvironmentTest, JoinRecords) { } } +TEST_F(EnvironmentTest, DifferentReferenceLocInJoin) { + // This tests the case where the storage location for a reference-type + // variable is different for two states being joined. We used to believe this + // could not happen and therefore had an assertion disallowing this; this test + // exists to demonstrate that we can handle this condition without a failing + // assertion. See also the discussion here: + // https://discourse.llvm.org/t/70086/6 + + using namespace ast_matchers; + + std::string Code = R"cc( + void f(int &ref) {} + )cc"; + + auto Unit = + tooling::buildASTFromCodeWithArgs(Code, {"-fsyntax-only", "-std=c++11"}); + auto &Context = Unit->getASTContext(); + + ASSERT_EQ(Context.getDiagnostics().getClient()->getNumErrors(), 0U); + + const ValueDecl *Ref = findValueDecl(Context, "ref"); + + Environment Env1(DAContext); + StorageLocation &Loc1 = Env1.createStorageLocation(Context.IntTy); + Env1.setStorageLocation(*Ref, Loc1); + + Environment Env2(DAContext); + StorageLocation &Loc2 = Env2.createStorageLocation(Context.IntTy); + Env2.setStorageLocation(*Ref, Loc2); + + EXPECT_NE(&Loc1, &Loc2); + + Environment::ValueModel Model; + Environment EnvJoined = + Environment::join(Env1, Env2, Model, Environment::DiscardExprState); + + // Joining environments with different storage locations for the same + // declaration results in the declaration being removed from the joined + // environment. + EXPECT_EQ(EnvJoined.getStorageLocation(*Ref), nullptr); +} + TEST_F(EnvironmentTest, InitGlobalVarsFun) { using namespace ast_matchers; diff --git a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp index ca055a462a28..00dafb2988c6 100644 --- a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp @@ -1582,10 +1582,9 @@ TEST(TransferTest, FieldsDontHaveValuesInConstructorWithBaseClass) { [](const llvm::StringMap> &Results, ASTContext &ASTCtx) { const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - // FIXME: The field of the base class should already have been - // initialized with a value by the base constructor. This test documents - // the current buggy behavior. - EXPECT_EQ(getFieldValue(Env.getThisPointeeStorageLocation(), "BaseVal", + // The field of the base class should already have been initialized with + // a value by the base constructor. + EXPECT_NE(getFieldValue(Env.getThisPointeeStorageLocation(), "BaseVal", ASTCtx, Env), nullptr); EXPECT_EQ(getFieldValue(Env.getThisPointeeStorageLocation(), "Val", @@ -2998,8 +2997,12 @@ TEST(TransferTest, ResultObjectLocation) { TEST(TransferTest, ResultObjectLocationForDefaultArgExpr) { std::string Code = R"( - struct S {}; - void funcWithDefaultArg(S s = S()); + struct Inner {}; + struct Outer { + Inner I = {}; + }; + + void funcWithDefaultArg(Outer O = {}); void target() { funcWithDefaultArg(); // [[p]] @@ -3058,13 +3061,7 @@ TEST(TransferTest, ResultObjectLocationForDefaultInitExpr) { RecordStorageLocation &Loc = Env.getResultObjectLocation(*DefaultInit); - // FIXME: The result object location for the `CXXDefaultInitExpr` should - // be the location of the member variable being initialized, but we - // don't do this correctly yet; see also comments in - // `builtinTransferInitializer()`. - // For the time being, we just document the current erroneous behavior - // here (this should be `EXPECT_EQ` when the behavior is fixed). - EXPECT_NE(&Loc, Env.getThisPointeeStorageLocation()->getChild(*SField)); + EXPECT_EQ(&Loc, Env.getThisPointeeStorageLocation()->getChild(*SField)); }); } @@ -3101,6 +3098,79 @@ TEST(TransferTest, ResultObjectLocationForCXXOperatorCallExpr) { }); } +TEST(TransferTest, ResultObjectLocationForStdInitializerListExpr) { + std::string Code = R"( + namespace std { + template + struct initializer_list {}; + } // namespace std + + void target() { + std::initializer_list list = {1}; + // [[p]] + } + )"; + + using ast_matchers::cxxStdInitializerListExpr; + using ast_matchers::match; + using ast_matchers::selectFirst; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + auto *StdInitList = selectFirst( + "std_init_list", + match(cxxStdInitializerListExpr().bind("std_init_list"), ASTCtx)); + ASSERT_NE(StdInitList, nullptr); + + EXPECT_EQ(&Env.getResultObjectLocation(*StdInitList), + &getLocForDecl(ASTCtx, Env, "list")); + }); +} + +TEST(TransferTest, ResultObjectLocationPropagatesThroughConditionalOperator) { + std::string Code = R"( + struct A { + A(int); + }; + + void target(bool b) { + A a = b ? A(0) : A(1); + (void)0; // [[p]] + } + )"; + using ast_matchers::cxxConstructExpr; + using ast_matchers::equals; + using ast_matchers::hasArgument; + using ast_matchers::integerLiteral; + using ast_matchers::match; + using ast_matchers::selectFirst; + using ast_matchers::traverse; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + auto *ConstructExpr0 = selectFirst( + "construct", + match(cxxConstructExpr(hasArgument(0, integerLiteral(equals(0)))) + .bind("construct"), + ASTCtx)); + auto *ConstructExpr1 = selectFirst( + "construct", + match(cxxConstructExpr(hasArgument(0, integerLiteral(equals(1)))) + .bind("construct"), + ASTCtx)); + + auto &ALoc = getLocForDecl(ASTCtx, Env, "a"); + EXPECT_EQ(&Env.getResultObjectLocation(*ConstructExpr0), &ALoc); + EXPECT_EQ(&Env.getResultObjectLocation(*ConstructExpr1), &ALoc); + }); +} + TEST(TransferTest, StaticCast) { std::string Code = R"( void target(int Foo) { @@ -5886,6 +5956,38 @@ TEST(TransferTest, ContextSensitiveReturnRecord) { {BuiltinOptions{ContextSensitiveOptions{}}}); } +TEST(TransferTest, ContextSensitiveReturnSelfReferentialRecord) { + std::string Code = R"( + struct S { + S() { self = this; } + S *self; + }; + + S makeS() { + // RVO guarantees that this will be constructed directly into `MyS`. + return S(); + } + + void target() { + S MyS = makeS(); + // [[p]] + } + )"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); + + auto &MySLoc = getLocForDecl(ASTCtx, Env, "MyS"); + + auto *SelfVal = + cast(getFieldValue(&MySLoc, "self", ASTCtx, Env)); + EXPECT_EQ(&SelfVal->getPointeeLoc(), &MySLoc); + }, + {BuiltinOptions{ContextSensitiveOptions{}}}); +} + TEST(TransferTest, ContextSensitiveMethodLiteral) { std::string Code = R"( class MyClass { @@ -6830,50 +6932,6 @@ TEST(TransferTest, LambdaCaptureThis) { }); } -TEST(TransferTest, DifferentReferenceLocInJoin) { - // This test triggers a case where the storage location for a reference-type - // variable is different for two states being joined. We used to believe this - // could not happen and therefore had an assertion disallowing this; this test - // exists to demonstrate that we can handle this condition without a failing - // assertion. See also the discussion here: - // https://discourse.llvm.org/t/70086/6 - std::string Code = R"( - namespace std { - template struct initializer_list { - const T* begin(); - const T* end(); - }; - } - - void target(char* p, char* end) { - while (p != end) { - if (*p == ' ') { - p++; - continue; - } - - auto && range = {1, 2}; - for (auto b = range.begin(), e = range.end(); b != e; ++b) { - } - (void)0; - // [[p]] - } - } - )"; - runDataflow( - Code, - [](const llvm::StringMap> &Results, - ASTContext &ASTCtx) { - const Environment &Env = getEnvironmentAtAnnotation(Results, "p"); - - // Joining environments with different storage locations for the same - // declaration results in the declaration being removed from the joined - // environment. - const ValueDecl *VD = findValueDecl(ASTCtx, "range"); - ASSERT_EQ(Env.getStorageLocation(*VD), nullptr); - }); -} - // This test verifies correct modeling of a relational dependency that goes // through unmodeled functions (the simple `cond()` in this case). TEST(TransferTest, ConditionalRelation) { -- GitLab From 297eca981ea1133388c82ddbfaf9d86391abac65 Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Thu, 11 Apr 2024 08:23:48 +0200 Subject: [PATCH 487/695] [mlir][Interfaces] `ValueBoundsOpInterface`: Add API to compare values (#86915) This commit adds a new public API to `ValueBoundsOpInterface` to compare values/dims. Supported comparison operators are: LT, LE, EQ, GE, GT. The new `ValueBoundsOpInterface::compare` API replaces and generalizes `ValueBoundsOpInterface::areEqual`. Not only does it provide additional comparison operators, it also works in cases where the difference between the two values/dims is non-constant. The previous implementation of `areEqual` used to compute a constant bound of `val1 - val2` (check if it `== 0` or `!= 0`). Note: This commit refactors, generalizes and adds a public API for value/dim comparison. The comparison functionality itself was introduced in #85895 and is already in use for analyzing `scf.if`. In the long term, this improvement will allow for a more powerful analysis of subset ops. A future commit will update `areOverlappingSlices` to use the new comparison API. (`areEquivalentSlices` is already using the new API.) This will improve subset equivalence/disjointness checks with non-constant offsets/sizes/strides. --- .../mlir/Interfaces/ValueBoundsOpInterface.h | 57 ++++- .../SCF/IR/ValueBoundsOpInterfaceImpl.cpp | 31 +-- .../lib/Interfaces/ValueBoundsOpInterface.cpp | 237 +++++++++++++----- .../value-bounds-op-interface-impl.mlir | 43 +++- .../SCF/value-bounds-op-interface-impl.mlir | 12 + .../value-bounds-op-interface-impl.mlir | 16 +- .../Dialect/Affine/TestReifyValueBounds.cpp | 79 +++++- 7 files changed, 361 insertions(+), 114 deletions(-) diff --git a/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h b/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h index 3543ab52407a..1d7bc6ea961c 100644 --- a/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h +++ b/mlir/include/mlir/Interfaces/ValueBoundsOpInterface.h @@ -211,7 +211,8 @@ public: /// Comparison operator for `ValueBoundsConstraintSet::compare`. enum ComparisonOperator { LT, LE, EQ, GT, GE }; - /// Try to prove that, based on the current state of this constraint set + /// Populate constraints for lhs/rhs (until the stop condition is met). Then, + /// try to prove that, based on the current state of this constraint set /// (i.e., without analyzing additional IR or adding new constraints), the /// "lhs" value/dim is LE/LT/EQ/GT/GE than the "rhs" value/dim. /// @@ -220,24 +221,37 @@ public: /// proven. This could be because the specified relation does in fact not hold /// or because there is not enough information in the constraint set. In other /// words, if we do not know for sure, this function returns "false". - bool compare(Value lhs, std::optional lhsDim, ComparisonOperator cmp, - Value rhs, std::optional rhsDim); + bool populateAndCompare(OpFoldResult lhs, std::optional lhsDim, + ComparisonOperator cmp, OpFoldResult rhs, + std::optional rhsDim); + + /// Return "true" if "lhs cmp rhs" was proven to hold. Return "false" if the + /// specified relation could not be proven. This could be because the + /// specified relation does in fact not hold or because there is not enough + /// information in the constraint set. In other words, if we do not know for + /// sure, this function returns "false". + /// + /// This function keeps traversing the backward slice of lhs/rhs until could + /// prove the relation or until it ran out of IR. + static bool compare(OpFoldResult lhs, std::optional lhsDim, + ComparisonOperator cmp, OpFoldResult rhs, + std::optional rhsDim); + static bool compare(AffineMap lhs, ValueDimList lhsOperands, + ComparisonOperator cmp, AffineMap rhs, + ValueDimList rhsOperands); + static bool compare(AffineMap lhs, ArrayRef lhsOperands, + ComparisonOperator cmp, AffineMap rhs, + ArrayRef rhsOperands); /// Compute whether the given values/dimensions are equal. Return "failure" if /// equality could not be determined. /// /// `dim1`/`dim2` must be `nullopt` if and only if `value1`/`value2` are /// index-typed. - static FailureOr areEqual(Value value1, Value value2, + static FailureOr areEqual(OpFoldResult value1, OpFoldResult value2, std::optional dim1 = std::nullopt, std::optional dim2 = std::nullopt); - /// Compute whether the given values/attributes are equal. Return "failure" if - /// equality could not be determined. - /// - /// `ofr1`/`ofr2` must be of index type. - static FailureOr areEqual(OpFoldResult ofr1, OpFoldResult ofr2); - /// Return "true" if the given slices are guaranteed to be overlapping. /// Return "false" if the given slices are guaranteed to be non-overlapping. /// Return "failure" if unknown. @@ -294,6 +308,20 @@ protected: ValueBoundsConstraintSet(MLIRContext *ctx, StopConditionFn stopCondition); + /// Return "true" if, based on the current state of the constraint system, + /// "lhs cmp rhs" was proven to hold. Return "false" if the specified relation + /// could not be proven. This could be because the specified relation does in + /// fact not hold or because there is not enough information in the constraint + /// set. In other words, if we do not know for sure, this function returns + /// "false". + /// + /// This function does not analyze any IR and does not populate any additional + /// constraints. + bool compareValueDims(OpFoldResult lhs, std::optional lhsDim, + ComparisonOperator cmp, OpFoldResult rhs, + std::optional rhsDim); + bool comparePos(int64_t lhsPos, ComparisonOperator cmp, int64_t rhsPos); + /// Given an affine map with a single result (and map operands), add a new /// column to the constraint set that represents the result of the map. /// Traverse additional IR starting from the map operands as needed (as long @@ -319,6 +347,10 @@ protected: /// set. AffineExpr getPosExpr(int64_t pos); + /// Return "true" if the given value/dim is mapped (i.e., has a corresponding + /// column in the constraint system). + bool isMapped(Value value, std::optional dim = std::nullopt) const; + /// Insert a value/dimension into the constraint set. If `isSymbol` is set to /// "false", a dimension is added. The value/dimension is added to the /// worklist if `addToWorklist` is set. @@ -338,6 +370,11 @@ protected: /// dimensions but not for symbols. int64_t insert(bool isSymbol = true); + /// Insert the given affine map and its bound operands as a new column in the + /// constraint system. Return the position of the new column. Any operands + /// that were not analyzed yet are put on the worklist. + int64_t insert(AffineMap map, ValueDimList operands, bool isSymbol = true); + /// Project out the given column in the constraint set. void projectOut(int64_t pos); diff --git a/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp b/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp index 72c5aaa23067..087ffc438a83 100644 --- a/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/SCF/IR/ValueBoundsOpInterfaceImpl.cpp @@ -58,20 +58,11 @@ struct ForOpInterface Value iterArg = forOp.getRegionIterArg(iterArgIdx); Value initArg = forOp.getInitArgs()[iterArgIdx]; - // Populate constraints for the yielded value. - cstr.populateConstraints(yieldedValue, dim); - // Populate constraints for the iter_arg. This is just to ensure that the - // iter_arg is mapped in the constraint set, which is a prerequisite for - // `compare`. It may lead to a recursive call to this function in case the - // iter_arg was not visited when the constraints for the yielded value were - // populated, but no additional work is done. - cstr.populateConstraints(iterArg, dim); - // An EQ constraint can be added if the yielded value (dimension size) // equals the corresponding block argument (dimension size). - if (cstr.compare(yieldedValue, dim, - ValueBoundsConstraintSet::ComparisonOperator::EQ, iterArg, - dim)) { + if (cstr.populateAndCompare( + yieldedValue, dim, ValueBoundsConstraintSet::ComparisonOperator::EQ, + iterArg, dim)) { if (dim.has_value()) { cstr.bound(value)[*dim] == cstr.getExpr(initArg, dim); } else { @@ -113,10 +104,6 @@ struct IfOpInterface Value thenValue = ifOp.thenYield().getResults()[resultNum]; Value elseValue = ifOp.elseYield().getResults()[resultNum]; - // Populate constraints for the yielded value (and all values on the - // backward slice, as long as the current stop condition is not satisfied). - cstr.populateConstraints(thenValue, dim); - cstr.populateConstraints(elseValue, dim); auto boundsBuilder = cstr.bound(value); if (dim) boundsBuilder[*dim]; @@ -125,9 +112,9 @@ struct IfOpInterface // If thenValue <= elseValue: // * result <= elseValue // * result >= thenValue - if (cstr.compare(thenValue, dim, - ValueBoundsConstraintSet::ComparisonOperator::LE, - elseValue, dim)) { + if (cstr.populateAndCompare( + thenValue, dim, ValueBoundsConstraintSet::ComparisonOperator::LE, + elseValue, dim)) { if (dim) { cstr.bound(value)[*dim] >= cstr.getExpr(thenValue, dim); cstr.bound(value)[*dim] <= cstr.getExpr(elseValue, dim); @@ -139,9 +126,9 @@ struct IfOpInterface // If elseValue <= thenValue: // * result <= thenValue // * result >= elseValue - if (cstr.compare(elseValue, dim, - ValueBoundsConstraintSet::ComparisonOperator::LE, - thenValue, dim)) { + if (cstr.populateAndCompare( + elseValue, dim, ValueBoundsConstraintSet::ComparisonOperator::LE, + thenValue, dim)) { if (dim) { cstr.bound(value)[*dim] >= cstr.getExpr(elseValue, dim); cstr.bound(value)[*dim] <= cstr.getExpr(thenValue, dim); diff --git a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp index 6e3d6dd3c757..c138056ab41c 100644 --- a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp +++ b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp @@ -202,6 +202,28 @@ int64_t ValueBoundsConstraintSet::insert(bool isSymbol) { return pos; } +int64_t ValueBoundsConstraintSet::insert(AffineMap map, ValueDimList operands, + bool isSymbol) { + assert(map.getNumResults() == 1 && "expected affine map with one result"); + int64_t pos = insert(/*isSymbol=*/false); + + // Add map and operands to the constraint set. Dimensions are converted to + // symbols. All operands are added to the worklist (unless they were already + // processed). + auto mapper = [&](std::pair> v) { + return getExpr(v.first, v.second); + }; + SmallVector dimReplacements = llvm::to_vector( + llvm::map_range(ArrayRef(operands).take_front(map.getNumDims()), mapper)); + SmallVector symReplacements = llvm::to_vector( + llvm::map_range(ArrayRef(operands).drop_front(map.getNumDims()), mapper)); + addBound( + presburger::BoundType::EQ, pos, + map.getResult(0).replaceDimsAndSymbols(dimReplacements, symReplacements)); + + return pos; +} + int64_t ValueBoundsConstraintSet::getPos(Value value, std::optional dim) const { #ifndef NDEBUG @@ -224,6 +246,13 @@ AffineExpr ValueBoundsConstraintSet::getPosExpr(int64_t pos) { : builder.getAffineSymbolExpr(pos - cstr.getNumDimVars()); } +bool ValueBoundsConstraintSet::isMapped(Value value, + std::optional dim) const { + auto it = + valueDimToPosition.find(std::make_pair(value, dim.value_or(kIndexValue))); + return it != valueDimToPosition.end(); +} + static Operation *getOwnerOfValue(Value value) { if (auto bbArg = dyn_cast(value)) return bbArg.getOwner()->getParentOp(); @@ -560,27 +589,10 @@ void ValueBoundsConstraintSet::populateConstraints(Value value, int64_t ValueBoundsConstraintSet::populateConstraints(AffineMap map, ValueDimList operands) { - assert(map.getNumResults() == 1 && "expected affine map with one result"); - int64_t pos = insert(/*isSymbol=*/false); - - // Add map and operands to the constraint set. Dimensions are converted to - // symbols. All operands are added to the worklist (unless they were already - // processed). - auto mapper = [&](std::pair> v) { - return getExpr(v.first, v.second); - }; - SmallVector dimReplacements = llvm::to_vector( - llvm::map_range(ArrayRef(operands).take_front(map.getNumDims()), mapper)); - SmallVector symReplacements = llvm::to_vector( - llvm::map_range(ArrayRef(operands).drop_front(map.getNumDims()), mapper)); - addBound( - presburger::BoundType::EQ, pos, - map.getResult(0).replaceDimsAndSymbols(dimReplacements, symReplacements)); - + int64_t pos = insert(map, operands, /*isSymbol=*/false); // Process the backward slice of `operands` (i.e., reverse use-def chain) // until `stopCondition` is met. processWorklist(); - return pos; } @@ -600,9 +612,18 @@ ValueBoundsConstraintSet::computeConstantDelta(Value value1, Value value2, {{value1, dim1}, {value2, dim2}}); } -bool ValueBoundsConstraintSet::compare(Value lhs, std::optional lhsDim, - ComparisonOperator cmp, Value rhs, - std::optional rhsDim) { +bool ValueBoundsConstraintSet::compareValueDims(OpFoldResult lhs, + std::optional lhsDim, + ComparisonOperator cmp, + OpFoldResult rhs, + std::optional rhsDim) { +#ifndef NDEBUG + if (auto lhsVal = dyn_cast(lhs)) + assertValidValueDim(lhsVal, lhsDim); + if (auto rhsVal = dyn_cast(rhs)) + assertValidValueDim(rhsVal, rhsDim); +#endif // NDEBUG + // This function returns "true" if "lhs CMP rhs" is proven to hold. // // Example for ComparisonOperator::LE and index-typed values: We would like to @@ -621,24 +642,32 @@ bool ValueBoundsConstraintSet::compare(Value lhs, std::optional lhsDim, // EQ can be expressed as LE and GE. if (cmp == EQ) - return compare(lhs, lhsDim, ComparisonOperator::LE, rhs, rhsDim) && - compare(lhs, lhsDim, ComparisonOperator::GE, rhs, rhsDim); + return compareValueDims(lhs, lhsDim, ComparisonOperator::LE, rhs, rhsDim) && + compareValueDims(lhs, lhsDim, ComparisonOperator::GE, rhs, rhsDim); // Construct inequality. For the above example: lhs > rhs. // `IntegerRelation` inequalities are expressed in the "flattened" form and // with ">= 0". I.e., lhs - rhs - 1 >= 0. - SmallVector eq(cstr.getNumDimAndSymbolVars() + 1, 0); + SmallVector eq(cstr.getNumCols(), 0); + auto addToEq = [&](OpFoldResult ofr, std::optional dim, + int64_t factor) { + if (auto constVal = ::getConstantIntValue(ofr)) { + eq[cstr.getNumCols() - 1] += *constVal * factor; + } else { + eq[getPos(cast(ofr), dim)] += factor; + } + }; if (cmp == LT || cmp == LE) { - ++eq[getPos(lhs, lhsDim)]; - --eq[getPos(rhs, rhsDim)]; + addToEq(lhs, lhsDim, 1); + addToEq(rhs, rhsDim, -1); } else if (cmp == GT || cmp == GE) { - --eq[getPos(lhs, lhsDim)]; - ++eq[getPos(rhs, rhsDim)]; + addToEq(lhs, lhsDim, -1); + addToEq(rhs, rhsDim, 1); } else { llvm_unreachable("unsupported comparison operator"); } if (cmp == LE || cmp == GE) - eq[cstr.getNumDimAndSymbolVars()] -= 1; + eq[cstr.getNumCols() - 1] -= 1; // Add inequality to the constraint set and check if it made the constraint // set empty. @@ -649,40 +678,128 @@ bool ValueBoundsConstraintSet::compare(Value lhs, std::optional lhsDim, return isEmpty; } +bool ValueBoundsConstraintSet::comparePos(int64_t lhsPos, + ComparisonOperator cmp, + int64_t rhsPos) { + // This function returns "true" if "lhs CMP rhs" is proven to hold. For + // detailed documentation, see `compareValueDims`. + + // EQ can be expressed as LE and GE. + if (cmp == EQ) + return comparePos(lhsPos, ComparisonOperator::LE, rhsPos) && + comparePos(lhsPos, ComparisonOperator::GE, rhsPos); + + // Construct inequality. + SmallVector eq(cstr.getNumCols(), 0); + if (cmp == LT || cmp == LE) { + ++eq[lhsPos]; + --eq[rhsPos]; + } else if (cmp == GT || cmp == GE) { + --eq[lhsPos]; + ++eq[rhsPos]; + } else { + llvm_unreachable("unsupported comparison operator"); + } + if (cmp == LE || cmp == GE) + eq[cstr.getNumCols() - 1] -= 1; + + // Add inequality to the constraint set and check if it made the constraint + // set empty. + int64_t ineqPos = cstr.getNumInequalities(); + cstr.addInequality(eq); + bool isEmpty = cstr.isEmpty(); + cstr.removeInequality(ineqPos); + return isEmpty; +} + +bool ValueBoundsConstraintSet::populateAndCompare( + OpFoldResult lhs, std::optional lhsDim, ComparisonOperator cmp, + OpFoldResult rhs, std::optional rhsDim) { +#ifndef NDEBUG + if (auto lhsVal = dyn_cast(lhs)) + assertValidValueDim(lhsVal, lhsDim); + if (auto rhsVal = dyn_cast(rhs)) + assertValidValueDim(rhsVal, rhsDim); +#endif // NDEBUG + + if (auto lhsVal = dyn_cast(lhs)) + populateConstraints(lhsVal, lhsDim); + if (auto rhsVal = dyn_cast(rhs)) + populateConstraints(rhsVal, rhsDim); + + return compareValueDims(lhs, lhsDim, cmp, rhs, rhsDim); +} + +bool ValueBoundsConstraintSet::compare(OpFoldResult lhs, + std::optional lhsDim, + ComparisonOperator cmp, OpFoldResult rhs, + std::optional rhsDim) { + auto stopCondition = [&](Value v, std::optional dim, + ValueBoundsConstraintSet &cstr) { + // Keep processing as long as lhs/rhs are not mapped. + if (auto lhsVal = dyn_cast(lhs)) + if (!cstr.isMapped(lhsVal, dim)) + return false; + if (auto rhsVal = dyn_cast(rhs)) + if (!cstr.isMapped(rhsVal, dim)) + return false; + // Keep processing as long as the relation cannot be proven. + return cstr.compareValueDims(lhs, lhsDim, cmp, rhs, rhsDim); + }; + + ValueBoundsConstraintSet cstr(lhs.getContext(), stopCondition); + return cstr.populateAndCompare(lhs, lhsDim, cmp, rhs, rhsDim); +} + +bool ValueBoundsConstraintSet::compare(AffineMap lhs, ValueDimList lhsOperands, + ComparisonOperator cmp, AffineMap rhs, + ValueDimList rhsOperands) { + int64_t lhsPos = -1, rhsPos = -1; + auto stopCondition = [&](Value v, std::optional dim, + ValueBoundsConstraintSet &cstr) { + // Keep processing as long as lhs/rhs were not processed. + if (lhsPos >= cstr.positionToValueDim.size() || + rhsPos >= cstr.positionToValueDim.size()) + return false; + // Keep processing as long as the relation cannot be proven. + return cstr.comparePos(lhsPos, cmp, rhsPos); + }; + ValueBoundsConstraintSet cstr(lhs.getContext(), stopCondition); + lhsPos = cstr.insert(lhs, lhsOperands); + rhsPos = cstr.insert(rhs, rhsOperands); + cstr.processWorklist(); + return cstr.comparePos(lhsPos, cmp, rhsPos); +} + +bool ValueBoundsConstraintSet::compare(AffineMap lhs, + ArrayRef lhsOperands, + ComparisonOperator cmp, AffineMap rhs, + ArrayRef rhsOperands) { + ValueDimList lhsValueDimOperands = + llvm::map_to_vector(lhsOperands, [](Value v) { + return std::make_pair(v, std::optional()); + }); + ValueDimList rhsValueDimOperands = + llvm::map_to_vector(rhsOperands, [](Value v) { + return std::make_pair(v, std::optional()); + }); + return ValueBoundsConstraintSet::compare(lhs, lhsValueDimOperands, cmp, rhs, + rhsValueDimOperands); +} + FailureOr -ValueBoundsConstraintSet::areEqual(Value value1, Value value2, +ValueBoundsConstraintSet::areEqual(OpFoldResult value1, OpFoldResult value2, std::optional dim1, std::optional dim2) { - // Subtract the two values/dimensions from each other. If the result is 0, - // both are equal. - FailureOr delta = computeConstantDelta(value1, value2, dim1, dim2); - if (failed(delta)) - return failure(); - return *delta == 0; -} - -FailureOr ValueBoundsConstraintSet::areEqual(OpFoldResult ofr1, - OpFoldResult ofr2) { - Builder b(ofr1.getContext()); - AffineMap map = - AffineMap::get(/*dimCount=*/0, /*symbolCount=*/2, - b.getAffineSymbolExpr(0) - b.getAffineSymbolExpr(1)); - SmallVector ofrOperands; - ofrOperands.push_back(ofr1); - ofrOperands.push_back(ofr2); - SmallVector valueOperands; - AffineMap foldedMap = - foldAttributesIntoMap(b, map, ofrOperands, valueOperands); - ValueDimList valueDims; - for (Value v : valueOperands) { - assert(v.getType().isIndex() && "expected index type"); - valueDims.emplace_back(v, std::nullopt); - } - FailureOr delta = - computeConstantBound(presburger::BoundType::EQ, foldedMap, valueDims); - if (failed(delta)) - return failure(); - return *delta == 0; + if (ValueBoundsConstraintSet::compare(value1, dim1, ComparisonOperator::EQ, + value2, dim2)) + return true; + if (ValueBoundsConstraintSet::compare(value1, dim1, ComparisonOperator::LT, + value2, dim2) || + ValueBoundsConstraintSet::compare(value1, dim1, ComparisonOperator::GT, + value2, dim2)) + return false; + return failure(); } FailureOr diff --git a/mlir/test/Dialect/Affine/value-bounds-op-interface-impl.mlir b/mlir/test/Dialect/Affine/value-bounds-op-interface-impl.mlir index 55282e8334ab..10da91870f49 100644 --- a/mlir/test/Dialect/Affine/value-bounds-op-interface-impl.mlir +++ b/mlir/test/Dialect/Affine/value-bounds-op-interface-impl.mlir @@ -79,6 +79,17 @@ func.func @composed_affine_apply(%i1 : index) -> (index) { } +// ----- + +func.func @are_equal(%i1 : index) { + %i2 = affine.apply affine_map<(d0) -> ((d0 floordiv 32) * 16)>(%i1) + %i3 = affine.apply affine_map<(d0) -> ((d0 floordiv 32) * 16 + 8)>(%i1) + %s = affine.apply affine_map<()[s0, s1] -> (s0 - s1)>()[%i2, %i3] + // expected-remark @below{{false}} + "test.compare"(%i2, %i3) : (index, index) -> () + return +} + // ----- // Test for affine::fullyComposeAndCheckIfEqual @@ -87,6 +98,36 @@ func.func @composed_are_equal(%i1 : index) { %i3 = affine.apply affine_map<(d0) -> ((d0 floordiv 32) * 16 + 8)>(%i1) %s = affine.apply affine_map<()[s0, s1] -> (s0 - s1)>()[%i2, %i3] // expected-remark @below{{different}} - "test.are_equal"(%i2, %i3) {compose} : (index, index) -> () + "test.compare"(%i2, %i3) {compose} : (index, index) -> () + return +} + +// ----- + +func.func @compare_affine_max(%a: index, %b: index) { + %0 = affine.max affine_map<()[s0, s1] -> (s0, s1)>()[%a, %b] + // expected-remark @below{{true}} + "test.compare"(%0, %a) {cmp = "GE"} : (index, index) -> () + // expected-error @below{{unknown}} + "test.compare"(%0, %a) {cmp = "GT"} : (index, index) -> () + // expected-remark @below{{false}} + "test.compare"(%0, %a) {cmp = "LT"} : (index, index) -> () + // expected-error @below{{unknown}} + "test.compare"(%0, %a) {cmp = "LE"} : (index, index) -> () + return +} + +// ----- + +func.func @compare_affine_min(%a: index, %b: index) { + %0 = affine.min affine_map<()[s0, s1] -> (s0, s1)>()[%a, %b] + // expected-error @below{{unknown}} + "test.compare"(%0, %a) {cmp = "GE"} : (index, index) -> () + // expected-remark @below{{false}} + "test.compare"(%0, %a) {cmp = "GT"} : (index, index) -> () + // expected-error @below{{unknown}} + "test.compare"(%0, %a) {cmp = "LT"} : (index, index) -> () + // expected-remark @below{{true}} + "test.compare"(%0, %a) {cmp = "LE"} : (index, index) -> () return } diff --git a/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir b/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir index 0ea06737886d..9ab03da1c9a9 100644 --- a/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir +++ b/mlir/test/Dialect/SCF/value-bounds-op-interface-impl.mlir @@ -219,3 +219,15 @@ func.func @scf_if_eq(%a: index, %b: index, %c : i1) { "test.some_use"(%reify1) : (index) -> () return } + +// ----- + +func.func @compare_scf_for(%a: index, %b: index, %c: index) { + scf.for %iv = %a to %b step %c { + // expected-remark @below{{true}} + "test.compare"(%iv, %a) {cmp = "GE"} : (index, index) -> () + // expected-remark @below{{true}} + "test.compare"(%iv, %b) {cmp = "LT"} : (index, index) -> () + } + return +} diff --git a/mlir/test/Dialect/Tensor/value-bounds-op-interface-impl.mlir b/mlir/test/Dialect/Tensor/value-bounds-op-interface-impl.mlir index 45520da6aeb0..0c90bcdb4202 100644 --- a/mlir/test/Dialect/Tensor/value-bounds-op-interface-impl.mlir +++ b/mlir/test/Dialect/Tensor/value-bounds-op-interface-impl.mlir @@ -163,8 +163,8 @@ func.func @dynamic_dims_are_equal(%t: tensor) { %c0 = arith.constant 0 : index %dim0 = tensor.dim %t, %c0 : tensor %dim1 = tensor.dim %t, %c0 : tensor - // expected-remark @below {{equal}} - "test.are_equal"(%dim0, %dim1) : (index, index) -> () + // expected-remark @below {{true}} + "test.compare"(%dim0, %dim1) : (index, index) -> () return } @@ -175,8 +175,8 @@ func.func @dynamic_dims_are_different(%t: tensor) { %c1 = arith.constant 1 : index %dim0 = tensor.dim %t, %c0 : tensor %val = arith.addi %dim0, %c1 : index - // expected-remark @below {{different}} - "test.are_equal"(%dim0, %val) : (index, index) -> () + // expected-remark @below {{false}} + "test.compare"(%dim0, %val) : (index, index) -> () return } @@ -186,8 +186,8 @@ func.func @dynamic_dims_are_maybe_equal_1(%t: tensor) { %c0 = arith.constant 0 : index %c5 = arith.constant 5 : index %dim0 = tensor.dim %t, %c0 : tensor - // expected-error @below {{could not determine equality}} - "test.are_equal"(%dim0, %c5) : (index, index) -> () + // expected-error @below {{unknown}} + "test.compare"(%dim0, %c5) : (index, index) -> () return } @@ -198,7 +198,7 @@ func.func @dynamic_dims_are_maybe_equal_2(%t: tensor) { %c1 = arith.constant 1 : index %dim0 = tensor.dim %t, %c0 : tensor %dim1 = tensor.dim %t, %c1 : tensor - // expected-error @below {{could not determine equality}} - "test.are_equal"(%dim0, %dim1) : (index, index) -> () + // expected-error @below {{unknown}} + "test.compare"(%dim0, %dim1) : (index, index) -> () return } diff --git a/mlir/test/lib/Dialect/Affine/TestReifyValueBounds.cpp b/mlir/test/lib/Dialect/Affine/TestReifyValueBounds.cpp index 4b2b1a06341b..f38631054fb3 100644 --- a/mlir/test/lib/Dialect/Affine/TestReifyValueBounds.cpp +++ b/mlir/test/lib/Dialect/Affine/TestReifyValueBounds.cpp @@ -57,7 +57,7 @@ private: } // namespace -FailureOr parseBoundType(const std::string &type) { +static FailureOr parseBoundType(const std::string &type) { if (type == "EQ") return BoundType::EQ; if (type == "LB") @@ -67,6 +67,34 @@ FailureOr parseBoundType(const std::string &type) { return failure(); } +static FailureOr +parseComparisonOperator(const std::string &type) { + if (type == "EQ") + return ValueBoundsConstraintSet::ComparisonOperator::EQ; + if (type == "LT") + return ValueBoundsConstraintSet::ComparisonOperator::LT; + if (type == "LE") + return ValueBoundsConstraintSet::ComparisonOperator::LE; + if (type == "GT") + return ValueBoundsConstraintSet::ComparisonOperator::GT; + if (type == "GE") + return ValueBoundsConstraintSet::ComparisonOperator::GE; + return failure(); +} + +static ValueBoundsConstraintSet::ComparisonOperator +invertComparisonOperator(ValueBoundsConstraintSet::ComparisonOperator cmp) { + if (cmp == ValueBoundsConstraintSet::ComparisonOperator::LT) + return ValueBoundsConstraintSet::ComparisonOperator::GE; + if (cmp == ValueBoundsConstraintSet::ComparisonOperator::LE) + return ValueBoundsConstraintSet::ComparisonOperator::GT; + if (cmp == ValueBoundsConstraintSet::ComparisonOperator::GT) + return ValueBoundsConstraintSet::ComparisonOperator::LE; + if (cmp == ValueBoundsConstraintSet::ComparisonOperator::GE) + return ValueBoundsConstraintSet::ComparisonOperator::LT; + llvm_unreachable("unsupported comparison operator"); +} + /// Look for "test.reify_bound" ops in the input and replace their results with /// the reified values. static LogicalResult testReifyValueBounds(func::FuncOp funcOp, @@ -215,18 +243,34 @@ static LogicalResult testReifyValueBounds(func::FuncOp funcOp, return failure(result.wasInterrupted()); } -/// Look for "test.are_equal" ops and emit errors/remarks. +/// Look for "test.compare" ops and emit errors/remarks. static LogicalResult testEquality(func::FuncOp funcOp) { IRRewriter rewriter(funcOp.getContext()); WalkResult result = funcOp.walk([&](Operation *op) { - // Look for test.are_equal ops. - if (op->getName().getStringRef() == "test.are_equal") { + // Look for test.compare ops. + if (op->getName().getStringRef() == "test.compare") { if (op->getNumOperands() != 2 || !op->getOperand(0).getType().isIndex() || !op->getOperand(1).getType().isIndex()) { op->emitOpError("invalid op"); return WalkResult::skip(); } + + // Get comparison operator. + std::string cmpStr = "EQ"; + if (auto cmpAttr = op->getAttrOfType("cmp")) + cmpStr = cmpAttr.str(); + auto cmpType = parseComparisonOperator(cmpStr); + if (failed(cmpType)) { + op->emitOpError("invalid comparison operator"); + return WalkResult::interrupt(); + } + if (op->hasAttr("compose")) { + if (cmpType != ValueBoundsConstraintSet::EQ) { + op->emitOpError( + "comparison operator must be EQ when 'composed' is specified"); + return WalkResult::interrupt(); + } FailureOr delta = affine::fullyComposeAndComputeConstantDelta( op->getOperand(0), op->getOperand(1)); if (failed(delta)) { @@ -236,16 +280,25 @@ static LogicalResult testEquality(func::FuncOp funcOp) { } else { op->emitRemark("different"); } + return WalkResult::advance(); + } + + auto compare = [&](ValueBoundsConstraintSet::ComparisonOperator cmp) { + return ValueBoundsConstraintSet::compare( + /*lhs=*/op->getOperand(0), /*lhsDim=*/std::nullopt, cmp, + /*rhs=*/op->getOperand(1), /*rhsDim=*/std::nullopt); + }; + if (compare(*cmpType)) { + op->emitRemark("true"); + } else if (*cmpType != ValueBoundsConstraintSet::EQ && + compare(invertComparisonOperator(*cmpType))) { + op->emitRemark("false"); + } else if (*cmpType == ValueBoundsConstraintSet::EQ && + (compare(ValueBoundsConstraintSet::ComparisonOperator::LT) || + compare(ValueBoundsConstraintSet::ComparisonOperator::GT))) { + op->emitRemark("false"); } else { - FailureOr equal = ValueBoundsConstraintSet::areEqual( - op->getOperand(0), op->getOperand(1)); - if (failed(equal)) { - op->emitError("could not determine equality"); - } else if (*equal) { - op->emitRemark("equal"); - } else { - op->emitRemark("different"); - } + op->emitError("unknown"); } } return WalkResult::advance(); -- GitLab From 21265f692e4b3b2146b6095cf23122b20e8fa0ed Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Thu, 11 Apr 2024 08:27:12 +0200 Subject: [PATCH 488/695] [mlir][Interfaces] `ValueBoundsOpInterface`: Fix typo (#87976) This was likely a copy-and-paste typo. --- mlir/lib/Interfaces/ValueBoundsOpInterface.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp index c138056ab41c..fa66da4a0def 100644 --- a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp +++ b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp @@ -205,7 +205,7 @@ int64_t ValueBoundsConstraintSet::insert(bool isSymbol) { int64_t ValueBoundsConstraintSet::insert(AffineMap map, ValueDimList operands, bool isSymbol) { assert(map.getNumResults() == 1 && "expected affine map with one result"); - int64_t pos = insert(/*isSymbol=*/false); + int64_t pos = insert(isSymbol); // Add map and operands to the constraint set. Dimensions are converted to // symbols. All operands are added to the worklist (unless they were already -- GitLab From dc39028906ba4196c3ba544c43ef6b428cf47c51 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Thu, 11 Apr 2024 14:50:40 +0800 Subject: [PATCH 489/695] [mlir] Fix -Wsign-compare in ValueBoundsOpInterface.cpp (NFC) /llvm-project/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp:762:16: error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare] rhsPos >= cstr.positionToValueDim.size()) ~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /llvm-project/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp:761:16: error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_t' (aka 'unsigned long') [-Werror,-Wsign-compare] if (lhsPos >= cstr.positionToValueDim.size() || ~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2 errors generated. --- mlir/lib/Interfaces/ValueBoundsOpInterface.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp index fa66da4a0def..ffa4c0b55cad 100644 --- a/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp +++ b/mlir/lib/Interfaces/ValueBoundsOpInterface.cpp @@ -758,8 +758,8 @@ bool ValueBoundsConstraintSet::compare(AffineMap lhs, ValueDimList lhsOperands, auto stopCondition = [&](Value v, std::optional dim, ValueBoundsConstraintSet &cstr) { // Keep processing as long as lhs/rhs were not processed. - if (lhsPos >= cstr.positionToValueDim.size() || - rhsPos >= cstr.positionToValueDim.size()) + if (size_t(lhsPos) >= cstr.positionToValueDim.size() || + size_t(rhsPos) >= cstr.positionToValueDim.size()) return false; // Keep processing as long as the relation cannot be proven. return cstr.comparePos(lhsPos, cmp, rhsPos); -- GitLab From 3f7f446d3803a699f5964a7429c6e1de0d783452 Mon Sep 17 00:00:00 2001 From: Haohai Wen Date: Thu, 11 Apr 2024 15:28:32 +0800 Subject: [PATCH 490/695] [llvm-profgen] Remove temporary perf script files (#86668) The temporary perf script files converted from perf data will occupy lots of space for large project. This patch removes them when llvm-profgen exits normally or receives signals. --- llvm/tools/llvm-profgen/PerfReader.cpp | 6 ++++++ llvm/tools/llvm-profgen/PerfReader.h | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/llvm/tools/llvm-profgen/PerfReader.cpp b/llvm/tools/llvm-profgen/PerfReader.cpp index 878147642aa6..e9442027aed3 100644 --- a/llvm/tools/llvm-profgen/PerfReader.cpp +++ b/llvm/tools/llvm-profgen/PerfReader.cpp @@ -11,6 +11,7 @@ #include "llvm/DebugInfo/Symbolize/SymbolizableModule.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Process.h" +#include "llvm/Support/ToolOutputFile.h" #define DEBUG_TYPE "perf-reader" @@ -375,6 +376,9 @@ PerfScriptReader::convertPerfDataToTrace(ProfiledBinary *Binary, StringRef(ErrorFile)}; // Stderr sys::ExecuteAndWait(PerfPath, ScriptMMapArgs, std::nullopt, Redirects); + PerfScriptReader::TempFileCleanups.emplace_back(PerfTraceFile); + PerfScriptReader::TempFileCleanups.emplace_back(ErrorFile); + // Collect the PIDs TraceStream TraceIt(PerfTraceFile); std::string PIDs; @@ -1220,5 +1224,7 @@ void PerfScriptReader::parsePerfTraces() { writeUnsymbolizedProfile(OutputFilename); } +SmallVector PerfScriptReader::TempFileCleanups; + } // end namespace sampleprof } // end namespace llvm diff --git a/llvm/tools/llvm-profgen/PerfReader.h b/llvm/tools/llvm-profgen/PerfReader.h index e9f619350bf9..b821cbe13efa 100644 --- a/llvm/tools/llvm-profgen/PerfReader.h +++ b/llvm/tools/llvm-profgen/PerfReader.h @@ -21,6 +21,9 @@ using namespace llvm; using namespace sampleprof; namespace llvm { + +class CleanupInstaller; + namespace sampleprof { // Stream based trace line iterator @@ -604,6 +607,11 @@ public: // Extract perf script type by peaking at the input static PerfContent checkPerfScriptType(StringRef FileName); + // Cleanup installers for temporary files created by perf script command. + // Those files will be automatically removed when running destructor or + // receiving signals. + static SmallVector TempFileCleanups; + protected: // The parsed MMap event struct MMapEvent { -- GitLab From a53674359da8507af539bf879e1b8292e3720eb8 Mon Sep 17 00:00:00 2001 From: David Green Date: Thu, 11 Apr 2024 08:45:28 +0100 Subject: [PATCH 491/695] [AArch64] Add ZIP and UZP shuffle costs. (#88150) This adds some costs for the shuffle instructions that should be lowered to zip1/zip2/uzp1/uzp2 instructions. --- .../Target/AArch64/AArch64ISelLowering.cpp | 29 -------- .../Target/AArch64/AArch64PerfectShuffle.h | 33 ++++++++++ .../AArch64/AArch64TargetTransformInfo.cpp | 10 +++ .../CostModel/AArch64/shuffle-other.ll | 66 +++++++++---------- .../CostModel/AArch64/shuffle-store.ll | 14 ++-- .../AArch64/vecreduce-shuffle.ll | 2 +- 6 files changed, 84 insertions(+), 70 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 744b2cdef504..80181a77c9d2 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -11851,35 +11851,6 @@ static bool isREVMask(ArrayRef M, EVT VT, unsigned BlockSize) { return true; } -static bool isZIPMask(ArrayRef M, EVT VT, unsigned &WhichResult) { - unsigned NumElts = VT.getVectorNumElements(); - if (NumElts % 2 != 0) - return false; - WhichResult = (M[0] == 0 ? 0 : 1); - unsigned Idx = WhichResult * NumElts / 2; - for (unsigned i = 0; i != NumElts; i += 2) { - if ((M[i] >= 0 && (unsigned)M[i] != Idx) || - (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts)) - return false; - Idx += 1; - } - - return true; -} - -static bool isUZPMask(ArrayRef M, EVT VT, unsigned &WhichResult) { - unsigned NumElts = VT.getVectorNumElements(); - WhichResult = (M[0] == 0 ? 0 : 1); - for (unsigned i = 0; i != NumElts; ++i) { - if (M[i] < 0) - continue; // ignore UNDEF indices - if ((unsigned)M[i] != 2 * i + WhichResult) - return false; - } - - return true; -} - static bool isTRNMask(ArrayRef M, EVT VT, unsigned &WhichResult) { unsigned NumElts = VT.getVectorNumElements(); if (NumElts % 2 != 0) diff --git a/llvm/lib/Target/AArch64/AArch64PerfectShuffle.h b/llvm/lib/Target/AArch64/AArch64PerfectShuffle.h index 5846fd454b65..7abaead694d1 100644 --- a/llvm/lib/Target/AArch64/AArch64PerfectShuffle.h +++ b/llvm/lib/Target/AArch64/AArch64PerfectShuffle.h @@ -16,6 +16,8 @@ #include "llvm/ADT/ArrayRef.h" +namespace llvm { + // 31 entries have cost 0 // 756 entries have cost 1 // 3690 entries have cost 2 @@ -6618,4 +6620,35 @@ static unsigned getPerfectShuffleCost(llvm::ArrayRef M) { return (PFEntry >> 30) + 1; } +inline bool isZIPMask(ArrayRef M, EVT VT, unsigned &WhichResult) { + unsigned NumElts = VT.getVectorNumElements(); + if (NumElts % 2 != 0) + return false; + WhichResult = (M[0] == 0 ? 0 : 1); + unsigned Idx = WhichResult * NumElts / 2; + for (unsigned i = 0; i != NumElts; i += 2) { + if ((M[i] >= 0 && (unsigned)M[i] != Idx) || + (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts)) + return false; + Idx += 1; + } + + return true; +} + +inline bool isUZPMask(ArrayRef M, EVT VT, unsigned &WhichResult) { + unsigned NumElts = VT.getVectorNumElements(); + WhichResult = (M[0] == 0 ? 0 : 1); + for (unsigned i = 0; i != NumElts; ++i) { + if (M[i] < 0) + continue; // ignore UNDEF indices + if ((unsigned)M[i] != 2 * i + WhichResult) + return false; + } + + return true; +} + +} // namespace llvm + #endif diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 20150d738675..bd943de06b4b 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -3932,6 +3932,16 @@ InstructionCost AArch64TTIImpl::getShuffleCost( })) return 0; + // Check for other shuffles that are not SK_ kinds but we have native + // instructions for, for example ZIP and UZP. + unsigned Unused; + if (LT.second.isFixedLengthVector() && + LT.second.getVectorNumElements() == Mask.size() && + (Kind == TTI::SK_PermuteTwoSrc || Kind == TTI::SK_PermuteSingleSrc) && + (isZIPMask(Mask, LT.second, Unused) || + isUZPMask(Mask, LT.second, Unused))) + return 1; + if (Kind == TTI::SK_Broadcast || Kind == TTI::SK_Transpose || Kind == TTI::SK_Select || Kind == TTI::SK_PermuteSingleSrc || Kind == TTI::SK_Reverse || Kind == TTI::SK_Splice) { diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll index d469ce630593..6c45ebcb69f4 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll @@ -171,28 +171,28 @@ define void @zip() { ; CHECK-LABEL: 'zip' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <2 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %zipv2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %zip1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %zip2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %zip1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %zip2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %zipv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv2i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zipv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <2 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv2i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %zipv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %zip2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %zipv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %zip1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %zip2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %zipv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zipv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zip1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %zip2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %zipv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip1v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zip2v2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <2 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %zipv2i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> @@ -276,24 +276,24 @@ define void @zip() { define void @uzp() { ; CHECK-LABEL: 'uzp' -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %uzp1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %uzp2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv4i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv8i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %uzp1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %uzp2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %uzpv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzpv16i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %uzpv4i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %uzp2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %uzpv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %uzp1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %uzp2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %uzpv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzpv8i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzp1v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzp2v16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %uzpv16i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp1v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %uzp2v4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %uzpv4i32 = shufflevector <4 x i32> undef, <4 x i32> undef, <8 x i32> @@ -360,10 +360,10 @@ define void @uzp() { define void @multipart() { ; CHECK-LABEL: 'multipart' -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %v16a = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16a = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16b = shufflevector <8 x i16> undef, <8 x i16> undef, <8 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v16c = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> -; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %v16d = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16c = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v16d = shufflevector <16 x i16> undef, <16 x i16> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v32a = shufflevector <4 x i32> undef, <4 x i32> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32a4 = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32idrev = shufflevector <16 x i32> undef, <16 x i32> undef, <16 x i32> diff --git a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll index 12de334574f5..cd434afddc9a 100644 --- a/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll +++ b/llvm/test/Analysis/CostModel/AArch64/shuffle-store.ll @@ -5,21 +5,21 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" define void @vst2(ptr %p) { ; CHECK-LABEL: 'vst2' -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i8 = shufflevector <2 x i8> undef, <2 x i8> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <4 x i8> %v4i8, ptr %p, align 4 -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i8 = shufflevector <4 x i8> undef, <4 x i8> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i8> %v8i8, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v16i8 = shufflevector <8 x i8> undef, <8 x i8> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <16 x i8> %v16i8, ptr %p, align 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v32i8 = shufflevector <16 x i8> undef, <16 x i8> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <32 x i8> %v32i8, ptr %p, align 32 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i16 = shufflevector <2 x i16> undef, <2 x i16> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i16> %v4i16, ptr %p, align 8 -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v8i16 = shufflevector <4 x i16> undef, <4 x i16> undef, <8 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <8 x i16> %v8i16, ptr %p, align 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v16i16 = shufflevector <8 x i16> undef, <8 x i16> undef, <16 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: store <16 x i16> %v16i16, ptr %p, align 32 -; CHECK-NEXT: Cost Model: Found an estimated cost of 112 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32i16 = shufflevector <16 x i16> undef, <16 x i16> undef, <32 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: store <32 x i16> %v32i16, ptr %p, align 64 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32 = shufflevector <2 x i32> undef, <2 x i32> undef, <4 x i32> ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: store <4 x i32> %v4i32, ptr %p, align 16 diff --git a/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll b/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll index c505cb7b181c..d69cb75664a8 100644 --- a/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll +++ b/llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll @@ -416,7 +416,7 @@ define i16 @reduceshuffle_twoin_notlowelt_v16i16(<16 x i16> %a, <16 x i16> %b) { define i16 @reduceshuffle_twoin_uneven_v16i16(<16 x i16> %a, <16 x i16> %b) { ; CHECK-LABEL: @reduceshuffle_twoin_uneven_v16i16( -; CHECK-NEXT: [[S:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <16 x i32> +; CHECK-NEXT: [[S:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <16 x i32> ; CHECK-NEXT: [[X:%.*]] = xor <16 x i16> [[S]], ; CHECK-NEXT: [[R:%.*]] = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> [[X]]) ; CHECK-NEXT: ret i16 [[R]] -- GitLab From 85bc6de67ef28cd203da0c5abc1485609bea989c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Wed, 10 Apr 2024 11:18:11 +0200 Subject: [PATCH 492/695] Revert "Use setup_host_tool for clang-ast-dump, fixes 76707" This reverts commit b4adb42151bbfa80be4cf6d076cbe5edf680693e. The original commit increased local rebuild times a lot. See the discussion in https://github.com/llvm/llvm-project/issues/76707 --- clang/lib/Tooling/CMakeLists.txt | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/clang/lib/Tooling/CMakeLists.txt b/clang/lib/Tooling/CMakeLists.txt index 8b4ab0e21296..91e6cbdcbc44 100644 --- a/clang/lib/Tooling/CMakeLists.txt +++ b/clang/lib/Tooling/CMakeLists.txt @@ -53,16 +53,14 @@ else() list(APPEND implicitDirs -I ${implicitDir}) endforeach() - setup_host_tool(clang-ast-dump CLANG_AST_DUMP clang_ast_dump_exe clang_ast_dump_target) - include(GetClangResourceDir) get_clang_resource_dir(resource_dir PREFIX ${LLVM_BINARY_DIR}) add_custom_command( COMMENT Generate ASTNodeAPI.json OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/ASTNodeAPI.json - DEPENDS ${clang_ast_dump_target} clang-resource-headers + DEPENDS clang-ast-dump clang-resource-headers COMMAND - ${clang_ast_dump_exe} + $ # Skip this in debug mode because parsing AST.h is too slow --skip-processing=${skip_expensive_processing} -I ${resource_dir}/include -- GitLab From d7e0ea205fa111fba46e08f3df2860f76b47acb6 Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Thu, 11 Apr 2024 03:33:04 -0400 Subject: [PATCH 493/695] [PowerPC] add testcase for a xxinsertw bug, NFC --- llvm/test/CodeGen/PowerPC/xxinsertw.ll | 36 ++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/xxinsertw.ll diff --git a/llvm/test/CodeGen/PowerPC/xxinsertw.ll b/llvm/test/CodeGen/PowerPC/xxinsertw.ll new file mode 100644 index 000000000000..b48eac06a694 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/xxinsertw.ll @@ -0,0 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-ibm-aix -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -stop-after=finalize-isel -verify-machineinstrs < %s | \ +; RUN: FileCheck %s + +define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) { + ; CHECK-LABEL: name: foo + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: liveins: $x3, $x4, $x5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY $x5 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:g8rc = COPY $x4 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:g8rc = COPY $x3 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprc = COPY [[COPY1]].sub_32 + ; CHECK-NEXT: [[MTVSRWZ:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY3]] + ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ]], %subreg.sub_64 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY2]].sub_32 + ; CHECK-NEXT: [[MTVSRWZ1:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY4]] + ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:vrrc = SUBREG_TO_REG 1, killed [[MTVSRWZ1]], %subreg.sub_64 + ; CHECK-NEXT: [[VMRGOW:%[0-9]+]]:vrrc = VMRGOW killed [[SUBREG_TO_REG1]], killed [[SUBREG_TO_REG]] + ; CHECK-NEXT: [[LDtocCPT:%[0-9]+]]:g8rc_and_g8rc_nox0 = LDtocCPT %const.0, $x2 :: (load (s64) from got) + ; CHECK-NEXT: [[LXV:%[0-9]+]]:vsrc = LXV 0, killed [[LDtocCPT]] :: (load (s128) from constant-pool) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32 + ; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]] + ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64 + ; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]] + ; CHECK-NEXT: [[DEF:%[0-9]+]]:vsrc = IMPLICIT_DEF + ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[DEF]], killed [[XXPERM]], 8 + ; CHECK-NEXT: $v2 = COPY [[XXINSERTW]] + ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2 + %1 = insertelement <4 x i1> poison, i1 %c1, i64 0 + %2 = insertelement <4 x i1> %1, i1 %c2, i64 1 + %3 = insertelement <4 x i1> %2, i1 %c3, i64 3 + %4 = shufflevector <4 x i1> %3, <4 x i1> poison, <4 x i32> + ret <4 x i1> %4 +} -- GitLab From 053750c3b42c126eb4620f62cbf4e665803b941d Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Thu, 11 Apr 2024 03:39:07 -0400 Subject: [PATCH 494/695] [PowerPC] Fix the undef register for VECINSERT If the V2 of the vector_shuffle is undef, the two vector inputs are expected to be the same when do the VECINSERT transformation. For now the first operand of VECINSERT is set to undef which is not right. This patch fixes this bug. --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 +++- llvm/test/CodeGen/PowerPC/xxinsertw.ll | 3 +-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 43e4a34a9b34..52d5b7136705 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10142,7 +10142,9 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, if (Subtarget.hasP9Vector() && PPC::isXXINSERTWMask(SVOp, ShiftElts, InsertAtByte, Swap, isLittleEndian)) { - if (Swap) + if (V2.isUndef()) + V2 = V1; + else if (Swap) std::swap(V1, V2); SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2); diff --git a/llvm/test/CodeGen/PowerPC/xxinsertw.ll b/llvm/test/CodeGen/PowerPC/xxinsertw.ll index b48eac06a694..f944b5a175be 100644 --- a/llvm/test/CodeGen/PowerPC/xxinsertw.ll +++ b/llvm/test/CodeGen/PowerPC/xxinsertw.ll @@ -24,8 +24,7 @@ define <4 x i1> @foo(i1 %c1, i1 %c2, i1 %c3) { ; CHECK-NEXT: [[MTVSRWZ2:%[0-9]+]]:vsfrc = MTVSRWZ killed [[COPY5]] ; CHECK-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:vsrc = SUBREG_TO_REG 1, killed [[MTVSRWZ2]], %subreg.sub_64 ; CHECK-NEXT: [[XXPERM:%[0-9]+]]:vsrc = XXPERM killed [[VMRGOW]], [[SUBREG_TO_REG2]], killed [[LXV]] - ; CHECK-NEXT: [[DEF:%[0-9]+]]:vsrc = IMPLICIT_DEF - ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[DEF]], killed [[XXPERM]], 8 + ; CHECK-NEXT: [[XXINSERTW:%[0-9]+]]:vsrc = XXINSERTW [[XXPERM]], [[XXPERM]], 8 ; CHECK-NEXT: $v2 = COPY [[XXINSERTW]] ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $v2 %1 = insertelement <4 x i1> poison, i1 %c1, i64 0 -- GitLab From a1cd5e69544ad3e6a865f5e0593ac26195ccb4f7 Mon Sep 17 00:00:00 2001 From: Michael Klemm Date: Thu, 11 Apr 2024 10:18:34 +0200 Subject: [PATCH 495/695] [flang] Do not create .f18.mod files for each compiled module (#85249) The default CMake scripts had a copy operation to copy a compiled `.mod` file to also be available with suffix `.f18.mod`. This seems no longer needed. Also updated ModFiles.md to point to `-module-suffix`. --------- Co-authored-by: Kiran Chandramohan --- flang/docs/ModFiles.md | 4 +++- flang/tools/f18/CMakeLists.txt | 7 ++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/flang/docs/ModFiles.md b/flang/docs/ModFiles.md index e55d72fa3a70..7463454c8563 100644 --- a/flang/docs/ModFiles.md +++ b/flang/docs/ModFiles.md @@ -27,7 +27,9 @@ often use `rm *.mod` to clean up. The disadvantage of using the same name as other compilers is that it is not clear which compiler created a `.mod` file and files from multiple compilers cannot be in the same directory. This could be solved by adding something -between the module name and extension, e.g. `-f18.mod`. +between the module name and extension, e.g. `-f18.mod`. If this +is needed, Flang's fc1 accepts the option `-module-suffix` to alter the suffix +used for the module file. ## Format diff --git a/flang/tools/f18/CMakeLists.txt b/flang/tools/f18/CMakeLists.txt index e266055a4bf0..dda3b6887be8 100644 --- a/flang/tools/f18/CMakeLists.txt +++ b/flang/tools/f18/CMakeLists.txt @@ -62,11 +62,8 @@ if (NOT CMAKE_CROSSCOMPILING) ${FLANG_SOURCE_DIR}/module/${filename}.f90 DEPENDS flang-new ${FLANG_SOURCE_DIR}/module/${filename}.f90 ${FLANG_SOURCE_DIR}/module/__fortran_builtins.f90 ${depends} ) - add_custom_command(OUTPUT ${base}.f18.mod - DEPENDS ${base}.mod - COMMAND ${CMAKE_COMMAND} -E copy ${base}.mod ${base}.f18.mod) - list(APPEND MODULE_FILES ${base}.mod ${base}.f18.mod) - install(FILES ${base}.mod ${base}.f18.mod DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}/flang") + list(APPEND MODULE_FILES ${base}.mod) + install(FILES ${base}.mod DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}/flang") endforeach() # Special case for omp_lib.mod, because its source comes from openmp/runtime/src/include. -- GitLab From 9c6e54b154cbbb7da0f45b4ae1e66bcf492151f1 Mon Sep 17 00:00:00 2001 From: Maciej Gabka Date: Thu, 11 Apr 2024 09:32:17 +0100 Subject: [PATCH 496/695] [AArch64] Fix to Neoverse V2 scheduling model (#88130) The size of ROB was incorrecty copied from the Neoverse N2, while it has actually higher value as descibed in https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/arm-neoverse-v2-platform-best-in-class-cloud-and-ai-ml-performance --- llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td index 4d7f44e7b9b9..7fed8fed9001 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td +++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td @@ -15,7 +15,7 @@ def NeoverseV2Model : SchedMachineModel { let IssueWidth = 16; // Micro-ops dispatched at a time. - let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2. + let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. let LoadLatency = 4; // Optimistic load latency. let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2. let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57. -- GitLab From cd14e7132f18dccd5fc7ed5e60258460bc1352f8 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Thu, 11 Apr 2024 09:36:56 +0100 Subject: [PATCH 497/695] lld/AArch64: handle more relocation addends (#87328) The function getImplicitAddend() is incomplete, as it is possible to cook up object files with other relocation addends. Although using llvm-mc or the clang integrated assembler does not produce such object files, a proprietary assembler known as armasm can: https://developer.arm.com/documentation/101754/0622/armasm-Legacy-Assembler-Reference armasm is in a frozen state, but it is still actively used in a lot of legacy codebases as the directives, macros and operators are very different from the clang integrated assembler. This makes porting a lot of legacy code from armasm syntax impractical for a lot of projects. Some internal testing of projects using open-source clang and lld fell over at link time when legacy armasm objects were included in the link. The goal of this patch is to enable people with legacy armasm objects to be able to use lld as the linker. Sadly armasm uses SHT_REL format relocations for AArch64 rather than SHT_RELA, which causes lld to reject the objects. As a frozen project we know the small number of relocations that the assembler officially supports and won't include (outside the equivalent of the .reloc directive which I think we can rule out of scope as that is not commonly used). The benefit to lld is that it will ease migration from a proprietary to an open-source toolchain. The drawback is the implementation of a small number of SHT_REL relocations. Although this patch doesn't aim to comprehensively cover all possible relocation addends, it does extend lld to work with the relocation addends that armasm produces, using the canonical aaelf64 document as a reference: https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst --- lld/ELF/Arch/AArch64.cpp | 42 +++++++++++++++---- .../ELF/aarch64-reloc-implicit-addend.test | 15 ++++++- 2 files changed, 48 insertions(+), 9 deletions(-) diff --git a/lld/ELF/Arch/AArch64.cpp b/lld/ELF/Arch/AArch64.cpp index 017c17c2b03d..2bf6e2c6c851 100644 --- a/lld/ELF/Arch/AArch64.cpp +++ b/lld/ELF/Arch/AArch64.cpp @@ -69,6 +69,13 @@ struct AArch64Relaxer { }; } // namespace +// Return the bits [Start, End] from Val shifted Start bits. +// For instance, getBits(0xF0, 4, 8) returns 0xF. +static uint64_t getBits(uint64_t val, int start, int end) { + uint64_t mask = ((uint64_t)1 << (end + 1 - start)) - 1; + return (val >> start) & mask; +} + AArch64::AArch64() { copyRel = R_AARCH64_COPY; relativeRel = R_AARCH64_RELATIVE; @@ -219,6 +226,10 @@ int64_t AArch64::getImplicitAddend(const uint8_t *buf, RelType type) const { case R_AARCH64_GLOB_DAT: case R_AARCH64_JUMP_SLOT: return 0; + case R_AARCH64_ABS16: + case R_AARCH64_PREL16: + return SignExtend64<16>(read16(buf)); + case R_AARCH64_ABS32: case R_AARCH64_PREL32: return SignExtend64<32>(read32(buf)); case R_AARCH64_ABS64: @@ -227,6 +238,30 @@ int64_t AArch64::getImplicitAddend(const uint8_t *buf, RelType type) const { case R_AARCH64_IRELATIVE: case R_AARCH64_TLS_TPREL64: return read64(buf); + case R_AARCH64_MOVW_UABS_G0: + case R_AARCH64_MOVW_UABS_G0_NC: + return getBits(SignExtend64<16>(read16(buf)), 0, 15); + case R_AARCH64_MOVW_UABS_G1: + case R_AARCH64_MOVW_UABS_G1_NC: + return getBits(SignExtend64<32>(read32(buf)), 16, 31); + case R_AARCH64_MOVW_UABS_G2: + case R_AARCH64_MOVW_UABS_G2_NC: + return getBits(read64(buf), 32, 47); + case R_AARCH64_MOVW_UABS_G3: + return getBits(read64(buf), 48, 63); + case R_AARCH64_TSTBR14: + return getBits(SignExtend64<32>(read32(buf)), 2, 15); + case R_AARCH64_CONDBR19: + case R_AARCH64_LD_PREL_LO19: + return getBits(SignExtend64<32>(read32(buf)), 2, 20); + case R_AARCH64_ADD_ABS_LO12_NC: + return getBits(SignExtend64<16>(read16(buf)), 0, 11); + case R_AARCH64_ADR_PREL_PG_HI21: + case R_AARCH64_ADR_PREL_PG_HI21_NC: + return getBits(SignExtend64<32>(read32(buf)), 12, 32); + case R_AARCH64_JUMP26: + case R_AARCH64_CALL26: + return getBits(SignExtend64<32>(read32(buf)), 2, 27); default: internalLinkerError(getErrorLocation(buf), "cannot read addend for relocation " + toString(type)); @@ -330,13 +365,6 @@ static void write32AArch64Addr(uint8_t *l, uint64_t imm) { write32le(l, (read32le(l) & ~mask) | immLo | immHi); } -// Return the bits [Start, End] from Val shifted Start bits. -// For instance, getBits(0xF0, 4, 8) returns 0xF. -static uint64_t getBits(uint64_t val, int start, int end) { - uint64_t mask = ((uint64_t)1 << (end + 1 - start)) - 1; - return (val >> start) & mask; -} - static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); } // Update the immediate field in a AARCH64 ldr, str, and add instruction. diff --git a/lld/test/ELF/aarch64-reloc-implicit-addend.test b/lld/test/ELF/aarch64-reloc-implicit-addend.test index 15f42c4d87b5..804ed97a2737 100644 --- a/lld/test/ELF/aarch64-reloc-implicit-addend.test +++ b/lld/test/ELF/aarch64-reloc-implicit-addend.test @@ -1,8 +1,19 @@ ## Test certain REL relocation types generated by legacy armasm. # RUN: yaml2obj %s -o %t.o -# RUN: not ld.lld %t.o -o /dev/null 2>&1 | FileCheck %s +# RUN: ld.lld %t.o -o %t +# RUN: llvm-objdump -s %t | FileCheck %s -# CHECK-COUNT-17: internal linker error: cannot read addend +# CHECK: Contents of section .abs: +# CHECK-NEXT: [[#%x,]] 29002800 00002700 00000000 0000fcff ).(...'......... +# CHECK-NEXT: [[#%x,]] ffffffff ffff ...... +# CHECK-NEXT: Contents of section .uabs: +# CHECK-NEXT: [[#%x,]] 40ffffff 40ffffff 20ffffff 20ffffff @...@... ... ... +# CHECK-NEXT: [[#%x,]] 00ffffff 00ffffff ........ +# CHECK-NEXT: Contents of section .prel: +# CHECK-NEXT: [[#%x,]] 00ffffff fcfeffff f8feffff a0ffffff ................ +# CHECK-NEXT: [[#%x,]] 0010009f 0010009f ........ +# CHECK-NEXT: Contents of section .branch: +# CHECK-NEXT: [[#%x,]] f0ffffff f0ffffff fdffffff fcffff14 ................ --- !ELF -- GitLab From def6174d2a7a5a66b3871d4ce5035a71e513e6ef Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Thu, 11 Apr 2024 10:37:57 +0200 Subject: [PATCH 498/695] [BOLT] Emit empty FDE for injected functions This fixes an issue where `PatchEntries` overwrites function body but keeps CFI untouched. Existing FDEs thus become invalid. This doesn't affect unwinding because patched functions are transparent from EH/unwinding perspective, but it breaks BOLT during disassembling those functions. Emit empty FDE for injected functions (emitted to the same address as .org functions) that take precedence over the original FDE. This adds eh_frame overhead, but restores the ability to disassemble .org functions. Note that the overhead is avoided in `-use-old-text` mode. Test Plan: updated bolt/test/X86/patch-entries.test Reviewers: rafaelauler, maksfb, dcci, ayermolo Reviewed By: maksfb, dcci Pull Request: https://github.com/llvm/llvm-project/pull/87967 --- bolt/include/bolt/Core/BinaryFunction.h | 3 ++- bolt/test/X86/patch-entries.test | 23 ++++++++++++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/bolt/include/bolt/Core/BinaryFunction.h b/bolt/include/bolt/Core/BinaryFunction.h index bc047fefa315..26d2d01f8626 100644 --- a/bolt/include/bolt/Core/BinaryFunction.h +++ b/bolt/include/bolt/Core/BinaryFunction.h @@ -1402,7 +1402,8 @@ public: /// Return true if the function has CFI instructions bool hasCFI() const { - return !FrameInstructions.empty() || !CIEFrameInstructions.empty(); + return !FrameInstructions.empty() || !CIEFrameInstructions.empty() || + IsInjected; } /// Return unique number associated with the function. diff --git a/bolt/test/X86/patch-entries.test b/bolt/test/X86/patch-entries.test index 54f358f273e7..4a725412dd61 100644 --- a/bolt/test/X86/patch-entries.test +++ b/bolt/test/X86/patch-entries.test @@ -7,4 +7,25 @@ REQUIRES: system-linux RUN: %clang %cflags -no-pie -g %p/Inputs/patch-entries.c -fuse-ld=lld -o %t.exe \ RUN: -Wl,-q -I%p/../Inputs -RUN: llvm-bolt -relocs %t.exe -o %t.out --update-debug-sections --force-patch +RUN: llvm-bolt -relocs %t.exe -o %t.out --update-debug-sections --force-patch \ +RUN: --enable-bat + +# Check that patched functions can be disassembled (override FDE from the +# original function) +# PREAGG: B X:0 #foo.org.0# 1 0 +RUN: link_fdata %s %t.out %t.preagg PREAGG +RUN: perf2bolt %t.out -p %t.preagg --pa -o %t.yaml --profile-format=yaml \ +RUN: -print-disasm -print-only=foo.org.0/1 2>&1 | FileCheck %s +CHECK-NOT: BOLT-WARNING: sizes differ for function foo.org.0/1 +CHECK: Binary Function "foo.org.0/1(*2)" after disassembly { + +# Check the expected eh_frame contents +RUN: llvm-nm --print-size %t.out > %t.foo +RUN: llvm-objdump %t.out --dwarf=frames >> %t.foo +RUN: FileCheck %s --input-file %t.foo --check-prefix=CHECK-FOO +CHECK-FOO: 0000000000[[#%x,FOO:]] [[#%x,OPTSIZE:]] t foo +CHECK-FOO: 0000000000[[#%x,ORG:]] [[#%x,ORGSIZE:]] t foo.org.0 +# patched FDE comes first +CHECK-FOO: FDE {{.*}} pc=00[[#%x,ORG]]...00[[#%x,ORG+ORGSIZE]] +# original FDE comes second +CHECK-FOO: FDE {{.*}} pc=00[[#%x,ORG]]...00[[#%x,ORG+OPTSIZE]] -- GitLab From fe3b20d5ab4b47823fb48ad7cfbc47b8224ce826 Mon Sep 17 00:00:00 2001 From: NagyDonat Date: Thu, 11 Apr 2024 10:44:35 +0200 Subject: [PATCH 499/695] [analyzer] Use CDM::CLibrary instead of isGlobalCFunction() (#88267) This commit updates several checkers to use call descriptions with the matching mode `CDM::CLibrary` instead of checking `Call.isGlobalCFunction()` after performing the match. This resolves several TODOs in various checkers. Note that both matching with `CDM::CLibrary` and calling `isGlobalCFunction` leads to `CheckerContext::isCLibraryFunction()` checks (so this change is close to being NFC), but if it is used via the matching mode then the checker can automatically recognize the builtin variants of the matched functions. I'll also make similar changes in GenericTaintChecker, but that checker has separate and inconsistent rules for handling the normal and the builtin variant of several functions (e.g. `memcpy` and `__builtin_memcpy`), so I'll put those changes into a separate commit. --- .../Checkers/BasicObjCFoundationChecks.cpp | 12 +- .../Checkers/PthreadLockChecker.cpp | 115 +++++++++++------- .../Checkers/SimpleStreamChecker.cpp | 10 +- .../StaticAnalyzer/Checkers/StreamChecker.cpp | 69 +++++------ .../StaticAnalyzer/Checkers/ValistChecker.cpp | 35 +++--- 5 files changed, 130 insertions(+), 111 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp b/clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp index c72a97cc01e9..80f128b917b2 100644 --- a/clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/BasicObjCFoundationChecks.cpp @@ -542,10 +542,10 @@ namespace { class CFRetainReleaseChecker : public Checker { mutable APIMisuse BT{this, "null passed to CF memory management function"}; const CallDescriptionSet ModelledCalls = { - {{"CFRetain"}, 1}, - {{"CFRelease"}, 1}, - {{"CFMakeCollectable"}, 1}, - {{"CFAutorelease"}, 1}, + {CDM::CLibrary, {"CFRetain"}, 1}, + {CDM::CLibrary, {"CFRelease"}, 1}, + {CDM::CLibrary, {"CFMakeCollectable"}, 1}, + {CDM::CLibrary, {"CFAutorelease"}, 1}, }; public: @@ -555,10 +555,6 @@ public: void CFRetainReleaseChecker::checkPreCall(const CallEvent &Call, CheckerContext &C) const { - // TODO: Make this check part of CallDescription. - if (!Call.isGlobalCFunction()) - return; - // Check if we called CFRetain/CFRelease/CFMakeCollectable/CFAutorelease. if (!ModelledCalls.contains(Call)) return; diff --git a/clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp index fa8572cf85ed..86530086ff1b 100644 --- a/clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/PthreadLockChecker.cpp @@ -87,7 +87,8 @@ private: CheckerKind CheckKind) const; CallDescriptionMap PThreadCallbacks = { // Init. - {{{"pthread_mutex_init"}, 2}, &PthreadLockChecker::InitAnyLock}, + {{CDM::CLibrary, {"pthread_mutex_init"}, 2}, + &PthreadLockChecker::InitAnyLock}, // TODO: pthread_rwlock_init(2 arguments). // TODO: lck_mtx_init(3 arguments). // TODO: lck_mtx_alloc_init(2 arguments) => returns the mutex. @@ -95,74 +96,106 @@ private: // TODO: lck_rw_alloc_init(2 arguments) => returns the mutex. // Acquire. - {{{"pthread_mutex_lock"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, - {{{"pthread_rwlock_rdlock"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, - {{{"pthread_rwlock_wrlock"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, - {{{"lck_mtx_lock"}, 1}, &PthreadLockChecker::AcquireXNULock}, - {{{"lck_rw_lock_exclusive"}, 1}, &PthreadLockChecker::AcquireXNULock}, - {{{"lck_rw_lock_shared"}, 1}, &PthreadLockChecker::AcquireXNULock}, + {{CDM::CLibrary, {"pthread_mutex_lock"}, 1}, + &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"pthread_rwlock_rdlock"}, 1}, + &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"pthread_rwlock_wrlock"}, 1}, + &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"lck_mtx_lock"}, 1}, + &PthreadLockChecker::AcquireXNULock}, + {{CDM::CLibrary, {"lck_rw_lock_exclusive"}, 1}, + &PthreadLockChecker::AcquireXNULock}, + {{CDM::CLibrary, {"lck_rw_lock_shared"}, 1}, + &PthreadLockChecker::AcquireXNULock}, // Try. - {{{"pthread_mutex_trylock"}, 1}, &PthreadLockChecker::TryPthreadLock}, - {{{"pthread_rwlock_tryrdlock"}, 1}, &PthreadLockChecker::TryPthreadLock}, - {{{"pthread_rwlock_trywrlock"}, 1}, &PthreadLockChecker::TryPthreadLock}, - {{{"lck_mtx_try_lock"}, 1}, &PthreadLockChecker::TryXNULock}, - {{{"lck_rw_try_lock_exclusive"}, 1}, &PthreadLockChecker::TryXNULock}, - {{{"lck_rw_try_lock_shared"}, 1}, &PthreadLockChecker::TryXNULock}, + {{CDM::CLibrary, {"pthread_mutex_trylock"}, 1}, + &PthreadLockChecker::TryPthreadLock}, + {{CDM::CLibrary, {"pthread_rwlock_tryrdlock"}, 1}, + &PthreadLockChecker::TryPthreadLock}, + {{CDM::CLibrary, {"pthread_rwlock_trywrlock"}, 1}, + &PthreadLockChecker::TryPthreadLock}, + {{CDM::CLibrary, {"lck_mtx_try_lock"}, 1}, + &PthreadLockChecker::TryXNULock}, + {{CDM::CLibrary, {"lck_rw_try_lock_exclusive"}, 1}, + &PthreadLockChecker::TryXNULock}, + {{CDM::CLibrary, {"lck_rw_try_lock_shared"}, 1}, + &PthreadLockChecker::TryXNULock}, // Release. - {{{"pthread_mutex_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"pthread_rwlock_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"lck_mtx_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"lck_rw_unlock_exclusive"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"lck_rw_unlock_shared"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"lck_rw_done"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"pthread_mutex_unlock"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"pthread_rwlock_unlock"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"lck_mtx_unlock"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"lck_rw_unlock_exclusive"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"lck_rw_unlock_shared"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"lck_rw_done"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, // Destroy. - {{{"pthread_mutex_destroy"}, 1}, &PthreadLockChecker::DestroyPthreadLock}, - {{{"lck_mtx_destroy"}, 2}, &PthreadLockChecker::DestroyXNULock}, + {{CDM::CLibrary, {"pthread_mutex_destroy"}, 1}, + &PthreadLockChecker::DestroyPthreadLock}, + {{CDM::CLibrary, {"lck_mtx_destroy"}, 2}, + &PthreadLockChecker::DestroyXNULock}, // TODO: pthread_rwlock_destroy(1 argument). // TODO: lck_rw_destroy(2 arguments). }; CallDescriptionMap FuchsiaCallbacks = { // Init. - {{{"spin_lock_init"}, 1}, &PthreadLockChecker::InitAnyLock}, + {{CDM::CLibrary, {"spin_lock_init"}, 1}, + &PthreadLockChecker::InitAnyLock}, // Acquire. - {{{"spin_lock"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, - {{{"spin_lock_save"}, 3}, &PthreadLockChecker::AcquirePthreadLock}, - {{{"sync_mutex_lock"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, - {{{"sync_mutex_lock_with_waiter"}, 1}, + {{CDM::CLibrary, {"spin_lock"}, 1}, + &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"spin_lock_save"}, 3}, + &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"sync_mutex_lock"}, 1}, + &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"sync_mutex_lock_with_waiter"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, // Try. - {{{"spin_trylock"}, 1}, &PthreadLockChecker::TryFuchsiaLock}, - {{{"sync_mutex_trylock"}, 1}, &PthreadLockChecker::TryFuchsiaLock}, - {{{"sync_mutex_timedlock"}, 2}, &PthreadLockChecker::TryFuchsiaLock}, + {{CDM::CLibrary, {"spin_trylock"}, 1}, + &PthreadLockChecker::TryFuchsiaLock}, + {{CDM::CLibrary, {"sync_mutex_trylock"}, 1}, + &PthreadLockChecker::TryFuchsiaLock}, + {{CDM::CLibrary, {"sync_mutex_timedlock"}, 2}, + &PthreadLockChecker::TryFuchsiaLock}, // Release. - {{{"spin_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"spin_unlock_restore"}, 3}, &PthreadLockChecker::ReleaseAnyLock}, - {{{"sync_mutex_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"spin_unlock"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"spin_unlock_restore"}, 3}, + &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"sync_mutex_unlock"}, 1}, + &PthreadLockChecker::ReleaseAnyLock}, }; CallDescriptionMap C11Callbacks = { // Init. - {{{"mtx_init"}, 2}, &PthreadLockChecker::InitAnyLock}, + {{CDM::CLibrary, {"mtx_init"}, 2}, &PthreadLockChecker::InitAnyLock}, // Acquire. - {{{"mtx_lock"}, 1}, &PthreadLockChecker::AcquirePthreadLock}, + {{CDM::CLibrary, {"mtx_lock"}, 1}, + &PthreadLockChecker::AcquirePthreadLock}, // Try. - {{{"mtx_trylock"}, 1}, &PthreadLockChecker::TryC11Lock}, - {{{"mtx_timedlock"}, 2}, &PthreadLockChecker::TryC11Lock}, + {{CDM::CLibrary, {"mtx_trylock"}, 1}, &PthreadLockChecker::TryC11Lock}, + {{CDM::CLibrary, {"mtx_timedlock"}, 2}, &PthreadLockChecker::TryC11Lock}, // Release. - {{{"mtx_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, + {{CDM::CLibrary, {"mtx_unlock"}, 1}, &PthreadLockChecker::ReleaseAnyLock}, // Destroy - {{{"mtx_destroy"}, 1}, &PthreadLockChecker::DestroyPthreadLock}, + {{CDM::CLibrary, {"mtx_destroy"}, 1}, + &PthreadLockChecker::DestroyPthreadLock}, }; ProgramStateRef resolvePossiblyDestroyedMutex(ProgramStateRef state, @@ -258,13 +291,9 @@ REGISTER_MAP_WITH_PROGRAMSTATE(DestroyRetVal, const MemRegion *, SymbolRef) void PthreadLockChecker::checkPostCall(const CallEvent &Call, CheckerContext &C) const { - // An additional umbrella check that all functions modeled by this checker - // are global C functions. - // TODO: Maybe make this the default behavior of CallDescription - // with exactly one identifier? // FIXME: Try to handle cases when the implementation was inlined rather // than just giving up. - if (!Call.isGlobalCFunction() || C.wasInlined) + if (C.wasInlined) return; if (const FnCheck *Callback = PThreadCallbacks.lookup(Call)) diff --git a/clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp index 50d50562d3e7..5152624d00f4 100644 --- a/clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/SimpleStreamChecker.cpp @@ -52,8 +52,8 @@ class SimpleStreamChecker : public Checker { - const CallDescription OpenFn{{"fopen"}, 2}; - const CallDescription CloseFn{{"fclose"}, 1}; + const CallDescription OpenFn{CDM::CLibrary, {"fopen"}, 2}; + const CallDescription CloseFn{CDM::CLibrary, {"fclose"}, 1}; const BugType DoubleCloseBugType{this, "Double fclose", "Unix Stream API Error"}; @@ -92,9 +92,6 @@ REGISTER_MAP_WITH_PROGRAMSTATE(StreamMap, SymbolRef, StreamState) void SimpleStreamChecker::checkPostCall(const CallEvent &Call, CheckerContext &C) const { - if (!Call.isGlobalCFunction()) - return; - if (!OpenFn.matches(Call)) return; @@ -111,9 +108,6 @@ void SimpleStreamChecker::checkPostCall(const CallEvent &Call, void SimpleStreamChecker::checkPreCall(const CallEvent &Call, CheckerContext &C) const { - if (!Call.isGlobalCFunction()) - return; - if (!CloseFn.matches(Call)) return; diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index 31c756ab0c58..bd495cd0f971 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -302,85 +302,88 @@ public: private: CallDescriptionMap FnDescriptions = { - {{{"fopen"}, 2}, {nullptr, &StreamChecker::evalFopen, ArgNone}}, - {{{"fdopen"}, 2}, {nullptr, &StreamChecker::evalFopen, ArgNone}}, - {{{"freopen"}, 3}, + {{CDM::CLibrary, {"fopen"}, 2}, + {nullptr, &StreamChecker::evalFopen, ArgNone}}, + {{CDM::CLibrary, {"fdopen"}, 2}, + {nullptr, &StreamChecker::evalFopen, ArgNone}}, + {{CDM::CLibrary, {"freopen"}, 3}, {&StreamChecker::preFreopen, &StreamChecker::evalFreopen, 2}}, - {{{"tmpfile"}, 0}, {nullptr, &StreamChecker::evalFopen, ArgNone}}, - {{{"fclose"}, 1}, + {{CDM::CLibrary, {"tmpfile"}, 0}, + {nullptr, &StreamChecker::evalFopen, ArgNone}}, + {{CDM::CLibrary, {"fclose"}, 1}, {&StreamChecker::preDefault, &StreamChecker::evalFclose, 0}}, - {{{"fread"}, 4}, + {{CDM::CLibrary, {"fread"}, 4}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalFreadFwrite, _1, _2, _3, _4, true), 3}}, - {{{"fwrite"}, 4}, + {{CDM::CLibrary, {"fwrite"}, 4}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalFreadFwrite, _1, _2, _3, _4, false), 3}}, - {{{"fgetc"}, 1}, + {{CDM::CLibrary, {"fgetc"}, 1}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalFgetx, _1, _2, _3, _4, true), 0}}, - {{{"fgets"}, 3}, + {{CDM::CLibrary, {"fgets"}, 3}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalFgetx, _1, _2, _3, _4, false), 2}}, - {{{"getc"}, 1}, + {{CDM::CLibrary, {"getc"}, 1}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalFgetx, _1, _2, _3, _4, true), 0}}, - {{{"fputc"}, 2}, + {{CDM::CLibrary, {"fputc"}, 2}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalFputx, _1, _2, _3, _4, true), 1}}, - {{{"fputs"}, 2}, + {{CDM::CLibrary, {"fputs"}, 2}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalFputx, _1, _2, _3, _4, false), 1}}, - {{{"putc"}, 2}, + {{CDM::CLibrary, {"putc"}, 2}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalFputx, _1, _2, _3, _4, true), 1}}, - {{{"fprintf"}}, + {{CDM::CLibrary, {"fprintf"}}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalFprintf, _1, _2, _3, _4), 0}}, - {{{"vfprintf"}, 3}, + {{CDM::CLibrary, {"vfprintf"}, 3}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalFprintf, _1, _2, _3, _4), 0}}, - {{{"fscanf"}}, + {{CDM::CLibrary, {"fscanf"}}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalFscanf, _1, _2, _3, _4), 0}}, - {{{"vfscanf"}, 3}, + {{CDM::CLibrary, {"vfscanf"}, 3}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalFscanf, _1, _2, _3, _4), 0}}, - {{{"ungetc"}, 2}, + {{CDM::CLibrary, {"ungetc"}, 2}, {&StreamChecker::preWrite, std::bind(&StreamChecker::evalUngetc, _1, _2, _3, _4), 1}}, - {{{"getdelim"}, 4}, + {{CDM::CLibrary, {"getdelim"}, 4}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalGetdelim, _1, _2, _3, _4), 3}}, - {{{"getline"}, 3}, + {{CDM::CLibrary, {"getline"}, 3}, {&StreamChecker::preRead, std::bind(&StreamChecker::evalGetdelim, _1, _2, _3, _4), 2}}, - {{{"fseek"}, 3}, + {{CDM::CLibrary, {"fseek"}, 3}, {&StreamChecker::preFseek, &StreamChecker::evalFseek, 0}}, - {{{"fseeko"}, 3}, + {{CDM::CLibrary, {"fseeko"}, 3}, {&StreamChecker::preFseek, &StreamChecker::evalFseek, 0}}, - {{{"ftell"}, 1}, + {{CDM::CLibrary, {"ftell"}, 1}, {&StreamChecker::preWrite, &StreamChecker::evalFtell, 0}}, - {{{"ftello"}, 1}, + {{CDM::CLibrary, {"ftello"}, 1}, {&StreamChecker::preWrite, &StreamChecker::evalFtell, 0}}, - {{{"fflush"}, 1}, + {{CDM::CLibrary, {"fflush"}, 1}, {&StreamChecker::preFflush, &StreamChecker::evalFflush, 0}}, - {{{"rewind"}, 1}, + {{CDM::CLibrary, {"rewind"}, 1}, {&StreamChecker::preDefault, &StreamChecker::evalRewind, 0}}, - {{{"fgetpos"}, 2}, + {{CDM::CLibrary, {"fgetpos"}, 2}, {&StreamChecker::preWrite, &StreamChecker::evalFgetpos, 0}}, - {{{"fsetpos"}, 2}, + {{CDM::CLibrary, {"fsetpos"}, 2}, {&StreamChecker::preDefault, &StreamChecker::evalFsetpos, 0}}, - {{{"clearerr"}, 1}, + {{CDM::CLibrary, {"clearerr"}, 1}, {&StreamChecker::preDefault, &StreamChecker::evalClearerr, 0}}, - {{{"feof"}, 1}, + {{CDM::CLibrary, {"feof"}, 1}, {&StreamChecker::preDefault, std::bind(&StreamChecker::evalFeofFerror, _1, _2, _3, _4, ErrorFEof), 0}}, - {{{"ferror"}, 1}, + {{CDM::CLibrary, {"ferror"}, 1}, {&StreamChecker::preDefault, std::bind(&StreamChecker::evalFeofFerror, _1, _2, _3, _4, ErrorFError), 0}}, - {{{"fileno"}, 1}, + {{CDM::CLibrary, {"fileno"}, 1}, {&StreamChecker::preDefault, &StreamChecker::evalFileno, 0}}, }; @@ -540,8 +543,6 @@ private: const FnDescription *lookupFn(const CallEvent &Call) const { // Recognize "global C functions" with only integral or pointer arguments // (and matching name) as stream functions. - if (!Call.isGlobalCFunction()) - return nullptr; for (auto *P : Call.parameters()) { QualType T = P->getType(); if (!T->isIntegralOrEnumerationType() && !T->isPointerType() && diff --git a/clang/lib/StaticAnalyzer/Checkers/ValistChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/ValistChecker.cpp index 2d1b873abf73..28320f46f237 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ValistChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ValistChecker.cpp @@ -100,32 +100,31 @@ private: }; const SmallVector - ValistChecker::VAListAccepters = {{{{"vfprintf"}, 3}, 2}, - {{{"vfscanf"}, 3}, 2}, - {{{"vprintf"}, 2}, 1}, - {{{"vscanf"}, 2}, 1}, - {{{"vsnprintf"}, 4}, 3}, - {{{"vsprintf"}, 3}, 2}, - {{{"vsscanf"}, 3}, 2}, - {{{"vfwprintf"}, 3}, 2}, - {{{"vfwscanf"}, 3}, 2}, - {{{"vwprintf"}, 2}, 1}, - {{{"vwscanf"}, 2}, 1}, - {{{"vswprintf"}, 4}, 3}, + ValistChecker::VAListAccepters = {{{CDM::CLibrary, {"vfprintf"}, 3}, 2}, + {{CDM::CLibrary, {"vfscanf"}, 3}, 2}, + {{CDM::CLibrary, {"vprintf"}, 2}, 1}, + {{CDM::CLibrary, {"vscanf"}, 2}, 1}, + {{CDM::CLibrary, {"vsnprintf"}, 4}, 3}, + {{CDM::CLibrary, {"vsprintf"}, 3}, 2}, + {{CDM::CLibrary, {"vsscanf"}, 3}, 2}, + {{CDM::CLibrary, {"vfwprintf"}, 3}, 2}, + {{CDM::CLibrary, {"vfwscanf"}, 3}, 2}, + {{CDM::CLibrary, {"vwprintf"}, 2}, 1}, + {{CDM::CLibrary, {"vwscanf"}, 2}, 1}, + {{CDM::CLibrary, {"vswprintf"}, 4}, 3}, // vswprintf is the wide version of // vsnprintf, vsprintf has no wide version - {{{"vswscanf"}, 3}, 2}}; + {{CDM::CLibrary, {"vswscanf"}, 3}, 2}}; -const CallDescription ValistChecker::VaStart({"__builtin_va_start"}, /*Args=*/2, +const CallDescription ValistChecker::VaStart(CDM::CLibrary, + {"__builtin_va_start"}, /*Args=*/2, /*Params=*/1), - ValistChecker::VaCopy({"__builtin_va_copy"}, 2), - ValistChecker::VaEnd({"__builtin_va_end"}, 1); + ValistChecker::VaCopy(CDM::CLibrary, {"__builtin_va_copy"}, 2), + ValistChecker::VaEnd(CDM::CLibrary, {"__builtin_va_end"}, 1); } // end anonymous namespace void ValistChecker::checkPreCall(const CallEvent &Call, CheckerContext &C) const { - if (!Call.isGlobalCFunction()) - return; if (VaStart.matches(Call)) checkVAListStartCall(Call, C, false); else if (VaCopy.matches(Call)) -- GitLab From 5c9315f575370393ccc89ef0229743c05f6fe703 Mon Sep 17 00:00:00 2001 From: Johannes Reifferscheid Date: Thu, 11 Apr 2024 10:54:50 +0200 Subject: [PATCH 500/695] Fix complex log1p accuracy with large abs values. (#88364) This ports openxla/xla#10503 by @pearu. In addition to the filecheck test here, the accuracy was tested with XLA's complex_unary_op_test and its MLIR emitters. This is a fixed version of https://github.com/llvm/llvm-project/pull/88260. The previous version relied on implementation-specific behavior in the order of evaluation of maxAbsOfRealPlusOneAndImagMinusOne's operands. --- .../ComplexToStandard/ComplexToStandard.cpp | 51 ++++++++++--------- .../convert-to-standard.mlir | 48 ++++++++++------- 2 files changed, 58 insertions(+), 41 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 9c3c4d96a301..a6fcf6a758c0 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -570,37 +570,40 @@ struct Log1pOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { auto type = cast(adaptor.getComplex().getType()); auto elementType = cast(type.getElementType()); - arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); + arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); mlir::ImplicitLocOpBuilder b(op.getLoc(), rewriter); - Value real = b.create(elementType, adaptor.getComplex()); - Value imag = b.create(elementType, adaptor.getComplex()); + Value real = b.create(adaptor.getComplex()); + Value imag = b.create(adaptor.getComplex()); Value half = b.create(elementType, b.getFloatAttr(elementType, 0.5)); Value one = b.create(elementType, b.getFloatAttr(elementType, 1)); - Value two = b.create(elementType, - b.getFloatAttr(elementType, 2)); - - // log1p(a+bi) = .5*log((a+1)^2+b^2) + i*atan2(b, a + 1) - // log((a+1)+bi) = .5*log(a*a + 2*a + 1 + b*b) + i*atan2(b, a+1) - // log((a+1)+bi) = .5*log1p(a*a + 2*a + b*b) + i*atan2(b, a+1) - Value sumSq = b.create(real, real, fmf.getValue()); - sumSq = b.create( - sumSq, b.create(real, two, fmf.getValue()), - fmf.getValue()); - sumSq = b.create( - sumSq, b.create(imag, imag, fmf.getValue()), - fmf.getValue()); - Value logSumSq = - b.create(elementType, sumSq, fmf.getValue()); - Value resultReal = b.create(logSumSq, half, fmf.getValue()); - - Value realPlusOne = b.create(real, one, fmf.getValue()); - - Value resultImag = - b.create(elementType, imag, realPlusOne, fmf.getValue()); + Value realPlusOne = b.create(real, one, fmf); + Value absRealPlusOne = b.create(realPlusOne, fmf); + Value absImag = b.create(imag, fmf); + + Value maxAbs = b.create(absRealPlusOne, absImag, fmf); + Value minAbs = b.create(absRealPlusOne, absImag, fmf); + + Value useReal = b.create(arith::CmpFPredicate::OGT, + realPlusOne, absImag, fmf); + Value maxMinusOne = b.create(maxAbs, one, fmf); + Value maxAbsOfRealPlusOneAndImagMinusOne = + b.create(useReal, real, maxMinusOne); + Value minMaxRatio = b.create(minAbs, maxAbs, fmf); + Value logOfMaxAbsOfRealPlusOneAndImag = + b.create(maxAbsOfRealPlusOneAndImagMinusOne, fmf); + Value logOfSqrtPart = b.create( + b.create(minMaxRatio, minMaxRatio, fmf), fmf); + Value r = b.create( + b.create(half, logOfSqrtPart, fmf), + logOfMaxAbsOfRealPlusOneAndImag, fmf); + Value resultReal = b.create( + b.create(arith::CmpFPredicate::UNO, r, r, fmf), minAbs, + r); + Value resultImag = b.create(imag, realPlusOne, fmf); rewriter.replaceOpWithNewOp(op, type, resultReal, resultImag); return success(); diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index f5d9499eadda..46dba04a88aa 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -300,15 +300,22 @@ func.func @complex_log1p(%arg: complex) -> complex { // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32 -// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] : f32 -// CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] : f32 -// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] : f32 -// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] : f32 -// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] : f32 -// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] : f32 -// CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] : f32 // CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] : f32 +// CHECK: %[[ABS_REAL_PLUS_ONE:.*]] = math.absf %[[REAL_PLUS_ONE]] : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 +// CHECK: %[[CMPF:.*]] = arith.cmpf ogt, %[[REAL_PLUS_ONE]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MAX_MINUS_ONE:.*]] = arith.subf %[[MAX]], %[[ONE]] : f32 +// CHECK: %[[SELECT:.*]] = arith.select %[[CMPF]], %0, %[[MAX_MINUS_ONE]] : f32 +// CHECK: %[[MIN_MAX_RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[LOG_1:.*]] = math.log1p %[[SELECT]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[MIN_MAX_RATIO]], %[[MIN_MAX_RATIO]] : f32 +// CHECK: %[[LOG_SQ:.*]] = math.log1p %[[RATIO_SQ]] : f32 +// CHECK: %[[HALF_LOG_SQ:.*]] = arith.mulf %cst, %[[LOG_SQ]] : f32 +// CHECK: %[[R:.*]] = arith.addf %[[HALF_LOG_SQ]], %[[LOG_1]] : f32 +// CHECK: %[[ISNAN:.*]] = arith.cmpf uno, %[[R]], %[[R]] : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[ISNAN]], %[[MIN]], %[[R]] : f32 // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex @@ -963,15 +970,22 @@ func.func @complex_log1p_with_fmf(%arg: complex) -> complex { // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[ONE_HALF:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[TWO:.*]] = arith.constant 2.000000e+00 : f32 -// CHECK: %[[SQ_SUM_0:.*]] = arith.mulf %[[REAL]], %[[REAL]] fastmath : f32 -// CHECK: %[[TWO_REAL:.*]] = arith.mulf %[[REAL]], %[[TWO]] fastmath : f32 -// CHECK: %[[SQ_SUM_1:.*]] = arith.addf %[[SQ_SUM_0]], %[[TWO_REAL]] fastmath : f32 -// CHECK: %[[SQ_IMAG:.*]] = arith.mulf %[[IMAG]], %[[IMAG]] fastmath : f32 -// CHECK: %[[SQ_SUM_2:.*]] = arith.addf %[[SQ_SUM_1]], %[[SQ_IMAG]] fastmath : f32 -// CHECK: %[[LOG_SQ_SUM:.*]] = math.log1p %[[SQ_SUM_2]] fastmath : f32 -// CHECK: %[[RESULT_REAL:.*]] = arith.mulf %[[LOG_SQ_SUM]], %[[ONE_HALF]] fastmath : f32 -// CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] fastmath : f32 +// CHECK: %[[REAL_PLUS_ONE:.*]] = arith.addf %[[REAL]], %[[ONE]] fastmath : f32 +// CHECK: %[[ABS_REAL_PLUS_ONE:.*]] = math.absf %[[REAL_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[CMPF:.*]] = arith.cmpf ogt, %[[REAL_PLUS_ONE]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MAX_MINUS_ONE:.*]] = arith.subf %[[MAX]], %[[ONE]] fastmath : f32 +// CHECK: %[[SELECT:.*]] = arith.select %[[CMPF]], %0, %[[MAX_MINUS_ONE]] : f32 +// CHECK: %[[MIN_MAX_RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[LOG_1:.*]] = math.log1p %[[SELECT]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[MIN_MAX_RATIO]], %[[MIN_MAX_RATIO]] fastmath : f32 +// CHECK: %[[LOG_SQ:.*]] = math.log1p %[[RATIO_SQ]] fastmath : f32 +// CHECK: %[[HALF_LOG_SQ:.*]] = arith.mulf %cst, %[[LOG_SQ]] fastmath : f32 +// CHECK: %[[R:.*]] = arith.addf %[[HALF_LOG_SQ]], %[[LOG_1]] fastmath : f32 +// CHECK: %[[ISNAN:.*]] = arith.cmpf uno, %[[R]], %[[R]] fastmath : f32 +// CHECK: %[[RESULT_REAL:.*]] = arith.select %[[ISNAN]], %[[MIN]], %[[R]] : f32 // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG]], %[[REAL_PLUS_ONE]] fastmath : f32 // CHECK: %[[RESULT:.*]] = complex.create %[[RESULT_REAL]], %[[RESULT_IMAG]] : complex // CHECK: return %[[RESULT]] : complex -- GitLab From db2fb3d96b217f0d2e139e7816c98d9f95974f25 Mon Sep 17 00:00:00 2001 From: Freddy Ye Date: Thu, 11 Apr 2024 16:57:32 +0800 Subject: [PATCH 501/695] [X86] Define __APX_F__ when APX is enabled. (#88343) Relate gcc patch: https://gcc.gnu.org/pipermail/gcc-patches/2024-April/648789.html --- clang/lib/Basic/Targets/X86.cpp | 3 +++ clang/test/Preprocessor/x86_target_features.c | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 1966af17904d..bf1767c87fe1 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -954,6 +954,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__CCMP__"); if (HasCF) Builder.defineMacro("__CF__"); + // Condition here is aligned with the feature set of mapxf in Options.td + if (HasEGPR && HasPush2Pop2 && HasPPX && HasNDD) + Builder.defineMacro("__APX_F__"); // Each case falls through to the previous one here. switch (SSELevel) { diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c index a1882043910f..5602c59158fe 100644 --- a/clang/test/Preprocessor/x86_target_features.c +++ b/clang/test/Preprocessor/x86_target_features.c @@ -803,7 +803,8 @@ // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd -x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-prefix=CCMP %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=cf -x c -E -dM -o - %s | FileCheck --check-prefix=CF %s -// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX,NDD %s +// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX,NDD,APXF %s +// APXF: #define __APX_F__ 1 // CCMP: #define __CCMP__ 1 // CF: #define __CF__ 1 // EGPR: #define __EGPR__ 1 -- GitLab From 32b95a37083d1fee1a638e292be0aac9a98792fd Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 10:05:53 +0100 Subject: [PATCH 502/695] [VectorCombine][X86] Extend shuffle(bitcast(x),bitcast(y)) test coverage As discussed on #87510 the intention is to fold shuffle(bitcast(x),bitcast(y)) -> bitcast(shuffle(x,y)), but it must not interfere with existing bitcast(shuffle(bitcast(x),bitcast(y))) folds. --- .../VectorCombine/X86/shuffle-of-casts.ll | 67 ++++++++++++++++--- 1 file changed, 56 insertions(+), 11 deletions(-) diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll index 2031c2d04c60..60c6ff97c58b 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll @@ -165,6 +165,51 @@ define <8 x double> @interleave_fpext_v4f32_v8f64(<4 x float> %a0, <4 x float> % ret <8 x double> %r } +; TODO - bitcasts (same element count) + +define <8 x float> @concat_bitcast_v4i32_v8f32(<4 x i32> %a0, <4 x i32> %a1) { +; CHECK-LABEL: @concat_bitcast_v4i32_v8f32( +; CHECK-NEXT: [[X0:%.*]] = bitcast <4 x i32> [[A0:%.*]] to <4 x float> +; CHECK-NEXT: [[X1:%.*]] = bitcast <4 x i32> [[A1:%.*]] to <4 x float> +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X0]], <4 x float> [[X1]], <8 x i32> +; CHECK-NEXT: ret <8 x float> [[R]] +; + %x0 = bitcast <4 x i32> %a0 to <4 x float> + %x1 = bitcast <4 x i32> %a1 to <4 x float> + %r = shufflevector <4 x float> %x0, <4 x float> %x1, <8 x i32> + ret <8 x float> %r +} + +; TODO - bitcasts (lower element count) + +define <4 x double> @concat_bitcast_v8i16_v4f64(<8 x i16> %a0, <8 x i16> %a1) { +; CHECK-LABEL: @concat_bitcast_v8i16_v4f64( +; CHECK-NEXT: [[X0:%.*]] = bitcast <8 x i16> [[A0:%.*]] to <2 x double> +; CHECK-NEXT: [[X1:%.*]] = bitcast <8 x i16> [[A1:%.*]] to <2 x double> +; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x double> [[X0]], <2 x double> [[X1]], <4 x i32> +; CHECK-NEXT: ret <4 x double> [[R]] +; + %x0 = bitcast <8 x i16> %a0 to <2 x double> + %x1 = bitcast <8 x i16> %a1 to <2 x double> + %r = shufflevector <2 x double> %x0, <2 x double> %x1, <4 x i32> + ret <4 x double> %r +} + +; TODO - bitcasts (higher element count) + +define <16 x i16> @concat_bitcast_v4i32_v16i16(<4 x i32> %a0, <4 x i32> %a1) { +; CHECK-LABEL: @concat_bitcast_v4i32_v16i16( +; CHECK-NEXT: [[X0:%.*]] = bitcast <4 x i32> [[A0:%.*]] to <8 x i16> +; CHECK-NEXT: [[X1:%.*]] = bitcast <4 x i32> [[A1:%.*]] to <8 x i16> +; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[X0]], <8 x i16> [[X1]], <16 x i32> +; CHECK-NEXT: ret <16 x i16> [[R]] +; + %x0 = bitcast <4 x i32> %a0 to <8 x i16> + %x1 = bitcast <4 x i32> %a1 to <8 x i16> + %r = shufflevector <8 x i16> %x0, <8 x i16> %x1, <16 x i32> + ret <16 x i16> %r +} + ; negative - multiuse define <8 x i16> @concat_trunc_v4i32_v8i16_multiuse(<4 x i32> %a0, <4 x i32> %a1, ptr %a2) { @@ -182,19 +227,19 @@ define <8 x i16> @concat_trunc_v4i32_v8i16_multiuse(<4 x i32> %a0, <4 x i32> %a1 ret <8 x i16> %r } -; negative - bitcasts +; negative - bitcasts (unscalable higher element count) -define <8 x float> @concat_bitcast_v4i32_v8f32(<4 x i32> %a0, <4 x i32> %a1) { -; CHECK-LABEL: @concat_bitcast_v4i32_v8f32( -; CHECK-NEXT: [[X0:%.*]] = bitcast <4 x i32> [[A0:%.*]] to <4 x float> -; CHECK-NEXT: [[X1:%.*]] = bitcast <4 x i32> [[A1:%.*]] to <4 x float> -; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X0]], <4 x float> [[X1]], <8 x i32> -; CHECK-NEXT: ret <8 x float> [[R]] +define <16 x i16> @revpair_bitcast_v4i32_v16i16(<4 x i32> %a0, <4 x i32> %a1) { +; CHECK-LABEL: @revpair_bitcast_v4i32_v16i16( +; CHECK-NEXT: [[X0:%.*]] = bitcast <4 x i32> [[A0:%.*]] to <8 x i16> +; CHECK-NEXT: [[X1:%.*]] = bitcast <4 x i32> [[A1:%.*]] to <8 x i16> +; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[X0]], <8 x i16> [[X1]], <16 x i32> +; CHECK-NEXT: ret <16 x i16> [[R]] ; - %x0 = bitcast <4 x i32> %a0 to <4 x float> - %x1 = bitcast <4 x i32> %a1 to <4 x float> - %r = shufflevector <4 x float> %x0, <4 x float> %x1, <8 x i32> - ret <8 x float> %r + %x0 = bitcast <4 x i32> %a0 to <8 x i16> + %x1 = bitcast <4 x i32> %a1 to <8 x i16> + %r = shufflevector <8 x i16> %x0, <8 x i16> %x1, <16 x i32> + ret <16 x i16> %r } ; negative - src type mismatch -- GitLab From 478c42004c2bd4c91a01c47450eca6cdb6b0982d Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Thu, 11 Apr 2024 10:25:56 +0100 Subject: [PATCH 503/695] [VPlan] Update recipe ::clone definitions to use cloned tys (NFC). Update definitions on ::clone in recipe sub-types to use the sub-type as return type. This avoids typecasts down to the cloned type in some cases. --- llvm/lib/Transforms/Vectorize/VPlan.h | 56 ++++++++++++++------------- 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 5dc905a3c407..d86a81d4fb4c 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -888,6 +888,8 @@ public: return R && classof(R); } + virtual VPSingleDefRecipe *clone() override = 0; + /// Returns the underlying instruction. Instruction *getUnderlyingInstr() { return cast(getUnderlyingValue()); @@ -1248,7 +1250,7 @@ public: VP_CLASSOF_IMPL(VPDef::VPInstructionSC) - VPRecipeBase *clone() override { + VPInstruction *clone() override { SmallVector Operands(operands()); auto *New = new VPInstruction(Opcode, Operands, getDebugLoc(), Name); New->transferFlags(*this); @@ -1335,7 +1337,7 @@ public: ~VPWidenRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenRecipe *clone() override { auto *R = new VPWidenRecipe(*getUnderlyingInstr(), operands()); R->transferFlags(*this); return R; @@ -1380,7 +1382,7 @@ public: ~VPWidenCastRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenCastRecipe *clone() override { if (auto *UV = getUnderlyingValue()) return new VPWidenCastRecipe(Opcode, getOperand(0), ResultTy, *cast(UV)); @@ -1420,7 +1422,7 @@ public: ~VPScalarCastRecipe() override = default; - VPRecipeBase *clone() override { + VPScalarCastRecipe *clone() override { return new VPScalarCastRecipe(Opcode, getOperand(0), ResultTy); } @@ -1465,7 +1467,7 @@ public: ~VPWidenCallRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenCallRecipe *clone() override { return new VPWidenCallRecipe(*cast(getUnderlyingInstr()), operands(), VectorIntrinsicID, getDebugLoc(), Variant); @@ -1492,7 +1494,7 @@ struct VPWidenSelectRecipe : public VPSingleDefRecipe { ~VPWidenSelectRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenSelectRecipe *clone() override { return new VPWidenSelectRecipe(*cast(getUnderlyingInstr()), operands()); } @@ -1540,7 +1542,7 @@ public: ~VPWidenGEPRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenGEPRecipe *clone() override { return new VPWidenGEPRecipe(cast(getUnderlyingInstr()), operands()); } @@ -1581,7 +1583,7 @@ public: return true; } - VPRecipeBase *clone() override { + VPVectorPointerRecipe *clone() override { return new VPVectorPointerRecipe(getOperand(0), IndexedTy, IsReverse, isInBounds(), getDebugLoc()); } @@ -1696,7 +1698,7 @@ public: ~VPWidenIntOrFpInductionRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenIntOrFpInductionRecipe *clone() override { return new VPWidenIntOrFpInductionRecipe(IV, getStartValue(), getStepValue(), IndDesc, Trunc); } @@ -1771,7 +1773,7 @@ public: ~VPWidenPointerInductionRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenPointerInductionRecipe *clone() override { return new VPWidenPointerInductionRecipe( cast(getUnderlyingInstr()), getOperand(0), getOperand(1), IndDesc, IsScalarAfterVectorization); @@ -1810,7 +1812,7 @@ public: addOperand(Start); } - VPRecipeBase *clone() override { + VPWidenPHIRecipe *clone() override { llvm_unreachable("cloning not implemented yet"); } @@ -1853,7 +1855,7 @@ struct VPFirstOrderRecurrencePHIRecipe : public VPHeaderPHIRecipe { return R->getVPDefID() == VPDef::VPFirstOrderRecurrencePHISC; } - VPRecipeBase *clone() override { + VPFirstOrderRecurrencePHIRecipe *clone() override { return new VPFirstOrderRecurrencePHIRecipe( cast(getUnderlyingInstr()), *getOperand(0)); } @@ -1893,7 +1895,7 @@ public: ~VPReductionPHIRecipe() override = default; - VPRecipeBase *clone() override { + VPReductionPHIRecipe *clone() override { auto *R = new VPReductionPHIRecipe(cast(getUnderlyingInstr()), RdxDesc, *getOperand(0), IsInLoop, IsOrdered); @@ -1940,7 +1942,7 @@ public: "Expected an odd number of operands"); } - VPRecipeBase *clone() override { + VPBlendRecipe *clone() override { SmallVector Ops(operands()); return new VPBlendRecipe(cast(getUnderlyingValue()), Ops); } @@ -2019,7 +2021,7 @@ public: } ~VPInterleaveRecipe() override = default; - VPRecipeBase *clone() override { + VPInterleaveRecipe *clone() override { return new VPInterleaveRecipe(IG, getAddr(), getStoredValues(), getMask(), NeedsMaskForGaps); } @@ -2093,7 +2095,7 @@ public: ~VPReductionRecipe() override = default; - VPRecipeBase *clone() override { + VPReductionRecipe *clone() override { return new VPReductionRecipe(RdxDesc, getUnderlyingInstr(), getChainOp(), getVecOp(), getCondOp(), IsOrdered); } @@ -2142,7 +2144,7 @@ public: ~VPReplicateRecipe() override = default; - VPRecipeBase *clone() override { + VPReplicateRecipe *clone() override { auto *Copy = new VPReplicateRecipe(getUnderlyingInstr(), operands(), IsUniform, isPredicated() ? getMask() : nullptr); @@ -2204,7 +2206,7 @@ public: addOperand(BlockInMask); } - VPRecipeBase *clone() override { + VPBranchOnMaskRecipe *clone() override { return new VPBranchOnMaskRecipe(getOperand(0)); } @@ -2255,7 +2257,7 @@ public: : VPSingleDefRecipe(VPDef::VPPredInstPHISC, PredV) {} ~VPPredInstPHIRecipe() override = default; - VPRecipeBase *clone() override { + VPPredInstPHIRecipe *clone() override { return new VPPredInstPHIRecipe(getOperand(0)); } @@ -2323,7 +2325,7 @@ public: setMask(Mask); } - VPRecipeBase *clone() override { + VPWidenMemoryInstructionRecipe *clone() override { if (isStore()) return new VPWidenMemoryInstructionRecipe( cast(Ingredient), getAddr(), getStoredValue(), getMask(), @@ -2399,7 +2401,9 @@ public: ~VPExpandSCEVRecipe() override = default; - VPRecipeBase *clone() override { return new VPExpandSCEVRecipe(Expr, SE); } + VPExpandSCEVRecipe *clone() override { + return new VPExpandSCEVRecipe(Expr, SE); + } VP_CLASSOF_IMPL(VPDef::VPExpandSCEVSC) @@ -2426,7 +2430,7 @@ public: ~VPCanonicalIVPHIRecipe() override = default; - VPRecipeBase *clone() override { + VPCanonicalIVPHIRecipe *clone() override { auto *R = new VPCanonicalIVPHIRecipe(getOperand(0), getDebugLoc()); R->addOperand(getBackedgeValue()); return R; @@ -2484,7 +2488,7 @@ public: ~VPActiveLaneMaskPHIRecipe() override = default; - VPRecipeBase *clone() override { + VPActiveLaneMaskPHIRecipe *clone() override { return new VPActiveLaneMaskPHIRecipe(getOperand(0), getDebugLoc()); } @@ -2551,7 +2555,7 @@ public: ~VPWidenCanonicalIVRecipe() override = default; - VPRecipeBase *clone() override { + VPWidenCanonicalIVRecipe *clone() override { return new VPWidenCanonicalIVRecipe( cast(getOperand(0))); } @@ -2602,7 +2606,7 @@ public: ~VPDerivedIVRecipe() override = default; - VPRecipeBase *clone() override { + VPDerivedIVRecipe *clone() override { return new VPDerivedIVRecipe(Kind, FPBinOp, getStartValue(), getOperand(1), getStepValue()); } @@ -2656,7 +2660,7 @@ public: ~VPScalarIVStepsRecipe() override = default; - VPRecipeBase *clone() override { + VPScalarIVStepsRecipe *clone() override { return new VPScalarIVStepsRecipe( getOperand(0), getOperand(1), InductionOpcode, hasFastMathFlags() ? getFastMathFlags() : FastMathFlags()); -- GitLab From 462e1023838703f1d3e763869afdd72ec5342a33 Mon Sep 17 00:00:00 2001 From: Poseydon42 Date: Thu, 11 Apr 2024 10:40:52 +0100 Subject: [PATCH 504/695] [InstCombine] Fold (X / C) < X and (X >> C) < X into X > 0 (#85555) Proofs: https://alive2.llvm.org/ce/z/52droC This resolves #85313. --- .../InstCombine/InstCombineCompares.cpp | 34 +++++ .../InstCombine/icmp-div-constant.ll | 141 ++++++++++++++++++ 2 files changed, 175 insertions(+) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 9ff1e3aa5502..7292bb62702a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -7163,6 +7163,40 @@ Instruction *InstCombinerImpl::foldICmpCommutative(ICmpInst::Predicate Pred, if (Value *V = foldICmpWithLowBitMaskedVal(Pred, Op0, Op1, Q, *this)) return replaceInstUsesWith(CxtI, V); + // Folding (X / Y) pred X => X swap(pred) 0 for constant Y other than 0 or 1 + { + const APInt *Divisor; + if (match(Op0, m_UDiv(m_Specific(Op1), m_APInt(Divisor))) && + Divisor->ugt(1)) { + return new ICmpInst(ICmpInst::getSwappedPredicate(Pred), Op1, + Constant::getNullValue(Op1->getType())); + } + + if (!ICmpInst::isUnsigned(Pred) && + match(Op0, m_SDiv(m_Specific(Op1), m_APInt(Divisor))) && + Divisor->ugt(1)) { + return new ICmpInst(ICmpInst::getSwappedPredicate(Pred), Op1, + Constant::getNullValue(Op1->getType())); + } + } + + // Another case of this fold is (X >> Y) pred X => X swap(pred) 0 if Y != 0 + { + const APInt *Shift; + if (match(Op0, m_LShr(m_Specific(Op1), m_APInt(Shift))) && + !Shift->isZero()) { + return new ICmpInst(ICmpInst::getSwappedPredicate(Pred), Op1, + Constant::getNullValue(Op1->getType())); + } + + if ((Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_SGE) && + match(Op0, m_AShr(m_Specific(Op1), m_APInt(Shift))) && + !Shift->isZero()) { + return new ICmpInst(ICmpInst::getSwappedPredicate(Pred), Op1, + Constant::getNullValue(Op1->getType())); + } + } + return nullptr; } diff --git a/llvm/test/Transforms/InstCombine/icmp-div-constant.ll b/llvm/test/Transforms/InstCombine/icmp-div-constant.ll index 8dcb96284685..b047715432d7 100644 --- a/llvm/test/Transforms/InstCombine/icmp-div-constant.ll +++ b/llvm/test/Transforms/InstCombine/icmp-div-constant.ll @@ -375,3 +375,144 @@ define i1 @sdiv_eq_smin_use(i32 %x, i32 %y) { %r = icmp eq i32 %d, -2147483648 ret i1 %r } + +; Fold (X / C) cmp X into X ~cmp 0 (~cmp is the inverse predicate of cmp), for some C != 1 +; Alternative form of this fold is when division is replaced with logic right shift + +define i1 @sdiv_x_by_const_cmp_x(i32 %x) { +; CHECK-LABEL: @sdiv_x_by_const_cmp_x( +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; + %v = sdiv i32 %x, 13 + %r = icmp eq i32 %v, %x + ret i1 %r +} + +define i1 @udiv_x_by_const_cmp_x(i32 %x) { +; CHECK-LABEL: @udiv_x_by_const_cmp_x( +; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; + %1 = udiv i32 %x, 123 + %2 = icmp slt i32 %1, %x + ret i1 %2 +} + +; Same as above but with right shift instead of division (C != 0) + +define i1 @lshr_x_by_const_cmp_x(i32 %x) { +; CHECK-LABEL: @lshr_x_by_const_cmp_x( +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; + %v = lshr i32 %x, 1 + %r = icmp eq i32 %v, %x + ret i1 %r +} + +define <4 x i1> @lshr_by_const_cmp_sle_value(<4 x i32> %x) { +; CHECK-LABEL: @lshr_by_const_cmp_sle_value( +; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[X:%.*]], +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %v = lshr <4 x i32> %x, + %r = icmp sle <4 x i32> %v, %x + ret <4 x i1> %r +} + +define i1 @lshr_by_const_cmp_sge_value(i32 %x) { +; CHECK-LABEL: @lshr_by_const_cmp_sge_value( +; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %v = lshr i32 %x, 3 + %r = icmp sge i32 %v, %x + ret i1 %r +} + +define i1 @ashr_x_by_const_cmp_sge_x(i32 %x) { +; CHECK-LABEL: @ashr_x_by_const_cmp_sge_x( +; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[R]] +; + %v = ashr i32 %x, 5 + %r = icmp sge i32 %v, %x + ret i1 %r +} + +; Negative test - constant is 1 + +define <2 x i1> @udiv_x_by_const_cmp_eq_value_neg(<2 x i32> %x) { +; CHECK-LABEL: @udiv_x_by_const_cmp_eq_value_neg( +; CHECK-NEXT: [[V:%.*]] = udiv <2 x i32> [[X:%.*]], +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i32> [[V]], [[X]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %v = udiv <2 x i32> %x, + %r = icmp eq <2 x i32> %v, %x + ret <2 x i1> %r +} + +define <2 x i1> @sdiv_x_by_const_cmp_eq_value_neg(<2 x i32> %x) { +; CHECK-LABEL: @sdiv_x_by_const_cmp_eq_value_neg( +; CHECK-NEXT: [[V:%.*]] = sdiv <2 x i32> [[X:%.*]], +; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i32> [[V]], [[X]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %v = sdiv <2 x i32> %x, + %r = icmp eq <2 x i32> %v, %x + ret <2 x i1> %r +} + +; Negative test - constant is 0 + +define <2 x i1> @lshr_x_by_const_cmp_slt_value_neg(<2 x i32> %x) { +; CHECK-LABEL: @lshr_x_by_const_cmp_slt_value_neg( +; CHECK-NEXT: [[V:%.*]] = lshr <2 x i32> [[X:%.*]], +; CHECK-NEXT: [[R:%.*]] = icmp slt <2 x i32> [[V]], [[X]] +; CHECK-NEXT: ret <2 x i1> [[R]] +; + %v = lshr <2 x i32> %x, + %r = icmp slt <2 x i32> %v, %x + ret <2 x i1> %r +} + +; Negative test - unsigned predicate with sdiv + +define i1 @sdiv_x_by_const_cmp_ult_value_neg(i32 %x) { +; CHECK-LABEL: @sdiv_x_by_const_cmp_ult_value_neg( +; CHECK-NEXT: [[V:%.*]] = sdiv i32 [[X:%.*]], 3 +; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[V]], [[X]] +; CHECK-NEXT: ret i1 [[R]] +; + %v = sdiv i32 %x, 3 + %r = icmp ult i32 %v, %x + ret i1 %r +} + +; Negative case - one of the components of a vector is 1 + +define <4 x i1> @sdiv_x_by_const_cmp_sgt_value_neg(<4 x i32> %x) { +; CHECK-LABEL: @sdiv_x_by_const_cmp_sgt_value_neg( +; CHECK-NEXT: [[V:%.*]] = sdiv <4 x i32> [[X:%.*]], +; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[V]], [[X]] +; CHECK-NEXT: ret <4 x i1> [[R]] +; + %v = sdiv <4 x i32> %x, + %r = icmp sgt <4 x i32> %v, %x + ret <4 x i1> %r +} + +; Negative case - ashr only allows sge/slt predicates + +define i1 @ashr_x_by_const_cmp_sle_value_neg(i32 %x) { +; CHECK-LABEL: @ashr_x_by_const_cmp_sle_value_neg( +; CHECK-NEXT: [[V:%.*]] = ashr i32 [[X:%.*]], 3 +; CHECK-NEXT: [[R:%.*]] = icmp sle i32 [[V]], [[X]] +; CHECK-NEXT: ret i1 [[R]] +; + %v = ashr i32 %x, 3 + %r = icmp sle i32 %v, %x + ret i1 %r +} -- GitLab From 82ae646eb49cfd762db7db0a74b130970fe45d97 Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Thu, 11 Apr 2024 10:41:07 +0100 Subject: [PATCH 505/695] [llvm-mca] Remove spurious include_directories() (#88277) llvm-mca does not have an include directory so this commit removes the spurious include_directories directive. --- llvm/tools/llvm-mca/CMakeLists.txt | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/tools/llvm-mca/CMakeLists.txt b/llvm/tools/llvm-mca/CMakeLists.txt index 878a05c51cfb..4ef8b9afa12a 100644 --- a/llvm/tools/llvm-mca/CMakeLists.txt +++ b/llvm/tools/llvm-mca/CMakeLists.txt @@ -1,5 +1,3 @@ -include_directories(include) - set(LLVM_LINK_COMPONENTS AllTargetsAsmParsers AllTargetsMCAs # CustomBehaviour and InstrPostProcess -- GitLab From e7bc53726459bba3a48b1f529f1fd9472ad9051c Mon Sep 17 00:00:00 2001 From: Andreas Jonson Date: Thu, 11 Apr 2024 11:42:59 +0200 Subject: [PATCH 506/695] [IPSCCP] Add range attribute handling (#86747) Support the new range attribute to infer ConstantRanges in IPSCCP. --- .../llvm/Transforms/Utils/SCCPSolver.h | 4 + llvm/lib/Transforms/IPO/SCCP.cpp | 3 +- llvm/lib/Transforms/Utils/SCCPSolver.cpp | 40 ++++- llvm/test/Transforms/SCCP/range-attribute.ll | 154 ++++++++++++++++++ 4 files changed, 197 insertions(+), 4 deletions(-) create mode 100644 llvm/test/Transforms/SCCP/range-attribute.ll diff --git a/llvm/include/llvm/Transforms/Utils/SCCPSolver.h b/llvm/include/llvm/Transforms/Utils/SCCPSolver.h index 1a95f80812aa..9f7ccd4a8a32 100644 --- a/llvm/include/llvm/Transforms/Utils/SCCPSolver.h +++ b/llvm/include/llvm/Transforms/Utils/SCCPSolver.h @@ -151,6 +151,10 @@ public: /// works with both scalars and structs. void markOverdefined(Value *V); + /// trackValueOfArgument - Mark the specified argument overdefined unless it + /// have range attribute. This works with both scalars and structs. + void trackValueOfArgument(Argument *V); + // isStructLatticeConstant - Return true if all the lattice values // corresponding to elements of the structure are constants, // false otherwise. diff --git a/llvm/lib/Transforms/IPO/SCCP.cpp b/llvm/lib/Transforms/IPO/SCCP.cpp index b1f9b827dcba..f8920541e6fd 100644 --- a/llvm/lib/Transforms/IPO/SCCP.cpp +++ b/llvm/lib/Transforms/IPO/SCCP.cpp @@ -144,9 +144,8 @@ static bool runIPSCCP( // Assume the function is called. Solver.markBlockExecutable(&F.front()); - // Assume nothing about the incoming arguments. for (Argument &AI : F.args()) - Solver.markOverdefined(&AI); + Solver.trackValueOfArgument(&AI); } // Determine if we can track any of the module's global variables. If so, add diff --git a/llvm/lib/Transforms/Utils/SCCPSolver.cpp b/llvm/lib/Transforms/Utils/SCCPSolver.cpp index 38fc7763c5b2..b82ed25a6d0c 100644 --- a/llvm/lib/Transforms/Utils/SCCPSolver.cpp +++ b/llvm/lib/Transforms/Utils/SCCPSolver.cpp @@ -428,6 +428,13 @@ private: return markConstant(ValueState[V], V, C); } + /// markConstantRange - Mark the object as constant range with \p CR. If the + /// object is not a constant range with the range \p CR, add it to the + /// instruction work list so that the users of the instruction are updated + /// later. + bool markConstantRange(ValueLatticeElement &IV, Value *V, + const ConstantRange &CR); + // markOverdefined - Make a value be marked as "overdefined". If the // value is not already overdefined, add it to the overdefined instruction // work list so that the users of the instruction are updated later. @@ -788,6 +795,17 @@ public: markOverdefined(ValueState[V], V); } + void trackValueOfArgument(Argument *A) { + if (A->getType()->isIntegerTy()) { + if (std::optional Range = A->getRange()) { + markConstantRange(ValueState[A], A, *Range); + return; + } + } + // Assume nothing about the incoming arguments without range. + markOverdefined(A); + } + bool isStructLatticeConstant(Function *F, StructType *STy); Constant *getConstant(const ValueLatticeElement &LV, Type *Ty) const; @@ -873,6 +891,15 @@ bool SCCPInstVisitor::markConstant(ValueLatticeElement &IV, Value *V, return true; } +bool SCCPInstVisitor::markConstantRange(ValueLatticeElement &IV, Value *V, + const ConstantRange &CR) { + if (!IV.markConstantRange(CR)) + return false; + LLVM_DEBUG(dbgs() << "markConstantRange: " << CR << ": " << *V << '\n'); + pushToWorkList(IV, V); + return true; +} + bool SCCPInstVisitor::markOverdefined(ValueLatticeElement &IV, Value *V) { if (!IV.markOverdefined()) return false; @@ -1581,10 +1608,15 @@ void SCCPInstVisitor::visitStoreInst(StoreInst &SI) { } static ValueLatticeElement getValueFromMetadata(const Instruction *I) { - if (MDNode *Ranges = I->getMetadata(LLVMContext::MD_range)) - if (I->getType()->isIntegerTy()) + if (I->getType()->isIntegerTy()) { + if (MDNode *Ranges = I->getMetadata(LLVMContext::MD_range)) return ValueLatticeElement::getRange( getConstantRangeFromMetadata(*Ranges)); + + if (const auto *CB = dyn_cast(I)) + if (std::optional Range = CB->getRange()) + return ValueLatticeElement::getRange(*Range); + } if (I->hasMetadata(LLVMContext::MD_nonnull)) return ValueLatticeElement::getNot( ConstantPointerNull::get(cast(I->getType()))); @@ -2090,6 +2122,10 @@ const SmallPtrSet SCCPSolver::getMRVFunctionsTracked() { void SCCPSolver::markOverdefined(Value *V) { Visitor->markOverdefined(V); } +void SCCPSolver::trackValueOfArgument(Argument *V) { + Visitor->trackValueOfArgument(V); +} + bool SCCPSolver::isStructLatticeConstant(Function *F, StructType *STy) { return Visitor->isStructLatticeConstant(F, STy); } diff --git a/llvm/test/Transforms/SCCP/range-attribute.ll b/llvm/test/Transforms/SCCP/range-attribute.ll new file mode 100644 index 000000000000..ae66af91bb8e --- /dev/null +++ b/llvm/test/Transforms/SCCP/range-attribute.ll @@ -0,0 +1,154 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -passes=ipsccp -S | FileCheck %s + +declare void @use(i1) +declare i32 @get_i32() + +define void @range_attribute(i32 range(i32 0, 10) %v) { +; CHECK-LABEL: @range_attribute( +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[V:%.*]], 9 +; CHECK-NEXT: call void @use(i1 [[C2]]) +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: [[C4:%.*]] = icmp ugt i32 [[V]], 8 +; CHECK-NEXT: call void @use(i1 [[C4]]) +; CHECK-NEXT: ret void +; + %c1 = icmp ult i32 %v, 10 + call void @use(i1 %c1) + %c2 = icmp ult i32 %v, 9 + call void @use(i1 %c2) + %c3 = icmp ugt i32 %v, 9 + call void @use(i1 %c3) + %c4 = icmp ugt i32 %v, 8 + call void @use(i1 %c4) + ret void +} + +define i32 @range_attribute_single(i32 range(i32 0, 1) %v) { +; CHECK-LABEL: @range_attribute_single( +; CHECK-NEXT: ret i32 0 +; + ret i32 %v +} + +define void @call_range_attribute() { +; CHECK-LABEL: @call_range_attribute( +; CHECK-NEXT: [[V:%.*]] = call range(i32 0, 10) i32 @get_i32() +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[V]], 9 +; CHECK-NEXT: call void @use(i1 [[C2]]) +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: [[C4:%.*]] = icmp ugt i32 [[V]], 8 +; CHECK-NEXT: call void @use(i1 [[C4]]) +; CHECK-NEXT: ret void +; + %v = call range(i32 0, 10) i32 @get_i32() + %c1 = icmp ult i32 %v, 10 + call void @use(i1 %c1) + %c2 = icmp ult i32 %v, 9 + call void @use(i1 %c2) + %c3 = icmp ugt i32 %v, 9 + call void @use(i1 %c3) + %c4 = icmp ugt i32 %v, 8 + call void @use(i1 %c4) + ret void +} + + +declare range(i32 0, 10) i32 @get_i32_in_range() + +define void @call_range_result() { +; CHECK-LABEL: @call_range_result( +; CHECK-NEXT: [[V:%.*]] = call i32 @get_i32_in_range() +; CHECK-NEXT: call void @use(i1 true) +; CHECK-NEXT: [[C2:%.*]] = icmp ult i32 [[V]], 9 +; CHECK-NEXT: call void @use(i1 [[C2]]) +; CHECK-NEXT: call void @use(i1 false) +; CHECK-NEXT: [[C4:%.*]] = icmp ugt i32 [[V]], 8 +; CHECK-NEXT: call void @use(i1 [[C4]]) +; CHECK-NEXT: ret void +; + %v = call i32 @get_i32_in_range() + %c1 = icmp ult i32 %v, 10 + call void @use(i1 %c1) + %c2 = icmp ult i32 %v, 9 + call void @use(i1 %c2) + %c3 = icmp ugt i32 %v, 9 + call void @use(i1 %c3) + %c4 = icmp ugt i32 %v, 8 + call void @use(i1 %c4) + ret void +} + +define internal i1 @ip_cmp_range_attribute(i32 %v) { +; CHECK-LABEL: @ip_cmp_range_attribute( +; CHECK-NEXT: ret i1 undef +; + %c = icmp ult i32 %v, 10 + ret i1 %c +} + +define i1 @ip_range_attribute(i32 range(i32 0, 10) %v) { +; CHECK-LABEL: @ip_range_attribute( +; CHECK-NEXT: [[C:%.*]] = call i1 @ip_cmp_range_attribute(i32 [[V:%.*]]) +; CHECK-NEXT: ret i1 true +; + %c = call i1 @ip_cmp_range_attribute(i32 %v) + ret i1 %c +} + +define internal i1 @ip_cmp_range_call(i32 %v) { +; CHECK-LABEL: @ip_cmp_range_call( +; CHECK-NEXT: ret i1 undef +; + %c = icmp ult i32 %v, 10 + ret i1 %c +} + +define i1 @ip_range_call() { +; CHECK-LABEL: @ip_range_call( +; CHECK-NEXT: [[V:%.*]] = call range(i32 0, 10) i32 @get_i32() +; CHECK-NEXT: [[C:%.*]] = call i1 @ip_cmp_range_call(i32 [[V]]) +; CHECK-NEXT: ret i1 true +; + %v = call range(i32 0, 10) i32 @get_i32() + %c = call i1 @ip_cmp_range_call(i32 %v) + ret i1 %c +} + +define internal i1 @ip_cmp_range_result(i32 %v) { +; CHECK-LABEL: @ip_cmp_range_result( +; CHECK-NEXT: ret i1 undef +; + %c = icmp ult i32 %v, 10 + ret i1 %c +} + +define i1 @ip_range_result() { +; CHECK-LABEL: @ip_range_result( +; CHECK-NEXT: [[V:%.*]] = call range(i32 0, 10) i32 @get_i32() +; CHECK-NEXT: [[C:%.*]] = call i1 @ip_cmp_range_result(i32 [[V]]) +; CHECK-NEXT: ret i1 true +; + %v = call range(i32 0, 10) i32 @get_i32() + %c = call i1 @ip_cmp_range_result(i32 %v) + ret i1 %c +} + +define internal i1 @ip_cmp_with_range_attribute(i32 range(i32 0, 10) %v) { +; CHECK-LABEL: @ip_cmp_with_range_attribute( +; CHECK-NEXT: ret i1 undef +; + %c = icmp eq i32 %v, 5 + ret i1 %c +} + +define i1 @ip_range_attribute_constant() { +; CHECK-LABEL: @ip_range_attribute_constant( +; CHECK-NEXT: [[C:%.*]] = call i1 @ip_cmp_with_range_attribute(i32 5) +; CHECK-NEXT: ret i1 true +; + %c = call i1 @ip_cmp_with_range_attribute(i32 5) + ret i1 %c +} -- GitLab From eef63d3c92766c6f8e78eefb9bb37ae01fbedbfc Mon Sep 17 00:00:00 2001 From: Tom Eccles Date: Thu, 11 Apr 2024 10:43:49 +0100 Subject: [PATCH 507/695] [mlir][OpenMP] add missing load for reduction cleanup region (#88289) I missed this before. For by-ref reductions, the private reduction variable is a pointer to the pointer to the variable. So an extra load is required to get the right value. See the "red.private.value.n" loads in the reduction combiner region for reference. --- .../Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp | 13 +++++++++++-- .../LLVMIR/openmp-parallel-reduction-cleanup.mlir | 6 ++++-- .../LLVMIR/openmp-wsloop-reduction-cleanup.mlir | 6 ++++-- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index a59677c02fc3..300fc8ba56fc 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -889,8 +889,17 @@ static LogicalResult inlineReductionCleanup( // map the argument to the cleanup region Block &entry = cleanupRegion.front(); - moduleTranslation.mapValue(entry.getArgument(0), - privateReductionVariables[i]); + + llvm::Instruction *potentialTerminator = + builder.GetInsertBlock()->empty() ? nullptr + : &builder.GetInsertBlock()->back(); + if (potentialTerminator && potentialTerminator->isTerminator()) + builder.SetInsertPoint(potentialTerminator); + llvm::Value *reductionVar = builder.CreateLoad( + moduleTranslation.convertType(entry.getArgument(0).getType()), + privateReductionVariables[i]); + + moduleTranslation.mapValue(entry.getArgument(0), reductionVar); if (failed(inlineConvertOmpRegions(cleanupRegion, "omp.reduction.cleanup", builder, moduleTranslation))) diff --git a/mlir/test/Target/LLVMIR/openmp-parallel-reduction-cleanup.mlir b/mlir/test/Target/LLVMIR/openmp-parallel-reduction-cleanup.mlir index 9ae4c4ad392b..b7f71f438e56 100644 --- a/mlir/test/Target/LLVMIR/openmp-parallel-reduction-cleanup.mlir +++ b/mlir/test/Target/LLVMIR/openmp-parallel-reduction-cleanup.mlir @@ -86,8 +86,10 @@ // Cleanup region: // CHECK: [[OMP_FINALIZE]]: -// CHECK: call void @free(ptr %[[PRIV_PTR_I]]) -// CHECK: call void @free(ptr %[[PRIV_PTR_J]]) +// CHECK: %[[PRIV_I:.+]] = load ptr, ptr %[[PRIV_PTR_I]], align 8 +// CHECK: call void @free(ptr %[[PRIV_I]]) +// CHECK: %[[PRIV_J:.+]] = load ptr, ptr %[[PRIV_PTR_J]], align 8 +// CHECK: call void @free(ptr %[[PRIV_J]]) // Reduction function. // CHECK: define internal void @[[REDFUNC]] diff --git a/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir b/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir index a1e17afa53e2..3842522934e4 100644 --- a/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir +++ b/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir @@ -63,8 +63,10 @@ // Weirdly the finalization block is generated before the reduction blocks: // CHECK: [[FINALIZE:.+]]: // CHECK: call void @__kmpc_barrier -// CHECK: call void @free(ptr %[[PRIV_PTR_I]]) -// CHECK: call void @free(ptr %[[PRIV_PTR_J]]) +// CHECK: %[[PRIV_I:.+]] = load ptr, ptr %[[PRIV_PTR_I]], align 8 +// CHECK: call void @free(ptr %[[PRIV_I]]) +// CHECK: %[[PRIV_J:.+]] = load ptr, ptr %[[PRIV_PTR_J]], align 8 +// CHECK: call void @free(ptr %[[PRIV_J]]) // CHECK: ret void // Non-atomic reduction: -- GitLab From 6f068b9cf1ac09945c096269f0c6c276d2ec95c4 Mon Sep 17 00:00:00 2001 From: Tom Eccles Date: Thu, 11 Apr 2024 10:44:09 +0100 Subject: [PATCH 508/695] [flang][OpenMP] Allocate array reduction variables on the heap (#87773) Following up on a review comment: https://github.com/llvm/llvm-project/pull/84958#discussion_r1527627848 Reductions might be inlined inside of a loop so stack allocations are not safe. Normally flang allocates arrays on the stack. Allocatable arrays have a different type: fir.box>> instead of fir.box>. This patch will allocate all arrays on the heap. Reductions on allocatable arrays still aren't supported (but I will get to this soon). --- flang/lib/Lower/OpenMP/ReductionProcessor.cpp | 78 +++++++++++++++++-- .../Lower/OpenMP/parallel-reduction-array.f90 | 20 ++++- .../OpenMP/parallel-reduction-array2.f90 | 20 ++++- .../test/Lower/OpenMP/parallel-reduction3.f90 | 31 ++++---- .../wsloop-reduction-array-assumed-shape.f90 | 17 +++- .../Lower/OpenMP/wsloop-reduction-array.f90 | 19 ++++- .../Lower/OpenMP/wsloop-reduction-array2.f90 | 21 ++++- 7 files changed, 171 insertions(+), 35 deletions(-) diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp index 0453c0152277..918edf27baf6 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp @@ -20,6 +20,7 @@ #include "flang/Optimizer/Builder/Todo.h" #include "flang/Optimizer/Dialect/FIRType.h" #include "flang/Optimizer/HLFIR/HLFIROps.h" +#include "flang/Optimizer/Support/FatalError.h" #include "flang/Parser/tools.h" #include "mlir/Dialect/OpenMP/OpenMPDialect.h" #include "llvm/Support/CommandLine.h" @@ -391,8 +392,60 @@ static void genCombiner(fir::FirOpBuilder &builder, mlir::Location loc, TODO(loc, "OpenMP genCombiner for unsupported reduction variable type"); } +static void +createReductionCleanupRegion(fir::FirOpBuilder &builder, mlir::Location loc, + mlir::omp::DeclareReductionOp &reductionDecl) { + mlir::Type redTy = reductionDecl.getType(); + + mlir::Region &cleanupRegion = reductionDecl.getCleanupRegion(); + assert(cleanupRegion.empty()); + mlir::Block *block = + builder.createBlock(&cleanupRegion, cleanupRegion.end(), {redTy}, {loc}); + builder.setInsertionPointToEnd(block); + + auto typeError = [loc]() { + fir::emitFatalError(loc, + "Attempt to create an omp reduction cleanup region " + "for a type that wasn't allocated", + /*genCrashDiag=*/true); + }; + + mlir::Type valTy = fir::unwrapRefType(redTy); + if (auto boxTy = mlir::dyn_cast_or_null(valTy)) { + mlir::Type innerTy = fir::extractSequenceType(boxTy); + if (!mlir::isa(innerTy)) + typeError(); + + mlir::Value arg = block->getArgument(0); + arg = builder.loadIfRef(loc, arg); + assert(mlir::isa(arg.getType())); + + // Deallocate box + // The FIR type system doesn't nesecarrily know that this is a mutable box + // if we allocated the thread local array on the heap to avoid looped stack + // allocations. + mlir::Value addr = + hlfir::genVariableRawAddress(loc, builder, hlfir::Entity{arg}); + mlir::Value isAllocated = builder.genIsNotNullAddr(loc, addr); + fir::IfOp ifOp = + builder.create(loc, isAllocated, /*withElseRegion=*/false); + builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); + + mlir::Value cast = builder.createConvert( + loc, fir::HeapType::get(fir::dyn_cast_ptrEleTy(addr.getType())), addr); + builder.create(loc, cast); + + builder.setInsertionPointAfter(ifOp); + builder.create(loc); + return; + } + + typeError(); +} + static mlir::Value createReductionInitRegion(fir::FirOpBuilder &builder, mlir::Location loc, + mlir::omp::DeclareReductionOp &reductionDecl, const ReductionProcessor::ReductionIdentifier redId, mlir::Type type, bool isByRef) { mlir::Type ty = fir::unwrapRefType(type); @@ -419,11 +472,24 @@ createReductionInitRegion(fir::FirOpBuilder &builder, mlir::Location loc, // Create the private copy from the initial fir.box: hlfir::Entity source = hlfir::Entity{builder.getBlock()->getArgument(0)}; - // TODO: if the whole reduction is nested inside of a loop, this alloca - // could lead to a stack overflow (the memory is only freed at the end of - // the stack frame). The reduction declare operation needs a deallocation - // region to undo the init region. - hlfir::Entity temp = createStackTempFromMold(loc, builder, source); + // Allocating on the heap in case the whole reduction is nested inside of a + // loop + // TODO: compare performance here to using allocas - this could be made to + // work by inserting stacksave/stackrestore around the reduction in + // openmpirbuilder + auto [temp, needsDealloc] = createTempFromMold(loc, builder, source); + // if needsDealloc isn't statically false, add cleanup region. TODO: always + // do this for allocatable boxes because they might have been re-allocated + // in the body of the loop/parallel region + std::optional cstNeedsDealloc = + fir::getIntIfConstant(needsDealloc); + assert(cstNeedsDealloc.has_value() && + "createTempFromMold decides this statically"); + if (cstNeedsDealloc.has_value() && *cstNeedsDealloc != false) { + auto insPt = builder.saveInsertionPoint(); + createReductionCleanupRegion(builder, loc, reductionDecl); + builder.restoreInsertionPoint(insPt); + } // Put the temporary inside of a box: hlfir::Entity box = hlfir::genVariableBox(loc, builder, temp); @@ -462,7 +528,7 @@ mlir::omp::DeclareReductionOp ReductionProcessor::createDeclareReduction( builder.setInsertionPointToEnd(&decl.getInitializerRegion().back()); mlir::Value init = - createReductionInitRegion(builder, loc, redId, type, isByRef); + createReductionInitRegion(builder, loc, decl, redId, type, isByRef); builder.create(loc, init); builder.createBlock(&decl.getReductionRegion(), diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array.f90 b/flang/test/Lower/OpenMP/parallel-reduction-array.f90 index 56dcabbb75c3..26c9d4f08509 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-array.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-array.f90 @@ -15,13 +15,15 @@ end program ! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_box_3xi32 : !fir.ref>> init { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): -! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.array<3xi32> {bindc_name = ".tmp"} ! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_0]] : !fir.ref>> ! CHECK: %[[VAL_4:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<3xi32> {bindc_name = ".tmp", uniq_name = ""} +! CHECK: %[[TRUE:.*]] = arith.constant true +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, +!fir.shape<1>) -> (!fir.heap>, !fir.heap>) +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> @@ -43,6 +45,18 @@ end program ! CHECK: fir.store %[[VAL_13]] to %[[VAL_9]] : !fir.ref ! CHECK: } ! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL: func.func @_QQmain() diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 b/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 index 94bff410a2f0..bed04401248b 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 @@ -15,13 +15,15 @@ end program ! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_box_3xi32 : !fir.ref>> init { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): -! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.array<3xi32> {bindc_name = ".tmp"} ! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_0]] : !fir.ref>> ! CHECK: %[[VAL_4:.*]] = arith.constant 3 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<3xi32> +! CHECK: %[[TRUE:.*]] = arith.constant true +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, +!fir.shape<1>) -> (!fir.heap>, !fir.heap>) +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> @@ -43,6 +45,18 @@ end program ! CHECK: fir.store %[[VAL_13]] to %[[VAL_9]] : !fir.ref ! CHECK: } ! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL: func.func @_QQmain() attributes {fir.bindc_name = "reduce"} { diff --git a/flang/test/Lower/OpenMP/parallel-reduction3.f90 b/flang/test/Lower/OpenMP/parallel-reduction3.f90 index b25759713e31..ce6bd17265dd 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction3.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction3.f90 @@ -1,15 +1,6 @@ -! NOTE: Assertions have been autogenerated by utils/generate-test-checks.py - -! The script is designed to make adding checks to -! a test case fast, it is *not* designed to be authoritative -! about what constitutes a good test! The CHECK should be -! minimized and named to reflect the test intent. - ! RUN: bbc -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s ! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - - ! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_box_Uxi32 : !fir.ref>> init { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): ! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i32 @@ -17,14 +8,14 @@ ! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_4:.*]]:3 = fir.box_dims %[[VAL_2]], %[[VAL_3]] : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp"} -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_6:.*]] = fir.allocmem !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp", uniq_name = ""} +! CHECK: %[[TRUE:.*]] = arith.constant true +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.box>, !fir.heap>) ! CHECK: hlfir.assign %[[VAL_1]] to %[[VAL_7]]#0 : i32, !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_7]]#0 to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) - -! CHECK-LABEL: } combiner { +! CHECK: } combiner { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>, %[[VAL_1:.*]]: !fir.ref>>): ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref>> ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]] : !fir.ref>> @@ -41,6 +32,18 @@ ! CHECK: fir.store %[[VAL_13]] to %[[VAL_9]] : !fir.ref ! CHECK: } ! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL: func.func @_QPs( @@ -122,4 +125,4 @@ subroutine s(x) !$omp end parallel do if (c(1) /= 5050) stop 1 -end subroutine s \ No newline at end of file +end subroutine s diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 index a1f339faea5c..8f83a30c9fe7 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 @@ -29,8 +29,9 @@ end program ! CHECK: %[[VAL_3:.*]] = arith.constant 0 : index ! CHECK: %[[VAL_4:.*]]:3 = fir.box_dims %[[VAL_2]], %[[VAL_3]] : (!fir.box>, index) -> (index, index, index) ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]] = fir.alloca !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp"} -! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.ref>, !fir.shape<1>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_6:.*]] = fir.allocmem !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp", uniq_name = ""} +! CHECK: %[[TRUE:.*]] = arith.constant true +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.box>, !fir.heap>) ! CHECK: hlfir.assign %[[VAL_1]] to %[[VAL_7]]#0 : f64, !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_7]]#0 to %[[VAL_8]] : !fir.ref>> @@ -53,6 +54,18 @@ end program ! CHECK: fir.store %[[VAL_13]] to %[[VAL_9]] : !fir.ref ! CHECK: } ! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL: func.func private @_QFPreduce( diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 index a898204c881d..a08bca9eb283 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 @@ -16,13 +16,14 @@ end program ! CHECK-LABEL omp.declare_reduction @add_reduction_byref_box_2xi32 : !fir.ref>> init { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): -! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.array<2xi32> {bindc_name = ".tmp"} ! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_0]] : !fir.ref>> ! CHECK: %[[VAL_4:.*]] = arith.constant 2 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<2xi32> {bindc_name = ".tmp", uniq_name = ""} +! CHECK: %[[TRUE:.*]] = arith.constant true +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.heap>, !fir.heap>) +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> @@ -45,6 +46,18 @@ end program ! CHECK: fir.store %[[VAL_13]] to %[[VAL_9]] : !fir.ref ! CHECK: } ! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL func.func @_QQmain() attributes {fir.bindc_name = "reduce"} { diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 index f3745c846091..045208d6f7ff 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 @@ -16,19 +16,20 @@ end program ! CHECK-LABEL omp.declare_reduction @add_reduction_byref_box_2xi32 : !fir.ref>> init { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): -! CHECK: %[[VAL_1:.*]] = fir.alloca !fir.array<2xi32> {bindc_name = ".tmp"} ! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_0]] : !fir.ref>> ! CHECK: %[[VAL_4:.*]] = arith.constant 2 : index ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<2xi32> {bindc_name = ".tmp", uniq_name = ""} +! CHECK: %[[TRUE:.*]] = arith.constant true +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.heap>, !fir.heap>) +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: %[[VAL_8:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) -! CHECK-LABEL } combiner { +! CHECK: } combiner { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>, %[[VAL_1:.*]]: !fir.ref>>): ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref>> ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]] : !fir.ref>> @@ -45,6 +46,18 @@ end program ! CHECK: fir.store %[[VAL_13]] to %[[VAL_9]] : !fir.ref ! CHECK: } ! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield ! CHECK: } ! CHECK-LABEL: func.func @_QQmain() attributes {fir.bindc_name = "reduce"} { -- GitLab From b800a9352330a5b3db91d43f2cc6a0ddeda03aa6 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 10:36:02 +0100 Subject: [PATCH 509/695] Fix MSVC "not all control paths return a value" warning. NFC. --- llvm/lib/IR/AsmWriter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 609de920ba7d..941f6a7a7d82 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -3313,7 +3313,7 @@ static const char *getImportTypeName(GlobalValueSummary::ImportKind IK) { case GlobalValueSummary::Declaration: return "declaration"; } - assert(false && "invalid import kind"); + llvm_unreachable("invalid import kind"); } void AssemblyWriter::printFunctionSummary(const FunctionSummary *FS) { -- GitLab From 759422c6df2dfe42d01bb64b42f43ab57db6e59e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 10:42:49 +0100 Subject: [PATCH 510/695] [DAG] visitEXTRACT_SUBVECTOR - pull out repeated SDLoc. NFC. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8fe074666a3d..95c1cde0b934 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -24433,6 +24433,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { EVT NVT = N->getValueType(0); SDValue V = N->getOperand(0); uint64_t ExtIdx = N->getConstantOperandVal(1); + SDLoc DL(N); // Extract from UNDEF is UNDEF. if (V.isUndef()) @@ -24448,7 +24449,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { if (TLI.isExtractSubvectorCheap(NVT, V.getOperand(0).getValueType(), V.getConstantOperandVal(1)) && TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NVT)) { - return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, V.getOperand(0), + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, V.getOperand(0), V.getOperand(1)); } } @@ -24457,7 +24458,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { if (V.getOpcode() == ISD::SPLAT_VECTOR) if (DAG.isConstantValueOfAnyType(V.getOperand(0)) || V.hasOneUse()) if (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, NVT)) - return DAG.getSplatVector(NVT, SDLoc(N), V.getOperand(0)); + return DAG.getSplatVector(NVT, DL, V.getOperand(0)); // Try to move vector bitcast after extract_subv by scaling extraction index: // extract_subv (bitcast X), Index --> bitcast (extract_subv X, Index') @@ -24471,10 +24472,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { if ((SrcNumElts % DestNumElts) == 0) { unsigned SrcDestRatio = SrcNumElts / DestNumElts; ElementCount NewExtEC = NVT.getVectorElementCount() * SrcDestRatio; - EVT NewExtVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), - NewExtEC); + EVT NewExtVT = + EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(), NewExtEC); if (TLI.isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, NewExtVT)) { - SDLoc DL(N); SDValue NewIndex = DAG.getVectorIdxConstant(ExtIdx * SrcDestRatio, DL); SDValue NewExtract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewExtVT, V.getOperand(0), NewIndex); @@ -24488,7 +24488,6 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { NVT.getVectorElementCount().divideCoefficientBy(DestSrcRatio); EVT ScalarVT = SrcVT.getScalarType(); if ((ExtIdx % DestSrcRatio) == 0) { - SDLoc DL(N); unsigned IndexValScaled = ExtIdx / DestSrcRatio; EVT NewExtVT = EVT::getVectorVT(*DAG.getContext(), ScalarVT, NewExtEC); @@ -24536,7 +24535,6 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { // v2i8 extract_subvec v8i8 Y, 6 if (NVT.isFixedLengthVector() && ConcatSrcVT.isFixedLengthVector() && ConcatSrcNumElts % ExtNumElts == 0) { - SDLoc DL(N); unsigned NewExtIdx = ExtIdx - ConcatOpIdx * ConcatSrcNumElts; assert(NewExtIdx + ExtNumElts <= ConcatSrcNumElts && "Trying to extract from >1 concat operand?"); @@ -24575,13 +24573,13 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { if (NumElems == 1) { SDValue Src = V->getOperand(IdxVal); if (EltVT != Src.getValueType()) - Src = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Src); + Src = DAG.getNode(ISD::TRUNCATE, DL, EltVT, Src); return DAG.getBitcast(NVT, Src); } // Extract the pieces from the original build_vector. - SDValue BuildVec = DAG.getBuildVector(ExtractVT, SDLoc(N), - V->ops().slice(IdxVal, NumElems)); + SDValue BuildVec = + DAG.getBuildVector(ExtractVT, DL, V->ops().slice(IdxVal, NumElems)); return DAG.getBitcast(NVT, BuildVec); } } @@ -24608,7 +24606,7 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode *N) { return DAG.getBitcast(NVT, V.getOperand(1)); } return DAG.getNode( - ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, + ISD::EXTRACT_SUBVECTOR, DL, NVT, DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)), N->getOperand(1)); } -- GitLab From cca30dfb5935e05837e37cced4407a63393c6642 Mon Sep 17 00:00:00 2001 From: nikitalita Date: Thu, 11 Apr 2024 03:08:38 -0700 Subject: [PATCH 511/695] [DebugInfo][ObjectYAML] Remove duplicate "Flags" field from LabelSym (#88194) There was a duplicate flags field mistakenly left in LabelSym. [LabelSym only has one flags field](https://github.com/microsoft/microsoft-pdb/blob/805655a28bd8198004be2ac27e6e0290121a5e89/include/cvinfo.h#L3806) --- llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp b/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp index 64e1a58aa71a..e1d2700623ec 100644 --- a/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp +++ b/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp @@ -467,7 +467,6 @@ template <> void SymbolRecordImpl::map(IO &IO) { IO.mapOptional("Offset", Symbol.CodeOffset, 0U); IO.mapOptional("Segment", Symbol.Segment, uint16_t(0)); IO.mapRequired("Flags", Symbol.Flags); - IO.mapRequired("Flags", Symbol.Flags); IO.mapRequired("DisplayName", Symbol.Name); } -- GitLab From b60974dc9e5d98054f5a3a0dac7eab70e38bd416 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 11:12:39 +0100 Subject: [PATCH 512/695] [VectorCombine][X86] Extend bitcast(shuffle(x,y)) test coverage As discussed on #87510 the intention is only to fold bitcast(shuffle(x,y)) -> shuffle(bitcast(x),bitcast(y)) if we won't actually increase the number of bitcasts (i.e. x or y is already bitcasted from the correct type). --- .../Transforms/VectorCombine/X86/shuffle.ll | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll index d1484fd5ab33..5020d37f86f5 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll @@ -121,6 +121,48 @@ define <16 x i8> @bitcast_shuf_uses(<4 x i32> %v) { ret <16 x i8> %r } +; shuffle of 2 operands removes bitcasts + +define <4 x i64> @bitcast_shuf_remove_bitcasts(<2 x i64> %a0, <2 x i64> %a1) { +; CHECK-LABEL: @bitcast_shuf_remove_bitcasts( +; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <4 x i32> +; CHECK-NEXT: ret <4 x i64> [[R]] +; + %bc0 = bitcast <2 x i64> %a0 to <4 x i32> + %bc1 = bitcast <2 x i64> %a1 to <4 x i32> + %shuf = shufflevector <4 x i32> %bc0, <4 x i32> %bc1, <8 x i32> + %r = bitcast <8 x i32> %shuf to <4 x i64> + ret <4 x i64> %r +} + +; shuffle of 2 operands must reduce bitcasts + +define <8 x i32> @bitcast_shuf_one_bitcast(<4 x i32> %a0, <2 x i64> %a1) { +; CHECK-LABEL: @bitcast_shuf_one_bitcast( +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[A1:%.*]] to <4 x i32> +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> [[TMP1]], <8 x i32> +; CHECK-NEXT: ret <8 x i32> [[R]] +; + %bc0 = bitcast <4 x i32> %a0 to <2 x i64> + %shuf = shufflevector <2 x i64> %bc0, <2 x i64> %a1, <4 x i32> + %r = bitcast <4 x i64> %shuf to <8 x i32> + ret <8 x i32> %r +} + +; TODO - Negative test - shuffle of 2 operands must not increase bitcasts + +define <8 x i32> @bitcast_shuf_too_many_bitcasts(<2 x i64> %a0, <2 x i64> %a1) { +; CHECK-LABEL: @bitcast_shuf_too_many_bitcasts( +; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[A0:%.*]] to <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[A1:%.*]] to <4 x i32> +; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <8 x i32> +; CHECK-NEXT: ret <8 x i32> [[R]] +; + %shuf = shufflevector <2 x i64> %a0, <2 x i64> %a1, <4 x i32> + %r = bitcast <4 x i64> %shuf to <8 x i32> + ret <8 x i32> %r +} + define <2 x i64> @PR35454_1(<2 x i64> %v) { ; SSE-LABEL: @PR35454_1( ; SSE-NEXT: [[BC:%.*]] = bitcast <2 x i64> [[V:%.*]] to <4 x i32> -- GitLab From a8b461603b3fab3b229ea6552433cb359c30350c Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Thu, 11 Apr 2024 10:25:53 +0000 Subject: [PATCH 513/695] [mlir] Apply ClangTidy BugProne fix forwarding reference passed to std::move(), which may unexpectedly cause lvalues to be moved; use std::forward() instead. --- mlir/lib/Transforms/Utils/DialectConversion.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Transforms/Utils/DialectConversion.cpp b/mlir/lib/Transforms/Utils/DialectConversion.cpp index 8671c1008902..f4e34a03d3d0 100644 --- a/mlir/lib/Transforms/Utils/DialectConversion.cpp +++ b/mlir/lib/Transforms/Utils/DialectConversion.cpp @@ -757,7 +757,7 @@ private: /// rewrite type and operation among the given rewrites. template static bool hasRewrite(R &&rewrites, Operation *op) { - return any_of(std::move(rewrites), [&](auto &rewrite) { + return any_of(std::forward(rewrites), [&](auto &rewrite) { auto *rewriteTy = dyn_cast(rewrite.get()); return rewriteTy && rewriteTy->getOperation() == op; }); -- GitLab From 962534c4b490239269bb2e11d036596826539046 Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Thu, 11 Apr 2024 10:28:10 +0000 Subject: [PATCH 514/695] [mlir] Apply ClangTidy BugProne patch This time for real. --- mlir/lib/Transforms/Utils/DialectConversion.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Transforms/Utils/DialectConversion.cpp b/mlir/lib/Transforms/Utils/DialectConversion.cpp index f4e34a03d3d0..d85938847c77 100644 --- a/mlir/lib/Transforms/Utils/DialectConversion.cpp +++ b/mlir/lib/Transforms/Utils/DialectConversion.cpp @@ -757,7 +757,7 @@ private: /// rewrite type and operation among the given rewrites. template static bool hasRewrite(R &&rewrites, Operation *op) { - return any_of(std::forward(rewrites), [&](auto &rewrite) { + return any_of(std::forward(rewrites), [&](auto &rewrite) { auto *rewriteTy = dyn_cast(rewrite.get()); return rewriteTy && rewriteTy->getOperation() == op; }); -- GitLab From 364963a0a3935ced1acb2e959ecd08aef39405ef Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Thu, 11 Apr 2024 06:29:51 -0400 Subject: [PATCH 515/695] [BOLT][NFC] Do not assume text section name in more places (#88303) Fixes a couple more places where ".text" is presumed for the main code section name. --- bolt/lib/Rewrite/RewriteInstance.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index 0c8ee0d41723..1f778d030f7a 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -556,7 +556,7 @@ Error RewriteInstance::discoverStorage() { if (Error E = SectionNameOrErr.takeError()) return E; StringRef SectionName = SectionNameOrErr.get(); - if (SectionName == ".text") { + if (SectionName == BC->getMainCodeSectionName()) { BC->OldTextSectionAddress = Section.getAddress(); BC->OldTextSectionSize = Section.getSize(); @@ -1864,7 +1864,8 @@ Error RewriteInstance::readSpecialSections() { "Use -update-debug-sections to keep it.\n"; } - HasTextRelocations = (bool)BC->getUniqueSectionByName(".rela.text"); + HasTextRelocations = (bool)BC->getUniqueSectionByName( + ".rela" + std::string(BC->getMainCodeSectionName())); HasSymbolTable = (bool)BC->getUniqueSectionByName(".symtab"); EHFrameSection = BC->getUniqueSectionByName(".eh_frame"); BuildIDSection = BC->getUniqueSectionByName(".note.gnu.build-id"); @@ -3441,7 +3442,8 @@ void RewriteInstance::emitAndLink() { ErrorOr TextSection = BC->getUniqueSectionByName(BC->getMainCodeSectionName()); if (BC->HasRelocations && TextSection) - BC->renameSection(*TextSection, getOrgSecPrefix() + ".text"); + BC->renameSection(*TextSection, + getOrgSecPrefix() + BC->getMainCodeSectionName()); ////////////////////////////////////////////////////////////////////////////// // Assign addresses to new sections. -- GitLab From e2d482395992d725663543d297f5ab3cc5918fcc Mon Sep 17 00:00:00 2001 From: Nathan Sidwell Date: Thu, 11 Apr 2024 06:35:28 -0400 Subject: [PATCH 516/695] [BOLT][NFC] Make RepRet X86-specific (#88286) Bolt's RepRet pass is x86-specific, no need to add it for non-x86 targets. --- bolt/lib/Rewrite/BinaryPassManager.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/bolt/lib/Rewrite/BinaryPassManager.cpp b/bolt/lib/Rewrite/BinaryPassManager.cpp index 6c26bb795726..be4888ccfa56 100644 --- a/bolt/lib/Rewrite/BinaryPassManager.cpp +++ b/bolt/lib/Rewrite/BinaryPassManager.cpp @@ -377,8 +377,9 @@ Error BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) { Manager.registerPass(std::make_unique(PrintNormalized)); - Manager.registerPass(std::make_unique(NeverPrint), - opts::StripRepRet); + if (BC.isX86()) + Manager.registerPass(std::make_unique(NeverPrint), + opts::StripRepRet); Manager.registerPass(std::make_unique(PrintICF), opts::ICF); -- GitLab From a403ad9336a24c459ee79d2cb7675c4b1f32bfd9 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 11:26:41 +0100 Subject: [PATCH 517/695] [VectorCombine] foldBitcastShuffle - limit bitcast(shuffle(x,y)) -> shuffle(bitcast(x),bitcast(y)) Only fold bitcast(shuffle(x,y)) -> shuffle(bitcast(x),bitcast(y)) if we won't actually increase the number of bitcasts (i.e. x or y is already bitcasted from the correct type). --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 13 ++++++++++++- llvm/test/Transforms/VectorCombine/X86/shuffle.ll | 7 +++---- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 633b46e2dc8b..2f9767538e6c 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -713,6 +713,18 @@ bool VectorCombine::foldBitcastShuffle(Instruction &I) { if (SrcTy->getPrimitiveSizeInBits() % DestEltSize != 0) return false; + bool IsUnary = isa(V1); + + // For binary shuffles, only fold bitcast(shuffle(X,Y)) + // if it won't increase the number of bitcasts. + if (!IsUnary) { + auto *BCTy0 = dyn_cast(peekThroughBitcasts(V0)->getType()); + auto *BCTy1 = dyn_cast(peekThroughBitcasts(V1)->getType()); + if (!(BCTy0 && BCTy0->getElementType() == DestTy->getElementType()) && + !(BCTy1 && BCTy1->getElementType() == DestTy->getElementType())) + return false; + } + SmallVector NewMask; if (DestEltSize <= SrcEltSize) { // The bitcast is from wide to narrow/equal elements. The shuffle mask can @@ -736,7 +748,6 @@ bool VectorCombine::foldBitcastShuffle(Instruction &I) { FixedVectorType::get(DestTy->getScalarType(), NumSrcElts); auto *OldShuffleTy = FixedVectorType::get(SrcTy->getScalarType(), Mask.size()); - bool IsUnary = isa(V1); unsigned NumOps = IsUnary ? 1 : 2; // The new shuffle must not cost more than the old shuffle. diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll index 5020d37f86f5..3d47f373ab77 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll @@ -149,13 +149,12 @@ define <8 x i32> @bitcast_shuf_one_bitcast(<4 x i32> %a0, <2 x i64> %a1) { ret <8 x i32> %r } -; TODO - Negative test - shuffle of 2 operands must not increase bitcasts +; Negative test - shuffle of 2 operands must not increase bitcasts define <8 x i32> @bitcast_shuf_too_many_bitcasts(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: @bitcast_shuf_too_many_bitcasts( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[A0:%.*]] to <4 x i32> -; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[A1:%.*]] to <4 x i32> -; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <8 x i32> +; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = bitcast <4 x i64> [[SHUF]] to <8 x i32> ; CHECK-NEXT: ret <8 x i32> [[R]] ; %shuf = shufflevector <2 x i64> %a0, <2 x i64> %a1, <4 x i32> -- GitLab From 717d3f3974f43d90c1b8829a4077bbc2a2413c83 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 11:42:57 +0100 Subject: [PATCH 518/695] [VectorCombine] foldShuffleOfCastops - add initial shuffle(bitcast(x),bitcast(y)) -> bitcast(shuffle(x,y)) support Just handle cases where the bitcast src/dst element counts are the same (future patches will add shuffle mask scaling) --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 7 +++---- llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll | 7 +++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 2f9767538e6c..b74fdf27d213 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1459,7 +1459,7 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { return false; Instruction::CastOps Opcode = C0->getOpcode(); - if (Opcode == Instruction::BitCast || C0->getSrcTy() != C1->getSrcTy()) + if (C0->getSrcTy() != C1->getSrcTy()) return false; // Handle shuffle(zext_nneg(x), sext(y)) -> sext(shuffle(x,y)) folds. @@ -1473,10 +1473,9 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { auto *ShuffleDstTy = dyn_cast(I.getType()); auto *CastDstTy = dyn_cast(C0->getDestTy()); auto *CastSrcTy = dyn_cast(C0->getSrcTy()); - if (!ShuffleDstTy || !CastDstTy || !CastSrcTy) + if (!ShuffleDstTy || !CastDstTy || !CastSrcTy || + CastDstTy->getElementCount() != CastSrcTy->getElementCount()) return false; - assert(CastDstTy->getElementCount() == CastSrcTy->getElementCount() && - "Unexpected src/dst element counts"); auto *NewShuffleDstTy = FixedVectorType::get(CastSrcTy->getScalarType(), Mask.size()); diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll index 60c6ff97c58b..97fceacd8275 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll @@ -165,13 +165,12 @@ define <8 x double> @interleave_fpext_v4f32_v8f64(<4 x float> %a0, <4 x float> % ret <8 x double> %r } -; TODO - bitcasts (same element count) +; bitcasts (same element count) define <8 x float> @concat_bitcast_v4i32_v8f32(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: @concat_bitcast_v4i32_v8f32( -; CHECK-NEXT: [[X0:%.*]] = bitcast <4 x i32> [[A0:%.*]] to <4 x float> -; CHECK-NEXT: [[X1:%.*]] = bitcast <4 x i32> [[A1:%.*]] to <4 x float> -; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X0]], <4 x float> [[X1]], <8 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]], <8 x i32> +; CHECK-NEXT: [[R:%.*]] = bitcast <8 x i32> [[TMP1]] to <8 x float> ; CHECK-NEXT: ret <8 x float> [[R]] ; %x0 = bitcast <4 x i32> %a0 to <4 x float> -- GitLab From 9d9bb7b1b6e96dc833133dacf1e2c7d9792e640e Mon Sep 17 00:00:00 2001 From: Johannes Reifferscheid Date: Thu, 11 Apr 2024 12:57:46 +0200 Subject: [PATCH 519/695] Fix complex abs corner cases. (#88373) The current implementation fails for very small and very large values. For example, (0, -inf) should return inf, but it returns -inf. This ports the logic used in XLA. Tested with XLA's exhaustive_binary_test_f32_f64. --- .../ComplexToStandard/ComplexToStandard.cpp | 54 +-- .../convert-to-standard.mlir | 348 +++++++----------- .../ComplexToStandard/full-conversion.mlir | 34 +- 3 files changed, 162 insertions(+), 274 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index a6fcf6a758c0..462036e51a1f 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -26,7 +26,7 @@ namespace mlir { using namespace mlir; namespace { -// The algorithm is listed in https://dl.acm.org/doi/pdf/10.1145/363717.363780. + struct AbsOpConversion : public OpConversionPattern { using OpConversionPattern::OpConversionPattern; @@ -35,49 +35,27 @@ struct AbsOpConversion : public OpConversionPattern { ConversionPatternRewriter &rewriter) const override { mlir::ImplicitLocOpBuilder b(op.getLoc(), rewriter); - arith::FastMathFlagsAttr fmf = op.getFastMathFlagsAttr(); + arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); Type elementType = op.getType(); - Value arg = adaptor.getComplex(); - - Value zero = - b.create(elementType, b.getZeroAttr(elementType)); Value one = b.create(elementType, b.getFloatAttr(elementType, 1.0)); - Value real = b.create(elementType, arg); - Value imag = b.create(elementType, arg); - - Value realIsZero = - b.create(arith::CmpFPredicate::OEQ, real, zero); - Value imagIsZero = - b.create(arith::CmpFPredicate::OEQ, imag, zero); + Value real = b.create(adaptor.getComplex()); + Value imag = b.create(adaptor.getComplex()); + Value absReal = b.create(real, fmf); + Value absImag = b.create(imag, fmf); - // Real > Imag - Value imagDivReal = b.create(imag, real, fmf.getValue()); - Value imagSq = - b.create(imagDivReal, imagDivReal, fmf.getValue()); - Value imagSqPlusOne = b.create(imagSq, one, fmf.getValue()); - Value imagSqrt = b.create(imagSqPlusOne, fmf.getValue()); - Value realAbs = b.create(real, fmf.getValue()); - Value absImag = b.create(imagSqrt, realAbs, fmf.getValue()); - - // Real <= Imag - Value realDivImag = b.create(real, imag, fmf.getValue()); - Value realSq = - b.create(realDivImag, realDivImag, fmf.getValue()); - Value realSqPlusOne = b.create(realSq, one, fmf.getValue()); - Value realSqrt = b.create(realSqPlusOne, fmf.getValue()); - Value imagAbs = b.create(imag, fmf.getValue()); - Value absReal = b.create(realSqrt, imagAbs, fmf.getValue()); - - rewriter.replaceOpWithNewOp( - op, realIsZero, imagAbs, - b.create( - imagIsZero, realAbs, - b.create( - b.create(arith::CmpFPredicate::OGT, real, imag), - absImag, absReal))); + Value max = b.create(absReal, absImag, fmf); + Value min = b.create(absReal, absImag, fmf); + Value ratio = b.create(min, max, fmf); + Value ratioSq = b.create(ratio, ratio, fmf); + Value ratioSqPlusOne = b.create(ratioSq, one, fmf); + Value sqrt = b.create(ratioSqPlusOne, fmf); + Value result = b.create(max, sqrt, fmf); + Value isNaN = + b.create(arith::CmpFPredicate::UNO, result, result, fmf); + rewriter.replaceOpWithNewOp(op, isNaN, min, result); return success(); } diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index 46dba04a88aa..a1de61d10bb2 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -8,29 +8,21 @@ func.func @complex_abs(%arg: complex) -> f32 { return %abs : f32 } -// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 // CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 -// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG]], %[[REAL]] : f32 -// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] : f32 -// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] : f32 -// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL]] : f32 -// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] : f32 -// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] : f32 -// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] : f32 -// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG]] : f32 -// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] : f32 -// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 -// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 -// CHECK: %[[ABS3:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 -// CHECK: return %[[ABS3]] : f32 +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: return %[[ABS]] : f32 // ----- @@ -258,29 +250,21 @@ func.func @complex_log(%arg: complex) -> complex { %log = complex.log %arg: complex return %log : complex } -// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 // CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 -// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG]], %[[REAL]] : f32 -// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] : f32 -// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] : f32 -// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL]] : f32 -// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] : f32 -// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] : f32 -// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] : f32 -// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG]] : f32 -// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] : f32 -// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 -// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 -// CHECK: %[[NORM:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 -// CHECK: %[[RESULT_REAL:.*]] = math.log %[[NORM]] : f32 +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] : f32 +// CHECK: %[[RESULT:.*]] = arith.mulf %[[MAX]], %[[SQRT]] : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[RESULT]], %[[RESULT]] : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[RESULT]] : f32 +// CHECK: %[[RESULT_REAL:.*]] = math.log %[[ABS]] : f32 // CHECK: %[[REAL2:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG2:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG2]], %[[REAL2]] : f32 @@ -509,30 +493,22 @@ func.func @complex_sign(%arg: complex) -> complex { // CHECK: %[[REAL_IS_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 // CHECK: %[[IMAG_IS_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 // CHECK: %[[IS_ZERO:.*]] = arith.andi %[[REAL_IS_ZERO]], %[[IMAG_IS_ZERO]] : i1 -// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 // CHECK: %[[REAL2:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG2:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL2]], %[[ZERO]] : f32 -// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG2]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG2]], %[[REAL2]] : f32 -// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] : f32 -// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] : f32 -// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL2]] : f32 -// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] : f32 -// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL2]], %[[IMAG2]] : f32 -// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] : f32 -// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] : f32 -// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG2]] : f32 -// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] : f32 -// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL2]], %[[IMAG2]] : f32 -// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 -// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 -// CHECK: %[[NORM:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 -// CHECK: %[[REAL_SIGN:.*]] = arith.divf %[[REAL]], %[[NORM]] : f32 -// CHECK: %[[IMAG_SIGN:.*]] = arith.divf %[[IMAG]], %[[NORM]] : f32 +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL2]] : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG2]] : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[REAL_SIGN:.*]] = arith.divf %[[REAL]], %[[ABS]] : f32 +// CHECK: %[[IMAG_SIGN:.*]] = arith.divf %[[IMAG]], %[[ABS]] : f32 // CHECK: %[[SIGN:.*]] = complex.create %[[REAL_SIGN]], %[[IMAG_SIGN]] : complex // CHECK: %[[RESULT:.*]] = arith.select %[[IS_ZERO]], %[[ARG]], %[[SIGN]] : complex // CHECK: return %[[RESULT]] : complex @@ -725,29 +701,21 @@ func.func @complex_sqrt(%arg: complex) -> complex { // CHECK: %[[VAR0:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[VAR1:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[VAR2:.*]] = math.absf %[[VAR0]] : f32 -// CHECK: %[[CST0:.*]] = arith.constant 0.000000e+00 : f32 -// CHECK: %[[CST1:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[VAR3:.*]] = complex.re %[[ARG]] : complex -// CHECK: %[[VAR4:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[VAR5:.*]] = arith.cmpf oeq, %[[VAR3]], %[[CST0]] : f32 -// CHECK: %[[VAR6:.*]] = arith.cmpf oeq, %[[VAR4]], %[[CST0]] : f32 -// CHECK: %[[VAR7:.*]] = arith.divf %[[VAR4]], %[[VAR3]] : f32 -// CHECK: %[[VAR8:.*]] = arith.mulf %[[VAR7]], %[[VAR7]] : f32 -// CHECK: %[[VAR9:.*]] = arith.addf %[[VAR8]], %[[CST1]] : f32 -// CHECK: %[[VAR10:.*]] = math.sqrt %[[VAR9]] : f32 -// CHECK: %[[VAR11:.*]] = math.absf %[[VAR3]] : f32 -// CHECK: %[[VAR12:.*]] = arith.mulf %[[VAR10]], %[[VAR11]] : f32 -// CHECK: %[[VAR13:.*]] = arith.divf %[[VAR3]], %[[VAR4]] : f32 -// CHECK: %[[VAR14:.*]] = arith.mulf %[[VAR13]], %[[VAR13]] : f32 -// CHECK: %[[VAR15:.*]] = arith.addf %[[VAR14]], %[[CST1]] : f32 -// CHECK: %[[VAR16:.*]] = math.sqrt %[[VAR15]] : f32 -// CHECK: %[[VAR17:.*]] = math.absf %[[VAR4]] : f32 -// CHECK: %[[VAR18:.*]] = arith.mulf %[[VAR16]], %[[VAR17]] : f32 -// CHECK: %[[VAR19:.*]] = arith.cmpf ogt, %[[VAR3]], %[[VAR4]] : f32 -// CHECK: %[[VAR20:.*]] = arith.select %[[VAR19]], %[[VAR12]], %[[VAR18]] : f32 -// CHECK: %[[VAR21:.*]] = arith.select %[[VAR6]], %[[VAR11]], %[[VAR20]] : f32 -// CHECK: %[[VAR22:.*]] = arith.select %[[VAR5]], %[[VAR17]], %[[VAR21]] : f32 -// CHECK: %[[VAR23:.*]] = arith.addf %[[VAR2]], %[[VAR22]] : f32 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex +// CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[VAR23:.*]] = arith.addf %[[VAR2]], %[[ABS]] : f32 // CHECK: %[[CST2:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[VAR24:.*]] = arith.mulf %[[VAR23]], %[[CST2]] : f32 // CHECK: %[[VAR25:.*]] = math.sqrt %[[VAR24]] : f32 @@ -821,29 +789,21 @@ func.func @complex_abs_with_fmf(%arg: complex) -> f32 { %abs = complex.abs %arg fastmath : complex return %abs : f32 } -// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 // CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 -// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG]], %[[REAL]] fastmath : f32 -// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] fastmath : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] fastmath : f32 -// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] fastmath : f32 -// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL]] fastmath : f32 -// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] fastmath : f32 -// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL]], %[[IMAG]] fastmath : f32 -// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] fastmath : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] fastmath : f32 -// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] fastmath : f32 -// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG]] fastmath : f32 -// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] fastmath : f32 -// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 -// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 -// CHECK: %[[ABS3:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 -// CHECK: return %[[ABS3]] : f32 +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] fastmath : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] fastmath : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] fastmath : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: return %[[ABS]] : f32 // ----- @@ -928,29 +888,21 @@ func.func @complex_log_with_fmf(%arg: complex) -> complex { %log = complex.log %arg fastmath : complex return %log : complex } -// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 // CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 -// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG]], %[[REAL]] fastmath : f32 -// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] fastmath : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] fastmath : f32 -// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] fastmath : f32 -// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL]] fastmath : f32 -// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] fastmath : f32 -// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL]], %[[IMAG]] fastmath : f32 -// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] fastmath : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] fastmath : f32 -// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] fastmath : f32 -// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG]] fastmath : f32 -// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] fastmath : f32 -// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 -// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 -// CHECK: %[[NORM:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 -// CHECK: %[[RESULT_REAL:.*]] = math.log %[[NORM]] fastmath : f32 +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] fastmath : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] fastmath : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] fastmath : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[RESULT_REAL:.*]] = math.log %[[ABS]] fastmath : f32 // CHECK: %[[REAL2:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG2:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[RESULT_IMAG:.*]] = math.atan2 %[[IMAG2]], %[[REAL2]] fastmath : f32 @@ -1318,29 +1270,21 @@ func.func @complex_atan2_with_fmf(%lhs: complex, // CHECK: %[[VAR187:.*]] = complex.re %[[VAR186]] : complex // CHECK: %[[VAR188:.*]] = complex.im %[[VAR186]] : complex // CHECK: %[[VAR189:.*]] = math.absf %[[VAR187]] fastmath : f32 -// CHECK: %[[CST_7:.*]] = arith.constant 0.000000e+00 : f32 -// CHECK: %[[CST_8:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[VAR190:.*]] = complex.re %[[VAR186]] : complex -// CHECK: %[[VAR191:.*]] = complex.im %[[VAR186]] : complex -// CHECK: %[[VAR192:.*]] = arith.cmpf oeq, %[[VAR190]], %[[CST_7]] : f32 -// CHECK: %[[VAR193:.*]] = arith.cmpf oeq, %[[VAR191]], %[[CST_7]] : f32 -// CHECK: %[[VAR194:.*]] = arith.divf %[[VAR191]], %[[VAR190]] fastmath : f32 -// CHECK: %[[VAR195:.*]] = arith.mulf %[[VAR194]], %[[VAR194]] fastmath : f32 -// CHECK: %[[VAR196:.*]] = arith.addf %[[VAR195]], %[[CST_8]] fastmath : f32 -// CHECK: %[[VAR197:.*]] = math.sqrt %[[VAR196]] fastmath : f32 -// CHECK: %[[VAR198:.*]] = math.absf %[[VAR190]] fastmath : f32 -// CHECK: %[[VAR199:.*]] = arith.mulf %[[VAR197]], %[[VAR198]] fastmath : f32 -// CHECK: %[[VAR200:.*]] = arith.divf %[[VAR190]], %[[VAR191]] fastmath : f32 -// CHECK: %[[VAR201:.*]] = arith.mulf %[[VAR200]], %[[VAR200]] fastmath : f32 -// CHECK: %[[VAR202:.*]] = arith.addf %[[VAR201]], %[[CST_8]] fastmath : f32 -// CHECK: %[[VAR203:.*]] = math.sqrt %[[VAR202]] fastmath : f32 -// CHECK: %[[VAR204:.*]] = math.absf %[[VAR191]] fastmath : f32 -// CHECK: %[[VAR205:.*]] = arith.mulf %[[VAR203]], %[[VAR204]] fastmath : f32 -// CHECK: %[[VAR206:.*]] = arith.cmpf ogt, %[[VAR190]], %[[VAR191]] : f32 -// CHECK: %[[VAR207:.*]] = arith.select %[[VAR206]], %[[VAR199]], %[[VAR205]] : f32 -// CHECK: %[[VAR208:.*]] = arith.select %[[VAR193]], %[[VAR198]], %[[VAR207]] : f32 -// CHECK: %[[VAR209:.*]] = arith.select %[[VAR192]], %[[VAR204]], %[[VAR208]] : f32 -// CHECK: %[[VAR210:.*]] = arith.addf %[[VAR189]], %[[VAR209]] fastmath : f32 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[REAL:.*]] = complex.re %[[VAR186]] : complex +// CHECK: %[[IMAG:.*]] = complex.im %[[VAR186]] : complex +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] fastmath : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] fastmath : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] fastmath : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[VAR210:.*]] = arith.addf %[[VAR189]], %[[ABS]] fastmath : f32 // CHECK: %[[CST_9:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[VAR211:.*]] = arith.mulf %[[VAR210]], %[[CST_9]] fastmath : f32 // CHECK: %[[VAR212:.*]] = math.sqrt %[[VAR211]] fastmath : f32 @@ -1556,29 +1500,21 @@ func.func @complex_atan2_with_fmf(%lhs: complex, // CHECK: %[[VAR413:.*]] = arith.select %[[VAR412]], %[[VAR408]], %[[VAR402]] : f32 // CHECK: %[[VAR414:.*]] = arith.select %[[VAR412]], %[[VAR409]], %[[VAR403]] : f32 // CHECK: %[[VAR415:.*]] = complex.create %[[VAR413]], %[[VAR414]] : complex -// CHECK: %[[CST_19:.*]] = arith.constant 0.000000e+00 : f32 -// CHECK: %[[CST_20:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[VAR416:.*]] = complex.re %[[VAR415]] : complex -// CHECK: %[[VAR417:.*]] = complex.im %[[VAR415]] : complex -// CHECK: %[[VAR418:.*]] = arith.cmpf oeq, %[[VAR416]], %[[CST_19]] : f32 -// CHECK: %[[VAR419:.*]] = arith.cmpf oeq, %[[VAR417]], %[[CST_19]] : f32 -// CHECK: %[[VAR420:.*]] = arith.divf %[[VAR417]], %[[VAR416]] fastmath : f32 -// CHECK: %[[VAR421:.*]] = arith.mulf %[[VAR420]], %[[VAR420]] fastmath : f32 -// CHECK: %[[VAR422:.*]] = arith.addf %[[VAR421]], %[[CST_20]] fastmath : f32 -// CHECK: %[[VAR423:.*]] = math.sqrt %[[VAR422]] fastmath : f32 -// CHECK: %[[VAR424:.*]] = math.absf %[[VAR416]] fastmath : f32 -// CHECK: %[[VAR425:.*]] = arith.mulf %[[VAR423]], %[[VAR424]] fastmath : f32 -// CHECK: %[[VAR426:.*]] = arith.divf %[[VAR416]], %[[VAR417]] fastmath : f32 -// CHECK: %[[VAR427:.*]] = arith.mulf %[[VAR426]], %[[VAR426]] fastmath : f32 -// CHECK: %[[VAR428:.*]] = arith.addf %[[VAR427]], %[[CST_20]] fastmath : f32 -// CHECK: %[[VAR429:.*]] = math.sqrt %[[VAR428]] fastmath : f32 -// CHECK: %[[VAR430:.*]] = math.absf %[[VAR417]] fastmath : f32 -// CHECK: %[[VAR431:.*]] = arith.mulf %[[VAR429]], %[[VAR430]] fastmath : f32 -// CHECK: %[[VAR432:.*]] = arith.cmpf ogt, %[[VAR416]], %[[VAR417]] : f32 -// CHECK: %[[VAR433:.*]] = arith.select %[[VAR432]], %[[VAR425]], %[[VAR431]] : f32 -// CHECK: %[[VAR434:.*]] = arith.select %[[VAR419]], %[[VAR424]], %[[VAR433]] : f32 -// CHECK: %[[VAR435:.*]] = arith.select %[[VAR418]], %[[VAR430]], %[[VAR434]] : f32 -// CHECK: %[[VAR436:.*]] = math.log %[[VAR435]] fastmath : f32 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[REAL:.*]] = complex.re %[[VAR415]] : complex +// CHECK: %[[IMAG:.*]] = complex.im %[[VAR415]] : complex +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] fastmath : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] fastmath : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] fastmath : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[VAR436:.*]] = math.log %[[ABS]] fastmath : f32 // CHECK: %[[VAR437:.*]] = complex.re %[[VAR415]] : complex // CHECK: %[[VAR438:.*]] = complex.im %[[VAR415]] : complex // CHECK: %[[VAR439:.*]] = math.atan2 %[[VAR438]], %[[VAR437]] fastmath : f32 @@ -1805,29 +1741,21 @@ func.func @complex_sqrt_with_fmf(%arg: complex) -> complex { // CHECK: %[[VAR0:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[VAR1:.*]] = complex.im %[[ARG]] : complex // CHECK: %[[VAR2:.*]] = math.absf %[[VAR0]] fastmath : f32 -// CHECK: %[[CST0:.*]] = arith.constant 0.000000e+00 : f32 -// CHECK: %[[CST1:.*]] = arith.constant 1.000000e+00 : f32 -// CHECK: %[[VAR3:.*]] = complex.re %[[ARG]] : complex -// CHECK: %[[VAR4:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[VAR5:.*]] = arith.cmpf oeq, %[[VAR3]], %[[CST0]] : f32 -// CHECK: %[[VAR6:.*]] = arith.cmpf oeq, %[[VAR4]], %[[CST0]] : f32 -// CHECK: %[[VAR7:.*]] = arith.divf %[[VAR4]], %[[VAR3]] fastmath : f32 -// CHECK: %[[VAR8:.*]] = arith.mulf %[[VAR7]], %[[VAR7]] fastmath : f32 -// CHECK: %[[VAR9:.*]] = arith.addf %[[VAR8]], %[[CST1]] fastmath : f32 -// CHECK: %[[VAR10:.*]] = math.sqrt %[[VAR9]] fastmath : f32 -// CHECK: %[[VAR11:.*]] = math.absf %[[VAR3]] fastmath : f32 -// CHECK: %[[VAR12:.*]] = arith.mulf %[[VAR10]], %[[VAR11]] fastmath : f32 -// CHECK: %[[VAR13:.*]] = arith.divf %[[VAR3]], %[[VAR4]] fastmath : f32 -// CHECK: %[[VAR14:.*]] = arith.mulf %[[VAR13]], %[[VAR13]] fastmath : f32 -// CHECK: %[[VAR15:.*]] = arith.addf %[[VAR14]], %[[CST1]] fastmath : f32 -// CHECK: %[[VAR16:.*]] = math.sqrt %[[VAR15]] fastmath : f32 -// CHECK: %[[VAR17:.*]] = math.absf %[[VAR4]] fastmath : f32 -// CHECK: %[[VAR18:.*]] = arith.mulf %[[VAR16]], %[[VAR17]] fastmath : f32 -// CHECK: %[[VAR19:.*]] = arith.cmpf ogt, %[[VAR3]], %[[VAR4]] : f32 -// CHECK: %[[VAR20:.*]] = arith.select %[[VAR19]], %[[VAR12]], %[[VAR18]] : f32 -// CHECK: %[[VAR21:.*]] = arith.select %[[VAR6]], %[[VAR11]], %[[VAR20]] : f32 -// CHECK: %[[VAR22:.*]] = arith.select %[[VAR5]], %[[VAR17]], %[[VAR21]] : f32 -// CHECK: %[[VAR23:.*]] = arith.addf %[[VAR2]], %[[VAR22]] fastmath : f32 +// CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 +// CHECK: %[[REAL:.*]] = complex.re %[[ARG]] : complex +// CHECK: %[[IMAG:.*]] = complex.im %[[ARG]] : complex +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] fastmath : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] fastmath : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] fastmath : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[VAR23:.*]] = arith.addf %[[VAR2]], %[[ABS]] fastmath : f32 // CHECK: %[[CST2:.*]] = arith.constant 5.000000e-01 : f32 // CHECK: %[[VAR24:.*]] = arith.mulf %[[VAR23]], %[[CST2]] fastmath : f32 // CHECK: %[[VAR25:.*]] = math.sqrt %[[VAR24]] fastmath : f32 @@ -1910,30 +1838,22 @@ func.func @complex_sign_with_fmf(%arg: complex) -> complex { // CHECK: %[[REAL_IS_ZERO:.*]] = arith.cmpf oeq, %[[REAL]], %[[ZERO]] : f32 // CHECK: %[[IMAG_IS_ZERO:.*]] = arith.cmpf oeq, %[[IMAG]], %[[ZERO]] : f32 // CHECK: %[[IS_ZERO:.*]] = arith.andi %[[REAL_IS_ZERO]], %[[IMAG_IS_ZERO]] : i1 -// CHECK: %[[ZERO:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[ONE:.*]] = arith.constant 1.000000e+00 : f32 // CHECK: %[[REAL2:.*]] = complex.re %[[ARG]] : complex // CHECK: %[[IMAG2:.*]] = complex.im %[[ARG]] : complex -// CHECK: %[[IS_REAL_ZERO:.*]] = arith.cmpf oeq, %[[REAL2]], %[[ZERO]] : f32 -// CHECK: %[[IS_IMAG_ZERO:.*]] = arith.cmpf oeq, %[[IMAG2]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = arith.divf %[[IMAG2]], %[[REAL2]] fastmath : f32 -// CHECK: %[[IMAG_SQ:.*]] = arith.mulf %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] fastmath : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = arith.addf %[[IMAG_SQ]], %[[ONE]] fastmath : f32 -// CHECK: %[[IMAG_SQRT:.*]] = math.sqrt %[[IMAG_SQ_PLUS_ONE]] fastmath : f32 -// CHECK: %[[REAL_ABS:.*]] = math.absf %[[REAL2]] fastmath : f32 -// CHECK: %[[ABS_IMAG:.*]] = arith.mulf %[[IMAG_SQRT]], %[[REAL_ABS]] fastmath : f32 -// CHECK: %[[REAL_DIV_IMAG:.*]] = arith.divf %[[REAL2]], %[[IMAG2]] fastmath : f32 -// CHECK: %[[REAL_SQ:.*]] = arith.mulf %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] fastmath : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = arith.addf %[[REAL_SQ]], %[[ONE]] fastmath : f32 -// CHECK: %[[REAL_SQRT:.*]] = math.sqrt %[[REAL_SQ_PLUS_ONE]] fastmath : f32 -// CHECK: %[[IMAG_ABS:.*]] = math.absf %[[IMAG2]] fastmath : f32 -// CHECK: %[[ABS_REAL:.*]] = arith.mulf %[[REAL_SQRT]], %[[IMAG_ABS]] fastmath : f32 -// CHECK: %[[REAL_GT_IMAG:.*]] = arith.cmpf ogt, %[[REAL2]], %[[IMAG2]] : f32 -// CHECK: %[[ABS1:.*]] = arith.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : f32 -// CHECK: %[[ABS2:.*]] = arith.select %[[IS_IMAG_ZERO]], %[[REAL_ABS]], %[[ABS1]] : f32 -// CHECK: %[[NORM:.*]] = arith.select %[[IS_REAL_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : f32 -// CHECK: %[[REAL_SIGN:.*]] = arith.divf %[[REAL]], %[[NORM]] fastmath : f32 -// CHECK: %[[IMAG_SIGN:.*]] = arith.divf %[[IMAG]], %[[NORM]] fastmath : f32 +// CHECK: %[[ABS_REAL:.*]] = math.absf %[[REAL2]] fastmath : f32 +// CHECK: %[[ABS_IMAG:.*]] = math.absf %[[IMAG2]] fastmath : f32 +// CHECK: %[[MAX:.*]] = arith.maximumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[MIN:.*]] = arith.minimumf %[[ABS_REAL]], %[[ABS_IMAG]] fastmath : f32 +// CHECK: %[[RATIO:.*]] = arith.divf %[[MIN]], %[[MAX]] fastmath : f32 +// CHECK: %[[RATIO_SQ:.*]] = arith.mulf %[[RATIO]], %[[RATIO]] fastmath : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = arith.addf %[[RATIO_SQ]], %[[ONE]] fastmath : f32 +// CHECK: %[[SQRT:.*]] = math.sqrt %[[RATIO_SQ_PLUS_ONE]] fastmath : f32 +// CHECK: %[[ABS_OR_NAN:.*]] = arith.mulf %[[MAX]], %[[SQRT]] fastmath : f32 +// CHECK: %[[IS_NAN:.*]] = arith.cmpf uno, %[[ABS_OR_NAN]], %[[ABS_OR_NAN]] fastmath : f32 +// CHECK: %[[ABS:.*]] = arith.select %[[IS_NAN]], %[[MIN]], %[[ABS_OR_NAN]] : f32 +// CHECK: %[[REAL_SIGN:.*]] = arith.divf %[[REAL]], %[[ABS]] fastmath : f32 +// CHECK: %[[IMAG_SIGN:.*]] = arith.divf %[[IMAG]], %[[ABS]] fastmath : f32 // CHECK: %[[SIGN:.*]] = complex.create %[[REAL_SIGN]], %[[IMAG_SIGN]] : complex // CHECK: %[[RESULT:.*]] = arith.select %[[IS_ZERO]], %[[ARG]], %[[SIGN]] : complex // CHECK: return %[[RESULT]] : complex diff --git a/mlir/test/Conversion/ComplexToStandard/full-conversion.mlir b/mlir/test/Conversion/ComplexToStandard/full-conversion.mlir index 0f23e20167f4..2649d004a76a 100644 --- a/mlir/test/Conversion/ComplexToStandard/full-conversion.mlir +++ b/mlir/test/Conversion/ComplexToStandard/full-conversion.mlir @@ -6,32 +6,22 @@ func.func @complex_abs(%arg: complex) -> f32 { %abs = complex.abs %arg: complex return %abs : f32 } -// CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0.000000e+00 : f32) : f32 // CHECK: %[[ONE:.*]] = llvm.mlir.constant(1.000000e+00 : f32) : f32 // CHECK: %[[REAL:.*]] = llvm.extractvalue %[[ARG]][0] : ![[C_TY]] // CHECK: %[[IMAG:.*]] = llvm.extractvalue %[[ARG]][1] : ![[C_TY]] -// CHECK: %[[REAL_IS_ZERO:.*]] = llvm.fcmp "oeq" %[[REAL]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_IS_ZERO:.*]] = llvm.fcmp "oeq" %[[IMAG]], %[[ZERO]] : f32 -// CHECK: %[[IMAG_DIV_REAL:.*]] = llvm.fdiv %[[IMAG]], %[[REAL]] : f32 -// CHECK: %[[IMAG_SQ:.*]] = llvm.fmul %[[IMAG_DIV_REAL]], %[[IMAG_DIV_REAL]] : f32 -// CHECK: %[[IMAG_SQ_PLUS_ONE:.*]] = llvm.fadd %[[IMAG_SQ]], %[[ONE]] : f32 -// CHECK: %[[IMAG_SQRT:.*]] = llvm.intr.sqrt(%[[IMAG_SQ_PLUS_ONE]]) : (f32) -> f32 -// CHECK: %[[REAL_ABS:.*]] = llvm.intr.fabs(%[[REAL]]) : (f32) -> f32 -// CHECK: %[[ABS_IMAG:.*]] = llvm.fmul %[[IMAG_SQRT]], %[[REAL_ABS]] : f32 - -// CHECK: %[[REAL_DIV_IMAG:.*]] = llvm.fdiv %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[REAL_SQ:.*]] = llvm.fmul %[[REAL_DIV_IMAG]], %[[REAL_DIV_IMAG]] : f32 -// CHECK: %[[REAL_SQ_PLUS_ONE:.*]] = llvm.fadd %[[REAL_SQ]], %[[ONE]] : f32 -// CHECK: %[[REAL_SQRT:.*]] = llvm.intr.sqrt(%[[REAL_SQ_PLUS_ONE]]) : (f32) -> f32 -// CHECK: %[[IMAG_ABS:.*]] = llvm.intr.fabs(%[[IMAG]]) : (f32) -> f32 -// CHECK: %[[ABS_REAL:.*]] = llvm.fmul %[[REAL_SQRT]], %[[IMAG_ABS]] : f32 - -// CHECK: %[[REAL_GT_IMAG:.*]] = llvm.fcmp "ogt" %[[REAL]], %[[IMAG]] : f32 -// CHECK: %[[ABS1:.*]] = llvm.select %[[REAL_GT_IMAG]], %[[ABS_IMAG]], %[[ABS_REAL]] : i1, f32 -// CHECK: %[[ABS2:.*]] = llvm.select %[[IMAG_IS_ZERO]], %[[REAL_ABS]], %[[ABS1]] : i1, f32 -// CHECK: %[[NORM:.*]] = llvm.select %[[REAL_IS_ZERO]], %[[IMAG_ABS]], %[[ABS2]] : i1, f32 -// CHECK: llvm.return %[[NORM]] : f32 +// CHECK: %[[ABS_REAL:.*]] = llvm.intr.fabs(%[[REAL]]) : (f32) -> f32 +// CHECK: %[[ABS_IMAG:.*]] = llvm.intr.fabs(%[[IMAG]]) : (f32) -> f32 +// CHECK: %[[MAX:.*]] = llvm.intr.maximum(%[[ABS_REAL]], %[[ABS_IMAG]]) : (f32, f32) -> f32 +// CHECK: %[[MIN:.*]] = llvm.intr.minimum(%[[ABS_REAL]], %[[ABS_IMAG]]) : (f32, f32) -> f32 +// CHECK: %[[RATIO:.*]] = llvm.fdiv %[[MIN]], %[[MAX]] : f32 +// CHECK: %[[RATIO_SQ:.*]] = llvm.fmul %[[RATIO]], %[[RATIO]] : f32 +// CHECK: %[[RATIO_SQ_PLUS_ONE:.*]] = llvm.fadd %[[RATIO_SQ]], %[[ONE]] : f32 +// CHECK: %[[SQRT:.*]] = llvm.intr.sqrt(%[[RATIO_SQ_PLUS_ONE]]) : (f32) -> f32 +// CHECK: %[[RESULT:.*]] = llvm.fmul %[[MAX]], %[[SQRT]] : f32 +// CHECK: %[[IS_NAN:.*]] = llvm.fcmp "uno" %[[RESULT]], %11 : f32 +// CHECK: %[[RET:.*]] = llvm.select %[[IS_NAN]], %[[MIN]], %[[RESULT]] : i1, f32 +// CHECK: llvm.return %[[RET]] : f32 // CHECK-LABEL: llvm.func @complex_eq // CHECK-SAME: %[[LHS:.*]]: ![[C_TY:.*]], %[[RHS:.*]]: ![[C_TY:.*]]) -- GitLab From b1094776152b68efa05f69b7b833f9cbc0727efc Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Thu, 11 Apr 2024 19:10:53 +0800 Subject: [PATCH 520/695] [InstCombine] Infer nsw/nuw for trunc (#87910) This patch adds support for inferring trunc's nsw/nuw flags. --- clang/test/CodeGen/ms-intrinsics-other.c | 4 +- clang/test/CodeGen/ms-intrinsics.c | 4 +- clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 2 +- clang/test/Headers/__clang_hip_math.hip | 2 +- .../InstCombine/InstCombineCasts.cpp | 15 +++- .../RISCV/riscv-vsetvli-knownbits.ll | 4 +- .../RISCV/riscv-vsetvlimax-knownbits.ll | 4 +- llvm/test/Transforms/InstCombine/add.ll | 2 +- .../Transforms/InstCombine/binop-itofp.ll | 12 ++-- .../test/Transforms/InstCombine/bswap-fold.ll | 8 +-- llvm/test/Transforms/InstCombine/bswap.ll | 4 +- llvm/test/Transforms/InstCombine/cast.ll | 30 ++++---- .../Transforms/InstCombine/cmp-intrinsic.ll | 4 +- .../Transforms/InstCombine/compare-signs.ll | 4 +- llvm/test/Transforms/InstCombine/ctpop.ll | 2 +- .../extractelement-inseltpoison.ll | 10 +-- .../Transforms/InstCombine/extractelement.ll | 28 ++++---- llvm/test/Transforms/InstCombine/ffs-1.ll | 2 +- llvm/test/Transforms/InstCombine/fls.ll | 2 +- .../InstCombine/fold-log2-ceil-idiom.ll | 2 +- .../high-bit-signmask-with-trunc.ll | 20 +++--- .../Transforms/InstCombine/icmp-mul-zext.ll | 2 +- .../InstCombine/icmp-of-trunc-ext.ll | 20 +++--- .../InstCombine/icmp-topbitssame.ll | 8 +-- .../Transforms/InstCombine/insert-trunc.ll | 14 ++-- .../Transforms/InstCombine/insertelt-trunc.ll | 34 ++++----- .../test/Transforms/InstCombine/known-bits.ll | 2 +- .../Transforms/InstCombine/known-non-zero.ll | 4 +- .../InstCombine/known-phi-recurse.ll | 18 ++--- .../logical-select-inseltpoison.ll | 2 +- .../Transforms/InstCombine/logical-select.ll | 2 +- .../lshr-trunc-sext-to-ashr-sext.ll | 12 ++-- llvm/test/Transforms/InstCombine/lshr.ll | 22 +++--- .../merging-multiple-stores-into-successor.ll | 2 +- llvm/test/Transforms/InstCombine/narrow.ll | 2 +- .../Transforms/InstCombine/negated-bitmask.ll | 4 +- llvm/test/Transforms/InstCombine/pr34349.ll | 2 +- .../InstCombine/reduction-add-sext-zext-i1.ll | 4 +- llvm/test/Transforms/InstCombine/sadd_sat.ll | 38 +++++----- .../InstCombine/select-cmp-cttz-ctlz.ll | 28 ++++---- .../InstCombine/select-imm-canon.ll | 6 +- llvm/test/Transforms/InstCombine/select.ll | 2 +- .../InstCombine/sext-of-trunc-nsw.ll | 6 +- llvm/test/Transforms/InstCombine/sext.ll | 2 +- llvm/test/Transforms/InstCombine/shift-add.ll | 2 +- ...ciation-in-bittest-with-truncation-lshr.ll | 4 +- ...ount-reassociation-with-truncation-ashr.ll | 8 +-- ...ount-reassociation-with-truncation-lshr.ll | 8 +-- .../Transforms/InstCombine/shift-shift.ll | 6 +- llvm/test/Transforms/InstCombine/shift.ll | 6 +- .../test/Transforms/InstCombine/shl-demand.ll | 2 +- ...-test-via-right-shifting-all-other-bits.ll | 4 +- .../Transforms/InstCombine/trunc-demand.ll | 8 +-- .../InstCombine/trunc-inseltpoison.ll | 6 +- .../InstCombine/trunc-shift-trunc.ll | 4 +- llvm/test/Transforms/InstCombine/trunc.ll | 6 +- .../InstCombine/truncating-saturate.ll | 20 +++--- .../Transforms/InstCombine/vector-trunc.ll | 4 +- llvm/test/Transforms/InstCombine/xor-ashr.ll | 4 +- .../zext-ctlz-trunc-to-ctlz-add.ll | 4 +- .../AArch64/deterministic-type-shrinkage.ll | 16 ++--- .../LoopVectorize/AArch64/intrinsiccost.ll | 6 +- .../LoopVectorize/X86/intrinsiccost.ll | 8 +-- .../Transforms/LoopVectorize/reduction.ll | 4 +- .../PhaseOrdering/AArch64/quant_4x4.ll | 72 +++++++++---------- .../Transforms/SLPVectorizer/X86/pr46983.ll | 2 +- 66 files changed, 309 insertions(+), 296 deletions(-) diff --git a/clang/test/CodeGen/ms-intrinsics-other.c b/clang/test/CodeGen/ms-intrinsics-other.c index 36c40dddcbb4..0e9dfe34b84c 100644 --- a/clang/test/CodeGen/ms-intrinsics-other.c +++ b/clang/test/CodeGen/ms-intrinsics-other.c @@ -87,7 +87,7 @@ unsigned char test_BitScanForward64(unsigned LONG *Index, unsigned __int64 Mask) // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[INDEX:%[0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %Mask, i1 true) -// CHECK: [[TRUNC_INDEX:%[0-9]+]] = trunc i64 [[INDEX]] to i32 +// CHECK: [[TRUNC_INDEX:%[0-9]+]] = trunc nuw nsw i64 [[INDEX]] to i32 // CHECK: store i32 [[TRUNC_INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] @@ -102,7 +102,7 @@ unsigned char test_BitScanReverse64(unsigned LONG *Index, unsigned __int64 Mask) // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[REVINDEX:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %Mask, i1 true) -// CHECK: [[TRUNC_REVINDEX:%[0-9]+]] = trunc i64 [[REVINDEX]] to i32 +// CHECK: [[TRUNC_REVINDEX:%[0-9]+]] = trunc nuw nsw i64 [[REVINDEX]] to i32 // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63 // CHECK: store i32 [[INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] diff --git a/clang/test/CodeGen/ms-intrinsics.c b/clang/test/CodeGen/ms-intrinsics.c index 5bb003d1f91f..6eabd725e2f7 100644 --- a/clang/test/CodeGen/ms-intrinsics.c +++ b/clang/test/CodeGen/ms-intrinsics.c @@ -189,7 +189,7 @@ unsigned char test_BitScanForward64(unsigned long *Index, unsigned __int64 Mask) // CHECK-ARM-X64: ret i8 [[RESULT]] // CHECK-ARM-X64: [[ISNOTZERO_LABEL]]: // CHECK-ARM-X64: [[INDEX:%[0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %Mask, i1 true) -// CHECK-ARM-X64: [[TRUNC_INDEX:%[0-9]+]] = trunc i64 [[INDEX]] to i32 +// CHECK-ARM-X64: [[TRUNC_INDEX:%[0-9]+]] = trunc nuw nsw i64 [[INDEX]] to i32 // CHECK-ARM-X64: store i32 [[TRUNC_INDEX]], ptr %Index, align 4 // CHECK-ARM-X64: br label %[[END_LABEL]] @@ -204,7 +204,7 @@ unsigned char test_BitScanReverse64(unsigned long *Index, unsigned __int64 Mask) // CHECK-ARM-X64: ret i8 [[RESULT]] // CHECK-ARM-X64: [[ISNOTZERO_LABEL]]: // CHECK-ARM-X64: [[REVINDEX:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %Mask, i1 true) -// CHECK-ARM-X64: [[TRUNC_REVINDEX:%[0-9]+]] = trunc i64 [[REVINDEX]] to i32 +// CHECK-ARM-X64: [[TRUNC_REVINDEX:%[0-9]+]] = trunc nuw nsw i64 [[REVINDEX]] to i32 // CHECK-ARM-X64: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63 // CHECK-ARM-X64: store i32 [[INDEX]], ptr %Index, align 4 // CHECK-ARM-X64: br label %[[END_LABEL]] diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl index 8a4533633706..bdca97c88786 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl @@ -528,7 +528,7 @@ void test_read_exec_lo(global uint* out) { // CHECK-LABEL: @test_read_exec_hi( // CHECK: call i64 @llvm.amdgcn.ballot.i64(i1 true) // CHECK: lshr i64 [[A:%.*]], 32 -// CHECK: trunc i64 [[B:%.*]] to i32 +// CHECK: trunc nuw i64 [[B:%.*]] to i32 void test_read_exec_hi(global uint* out) { *out = __builtin_amdgcn_read_exec_hi(); } diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip index 37099de74fb8..2e5f521a5fea 100644 --- a/clang/test/Headers/__clang_hip_math.hip +++ b/clang/test/Headers/__clang_hip_math.hip @@ -3703,7 +3703,7 @@ extern "C" __device__ BOOL_TYPE test___signbitf(float x) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[X:%.*]] to i64 // CHECK-NEXT: [[DOTLOBIT:%.*]] = lshr i64 [[TMP0]], 63 -// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[DOTLOBIT]] to i32 +// CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[DOTLOBIT]] to i32 // CHECK-NEXT: ret i32 [[CONV]] // extern "C" __device__ BOOL_TYPE test___signbit(double x) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 0652a8ba80b3..437e9b92c703 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -897,7 +897,20 @@ Instruction *InstCombinerImpl::visitTrunc(TruncInst &Trunc) { } } - return nullptr; + bool Changed = false; + if (!Trunc.hasNoSignedWrap() && + ComputeMaxSignificantBits(Src, /*Depth=*/0, &Trunc) <= DestWidth) { + Trunc.setHasNoSignedWrap(true); + Changed = true; + } + if (!Trunc.hasNoUnsignedWrap() && + MaskedValueIsZero(Src, APInt::getBitsSetFrom(SrcWidth, DestWidth), + /*Depth=*/0, &Trunc)) { + Trunc.setHasNoUnsignedWrap(true); + Changed = true; + } + + return Changed ? &Trunc : nullptr; } Instruction *InstCombinerImpl::transformZExtICmp(ICmpInst *Cmp, diff --git a/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll b/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll index 1afae6565fe2..6e0acfd68511 100644 --- a/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll +++ b/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvli-knownbits.ll @@ -45,7 +45,7 @@ entry: define signext i32 @vsetvl_sext() nounwind #0 { ; CHECK-LABEL: @vsetvl_sext( ; CHECK-NEXT: [[A:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 1, i64 1) -; CHECK-NEXT: [[B:%.*]] = trunc i64 [[A]] to i32 +; CHECK-NEXT: [[B:%.*]] = trunc nuw nsw i64 [[A]] to i32 ; CHECK-NEXT: ret i32 [[B]] ; %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1) @@ -56,7 +56,7 @@ define signext i32 @vsetvl_sext() nounwind #0 { define zeroext i32 @vsetvl_zext() nounwind #0 { ; CHECK-LABEL: @vsetvl_zext( ; CHECK-NEXT: [[A:%.*]] = call i64 @llvm.riscv.vsetvli.i64(i64 1, i64 1, i64 1) -; CHECK-NEXT: [[B:%.*]] = trunc i64 [[A]] to i32 +; CHECK-NEXT: [[B:%.*]] = trunc nuw nsw i64 [[A]] to i32 ; CHECK-NEXT: ret i32 [[B]] ; %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1) diff --git a/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-knownbits.ll b/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-knownbits.ll index 093ba75e87b5..811a29c7e562 100644 --- a/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-knownbits.ll +++ b/llvm/test/Transforms/InstCombine/RISCV/riscv-vsetvlimax-knownbits.ll @@ -45,7 +45,7 @@ entry: define signext i32 @vsetvlmax_sext() nounwind #0 { ; CHECK-LABEL: @vsetvlmax_sext( ; CHECK-NEXT: [[A:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) -; CHECK-NEXT: [[B:%.*]] = trunc i64 [[A]] to i32 +; CHECK-NEXT: [[B:%.*]] = trunc nuw nsw i64 [[A]] to i32 ; CHECK-NEXT: ret i32 [[B]] ; %a = call i64 @llvm.riscv.vsetvlimax(i64 1, i64 1) @@ -56,7 +56,7 @@ define signext i32 @vsetvlmax_sext() nounwind #0 { define zeroext i32 @vsetvlmax_zext() nounwind #0 { ; CHECK-LABEL: @vsetvlmax_zext( ; CHECK-NEXT: [[A:%.*]] = call i64 @llvm.riscv.vsetvlimax.i64(i64 1, i64 1) -; CHECK-NEXT: [[B:%.*]] = trunc i64 [[A]] to i32 +; CHECK-NEXT: [[B:%.*]] = trunc nuw nsw i64 [[A]] to i32 ; CHECK-NEXT: ret i32 [[B]] ; %a = call i64 @llvm.riscv.vsetvlimax(i64 1, i64 1) diff --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll index ec3aca26514c..23eee8547597 100644 --- a/llvm/test/Transforms/InstCombine/add.ll +++ b/llvm/test/Transforms/InstCombine/add.ll @@ -2375,7 +2375,7 @@ define { i64, i64 } @PR57576(i64 noundef %x, i64 noundef %y, i64 noundef %z, i64 ; CHECK-NEXT: [[SUB:%.*]] = sub i128 [[XY]], [[ZZ]] ; CHECK-NEXT: [[T:%.*]] = trunc i128 [[SUB]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i128 [[SUB]], 64 -; CHECK-NEXT: [[DOTTR:%.*]] = trunc i128 [[TMP1]] to i64 +; CHECK-NEXT: [[DOTTR:%.*]] = trunc nuw i128 [[TMP1]] to i64 ; CHECK-NEXT: [[DOTNARROW:%.*]] = sub i64 [[DOTTR]], [[W:%.*]] ; CHECK-NEXT: [[R1:%.*]] = insertvalue { i64, i64 } poison, i64 [[T]], 0 ; CHECK-NEXT: [[R2:%.*]] = insertvalue { i64, i64 } [[R1]], i64 [[DOTNARROW]], 1 diff --git a/llvm/test/Transforms/InstCombine/binop-itofp.ll b/llvm/test/Transforms/InstCombine/binop-itofp.ll index cd9ec1e59203..d72a54e8babc 100644 --- a/llvm/test/Transforms/InstCombine/binop-itofp.ll +++ b/llvm/test/Transforms/InstCombine/binop-itofp.ll @@ -1010,7 +1010,7 @@ define float @test_ui_add_with_signed_constant(i32 %shr.i) { define float @missed_nonzero_check_on_constant_for_si_fmul(i1 %c, i1 %.b, ptr %g_2345) { ; CHECK-LABEL: @missed_nonzero_check_on_constant_for_si_fmul( ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i32 65529, i32 53264 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i32 [[SEL]] to i16 ; CHECK-NEXT: [[CONV1_I:%.*]] = sitofp i16 [[CONV_I]] to float ; CHECK-NEXT: [[MUL3_I_I:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[CONV1_I]]) ; CHECK-NEXT: store i32 [[SEL]], ptr [[G_2345:%.*]], align 4 @@ -1027,7 +1027,7 @@ define float @missed_nonzero_check_on_constant_for_si_fmul(i1 %c, i1 %.b, ptr %g define <2 x float> @missed_nonzero_check_on_constant_for_si_fmul_vec(i1 %c, i1 %.b, ptr %g_2345) { ; CHECK-LABEL: @missed_nonzero_check_on_constant_for_si_fmul_vec( ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i32 65529, i32 53264 -; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc nuw i32 [[SEL]] to i16 ; CHECK-NEXT: [[CONV_I_V:%.*]] = insertelement <2 x i16> poison, i16 [[CONV_I_S]], i64 0 ; CHECK-NEXT: [[CONV_I:%.*]] = shufflevector <2 x i16> [[CONV_I_V]], <2 x i16> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[CONV1_I:%.*]] = sitofp <2 x i16> [[CONV_I]] to <2 x float> @@ -1048,7 +1048,7 @@ define <2 x float> @missed_nonzero_check_on_constant_for_si_fmul_vec(i1 %c, i1 % define float @negzero_check_on_constant_for_si_fmul(i1 %c, i1 %.b, ptr %g_2345) { ; CHECK-LABEL: @negzero_check_on_constant_for_si_fmul( ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i32 65529, i32 53264 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i32 [[SEL]] to i16 ; CHECK-NEXT: [[CONV1_I:%.*]] = sitofp i16 [[CONV_I]] to float ; CHECK-NEXT: [[TMP1:%.*]] = fneg float [[CONV1_I]] ; CHECK-NEXT: [[MUL3_I_I:%.*]] = call float @llvm.copysign.f32(float 0.000000e+00, float [[TMP1]]) @@ -1066,7 +1066,7 @@ define float @negzero_check_on_constant_for_si_fmul(i1 %c, i1 %.b, ptr %g_2345) define <2 x float> @nonzero_check_on_constant_for_si_fmul_vec_w_undef(i1 %c, i1 %.b, ptr %g_2345) { ; CHECK-LABEL: @nonzero_check_on_constant_for_si_fmul_vec_w_undef( ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i32 65529, i32 53264 -; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc nuw i32 [[SEL]] to i16 ; CHECK-NEXT: [[CONV_I_V:%.*]] = insertelement <2 x i16> poison, i16 [[CONV_I_S]], i64 0 ; CHECK-NEXT: [[CONV_I:%.*]] = shufflevector <2 x i16> [[CONV_I_V]], <2 x i16> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[CONV1_I:%.*]] = sitofp <2 x i16> [[CONV_I]] to <2 x float> @@ -1087,7 +1087,7 @@ define <2 x float> @nonzero_check_on_constant_for_si_fmul_vec_w_undef(i1 %c, i1 define <2 x float> @nonzero_check_on_constant_for_si_fmul_nz_vec_w_undef(i1 %c, i1 %.b, ptr %g_2345) { ; CHECK-LABEL: @nonzero_check_on_constant_for_si_fmul_nz_vec_w_undef( ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i32 65529, i32 53264 -; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc nuw i32 [[SEL]] to i16 ; CHECK-NEXT: [[CONV_I_V:%.*]] = insertelement <2 x i16> poison, i16 [[CONV_I_S]], i64 0 ; CHECK-NEXT: [[CONV_I:%.*]] = shufflevector <2 x i16> [[CONV_I_V]], <2 x i16> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[CONV1_I:%.*]] = sitofp <2 x i16> [[CONV_I]] to <2 x float> @@ -1108,7 +1108,7 @@ define <2 x float> @nonzero_check_on_constant_for_si_fmul_nz_vec_w_undef(i1 %c, define <2 x float> @nonzero_check_on_constant_for_si_fmul_negz_vec_w_undef(i1 %c, i1 %.b, ptr %g_2345) { ; CHECK-LABEL: @nonzero_check_on_constant_for_si_fmul_negz_vec_w_undef( ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[C:%.*]], i32 65529, i32 53264 -; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc i32 [[SEL]] to i16 +; CHECK-NEXT: [[CONV_I_S:%.*]] = trunc nuw i32 [[SEL]] to i16 ; CHECK-NEXT: [[CONV_I_V:%.*]] = insertelement <2 x i16> poison, i16 [[CONV_I_S]], i64 0 ; CHECK-NEXT: [[CONV_I:%.*]] = shufflevector <2 x i16> [[CONV_I_V]], <2 x i16> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[CONV1_I:%.*]] = sitofp <2 x i16> [[CONV_I]] to <2 x float> diff --git a/llvm/test/Transforms/InstCombine/bswap-fold.ll b/llvm/test/Transforms/InstCombine/bswap-fold.ll index 05933d37057c..19522168beaf 100644 --- a/llvm/test/Transforms/InstCombine/bswap-fold.ll +++ b/llvm/test/Transforms/InstCombine/bswap-fold.ll @@ -211,7 +211,7 @@ define i64 @variable_shl_not_masked_enough_i64(i64 %x, i64 %n) { define i16 @test7(i32 %A) { ; CHECK-LABEL: @test7( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[A:%.*]], 16 -; CHECK-NEXT: [[D:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[D:%.*]] = trunc nuw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[D]] ; %B = tail call i32 @llvm.bswap.i32(i32 %A) nounwind @@ -223,7 +223,7 @@ define i16 @test7(i32 %A) { define <2 x i16> @test7_vector(<2 x i32> %A) { ; CHECK-LABEL: @test7_vector( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[D:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16> +; CHECK-NEXT: [[D:%.*]] = trunc nuw <2 x i32> [[TMP1]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[D]] ; %B = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %A) nounwind @@ -235,7 +235,7 @@ define <2 x i16> @test7_vector(<2 x i32> %A) { define i16 @test8(i64 %A) { ; CHECK-LABEL: @test8( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[A:%.*]], 48 -; CHECK-NEXT: [[D:%.*]] = trunc i64 [[TMP1]] to i16 +; CHECK-NEXT: [[D:%.*]] = trunc nuw i64 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[D]] ; %B = tail call i64 @llvm.bswap.i64(i64 %A) nounwind @@ -247,7 +247,7 @@ define i16 @test8(i64 %A) { define <2 x i16> @test8_vector(<2 x i64> %A) { ; CHECK-LABEL: @test8_vector( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[A:%.*]], -; CHECK-NEXT: [[D:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i16> +; CHECK-NEXT: [[D:%.*]] = trunc nuw <2 x i64> [[TMP1]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[D]] ; %B = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %A) nounwind diff --git a/llvm/test/Transforms/InstCombine/bswap.ll b/llvm/test/Transforms/InstCombine/bswap.ll index 21eb170b8c58..d42583bb5699 100644 --- a/llvm/test/Transforms/InstCombine/bswap.ll +++ b/llvm/test/Transforms/InstCombine/bswap.ll @@ -43,7 +43,7 @@ define i16 @test1_trunc(i32 %i) { ; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[I]], 8 ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], 65280 ; CHECK-NEXT: [[T5:%.*]] = or disjoint i32 [[T1]], [[T4]] -; CHECK-NEXT: [[T13:%.*]] = trunc i32 [[T5]] to i16 +; CHECK-NEXT: [[T13:%.*]] = trunc nuw i32 [[T5]] to i16 ; CHECK-NEXT: ret i16 [[T13]] ; %t1 = lshr i32 %i, 24 @@ -61,7 +61,7 @@ define i16 @test1_trunc_extra_use(i32 %i) { ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], 65280 ; CHECK-NEXT: [[T5:%.*]] = or disjoint i32 [[T1]], [[T4]] ; CHECK-NEXT: call void @extra_use(i32 [[T5]]) -; CHECK-NEXT: [[T13:%.*]] = trunc i32 [[T5]] to i16 +; CHECK-NEXT: [[T13:%.*]] = trunc nuw i32 [[T5]] to i16 ; CHECK-NEXT: ret i16 [[T13]] ; %t1 = lshr i32 %i, 24 diff --git a/llvm/test/Transforms/InstCombine/cast.ll b/llvm/test/Transforms/InstCombine/cast.ll index 97554e946204..d9c93ba27729 100644 --- a/llvm/test/Transforms/InstCombine/cast.ll +++ b/llvm/test/Transforms/InstCombine/cast.ll @@ -1471,7 +1471,7 @@ define i64 @test91(i64 %A) { ; ALL-LABEL: @test91( ; ALL-NEXT: [[B:%.*]] = sext i64 [[A:%.*]] to i96 ; ALL-NEXT: [[C:%.*]] = lshr i96 [[B]], 48 -; ALL-NEXT: [[D:%.*]] = trunc i96 [[C]] to i64 +; ALL-NEXT: [[D:%.*]] = trunc nuw nsw i96 [[C]] to i64 ; ALL-NEXT: ret i64 [[D]] ; %B = sext i64 %A to i96 @@ -1676,7 +1676,7 @@ define i8 @trunc_lshr_overshift_sext_uses3(i8 %A) { define i8 @trunc_lshr_sext_wide_input(i16 %A) { ; ALL-LABEL: @trunc_lshr_sext_wide_input( ; ALL-NEXT: [[TMP1:%.*]] = ashr i16 [[A:%.*]], 9 -; ALL-NEXT: [[D:%.*]] = trunc i16 [[TMP1]] to i8 +; ALL-NEXT: [[D:%.*]] = trunc nsw i16 [[TMP1]] to i8 ; ALL-NEXT: ret i8 [[D]] ; %B = sext i16 %A to i32 @@ -1688,7 +1688,7 @@ define i8 @trunc_lshr_sext_wide_input(i16 %A) { define i8 @trunc_lshr_sext_wide_input_exact(i16 %A) { ; ALL-LABEL: @trunc_lshr_sext_wide_input_exact( ; ALL-NEXT: [[TMP1:%.*]] = ashr exact i16 [[A:%.*]], 9 -; ALL-NEXT: [[D:%.*]] = trunc i16 [[TMP1]] to i8 +; ALL-NEXT: [[D:%.*]] = trunc nsw i16 [[TMP1]] to i8 ; ALL-NEXT: ret i8 [[D]] ; %B = sext i16 %A to i32 @@ -1702,7 +1702,7 @@ define <2 x i8> @trunc_lshr_sext_wide_input_uses1(<2 x i16> %A) { ; ALL-NEXT: [[B:%.*]] = sext <2 x i16> [[A:%.*]] to <2 x i32> ; ALL-NEXT: call void @use_v2i32(<2 x i32> [[B]]) ; ALL-NEXT: [[TMP1:%.*]] = ashr <2 x i16> [[A]], -; ALL-NEXT: [[D:%.*]] = trunc <2 x i16> [[TMP1]] to <2 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nsw <2 x i16> [[TMP1]] to <2 x i8> ; ALL-NEXT: ret <2 x i8> [[D]] ; %B = sext <2 x i16> %A to <2 x i32> @@ -1747,7 +1747,7 @@ define <2 x i8> @trunc_lshr_sext_wide_input_uses3(<2 x i16> %A) { define <2 x i8> @trunc_lshr_overshift_wide_input_sext(<2 x i16> %A) { ; ALL-LABEL: @trunc_lshr_overshift_wide_input_sext( ; ALL-NEXT: [[TMP1:%.*]] = ashr <2 x i16> [[A:%.*]], -; ALL-NEXT: [[D:%.*]] = trunc <2 x i16> [[TMP1]] to <2 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nsw <2 x i16> [[TMP1]] to <2 x i8> ; ALL-NEXT: ret <2 x i8> [[D]] ; %B = sext <2 x i16> %A to <2 x i32> @@ -1761,7 +1761,7 @@ define i8 @trunc_lshr_overshift_sext_wide_input_uses1(i16 %A) { ; ALL-NEXT: [[B:%.*]] = sext i16 [[A:%.*]] to i32 ; ALL-NEXT: call void @use_i32(i32 [[B]]) ; ALL-NEXT: [[TMP1:%.*]] = ashr i16 [[A]], 15 -; ALL-NEXT: [[D:%.*]] = trunc i16 [[TMP1]] to i8 +; ALL-NEXT: [[D:%.*]] = trunc nsw i16 [[TMP1]] to i8 ; ALL-NEXT: ret i8 [[D]] ; %B = sext i16 %A to i32 @@ -1776,7 +1776,7 @@ define <2 x i8> @trunc_lshr_overshift_sext_wide_input_uses2(<2 x i16> %A) { ; ALL-NEXT: [[TMP1:%.*]] = ashr <2 x i16> [[A:%.*]], ; ALL-NEXT: [[C:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> ; ALL-NEXT: call void @use_v2i32(<2 x i32> [[C]]) -; ALL-NEXT: [[D:%.*]] = trunc <2 x i16> [[TMP1]] to <2 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nsw <2 x i16> [[TMP1]] to <2 x i8> ; ALL-NEXT: ret <2 x i8> [[D]] ; %B = sext <2 x i16> %A to <2 x i32> @@ -1925,7 +1925,7 @@ define <2 x i8> @trunc_lshr_overshift2_sext(<2 x i8> %A) { ; ALL-LABEL: @trunc_lshr_overshift2_sext( ; ALL-NEXT: [[B:%.*]] = sext <2 x i8> [[A:%.*]] to <2 x i32> ; ALL-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], -; ALL-NEXT: [[D:%.*]] = trunc <2 x i32> [[C]] to <2 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nuw nsw <2 x i32> [[C]] to <2 x i8> ; ALL-NEXT: ret <2 x i8> [[D]] ; %B = sext <2 x i8> %A to <2 x i32> @@ -1939,7 +1939,7 @@ define i8 @trunc_lshr_overshift2_sext_uses1(i8 %A) { ; ALL-NEXT: [[B:%.*]] = sext i8 [[A:%.*]] to i32 ; ALL-NEXT: call void @use_i32(i32 [[B]]) ; ALL-NEXT: [[C:%.*]] = lshr i32 [[B]], 25 -; ALL-NEXT: [[D:%.*]] = trunc i32 [[C]] to i8 +; ALL-NEXT: [[D:%.*]] = trunc nuw nsw i32 [[C]] to i8 ; ALL-NEXT: ret i8 [[D]] ; %B = sext i8 %A to i32 @@ -1954,7 +1954,7 @@ define <2 x i8> @trunc_lshr_overshift2_sext_uses2(<2 x i8> %A) { ; ALL-NEXT: [[B:%.*]] = sext <2 x i8> [[A:%.*]] to <2 x i32> ; ALL-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], ; ALL-NEXT: call void @use_v2i32(<2 x i32> [[C]]) -; ALL-NEXT: [[D:%.*]] = trunc <2 x i32> [[C]] to <2 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nuw nsw <2 x i32> [[C]] to <2 x i8> ; ALL-NEXT: ret <2 x i8> [[D]] ; %B = sext <2 x i8> %A to <2 x i32> @@ -1970,7 +1970,7 @@ define i8 @trunc_lshr_overshift2_sext_uses3(i8 %A) { ; ALL-NEXT: call void @use_i32(i32 [[B]]) ; ALL-NEXT: [[C:%.*]] = lshr i32 [[B]], 25 ; ALL-NEXT: call void @use_i32(i32 [[C]]) -; ALL-NEXT: [[D:%.*]] = trunc i32 [[C]] to i8 +; ALL-NEXT: [[D:%.*]] = trunc nuw nsw i32 [[C]] to i8 ; ALL-NEXT: ret i8 [[D]] ; %B = sext i8 %A to i32 @@ -2018,7 +2018,7 @@ define <2 x i8> @trunc_lshr_zext_uniform_undef(<2 x i8> %A) { ; ALL-LABEL: @trunc_lshr_zext_uniform_undef( ; ALL-NEXT: [[B:%.*]] = zext <2 x i8> [[A:%.*]] to <2 x i32> ; ALL-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], -; ALL-NEXT: [[D:%.*]] = trunc <2 x i32> [[C]] to <2 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nuw <2 x i32> [[C]] to <2 x i8> ; ALL-NEXT: ret <2 x i8> [[D]] ; %B = zext <2 x i8> %A to <2 x i32> @@ -2042,7 +2042,7 @@ define <3 x i8> @trunc_lshr_zext_nonuniform_undef(<3 x i8> %A) { ; ALL-LABEL: @trunc_lshr_zext_nonuniform_undef( ; ALL-NEXT: [[B:%.*]] = zext <3 x i8> [[A:%.*]] to <3 x i32> ; ALL-NEXT: [[C:%.*]] = lshr <3 x i32> [[B]], -; ALL-NEXT: [[D:%.*]] = trunc <3 x i32> [[C]] to <3 x i8> +; ALL-NEXT: [[D:%.*]] = trunc nuw <3 x i32> [[C]] to <3 x i8> ; ALL-NEXT: ret <3 x i8> [[D]] ; %B = zext <3 x i8> %A to <3 x i32> @@ -2095,7 +2095,7 @@ define i4 @pr33078_3(i8 %A) { ; ALL-LABEL: @pr33078_3( ; ALL-NEXT: [[B:%.*]] = sext i8 [[A:%.*]] to i16 ; ALL-NEXT: [[C:%.*]] = lshr i16 [[B]], 12 -; ALL-NEXT: [[D:%.*]] = trunc i16 [[C]] to i4 +; ALL-NEXT: [[D:%.*]] = trunc nuw i16 [[C]] to i4 ; ALL-NEXT: ret i4 [[D]] ; %B = sext i8 %A to i16 @@ -2109,7 +2109,7 @@ define i8 @pr33078_4(i3 %x) { ; ALL-LABEL: @pr33078_4( ; ALL-NEXT: [[B:%.*]] = sext i3 [[X:%.*]] to i16 ; ALL-NEXT: [[C:%.*]] = lshr i16 [[B]], 13 -; ALL-NEXT: [[D:%.*]] = trunc i16 [[C]] to i8 +; ALL-NEXT: [[D:%.*]] = trunc nuw nsw i16 [[C]] to i8 ; ALL-NEXT: ret i8 [[D]] ; %B = sext i3 %x to i16 diff --git a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll index 5955650167c2..66cbb2636cbc 100644 --- a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll +++ b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll @@ -618,7 +618,7 @@ define i1 @trunc_cttz_false_ult_other_i32_i6(i32 %x) { define i1 @trunc_cttz_false_ult_other_i32_i6_extra_use(i32 %x) { ; CHECK-LABEL: @trunc_cttz_false_ult_other_i32_i6_extra_use( ; CHECK-NEXT: [[TZ:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[TZ]] to i6 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw i32 [[TZ]] to i6 ; CHECK-NEXT: call void @use6(i6 [[TRUNC]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i6 [[TRUNC]], 7 ; CHECK-NEXT: ret i1 [[CMP]] @@ -720,7 +720,7 @@ define i1 @trunc_ctlz_false_ugt_other_i32_i6(i32 %x) { define i1 @trunc_ctlz_false_ugt_other_i32_i6_extra_use(i32 %x) { ; CHECK-LABEL: @trunc_ctlz_false_ugt_other_i32_i6_extra_use( ; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LZ]] to i6 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw i32 [[LZ]] to i6 ; CHECK-NEXT: call void @use6(i6 [[TRUNC]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i6 [[TRUNC]], 4 ; CHECK-NEXT: ret i1 [[CMP]] diff --git a/llvm/test/Transforms/InstCombine/compare-signs.ll b/llvm/test/Transforms/InstCombine/compare-signs.ll index d7aa710e1ef0..3730d46d5f0f 100644 --- a/llvm/test/Transforms/InstCombine/compare-signs.ll +++ b/llvm/test/Transforms/InstCombine/compare-signs.ll @@ -223,7 +223,7 @@ define <2 x i1> @shift_trunc_signbit_test_vec_uses(<2 x i17> %x, ptr %p1, ptr %p ; CHECK-LABEL: @shift_trunc_signbit_test_vec_uses( ; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i17> [[X:%.*]], ; CHECK-NEXT: store <2 x i17> [[SH]], ptr [[P1:%.*]], align 8 -; CHECK-NEXT: [[TR:%.*]] = trunc <2 x i17> [[SH]] to <2 x i13> +; CHECK-NEXT: [[TR:%.*]] = trunc nuw <2 x i17> [[SH]] to <2 x i13> ; CHECK-NEXT: store <2 x i13> [[TR]], ptr [[P2:%.*]], align 4 ; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i17> [[X]], ; CHECK-NEXT: ret <2 x i1> [[R]] @@ -255,7 +255,7 @@ define i1 @shift_trunc_wrong_shift(i32 %x) { define i1 @shift_trunc_wrong_cmp(i32 %x) { ; CHECK-LABEL: @shift_trunc_wrong_cmp( ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 24 -; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[SH]] to i8 +; CHECK-NEXT: [[TR:%.*]] = trunc nuw i32 [[SH]] to i8 ; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[TR]], 1 ; CHECK-NEXT: ret i1 [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/ctpop.ll b/llvm/test/Transforms/InstCombine/ctpop.ll index dcea5fa87479..27194724b7d8 100644 --- a/llvm/test/Transforms/InstCombine/ctpop.ll +++ b/llvm/test/Transforms/InstCombine/ctpop.ll @@ -397,7 +397,7 @@ define i32 @parity_xor_trunc(i64 %arg, i64 %arg1) { ; CHECK-LABEL: @parity_xor_trunc( ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[ARG1:%.*]], [[ARG:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP1]]), !range [[RNG5:![0-9]+]] -; CHECK-NEXT: [[I4:%.*]] = trunc i64 [[TMP2]] to i32 +; CHECK-NEXT: [[I4:%.*]] = trunc nuw nsw i64 [[TMP2]] to i32 ; CHECK-NEXT: [[I5:%.*]] = and i32 [[I4]], 1 ; CHECK-NEXT: ret i32 [[I5]] ; diff --git a/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll index 877aa2e523a3..57e81d2da898 100644 --- a/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll @@ -48,7 +48,7 @@ define i32 @bitcasted_inselt_wide_source_zero_elt(i64 %x) { ; ; BE-LABEL: @bitcasted_inselt_wide_source_zero_elt( ; BE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32 -; BE-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32 +; BE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; BE-NEXT: ret i32 [[R]] ; %i = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0 @@ -64,7 +64,7 @@ define i16 @bitcasted_inselt_wide_source_modulo_elt(i64 %x) { ; ; BE-LABEL: @bitcasted_inselt_wide_source_modulo_elt( ; BE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 48 -; BE-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i16 +; BE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP1]] to i16 ; BE-NEXT: ret i16 [[R]] ; %i = insertelement <2 x i64> poison, i64 %x, i32 1 @@ -76,7 +76,7 @@ define i16 @bitcasted_inselt_wide_source_modulo_elt(i64 %x) { define i32 @bitcasted_inselt_wide_source_not_modulo_elt(i64 %x) { ; LE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt( ; LE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32 -; LE-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32 +; LE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; LE-NEXT: ret i32 [[R]] ; ; BE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt( @@ -166,7 +166,7 @@ define i8 @bitcasted_inselt_wide_source_uses(i32 %x) { define float @bitcasted_inselt_to_FP(i64 %x) { ; LE-LABEL: @bitcasted_inselt_to_FP( ; LE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32 -; LE-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32 +; LE-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; LE-NEXT: [[R:%.*]] = bitcast i32 [[TMP2]] to float ; LE-NEXT: ret float [[R]] ; @@ -218,7 +218,7 @@ define i32 @bitcasted_inselt_from_FP(double %x) { ; LE-LABEL: @bitcasted_inselt_from_FP( ; LE-NEXT: [[TMP1:%.*]] = bitcast double [[X:%.*]] to i64 ; LE-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 32 -; LE-NEXT: [[R:%.*]] = trunc i64 [[TMP2]] to i32 +; LE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP2]] to i32 ; LE-NEXT: ret i32 [[R]] ; ; BE-LABEL: @bitcasted_inselt_from_FP( diff --git a/llvm/test/Transforms/InstCombine/extractelement.ll b/llvm/test/Transforms/InstCombine/extractelement.ll index bc5dd060a540..28a4702559c4 100644 --- a/llvm/test/Transforms/InstCombine/extractelement.ll +++ b/llvm/test/Transforms/InstCombine/extractelement.ll @@ -50,7 +50,7 @@ define i32 @bitcasted_inselt_wide_source_zero_elt(i64 %x) { ; ; ANYBE-LABEL: @bitcasted_inselt_wide_source_zero_elt( ; ANYBE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32 -; ANYBE-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32 +; ANYBE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; ANYBE-NEXT: ret i32 [[R]] ; %i = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0 @@ -66,7 +66,7 @@ define i16 @bitcasted_inselt_wide_source_modulo_elt(i64 %x) { ; ; ANYBE-LABEL: @bitcasted_inselt_wide_source_modulo_elt( ; ANYBE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 48 -; ANYBE-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i16 +; ANYBE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP1]] to i16 ; ANYBE-NEXT: ret i16 [[R]] ; %i = insertelement <2 x i64> undef, i64 %x, i32 1 @@ -78,7 +78,7 @@ define i16 @bitcasted_inselt_wide_source_modulo_elt(i64 %x) { define i32 @bitcasted_inselt_wide_source_not_modulo_elt(i64 %x) { ; ANYLE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt( ; ANYLE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32 -; ANYLE-NEXT: [[R:%.*]] = trunc i64 [[TMP1]] to i32 +; ANYLE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; ANYLE-NEXT: ret i32 [[R]] ; ; ANYBE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt( @@ -168,7 +168,7 @@ define i8 @bitcasted_inselt_wide_source_uses(i32 %x) { define float @bitcasted_inselt_to_FP(i64 %x) { ; ANYLE-LABEL: @bitcasted_inselt_to_FP( ; ANYLE-NEXT: [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32 -; ANYLE-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32 +; ANYLE-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; ANYLE-NEXT: [[R:%.*]] = bitcast i32 [[TMP2]] to float ; ANYLE-NEXT: ret float [[R]] ; @@ -220,7 +220,7 @@ define i32 @bitcasted_inselt_from_FP(double %x) { ; ANYLE-LABEL: @bitcasted_inselt_from_FP( ; ANYLE-NEXT: [[TMP1:%.*]] = bitcast double [[X:%.*]] to i64 ; ANYLE-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 32 -; ANYLE-NEXT: [[R:%.*]] = trunc i64 [[TMP2]] to i32 +; ANYLE-NEXT: [[R:%.*]] = trunc nuw i64 [[TMP2]] to i32 ; ANYLE-NEXT: ret i32 [[R]] ; ; ANYBE-LABEL: @bitcasted_inselt_from_FP( @@ -341,7 +341,7 @@ define i8 @bitcast_scalar_supported_type_index0(i32 %x) { ; ; ANYBE-LABEL: @bitcast_scalar_supported_type_index0( ; ANYBE-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[X:%.*]], 24 -; ANYBE-NEXT: [[R:%.*]] = trunc i32 [[EXTELT_OFFSET]] to i8 +; ANYBE-NEXT: [[R:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i8 ; ANYBE-NEXT: ret i8 [[R]] ; %v = bitcast i32 %x to <4 x i8> @@ -443,7 +443,7 @@ define half @bitcast_fp16vec_index0(i32 %x) { ; ; ANYBE-LABEL: @bitcast_fp16vec_index0( ; ANYBE-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[X:%.*]], 16 -; ANYBE-NEXT: [[TMP1:%.*]] = trunc i32 [[EXTELT_OFFSET]] to i16 +; ANYBE-NEXT: [[TMP1:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 ; ANYBE-NEXT: [[R:%.*]] = bitcast i16 [[TMP1]] to half ; ANYBE-NEXT: ret half [[R]] ; @@ -455,7 +455,7 @@ define half @bitcast_fp16vec_index0(i32 %x) { define half @bitcast_fp16vec_index1(i32 %x) { ; ANYLE-LABEL: @bitcast_fp16vec_index1( ; ANYLE-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[X:%.*]], 16 -; ANYLE-NEXT: [[TMP1:%.*]] = trunc i32 [[EXTELT_OFFSET]] to i16 +; ANYLE-NEXT: [[TMP1:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 ; ANYLE-NEXT: [[R:%.*]] = bitcast i16 [[TMP1]] to half ; ANYLE-NEXT: ret half [[R]] ; @@ -477,7 +477,7 @@ define bfloat @bitcast_bfp16vec_index0(i32 %x) { ; ; ANYBE-LABEL: @bitcast_bfp16vec_index0( ; ANYBE-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[X:%.*]], 16 -; ANYBE-NEXT: [[TMP1:%.*]] = trunc i32 [[EXTELT_OFFSET]] to i16 +; ANYBE-NEXT: [[TMP1:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 ; ANYBE-NEXT: [[R:%.*]] = bitcast i16 [[TMP1]] to bfloat ; ANYBE-NEXT: ret bfloat [[R]] ; @@ -489,7 +489,7 @@ define bfloat @bitcast_bfp16vec_index0(i32 %x) { define bfloat @bitcast_bfp16vec_index1(i32 %x) { ; ANYLE-LABEL: @bitcast_bfp16vec_index1( ; ANYLE-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i32 [[X:%.*]], 16 -; ANYLE-NEXT: [[TMP1:%.*]] = trunc i32 [[EXTELT_OFFSET]] to i16 +; ANYLE-NEXT: [[TMP1:%.*]] = trunc nuw i32 [[EXTELT_OFFSET]] to i16 ; ANYLE-NEXT: [[R:%.*]] = bitcast i16 [[TMP1]] to bfloat ; ANYLE-NEXT: ret bfloat [[R]] ; @@ -511,7 +511,7 @@ define float @bitcast_fp32vec_index0(i64 %x) { ; ; BE64-LABEL: @bitcast_fp32vec_index0( ; BE64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[X:%.*]], 32 -; BE64-NEXT: [[TMP1:%.*]] = trunc i64 [[EXTELT_OFFSET]] to i32 +; BE64-NEXT: [[TMP1:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i32 ; BE64-NEXT: [[R:%.*]] = bitcast i32 [[TMP1]] to float ; BE64-NEXT: ret float [[R]] ; @@ -528,7 +528,7 @@ define float @bitcast_fp32vec_index0(i64 %x) { define float @bitcast_fp32vec_index1(i64 %x) { ; LE64-LABEL: @bitcast_fp32vec_index1( ; LE64-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i64 [[X:%.*]], 32 -; LE64-NEXT: [[TMP1:%.*]] = trunc i64 [[EXTELT_OFFSET]] to i32 +; LE64-NEXT: [[TMP1:%.*]] = trunc nuw i64 [[EXTELT_OFFSET]] to i32 ; LE64-NEXT: [[R:%.*]] = bitcast i32 [[TMP1]] to float ; LE64-NEXT: ret float [[R]] ; @@ -570,7 +570,7 @@ define double @bitcast_fp64vec_index0(i128 %x) { ; ; BE128-LABEL: @bitcast_fp64vec_index0( ; BE128-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i128 [[X:%.*]], 64 -; BE128-NEXT: [[TMP1:%.*]] = trunc i128 [[EXTELT_OFFSET]] to i64 +; BE128-NEXT: [[TMP1:%.*]] = trunc nuw i128 [[EXTELT_OFFSET]] to i64 ; BE128-NEXT: [[R:%.*]] = bitcast i64 [[TMP1]] to double ; BE128-NEXT: ret double [[R]] ; @@ -587,7 +587,7 @@ define double @bitcast_fp64vec_index1(i128 %x) { ; ; LE128-LABEL: @bitcast_fp64vec_index1( ; LE128-NEXT: [[EXTELT_OFFSET:%.*]] = lshr i128 [[X:%.*]], 64 -; LE128-NEXT: [[TMP1:%.*]] = trunc i128 [[EXTELT_OFFSET]] to i64 +; LE128-NEXT: [[TMP1:%.*]] = trunc nuw i128 [[EXTELT_OFFSET]] to i64 ; LE128-NEXT: [[R:%.*]] = bitcast i64 [[TMP1]] to double ; LE128-NEXT: ret double [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/ffs-1.ll b/llvm/test/Transforms/InstCombine/ffs-1.ll index a610376da8b5..7cf080765bb1 100644 --- a/llvm/test/Transforms/InstCombine/ffs-1.ll +++ b/llvm/test/Transforms/InstCombine/ffs-1.ll @@ -181,7 +181,7 @@ define i32 @test_simplify15(i64 %x) { ; ; TARGET-LABEL: @test_simplify15( ; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true), !range !1 -; TARGET-NEXT: [[TMP1:%.*]] = trunc i64 [[CTTZ]] to i32 +; TARGET-NEXT: [[TMP1:%.*]] = trunc nuw nsw i64 [[CTTZ]] to i32 ; TARGET-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1 ; TARGET-NEXT: [[TMP3:%.*]] = icmp eq i64 %x, 0 ; TARGET-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]] diff --git a/llvm/test/Transforms/InstCombine/fls.ll b/llvm/test/Transforms/InstCombine/fls.ll index 8b25a313b6b8..7710093e195a 100644 --- a/llvm/test/Transforms/InstCombine/fls.ll +++ b/llvm/test/Transforms/InstCombine/fls.ll @@ -32,7 +32,7 @@ define i32 @myflsll() { define i32 @flsnotconst(i64 %z) { ; CHECK-LABEL: @flsnotconst( ; CHECK-NEXT: [[CTLZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[Z:%.*]], i1 false), !range [[RNG0:![0-9]+]] -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[CTLZ]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i64 [[CTLZ]] to i32 ; CHECK-NEXT: [[GOO:%.*]] = sub nsw i32 64, [[TMP1]] ; CHECK-NEXT: ret i32 [[GOO]] ; diff --git a/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll b/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll index 434d98449f99..a631aacd97ff 100644 --- a/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll +++ b/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll @@ -282,7 +282,7 @@ define i5 @log2_ceil_idiom_trunc_multiuse4(i32 %x) { ; CHECK-LABEL: define i5 @log2_ceil_idiom_trunc_multiuse4( ; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[CTLZ]] to i5 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw i32 [[CTLZ]] to i5 ; CHECK-NEXT: call void @use5(i5 [[TRUNC]]) ; CHECK-NEXT: [[XOR:%.*]] = xor i5 [[TRUNC]], -1 ; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] diff --git a/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll b/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll index e87d90909e84..3ebab115f654 100644 --- a/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll +++ b/llvm/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll @@ -4,7 +4,7 @@ define i32 @t0(i64 %x) { ; CHECK-LABEL: @t0( ; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63 -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32 +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nsw i64 [[T0_NEG]] to i32 ; CHECK-NEXT: ret i32 [[T1_NEG]] ; %t0 = lshr i64 %x, 63 @@ -15,7 +15,7 @@ define i32 @t0(i64 %x) { define i32 @t1_exact(i64 %x) { ; CHECK-LABEL: @t1_exact( ; CHECK-NEXT: [[T0_NEG:%.*]] = ashr exact i64 [[X:%.*]], 63 -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32 +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nsw i64 [[T0_NEG]] to i32 ; CHECK-NEXT: ret i32 [[T1_NEG]] ; %t0 = lshr exact i64 %x, 63 @@ -26,7 +26,7 @@ define i32 @t1_exact(i64 %x) { define i32 @t2(i64 %x) { ; CHECK-LABEL: @t2( ; CHECK-NEXT: [[T0_NEG:%.*]] = lshr i64 [[X:%.*]], 63 -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32 +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nuw nsw i64 [[T0_NEG]] to i32 ; CHECK-NEXT: ret i32 [[T1_NEG]] ; %t0 = ashr i64 %x, 63 @@ -37,7 +37,7 @@ define i32 @t2(i64 %x) { define i32 @t3_exact(i64 %x) { ; CHECK-LABEL: @t3_exact( ; CHECK-NEXT: [[T0_NEG:%.*]] = lshr exact i64 [[X:%.*]], 63 -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32 +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nuw nsw i64 [[T0_NEG]] to i32 ; CHECK-NEXT: ret i32 [[T1_NEG]] ; %t0 = ashr exact i64 %x, 63 @@ -49,7 +49,7 @@ define i32 @t3_exact(i64 %x) { define <2 x i32> @t4(<2 x i64> %x) { ; CHECK-LABEL: @t4( ; CHECK-NEXT: [[T0_NEG:%.*]] = ashr <2 x i64> [[X:%.*]], -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc <2 x i64> [[T0_NEG]] to <2 x i32> +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nsw <2 x i64> [[T0_NEG]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[T1_NEG]] ; %t0 = lshr <2 x i64> %x, @@ -79,7 +79,7 @@ define i32 @t6(i64 %x) { ; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63 ; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X]], 63 ; CHECK-NEXT: call void @use64(i64 [[T0]]) -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32 +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nsw i64 [[T0_NEG]] to i32 ; CHECK-NEXT: ret i32 [[T1_NEG]] ; %t0 = lshr i64 %x, 63 @@ -92,7 +92,7 @@ define i32 @t6(i64 %x) { define i32 @n7(i64 %x) { ; CHECK-LABEL: @n7( ; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63 -; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32 +; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw i64 [[T0]] to i32 ; CHECK-NEXT: call void @use32(i32 [[T1]]) ; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]] ; CHECK-NEXT: ret i32 [[R]] @@ -108,7 +108,7 @@ define i32 @n8(i64 %x) { ; CHECK-LABEL: @n8( ; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63 ; CHECK-NEXT: call void @use64(i64 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32 +; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw i64 [[T0]] to i32 ; CHECK-NEXT: call void @use32(i32 [[T1]]) ; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]] ; CHECK-NEXT: ret i32 [[R]] @@ -124,7 +124,7 @@ define i32 @n8(i64 %x) { define i32 @n9(i64 %x) { ; CHECK-LABEL: @n9( ; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 62 -; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32 +; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw i64 [[T0]] to i32 ; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]] ; CHECK-NEXT: ret i32 [[R]] ; @@ -137,7 +137,7 @@ define i32 @n9(i64 %x) { define i32 @n10(i64 %x) { ; CHECK-LABEL: @n10( ; CHECK-NEXT: [[T0_NEG:%.*]] = ashr i64 [[X:%.*]], 63 -; CHECK-NEXT: [[T1_NEG:%.*]] = trunc i64 [[T0_NEG]] to i32 +; CHECK-NEXT: [[T1_NEG:%.*]] = trunc nsw i64 [[T0_NEG]] to i32 ; CHECK-NEXT: [[R:%.*]] = add nsw i32 [[T1_NEG]], 1 ; CHECK-NEXT: ret i32 [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll index d858c91becb5..aa23a6d27f69 100644 --- a/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll +++ b/llvm/test/Transforms/InstCombine/icmp-mul-zext.ll @@ -60,7 +60,7 @@ define void @PR33765(i8 %beth) { ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[BETH:%.*]] to i32 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[CONV]], [[CONV]] ; CHECK-NEXT: [[TINKY:%.*]] = load i16, ptr @glob, align 2 -; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[MUL]] to i16 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw i32 [[MUL]] to i16 ; CHECK-NEXT: [[CONV14:%.*]] = and i16 [[TINKY]], [[TMP1]] ; CHECK-NEXT: store i16 [[CONV14]], ptr @glob, align 2 ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll b/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll index 85f67bfa335b..7f616bbb2a83 100644 --- a/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll +++ b/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll @@ -28,8 +28,8 @@ define i1 @icmp_trunc_x_trunc_y_fail_from_illegal1(i256 %x, i256 %y) { ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i256 [[Y:%.*]], 65536 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) -; CHECK-NEXT: [[X16:%.*]] = trunc i256 [[X]] to i16 -; CHECK-NEXT: [[Y16:%.*]] = trunc i256 [[Y]] to i16 +; CHECK-NEXT: [[X16:%.*]] = trunc nuw i256 [[X]] to i16 +; CHECK-NEXT: [[Y16:%.*]] = trunc nuw i256 [[Y]] to i16 ; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[X16]], [[Y16]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -49,7 +49,7 @@ define i1 @icmp_trunc_x_trunc_y_illegal_trunc_to_legal_anyways(i123 %x, i32 %y) ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i32 [[Y:%.*]], 65536 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) -; CHECK-NEXT: [[TMP1:%.*]] = trunc i123 [[X]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i123 [[X]] to i32 ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP1]], [[Y]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -89,7 +89,7 @@ define i1 @icmp_trunc_x_trunc_y_3(i64 %x, i32 %y) { ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i32 [[Y:%.*]], 256 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i64 [[X]] to i32 ; CHECK-NEXT: [[R:%.*]] = icmp uge i32 [[TMP1]], [[Y]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -109,7 +109,7 @@ define i1 @icmp_trunc_x_trunc_y_fail_maybe_dirty_upper(i32 %x, i32 %y) { ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i32 [[Y:%.*]], 65537 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) -; CHECK-NEXT: [[X16:%.*]] = trunc i32 [[X]] to i16 +; CHECK-NEXT: [[X16:%.*]] = trunc nuw i32 [[X]] to i16 ; CHECK-NEXT: [[Y16:%.*]] = trunc i32 [[Y]] to i16 ; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[X16]], [[Y16]] ; CHECK-NEXT: ret i1 [[R]] @@ -131,7 +131,7 @@ define i1 @icmp_trunc_x_trunc_y_fail_maybe_dirty_upper_2(i32 %x, i32 %y) { ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) ; CHECK-NEXT: [[X16:%.*]] = trunc i32 [[X]] to i16 -; CHECK-NEXT: [[Y16:%.*]] = trunc i32 [[Y]] to i16 +; CHECK-NEXT: [[Y16:%.*]] = trunc nuw i32 [[Y]] to i16 ; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[X16]], [[Y16]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -151,7 +151,7 @@ define i1 @icmp_trunc_x_trunc_y_swap0(i33 %x, i32 %y) { ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i32 [[Y:%.*]], 65536 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) -; CHECK-NEXT: [[TMP1:%.*]] = trunc i33 [[X]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i33 [[X]] to i32 ; CHECK-NEXT: [[R:%.*]] = icmp ule i32 [[TMP1]], [[Y]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -171,7 +171,7 @@ define i1 @icmp_trunc_x_trunc_y_swap1(i33 %x, i32 %y) { ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i32 [[Y:%.*]], 65536 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) -; CHECK-NEXT: [[TMP1:%.*]] = trunc i33 [[X]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i33 [[X]] to i32 ; CHECK-NEXT: [[R:%.*]] = icmp uge i32 [[TMP1]], [[Y]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -238,7 +238,7 @@ define i1 @icmp_trunc_x_zext_y_3_fail_illegal(i6 %x, i45 %y) { ; CHECK-NEXT: [[Y_LB_ONLY:%.*]] = icmp ult i45 [[Y:%.*]], 65536 ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_LB_ONLY]]) ; CHECK-NEXT: [[X16:%.*]] = zext i6 [[X:%.*]] to i16 -; CHECK-NEXT: [[Y16:%.*]] = trunc i45 [[Y]] to i16 +; CHECK-NEXT: [[Y16:%.*]] = trunc nuw i45 [[Y]] to i16 ; CHECK-NEXT: [[R:%.*]] = icmp ne i16 [[Y16]], [[X16]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -254,7 +254,7 @@ define i1 @icmp_trunc_x_zext_y_fail_multiuse(i32 %x, i8 %y) { ; CHECK-LABEL: @icmp_trunc_x_zext_y_fail_multiuse( ; CHECK-NEXT: [[X_LB_ONLY:%.*]] = icmp ult i32 [[X:%.*]], 65536 ; CHECK-NEXT: call void @llvm.assume(i1 [[X_LB_ONLY]]) -; CHECK-NEXT: [[X16:%.*]] = trunc i32 [[X]] to i16 +; CHECK-NEXT: [[X16:%.*]] = trunc nuw i32 [[X]] to i16 ; CHECK-NEXT: [[Y16:%.*]] = zext i8 [[Y:%.*]] to i16 ; CHECK-NEXT: call void @use(i16 [[Y16]]) ; CHECK-NEXT: [[R:%.*]] = icmp ule i16 [[X16]], [[Y16]] diff --git a/llvm/test/Transforms/InstCombine/icmp-topbitssame.ll b/llvm/test/Transforms/InstCombine/icmp-topbitssame.ll index 284dc036d11d..4e11ecbcb889 100644 --- a/llvm/test/Transforms/InstCombine/icmp-topbitssame.ll +++ b/llvm/test/Transforms/InstCombine/icmp-topbitssame.ll @@ -128,7 +128,7 @@ define i1 @wrongimm1(i16 %add) { define i1 @wrongimm2(i16 %add) { ; CHECK-LABEL: @wrongimm2( ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i16 [[SH]] to i8 ; CHECK-NEXT: [[CONV1_I:%.*]] = trunc i16 [[ADD]] to i8 ; CHECK-NEXT: [[SHR2_I:%.*]] = ashr i8 [[CONV1_I]], 6 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[SHR2_I]], [[CONV_I]] @@ -145,7 +145,7 @@ define i1 @wrongimm2(i16 %add) { define i1 @slt(i64 %add) { ; CHECK-LABEL: @slt( ; CHECK-NEXT: [[SH:%.*]] = lshr i64 [[ADD:%.*]], 32 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[SH]] to i32 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i64 [[SH]] to i32 ; CHECK-NEXT: [[CONV1_I:%.*]] = trunc i64 [[ADD]] to i32 ; CHECK-NEXT: [[SHR2_I:%.*]] = ashr i32 [[CONV1_I]], 31 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp slt i32 [[SHR2_I]], [[CONV_I]] @@ -182,7 +182,7 @@ define i1 @extrause_a(i16 %add) { define i1 @extrause_l(i16 %add) { ; CHECK-LABEL: @extrause_l( ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i16 [[SH]] to i8 ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD]], 128 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i16 [[TMP1]], 256 ; CHECK-NEXT: call void @use(i8 [[CONV_I]]) @@ -200,7 +200,7 @@ define i1 @extrause_l(i16 %add) { define i1 @extrause_la(i16 %add) { ; CHECK-LABEL: @extrause_la( ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i16 [[SH]] to i8 ; CHECK-NEXT: [[CONV1_I:%.*]] = trunc i16 [[ADD]] to i8 ; CHECK-NEXT: [[SHR2_I:%.*]] = ashr i8 [[CONV1_I]], 7 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[SHR2_I]], [[CONV_I]] diff --git a/llvm/test/Transforms/InstCombine/insert-trunc.ll b/llvm/test/Transforms/InstCombine/insert-trunc.ll index 3ae128e55b43..3a160513ccb1 100644 --- a/llvm/test/Transforms/InstCombine/insert-trunc.ll +++ b/llvm/test/Transforms/InstCombine/insert-trunc.ll @@ -146,7 +146,7 @@ define <4 x i16> @lshr_same_length_poison_basevec_be(i64 %x) { define <4 x i16> @lshr_same_length_poison_basevec_both_endian(i64 %x) { ; ALL-LABEL: @lshr_same_length_poison_basevec_both_endian( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 48 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i16 +; ALL-NEXT: [[T:%.*]] = trunc nuw i64 [[S]] to i16 ; ALL-NEXT: [[R:%.*]] = insertelement <4 x i16> poison, i16 [[T]], i64 0 ; ALL-NEXT: ret <4 x i16> [[R]] ; @@ -159,7 +159,7 @@ define <4 x i16> @lshr_same_length_poison_basevec_both_endian(i64 %x) { define <4 x i16> @lshr_wrong_index_same_length_poison_basevec(i64 %x) { ; ALL-LABEL: @lshr_wrong_index_same_length_poison_basevec( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 48 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i16 +; ALL-NEXT: [[T:%.*]] = trunc nuw i64 [[S]] to i16 ; ALL-NEXT: [[R:%.*]] = insertelement <4 x i16> poison, i16 [[T]], i64 1 ; ALL-NEXT: ret <4 x i16> [[R]] ; @@ -172,7 +172,7 @@ define <4 x i16> @lshr_wrong_index_same_length_poison_basevec(i64 %x) { define <8 x i16> @lshr_longer_length_poison_basevec_le(i64 %x) { ; ALL-LABEL: @lshr_longer_length_poison_basevec_le( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 48 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i16 +; ALL-NEXT: [[T:%.*]] = trunc nuw i64 [[S]] to i16 ; ALL-NEXT: [[R:%.*]] = insertelement <8 x i16> poison, i16 [[T]], i64 3 ; ALL-NEXT: ret <8 x i16> [[R]] ; @@ -250,7 +250,7 @@ define <4 x i8> @lshr_wrong_index_shorter_length_poison_basevec(i64 %x) { define <4 x i8> @lshr_wrong_shift_shorter_length_poison_basevec(i64 %x) { ; ALL-LABEL: @lshr_wrong_shift_shorter_length_poison_basevec( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 57 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i8 +; ALL-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[S]] to i8 ; ALL-NEXT: [[R:%.*]] = insertelement <4 x i8> poison, i8 [[T]], i64 0 ; ALL-NEXT: ret <4 x i8> [[R]] ; @@ -392,7 +392,7 @@ define <4 x i16> @lshr_same_length_basevec_be(i64 %x, <4 x i16> %v) { define <4 x i16> @lshr_same_length_basevec_both_endian(i64 %x, <4 x i16> %v) { ; ALL-LABEL: @lshr_same_length_basevec_both_endian( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 48 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i16 +; ALL-NEXT: [[T:%.*]] = trunc nuw i64 [[S]] to i16 ; ALL-NEXT: [[R:%.*]] = insertelement <4 x i16> [[V:%.*]], i16 [[T]], i64 3 ; ALL-NEXT: ret <4 x i16> [[R]] ; @@ -405,7 +405,7 @@ define <4 x i16> @lshr_same_length_basevec_both_endian(i64 %x, <4 x i16> %v) { define <4 x i16> @lshr_wrong_index_same_length_basevec(i64 %x, <4 x i16> %v) { ; ALL-LABEL: @lshr_wrong_index_same_length_basevec( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 48 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i16 +; ALL-NEXT: [[T:%.*]] = trunc nuw i64 [[S]] to i16 ; ALL-NEXT: [[R:%.*]] = insertelement <4 x i16> [[V:%.*]], i16 [[T]], i64 1 ; ALL-NEXT: ret <4 x i16> [[R]] ; @@ -418,7 +418,7 @@ define <4 x i16> @lshr_wrong_index_same_length_basevec(i64 %x, <4 x i16> %v) { define <8 x i16> @lshr_longer_length_basevec_le(i64 %x, <8 x i16> %v) { ; ALL-LABEL: @lshr_longer_length_basevec_le( ; ALL-NEXT: [[S:%.*]] = lshr i64 [[X:%.*]], 48 -; ALL-NEXT: [[T:%.*]] = trunc i64 [[S]] to i16 +; ALL-NEXT: [[T:%.*]] = trunc nuw i64 [[S]] to i16 ; ALL-NEXT: [[R:%.*]] = insertelement <8 x i16> [[V:%.*]], i16 [[T]], i64 3 ; ALL-NEXT: ret <8 x i16> [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/insertelt-trunc.ll b/llvm/test/Transforms/InstCombine/insertelt-trunc.ll index a2721bf13e74..f5f1051ea201 100644 --- a/llvm/test/Transforms/InstCombine/insertelt-trunc.ll +++ b/llvm/test/Transforms/InstCombine/insertelt-trunc.ll @@ -9,7 +9,7 @@ declare void @use_vec(<8 x i16>) define <4 x i16> @insert_01_poison_v4i16(i32 %x) { ; BE-LABEL: @insert_01_poison_v4i16( ; BE-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; BE-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; BE-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; BE-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; BE-NEXT: [[INS0:%.*]] = insertelement <4 x i16> poison, i16 [[LO16]], i64 0 ; BE-NEXT: [[INS1:%.*]] = insertelement <4 x i16> [[INS0]], i16 [[HI16]], i64 1 @@ -36,7 +36,7 @@ define <8 x i16> @insert_10_poison_v8i16(i32 %x) { ; ; LE-LABEL: @insert_10_poison_v8i16( ; LE-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; LE-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; LE-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; LE-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; LE-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> poison, i16 [[HI16]], i64 0 ; LE-NEXT: [[INS1:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[LO16]], i64 1 @@ -55,7 +55,7 @@ define <8 x i16> @insert_10_poison_v8i16(i32 %x) { define <4 x i32> @insert_12_poison_v4i32(i64 %x) { ; ALL-LABEL: @insert_12_poison_v4i32( ; ALL-NEXT: [[HI64:%.*]] = lshr i64 [[X:%.*]], 32 -; ALL-NEXT: [[HI32:%.*]] = trunc i64 [[HI64]] to i32 +; ALL-NEXT: [[HI32:%.*]] = trunc nuw i64 [[HI64]] to i32 ; ALL-NEXT: [[LO32:%.*]] = trunc i64 [[X]] to i32 ; ALL-NEXT: [[INS0:%.*]] = insertelement <4 x i32> poison, i32 [[LO32]], i64 1 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i32> [[INS0]], i32 [[HI32]], i64 2 @@ -74,7 +74,7 @@ define <4 x i32> @insert_12_poison_v4i32(i64 %x) { define <4 x i16> @insert_21_poison_v4i16(i32 %x) { ; ALL-LABEL: @insert_21_poison_v4i16( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[HI16]], i64 1 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[LO16]], i64 2 @@ -91,7 +91,7 @@ define <4 x i16> @insert_21_poison_v4i16(i32 %x) { define <4 x i32> @insert_23_poison_v4i32(i64 %x) { ; BE-LABEL: @insert_23_poison_v4i32( ; BE-NEXT: [[HI64:%.*]] = lshr i64 [[X:%.*]], 32 -; BE-NEXT: [[HI32:%.*]] = trunc i64 [[HI64]] to i32 +; BE-NEXT: [[HI32:%.*]] = trunc nuw i64 [[HI64]] to i32 ; BE-NEXT: [[LO32:%.*]] = trunc i64 [[X]] to i32 ; BE-NEXT: [[INS0:%.*]] = insertelement <4 x i32> poison, i32 [[LO32]], i64 2 ; BE-NEXT: [[INS1:%.*]] = insertelement <4 x i32> [[INS0]], i32 [[HI32]], i64 3 @@ -118,7 +118,7 @@ define <4 x i16> @insert_32_poison_v4i16(i32 %x) { ; ; LE-LABEL: @insert_32_poison_v4i16( ; LE-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; LE-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; LE-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; LE-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; LE-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[HI16]], i64 2 ; LE-NEXT: [[INS1:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[LO16]], i64 3 @@ -140,7 +140,7 @@ define <4 x i16> @insert_32_poison_v4i16(i32 %x) { define <2 x i16> @insert_01_v2i16(i32 %x, <2 x i16> %v) { ; BE-LABEL: @insert_01_v2i16( ; BE-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; BE-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; BE-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; BE-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; BE-NEXT: [[INS0:%.*]] = insertelement <2 x i16> poison, i16 [[LO16]], i64 0 ; BE-NEXT: [[INS1:%.*]] = insertelement <2 x i16> [[INS0]], i16 [[HI16]], i64 1 @@ -163,7 +163,7 @@ define <2 x i16> @insert_01_v2i16(i32 %x, <2 x i16> %v) { define <8 x i16> @insert_10_v8i16(i32 %x, <8 x i16> %v) { ; ALL-LABEL: @insert_10_v8i16( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[V:%.*]], i16 [[HI16]], i64 0 ; ALL-NEXT: [[INS1:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[LO16]], i64 1 @@ -182,7 +182,7 @@ define <8 x i16> @insert_10_v8i16(i32 %x, <8 x i16> %v) { define <4 x i32> @insert_12_v4i32(i64 %x, <4 x i32> %v) { ; ALL-LABEL: @insert_12_v4i32( ; ALL-NEXT: [[HI64:%.*]] = lshr i64 [[X:%.*]], 32 -; ALL-NEXT: [[HI32:%.*]] = trunc i64 [[HI64]] to i32 +; ALL-NEXT: [[HI32:%.*]] = trunc nuw i64 [[HI64]] to i32 ; ALL-NEXT: [[LO32:%.*]] = trunc i64 [[X]] to i32 ; ALL-NEXT: [[INS0:%.*]] = insertelement <4 x i32> [[V:%.*]], i32 [[LO32]], i64 1 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i32> [[INS0]], i32 [[HI32]], i64 2 @@ -201,7 +201,7 @@ define <4 x i32> @insert_12_v4i32(i64 %x, <4 x i32> %v) { define <4 x i16> @insert_21_v4i16(i32 %x, <4 x i16> %v) { ; ALL-LABEL: @insert_21_v4i16( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[V:%.*]], i16 [[HI16]], i64 1 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[LO16]], i64 2 @@ -220,7 +220,7 @@ define <4 x i16> @insert_21_v4i16(i32 %x, <4 x i16> %v) { define <4 x i32> @insert_23_v4i32(i64 %x, <4 x i32> %v) { ; ALL-LABEL: @insert_23_v4i32( ; ALL-NEXT: [[HI64:%.*]] = lshr i64 [[X:%.*]], 32 -; ALL-NEXT: [[HI32:%.*]] = trunc i64 [[HI64]] to i32 +; ALL-NEXT: [[HI32:%.*]] = trunc nuw i64 [[HI64]] to i32 ; ALL-NEXT: [[LO32:%.*]] = trunc i64 [[X]] to i32 ; ALL-NEXT: [[INS0:%.*]] = insertelement <4 x i32> [[V:%.*]], i32 [[LO32]], i64 2 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i32> [[INS0]], i32 [[HI32]], i64 3 @@ -239,7 +239,7 @@ define <4 x i32> @insert_23_v4i32(i64 %x, <4 x i32> %v) { define <4 x i16> @insert_32_v4i16(i32 %x, <4 x i16> %v) { ; ALL-LABEL: @insert_32_v4i16( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[V:%.*]], i16 [[HI16]], i64 2 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[LO16]], i64 3 @@ -277,7 +277,7 @@ define <4 x i16> @insert_01_v4i16_wrong_shift1(i32 %x) { define <4 x i16> @insert_01_v4i16_wrong_op(i32 %x, i32 %y) { ; ALL-LABEL: @insert_01_v4i16_wrong_op( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[Y:%.*]] to i16 ; ALL-NEXT: [[INS0:%.*]] = insertelement <4 x i16> poison, i16 [[LO16]], i64 0 ; ALL-NEXT: [[INS1:%.*]] = insertelement <4 x i16> [[INS0]], i16 [[HI16]], i64 1 @@ -296,7 +296,7 @@ define <4 x i16> @insert_01_v4i16_wrong_op(i32 %x, i32 %y) { define <8 x i16> @insert_67_v4i16_uses1(i32 %x, <8 x i16> %v) { ; ALL-LABEL: @insert_67_v4i16_uses1( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: call void @use(i16 [[HI16]]) ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: [[INS0:%.*]] = insertelement <8 x i16> [[V:%.*]], i16 [[LO16]], i64 6 @@ -318,7 +318,7 @@ define <8 x i16> @insert_67_v4i16_uses1(i32 %x, <8 x i16> %v) { define <8 x i16> @insert_76_v4i16_uses2(i32 %x, <8 x i16> %v) { ; ALL-LABEL: @insert_76_v4i16_uses2( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: call void @use(i16 [[LO16]]) ; ALL-NEXT: [[TMP1:%.*]] = insertelement <8 x i16> [[V:%.*]], i16 [[HI16]], i64 6 @@ -339,7 +339,7 @@ define <8 x i16> @insert_76_v4i16_uses2(i32 %x, <8 x i16> %v) { define <8 x i16> @insert_67_v4i16_uses3(i32 %x, <8 x i16> %v) { ; ALL-LABEL: @insert_67_v4i16_uses3( ; ALL-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; ALL-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; ALL-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; ALL-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; ALL-NEXT: [[INS0:%.*]] = insertelement <8 x i16> [[V:%.*]], i16 [[LO16]], i64 6 ; ALL-NEXT: call void @use_vec(<8 x i16> [[INS0]]) @@ -360,7 +360,7 @@ define <8 x i16> @insert_67_v4i16_uses3(i32 %x, <8 x i16> %v) { define <4 x i16> @insert_01_poison_v4i16_high_first(i32 %x) { ; BE-LABEL: @insert_01_poison_v4i16_high_first( ; BE-NEXT: [[HI32:%.*]] = lshr i32 [[X:%.*]], 16 -; BE-NEXT: [[HI16:%.*]] = trunc i32 [[HI32]] to i16 +; BE-NEXT: [[HI16:%.*]] = trunc nuw i32 [[HI32]] to i16 ; BE-NEXT: [[LO16:%.*]] = trunc i32 [[X]] to i16 ; BE-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[LO16]], i64 0 ; BE-NEXT: [[INS0:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[HI16]], i64 1 diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll index e27e4a3eddfb..d210b19bb7fa 100644 --- a/llvm/test/Transforms/InstCombine/known-bits.ll +++ b/llvm/test/Transforms/InstCombine/known-bits.ll @@ -455,7 +455,7 @@ define i64 @test_icmp_trunc5(i64 %n) { ; CHECK-LABEL: @test_icmp_trunc5( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[N:%.*]], 47 -; CHECK-NEXT: [[CONV1:%.*]] = trunc i64 [[SHR]] to i32 +; CHECK-NEXT: [[CONV1:%.*]] = trunc nsw i64 [[SHR]] to i32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CONV1]], -13 ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] ; CHECK: if.then: diff --git a/llvm/test/Transforms/InstCombine/known-non-zero.ll b/llvm/test/Transforms/InstCombine/known-non-zero.ll index 7965b47911c4..f1c757cafefb 100644 --- a/llvm/test/Transforms/InstCombine/known-non-zero.ll +++ b/llvm/test/Transforms/InstCombine/known-non-zero.ll @@ -14,7 +14,7 @@ define i32 @test0(i64 %x) { ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: ; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.cttz.i64(i64 [[X]], i1 true), !range [[RNG0:![0-9]+]] -; CHECK-NEXT: [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32 +; CHECK-NEXT: [[CTZ32:%.*]] = trunc nuw nsw i64 [[CTZ]] to i32 ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[CTZ32]], [[NON_ZERO]] ], [ 0, [[START:%.*]] ] @@ -41,7 +41,7 @@ define i32 @test1(i64 %x) { ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: ; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] -; CHECK-NEXT: [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32 +; CHECK-NEXT: [[CTZ32:%.*]] = trunc nuw nsw i64 [[CTZ]] to i32 ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[CTZ32]], [[NON_ZERO]] ], [ 0, [[START:%.*]] ] diff --git a/llvm/test/Transforms/InstCombine/known-phi-recurse.ll b/llvm/test/Transforms/InstCombine/known-phi-recurse.ll index 78654155c36c..d33e08ffaf9b 100644 --- a/llvm/test/Transforms/InstCombine/known-phi-recurse.ll +++ b/llvm/test/Transforms/InstCombine/known-phi-recurse.ll @@ -17,7 +17,7 @@ define i32 @single_entry_phi(i64 %x, i1 %c) { ; CHECK-NEXT: br i1 [[C:%.*]], label [[END:%.*]], label [[BODY]] ; CHECK: end: ; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0:![0-9]+]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[Y]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: ret i32 [[TRUNC]] ; entry: @@ -37,7 +37,7 @@ define i32 @two_entry_phi_with_constant(i64 %x, i1 %c) { ; CHECK-LABEL: @two_entry_phi_with_constant( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[Y]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: br i1 [[C:%.*]], label [[END:%.*]], label [[BODY:%.*]] ; CHECK: body: ; CHECK-NEXT: br label [[END]] @@ -62,11 +62,11 @@ define i32 @two_entry_phi_non_constant(i64 %x, i64 %x2, i1 %c) { ; CHECK-LABEL: @two_entry_phi_non_constant( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[Y]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: br i1 [[C:%.*]], label [[END:%.*]], label [[BODY:%.*]] ; CHECK: body: ; CHECK-NEXT: [[Y2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X2:%.*]]), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC2:%.*]] = trunc i64 [[Y2]] to i32 +; CHECK-NEXT: [[TRUNC2:%.*]] = trunc nuw nsw i64 [[Y2]] to i32 ; CHECK-NEXT: br label [[END]] ; CHECK: end: ; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[TRUNC]], [[ENTRY:%.*]] ], [ [[TRUNC2]], [[BODY]] ] @@ -91,12 +91,12 @@ define i32 @neg_many_branches(i64 %x) { ; CHECK-LABEL: @neg_many_branches( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0]] -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[Y]] to i32 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: switch i32 [[TRUNC]], label [[END:%.*]] [ -; CHECK-NEXT: i32 1, label [[ONE:%.*]] -; CHECK-NEXT: i32 2, label [[TWO:%.*]] -; CHECK-NEXT: i32 3, label [[THREE:%.*]] -; CHECK-NEXT: i32 4, label [[FOUR:%.*]] +; CHECK-NEXT: i32 1, label [[ONE:%.*]] +; CHECK-NEXT: i32 2, label [[TWO:%.*]] +; CHECK-NEXT: i32 3, label [[THREE:%.*]] +; CHECK-NEXT: i32 4, label [[FOUR:%.*]] ; CHECK-NEXT: ] ; CHECK: one: ; CHECK-NEXT: [[A:%.*]] = add nuw nsw i32 [[TRUNC]], 1 diff --git a/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll b/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll index b3d147621b59..20d60206ebcd 100644 --- a/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/logical-select-inseltpoison.ll @@ -647,7 +647,7 @@ define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> % ; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> ; CHECK-NEXT: [[S4:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> ; CHECK-NEXT: [[SHUF_OR2:%.*]] = or <4 x i32> [[S3]], [[S4]] -; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[SHUF_OR2]] to <4 x i1> +; CHECK-NEXT: [[TMP1:%.*]] = trunc nsw <4 x i32> [[SHUF_OR2]] to <4 x i1> ; CHECK-NEXT: [[SEL_V:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[Z:%.*]], <4 x float> [[X]] ; CHECK-NEXT: [[SEL:%.*]] = bitcast <4 x float> [[SEL_V]] to <4 x i32> ; CHECK-NEXT: ret <4 x i32> [[SEL]] diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll index c850b87bb2dd..6e2ed6bf796d 100644 --- a/llvm/test/Transforms/InstCombine/logical-select.ll +++ b/llvm/test/Transforms/InstCombine/logical-select.ll @@ -683,7 +683,7 @@ define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> % ; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> ; CHECK-NEXT: [[S4:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> ; CHECK-NEXT: [[SHUF_OR2:%.*]] = or <4 x i32> [[S3]], [[S4]] -; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[SHUF_OR2]] to <4 x i1> +; CHECK-NEXT: [[TMP1:%.*]] = trunc nsw <4 x i32> [[SHUF_OR2]] to <4 x i1> ; CHECK-NEXT: [[SEL_V:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[Z:%.*]], <4 x float> [[X]] ; CHECK-NEXT: [[SEL:%.*]] = bitcast <4 x float> [[SEL_V]] to <4 x i32> ; CHECK-NEXT: ret <4 x i32> [[SEL]] diff --git a/llvm/test/Transforms/InstCombine/lshr-trunc-sext-to-ashr-sext.ll b/llvm/test/Transforms/InstCombine/lshr-trunc-sext-to-ashr-sext.ll index 8d82213d8022..8e7491ee4037 100644 --- a/llvm/test/Transforms/InstCombine/lshr-trunc-sext-to-ashr-sext.ll +++ b/llvm/test/Transforms/InstCombine/lshr-trunc-sext-to-ashr-sext.ll @@ -91,7 +91,7 @@ define <2 x i16> @t5_vec_undef(<2 x i8> %x) { define i16 @t6_extrause0(i8 %x) { ; CHECK-LABEL: @t6_extrause0( ; CHECK-NEXT: [[A:%.*]] = lshr i8 [[X:%.*]], 4 -; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i4 +; CHECK-NEXT: [[B:%.*]] = trunc nuw i8 [[A]] to i4 ; CHECK-NEXT: call void @use4(i4 [[B]]) ; CHECK-NEXT: [[C:%.*]] = sext i4 [[B]] to i16 ; CHECK-NEXT: ret i16 [[C]] @@ -157,7 +157,7 @@ define i16 @t10_extrause2(i8 %x) { ; CHECK-LABEL: @t10_extrause2( ; CHECK-NEXT: [[A:%.*]] = lshr i8 [[X:%.*]], 4 ; CHECK-NEXT: call void @use8(i8 [[A]]) -; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i4 +; CHECK-NEXT: [[B:%.*]] = trunc nuw i8 [[A]] to i4 ; CHECK-NEXT: call void @use4(i4 [[B]]) ; CHECK-NEXT: [[C:%.*]] = sext i4 [[B]] to i16 ; CHECK-NEXT: ret i16 [[C]] @@ -189,7 +189,7 @@ define <2 x i16> @t11_extrause2_vec_undef(<2 x i8> %x) { define <2 x i10> @wide_source_shifted_signbit(<2 x i32> %x) { ; CHECK-LABEL: @wide_source_shifted_signbit( ; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[C:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i10> +; CHECK-NEXT: [[C:%.*]] = trunc nsw <2 x i32> [[TMP1]] to <2 x i10> ; CHECK-NEXT: ret <2 x i10> [[C]] ; %a = lshr <2 x i32> %x, @@ -203,7 +203,7 @@ define i10 @wide_source_shifted_signbit_use1(i32 %x) { ; CHECK-NEXT: [[A:%.*]] = lshr i32 [[X:%.*]], 24 ; CHECK-NEXT: call void @use32(i32 [[A]]) ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X]], 24 -; CHECK-NEXT: [[C:%.*]] = trunc i32 [[TMP1]] to i10 +; CHECK-NEXT: [[C:%.*]] = trunc nsw i32 [[TMP1]] to i10 ; CHECK-NEXT: ret i10 [[C]] ; %a = lshr i32 %x, 24 @@ -216,7 +216,7 @@ define i10 @wide_source_shifted_signbit_use1(i32 %x) { define i10 @wide_source_shifted_signbit_use2(i32 %x) { ; CHECK-LABEL: @wide_source_shifted_signbit_use2( ; CHECK-NEXT: [[A:%.*]] = lshr i32 [[X:%.*]], 24 -; CHECK-NEXT: [[B:%.*]] = trunc i32 [[A]] to i8 +; CHECK-NEXT: [[B:%.*]] = trunc nuw i32 [[A]] to i8 ; CHECK-NEXT: call void @use8(i8 [[B]]) ; CHECK-NEXT: [[C:%.*]] = sext i8 [[B]] to i10 ; CHECK-NEXT: ret i10 [[C]] @@ -256,7 +256,7 @@ define i32 @same_source_shifted_signbit_use1(i32 %x) { define i32 @same_source_shifted_signbit_use2(i32 %x) { ; CHECK-LABEL: @same_source_shifted_signbit_use2( ; CHECK-NEXT: [[A:%.*]] = lshr i32 [[X:%.*]], 24 -; CHECK-NEXT: [[B:%.*]] = trunc i32 [[A]] to i8 +; CHECK-NEXT: [[B:%.*]] = trunc nuw i32 [[A]] to i8 ; CHECK-NEXT: call void @use8(i8 [[B]]) ; CHECK-NEXT: [[C:%.*]] = sext i8 [[B]] to i32 ; CHECK-NEXT: ret i32 [[C]] diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll index 02c2bbc2819b..7d611ba188d6 100644 --- a/llvm/test/Transforms/InstCombine/lshr.ll +++ b/llvm/test/Transforms/InstCombine/lshr.ll @@ -476,7 +476,7 @@ define i32 @srem2_lshr30(i32 %x) { define i12 @trunc_sandwich(i32 %x) { ; CHECK-LABEL: @trunc_sandwich( ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X:%.*]], 30 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 28 @@ -488,7 +488,7 @@ define i12 @trunc_sandwich(i32 %x) { define <2 x i12> @trunc_sandwich_splat_vec(<2 x i32> %x) { ; CHECK-LABEL: @trunc_sandwich_splat_vec( ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[R1:%.*]] = trunc <2 x i32> [[SUM_SHIFT]] to <2 x i12> +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw <2 x i32> [[SUM_SHIFT]] to <2 x i12> ; CHECK-NEXT: ret <2 x i12> [[R1]] ; %sh = lshr <2 x i32> %x, @@ -500,7 +500,7 @@ define <2 x i12> @trunc_sandwich_splat_vec(<2 x i32> %x) { define i12 @trunc_sandwich_min_shift1(i32 %x) { ; CHECK-LABEL: @trunc_sandwich_min_shift1( ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X:%.*]], 21 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 20 @@ -512,7 +512,7 @@ define i12 @trunc_sandwich_min_shift1(i32 %x) { define i12 @trunc_sandwich_small_shift1(i32 %x) { ; CHECK-LABEL: @trunc_sandwich_small_shift1( ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X:%.*]], 20 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: [[R:%.*]] = and i12 [[R1]], 2047 ; CHECK-NEXT: ret i12 [[R]] ; @@ -525,7 +525,7 @@ define i12 @trunc_sandwich_small_shift1(i32 %x) { define i12 @trunc_sandwich_max_sum_shift(i32 %x) { ; CHECK-LABEL: @trunc_sandwich_max_sum_shift( ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 20 @@ -537,7 +537,7 @@ define i12 @trunc_sandwich_max_sum_shift(i32 %x) { define i12 @trunc_sandwich_max_sum_shift2(i32 %x) { ; CHECK-LABEL: @trunc_sandwich_max_sum_shift2( ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 30 @@ -571,7 +571,7 @@ define i12 @trunc_sandwich_use1(i32 %x) { ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 28 ; CHECK-NEXT: call void @use(i32 [[SH]]) ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X]], 30 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 28 @@ -586,7 +586,7 @@ define <3 x i9> @trunc_sandwich_splat_vec_use1(<3 x i14> %x) { ; CHECK-NEXT: [[SH:%.*]] = lshr <3 x i14> [[X:%.*]], ; CHECK-NEXT: call void @usevec(<3 x i14> [[SH]]) ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr <3 x i14> [[X]], -; CHECK-NEXT: [[R1:%.*]] = trunc <3 x i14> [[SUM_SHIFT]] to <3 x i9> +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw <3 x i14> [[SUM_SHIFT]] to <3 x i9> ; CHECK-NEXT: ret <3 x i9> [[R1]] ; %sh = lshr <3 x i14> %x, @@ -601,7 +601,7 @@ define i12 @trunc_sandwich_min_shift1_use1(i32 %x) { ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 20 ; CHECK-NEXT: call void @use(i32 [[SH]]) ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X]], 21 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 20 @@ -633,7 +633,7 @@ define i12 @trunc_sandwich_max_sum_shift_use1(i32 %x) { ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 20 ; CHECK-NEXT: call void @use(i32 [[SH]]) ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X]], 31 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 20 @@ -648,7 +648,7 @@ define i12 @trunc_sandwich_max_sum_shift2_use1(i32 %x) { ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 30 ; CHECK-NEXT: call void @use(i32 [[SH]]) ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i32 [[X]], 31 -; CHECK-NEXT: [[R1:%.*]] = trunc i32 [[SUM_SHIFT]] to i12 +; CHECK-NEXT: [[R1:%.*]] = trunc nuw nsw i32 [[SUM_SHIFT]] to i12 ; CHECK-NEXT: ret i12 [[R1]] ; %sh = lshr i32 %x, 30 diff --git a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll index 58174f21f767..866381ff2887 100644 --- a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll +++ b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll @@ -320,7 +320,7 @@ define void @pr46688(i1 %cond, i32 %x, i16 %d, ptr %p1, ptr %p2) { ; CHECK-NEXT: [[THR1_PN:%.*]] = lshr i32 [[THR_PN]], [[X]] ; CHECK-NEXT: [[THR2_PN:%.*]] = lshr i32 [[THR1_PN]], [[X]] ; CHECK-NEXT: [[STOREMERGE:%.*]] = lshr i32 [[THR2_PN]], [[X]] -; CHECK-NEXT: [[STOREMERGE1:%.*]] = trunc i32 [[STOREMERGE]] to i16 +; CHECK-NEXT: [[STOREMERGE1:%.*]] = trunc nuw i32 [[STOREMERGE]] to i16 ; CHECK-NEXT: store i16 [[STOREMERGE1]], ptr [[P1:%.*]], align 2 ; CHECK-NEXT: store i32 [[STOREMERGE]], ptr [[P2:%.*]], align 4 ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/InstCombine/narrow.ll b/llvm/test/Transforms/InstCombine/narrow.ll index 781974d33bf1..40229f8511f7 100644 --- a/llvm/test/Transforms/InstCombine/narrow.ll +++ b/llvm/test/Transforms/InstCombine/narrow.ll @@ -76,7 +76,7 @@ define <2 x i8> @shrink_or_vec(<2 x i16> %a) { define i31 @shrink_and(i64 %a) { ; CHECK-LABEL: @shrink_and( ; CHECK-NEXT: [[AND:%.*]] = and i64 [[A:%.*]], 42 -; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[AND]] to i31 +; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[AND]] to i31 ; CHECK-NEXT: ret i31 [[TRUNC]] ; %and = and i64 %a, 42 diff --git a/llvm/test/Transforms/InstCombine/negated-bitmask.ll b/llvm/test/Transforms/InstCombine/negated-bitmask.ll index fe2386bd65c3..918867818634 100644 --- a/llvm/test/Transforms/InstCombine/negated-bitmask.ll +++ b/llvm/test/Transforms/InstCombine/negated-bitmask.ll @@ -70,7 +70,7 @@ define i8 @sub_mask1_trunc_lshr(i64 %a0) { ; CHECK-LABEL: @sub_mask1_trunc_lshr( ; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[A0:%.*]], 48 ; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP1]], 63 -; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8 +; CHECK-NEXT: [[TMP3:%.*]] = trunc nsw i64 [[TMP2]] to i8 ; CHECK-NEXT: [[NEG:%.*]] = add nsw i8 [[TMP3]], 10 ; CHECK-NEXT: ret i8 [[NEG]] ; @@ -85,7 +85,7 @@ define i32 @sub_sext_mask1_trunc_lshr(i64 %a0) { ; CHECK-LABEL: @sub_sext_mask1_trunc_lshr( ; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[A0:%.*]], 48 ; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[TMP1]], 63 -; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8 +; CHECK-NEXT: [[TMP3:%.*]] = trunc nsw i64 [[TMP2]] to i8 ; CHECK-NEXT: [[NARROW:%.*]] = add nsw i8 [[TMP3]], 10 ; CHECK-NEXT: [[NEG:%.*]] = zext i8 [[NARROW]] to i32 ; CHECK-NEXT: ret i32 [[NEG]] diff --git a/llvm/test/Transforms/InstCombine/pr34349.ll b/llvm/test/Transforms/InstCombine/pr34349.ll index ea4afaa245c6..89947650b26b 100644 --- a/llvm/test/Transforms/InstCombine/pr34349.ll +++ b/llvm/test/Transforms/InstCombine/pr34349.ll @@ -7,7 +7,7 @@ define i8 @fast_div_201(i8 %p) { ; CHECK-NEXT: [[V3:%.*]] = zext i8 [[P:%.*]] to i16 ; CHECK-NEXT: [[V4:%.*]] = mul nuw nsw i16 [[V3]], 71 ; CHECK-NEXT: [[V5:%.*]] = lshr i16 [[V4]], 8 -; CHECK-NEXT: [[V6:%.*]] = trunc i16 [[V5]] to i8 +; CHECK-NEXT: [[V6:%.*]] = trunc nuw nsw i16 [[V5]] to i8 ; CHECK-NEXT: [[V7:%.*]] = sub i8 [[P]], [[V6]] ; CHECK-NEXT: [[V8:%.*]] = lshr i8 [[V7]], 1 ; CHECK-NEXT: [[V13:%.*]] = add nuw i8 [[V8]], [[V6]] diff --git a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll index ad55b506a108..b94be990199b 100644 --- a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll +++ b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll @@ -53,7 +53,7 @@ define i8 @reduce_add_zext_long(<128 x i1> %x) { ; CHECK-LABEL: @reduce_add_zext_long( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]] -; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8 +; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i8 ; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]] ; CHECK-NEXT: ret i8 [[RES]] ; @@ -67,7 +67,7 @@ define i8 @reduce_add_zext_long_external_use(<128 x i1> %x) { ; CHECK-LABEL: @reduce_add_zext_long_external_use( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 ; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]] -; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i8 +; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i8 ; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0 ; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8 diff --git a/llvm/test/Transforms/InstCombine/sadd_sat.ll b/llvm/test/Transforms/InstCombine/sadd_sat.ll index 5ccb6f92b6c7..1cce297122f8 100644 --- a/llvm/test/Transforms/InstCombine/sadd_sat.ll +++ b/llvm/test/Transforms/InstCombine/sadd_sat.ll @@ -79,7 +79,7 @@ define i32 @smul_sat32(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = mul nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: ret i32 [[CONV7]] ; entry: @@ -102,7 +102,7 @@ define i32 @smul_sat32_mm(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = mul nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: ret i32 [[CONV7]] ; entry: @@ -295,7 +295,7 @@ define signext i4 @sadd_sat4(i4 signext %a, i4 signext %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 7) ; CHECK-NEXT: [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -8) -; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[SPEC_STORE_SELECT10]] to i4 +; CHECK-NEXT: [[CONV9:%.*]] = trunc nsw i32 [[SPEC_STORE_SELECT10]] to i4 ; CHECK-NEXT: ret i4 [[CONV9]] ; entry: @@ -318,7 +318,7 @@ define signext i4 @ssub_sat4(i4 signext %a, i4 signext %b) { ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[CONV]], [[CONV1]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[SUB]], i32 7) ; CHECK-NEXT: [[SPEC_STORE_SELECT10:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -8) -; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[SPEC_STORE_SELECT10]] to i4 +; CHECK-NEXT: [[CONV9:%.*]] = trunc nsw i32 [[SPEC_STORE_SELECT10]] to i4 ; CHECK-NEXT: ret i4 [[CONV9]] ; entry: @@ -465,7 +465,7 @@ define i32 @sadd_sat32_extrause_2(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: call void @use64(i64 [[SPEC_STORE_SELECT]]) ; CHECK-NEXT: ret i32 [[CONV7]] ; @@ -490,7 +490,7 @@ define i32 @sadd_sat32_extrause_2_mm(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: call void @use64(i64 [[SPEC_STORE_SELECT]]) ; CHECK-NEXT: ret i32 [[CONV7]] ; @@ -513,7 +513,7 @@ define i32 @sadd_sat32_extrause_3(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: call void @use64(i64 [[ADD]]) ; CHECK-NEXT: ret i32 [[CONV7]] ; @@ -538,7 +538,7 @@ define i32 @sadd_sat32_extrause_3_mm(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 2147483647) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -2147483648) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: call void @use64(i64 [[ADD]]) ; CHECK-NEXT: ret i32 [[CONV7]] ; @@ -561,7 +561,7 @@ define i32 @sadd_sat32_trunc(i32 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smin.i64(i64 [[ADD]], i64 32767) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smax.i64(i64 [[SPEC_STORE_SELECT]], i64 -32768) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: ret i32 [[CONV7]] ; entry: @@ -603,7 +603,7 @@ define i8 @sadd_sat8_ext8(i8 %a, i16 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i32 @llvm.smin.i32(i32 [[ADD]], i32 127) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i32 @llvm.smax.i32(i32 [[SPEC_STORE_SELECT]], i32 -128) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[SPEC_STORE_SELECT8]] to i8 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i32 [[SPEC_STORE_SELECT8]] to i8 ; CHECK-NEXT: ret i8 [[CONV7]] ; entry: @@ -625,7 +625,7 @@ define i32 @sadd_sat32_zext(i32 %a, i32 %b) { ; CHECK-NEXT: [[CONV1:%.*]] = zext i32 [[B:%.*]] to i64 ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[CONV1]], [[CONV]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.umin.i64(i64 [[ADD]], i64 2147483647) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nuw nsw i64 [[SPEC_STORE_SELECT]] to i32 ; CHECK-NEXT: ret i32 [[CONV7]] ; entry: @@ -680,7 +680,7 @@ define i32 @ashrA(i64 %a, i32 %b) { ; CHECK-LABEL: @ashrA( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32 -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw i64 [[TMP0]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[TMP1]], i32 [[B:%.*]]) ; CHECK-NEXT: ret i32 [[TMP2]] ; @@ -698,7 +698,7 @@ define i32 @ashrB(i32 %a, i64 %b) { ; CHECK-LABEL: @ashrB( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[B:%.*]], 32 -; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw i64 [[TMP0]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[TMP1]], i32 [[A:%.*]]) ; CHECK-NEXT: ret i32 [[TMP2]] ; @@ -719,8 +719,8 @@ define i32 @ashrAB(i64 %a, i64 %b) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = lshr i64 [[A:%.*]], 32 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[B:%.*]], 32 -; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32 -; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP0]] to i32 +; CHECK-NEXT: [[TMP2:%.*]] = trunc nuw i64 [[TMP1]] to i32 +; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i64 [[TMP0]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[TMP2]], i32 [[TMP3]]) ; CHECK-NEXT: ret i32 [[TMP4]] ; @@ -744,7 +744,7 @@ define i32 @ashrA31(i64 %a, i32 %b) { ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV]], [[CONV1]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD]], i64 -2147483648) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call i64 @llvm.smin.i64(i64 [[SPEC_STORE_SELECT]], i64 2147483647) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i64 [[SPEC_STORE_SELECT8]] to i32 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i64 [[SPEC_STORE_SELECT8]] to i32 ; CHECK-NEXT: ret i32 [[CONV7]] ; entry: @@ -763,7 +763,7 @@ define i32 @ashrA33(i64 %a, i32 %b) { ; CHECK-LABEL: @ashrA33( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CONV:%.*]] = ashr i64 [[A:%.*]], 33 -; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[CONV]] to i32 +; CHECK-NEXT: [[TMP0:%.*]] = trunc nsw i64 [[CONV]] to i32 ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[TMP0]], i32 [[B:%.*]]) ; CHECK-NEXT: ret i32 [[TMP1]] ; @@ -787,7 +787,7 @@ define <2 x i8> @ashrv2i8(<2 x i16> %a, <2 x i8> %b) { ; CHECK-NEXT: [[ADD:%.*]] = add <2 x i16> [[CONV]], [[CONV1]] ; CHECK-NEXT: [[SPEC_STORE_SELECT:%.*]] = call <2 x i16> @llvm.smax.v2i16(<2 x i16> [[ADD]], <2 x i16> ) ; CHECK-NEXT: [[SPEC_STORE_SELECT8:%.*]] = call <2 x i16> @llvm.smin.v2i16(<2 x i16> [[SPEC_STORE_SELECT]], <2 x i16> ) -; CHECK-NEXT: [[CONV7:%.*]] = trunc <2 x i16> [[SPEC_STORE_SELECT8]] to <2 x i8> +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw <2 x i16> [[SPEC_STORE_SELECT8]] to <2 x i8> ; CHECK-NEXT: ret <2 x i8> [[CONV7]] ; entry: @@ -806,7 +806,7 @@ define <2 x i8> @ashrv2i8_s(<2 x i16> %a, <2 x i8> %b) { ; CHECK-LABEL: @ashrv2i8_s( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = lshr <2 x i16> [[A:%.*]], -; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i16> [[TMP0]] to <2 x i8> +; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw <2 x i16> [[TMP0]] to <2 x i8> ; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8> [[TMP1]], <2 x i8> [[B:%.*]]) ; CHECK-NEXT: ret <2 x i8> [[TMP2]] ; diff --git a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll index 03dd6188ac03..69896f855f5f 100644 --- a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll +++ b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll @@ -220,7 +220,7 @@ define i64 @test6c(i32 %x) { define i16 @test1d(i64 %x) { ; CHECK-LABEL: @test1d( ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[CT]] to i16 +; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CONV]] ; %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true) @@ -233,7 +233,7 @@ define i16 @test1d(i64 %x) { define i32 @test2d(i64 %x) { ; CHECK-LABEL: @test2d( ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true) @@ -246,7 +246,7 @@ define i32 @test2d(i64 %x) { define i16 @test3d(i32 %x) { ; CHECK-LABEL: @test3d( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i32 [[CT]] to i16 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i32 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CAST]] ; %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true) @@ -259,7 +259,7 @@ define i16 @test3d(i32 %x) { define i16 @test4d(i64 %x) { ; CHECK-LABEL: @test4d( ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i16 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CAST]] ; %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true) @@ -272,7 +272,7 @@ define i16 @test4d(i64 %x) { define i32 @test5d(i64 %x) { ; CHECK-LABEL: @test5d( ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true) @@ -288,7 +288,7 @@ define i32 @not_op_ctlz(i64 %x) { ; CHECK-LABEL: @not_op_ctlz( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -1 ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[N]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; %n = xor i64 %x, -1 @@ -303,7 +303,7 @@ define i32 @not_op_cttz(i64 %x) { ; CHECK-LABEL: @not_op_cttz( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -1 ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[N]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; %n = xor i64 %x, -1 @@ -320,7 +320,7 @@ define i32 @not_op_ctlz_wrong_xor_op1(i64 %x) { ; CHECK-LABEL: @not_op_ctlz_wrong_xor_op1( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -2 ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[N]], i1 true), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X]], -1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]] ; CHECK-NEXT: ret i32 [[R]] @@ -339,7 +339,7 @@ define i32 @not_op_ctlz_wrong_xor_op0(i64 %x, i64 %y) { ; CHECK-LABEL: @not_op_ctlz_wrong_xor_op0( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[Y:%.*]], -1 ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[N]], i1 true), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], -1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]] ; CHECK-NEXT: ret i32 [[R]] @@ -358,7 +358,7 @@ define i32 @not_op_cttz_wrong_cmp(i64 %x) { ; CHECK-LABEL: @not_op_cttz_wrong_cmp( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -1 ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[N]], i1 true), !range [[RNG2]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i64 [[CT]] to i32 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]] ; CHECK-NEXT: ret i32 [[R]] @@ -374,7 +374,7 @@ define i32 @not_op_cttz_wrong_cmp(i64 %x) { define i16 @test6d(i32 %x) { ; CHECK-LABEL: @test6d( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CAST:%.*]] = trunc i32 [[CT]] to i16 +; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i32 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CAST]] ; %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) @@ -400,7 +400,7 @@ define i64 @select_bug1(i32 %x) { define i16 @select_bug2(i32 %x) { ; CHECK-LABEL: @select_bug2( ; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] -; CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[CT]] to i16 +; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i32 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CONV]] ; %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 false) @@ -595,7 +595,7 @@ define i64 @test_multiuse_zext_undef(i32 %x, ptr %p) { define i16 @test_multiuse_trunc_def(i64 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_trunc_def( ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[CT]] to i16 +; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: store i16 [[CONV]], ptr [[P:%.*]], align 2 ; CHECK-NEXT: ret i16 [[CONV]] ; @@ -610,7 +610,7 @@ define i16 @test_multiuse_trunc_def(i64 %x, ptr %p) { define i16 @test_multiuse_trunc_undef(i64 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_trunc_undef( ; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] -; CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[CT]] to i16 +; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: store i16 [[CONV]], ptr [[P:%.*]], align 2 ; CHECK-NEXT: ret i16 [[CONV]] ; diff --git a/llvm/test/Transforms/InstCombine/select-imm-canon.ll b/llvm/test/Transforms/InstCombine/select-imm-canon.ll index cde6329fd1b2..6d57af9d939d 100644 --- a/llvm/test/Transforms/InstCombine/select-imm-canon.ll +++ b/llvm/test/Transforms/InstCombine/select-imm-canon.ll @@ -20,7 +20,7 @@ define i8 @double(i32 %A) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128) ; CHECK-NEXT: [[CONV71:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 127) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[CONV71]] to i8 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i32 [[CONV71]] to i8 ; CHECK-NEXT: ret i8 [[CONV7]] ; entry: @@ -51,7 +51,7 @@ define i8 @original(i32 %A, i32 %B) { ; CHECK-LABEL: @original( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128) ; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[SPEC_SELECT_I]] to i8 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i32 [[SPEC_SELECT_I]] to i8 ; CHECK-NEXT: ret i8 [[CONV7]] ; %cmp4.i = icmp slt i32 127, %A @@ -68,7 +68,7 @@ define i8 @original_logical(i32 %A, i32 %B) { ; CHECK-LABEL: @original_logical( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[A:%.*]], i32 -128) ; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127) -; CHECK-NEXT: [[CONV7:%.*]] = trunc i32 [[SPEC_SELECT_I]] to i8 +; CHECK-NEXT: [[CONV7:%.*]] = trunc nsw i32 [[SPEC_SELECT_I]] to i8 ; CHECK-NEXT: ret i8 [[CONV7]] ; %cmp4.i = icmp slt i32 127, %A diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll index 05fcf6623529..bd8145ab2a35 100644 --- a/llvm/test/Transforms/InstCombine/select.ll +++ b/llvm/test/Transforms/InstCombine/select.ll @@ -452,7 +452,7 @@ define i64 @test21(i32 %x) { define i16 @test22(i32 %x) { ; CHECK-LABEL: @test22( ; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[RETVAL:%.*]] = trunc i32 [[X_LOBIT]] to i16 +; CHECK-NEXT: [[RETVAL:%.*]] = trunc nsw i32 [[X_LOBIT]] to i16 ; CHECK-NEXT: ret i16 [[RETVAL]] ; %t = icmp slt i32 %x, 0 diff --git a/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll b/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll index 5b9334ab93cb..b992460d0be6 100644 --- a/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll +++ b/llvm/test/Transforms/InstCombine/sext-of-trunc-nsw.ll @@ -86,7 +86,7 @@ define i16 @t5_extrause(i8 %x) { ; CHECK-LABEL: @t5_extrause( ; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 5 ; CHECK-NEXT: call void @use8(i8 [[A]]) -; CHECK-NEXT: [[B:%.*]] = trunc i8 [[A]] to i4 +; CHECK-NEXT: [[B:%.*]] = trunc nsw i8 [[A]] to i4 ; CHECK-NEXT: call void @use4(i4 [[B]]) ; CHECK-NEXT: [[C:%.*]] = sext i8 [[A]] to i16 ; CHECK-NEXT: ret i16 [[C]] @@ -134,7 +134,7 @@ define i24 @wide_source_matching_signbits(i32 %x) { ; CHECK-LABEL: @wide_source_matching_signbits( ; CHECK-NEXT: [[M:%.*]] = and i32 [[X:%.*]], 7 ; CHECK-NEXT: [[A:%.*]] = shl nsw i32 -1, [[M]] -; CHECK-NEXT: [[C:%.*]] = trunc i32 [[A]] to i24 +; CHECK-NEXT: [[C:%.*]] = trunc nsw i32 [[A]] to i24 ; CHECK-NEXT: ret i24 [[C]] ; %m = and i32 %x, 7 @@ -194,7 +194,7 @@ define i32 @same_source_matching_signbits_extra_use(i32 %x) { ; CHECK-LABEL: @same_source_matching_signbits_extra_use( ; CHECK-NEXT: [[M:%.*]] = and i32 [[X:%.*]], 7 ; CHECK-NEXT: [[A:%.*]] = shl nsw i32 -1, [[M]] -; CHECK-NEXT: [[B:%.*]] = trunc i32 [[A]] to i8 +; CHECK-NEXT: [[B:%.*]] = trunc nsw i32 [[A]] to i8 ; CHECK-NEXT: call void @use8(i8 [[B]]) ; CHECK-NEXT: ret i32 [[A]] ; diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll index 186745362a44..e3b6058ce7f8 100644 --- a/llvm/test/Transforms/InstCombine/sext.ll +++ b/llvm/test/Transforms/InstCombine/sext.ll @@ -385,7 +385,7 @@ define i16 @smear_set_bit_different_dest_type(i32 %x) { ; CHECK-LABEL: @smear_set_bit_different_dest_type( ; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 24 ; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[TMP1]], 31 -; CHECK-NEXT: [[S:%.*]] = trunc i32 [[TMP2]] to i16 +; CHECK-NEXT: [[S:%.*]] = trunc nsw i32 [[TMP2]] to i16 ; CHECK-NEXT: ret i16 [[S]] ; %t = trunc i32 %x to i8 diff --git a/llvm/test/Transforms/InstCombine/shift-add.ll b/llvm/test/Transforms/InstCombine/shift-add.ll index aa3a238e0949..7f948848844c 100644 --- a/llvm/test/Transforms/InstCombine/shift-add.ll +++ b/llvm/test/Transforms/InstCombine/shift-add.ll @@ -742,7 +742,7 @@ define <3 x i32> @add3_i96(<3 x i32> %0, <3 x i32> %1) { ; CHECK-NEXT: [[TMP13:%.*]] = extractelement <3 x i32> [[TMP1]], i64 2 ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 32 -; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 +; CHECK-NEXT: [[TMP16:%.*]] = trunc nuw nsw i64 [[TMP15]] to i32 ; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP14]], [[TMP16]] ; CHECK-NEXT: [[TMP18:%.*]] = insertelement <3 x i32> poison, i32 [[ADD_NARROWED]], i64 0 ; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP11]] to i32 diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll index 60a7dce2a875..a0a3c8edfb4b 100644 --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-in-bittest-with-truncation-lshr.ll @@ -139,7 +139,7 @@ define i1 @n4(i32 %x, i32 %len) { ; CHECK-NEXT: [[T2:%.*]] = add i32 [[LEN]], -16 ; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg i32 [[T2]] to i64 ; CHECK-NEXT: [[T3:%.*]] = lshr i64 262143, [[T2_WIDE]] -; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc i64 [[T3]] to i32 +; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc nuw nsw i64 [[T3]] to i32 ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[T3_TRUNC]] ; CHECK-NEXT: [[T5:%.*]] = icmp ne i32 [[T4]], 0 ; CHECK-NEXT: ret i1 [[T5]] @@ -229,7 +229,7 @@ define <2 x i1> @n8_vec(<2 x i32> %x, <2 x i32> %len) { ; CHECK-NEXT: [[T2:%.*]] = add <2 x i32> [[LEN]], ; CHECK-NEXT: [[T2_WIDE:%.*]] = zext nneg <2 x i32> [[T2]] to <2 x i64> ; CHECK-NEXT: [[T3:%.*]] = lshr <2 x i64> , [[T2_WIDE]] -; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc <2 x i64> [[T3]] to <2 x i32> +; CHECK-NEXT: [[T3_TRUNC:%.*]] = trunc nuw nsw <2 x i64> [[T3]] to <2 x i32> ; CHECK-NEXT: [[T4:%.*]] = and <2 x i32> [[T1]], [[T3_TRUNC]] ; CHECK-NEXT: [[T5:%.*]] = icmp ne <2 x i32> [[T4]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[T5]] diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll index 6773cbac1d1e..84dd4c57ebc6 100644 --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-ashr.ll @@ -13,7 +13,7 @@ define i16 @t0(i32 %x, i16 %y) { ; CHECK-LABEL: @t0( ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[T5:%.*]] = trunc nsw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[T5]] ; %t0 = sub i16 32, %y @@ -30,7 +30,7 @@ define i16 @t0(i32 %x, i16 %y) { define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) { ; CHECK-LABEL: @t1_vec_splat( ; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16> +; CHECK-NEXT: [[T5:%.*]] = trunc nsw <2 x i32> [[TMP1]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[T5]] ; %t0 = sub <2 x i16> , %y @@ -100,7 +100,7 @@ define i16 @t6_extrause0(i32 %x, i16 %y) { ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16 ; CHECK-NEXT: call void @use16(i16 [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X]], 31 -; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[T5:%.*]] = trunc nsw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[T5]] ; %t0 = sub i16 32, %y @@ -118,7 +118,7 @@ define i16 @t7_extrause1(i32 %x, i16 %y) { ; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -1 ; CHECK-NEXT: call void @use16(i16 [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[T5:%.*]] = trunc nsw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[T5]] ; %t0 = sub i16 32, %y diff --git a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-lshr.ll b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-lshr.ll index 63099a8af81f..214ec88d2e55 100644 --- a/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-lshr.ll +++ b/llvm/test/Transforms/InstCombine/shift-amount-reassociation-with-truncation-lshr.ll @@ -13,7 +13,7 @@ define i16 @t0(i32 %x, i16 %y) { ; CHECK-LABEL: @t0( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[T5:%.*]] = trunc nuw nsw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[T5]] ; %t0 = sub i16 32, %y @@ -30,7 +30,7 @@ define i16 @t0(i32 %x, i16 %y) { define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) { ; CHECK-LABEL: @t1_vec_splat( ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[T5:%.*]] = trunc <2 x i32> [[TMP1]] to <2 x i16> +; CHECK-NEXT: [[T5:%.*]] = trunc nuw nsw <2 x i32> [[TMP1]] to <2 x i16> ; CHECK-NEXT: ret <2 x i16> [[T5]] ; %t0 = sub <2 x i16> , %y @@ -100,7 +100,7 @@ define i16 @t6_extrause0(i32 %x, i16 %y) { ; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16 ; CHECK-NEXT: call void @use16(i16 [[T3]]) ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X]], 31 -; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[T5:%.*]] = trunc nuw nsw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[T5]] ; %t0 = sub i16 32, %y @@ -118,7 +118,7 @@ define i16 @t7_extrause1(i32 %x, i16 %y) { ; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y:%.*]], -1 ; CHECK-NEXT: call void @use16(i16 [[T4]]) ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[T5:%.*]] = trunc i32 [[TMP1]] to i16 +; CHECK-NEXT: [[T5:%.*]] = trunc nuw nsw i32 [[TMP1]] to i16 ; CHECK-NEXT: ret i16 [[T5]] ; %t0 = sub i16 32, %y diff --git a/llvm/test/Transforms/InstCombine/shift-shift.ll b/llvm/test/Transforms/InstCombine/shift-shift.ll index 8a40863300d4..7c35718601ba 100644 --- a/llvm/test/Transforms/InstCombine/shift-shift.ll +++ b/llvm/test/Transforms/InstCombine/shift-shift.ll @@ -166,7 +166,7 @@ define i8 @shl_trunc_smaller_lshr(i32 %x) { define i24 @shl_trunc_bigger_ashr(i32 %x) { ; CHECK-LABEL: @shl_trunc_bigger_ashr( ; CHECK-NEXT: [[SH_DIFF:%.*]] = ashr i32 [[X:%.*]], 9 -; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc i32 [[SH_DIFF]] to i24 +; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc nsw i32 [[SH_DIFF]] to i24 ; CHECK-NEXT: [[LT:%.*]] = and i24 [[TR_SH_DIFF]], -8 ; CHECK-NEXT: ret i24 [[LT]] ; @@ -502,7 +502,7 @@ define <2 x i6> @shl_lshr_demand5_undef_left(<2 x i8> %x) { ; CHECK-LABEL: @shl_lshr_demand5_undef_left( ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> , [[X:%.*]] ; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i8> [[SHL]], -; CHECK-NEXT: [[R:%.*]] = trunc <2 x i8> [[LSHR]] to <2 x i6> +; CHECK-NEXT: [[R:%.*]] = trunc nuw <2 x i8> [[LSHR]] to <2 x i6> ; CHECK-NEXT: ret <2 x i6> [[R]] ; %shl = shl <2 x i8> , %x ; 0b1001_0100 @@ -561,7 +561,7 @@ define <2 x i6> @shl_lshr_demand5_nonuniform_vec_both(<2 x i8> %x) { ; CHECK-LABEL: @shl_lshr_demand5_nonuniform_vec_both( ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> , [[X:%.*]] ; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i8> [[SHL]], -; CHECK-NEXT: [[R:%.*]] = trunc <2 x i8> [[LSHR]] to <2 x i6> +; CHECK-NEXT: [[R:%.*]] = trunc nuw <2 x i8> [[LSHR]] to <2 x i6> ; CHECK-NEXT: ret <2 x i6> [[R]] ; %shl = shl <2 x i8> , %x ; 0b1001_1000, 0b1001_0100 diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll index bef7fc81a7d1..bb8661919c89 100644 --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -423,7 +423,7 @@ define i32 @test29(i64 %d18) { ; CHECK-LABEL: @test29( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr i64 [[D18:%.*]], 63 -; CHECK-NEXT: [[I101:%.*]] = trunc i64 [[SUM_SHIFT]] to i32 +; CHECK-NEXT: [[I101:%.*]] = trunc nuw nsw i64 [[SUM_SHIFT]] to i32 ; CHECK-NEXT: ret i32 [[I101]] ; entry: @@ -437,7 +437,7 @@ define <2 x i32> @test29_uniform(<2 x i64> %d18) { ; CHECK-LABEL: @test29_uniform( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SUM_SHIFT:%.*]] = lshr <2 x i64> [[D18:%.*]], -; CHECK-NEXT: [[I101:%.*]] = trunc <2 x i64> [[SUM_SHIFT]] to <2 x i32> +; CHECK-NEXT: [[I101:%.*]] = trunc nuw nsw <2 x i64> [[SUM_SHIFT]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[I101]] ; entry: @@ -466,7 +466,7 @@ define <2 x i32> @test29_poison(<2 x i64> %d18) { ; CHECK-LABEL: @test29_poison( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[I916:%.*]] = lshr <2 x i64> [[D18:%.*]], -; CHECK-NEXT: [[I917:%.*]] = trunc <2 x i64> [[I916]] to <2 x i32> +; CHECK-NEXT: [[I917:%.*]] = trunc nuw <2 x i64> [[I916]] to <2 x i32> ; CHECK-NEXT: [[I10:%.*]] = lshr <2 x i32> [[I917]], ; CHECK-NEXT: ret <2 x i32> [[I10]] ; diff --git a/llvm/test/Transforms/InstCombine/shl-demand.ll b/llvm/test/Transforms/InstCombine/shl-demand.ll index 26175ebbe153..08e6e7458184 100644 --- a/llvm/test/Transforms/InstCombine/shl-demand.ll +++ b/llvm/test/Transforms/InstCombine/shl-demand.ll @@ -222,7 +222,7 @@ define i8 @must_drop_poison(i32 %x, i32 %y) { define i32 @f_t15_t01_t09(i40 %t2) { ; CHECK-LABEL: @f_t15_t01_t09( ; CHECK-NEXT: [[SH_DIFF:%.*]] = ashr i40 [[T2:%.*]], 15 -; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc i40 [[SH_DIFF]] to i32 +; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc nsw i40 [[SH_DIFF]] to i32 ; CHECK-NEXT: [[SHL1:%.*]] = and i32 [[TR_SH_DIFF]], -65536 ; CHECK-NEXT: ret i32 [[SHL1]] ; diff --git a/llvm/test/Transforms/InstCombine/sign-bit-test-via-right-shifting-all-other-bits.ll b/llvm/test/Transforms/InstCombine/sign-bit-test-via-right-shifting-all-other-bits.ll index d3ac6cfa9c60..30fad66bf521 100644 --- a/llvm/test/Transforms/InstCombine/sign-bit-test-via-right-shifting-all-other-bits.ll +++ b/llvm/test/Transforms/InstCombine/sign-bit-test-via-right-shifting-all-other-bits.ll @@ -322,7 +322,7 @@ define i1 @unsigned_sign_bit_extract_with_trunc_extrause(i64 %x) { ; CHECK-LABEL: @unsigned_sign_bit_extract_with_trunc_extrause( ; CHECK-NEXT: [[SIGNBIT:%.*]] = lshr i64 [[X:%.*]], 63 ; CHECK-NEXT: call void @use64(i64 [[SIGNBIT]]) -; CHECK-NEXT: [[SIGNBIT_NARROW:%.*]] = trunc i64 [[SIGNBIT]] to i32 +; CHECK-NEXT: [[SIGNBIT_NARROW:%.*]] = trunc nuw nsw i64 [[SIGNBIT]] to i32 ; CHECK-NEXT: call void @use32(i32 [[SIGNBIT_NARROW]]) ; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i64 [[X]], 0 ; CHECK-NEXT: ret i1 [[ISNEG]] @@ -348,7 +348,7 @@ define i1 @signed_sign_bit_extract_trunc_extrause(i64 %x) { ; CHECK-LABEL: @signed_sign_bit_extract_trunc_extrause( ; CHECK-NEXT: [[SIGNSMEAR:%.*]] = ashr i64 [[X:%.*]], 63 ; CHECK-NEXT: call void @use64(i64 [[SIGNSMEAR]]) -; CHECK-NEXT: [[SIGNSMEAR_NARROW:%.*]] = trunc i64 [[SIGNSMEAR]] to i32 +; CHECK-NEXT: [[SIGNSMEAR_NARROW:%.*]] = trunc nsw i64 [[SIGNSMEAR]] to i32 ; CHECK-NEXT: call void @use32(i32 [[SIGNSMEAR_NARROW]]) ; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i64 [[X]], 0 ; CHECK-NEXT: ret i1 [[ISNEG]] diff --git a/llvm/test/Transforms/InstCombine/trunc-demand.ll b/llvm/test/Transforms/InstCombine/trunc-demand.ll index 4f6e79285eaa..9d7bf589268e 100644 --- a/llvm/test/Transforms/InstCombine/trunc-demand.ll +++ b/llvm/test/Transforms/InstCombine/trunc-demand.ll @@ -36,7 +36,7 @@ define i6 @trunc_lshr_exact_mask(i8 %x) { define i6 @trunc_lshr_big_mask(i8 %x) { ; CHECK-LABEL: @trunc_lshr_big_mask( ; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2 -; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6 +; CHECK-NEXT: [[T:%.*]] = trunc nuw i8 [[S]] to i6 ; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 31 ; CHECK-NEXT: ret i6 [[R]] ; @@ -52,7 +52,7 @@ define i6 @trunc_lshr_use1(i8 %x) { ; CHECK-LABEL: @trunc_lshr_use1( ; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2 ; CHECK-NEXT: call void @use8(i8 [[S]]) -; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6 +; CHECK-NEXT: [[T:%.*]] = trunc nuw i8 [[S]] to i6 ; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15 ; CHECK-NEXT: ret i6 [[R]] ; @@ -68,7 +68,7 @@ define i6 @trunc_lshr_use1(i8 %x) { define i6 @trunc_lshr_use2(i8 %x) { ; CHECK-LABEL: @trunc_lshr_use2( ; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 2 -; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6 +; CHECK-NEXT: [[T:%.*]] = trunc nuw i8 [[S]] to i6 ; CHECK-NEXT: call void @use6(i6 [[T]]) ; CHECK-NEXT: [[R:%.*]] = and i6 [[T]], 15 ; CHECK-NEXT: ret i6 [[R]] @@ -157,7 +157,7 @@ define i6 @or_trunc_lshr_more(i8 %x) { define i6 @or_trunc_lshr_small_mask(i8 %x) { ; CHECK-LABEL: @or_trunc_lshr_small_mask( ; CHECK-NEXT: [[S:%.*]] = lshr i8 [[X:%.*]], 4 -; CHECK-NEXT: [[T:%.*]] = trunc i8 [[S]] to i6 +; CHECK-NEXT: [[T:%.*]] = trunc nuw nsw i8 [[S]] to i6 ; CHECK-NEXT: [[R:%.*]] = or i6 [[T]], -8 ; CHECK-NEXT: ret i6 [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll b/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll index 87c90bb91f39..4c857125365a 100644 --- a/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll @@ -171,7 +171,7 @@ define i32 @test5(i32 %A) { define i32 @test6(i64 %A) { ; CHECK-LABEL: @test6( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[A:%.*]], 32 -; CHECK-NEXT: [[D:%.*]] = trunc i64 [[TMP1]] to i32 +; CHECK-NEXT: [[D:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[D]] ; %B = zext i64 %A to i128 @@ -459,7 +459,7 @@ define <2 x i64> @test12_vec_undef(<2 x i32> %A, <2 x i32> %B) { ; CHECK-NEXT: [[D:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i128> ; CHECK-NEXT: [[E:%.*]] = and <2 x i128> [[D]], ; CHECK-NEXT: [[F:%.*]] = lshr <2 x i128> [[C]], [[E]] -; CHECK-NEXT: [[G:%.*]] = trunc <2 x i128> [[F]] to <2 x i64> +; CHECK-NEXT: [[G:%.*]] = trunc nuw nsw <2 x i128> [[F]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[G]] ; %C = zext <2 x i32> %A to <2 x i128> @@ -524,7 +524,7 @@ define <2 x i64> @test13_vec_undef(<2 x i32> %A, <2 x i32> %B) { ; CHECK-NEXT: [[D:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i128> ; CHECK-NEXT: [[E:%.*]] = and <2 x i128> [[D]], ; CHECK-NEXT: [[F:%.*]] = ashr <2 x i128> [[C]], [[E]] -; CHECK-NEXT: [[G:%.*]] = trunc <2 x i128> [[F]] to <2 x i64> +; CHECK-NEXT: [[G:%.*]] = trunc nsw <2 x i128> [[F]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[G]] ; %C = sext <2 x i32> %A to <2 x i128> diff --git a/llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll b/llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll index e578b604c9d6..2c5f428cf98d 100644 --- a/llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll +++ b/llvm/test/Transforms/InstCombine/trunc-shift-trunc.ll @@ -72,7 +72,7 @@ define i8 @trunc_lshr_trunc_outofrange(i64 %a) { ; CHECK-LABEL: @trunc_lshr_trunc_outofrange( ; CHECK-NEXT: [[B:%.*]] = trunc i64 [[A:%.*]] to i32 ; CHECK-NEXT: [[C:%.*]] = lshr i32 [[B]], 25 -; CHECK-NEXT: [[D:%.*]] = trunc i32 [[C]] to i8 +; CHECK-NEXT: [[D:%.*]] = trunc nuw nsw i32 [[C]] to i8 ; CHECK-NEXT: ret i8 [[D]] ; %b = trunc i64 %a to i32 @@ -158,7 +158,7 @@ define i8 @trunc_ashr_trunc_outofrange(i64 %a) { ; CHECK-LABEL: @trunc_ashr_trunc_outofrange( ; CHECK-NEXT: [[B:%.*]] = trunc i64 [[A:%.*]] to i32 ; CHECK-NEXT: [[C:%.*]] = ashr i32 [[B]], 25 -; CHECK-NEXT: [[D:%.*]] = trunc i32 [[C]] to i8 +; CHECK-NEXT: [[D:%.*]] = trunc nsw i32 [[C]] to i8 ; CHECK-NEXT: ret i8 [[D]] ; %b = trunc i64 %a to i32 diff --git a/llvm/test/Transforms/InstCombine/trunc.ll b/llvm/test/Transforms/InstCombine/trunc.ll index 760825d6b1da..c77d7269f2cf 100644 --- a/llvm/test/Transforms/InstCombine/trunc.ll +++ b/llvm/test/Transforms/InstCombine/trunc.ll @@ -171,7 +171,7 @@ define i32 @test5(i32 %A) { define i32 @test6(i64 %A) { ; CHECK-LABEL: @test6( ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[A:%.*]], 32 -; CHECK-NEXT: [[D:%.*]] = trunc i64 [[TMP1]] to i32 +; CHECK-NEXT: [[D:%.*]] = trunc nuw i64 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[D]] ; %B = zext i64 %A to i128 @@ -459,7 +459,7 @@ define <2 x i64> @test12_vec_undef(<2 x i32> %A, <2 x i32> %B) { ; CHECK-NEXT: [[D:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i128> ; CHECK-NEXT: [[E:%.*]] = and <2 x i128> [[D]], ; CHECK-NEXT: [[F:%.*]] = lshr <2 x i128> [[C]], [[E]] -; CHECK-NEXT: [[G:%.*]] = trunc <2 x i128> [[F]] to <2 x i64> +; CHECK-NEXT: [[G:%.*]] = trunc nuw nsw <2 x i128> [[F]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[G]] ; %C = zext <2 x i32> %A to <2 x i128> @@ -524,7 +524,7 @@ define <2 x i64> @test13_vec_undef(<2 x i32> %A, <2 x i32> %B) { ; CHECK-NEXT: [[D:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i128> ; CHECK-NEXT: [[E:%.*]] = and <2 x i128> [[D]], ; CHECK-NEXT: [[F:%.*]] = ashr <2 x i128> [[C]], [[E]] -; CHECK-NEXT: [[G:%.*]] = trunc <2 x i128> [[F]] to <2 x i64> +; CHECK-NEXT: [[G:%.*]] = trunc nsw <2 x i128> [[F]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[G]] ; %C = sext <2 x i32> %A to <2 x i128> diff --git a/llvm/test/Transforms/InstCombine/truncating-saturate.ll b/llvm/test/Transforms/InstCombine/truncating-saturate.ll index e4df94afd174..c0111528e2a4 100644 --- a/llvm/test/Transforms/InstCombine/truncating-saturate.ll +++ b/llvm/test/Transforms/InstCombine/truncating-saturate.ll @@ -10,7 +10,7 @@ define i8 @testi16i8(i16 %add) { ; CHECK-LABEL: @testi16i8( ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ADD:%.*]], i16 -128) ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127) -; CHECK-NEXT: [[COND_I:%.*]] = trunc i16 [[TMP2]] to i8 +; CHECK-NEXT: [[COND_I:%.*]] = trunc nsw i16 [[TMP2]] to i8 ; CHECK-NEXT: ret i8 [[COND_I]] ; %sh = lshr i16 %add, 8 @@ -29,7 +29,7 @@ define i32 @testi64i32(i64 %add) { ; CHECK-LABEL: @testi64i32( ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.smax.i64(i64 [[ADD:%.*]], i64 -2147483648) ; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.smin.i64(i64 [[TMP1]], i64 2147483647) -; CHECK-NEXT: [[COND_I:%.*]] = trunc i64 [[TMP2]] to i32 +; CHECK-NEXT: [[COND_I:%.*]] = trunc nsw i64 [[TMP2]] to i32 ; CHECK-NEXT: ret i32 [[COND_I]] ; %sh = lshr i64 %add, 32 @@ -48,7 +48,7 @@ define i16 @testi32i16i8(i32 %add) { ; CHECK-LABEL: @testi32i16i8( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD:%.*]], i32 -128) ; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP1]], i32 127) -; CHECK-NEXT: [[R:%.*]] = trunc i32 [[TMP2]] to i16 +; CHECK-NEXT: [[R:%.*]] = trunc nsw i32 [[TMP2]] to i16 ; CHECK-NEXT: ret i16 [[R]] ; %a = add i32 %add, 128 @@ -64,7 +64,7 @@ define <4 x i16> @testv4i32i16i8(<4 x i32> %add) { ; CHECK-LABEL: @testv4i32i16i8( ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[ADD:%.*]], <4 x i32> ) ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[TMP1]], <4 x i32> ) -; CHECK-NEXT: [[R:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16> +; CHECK-NEXT: [[R:%.*]] = trunc nsw <4 x i32> [[TMP2]] to <4 x i16> ; CHECK-NEXT: ret <4 x i16> [[R]] ; %a = add <4 x i32> %add, @@ -149,7 +149,7 @@ define <4 x i8> @testv4i16i8(<4 x i16> %add) { ; CHECK-LABEL: @testv4i16i8( ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.smax.v4i16(<4 x i16> [[ADD:%.*]], <4 x i16> ) ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.smin.v4i16(<4 x i16> [[TMP1]], <4 x i16> ) -; CHECK-NEXT: [[COND_I:%.*]] = trunc <4 x i16> [[TMP2]] to <4 x i8> +; CHECK-NEXT: [[COND_I:%.*]] = trunc nsw <4 x i16> [[TMP2]] to <4 x i8> ; CHECK-NEXT: ret <4 x i8> [[COND_I]] ; %sh = lshr <4 x i16> %add, @@ -188,7 +188,7 @@ define i8 @testi16i8_revcmp(i16 %add) { ; CHECK-LABEL: @testi16i8_revcmp( ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ADD:%.*]], i16 -128) ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127) -; CHECK-NEXT: [[COND_I:%.*]] = trunc i16 [[TMP2]] to i8 +; CHECK-NEXT: [[COND_I:%.*]] = trunc nsw i16 [[TMP2]] to i8 ; CHECK-NEXT: ret i8 [[COND_I]] ; %sh = lshr i16 %add, 8 @@ -207,7 +207,7 @@ define i8 @testi16i8_revselect(i16 %add) { ; CHECK-LABEL: @testi16i8_revselect( ; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.smax.i16(i16 [[ADD:%.*]], i16 -128) ; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.smin.i16(i16 [[TMP1]], i16 127) -; CHECK-NEXT: [[COND_I:%.*]] = trunc i16 [[TMP2]] to i8 +; CHECK-NEXT: [[COND_I:%.*]] = trunc nsw i16 [[TMP2]] to i8 ; CHECK-NEXT: ret i8 [[COND_I]] ; %sh = lshr i16 %add, 8 @@ -268,7 +268,7 @@ define i16 @differentconsts(i32 %x, i16 %replacement_low, i16 %replacement_high) define i8 @badimm1(i16 %add) { ; CHECK-LABEL: @badimm1( ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 9 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw nsw i16 [[SH]] to i8 ; CHECK-NEXT: [[CONV1_I:%.*]] = trunc i16 [[ADD]] to i8 ; CHECK-NEXT: [[SHR2_I:%.*]] = ashr i8 [[CONV1_I]], 7 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[SHR2_I]], [[CONV_I]] @@ -292,7 +292,7 @@ define i8 @badimm1(i16 %add) { define i8 @badimm2(i16 %add) { ; CHECK-LABEL: @badimm2( ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8 -; CHECK-NEXT: [[CONV_I:%.*]] = trunc i16 [[SH]] to i8 +; CHECK-NEXT: [[CONV_I:%.*]] = trunc nuw i16 [[SH]] to i8 ; CHECK-NEXT: [[CONV1_I:%.*]] = trunc i16 [[ADD]] to i8 ; CHECK-NEXT: [[SHR2_I:%.*]] = ashr i8 [[CONV1_I]], 6 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp eq i8 [[SHR2_I]], [[CONV_I]] @@ -319,7 +319,7 @@ define i8 @badimm3(i16 %add) { ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD]], 128 ; CHECK-NEXT: [[CMP_NOT_I:%.*]] = icmp ult i16 [[TMP1]], 256 ; CHECK-NEXT: [[SHR4_I:%.*]] = ashr i16 [[ADD]], 14 -; CHECK-NEXT: [[CONV5_I:%.*]] = trunc i16 [[SHR4_I]] to i8 +; CHECK-NEXT: [[CONV5_I:%.*]] = trunc nsw i16 [[SHR4_I]] to i8 ; CHECK-NEXT: [[XOR_I:%.*]] = xor i8 [[CONV5_I]], 127 ; CHECK-NEXT: [[COND_I:%.*]] = select i1 [[CMP_NOT_I]], i8 [[CONV1_I]], i8 [[XOR_I]] ; CHECK-NEXT: ret i8 [[COND_I]] diff --git a/llvm/test/Transforms/InstCombine/vector-trunc.ll b/llvm/test/Transforms/InstCombine/vector-trunc.ll index eeb5a3fdb739..bccb12e66eba 100644 --- a/llvm/test/Transforms/InstCombine/vector-trunc.ll +++ b/llvm/test/Transforms/InstCombine/vector-trunc.ll @@ -4,7 +4,7 @@ define <4 x i16> @trunc_add_nsw(<4 x i32> %0) { ; CHECK-LABEL: @trunc_add_nsw( ; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP0:%.*]], -; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = trunc nsw <4 x i32> [[TMP2]] to <4 x i16> ; CHECK-NEXT: [[TMP4:%.*]] = add nsw <4 x i16> [[TMP3]], ; CHECK-NEXT: ret <4 x i16> [[TMP4]] ; @@ -17,7 +17,7 @@ define <4 x i16> @trunc_add_nsw(<4 x i32> %0) { define <4 x i16> @trunc_add_no_nsw(<4 x i32> %0) { ; CHECK-LABEL: @trunc_add_no_nsw( ; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP0:%.*]], -; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16> +; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw <4 x i32> [[TMP2]] to <4 x i16> ; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP3]], ; CHECK-NEXT: ret <4 x i16> [[TMP4]] ; diff --git a/llvm/test/Transforms/InstCombine/xor-ashr.ll b/llvm/test/Transforms/InstCombine/xor-ashr.ll index 32ca8e338c2c..097e04b3b9cb 100644 --- a/llvm/test/Transforms/InstCombine/xor-ashr.ll +++ b/llvm/test/Transforms/InstCombine/xor-ashr.ll @@ -80,7 +80,7 @@ define <4 x i8> @testv4i16i8_undef(<4 x i16> %add) { define i8 @wrongimm(i16 %add) { ; CHECK-LABEL: @wrongimm( ; CHECK-NEXT: [[SH:%.*]] = ashr i16 [[ADD:%.*]], 14 -; CHECK-NEXT: [[T:%.*]] = trunc i16 [[SH]] to i8 +; CHECK-NEXT: [[T:%.*]] = trunc nsw i16 [[SH]] to i8 ; CHECK-NEXT: [[X:%.*]] = xor i8 [[T]], 27 ; CHECK-NEXT: ret i8 [[X]] ; @@ -140,7 +140,7 @@ define i16 @extrause_trunc1(i32 %add) { define i16 @extrause_trunc2(i32 %add) { ; CHECK-LABEL: @extrause_trunc2( ; CHECK-NEXT: [[SH:%.*]] = ashr i32 [[ADD:%.*]], 31 -; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SH]] to i16 +; CHECK-NEXT: [[T:%.*]] = trunc nsw i32 [[SH]] to i16 ; CHECK-NEXT: call void @use16(i16 [[T]]) ; CHECK-NEXT: [[X:%.*]] = xor i16 [[T]], 127 ; CHECK-NEXT: ret i16 [[X]] diff --git a/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll b/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll index f082873bf783..c8eb513a8440 100644 --- a/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll +++ b/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll @@ -57,7 +57,7 @@ define <2 x i17> @trunc_ctlz_zext_v2i17_v2i32_multiple_uses(<2 x i17> %x) { ; CHECK-LABEL: @trunc_ctlz_zext_v2i17_v2i32_multiple_uses( ; CHECK-NEXT: [[Z:%.*]] = zext <2 x i17> [[X:%.*]] to <2 x i32> ; CHECK-NEXT: [[P:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[Z]], i1 false), !range [[RNG2:![0-9]+]] -; CHECK-NEXT: [[ZZ:%.*]] = trunc <2 x i32> [[P]] to <2 x i17> +; CHECK-NEXT: [[ZZ:%.*]] = trunc nuw nsw <2 x i32> [[P]] to <2 x i17> ; CHECK-NEXT: call void @use(<2 x i32> [[P]]) ; CHECK-NEXT: ret <2 x i17> [[ZZ]] ; @@ -91,7 +91,7 @@ define i16 @trunc_ctlz_zext_i10_i32(i10 %x) { ; CHECK-LABEL: @trunc_ctlz_zext_i10_i32( ; CHECK-NEXT: [[Z:%.*]] = zext i10 [[X:%.*]] to i32 ; CHECK-NEXT: [[P:%.*]] = call i32 @llvm.ctlz.i32(i32 [[Z]], i1 false), !range [[RNG3:![0-9]+]] -; CHECK-NEXT: [[ZZ:%.*]] = trunc i32 [[P]] to i16 +; CHECK-NEXT: [[ZZ:%.*]] = trunc nuw nsw i32 [[P]] to i16 ; CHECK-NEXT: ret i16 [[ZZ]] ; %z = zext i10 %x to i32 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll b/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll index 9a7b9f570cf7..ed8d8e15282d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll @@ -34,14 +34,14 @@ define void @test_pr25490(i32 %n, ptr noalias nocapture %a, ptr noalias nocaptur ; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i16> ; CHECK-NEXT: [[TMP5:%.*]] = mul nuw <16 x i16> [[TMP3]], [[TMP4]] ; CHECK-NEXT: [[TMP6:%.*]] = lshr <16 x i16> [[TMP5]], -; CHECK-NEXT: [[TMP7:%.*]] = trunc <16 x i16> [[TMP6]] to <16 x i8> +; CHECK-NEXT: [[TMP7:%.*]] = trunc nuw <16 x i16> [[TMP6]] to <16 x i8> ; CHECK-NEXT: store <16 x i8> [[TMP7]], ptr [[TMP2]], align 1 ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <16 x i8>, ptr [[TMP8]], align 1 ; CHECK-NEXT: [[TMP9:%.*]] = zext <16 x i8> [[WIDE_LOAD3]] to <16 x i16> ; CHECK-NEXT: [[TMP10:%.*]] = mul nuw <16 x i16> [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = lshr <16 x i16> [[TMP10]], -; CHECK-NEXT: [[TMP12:%.*]] = trunc <16 x i16> [[TMP11]] to <16 x i8> +; CHECK-NEXT: [[TMP12:%.*]] = trunc nuw <16 x i16> [[TMP11]] to <16 x i8> ; CHECK-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP8]], align 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] @@ -67,14 +67,14 @@ define void @test_pr25490(i32 %n, ptr noalias nocapture %a, ptr noalias nocaptur ; CHECK-NEXT: [[TMP17:%.*]] = zext <8 x i8> [[WIDE_LOAD8]] to <8 x i16> ; CHECK-NEXT: [[TMP18:%.*]] = mul nuw <8 x i16> [[TMP16]], [[TMP17]] ; CHECK-NEXT: [[TMP19:%.*]] = lshr <8 x i16> [[TMP18]], -; CHECK-NEXT: [[TMP20:%.*]] = trunc <8 x i16> [[TMP19]] to <8 x i8> +; CHECK-NEXT: [[TMP20:%.*]] = trunc nuw <8 x i16> [[TMP19]] to <8 x i8> ; CHECK-NEXT: store <8 x i8> [[TMP20]], ptr [[TMP15]], align 1 ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDEX7]] ; CHECK-NEXT: [[WIDE_LOAD10:%.*]] = load <8 x i8>, ptr [[TMP21]], align 1 ; CHECK-NEXT: [[TMP22:%.*]] = zext <8 x i8> [[WIDE_LOAD10]] to <8 x i16> ; CHECK-NEXT: [[TMP23:%.*]] = mul nuw <8 x i16> [[TMP22]], [[TMP17]] ; CHECK-NEXT: [[TMP24:%.*]] = lshr <8 x i16> [[TMP23]], -; CHECK-NEXT: [[TMP25:%.*]] = trunc <8 x i16> [[TMP24]] to <8 x i8> +; CHECK-NEXT: [[TMP25:%.*]] = trunc nuw <8 x i16> [[TMP24]] to <8 x i8> ; CHECK-NEXT: store <8 x i8> [[TMP25]], ptr [[TMP21]], align 1 ; CHECK-NEXT: [[INDEX_NEXT11]] = add nuw i64 [[INDEX7]], 8 ; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT11]], [[N_VEC5]] @@ -99,14 +99,14 @@ define void @test_pr25490(i32 %n, ptr noalias nocapture %a, ptr noalias nocaptur ; CHECK-NEXT: [[CONV3:%.*]] = zext i8 [[TMP28]] to i32 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[CONV3]], [[CONV]] ; CHECK-NEXT: [[SHR_26:%.*]] = lshr i32 [[MUL]], 8 -; CHECK-NEXT: [[CONV4:%.*]] = trunc i32 [[SHR_26]] to i8 +; CHECK-NEXT: [[CONV4:%.*]] = trunc nuw i32 [[SHR_26]] to i8 ; CHECK-NEXT: store i8 [[CONV4]], ptr [[ARRAYIDX2]], align 1 ; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDVARS_IV]] ; CHECK-NEXT: [[TMP29:%.*]] = load i8, ptr [[ARRAYIDX8]], align 1 ; CHECK-NEXT: [[CONV9:%.*]] = zext i8 [[TMP29]] to i32 ; CHECK-NEXT: [[MUL10:%.*]] = mul nuw nsw i32 [[CONV9]], [[CONV]] ; CHECK-NEXT: [[SHR11_27:%.*]] = lshr i32 [[MUL10]], 8 -; CHECK-NEXT: [[CONV12:%.*]] = trunc i32 [[SHR11_27]] to i8 +; CHECK-NEXT: [[CONV12:%.*]] = trunc nuw i32 [[SHR11_27]] to i8 ; CHECK-NEXT: store i8 [[CONV12]], ptr [[ARRAYIDX8]], align 1 ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 ; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 @@ -172,8 +172,8 @@ define void @test_shrink_zext_in_preheader(ptr noalias %src, ptr noalias %dst, i ; CHECK-NEXT: [[TMP6:%.*]] = mul <16 x i16> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[TMP7:%.*]] = lshr <16 x i16> [[TMP5]], ; CHECK-NEXT: [[TMP8:%.*]] = lshr <16 x i16> [[TMP6]], -; CHECK-NEXT: [[TMP9:%.*]] = trunc <16 x i16> [[TMP7]] to <16 x i8> -; CHECK-NEXT: [[TMP10:%.*]] = trunc <16 x i16> [[TMP8]] to <16 x i8> +; CHECK-NEXT: [[TMP9:%.*]] = trunc nuw <16 x i16> [[TMP7]] to <16 x i8> +; CHECK-NEXT: [[TMP10:%.*]] = trunc nuw <16 x i16> [[TMP8]] to <16 x i8> ; CHECK-NEXT: [[TMP11:%.*]] = sext i32 [[INDEX]] to i64 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP11]] ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[TMP12]], i64 16 diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll index b772a3814a64..0f26092f510c 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll @@ -23,7 +23,7 @@ define void @saddsat(ptr nocapture readonly %pSrc, i16 signext %offset, ptr noca ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967280 -; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i32 +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc nuw i64 [[N_VEC]] to i32 ; CHECK-NEXT: [[IND_END:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST]] ; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[N_VEC]], 1 ; CHECK-NEXT: [[IND_END1:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[TMP1]] @@ -138,7 +138,7 @@ define void @umin(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocaptur ; CHECK: vec.epilog.iter.check: ; CHECK-NEXT: [[IND_END18:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC]] ; CHECK-NEXT: [[IND_END15:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC]] -; CHECK-NEXT: [[DOTCAST11:%.*]] = trunc i64 [[N_VEC]] to i32 +; CHECK-NEXT: [[DOTCAST11:%.*]] = trunc nuw i64 [[N_VEC]] to i32 ; CHECK-NEXT: [[IND_END12:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST11]] ; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = and i64 [[TMP0]], 24 ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp eq i64 [[N_VEC_REMAINING]], 0 @@ -146,7 +146,7 @@ define void @umin(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocaptur ; CHECK: vec.epilog.ph: ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: [[N_VEC9:%.*]] = and i64 [[TMP0]], 4294967288 -; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC9]] to i32 +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc nuw i64 [[N_VEC9]] to i32 ; CHECK-NEXT: [[IND_END10:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST]] ; CHECK-NEXT: [[IND_END14:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC9]] ; CHECK-NEXT: [[IND_END17:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC9]] diff --git a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll index 23b653bbda38..b5effe73fa73 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll @@ -60,7 +60,7 @@ define void @uaddsat(ptr nocapture readonly %pSrc, i16 signext %offset, ptr noca ; CHECK-NEXT: [[IND_END24:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP14]] ; CHECK-NEXT: [[TMP15:%.*]] = shl nuw nsw i64 [[N_VEC]], 1 ; CHECK-NEXT: [[IND_END21:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP15]] -; CHECK-NEXT: [[DOTCAST17:%.*]] = trunc i64 [[N_VEC]] to i32 +; CHECK-NEXT: [[DOTCAST17:%.*]] = trunc nuw i64 [[N_VEC]] to i32 ; CHECK-NEXT: [[IND_END18:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST17]] ; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = and i64 [[TMP0]], 56 ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp eq i64 [[N_VEC_REMAINING]], 0 @@ -68,7 +68,7 @@ define void @uaddsat(ptr nocapture readonly %pSrc, i16 signext %offset, ptr noca ; CHECK: vec.epilog.ph: ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: [[N_VEC15:%.*]] = and i64 [[TMP0]], 4294967288 -; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC15]] to i32 +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc nuw i64 [[N_VEC15]] to i32 ; CHECK-NEXT: [[IND_END16:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST]] ; CHECK-NEXT: [[TMP16:%.*]] = shl nuw nsw i64 [[N_VEC15]], 1 ; CHECK-NEXT: [[IND_END20:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP16]] @@ -183,7 +183,7 @@ define void @fshl(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocaptur ; CHECK: vec.epilog.iter.check: ; CHECK-NEXT: [[IND_END24:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC]] ; CHECK-NEXT: [[IND_END21:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC]] -; CHECK-NEXT: [[DOTCAST17:%.*]] = trunc i64 [[N_VEC]] to i32 +; CHECK-NEXT: [[DOTCAST17:%.*]] = trunc nuw i64 [[N_VEC]] to i32 ; CHECK-NEXT: [[IND_END18:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST17]] ; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = and i64 [[TMP0]], 112 ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp eq i64 [[N_VEC_REMAINING]], 0 @@ -191,7 +191,7 @@ define void @fshl(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocaptur ; CHECK: vec.epilog.ph: ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: [[N_VEC15:%.*]] = and i64 [[TMP0]], 4294967280 -; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC15]] to i32 +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc nuw i64 [[N_VEC15]] to i32 ; CHECK-NEXT: [[IND_END16:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST]] ; CHECK-NEXT: [[IND_END20:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[N_VEC15]] ; CHECK-NEXT: [[IND_END23:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[N_VEC15]] diff --git a/llvm/test/Transforms/LoopVectorize/reduction.ll b/llvm/test/Transforms/LoopVectorize/reduction.ll index a47a38510eee..b66ce4047ad9 100644 --- a/llvm/test/Transforms/LoopVectorize/reduction.ll +++ b/llvm/test/Transforms/LoopVectorize/reduction.ll @@ -1205,7 +1205,7 @@ define i64 @reduction_with_phi_with_one_incoming_on_backedge(i16 %n, ptr %A) { ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[TMP1]], 32764 -; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[N_VEC]] to i16 +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc nuw nsw i32 [[N_VEC]] to i16 ; CHECK-NEXT: [[IND_END:%.*]] = or disjoint i16 [[DOTCAST]], 1 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: @@ -1283,7 +1283,7 @@ define i64 @reduction_with_phi_with_two_incoming_on_backedge(i16 %n, ptr %A) { ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: ; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[TMP1]], 32764 -; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i32 [[N_VEC]] to i16 +; CHECK-NEXT: [[DOTCAST:%.*]] = trunc nuw nsw i32 [[N_VEC]] to i16 ; CHECK-NEXT: [[IND_END:%.*]] = or disjoint i16 [[DOTCAST]], 1 ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll index d18b207e8707..9206893cb234 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll @@ -45,8 +45,8 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[TMP14:%.*]] = mul <8 x i32> [[TMP12]], [[TMP10]] ; CHECK-NEXT: [[TMP15:%.*]] = lshr <8 x i32> [[TMP13]], ; CHECK-NEXT: [[TMP16:%.*]] = lshr <8 x i32> [[TMP14]], -; CHECK-NEXT: [[TMP17:%.*]] = trunc <8 x i32> [[TMP15]] to <8 x i16> -; CHECK-NEXT: [[TMP18:%.*]] = trunc <8 x i32> [[TMP16]] to <8 x i16> +; CHECK-NEXT: [[TMP17:%.*]] = trunc nuw <8 x i32> [[TMP15]] to <8 x i16> +; CHECK-NEXT: [[TMP18:%.*]] = trunc nuw <8 x i32> [[TMP16]] to <8 x i16> ; CHECK-NEXT: [[TMP19:%.*]] = sub <8 x i16> zeroinitializer, [[TMP17]] ; CHECK-NEXT: [[TMP20:%.*]] = sub <8 x i16> zeroinitializer, [[TMP18]] ; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw <8 x i32> [[TMP6]], [[TMP1]] @@ -55,8 +55,8 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[TMP24:%.*]] = mul <8 x i32> [[TMP22]], [[TMP10]] ; CHECK-NEXT: [[TMP25:%.*]] = lshr <8 x i32> [[TMP23]], ; CHECK-NEXT: [[TMP26:%.*]] = lshr <8 x i32> [[TMP24]], -; CHECK-NEXT: [[TMP27:%.*]] = trunc <8 x i32> [[TMP25]] to <8 x i16> -; CHECK-NEXT: [[TMP28:%.*]] = trunc <8 x i32> [[TMP26]] to <8 x i16> +; CHECK-NEXT: [[TMP27:%.*]] = trunc nuw <8 x i32> [[TMP25]] to <8 x i16> +; CHECK-NEXT: [[TMP28:%.*]] = trunc nuw <8 x i32> [[TMP26]] to <8 x i16> ; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP3]], <8 x i16> [[TMP27]], <8 x i16> [[TMP19]] ; CHECK-NEXT: [[PREDPHI34:%.*]] = select <8 x i1> [[TMP4]], <8 x i16> [[TMP28]], <8 x i16> [[TMP20]] ; CHECK-NEXT: store <8 x i16> [[PREDPHI]], ptr [[DCT]], align 2, !alias.scope [[META0]], !noalias [[META3]] @@ -83,13 +83,13 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[CONV5]], [[CONV]] ; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[ADD]], [[CONV11]] ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[MUL]], 16 -; CHECK-NEXT: [[CONV12:%.*]] = trunc i32 [[SHR]] to i16 +; CHECK-NEXT: [[CONV12:%.*]] = trunc nuw i32 [[SHR]] to i16 ; CHECK-NEXT: br label [[IF_END:%.*]] ; CHECK: if.else: ; CHECK-NEXT: [[ADD21:%.*]] = sub nsw i32 [[CONV5]], [[CONV]] ; CHECK-NEXT: [[MUL25:%.*]] = mul i32 [[ADD21]], [[CONV11]] ; CHECK-NEXT: [[SHR26:%.*]] = lshr i32 [[MUL25]], 16 -; CHECK-NEXT: [[TMP33:%.*]] = trunc i32 [[SHR26]] to i16 +; CHECK-NEXT: [[TMP33:%.*]] = trunc nuw i32 [[SHR26]] to i16 ; CHECK-NEXT: [[CONV28:%.*]] = sub i16 0, [[TMP33]] ; CHECK-NEXT: br label [[IF_END]] ; CHECK: if.end: @@ -110,14 +110,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_1:%.*]] = sub nsw i32 [[CONV5_1]], [[CONV_1]] ; CHECK-NEXT: [[MUL25_1:%.*]] = mul i32 [[ADD21_1]], [[CONV11_1]] ; CHECK-NEXT: [[SHR26_1:%.*]] = lshr i32 [[MUL25_1]], 16 -; CHECK-NEXT: [[TMP37:%.*]] = trunc i32 [[SHR26_1]] to i16 +; CHECK-NEXT: [[TMP37:%.*]] = trunc nuw i32 [[SHR26_1]] to i16 ; CHECK-NEXT: [[CONV28_1:%.*]] = sub i16 0, [[TMP37]] ; CHECK-NEXT: br label [[IF_END_1:%.*]] ; CHECK: if.then.1: ; CHECK-NEXT: [[ADD_1:%.*]] = add nuw nsw i32 [[CONV5_1]], [[CONV_1]] ; CHECK-NEXT: [[MUL_1:%.*]] = mul i32 [[ADD_1]], [[CONV11_1]] ; CHECK-NEXT: [[SHR_1:%.*]] = lshr i32 [[MUL_1]], 16 -; CHECK-NEXT: [[CONV12_1:%.*]] = trunc i32 [[SHR_1]] to i16 +; CHECK-NEXT: [[CONV12_1:%.*]] = trunc nuw i32 [[SHR_1]] to i16 ; CHECK-NEXT: br label [[IF_END_1]] ; CHECK: if.end.1: ; CHECK-NEXT: [[STOREMERGE_1:%.*]] = phi i16 [ [[CONV28_1]], [[IF_ELSE_1]] ], [ [[CONV12_1]], [[IF_THEN_1]] ] @@ -138,14 +138,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_2:%.*]] = sub nsw i32 [[CONV5_2]], [[CONV_2]] ; CHECK-NEXT: [[MUL25_2:%.*]] = mul i32 [[ADD21_2]], [[CONV11_2]] ; CHECK-NEXT: [[SHR26_2:%.*]] = lshr i32 [[MUL25_2]], 16 -; CHECK-NEXT: [[TMP41:%.*]] = trunc i32 [[SHR26_2]] to i16 +; CHECK-NEXT: [[TMP41:%.*]] = trunc nuw i32 [[SHR26_2]] to i16 ; CHECK-NEXT: [[CONV28_2:%.*]] = sub i16 0, [[TMP41]] ; CHECK-NEXT: br label [[IF_END_2:%.*]] ; CHECK: if.then.2: ; CHECK-NEXT: [[ADD_2:%.*]] = add nuw nsw i32 [[CONV5_2]], [[CONV_2]] ; CHECK-NEXT: [[MUL_2:%.*]] = mul i32 [[ADD_2]], [[CONV11_2]] ; CHECK-NEXT: [[SHR_2:%.*]] = lshr i32 [[MUL_2]], 16 -; CHECK-NEXT: [[CONV12_2:%.*]] = trunc i32 [[SHR_2]] to i16 +; CHECK-NEXT: [[CONV12_2:%.*]] = trunc nuw i32 [[SHR_2]] to i16 ; CHECK-NEXT: br label [[IF_END_2]] ; CHECK: if.end.2: ; CHECK-NEXT: [[STOREMERGE_2:%.*]] = phi i16 [ [[CONV28_2]], [[IF_ELSE_2]] ], [ [[CONV12_2]], [[IF_THEN_2]] ] @@ -166,14 +166,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_3:%.*]] = sub nsw i32 [[CONV5_3]], [[CONV_3]] ; CHECK-NEXT: [[MUL25_3:%.*]] = mul i32 [[ADD21_3]], [[CONV11_3]] ; CHECK-NEXT: [[SHR26_3:%.*]] = lshr i32 [[MUL25_3]], 16 -; CHECK-NEXT: [[TMP45:%.*]] = trunc i32 [[SHR26_3]] to i16 +; CHECK-NEXT: [[TMP45:%.*]] = trunc nuw i32 [[SHR26_3]] to i16 ; CHECK-NEXT: [[CONV28_3:%.*]] = sub i16 0, [[TMP45]] ; CHECK-NEXT: br label [[IF_END_3:%.*]] ; CHECK: if.then.3: ; CHECK-NEXT: [[ADD_3:%.*]] = add nuw nsw i32 [[CONV5_3]], [[CONV_3]] ; CHECK-NEXT: [[MUL_3:%.*]] = mul i32 [[ADD_3]], [[CONV11_3]] ; CHECK-NEXT: [[SHR_3:%.*]] = lshr i32 [[MUL_3]], 16 -; CHECK-NEXT: [[CONV12_3:%.*]] = trunc i32 [[SHR_3]] to i16 +; CHECK-NEXT: [[CONV12_3:%.*]] = trunc nuw i32 [[SHR_3]] to i16 ; CHECK-NEXT: br label [[IF_END_3]] ; CHECK: if.end.3: ; CHECK-NEXT: [[STOREMERGE_3:%.*]] = phi i16 [ [[CONV28_3]], [[IF_ELSE_3]] ], [ [[CONV12_3]], [[IF_THEN_3]] ] @@ -194,14 +194,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_4:%.*]] = sub nsw i32 [[CONV5_4]], [[CONV_4]] ; CHECK-NEXT: [[MUL25_4:%.*]] = mul i32 [[ADD21_4]], [[CONV11_4]] ; CHECK-NEXT: [[SHR26_4:%.*]] = lshr i32 [[MUL25_4]], 16 -; CHECK-NEXT: [[TMP49:%.*]] = trunc i32 [[SHR26_4]] to i16 +; CHECK-NEXT: [[TMP49:%.*]] = trunc nuw i32 [[SHR26_4]] to i16 ; CHECK-NEXT: [[CONV28_4:%.*]] = sub i16 0, [[TMP49]] ; CHECK-NEXT: br label [[IF_END_4:%.*]] ; CHECK: if.then.4: ; CHECK-NEXT: [[ADD_4:%.*]] = add nuw nsw i32 [[CONV5_4]], [[CONV_4]] ; CHECK-NEXT: [[MUL_4:%.*]] = mul i32 [[ADD_4]], [[CONV11_4]] ; CHECK-NEXT: [[SHR_4:%.*]] = lshr i32 [[MUL_4]], 16 -; CHECK-NEXT: [[CONV12_4:%.*]] = trunc i32 [[SHR_4]] to i16 +; CHECK-NEXT: [[CONV12_4:%.*]] = trunc nuw i32 [[SHR_4]] to i16 ; CHECK-NEXT: br label [[IF_END_4]] ; CHECK: if.end.4: ; CHECK-NEXT: [[STOREMERGE_4:%.*]] = phi i16 [ [[CONV28_4]], [[IF_ELSE_4]] ], [ [[CONV12_4]], [[IF_THEN_4]] ] @@ -222,14 +222,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_5:%.*]] = sub nsw i32 [[CONV5_5]], [[CONV_5]] ; CHECK-NEXT: [[MUL25_5:%.*]] = mul i32 [[ADD21_5]], [[CONV11_5]] ; CHECK-NEXT: [[SHR26_5:%.*]] = lshr i32 [[MUL25_5]], 16 -; CHECK-NEXT: [[TMP53:%.*]] = trunc i32 [[SHR26_5]] to i16 +; CHECK-NEXT: [[TMP53:%.*]] = trunc nuw i32 [[SHR26_5]] to i16 ; CHECK-NEXT: [[CONV28_5:%.*]] = sub i16 0, [[TMP53]] ; CHECK-NEXT: br label [[IF_END_5:%.*]] ; CHECK: if.then.5: ; CHECK-NEXT: [[ADD_5:%.*]] = add nuw nsw i32 [[CONV5_5]], [[CONV_5]] ; CHECK-NEXT: [[MUL_5:%.*]] = mul i32 [[ADD_5]], [[CONV11_5]] ; CHECK-NEXT: [[SHR_5:%.*]] = lshr i32 [[MUL_5]], 16 -; CHECK-NEXT: [[CONV12_5:%.*]] = trunc i32 [[SHR_5]] to i16 +; CHECK-NEXT: [[CONV12_5:%.*]] = trunc nuw i32 [[SHR_5]] to i16 ; CHECK-NEXT: br label [[IF_END_5]] ; CHECK: if.end.5: ; CHECK-NEXT: [[STOREMERGE_5:%.*]] = phi i16 [ [[CONV28_5]], [[IF_ELSE_5]] ], [ [[CONV12_5]], [[IF_THEN_5]] ] @@ -250,14 +250,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_6:%.*]] = sub nsw i32 [[CONV5_6]], [[CONV_6]] ; CHECK-NEXT: [[MUL25_6:%.*]] = mul i32 [[ADD21_6]], [[CONV11_6]] ; CHECK-NEXT: [[SHR26_6:%.*]] = lshr i32 [[MUL25_6]], 16 -; CHECK-NEXT: [[TMP57:%.*]] = trunc i32 [[SHR26_6]] to i16 +; CHECK-NEXT: [[TMP57:%.*]] = trunc nuw i32 [[SHR26_6]] to i16 ; CHECK-NEXT: [[CONV28_6:%.*]] = sub i16 0, [[TMP57]] ; CHECK-NEXT: br label [[IF_END_6:%.*]] ; CHECK: if.then.6: ; CHECK-NEXT: [[ADD_6:%.*]] = add nuw nsw i32 [[CONV5_6]], [[CONV_6]] ; CHECK-NEXT: [[MUL_6:%.*]] = mul i32 [[ADD_6]], [[CONV11_6]] ; CHECK-NEXT: [[SHR_6:%.*]] = lshr i32 [[MUL_6]], 16 -; CHECK-NEXT: [[CONV12_6:%.*]] = trunc i32 [[SHR_6]] to i16 +; CHECK-NEXT: [[CONV12_6:%.*]] = trunc nuw i32 [[SHR_6]] to i16 ; CHECK-NEXT: br label [[IF_END_6]] ; CHECK: if.end.6: ; CHECK-NEXT: [[STOREMERGE_6:%.*]] = phi i16 [ [[CONV28_6]], [[IF_ELSE_6]] ], [ [[CONV12_6]], [[IF_THEN_6]] ] @@ -278,14 +278,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_7:%.*]] = sub nsw i32 [[CONV5_7]], [[CONV_7]] ; CHECK-NEXT: [[MUL25_7:%.*]] = mul i32 [[ADD21_7]], [[CONV11_7]] ; CHECK-NEXT: [[SHR26_7:%.*]] = lshr i32 [[MUL25_7]], 16 -; CHECK-NEXT: [[TMP61:%.*]] = trunc i32 [[SHR26_7]] to i16 +; CHECK-NEXT: [[TMP61:%.*]] = trunc nuw i32 [[SHR26_7]] to i16 ; CHECK-NEXT: [[CONV28_7:%.*]] = sub i16 0, [[TMP61]] ; CHECK-NEXT: br label [[IF_END_7:%.*]] ; CHECK: if.then.7: ; CHECK-NEXT: [[ADD_7:%.*]] = add nuw nsw i32 [[CONV5_7]], [[CONV_7]] ; CHECK-NEXT: [[MUL_7:%.*]] = mul i32 [[ADD_7]], [[CONV11_7]] ; CHECK-NEXT: [[SHR_7:%.*]] = lshr i32 [[MUL_7]], 16 -; CHECK-NEXT: [[CONV12_7:%.*]] = trunc i32 [[SHR_7]] to i16 +; CHECK-NEXT: [[CONV12_7:%.*]] = trunc nuw i32 [[SHR_7]] to i16 ; CHECK-NEXT: br label [[IF_END_7]] ; CHECK: if.end.7: ; CHECK-NEXT: [[STOREMERGE_7:%.*]] = phi i16 [ [[CONV28_7]], [[IF_ELSE_7]] ], [ [[CONV12_7]], [[IF_THEN_7]] ] @@ -306,14 +306,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_8:%.*]] = sub nsw i32 [[CONV5_8]], [[CONV_8]] ; CHECK-NEXT: [[MUL25_8:%.*]] = mul i32 [[ADD21_8]], [[CONV11_8]] ; CHECK-NEXT: [[SHR26_8:%.*]] = lshr i32 [[MUL25_8]], 16 -; CHECK-NEXT: [[TMP65:%.*]] = trunc i32 [[SHR26_8]] to i16 +; CHECK-NEXT: [[TMP65:%.*]] = trunc nuw i32 [[SHR26_8]] to i16 ; CHECK-NEXT: [[CONV28_8:%.*]] = sub i16 0, [[TMP65]] ; CHECK-NEXT: br label [[IF_END_8:%.*]] ; CHECK: if.then.8: ; CHECK-NEXT: [[ADD_8:%.*]] = add nuw nsw i32 [[CONV5_8]], [[CONV_8]] ; CHECK-NEXT: [[MUL_8:%.*]] = mul i32 [[ADD_8]], [[CONV11_8]] ; CHECK-NEXT: [[SHR_8:%.*]] = lshr i32 [[MUL_8]], 16 -; CHECK-NEXT: [[CONV12_8:%.*]] = trunc i32 [[SHR_8]] to i16 +; CHECK-NEXT: [[CONV12_8:%.*]] = trunc nuw i32 [[SHR_8]] to i16 ; CHECK-NEXT: br label [[IF_END_8]] ; CHECK: if.end.8: ; CHECK-NEXT: [[STOREMERGE_8:%.*]] = phi i16 [ [[CONV28_8]], [[IF_ELSE_8]] ], [ [[CONV12_8]], [[IF_THEN_8]] ] @@ -334,14 +334,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_9:%.*]] = sub nsw i32 [[CONV5_9]], [[CONV_9]] ; CHECK-NEXT: [[MUL25_9:%.*]] = mul i32 [[ADD21_9]], [[CONV11_9]] ; CHECK-NEXT: [[SHR26_9:%.*]] = lshr i32 [[MUL25_9]], 16 -; CHECK-NEXT: [[TMP69:%.*]] = trunc i32 [[SHR26_9]] to i16 +; CHECK-NEXT: [[TMP69:%.*]] = trunc nuw i32 [[SHR26_9]] to i16 ; CHECK-NEXT: [[CONV28_9:%.*]] = sub i16 0, [[TMP69]] ; CHECK-NEXT: br label [[IF_END_9:%.*]] ; CHECK: if.then.9: ; CHECK-NEXT: [[ADD_9:%.*]] = add nuw nsw i32 [[CONV5_9]], [[CONV_9]] ; CHECK-NEXT: [[MUL_9:%.*]] = mul i32 [[ADD_9]], [[CONV11_9]] ; CHECK-NEXT: [[SHR_9:%.*]] = lshr i32 [[MUL_9]], 16 -; CHECK-NEXT: [[CONV12_9:%.*]] = trunc i32 [[SHR_9]] to i16 +; CHECK-NEXT: [[CONV12_9:%.*]] = trunc nuw i32 [[SHR_9]] to i16 ; CHECK-NEXT: br label [[IF_END_9]] ; CHECK: if.end.9: ; CHECK-NEXT: [[STOREMERGE_9:%.*]] = phi i16 [ [[CONV28_9]], [[IF_ELSE_9]] ], [ [[CONV12_9]], [[IF_THEN_9]] ] @@ -362,14 +362,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_10:%.*]] = sub nsw i32 [[CONV5_10]], [[CONV_10]] ; CHECK-NEXT: [[MUL25_10:%.*]] = mul i32 [[ADD21_10]], [[CONV11_10]] ; CHECK-NEXT: [[SHR26_10:%.*]] = lshr i32 [[MUL25_10]], 16 -; CHECK-NEXT: [[TMP73:%.*]] = trunc i32 [[SHR26_10]] to i16 +; CHECK-NEXT: [[TMP73:%.*]] = trunc nuw i32 [[SHR26_10]] to i16 ; CHECK-NEXT: [[CONV28_10:%.*]] = sub i16 0, [[TMP73]] ; CHECK-NEXT: br label [[IF_END_10:%.*]] ; CHECK: if.then.10: ; CHECK-NEXT: [[ADD_10:%.*]] = add nuw nsw i32 [[CONV5_10]], [[CONV_10]] ; CHECK-NEXT: [[MUL_10:%.*]] = mul i32 [[ADD_10]], [[CONV11_10]] ; CHECK-NEXT: [[SHR_10:%.*]] = lshr i32 [[MUL_10]], 16 -; CHECK-NEXT: [[CONV12_10:%.*]] = trunc i32 [[SHR_10]] to i16 +; CHECK-NEXT: [[CONV12_10:%.*]] = trunc nuw i32 [[SHR_10]] to i16 ; CHECK-NEXT: br label [[IF_END_10]] ; CHECK: if.end.10: ; CHECK-NEXT: [[STOREMERGE_10:%.*]] = phi i16 [ [[CONV28_10]], [[IF_ELSE_10]] ], [ [[CONV12_10]], [[IF_THEN_10]] ] @@ -390,14 +390,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_11:%.*]] = sub nsw i32 [[CONV5_11]], [[CONV_11]] ; CHECK-NEXT: [[MUL25_11:%.*]] = mul i32 [[ADD21_11]], [[CONV11_11]] ; CHECK-NEXT: [[SHR26_11:%.*]] = lshr i32 [[MUL25_11]], 16 -; CHECK-NEXT: [[TMP77:%.*]] = trunc i32 [[SHR26_11]] to i16 +; CHECK-NEXT: [[TMP77:%.*]] = trunc nuw i32 [[SHR26_11]] to i16 ; CHECK-NEXT: [[CONV28_11:%.*]] = sub i16 0, [[TMP77]] ; CHECK-NEXT: br label [[IF_END_11:%.*]] ; CHECK: if.then.11: ; CHECK-NEXT: [[ADD_11:%.*]] = add nuw nsw i32 [[CONV5_11]], [[CONV_11]] ; CHECK-NEXT: [[MUL_11:%.*]] = mul i32 [[ADD_11]], [[CONV11_11]] ; CHECK-NEXT: [[SHR_11:%.*]] = lshr i32 [[MUL_11]], 16 -; CHECK-NEXT: [[CONV12_11:%.*]] = trunc i32 [[SHR_11]] to i16 +; CHECK-NEXT: [[CONV12_11:%.*]] = trunc nuw i32 [[SHR_11]] to i16 ; CHECK-NEXT: br label [[IF_END_11]] ; CHECK: if.end.11: ; CHECK-NEXT: [[STOREMERGE_11:%.*]] = phi i16 [ [[CONV28_11]], [[IF_ELSE_11]] ], [ [[CONV12_11]], [[IF_THEN_11]] ] @@ -418,14 +418,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_12:%.*]] = sub nsw i32 [[CONV5_12]], [[CONV_12]] ; CHECK-NEXT: [[MUL25_12:%.*]] = mul i32 [[ADD21_12]], [[CONV11_12]] ; CHECK-NEXT: [[SHR26_12:%.*]] = lshr i32 [[MUL25_12]], 16 -; CHECK-NEXT: [[TMP81:%.*]] = trunc i32 [[SHR26_12]] to i16 +; CHECK-NEXT: [[TMP81:%.*]] = trunc nuw i32 [[SHR26_12]] to i16 ; CHECK-NEXT: [[CONV28_12:%.*]] = sub i16 0, [[TMP81]] ; CHECK-NEXT: br label [[IF_END_12:%.*]] ; CHECK: if.then.12: ; CHECK-NEXT: [[ADD_12:%.*]] = add nuw nsw i32 [[CONV5_12]], [[CONV_12]] ; CHECK-NEXT: [[MUL_12:%.*]] = mul i32 [[ADD_12]], [[CONV11_12]] ; CHECK-NEXT: [[SHR_12:%.*]] = lshr i32 [[MUL_12]], 16 -; CHECK-NEXT: [[CONV12_12:%.*]] = trunc i32 [[SHR_12]] to i16 +; CHECK-NEXT: [[CONV12_12:%.*]] = trunc nuw i32 [[SHR_12]] to i16 ; CHECK-NEXT: br label [[IF_END_12]] ; CHECK: if.end.12: ; CHECK-NEXT: [[STOREMERGE_12:%.*]] = phi i16 [ [[CONV28_12]], [[IF_ELSE_12]] ], [ [[CONV12_12]], [[IF_THEN_12]] ] @@ -446,14 +446,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_13:%.*]] = sub nsw i32 [[CONV5_13]], [[CONV_13]] ; CHECK-NEXT: [[MUL25_13:%.*]] = mul i32 [[ADD21_13]], [[CONV11_13]] ; CHECK-NEXT: [[SHR26_13:%.*]] = lshr i32 [[MUL25_13]], 16 -; CHECK-NEXT: [[TMP85:%.*]] = trunc i32 [[SHR26_13]] to i16 +; CHECK-NEXT: [[TMP85:%.*]] = trunc nuw i32 [[SHR26_13]] to i16 ; CHECK-NEXT: [[CONV28_13:%.*]] = sub i16 0, [[TMP85]] ; CHECK-NEXT: br label [[IF_END_13:%.*]] ; CHECK: if.then.13: ; CHECK-NEXT: [[ADD_13:%.*]] = add nuw nsw i32 [[CONV5_13]], [[CONV_13]] ; CHECK-NEXT: [[MUL_13:%.*]] = mul i32 [[ADD_13]], [[CONV11_13]] ; CHECK-NEXT: [[SHR_13:%.*]] = lshr i32 [[MUL_13]], 16 -; CHECK-NEXT: [[CONV12_13:%.*]] = trunc i32 [[SHR_13]] to i16 +; CHECK-NEXT: [[CONV12_13:%.*]] = trunc nuw i32 [[SHR_13]] to i16 ; CHECK-NEXT: br label [[IF_END_13]] ; CHECK: if.end.13: ; CHECK-NEXT: [[STOREMERGE_13:%.*]] = phi i16 [ [[CONV28_13]], [[IF_ELSE_13]] ], [ [[CONV12_13]], [[IF_THEN_13]] ] @@ -474,14 +474,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_14:%.*]] = sub nsw i32 [[CONV5_14]], [[CONV_14]] ; CHECK-NEXT: [[MUL25_14:%.*]] = mul i32 [[ADD21_14]], [[CONV11_14]] ; CHECK-NEXT: [[SHR26_14:%.*]] = lshr i32 [[MUL25_14]], 16 -; CHECK-NEXT: [[TMP89:%.*]] = trunc i32 [[SHR26_14]] to i16 +; CHECK-NEXT: [[TMP89:%.*]] = trunc nuw i32 [[SHR26_14]] to i16 ; CHECK-NEXT: [[CONV28_14:%.*]] = sub i16 0, [[TMP89]] ; CHECK-NEXT: br label [[IF_END_14:%.*]] ; CHECK: if.then.14: ; CHECK-NEXT: [[ADD_14:%.*]] = add nuw nsw i32 [[CONV5_14]], [[CONV_14]] ; CHECK-NEXT: [[MUL_14:%.*]] = mul i32 [[ADD_14]], [[CONV11_14]] ; CHECK-NEXT: [[SHR_14:%.*]] = lshr i32 [[MUL_14]], 16 -; CHECK-NEXT: [[CONV12_14:%.*]] = trunc i32 [[SHR_14]] to i16 +; CHECK-NEXT: [[CONV12_14:%.*]] = trunc nuw i32 [[SHR_14]] to i16 ; CHECK-NEXT: br label [[IF_END_14]] ; CHECK: if.end.14: ; CHECK-NEXT: [[STOREMERGE_14:%.*]] = phi i16 [ [[CONV28_14]], [[IF_ELSE_14]] ], [ [[CONV12_14]], [[IF_THEN_14]] ] @@ -502,14 +502,14 @@ define i32 @quant_4x4(ptr noundef %dct, ptr noundef %mf, ptr noundef %bias) { ; CHECK-NEXT: [[ADD21_15:%.*]] = sub nsw i32 [[CONV5_15]], [[CONV_15]] ; CHECK-NEXT: [[MUL25_15:%.*]] = mul i32 [[ADD21_15]], [[CONV11_15]] ; CHECK-NEXT: [[SHR26_15:%.*]] = lshr i32 [[MUL25_15]], 16 -; CHECK-NEXT: [[TMP93:%.*]] = trunc i32 [[SHR26_15]] to i16 +; CHECK-NEXT: [[TMP93:%.*]] = trunc nuw i32 [[SHR26_15]] to i16 ; CHECK-NEXT: [[CONV28_15:%.*]] = sub i16 0, [[TMP93]] ; CHECK-NEXT: br label [[IF_END_15]] ; CHECK: if.then.15: ; CHECK-NEXT: [[ADD_15:%.*]] = add nuw nsw i32 [[CONV5_15]], [[CONV_15]] ; CHECK-NEXT: [[MUL_15:%.*]] = mul i32 [[ADD_15]], [[CONV11_15]] ; CHECK-NEXT: [[SHR_15:%.*]] = lshr i32 [[MUL_15]], 16 -; CHECK-NEXT: [[CONV12_15:%.*]] = trunc i32 [[SHR_15]] to i16 +; CHECK-NEXT: [[CONV12_15:%.*]] = trunc nuw i32 [[SHR_15]] to i16 ; CHECK-NEXT: br label [[IF_END_15]] ; CHECK: if.end.15: ; CHECK-NEXT: [[STOREMERGE_15:%.*]] = phi i16 [ [[CONV28_15]], [[IF_ELSE_15]] ], [ [[CONV12_15]], [[IF_THEN_15]] ] diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll index c38f2748a976..75505f632a43 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll @@ -55,7 +55,7 @@ define void @store_i8(ptr nocapture %0, i32 %1, i32 %2) { ; CHECK-NEXT: [[TMP8:%.*]] = mul <4 x i32> [[TMP7]], [[TMP5]] ; CHECK-NEXT: [[TMP9:%.*]] = lshr <4 x i32> [[TMP8]], ; CHECK-NEXT: [[TMP10:%.*]] = call <4 x i32> @llvm.umin.v4i32(<4 x i32> [[TMP9]], <4 x i32> ) -; CHECK-NEXT: [[TMP11:%.*]] = trunc <4 x i32> [[TMP10]] to <4 x i8> +; CHECK-NEXT: [[TMP11:%.*]] = trunc nuw <4 x i32> [[TMP10]] to <4 x i8> ; CHECK-NEXT: store <4 x i8> [[TMP11]], ptr [[TMP0]], align 1, !tbaa [[TBAA4]] ; CHECK-NEXT: ret void ; -- GitLab From 496de32ee2c34880c7d3396bbd09e45d5d5c8a9e Mon Sep 17 00:00:00 2001 From: paperchalice Date: Thu, 11 Apr 2024 19:13:06 +0800 Subject: [PATCH 521/695] [NewPM] Remove `MachinePassInfoMixin` (#88243) Unify the inheritance paths of IR and machine function. --- .../llvm/CodeGen/DeadMachineInstructionElim.h | 2 +- .../llvm/CodeGen/FreeMachineFunction.h | 3 +- llvm/include/llvm/CodeGen/MIRPrinter.h | 4 +- .../include/llvm/CodeGen/MachinePassManager.h | 108 +++++++----------- llvm/include/llvm/Passes/CodeGenPassBuilder.h | 4 +- llvm/include/llvm/Passes/PassBuilder.h | 3 +- llvm/lib/Passes/PassBuilder.cpp | 2 +- .../MIR/PassBuilderCallbacksTest.cpp | 2 +- 8 files changed, 49 insertions(+), 79 deletions(-) diff --git a/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h b/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h index b9fe7cfccf9a..56cfa1e08718 100644 --- a/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h +++ b/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h @@ -14,7 +14,7 @@ namespace llvm { class DeadMachineInstructionElimPass - : public MachinePassInfoMixin { + : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); diff --git a/llvm/include/llvm/CodeGen/FreeMachineFunction.h b/llvm/include/llvm/CodeGen/FreeMachineFunction.h index 77b76c591201..5f21c6720350 100644 --- a/llvm/include/llvm/CodeGen/FreeMachineFunction.h +++ b/llvm/include/llvm/CodeGen/FreeMachineFunction.h @@ -13,8 +13,7 @@ namespace llvm { -class FreeMachineFunctionPass - : public MachinePassInfoMixin { +class FreeMachineFunctionPass : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM); diff --git a/llvm/include/llvm/CodeGen/MIRPrinter.h b/llvm/include/llvm/CodeGen/MIRPrinter.h index daa0d7e2691f..d0a11e1c4a2f 100644 --- a/llvm/include/llvm/CodeGen/MIRPrinter.h +++ b/llvm/include/llvm/CodeGen/MIRPrinter.h @@ -24,7 +24,7 @@ class MachineFunction; class Module; template class SmallVectorImpl; -class PrintMIRPreparePass : public MachinePassInfoMixin { +class PrintMIRPreparePass : public PassInfoMixin { raw_ostream &OS; public: @@ -32,7 +32,7 @@ public: PreservedAnalyses run(Module &M, ModuleAnalysisManager &MFAM); }; -class PrintMIRPass : public MachinePassInfoMixin { +class PrintMIRPass : public PassInfoMixin { raw_ostream &OS; public: diff --git a/llvm/include/llvm/CodeGen/MachinePassManager.h b/llvm/include/llvm/CodeGen/MachinePassManager.h index 8689fd19030f..4f0b6ba2b1e7 100644 --- a/llvm/include/llvm/CodeGen/MachinePassManager.h +++ b/llvm/include/llvm/CodeGen/MachinePassManager.h @@ -36,65 +36,6 @@ class MachineFunction; extern template class AnalysisManager; using MachineFunctionAnalysisManager = AnalysisManager; -/// A CRTP mix-in that provides informational APIs needed for machine passes. -/// -/// This provides some boilerplate for types that are machine passes. It -/// automatically mixes in \c PassInfoMixin. -template -struct MachinePassInfoMixin : public PassInfoMixin { -protected: - class PropertyChanger { - MachineFunction &MF; - - template - using has_get_required_properties_t = - decltype(std::declval().getRequiredProperties()); - - template - using has_get_set_properties_t = - decltype(std::declval().getSetProperties()); - - template - using has_get_cleared_properties_t = - decltype(std::declval().getClearedProperties()); - - public: - PropertyChanger(MachineFunction &MF) : MF(MF) { -#ifndef NDEBUG - if constexpr (is_detected::value) { - auto &MFProps = MF.getProperties(); - auto RequiredProperties = DerivedT::getRequiredProperties(); - if (!MFProps.verifyRequiredProperties(RequiredProperties)) { - errs() << "MachineFunctionProperties required by " << DerivedT::name() - << " pass are not met by function " << MF.getName() << ".\n" - << "Required properties: "; - RequiredProperties.print(errs()); - errs() << "\nCurrent properties: "; - MFProps.print(errs()); - errs() << '\n'; - report_fatal_error("MachineFunctionProperties check failed"); - } - } -#endif - } - - ~PropertyChanger() { - if constexpr (is_detected::value) - MF.getProperties().set(DerivedT::getSetProperties()); - if constexpr (is_detected::value) - MF.getProperties().reset(DerivedT::getClearedProperties()); - } - }; - -public: - PreservedAnalyses runImpl(MachineFunction &MF, - MachineFunctionAnalysisManager &MFAM) { - PropertyChanger PC(MF); - return static_cast(this)->run(MF, MFAM); - } -}; - namespace detail { template @@ -117,8 +58,44 @@ struct MachinePassModel MachinePassModel &operator=(const MachinePassModel &) = delete; PreservedAnalyses run(MachineFunction &IR, MachineFunctionAnalysisManager &AM) override { - return this->Pass.runImpl(IR, AM); +#ifndef NDEBUG + if constexpr (is_detected::value) { + auto &MFProps = IR.getProperties(); + auto RequiredProperties = PassT::getRequiredProperties(); + if (!MFProps.verifyRequiredProperties(RequiredProperties)) { + errs() << "MachineFunctionProperties required by " << PassT::name() + << " pass are not met by function " << IR.getName() << ".\n" + << "Required properties: "; + RequiredProperties.print(errs()); + errs() << "\nCurrent properties: "; + MFProps.print(errs()); + errs() << '\n'; + report_fatal_error("MachineFunctionProperties check failed"); + } + } +#endif + + auto PA = this->Pass.run(IR, AM); + + if constexpr (is_detected::value) + IR.getProperties().set(PassT::getSetProperties()); + if constexpr (is_detected::value) + IR.getProperties().reset(PassT::getClearedProperties()); + return PA; } + +private: + template + using has_get_required_properties_t = + decltype(std::declval().getRequiredProperties()); + + template + using has_get_set_properties_t = + decltype(std::declval().getSetProperties()); + + template + using has_get_cleared_properties_t = + decltype(std::declval().getClearedProperties()); }; } // namespace detail @@ -246,20 +223,15 @@ createModuleToMachineFunctionPassAdaptor(MachineFunctionPassT &&Pass) { template <> template void PassManager::addPass(PassT &&Pass) { - using PassModelT = - detail::PassModel; using MachinePassModelT = detail::MachinePassModel; // Do not use make_unique or emplace_back, they cause too many template // instantiations, causing terrible compile times. - if constexpr (std::is_base_of_v, PassT>) { - Passes.push_back(std::unique_ptr( - new MachinePassModelT(std::forward(Pass)))); - } else if constexpr (std::is_same_v>) { + if constexpr (std::is_same_v>) { for (auto &P : Pass.Passes) Passes.push_back(std::move(P)); } else { - Passes.push_back(std::unique_ptr( - new PassModelT(std::forward(Pass)))); + Passes.push_back(std::unique_ptr( + new MachinePassModelT(std::forward(Pass)))); } } diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index ab231dbbb6a6..ed5d8affa793 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -87,14 +87,14 @@ namespace llvm { } \ }; #define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \ - struct PASS_NAME : public MachinePassInfoMixin { \ + struct PASS_NAME : public PassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ PreservedAnalyses run(Module &, ModuleAnalysisManager &) { \ return PreservedAnalyses::all(); \ } \ }; #define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \ - struct PASS_NAME : public MachinePassInfoMixin { \ + struct PASS_NAME : public PassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ PreservedAnalyses run(MachineFunction &, \ MachineFunctionAnalysisManager &) { \ diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h index d1232124d5d8..c8f643452bb1 100644 --- a/llvm/include/llvm/Passes/PassBuilder.h +++ b/llvm/include/llvm/Passes/PassBuilder.h @@ -909,8 +909,7 @@ struct NoOpLoopPass : PassInfoMixin { }; /// No-op machine function pass which does nothing. -struct NoOpMachineFunctionPass - : public MachinePassInfoMixin { +struct NoOpMachineFunctionPass : public PassInfoMixin { PreservedAnalyses run(MachineFunction &, MachineFunctionAnalysisManager &) { return PreservedAnalyses::all(); } diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 832ee352205a..8d408ca2363a 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -368,7 +368,7 @@ public: // A pass requires all MachineFunctionProperties. // DO NOT USE THIS EXCEPT FOR TESTING! class RequireAllMachineFunctionPropertiesPass - : public MachinePassInfoMixin { + : public PassInfoMixin { public: PreservedAnalyses run(MachineFunction &, MachineFunctionAnalysisManager &) { return PreservedAnalyses::none(); diff --git a/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp b/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp index 8e3738dc9192..6fd4e54a929f 100644 --- a/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp +++ b/llvm/unittests/MIR/PassBuilderCallbacksTest.cpp @@ -233,7 +233,7 @@ protected: template class MockPassHandleBase { public: - class Pass : public MachinePassInfoMixin { + class Pass : public PassInfoMixin { friend MockPassHandleBase; DerivedT *Handle; -- GitLab From a6db20f2c39ecb5939890317068d5398c760746d Mon Sep 17 00:00:00 2001 From: Marc Auberer Date: Thu, 11 Apr 2024 14:15:16 +0200 Subject: [PATCH 522/695] [libcxx] Use generic builtins for popcount, clz and ctz (#86563) Fixes #86556 Use `__builtin_popcountg` instead of `__buildin_popcount{l|ll}` Use `__builtin_clzg instead` of `__buildin_clz{l|ll}` Use `__builtin_ctzg instead` of `__builtin_ctz{l|ll}` The generic variant of the builtins can be used to simplify some logic with >= Clang 19 or >= GCC 14, where these generic variants are available. As for backwards compatibility reasons, we can't completely remove the old logic. Therefore, I left ToDo comments to address this, as soon as support for pre Clang 19 as well as pre GCC 14 is dropped. --------- Co-authored-by: Nick Desaulniers --- libcxx/include/__bit/countl.h | 11 +++++++++++ libcxx/include/__bit/countr.h | 8 +++++++- libcxx/include/__bit/popcount.h | 7 +++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/libcxx/include/__bit/countl.h b/libcxx/include/__bit/countl.h index 396cfc2c3f40..13df8d4e66c4 100644 --- a/libcxx/include/__bit/countl.h +++ b/libcxx/include/__bit/countl.h @@ -6,6 +6,9 @@ // //===----------------------------------------------------------------------===// +// TODO: __builtin_clzg is available since Clang 19 and GCC 14. When support for older versions is dropped, we can +// refactor this code to exclusively use __builtin_clzg. + #ifndef _LIBCPP___BIT_COUNTL_H #define _LIBCPP___BIT_COUNTL_H @@ -38,6 +41,9 @@ _LIBCPP_NODISCARD inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR int __libcpp_cl #ifndef _LIBCPP_HAS_NO_INT128 inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR int __libcpp_clz(__uint128_t __x) _NOEXCEPT { +# if __has_builtin(__builtin_clzg) + return __builtin_clzg(__x); +# else // The function is written in this form due to C++ constexpr limitations. // The algorithm: // - Test whether any bit in the high 64-bits is set @@ -49,12 +55,16 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR int __libcpp_clz(__uint128_t __x) // zeros in the high 64-bits. return ((__x >> 64) == 0) ? (64 + __builtin_clzll(static_cast(__x))) : __builtin_clzll(static_cast(__x >> 64)); +# endif } #endif // _LIBCPP_HAS_NO_INT128 template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int __countl_zero(_Tp __t) _NOEXCEPT { static_assert(__libcpp_is_unsigned_integer<_Tp>::value, "__countl_zero requires an unsigned integer type"); +#if __has_builtin(__builtin_clzg) + return __builtin_clzg(__t, numeric_limits<_Tp>::digits); +#else // __has_builtin(__builtin_clzg) if (__t == 0) return numeric_limits<_Tp>::digits; @@ -79,6 +89,7 @@ _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int __countl_zero(_Tp __t) _ } return __ret + __iter; } +#endif // __has_builtin(__builtin_clzg) } #if _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__bit/countr.h b/libcxx/include/__bit/countr.h index b6b3ac52ca4e..724a0bc23801 100644 --- a/libcxx/include/__bit/countr.h +++ b/libcxx/include/__bit/countr.h @@ -6,6 +6,9 @@ // //===----------------------------------------------------------------------===// +// TODO: __builtin_ctzg is available since Clang 19 and GCC 14. When support for older versions is dropped, we can +// refactor this code to exclusively use __builtin_ctzg. + #ifndef _LIBCPP___BIT_COUNTR_H #define _LIBCPP___BIT_COUNTR_H @@ -37,9 +40,11 @@ _LIBCPP_NODISCARD inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR int __libcpp_ct template _LIBCPP_NODISCARD _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int __countr_zero(_Tp __t) _NOEXCEPT { +#if __has_builtin(__builtin_ctzg) + return __builtin_ctzg(__t, numeric_limits<_Tp>::digits); +#else // __has_builtin(__builtin_ctzg) if (__t == 0) return numeric_limits<_Tp>::digits; - if (sizeof(_Tp) <= sizeof(unsigned int)) return std::__libcpp_ctz(static_cast(__t)); else if (sizeof(_Tp) <= sizeof(unsigned long)) @@ -55,6 +60,7 @@ _LIBCPP_NODISCARD _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 int __coun } return __ret + std::__libcpp_ctz(static_cast(__t)); } +#endif // __has_builtin(__builtin_ctzg) } #if _LIBCPP_STD_VER >= 20 diff --git a/libcxx/include/__bit/popcount.h b/libcxx/include/__bit/popcount.h index b0319cef2518..37b3a3e1f3f2 100644 --- a/libcxx/include/__bit/popcount.h +++ b/libcxx/include/__bit/popcount.h @@ -6,6 +6,9 @@ // //===----------------------------------------------------------------------===// +// TODO: __builtin_popcountg is available since Clang 19 and GCC 14. When support for older versions is dropped, we can +// refactor this code to exclusively use __builtin_popcountg. + #ifndef _LIBCPP___BIT_POPCOUNT_H #define _LIBCPP___BIT_POPCOUNT_H @@ -39,6 +42,9 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR int __libcpp_popcount(unsigned lo template <__libcpp_unsigned_integer _Tp> _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI constexpr int popcount(_Tp __t) noexcept { +# if __has_builtin(__builtin_popcountg) + return __builtin_popcountg(__t); +# else // __has_builtin(__builtin_popcountg) if (sizeof(_Tp) <= sizeof(unsigned int)) return std::__libcpp_popcount(static_cast(__t)); else if (sizeof(_Tp) <= sizeof(unsigned long)) @@ -53,6 +59,7 @@ _LIBCPP_NODISCARD_EXT _LIBCPP_HIDE_FROM_ABI constexpr int popcount(_Tp __t) noex } return __ret; } +# endif // __has_builtin(__builtin_popcountg) } #endif // _LIBCPP_STD_VER >= 20 -- GitLab From 402f15ea92061d94412807887c8115374974967e Mon Sep 17 00:00:00 2001 From: martinboehme Date: Thu, 11 Apr 2024 14:38:18 +0200 Subject: [PATCH 523/695] [clang][dataflow] Remove deprecated alias `ControlFlowContext`. (#88358) --- clang/docs/tools/clang-formatted-files.txt | 1 - .../FlowSensitive/ControlFlowContext.h | 27 ------------------- 2 files changed, 28 deletions(-) delete mode 100644 clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt index 8fd4fed25a32..3089438c23d9 100644 --- a/clang/docs/tools/clang-formatted-files.txt +++ b/clang/docs/tools/clang-formatted-files.txt @@ -123,7 +123,6 @@ clang/include/clang/Analysis/Analyses/CalledOnceCheck.h clang/include/clang/Analysis/Analyses/CFGReachabilityAnalysis.h clang/include/clang/Analysis/Analyses/ExprMutationAnalyzer.h clang/include/clang/Analysis/FlowSensitive/AdornedCFG.h -clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h clang/include/clang/Analysis/FlowSensitive/DataflowAnalysis.h clang/include/clang/Analysis/FlowSensitive/DataflowAnalysisContext.h clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h diff --git a/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h b/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h deleted file mode 100644 index 3972962d0b2d..000000000000 --- a/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h +++ /dev/null @@ -1,27 +0,0 @@ -//===-- ControlFlowContext.h ------------------------------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file defines a deprecated alias for AdornedCFG. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CLANG_ANALYSIS_FLOWSENSITIVE_CONTROLFLOWCONTEXT_H -#define LLVM_CLANG_ANALYSIS_FLOWSENSITIVE_CONTROLFLOWCONTEXT_H - -#include "clang/Analysis/FlowSensitive/AdornedCFG.h" - -namespace clang { -namespace dataflow { - -// This is a deprecated alias. Use `AdornedCFG` instead. -using ControlFlowContext = AdornedCFG; - -} // namespace dataflow -} // namespace clang - -#endif // LLVM_CLANG_ANALYSIS_FLOWSENSITIVE_CONTROLFLOWCONTEXT_H -- GitLab From 6fd2fdccf2f28fc155f614eec41f785492aad618 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 14:02:56 +0100 Subject: [PATCH 524/695] [VectorCombine] foldShuffleOfCastops - extend shuffle(bitcast(x),bitcast(y)) -> bitcast(shuffle(x,y)) support Handle shuffle mask scaling handling for cases where the bitcast src/dst element counts are different --- clang/test/CodeGen/X86/avx-shuffle-builtins.c | 3 +- .../Transforms/Vectorize/VectorCombine.cpp | 40 ++++++++++++++----- .../Transforms/PhaseOrdering/X86/pr67803.ll | 5 +-- .../VectorCombine/X86/shuffle-of-casts.ll | 14 +++---- .../Transforms/VectorCombine/X86/shuffle.ll | 5 ++- 5 files changed, 43 insertions(+), 24 deletions(-) diff --git a/clang/test/CodeGen/X86/avx-shuffle-builtins.c b/clang/test/CodeGen/X86/avx-shuffle-builtins.c index 49a56e73230d..d184d28f3e07 100644 --- a/clang/test/CodeGen/X86/avx-shuffle-builtins.c +++ b/clang/test/CodeGen/X86/avx-shuffle-builtins.c @@ -61,8 +61,7 @@ __m256 test_mm256_permute2f128_ps(__m256 a, __m256 b) { __m256i test_mm256_permute2f128_si256(__m256i a, __m256i b) { // CHECK-LABEL: test_mm256_permute2f128_si256 - // X64: shufflevector{{.*}} - // X86: shufflevector{{.*}} + // CHECK: shufflevector{{.*}} return _mm256_permute2f128_si256(a, b, 0x20); } diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index b74fdf27d213..658e8e74fe5b 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1448,9 +1448,9 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) { /// into "castop (shuffle)". bool VectorCombine::foldShuffleOfCastops(Instruction &I) { Value *V0, *V1; - ArrayRef Mask; + ArrayRef OldMask; if (!match(&I, m_Shuffle(m_OneUse(m_Value(V0)), m_OneUse(m_Value(V1)), - m_Mask(Mask)))) + m_Mask(OldMask)))) return false; auto *C0 = dyn_cast(V0); @@ -1473,12 +1473,32 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { auto *ShuffleDstTy = dyn_cast(I.getType()); auto *CastDstTy = dyn_cast(C0->getDestTy()); auto *CastSrcTy = dyn_cast(C0->getSrcTy()); - if (!ShuffleDstTy || !CastDstTy || !CastSrcTy || - CastDstTy->getElementCount() != CastSrcTy->getElementCount()) + if (!ShuffleDstTy || !CastDstTy || !CastSrcTy) return false; + unsigned NumSrcElts = CastSrcTy->getNumElements(); + unsigned NumDstElts = CastDstTy->getNumElements(); + assert((NumDstElts == NumSrcElts || Opcode == Instruction::BitCast) && + "Only bitcasts expected to alter src/dst element counts"); + + SmallVector NewMask; + if (NumSrcElts >= NumDstElts) { + // The bitcast is from wide to narrow/equal elements. The shuffle mask can + // always be expanded to the equivalent form choosing narrower elements. + assert(NumSrcElts % NumDstElts == 0 && "Unexpected shuffle mask"); + unsigned ScaleFactor = NumSrcElts / NumDstElts; + narrowShuffleMaskElts(ScaleFactor, OldMask, NewMask); + } else { + // The bitcast is from narrow elements to wide elements. The shuffle mask + // must choose consecutive elements to allow casting first. + assert(NumDstElts % NumSrcElts == 0 && "Unexpected shuffle mask"); + unsigned ScaleFactor = NumDstElts / NumSrcElts; + if (!widenShuffleMaskElts(ScaleFactor, OldMask, NewMask)) + return false; + } + auto *NewShuffleDstTy = - FixedVectorType::get(CastSrcTy->getScalarType(), Mask.size()); + FixedVectorType::get(CastSrcTy->getScalarType(), NewMask.size()); // Try to replace a castop with a shuffle if the shuffle is not costly. TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; @@ -1489,11 +1509,11 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { TTI.getCastInstrCost(C1->getOpcode(), CastDstTy, CastSrcTy, TTI::CastContextHint::None, CostKind); OldCost += - TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, CastDstTy, Mask, - CostKind, 0, nullptr, std::nullopt, &I); + TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, CastDstTy, + OldMask, CostKind, 0, nullptr, std::nullopt, &I); InstructionCost NewCost = TTI.getShuffleCost( - TargetTransformInfo::SK_PermuteTwoSrc, CastSrcTy, Mask, CostKind); + TargetTransformInfo::SK_PermuteTwoSrc, CastSrcTy, NewMask, CostKind); NewCost += TTI.getCastInstrCost(Opcode, ShuffleDstTy, NewShuffleDstTy, TTI::CastContextHint::None, CostKind); @@ -1503,8 +1523,8 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { if (NewCost > OldCost) return false; - Value *Shuf = - Builder.CreateShuffleVector(C0->getOperand(0), C1->getOperand(0), Mask); + Value *Shuf = Builder.CreateShuffleVector(C0->getOperand(0), + C1->getOperand(0), NewMask); Value *Cast = Builder.CreateCast(Opcode, Shuf, ShuffleDstTy); // Intersect flags from the old casts. diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr67803.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr67803.ll index 45e411d73316..36535264bd0f 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/pr67803.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/pr67803.ll @@ -17,7 +17,6 @@ define <4 x i64> @PR67803(<4 x i64> %x, <4 x i64> %y, <4 x i64> %a, <4 x i64> %b ; CHECK-NEXT: [[TMP9:%.*]] = bitcast <8 x i32> [[TMP3]] to <32 x i8> ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <32 x i8> [[TMP9]], <32 x i8> poison, <16 x i32> ; CHECK-NEXT: [[TMP11:%.*]] = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> [[TMP6]], <16 x i8> [[TMP8]], <16 x i8> [[TMP10]]) -; CHECK-NEXT: [[TMP12:%.*]] = bitcast <16 x i8> [[TMP11]] to <2 x i64> ; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i64> [[A]] to <32 x i8> ; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <32 x i8> [[TMP13]], <32 x i8> poison, <16 x i32> ; CHECK-NEXT: [[TMP15:%.*]] = bitcast <4 x i64> [[B]] to <32 x i8> @@ -25,8 +24,8 @@ define <4 x i64> @PR67803(<4 x i64> %x, <4 x i64> %y, <4 x i64> %a, <4 x i64> %b ; CHECK-NEXT: [[TMP17:%.*]] = bitcast <8 x i32> [[TMP3]] to <32 x i8> ; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <32 x i8> [[TMP17]], <32 x i8> poison, <16 x i32> ; CHECK-NEXT: [[TMP19:%.*]] = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> [[TMP14]], <16 x i8> [[TMP16]], <16 x i8> [[TMP18]]) -; CHECK-NEXT: [[TMP20:%.*]] = bitcast <16 x i8> [[TMP19]] to <2 x i64> -; CHECK-NEXT: [[SHUFFLE_I23:%.*]] = shufflevector <2 x i64> [[TMP12]], <2 x i64> [[TMP20]], <4 x i32> +; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <16 x i8> [[TMP11]], <16 x i8> [[TMP19]], <32 x i32> +; CHECK-NEXT: [[SHUFFLE_I23:%.*]] = bitcast <32 x i8> [[TMP20]] to <4 x i64> ; CHECK-NEXT: ret <4 x i64> [[SHUFFLE_I23]] ; entry: diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll index 97fceacd8275..4f8cfea146ea 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-casts.ll @@ -179,13 +179,12 @@ define <8 x float> @concat_bitcast_v4i32_v8f32(<4 x i32> %a0, <4 x i32> %a1) { ret <8 x float> %r } -; TODO - bitcasts (lower element count) +; bitcasts (lower element count) define <4 x double> @concat_bitcast_v8i16_v4f64(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK-LABEL: @concat_bitcast_v8i16_v4f64( -; CHECK-NEXT: [[X0:%.*]] = bitcast <8 x i16> [[A0:%.*]] to <2 x double> -; CHECK-NEXT: [[X1:%.*]] = bitcast <8 x i16> [[A1:%.*]] to <2 x double> -; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x double> [[X0]], <2 x double> [[X1]], <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]], <16 x i32> +; CHECK-NEXT: [[R:%.*]] = bitcast <16 x i16> [[TMP1]] to <4 x double> ; CHECK-NEXT: ret <4 x double> [[R]] ; %x0 = bitcast <8 x i16> %a0 to <2 x double> @@ -194,13 +193,12 @@ define <4 x double> @concat_bitcast_v8i16_v4f64(<8 x i16> %a0, <8 x i16> %a1) { ret <4 x double> %r } -; TODO - bitcasts (higher element count) +; bitcasts (higher element count) define <16 x i16> @concat_bitcast_v4i32_v16i16(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK-LABEL: @concat_bitcast_v4i32_v16i16( -; CHECK-NEXT: [[X0:%.*]] = bitcast <4 x i32> [[A0:%.*]] to <8 x i16> -; CHECK-NEXT: [[X1:%.*]] = bitcast <4 x i32> [[A1:%.*]] to <8 x i16> -; CHECK-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[X0]], <8 x i16> [[X1]], <16 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]], <8 x i32> +; CHECK-NEXT: [[R:%.*]] = bitcast <8 x i32> [[TMP1]] to <16 x i16> ; CHECK-NEXT: ret <16 x i16> [[R]] ; %x0 = bitcast <4 x i32> %a0 to <8 x i16> diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll index 3d47f373ab77..8337bb37bc54 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle.ll @@ -122,11 +122,14 @@ define <16 x i8> @bitcast_shuf_uses(<4 x i32> %v) { } ; shuffle of 2 operands removes bitcasts +; TODO - can we remove the empty bitcast(bitcast()) ? define <4 x i64> @bitcast_shuf_remove_bitcasts(<2 x i64> %a0, <2 x i64> %a1) { ; CHECK-LABEL: @bitcast_shuf_remove_bitcasts( ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], <4 x i32> -; CHECK-NEXT: ret <4 x i64> [[R]] +; CHECK-NEXT: [[SHUF:%.*]] = bitcast <4 x i64> [[R]] to <8 x i32> +; CHECK-NEXT: [[R1:%.*]] = bitcast <8 x i32> [[SHUF]] to <4 x i64> +; CHECK-NEXT: ret <4 x i64> [[R1]] ; %bc0 = bitcast <2 x i64> %a0 to <4 x i32> %bc1 = bitcast <2 x i64> %a1 to <4 x i32> -- GitLab From 77dd43570bf7a4bad688de8d8326c34590a0fa94 Mon Sep 17 00:00:00 2001 From: Johannes Reifferscheid Date: Thu, 11 Apr 2024 15:08:54 +0200 Subject: [PATCH 525/695] Fix complex power for large inputs. (#88387) For example, 1e30^1.2 currently overflows. Also forward fastmath flags. This ports XLA's logic and was verified with its test suite. Note that rsqrt and sqrt are still broken. --- .../ComplexToStandard/ComplexToStandard.cpp | 149 +++++++++++------- .../convert-to-standard.mlir | 21 ++- 2 files changed, 115 insertions(+), 55 deletions(-) diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 462036e51a1f..9c82e8105f06 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -989,65 +989,107 @@ struct ConjOpConversion : public OpConversionPattern { } }; -/// Coverts x^y = (a+bi)^(c+di) to +/// Converts lhs^y = (a+bi)^(c+di) to /// (a*a+b*b)^(0.5c) * exp(-d*atan2(b,a)) * (cos(q) + i*sin(q)), /// where q = c*atan2(b,a)+0.5d*ln(a*a+b*b) static Value powOpConversionImpl(mlir::ImplicitLocOpBuilder &builder, - ComplexType type, Value a, Value b, Value c, - Value d) { + ComplexType type, Value lhs, Value c, Value d, + arith::FastMathFlags fmf) { auto elementType = cast(type.getElementType()); - // Compute (a*a+b*b)^(0.5c). - Value aaPbb = builder.create( - builder.create(a, a), builder.create(b, b)); - Value half = builder.create( - elementType, builder.getFloatAttr(elementType, 0.5)); - Value halfC = builder.create(half, c); - Value aaPbbTohalfC = builder.create(aaPbb, halfC); - - // Compute exp(-d*atan2(b,a)). - Value negD = builder.create(d); - Value argX = builder.create(b, a); - Value negDArgX = builder.create(negD, argX); - Value eToNegDArgX = builder.create(negDArgX); - - // Compute (a*a+b*b)^(0.5c) * exp(-d*atan2(b,a)). - Value coeff = builder.create(aaPbbTohalfC, eToNegDArgX); - - // Compute c*atan2(b,a)+0.5d*ln(a*a+b*b). - Value lnAaPbb = builder.create(aaPbb); - Value halfD = builder.create(half, d); - Value q = builder.create( - builder.create(c, argX), - builder.create(halfD, lnAaPbb)); - - Value cosQ = builder.create(q); - Value sinQ = builder.create(q); + Value a = builder.create(lhs); + Value b = builder.create(lhs); + + Value abs = builder.create(lhs, fmf); + Value absToC = builder.create(abs, c, fmf); + + Value negD = builder.create(d, fmf); + Value argLhs = builder.create(b, a, fmf); + Value negDArgLhs = builder.create(negD, argLhs, fmf); + Value expNegDArgLhs = builder.create(negDArgLhs, fmf); + + Value coeff = builder.create(absToC, expNegDArgLhs, fmf); + Value lnAbs = builder.create(abs, fmf); + Value cArgLhs = builder.create(c, argLhs, fmf); + Value dLnAbs = builder.create(d, lnAbs, fmf); + Value q = builder.create(cArgLhs, dLnAbs, fmf); + Value cosQ = builder.create(q, fmf); + Value sinQ = builder.create(q, fmf); + + Value inf = builder.create( + elementType, + builder.getFloatAttr(elementType, + APFloat::getInf(elementType.getFloatSemantics()))); Value zero = builder.create( - elementType, builder.getFloatAttr(elementType, 0)); + elementType, builder.getFloatAttr(elementType, 0.0)); Value one = builder.create( - elementType, builder.getFloatAttr(elementType, 1)); - - Value xEqZero = - builder.create(arith::CmpFPredicate::OEQ, aaPbb, zero); - Value yGeZero = builder.create( - builder.create(arith::CmpFPredicate::OGE, c, zero), - builder.create(arith::CmpFPredicate::OEQ, d, zero)); - Value cEqZero = - builder.create(arith::CmpFPredicate::OEQ, c, zero); - Value complexZero = builder.create(type, zero, zero); + elementType, builder.getFloatAttr(elementType, 1.0)); Value complexOne = builder.create(type, one, zero); - Value complexOther = builder.create( - type, builder.create(coeff, cosQ), - builder.create(coeff, sinQ)); + Value complexZero = builder.create(type, zero, zero); + Value complexInf = builder.create(type, inf, zero); - // x^y is 0 if x is 0 and y > 0. 0^0 is defined to be 1.0, see + // Case 0: + // d^c is 0 if d is 0 and c > 0. 0^0 is defined to be 1.0, see + // Branch Cuts for Complex Elementary Functions or Much Ado About + // Nothing's Sign Bit, W. Kahan, Section 10. + Value absEqZero = + builder.create(arith::CmpFPredicate::OEQ, abs, zero, fmf); + Value dEqZero = + builder.create(arith::CmpFPredicate::OEQ, d, zero, fmf); + Value cEqZero = + builder.create(arith::CmpFPredicate::OEQ, c, zero, fmf); + Value bEqZero = + builder.create(arith::CmpFPredicate::OEQ, b, zero, fmf); + + Value zeroLeC = + builder.create(arith::CmpFPredicate::OLE, zero, c, fmf); + Value coeffCosQ = builder.create(coeff, cosQ, fmf); + Value coeffSinQ = builder.create(coeff, sinQ, fmf); + Value complexOneOrZero = + builder.create(cEqZero, complexOne, complexZero); + Value coeffCosSin = + builder.create(type, coeffCosQ, coeffSinQ); + Value cutoff0 = builder.create( + builder.create( + builder.create(absEqZero, dEqZero), zeroLeC), + complexOneOrZero, coeffCosSin); + + // Case 1: + // x^0 is defined to be 1 for any x, see // Branch Cuts for Complex Elementary Functions or Much Ado About // Nothing's Sign Bit, W. Kahan, Section 10. - return builder.create( - builder.create(xEqZero, yGeZero), - builder.create(cEqZero, complexOne, complexZero), - complexOther); + Value rhsEqZero = builder.create(cEqZero, dEqZero); + Value cutoff1 = + builder.create(rhsEqZero, complexOne, cutoff0); + + // Case 2: + // 1^(c + d*i) = 1 + 0*i + Value lhsEqOne = builder.create( + builder.create(arith::CmpFPredicate::OEQ, a, one), + bEqZero); + Value cutoff2 = + builder.create(lhsEqOne, complexOne, cutoff1); + + // Case 3: + // inf^(c + 0*i) = inf + 0*i, c > 0 + Value lhsEqInf = builder.create( + builder.create(arith::CmpFPredicate::OEQ, a, inf), + bEqZero); + Value rhsGt0 = builder.create( + dEqZero, + builder.create(arith::CmpFPredicate::OGT, c, zero)); + Value cutoff3 = builder.create( + builder.create(lhsEqInf, rhsGt0), complexInf, cutoff2); + + // Case 4: + // inf^(c + 0*i) = 0 + 0*i, c < 0 + Value rhsLt0 = builder.create( + dEqZero, + builder.create(arith::CmpFPredicate::OLT, c, zero)); + Value cutoff4 = builder.create( + builder.create(lhsEqInf, rhsLt0), complexZero, cutoff3); + + return cutoff4; } struct PowOpConversion : public OpConversionPattern { @@ -1060,12 +1102,11 @@ struct PowOpConversion : public OpConversionPattern { auto type = cast(adaptor.getLhs().getType()); auto elementType = cast(type.getElementType()); - Value a = builder.create(elementType, adaptor.getLhs()); - Value b = builder.create(elementType, adaptor.getLhs()); Value c = builder.create(elementType, adaptor.getRhs()); Value d = builder.create(elementType, adaptor.getRhs()); - rewriter.replaceOp(op, {powOpConversionImpl(builder, type, a, b, c, d)}); + rewriter.replaceOp(op, {powOpConversionImpl(builder, type, adaptor.getLhs(), + c, d, op.getFastmath())}); return success(); } }; @@ -1080,14 +1121,14 @@ struct RsqrtOpConversion : public OpConversionPattern { auto type = cast(adaptor.getComplex().getType()); auto elementType = cast(type.getElementType()); - Value a = builder.create(elementType, adaptor.getComplex()); - Value b = builder.create(elementType, adaptor.getComplex()); Value c = builder.create( elementType, builder.getFloatAttr(elementType, -0.5)); Value d = builder.create( elementType, builder.getFloatAttr(elementType, 0)); - rewriter.replaceOp(op, {powOpConversionImpl(builder, type, a, b, c, d)}); + rewriter.replaceOp(op, + {powOpConversionImpl(builder, type, adaptor.getComplex(), + c, d, op.getFastmath())}); return success(); } }; diff --git a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir index a1de61d10bb2..8d2fb09daa87 100644 --- a/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir +++ b/mlir/test/Conversion/ComplexToStandard/convert-to-standard.mlir @@ -753,13 +753,32 @@ func.func @complex_conj(%arg: complex) -> complex { // ----- -// CHECK-LABEL: func.func @complex_pow +// CHECK-LABEL: func.func @complex_pow +// CHECK-SAME: %[[LHS:.*]]: complex, %[[RHS:.*]]: complex func.func @complex_pow(%lhs: complex, %rhs: complex) -> complex { %pow = complex.pow %lhs, %rhs : complex return %pow : complex } +// CHECK: %[[A:.*]] = complex.re %[[LHS]] +// CHECK: %[[B:.*]] = complex.im %[[LHS]] +// CHECK: math.atan2 %[[B]], %[[A]] : f32 + +// ----- + +// CHECK-LABEL: func.func @complex_pow_with_fmf +// CHECK-SAME: %[[LHS:.*]]: complex, %[[RHS:.*]]: complex +func.func @complex_pow_with_fmf(%lhs: complex, + %rhs: complex) -> complex { + %pow = complex.pow %lhs, %rhs fastmath : complex + return %pow : complex +} + +// CHECK: %[[A:.*]] = complex.re %[[LHS]] +// CHECK: %[[B:.*]] = complex.im %[[LHS]] +// CHECK: math.atan2 %[[B]], %[[A]] fastmath : f32 + // ----- // CHECK-LABEL: func.func @complex_rsqrt -- GitLab From 599adf30afe5802fab80419ec5bb896036a1c8fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?kadir=20=C3=A7etinkaya?= Date: Thu, 11 Apr 2024 15:33:35 +0200 Subject: [PATCH 526/695] [include-cleaner] Dont apply name-match for non-owning headers (#82625) --- .../include-cleaner/lib/FindHeaders.cpp | 6 ++++++ .../unittests/FindHeadersTest.cpp | 19 +++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/clang-tools-extra/include-cleaner/lib/FindHeaders.cpp b/clang-tools-extra/include-cleaner/lib/FindHeaders.cpp index fd2de6a17ad4..7b28d1c252d7 100644 --- a/clang-tools-extra/include-cleaner/lib/FindHeaders.cpp +++ b/clang-tools-extra/include-cleaner/lib/FindHeaders.cpp @@ -275,6 +275,12 @@ llvm::SmallVector
headersForSymbol(const Symbol &S, // are already ranked in the stdlib mapping. if (H.kind() == Header::Standard) continue; + // Don't apply name match hints to exporting headers. As they usually have + // names similar to the original header, e.g. foo_wrapper/foo.h vs + // foo/foo.h, but shouldn't be preferred (unless marked as the public + // interface). + if ((H.Hint & Hints::OriginHeader) == Hints::None) + continue; if (nameMatch(SymbolName, H)) H.Hint |= Hints::PreferredHeader; } diff --git a/clang-tools-extra/include-cleaner/unittests/FindHeadersTest.cpp b/clang-tools-extra/include-cleaner/unittests/FindHeadersTest.cpp index 5a2a41b2d99b..07302142a13e 100644 --- a/clang-tools-extra/include-cleaner/unittests/FindHeadersTest.cpp +++ b/clang-tools-extra/include-cleaner/unittests/FindHeadersTest.cpp @@ -628,5 +628,24 @@ TEST_F(HeadersForSymbolTest, StandardHeaders) { tooling::stdlib::Header::named(""))); } +TEST_F(HeadersForSymbolTest, ExporterNoNameMatch) { + Inputs.Code = R"cpp( + #include "exporter/foo.h" + #include "foo_public.h" + )cpp"; + Inputs.ExtraArgs.emplace_back("-I."); + // Deliberately named as foo_public to make sure it doesn't get name-match + // boost and also gets lexicographically bigger order than "exporter/foo.h". + Inputs.ExtraFiles["foo_public.h"] = guard(R"cpp( + struct foo {}; + )cpp"); + Inputs.ExtraFiles["exporter/foo.h"] = guard(R"cpp( + #include "foo_public.h" // IWYU pragma: export + )cpp"); + buildAST(); + EXPECT_THAT(headersForFoo(), ElementsAre(physicalHeader("foo_public.h"), + physicalHeader("exporter/foo.h"))); +} + } // namespace } // namespace clang::include_cleaner -- GitLab From 61ea1bc23aa941714be3ec818c922e4ee5a279a3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 15:23:50 +0100 Subject: [PATCH 527/695] [VectorCombine][X86] Add test coverage for #67803 We are still missing a fold for shuffle(bitcast(sext(x)),bitcast(sext(y))) -> bitcast(sext(shuffle(x,y))) due to foldShuffleOfCastops failing to add new instructions back onto the worklist --- .../Transforms/VectorCombine/X86/pr67803.ll | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 llvm/test/Transforms/VectorCombine/X86/pr67803.ll diff --git a/llvm/test/Transforms/VectorCombine/X86/pr67803.ll b/llvm/test/Transforms/VectorCombine/X86/pr67803.ll new file mode 100644 index 000000000000..da94bf7f0c90 --- /dev/null +++ b/llvm/test/Transforms/VectorCombine/X86/pr67803.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=avx | FileCheck %s +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s + +define <4 x i64> @PR67803(<8 x i32> %x, <8 x i32> %y, <8 x float> %a, <8 x float> %b) { +; CHECK-LABEL: @PR67803( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[CMP_LO:%.*]] = shufflevector <8 x i1> [[CMP]], <8 x i1> poison, <4 x i32> +; CHECK-NEXT: [[CMP_HI:%.*]] = shufflevector <8 x i1> [[CMP]], <8 x i1> poison, <4 x i32> +; CHECK-NEXT: [[SEXT_LO:%.*]] = sext <4 x i1> [[CMP_LO]] to <4 x i32> +; CHECK-NEXT: [[SEXT_HI:%.*]] = sext <4 x i1> [[CMP_HI]] to <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SEXT_LO]], <4 x i32> [[SEXT_HI]], <8 x i32> +; CHECK-NEXT: [[CONCAT:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64> +; CHECK-NEXT: [[MASK:%.*]] = bitcast <4 x i64> [[CONCAT]] to <8 x float> +; CHECK-NEXT: [[SEL:%.*]] = tail call noundef <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x float> [[MASK]]) +; CHECK-NEXT: [[RES:%.*]] = bitcast <8 x float> [[SEL]] to <4 x i64> +; CHECK-NEXT: ret <4 x i64> [[RES]] +; +entry: + %cmp = icmp sgt <8 x i32> %x, %y + %cmp.lo = shufflevector <8 x i1> %cmp, <8 x i1> poison, <4 x i32> + %cmp.hi = shufflevector <8 x i1> %cmp, <8 x i1> poison, <4 x i32> + %sext.lo = sext <4 x i1> %cmp.lo to <4 x i32> + %sext.hi = sext <4 x i1> %cmp.hi to <4 x i32> + %bitcast.lo = bitcast <4 x i32> %sext.lo to <2 x i64> + %bitcast.hi = bitcast <4 x i32> %sext.hi to <2 x i64> + %concat = shufflevector <2 x i64> %bitcast.lo, <2 x i64> %bitcast.hi, <4 x i32> + %mask = bitcast <4 x i64> %concat to <8 x float> + %sel = tail call noundef <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %mask) + %res = bitcast <8 x float> %sel to <4 x i64> + ret <4 x i64> %res +} -- GitLab From ff74236f342c7bc185f56a07bab7bd0cf356c7c6 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 15:47:09 +0100 Subject: [PATCH 528/695] [VectorCombine] foldShuffleOfCastops - ensure we add all new instructions onto the worklist When creating cast(shuffle(x,y)) we were only adding the cast() to the worklist, not the new shuffle, preventing recursive combines. foldShuffleOfBinops is also failing to do this, but I still need to add test coverage for this. --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 3 +++ llvm/test/Transforms/VectorCombine/X86/pr67803.ll | 5 ++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 658e8e74fe5b..44cba60013af 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1440,6 +1440,8 @@ bool VectorCombine::foldShuffleOfBinops(Instruction &I) { NewInst->copyIRFlags(B0); NewInst->andIRFlags(B1); } + + // TODO: Add Shuf0/Shuf1 to WorkList? replaceValue(I, *NewBO); return true; } @@ -1533,6 +1535,7 @@ bool VectorCombine::foldShuffleOfCastops(Instruction &I) { NewInst->andIRFlags(C1); } + Worklist.pushValue(Shuf); replaceValue(I, *Cast); return true; } diff --git a/llvm/test/Transforms/VectorCombine/X86/pr67803.ll b/llvm/test/Transforms/VectorCombine/X86/pr67803.ll index da94bf7f0c90..69fd6f6a10e2 100644 --- a/llvm/test/Transforms/VectorCombine/X86/pr67803.ll +++ b/llvm/test/Transforms/VectorCombine/X86/pr67803.ll @@ -8,9 +8,8 @@ define <4 x i64> @PR67803(<8 x i32> %x, <8 x i32> %y, <8 x float> %a, <8 x float ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i32> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[CMP_LO:%.*]] = shufflevector <8 x i1> [[CMP]], <8 x i1> poison, <4 x i32> ; CHECK-NEXT: [[CMP_HI:%.*]] = shufflevector <8 x i1> [[CMP]], <8 x i1> poison, <4 x i32> -; CHECK-NEXT: [[SEXT_LO:%.*]] = sext <4 x i1> [[CMP_LO]] to <4 x i32> -; CHECK-NEXT: [[SEXT_HI:%.*]] = sext <4 x i1> [[CMP_HI]] to <4 x i32> -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[SEXT_LO]], <4 x i32> [[SEXT_HI]], <8 x i32> +; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x i1> [[CMP_LO]], <4 x i1> [[CMP_HI]], <8 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i1> [[TMP0]] to <8 x i32> ; CHECK-NEXT: [[CONCAT:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64> ; CHECK-NEXT: [[MASK:%.*]] = bitcast <4 x i64> [[CONCAT]] to <8 x float> ; CHECK-NEXT: [[SEL:%.*]] = tail call noundef <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x float> [[MASK]]) -- GitLab From 44718311dee486f1823876e8af9100afcc50041b Mon Sep 17 00:00:00 2001 From: Jakub Kuderski Date: Thu, 11 Apr 2024 11:07:17 -0400 Subject: [PATCH 529/695] [mlir][amdgpu] Remove shared memory optimization pass (#88225) This implementation has a number of issues and ultimately does not work on gfx9. * It does not reduce bank conflicts with wide memory accesses. * It does not correctly account for when LDS bank conflicts occur on amdgpu. * The implementation is too fragile to be used on real-world code. For example, the code bails out on any `memref.subview` in the root op, even when the subview is not a user of any of the `memref.alloc` ops. I do not see how these can be easily fixed, therefore I think it's better to delete this code. --- .../mlir/Dialect/AMDGPU/CMakeLists.txt | 1 - mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td | 17 -- .../AMDGPU/TransformOps/AMDGPUTransformOps.h | 48 ---- .../AMDGPU/TransformOps/AMDGPUTransformOps.td | 47 ---- .../AMDGPU/TransformOps/CMakeLists.txt | 4 - .../mlir/Dialect/AMDGPU/Transforms/Passes.h | 2 +- .../mlir/Dialect/AMDGPU/Transforms/Passes.td | 20 -- .../Dialect/AMDGPU/Transforms/Transforms.h | 61 ---- .../mlir/Dialect/AMDGPU/Transforms/Utils.h | 24 -- mlir/include/mlir/InitAllExtensions.h | 2 - mlir/lib/Dialect/AMDGPU/CMakeLists.txt | 1 - mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp | 15 - .../TransformOps/AMDGPUTransformOps.cpp | 67 ----- .../AMDGPU/TransformOps/CMakeLists.txt | 25 -- .../Dialect/AMDGPU/Transforms/CMakeLists.txt | 3 - .../Transforms/OptimizeSharedMemory.cpp | 261 ------------------ mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp | 39 --- .../AMDGPU/optimize_shmem_reads_writes.mlir | 50 ---- ...transform_optimize_shmem_reads_writes.mlir | 54 ---- .../llvm-project-overlay/mlir/BUILD.bazel | 54 ---- 20 files changed, 1 insertion(+), 794 deletions(-) delete mode 100644 mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h delete mode 100644 mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.td delete mode 100644 mlir/include/mlir/Dialect/AMDGPU/TransformOps/CMakeLists.txt delete mode 100644 mlir/include/mlir/Dialect/AMDGPU/Transforms/Transforms.h delete mode 100644 mlir/include/mlir/Dialect/AMDGPU/Transforms/Utils.h delete mode 100644 mlir/lib/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp delete mode 100644 mlir/lib/Dialect/AMDGPU/TransformOps/CMakeLists.txt delete mode 100644 mlir/lib/Dialect/AMDGPU/Transforms/OptimizeSharedMemory.cpp delete mode 100644 mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp delete mode 100644 mlir/test/Dialect/AMDGPU/optimize_shmem_reads_writes.mlir delete mode 100644 mlir/test/Dialect/AMDGPU/transform_optimize_shmem_reads_writes.mlir diff --git a/mlir/include/mlir/Dialect/AMDGPU/CMakeLists.txt b/mlir/include/mlir/Dialect/AMDGPU/CMakeLists.txt index 660deb21479d..9f57627c321f 100644 --- a/mlir/include/mlir/Dialect/AMDGPU/CMakeLists.txt +++ b/mlir/include/mlir/Dialect/AMDGPU/CMakeLists.txt @@ -1,3 +1,2 @@ add_subdirectory(IR) -add_subdirectory(TransformOps) add_subdirectory(Transforms) diff --git a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td index 21942b179a00..3f27e1541cf3 100644 --- a/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td +++ b/mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td @@ -29,23 +29,6 @@ def AMDGPU_Dialect : Dialect { "gpu::GPUDialect" ]; let useDefaultAttributePrinterParser = 1; - - let extraClassDeclaration = [{ - /// Return true if the given MemRefType has an integer address - /// space that matches the ROCDL shared memory address space or - /// is a gpu::AddressSpaceAttr attribute with value 'workgroup`. - static bool hasSharedMemoryAddressSpace(MemRefType type); - - /// Return true if the given Attribute has an integer address - /// space that matches the ROCDL shared memory address space or - /// is a gpu::AddressSpaceAttr attribute with value 'workgroup`. - static bool isSharedMemoryAddressSpace(Attribute type); - - /// Defines the MemRef memory space attribute numeric value that indicates - /// a memref is located in shared memory. This should correspond to the - /// value used in ROCDL. - static constexpr unsigned kSharedMemoryAddressSpace = 3; - }]; } //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h b/mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h deleted file mode 100644 index dcf934c71dd1..000000000000 --- a/mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h +++ /dev/null @@ -1,48 +0,0 @@ -//===- AMDGPUTransformOps.h - AMDGPU transform ops ---------------*- C++-*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef MLIR_DIALECT_AMDGPU_TRANSFORMOPS_AMDGPUTRANSFORMOPS_H -#define MLIR_DIALECT_AMDGPU_TRANSFORMOPS_AMDGPUTRANSFORMOPS_H - -#include "mlir/Dialect/Func/IR/FuncOps.h" -#include "mlir/Dialect/Transform/IR/TransformAttrs.h" -#include "mlir/Dialect/Transform/IR/TransformDialect.h" -#include "mlir/Dialect/Transform/Interfaces/TransformInterfaces.h" -#include "mlir/IR/OpImplementation.h" -#include "mlir/IR/RegionKindInterface.h" - -namespace mlir { -namespace transform { -class TransformHandleTypeInterface; -} // namespace transform -} // namespace mlir - -namespace mlir { -class DialectRegistry; - -namespace linalg { -class LinalgOp; -} // namespace linalg - -namespace scf { -class ForOp; -} // namespace scf - -namespace amdgpu { -void registerTransformDialectExtension(DialectRegistry ®istry); -} // namespace amdgpu -} // namespace mlir - -//===----------------------------------------------------------------------===// -// AMDGPU Transform Operations -//===----------------------------------------------------------------------===// - -#define GET_OP_CLASSES -#include "mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h.inc" - -#endif // MLIR_DIALECT_AMDGPU_TRANSFORMOPS_AMDGPUTRANSFORMOPS_H diff --git a/mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.td b/mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.td deleted file mode 100644 index 8aaa87511a2b..000000000000 --- a/mlir/include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.td +++ /dev/null @@ -1,47 +0,0 @@ -//===- AMDGPUTransformOps.td - AMDGPU transform ops --------*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef AMDGPU_TRANSFORM_OPS -#define AMDGPU_TRANSFORM_OPS - -include "mlir/Dialect/Transform/IR/TransformAttrs.td" -include "mlir/Dialect/Transform/IR/TransformDialect.td" -include "mlir/Dialect/Transform/Interfaces/TransformInterfaces.td" -include "mlir/Dialect/Transform/IR/TransformTypes.td" - -include "mlir/Interfaces/SideEffectInterfaces.td" -//===----------------------------------------------------------------------===// -// ApplyOptimizeSharedMemoryReadsAndWritesOp -//===----------------------------------------------------------------------===// - -def ApplyOptimizeSharedMemoryReadsAndWritesOp : - Op, - TransformOpInterface, TransformEachOpTrait]> { - let summary = "Reduce shared memory bank conflicts"; - let description = [{ This op attempts to optimize GPU Shared memory - reads/writes with the goal of avoiding bank conflicts. - }]; - - let arguments = (ins TransformHandleTypeInterface:$target, - DefaultValuedOptionalAttr:$sharedMemoryLineSizeBytes, - DefaultValuedOptionalAttr:$defaultVectorSizeBits); - let results = (outs); - - let assemblyFormat = "$target attr-dict `:` functional-type(operands, results)"; - - let extraClassDeclaration = [{ - ::mlir::DiagnosedSilenceableFailure applyToOne( - ::mlir::transform::TransformRewriter &rewriter, - ::mlir::func::FuncOp funcOp, - ::mlir::transform::ApplyToEachResultList &results, - ::mlir::transform::TransformState &state); - }]; -} - -#endif // AMDGPU_TRANSFORM_OPS diff --git a/mlir/include/mlir/Dialect/AMDGPU/TransformOps/CMakeLists.txt b/mlir/include/mlir/Dialect/AMDGPU/TransformOps/CMakeLists.txt deleted file mode 100644 index 07bfebc9f96d..000000000000 --- a/mlir/include/mlir/Dialect/AMDGPU/TransformOps/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -set(LLVM_TARGET_DEFINITIONS AMDGPUTransformOps.td) -mlir_tablegen(AMDGPUTransformOps.h.inc -gen-op-decls) -mlir_tablegen(AMDGPUTransformOps.cpp.inc -gen-op-defs) -add_public_tablegen_target(MLIRAMDGPUTransformOpsIncGen) diff --git a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h b/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h index ab695756d2a7..8dd5ff1a4b19 100644 --- a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h +++ b/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h @@ -20,7 +20,7 @@ namespace mlir { class ConversionTarget; namespace amdgpu { -#define GEN_PASS_DECL +#define GEN_PASS_DECL_AMDGPUEMULATEATOMICSPASS #define GEN_PASS_REGISTRATION #include "mlir/Dialect/AMDGPU/Transforms/Passes.h.inc" diff --git a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td b/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td index 67f951fd19d1..e6b27aa842df 100644 --- a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td @@ -30,24 +30,4 @@ def AmdgpuEmulateAtomicsPass : Pass<"amdgpu-emulate-atomics"> { "Chipset that these operations will run on">]; } -def OptimizeSharedMemory : Pass<"amdgpu-optimize-shared-memory"> { - let summary = "Optimizes accesses to shared memory memrefs in order to reduce bank conflicts."; - let description = [{ - This pass adds a transformation and pass to the AMDGPU dialect that - attempts to optimize reads/writes from a memref representing GPU shared - memory in order to avoid bank conflicts. - }]; - let dependentDialects = [ - "memref::MemRefDialect", "vector::VectorDialect" - ]; - let options = [ - Option<"sharedMemoryLineSizeBytes", "shared-memory-line-size-bytes", "int64_t", - /*default=*/"128", - "Shared memory line size in bytes">, - Option<"defaultVectorSizeBits", "default-vector-size-bits", "int64_t", - /*default=*/"128", - "Default vector size in bits">, - ]; -} - #endif // MLIR_DIALECT_AMDGPU_TRANSFORMS_PASSES_TD_ diff --git a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Transforms.h b/mlir/include/mlir/Dialect/AMDGPU/Transforms/Transforms.h deleted file mode 100644 index 843cea2c503b..000000000000 --- a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Transforms.h +++ /dev/null @@ -1,61 +0,0 @@ -//===- Transforms.h - AMDGPU Dialect transformations -------------*- C++-*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file declares functions that assist transformations for the amdgpu -// dialect. -// -//===----------------------------------------------------------------------===// -#ifndef MLIR_DIALECT_AMDGPU_TRANSFORMS_TRANSFORMS_H_ -#define MLIR_DIALECT_AMDGPU_TRANSFORMS_TRANSFORMS_H_ - -#include "mlir/Dialect/Func/IR/FuncOps.h" -#include "mlir/IR/Operation.h" -#include "mlir/Support/LogicalResult.h" - -namespace mlir { -class RewriterBase; - -namespace amdgpu { - -/// -/// Passes -/// - -/// Optimizes vectorized accesses to a shared memory buffer specified by -/// memrefValue. This transformation assumes the following: -/// 1) All relevant accesses to `memrefValue` are contained with `parentOp`. -/// 2) The function will fail precondition checks if any subviews are -/// taken of `memrefValue`. All reads/writes to `memrefValue` should occur -/// through `memrefValue` directly. -/// -/// Shared memory bank conflicts occur when multiple threads attempt to read or -/// write locations assigned to the same shared memory bank. For `2^N` byte -/// vectorized accesses, we need to be concerned with conflicts among threads -/// identified as `(tid) -> tid.floordiv(2^{7-N})`. As such, this transformation -/// changes any indexed memory access (vector.load, memref.load, etc) -/// such that the final dimension's index value is permuted such that -/// `newColIndex = oldColIndex % vectorSize + -/// perm[rowIndex](oldColIndex/vectorSize, rowIndex)` where `rowIndex` is the -/// index for the second-to last dimension and `perm[rowIndex]` is a permutation -/// function that depends on the row Index. The permutation function is chosen -/// to ensure that sequential distributed+vectorized reads/writes down a single -/// dimension of the memref have minimal conflicts. -LogicalResult -optimizeSharedMemoryReadsAndWrites(Operation *parentOp, Value memrefValue, - int64_t sharedMemoryLineSizeBytes, - int64_t defaultVectorSizeBits); - -std::optional -optimizeSharedMemoryReadsAndWritesOp(func::FuncOp funcOp, - int64_t sharedMemoryLineSizeBytes, - int64_t defaultVectorSizeBits); - -} // namespace amdgpu -} // namespace mlir - -#endif // MLIR_DIALECT_AMDGPU_TRANSFORMS_TRANSFORMS_H_ diff --git a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Utils.h b/mlir/include/mlir/Dialect/AMDGPU/Transforms/Utils.h deleted file mode 100644 index 9e5e9589d62f..000000000000 --- a/mlir/include/mlir/Dialect/AMDGPU/Transforms/Utils.h +++ /dev/null @@ -1,24 +0,0 @@ -//===- Utils.h - Transform utilities -----------------------------*- C++-*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/IR/Operation.h" - -namespace mlir { -namespace amdgpu { - -/// Get and set the indices that the given load/store operation is operating on. -/// Preconditions: -/// - The Op must have memory affects. -/// - Considers memref::LoadOp, vector::LoadOp, and vector::TransferReadOp. -/// - Considers memref::StoreOp, vector::StoreOp, and vector::TransferWriteOp. -/// - Excludes subview op. -std::optional getIndices(Operation *op); -void setIndices(Operation *op, ArrayRef indices); - -} // namespace amdgpu -} // namespace mlir diff --git a/mlir/include/mlir/InitAllExtensions.h b/mlir/include/mlir/InitAllExtensions.h index b31fb26f00f8..7708ca5571de 100644 --- a/mlir/include/mlir/InitAllExtensions.h +++ b/mlir/include/mlir/InitAllExtensions.h @@ -23,7 +23,6 @@ #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" #include "mlir/Conversion/NVVMToLLVM/NVVMToLLVM.h" #include "mlir/Conversion/UBToLLVM/UBToLLVM.h" -#include "mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h" #include "mlir/Dialect/Affine/TransformOps/AffineTransformOps.h" #include "mlir/Dialect/Bufferization/TransformOps/BufferizationTransformOps.h" #include "mlir/Dialect/Func/Extensions/AllExtensions.h" @@ -67,7 +66,6 @@ inline void registerAllExtensions(DialectRegistry ®istry) { ub::registerConvertUBToLLVMInterface(registry); // Register all transform dialect extensions. - amdgpu::registerTransformDialectExtension(registry); affine::registerTransformDialectExtension(registry); bufferization::registerTransformDialectExtension(registry); func::registerTransformDialectExtension(registry); diff --git a/mlir/lib/Dialect/AMDGPU/CMakeLists.txt b/mlir/lib/Dialect/AMDGPU/CMakeLists.txt index c47e4c5495c1..31167e6af908 100644 --- a/mlir/lib/Dialect/AMDGPU/CMakeLists.txt +++ b/mlir/lib/Dialect/AMDGPU/CMakeLists.txt @@ -1,4 +1,3 @@ add_subdirectory(IR) -add_subdirectory(TransformOps) add_subdirectory(Transforms) add_subdirectory(Utils) diff --git a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp index 4e72fbf56b80..2575ad498481 100644 --- a/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp +++ b/mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp @@ -43,21 +43,6 @@ void AMDGPUDialect::initialize() { >(); } -bool amdgpu::AMDGPUDialect::isSharedMemoryAddressSpace(Attribute memorySpace) { - if (!memorySpace) - return false; - if (auto intAttr = llvm::dyn_cast(memorySpace)) - return intAttr.getInt() == AMDGPUDialect::kSharedMemoryAddressSpace; - if (auto gpuAttr = llvm::dyn_cast(memorySpace)) - return gpuAttr.getValue() == gpu::AddressSpace::Workgroup; - return false; -} - -bool amdgpu::AMDGPUDialect::hasSharedMemoryAddressSpace(MemRefType type) { - Attribute memorySpace = type.getMemorySpace(); - return isSharedMemoryAddressSpace(memorySpace); -} - //===----------------------------------------------------------------------===// // 8-bit float ops //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp b/mlir/lib/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp deleted file mode 100644 index b7e17a928973..000000000000 --- a/mlir/lib/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp +++ /dev/null @@ -1,67 +0,0 @@ -//===- AMDGPUTransformOps.cpp - Implementation of AMDGPU transform ops-----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h" - -#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h" -#include "mlir/Dialect/AMDGPU/Transforms/Transforms.h" -#include "mlir/Dialect/Affine/IR/AffineOps.h" -#include "mlir/Dialect/Vector/IR/VectorOps.h" - -using namespace mlir; -using namespace mlir::amdgpu; -using namespace mlir::transform; -using namespace mlir::func; - -#define DEBUG_TYPE "amdgpu-transforms" -#define DBGS() (llvm::dbgs() << "[" DEBUG_TYPE "]: ") -#define DBGSNL() (llvm::dbgs() << "\n") -#define LDBG(X) LLVM_DEBUG(DBGS() << (X) << "\n") - -DiagnosedSilenceableFailure -ApplyOptimizeSharedMemoryReadsAndWritesOp::applyToOne( - TransformRewriter &rewriter, FuncOp funcOp, ApplyToEachResultList &results, - TransformState &state) { - optimizeSharedMemoryReadsAndWritesOp(funcOp, getSharedMemoryLineSizeBytes(), - getDefaultVectorSizeBits()); - return DiagnosedSilenceableFailure::success(); -} - -void ApplyOptimizeSharedMemoryReadsAndWritesOp::getEffects( - SmallVectorImpl &effects) { - onlyReadsHandle(getTarget(), effects); - modifiesPayload(effects); -} - -//===----------------------------------------------------------------------===// -// Transform op registration -//===----------------------------------------------------------------------===// - -namespace { -class AMDGPUTransformDialectExtension - : public TransformDialectExtension { -public: - AMDGPUTransformDialectExtension() { - declareGeneratedDialect(); - declareGeneratedDialect(); - declareGeneratedDialect(); - declareGeneratedDialect(); - registerTransformOps< -#define GET_OP_LIST -#include "mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp.inc" - >(); - } -}; -} // namespace - -#define GET_OP_CLASSES -#include "mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp.inc" - -void amdgpu::registerTransformDialectExtension(DialectRegistry ®istry) { - registry.addExtensions(); -} diff --git a/mlir/lib/Dialect/AMDGPU/TransformOps/CMakeLists.txt b/mlir/lib/Dialect/AMDGPU/TransformOps/CMakeLists.txt deleted file mode 100644 index c39a3b55eabc..000000000000 --- a/mlir/lib/Dialect/AMDGPU/TransformOps/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -add_mlir_dialect_library(MLIRAMDGPUTransformOps - AMDGPUTransformOps.cpp - - ADDITIONAL_HEADER_DIRS - ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/AMDGPU/TransformOps - - DEPENDS - MLIRAMDGPUTransformOpsIncGen - - LINK_LIBS PUBLIC - MLIRAffineDialect - MLIRArithDialect - MLIRIR - MLIRLinalgDialect - MLIRAMDGPUDialect - MLIRAMDGPUTransforms - MLIRParser - MLIRSideEffectInterfaces - MLIRSCFDialect - MLIRSCFTransforms - MLIRTransformDialect - MLIRTransformDialectUtils - MLIRVectorTransforms - - ) diff --git a/mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt b/mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt index a955d585b9a1..0889a21bddc4 100644 --- a/mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt @@ -1,7 +1,5 @@ add_mlir_dialect_library(MLIRAMDGPUTransforms EmulateAtomics.cpp - OptimizeSharedMemory.cpp - Utils.cpp ADDITIONAL_HEADER_DIRS {$MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/AMDGPU/Transforms @@ -19,5 +17,4 @@ add_mlir_dialect_library(MLIRAMDGPUTransforms MLIRPass MLIRTransforms MLIRTransformUtils - MLIRVectorDialect ) diff --git a/mlir/lib/Dialect/AMDGPU/Transforms/OptimizeSharedMemory.cpp b/mlir/lib/Dialect/AMDGPU/Transforms/OptimizeSharedMemory.cpp deleted file mode 100644 index 32fab265e03c..000000000000 --- a/mlir/lib/Dialect/AMDGPU/Transforms/OptimizeSharedMemory.cpp +++ /dev/null @@ -1,261 +0,0 @@ -//===- OptimizeSharedMemory.cpp - MLIR AMDGPU pass implementation ---------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file implements transforms to optimize accesses to shared memory. -// It is inspired by -// https://github.com/llvm/llvm-project/blob/main/mlir/lib/Dialect/NVGPU/Transforms/OptimizeSharedMemory.cpp -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/AMDGPU/Transforms/Passes.h" - -#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h" -#include "mlir/Dialect/AMDGPU/Transforms/Transforms.h" -#include "mlir/Dialect/AMDGPU/Transforms/Utils.h" -#include "mlir/Dialect/Arith/IR/Arith.h" -#include "mlir/Dialect/Func/IR/FuncOps.h" -#include "mlir/Dialect/GPU/IR/GPUDialect.h" -#include "mlir/Dialect/MemRef/IR/MemRef.h" -#include "mlir/Dialect/Vector/IR/VectorOps.h" -#include "mlir/Interfaces/SideEffectInterfaces.h" -#include "mlir/Support/LogicalResult.h" - -namespace mlir { -namespace amdgpu { -#define GEN_PASS_DEF_OPTIMIZESHAREDMEMORY -#include "mlir/Dialect/AMDGPU/Transforms/Passes.h.inc" -} // namespace amdgpu -} // namespace mlir - -using namespace mlir; -using namespace mlir::amdgpu; - -/// Uses `srcIndexValue` to permute `tgtIndexValue` via -/// `result = xor(floordiv(srcIdxVal,permuteEveryN), -/// floordiv(tgtIdxVal,vectorSize))) -/// + tgtIdxVal % vectorSize` -/// This is done using an optimized sequence of `arith` operations. -static Value permuteVectorOffset(OpBuilder &b, Location loc, - ArrayRef indices, MemRefType memrefTy, - int64_t srcDim, int64_t tgtDim, - int64_t sharedMemoryLineSizeBytes, - int64_t defaultVectorSizeBits) { - // Adjust the src index to change how often the permutation changes - // if necessary. - Value src = indices[srcDim]; - - // We only want to permute every N iterations of the target dim where N is - // ceil(sharedMemoryLineSizeBytes / dimSizeBytes(tgtDim)). - const int64_t permuteEveryN = std::max( - 1, sharedMemoryLineSizeBytes / ((memrefTy.getDimSize(tgtDim) * - memrefTy.getElementTypeBitWidth()) / - 8)); - - // clang-format off - // Index bit representation (b0 = least significant bit) for dim(1) - // of a `memref` is as follows: - // N := log2(128/elementSizeBits) - // M := log2(dimSize(1)) - // then - // bits[0:N] = sub-vector element offset - // bits[N:M] = vector index - // clang-format on - int64_t n = - llvm::Log2_64(defaultVectorSizeBits / memrefTy.getElementTypeBitWidth()); - int64_t m = llvm::Log2_64(memrefTy.getDimSize(tgtDim)); - - // Capture bits[0:(M-N)] of src by first creating a (M-N) mask. - int64_t mask = (1LL << (m - n)) - 1; - if (permuteEveryN > 1) - mask = mask << llvm::Log2_64(permuteEveryN); - Value srcBits = b.create(loc, mask); - srcBits = b.create(loc, src, srcBits); - - /// Use the src bits to permute the target bits b[N:M] containing the - /// vector offset. - if (permuteEveryN > 1) { - int64_t shlBits = n - llvm::Log2_64(permuteEveryN); - if (shlBits > 0) { - Value finalShiftVal = b.create(loc, shlBits); - srcBits = b.createOrFold(loc, srcBits, finalShiftVal); - } else if (shlBits < 0) { - Value finalShiftVal = b.create(loc, -1 * shlBits); - srcBits = b.createOrFold(loc, srcBits, finalShiftVal); - } - } else { - Value finalShiftVal = b.create(loc, n); - srcBits = b.createOrFold(loc, srcBits, finalShiftVal); - } - - Value permutedVectorIdx = - b.create(loc, indices[tgtDim], srcBits); - return permutedVectorIdx; -} - -static void transformIndices(OpBuilder &builder, Location loc, - SmallVector &indices, - MemRefType memrefTy, int64_t srcDim, - int64_t tgtDim, int64_t sharedMemoryLineSizeBytes, - int64_t defaultVectorSizeBits) { - indices[tgtDim] = - permuteVectorOffset(builder, loc, indices, memrefTy, srcDim, tgtDim, - sharedMemoryLineSizeBytes, defaultVectorSizeBits); -} - -// Return all operations within `parentOp` that read from or write to -// `shmMemRef`. -static LogicalResult -getShmReadAndWriteOps(Operation *parentOp, Value shmMemRef, - SmallVector &readOps, - SmallVector &writeOps) { - parentOp->walk([&](Operation *op) { - MemoryEffectOpInterface iface = dyn_cast(op); - if (!iface) - return; - std::optional effect = - iface.getEffectOnValue(shmMemRef); - if (effect) { - readOps.push_back(op); - return; - } - effect = iface.getEffectOnValue(shmMemRef); - if (effect) - writeOps.push_back(op); - }); - - // Restrict to a supported set of ops. We also require at least 2D access, - // although this could be relaxed. - if (llvm::any_of(readOps, [](Operation *op) { - return !isa( - op) || - amdgpu::getIndices(op)->size() < 2; - })) - return failure(); - if (llvm::any_of(writeOps, [](Operation *op) { - return !isa( - op) || - amdgpu::getIndices(op)->size() < 2; - })) - return failure(); - - return success(); -} - -LogicalResult amdgpu::optimizeSharedMemoryReadsAndWrites( - Operation *parentOp, Value memrefValue, int64_t sharedMemoryLineSizeBytes, - int64_t defaultVectorSizeBits) { - auto memRefType = dyn_cast(memrefValue.getType()); - if (!memRefType || - !amdgpu::AMDGPUDialect::hasSharedMemoryAddressSpace(memRefType)) - return failure(); - - // Abort if the given value has any sub-views; we do not do any alias - // analysis. - bool hasSubView = false; - parentOp->walk([&](memref::SubViewOp subView) { hasSubView = true; }); - if (hasSubView) - return failure(); - - // Check if this is necessary given the assumption of 128b accesses: - // If dim[rank-1] is small enough to fit 8 rows in a 128B line. - const int64_t rowSize = memRefType.getDimSize(memRefType.getRank() - 1); - const int64_t rowsPerLine = - (8 * sharedMemoryLineSizeBytes / memRefType.getElementTypeBitWidth()) / - rowSize; - const int64_t threadGroupSize = - 1LL << (7 - llvm::Log2_64(defaultVectorSizeBits / 8)); - if (rowsPerLine >= threadGroupSize) - return failure(); - - // Get sets of operations within the function that read/write to shared - // memory. - SmallVector shmReadOps; - SmallVector shmWriteOps; - if (failed(getShmReadAndWriteOps(parentOp, memrefValue, shmReadOps, - shmWriteOps))) - return failure(); - - if (shmReadOps.empty() || shmWriteOps.empty()) - return failure(); - - OpBuilder builder(parentOp->getContext()); - - int64_t tgtDim = memRefType.getRank() - 1; - int64_t srcDim = memRefType.getRank() - 2; - - // Transform indices for the ops writing to shared memory. - while (!shmWriteOps.empty()) { - Operation *shmWriteOp = shmWriteOps.pop_back_val(); - builder.setInsertionPoint(shmWriteOp); - - auto indices = amdgpu::getIndices(shmWriteOp); - SmallVector transformedIndices(indices->begin(), indices->end()); - transformIndices(builder, shmWriteOp->getLoc(), transformedIndices, - memRefType, srcDim, tgtDim, sharedMemoryLineSizeBytes, - defaultVectorSizeBits); - amdgpu::setIndices(shmWriteOp, transformedIndices); - } - - // Transform indices for the ops reading from shared memory. - while (!shmReadOps.empty()) { - Operation *shmReadOp = shmReadOps.pop_back_val(); - builder.setInsertionPoint(shmReadOp); - - auto indices = amdgpu::getIndices(shmReadOp); - SmallVector transformedIndices(indices->begin(), indices->end()); - transformIndices(builder, shmReadOp->getLoc(), transformedIndices, - memRefType, srcDim, tgtDim, sharedMemoryLineSizeBytes, - defaultVectorSizeBits); - amdgpu::setIndices(shmReadOp, transformedIndices); - } - - return success(); -} - -std::optional -amdgpu::optimizeSharedMemoryReadsAndWritesOp(func::FuncOp funcOp, - int64_t sharedMemoryLineSizeBytes, - int64_t defaultVectorSizeBits) { - SmallVector shmAllocOps; - funcOp.walk([&](memref::AllocOp allocOp) { - if (!amdgpu::AMDGPUDialect::hasSharedMemoryAddressSpace(allocOp.getType())) - return; - shmAllocOps.push_back(allocOp); - }); - for (auto allocOp : shmAllocOps) { - if (failed(amdgpu::optimizeSharedMemoryReadsAndWrites( - funcOp, allocOp.getMemref(), sharedMemoryLineSizeBytes, - defaultVectorSizeBits))) - return failure(); - } - return success(); -} - -struct OptimizeSharedMemoryPass - : public amdgpu::impl::OptimizeSharedMemoryBase { -public: - OptimizeSharedMemoryPass() = default; - OptimizeSharedMemoryPass(const OptimizeSharedMemoryOptions &options) - : OptimizeSharedMemoryBase(options) {} - void runOnOperation() override { - Operation *op = getOperation(); - SmallVector shmAllocOps; - op->walk([&](memref::AllocOp allocOp) { - if (!amdgpu::AMDGPUDialect::hasSharedMemoryAddressSpace( - allocOp.getType())) - return; - shmAllocOps.push_back(allocOp); - }); - for (auto allocOp : shmAllocOps) { - if (failed(optimizeSharedMemoryReadsAndWrites(op, allocOp.getMemref(), - sharedMemoryLineSizeBytes, - defaultVectorSizeBits))) - return; - } - } -}; diff --git a/mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp b/mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp deleted file mode 100644 index 8163eeafdf1f..000000000000 --- a/mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp +++ /dev/null @@ -1,39 +0,0 @@ -#include "mlir/Dialect/AMDGPU/Transforms/Utils.h" - -#include "mlir/Dialect/AMDGPU/IR/AMDGPUDialect.h" -#include "mlir/Dialect/MemRef/IR/MemRef.h" -#include "mlir/Dialect/Vector/IR/VectorOps.h" - -using namespace mlir; -using namespace mlir::amdgpu; - -std::optional amdgpu::getIndices(Operation *op) { - if (auto loadOp = dyn_cast(op)) - return loadOp.getIndices(); - if (auto storeOp = dyn_cast(op)) - return storeOp.getIndices(); - if (auto vectorReadOp = dyn_cast(op)) - return vectorReadOp.getIndices(); - if (auto vectorStoreOp = dyn_cast(op)) - return vectorStoreOp.getIndices(); - if (auto transferReadOp = dyn_cast(op)) - return transferReadOp.getIndices(); - if (auto transferWriteOp = dyn_cast(op)) - return transferWriteOp.getIndices(); - return std::nullopt; -} - -void amdgpu::setIndices(Operation *op, ArrayRef indices) { - if (auto loadOp = dyn_cast(op)) - return loadOp.getIndicesMutable().assign(indices); - if (auto storeOp = dyn_cast(op)) - return storeOp.getIndicesMutable().assign(indices); - if (auto vectorReadOp = dyn_cast(op)) - return vectorReadOp.getIndicesMutable().assign(indices); - if (auto vectorStoreOp = dyn_cast(op)) - return vectorStoreOp.getIndicesMutable().assign(indices); - if (auto transferReadOp = dyn_cast(op)) - return transferReadOp.getIndicesMutable().assign(indices); - if (auto transferWriteOp = dyn_cast(op)) - return transferWriteOp.getIndicesMutable().assign(indices); -} diff --git a/mlir/test/Dialect/AMDGPU/optimize_shmem_reads_writes.mlir b/mlir/test/Dialect/AMDGPU/optimize_shmem_reads_writes.mlir deleted file mode 100644 index 983eee732e2a..000000000000 --- a/mlir/test/Dialect/AMDGPU/optimize_shmem_reads_writes.mlir +++ /dev/null @@ -1,50 +0,0 @@ -// RUN: mlir-opt %s --pass-pipeline='builtin.module(func.func(amdgpu-optimize-shared-memory))' | FileCheck %s - - // CHECK: @optimize_shmem([[arg0:%.+]]: memref<{{.*}}>, [[readRow:%.+]]: index, [[readCol:%.+]]: index, [[writeRow:%.+]]: index, [[writeCol:%.+]]: index, [[fragRow:%.+]]: index, [[fragCol:%.+]]: index, [[fragColPerm:%.+]]: index, [[stRow:%.+]]: index, [[stCol:%.+]]: index) - func.func @optimize_shmem(%arg0: memref<4096x4096xf16>, - %readRow: index, %readCol: index, - %writeRow: index, %writeCol: index, - %fragRow: index, %fragCol: index, - %fragColPerm: index, - %stRow: index, %stCol: index) { - // CHECK: %[[cst:.+]] = arith.constant 0.000000e+00 : f16 - %cst = arith.constant 0.000000e+00 : f16 - - // CHECK: [[shmA:%.+]] = memref.alloc - // CHECK: [[shmB:%.+]] = memref.alloc - %shmA = memref.alloc() {alignment = 64 : i64} : memref<128x32xf16, 3> - %shmB = memref.alloc() {alignment = 64 : i64} : memref<256x32xf16, 3> - - %0 = vector.transfer_read %arg0[%readRow, %readCol], %cst {in_bounds = [true, true]} : memref<4096x4096xf16>, vector<1x8xf16> - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[stRow:%.+]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol:%.+]], [[xorBits]] - vector.transfer_write %0, %shmB[%writeRow, %writeCol] {in_bounds = [true, true]} : vector<1x8xf16>, memref<256x32xf16, 3> - gpu.barrier - gpu.barrier - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol:%.+]], [[xorBits]] - %1 = vector.load %shmB[%fragRow, %fragColPerm] : memref<256x32xf16, 3>, vector<8xf16> - - %2 = vector.transfer_read %arg0[%readRow, %readCol], %cst {in_bounds = [true, true]} : memref<4096x4096xf16>, vector<1x8xf16> - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[stRow:%.+]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol:%.+]], [[xorBits]] - vector.transfer_write %2, %shmA[%writeRow, %writeCol] {in_bounds = [true, true]} : vector<1x8xf16>, memref<128x32xf16, 3> - gpu.barrier - gpu.barrier - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol:%.+]], [[xorBits]] - %3 = vector.load %shmA[%fragRow, %fragColPerm] : memref<128x32xf16, 3>, vector<8xf16> - return - } diff --git a/mlir/test/Dialect/AMDGPU/transform_optimize_shmem_reads_writes.mlir b/mlir/test/Dialect/AMDGPU/transform_optimize_shmem_reads_writes.mlir deleted file mode 100644 index b1bb91ffc297..000000000000 --- a/mlir/test/Dialect/AMDGPU/transform_optimize_shmem_reads_writes.mlir +++ /dev/null @@ -1,54 +0,0 @@ -// RUN: mlir-opt %s -transform-interpreter | FileCheck %s - - // CHECK: @optimize_shmem([[arg0:%.+]]: memref<{{.*}}>, [[readRow:%.+]]: index, [[readCol:%.+]]: index, [[writeRow:%.+]]: index, [[writeCol:%.+]]: index, [[fragRow:%.+]]: index, [[fragCol:%.+]]: index, [[fragColPerm:%.+]]: index, [[stRow:%.+]]: index, [[stCol:%.+]]: index) - func.func @optimize_shmem(%arg0: memref<4096x4096xf16>, - %readRow: index, %readCol: index, - %writeRow: index, %writeCol: index, - %fragRow: index, %fragCol: index, - %fragColPerm: index, - %stRow: index, %stCol: index) { - %cst = arith.constant 0.000000e+00 : f16 - - %shmA = memref.alloc() {alignment = 64 : i64} : memref<128x32xf16, 3> - %shmB = memref.alloc() {alignment = 64 : i64} : memref<256x32xf16, 3> - - %0 = vector.transfer_read %arg0[%readRow, %readCol], %cst {in_bounds = [true, true]} : memref<4096x4096xf16>, vector<1x8xf16> - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[stRow:%.+]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol:%.+]], [[xorBits]] - vector.transfer_write %0, %shmB[%writeRow, %writeCol] {in_bounds = [true, true]} : vector<1x8xf16>, memref<256x32xf16, 3> - gpu.barrier - gpu.barrier - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol:%.+]], [[xorBits]] - %1 = vector.load %shmB[%fragRow, %fragColPerm] : memref<256x32xf16, 3>, vector<8xf16> - %2 = vector.transfer_read %arg0[%readRow, %readCol], %cst {in_bounds = [true, true]} : memref<4096x4096xf16>, vector<1x8xf16> - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[stRow:%.+]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[stColPerm:%.+]] = arith.xori [[stCol:%.+]], [[xorBits]] - vector.transfer_write %2, %shmA[%writeRow, %writeCol] {in_bounds = [true, true]} : vector<1x8xf16>, memref<128x32xf16, 3> - gpu.barrier - gpu.barrier - // CHECK: [[c6:%.+]] = arith.constant 6 : index - // CHECK: [[srcBits:%.+]] = arith.andi [[fragRow]], [[c6]] - // CHECK: [[c2:%.+]] = arith.constant 2 : index - // CHECK: [[xorBits:%.+]] = arith.shli [[srcBits]], [[c2]] - // CHECK: [[fragColPerm:%.+]] = arith.xori [[fragCol:%.+]], [[xorBits]] - %3 = vector.load %shmA[%fragRow, %fragColPerm] : memref<128x32xf16, 3>, vector<8xf16> - return - } - -module attributes { transform.with_named_sequence } { - transform.named_sequence @__transform_main(%root: !transform.any_op {transform.readonly}) { - %0 = transform.structured.match ops{["func.func"]} in %root : (!transform.any_op) -> !transform.any_op - transform.amdgpu.optimize_shared_memory_reads_and_writes %0 {sharedMemoryLineSizeBytes = 128, defaultVectorSizeBits = 128}: (!transform.any_op) -> () - transform.yield - } // @__transform_main -} // module diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 497edcfceffe..67052fcd3993 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -1552,58 +1552,6 @@ cc_library( ], ) -cc_library( - name = "AMDGPUTransformOps", - srcs = glob([ - "lib/Dialect/AMDGPU/TransformOps/*.cpp", - ]), - hdrs = glob([ - "include/mlir/Dialect/AMDGPU/TransformOps/*.h", - ]), - includes = ["include"], - deps = [ - ":AMDGPUDialect", - ":AMDGPUTransformOpsIncGen", - ":AMDGPUTransforms", - ":AffineDialect", - ":FuncDialect", - ":IR", - ":TransformDialect", - ":TransformDialectInterfaces", - ":VectorDialect", - ], -) - -td_library( - name = "AMDGPUTransformOpsTdFiles", - srcs = glob([ - "include/mlir/Dialect/AMDGPU/TransformOps/*.td", - ]), - includes = ["include"], - deps = [ - ":TransformDialectTdFiles", - ], -) - -gentbl_cc_library( - name = "AMDGPUTransformOpsIncGen", - tbl_outs = [ - ( - ["-gen-op-decls"], - "include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.h.inc", - ), - ( - ["-gen-op-defs"], - "include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.cpp.inc", - ), - ], - tblgen = ":mlir-tblgen", - td_file = "include/mlir/Dialect/AMDGPU/TransformOps/AMDGPUTransformOps.td", - deps = [ - ":AMDGPUTransformOpsTdFiles", - ], -) - gentbl_cc_library( name = "AMDGPUPassIncGen", tbl_outs = [ @@ -4787,7 +4735,6 @@ cc_library( name = "AllExtensions", hdrs = ["include/mlir/InitAllExtensions.h"], deps = [ - ":AMDGPUTransformOps", ":AffineTransformOps", ":ArithToLLVM", ":BufferizationTransformOps", @@ -9033,7 +8980,6 @@ cc_library( deps = [ ":AMDGPUDialect", ":AMDGPUToROCDL", - ":AMDGPUTransformOps", ":AMDGPUTransforms", ":AMXDialect", ":AMXTransforms", -- GitLab From 198ffb85314f7741ed048de67d68ca83bb30e16e Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Thu, 11 Apr 2024 11:23:24 -0400 Subject: [PATCH 530/695] [Clang][Sema] Implement approved resolution for CWG2858 (#88042) The approved resolution for CWG2858 changes [expr.prim.id.qual] p2 sentence 2 to read: > A declarative _nested-name-specifier_ shall not have a _computed-type-specifier_. This patch implements the approved resolution. Since we don't consider _nested-name-specifiers_ in friend declarations to be declarative (yet), it currently isn't possible to write a test that would produce this diagnostic (`diagnoseQualifiedDeclaration` is never called if the `DeclContext` can't be computed). Nevertheless, tests were added which will produce the diagnostic once we start calling `diagnoseQualifiedDeclaration` for friend declarations. --- clang/docs/ReleaseNotes.rst | 3 +++ .../clang/Basic/DiagnosticSemaKinds.td | 7 +++--- clang/lib/Sema/SemaDecl.cpp | 13 +++++------ clang/test/CXX/dcl.decl/dcl.meaning/p1-0x.cpp | 4 ++-- clang/test/CXX/drs/dr28xx.cpp | 23 +++++++++++++++++++ clang/test/Parser/cxx-class.cpp | 6 ++--- 6 files changed, 40 insertions(+), 16 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index c4a4893aec5c..93318871fa9f 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -147,6 +147,9 @@ Resolutions to C++ Defect Reports compatibility of two types. (`CWG2759: [[no_unique_address] and common initial sequence `_). +- Clang now diagnoses declarative nested-name-specifiers with pack-index-specifiers. + (`CWG2858: Declarative nested-name-specifiers and pack-index-specifiers `_). + C Language Changes ------------------ diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 059a8f58da5d..180e913155d6 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -2402,10 +2402,6 @@ def err_selected_explicit_constructor : Error< def note_explicit_ctor_deduction_guide_here : Note< "explicit %select{constructor|deduction guide}0 declared here">; -// C++11 decltype -def err_decltype_in_declarator : Error< - "'decltype' cannot be used to name a declaration">; - // C++11 auto def warn_cxx98_compat_auto_type_specifier : Warning< "'auto' type specifier is incompatible with C++98">, @@ -8313,6 +8309,9 @@ def ext_template_after_declarative_nns : ExtWarn< def ext_alias_template_in_declarative_nns : ExtWarn< "a declarative nested name specifier cannot name an alias template">, InGroup>; +def err_computed_type_in_declarative_nns : Error< + "a %select{pack indexing|'decltype'}0 specifier cannot be used in " + "a declarative nested name specifier">; def err_no_typeid_with_fno_rtti : Error< "use of typeid requires -frtti">; diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 5a23179dfbbf..a4699d6ba2c7 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -6335,16 +6335,15 @@ bool Sema::diagnoseQualifiedDeclaration(CXXScopeSpec &SS, DeclContext *DC, if (TST->isDependentType() && TST->isTypeAlias()) Diag(Loc, diag::ext_alias_template_in_declarative_nns) << SpecLoc.getLocalSourceRange(); - } else if (T->isDecltypeType()) { + } else if (T->isDecltypeType() || T->getAsAdjusted()) { // C++23 [expr.prim.id.qual]p2: // [...] A declarative nested-name-specifier shall not have a - // decltype-specifier. + // computed-type-specifier. // - // FIXME: This wording appears to be defective as it does not forbid - // declarative nested-name-specifiers with pack-index-specifiers. - // See https://github.com/cplusplus/CWG/issues/499. - Diag(Loc, diag::err_decltype_in_declarator) - << SpecLoc.getTypeLoc().getSourceRange(); + // CWG2858 changed this from 'decltype-specifier' to + // 'computed-type-specifier'. + Diag(Loc, diag::err_computed_type_in_declarative_nns) + << T->isDecltypeType() << SpecLoc.getTypeLoc().getSourceRange(); } } } while ((SpecLoc = SpecLoc.getPrefix())); diff --git a/clang/test/CXX/dcl.decl/dcl.meaning/p1-0x.cpp b/clang/test/CXX/dcl.decl/dcl.meaning/p1-0x.cpp index fbe9c0895aea..13be079a40bc 100644 --- a/clang/test/CXX/dcl.decl/dcl.meaning/p1-0x.cpp +++ b/clang/test/CXX/dcl.decl/dcl.meaning/p1-0x.cpp @@ -6,8 +6,8 @@ class foo { void func(); }; -int decltype(foo())::i; // expected-error{{'decltype' cannot be used to name a declaration}} -void decltype(foo())::func() { // expected-error{{'decltype' cannot be used to name a declaration}} +int decltype(foo())::i; // expected-error{{a 'decltype' specifier cannot be used in a declarative nested name specifier}} +void decltype(foo())::func() { // expected-error{{a 'decltype' specifier cannot be used in a declarative nested name specifier}} } diff --git a/clang/test/CXX/drs/dr28xx.cpp b/clang/test/CXX/drs/dr28xx.cpp index 7f72003d66f1..9b21d3410a04 100644 --- a/clang/test/CXX/drs/dr28xx.cpp +++ b/clang/test/CXX/drs/dr28xx.cpp @@ -58,3 +58,26 @@ void B::g() requires true; #endif } // namespace dr2847 + +namespace dr2858 { // dr2858: 19 + +#if __cplusplus > 202302L + +template +struct A { + // FIXME: The nested-name-specifier in the following friend declarations are declarative, + // but we don't treat them as such (yet). + friend void Ts...[0]::f(); + template + friend void Ts...[0]::g(); + + friend struct Ts...[0]::B; + // FIXME: The index of the pack-index-specifier is printed as a memory address in the diagnostic. + template + friend struct Ts...[0]::C; + // expected-warning-re@-1 {{dependent nested name specifier 'Ts...[{{.*}}]::' for friend template declaration is not supported; ignoring this friend declaration}} +}; + +#endif + +} // namespace dr2858 diff --git a/clang/test/Parser/cxx-class.cpp b/clang/test/Parser/cxx-class.cpp index 046d2dd580f0..c90c7e030a8b 100644 --- a/clang/test/Parser/cxx-class.cpp +++ b/clang/test/Parser/cxx-class.cpp @@ -59,14 +59,14 @@ typedef union { } y; } bug3177; -// check that we don't consume the token after the access specifier +// check that we don't consume the token after the access specifier // when it's not a colon class D { public // expected-error{{expected ':'}} int i; }; -// consume the token after the access specifier if it's a semicolon +// consume the token after the access specifier if it's a semicolon // that was meant to be a colon class E { public; // expected-error{{expected ':'}} @@ -281,7 +281,7 @@ struct A {} ::PR41192::a; // ok, no missing ';' here expected-warning {{extra q #if __cplusplus >= 201103L struct C; struct D { static C c; }; -struct C {} decltype(D())::c; // expected-error {{'decltype' cannot be used to name a declaration}} +struct C {} decltype(D())::c; // expected-error {{a 'decltype' specifier cannot be used in a declarative nested name specifier}} #endif } -- GitLab From 298ea9bfd50ca41c77e45065700df06adb6264ae Mon Sep 17 00:00:00 2001 From: Raghu Maddhipatla <7686592+raghavendhra@users.noreply.github.com> Date: Thu, 11 Apr 2024 10:26:54 -0500 Subject: [PATCH 531/695] [Flang] [OpenMP] [MLIR] [Lowering] Add lowering support for IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses on OMP TARGET directive. (#88206) Added lowering support for IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses for OMP TARGET directive and added related tests for these changes. IS_DEVICE_PTR and HAS_DEVICE_ADDR clauses apply to OMP TARGET directive OpenMP spec states The **is_device_ptr** clause indicates that its list items are device pointers. The **has_device_addr** clause indicates that its list items already have device addresses and therefore they may be directly accessed from a target device. Whereas USE_DEVICE_PTR and USE_DEVICE_ADDR clauses apply to OMP TARGET DATA directive and OpenMP spec for them states Each list item in the **use_device_ptr** clause results in a new list item that is a device pointer that refers to a device address Each list item in a **use_device_addr** clause that is present in the device data environment is treated as if it is implicitly mapped by a map clause on the construct with a map-type of alloc Fixed build error caused by Squash merge which needs rebase --- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 29 +++++++++++++ flang/lib/Lower/OpenMP/ClauseProcessor.h | 12 ++++++ flang/lib/Lower/OpenMP/OpenMP.cpp | 22 +++++++--- flang/test/Lower/OpenMP/FIR/target.f90 | 43 ++++++++++++++++++- .../Dialect/OpenMP/OpenMPClauseOperands.h | 16 ++++--- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 18 ++++++-- mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 9 ++-- mlir/test/Dialect/OpenMP/invalid.mlir | 2 +- mlir/test/Dialect/OpenMP/ops.mlir | 8 ++-- 9 files changed, 136 insertions(+), 23 deletions(-) diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 0a57a1496289..fb24c8d1fe3e 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -751,6 +751,20 @@ bool ClauseProcessor::processDepend( }); } +bool ClauseProcessor::processHasDeviceAddr( + llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl &isDeviceSymbols) + const { + return findRepeatableClause( + [&](const omp::clause::HasDeviceAddr &devAddrClause, + const Fortran::parser::CharBlock &) { + addUseDeviceClause(converter, devAddrClause.v, operands, isDeviceTypes, + isDeviceLocs, isDeviceSymbols); + }); +} + bool ClauseProcessor::processIf( omp::clause::If::DirectiveNameModifier directiveName, mlir::Value &result) const { @@ -771,6 +785,20 @@ bool ClauseProcessor::processIf( return found; } +bool ClauseProcessor::processIsDevicePtr( + llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl &isDeviceSymbols) + const { + return findRepeatableClause( + [&](const omp::clause::IsDevicePtr &devPtrClause, + const Fortran::parser::CharBlock &) { + addUseDeviceClause(converter, devPtrClause.v, operands, isDeviceTypes, + isDeviceLocs, isDeviceSymbols); + }); +} + bool ClauseProcessor::processLink( llvm::SmallVectorImpl &result) const { return findRepeatableClause( @@ -993,6 +1021,7 @@ bool ClauseProcessor::processUseDevicePtr( useDeviceLocs, useDeviceSymbols); }); } + } // namespace omp } // namespace lower } // namespace Fortran diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.h b/flang/lib/Lower/OpenMP/ClauseProcessor.h index d31d6a5c2062..df8f4f5310fc 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.h +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.h @@ -66,6 +66,12 @@ public: bool processDeviceType(mlir::omp::DeclareTargetDeviceType &result) const; bool processFinal(Fortran::lower::StatementContext &stmtCtx, mlir::Value &result) const; + bool + processHasDeviceAddr(llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl + &isDeviceSymbols) const; bool processHint(mlir::IntegerAttr &result) const; bool processMergeable(mlir::UnitAttr &result) const; bool processNowait(mlir::UnitAttr &result) const; @@ -104,6 +110,12 @@ public: bool processIf(omp::clause::If::DirectiveNameModifier directiveName, mlir::Value &result) const; bool + processIsDevicePtr(llvm::SmallVectorImpl &operands, + llvm::SmallVectorImpl &isDeviceTypes, + llvm::SmallVectorImpl &isDeviceLocs, + llvm::SmallVectorImpl + &isDeviceSymbols) const; + bool processLink(llvm::SmallVectorImpl &result) const; // This method is used to process a map clause. diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 340921c86724..50ad889052ab 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -1294,6 +1294,11 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, llvm::SmallVector mapSymTypes; llvm::SmallVector mapSymLocs; llvm::SmallVector mapSymbols; + llvm::SmallVector devicePtrOperands, deviceAddrOperands; + llvm::SmallVector devicePtrTypes, deviceAddrTypes; + llvm::SmallVector devicePtrLocs, deviceAddrLocs; + llvm::SmallVector devicePtrSymbols, + deviceAddrSymbols; ClauseProcessor cp(converter, semaCtx, clauseList); cp.processIf(llvm::omp::Directive::OMPD_target, ifClauseOperand); @@ -1303,11 +1308,15 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, cp.processNowait(nowaitAttr); cp.processMap(currentLocation, directive, stmtCtx, mapOperands, &mapSymTypes, &mapSymLocs, &mapSymbols); + cp.processIsDevicePtr(devicePtrOperands, devicePtrTypes, devicePtrLocs, + devicePtrSymbols); + cp.processHasDeviceAddr(deviceAddrOperands, deviceAddrTypes, deviceAddrLocs, + deviceAddrSymbols); - cp.processTODO( - currentLocation, llvm::omp::Directive::OMPD_target); + cp.processTODO(currentLocation, + llvm::omp::Directive::OMPD_target); // 5.8.1 Implicit Data-Mapping Attribute Rules // The following code follows the implicit data-mapping rules to map all the @@ -1400,7 +1409,8 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, ? nullptr : mlir::ArrayAttr::get(converter.getFirOpBuilder().getContext(), dependTypeOperands), - dependOperands, nowaitAttr, mapOperands); + dependOperands, nowaitAttr, devicePtrOperands, deviceAddrOperands, + mapOperands); genBodyOfTargetOp(converter, semaCtx, eval, genNested, targetOp, mapSymTypes, mapSymLocs, mapSymbols, currentLocation); @@ -2059,6 +2069,8 @@ genOMP(Fortran::lower::AbstractConverter &converter, !std::get_if(&clause.u) && !std::get_if(&clause.u) && !std::get_if(&clause.u) && + !std::get_if(&clause.u) && + !std::get_if(&clause.u) && !std::get_if(&clause.u) && !std::get_if(&clause.u)) { TODO(clauseLocation, "OpenMP Block construct clause"); diff --git a/flang/test/Lower/OpenMP/FIR/target.f90 b/flang/test/Lower/OpenMP/FIR/target.f90 index 821196b83c3b..022327f9c25d 100644 --- a/flang/test/Lower/OpenMP/FIR/target.f90 +++ b/flang/test/Lower/OpenMP/FIR/target.f90 @@ -506,4 +506,45 @@ subroutine omp_target_parallel_do !CHECK: omp.terminator !CHECK: } !$omp end target parallel do - end subroutine omp_target_parallel_do +end subroutine omp_target_parallel_do + +!=============================================================================== +! Target `is_device_ptr` clause +!=============================================================================== + +!CHECK-LABEL: func.func @_QPomp_target_is_device_ptr() { +subroutine omp_target_is_device_ptr + use iso_c_binding, only : c_ptr, c_loc + !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> {bindc_name = "a", uniq_name = "_QFomp_target_is_device_ptrEa"} + type(c_ptr) :: a + !CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "b", fir.target, uniq_name = "_QFomp_target_is_device_ptrEb"} + integer, target :: b + !CHECK: %[[MAP_0:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(tofrom) capture(ByRef) -> !fir.ref> {name = "a"} + !CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr(%[[VAL_0:.*]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "b"} + !CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByRef) -> !fir.ref> {name = "a"} + !CHECK: omp.target is_device_ptr(%[[DEV_PTR:.*]] : !fir.ref>) map_entries(%[[MAP_0:.*]] -> %[[ARG0:.*]], %[[MAP_1:.*]] -> %[[ARG1:.*]], %[[MAP_2:.*]] -> %[[ARG2:.*]] : !fir.ref>, !fir.ref, !fir.ref>) { + !CHECK: ^bb0(%[[ARG0]]: !fir.ref>, %[[ARG1]]: !fir.ref, %[[ARG2]]: !fir.ref>): + !$omp target map(tofrom: a,b) is_device_ptr(a) + !CHECK: {{.*}} = fir.coordinate_of %[[VAL_0:.*]], {{.*}} : (!fir.ref>, !fir.field) -> !fir.ref + a = c_loc(b) + !CHECK: omp.terminator + !$omp end target + !CHECK: } +end subroutine omp_target_is_device_ptr + + !=============================================================================== + ! Target `has_device_addr` clause + !=============================================================================== + + !CHECK-LABEL: func.func @_QPomp_target_has_device_addr() { + subroutine omp_target_has_device_addr + !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFomp_target_has_device_addrEa"} + integer, pointer :: a + !CHECK: omp.target has_device_addr(%[[VAL_0:.*]] : !fir.ref>>) map_entries({{.*}} -> {{.*}}, {{.*}} -> {{.*}} : !fir.llvm_ptr>, !fir.ref>>) { + !$omp target has_device_addr(a) + !CHECK: {{.*}} = fir.load %[[VAL_0:.*]] : !fir.ref>> + a = 10 + !CHECK: omp.terminator + !$omp end target + !CHECK: } +end subroutine omp_target_has_device_addr diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h index 6454076f7593..4ce7e47da046 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h @@ -81,6 +81,9 @@ struct GrainsizeClauseOps { Value grainsizeVar; }; +struct HasDeviceAddrOps { + llvm::SmallVector hasDeviceAddrVars; +}; struct HintClauseOps { IntegerAttr hintAttr; }; @@ -94,6 +97,10 @@ struct InReductionClauseOps { llvm::SmallVector inReductionDeclSymbols; }; +struct IsDevicePtrOps { + llvm::SmallVector isDevicePtrVars; +}; + struct LinearClauseOps { llvm::SmallVector linearVars, linearStepVars; }; @@ -251,13 +258,12 @@ using SimdLoopClauseOps = using SingleClauseOps = detail::Clauses; -// TODO `defaultmap`, `has_device_addr`, `is_device_ptr`, `uses_allocators` -// clauses. +// TODO `defaultmap`, `uses_allocators` clauses. using TargetClauseOps = detail::Clauses; + HasDeviceAddrOps, IfClauseOps, InReductionClauseOps, + IsDevicePtrOps, MapClauseOps, NowaitClauseOps, + PrivateClauseOps, ReductionClauseOps, ThreadLimitClauseOps>; using TargetDataClauseOps = detail::Clauses; diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index a38a82f9cc60..2a8582be3833 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -1678,14 +1678,23 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac The optional $thread_limit specifies the limit on the number of threads - The optional $nowait elliminates the implicit barrier so the parent task can make progress + The optional $nowait eliminates the implicit barrier so the parent task can make progress even if the target task is not yet completed. The `depends` and `depend_vars` arguments are variadic lists of values that specify the dependencies of this particular target task in relation to other tasks. - TODO: is_device_ptr, defaultmap, in_reduction + The optional $is_device_ptr indicates list items are device pointers. + + The optional $has_device_addr indicates that list items already have device + addresses, so they may be directly accessed from the target device. This + includes array sections. + + The optional $map_operands maps data from the task’s environment to the + device environment. + + TODO: defaultmap, in_reduction }]; @@ -1695,8 +1704,9 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac OptionalAttr:$depends, Variadic:$depend_vars, UnitAttr:$nowait, + Variadic:$is_device_ptr, + Variadic:$has_device_addr, Variadic:$map_operands); - let regions = (region AnyRegion:$region); let builders = [ @@ -1708,6 +1718,8 @@ def TargetOp : OpenMP_Op<"target", [IsolatedFromAbove, MapClauseOwningOpInterfac | `device` `(` $device `:` type($device) `)` | `thread_limit` `(` $thread_limit `:` type($thread_limit) `)` | `nowait` $nowait + | `is_device_ptr` `(` $is_device_ptr `:` type($is_device_ptr) `)` + | `has_device_addr` `(` $has_device_addr `:` type($has_device_addr) `)` | `map_entries` `(` custom($map_operands, type($map_operands)) `)` | `depend` `(` custom($depend_vars, type($depend_vars), $depends) `)` ) $region attr-dict diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index 543655338db8..2d5b2231d2dd 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -1258,10 +1258,11 @@ void TargetOp::build(OpBuilder &builder, OperationState &state, // TODO Store clauses in op: allocateVars, allocatorVars, inReductionVars, // inReductionDeclSymbols, privateVars, privatizers, reductionVars, // reductionByRefAttr, reductionDeclSymbols. - TargetOp::build(builder, state, clauses.ifVar, clauses.deviceVar, - clauses.threadLimitVar, - makeArrayAttr(ctx, clauses.dependTypeAttrs), - clauses.dependVars, clauses.nowaitAttr, clauses.mapVars); + TargetOp::build( + builder, state, clauses.ifVar, clauses.deviceVar, clauses.threadLimitVar, + makeArrayAttr(ctx, clauses.dependTypeAttrs), clauses.dependVars, + clauses.nowaitAttr, clauses.isDevicePtrVars, clauses.hasDeviceAddrVars, + clauses.mapVars); } LogicalResult TargetOp::verify() { diff --git a/mlir/test/Dialect/OpenMP/invalid.mlir b/mlir/test/Dialect/OpenMP/invalid.mlir index 1134db77d5ba..27a440b3f97c 100644 --- a/mlir/test/Dialect/OpenMP/invalid.mlir +++ b/mlir/test/Dialect/OpenMP/invalid.mlir @@ -1809,7 +1809,7 @@ func.func @omp_target_depend(%data_var: memref) { // expected-error @below {{op expected as many depend values as depend variables}} "omp.target"(%data_var) ({ "omp.terminator"() : () -> () - }) {depends = [], operandSegmentSizes = array} : (memref) -> () + }) {depends = [], operandSegmentSizes = array} : (memref) -> () "func.return"() : () -> () } diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index e2c255c7a3cc..ad5b74b84ac7 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -510,22 +510,22 @@ return // CHECK-LABEL: omp_target -func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %map1: memref, %map2: memref) -> () { +func.func @omp_target(%if_cond : i1, %device : si32, %num_threads : i32, %device_ptr: memref, %device_addr: memref, %map1: memref, %map2: memref) -> () { // Test with optional operands; if_expr, device, thread_limit, private, firstprivate and nowait. // CHECK: omp.target if({{.*}}) device({{.*}}) thread_limit({{.*}}) nowait "omp.target"(%if_cond, %device, %num_threads) ({ // CHECK: omp.terminator omp.terminator - }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () + }) {nowait, operandSegmentSizes = array} : ( i1, si32, i32 ) -> () // Test with optional map clause. // CHECK: %[[MAP_A:.*]] = omp.map.info var_ptr(%[[VAL_1:.*]] : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} // CHECK: %[[MAP_B:.*]] = omp.map.info var_ptr(%[[VAL_2:.*]] : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} - // CHECK: omp.target map_entries(%[[MAP_A]] -> {{.*}}, %[[MAP_B]] -> {{.*}} : memref, memref) { + // CHECK: omp.target is_device_ptr(%[[VAL_4:.*]] : memref) has_device_addr(%[[VAL_5:.*]] : memref) map_entries(%[[MAP_A]] -> {{.*}}, %[[MAP_B]] -> {{.*}} : memref, memref) { %mapv1 = omp.map.info var_ptr(%map1 : memref, tensor) map_clauses(tofrom) capture(ByRef) -> memref {name = ""} %mapv2 = omp.map.info var_ptr(%map2 : memref, tensor) map_clauses(exit_release_or_enter_alloc) capture(ByRef) -> memref {name = ""} - omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) { + omp.target map_entries(%mapv1 -> %arg0, %mapv2 -> %arg1 : memref, memref) is_device_ptr(%device_ptr : memref) has_device_addr(%device_addr : memref) { ^bb0(%arg0: memref, %arg1: memref): omp.terminator } -- GitLab From ffb5bea2be9f966a39f243a7d8c2f48a1343cb4c Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 11 Apr 2024 16:33:05 +0100 Subject: [PATCH 532/695] [X86] LowerBITREVERSE - support SSE-only GFNI i32/i64 bitreverse Support Tremont CPUs which don't have AVX but do have GFNI. Noticed while trying to workout how to clean up the costmodel for GFNI bitreverse --- llvm/lib/Target/X86/X86ISelLowering.cpp | 17 ++++---- llvm/test/CodeGen/X86/vector-bitreverse.ll | 46 ++++------------------ 2 files changed, 15 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 52be35aafb0f..f274da6f6f77 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -1286,6 +1286,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::CTLZ, VT, Custom); } + if (Subtarget.hasGFNI()) { + setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); + setOperationAction(ISD::BITREVERSE, MVT::i64, Custom); + } + // These might be better off as horizontal vector ops. setOperationAction(ISD::ADD, MVT::i16, Custom); setOperationAction(ISD::ADD, MVT::i32, Custom); @@ -1496,11 +1501,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::TRUNCATE, MVT::v32i32, Custom); setOperationAction(ISD::TRUNCATE, MVT::v32i64, Custom); - if (Subtarget.hasGFNI()) { - setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); - setOperationAction(ISD::BITREVERSE, MVT::i64, Custom); - } - for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { setOperationAction(ISD::SETCC, VT, Custom); setOperationAction(ISD::CTPOP, VT, Custom); @@ -31337,12 +31337,9 @@ static SDValue LowerBITREVERSE(SDValue Op, const X86Subtarget &Subtarget, if (VT.is256BitVector() && !Subtarget.hasInt256()) return splitVectorIntUnary(Op, DAG, DL); - // Lower i32/i64 to GFNI as vXi8 BITREVERSE + BSWAP + // Lower i32/i64 as vXi8 BITREVERSE + BSWAP if (!VT.isVector()) { - - assert((VT.getScalarType() == MVT::i32) || - (VT.getScalarType() == MVT::i64)); - + assert((VT == MVT::i32 || VT == MVT::i64) && "Only tested for i32/i64"); MVT VecVT = MVT::getVectorVT(VT, 128 / VT.getSizeInBits()); SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, In); Res = DAG.getNode(ISD::BITREVERSE, DL, MVT::v16i8, diff --git a/llvm/test/CodeGen/X86/vector-bitreverse.ll b/llvm/test/CodeGen/X86/vector-bitreverse.ll index 1c5326d35bb0..b22b508db8b2 100644 --- a/llvm/test/CodeGen/X86/vector-bitreverse.ll +++ b/llvm/test/CodeGen/X86/vector-bitreverse.ll @@ -254,24 +254,10 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; ; GFNISSE-LABEL: test_bitreverse_i32: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: # kill: def $edi killed $edi def $rdi -; GFNISSE-NEXT: bswapl %edi -; GFNISSE-NEXT: movl %edi, %eax -; GFNISSE-NEXT: andl $252645135, %eax # imm = 0xF0F0F0F -; GFNISSE-NEXT: shll $4, %eax -; GFNISSE-NEXT: shrl $4, %edi -; GFNISSE-NEXT: andl $252645135, %edi # imm = 0xF0F0F0F -; GFNISSE-NEXT: orl %eax, %edi -; GFNISSE-NEXT: movl %edi, %eax -; GFNISSE-NEXT: andl $858993459, %eax # imm = 0x33333333 -; GFNISSE-NEXT: shrl $2, %edi -; GFNISSE-NEXT: andl $858993459, %edi # imm = 0x33333333 -; GFNISSE-NEXT: leal (%rdi,%rax,4), %eax -; GFNISSE-NEXT: movl %eax, %ecx -; GFNISSE-NEXT: andl $1431655765, %ecx # imm = 0x55555555 -; GFNISSE-NEXT: shrl %eax -; GFNISSE-NEXT: andl $1431655765, %eax # imm = 0x55555555 -; GFNISSE-NEXT: leal (%rax,%rcx,2), %eax +; GFNISSE-NEXT: movd %edi, %xmm0 +; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; GFNISSE-NEXT: movd %xmm0, %eax +; GFNISSE-NEXT: bswapl %eax ; GFNISSE-NEXT: retq ; ; GFNIAVX-LABEL: test_bitreverse_i32: @@ -343,26 +329,10 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; ; GFNISSE-LABEL: test_bitreverse_i64: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: bswapq %rdi -; GFNISSE-NEXT: movq %rdi, %rax -; GFNISSE-NEXT: shrq $4, %rax -; GFNISSE-NEXT: movabsq $1085102592571150095, %rcx # imm = 0xF0F0F0F0F0F0F0F -; GFNISSE-NEXT: andq %rcx, %rax -; GFNISSE-NEXT: andq %rcx, %rdi -; GFNISSE-NEXT: shlq $4, %rdi -; GFNISSE-NEXT: orq %rax, %rdi -; GFNISSE-NEXT: movabsq $3689348814741910323, %rax # imm = 0x3333333333333333 -; GFNISSE-NEXT: movq %rdi, %rcx -; GFNISSE-NEXT: andq %rax, %rcx -; GFNISSE-NEXT: shrq $2, %rdi -; GFNISSE-NEXT: andq %rax, %rdi -; GFNISSE-NEXT: leaq (%rdi,%rcx,4), %rax -; GFNISSE-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555 -; GFNISSE-NEXT: movq %rax, %rdx -; GFNISSE-NEXT: andq %rcx, %rdx -; GFNISSE-NEXT: shrq %rax -; GFNISSE-NEXT: andq %rcx, %rax -; GFNISSE-NEXT: leaq (%rax,%rdx,2), %rax +; GFNISSE-NEXT: movq %rdi, %xmm0 +; GFNISSE-NEXT: gf2p8affineqb $0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; GFNISSE-NEXT: movq %xmm0, %rax +; GFNISSE-NEXT: bswapq %rax ; GFNISSE-NEXT: retq ; ; GFNIAVX-LABEL: test_bitreverse_i64: -- GitLab From 7ab7e7a55f3fce08ccd3cbcae94dabe99dd9e94a Mon Sep 17 00:00:00 2001 From: Xu Zhang Date: Thu, 11 Apr 2024 23:49:59 +0800 Subject: [PATCH 533/695] [libc][docs] Generate docs for signal.h & optimized is_implemented func (#88028) Fixes #87835 This patch added the documentation for the POSIX functions according to [n3096](https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3096.pdf) Section 7.14, and gives the *docgen.py* script a more elegant *is_implemented* function. --- libc/docs/index.rst | 1 + libc/docs/signal.rst | 43 +++++++++++++++++++++++++++++++++++ libc/utils/docgen/docgen.py | 13 +++++++---- libc/utils/docgen/signal.json | 29 +++++++++++++++++++++++ 4 files changed, 82 insertions(+), 4 deletions(-) create mode 100644 libc/docs/signal.rst create mode 100644 libc/utils/docgen/signal.json diff --git a/libc/docs/index.rst b/libc/docs/index.rst index 8470c8d9287c..11d5ae197d71 100644 --- a/libc/docs/index.rst +++ b/libc/docs/index.rst @@ -70,6 +70,7 @@ stages there is no ABI stability in any form. libc_search c23 ctype + signal .. toctree:: :hidden: diff --git a/libc/docs/signal.rst b/libc/docs/signal.rst new file mode 100644 index 000000000000..7903bb439cb3 --- /dev/null +++ b/libc/docs/signal.rst @@ -0,0 +1,43 @@ +.. include:: check.rst + +signal.h Functions +================== + +.. list-table:: + :widths: auto + :align: center + :header-rows: 1 + + * - Function + - Implemented + - Standard + * - kill + - |check| + - + * - raise + - |check| + - 7.14.2.1 + * - sigaction + - |check| + - + * - sigaddset + - |check| + - + * - sigaltstack + - |check| + - + * - sigdelset + - |check| + - + * - sigemptyset + - |check| + - + * - sigfillset + - |check| + - + * - signal + - |check| + - 7.14.1.1 + * - sigprocmask + - |check| + - diff --git a/libc/utils/docgen/docgen.py b/libc/utils/docgen/docgen.py index 7411b4506f08..36eb409421b4 100755 --- a/libc/utils/docgen/docgen.py +++ b/libc/utils/docgen/docgen.py @@ -23,12 +23,17 @@ def load_api(hname: str) -> Dict: # TODO: we may need to get more sophisticated for less generic implementations. # Does libc/src/{hname minus .h suffix}/{fname}.cpp exist? def is_implemented(hname: str, fname: str) -> bool: - return Path( + path = Path( Path(__file__).parent.parent.parent, "src", - hname.rstrip(".h"), - fname + ".cpp", - ).exists() + hname.rstrip(".h") + ) + # Recursively search for the target source file in the subdirectories under + # libc/src/{hname}. + for _ in path.glob("**/" + fname + ".cpp"): + return True + + return False def print_functions(header: str, functions: Dict): diff --git a/libc/utils/docgen/signal.json b/libc/utils/docgen/signal.json new file mode 100644 index 000000000000..976021a803a6 --- /dev/null +++ b/libc/utils/docgen/signal.json @@ -0,0 +1,29 @@ +{ + "macros": [ + "SIG_DFL", + "SIG_ERR", + "SIG_IGN", + "SIGABRT", + "SIGFPE", + "SIGILL", + "SIGINT", + "SIGSEGV", + "SIGTERM" + ], + "functions": { + "kill": null, + "sigaction": null, + "sigaddset": null, + "sigaltstack": null, + "sigdelset": null, + "sigemptyset": null, + "sigfillset": null, + "sigprocmask": null, + "signal": { + "defined": "7.14.1.1" + }, + "raise": { + "defined": "7.14.2.1" + } + } +} -- GitLab From b63fe0d72e2df3b3c4b9fcb91aea07b2582be195 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Thu, 11 Apr 2024 17:55:25 +0200 Subject: [PATCH 534/695] [libc++][NFC] Reduce the memory footprint of __copy_cv a bit (#87718) Instead of instantiating `__copy_cv` for every combination of `_From` and `_To` this only instantiates `__copy_cv` for every `_From` type, reducing the number of instantiations. --- libcxx/include/__type_traits/copy_cv.h | 28 +++++++++++++++----------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/libcxx/include/__type_traits/copy_cv.h b/libcxx/include/__type_traits/copy_cv.h index b1c057ff778b..d482cb42bffe 100644 --- a/libcxx/include/__type_traits/copy_cv.h +++ b/libcxx/include/__type_traits/copy_cv.h @@ -19,28 +19,32 @@ _LIBCPP_BEGIN_NAMESPACE_STD // Let COPYCV(FROM, TO) be an alias for type TO with the addition of FROM's // top-level cv-qualifiers. -template +template struct __copy_cv { - using type = _To; + template + using __apply = _To; }; -template -struct __copy_cv { - using type = const _To; +template +struct __copy_cv { + template + using __apply = const _To; }; -template -struct __copy_cv { - using type = volatile _To; +template +struct __copy_cv { + template + using __apply = volatile _To; }; -template -struct __copy_cv { - using type = const volatile _To; +template +struct __copy_cv { + template + using __apply = const volatile _To; }; template -using __copy_cv_t = typename __copy_cv<_From, _To>::type; +using __copy_cv_t = typename __copy_cv<_From>::template __apply<_To>; _LIBCPP_END_NAMESPACE_STD -- GitLab From 72f9881c3ffcf4be6361c3e4312d91c9c8d94a98 Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Thu, 11 Apr 2024 17:09:07 +0100 Subject: [PATCH 535/695] [libclc] Refactor build system to allow in-tree builds (#87622) The previous build system was adding custom "OpenCL" and "LLVM IR" languages in CMake to build the builtin libraries. This was making it harder to build in-tree because the tool binaries needed to be present at configure time. This commit refactors the build system to use custom commands to build the bytecode files one by one, and link them all together into the final bytecode library. It also enables in-tree builds by aliasing the clang/llvm-link/etc. tool targets to internal targets, which are imported from the LLVM installation directory when building out of tree. Diffing (with llvm-diff) all of the final bytecode libraries in an out-of-tree configuration against those built using the current tip system shows no changes. Note that there are textual changes to metadata IDs which confuse regular diff, and that llvm-diff 14 and below may show false-positives. This commit also removes a file listed in one of the SOURCEs which didn't exist and which was preventing the use of ENABLE_RUNTIME_SUBNORMAL when configuring CMake. --- libclc/CMakeLists.txt | 277 +++++++++++------- libclc/cmake/CMakeCLCCompiler.cmake.in | 9 - libclc/cmake/CMakeCLCInformation.cmake | 12 - libclc/cmake/CMakeDetermineCLCCompiler.cmake | 18 -- .../cmake/CMakeDetermineLLAsmCompiler.cmake | 24 -- libclc/cmake/CMakeLLAsmCompiler.cmake.in | 10 - libclc/cmake/CMakeLLAsmInformation.cmake | 12 - libclc/cmake/CMakeTestCLCCompiler.cmake | 56 ---- libclc/cmake/CMakeTestLLAsmCompiler.cmake | 56 ---- libclc/cmake/modules/AddLibclc.cmake | 156 ++++++++++ libclc/generic/lib/SOURCES | 1 - llvm/tools/CMakeLists.txt | 3 + 12 files changed, 322 insertions(+), 312 deletions(-) delete mode 100644 libclc/cmake/CMakeCLCCompiler.cmake.in delete mode 100644 libclc/cmake/CMakeCLCInformation.cmake delete mode 100644 libclc/cmake/CMakeDetermineCLCCompiler.cmake delete mode 100644 libclc/cmake/CMakeDetermineLLAsmCompiler.cmake delete mode 100644 libclc/cmake/CMakeLLAsmCompiler.cmake.in delete mode 100644 libclc/cmake/CMakeLLAsmInformation.cmake delete mode 100644 libclc/cmake/CMakeTestCLCCompiler.cmake delete mode 100644 libclc/cmake/CMakeTestLLAsmCompiler.cmake create mode 100644 libclc/cmake/modules/AddLibclc.cmake diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt index c6e3cdf23fe0..7528228b3b7f 100644 --- a/libclc/CMakeLists.txt +++ b/libclc/CMakeLists.txt @@ -4,6 +4,15 @@ project( libclc VERSION 0.2.0 LANGUAGES CXX C) set(CMAKE_CXX_STANDARD 17) +# Add path for custom modules +list( INSERT CMAKE_MODULE_PATH 0 "${PROJECT_SOURCE_DIR}/cmake/modules" ) + +set( LIBCLC_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR} ) +set( LIBCLC_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR} ) +set( LIBCLC_OBJFILE_DIR ${LIBCLC_BINARY_DIR}/obj.libclc.dir ) + +include( AddLibclc ) + include( GNUInstallDirs ) set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS amdgcn-amdhsa/lib/SOURCES; @@ -27,31 +36,51 @@ set( LIBCLC_TARGETS_TO_BUILD "all" option( ENABLE_RUNTIME_SUBNORMAL "Enable runtime linking of subnormal support." OFF ) -find_package(LLVM REQUIRED HINTS "${LLVM_CMAKE_DIR}") -include(AddLLVM) +if( LIBCLC_STANDALONE_BUILD OR CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR ) + # Out-of-tree configuration + set( LIBCLC_STANDALONE_BUILD TRUE ) -message( STATUS "libclc LLVM version: ${LLVM_PACKAGE_VERSION}" ) + find_package(LLVM REQUIRED HINTS "${LLVM_CMAKE_DIR}") + include(AddLLVM) -if( LLVM_PACKAGE_VERSION VERSION_LESS LIBCLC_MIN_LLVM ) - message( FATAL_ERROR "libclc needs at least LLVM ${LIBCLC_MIN_LLVM}" ) -endif() + message( STATUS "libclc LLVM version: ${LLVM_PACKAGE_VERSION}" ) -find_program( LLVM_CLANG clang PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) -find_program( LLVM_AS llvm-as PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) -find_program( LLVM_LINK llvm-link PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) -find_program( LLVM_OPT opt PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) -find_program( LLVM_SPIRV llvm-spirv PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) + if( LLVM_PACKAGE_VERSION VERSION_LESS LIBCLC_MIN_LLVM ) + message( FATAL_ERROR "libclc needs at least LLVM ${LIBCLC_MIN_LLVM}" ) + endif() + + # Import required tools as targets + foreach( tool clang llvm-as llvm-link opt ) + find_program( LLVM_TOOL_${tool} ${tool} PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) + add_executable( libclc::${tool} IMPORTED GLOBAL ) + set_target_properties( libclc::${tool} PROPERTIES IMPORTED_LOCATION ${LLVM_TOOL_${tool}} ) + endforeach() +else() + # In-tree configuration + set( LIBCLC_STANDALONE_BUILD FALSE ) + + set( LLVM_PACKAGE_VERSION ${LLVM_VERSION} ) -# Print toolchain -message( STATUS "libclc toolchain - clang: ${LLVM_CLANG}" ) -message( STATUS "libclc toolchain - llvm-as: ${LLVM_AS}" ) -message( STATUS "libclc toolchain - llvm-link: ${LLVM_LINK}" ) -message( STATUS "libclc toolchain - opt: ${LLVM_OPT}" ) -message( STATUS "libclc toolchain - llvm-spirv: ${LLVM_SPIRV}" ) -if( NOT LLVM_CLANG OR NOT LLVM_OPT OR NOT LLVM_AS OR NOT LLVM_LINK ) + # Note that we check this later (for both build types) but we can provide a + # more useful error message when built in-tree. We assume that LLVM tools are + # always available so don't warn here. + if( NOT clang IN_LIST LLVM_ENABLE_PROJECTS ) + message(FATAL_ERROR "Clang is not enabled, but is required to build libclc in-tree") + endif() + + foreach( tool clang llvm-as llvm-link opt ) + add_executable(libclc::${tool} ALIAS ${tool}) + endforeach() +endif() + +if( NOT TARGET libclc::clang OR NOT TARGET libclc::opt + OR NOT TARGET libclc::llvm-as OR NOT TARGET libclc::llvm-link ) message( FATAL_ERROR "libclc toolchain incomplete!" ) endif() +# llvm-spirv is an optional dependency, used to build spirv-* targets. +find_program( LLVM_SPIRV llvm-spirv PATHS ${LLVM_TOOLS_BINARY_DIR} NO_DEFAULT_PATH ) + # List of all targets. Note that some are added dynamically below. set( LIBCLC_TARGETS_ALL amdgcn-- @@ -90,24 +119,9 @@ if( "spirv-mesa3d-" IN_LIST LIBCLC_TARGETS_TO_BUILD OR "spirv64-mesa3d-" IN_LIST endif() endif() -set( CMAKE_MODULE_PATH ${PROJECT_SOURCE_DIR}/cmake ) -set( CMAKE_CLC_COMPILER ${LLVM_CLANG} ) -set( CMAKE_CLC_ARCHIVE ${LLVM_LINK} ) -set( CMAKE_LLAsm_PREPROCESSOR ${LLVM_CLANG} ) -set( CMAKE_LLAsm_COMPILER ${LLVM_AS} ) -set( CMAKE_LLAsm_ARCHIVE ${LLVM_LINK} ) - # Construct LLVM version define set( LLVM_VERSION_DEFINE "-DHAVE_LLVM=0x${LLVM_VERSION_MAJOR}0${LLVM_VERSION_MINOR}" ) - -# LLVM 13 enables standard includes by default -if( LLVM_PACKAGE_VERSION VERSION_GREATER_EQUAL 13.0.0 ) - set( CMAKE_LLAsm_FLAGS "${CMAKE_LLAsm_FLAGS} -cl-no-stdinc" ) - set( CMAKE_CLC_FLAGS "${CMAKE_CLC_FLAGS} -cl-no-stdinc" ) -endif() - -enable_language( CLC LLAsm ) # This needs to be set before any target that needs it # We need to use LLVM_INCLUDE_DIRS here, because if we are linking to an # llvm build directory, this includes $src/llvm/include which is where all the @@ -122,7 +136,7 @@ set(LLVM_LINK_COMPONENTS IRReader Support ) -if(CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR) +if( LIBCLC_STANDALONE_BUILD ) add_llvm_executable( prepare_builtins utils/prepare-builtins.cpp ) else() add_llvm_utility( prepare_builtins utils/prepare-builtins.cpp ) @@ -167,12 +181,14 @@ install( FILES ${CMAKE_CURRENT_BINARY_DIR}/libclc.pc DESTINATION "${CMAKE_INSTAL install( DIRECTORY generic/include/clc DESTINATION "${CMAKE_INSTALL_INCLUDEDIR}" ) if( ENABLE_RUNTIME_SUBNORMAL ) - add_library( subnormal_use_default STATIC - generic/lib/subnormal_use_default.ll ) - add_library( subnormal_disable STATIC - generic/lib/subnormal_disable.ll ) - install( TARGETS subnormal_use_default subnormal_disable ARCHIVE - DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) + foreach( file subnormal_use_default subnormal_disable ) + link_bc( + TARGET ${file} + INPUTS ${PROJECT_SOURCE_DIR}/generic/lib/${file}.ll + ) + install( FILES $ ARCHIVE + DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) + endforeach() endif() find_package( Python3 REQUIRED COMPONENTS Interpreter ) @@ -232,19 +248,19 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) # Add the generated convert.cl here to prevent adding the one listed in # SOURCES + set( objects ) # A "set" of already-added input files + set( rel_files ) # Source directory input files, relative to the root dir + set( gen_files ) # Generated binary input files, relative to the binary dir if( NOT ${ARCH} STREQUAL "spirv" AND NOT ${ARCH} STREQUAL "spirv64" ) if( NOT ENABLE_RUNTIME_SUBNORMAL AND NOT ${ARCH} STREQUAL "clspv" AND NOT ${ARCH} STREQUAL "clspv64" ) - set( rel_files convert.cl ) - set( objects convert.cl ) + list( APPEND gen_files convert.cl ) + list( APPEND objects convert.cl ) list( APPEND rel_files generic/lib/subnormal_use_default.ll ) elseif(${ARCH} STREQUAL "clspv" OR ${ARCH} STREQUAL "clspv64") - set( rel_files clspv-convert.cl ) - set( objects clspv-convert.cl ) + list( APPEND gen_files clspv-convert.cl ) + list( APPEND objects clspv-convert.cl ) endif() - else() - set( rel_files ) - set( objects ) endif() foreach( l ${source_list} ) @@ -252,46 +268,35 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) string( REPLACE "\n" ";" file_list ${file_list} ) get_filename_component( dir ${l} DIRECTORY ) foreach( f ${file_list} ) - list( FIND objects ${f} found ) - if( found EQUAL -1 ) + # Only add each file once, so that targets can 'specialize' builtins + if( NOT ${f} IN_LIST objects ) list( APPEND objects ${f} ) list( APPEND rel_files ${dir}/${f} ) - # FIXME: This should really go away - file( TO_CMAKE_PATH ${PROJECT_SOURCE_DIR}/${dir}/${f} src_loc ) - get_filename_component( fdir ${src_loc} DIRECTORY ) - - set_source_files_properties( ${dir}/${f} - PROPERTIES COMPILE_FLAGS "-I ${fdir}" ) endif() endforeach() endforeach() foreach( d ${${t}_devices} ) - # Some targets don't have a specific GPU to target - if( ${d} STREQUAL "none" OR ${ARCH} STREQUAL "spirv" OR ${ARCH} STREQUAL "spirv64" ) - set( mcpu ) - set( arch_suffix "${t}" ) - else() - set( mcpu "-mcpu=${d}" ) - set( arch_suffix "${d}-${t}" ) + get_libclc_device_info( + TRIPLE ${t} + DEVICE ${d} + CPU cpu + ARCH_SUFFIX arch_suffix + CLANG_TRIPLE clang_triple + ) + + set( mcpu ) + if( NOT "${cpu}" STREQUAL "" ) + set( mcpu "-mcpu=${cpu}" ) endif() + message( STATUS " device: ${d} ( ${${d}_aliases} )" ) - if ( ${ARCH} STREQUAL "spirv" OR ${ARCH} STREQUAL "spirv64" ) - if( ${ARCH} STREQUAL "spirv" ) - set( t "spir--" ) - else() - set( t "spir64--" ) - endif() + if ( ARCH STREQUAL spirv OR ARCH STREQUAL spirv64 ) set( build_flags -O0 -finline-hint-functions ) set( opt_flags ) set( spvflags --spirv-max-version=1.1 ) - elseif( ${ARCH} STREQUAL "clspv" ) - set( t "spir--" ) - set( build_flags "-Wno-unknown-assumption") - set( opt_flags -O3 ) - elseif( ${ARCH} STREQUAL "clspv64" ) - set( t "spir64--" ) + elseif( ARCH STREQUAL clspv OR ARCH STREQUAL clspv64 ) set( build_flags "-Wno-unknown-assumption") set( opt_flags -O3 ) else() @@ -299,53 +304,97 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) set( opt_flags -O3 ) endif() + set( LIBCLC_ARCH_OBJFILE_DIR "${LIBCLC_OBJFILE_DIR}/${arch_suffix}" ) + file( MAKE_DIRECTORY ${LIBCLC_ARCH_OBJFILE_DIR} ) + + string( TOUPPER "CLC_${ARCH}" CLC_TARGET_DEFINE ) + + list( APPEND build_flags + -D__CLC_INTERNAL + -D${CLC_TARGET_DEFINE} + -I${PROJECT_SOURCE_DIR}/generic/include + # FIXME: Fix libclc to not require disabling this noisy warning + -Wno-bitwise-conditional-parentheses + ) + + set( bytecode_files "" ) + foreach( file IN LISTS gen_files rel_files ) + # We need to take each file and produce an absolute input file, as well + # as a unique architecture-specific output file. We deal with a mix of + # different input files, which makes this trickier. + if( ${file} IN_LIST gen_files ) + # Generated files are given just as file names, which we must make + # absolute to the binary directory. + set( input_file ${CMAKE_CURRENT_BINARY_DIR}/${file} ) + set( output_file "${LIBCLC_ARCH_OBJFILE_DIR}/${file}.o" ) + else() + # Other files are originally relative to each SOURCE file, which are + # then make relative to the libclc root directory. We must normalize + # the path (e.g., ironing out any ".."), then make it relative to the + # root directory again, and use that relative path component for the + # binary path. + get_filename_component( abs_path ${file} ABSOLUTE BASE_DIR ${PROJECT_SOURCE_DIR} ) + file( RELATIVE_PATH root_rel_path ${PROJECT_SOURCE_DIR} ${abs_path} ) + set( input_file ${PROJECT_SOURCE_DIR}/${file} ) + set( output_file "${LIBCLC_ARCH_OBJFILE_DIR}/${root_rel_path}.o" ) + endif() + + get_filename_component( file_dir ${file} DIRECTORY ) + + compile_to_bc( + TRIPLE ${clang_triple} + INPUT ${input_file} + OUTPUT ${output_file} + EXTRA_OPTS "${mcpu}" -fno-builtin -nostdlib + "${build_flags}" -I${PROJECT_SOURCE_DIR}/${file_dir} + ) + list( APPEND bytecode_files ${output_file} ) + endforeach() + set( builtins_link_lib_tgt builtins.link.${arch_suffix} ) - add_library( ${builtins_link_lib_tgt} STATIC ${rel_files} ) - # Make sure we depend on the pseudo target to prevent - # multiple invocations - add_dependencies( ${builtins_link_lib_tgt} generate_convert.cl ) - add_dependencies( ${builtins_link_lib_tgt} clspv-generate_convert.cl ) - # CMake will turn this include into absolute path - target_include_directories( ${builtins_link_lib_tgt} PRIVATE - "generic/include" ) - target_compile_definitions( ${builtins_link_lib_tgt} PRIVATE - "__CLC_INTERNAL" ) - string( TOUPPER "-DCLC_${ARCH}" CLC_TARGET_DEFINE ) - target_compile_definitions( ${builtins_link_lib_tgt} PRIVATE - ${CLC_TARGET_DEFINE} ) - target_compile_options( ${builtins_link_lib_tgt} PRIVATE -target - ${t} ${mcpu} -fno-builtin -nostdlib ${build_flags} ) - set_target_properties( ${builtins_link_lib_tgt} PROPERTIES - LINKER_LANGUAGE CLC ) - - set( obj_suffix ${arch_suffix}.bc ) - set( builtins_opt_lib_tgt builtins.opt.${obj_suffix} ) - - # Add opt target - add_custom_command( OUTPUT ${builtins_opt_lib_tgt} - COMMAND ${LLVM_OPT} ${opt_flags} -o ${builtins_opt_lib_tgt} - $ - DEPENDS ${builtins_link_lib_tgt} ) - add_custom_target( "opt.${obj_suffix}" ALL - DEPENDS ${builtins_opt_lib_tgt} ) - - if( ${ARCH} STREQUAL "spirv" OR ${ARCH} STREQUAL "spirv64" ) + + link_bc( + TARGET ${builtins_link_lib_tgt} + INPUTS ${bytecode_files} + ) + + set( builtins_link_lib $ ) + + if( ARCH STREQUAL spirv OR ARCH STREQUAL spirv64 ) set( spv_suffix ${arch_suffix}.spv ) - add_custom_command( OUTPUT "${spv_suffix}" - COMMAND ${LLVM_SPIRV} ${spvflags} -o "${spv_suffix}" $ - DEPENDS ${builtins_link_lib_tgt} ) + add_custom_command( OUTPUT ${spv_suffix} + COMMAND ${LLVM_SPIRV} ${spvflags} -o ${spv_suffix} ${builtins_link_lib} + DEPENDS ${builtins_link_lib_tgt} + ) add_custom_target( "prepare-${spv_suffix}" ALL DEPENDS "${spv_suffix}" ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${spv_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) else() + set( builtins_opt_lib_tgt builtins.opt.${arch_suffix} ) + + # Add opt target + add_custom_command( OUTPUT ${builtins_opt_lib_tgt}.bc + COMMAND libclc::opt ${opt_flags} -o ${builtins_opt_lib_tgt}.bc + ${builtins_link_lib} + DEPENDS libclc::opt ${builtins_link_lib_tgt} + ) + add_custom_target( ${builtins_opt_lib_tgt} + ALL DEPENDS ${builtins_opt_lib_tgt}.bc + ) + set_target_properties( ${builtins_opt_lib_tgt} + PROPERTIES TARGET_FILE ${builtins_opt_lib_tgt}.bc + ) + # Add prepare target - add_custom_command( OUTPUT "${obj_suffix}" - COMMAND prepare_builtins -o "${obj_suffix}" ${builtins_opt_lib_tgt} - DEPENDS "opt.${obj_suffix}" ${builtins_opt_lib_tgt} prepare_builtins ) - add_custom_target( "prepare-${obj_suffix}" ALL DEPENDS "${obj_suffix}" ) + set( obj_suffix ${arch_suffix}.bc ) + add_custom_command( OUTPUT ${obj_suffix} + COMMAND prepare_builtins -o ${obj_suffix} + $ + DEPENDS ${builtins_opt_lib_tgt} prepare_builtins ) + add_custom_target( prepare-${obj_suffix} ALL DEPENDS ${obj_suffix} ) # nvptx-- targets don't include workitem builtins - if( NOT ${t} MATCHES ".*ptx.*--$" ) + if( NOT clang_triple MATCHES ".*ptx.*--$" ) add_test( NAME external-calls-${obj_suffix} COMMAND ./check_external_calls.sh ${CMAKE_CURRENT_BINARY_DIR}/${obj_suffix} ${LLVM_TOOLS_BINARY_DIR} WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} ) @@ -353,10 +402,10 @@ foreach( t ${LIBCLC_TARGETS_TO_BUILD} ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${obj_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) foreach( a ${${d}_aliases} ) - set( alias_suffix "${a}-${t}.bc" ) + set( alias_suffix "${a}-${clang_triple}.bc" ) add_custom_target( ${alias_suffix} ALL COMMAND ${CMAKE_COMMAND} -E create_symlink ${obj_suffix} ${alias_suffix} - DEPENDS "prepare-${obj_suffix}" ) + DEPENDS prepare-${obj_suffix} ) install( FILES ${CMAKE_CURRENT_BINARY_DIR}/${alias_suffix} DESTINATION "${CMAKE_INSTALL_DATADIR}/clc" ) endforeach( a ) endif() diff --git a/libclc/cmake/CMakeCLCCompiler.cmake.in b/libclc/cmake/CMakeCLCCompiler.cmake.in deleted file mode 100644 index 2730b83d9e7d..000000000000 --- a/libclc/cmake/CMakeCLCCompiler.cmake.in +++ /dev/null @@ -1,9 +0,0 @@ -set(CMAKE_CLC_COMPILER "@CMAKE_CLC_COMPILER@") -set(CMAKE_CLC_COMPILER_LOADED 1) - -set(CMAKE_CLC_SOURCE_FILE_EXTENSIONS cl) -set(CMAKE_CLC_OUTPUT_EXTENSION .bc) -set(CMAKE_CLC_OUTPUT_EXTENSION_REPLACE 1) -set(CMAKE_STATIC_LIBRARY_PREFIX_CLC "") -set(CMAKE_STATIC_LIBRARY_SUFFIX_CLC ".bc") -set(CMAKE_CLC_COMPILER_ENV_VAR "CLC_COMPILER") diff --git a/libclc/cmake/CMakeCLCInformation.cmake b/libclc/cmake/CMakeCLCInformation.cmake deleted file mode 100644 index 95327e443972..000000000000 --- a/libclc/cmake/CMakeCLCInformation.cmake +++ /dev/null @@ -1,12 +0,0 @@ -if(NOT CMAKE_CLC_COMPILE_OBJECT) - set(CMAKE_CLC_COMPILE_OBJECT - " -o -c -emit-llvm") -endif() - -if(NOT CMAKE_CLC_CREATE_STATIC_LIBRARY) - set(CMAKE_CLC_CREATE_STATIC_LIBRARY - " -o ") -endif() - -set(CMAKE_INCLUDE_FLAG_CLC "-I") -set(CMAKE_DEPFILE_FLAGS_CLC "-MD -MT -MF ") diff --git a/libclc/cmake/CMakeDetermineCLCCompiler.cmake b/libclc/cmake/CMakeDetermineCLCCompiler.cmake deleted file mode 100644 index 94d85d9e666a..000000000000 --- a/libclc/cmake/CMakeDetermineCLCCompiler.cmake +++ /dev/null @@ -1,18 +0,0 @@ -include(${CMAKE_ROOT}/Modules/CMakeDetermineCompiler.cmake) - -if(NOT CMAKE_CLC_COMPILER) - find_program(CMAKE_CLC_COMPILER NAMES clang) -endif() -mark_as_advanced(CMAKE_CLC_COMPILER) - -if(NOT CMAKE_CLC_ARCHIVE) - find_program(CMAKE_CLC_ARCHIVE NAMES llvm-link) -endif() -mark_as_advanced(CMAKE_CLC_ARCHIVE) - -set(CMAKE_CLC_COMPILER_ENV_VAR "CLC_COMPILER") -set(CMAKE_CLC_ARCHIVE_ENV_VAR "CLC_LINKER") -find_file(clc_comp_in CMakeCLCCompiler.cmake.in PATHS ${CMAKE_ROOT}/Modules ${CMAKE_MODULE_PATH}) -# configure all variables set in this file -configure_file(${clc_comp_in} ${CMAKE_PLATFORM_INFO_DIR}/CMakeCLCCompiler.cmake @ONLY) -mark_as_advanced(clc_comp_in) diff --git a/libclc/cmake/CMakeDetermineLLAsmCompiler.cmake b/libclc/cmake/CMakeDetermineLLAsmCompiler.cmake deleted file mode 100644 index 1c424c79cb45..000000000000 --- a/libclc/cmake/CMakeDetermineLLAsmCompiler.cmake +++ /dev/null @@ -1,24 +0,0 @@ -include(${CMAKE_ROOT}/Modules/CMakeDetermineCompiler.cmake) - -if(NOT CMAKE_LLAsm_PREPROCESSOR) - find_program(CMAKE_LLAsm_PREPROCESSOR NAMES clang) -endif() -mark_as_advanced(CMAKE_LLAsm_PREPROCESSOR) - -if(NOT CMAKE_LLAsm_COMPILER) - find_program(CMAKE_LLAsm_COMPILER NAMES llvm-as) -endif() -mark_as_advanced(CMAKE_LLAsm_ASSEMBLER) - -if(NOT CMAKE_LLAsm_ARCHIVE) - find_program(CMAKE_LLAsm_ARCHIVE NAMES llvm-link) -endif() -mark_as_advanced(CMAKE_LLAsm_ARCHIVE) - -set(CMAKE_LLAsm_PREPROCESSOR_ENV_VAR "LL_PREPROCESSOR") -set(CMAKE_LLAsm_COMPILER_ENV_VAR "LL_ASSEMBLER") -set(CMAKE_LLAsm_ARCHIVE_ENV_VAR "LL_LINKER") -find_file(ll_comp_in CMakeLLAsmCompiler.cmake.in PATHS ${CMAKE_ROOT}/Modules ${CMAKE_MODULE_PATH}) -# configure all variables set in this file -configure_file(${ll_comp_in} ${CMAKE_PLATFORM_INFO_DIR}/CMakeLLAsmCompiler.cmake @ONLY) -mark_as_advanced(ll_comp_in) diff --git a/libclc/cmake/CMakeLLAsmCompiler.cmake.in b/libclc/cmake/CMakeLLAsmCompiler.cmake.in deleted file mode 100644 index 2b00f69234dd..000000000000 --- a/libclc/cmake/CMakeLLAsmCompiler.cmake.in +++ /dev/null @@ -1,10 +0,0 @@ -set(CMAKE_LLAsm_PREPROCESSOR "@CMAKE_LLAsm_PREPROCESSOR@") -set(CMAKE_LLAsm_COMPILER "@CMAKE_LLAsm_COMPILER@") -set(CMAKE_LLAsm_ARCHIVE "@CMAKE_LLAsm_ARCHIVE@") -set(CMAKE_LLAsm_COMPILER_LOADED 1) - -set(CMAKE_LLAsm_SOURCE_FILE_EXTENSIONS ll) -set(CMAKE_LLAsm_OUTPUT_EXTENSION .bc) -set(CMAKE_LLAsm_OUTPUT_EXTENSION_REPLACE 1) -set(CMAKE_STATIC_LIBRARY_PREFIX_LLAsm "") -set(CMAKE_STATIC_LIBRARY_SUFFIX_LLAsm ".bc") diff --git a/libclc/cmake/CMakeLLAsmInformation.cmake b/libclc/cmake/CMakeLLAsmInformation.cmake deleted file mode 100644 index 35ec3081da0f..000000000000 --- a/libclc/cmake/CMakeLLAsmInformation.cmake +++ /dev/null @@ -1,12 +0,0 @@ -if(NOT CMAKE_LLAsm_COMPILE_OBJECT) - set(CMAKE_LLAsm_COMPILE_OBJECT - "${CMAKE_LLAsm_PREPROCESSOR} -E -P -x cl -o .temp" - " -o .temp") -endif() - -if(NOT CMAKE_LLAsm_CREATE_STATIC_LIBRARY) - set(CMAKE_LLAsm_CREATE_STATIC_LIBRARY - " -o ") -endif() - -set(CMAKE_INCLUDE_FLAG_LLAsm "-I") diff --git a/libclc/cmake/CMakeTestCLCCompiler.cmake b/libclc/cmake/CMakeTestCLCCompiler.cmake deleted file mode 100644 index 869fcc3d01ab..000000000000 --- a/libclc/cmake/CMakeTestCLCCompiler.cmake +++ /dev/null @@ -1,56 +0,0 @@ -if(CMAKE_CLC_COMPILER_FORCED) - # The compiler configuration was forced by the user. - # Assume the user has configured all compiler information. - set(CMAKE_CLC_COMPILER_WORKS TRUE) - return() -endif() - -include(CMakeTestCompilerCommon) - -# Remove any cached result from an older CMake version. -# We now store this in CMakeCCompiler.cmake. -unset(CMAKE_CLC_COMPILER_WORKS CACHE) - -# This file is used by EnableLanguage in cmGlobalGenerator to -# determine that that selected CLC compiler can actually compile -# and link the most basic of programs. If not, a fatal error -# is set and cmake stops processing commands and will not generate -# any makefiles or projects. -if(NOT CMAKE_CLC_COMPILER_WORKS) - PrintTestCompilerStatus("CLC" "") - file(WRITE ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/testCLCCompiler.cl - "__kernel void test_k(global int * a)\n" - "{ *a = 1; }\n") - try_compile(CMAKE_CLC_COMPILER_WORKS ${CMAKE_BINARY_DIR} - ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/testCLCCompiler.cl - # We never generate executable so bypass the link step - CMAKE_FLAGS -DCMAKE_CLC_LINK_EXECUTABLE='echo' - OUTPUT_VARIABLE __CMAKE_CLC_COMPILER_OUTPUT) - # Move result from cache to normal variable. - set(CMAKE_CLC_COMPILER_WORKS ${CMAKE_CLC_COMPILER_WORKS}) - unset(CMAKE_CLC_COMPILER_WORKS CACHE) - set(CLC_TEST_WAS_RUN 1) -endif() - -if(NOT CMAKE_CLC_COMPILER_WORKS) - PrintTestCompilerStatus("CLC" " -- broken") - file(APPEND ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeError.log - "Determining if the CLC compiler works failed with " - "the following output:\n${__CMAKE_CLC_COMPILER_OUTPUT}\n\n") - message(FATAL_ERROR "The CLC compiler \"${CMAKE_CLC_COMPILER}\" " - "is not able to compile a simple test program.\nIt fails " - "with the following output:\n ${__CMAKE_CLC_COMPILER_OUTPUT}\n\n" - "CMake will not be able to correctly generate this project.") -else() - if(CLC_TEST_WAS_RUN) - PrintTestCompilerStatus("CLC" " -- works") - file(APPEND ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeOutput.log - "Determining if the CLC compiler works passed with " - "the following output:\n${__CMAKE_CLC_COMPILER_OUTPUT}\n\n") - endif() - - include(${CMAKE_PLATFORM_INFO_DIR}/CMakeCLCCompiler.cmake) - -endif() - -unset(__CMAKE_CLC_COMPILER_OUTPUT) diff --git a/libclc/cmake/CMakeTestLLAsmCompiler.cmake b/libclc/cmake/CMakeTestLLAsmCompiler.cmake deleted file mode 100644 index 35948ee07a94..000000000000 --- a/libclc/cmake/CMakeTestLLAsmCompiler.cmake +++ /dev/null @@ -1,56 +0,0 @@ -if(CMAKE_LLAsm_COMPILER_FORCED) - # The compiler configuration was forced by the user. - # Assume the user has configured all compiler information. - set(CMAKE_LLAsm_COMPILER_WORKS TRUE) - return() -endif() - -include(CMakeTestCompilerCommon) - -# Remove any cached result from an older CMake version. -# We now store this in CMakeCCompiler.cmake. -unset(CMAKE_LLAsm_COMPILER_WORKS CACHE) - -# This file is used by EnableLanguage in cmGlobalGenerator to -# determine that that selected llvm assembler can actually compile -# and link the most basic of programs. If not, a fatal error -# is set and cmake stops processing commands and will not generate -# any makefiles or projects. -if(NOT CMAKE_LLAsm_COMPILER_WORKS) - PrintTestCompilerStatus("LLAsm" "") - file(WRITE ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/testLLAsmCompiler.ll - "define i32 @test() {\n" - "ret i32 0 }\n" ) - try_compile(CMAKE_LLAsm_COMPILER_WORKS ${CMAKE_BINARY_DIR} - ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/testLLAsmCompiler.ll - # We never generate executable so bypass the link step - CMAKE_FLAGS -DCMAKE_LLAsm_LINK_EXECUTABLE='echo' - OUTPUT_VARIABLE __CMAKE_LLAsm_COMPILER_OUTPUT) - # Move result from cache to normal variable. - set(CMAKE_LLAsm_COMPILER_WORKS ${CMAKE_LLAsm_COMPILER_WORKS}) - unset(CMAKE_LLAsm_COMPILER_WORKS CACHE) - set(LLAsm_TEST_WAS_RUN 1) -endif() - -if(NOT CMAKE_LLAsm_COMPILER_WORKS) - PrintTestCompilerStatus("LLAsm" " -- broken") - file(APPEND ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeError.log - "Determining if the LLAsm compiler works failed with " - "the following output:\n${__CMAKE_LLAsm_COMPILER_OUTPUT}\n\n") - message(FATAL_ERROR "The LLAsm compiler \"${CMAKE_LLAsm_COMPILER}\" " - "is not able to compile a simple test program.\nIt fails " - "with the following output:\n ${__CMAKE_LLAsm_COMPILER_OUTPUT}\n\n" - "CMake will not be able to correctly generate this project.") -else() - if(LLAsm_TEST_WAS_RUN) - PrintTestCompilerStatus("LLAsm" " -- works") - file(APPEND ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeOutput.log - "Determining if the LLAsm compiler works passed with " - "the following output:\n${__CMAKE_LLAsm_COMPILER_OUTPUT}\n\n") - endif() - - include(${CMAKE_PLATFORM_INFO_DIR}/CMakeLLAsmCompiler.cmake) - -endif() - -unset(__CMAKE_LLAsm_COMPILER_OUTPUT) diff --git a/libclc/cmake/modules/AddLibclc.cmake b/libclc/cmake/modules/AddLibclc.cmake new file mode 100644 index 000000000000..5e09cde8035c --- /dev/null +++ b/libclc/cmake/modules/AddLibclc.cmake @@ -0,0 +1,156 @@ +# Compiles an OpenCL C - or assembles an LL file - to bytecode +# +# Arguments: +# * TRIPLE +# Target triple for which to compile the bytecode file. +# * INPUT +# File to compile/assemble to bytecode +# * OUTPUT +# Bytecode file to generate +# * EXTRA_OPTS ... +# List of compiler options to use. Note that some are added by default. +# * DEPENDENCIES ... +# List of extra dependencies to inject +# +# Depends on the libclc::clang and libclc::llvm-as targets for compiling and +# assembling, respectively. +function(compile_to_bc) + cmake_parse_arguments(ARG + "" + "TRIPLE;INPUT;OUTPUT" + "EXTRA_OPTS;DEPENDENCIES" + ${ARGN} + ) + + # If this is an LLVM IR file (identified soley by its file suffix), + # pre-process it with clang to a temp file, then assemble that to bytecode. + set( TMP_SUFFIX ) + get_filename_component( FILE_EXT ${ARG_INPUT} EXT ) + if( NOT ${FILE_EXT} STREQUAL ".ll" ) + # Pass '-c' when not running the preprocessor + set( PP_OPTS -c ) + else() + set( PP_OPTS -E;-P ) + set( TMP_SUFFIX .tmp ) + endif() + + set( TARGET_ARG ) + if( ARG_TRIPLE ) + set( TARGET_ARG "-target" ${ARG_TRIPLE} ) + endif() + + add_custom_command( + OUTPUT ${ARG_OUTPUT}${TMP_SUFFIX} + COMMAND libclc::clang + ${TARGET_ARG} + ${PP_OPTS} + ${ARG_EXTRA_OPTS} + -MD -MF ${ARG_OUTPUT}.d -MT ${ARG_OUTPUT}${TMP_SUFFIX} + # LLVM 13 enables standard includes by default - we don't want + # those when pre-processing IR. We disable it unconditionally. + $<$:-cl-no-stdinc> + -emit-llvm + -o ${ARG_OUTPUT}${TMP_SUFFIX} + -x cl + ${ARG_INPUT} + DEPENDS + libclc::clang + ${ARG_INPUT} + ${ARG_DEPENDENCIES} + DEPFILE ${ARG_OUTPUT}.d + ) + + if( ${FILE_EXT} STREQUAL ".ll" ) + add_custom_command( + OUTPUT ${ARG_OUTPUT} + COMMAND libclc::llvm-as -o ${ARG_OUTPUT} ${ARG_OUTPUT}${TMP_SUFFIX} + DEPENDS libclc::llvm-as ${ARG_OUTPUT}${TMP_SUFFIX} + ) + endif() +endfunction() + +# Links together one or more bytecode files +# +# Arguments: +# * TARGET +# Custom target to create +# * INPUT ... +# List of bytecode files to link together +function(link_bc) + cmake_parse_arguments(ARG + "" + "TARGET" + "INPUTS" + ${ARGN} + ) + + add_custom_command( + OUTPUT ${ARG_TARGET}.bc + COMMAND libclc::llvm-link -o ${ARG_TARGET}.bc ${ARG_INPUTS} + DEPENDS libclc::llvm-link ${ARG_INPUTS} + ) + + add_custom_target( ${ARG_TARGET} ALL DEPENDS ${ARG_TARGET}.bc ) + set_target_properties( ${ARG_TARGET} PROPERTIES TARGET_FILE ${ARG_TARGET}.bc ) +endfunction() + +# Decomposes and returns variables based on a libclc triple and architecture +# combination. Returns data via one or more optional output variables. +# +# Arguments: +# * TRIPLE +# libclc target triple to query +# * DEVICE +# libclc device to query +# +# Optional Arguments: +# * CPU +# Variable name to be set to the target CPU +# * ARCH_SUFFIX +# Variable name to be set to the triple/architecture suffix +# * CLANG_TRIPLE +# Variable name to be set to the normalized clang triple +function(get_libclc_device_info) + cmake_parse_arguments(ARG + "" + "TRIPLE;DEVICE;CPU;ARCH_SUFFIX;CLANG_TRIPLE" + "" + ${ARGN} + ) + + if( NOT ARG_TRIPLE OR NOT ARG_DEVICE ) + message( FATAL_ERROR "Must provide both TRIPLE and DEVICE" ) + endif() + + string( REPLACE "-" ";" TRIPLE ${ARG_TRIPLE} ) + list( GET TRIPLE 0 ARCH ) + + # Some targets don't have a specific device architecture to target + if( ARG_DEVICE STREQUAL none OR ARCH STREQUAL spirv OR ARCH STREQUAL spirv64 ) + set( cpu ) + set( arch_suffix "${ARG_TRIPLE}" ) + else() + set( cpu "${ARG_DEVICE}" ) + set( arch_suffix "${ARG_DEVICE}-${ARG_TRIPLE}" ) + endif() + + if( ARG_CPU ) + set( ${ARG_CPU} ${cpu} PARENT_SCOPE ) + endif() + + if( ARG_ARCH_SUFFIX ) + set( ${ARG_ARCH_SUFFIX} ${arch_suffix} PARENT_SCOPE ) + endif() + + # Some libclc targets are not real clang triples: return their canonical + # triples. + if( ARCH STREQUAL spirv OR ARCH STREQUAL clspv ) + set( ARG_TRIPLE "spir--" ) + elseif( ARCH STREQUAL spirv64 OR ARCH STREQUAL clspv64 ) + set( ARG_TRIPLE "spir64--" ) + endif() + + if( ARG_CLANG_TRIPLE ) + set( ${ARG_CLANG_TRIPLE} ${ARG_TRIPLE} PARENT_SCOPE ) + endif() +endfunction() diff --git a/libclc/generic/lib/SOURCES b/libclc/generic/lib/SOURCES index ee2736b5fbc5..579e909e53d4 100644 --- a/libclc/generic/lib/SOURCES +++ b/libclc/generic/lib/SOURCES @@ -48,7 +48,6 @@ cl_khr_int64_extended_atomics/atom_max.cl cl_khr_int64_extended_atomics/atom_min.cl cl_khr_int64_extended_atomics/atom_or.cl cl_khr_int64_extended_atomics/atom_xor.cl -convert.cl common/degrees.cl common/mix.cl common/radians.cl diff --git a/llvm/tools/CMakeLists.txt b/llvm/tools/CMakeLists.txt index cde57367934e..db66dad5dc0d 100644 --- a/llvm/tools/CMakeLists.txt +++ b/llvm/tools/CMakeLists.txt @@ -52,6 +52,9 @@ add_llvm_implicit_projects() add_llvm_external_project(polly) +# libclc depends on clang +add_llvm_external_project(libclc) + # Add subprojects specified using LLVM_EXTERNAL_PROJECTS foreach(p ${LLVM_EXTERNAL_PROJECTS}) add_llvm_external_project(${p}) -- GitLab From 0d96422768908a8235f05a5d3b1d43ecc6038004 Mon Sep 17 00:00:00 2001 From: Derek Schuff Date: Thu, 11 Apr 2024 09:30:48 -0700 Subject: [PATCH 536/695] [Object][Wasm] Move wasm Object tests into their own directory (NFC) (#81072) --- .../{wasm-bad-data-symbol.yaml => Wasm/bad-data-symbol.yaml} | 0 .../bad-metadata-version.yaml} | 0 llvm/test/Object/Wasm/bad-reloc-type.test | 3 +++ .../{wasm-bad-relocation.yaml => Wasm/bad-relocation.yaml} | 0 llvm/test/Object/Wasm/bad-symbol-type.test | 3 +++ .../{wasm-duplicate-name.test => Wasm/duplicate-name.test} | 0 .../Object/{wasm-invalid-file.yaml => Wasm/invalid-file.yaml} | 0 .../invalid-section-order.test} | 2 +- .../{wasm-invalid-start.test => Wasm/invalid-start.test} | 0 .../linked-namesec-with-linkingsec.yaml} | 0 .../linked-symbol-table.yaml} | 0 llvm/test/Object/Wasm/missing-version.test | 2 ++ .../{wasm-obj2yaml-tables.test => Wasm/obj2yaml-tables.test} | 2 +- .../relocs-and-producers.yaml} | 0 llvm/test/Object/Wasm/string-outside-section.test | 3 +++ llvm/test/Object/wasm-bad-reloc-type.test | 3 --- llvm/test/Object/wasm-bad-symbol-type.test | 3 --- llvm/test/Object/wasm-missing-version.test | 2 -- llvm/test/Object/wasm-string-outside-section.test | 3 --- 19 files changed, 13 insertions(+), 13 deletions(-) rename llvm/test/Object/{wasm-bad-data-symbol.yaml => Wasm/bad-data-symbol.yaml} (100%) rename llvm/test/Object/{wasm-bad-metadata-version.yaml => Wasm/bad-metadata-version.yaml} (100%) create mode 100644 llvm/test/Object/Wasm/bad-reloc-type.test rename llvm/test/Object/{wasm-bad-relocation.yaml => Wasm/bad-relocation.yaml} (100%) create mode 100644 llvm/test/Object/Wasm/bad-symbol-type.test rename llvm/test/Object/{wasm-duplicate-name.test => Wasm/duplicate-name.test} (100%) rename llvm/test/Object/{wasm-invalid-file.yaml => Wasm/invalid-file.yaml} (100%) rename llvm/test/Object/{wasm-invalid-section-order.test => Wasm/invalid-section-order.test} (82%) rename llvm/test/Object/{wasm-invalid-start.test => Wasm/invalid-start.test} (100%) rename llvm/test/Object/{wasm-linked-namesec-with-linkingsec.yaml => Wasm/linked-namesec-with-linkingsec.yaml} (100%) rename llvm/test/Object/{wasm-linked-symbol-table.yaml => Wasm/linked-symbol-table.yaml} (100%) create mode 100644 llvm/test/Object/Wasm/missing-version.test rename llvm/test/Object/{wasm-obj2yaml-tables.test => Wasm/obj2yaml-tables.test} (98%) rename llvm/test/Object/{wasm-relocs-and-producers.yaml => Wasm/relocs-and-producers.yaml} (100%) create mode 100644 llvm/test/Object/Wasm/string-outside-section.test delete mode 100644 llvm/test/Object/wasm-bad-reloc-type.test delete mode 100644 llvm/test/Object/wasm-bad-symbol-type.test delete mode 100644 llvm/test/Object/wasm-missing-version.test delete mode 100644 llvm/test/Object/wasm-string-outside-section.test diff --git a/llvm/test/Object/wasm-bad-data-symbol.yaml b/llvm/test/Object/Wasm/bad-data-symbol.yaml similarity index 100% rename from llvm/test/Object/wasm-bad-data-symbol.yaml rename to llvm/test/Object/Wasm/bad-data-symbol.yaml diff --git a/llvm/test/Object/wasm-bad-metadata-version.yaml b/llvm/test/Object/Wasm/bad-metadata-version.yaml similarity index 100% rename from llvm/test/Object/wasm-bad-metadata-version.yaml rename to llvm/test/Object/Wasm/bad-metadata-version.yaml diff --git a/llvm/test/Object/Wasm/bad-reloc-type.test b/llvm/test/Object/Wasm/bad-reloc-type.test new file mode 100644 index 000000000000..4e210271c0b9 --- /dev/null +++ b/llvm/test/Object/Wasm/bad-reloc-type.test @@ -0,0 +1,3 @@ +RUN: not llvm-objdump -s %p/../Inputs/WASM/bad-reloc-type.wasm 2>&1 | FileCheck %s + +CHECK: invalid relocation type: 63 diff --git a/llvm/test/Object/wasm-bad-relocation.yaml b/llvm/test/Object/Wasm/bad-relocation.yaml similarity index 100% rename from llvm/test/Object/wasm-bad-relocation.yaml rename to llvm/test/Object/Wasm/bad-relocation.yaml diff --git a/llvm/test/Object/Wasm/bad-symbol-type.test b/llvm/test/Object/Wasm/bad-symbol-type.test new file mode 100644 index 000000000000..5b9770f18bb6 --- /dev/null +++ b/llvm/test/Object/Wasm/bad-symbol-type.test @@ -0,0 +1,3 @@ +RUN: not llvm-objdump -s %p/../Inputs/WASM/bad-symbol-type.wasm 2>&1 | FileCheck %s + +CHECK: invalid symbol type: 63 diff --git a/llvm/test/Object/wasm-duplicate-name.test b/llvm/test/Object/Wasm/duplicate-name.test similarity index 100% rename from llvm/test/Object/wasm-duplicate-name.test rename to llvm/test/Object/Wasm/duplicate-name.test diff --git a/llvm/test/Object/wasm-invalid-file.yaml b/llvm/test/Object/Wasm/invalid-file.yaml similarity index 100% rename from llvm/test/Object/wasm-invalid-file.yaml rename to llvm/test/Object/Wasm/invalid-file.yaml diff --git a/llvm/test/Object/wasm-invalid-section-order.test b/llvm/test/Object/Wasm/invalid-section-order.test similarity index 82% rename from llvm/test/Object/wasm-invalid-section-order.test rename to llvm/test/Object/Wasm/invalid-section-order.test index 9a67f09150e5..93cf9eb57059 100644 --- a/llvm/test/Object/wasm-invalid-section-order.test +++ b/llvm/test/Object/Wasm/invalid-section-order.test @@ -1,4 +1,4 @@ -# RUN: not obj2yaml %p/Inputs/WASM/invalid-section-order.wasm 2>&1 | FileCheck %s +# RUN: not obj2yaml %p/../Inputs/WASM/invalid-section-order.wasm 2>&1 | FileCheck %s # CHECK: {{.*}}: out of order section type: 10 # Inputs/WASM/invalid-section-order.wasm is generated from this ll file, by diff --git a/llvm/test/Object/wasm-invalid-start.test b/llvm/test/Object/Wasm/invalid-start.test similarity index 100% rename from llvm/test/Object/wasm-invalid-start.test rename to llvm/test/Object/Wasm/invalid-start.test diff --git a/llvm/test/Object/wasm-linked-namesec-with-linkingsec.yaml b/llvm/test/Object/Wasm/linked-namesec-with-linkingsec.yaml similarity index 100% rename from llvm/test/Object/wasm-linked-namesec-with-linkingsec.yaml rename to llvm/test/Object/Wasm/linked-namesec-with-linkingsec.yaml diff --git a/llvm/test/Object/wasm-linked-symbol-table.yaml b/llvm/test/Object/Wasm/linked-symbol-table.yaml similarity index 100% rename from llvm/test/Object/wasm-linked-symbol-table.yaml rename to llvm/test/Object/Wasm/linked-symbol-table.yaml diff --git a/llvm/test/Object/Wasm/missing-version.test b/llvm/test/Object/Wasm/missing-version.test new file mode 100644 index 000000000000..754658e9d0dd --- /dev/null +++ b/llvm/test/Object/Wasm/missing-version.test @@ -0,0 +1,2 @@ +# RUN: not llvm-objdump -h %p/../Inputs/WASM/missing-version.wasm 2>&1 | FileCheck %s +# CHECK: {{.*}}: missing version number diff --git a/llvm/test/Object/wasm-obj2yaml-tables.test b/llvm/test/Object/Wasm/obj2yaml-tables.test similarity index 98% rename from llvm/test/Object/wasm-obj2yaml-tables.test rename to llvm/test/Object/Wasm/obj2yaml-tables.test index 870ffd179a1c..877238437b01 100644 --- a/llvm/test/Object/wasm-obj2yaml-tables.test +++ b/llvm/test/Object/Wasm/obj2yaml-tables.test @@ -1,4 +1,4 @@ -RUN: obj2yaml %p/Inputs/WASM/multi-table.wasm | FileCheck %s +RUN: obj2yaml %p/../Inputs/WASM/multi-table.wasm | FileCheck %s # CHECK: - Type: TABLE diff --git a/llvm/test/Object/wasm-relocs-and-producers.yaml b/llvm/test/Object/Wasm/relocs-and-producers.yaml similarity index 100% rename from llvm/test/Object/wasm-relocs-and-producers.yaml rename to llvm/test/Object/Wasm/relocs-and-producers.yaml diff --git a/llvm/test/Object/Wasm/string-outside-section.test b/llvm/test/Object/Wasm/string-outside-section.test new file mode 100644 index 000000000000..31f4a6080d9b --- /dev/null +++ b/llvm/test/Object/Wasm/string-outside-section.test @@ -0,0 +1,3 @@ +RUN: not --crash llvm-objdump -s %p/../Inputs/WASM/string-outside-section.wasm 2>&1 | FileCheck %s + +CHECK: LLVM ERROR: EOF while reading string diff --git a/llvm/test/Object/wasm-bad-reloc-type.test b/llvm/test/Object/wasm-bad-reloc-type.test deleted file mode 100644 index 000acbd55fce..000000000000 --- a/llvm/test/Object/wasm-bad-reloc-type.test +++ /dev/null @@ -1,3 +0,0 @@ -RUN: not llvm-objdump -s %p/Inputs/WASM/bad-reloc-type.wasm 2>&1 | FileCheck %s - -CHECK: invalid relocation type: 63 diff --git a/llvm/test/Object/wasm-bad-symbol-type.test b/llvm/test/Object/wasm-bad-symbol-type.test deleted file mode 100644 index 4b7c30ad8b73..000000000000 --- a/llvm/test/Object/wasm-bad-symbol-type.test +++ /dev/null @@ -1,3 +0,0 @@ -RUN: not llvm-objdump -s %p/Inputs/WASM/bad-symbol-type.wasm 2>&1 | FileCheck %s - -CHECK: invalid symbol type: 63 diff --git a/llvm/test/Object/wasm-missing-version.test b/llvm/test/Object/wasm-missing-version.test deleted file mode 100644 index beb0b5e9105b..000000000000 --- a/llvm/test/Object/wasm-missing-version.test +++ /dev/null @@ -1,2 +0,0 @@ -# RUN: not llvm-objdump -h %p/Inputs/WASM/missing-version.wasm 2>&1 | FileCheck %s -# CHECK: {{.*}}: missing version number diff --git a/llvm/test/Object/wasm-string-outside-section.test b/llvm/test/Object/wasm-string-outside-section.test deleted file mode 100644 index 3fa6217bae8e..000000000000 --- a/llvm/test/Object/wasm-string-outside-section.test +++ /dev/null @@ -1,3 +0,0 @@ -RUN: not --crash llvm-objdump -s %p/Inputs/WASM/string-outside-section.wasm 2>&1 | FileCheck %s - -CHECK: LLVM ERROR: EOF while reading string -- GitLab From 3c4b673af05f53e8a4d1a382b5c86367ea512c9e Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Thu, 11 Apr 2024 12:36:56 -0400 Subject: [PATCH 537/695] [libc++] Fix -Wgnu-include-next in stddef.h (#88214) As reported in #86843, we must have #pragma GCC system_header before we use #include_next, otherwise the compiler may not understand that we're in a system header and may issue a diagnostic for our usage of --- libcxx/include/stddef.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/libcxx/include/stddef.h b/libcxx/include/stddef.h index 470b5408336c..1583e78e3739 100644 --- a/libcxx/include/stddef.h +++ b/libcxx/include/stddef.h @@ -26,6 +26,10 @@ Types: #include <__config> +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + // Note: This include is outside of header guards because we sometimes get included multiple times // with different defines and the underlying will know how to deal with that. #include_next @@ -33,10 +37,6 @@ Types: #ifndef _LIBCPP_STDDEF_H # define _LIBCPP_STDDEF_H -# if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) -# pragma GCC system_header -# endif - # ifdef __cplusplus typedef decltype(nullptr) nullptr_t; # endif -- GitLab From 357f6c7826437f6527db6f99f756a34fb5e0f716 Mon Sep 17 00:00:00 2001 From: abidh Date: Thu, 11 Apr 2024 17:53:25 +0100 Subject: [PATCH 538/695] [flang] Add design document for debug info generation. (#86939) This document discusses some options where the debug metadata can be generated. It also goes through various language constructs and explains how the debug metadata will look like for that construct and how we can extract that information. The real point of discussion is how and where to extract the information about various language features to generate the debug metadata. The structure of the metadata itself is mostly settled as that is dictated by the DWARF and structure of LLVM IR metadata. The classic flang and gfortran generate quite similar DWARF for the various language constructs. This document is based on what Kiran posted in https://reviews.llvm.org/D138534. --------- Co-authored-by: Tom Eccles Co-authored-by: Kiran Chandramohan --- flang/docs/DebugGeneration.md | 442 ++++++++++++++++++++++++++++++++++ flang/docs/index.md | 1 + 2 files changed, 443 insertions(+) create mode 100644 flang/docs/DebugGeneration.md diff --git a/flang/docs/DebugGeneration.md b/flang/docs/DebugGeneration.md new file mode 100644 index 000000000000..9409d7e07b10 --- /dev/null +++ b/flang/docs/DebugGeneration.md @@ -0,0 +1,442 @@ +# Debug Generation + +Application developers spend a significant time debugging the applications that +they create. Hence it is important that a compiler provide support for a good +debug experience. DWARF[1] is the standard debugging file format used by +compilers and debuggers. The LLVM infrastructure supports debug info generation +using metadata[2]. Support for generating debug metadata is present +in MLIR by way of MLIR attributes. Flang can leverage these MLIR attributes to +generate good debug information. + +We can break the work for debug generation into two separate tasks: +1) Line Table generation +2) Full debug generation +The support for Fortran Debug in LLVM infrastructure[3] has made great progress +due to many Fortran frontends adopting LLVM as the backend as well as the +availability of the Classic Flang compiler. + +## Driver Flags +By default, Flang will not generate any debug or linetable information. +Debug information will be generated if the following flags are present. + +-gline-tables-only, -g1 : Emit debug line number tables only +-g : Emit full debug info + +## Line Table Generation + +There is existing AddDebugFoundationPass which add `FusedLoc` with a +`SubprogramAttr` on FuncOp. This allows MLIR to generate LLVM IR metadata +for that function. However, following values are hardcoded at the moment. These +will instead be passed from the driver. + +- Details of the compiler (name and version and git hash). +- Language Standard. We can set it to Fortran95 for now and periodically +revise it when full support for later standards is available. +- Optimisation Level. +- Type of debug generated (linetable/full debug). +- Calling Convention: `DW_CC_normal` by default and `DW_CC_program` if it is +the main program. + +`DISubroutineTypeAttr` currently has a fixed type. This will be changed to +match the signature of the actual function/subroutine. + + +## Full Debug Generation + +Full debug info will include metadata to describe functions, variables and +types. Flang will generate debug metadata in the form of MLIR attributes. These +attributes will be converted to the format expected by LLVM IR in DebugTranslation[4]. + +Debug metadata generation can be broken down in 2 steps. + +1. MLIR attributes are generated by reading information from AST or FIR. This +step can happen anytime before or during conversion to LLVM dialect. An example +of the metadata generated in this step is `DILocalVariableAttr` or +`DIDerivedTypeAttr`. + +2. Changes that can only happen during or after conversion to LLVM dialect. The +example of this is passing `DIGlobalVariableExpressionAttr` while +creating `LLVM::GlobalOp`. Another example will be generation of `DbgDeclareOp` +that is required for local variables. It can only be created after conversion to +LLVM dialect as it requires LLVM.Ptr type. The changes required for step 2 are +quite minimal. The bulk of the work happens in step 1. + +One design decision that we need to make is to decide where to perform step 1. +Here are some possible options: + +**During conversion to LLVM dialect** + +Pros: +1. Do step 1 and 2 in one place. +2. No chance of missing any change introduced by an earlier transformation. + +Cons: +1. Passing a lot of information from the driver as discussed in the line table +section above may muddle interface of FIRToLLVMConversion. +2. `DeclareOp` is removed before this pass. +3. Even if `DeclareOp` is retained, creating debug metadata while some ops have +been converted to LLVMdialect and others are not may cause its own issues. We +have to walk the ops chain to extract the information which may be problematic +in this case. +4. Some source information is lost by this point. Examples include +information about namelists, source line information about field of derived +types etc. + +**During a pass before conversion to LLVM dialect** + +This is similar to what AddDebugFoundationPass is currently doing. + +Pros: +1. One central location dedicated to debug information processing. This can +result in a cleaner implementation. +2. Similar to above, less chance of missing any change introduced by an earlier +transformation. + +Cons: +1. Step 2 still need to happen during conversion to LLVM dialect. But +changes required for step 2 are quite minimal. +2. Similar to above, some source information may be lost by this point. + +**During Lowering from AST** + +Pros +1. We have better source information. + +Cons: +1. There may be change in the code after lowering which may not be +reflected in debug information. +2. Comments on an earlier PR [5] advised against this approach. + +## Design + +The design below assumes that we are extracting the information from FIR. +If we generate debug metadata during lowering then the description below +may need to change. Although the generated metadata remains the same in +both cases. + +The AddDebugFoundationPass will be renamed to AddDebugInfo Pass. The +information mentioned in the line info section above will be passed to it from +the driver. This pass will run quite late in the pipeline but before +`DeclareOp` is removed. + +In this pass, we will iterate through the `GlobalOp`, `TypeInfoOp`, `FuncOp` +and `DeclareOp` to extract the source information and build the MLIR +attributes. A class will be added to handle conversion of MLIR and FIR types to +`DITypeAttr`. + +Following sections provide details of how various language constructs will be +handled. In these sections, the LLVM IR metadata and MLIR attributes have been +used interchangeably. As an example, `DILocalVariableAttr` is an MLIR attribute +which gets translated to LLVM IR's `DILocalVariable`. + +### Variables + +#### Local Variables + In MLIR, local variables are represented by `DILocalVariableAttr` which + stores information like source location and type. They also require a + `DbgDeclareOp` which binds `DILocalVariableAttr` with a location. + + In FIR, `DeclareOp` has source information about the variable. The + `DeclareOp` will be processed to create `DILocalVariableAttr`. This attr is + attached to the memref op of the `DeclareOp` using a `FusedLoc` approach. + + During conversion to LLVM dialect, when an op is encountered that has a + `DILocalVariableAttr` in its `FusedLoc`, a `DbgDeclareOp` is created which + binds the attr with its location. + + The change in the IR look like as follows: + +``` + original fir + %2 = fir.alloca i32 loc(#loc4) + %3 = fir.declare %2 {uniq_name = "_QMhelperFchangeEi"} + + Fir with FusedLoc. + + %2 = fir.alloca i32 loc(#loc38) + %3 = fir.declare %2 {uniq_name = "_QMhelperFchangeEi"} + #di_local_variable5 = #llvm.di_local_variable + #loc38 = loc(fused<#di_local_variable5>[#loc4]) + + After conversion to llvm dialect + + #di_local_variable = #llvm.di_local_variable + %1 = llvm.alloca %0 x i64 + llvm.intr.dbg.declare #di_local_variable = %1 +``` + +#### Function Arguments + +Arguments work in similar way, but they present a difficulty that `DeclareOp`'s +memref points to `BlockArgument`. Unlike the op in local variable case, +the `BlockArgument` are not handled by the FIRToLLVMLowering. This can easily +be handled by adding after conversion to LLVM dialect either in FIRToLLVMLowering +or in a separate pass. + +### Module + +In debug metadata, the Fortran module will be represented by `DIModuleAttr`. +The variables or functions inside module will have scope pointing to the parent module. + +``` +module helper + real glr + ... +end module helper + +!1 = !DICompileUnit(language: DW_LANG_Fortran90 ...) +!2 = !DIModule(scope: !1, name: "helper" ...) +!3 = !DIGlobalVariable(scope: !2, name: "glr" ...) + +Use of a module results in the following metadata. +!4 = !DIImportedEntity(tag: DW_TAG_imported_module, entity: !2) +``` + +Modules are not first class entities in the FIR. So there is no way to get +the location where they are declared in source file. + +But the information that a variable or function is part of a module +can be extracted from its mangled name along with name of the module. There is +a `GlobalOp` generated for each module variable in FIR and there is also a +`DeclareOp` in each function where the module variable is used. + +We will use the `GlobalOp` to generate the `DIModuleAttr` and associated +`DIGlobalVariableAttr`. A `DeclareOp` for module variable will be used +to generate `DIImportedEntityAttr`. Care will be taken to avoid generating +duplicate `DIImportedEntityAttr` entries in same function. + +### Derived Types + +A derived type will be represented in metadata by `DICompositeType` with a tag of +`DW_TAG_structure_type`. It will have elements which point to the components. + +``` + type :: t_pair + integer :: i + real :: x + end type +!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "t_pair", elements: !2 ...) +!2 = !{!3, !4} +!3 = !DIDerivedType(tag: DW_TAG_member, scope: !1, name: "i", size: 32, offset: 0, baseType: !5 ...) +!4 = !DIDerivedType(tag: DW_TAG_member, scope: !1, name: "x", size: 32, offset: 32, baseType: !6 ...) +!5 = !DIBasicType(tag: DW_TAG_base_type, name: "integer" ...) +!6 = !DIBasicType(tag: DW_TAG_base_type, name: "real" ...) +``` + +In FIR, `RecordType` and `TypeInfoOp` can be used to get information about the +location of the derived type and the types of its components. We may also use +`FusedLoc` on `TypeInfoOp` to encode location information for all the components +of the derived type. + +### CommonBlocks + +A common block will be represented in metadata by `DICommonBlockAttr` which +will be used as scope by the variable inside common block. `DIExpression` +can be used to give the offset of any given variable inside the global storage +for common block. + +``` +integer a, b +common /test/ a, b + +;@test_ = common global [8 x i8] zeroinitializer, !dbg !5, !dbg !6 +!1 = !DISubprogram() +!2 = !DICommonBlock(scope: !1, name: "test" ...) +!3 = !DIGlobalVariable(scope: !2, name: "a" ...) +!4 = !DIExpression() +!5 = !DIGlobalVariableExpression(var: !3, expr: !4) +!6 = !DIGlobalVariable(scope: !2, name: "b" ...) +!7 = !DIExpression(DW_OP_plus_uconst, 4) +!8 = !DIGlobalVariableExpression(var: !6, expr: !7) +``` + +In FIR, a common block results in a `GlobalOp` with common linkage. Every +function where the common block is used has `DeclareOp` for that variable. +This `DeclareOp` will point to global storage through +`CoordinateOp` and `AddrOfOp`. The `CoordinateOp` has the offset of the +location of this variable in global storage. There is enough information to +generate the required metadata. Although it requires walking up the chain from +`DeclaredOp` to locate `CoordinateOp` and `AddrOfOp`. + +### Arrays + +The type of fixed size array is represented using `DICompositeType`. The +`DISubrangeAttr` is used to provide bounds in any given dimensions. + +``` +integer abc(4,5) + +!1 = !DICompositeType(tag: DW_TAG_array_type, baseType: !5, elements: !2 ...) +!2 = !{ !3, !4 } +!3 = !DISubrange(lowerBound: 1, upperBound: 4 ...) +!4 = !DISubrange(lowerBound: 1, upperBound: 5 ...) +!5 = !DIBasicType(tag: DW_TAG_base_type, name: "integer" ...) + +``` + +#### Adjustable + +The debug metadata for the adjustable array looks similar to fixed sized array +with one change. The bounds are not constant values but point to a +`DILocalVariableAttr`. + +In FIR, the `DeclareOp` points to a `ShapeOp` and we can walk the chain +to get the value that represents the array bound in any dimension. We will +create a `DILocalVariableAttr` that will point to that location. This +variable will be used in the `DISubrangeAttr`. Note that this +`DILocalVariableAttr` does not correspond to any source variable. + +#### Assumed Size + +This is treated as raw array. Debug information will not provide any upper bound +information for the last dimension. + +#### Assumed Shape +The assumed shape array will use the similar representation as fixed size +array but there will be 2 differences. + +1. There will be a `datalocation` field which will be an expression. This will +enable debugger to get the data pointer from array descriptor. + +2. The field in `DISubrangeAttr` for array bounds will be expression which will +allow the debugger to get the bounds from descriptor. + +``` +integer(4), intent(out) :: a(:,:) + +!1 = !DICompositeType(tag: DW_TAG_array_type, baseType: !8, elements: !2, dataLocation: !3) +!2 = !{!5, !7} +!3 = !DIExpression(DW_OP_push_object_address, DW_OP_deref) +!4 = !DIExpression(DW_OP_push_object_address, DW_OP_plus_uconst, 32, DW_OP_deref) +!5 = !DISubrange(lowerBound: !1, upperBound: !4 ...) +!6 = !DIExpression(DW_OP_push_object_address, DW_OP_plus_uconst, 56, DW_OP_deref) +!7 = !DISubrange(lowerBound: !1, upperBound: !6, ...) +!8 = !DIBasicType(tag: DW_TAG_base_type, name: "integer" ...) +``` + +In assumed shape case, the rank can be determined from the FIR's `SequenceType`. +This allows us to generate a `DISubrangeAttr` in each dimension. + +#### Assumed Rank + +This is currently unsupported in flang. Its representation will be similar to +array representation for assumed shape array with the following difference. + +1. `DICompositeTypeAttr` will have a rank field which will be an expression. +It will be used to get the rank value from descriptor. +2. Instead of `DISubrangeType` for each dimension, there will be a single +`DIGenericSubrange` which will allow debuggers to calculate bounds in any +dimension. + +### Pointers and Allocatables +The pointer and allocatable will be represented using `DICompositeTypeAttr`. It +is quirk of DWARF that scalar allocatable or pointer variables will show up in +the debug info as pointer to scalar while array pointer or allocatable +variables show up as arrays. The behavior is same in gfortran and classic flang. + +``` + integer, allocatable :: ar(:) + integer, pointer :: sc + +!1 = !DILocalVariable(name: "sc", type: !2) +!2 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !3, associated: !9 ...) +!3 = !DIBasicType(tag: DW_TAG_base_type, name: "integer", ...) +!4 = !DILocalVariable(name: "ar", type: !5 ...) +!5 = !DICompositeType(tag: DW_TAG_array_type, baseType: !3, elements: !6, dataLocation: !8, allocated: !9) +!6 = !{!7} +!7 = !DISubrange(lowerBound: !10, upperBound: !11 ...) +!8 = !DIExpression(DW_OP_push_object_address, DW_OP_deref) +!9 = !DIExpression(DW_OP_push_object_address, DW_OP_deref, DW_OP_lit0, DW_OP_ne) +!10 = !DIExpression(DW_OP_push_object_address, DW_OP_plus_uconst, 24, DW_OP_deref) +!11 = !DIExpression(DW_OP_push_object_address, DW_OP_plus_uconst, 32, DW_OP_deref) + +``` + +IN FIR, these variable are represent as > or +fir.box>. There is also `allocatable` or `pointer` attribute on +the `DeclareOp`. This allows us to generate allocated/associated status of +these variables. The metadata to get the information from the descriptor is +similar to arrays. + +### Strings + +The `DIStringTypeAttr` can represent both fixed size and allocatable strings. For +the allocatable case, the `stringLengthExpression` and `stringLocationExpression` +are used to provide the length and the location of the string respectively. + +``` + character(len=:), allocatable :: var + character(len=20) :: fixed + +!1 = !DILocalVariable(name: "var", type: !2) +!2 = !DIStringType(name: "character(*)", stringLengthExpression: !4, stringLocationExpression: !3 ...) +!3 = !DIExpression(DW_OP_push_object_address, DW_OP_deref) +!4 = !DIExpression(DW_OP_push_object_address, DW_OP_plus_uconst, 8) + +!5 = !DILocalVariable(name: "fixed", type: !6) +!6 = !DIStringType(name: "character (20)", size: 160) + +``` + +### Association + +They will be treated like normal variables. Although we may require to handle +the case where the `DeclareOp` of one variable points to the `DeclareOp` of +another variable (e.g. a => b). + +### Namelists + +FIR does not seem to have a way to extract information about namelists. + +``` +namelist /abc/ x3, y3 + +(gdb) p abc +$1 = ( x3 = 100, y3 = 500 ) +(gdb) p x3 +$2 = 100 +(gdb) p y3 +$3 = 500 +``` + +Even without namelist support, we should be able to see the value of the +individual variables like `x3` and `y3` in the above example. But we would not +be able to evaluate the namelist and have the debugger prints the value of all +the variables in it as shown above for `abc`. + +## Missing metadata in MLIR + +Some metadata types that are needed for fortran are present in LLVM IR but are +absent from MLIR. A non comprehensive list is given below. + +1. `DICommonBlockAttr` +2. `DIGenericSubrangeAttr` +3. `DISubrangeAttr` in MLIR takes IntegerAttr at the moment so only works +with fixed sizes arrays. It needs to also accept `DIExpressionAttr` or +`DILocalVariableAttr` to support assumed shape and adjustable arrays. +4. The `DICompositeTypeAttr` will need to have field for `datalocation`, +`rank`, `allocated` and `associated`. +5. `DIStringTypeAttr` + +# Testing + +- LLVM LIT tests will be added to test: + - the driver and ensure that it passes the line table and full debug + info generation appropriately. + - that the pass works as expected and generates debug info. Test will be + with `fir-opt`. + - with `flang -fc1` that end-to-end debug info generation works. +- Manual external tests will be written to ensure that the following works + in debug tools + - Break at lines. + - Break at functions. + - print type (ptype) of function names. + - print values and types (ptype) of various type of variables +- Manually run `GDB`'s gdb.fortran testsuite with llvm-flang. + +# Resources +- [1] https://dwarfstd.org/doc/DWARF5.pdf +- [2] https://llvm.org/docs/LangRef.html#metadata +- [3] https://archive.fosdem.org/2022/schedule/event/llvm_fortran_debug/ +- [4] https://github.com/llvm/llvm-project/blob/main/mlir/lib/Target/LLVMIR/DebugTranslation.cpp +- [5] https://github.com/llvm/llvm-project/pull/84202 diff --git a/flang/docs/index.md b/flang/docs/index.md index 4a0b145df10b..70478fa0936d 100644 --- a/flang/docs/index.md +++ b/flang/docs/index.md @@ -47,6 +47,7 @@ on how to get in touch with us and to learn more about the current status. Character ComplexOperations ControlFlowGraph + DebugGeneration Directives DoConcurrent Extensions -- GitLab From f135d224a6d078ca3b0722db94e1d772fdbd68ad Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 11 Apr 2024 09:50:41 -0700 Subject: [PATCH 539/695] [SLP][NFC]Add a test with the zext feeding into sitofp instructions. --- .../X86/sitofp-minbitwidth-node.ll | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll new file mode 100644 index 000000000000..00dd9b7e6fb4 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-minbitwidth-node.ll @@ -0,0 +1,57 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=slp-vectorizer -mtriple=x86_64 -mcpu=k8 -mattr=+sse4.1 -S < %s | FileCheck %s + +define void @foo(ptr %ptr) { +; CHECK-LABEL: define void @foo( +; CHECK-SAME: ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 328 +; CHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds i8, ptr [[PTR]], i64 334 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr [[GEP0]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = xor <2 x i16> [[TMP1]], +; CHECK-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double> +; CHECK-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr [[GEP3]], align 2 +; CHECK-NEXT: [[TMP6:%.*]] = zext <2 x i16> [[TMP5]] to <2 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i16> [[TMP1]] to <2 x i32> +; CHECK-NEXT: [[TMP7:%.*]] = sub nsw <2 x i32> [[TMP6]], [[TMP2]] +; CHECK-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double> +; CHECK-NEXT: [[TMP9:%.*]] = fdiv <2 x double> [[TMP4]], [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <2 x double> [[TMP9]], i32 0 +; CHECK-NEXT: [[TMP11:%.*]] = extractelement <2 x double> [[TMP9]], i32 1 +; CHECK-NEXT: [[FCMP:%.*]] = fcmp olt double [[TMP11]], [[TMP10]] +; CHECK-NEXT: ret void +; + %gep0 = getelementptr inbounds i8, ptr %ptr, i64 328 + %gep1 = getelementptr inbounds i8, ptr %ptr, i64 330 + + %gep3 = getelementptr inbounds i8, ptr %ptr, i64 334 + %gep4 = getelementptr inbounds i8, ptr %ptr, i64 336 + + %ld0 = load i16, ptr %gep0, align 8 + %ld1 = load i16, ptr %gep1, align 2 + + %zext0 = zext i16 %ld0 to i32 + %zext1 = zext i16 %ld1 to i32 + + %xor0 = xor i32 %zext0, 65535 + %xor1 = xor i32 %zext1, 65535 + + %sitofp0 = sitofp i32 %xor0 to double + %sitofp1 = sitofp i32 %xor1 to double + + %ld3 = load i16, ptr %gep3, align 2 + %ld4 = load i16, ptr %gep4, align 8 + + %zext3 = zext i16 %ld3 to i32 + %zext4 = zext i16 %ld4 to i32 + + %sub30 = sub nsw i32 %zext3, %zext0 + %sub41 = sub nsw i32 %zext4, %zext1 + + %sitofp30 = sitofp i32 %sub30 to double + %sitofp41 = sitofp i32 %sub41 to double + + %fdiv030 = fdiv double %sitofp0, %sitofp30 + %fdiv141 = fdiv double %sitofp1, %sitofp41 + %fcmp = fcmp olt double %fdiv141, %fdiv030 + ret void +} -- GitLab From 3749e0d43fb56cf22cc72274c287b7bfdda9821d Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 11 Apr 2024 09:54:41 -0700 Subject: [PATCH 540/695] [memprof] Use structured binding (NFC) (#88363) --- llvm/lib/ProfileData/MemProfReader.cpp | 20 +++++++++----------- llvm/tools/llvm-profdata/llvm-profdata.cpp | 4 ++-- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/llvm/lib/ProfileData/MemProfReader.cpp b/llvm/lib/ProfileData/MemProfReader.cpp index 4ccec26597c0..580867a9083f 100644 --- a/llvm/lib/ProfileData/MemProfReader.cpp +++ b/llvm/lib/ProfileData/MemProfReader.cpp @@ -142,13 +142,13 @@ CallStackMap readStackInfo(const char *Ptr) { // any stack ids observed previously map to a different set of program counter // addresses. bool mergeStackMap(const CallStackMap &From, CallStackMap &To) { - for (const auto &IdStack : From) { - auto I = To.find(IdStack.first); + for (const auto &[Id, Stack] : From) { + auto I = To.find(Id); if (I == To.end()) { - To[IdStack.first] = IdStack.second; + To[Id] = Stack; } else { // Check that the PCs are the same (in order). - if (IdStack.second != I->second) + if (Stack != I->second) return true; } } @@ -275,10 +275,10 @@ void RawMemProfReader::printYAML(raw_ostream &OS) { } // Print out the merged contents of the profiles. OS << " Records:\n"; - for (const auto &Entry : *this) { + for (const auto &[GUID, Record] : *this) { OS << " -\n"; - OS << " FunctionGUID: " << Entry.first << "\n"; - Entry.second.print(OS); + OS << " FunctionGUID: " << GUID << "\n"; + Record.print(OS); } } @@ -405,9 +405,7 @@ Error RawMemProfReader::mapRawProfileToRecords() { // Convert the raw profile callstack data into memprof records. While doing so // keep track of related contexts so that we can fill these in later. - for (const auto &Entry : CallstackProfileData) { - const uint64_t StackId = Entry.first; - + for (const auto &[StackId, MIB] : CallstackProfileData) { auto It = StackMap.find(StackId); if (It == StackMap.end()) return make_error( @@ -455,7 +453,7 @@ Error RawMemProfReader::mapRawProfileToRecords() { auto Result = FunctionProfileData.insert({F.Function, IndexedMemProfRecord()}); IndexedMemProfRecord &Record = Result.first->second; - Record.AllocSites.emplace_back(Callstack, CSId, Entry.second); + Record.AllocSites.emplace_back(Callstack, CSId, MIB); if (!F.IsInlineFrame) break; diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index 6a70773613b7..66a4cea03534 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -679,8 +679,8 @@ static void loadInput(const WeightedFile &Input, SymbolRemapper *Remapper, } const auto &FunctionProfileData = Reader->getProfileData(); // Add the memprof records into the writer context. - for (const auto &I : FunctionProfileData) { - WC->Writer.addMemProfRecord(/*Id=*/I.first, /*Record=*/I.second); + for (const auto &[GUID, Record] : FunctionProfileData) { + WC->Writer.addMemProfRecord(GUID, Record); } return; } -- GitLab From db9a17a4075d2ba4cf9edfa90018da6c11908e2a Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 11 Apr 2024 09:56:01 -0700 Subject: [PATCH 541/695] [memprof] Use std::optional (NFC) (#88366) --- llvm/lib/ProfileData/InstrProfReader.cpp | 9 ++++----- llvm/unittests/ProfileData/InstrProfTest.cpp | 9 ++++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp b/llvm/lib/ProfileData/InstrProfReader.cpp index 884334ed070e..a35366a106a3 100644 --- a/llvm/lib/ProfileData/InstrProfReader.cpp +++ b/llvm/lib/ProfileData/InstrProfReader.cpp @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -1506,13 +1507,11 @@ IndexedInstrProfReader::getMemProfRecord(const uint64_t FuncNameHash) { // Setup a callback to convert from frame ids to frame using the on-disk // FrameData hash table. - memprof::FrameId LastUnmappedFrameId = 0; - bool HasFrameMappingError = false; + std::optional LastUnmappedFrameId; auto IdToFrameCallback = [&](const memprof::FrameId Id) { auto FrIter = MemProfFrameTable->find(Id); if (FrIter == MemProfFrameTable->end()) { LastUnmappedFrameId = Id; - HasFrameMappingError = true; return memprof::Frame(0, 0, 0, false); } return *FrIter; @@ -1521,10 +1520,10 @@ IndexedInstrProfReader::getMemProfRecord(const uint64_t FuncNameHash) { memprof::MemProfRecord Record(*Iter, IdToFrameCallback); // Check that all frame ids were successfully converted to frames. - if (HasFrameMappingError) { + if (LastUnmappedFrameId) { return make_error(instrprof_error::hash_mismatch, "memprof frame not found for frame id " + - Twine(LastUnmappedFrameId)); + Twine(*LastUnmappedFrameId)); } return Record; } diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index 732f8fd792f8..82701c47daf7 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -19,6 +19,7 @@ #include "llvm/Testing/Support/Error.h" #include "gtest/gtest.h" #include +#include using namespace llvm; using ::testing::EndsWith; @@ -433,21 +434,19 @@ TEST_F(InstrProfTest, test_memprof) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - memprof::FrameId LastUnmappedFrameId = 0; - bool HasFrameMappingError = false; + std::optional LastUnmappedFrameId; auto IdToFrameCallback = [&](const memprof::FrameId Id) { auto Iter = IdToFrameMap.find(Id); if (Iter == IdToFrameMap.end()) { LastUnmappedFrameId = Id; - HasFrameMappingError = true; return memprof::Frame(0, 0, 0, false); } return Iter->second; }; const memprof::MemProfRecord WantRecord(IndexedMR, IdToFrameCallback); - ASSERT_FALSE(HasFrameMappingError) - << "could not map frame id: " << LastUnmappedFrameId; + ASSERT_FALSE(LastUnmappedFrameId.has_value()) + << "could not map frame id: " << *LastUnmappedFrameId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } -- GitLab From 8c3cb6b55b688b767e5d65bcc2891b17322e8d05 Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Thu, 11 Apr 2024 09:56:22 -0700 Subject: [PATCH 542/695] =?UTF-8?q?Reland=20"[lldb][sbdebugger]=20Move=20S?= =?UTF-8?q?BDebugger=20Broadcast=20bit=20enum=20into=20ll=E2=80=A6=20(#883?= =?UTF-8?q?31)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …db-enumerations.h" (#88324)" This reverts commit 9f6d08f2566a26144ea1753f80aebb1f2ecfdc63. This broke the build because of a usage of one of the original SBDebugger broadcast bits that wasn't updated in the original commit. --- lldb/include/lldb/API/SBDebugger.h | 7 ------- lldb/include/lldb/lldb-enumerations.h | 8 ++++++++ .../diagnostic_reporting/TestDiagnosticReporting.py | 2 +- .../progress_reporting/TestProgressReporting.py | 2 +- .../clang_modules/TestClangModuleBuildProgress.py | 2 +- lldb/test/API/macosx/rosetta/TestRosetta.py | 2 +- lldb/tools/lldb-dap/lldb-dap.cpp | 4 ++-- 7 files changed, 14 insertions(+), 13 deletions(-) diff --git a/lldb/include/lldb/API/SBDebugger.h b/lldb/include/lldb/API/SBDebugger.h index 62b2f91f5076..cf5409a12a05 100644 --- a/lldb/include/lldb/API/SBDebugger.h +++ b/lldb/include/lldb/API/SBDebugger.h @@ -42,13 +42,6 @@ public: class LLDB_API SBDebugger { public: - FLAGS_ANONYMOUS_ENUM(){ - eBroadcastBitProgress = (1 << 0), - eBroadcastBitWarning = (1 << 1), - eBroadcastBitError = (1 << 2), - eBroadcastBitProgressCategory = (1 << 3), - }; - SBDebugger(); SBDebugger(const lldb::SBDebugger &rhs); diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index 646f7bfda984..f3b07ea6d203 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -1339,6 +1339,14 @@ enum AddressMaskRange { eAddressMaskRangeAll = eAddressMaskRangeAny, }; +/// Used by the debugger to indicate which events are being broadcasted. +enum DebuggerBroadcastBit { + eBroadcastBitProgress = (1 << 0), + eBroadcastBitWarning = (1 << 1), + eBroadcastBitError = (1 << 2), + eBroadcastBitProgressCategory = (1 << 3), +}; + } // namespace lldb #endif // LLDB_LLDB_ENUMERATIONS_H diff --git a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py index 36a3be695628..6353e3e8cbed 100644 --- a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py +++ b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py @@ -15,7 +15,7 @@ class TestDiagnosticReporting(TestBase): self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( self.broadcaster, - lldb.SBDebugger.eBroadcastBitWarning | lldb.SBDebugger.eBroadcastBitError, + lldb.eBroadcastBitWarning | lldb.eBroadcastBitError, ) def test_dwarf_symbol_loading_diagnostic_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py index 9af53845ca1b..98988d7624da 100644 --- a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py +++ b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py @@ -13,7 +13,7 @@ class TestProgressReporting(TestBase): TestBase.setUp(self) self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( - self.broadcaster, lldb.SBDebugger.eBroadcastBitProgress + self.broadcaster, lldb.eBroadcastBitProgress ) def test_dwarf_symbol_loading_progress_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py index 228f676aedf6..33c7c269c081 100644 --- a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py +++ b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py @@ -34,7 +34,7 @@ class TestCase(TestBase): # other unrelated progress events. broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.SBDebugger.eBroadcastBitProgress + broadcaster, lldb.eBroadcastBitProgress ) # Trigger module builds. diff --git a/lldb/test/API/macosx/rosetta/TestRosetta.py b/lldb/test/API/macosx/rosetta/TestRosetta.py index ce40de475ef1..669db95a1624 100644 --- a/lldb/test/API/macosx/rosetta/TestRosetta.py +++ b/lldb/test/API/macosx/rosetta/TestRosetta.py @@ -49,7 +49,7 @@ class TestRosetta(TestBase): if rosetta_debugserver_installed(): broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.SBDebugger.eBroadcastBitWarning + broadcaster, lldb.eBroadcastBitWarning ) target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( diff --git a/lldb/tools/lldb-dap/lldb-dap.cpp b/lldb/tools/lldb-dap/lldb-dap.cpp index 55f8c920e600..25c5ad56e3d6 100644 --- a/lldb/tools/lldb-dap/lldb-dap.cpp +++ b/lldb/tools/lldb-dap/lldb-dap.cpp @@ -420,8 +420,8 @@ void SendStdOutStdErr(lldb::SBProcess &process) { void ProgressEventThreadFunction() { lldb::SBListener listener("lldb-dap.progress.listener"); - g_dap.debugger.GetBroadcaster().AddListener( - listener, lldb::SBDebugger::eBroadcastBitProgress); + g_dap.debugger.GetBroadcaster().AddListener(listener, + lldb::eBroadcastBitProgress); g_dap.broadcaster.AddListener(listener, eBroadcastBitStopProgressThread); lldb::SBEvent event; bool done = false; -- GitLab From 2ea7ec9737e3ca4e2ce23bf606e79e7066beae0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 11 Apr 2024 10:03:29 +0200 Subject: [PATCH 543/695] [clang][Interp][NFC] Expand pointer unittests Test integral pointers as well. --- clang/unittests/AST/Interp/toAPValue.cpp | 56 +++++++++++++++++++----- 1 file changed, 46 insertions(+), 10 deletions(-) diff --git a/clang/unittests/AST/Interp/toAPValue.cpp b/clang/unittests/AST/Interp/toAPValue.cpp index d0dfb40d5149..be7929228d28 100644 --- a/clang/unittests/AST/Interp/toAPValue.cpp +++ b/clang/unittests/AST/Interp/toAPValue.cpp @@ -20,7 +20,9 @@ TEST(ToAPValue, Pointers) { " A a[3];\n" "};\n" "constexpr S d = {{{true, false}, {false, true}, {false, false}}};\n" - "constexpr const bool *b = &d.a[1].z;\n"; + "constexpr const bool *b = &d.a[1].z;\n" + "const void *p = (void*)12;\n" + "const void *nullp = (void*)0;\n"; auto AST = tooling::buildASTFromCodeWithArgs( Code, {"-fexperimental-new-constant-interpreter"}); @@ -41,15 +43,49 @@ TEST(ToAPValue, Pointers) { return Prog.getPtrGlobal(*Prog.getGlobal(D)); }; - const Pointer &GP = getGlobalPtr("b"); - const Pointer &P = GP.deref(); - ASSERT_TRUE(P.isLive()); - APValue A = P.toAPValue(); - ASSERT_TRUE(A.isLValue()); - ASSERT_TRUE(A.hasLValuePath()); - const auto &Path = A.getLValuePath(); - ASSERT_EQ(Path.size(), 3u); - ASSERT_EQ(A.getLValueBase(), getDecl("d")); + { + const Pointer &GP = getGlobalPtr("b"); + const Pointer &P = GP.deref(); + ASSERT_TRUE(P.isLive()); + APValue A = P.toAPValue(); + ASSERT_TRUE(A.isLValue()); + ASSERT_TRUE(A.hasLValuePath()); + const auto &Path = A.getLValuePath(); + ASSERT_EQ(Path.size(), 3u); + ASSERT_EQ(A.getLValueBase(), getDecl("d")); + // FIXME: Also test all path elements. + } + + { + const ValueDecl *D = getDecl("p"); + ASSERT_NE(D, nullptr); + const Pointer &GP = getGlobalPtr("p"); + const Pointer &P = GP.deref(); + ASSERT_TRUE(P.isIntegralPointer()); + APValue A = P.toAPValue(); + ASSERT_TRUE(A.isLValue()); + ASSERT_TRUE(A.getLValueBase().isNull()); + APSInt I; + bool Success = A.toIntegralConstant(I, D->getType(), AST->getASTContext()); + ASSERT_TRUE(Success); + ASSERT_EQ(I, 12); + } + + { + const ValueDecl *D = getDecl("nullp"); + ASSERT_NE(D, nullptr); + const Pointer &GP = getGlobalPtr("nullp"); + const Pointer &P = GP.deref(); + ASSERT_TRUE(P.isIntegralPointer()); + APValue A = P.toAPValue(); + ASSERT_TRUE(A.isLValue()); + ASSERT_TRUE(A.getLValueBase().isNull()); + ASSERT_TRUE(A.isNullPointer()); + APSInt I; + bool Success = A.toIntegralConstant(I, D->getType(), AST->getASTContext()); + ASSERT_TRUE(Success); + ASSERT_EQ(I, 0); + } } TEST(ToAPValue, FunctionPointers) { -- GitLab From 64c3997939cf2d9b4fd1c24c89724d0b47afcd03 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 11 Apr 2024 17:53:57 +0200 Subject: [PATCH 544/695] [clang][Interp] Allow initializing static class members We need to handle this when registering global variables. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 34 ++++---- clang/lib/AST/Interp/Interp.cpp | 99 +++++++++++++++--------- clang/lib/AST/Interp/Program.cpp | 2 +- clang/test/AST/Interp/cxx23.cpp | 17 ++-- clang/test/AST/Interp/records.cpp | 32 +++++++- 5 files changed, 118 insertions(+), 66 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 84bacd457c85..01ec31e4077f 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -2778,26 +2778,34 @@ bool ByteCodeExprGen::visitVarDecl(const VarDecl *VD) { std::optional VarT = classify(VD->getType()); if (Context::shouldBeGloballyIndexed(VD)) { - // We've already seen and initialized this global. - if (P.getGlobal(VD)) - return true; - - std::optional GlobalIndex = P.createGlobal(VD, Init); - - if (!GlobalIndex) - return false; - - if (Init) { + auto initGlobal = [&](unsigned GlobalIndex) -> bool { + assert(Init); DeclScope LocalScope(this, VD); if (VarT) { if (!this->visit(Init)) return false; - return this->emitInitGlobal(*VarT, *GlobalIndex, VD); + return this->emitInitGlobal(*VarT, GlobalIndex, VD); } - return this->visitGlobalInitializer(Init, *GlobalIndex); + return this->visitGlobalInitializer(Init, GlobalIndex); + }; + + // We've already seen and initialized this global. + if (std::optional GlobalIndex = P.getGlobal(VD)) { + if (P.getPtrGlobal(*GlobalIndex).isInitialized()) + return true; + + // The previous attempt at initialization might've been unsuccessful, + // so let's try this one. + return Init && initGlobal(*GlobalIndex); } - return true; + + std::optional GlobalIndex = P.createGlobal(VD, Init); + + if (!GlobalIndex) + return false; + + return !Init || initGlobal(*GlobalIndex); } else { VariableScope LocalScope(this); if (VarT) { diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index e5e2c932f500..2607e0743251 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -56,22 +56,65 @@ static bool Jf(InterpState &S, CodePtr &PC, int32_t Offset) { return true; } +static void diagnoseMissingInitializer(InterpState &S, CodePtr OpPC, + const ValueDecl *VD) { + const SourceInfo &E = S.Current->getSource(OpPC); + S.FFDiag(E, diag::note_constexpr_var_init_unknown, 1) << VD; + S.Note(VD->getLocation(), diag::note_declared_at) << VD->getSourceRange(); +} + +static void diagnoseNonConstVariable(InterpState &S, CodePtr OpPC, + const ValueDecl *VD); +static bool diagnoseUnknownDecl(InterpState &S, CodePtr OpPC, + const ValueDecl *D) { + const SourceInfo &E = S.Current->getSource(OpPC); + + if (isa(D)) { + if (S.getLangOpts().CPlusPlus11) { + S.FFDiag(E, diag::note_constexpr_function_param_value_unknown) << D; + S.Note(D->getLocation(), diag::note_declared_at) << D->getSourceRange(); + } else { + S.FFDiag(E); + } + } else if (const auto *VD = dyn_cast(D)) { + if (!VD->getType().isConstQualified()) { + diagnoseNonConstVariable(S, OpPC, VD); + return false; + } + + // const, but no initializer. + if (!VD->getAnyInitializer()) { + diagnoseMissingInitializer(S, OpPC, VD); + return false; + } + } + return false; +} + static void diagnoseNonConstVariable(InterpState &S, CodePtr OpPC, const ValueDecl *VD) { if (!S.getLangOpts().CPlusPlus) return; const SourceInfo &Loc = S.Current->getSource(OpPC); + if (const auto *VarD = dyn_cast(VD); + VarD && VarD->getType().isConstQualified() && + !VarD->getAnyInitializer()) { + diagnoseMissingInitializer(S, OpPC, VD); + return; + } - if (VD->getType()->isIntegralOrEnumerationType()) + if (VD->getType()->isIntegralOrEnumerationType()) { S.FFDiag(Loc, diag::note_constexpr_ltor_non_const_int, 1) << VD; - else - S.FFDiag(Loc, - S.getLangOpts().CPlusPlus11 - ? diag::note_constexpr_ltor_non_constexpr - : diag::note_constexpr_ltor_non_integral, - 1) - << VD << VD->getType(); + S.Note(VD->getLocation(), diag::note_declared_at); + return; + } + + S.FFDiag(Loc, + S.getLangOpts().CPlusPlus11 ? diag::note_constexpr_ltor_non_constexpr + : diag::note_constexpr_ltor_non_integral, + 1) + << VD << VD->getType(); S.Note(VD->getLocation(), diag::note_declared_at); } @@ -202,6 +245,9 @@ bool CheckExtern(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { if (!Ptr.isExtern()) return true; + if (Ptr.isInitialized()) + return true; + if (!S.checkingPotentialConstantExpression() && S.getLangOpts().CPlusPlus) { const auto *VD = Ptr.getDeclDesc()->asValueDecl(); diagnoseNonConstVariable(S, OpPC, VD); @@ -369,9 +415,15 @@ bool CheckInitialized(InterpState &S, CodePtr OpPC, const Pointer &Ptr, if (const auto *VD = Ptr.getDeclDesc()->asVarDecl(); VD && VD->hasGlobalStorage()) { const SourceInfo &Loc = S.Current->getSource(OpPC); - S.FFDiag(Loc, diag::note_constexpr_var_init_non_constant, 1) << VD; - S.Note(VD->getLocation(), diag::note_declared_at); + if (VD->getAnyInitializer()) { + S.FFDiag(Loc, diag::note_constexpr_var_init_non_constant, 1) << VD; + S.Note(VD->getLocation(), diag::note_declared_at); + } else { + diagnoseMissingInitializer(S, OpPC, VD); + } + return false; } + if (!S.checkingPotentialConstantExpression()) { S.FFDiag(S.Current->getSource(OpPC), diag::note_constexpr_access_uninit) << AK << /*uninitialized=*/true << S.Current->getRange(OpPC); @@ -598,33 +650,6 @@ bool CheckFloatResult(InterpState &S, CodePtr OpPC, const Floating &Result, return true; } -static bool diagnoseUnknownDecl(InterpState &S, CodePtr OpPC, - const ValueDecl *D) { - const SourceInfo &E = S.Current->getSource(OpPC); - - if (isa(D)) { - if (S.getLangOpts().CPlusPlus11) { - S.FFDiag(E, diag::note_constexpr_function_param_value_unknown) << D; - S.Note(D->getLocation(), diag::note_declared_at) << D->getSourceRange(); - } else { - S.FFDiag(E); - } - } else if (const auto *VD = dyn_cast(D)) { - if (!VD->getType().isConstQualified()) { - diagnoseNonConstVariable(S, OpPC, VD); - return false; - } - - // const, but no initializer. - if (!VD->getAnyInitializer()) { - S.FFDiag(E, diag::note_constexpr_var_init_unknown, 1) << VD; - S.Note(VD->getLocation(), diag::note_declared_at) << VD->getSourceRange(); - return false; - } - } - return false; -} - /// We aleady know the given DeclRefExpr is invalid for some reason, /// now figure out why and print appropriate diagnostics. bool CheckDeclRef(InterpState &S, CodePtr OpPC, const DeclRefExpr *DR) { diff --git a/clang/lib/AST/Interp/Program.cpp b/clang/lib/AST/Interp/Program.cpp index 82367164743f..e6f22e79451e 100644 --- a/clang/lib/AST/Interp/Program.cpp +++ b/clang/lib/AST/Interp/Program.cpp @@ -177,7 +177,7 @@ std::optional Program::createGlobal(const ValueDecl *VD, bool IsStatic, IsExtern; if (const auto *Var = dyn_cast(VD)) { IsStatic = Context::shouldBeGloballyIndexed(VD); - IsExtern = !Var->getAnyInitializer(); + IsExtern = Var->hasExternalStorage(); } else if (isa(VD)) { IsStatic = true; IsExtern = false; diff --git a/clang/test/AST/Interp/cxx23.cpp b/clang/test/AST/Interp/cxx23.cpp index 042e29613aa7..f0325eef6d87 100644 --- a/clang/test/AST/Interp/cxx23.cpp +++ b/clang/test/AST/Interp/cxx23.cpp @@ -5,23 +5,18 @@ /// FIXME: The new interpreter is missing all the 'control flows through...' diagnostics. -constexpr int f(int n) { // ref20-error {{constexpr function never produces a constant expression}} \ - // expected20-error {{constexpr function never produces a constant expression}} +constexpr int f(int n) { // ref20-error {{constexpr function never produces a constant expression}} static const int m = n; // ref20-note {{control flows through the definition of a static variable}} \ // ref20-warning {{is a C++23 extension}} \ - // expected20-warning {{is a C++23 extension}} \ - // expected20-note {{declared here}} \ + // expected20-warning {{is a C++23 extension}} - return m; // expected20-note {{initializer of 'm' is not a constant expression}} + return m; } -constexpr int g(int n) { // ref20-error {{constexpr function never produces a constant expression}} \ - // expected20-error {{constexpr function never produces a constant expression}} +constexpr int g(int n) { // ref20-error {{constexpr function never produces a constant expression}} thread_local const int m = n; // ref20-note {{control flows through the definition of a thread_local variable}} \ // ref20-warning {{is a C++23 extension}} \ - // expected20-warning {{is a C++23 extension}} \ - // expected20-note {{declared here}} - return m; // expected20-note {{initializer of 'm' is not a constant expression}} - + // expected20-warning {{is a C++23 extension}} + return m; } constexpr int c_thread_local(int n) { // ref20-error {{constexpr function never produces a constant expression}} \ diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index 0f76e0cfe992..f251497ed701 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -1,11 +1,11 @@ -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify=expected,both %s // RUN: %clang_cc1 -fexperimental-new-constant-interpreter -std=c++14 -verify=expected,both %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -std=c++17 -verify=expected,both %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -std=c++17 -triple i686 -verify=expected,both %s // RUN: %clang_cc1 -fexperimental-new-constant-interpreter -std=c++20 -verify=expected,both %s -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -triple i686 -verify=expected,both %s -// RUN: %clang_cc1 -verify=ref,both %s // RUN: %clang_cc1 -verify=ref,both -std=c++14 %s +// RUN: %clang_cc1 -verify=ref,both -std=c++17 %s +// RUN: %clang_cc1 -verify=ref,both -std=c++17 -triple i686 %s // RUN: %clang_cc1 -verify=ref,both -std=c++20 %s -// RUN: %clang_cc1 -verify=ref,both -triple i686 %s /// Used to crash. struct Empty {}; @@ -1285,3 +1285,27 @@ namespace { } } #endif + +namespace pr18633 { + struct A1 { + static const int sz; + static const int sz2; + }; + const int A1::sz2 = 11; + template + void func () { + int arr[A1::sz]; + // both-warning@-1 {{variable length arrays in C++ are a Clang extension}} + // both-note@-2 {{initializer of 'sz' is unknown}} + // both-note@-9 {{declared here}} + } + template + void func2 () { + int arr[A1::sz2]; + } + const int A1::sz = 12; + void func2() { + func(); + func2(); + } +} -- GitLab From 5122a2c2320c7b14f6585e63b7fc43ac82a550c2 Mon Sep 17 00:00:00 2001 From: Aart Bik Date: Thu, 11 Apr 2024 10:07:24 -0700 Subject: [PATCH 545/695] [mlir][sparse] allow for direct-out passing of sparse tensor buffers (#88327) In order to support various external frameworks (JAX vs PyTorch) we need a bit more flexibility in [dis]assembling external buffers to and from sparse tensors in MLIR land. This PR adds a direct-out option that avoids the rigid pre-allocated for copy-out semantics. Note that over time, we expect the [dis]assemble operations to converge into something that supports all sorts of external frameworks. Until then, this option helps in experimenting with different options. --- .../Dialect/SparseTensor/Transforms/Passes.h | 3 +- .../Dialect/SparseTensor/Transforms/Passes.td | 9 ++ .../Transforms/SparseAssembler.cpp | 87 ++++++++++++------- .../Transforms/SparseTensorConversion.cpp | 9 +- .../Transforms/SparseTensorPasses.cpp | 3 +- .../Dialect/SparseTensor/external_direct.mlir | 52 +++++++++++ 6 files changed, 125 insertions(+), 38 deletions(-) create mode 100644 mlir/test/Dialect/SparseTensor/external_direct.mlir diff --git a/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h b/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h index 61b07d222d15..d6d038ef65bd 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h +++ b/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h @@ -60,9 +60,10 @@ enum class SparseEmitStrategy { // The SparseAssembler pass. //===----------------------------------------------------------------------===// -void populateSparseAssembler(RewritePatternSet &patterns); +void populateSparseAssembler(RewritePatternSet &patterns, bool directOut); std::unique_ptr createSparseAssembler(); +std::unique_ptr createSparseAssembler(bool directOut); //===----------------------------------------------------------------------===// // The SparseReinterpretMap pass. diff --git a/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td b/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td index 58e2d6f32386..4706d5ba2f21 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td @@ -23,12 +23,21 @@ def SparseAssembler : Pass<"sparse-assembler", "ModuleOp"> { sparse tensors as numpy arrays from and to Python. Note that eventual bufferization decisions (e.g. who [de]allocates the underlying memory) should be resolved in agreement with the external runtime. + + By default, the pass uses the [dis]assemble operations to input and output + sparse tensors. When the direct-out option is set, however, the output + directly returns the MLIR allocated buffers to the external runtime. }]; let constructor = "mlir::createSparseAssembler()"; let dependentDialects = [ + "bufferization::BufferizationDialect", "sparse_tensor::SparseTensorDialect", "tensor::TensorDialect", ]; + let options = [ + Option<"directOut", "direct-out", "bool", + "false", "Directly returns buffers externally">, + ]; } def SparseReinterpretMap : Pass<"sparse-reinterpret-map", "ModuleOp"> { diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp index a91d32a23cac..eafbe95b7aeb 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp @@ -8,6 +8,7 @@ #include "Utils/CodegenUtils.h" +#include "mlir/Dialect/Bufferization/IR/Bufferization.h" #include "mlir/Dialect/SparseTensor/IR/SparseTensor.h" #include "mlir/Dialect/SparseTensor/IR/SparseTensorStorageLayout.h" #include "mlir/Dialect/SparseTensor/IR/SparseTensorType.h" @@ -24,7 +25,7 @@ using namespace sparse_tensor; // Convert type range to new types range, with sparse tensors externalized. static void convTypes(TypeRange types, SmallVectorImpl &convTypes, - SmallVectorImpl *extraTypes = nullptr) { + SmallVectorImpl *extraTypes, bool directOut) { for (auto type : types) { // All "dense" data passes through unmodified. if (!getSparseTensorEncoding(type)) { @@ -32,31 +33,33 @@ static void convTypes(TypeRange types, SmallVectorImpl &convTypes, continue; } - // Convert the external representation of the position/coordinate array + // Convert the external representations of the pos/crd/val arrays. const SparseTensorType stt(cast(type)); - foreachFieldAndTypeInSparseTensor(stt, [&convTypes, extraTypes]( - Type t, FieldIndex, - SparseTensorFieldKind kind, - Level, LevelType) { - if (kind == SparseTensorFieldKind::CrdMemRef || - kind == SparseTensorFieldKind::PosMemRef || - kind == SparseTensorFieldKind::ValMemRef) { - ShapedType st = t.cast(); - auto rtp = RankedTensorType::get(st.getShape(), st.getElementType()); - convTypes.push_back(rtp); - if (extraTypes) - extraTypes->push_back(rtp); - } - return true; - }); + foreachFieldAndTypeInSparseTensor( + stt, [&convTypes, extraTypes, directOut](Type t, FieldIndex, + SparseTensorFieldKind kind, + Level, LevelType) { + if (kind == SparseTensorFieldKind::PosMemRef || + kind == SparseTensorFieldKind::CrdMemRef || + kind == SparseTensorFieldKind::ValMemRef) { + auto rtp = t.cast(); + if (!directOut) { + rtp = RankedTensorType::get(rtp.getShape(), rtp.getElementType()); + if (extraTypes) + extraTypes->push_back(rtp); + } + convTypes.push_back(rtp); + } + return true; + }); } } // Convert input and output values to [dis]assemble ops for sparse tensors. static void convVals(OpBuilder &builder, Location loc, TypeRange types, ValueRange fromVals, ValueRange extraVals, - SmallVectorImpl &toVals, unsigned extra, - bool isIn) { + SmallVectorImpl &toVals, unsigned extra, bool isIn, + bool directOut) { unsigned idx = 0; for (auto type : types) { // All "dense" data passes through unmodified. @@ -73,18 +76,29 @@ static void convVals(OpBuilder &builder, Location loc, TypeRange types, if (!isIn) inputs.push_back(fromVals[idx++]); // The sparse tensor to disassemble - // Collect the external representations of the pos/crd arrays. + // Collect the external representations of the pos/crd/val arrays. foreachFieldAndTypeInSparseTensor(stt, [&, isIn](Type t, FieldIndex, SparseTensorFieldKind kind, - Level, LevelType) { - if (kind == SparseTensorFieldKind::CrdMemRef || - kind == SparseTensorFieldKind::PosMemRef || + Level lv, LevelType) { + if (kind == SparseTensorFieldKind::PosMemRef || + kind == SparseTensorFieldKind::CrdMemRef || kind == SparseTensorFieldKind::ValMemRef) { if (isIn) { inputs.push_back(fromVals[idx++]); + } else if (directOut) { + Value mem; + if (kind == SparseTensorFieldKind::PosMemRef) + mem = builder.create(loc, inputs[0], + lv); + else if (kind == SparseTensorFieldKind::CrdMemRef) + mem = builder.create(loc, inputs[0], + lv); + else + mem = builder.create(loc, inputs[0]); + toVals.push_back(mem); } else { - ShapedType st = t.cast(); - auto rtp = RankedTensorType::get(st.getShape(), st.getElementType()); + ShapedType rtp = t.cast(); + rtp = RankedTensorType::get(rtp.getShape(), rtp.getElementType()); inputs.push_back(extraVals[extra++]); retTypes.push_back(rtp); cntTypes.push_back(builder.getIndexType()); @@ -97,7 +111,7 @@ static void convVals(OpBuilder &builder, Location loc, TypeRange types, // Assemble multiple inputs into a single sparse tensor. auto a = builder.create(loc, rtp, inputs); toVals.push_back(a.getResult()); - } else { + } else if (!directOut) { // Disassemble a single sparse input into multiple outputs. // Note that this includes the counters, which are dropped. unsigned len = retTypes.size(); @@ -144,11 +158,14 @@ namespace { // return ..., t1..tn, ... // } // -// TODO: refine output sparse tensors to work well with external framework +// (with a direct-out variant without the disassemble). // struct SparseFuncAssembler : public OpRewritePattern { using OpRewritePattern::OpRewritePattern; + SparseFuncAssembler(MLIRContext *context, bool dO) + : OpRewritePattern(context), directOut(dO) {} + LogicalResult matchAndRewrite(func::FuncOp funcOp, PatternRewriter &rewriter) const override { // Only rewrite public entry methods. @@ -159,8 +176,8 @@ struct SparseFuncAssembler : public OpRewritePattern { SmallVector inputTypes; SmallVector outputTypes; SmallVector extraTypes; - convTypes(funcOp.getArgumentTypes(), inputTypes); - convTypes(funcOp.getResultTypes(), outputTypes, &extraTypes); + convTypes(funcOp.getArgumentTypes(), inputTypes, nullptr, false); + convTypes(funcOp.getResultTypes(), outputTypes, &extraTypes, directOut); // Only sparse inputs or outputs need a wrapper method. if (inputTypes.size() == funcOp.getArgumentTypes().size() && @@ -192,7 +209,7 @@ struct SparseFuncAssembler : public OpRewritePattern { // Convert inputs. SmallVector inputs; convVals(rewriter, loc, funcOp.getArgumentTypes(), body->getArguments(), - ValueRange(), inputs, 0, /*isIn=*/true); + ValueRange(), inputs, /*extra=*/0, /*isIn=*/true, directOut); // Call the original, now private method. A subsequent inlining pass can // determine whether cloning the method body in place is worthwhile. @@ -203,7 +220,7 @@ struct SparseFuncAssembler : public OpRewritePattern { // Convert outputs and return. SmallVector outputs; convVals(rewriter, loc, funcOp.getResultTypes(), call.getResults(), - body->getArguments(), outputs, extra, /*isIn=*/false); + body->getArguments(), outputs, extra, /*isIn=*/false, directOut); rewriter.create(loc, outputs); // Finally, migrate a potential c-interface property. @@ -215,6 +232,9 @@ struct SparseFuncAssembler : public OpRewritePattern { } return success(); } + +private: + const bool directOut; }; } // namespace @@ -223,6 +243,7 @@ struct SparseFuncAssembler : public OpRewritePattern { // Public method for populating conversion rules. //===----------------------------------------------------------------------===// -void mlir::populateSparseAssembler(RewritePatternSet &patterns) { - patterns.add(patterns.getContext()); +void mlir::populateSparseAssembler(RewritePatternSet &patterns, + bool directOut) { + patterns.add(patterns.getContext(), directOut); } diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp index c52fa3751e6b..f0d162bdb84d 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorConversion.cpp @@ -767,6 +767,12 @@ public: }; /// Sparse conversion rule for the sparse_tensor.disassemble operator. +/// Note that the current implementation simply exposes the buffers to +/// the external client. This assumes the client only reads the buffers +/// (usually copying it to the external data structures, such as numpy +/// arrays). The semantics of the disassemble operation technically +/// require that the copying is done here already using the out-levels +/// and out-values clause. class SparseTensorDisassembleConverter : public OpConversionPattern { public: @@ -774,9 +780,6 @@ public: LogicalResult matchAndRewrite(DisassembleOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const override { - // We simply expose the buffers to the external client. This - // assumes the client only reads the buffers (usually copying it - // to the external data structures, such as numpy arrays). Location loc = op->getLoc(); auto stt = getSparseTensorType(op.getTensor()); SmallVector retVal; diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp index acea25f02398..b42d58634a36 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp @@ -50,11 +50,12 @@ namespace { struct SparseAssembler : public impl::SparseAssemblerBase { SparseAssembler() = default; SparseAssembler(const SparseAssembler &pass) = default; + SparseAssembler(bool dO) { directOut = dO; } void runOnOperation() override { auto *ctx = &getContext(); RewritePatternSet patterns(ctx); - populateSparseAssembler(patterns); + populateSparseAssembler(patterns, directOut); (void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns)); } }; diff --git a/mlir/test/Dialect/SparseTensor/external_direct.mlir b/mlir/test/Dialect/SparseTensor/external_direct.mlir new file mode 100644 index 000000000000..78c4a295686b --- /dev/null +++ b/mlir/test/Dialect/SparseTensor/external_direct.mlir @@ -0,0 +1,52 @@ +// RUN: mlir-opt %s --sparse-assembler="direct-out=True" -split-input-file | FileCheck %s + +// ----- + +// CHECK-LABEL: func.func @sparse_in( +// CHECK-SAME: %[[B:.*0]]: tensor, +// CHECK-SAME: %[[C:.*1]]: tensor, +// CHECK-SAME: %[[A:.*]]: tensor) -> tensor<64x64xf32> { +// CHECK: %[[I:.*]] = sparse_tensor.assemble (%[[B]], %[[C]]), %[[A]] +// CHECK: %[[F:.*]] = call @_internal_sparse_in(%[[I]]) +// CHECK: return %[[F]] : tensor<64x64xf32> +// CHECK: } +// CHECK: func.func private @_internal_sparse_in +#sparse = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed) }> +func.func @sparse_in(%arg0: tensor<64x64xf32, #sparse>) -> tensor<64x64xf32> { + %0 = sparse_tensor.convert %arg0 : tensor<64x64xf32, #sparse> to tensor<64x64xf32> + return %0 : tensor<64x64xf32> +} + +// ----- + +// CHECK-LABEL: func.func @sparse_out( +// CHECK-SAME: %[[X:.*0]]: tensor<64x64xf32>) +// CHECK: %[[F:.*]] = call @_internal_sparse_out(%[[X]]) +// CHECK: %[[P:.*]] = sparse_tensor.positions %[[F]] +// CHECK: %[[C:.*]] = sparse_tensor.coordinates %[[F]] +// CHECK: %[[V:.*]] = sparse_tensor.values %[[F]] +// CHECK: return %[[P]], %[[C]], %[[V]] +// CHECK: } +// CHECK: func.func private @_internal_sparse_out +#sparse = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed) }> +func.func @sparse_out(%arg0: tensor<64x64xf32>) -> tensor<64x64xf32, #sparse> { + %0 = sparse_tensor.convert %arg0 : tensor<64x64xf32> to tensor<64x64xf32, #sparse> + return %0 : tensor<64x64xf32, #sparse> +} + +// ----- + +// CHECK-LABEL: func.func @sparse_out2( +// CHECK-SAME: %[[X:.*0]]: tensor<64x64xf32>) +// CHECK: %[[F:.*]]:2 = call @_internal_sparse_out2(%[[X]]) +// CHECK: %[[P:.*]] = sparse_tensor.positions %[[F]]#1 +// CHECK: %[[C:.*]] = sparse_tensor.coordinates %[[F]]#1 +// CHECK: %[[V:.*]] = sparse_tensor.values %[[F]]#1 +// CHECK: return %[[F]]#0, %[[P]], %[[C]], %[[V]] +// CHECK: } +// CHECK: func.func private @_internal_sparse_out2 +#sparse = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed) }> +func.func @sparse_out2(%arg0: tensor<64x64xf32>) -> (tensor<64x64xf32>, tensor<64x64xf32, #sparse>) { + %0 = sparse_tensor.convert %arg0 : tensor<64x64xf32> to tensor<64x64xf32, #sparse> + return %arg0, %0 : tensor<64x64xf32>, tensor<64x64xf32, #sparse> +} -- GitLab From f626a35086d90f25986e3f06e01a54cca91250d8 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Thu, 11 Apr 2024 10:11:58 -0700 Subject: [PATCH 546/695] [libc] Codify header inclusion policy (#87017) When supporting "overlay" vs "fullbuild" modes, "what ABI are you using?" becomes a fundamental question to have concrete answers for. Overlay mode MUST match the ABI of the system being overlayed onto; fullbuild more flexible (the only system ABI relevant is the OS kernel). When implementing llvm-libc we generally prefer the include-what-you use style of avoiding transitive dependencies (since that makes refactoring headers more painful, and slows down build times). So what header do you include for any given type or function declaration? For any given userspace program, the answer is straightforward. But for llvm-libc which is trying to support multiple ABIs (at least one per configuration), the answer is perhaps less clear. This proposal seeks to add one layer of indirection relative to what's being done today. It then converts users of sigset_t and struct epoll_event and the epoll implemenations over to this convention as an example. --- libc/docs/dev/code_style.rst | 33 +++++++++++++++++++ libc/docs/usage_modes.rst | 6 +++- libc/hdr/CMakeLists.txt | 2 ++ libc/hdr/types/CMakeLists.txt | 23 +++++++++++++ libc/hdr/types/sigset_t.h | 21 ++++++++++++ libc/hdr/types/struct_epoll_event.h | 21 ++++++++++++ libc/hdr/types/struct_timespec.h | 21 ++++++++++++ libc/src/signal/linux/CMakeLists.txt | 16 +++++---- libc/src/signal/linux/raise.cpp | 5 +-- libc/src/signal/linux/sigaction.cpp | 7 ++-- libc/src/signal/linux/sigaddset.cpp | 4 +-- libc/src/signal/linux/sigdelset.cpp | 4 +-- libc/src/signal/linux/sigfillset.cpp | 4 +-- libc/src/signal/linux/signal_utils.h | 3 +- libc/src/signal/linux/sigprocmask.cpp | 6 ++-- libc/src/signal/sigaddset.h | 2 +- libc/src/signal/sigdelset.h | 2 +- libc/src/signal/sigemptyset.h | 2 +- libc/src/signal/sigfillset.h | 2 +- libc/src/signal/sigprocmask.h | 2 +- libc/src/sys/epoll/epoll_pwait.h | 7 ++-- libc/src/sys/epoll/epoll_pwait2.h | 9 ++--- libc/src/sys/epoll/epoll_wait.h | 5 +-- libc/src/sys/epoll/linux/CMakeLists.txt | 14 +++++--- libc/src/sys/epoll/linux/epoll_pwait.cpp | 10 ++---- libc/src/sys/epoll/linux/epoll_pwait2.cpp | 12 +++---- libc/src/sys/epoll/linux/epoll_wait.cpp | 9 ++--- libc/src/sys/select/linux/select.cpp | 8 ++--- .../llvm-project-overlay/libc/BUILD.bazel | 13 ++++++++ 29 files changed, 200 insertions(+), 73 deletions(-) create mode 100644 libc/hdr/types/CMakeLists.txt create mode 100644 libc/hdr/types/sigset_t.h create mode 100644 libc/hdr/types/struct_epoll_event.h create mode 100644 libc/hdr/types/struct_timespec.h diff --git a/libc/docs/dev/code_style.rst b/libc/docs/dev/code_style.rst index 22a18b7a4cc1..ee4e4257c9fa 100644 --- a/libc/docs/dev/code_style.rst +++ b/libc/docs/dev/code_style.rst @@ -186,3 +186,36 @@ We expect contributions to be free of warnings from the `minimum supported compiler versions`__ (and newer). .. __: https://libc.llvm.org/compiler_support.html#minimum-supported-versions + +Header Inclusion Policy +======================= + +Because llvm-libc supports +`Overlay Mode `__ and +`Fullbuild Mode `__ care must be +taken when ``#include``'ing certain headers. + +The ``include/`` directory contains public facing headers that users must +consume for fullbuild mode. As such, types defined here will have ABI +implications as these definitions may differ from the underlying system for +overlay mode and are NEVER appropriate to include in ``libc/src/`` without +preprocessor guards for ``LLVM_LIBC_FULL_BUILD``. + +Consider the case where an implementation in ``libc/src/`` may wish to refer to +a ``sigset_t``, what header should be included? ````, ````, +````? + +None of the above. Instead, code under ``src/`` should ``#include +"hdr/types/sigset_t.h"`` which contains preprocessor guards on +``LLVM_LIBC_FULL_BUILD`` to either include the public type (fullbuild mode) or +the underlying system header (overlay mode). + +Implementations in ``libc/src/`` should NOT be ``#include``'ing using ``<>`` or +``"include/*``, except for these "proxy" headers that first check for +``LLVM_LIBC_FULL_BUILD``. + +These "proxy" headers are similarly used when referring to preprocessor +defines. Code under ``libc/src/`` should ``#include`` a proxy header from +``hdr/``, which contains a guard on ``LLVM_LIBC_FULL_BUILD`` to either include +our header from ``libc/include/`` (fullbuild) or the corresponding underlying +system header (overlay). diff --git a/libc/docs/usage_modes.rst b/libc/docs/usage_modes.rst index 11c10623b61d..8e5dcca6e0a7 100644 --- a/libc/docs/usage_modes.rst +++ b/libc/docs/usage_modes.rst @@ -6,6 +6,10 @@ The libc can used in two different modes: #. The **overlay** mode: In this mode, the link order semantics are exploited to overlay implementations from LLVM's libc over the system libc. See - :ref:`overlay_mode` for more information about this mode. + :ref:`overlay_mode` for more information about this mode. In this mode, libc + uses the ABI of the system it's being overlayed onto. Headers are NOT + generated. libllvmlibc.a is the only build artifact. #. The **fullbuild** mode: In this mode, LLVM's libc is used as the only libc for the binary. See :ref:`fullbuild_mode` for information about this mode. + In this mode, libc uses its own ABI. Headers are generated along with a + libc.a. diff --git a/libc/hdr/CMakeLists.txt b/libc/hdr/CMakeLists.txt index 5a1acd9d17ab..38ef56e3f04c 100644 --- a/libc/hdr/CMakeLists.txt +++ b/libc/hdr/CMakeLists.txt @@ -40,3 +40,5 @@ add_proxy_header_library( libc.include.llvm-libc-macros.fenv_macros libc.include.fenv ) + +add_subdirectory(types) diff --git a/libc/hdr/types/CMakeLists.txt b/libc/hdr/types/CMakeLists.txt new file mode 100644 index 000000000000..b685d82fd8cc --- /dev/null +++ b/libc/hdr/types/CMakeLists.txt @@ -0,0 +1,23 @@ +add_proxy_header_library( + sigset_t + HDRS + sigset_t.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.sigset_t +) + +add_proxy_header_library( + struct_epoll_event + HDRS + struct_epoll_event.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.struct_epoll_event +) + +add_proxy_header_library( + struct_timespec + HDRS + struct_timespec.h + FULL_BUILD_DEPENDS + libc.include.llvm-libc-types.struct_timespec +) diff --git a/libc/hdr/types/sigset_t.h b/libc/hdr/types/sigset_t.h new file mode 100644 index 000000000000..695ec3029f68 --- /dev/null +++ b/libc/hdr/types/sigset_t.h @@ -0,0 +1,21 @@ +//===-- Proxy for sigset_t ------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIBC_HDR_TYPES_SIGSET_T_H +#define LLVM_LIBC_HDR_TYPES_SIGSET_T_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/sigset_t.h" + +#else + +#include + +#endif // LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_SIGSET_T_H diff --git a/libc/hdr/types/struct_epoll_event.h b/libc/hdr/types/struct_epoll_event.h new file mode 100644 index 000000000000..5bb98ce05bb2 --- /dev/null +++ b/libc/hdr/types/struct_epoll_event.h @@ -0,0 +1,21 @@ +//===-- Proxy for struct epoll_event --------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIBC_HDR_TYPES_STRUCT_EPOLL_EVENT_H +#define LLVM_LIBC_HDR_TYPES_STRUCT_EPOLL_EVENT_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/struct_epoll_event.h" + +#else + +#include + +#endif // LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_STRUCT_EPOLL_EVENT_H diff --git a/libc/hdr/types/struct_timespec.h b/libc/hdr/types/struct_timespec.h new file mode 100644 index 000000000000..1f121f3d24d8 --- /dev/null +++ b/libc/hdr/types/struct_timespec.h @@ -0,0 +1,21 @@ +//===-- Proxy for struct timespec ----------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIBC_HDR_TYPES_STRUCT_TIMESPEC_H +#define LLVM_LIBC_HDR_TYPES_STRUCT_TIMESPEC_H + +#ifdef LIBC_FULL_BUILD + +#include "include/llvm-libc-types/struct_timespec.h" + +#else + +#include + +#endif // LIBC_FULL_BUILD + +#endif // LLVM_LIBC_HDR_TYPES_STRUCT_TIMESPEC_H diff --git a/libc/src/signal/linux/CMakeLists.txt b/libc/src/signal/linux/CMakeLists.txt index 77a2453b25a0..7606b4b21d3d 100644 --- a/libc/src/signal/linux/CMakeLists.txt +++ b/libc/src/signal/linux/CMakeLists.txt @@ -3,6 +3,8 @@ add_header_library( HDRS signal_utils.h DEPENDS + libc.hdr.types.sigset_t + libc.include.signal libc.include.sys_syscall libc.src.__support.OSUtil.osutil ) @@ -28,7 +30,7 @@ add_entrypoint_object( ../raise.h DEPENDS .signal_utils - libc.include.signal + libc.hdr.types.sigset_t libc.include.sys_syscall libc.src.__support.OSUtil.osutil ) @@ -57,7 +59,7 @@ add_entrypoint_object( ../sigaction.h DEPENDS .__restore - libc.include.signal + libc.hdr.types.sigset_t libc.include.sys_syscall libc.src.__support.OSUtil.osutil libc.src.errno.errno @@ -84,7 +86,7 @@ add_entrypoint_object( ../sigprocmask.h DEPENDS .signal_utils - libc.include.signal + libc.hdr.types.sigset_t libc.include.sys_syscall libc.src.__support.OSUtil.osutil libc.src.errno.errno @@ -98,7 +100,7 @@ add_entrypoint_object( ../sigemptyset.h DEPENDS .signal_utils - libc.include.signal + libc.hdr.types.sigset_t libc.src.errno.errno ) @@ -110,7 +112,7 @@ add_entrypoint_object( ../sigaddset.h DEPENDS .signal_utils - libc.include.signal + libc.hdr.types.sigset_t libc.src.errno.errno ) @@ -133,7 +135,7 @@ add_entrypoint_object( ../sigfillset.h DEPENDS .signal_utils - libc.include.signal + libc.hdr.types.sigset_t libc.src.errno.errno ) @@ -145,6 +147,6 @@ add_entrypoint_object( ../sigdelset.h DEPENDS .signal_utils - libc.include.signal + libc.hdr.types.sigset_t libc.src.errno.errno ) diff --git a/libc/src/signal/linux/raise.cpp b/libc/src/signal/linux/raise.cpp index dd6f5eb4b357..2250df547844 100644 --- a/libc/src/signal/linux/raise.cpp +++ b/libc/src/signal/linux/raise.cpp @@ -7,14 +7,15 @@ //===----------------------------------------------------------------------===// #include "src/signal/raise.h" -#include "src/signal/linux/signal_utils.h" +#include "hdr/types/sigset_t.h" #include "src/__support/common.h" +#include "src/signal/linux/signal_utils.h" namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, raise, (int sig)) { - ::sigset_t sigset; + sigset_t sigset; block_all_signals(sigset); long pid = LIBC_NAMESPACE::syscall_impl(SYS_getpid); long tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); diff --git a/libc/src/signal/linux/sigaction.cpp b/libc/src/signal/linux/sigaction.cpp index 7ddc2dc5cbcc..7b220e5c37f6 100644 --- a/libc/src/signal/linux/sigaction.cpp +++ b/libc/src/signal/linux/sigaction.cpp @@ -7,12 +7,11 @@ //===----------------------------------------------------------------------===// #include "src/signal/sigaction.h" -#include "src/errno/libc_errno.h" -#include "src/signal/linux/signal_utils.h" +#include "hdr/types/sigset_t.h" #include "src/__support/common.h" - -#include +#include "src/errno/libc_errno.h" +#include "src/signal/linux/signal_utils.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/signal/linux/sigaddset.cpp b/libc/src/signal/linux/sigaddset.cpp index 536391734e05..8fc5d43180e2 100644 --- a/libc/src/signal/linux/sigaddset.cpp +++ b/libc/src/signal/linux/sigaddset.cpp @@ -7,12 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/signal/sigaddset.h" + +#include "hdr/types/sigset_t.h" #include "src/__support/common.h" #include "src/errno/libc_errno.h" #include "src/signal/linux/signal_utils.h" -#include - namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, sigaddset, (sigset_t * set, int signum)) { diff --git a/libc/src/signal/linux/sigdelset.cpp b/libc/src/signal/linux/sigdelset.cpp index 5cb645e461cf..997f4574c05d 100644 --- a/libc/src/signal/linux/sigdelset.cpp +++ b/libc/src/signal/linux/sigdelset.cpp @@ -7,12 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/signal/sigdelset.h" + +#include "hdr/types/sigset_t.h" #include "src/__support/common.h" #include "src/errno/libc_errno.h" #include "src/signal/linux/signal_utils.h" -#include - namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, sigdelset, (sigset_t * set, int signum)) { diff --git a/libc/src/signal/linux/sigfillset.cpp b/libc/src/signal/linux/sigfillset.cpp index e17c85a897ce..d98bbf7f619c 100644 --- a/libc/src/signal/linux/sigfillset.cpp +++ b/libc/src/signal/linux/sigfillset.cpp @@ -7,12 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/signal/sigfillset.h" + +#include "hdr/types/sigset_t.h" #include "src/__support/common.h" #include "src/errno/libc_errno.h" #include "src/signal/linux/signal_utils.h" -#include - namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, sigfillset, (sigset_t * set)) { diff --git a/libc/src/signal/linux/signal_utils.h b/libc/src/signal/linux/signal_utils.h index 5e9dd9a5c53a..3fd0cc0b7b45 100644 --- a/libc/src/signal/linux/signal_utils.h +++ b/libc/src/signal/linux/signal_utils.h @@ -9,10 +9,11 @@ #ifndef LLVM_LIBC_SRC_SIGNAL_LINUX_SIGNAL_UTILS_H #define LLVM_LIBC_SRC_SIGNAL_LINUX_SIGNAL_UTILS_H +#include "hdr/types/sigset_t.h" #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" -#include +#include // sigaction #include #include // For syscall numbers. diff --git a/libc/src/signal/linux/sigprocmask.cpp b/libc/src/signal/linux/sigprocmask.cpp index 79a35dd59d75..0e94efb6400c 100644 --- a/libc/src/signal/linux/sigprocmask.cpp +++ b/libc/src/signal/linux/sigprocmask.cpp @@ -7,13 +7,13 @@ //===----------------------------------------------------------------------===// #include "src/signal/sigprocmask.h" + +#include "hdr/types/sigset_t.h" #include "src/__support/OSUtil/syscall.h" // For internal syscall function. +#include "src/__support/common.h" #include "src/errno/libc_errno.h" #include "src/signal/linux/signal_utils.h" -#include "src/__support/common.h" - -#include #include // For syscall numbers. namespace LIBC_NAMESPACE { diff --git a/libc/src/signal/sigaddset.h b/libc/src/signal/sigaddset.h index 626eb20a295c..c703b46bc605 100644 --- a/libc/src/signal/sigaddset.h +++ b/libc/src/signal/sigaddset.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_SIGNAL_SIGADDSET_H #define LLVM_LIBC_SRC_SIGNAL_SIGADDSET_H -#include +#include "hdr/types/sigset_t.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/signal/sigdelset.h b/libc/src/signal/sigdelset.h index c4fdb9975fa3..7bdb6e6d18fd 100644 --- a/libc/src/signal/sigdelset.h +++ b/libc/src/signal/sigdelset.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_SIGNAL_SIGDELSET_H #define LLVM_LIBC_SRC_SIGNAL_SIGDELSET_H -#include +#include "hdr/types/sigset_t.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/signal/sigemptyset.h b/libc/src/signal/sigemptyset.h index f3763d1f4f3d..661fd33b888e 100644 --- a/libc/src/signal/sigemptyset.h +++ b/libc/src/signal/sigemptyset.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_SIGNAL_SIGEMPTYSET_H #define LLVM_LIBC_SRC_SIGNAL_SIGEMPTYSET_H -#include +#include "hdr/types/sigset_t.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/signal/sigfillset.h b/libc/src/signal/sigfillset.h index d8e3168871ea..2849aacf953b 100644 --- a/libc/src/signal/sigfillset.h +++ b/libc/src/signal/sigfillset.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_SIGNAL_SIGFILLSET_H #define LLVM_LIBC_SRC_SIGNAL_SIGFILLSET_H -#include +#include "hdr/types/sigset_t.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/signal/sigprocmask.h b/libc/src/signal/sigprocmask.h index e0658860579e..8569578eb68c 100644 --- a/libc/src/signal/sigprocmask.h +++ b/libc/src/signal/sigprocmask.h @@ -9,7 +9,7 @@ #ifndef LLVM_LIBC_SRC_SIGNAL_SIGPROCMASK_H #define LLVM_LIBC_SRC_SIGNAL_SIGPROCMASK_H -#include +#include "hdr/types/sigset_t.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/epoll/epoll_pwait.h b/libc/src/sys/epoll/epoll_pwait.h index 9dcb55533009..801aa9761000 100644 --- a/libc/src/sys/epoll/epoll_pwait.h +++ b/libc/src/sys/epoll/epoll_pwait.h @@ -9,11 +9,8 @@ #ifndef LLVM_LIBC_SRC_SYS_EPOLL_EPOLL_PWAIT_H #define LLVM_LIBC_SRC_SYS_EPOLL_EPOLL_PWAIT_H -// TODO: Use this include once the include headers are also using quotes. -// #include "include/llvm-libc-types/sigset_t.h" -// #include "include/llvm-libc-types/struct_epoll_event.h" - -#include +#include "hdr/types/sigset_t.h" +#include "hdr/types/struct_epoll_event.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/epoll/epoll_pwait2.h b/libc/src/sys/epoll/epoll_pwait2.h index 622ede6a0f9f..7fc528b2fd25 100644 --- a/libc/src/sys/epoll/epoll_pwait2.h +++ b/libc/src/sys/epoll/epoll_pwait2.h @@ -9,12 +9,9 @@ #ifndef LLVM_LIBC_SRC_SYS_EPOLL_EPOLL_PWAIT2_H #define LLVM_LIBC_SRC_SYS_EPOLL_EPOLL_PWAIT2_H -// TODO: Use this include once the include headers are also using quotes. -// #include "include/llvm-libc-types/sigset_t.h" -// #include "include/llvm-libc-types/struct_epoll_event.h" -// #include "include/llvm-libc-types/struct_timespec.h" - -#include +#include "hdr/types/sigset_t.h" +#include "hdr/types/struct_epoll_event.h" +#include "hdr/types/struct_timespec.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/epoll/epoll_wait.h b/libc/src/sys/epoll/epoll_wait.h index d51c9100846c..b546e91e4c2e 100644 --- a/libc/src/sys/epoll/epoll_wait.h +++ b/libc/src/sys/epoll/epoll_wait.h @@ -9,10 +9,7 @@ #ifndef LLVM_LIBC_SRC_SYS_EPOLL_EPOLL_WAIT_H #define LLVM_LIBC_SRC_SYS_EPOLL_EPOLL_WAIT_H -// TODO: Use this include once the include headers are also using quotes. -// #include "include/llvm-libc-types/struct_epoll_event.h" - -#include +#include "hdr/types/struct_epoll_event.h" namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/epoll/linux/CMakeLists.txt b/libc/src/sys/epoll/linux/CMakeLists.txt index a27905d962dc..586aac7055dc 100644 --- a/libc/src/sys/epoll/linux/CMakeLists.txt +++ b/libc/src/sys/epoll/linux/CMakeLists.txt @@ -5,7 +5,9 @@ add_entrypoint_object( HDRS ../epoll_wait.h DEPENDS - libc.include.sys_epoll + libc.hdr.types.sigset_t + libc.hdr.types.struct_epoll_event + libc.hdr.types.struct_timespec libc.include.sys_syscall libc.src.__support.OSUtil.osutil libc.src.errno.errno @@ -18,7 +20,9 @@ add_entrypoint_object( HDRS ../epoll_pwait.h DEPENDS - libc.include.sys_epoll + libc.hdr.types.sigset_t + libc.hdr.types.struct_epoll_event + libc.hdr.types.struct_timespec libc.include.signal libc.include.sys_syscall libc.src.__support.OSUtil.osutil @@ -32,10 +36,12 @@ add_entrypoint_object( HDRS ../epoll_pwait2.h DEPENDS - libc.include.sys_epoll + libc.hdr.types.sigset_t + libc.hdr.types.struct_epoll_event + libc.hdr.types.struct_timespec libc.include.signal - libc.include.time libc.include.sys_syscall + libc.include.time libc.src.__support.OSUtil.osutil libc.src.errno.errno ) diff --git a/libc/src/sys/epoll/linux/epoll_pwait.cpp b/libc/src/sys/epoll/linux/epoll_pwait.cpp index ee1b4e66e984..ac012944a957 100644 --- a/libc/src/sys/epoll/linux/epoll_pwait.cpp +++ b/libc/src/sys/epoll/linux/epoll_pwait.cpp @@ -8,17 +8,13 @@ #include "src/sys/epoll/epoll_pwait.h" +#include "hdr/types/sigset_t.h" +#include "hdr/types/struct_epoll_event.h" #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" - #include "src/errno/libc_errno.h" -#include // For syscall numbers. -// TODO: Use this include once the include headers are also using quotes. -// #include "include/llvm-libc-types/sigset_t.h" -// #include "include/llvm-libc-types/struct_epoll_event.h" - -#include +#include // For syscall numbers. namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/epoll/linux/epoll_pwait2.cpp b/libc/src/sys/epoll/linux/epoll_pwait2.cpp index 671dede2a105..3c42e38deb22 100644 --- a/libc/src/sys/epoll/linux/epoll_pwait2.cpp +++ b/libc/src/sys/epoll/linux/epoll_pwait2.cpp @@ -8,18 +8,14 @@ #include "src/sys/epoll/epoll_pwait2.h" +#include "hdr/types/sigset_t.h" +#include "hdr/types/struct_epoll_event.h" +#include "hdr/types/struct_timespec.h" #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" - #include "src/errno/libc_errno.h" -#include // For syscall numbers. -// TODO: Use this include once the include headers are also using quotes. -// #include "include/llvm-libc-types/sigset_t.h" -// #include "include/llvm-libc-types/struct_epoll_event.h" -// #include "include/llvm-libc-types/struct_timespec.h" - -#include +#include // For syscall numbers. namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/epoll/linux/epoll_wait.cpp b/libc/src/sys/epoll/linux/epoll_wait.cpp index 0c43edf76454..18dd6e2b8354 100644 --- a/libc/src/sys/epoll/linux/epoll_wait.cpp +++ b/libc/src/sys/epoll/linux/epoll_wait.cpp @@ -8,16 +8,13 @@ #include "src/sys/epoll/epoll_wait.h" +#include "hdr/types/sigset_t.h" +#include "hdr/types/struct_epoll_event.h" #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" #include "src/errno/libc_errno.h" -#include // For syscall numbers. - -// TODO: Use this include once the include headers are also using quotes. -// #include "include/llvm-libc-types/sigset_t.h" -// #include "include/llvm-libc-types/struct_epoll_event.h" -#include +#include // For syscall numbers. namespace LIBC_NAMESPACE { diff --git a/libc/src/sys/select/linux/select.cpp b/libc/src/sys/select/linux/select.cpp index 3f387c14ec56..9034b75e5c29 100644 --- a/libc/src/sys/select/linux/select.cpp +++ b/libc/src/sys/select/linux/select.cpp @@ -8,14 +8,14 @@ #include "src/sys/select/select.h" +#include "hdr/types/sigset_t.h" +#include "hdr/types/struct_timespec.h" #include "src/__support/CPP/limits.h" #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" - #include "src/errno/libc_errno.h" -#include -#include // For size_t -#include + +#include // For size_t #include // For syscall numbers. namespace LIBC_NAMESPACE { diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index d38dc3029f74..c61904a96711 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -3417,6 +3417,15 @@ libc_function( ############################## sys/epoll targets ############################### +libc_support_library( + name = "types_sigset_t", + hdrs = ["hdr/types/sigset_t.h"], +) +libc_support_library( + name = "types_struct_epoll_event", + hdrs = ["hdr/types/struct_epoll_event.h"], +) + libc_function( name = "epoll_wait", srcs = ["src/sys/epoll/linux/epoll_wait.cpp"], @@ -3429,6 +3438,8 @@ libc_function( deps = [ ":__support_osutil_syscall", ":errno", + ":types_sigset_t", + ":types_struct_epoll_event", ], ) @@ -3444,6 +3455,8 @@ libc_function( deps = [ ":__support_osutil_syscall", ":errno", + ":types_sigset_t", + ":types_struct_epoll_event", ], ) -- GitLab From 4e6d18f40642c2cc8e124bbe55810b2d9b2ac9c0 Mon Sep 17 00:00:00 2001 From: Krystian Stasiowski Date: Thu, 11 Apr 2024 13:20:05 -0400 Subject: [PATCH 547/695] [Clang][AST] Track whether template template parameters used the 'typename' keyword (#88139) This patch adds a `Typename` bit-field to `TemplateTemplateParmDecl` which stores whether the template template parameter was declared with the `typename` keyword. --- clang/docs/ReleaseNotes.rst | 4 ++ clang/include/clang/AST/DeclTemplate.h | 49 +++++++++++++------ clang/include/clang/Sema/Sema.h | 2 +- clang/lib/AST/ASTContext.cpp | 2 +- clang/lib/AST/ASTImporter.cpp | 3 +- clang/lib/AST/DeclPrinter.cpp | 5 +- clang/lib/AST/DeclTemplate.cpp | 18 +++---- clang/lib/Parse/ParseTemplate.cpp | 9 ++-- clang/lib/Sema/SemaTemplate.cpp | 24 ++++----- .../lib/Sema/SemaTemplateInstantiateDecl.cpp | 6 ++- clang/lib/Serialization/ASTReaderDecl.cpp | 1 + clang/lib/Serialization/ASTWriterDecl.cpp | 1 + clang/unittests/AST/DeclPrinterTest.cpp | 3 +- 13 files changed, 75 insertions(+), 52 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 93318871fa9f..93a380411604 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -360,6 +360,9 @@ Improvements to Clang's diagnostics Added the ``-Wtentative-definition-array`` warning group to cover this. Fixes #GH87766 +- Clang now uses the correct type-parameter-key (``class`` or ``typename``) when printing + template template parameter declarations. + Improvements to Clang's time-trace ---------------------------------- @@ -535,6 +538,7 @@ Bug Fixes to C++ Support Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ - Clang now properly preserves ``FoundDecls`` within a ``ConceptReference``. (#GH82628) +- The presence of the ``typename`` keyword is now stored in ``TemplateTemplateParmDecl``. Miscellaneous Bug Fixes ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h index cb598cb81840..f24e71ff2296 100644 --- a/clang/include/clang/AST/DeclTemplate.h +++ b/clang/include/clang/AST/DeclTemplate.h @@ -1581,26 +1581,36 @@ class TemplateTemplateParmDecl final DefaultArgStorage; DefArgStorage DefaultArgument; + /// Whether this template template parameter was declaration with + /// the 'typename' keyword. + /// + /// If false, it was declared with the 'class' keyword. + LLVM_PREFERRED_TYPE(bool) + unsigned Typename : 1; + /// Whether this parameter is a parameter pack. - bool ParameterPack; + LLVM_PREFERRED_TYPE(bool) + unsigned ParameterPack : 1; /// Whether this template template parameter is an "expanded" /// parameter pack, meaning that it is a pack expansion and we /// already know the set of template parameters that expansion expands to. - bool ExpandedParameterPack = false; + LLVM_PREFERRED_TYPE(bool) + unsigned ExpandedParameterPack : 1; /// The number of parameters in an expanded parameter pack. unsigned NumExpandedParams = 0; - TemplateTemplateParmDecl(DeclContext *DC, SourceLocation L, - unsigned D, unsigned P, bool ParameterPack, - IdentifierInfo *Id, TemplateParameterList *Params) + TemplateTemplateParmDecl(DeclContext *DC, SourceLocation L, unsigned D, + unsigned P, bool ParameterPack, IdentifierInfo *Id, + bool Typename, TemplateParameterList *Params) : TemplateDecl(TemplateTemplateParm, DC, L, Id, Params), - TemplateParmPosition(D, P), ParameterPack(ParameterPack) {} + TemplateParmPosition(D, P), Typename(Typename), + ParameterPack(ParameterPack), ExpandedParameterPack(false) {} - TemplateTemplateParmDecl(DeclContext *DC, SourceLocation L, - unsigned D, unsigned P, - IdentifierInfo *Id, TemplateParameterList *Params, + TemplateTemplateParmDecl(DeclContext *DC, SourceLocation L, unsigned D, + unsigned P, IdentifierInfo *Id, bool Typename, + TemplateParameterList *Params, ArrayRef Expansions); void anchor() override; @@ -1613,14 +1623,13 @@ public: static TemplateTemplateParmDecl *Create(const ASTContext &C, DeclContext *DC, SourceLocation L, unsigned D, unsigned P, bool ParameterPack, - IdentifierInfo *Id, + IdentifierInfo *Id, bool Typename, TemplateParameterList *Params); - static TemplateTemplateParmDecl *Create(const ASTContext &C, DeclContext *DC, - SourceLocation L, unsigned D, - unsigned P, - IdentifierInfo *Id, - TemplateParameterList *Params, - ArrayRef Expansions); + static TemplateTemplateParmDecl * + Create(const ASTContext &C, DeclContext *DC, SourceLocation L, unsigned D, + unsigned P, IdentifierInfo *Id, bool Typename, + TemplateParameterList *Params, + ArrayRef Expansions); static TemplateTemplateParmDecl *CreateDeserialized(ASTContext &C, unsigned ID); @@ -1634,6 +1643,14 @@ public: using TemplateParmPosition::setPosition; using TemplateParmPosition::getIndex; + /// Whether this template template parameter was declared with + /// the 'typename' keyword. + bool wasDeclaredWithTypename() const { return Typename; } + + /// Set whether this template template parameter was declared with + /// the 'typename' or 'class' keyword. + void setDeclaredWithTypename(bool withTypename) { Typename = withTypename; } + /// Whether this template template parameter is a template /// parameter pack. /// diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 0ee4f3c8e127..f2c55b13b6d3 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -9064,7 +9064,7 @@ public: Expr *DefaultArg); NamedDecl *ActOnTemplateTemplateParameter( Scope *S, SourceLocation TmpLoc, TemplateParameterList *Params, - SourceLocation EllipsisLoc, IdentifierInfo *ParamName, + bool Typename, SourceLocation EllipsisLoc, IdentifierInfo *ParamName, SourceLocation ParamNameLoc, unsigned Depth, unsigned Position, SourceLocation EqualLoc, ParsedTemplateArgument DefaultArg); diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 2fa6aedca4c6..6ce233704a58 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -799,7 +799,7 @@ ASTContext::getCanonicalTemplateTemplateParmDecl( TemplateTemplateParmDecl *CanonTTP = TemplateTemplateParmDecl::Create( *this, getTranslationUnitDecl(), SourceLocation(), TTP->getDepth(), - TTP->getPosition(), TTP->isParameterPack(), nullptr, + TTP->getPosition(), TTP->isParameterPack(), nullptr, /*Typename=*/false, TemplateParameterList::Create(*this, SourceLocation(), SourceLocation(), CanonParams, SourceLocation(), /*RequiresClause=*/nullptr)); diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index d5ec5ee40915..a5e43fc63166 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -5952,7 +5952,8 @@ ASTNodeImporter::VisitTemplateTemplateParmDecl(TemplateTemplateParmDecl *D) { ToD, D, Importer.getToContext(), Importer.getToContext().getTranslationUnitDecl(), *LocationOrErr, D->getDepth(), D->getPosition(), D->isParameterPack(), - (*NameOrErr).getAsIdentifierInfo(), *TemplateParamsOrErr)) + (*NameOrErr).getAsIdentifierInfo(), D->wasDeclaredWithTypename(), + *TemplateParamsOrErr)) return ToD; if (D->hasDefaultArgument()) { diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index 6afdb6cfccb1..c66774dd1df1 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -1218,7 +1218,10 @@ void DeclPrinter::VisitTemplateDecl(const TemplateDecl *D) { if (const TemplateTemplateParmDecl *TTP = dyn_cast(D)) { - Out << "class"; + if (TTP->wasDeclaredWithTypename()) + Out << "typename"; + else + Out << "class"; if (TTP->isParameterPack()) Out << " ..."; diff --git a/clang/lib/AST/DeclTemplate.cpp b/clang/lib/AST/DeclTemplate.cpp index 571ed81a42e4..5aa248419737 100644 --- a/clang/lib/AST/DeclTemplate.cpp +++ b/clang/lib/AST/DeclTemplate.cpp @@ -805,10 +805,10 @@ void TemplateTemplateParmDecl::anchor() {} TemplateTemplateParmDecl::TemplateTemplateParmDecl( DeclContext *DC, SourceLocation L, unsigned D, unsigned P, - IdentifierInfo *Id, TemplateParameterList *Params, + IdentifierInfo *Id, bool Typename, TemplateParameterList *Params, ArrayRef Expansions) : TemplateDecl(TemplateTemplateParm, DC, L, Id, Params), - TemplateParmPosition(D, P), ParameterPack(true), + TemplateParmPosition(D, P), Typename(Typename), ParameterPack(true), ExpandedParameterPack(true), NumExpandedParams(Expansions.size()) { if (!Expansions.empty()) std::uninitialized_copy(Expansions.begin(), Expansions.end(), @@ -819,26 +819,26 @@ TemplateTemplateParmDecl * TemplateTemplateParmDecl::Create(const ASTContext &C, DeclContext *DC, SourceLocation L, unsigned D, unsigned P, bool ParameterPack, IdentifierInfo *Id, - TemplateParameterList *Params) { + bool Typename, TemplateParameterList *Params) { return new (C, DC) TemplateTemplateParmDecl(DC, L, D, P, ParameterPack, Id, - Params); + Typename, Params); } TemplateTemplateParmDecl * TemplateTemplateParmDecl::Create(const ASTContext &C, DeclContext *DC, SourceLocation L, unsigned D, unsigned P, - IdentifierInfo *Id, + IdentifierInfo *Id, bool Typename, TemplateParameterList *Params, ArrayRef Expansions) { return new (C, DC, additionalSizeToAlloc(Expansions.size())) - TemplateTemplateParmDecl(DC, L, D, P, Id, Params, Expansions); + TemplateTemplateParmDecl(DC, L, D, P, Id, Typename, Params, Expansions); } TemplateTemplateParmDecl * TemplateTemplateParmDecl::CreateDeserialized(ASTContext &C, unsigned ID) { return new (C, ID) TemplateTemplateParmDecl(nullptr, SourceLocation(), 0, 0, - false, nullptr, nullptr); + false, nullptr, false, nullptr); } TemplateTemplateParmDecl * @@ -847,7 +847,7 @@ TemplateTemplateParmDecl::CreateDeserialized(ASTContext &C, unsigned ID, auto *TTP = new (C, ID, additionalSizeToAlloc(NumExpansions)) TemplateTemplateParmDecl(nullptr, SourceLocation(), 0, 0, nullptr, - nullptr, std::nullopt); + false, nullptr, std::nullopt); TTP->NumExpandedParams = NumExpansions; return TTP; } @@ -1469,7 +1469,7 @@ createMakeIntegerSeqParameterList(const ASTContext &C, DeclContext *DC) { // template class IntSeq auto *TemplateTemplateParm = TemplateTemplateParmDecl::Create( C, DC, SourceLocation(), /*Depth=*/0, /*Position=*/0, - /*ParameterPack=*/false, /*Id=*/nullptr, TPL); + /*ParameterPack=*/false, /*Id=*/nullptr, /*Typename=*/false, TPL); TemplateTemplateParm->setImplicit(true); // typename T diff --git a/clang/lib/Parse/ParseTemplate.cpp b/clang/lib/Parse/ParseTemplate.cpp index 03257500426e..b07ce451e878 100644 --- a/clang/lib/Parse/ParseTemplate.cpp +++ b/clang/lib/Parse/ParseTemplate.cpp @@ -805,10 +805,12 @@ NamedDecl *Parser::ParseTemplateTemplateParameter(unsigned Depth, // identifier, comma, or greater. Provide a fixit if the identifier, comma, // or greater appear immediately or after 'struct'. In the latter case, // replace the keyword with 'class'. + bool TypenameKeyword = false; if (!TryConsumeToken(tok::kw_class)) { bool Replace = Tok.isOneOf(tok::kw_typename, tok::kw_struct); const Token &Next = Tok.is(tok::kw_struct) ? NextToken() : Tok; if (Tok.is(tok::kw_typename)) { + TypenameKeyword = true; Diag(Tok.getLocation(), getLangOpts().CPlusPlus17 ? diag::warn_cxx14_compat_template_template_param_typename @@ -878,10 +880,9 @@ NamedDecl *Parser::ParseTemplateTemplateParameter(unsigned Depth, } } - return Actions.ActOnTemplateTemplateParameter(getCurScope(), TemplateLoc, - ParamList, EllipsisLoc, - ParamName, NameLoc, Depth, - Position, EqualLoc, DefaultArg); + return Actions.ActOnTemplateTemplateParameter( + getCurScope(), TemplateLoc, ParamList, TypenameKeyword, EllipsisLoc, + ParamName, NameLoc, Depth, Position, EqualLoc, DefaultArg); } /// ParseNonTypeTemplateParameter - Handle the parsing of non-type diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 951e5a31cab3..e0f5e53dc248 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -1630,26 +1630,20 @@ NamedDecl *Sema::ActOnNonTypeTemplateParameter(Scope *S, Declarator &D, /// ActOnTemplateTemplateParameter - Called when a C++ template template /// parameter (e.g. T in template